| blob | 3856446bc56b4b515293a9b2f1753ab6307094b5 |
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 if (TARGET_ARM) \
35 else \
37 \
38 if (TARGET_BIG_END) \
39 { \
41 if (TARGET_THUMB) \
43 if (TARGET_LITTLE_WORDS) \
45 } \
46 else \
47 { \
49 if (TARGET_THUMB) \
51 } \
52 \
53 if (TARGET_APCS_32) \
55 else \
57 \
58 if (TARGET_SOFT_FLOAT) \
60 \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
65 \
66 /* Add a define for interworking. \
68 if (TARGET_INTERWORK) \
70 \
73 } while (0)
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 #define TARGET_CPU_ep9312 0x0200
100 /* Configure didn't specify. */
101 #define TARGET_CPU_generic 0x8000
104 {
107 }
108 arm_cc;
112 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
117 /* Run-time compilation parameters selecting different hardware subsets. */
119 /* The floating point instruction architecture, can be 2 or 3 */
121 /* Define the information needed to generate branch insns. This is
122 stored from the compare operation. */
125 /* The label of the current constant pool. */
127 /* Set to 1 when a return insn is output, this means that the epilogue
128 is not needed. */
130 /* Used to produce AOF syntax assembler. */
132 \f
133 /* Just in case configure has failed to define anything. */
134 #ifndef TARGET_CPU_DEFAULT
135 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
136 #endif
138 /* If the configuration file doesn't specify the cpu, the subtarget may
139 override it. If it doesn't, then default to an ARM6. */
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
141 #undef TARGET_CPU_DEFAULT
143 #ifdef SUBTARGET_CPU_DEFAULT
144 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
145 #else
146 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
147 #endif
148 #endif
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
152 #else
153 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
155 #else
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
158 #else
159 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
161 #else
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
164 #else
165 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
167 #else
168 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
170 /* Set TARGET_DEFAULT to the default, but without soft-float. */
171 #ifdef TARGET_DEFAULT
172 #undef TARGET_DEFAULT
173 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
175 #else
176 Unrecognized value in TARGET_CPU_DEFAULT.
177 #endif
178 #endif
179 #endif
180 #endif
181 #endif
182 #endif
183 #endif
185 #undef CPP_SPEC
187 %{mapcs-32:%{mapcs-26: \
188 %e-mapcs-26 and -mapcs-32 may not be used together}} \
189 %{msoft-float:%{mhard-float: \
190 %e-msoft-float and -mhard_float may not be used together}} \
191 %{mbig-endian:%{mlittle-endian: \
192 %e-mbig-endian and -mlittle-endian may not be used together}}"
194 /* Set the architecture define -- if -march= is set, then it overrides
195 the -mcpu= setting. */
197 %{march=arm2:-D__ARM_ARCH_2__} \
198 %{march=arm250:-D__ARM_ARCH_2__} \
199 %{march=arm3:-D__ARM_ARCH_2__} \
200 %{march=arm6:-D__ARM_ARCH_3__} \
201 %{march=arm600:-D__ARM_ARCH_3__} \
202 %{march=arm610:-D__ARM_ARCH_3__} \
203 %{march=arm7:-D__ARM_ARCH_3__} \
204 %{march=arm700:-D__ARM_ARCH_3__} \
205 %{march=arm710:-D__ARM_ARCH_3__} \
206 %{march=arm720:-D__ARM_ARCH_3__} \
207 %{march=arm7100:-D__ARM_ARCH_3__} \
208 %{march=arm7500:-D__ARM_ARCH_3__} \
209 %{march=arm7500fe:-D__ARM_ARCH_3__} \
210 %{march=arm7m:-D__ARM_ARCH_3M__} \
211 %{march=arm7dm:-D__ARM_ARCH_3M__} \
212 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
213 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
214 %{march=arm8:-D__ARM_ARCH_4__} \
215 %{march=arm810:-D__ARM_ARCH_4__} \
216 %{march=arm9:-D__ARM_ARCH_4T__} \
217 %{march=arm920:-D__ARM_ARCH_4__} \
218 %{march=arm920t:-D__ARM_ARCH_4T__} \
219 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
220 %{march=strongarm:-D__ARM_ARCH_4__} \
221 %{march=strongarm110:-D__ARM_ARCH_4__} \
222 %{march=strongarm1100:-D__ARM_ARCH_4__} \
223 %{march=xscale:-D__ARM_ARCH_5TE__} \
224 %{march=xscale:-D__XSCALE__} \
225 %{march=ep9312:-D__ARM_ARCH_4T__} \
226 %{march=ep9312:-D__MAVERICK__} \
227 %{march=armv2:-D__ARM_ARCH_2__} \
228 %{march=armv2a:-D__ARM_ARCH_2__} \
229 %{march=armv3:-D__ARM_ARCH_3__} \
230 %{march=armv3m:-D__ARM_ARCH_3M__} \
231 %{march=armv4:-D__ARM_ARCH_4__} \
232 %{march=armv4t:-D__ARM_ARCH_4T__} \
233 %{march=armv5:-D__ARM_ARCH_5__} \
234 %{march=armv5t:-D__ARM_ARCH_5T__} \
235 %{march=armv5e:-D__ARM_ARCH_5E__} \
236 %{march=armv5te:-D__ARM_ARCH_5TE__} \
237 %{!march=*: \
238 %{mcpu=arm2:-D__ARM_ARCH_2__} \
239 %{mcpu=arm250:-D__ARM_ARCH_2__} \
240 %{mcpu=arm3:-D__ARM_ARCH_2__} \
241 %{mcpu=arm6:-D__ARM_ARCH_3__} \
242 %{mcpu=arm600:-D__ARM_ARCH_3__} \
243 %{mcpu=arm610:-D__ARM_ARCH_3__} \
244 %{mcpu=arm7:-D__ARM_ARCH_3__} \
245 %{mcpu=arm700:-D__ARM_ARCH_3__} \
246 %{mcpu=arm710:-D__ARM_ARCH_3__} \
247 %{mcpu=arm720:-D__ARM_ARCH_3__} \
248 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
249 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
250 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
251 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
252 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
253 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
254 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
255 %{mcpu=arm8:-D__ARM_ARCH_4__} \
256 %{mcpu=arm810:-D__ARM_ARCH_4__} \
257 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
258 %{mcpu=arm920:-D__ARM_ARCH_4__} \
259 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
260 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
261 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
262 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
263 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
264 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
265 %{mcpu=xscale:-D__XSCALE__} \
266 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
267 %{mcpu=ep9312:-D__MAVERICK__} \
268 %{!mcpu*:%(cpp_cpu_arch_default)}} \
269 "
271 #ifndef CC1_SPEC
273 #endif
275 /* This macro defines names of additional specifications to put in the specs
276 that can be used in various specifications like CC1_SPEC. Its definition
277 is an initializer with a subgrouping for each command option.
279 Each subgrouping contains a string constant, that defines the
280 specification name, and a string constant that used by the GCC driver
281 program.
283 Do not define this macro if it does not need to do anything. */
284 #define EXTRA_SPECS \
288 SUBTARGET_EXTRA_SPECS
290 #ifndef SUBTARGET_EXTRA_SPECS
291 #define SUBTARGET_EXTRA_SPECS
292 #endif
294 #ifndef SUBTARGET_CPP_SPEC
296 #endif
297 \f
298 /* Run-time Target Specification. */
299 #ifndef TARGET_VERSION
301 #endif
303 /* Nonzero if the function prologue (and epilogue) should obey
304 the ARM Procedure Call Standard. */
305 #define ARM_FLAG_APCS_FRAME (1 << 0)
307 /* Nonzero if the function prologue should output the function name to enable
308 the post mortem debugger to print a backtrace (very useful on RISCOS,
309 unused on RISCiX). Specifying this flag also enables
310 -fno-omit-frame-pointer.
311 XXX Must still be implemented in the prologue. */
312 #define ARM_FLAG_POKE (1 << 1)
314 /* Nonzero if floating point instructions are emulated by the FPE, in which
315 case instruction scheduling becomes very uninteresting. */
316 #define ARM_FLAG_FPE (1 << 2)
318 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
319 that assume restoration of the condition flags when returning from a
320 branch and link (ie a function). */
321 #define ARM_FLAG_APCS_32 (1 << 3)
323 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
325 /* Nonzero if stack checking should be performed on entry to each function
326 which allocates temporary variables on the stack. */
327 #define ARM_FLAG_APCS_STACK (1 << 4)
329 /* Nonzero if floating point parameters should be passed to functions in
330 floating point registers. */
331 #define ARM_FLAG_APCS_FLOAT (1 << 5)
333 /* Nonzero if re-entrant, position independent code should be generated.
334 This is equivalent to -fpic. */
335 #define ARM_FLAG_APCS_REENT (1 << 6)
337 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
338 be loaded using either LDRH or LDRB instructions. */
339 #define ARM_FLAG_MMU_TRAPS (1 << 7)
341 /* Nonzero if all floating point instructions are missing (and there is no
342 emulator either). Generate function calls for all ops in this case. */
343 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
345 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
346 #define ARM_FLAG_BIG_END (1 << 9)
348 /* Nonzero if we should compile for Thumb interworking. */
349 #define ARM_FLAG_INTERWORK (1 << 10)
351 /* Nonzero if we should have little-endian words even when compiling for
352 big-endian (for backwards compatibility with older versions of GCC). */
353 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
355 /* Nonzero if we need to protect the prolog from scheduling */
356 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
358 /* Nonzero if a call to abort should be generated if a noreturn
359 function tries to return. */
360 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
362 /* Nonzero if function prologues should not load the PIC register. */
363 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
365 /* Nonzero if all call instructions should be indirect. */
366 #define ARM_FLAG_LONG_CALLS (1 << 15)
368 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
369 #define ARM_FLAG_THUMB (1 << 16)
371 /* Set if a TPCS style stack frame should be generated, for non-leaf
372 functions, even if they do not need one. */
373 #define THUMB_FLAG_BACKTRACE (1 << 17)
375 /* Set if a TPCS style stack frame should be generated, for leaf
376 functions, even if they do not need one. */
377 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
379 /* Set if externally visible functions should assume that they
380 might be called in ARM mode, from a non-thumb aware code. */
381 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
383 /* Set if calls via function pointers should assume that their
384 destination is non-Thumb aware. */
385 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
387 /* Nonzero means target uses VFP FP. */
388 #define ARM_FLAG_VFP (1 << 21)
390 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
391 #define ARM_FLAG_ATPCS (1 << 22)
393 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
394 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
396 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
397 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
398 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
399 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
400 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
401 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
402 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
403 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
404 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
405 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
406 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
407 #define TARGET_CIRRUS (arm_is_cirrus)
408 #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
409 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
410 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
411 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
412 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
413 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
414 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
415 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
416 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
417 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
418 #define TARGET_ARM (! TARGET_THUMB)
420 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
421 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
422 #define TARGET_BACKTRACE (leaf_function_p () \
423 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
424 : (target_flags & THUMB_FLAG_BACKTRACE))
425 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
427 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
428 #ifndef SUBTARGET_SWITCHES
429 #define SUBTARGET_SWITCHES
430 #endif
432 #define TARGET_SWITCHES \
433 { \
508 SUBTARGET_SWITCHES \
510 }
512 #define TARGET_OPTIONS \
513 { \
526 }
528 struct arm_cpu_select
529 {
533 };
535 /* This is a magic array. If the user specifies a command line switch
536 which matches one of the entries in TARGET_OPTIONS then the corresponding
537 string pointer will be set to the value specified by the user. */
540 enum prog_mode_type
541 {
542 prog_mode26,
543 prog_mode32
544 };
546 /* Recast the program mode class to be the prog_mode attribute */
547 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
551 /* What sort of floating point unit do we have? Hardware or software.
552 If software, is it issue 2 or issue 3? */
553 enum floating_point_type
554 {
555 FP_HARD,
556 FP_SOFT2,
557 FP_SOFT3,
558 FP_CIRRUS
559 };
561 /* Recast the floating point class to be the floating point attribute. */
562 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
564 /* What type of floating point to tune for */
567 /* What type of floating point instructions are available */
570 /* Default floating point architecture. Override in sub-target if
571 necessary. */
572 #ifndef FP_DEFAULT
573 #define FP_DEFAULT FP_SOFT2
574 #endif
576 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
577 #undef FP_DEFAULT
578 #define FP_DEFAULT FP_CIRRUS
579 #endif
581 /* Nonzero if the processor has a fast multiply insn, and one that does
582 a 64-bit multiply of two 32-bit values. */
585 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
588 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
591 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
594 /* Nonzero if this chip can benefit from load scheduling. */
597 /* Nonzero if generating thumb code. */
600 /* Nonzero if this chip is a StrongARM. */
603 /* Nonzero if this chip is a Cirrus variant. */
606 /* Nonzero if this chip is an XScale. */
609 /* Nonzero if this chip is an ARM6 or an ARM7. */
612 #ifndef TARGET_DEFAULT
613 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
614 #endif
616 /* The frame pointer register used in gcc has nothing to do with debugging;
617 that is controlled by the APCS-FRAME option. */
618 #define CAN_DEBUG_WITHOUT_FP
620 #undef TARGET_MEM_FUNCTIONS
621 #define TARGET_MEM_FUNCTIONS 1
623 #define OVERRIDE_OPTIONS arm_override_options ()
625 /* Nonzero if PIC code requires explicit qualifiers to generate
626 PLT and GOT relocs rather than the assembler doing so implicitly.
627 Subtargets can override these if required. */
628 #ifndef NEED_GOT_RELOC
629 #define NEED_GOT_RELOC 0
630 #endif
631 #ifndef NEED_PLT_RELOC
632 #define NEED_PLT_RELOC 0
633 #endif
635 /* Nonzero if we need to refer to the GOT with a PC-relative
636 offset. In other words, generate
638 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
640 rather than
642 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
644 The default is true, which matches NetBSD. Subtargets can
645 override this if required. */
646 #ifndef GOT_PCREL
647 #define GOT_PCREL 1
648 #endif
649 \f
650 /* Target machine storage Layout. */
653 /* Define this macro if it is advisable to hold scalars in registers
654 in a wider mode than that declared by the program. In such cases,
655 the value is constrained to be within the bounds of the declared
656 type, but kept valid in the wider mode. The signedness of the
657 extension may differ from that of the type. */
659 /* It is far faster to zero extend chars than to sign extend them */
661 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
662 if (GET_MODE_CLASS (MODE) == MODE_INT \
663 && GET_MODE_SIZE (MODE) < 4) \
664 { \
665 if (MODE == QImode) \
666 UNSIGNEDP = 1; \
667 else if (MODE == HImode) \
668 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
669 (MODE) = SImode; \
670 }
672 /* Define this macro if the promotion described by `PROMOTE_MODE'
673 should also be done for outgoing function arguments. */
674 /* This is required to ensure that push insns always push a word. */
675 #define PROMOTE_FUNCTION_ARGS
677 /* Define this if most significant bit is lowest numbered
678 in instructions that operate on numbered bit-fields. */
679 #define BITS_BIG_ENDIAN 0
681 /* Define this if most significant byte of a word is the lowest numbered.
682 Most ARM processors are run in little endian mode, so that is the default.
683 If you want to have it run-time selectable, change the definition in a
684 cover file to be TARGET_BIG_ENDIAN. */
685 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
687 /* Define this if most significant word of a multiword number is the lowest
688 numbered.
689 This is always false, even when in big-endian mode. */
690 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
692 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
693 on processor pre-defineds when compiling libgcc2.c. */
694 #if defined(__ARMEB__) && !defined(__ARMWEL__)
695 #define LIBGCC2_WORDS_BIG_ENDIAN 1
696 #else
697 #define LIBGCC2_WORDS_BIG_ENDIAN 0
698 #endif
700 /* Define this if most significant word of doubles is the lowest numbered.
701 The rules are different based on whether or not we use FPA-format or
702 VFP-format doubles. */
703 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
705 #define UNITS_PER_WORD 4
707 #define PARM_BOUNDARY 32
709 #define STACK_BOUNDARY 32
711 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
713 #define FUNCTION_BOUNDARY 32
715 /* The lowest bit is used to indicate Thumb-mode functions, so the
716 vbit must go into the delta field of pointers to member
717 functions. */
718 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
720 #define EMPTY_FIELD_BOUNDARY 32
722 #define BIGGEST_ALIGNMENT 32
724 /* Make strings word-aligned so strcpy from constants will be faster. */
725 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
727 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
728 ((TREE_CODE (EXP) == STRING_CST \
729 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
730 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
732 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
733 value set in previous versions of this toolchain was 8, which produces more
734 compact structures. The command line option -mstructure_size_boundary=<n>
735 can be used to change this value. For compatibility with the ARM SDK
736 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
737 0020D) page 2-20 says "Structures are aligned on word boundaries". */
738 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
741 /* This is the value used to initialize arm_structure_size_boundary. If a
742 particular arm target wants to change the default value it should change
743 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
744 for an example of this. */
745 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
746 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
747 #endif
749 /* Used when parsing command line option -mstructure_size_boundary. */
752 /* Nonzero if move instructions will actually fail to work
753 when given unaligned data. */
754 #define STRICT_ALIGNMENT 1
755 \f
756 /* Standard register usage. */
758 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
759 (S - saved over call).
761 r0 * argument word/integer result
762 r1-r3 argument word
764 r4-r8 S register variable
765 r9 S (rfp) register variable (real frame pointer)
767 r10 F S (sl) stack limit (used by -mapcs-stack-check)
768 r11 F S (fp) argument pointer
769 r12 (ip) temp workspace
770 r13 F S (sp) lower end of current stack frame
771 r14 (lr) link address/workspace
772 r15 F (pc) program counter
774 f0 floating point result
775 f1-f3 floating point scratch
777 f4-f7 S floating point variable
779 cc This is NOT a real register, but is used internally
780 to represent things that use or set the condition
781 codes.
782 sfp This isn't either. It is used during rtl generation
783 since the offset between the frame pointer and the
784 auto's isn't known until after register allocation.
785 afp Nor this, we only need this because of non-local
786 goto. Without it fp appears to be used and the
787 elimination code won't get rid of sfp. It tracks
788 fp exactly at all times.
790 *: See CONDITIONAL_REGISTER_USAGE */
792 /*
793 mvf0 Cirrus floating point result
794 mvf1-mvf3 Cirrus floating point scratch
795 mvf4-mvf15 S Cirrus floating point variable. */
797 /* The stack backtrace structure is as follows:
798 fp points to here: | save code pointer | [fp]
799 | return link value | [fp, #-4]
800 | return sp value | [fp, #-8]
801 | return fp value | [fp, #-12]
802 [| saved r10 value |]
803 [| saved r9 value |]
804 [| saved r8 value |]
805 [| saved r7 value |]
806 [| saved r6 value |]
807 [| saved r5 value |]
808 [| saved r4 value |]
809 [| saved r3 value |]
810 [| saved r2 value |]
811 [| saved r1 value |]
812 [| saved r0 value |]
813 [| saved f7 value |] three words
814 [| saved f6 value |] three words
815 [| saved f5 value |] three words
816 [| saved f4 value |] three words
817 r0-r3 are not normally saved in a C function. */
819 /* 1 for registers that have pervasive standard uses
820 and are not available for the register allocator. */
821 #define FIXED_REGISTERS \
822 { \
823 0,0,0,0,0,0,0,0, \
824 0,0,0,0,0,1,0,1, \
825 0,0,0,0,0,0,0,0, \
826 1,1,1, \
827 1,1,1,1,1,1,1,1, \
828 1,1,1,1,1,1,1,1 \
829 }
831 /* 1 for registers not available across function calls.
832 These must include the FIXED_REGISTERS and also any
833 registers that can be used without being saved.
834 The latter must include the registers where values are returned
835 and the register where structure-value addresses are passed.
836 Aside from that, you can include as many other registers as you like.
837 The CC is not preserved over function calls on the ARM 6, so it is
838 easier to assume this for all. SFP is preserved, since FP is. */
839 #define CALL_USED_REGISTERS \
840 { \
841 1,1,1,1,0,0,0,0, \
842 0,0,0,0,1,1,1,1, \
843 1,1,1,1,0,0,0,0, \
844 1,1,1, \
845 1,1,1,1,1,1,1,1, \
846 1,1,1,1,1,1,1,1 \
847 }
849 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
850 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
851 #endif
853 #define CONDITIONAL_REGISTER_USAGE \
854 { \
855 int regno; \
856 \
857 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
858 { \
859 for (regno = FIRST_ARM_FP_REGNUM; \
860 regno <= LAST_ARM_FP_REGNUM; ++regno) \
861 fixed_regs[regno] = call_used_regs[regno] = 1; \
862 } \
863 \
864 if (TARGET_CIRRUS) \
865 { \
866 for (regno = FIRST_ARM_FP_REGNUM; \
867 regno <= LAST_ARM_FP_REGNUM; ++ regno) \
868 fixed_regs[regno] = call_used_regs[regno] = 1; \
869 for (regno = FIRST_CIRRUS_FP_REGNUM; \
870 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
871 { \
872 fixed_regs[regno] = 0; \
873 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
874 } \
875 } \
876 \
877 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
878 { \
879 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
880 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
881 } \
882 else if (TARGET_APCS_STACK) \
883 { \
884 fixed_regs[10] = 1; \
885 call_used_regs[10] = 1; \
886 } \
887 if (TARGET_APCS_FRAME) \
888 { \
889 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
890 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
891 } \
892 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
893 }
895 /* These are a couple of extensions to the formats accepted
896 by asm_fprintf:
897 %@ prints out ASM_COMMENT_START
898 %r prints out REGISTER_PREFIX reg_names[arg] */
899 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
901 fputs (ASM_COMMENT_START, FILE); \
902 break; \
903 \
905 fputs (REGISTER_PREFIX, FILE); \
906 fputs (reg_names [va_arg (ARGS, int)], FILE); \
907 break;
909 /* Round X up to the nearest word. */
910 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
912 /* Convert fron bytes to ints. */
913 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
915 /* The number of (integer) registers required to hold a quantity of type MODE. */
916 #define ARM_NUM_REGS(MODE) \
917 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
919 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
920 #define ARM_NUM_REGS2(MODE, TYPE) \
921 ARM_NUM_INTS ((MODE) == BLKmode ? \
922 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
924 /* The number of (integer) argument register available. */
925 #define NUM_ARG_REGS 4
927 /* Return the regiser number of the N'th (integer) argument. */
928 #define ARG_REGISTER(N) (N - 1)
931 returns, and will reserve its own hidden first argument. So
932 if this macro is enabled a *second* hidden argument will be
933 reserved, which will break binary compatibility with old
934 toolchains and also thunk handling. One day this should be
935 fixed. */
936 /* RTX for structure returns. NULL means use a hidden first argument. */
937 #define STRUCT_VALUE 0
938 #else
939 /* Register in which address to store a structure value
940 is passed to a function. */
941 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
942 #endif
944 /* Specify the registers used for certain standard purposes.
945 The values of these macros are register numbers. */
947 /* The number of the last argument register. */
948 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
950 /* The number of the last "lo" register (thumb). */
951 #define LAST_LO_REGNUM 7
953 /* The register that holds the return address in exception handlers. */
954 #define EXCEPTION_LR_REGNUM 2
956 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
957 as an invisible last argument (possible since varargs don't exist in
958 Pascal), so the following is not true. */
959 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
961 /* Define this to be where the real frame pointer is if it is not possible to
962 work out the offset between the frame pointer and the automatic variables
963 until after register allocation has taken place. FRAME_POINTER_REGNUM
964 should point to a special register that we will make sure is eliminated.
966 For the Thumb we have another problem. The TPCS defines the frame pointer
967 as r11, and GCC believes that it is always possible to use the frame pointer
968 as base register for addressing purposes. (See comments in
969 find_reloads_address()). But - the Thumb does not allow high registers,
970 including r11, to be used as base address registers. Hence our problem.
972 The solution used here, and in the old thumb port is to use r7 instead of
973 r11 as the hard frame pointer and to have special code to generate
974 backtrace structures on the stack (if required to do so via a command line
975 option) using r11. This is the only 'user visible' use of r11 as a frame
976 pointer. */
977 #define ARM_HARD_FRAME_POINTER_REGNUM 11
978 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
980 #define HARD_FRAME_POINTER_REGNUM \
981 (TARGET_ARM \
982 ? ARM_HARD_FRAME_POINTER_REGNUM \
983 : THUMB_HARD_FRAME_POINTER_REGNUM)
985 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
987 /* Register to use for pushing function arguments. */
988 #define STACK_POINTER_REGNUM SP_REGNUM
990 /* ARM floating pointer registers. */
991 #define FIRST_ARM_FP_REGNUM 16
992 #define LAST_ARM_FP_REGNUM 23
994 /* Base register for access to local variables of the function. */
995 #define FRAME_POINTER_REGNUM 25
997 /* Base register for access to arguments of the function. */
998 #define ARG_POINTER_REGNUM 26
1000 #define FIRST_CIRRUS_FP_REGNUM 27
1001 #define LAST_CIRRUS_FP_REGNUM 42
1002 #define IS_CIRRUS_REGNUM(REGNUM) \
1003 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1005 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
1006 /* Cirrus registers take us up to 43... */
1007 #define FIRST_PSEUDO_REGISTER 43
1009 /* Value should be nonzero if functions must have frame pointers.
1010 Zero means the frame pointer need not be set up (and parms may be accessed
1011 via the stack pointer) in functions that seem suitable.
1012 If we have to have a frame pointer we might as well make use of it.
1013 APCS says that the frame pointer does not need to be pushed in leaf
1014 functions, or simple tail call functions. */
1015 #define FRAME_POINTER_REQUIRED \
1016 (current_function_has_nonlocal_label \
1017 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1019 /* Return number of consecutive hard regs needed starting at reg REGNO
1020 to hold something of mode MODE.
1021 This is ordinarily the length in words of a value of mode MODE
1022 but can be less for certain modes in special long registers.
1024 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
1025 mode. */
1026 #define HARD_REGNO_NREGS(REGNO, MODE) \
1027 ((TARGET_ARM \
1028 && REGNO >= FIRST_ARM_FP_REGNUM \
1029 && REGNO != FRAME_POINTER_REGNUM \
1030 && REGNO != ARG_POINTER_REGNUM) \
1031 ? 1 : ARM_NUM_REGS (MODE))
1033 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1034 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1035 arm_hard_regno_mode_ok ((REGNO), (MODE))
1037 /* Value is 1 if it is a good idea to tie two pseudo registers
1038 when one has mode MODE1 and one has mode MODE2.
1039 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1040 for any hard reg, then this must be 0 for correct output. */
1041 #define MODES_TIEABLE_P(MODE1, MODE2) \
1042 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1044 /* The order in which register should be allocated. It is good to use ip
1045 since no saving is required (though calls clobber it) and it never contains
1046 function parameters. It is quite good to use lr since other calls may
1047 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1048 least likely to contain a function parameter; in addition results are
1049 returned in r0. */
1050 #define REG_ALLOC_ORDER \
1051 { \
1052 3, 2, 1, 0, 12, 14, 4, 5, \
1053 6, 7, 8, 10, 9, 11, 13, 15, \
1054 16, 17, 18, 19, 20, 21, 22, 23, \
1055 27, 28, 29, 30, 31, 32, 33, 34, \
1056 35, 36, 37, 38, 39, 40, 41, 42, \
1057 24, 25, 26 \
1058 }
1060 /* Interrupt functions can only use registers that have already been
1061 saved by the prologue, even if they would normally be
1062 call-clobbered. */
1063 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1064 (! IS_INTERRUPT (cfun->machine->func_type) || \
1065 regs_ever_live[DST])
1066 \f
1067 /* Register and constant classes. */
1069 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1070 Now that the Thumb is involved it has become more complicated. */
1071 enum reg_class
1072 {
1073 NO_REGS,
1074 FPU_REGS,
1075 CIRRUS_REGS,
1076 LO_REGS,
1077 STACK_REG,
1078 BASE_REGS,
1079 HI_REGS,
1080 CC_REG,
1081 GENERAL_REGS,
1082 ALL_REGS,
1083 LIM_REG_CLASSES
1084 };
1086 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1088 /* Give names of register classes as strings for dump file. */
1089 #define REG_CLASS_NAMES \
1090 { \
1101 }
1103 /* Define which registers fit in which classes.
1104 This is an initializer for a vector of HARD_REG_SET
1105 of length N_REG_CLASSES. */
1106 #define REG_CLASS_CONTENTS \
1107 { \
1118 }
1120 /* The same information, inverted:
1121 Return the class number of the smallest class containing
1122 reg number REGNO. This could be a conditional expression
1123 or could index an array. */
1124 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1126 /* The class value for index registers, and the one for base regs. */
1127 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1128 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1130 /* For the Thumb the high registers cannot be used as base registers
1131 when addressing quantities in QI or HI mode; if we don't know the
1132 mode, then we must be conservative. After reload we must also be
1133 conservative, since we can't support SP+reg addressing, and we
1134 can't fix up any bad substitutions. */
1135 #define MODE_BASE_REG_CLASS(MODE) \
1136 (TARGET_ARM ? GENERAL_REGS : \
1137 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1139 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1140 registers explicitly used in the rtl to be used as spill registers
1141 but prevents the compiler from extending the lifetime of these
1142 registers. */
1143 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1145 /* Get reg_class from a letter such as appears in the machine description.
1146 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1147 ARM, but several more letters for the Thumb. */
1148 #define REG_CLASS_FROM_LETTER(C) \
1152 : TARGET_ARM ? NO_REGS \
1157 : NO_REGS)
1159 /* The letters I, J, K, L and M in a register constraint string
1160 can be used to stand for particular ranges of immediate operands.
1161 This macro defines what the ranges are.
1162 C is the letter, and VALUE is a constant value.
1163 Return 1 if VALUE is in the range specified by C.
1164 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1165 J: valid indexing constants.
1166 K: ~value ok in rhs argument of data operand.
1167 L: -value ok in rhs argument of data operand.
1168 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1169 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1175 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1176 : 0)
1178 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1184 && ((VAL) & 3) == 0) : \
1187 : 0)
1189 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1190 (TARGET_ARM ? \
1191 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1193 /* Constant letter 'G' for the FPU immediate constants.
1194 'H' means the same constant negated. */
1195 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1199 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1200 (TARGET_ARM ? \
1201 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1203 /* For the ARM, `Q' means that this is a memory operand that is just
1204 an offset from a register.
1205 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1206 address. This means that the symbol is in the text segment and can be
1207 accessed without using a load. */
1209 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1212 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1213 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1216 0)
1218 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1220 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1222 #define EXTRA_CONSTRAINT(X, C) \
1223 (TARGET_ARM ? \
1224 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1226 /* Given an rtx X being reloaded into a reg required to be
1227 in class CLASS, return the class of reg to actually use.
1228 In general this is just CLASS, but for the Thumb we prefer
1229 a LO_REGS class or a subset. */
1230 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1231 (TARGET_ARM ? (CLASS) : \
1232 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1234 /* Must leave BASE_REGS reloads alone */
1235 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1236 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1237 ? ((true_regnum (X) == -1 ? LO_REGS \
1238 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1239 : NO_REGS)) \
1240 : NO_REGS)
1242 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1243 ((CLASS) != LO_REGS \
1244 ? ((true_regnum (X) == -1 ? LO_REGS \
1245 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1246 : NO_REGS)) \
1247 : NO_REGS)
1249 /* Return the register class of a scratch register needed to copy IN into
1250 or out of a register in CLASS in MODE. If it can be done directly,
1251 NO_REGS is returned. */
1252 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1253 (TARGET_ARM ? \
1254 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1255 ? GENERAL_REGS : NO_REGS) \
1256 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1258 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1259 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1261 ((TARGET_CIRRUS \
1262 && (CLASS) == CIRRUS_REGS \
1263 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1264 ? GENERAL_REGS : \
1265 (TARGET_ARM ? \
1266 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1267 && (GET_CODE (X) == MEM \
1268 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1269 && true_regnum (X) == -1))) \
1270 ? GENERAL_REGS : NO_REGS) \
1271 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1273 /* Try a machine-dependent way of reloading an illegitimate address
1274 operand. If we find one, push the reload and jump to WIN. This
1275 macro is used in only one place: `find_reloads_address' in reload.c.
1277 For the ARM, we wish to handle large displacements off a base
1278 register by splitting the addend across a MOV and the mem insn.
1279 This can cut the number of reloads needed. */
1280 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1281 do \
1282 { \
1283 if (GET_CODE (X) == PLUS \
1284 && GET_CODE (XEXP (X, 0)) == REG \
1285 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1286 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1287 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1288 { \
1289 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1290 HOST_WIDE_INT low, high; \
1291 \
1292 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1293 low = ((val & 0xf) ^ 0x8) - 0x8; \
1294 else if (TARGET_CIRRUS) \
1296 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1297 else if (MODE == SImode \
1298 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1299 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1301 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1302 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1304 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1305 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1306 && TARGET_HARD_FLOAT) \
1308 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1309 else \
1310 break; \
1311 \
1312 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1313 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1314 - (unsigned HOST_WIDE_INT) 0x80000000); \
1316 if (low == 0 || high == 0 || (high + low != val)) \
1317 break; \
1318 \
1319 /* Reload the high part into a base reg; leave the low part \
1321 X = gen_rtx_PLUS (GET_MODE (X), \
1322 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1323 GEN_INT (high)), \
1324 GEN_INT (low)); \
1325 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1326 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1327 VOIDmode, 0, 0, OPNUM, TYPE); \
1328 goto WIN; \
1329 } \
1330 } \
1331 while (0)
1333 /* ??? If an HImode FP+large_offset address is converted to an HImode
1334 SP+large_offset address, then reload won't know how to fix it. It sees
1335 only that SP isn't valid for HImode, and so reloads the SP into an index
1336 register, but the resulting address is still invalid because the offset
1337 is too big. We fix it here instead by reloading the entire address. */
1338 /* We could probably achieve better results by defining PROMOTE_MODE to help
1339 cope with the variances between the Thumb's signed and unsigned byte and
1340 halfword load instructions. */
1341 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1342 { \
1343 if (GET_CODE (X) == PLUS \
1344 && GET_MODE_SIZE (MODE) < 4 \
1345 && GET_CODE (XEXP (X, 0)) == REG \
1346 && XEXP (X, 0) == stack_pointer_rtx \
1347 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1348 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1349 { \
1350 rtx orig_X = X; \
1351 X = copy_rtx (X); \
1352 push_reload (orig_X, NULL_RTX, &X, NULL, \
1353 MODE_BASE_REG_CLASS (MODE), \
1354 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1355 goto WIN; \
1356 } \
1357 }
1359 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1360 if (TARGET_ARM) \
1361 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1362 else \
1363 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1365 /* Return the maximum number of consecutive registers
1366 needed to represent mode MODE in a register of class CLASS.
1367 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1368 #define CLASS_MAX_NREGS(CLASS, MODE) \
1369 (((CLASS) == FPU_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1371 /* If defined, gives a class of registers that cannot be used as the
1372 operand of a SUBREG that changes the mode of the object illegally. */
1374 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1375 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1376 (TARGET_ARM ? \
1377 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1378 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : \
1379 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1380 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1381 2) \
1382 : \
1383 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1384 \f
1385 /* Stack layout; function entry, exit and calling. */
1387 /* Define this if pushing a word on the stack
1388 makes the stack pointer a smaller address. */
1389 #define STACK_GROWS_DOWNWARD 1
1391 /* Define this if the nominal address of the stack frame
1392 is at the high-address end of the local variables;
1393 that is, each additional local variable allocated
1394 goes at a more negative offset in the frame. */
1395 #define FRAME_GROWS_DOWNWARD 1
1397 /* Offset within stack frame to start allocating local variables at.
1398 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1399 first local allocated. Otherwise, it is the offset to the BEGINNING
1400 of the first local allocated. */
1401 #define STARTING_FRAME_OFFSET 0
1403 /* If we generate an insn to push BYTES bytes,
1404 this says how many the stack pointer really advances by. */
1405 /* The push insns do not do this rounding implicitly.
1406 So don't define this. */
1407 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1409 /* Define this if the maximum size of all the outgoing args is to be
1410 accumulated and pushed during the prologue. The amount can be
1411 found in the variable current_function_outgoing_args_size. */
1412 #define ACCUMULATE_OUTGOING_ARGS 1
1414 /* Offset of first parameter from the argument pointer register value. */
1415 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1417 /* Value is the number of byte of arguments automatically
1418 popped when returning from a subroutine call.
1419 FUNDECL is the declaration node of the function (as a tree),
1420 FUNTYPE is the data type of the function (as a tree),
1421 or for a library call it is an identifier node for the subroutine name.
1422 SIZE is the number of bytes of arguments passed on the stack.
1424 On the ARM, the caller does not pop any of its arguments that were passed
1425 on the stack. */
1426 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1428 /* Define how to find the value returned by a library function
1429 assuming the value has mode MODE. */
1430 #define LIBCALL_VALUE(MODE) \
1431 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1432 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1433 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1434 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1435 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1437 /* Define how to find the value returned by a function.
1438 VALTYPE is the data type of the value (as a tree).
1439 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1440 otherwise, FUNC is 0. */
1441 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1442 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1444 /* 1 if N is a possible register number for a function value.
1445 On the ARM, only r0 and f0 can return results. */
1446 /* On a Cirrus chip, mvf0 can return results. */
1447 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1448 ((REGNO) == ARG_REGISTER (1) \
1449 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
1450 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1452 /* How large values are returned */
1453 /* A C expression which can inhibit the returning of certain function values
1454 in registers, based on the type of value. */
1455 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1457 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1458 values must be in memory. On the ARM, they need only do so if larger
1459 than a word, or if they contain elements offset from zero in the struct. */
1460 #define DEFAULT_PCC_STRUCT_RETURN 0
1462 /* Flags for the call/call_value rtl operations set up by function_arg. */
1467 /* These bits describe the different types of function supported
1468 by the ARM backend. They are exclusive. ie a function cannot be both a
1469 normal function and an interworked function, for example. Knowing the
1470 type of a function is important for determining its prologue and
1471 epilogue sequences.
1472 Note value 7 is currently unassigned. Also note that the interrupt
1473 function types all have bit 2 set, so that they can be tested for easily.
1474 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1475 machine_function structure is initialized (to zero) func_type will
1476 default to unknown. This will force the first use of arm_current_func_type
1477 to call arm_compute_func_type. */
1486 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1488 /* In addition functions can have several type modifiers,
1489 outlined by these bit masks: */
1495 /* Some macros to test these flags. */
1496 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1497 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1498 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1499 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1500 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1502 /* A C structure for machine-specific, per-function data.
1503 This is added to the cfun structure. */
1505 {
1506 /* Additional stack adjustment in __builtin_eh_throw. */
1507 rtx eh_epilogue_sp_ofs;
1508 /* Records if LR has to be saved for far jumps. */
1510 /* Records if ARG_POINTER was ever live. */
1512 /* Records if the save of LR has been eliminated. */
1514 /* The size of the stack frame. Only valid after reload. */
1516 /* Records the type of the current function. */
1518 /* Record if the function has a variable argument list. */
1520 }
1521 machine_function;
1523 /* A C type for declaring a variable that is used as the first argument of
1524 `FUNCTION_ARG' and other related values. For some target machines, the
1525 type `int' suffices and can hold the number of bytes of argument so far. */
1527 {
1528 /* This is the number of registers of arguments scanned so far. */
1530 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1534 /* Define where to put the arguments to a function.
1535 Value is zero to push the argument on the stack,
1536 or a hard register in which to store the argument.
1538 MODE is the argument's machine mode.
1539 TYPE is the data type of the argument (as a tree).
1540 This is null for libcalls where that information may
1541 not be available.
1542 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1543 the preceding args and about the function being called.
1544 NAMED is nonzero if this argument is a named parameter
1545 (otherwise it is an extra parameter matching an ellipsis).
1547 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1548 other arguments are passed on the stack. If (NAMED == 0) (which happens
1549 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1550 passed in the stack (function_prologue will indeed make it pass in the
1551 stack if necessary). */
1552 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1553 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1555 /* For an arg passed partly in registers and partly in memory,
1556 this is the number of registers used.
1557 For args passed entirely in registers or entirely in memory, zero. */
1558 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1559 ( NUM_ARG_REGS > (CUM).nregs \
1560 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1561 ? NUM_ARG_REGS - (CUM).nregs : 0)
1563 /* A C expression that indicates when an argument must be passed by
1564 reference. If nonzero for an argument, a copy of that argument is
1565 made in memory and a pointer to the argument is passed instead of
1566 the argument itself. The pointer is passed in whatever way is
1567 appropriate for passing a pointer to that type. */
1568 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1569 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1571 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1572 for a call to a function whose data type is FNTYPE.
1573 For a library call, FNTYPE is 0.
1574 On the ARM, the offset starts at 0. */
1575 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1576 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1578 /* Update the data in CUM to advance over an argument
1579 of mode MODE and data type TYPE.
1580 (TYPE is null for libcalls where that information may not be available.) */
1581 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1582 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1584 /* 1 if N is a possible register number for function argument passing.
1585 On the ARM, r0-r3 are used to pass args. */
1586 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1588 /* Implement `va_arg'. */
1589 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1590 arm_va_arg (valist, type)
1592 \f
1593 /* Perform any actions needed for a function that is receiving a variable
1594 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1595 of the current parameter. PRETEND_SIZE is a variable that should be set to
1596 the amount of stack that must be pushed by the prolog to pretend that our
1597 caller pushed it.
1599 Normally, this macro will push all remaining incoming registers on the
1600 stack and set PRETEND_SIZE to the length of the registers pushed.
1602 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1603 named arg and all anonymous args onto the stack.
1604 XXX I know the prologue shouldn't be pushing registers, but it is faster
1605 that way. */
1606 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1607 { \
1608 cfun->machine->uses_anonymous_args = 1; \
1609 if ((CUM).nregs < NUM_ARG_REGS) \
1610 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1611 }
1613 /* If your target environment doesn't prefix user functions with an
1614 underscore, you may wish to re-define this to prevent any conflicts.
1615 e.g. AOF may prefix mcount with an underscore. */
1616 #ifndef ARM_MCOUNT_NAME
1618 #endif
1620 /* Call the function profiler with a given profile label. The Acorn
1621 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1622 On the ARM the full profile code will look like:
1623 .data
1624 LP1
1625 .word 0
1626 .text
1627 mov ip, lr
1628 bl mcount
1629 .word LP1
1631 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1632 will output the .text section.
1634 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1635 ``prof'' doesn't seem to mind about this!
1637 Note - this version of the code is designed to work in both ARM and
1638 Thumb modes. */
1639 #ifndef ARM_FUNCTION_PROFILER
1640 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1641 { \
1642 char temp[20]; \
1643 rtx sym; \
1644 \
1646 IP_REGNUM, LR_REGNUM); \
1647 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1650 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1651 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1652 }
1653 #endif
1655 #ifdef THUMB_FUNCTION_PROFILER
1656 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1657 if (TARGET_ARM) \
1658 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1659 else \
1660 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1661 #else
1662 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1663 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1664 #endif
1666 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1667 the stack pointer does not matter. The value is tested only in
1668 functions that have frame pointers.
1669 No definition is equivalent to always zero.
1671 On the ARM, the function epilogue recovers the stack pointer from the
1672 frame. */
1673 #define EXIT_IGNORE_STACK 1
1675 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1677 /* Determine if the epilogue should be output as RTL.
1678 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1679 #define USE_RETURN_INSN(ISCOND) \
1680 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1682 /* Definitions for register eliminations.
1684 This is an array of structures. Each structure initializes one pair
1685 of eliminable registers. The "from" register number is given first,
1686 followed by "to". Eliminations of the same "from" register are listed
1687 in order of preference.
1689 We have two registers that can be eliminated on the ARM. First, the
1690 arg pointer register can often be eliminated in favor of the stack
1691 pointer register. Secondly, the pseudo frame pointer register can always
1692 be eliminated; it is replaced with either the stack or the real frame
1693 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1694 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1696 #define ELIMINABLE_REGS \
1697 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1698 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1699 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1700 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1701 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1702 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1703 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1705 /* Given FROM and TO register numbers, say whether this elimination is
1706 allowed. Frame pointer elimination is automatically handled.
1708 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1709 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1710 pointer, we must eliminate FRAME_POINTER_REGNUM into
1711 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1712 ARG_POINTER_REGNUM. */
1713 #define CAN_ELIMINATE(FROM, TO) \
1714 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1715 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1716 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1717 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1718 1)
1720 #define THUMB_REG_PUSHED_P(reg) \
1721 (regs_ever_live [reg] \
1722 && (! call_used_regs [reg] \
1723 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1724 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1726 /* Define the offset between two registers, one to be eliminated, and the
1727 other its replacement, at the start of a routine. */
1728 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1729 do \
1730 { \
1731 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1732 } \
1733 while (0)
1735 /* Note: This macro must match the code in thumb_function_prologue(). */
1736 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1737 { \
1738 (OFFSET) = 0; \
1739 if ((FROM) == ARG_POINTER_REGNUM) \
1740 { \
1741 int count_regs = 0; \
1742 int regno; \
1743 for (regno = 8; regno < 13; regno ++) \
1744 if (THUMB_REG_PUSHED_P (regno)) \
1745 count_regs ++; \
1746 if (count_regs) \
1747 (OFFSET) += 4 * count_regs; \
1748 count_regs = 0; \
1749 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1750 if (THUMB_REG_PUSHED_P (regno)) \
1751 count_regs ++; \
1752 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1753 (OFFSET) += 4 * (count_regs + 1); \
1754 if (TARGET_BACKTRACE) \
1755 { \
1756 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1757 (OFFSET) += 20; \
1758 else \
1759 (OFFSET) += 16; \
1760 } \
1761 } \
1762 if ((TO) == STACK_POINTER_REGNUM) \
1763 { \
1764 (OFFSET) += current_function_outgoing_args_size; \
1765 (OFFSET) += thumb_get_frame_size (); \
1766 } \
1767 }
1769 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1770 if (TARGET_ARM) \
1771 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1772 else \
1773 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1775 /* Special case handling of the location of arguments passed on the stack. */
1776 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1778 /* Initialize data used by insn expanders. This is called from insn_emit,
1779 once for every function before code is generated. */
1780 #define INIT_EXPANDERS arm_init_expanders ()
1782 /* Output assembler code for a block containing the constant parts
1783 of a trampoline, leaving space for the variable parts.
1785 On the ARM, (if r8 is the static chain regnum, and remembering that
1786 referencing pc adds an offset of 8) the trampoline looks like:
1787 ldr r8, [pc, #0]
1788 ldr pc, [pc]
1789 .word static chain value
1790 .word function's address
1791 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1792 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1793 { \
1795 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1797 PC_REGNUM, PC_REGNUM); \
1798 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1799 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1800 }
1802 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1803 Why - because it is easier. This code will always be branched to via
1804 a BX instruction and since the compiler magically generates the address
1805 of the function the linker has no opportunity to ensure that the
1806 bottom bit is set. Thus the processor will be in ARM mode when it
1807 reaches this code. So we duplicate the ARM trampoline code and add
1808 a switch into Thumb mode as well. */
1809 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1810 { \
1814 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1816 IP_REGNUM, PC_REGNUM); \
1818 IP_REGNUM, IP_REGNUM); \
1823 }
1825 #define TRAMPOLINE_TEMPLATE(FILE) \
1826 if (TARGET_ARM) \
1827 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1828 else \
1829 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1831 /* Length in units of the trampoline for entering a nested function. */
1832 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1834 /* Alignment required for a trampoline in bits. */
1835 #define TRAMPOLINE_ALIGNMENT 32
1837 /* Emit RTL insns to initialize the variable parts of a trampoline.
1838 FNADDR is an RTX for the address of the function's pure code.
1839 CXT is an RTX for the static chain value for the function. */
1840 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1841 { \
1842 emit_move_insn \
1843 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1844 emit_move_insn \
1845 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1846 }
1848 \f
1849 /* Addressing modes, and classification of registers for them. */
1850 #define HAVE_POST_INCREMENT 1
1851 #define HAVE_PRE_INCREMENT TARGET_ARM
1852 #define HAVE_POST_DECREMENT TARGET_ARM
1853 #define HAVE_PRE_DECREMENT TARGET_ARM
1854 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1855 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1856 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1857 #define HAVE_POST_MODIFY_REG TARGET_ARM
1859 /* Macros to check register numbers against specific register classes. */
1861 /* These assume that REGNO is a hard or pseudo reg number.
1862 They give nonzero only if REGNO is a hard reg of the suitable class
1863 or a pseudo reg currently allocated to a suitable hard reg.
1864 Since they use reg_renumber, they are safe only once reg_renumber
1865 has been allocated, which happens in local-alloc.c. */
1866 #define TEST_REGNO(R, TEST, VALUE) \
1867 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1869 /* On the ARM, don't allow the pc to be used. */
1870 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1871 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1872 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1873 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1875 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1876 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1877 || (GET_MODE_SIZE (MODE) >= 4 \
1878 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1880 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1881 (TARGET_THUMB \
1882 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1883 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1885 /* For ARM code, we don't care about the mode, but for Thumb, the index
1886 must be suitable for use in a QImode load. */
1887 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1888 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1890 /* Maximum number of registers that can appear in a valid memory address.
1891 Shifts in addresses can't be by a register. */
1892 #define MAX_REGS_PER_ADDRESS 2
1894 /* Recognize any constant value that is a valid address. */
1895 /* XXX We can address any constant, eventually... */
1897 #ifdef AOF_ASSEMBLER
1899 #define CONSTANT_ADDRESS_P(X) \
1900 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1902 #else
1904 #define CONSTANT_ADDRESS_P(X) \
1905 (GET_CODE (X) == SYMBOL_REF \
1906 && (CONSTANT_POOL_ADDRESS_P (X) \
1907 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1911 /* Nonzero if the constant value X is a legitimate general operand.
1912 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1914 On the ARM, allow any integer (invalid ones are removed later by insn
1915 patterns), nice doubles and symbol_refs which refer to the function's
1916 constant pool XXX.
1918 When generating pic allow anything. */
1919 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1921 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1922 ( GET_CODE (X) == CONST_INT \
1923 || GET_CODE (X) == CONST_DOUBLE \
1924 || CONSTANT_ADDRESS_P (X) \
1925 || flag_pic)
1927 #define LEGITIMATE_CONSTANT_P(X) \
1928 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1930 /* Special characters prefixed to function names
1931 in order to encode attribute like information.
1932 Note, '@' and '*' have already been taken. */
1936 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1937 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1939 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1940 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1942 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1943 #define SUBTARGET_NAME_ENCODING_LENGTHS
1944 #endif
1946 /* This is a C fragment for the inside of a switch statement.
1947 Each case label should return the number of characters to
1948 be stripped from the start of a function's name, if that
1949 name starts with the indicated character. */
1950 #define ARM_NAME_ENCODING_LENGTHS \
1951 case SHORT_CALL_FLAG_CHAR: return 1; \
1952 case LONG_CALL_FLAG_CHAR: return 1; \
1954 SUBTARGET_NAME_ENCODING_LENGTHS
1956 /* This is how to output a reference to a user-level label named NAME.
1957 `assemble_name' uses this. */
1958 #undef ASM_OUTPUT_LABELREF
1959 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1960 arm_asm_output_labelref (FILE, NAME)
1962 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1963 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1965 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1966 and check its validity for a certain class.
1967 We have two alternate definitions for each of them.
1968 The usual definition accepts all pseudo regs; the other rejects
1969 them unless they have been allocated suitable hard regs.
1970 The symbol REG_OK_STRICT causes the latter definition to be used. */
1971 #ifndef REG_OK_STRICT
1973 #define ARM_REG_OK_FOR_BASE_P(X) \
1974 (REGNO (X) <= LAST_ARM_REGNUM \
1975 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1976 || REGNO (X) == FRAME_POINTER_REGNUM \
1977 || REGNO (X) == ARG_POINTER_REGNUM)
1979 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1980 (REGNO (X) <= LAST_LO_REGNUM \
1981 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1982 || (GET_MODE_SIZE (MODE) >= 4 \
1983 && (REGNO (X) == STACK_POINTER_REGNUM \
1984 || (X) == hard_frame_pointer_rtx \
1985 || (X) == arg_pointer_rtx)))
1987 #define REG_STRICT_P 0
1991 #define ARM_REG_OK_FOR_BASE_P(X) \
1992 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1994 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1995 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1997 #define REG_STRICT_P 1
2001 /* Now define some helpers in terms of the above. */
2003 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2004 (TARGET_THUMB \
2005 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2006 : ARM_REG_OK_FOR_BASE_P (X))
2008 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2010 /* For Thumb, a valid index register is anything that can be used in
2011 a byte load instruction. */
2012 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2014 /* Nonzero if X is a hard reg that can be used as an index
2015 or if it is a pseudo reg. On the Thumb, the stack pointer
2016 is not suitable. */
2017 #define REG_OK_FOR_INDEX_P(X) \
2018 (TARGET_THUMB \
2019 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2020 : ARM_REG_OK_FOR_INDEX_P (X))
2022 \f
2023 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2024 that is a valid memory address for an instruction.
2025 The MODE argument is the machine mode for the MEM expression
2026 that wants to use this address. */
2028 #define ARM_BASE_REGISTER_RTX_P(X) \
2029 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2031 #define ARM_INDEX_REGISTER_RTX_P(X) \
2032 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2034 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2035 { \
2036 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2037 goto WIN; \
2038 }
2040 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2041 { \
2042 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2043 goto WIN; \
2044 }
2046 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2047 if (TARGET_ARM) \
2048 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2050 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2052 \f
2053 /* Try machine-dependent ways of modifying an illegitimate address
2054 to be legitimate. If we find one, return the new, valid address. */
2055 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2056 do { \
2057 X = arm_legitimize_address (X, OLDX, MODE); \
2058 \
2059 if (memory_address_p (MODE, X)) \
2060 goto WIN; \
2061 } while (0)
2063 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2064 do { \
2065 if (flag_pic) \
2066 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2067 } while (0)
2069 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2070 do { \
2071 if (TARGET_ARM) \
2072 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2073 else \
2074 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2075 } while (0)
2077 /* Go to LABEL if ADDR (a legitimate address expression)
2078 has an effect that depends on the machine mode it is used for. */
2079 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2080 { \
2081 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2082 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2083 goto LABEL; \
2084 }
2086 /* Nothing helpful to do for the Thumb */
2087 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2088 if (TARGET_ARM) \
2089 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2090 \f
2092 /* Specify the machine mode that this machine uses
2093 for the index in the tablejump instruction. */
2094 #define CASE_VECTOR_MODE Pmode
2096 /* Define as C expression which evaluates to nonzero if the tablejump
2097 instruction expects the table to contain offsets from the address of the
2098 table.
2099 Do not define this if the table should contain absolute addresses. */
2100 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2102 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2103 unsigned is probably best, but may break some code. */
2104 #ifndef DEFAULT_SIGNED_CHAR
2105 #define DEFAULT_SIGNED_CHAR 0
2106 #endif
2108 /* Don't cse the address of the function being compiled. */
2109 #define NO_RECURSIVE_FUNCTION_CSE 1
2111 /* Max number of bytes we can move from memory to memory
2112 in one reasonably fast instruction. */
2113 #define MOVE_MAX 4
2115 #undef MOVE_RATIO
2116 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2118 /* Define if operations between registers always perform the operation
2119 on the full register even if a narrower mode is specified. */
2120 #define WORD_REGISTER_OPERATIONS
2122 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2123 will either zero-extend or sign-extend. The value of this macro should
2124 be the code that says which one of the two operations is implicitly
2125 done, NIL if none. */
2126 #define LOAD_EXTEND_OP(MODE) \
2127 (TARGET_THUMB ? ZERO_EXTEND : \
2128 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2129 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2131 /* Nonzero if access to memory by bytes is slow and undesirable. */
2132 #define SLOW_BYTE_ACCESS 0
2134 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2136 /* Immediate shift counts are truncated by the output routines (or was it
2137 the assembler?). Shift counts in a register are truncated by ARM. Note
2138 that the native compiler puts too large (> 32) immediate shift counts
2139 into a register and shifts by the register, letting the ARM decide what
2140 to do instead of doing that itself. */
2141 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2142 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2143 On the arm, Y in a register is used modulo 256 for the shift. Only for
2144 rotates is modulo 32 used. */
2145 /* #define SHIFT_COUNT_TRUNCATED 1 */
2147 /* All integers have the same format so truncation is easy. */
2148 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2150 /* Calling from registers is a massive pain. */
2151 #define NO_FUNCTION_CSE 1
2153 /* Chars and shorts should be passed as ints. */
2154 #define PROMOTE_PROTOTYPES 1
2156 /* The machine modes of pointers and functions */
2157 #define Pmode SImode
2158 #define FUNCTION_MODE Pmode
2160 #define ARM_FRAME_RTX(X) \
2161 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2162 || (X) == arg_pointer_rtx)
2164 /* Moves to and from memory are quite expensive */
2165 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2166 (TARGET_ARM ? 10 : \
2167 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2168 * (CLASS == LO_REGS ? 1 : 2)))
2170 /* Try to generate sequences that don't involve branches, we can then use
2171 conditional instructions */
2172 #define BRANCH_COST \
2173 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2174 \f
2175 /* Position Independent Code. */
2176 /* We decide which register to use based on the compilation options and
2177 the assembler in use; this is more general than the APCS restriction of
2178 using sb (r9) all the time. */
2181 /* Used when parsing command line option -mpic-register=. */
2184 /* The register number of the register used to address a table of static
2185 data addresses in memory. */
2186 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2188 #define FINALIZE_PIC arm_finalize_pic (1)
2190 /* We can't directly access anything that contains a symbol,
2191 nor can we indirect via the constant pool. */
2192 #define LEGITIMATE_PIC_OPERAND_P(X) \
2193 (!(symbol_mentioned_p (X) \
2194 || label_mentioned_p (X) \
2195 || (GET_CODE (X) == SYMBOL_REF \
2196 && CONSTANT_POOL_ADDRESS_P (X) \
2197 && (symbol_mentioned_p (get_pool_constant (X)) \
2198 || label_mentioned_p (get_pool_constant (X))))))
2200 /* We need to know when we are making a constant pool; this determines
2201 whether data needs to be in the GOT or can be referenced via a GOT
2202 offset. */
2204 \f
2205 /* Handle pragmas for compatibility with Intel's compilers. */
2206 #define REGISTER_TARGET_PRAGMAS() do { \
2210 } while (0)
2212 /* Condition code information. */
2213 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2214 return the mode to be used for the comparison. */
2216 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2218 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2220 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2221 do \
2222 { \
2223 if (GET_CODE (OP1) == CONST_INT \
2224 && ! (const_ok_for_arm (INTVAL (OP1)) \
2225 || (const_ok_for_arm (- INTVAL (OP1))))) \
2226 { \
2227 rtx const_op = OP1; \
2228 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2229 OP1 = const_op; \
2230 } \
2231 } \
2232 while (0)
2234 #define STORE_FLAG_VALUE 1
2236 /* The arm5 clz instruction returns 32. */
2237 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2238 \f
2240 /* Gcc puts the pool in the wrong place for ARM, since we can only
2241 load addresses a limited distance around the pc. We do some
2242 special munging to move the constant pool values to the correct
2243 point in the code. */
2244 #define MACHINE_DEPENDENT_REORG(INSN) \
2245 arm_reorg (INSN); \
2247 #undef ASM_APP_OFF
2250 /* Output a push or a pop instruction (only used when profiling). */
2251 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2252 if (TARGET_ARM) \
2254 STACK_POINTER_REGNUM, REGNO); \
2255 else \
2259 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2260 if (TARGET_ARM) \
2262 STACK_POINTER_REGNUM, REGNO); \
2263 else \
2266 /* This is how to output a label which precedes a jumptable. Since
2267 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2268 #undef ASM_OUTPUT_CASE_LABEL
2269 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2270 do \
2271 { \
2272 if (TARGET_THUMB) \
2273 ASM_OUTPUT_ALIGN (FILE, 2); \
2274 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2275 } \
2276 while (0)
2278 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2279 do \
2280 { \
2281 if (TARGET_THUMB) \
2282 { \
2283 if (is_called_in_ARM_mode (DECL)) \
2285 else \
2287 } \
2288 if (TARGET_POKE_FUNCTION_NAME) \
2289 arm_poke_function_name (STREAM, (char *) NAME); \
2290 } \
2291 while (0)
2293 /* For aliases of functions we use .thumb_set instead. */
2294 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2295 do \
2296 { \
2297 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2298 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2299 \
2300 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2301 { \
2303 assemble_name (FILE, LABEL1); \
2305 assemble_name (FILE, LABEL2); \
2307 } \
2308 else \
2309 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2310 } \
2311 while (0)
2313 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2314 /* To support -falign-* switches we need to use .p2align so
2315 that alignment directives in code sections will be padded
2316 with no-op instructions, rather than zeroes. */
2317 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2318 if ((LOG) != 0) \
2319 { \
2320 if ((MAX_SKIP) == 0) \
2322 else \
2324 (LOG), (MAX_SKIP)); \
2325 }
2326 #endif
2327 \f
2328 /* Only perform branch elimination (by making instructions conditional) if
2329 we're optimising. Otherwise it's of no use anyway. */
2330 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2331 if (TARGET_ARM && optimize) \
2332 arm_final_prescan_insn (INSN); \
2333 else if (TARGET_THUMB) \
2334 thumb_final_prescan_insn (INSN)
2336 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2341 /* Output an operand of an instruction. */
2342 #define PRINT_OPERAND(STREAM, X, CODE) \
2343 arm_print_operand (STREAM, X, CODE)
2345 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2346 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2347 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2348 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2349 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2350 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2351 : 0))))
2353 /* Output the address of an operand. */
2354 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2355 { \
2356 int is_minus = GET_CODE (X) == MINUS; \
2357 \
2358 if (GET_CODE (X) == REG) \
2360 else if (GET_CODE (X) == PLUS || is_minus) \
2361 { \
2362 rtx base = XEXP (X, 0); \
2363 rtx index = XEXP (X, 1); \
2364 HOST_WIDE_INT offset = 0; \
2365 if (GET_CODE (base) != REG) \
2366 { \
2369 rtx temp = base; \
2370 base = index; \
2371 index = temp; \
2372 } \
2373 switch (GET_CODE (index)) \
2374 { \
2375 case CONST_INT: \
2376 offset = INTVAL (index); \
2377 if (is_minus) \
2378 offset = -offset; \
2380 REGNO (base), offset); \
2381 break; \
2382 \
2383 case REG: \
2386 REGNO (index)); \
2387 break; \
2388 \
2389 case MULT: \
2390 case ASHIFTRT: \
2391 case LSHIFTRT: \
2392 case ASHIFT: \
2393 case ROTATERT: \
2394 { \
2397 REGNO (XEXP (index, 0))); \
2400 break; \
2401 } \
2402 \
2403 default: \
2404 abort(); \
2405 } \
2406 } \
2407 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2408 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2409 { \
2410 extern enum machine_mode output_memory_reference_mode; \
2411 \
2412 if (GET_CODE (XEXP (X, 0)) != REG) \
2413 abort (); \
2414 \
2415 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2417 REGNO (XEXP (X, 0)), \
2419 GET_MODE_SIZE (output_memory_reference_mode)); \
2420 else \
2422 REGNO (XEXP (X, 0)), \
2424 GET_MODE_SIZE (output_memory_reference_mode)); \
2425 } \
2426 else if (GET_CODE (X) == PRE_MODIFY) \
2427 { \
2429 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2431 INTVAL (XEXP (XEXP (X, 1), 1))); \
2432 else \
2434 REGNO (XEXP (XEXP (X, 1), 1))); \
2435 } \
2436 else if (GET_CODE (X) == POST_MODIFY) \
2437 { \
2439 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2441 INTVAL (XEXP (XEXP (X, 1), 1))); \
2442 else \
2444 REGNO (XEXP (XEXP (X, 1), 1))); \
2445 } \
2446 else output_addr_const (STREAM, X); \
2447 }
2449 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2450 { \
2451 if (GET_CODE (X) == REG) \
2453 else if (GET_CODE (X) == POST_INC) \
2455 else if (GET_CODE (X) == PLUS) \
2456 { \
2457 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2459 REGNO (XEXP (X, 0)), \
2460 (int) INTVAL (XEXP (X, 1))); \
2461 else \
2463 REGNO (XEXP (X, 0)), \
2464 REGNO (XEXP (X, 1))); \
2465 } \
2466 else \
2467 output_addr_const (STREAM, X); \
2468 }
2470 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2471 if (TARGET_ARM) \
2472 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2473 else \
2474 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2476 /* A C expression whose value is RTL representing the value of the return
2477 address for the frame COUNT steps up from the current frame. */
2479 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2480 arm_return_addr (COUNT, FRAME)
2482 /* Mask of the bits in the PC that contain the real return address
2483 when running in 26-bit mode. */
2484 #define RETURN_ADDR_MASK26 (0x03fffffc)
2486 /* Pick up the return address upon entry to a procedure. Used for
2487 dwarf2 unwind information. This also enables the table driven
2488 mechanism. */
2489 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2490 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2492 /* Used to mask out junk bits from the return address, such as
2493 processor state, interrupt status, condition codes and the like. */
2494 #define MASK_RETURN_ADDR \
2495 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2496 in 26 bit mode, the condition codes must be masked out of the \
2497 return address. This does not apply to ARM6 and later processors \
2499 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2500 : (arm_arch4 || TARGET_THUMB) ? \
2501 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2502 : arm_gen_return_addr_mask ())
2504 \f
2505 /* Define the codes that are matched by predicates in arm.c */
2506 #define PREDICATE_CODES \
2532 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2533 UNGE, UNGT}}, \
2544 /* Define this if you have special predicates that know special things
2545 about modes. Genrecog will warn about certain forms of
2546 match_operand without a mode; if the operand predicate is listed in
2547 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2548 #define SPECIAL_MODE_PREDICATES \