1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
32 #include "coretypes.h"
37 #include "hard-reg-set.h"
39 #include "insn-config.h"
40 #include "conditions.h"
41 #include "insn-attr.h"
57 #include "target-def.h"
60 #define STAB_CODE_TYPE enum __stab_debug_code
62 #define STAB_CODE_TYPE int
65 extern tree lookup_name
PARAMS ((tree
));
67 /* Enumeration for all of the relational tests, so that we can build
68 arrays indexed by the test type, and not worry about the order
88 static enum internal_test map_test_to_internal_test
PARAMS ((enum rtx_code
));
89 static void get_float_compare_codes
PARAMS ((enum rtx_code
, enum rtx_code
*,
91 static int mips16_simple_memory_operand
PARAMS ((rtx
, rtx
,
93 static int m16_check_op
PARAMS ((rtx
, int, int, int));
94 static void block_move_loop
PARAMS ((rtx
, rtx
,
98 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
99 static void mips_arg_info
PARAMS ((const CUMULATIVE_ARGS
*,
102 struct mips_arg_info
*));
103 static rtx mips_add_large_offset_to_sp
PARAMS ((HOST_WIDE_INT
));
104 static void mips_annotate_frame_insn
PARAMS ((rtx
, rtx
));
105 static rtx mips_frame_set
PARAMS ((enum machine_mode
,
107 static void mips_emit_frame_related_store
PARAMS ((rtx
, rtx
,
109 static void save_restore_insns
PARAMS ((int, rtx
, long));
110 static void mips16_output_gp_offset
PARAMS ((FILE *, rtx
));
111 static void mips16_fp_args
PARAMS ((FILE *, int, int));
112 static void build_mips16_function_stub
PARAMS ((FILE *));
113 static void mips16_optimize_gp
PARAMS ((rtx
));
114 static rtx add_constant
PARAMS ((struct constant
**,
117 static void dump_constants
PARAMS ((struct constant
*,
119 static rtx mips_find_symbol
PARAMS ((rtx
));
120 static void abort_with_insn
PARAMS ((rtx
, const char *))
122 static int symbolic_expression_p
PARAMS ((rtx
));
123 static bool mips_assemble_integer
PARAMS ((rtx
, unsigned int, int));
124 static void mips_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
125 static void mips_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
126 static void mips_set_architecture
PARAMS ((const struct mips_cpu_info
*));
127 static void mips_set_tune
PARAMS ((const struct mips_cpu_info
*));
128 static bool mips_strict_matching_cpu_name_p
PARAMS ((const char *,
130 static bool mips_matching_cpu_name_p
PARAMS ((const char *,
132 static const struct mips_cpu_info
*mips_parse_cpu
PARAMS ((const char *,
134 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
135 static void copy_file_data
PARAMS ((FILE *, FILE *));
137 static void iris6_asm_named_section_1
PARAMS ((const char *,
140 static void iris6_asm_named_section
PARAMS ((const char *,
142 static int iris_section_align_entry_eq
PARAMS ((const PTR
, const PTR
));
143 static hashval_t iris_section_align_entry_hash
PARAMS ((const PTR
));
144 static int iris6_section_align_1
PARAMS ((void **, void *));
146 static int mips_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
147 static int mips_issue_rate
PARAMS ((void));
149 static struct machine_function
* mips_init_machine_status
PARAMS ((void));
150 static void mips_select_section
PARAMS ((tree
, int, unsigned HOST_WIDE_INT
))
152 static void mips_unique_section
PARAMS ((tree
, int))
154 static void mips_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
155 unsigned HOST_WIDE_INT
));
156 static int mips_use_dfa_pipeline_interface
PARAMS ((void));
157 static void mips_encode_section_info
PARAMS ((tree
, rtx
, int));
158 static bool mips_rtx_costs
PARAMS ((rtx
, int, int, int *));
159 static int mips_address_cost
PARAMS ((rtx
));
162 /* Structure to be filled in by compute_frame_size with register
163 save masks, and offsets for the current function. */
165 struct mips_frame_info
GTY(())
167 long total_size
; /* # bytes that the entire frame takes up */
168 long var_size
; /* # bytes that variables take up */
169 long args_size
; /* # bytes that outgoing arguments take up */
170 long extra_size
; /* # bytes of extra gunk */
171 int gp_reg_size
; /* # bytes needed to store gp regs */
172 int fp_reg_size
; /* # bytes needed to store fp regs */
173 long mask
; /* mask of saved gp registers */
174 long fmask
; /* mask of saved fp registers */
175 long gp_save_offset
; /* offset from vfp to store gp registers */
176 long fp_save_offset
; /* offset from vfp to store fp registers */
177 long gp_sp_offset
; /* offset from new sp to store gp registers */
178 long fp_sp_offset
; /* offset from new sp to store fp registers */
179 int initialized
; /* != 0 if frame size already calculated */
180 int num_gp
; /* number of gp registers saved */
181 int num_fp
; /* number of fp registers saved */
184 struct machine_function
GTY(()) {
185 /* Pseudo-reg holding the address of the current function when
186 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
187 used by mips_finalize_pic if it was created. */
188 rtx embedded_pic_fnaddr_rtx
;
190 /* Pseudo-reg holding the value of $28 in a mips16 function which
191 refers to GP relative global variables. */
192 rtx mips16_gp_pseudo_rtx
;
194 /* Current frame information, calculated by compute_frame_size. */
195 struct mips_frame_info frame
;
197 /* Length of instructions in function; mips16 only. */
201 /* Information about a single argument. */
204 /* True if the argument is a record or union type. */
207 /* True if the argument is passed in a floating-point register, or
208 would have been if we hadn't run out of registers. */
211 /* The argument's size, in bytes. */
212 unsigned int num_bytes
;
214 /* The number of words passed in registers, rounded up. */
215 unsigned int reg_words
;
217 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
218 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
220 unsigned int reg_offset
;
222 /* The number of words that must be passed on the stack, rounded up. */
223 unsigned int stack_words
;
225 /* The offset from the start of the stack overflow area of the argument's
226 first stack word. Only meaningful when STACK_WORDS is nonzero. */
227 unsigned int stack_offset
;
230 /* Global variables for machine-dependent things. */
232 /* Threshold for data being put into the small data/bss area, instead
233 of the normal data area (references to the small data/bss area take
234 1 instruction, and use the global pointer, references to the normal
235 data area takes 2 instructions). */
236 int mips_section_threshold
= -1;
238 /* Count the number of .file directives, so that .loc is up to date. */
239 int num_source_filenames
= 0;
241 /* Count the number of sdb related labels are generated (to find block
242 start and end boundaries). */
243 int sdb_label_count
= 0;
245 /* Next label # for each statement for Silicon Graphics IRIS systems. */
248 /* Nonzero if inside of a function, because the stupid MIPS asm can't
249 handle .files inside of functions. */
250 int inside_function
= 0;
252 /* Files to separate the text and the data output, so that all of the data
253 can be emitted before the text, which will mean that the assembler will
254 generate smaller code, based on the global pointer. */
255 FILE *asm_out_data_file
;
256 FILE *asm_out_text_file
;
258 /* Linked list of all externals that are to be emitted when optimizing
259 for the global pointer if they haven't been declared by the end of
260 the program with an appropriate .comm or initialization. */
264 struct extern_list
*next
; /* next external */
265 const char *name
; /* name of the external */
266 int size
; /* size in bytes */
269 /* Name of the file containing the current function. */
270 const char *current_function_file
= "";
272 /* Warning given that Mips ECOFF can't support changing files
273 within a function. */
274 int file_in_function_warning
= FALSE
;
276 /* Whether to suppress issuing .loc's because the user attempted
277 to change the filename within a function. */
278 int ignore_line_number
= FALSE
;
280 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
286 /* The next branch instruction is a branch likely, not branch normal. */
287 int mips_branch_likely
;
289 /* Count of delay slots and how many are filled. */
290 int dslots_load_total
;
291 int dslots_load_filled
;
292 int dslots_jump_total
;
293 int dslots_jump_filled
;
295 /* # of nops needed by previous insn */
296 int dslots_number_nops
;
298 /* Number of 1/2/3 word references to data items (ie, not jal's). */
301 /* registers to check for load delay */
302 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
304 /* Cached operands, and operator to compare for use in set/branch/trap
305 on condition codes. */
308 /* what type of branch to use */
309 enum cmp_type branch_type
;
311 /* The target cpu for code generation. */
312 enum processor_type mips_arch
;
313 const struct mips_cpu_info
*mips_arch_info
;
315 /* The target cpu for optimization and scheduling. */
316 enum processor_type mips_tune
;
317 const struct mips_cpu_info
*mips_tune_info
;
319 /* which instruction set architecture to use. */
322 /* which abi to use. */
325 /* Strings to hold which cpu and instruction set architecture to use. */
326 const char *mips_arch_string
; /* for -march=<xxx> */
327 const char *mips_tune_string
; /* for -mtune=<xxx> */
328 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
329 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
331 /* Whether we are generating mips16 code. This is a synonym for
332 TARGET_MIPS16, and exists for use as an attribute. */
335 /* This variable is set by -mno-mips16. We only care whether
336 -mno-mips16 appears or not, and using a string in this fashion is
337 just a way to avoid using up another bit in target_flags. */
338 const char *mips_no_mips16_string
;
340 /* Whether we are generating mips16 hard float code. In mips16 mode
341 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
342 -msoft-float was not specified by the user, which means that we
343 should arrange to call mips32 hard floating point code. */
344 int mips16_hard_float
;
346 /* This variable is set by -mentry. We only care whether -mentry
347 appears or not, and using a string in this fashion is just a way to
348 avoid using up another bit in target_flags. */
349 const char *mips_entry_string
;
351 const char *mips_cache_flush_func
= CACHE_FLUSH_FUNC
;
353 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
356 /* If TRUE, we split addresses into their high and low parts in the RTL. */
357 int mips_split_addresses
;
359 /* Generating calls to position independent functions? */
360 enum mips_abicalls_type mips_abicalls
;
362 /* Mode used for saving/restoring general purpose registers. */
363 static enum machine_mode gpr_mode
;
365 /* Array giving truth value on whether or not a given hard register
366 can support a given mode. */
367 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
369 /* The length of all strings seen when compiling for the mips16. This
370 is used to tell how many strings are in the constant pool, so that
371 we can see if we may have an overflow. This is reset each time the
372 constant pool is output. */
373 int mips_string_length
;
375 /* When generating mips16 code, a list of all strings that are to be
376 output after the current function. */
378 static GTY(()) rtx mips16_strings
;
380 /* In mips16 mode, we build a list of all the string constants we see
381 in a particular function. */
383 struct string_constant
385 struct string_constant
*next
;
389 static struct string_constant
*string_constants
;
391 /* List of all MIPS punctuation characters used by print_operand. */
392 char mips_print_operand_punct
[256];
394 /* Map GCC register number to debugger register number. */
395 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
397 /* Buffer to use to enclose a load/store operation with %{ %} to
398 turn on .set volatile. */
399 static char volatile_buffer
[60];
401 /* Hardware names for the registers. If -mrnames is used, this
402 will be overwritten with mips_sw_reg_names. */
404 char mips_reg_names
[][8] =
406 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
407 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
408 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
409 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
410 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
411 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
412 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
413 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
414 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
415 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
416 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
417 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
418 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
419 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
420 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
421 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
422 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
423 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
424 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
425 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
426 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
427 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
430 /* Mips software names for the registers, used to overwrite the
431 mips_reg_names array. */
433 char mips_sw_reg_names
[][8] =
435 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
436 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
437 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
438 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
439 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
440 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
441 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
442 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
443 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
444 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
445 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
446 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
447 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
448 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
449 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
450 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
451 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
452 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
453 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
454 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
455 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
456 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
459 /* Map hard register number to register class */
460 const enum reg_class mips_regno_to_class
[] =
462 GR_REGS
, GR_REGS
, M16_NA_REGS
, M16_NA_REGS
,
463 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
464 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
465 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
466 M16_NA_REGS
, M16_NA_REGS
, GR_REGS
, GR_REGS
,
467 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
468 T_REG
, GR_REGS
, GR_REGS
, GR_REGS
,
469 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
470 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
471 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
472 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
473 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
474 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
475 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
476 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
477 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
478 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
479 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
480 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
,
481 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
482 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
483 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
484 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
485 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
486 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
487 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
488 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
489 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
490 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
491 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
492 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
493 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
494 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
495 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
496 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
497 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
498 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
499 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
500 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
501 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
502 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
503 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
504 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
505 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
508 /* Map register constraint character to register class. */
509 enum reg_class mips_char_to_class
[256] =
511 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
512 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
513 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
514 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
515 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
516 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
517 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
518 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
519 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
520 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
521 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
522 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
523 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
524 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
525 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
526 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
527 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
528 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
529 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
530 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
531 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
532 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
533 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
534 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
535 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
536 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
537 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
538 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
539 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
540 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
541 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
542 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
543 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
544 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
545 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
546 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
547 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
548 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
549 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
550 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
551 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
552 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
553 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
554 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
555 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
556 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
557 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
558 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
559 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
560 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
561 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
562 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
563 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
564 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
565 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
566 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
567 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
568 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
569 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
570 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
571 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
572 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
573 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
574 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
577 /* A table describing all the processors gcc knows about. Names are
578 matched in the order listed. The first mention of an ISA level is
579 taken as the canonical name for that ISA.
581 To ease comparison, please keep this table in the same order as
582 gas's mips_cpu_info_table[]. */
583 const struct mips_cpu_info mips_cpu_info_table
[] = {
584 /* Entries for generic ISAs */
585 { "mips1", PROCESSOR_R3000
, 1 },
586 { "mips2", PROCESSOR_R6000
, 2 },
587 { "mips3", PROCESSOR_R4000
, 3 },
588 { "mips4", PROCESSOR_R8000
, 4 },
589 { "mips32", PROCESSOR_4KC
, 32 },
590 { "mips32r2", PROCESSOR_M4K
, 33 },
591 { "mips64", PROCESSOR_5KC
, 64 },
594 { "r3000", PROCESSOR_R3000
, 1 },
595 { "r2000", PROCESSOR_R3000
, 1 }, /* = r3000 */
596 { "r3900", PROCESSOR_R3900
, 1 },
599 { "r6000", PROCESSOR_R6000
, 2 },
602 { "r4000", PROCESSOR_R4000
, 3 },
603 { "vr4100", PROCESSOR_R4100
, 3 },
604 { "vr4111", PROCESSOR_R4111
, 3 },
605 { "vr4120", PROCESSOR_R4120
, 3 },
606 { "vr4300", PROCESSOR_R4300
, 3 },
607 { "r4400", PROCESSOR_R4000
, 3 }, /* = r4000 */
608 { "r4600", PROCESSOR_R4600
, 3 },
609 { "orion", PROCESSOR_R4600
, 3 }, /* = r4600 */
610 { "r4650", PROCESSOR_R4650
, 3 },
613 { "r8000", PROCESSOR_R8000
, 4 },
614 { "vr5000", PROCESSOR_R5000
, 4 },
615 { "vr5400", PROCESSOR_R5400
, 4 },
616 { "vr5500", PROCESSOR_R5500
, 4 },
619 { "4kc", PROCESSOR_4KC
, 32 },
620 { "4kp", PROCESSOR_4KC
, 32 }, /* = 4kc */
622 /* MIPS32 Release 2 */
623 { "m4k", PROCESSOR_M4K
, 33 },
626 { "5kc", PROCESSOR_5KC
, 64 },
627 { "20kc", PROCESSOR_20KC
, 64 },
628 { "sb1", PROCESSOR_SB1
, 64 },
629 { "sr71000", PROCESSOR_SR71000
, 64 },
635 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
636 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
637 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
640 /* Initialize the GCC target structure. */
641 #undef TARGET_ASM_ALIGNED_HI_OP
642 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
643 #undef TARGET_ASM_ALIGNED_SI_OP
644 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
645 #undef TARGET_ASM_INTEGER
646 #define TARGET_ASM_INTEGER mips_assemble_integer
648 #if TARGET_IRIX5 && !TARGET_IRIX6
649 #undef TARGET_ASM_UNALIGNED_HI_OP
650 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
651 #undef TARGET_ASM_UNALIGNED_SI_OP
652 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
653 #undef TARGET_ASM_UNALIGNED_DI_OP
654 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.dword\t"
657 #undef TARGET_ASM_FUNCTION_PROLOGUE
658 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
659 #undef TARGET_ASM_FUNCTION_EPILOGUE
660 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
661 #undef TARGET_ASM_SELECT_RTX_SECTION
662 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
664 #undef TARGET_SCHED_ADJUST_COST
665 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
666 #undef TARGET_SCHED_ISSUE_RATE
667 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
668 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
669 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
671 #undef TARGET_ENCODE_SECTION_INFO
672 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
674 #undef TARGET_VALID_POINTER_MODE
675 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
676 #undef TARGET_RTX_COSTS
677 #define TARGET_RTX_COSTS mips_rtx_costs
678 #undef TARGET_ADDRESS_COST
679 #define TARGET_ADDRESS_COST mips_address_cost
681 struct gcc_target targetm
= TARGET_INITIALIZER
;
683 /* Return truth value of whether OP can be used as an operands
684 where a register or 16 bit unsigned integer is needed. */
687 uns_arith_operand (op
, mode
)
689 enum machine_mode mode
;
691 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
694 return register_operand (op
, mode
);
697 /* Return truth value of whether OP can be used as an operands
698 where a 16 bit integer is needed */
701 arith_operand (op
, mode
)
703 enum machine_mode mode
;
705 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
708 /* On the mips16, a GP relative value is a signed 16 bit offset. */
709 if (TARGET_MIPS16
&& GET_CODE (op
) == CONST
&& mips16_gp_offset_p (op
))
712 return register_operand (op
, mode
);
715 /* Return truth value of whether OP can be used as an operand in a two
716 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
719 arith32_operand (op
, mode
)
721 enum machine_mode mode
;
723 if (GET_CODE (op
) == CONST_INT
)
726 return register_operand (op
, mode
);
729 /* Return truth value of whether OP is an integer which fits in 16 bits. */
734 enum machine_mode mode ATTRIBUTE_UNUSED
;
736 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
739 /* Return truth value of whether OP is a 32 bit integer which is too big to
740 be loaded with one instruction. */
745 enum machine_mode mode ATTRIBUTE_UNUSED
;
749 if (GET_CODE (op
) != CONST_INT
)
754 /* ior reg,$r0,value */
755 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
758 /* subu reg,$r0,value */
759 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
762 /* lui reg,value>>16 */
763 if ((value
& 0x0000ffff) == 0)
769 /* Return truth value of whether OP is a register or the constant 0.
770 In mips16 mode, we only accept a register, since the mips16 does
774 reg_or_0_operand (op
, mode
)
776 enum machine_mode mode
;
778 switch (GET_CODE (op
))
783 return INTVAL (op
) == 0;
788 return op
== CONST0_RTX (mode
);
791 return register_operand (op
, mode
);
795 /* Return truth value of whether OP is a register or the constant 0,
796 even in mips16 mode. */
799 true_reg_or_0_operand (op
, mode
)
801 enum machine_mode mode
;
803 switch (GET_CODE (op
))
806 return INTVAL (op
) == 0;
809 return op
== CONST0_RTX (mode
);
812 return register_operand (op
, mode
);
816 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
819 mips_const_double_ok (op
, mode
)
821 enum machine_mode mode
;
823 if (GET_CODE (op
) != CONST_DOUBLE
)
826 if (mode
== VOIDmode
)
829 /* We've no zero register in mips16 mode. */
833 if (mode
!= SFmode
&& mode
!= DFmode
)
836 if (op
== CONST0_RTX (mode
))
842 /* Accept the floating point constant 1 in the appropriate mode. */
845 const_float_1_operand (op
, mode
)
847 enum machine_mode mode
;
851 if (GET_CODE (op
) != CONST_DOUBLE
852 || mode
!= GET_MODE (op
)
853 || (mode
!= DFmode
&& mode
!= SFmode
))
856 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
858 return REAL_VALUES_EQUAL (d
, dconst1
);
861 /* Return true if a memory load or store of REG plus OFFSET in MODE
862 can be represented in a single word on the mips16. */
865 mips16_simple_memory_operand (reg
, offset
, mode
)
868 enum machine_mode mode
;
875 /* We can't tell, because we don't know how the value will
876 eventually be accessed. Returning 0 here does no great
877 harm; it just prevents some possible instruction scheduling. */
881 size
= GET_MODE_SIZE (mode
);
883 if (INTVAL (offset
) % size
!= 0)
885 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode
) == 4)
889 if (INTVAL (offset
) >= 0 && INTVAL (offset
) < (HOST_WIDE_INT
)(off
* size
))
894 /* Return truth value if a memory operand fits in a single instruction
895 (ie, register + small offset). */
898 simple_memory_operand (op
, mode
)
900 enum machine_mode mode
;
902 rtx addr
, plus0
, plus1
;
904 /* Eliminate non-memory operations */
905 if (GET_CODE (op
) != MEM
)
908 /* dword operations really put out 2 instructions, so eliminate them. */
909 /* ??? This isn't strictly correct. It is OK to accept multiword modes
910 here, since the length attributes are being set correctly, but only
911 if the address is offsettable. LO_SUM is not offsettable. */
912 if (GET_MODE_SIZE (GET_MODE (op
)) > (unsigned) UNITS_PER_WORD
)
915 /* Decode the address now. */
917 switch (GET_CODE (addr
))
926 return SMALL_INT (addr
);
929 plus0
= XEXP (addr
, 0);
930 plus1
= XEXP (addr
, 1);
931 if (GET_CODE (plus0
) == REG
932 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
)
934 || mips16_simple_memory_operand (plus0
, plus1
, mode
)))
937 else if (GET_CODE (plus1
) == REG
938 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)
940 || mips16_simple_memory_operand (plus1
, plus0
, mode
)))
947 /* We used to allow small symbol refs here (ie, stuff in .sdata
948 or .sbss), but this causes some bugs in G++. Also, it won't
949 interfere if the MIPS linker rewrites the store instruction
950 because the function is PIC. */
952 case LABEL_REF
: /* never gp relative */
956 /* If -G 0, we can never have a GP relative memory operation.
957 Also, save some time if not optimizing. */
962 rtx offset
= const0_rtx
;
963 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
964 if (GET_CODE (op
) != SYMBOL_REF
)
967 /* let's be paranoid.... */
968 if (! SMALL_INT (offset
))
975 return SYMBOL_REF_FLAG (addr
);
978 /* This SYMBOL_REF case is for the mips16. If the above case is
979 reenabled, this one should be merged in. */
981 /* References to the constant pool on the mips16 use a small
982 offset if the function is small. The only time we care about
983 getting this right is during delayed branch scheduling, so
984 don't need to check until then. The machine_dependent_reorg
985 function will set the total length of the instructions used
986 in the function (cfun->machine->insns_len). If that is small
987 enough, we know for sure that this is a small offset. It
988 would be better if we could take into account the location of
989 the instruction within the function, but we can't, because we
990 don't know where we are. */
992 && CONSTANT_POOL_ADDRESS_P (addr
)
993 && cfun
->machine
->insns_len
> 0)
997 size
= cfun
->machine
->insns_len
+ get_pool_size ();
998 if (GET_MODE_SIZE (mode
) == 4)
999 return size
< 4 * 0x100;
1000 else if (GET_MODE_SIZE (mode
) == 8)
1001 return size
< 8 * 0x20;
1015 /* Return nonzero for a memory address that can be used to load or store
1019 double_memory_operand (op
, mode
)
1021 enum machine_mode mode
;
1023 if (GET_CODE (op
) != MEM
1024 || ! memory_operand (op
, mode
))
1026 /* During reload, we accept a pseudo register if it has an
1027 appropriate memory address. If we don't do this, we will
1028 wind up reloading into a register, and then reloading that
1029 register from memory, when we could just reload directly from
1031 if (reload_in_progress
1032 && GET_CODE (op
) == REG
1033 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
1034 && reg_renumber
[REGNO (op
)] < 0
1035 && reg_equiv_mem
[REGNO (op
)] != 0
1036 && double_memory_operand (reg_equiv_mem
[REGNO (op
)], mode
))
1039 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
1040 the same test performed for 'm' in find_reloads. */
1042 if (reload_in_progress
1044 && (GET_CODE (op
) == MEM
1045 || (GET_CODE (op
) == REG
1046 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
1047 && reg_renumber
[REGNO (op
)] < 0)))
1050 if (reload_in_progress
1052 && GET_CODE (op
) == MEM
)
1056 addr
= XEXP (op
, 0);
1058 /* During reload on the mips16, we accept a large offset
1059 from the frame pointer or the stack pointer. This large
1060 address will get reloaded anyhow. */
1061 if (GET_CODE (addr
) == PLUS
1062 && GET_CODE (XEXP (addr
, 0)) == REG
1063 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1064 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1065 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1066 && ! SMALL_INT (XEXP (addr
, 1)))
1067 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1068 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1071 /* Similarly, we accept a case where the memory address is
1072 itself on the stack, and will be reloaded. */
1073 if (GET_CODE (addr
) == MEM
)
1077 maddr
= XEXP (addr
, 0);
1078 if (GET_CODE (maddr
) == PLUS
1079 && GET_CODE (XEXP (maddr
, 0)) == REG
1080 && (REGNO (XEXP (maddr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1081 || REGNO (XEXP (maddr
, 0)) == STACK_POINTER_REGNUM
)
1082 && ((GET_CODE (XEXP (maddr
, 1)) == CONST_INT
1083 && ! SMALL_INT (XEXP (maddr
, 1)))
1084 || (GET_CODE (XEXP (maddr
, 1)) == SYMBOL_REF
1085 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr
, 1)))))
1089 /* We also accept the same case when we have a 16 bit signed
1090 offset mixed in as well. The large address will get
1091 reloaded, and the 16 bit offset will be OK. */
1092 if (GET_CODE (addr
) == PLUS
1093 && GET_CODE (XEXP (addr
, 0)) == MEM
1094 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
1095 && SMALL_INT (XEXP (addr
, 1)))
1097 addr
= XEXP (XEXP (addr
, 0), 0);
1098 if (GET_CODE (addr
) == PLUS
1099 && GET_CODE (XEXP (addr
, 0)) == REG
1100 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1101 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1102 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1103 && ! SMALL_INT (XEXP (addr
, 1)))
1104 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1105 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1115 /* In this case we can use an instruction like sd. */
1119 /* Make sure that 4 added to the address is a valid memory address.
1120 This essentially just checks for overflow in an added constant. */
1122 if (CONSTANT_ADDRESS_P (XEXP (op
, 0)))
1125 op
= adjust_address_nv (op
, GET_MODE_CLASS (mode
) == MODE_INT
1126 ? SImode
: SFmode
, 4);
1127 return memory_address_p (GET_MODE (op
), XEXP (op
, 0));
1130 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1133 equality_op (op
, mode
)
1135 enum machine_mode mode
;
1137 if (mode
!= GET_MODE (op
))
1140 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
1143 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1148 enum machine_mode mode
;
1150 if (mode
!= GET_MODE (op
))
1153 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
1156 /* Return nonzero if the code is a relational operation suitable for a
1157 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1158 We need this in the insn that expands `trap_if' in order to prevent
1159 combine from erroneously altering the condition. */
1162 trap_cmp_op (op
, mode
)
1164 enum machine_mode mode
;
1166 if (mode
!= GET_MODE (op
))
1169 switch (GET_CODE (op
))
1184 /* Return nonzero if the operand is either the PC or a label_ref. */
1187 pc_or_label_operand (op
, mode
)
1189 enum machine_mode mode ATTRIBUTE_UNUSED
;
1194 if (GET_CODE (op
) == LABEL_REF
)
1200 /* Test for a valid operand for a call instruction.
1201 Don't allow the arg pointer register or virtual regs
1202 since they may change into reg + const, which the patterns
1203 can't handle yet. */
1206 call_insn_operand (op
, mode
)
1208 enum machine_mode mode ATTRIBUTE_UNUSED
;
1210 return (CONSTANT_ADDRESS_P (op
)
1211 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
1212 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1213 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
1216 /* Return nonzero if OPERAND is valid as a source operand for a move
1220 move_operand (op
, mode
)
1222 enum machine_mode mode
;
1224 /* Accept any general operand after reload has started; doing so
1225 avoids losing if reload does an in-place replacement of a register
1226 with a SYMBOL_REF or CONST. */
1227 return (general_operand (op
, mode
)
1228 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
1229 || reload_in_progress
|| reload_completed
)
1231 && GET_CODE (op
) == SYMBOL_REF
1232 && ! mips16_constant (op
, mode
, 1, 0)));
1235 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1236 This accepts not only general_operand, but also sign extended
1237 move_operands. Note that we need to accept sign extended constants
1238 in case a sign extended register which is used in an expression,
1239 and is equivalent to a constant, is spilled. We need to accept
1240 sign-extended memory in order to reload registers from stack slots,
1241 and so that we generate efficient code for extendsidi2. */
1244 movdi_operand (op
, mode
)
1246 enum machine_mode mode
;
1250 && GET_CODE (op
) == SIGN_EXTEND
1251 && GET_MODE (op
) == DImode
1252 && move_operand (XEXP (op
, 0), SImode
))
1255 return (general_operand (op
, mode
)
1257 && GET_CODE (op
) == SYMBOL_REF
1258 && ! mips16_constant (op
, mode
, 1, 0)));
1261 /* Like register_operand, but when in 64 bit mode also accept a sign
1262 extend of a 32 bit register, since the value is known to be already
1266 se_register_operand (op
, mode
)
1268 enum machine_mode mode
;
1272 && GET_CODE (op
) == SIGN_EXTEND
1273 && GET_MODE (op
) == DImode
1274 && GET_MODE (XEXP (op
, 0)) == SImode
1275 && register_operand (XEXP (op
, 0), SImode
))
1278 return register_operand (op
, mode
);
1281 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1282 extend of a 32 bit register, since the value is known to be already
1286 se_reg_or_0_operand (op
, mode
)
1288 enum machine_mode mode
;
1292 && GET_CODE (op
) == SIGN_EXTEND
1293 && GET_MODE (op
) == DImode
1294 && GET_MODE (XEXP (op
, 0)) == SImode
1295 && register_operand (XEXP (op
, 0), SImode
))
1298 return reg_or_0_operand (op
, mode
);
1301 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1302 extend of a 32 bit register, since the value is known to be already
1306 se_uns_arith_operand (op
, mode
)
1308 enum machine_mode mode
;
1312 && GET_CODE (op
) == SIGN_EXTEND
1313 && GET_MODE (op
) == DImode
1314 && GET_MODE (XEXP (op
, 0)) == SImode
1315 && register_operand (XEXP (op
, 0), SImode
))
1318 return uns_arith_operand (op
, mode
);
1321 /* Like arith_operand, but when in 64 bit mode also accept a sign
1322 extend of a 32 bit register, since the value is known to be already
1326 se_arith_operand (op
, mode
)
1328 enum machine_mode mode
;
1332 && GET_CODE (op
) == SIGN_EXTEND
1333 && GET_MODE (op
) == DImode
1334 && GET_MODE (XEXP (op
, 0)) == SImode
1335 && register_operand (XEXP (op
, 0), SImode
))
1338 return arith_operand (op
, mode
);
1341 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1342 extend of a 32 bit register, since the value is known to be already
1346 se_nonmemory_operand (op
, mode
)
1348 enum machine_mode mode
;
1352 && GET_CODE (op
) == SIGN_EXTEND
1353 && GET_MODE (op
) == DImode
1354 && GET_MODE (XEXP (op
, 0)) == SImode
1355 && register_operand (XEXP (op
, 0), SImode
))
1358 return nonmemory_operand (op
, mode
);
1361 /* Accept any operand that can appear in a mips16 constant table
1362 instruction. We can't use any of the standard operand functions
1363 because for these instructions we accept values that are not
1364 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1367 consttable_operand (op
, mode
)
1369 enum machine_mode mode ATTRIBUTE_UNUSED
;
1371 return CONSTANT_P (op
);
1374 /* Coprocessor operand; return true if rtx is a REG and refers to a
1378 coprocessor_operand (op
, mode
)
1380 enum machine_mode mode ATTRIBUTE_UNUSED
;
1382 return (GET_CODE (op
) == REG
1383 && COP0_REG_FIRST
<= REGNO (op
)
1384 && REGNO (op
) <= COP3_REG_LAST
);
1388 coprocessor2_operand (op
, mode
)
1390 enum machine_mode mode ATTRIBUTE_UNUSED
;
1392 return (GET_CODE (op
) == REG
1393 && COP2_REG_FIRST
<= REGNO (op
)
1394 && REGNO (op
) <= COP2_REG_LAST
);
1397 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1398 possibly with an offset. */
1401 symbolic_operand (op
, mode
)
1403 enum machine_mode mode
;
1405 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1407 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1409 if (GET_CODE (op
) == CONST
1410 && GET_CODE (XEXP (op
,0)) == PLUS
1411 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1412 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1417 /* Return nonzero if we split the address into high and low parts. */
1419 /* ??? We should also handle reg+array somewhere. We get four
1420 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1421 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1422 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1423 out of the address, then we have 4 instructions to combine. Perhaps
1424 add a 3->2 define_split for combine. */
1426 /* ??? We could also split a CONST_INT here if it is a large_int().
1427 However, it doesn't seem to be very useful to have %hi(constant).
1428 We would be better off by doing the masking ourselves and then putting
1429 the explicit high part of the constant in the RTL. This will give better
1430 optimization. Also, %hi(constant) needs assembler changes to work.
1431 There is already a define_split that does this. */
1434 mips_check_split (address
, mode
)
1436 enum machine_mode mode
;
1438 /* ??? This is the same check used in simple_memory_operand.
1439 We use it here because LO_SUM is not offsettable. */
1440 if (GET_MODE_SIZE (mode
) > (unsigned) UNITS_PER_WORD
)
1443 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
1444 || (GET_CODE (address
) == CONST
1445 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
1446 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
1447 || GET_CODE (address
) == LABEL_REF
)
1453 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1456 mips_reg_mode_ok_for_base_p (reg
, mode
, strict
)
1458 enum machine_mode mode
;
1462 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg
), mode
)
1463 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg
), mode
));
1466 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1467 returns a nonzero value if XINSN is a legitimate address for a
1468 memory operand of the indicated MODE. STRICT is nonzero if this
1469 function is called during reload. */
1472 mips_legitimate_address_p (mode
, xinsn
, strict
)
1473 enum machine_mode mode
;
1477 if (TARGET_DEBUG_B_MODE
)
1479 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1480 strict
? "" : "not ");
1481 GO_DEBUG_RTX (xinsn
);
1484 /* Check for constant before stripping off SUBREG, so that we don't
1485 accept (subreg (const_int)) which will fail to reload. */
1486 if (CONSTANT_ADDRESS_P (xinsn
)
1487 && ! (mips_split_addresses
&& mips_check_split (xinsn
, mode
))
1488 && (! TARGET_MIPS16
|| mips16_constant (xinsn
, mode
, 1, 0)))
1491 while (GET_CODE (xinsn
) == SUBREG
)
1492 xinsn
= SUBREG_REG (xinsn
);
1494 /* The mips16 can only use the stack pointer as a base register when
1495 loading SImode or DImode values. */
1496 if (GET_CODE (xinsn
) == REG
1497 && mips_reg_mode_ok_for_base_p (xinsn
, mode
, strict
))
1500 if (GET_CODE (xinsn
) == LO_SUM
&& mips_split_addresses
)
1502 register rtx xlow0
= XEXP (xinsn
, 0);
1503 register rtx xlow1
= XEXP (xinsn
, 1);
1505 while (GET_CODE (xlow0
) == SUBREG
)
1506 xlow0
= SUBREG_REG (xlow0
);
1507 if (GET_CODE (xlow0
) == REG
1508 && mips_reg_mode_ok_for_base_p (xlow0
, mode
, strict
)
1509 && mips_check_split (xlow1
, mode
))
1513 if (GET_CODE (xinsn
) == PLUS
)
1515 register rtx xplus0
= XEXP (xinsn
, 0);
1516 register rtx xplus1
= XEXP (xinsn
, 1);
1517 register enum rtx_code code0
;
1518 register enum rtx_code code1
;
1520 while (GET_CODE (xplus0
) == SUBREG
)
1521 xplus0
= SUBREG_REG (xplus0
);
1522 code0
= GET_CODE (xplus0
);
1524 while (GET_CODE (xplus1
) == SUBREG
)
1525 xplus1
= SUBREG_REG (xplus1
);
1526 code1
= GET_CODE (xplus1
);
1528 /* The mips16 can only use the stack pointer as a base register
1529 when loading SImode or DImode values. */
1531 && mips_reg_mode_ok_for_base_p (xplus0
, mode
, strict
))
1533 if (code1
== CONST_INT
&& SMALL_INT (xplus1
))
1536 /* On the mips16, we represent GP relative offsets in RTL.
1537 These are 16 bit signed values, and can serve as register
1540 && mips16_gp_offset_p (xplus1
))
1543 /* For some code sequences, you actually get better code by
1544 pretending that the MIPS supports an address mode of a
1545 constant address + a register, even though the real
1546 machine doesn't support it. This is because the
1547 assembler can use $r1 to load just the high 16 bits, add
1548 in the register, and fold the low 16 bits into the memory
1549 reference, whereas the compiler generates a 4 instruction
1550 sequence. On the other hand, CSE is not as effective.
1551 It would be a win to generate the lui directly, but the
1552 MIPS assembler does not have syntax to generate the
1553 appropriate relocation. */
1555 /* Also accept CONST_INT addresses here, so no else. */
1556 /* Reject combining an embedded PIC text segment reference
1557 with a register. That requires an additional
1559 /* ??? Reject combining an address with a register for the MIPS
1560 64 bit ABI, because the SGI assembler can not handle this. */
1561 if (!TARGET_DEBUG_A_MODE
1562 && (mips_abi
== ABI_32
1563 || mips_abi
== ABI_O64
1564 || mips_abi
== ABI_EABI
)
1565 && CONSTANT_ADDRESS_P (xplus1
)
1566 && ! mips_split_addresses
1567 && (!TARGET_EMBEDDED_PIC
1569 || GET_CODE (XEXP (xplus1
, 0)) != MINUS
)
1570 /* When assembling for machines with 64 bit registers,
1571 the assembler will sign-extend the constant "foo"
1572 in "la x, foo(x)" yielding the wrong result for:
1573 (set (blah:DI) (plus x y)). */
1575 || (code1
== CONST_INT
1576 && trunc_int_for_mode (INTVAL (xplus1
),
1577 SImode
) == INTVAL (xplus1
)))
1583 if (TARGET_DEBUG_B_MODE
)
1584 GO_PRINTF ("Not a legitimate address\n");
1586 /* The address was not legitimate. */
1591 /* We need a lot of little routines to check constant values on the
1592 mips16. These are used to figure out how long the instruction will
1593 be. It would be much better to do this using constraints, but
1594 there aren't nearly enough letters available. */
1597 m16_check_op (op
, low
, high
, mask
)
1603 return (GET_CODE (op
) == CONST_INT
1604 && INTVAL (op
) >= low
1605 && INTVAL (op
) <= high
1606 && (INTVAL (op
) & mask
) == 0);
1610 m16_uimm3_b (op
, mode
)
1612 enum machine_mode mode ATTRIBUTE_UNUSED
;
1614 return m16_check_op (op
, 0x1, 0x8, 0);
1618 m16_simm4_1 (op
, mode
)
1620 enum machine_mode mode ATTRIBUTE_UNUSED
;
1622 return m16_check_op (op
, - 0x8, 0x7, 0);
1626 m16_nsimm4_1 (op
, mode
)
1628 enum machine_mode mode ATTRIBUTE_UNUSED
;
1630 return m16_check_op (op
, - 0x7, 0x8, 0);
1634 m16_simm5_1 (op
, mode
)
1636 enum machine_mode mode ATTRIBUTE_UNUSED
;
1638 return m16_check_op (op
, - 0x10, 0xf, 0);
1642 m16_nsimm5_1 (op
, mode
)
1644 enum machine_mode mode ATTRIBUTE_UNUSED
;
1646 return m16_check_op (op
, - 0xf, 0x10, 0);
1650 m16_uimm5_4 (op
, mode
)
1652 enum machine_mode mode ATTRIBUTE_UNUSED
;
1654 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1658 m16_nuimm5_4 (op
, mode
)
1660 enum machine_mode mode ATTRIBUTE_UNUSED
;
1662 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1666 m16_simm8_1 (op
, mode
)
1668 enum machine_mode mode ATTRIBUTE_UNUSED
;
1670 return m16_check_op (op
, - 0x80, 0x7f, 0);
1674 m16_nsimm8_1 (op
, mode
)
1676 enum machine_mode mode ATTRIBUTE_UNUSED
;
1678 return m16_check_op (op
, - 0x7f, 0x80, 0);
1682 m16_uimm8_1 (op
, mode
)
1684 enum machine_mode mode ATTRIBUTE_UNUSED
;
1686 return m16_check_op (op
, 0x0, 0xff, 0);
1690 m16_nuimm8_1 (op
, mode
)
1692 enum machine_mode mode ATTRIBUTE_UNUSED
;
1694 return m16_check_op (op
, - 0xff, 0x0, 0);
1698 m16_uimm8_m1_1 (op
, mode
)
1700 enum machine_mode mode ATTRIBUTE_UNUSED
;
1702 return m16_check_op (op
, - 0x1, 0xfe, 0);
1706 m16_uimm8_4 (op
, mode
)
1708 enum machine_mode mode ATTRIBUTE_UNUSED
;
1710 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1714 m16_nuimm8_4 (op
, mode
)
1716 enum machine_mode mode ATTRIBUTE_UNUSED
;
1718 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1722 m16_simm8_8 (op
, mode
)
1724 enum machine_mode mode ATTRIBUTE_UNUSED
;
1726 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1730 m16_nsimm8_8 (op
, mode
)
1732 enum machine_mode mode ATTRIBUTE_UNUSED
;
1734 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1737 /* References to the string table on the mips16 only use a small
1738 offset if the function is small. See the comment in the SYMBOL_REF
1739 case in simple_memory_operand. We can't check for LABEL_REF here,
1740 because the offset is always large if the label is before the
1741 referencing instruction. */
1744 m16_usym8_4 (op
, mode
)
1746 enum machine_mode mode ATTRIBUTE_UNUSED
;
1748 if (GET_CODE (op
) == SYMBOL_REF
1749 && SYMBOL_REF_FLAG (op
)
1750 && cfun
->machine
->insns_len
> 0
1751 && XSTR (op
, 0)[0] == '*'
1752 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1753 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1754 && (cfun
->machine
->insns_len
+ get_pool_size () + mips_string_length
1757 struct string_constant
*l
;
1759 /* Make sure this symbol is on thelist of string constants to be
1760 output for this function. It is possible that it has already
1761 been output, in which case this requires a large offset. */
1762 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1763 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1771 m16_usym5_4 (op
, mode
)
1773 enum machine_mode mode ATTRIBUTE_UNUSED
;
1775 if (GET_CODE (op
) == SYMBOL_REF
1776 && SYMBOL_REF_FLAG (op
)
1777 && cfun
->machine
->insns_len
> 0
1778 && XSTR (op
, 0)[0] == '*'
1779 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1780 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1781 && (cfun
->machine
->insns_len
+ get_pool_size () + mips_string_length
1784 struct string_constant
*l
;
1786 /* Make sure this symbol is on thelist of string constants to be
1787 output for this function. It is possible that it has already
1788 been output, in which case this requires a large offset. */
1789 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1790 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1797 /* Returns an operand string for the given instruction's delay slot,
1798 after updating filled delay slot statistics.
1800 We assume that operands[0] is the target register that is set.
1802 In order to check the next insn, most of this functionality is moved
1803 to FINAL_PRESCAN_INSN, and we just set the global variables that
1806 /* ??? This function no longer does anything useful, because final_prescan_insn
1807 now will never emit a nop. */
1810 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
1811 const char *ret
; /* normal string to return */
1812 enum delay_type type
; /* type of delay */
1813 rtx operands
[]; /* operands to use */
1814 rtx cur_insn
; /* current insn */
1816 register rtx set_reg
;
1817 register enum machine_mode mode
;
1818 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
1819 register int num_nops
;
1821 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
1824 else if (type
== DELAY_HILO
)
1830 /* Make sure that we don't put nop's after labels. */
1831 next_insn
= NEXT_INSN (cur_insn
);
1832 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
1833 next_insn
= NEXT_INSN (next_insn
);
1835 dslots_load_total
+= num_nops
;
1836 if (TARGET_DEBUG_F_MODE
1838 || type
== DELAY_NONE
1842 || GET_CODE (next_insn
) == CODE_LABEL
1843 || (set_reg
= operands
[0]) == 0)
1845 dslots_number_nops
= 0;
1853 set_reg
= operands
[0];
1857 while (GET_CODE (set_reg
) == SUBREG
)
1858 set_reg
= SUBREG_REG (set_reg
);
1860 mode
= GET_MODE (set_reg
);
1861 dslots_number_nops
= num_nops
;
1862 mips_load_reg
= set_reg
;
1863 if (GET_MODE_SIZE (mode
)
1864 > (unsigned) (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
1865 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
1869 if (type
== DELAY_HILO
)
1871 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
1872 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
1884 /* Determine whether a memory reference takes one (based off of the GP
1885 pointer), two (normal), or three (label + reg) instructions, and bump the
1886 appropriate counter for -mstats. */
1889 mips_count_memory_refs (op
, num
)
1895 rtx addr
, plus0
, plus1
;
1896 enum rtx_code code0
, code1
;
1899 if (TARGET_DEBUG_B_MODE
)
1901 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1905 /* Skip MEM if passed, otherwise handle movsi of address. */
1906 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1908 /* Loop, going through the address RTL. */
1912 switch (GET_CODE (addr
))
1920 plus0
= XEXP (addr
, 0);
1921 plus1
= XEXP (addr
, 1);
1922 code0
= GET_CODE (plus0
);
1923 code1
= GET_CODE (plus1
);
1933 if (code0
== CONST_INT
)
1948 if (code1
== CONST_INT
)
1955 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1962 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1972 n_words
= 2; /* always 2 words */
1976 addr
= XEXP (addr
, 0);
1981 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1993 n_words
+= additional
;
1997 num_refs
[n_words
-1] += num
;
2001 /* Return a pseudo that points to the address of the current function.
2002 The first time it is called for a function, an initializer for the
2003 pseudo is emitted in the beginning of the function. */
2006 embedded_pic_fnaddr_reg ()
2008 if (cfun
->machine
->embedded_pic_fnaddr_rtx
== NULL
)
2012 cfun
->machine
->embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
2014 /* Output code at function start to initialize the pseudo-reg. */
2015 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2016 inline functions, because it is called after RTL for the function
2017 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2018 does not get copied, and ends up not matching the rest of the RTL.
2019 This solution works, but means that we get unnecessary code to
2020 initialize this value every time a function is inlined into another
2023 emit_insn (gen_get_fnaddr (cfun
->machine
->embedded_pic_fnaddr_rtx
,
2024 XEXP (DECL_RTL (current_function_decl
), 0)));
2027 push_topmost_sequence ();
2028 emit_insn_after (seq
, get_insns ());
2029 pop_topmost_sequence ();
2032 return cfun
->machine
->embedded_pic_fnaddr_rtx
;
2035 /* Return RTL for the offset from the current function to the argument.
2036 X is the symbol whose offset from the current function we want. */
2039 embedded_pic_offset (x
)
2042 /* Make sure it is emitted. */
2043 embedded_pic_fnaddr_reg ();
2046 gen_rtx_CONST (Pmode
,
2047 gen_rtx_MINUS (Pmode
, x
,
2048 XEXP (DECL_RTL (current_function_decl
), 0)));
2051 /* Return the appropriate instructions to move one operand to another. */
2054 mips_move_1word (operands
, insn
, unsignedp
)
2059 const char *ret
= 0;
2060 rtx op0
= operands
[0];
2061 rtx op1
= operands
[1];
2062 enum rtx_code code0
= GET_CODE (op0
);
2063 enum rtx_code code1
= GET_CODE (op1
);
2064 enum machine_mode mode
= GET_MODE (op0
);
2065 int subreg_offset0
= 0;
2066 int subreg_offset1
= 0;
2067 enum delay_type delay
= DELAY_NONE
;
2069 while (code0
== SUBREG
)
2071 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2072 GET_MODE (SUBREG_REG (op0
)),
2075 op0
= SUBREG_REG (op0
);
2076 code0
= GET_CODE (op0
);
2079 while (code1
== SUBREG
)
2081 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2082 GET_MODE (SUBREG_REG (op1
)),
2085 op1
= SUBREG_REG (op1
);
2086 code1
= GET_CODE (op1
);
2089 /* For our purposes, a condition code mode is the same as SImode. */
2095 int regno0
= REGNO (op0
) + subreg_offset0
;
2099 int regno1
= REGNO (op1
) + subreg_offset1
;
2101 /* Just in case, don't do anything for assigning a register
2102 to itself, unless we are filling a delay slot. */
2103 if (regno0
== regno1
&& set_nomacro
== 0)
2106 else if (GP_REG_P (regno0
))
2108 if (GP_REG_P (regno1
))
2109 ret
= "move\t%0,%1";
2111 else if (MD_REG_P (regno1
))
2114 if (regno1
!= HILO_REGNUM
)
2120 else if (ST_REG_P (regno1
) && ISA_HAS_8CC
)
2121 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
2126 if (FP_REG_P (regno1
))
2127 ret
= "mfc1\t%0,%1";
2128 else if (ALL_COP_REG_P (regno1
))
2130 static char retval
[] = "mfc_\t%0,%1";
2132 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2135 else if (regno1
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2136 ret
= "cfc1\t%0,$31";
2140 else if (FP_REG_P (regno0
))
2142 if (GP_REG_P (regno1
))
2145 ret
= "mtc1\t%1,%0";
2148 if (FP_REG_P (regno1
))
2149 ret
= "mov.s\t%0,%1";
2152 else if (MD_REG_P (regno0
))
2154 if (GP_REG_P (regno1
))
2157 if (regno0
!= HILO_REGNUM
&& ! TARGET_MIPS16
)
2162 else if (regno0
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2164 if (GP_REG_P (regno1
))
2167 ret
= "ctc1\t%0,$31";
2170 else if (ALL_COP_REG_P (regno0
))
2172 if (GP_REG_P (regno1
))
2174 static char retval
[] = "mtc_\t%1,%0";
2175 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2178 abort_with_insn (insn
,
2179 "mtc0 not supported; it disturbs virtual address translation");
2187 else if (code1
== MEM
)
2192 mips_count_memory_refs (op1
, 1);
2194 if (GP_REG_P (regno0
))
2196 /* For loads, use the mode of the memory item, instead of the
2197 target, so zero/sign extend can use this code as well. */
2198 switch (GET_MODE (op1
))
2207 ret
= ((unsignedp
&& TARGET_64BIT
)
2212 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
2215 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
2220 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
2223 else if (ALL_COP_REG_P (regno0
))
2225 static char retval
[] = "lwc_\t%0,%1";
2226 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2229 abort_with_insn (insn
,
2230 "loads from memory to COP0 are illegal");
2236 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
2238 size_t i
= strlen (ret
);
2239 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2242 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2243 ret
= volatile_buffer
;
2247 else if (code1
== CONST_INT
2248 || (code1
== CONST_DOUBLE
2249 && GET_MODE (op1
) == VOIDmode
))
2251 if (code1
== CONST_DOUBLE
)
2253 /* This can happen when storing constants into long long
2254 bitfields. Just store the least significant word of
2256 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2259 if (INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2261 if (GP_REG_P (regno0
))
2262 ret
= "move\t%0,%z1";
2264 else if (FP_REG_P (regno0
))
2267 ret
= "mtc1\t%z1,%0";
2270 else if (MD_REG_P (regno0
))
2277 else if (GP_REG_P (regno0
))
2279 /* Don't use X format, because that will give out of
2280 range numbers for 64 bit host and 32 bit target. */
2281 if (! TARGET_MIPS16
)
2282 ret
= "li\t%0,%1\t\t\t# %X1";
2285 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2287 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2288 ret
= "li\t%0,%n1\n\tneg\t%0";
2293 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
2295 if (op1
== CONST0_RTX (SFmode
))
2297 if (GP_REG_P (regno0
))
2298 ret
= "move\t%0,%.";
2300 else if (FP_REG_P (regno0
))
2303 ret
= "mtc1\t%.,%0";
2310 ret
= "li.s\t%0,%1";
2314 else if (code1
== LABEL_REF
)
2317 mips_count_memory_refs (op1
, 1);
2322 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2326 && GET_CODE (XEXP (op1
, 0)) == REG
2327 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2329 /* This case arises on the mips16; see
2330 mips16_gp_pseudo_reg. */
2331 ret
= "move\t%0,%+";
2333 else if (TARGET_MIPS16
2334 && code1
== SYMBOL_REF
2335 && SYMBOL_REF_FLAG (op1
)
2336 && (XSTR (op1
, 0)[0] != '*'
2337 || strncmp (XSTR (op1
, 0) + 1,
2339 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2341 /* This can occur when reloading the address of a GP
2342 relative symbol on the mips16. */
2343 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2348 mips_count_memory_refs (op1
, 1);
2354 else if (code1
== PLUS
)
2356 rtx add_op0
= XEXP (op1
, 0);
2357 rtx add_op1
= XEXP (op1
, 1);
2359 if (GET_CODE (XEXP (op1
, 1)) == REG
2360 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
2361 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
2363 operands
[2] = add_op0
;
2364 operands
[3] = add_op1
;
2365 ret
= "add%:\t%0,%2,%3";
2368 else if (code1
== HIGH
)
2370 operands
[1] = XEXP (op1
, 0);
2371 ret
= "lui\t%0,%%hi(%1)";
2375 else if (code0
== MEM
)
2378 mips_count_memory_refs (op0
, 1);
2382 int regno1
= REGNO (op1
) + subreg_offset1
;
2384 if (GP_REG_P (regno1
))
2388 case SFmode
: ret
= "sw\t%1,%0"; break;
2389 case SImode
: ret
= "sw\t%1,%0"; break;
2390 case HImode
: ret
= "sh\t%1,%0"; break;
2391 case QImode
: ret
= "sb\t%1,%0"; break;
2396 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
2398 else if (ALL_COP_REG_P (regno1
))
2400 static char retval
[] = "swc_\t%1,%0";
2402 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2407 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
2411 case SFmode
: ret
= "sw\t%z1,%0"; break;
2412 case SImode
: ret
= "sw\t%z1,%0"; break;
2413 case HImode
: ret
= "sh\t%z1,%0"; break;
2414 case QImode
: ret
= "sb\t%z1,%0"; break;
2419 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
2423 case SFmode
: ret
= "sw\t%.,%0"; break;
2424 case SImode
: ret
= "sw\t%.,%0"; break;
2425 case HImode
: ret
= "sh\t%.,%0"; break;
2426 case QImode
: ret
= "sb\t%.,%0"; break;
2431 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2433 size_t i
= strlen (ret
);
2435 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2438 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2439 ret
= volatile_buffer
;
2445 abort_with_insn (insn
, "bad move");
2449 if (delay
!= DELAY_NONE
)
2450 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2455 /* Return instructions to restore the global pointer from the stack,
2456 assuming TARGET_ABICALLS. Used by exception_receiver to set up
2457 the GP for exception handlers.
2459 OPERANDS is an array of operands whose contents are undefined
2460 on entry. INSN is the exception_handler instruction. */
2463 mips_restore_gp (operands
, insn
)
2464 rtx
*operands
, insn
;
2468 operands
[0] = pic_offset_table_rtx
;
2469 if (frame_pointer_needed
)
2470 loc
= hard_frame_pointer_rtx
;
2472 loc
= stack_pointer_rtx
;
2473 loc
= plus_constant (loc
, cfun
->machine
->frame
.args_size
);
2474 operands
[1] = gen_rtx_MEM (Pmode
, loc
);
2476 return mips_move_1word (operands
, insn
, 0);
2479 /* Return an instruction to sign-extend SImode value SRC and store it
2480 in DImode value DEST. INSN is the original extendsidi2-type insn. */
2483 mips_sign_extend (insn
, dest
, src
)
2484 rtx insn
, dest
, src
;
2486 rtx operands
[MAX_RECOG_OPERANDS
];
2488 if ((register_operand (src
, SImode
) && FP_REG_P (true_regnum (src
)))
2489 || memory_operand (src
, SImode
))
2491 /* If the source is a floating-point register, we need to use a
2492 32-bit move, since the float register is not kept sign-extended.
2493 If the source is in memory, we need a 32-bit load. */
2494 operands
[0] = gen_lowpart_SUBREG (SImode
, dest
);
2496 return mips_move_1word (operands
, insn
, false);
2502 return mips_move_2words (operands
, insn
);
2506 /* Return the appropriate instructions to move 2 words */
2509 mips_move_2words (operands
, insn
)
2513 const char *ret
= 0;
2514 rtx op0
= operands
[0];
2515 rtx op1
= operands
[1];
2516 enum rtx_code code0
= GET_CODE (operands
[0]);
2517 enum rtx_code code1
= GET_CODE (operands
[1]);
2518 int subreg_offset0
= 0;
2519 int subreg_offset1
= 0;
2520 enum delay_type delay
= DELAY_NONE
;
2522 if (code1
== SIGN_EXTEND
)
2523 return mips_sign_extend (insn
, op0
, XEXP (op1
, 0));
2525 while (code0
== SUBREG
)
2527 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2528 GET_MODE (SUBREG_REG (op0
)),
2531 op0
= SUBREG_REG (op0
);
2532 code0
= GET_CODE (op0
);
2535 while (code1
== SUBREG
)
2537 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2538 GET_MODE (SUBREG_REG (op1
)),
2541 op1
= SUBREG_REG (op1
);
2542 code1
= GET_CODE (op1
);
2547 int regno0
= REGNO (op0
) + subreg_offset0
;
2551 int regno1
= REGNO (op1
) + subreg_offset1
;
2553 /* Just in case, don't do anything for assigning a register
2554 to itself, unless we are filling a delay slot. */
2555 if (regno0
== regno1
&& set_nomacro
== 0)
2558 else if (FP_REG_P (regno0
))
2560 if (FP_REG_P (regno1
))
2561 ret
= "mov.d\t%0,%1";
2569 abort_with_insn (insn
, "bad move");
2571 #ifdef TARGET_FP_CALL_32
2572 if (FP_CALL_GP_REG_P (regno1
))
2573 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2576 ret
= "dmtc1\t%1,%0";
2579 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2583 else if (FP_REG_P (regno1
))
2589 abort_with_insn (insn
, "bad move");
2591 #ifdef TARGET_FP_CALL_32
2592 if (FP_CALL_GP_REG_P (regno0
))
2593 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2596 ret
= "dmfc1\t%0,%1";
2599 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2602 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
) && !TARGET_MIPS16
)
2607 if (regno0
!= HILO_REGNUM
)
2609 else if (regno1
== 0)
2610 ret
= "mtlo\t%.\n\tmthi\t%.";
2613 ret
= "mthi\t%M1\n\tmtlo\t%L1";
2616 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
2621 if (regno1
!= HILO_REGNUM
)
2625 ret
= "mfhi\t%M0\n\tmflo\t%L0";
2627 else if (GP_REG_P (regno0
) && ALL_COP_REG_P (regno1
)
2630 static char retval
[] = "dmfc_\t%0,%1";
2633 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2636 else if (ALL_COP_REG_P (regno0
) && GP_REG_P (regno1
)
2639 static char retval
[] = "dmtc_\t%1,%0";
2640 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2643 abort_with_insn (insn
,
2644 "dmtc0 not supported; it disturbs virtual address translation");
2649 else if (TARGET_64BIT
)
2650 ret
= "move\t%0,%1";
2652 else if (regno0
!= (regno1
+1))
2653 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
2656 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
2659 else if (code1
== CONST_DOUBLE
)
2661 /* Move zero from $0 unless !TARGET_64BIT and recipient
2662 is 64-bit fp reg, in which case generate a constant. */
2663 if (op1
!= CONST0_RTX (GET_MODE (op1
))
2664 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
2666 if (GET_MODE (op1
) == DFmode
)
2670 #ifdef TARGET_FP_CALL_32
2671 if (FP_CALL_GP_REG_P (regno0
))
2673 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
2675 split_double (op1
, operands
+ 2, operands
+ 3);
2676 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2679 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2683 /* GNU as emits 64-bit code for li.d if the ISA is 3
2684 or higher. For !TARGET_64BIT && gp registers we
2685 need to avoid this by using two li instructions
2687 if (ISA_HAS_64BIT_REGS
2689 && ! FP_REG_P (regno0
))
2691 split_double (op1
, operands
+ 2, operands
+ 3);
2692 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2695 ret
= "li.d\t%0,%1";
2698 else if (TARGET_64BIT
)
2700 if (! TARGET_MIPS16
)
2706 split_double (op1
, operands
+ 2, operands
+ 3);
2707 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2713 if (GP_REG_P (regno0
))
2715 #ifdef TARGET_FP_CALL_32
2716 && ! FP_CALL_GP_REG_P (regno0
)
2719 : "move\t%0,%.\n\tmove\t%D0,%.");
2721 else if (FP_REG_P (regno0
))
2726 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2731 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2733 if (GP_REG_P (regno0
))
2736 : "move\t%0,%.\n\tmove\t%D0,%.");
2738 else if (FP_REG_P (regno0
))
2745 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2747 else if (MD_REG_P (regno0
))
2750 ret
= (regno0
== HILO_REGNUM
2751 ? "mtlo\t%.\n\tmthi\t%."
2756 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
2757 && GP_REG_P (regno0
))
2763 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2765 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2766 ret
= "li\t%0,%n1\n\tneg\t%0";
2768 else if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2769 ret
= "li\t%0,%1\t\t# %X1";
2770 else if (HOST_BITS_PER_WIDE_INT
< 64)
2771 /* We can't use 'X' for negative numbers, because then we won't
2772 get the right value for the upper 32 bits. */
2773 ret
= (INTVAL (op1
) < 0
2774 ? "dli\t%0,%1\t\t\t# %X1"
2775 : "dli\t%0,%X1\t\t# %1");
2777 /* We must use 'X', because otherwise LONG_MIN will print as
2778 a number that the assembler won't accept. */
2779 ret
= "dli\t%0,%X1\t\t# %1";
2781 else if (HOST_BITS_PER_WIDE_INT
< 64)
2783 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
2786 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2787 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2788 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2790 operands
[2] = GEN_INT (1);
2791 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2795 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2799 /* We use multiple shifts here, to avoid warnings about out
2800 of range shifts on 32 bit hosts. */
2801 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
2803 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
2806 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2807 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2808 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2810 operands
[2] = GEN_INT (1);
2811 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2815 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2819 else if (code1
== MEM
)
2824 mips_count_memory_refs (op1
, 2);
2826 if (FP_REG_P (regno0
))
2829 else if (ALL_COP_REG_P (regno0
) && TARGET_64BIT
)
2831 static char retval
[] = "ldc_\t%0,%1";
2832 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2835 abort_with_insn (insn
,
2836 "loads from memory to COP0 are illegal");
2842 else if (TARGET_64BIT
)
2845 #ifdef TARGET_FP_CALL_32
2846 if (FP_CALL_GP_REG_P (regno0
))
2847 ret
= (double_memory_operand (op1
, GET_MODE (op1
))
2848 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2849 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2855 else if (double_memory_operand (op1
, GET_MODE (op1
)))
2856 ret
= (reg_mentioned_p (op0
, op1
)
2857 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2858 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2860 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
2862 size_t i
= strlen (ret
);
2864 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2867 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2868 ret
= volatile_buffer
;
2872 else if (code1
== LABEL_REF
)
2875 mips_count_memory_refs (op1
, 2);
2877 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2878 /* We deliberately remove the 'a' from '%1', so that we don't
2879 have to add SIGN_EXTEND support to print_operand_address.
2880 print_operand will just call print_operand_address in this
2881 case, so there is no problem. */
2884 ret
= "dla\t%0,%a1";
2886 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2890 && GET_CODE (XEXP (op1
, 0)) == REG
2891 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2893 /* This case arises on the mips16; see
2894 mips16_gp_pseudo_reg. */
2895 ret
= "move\t%0,%+";
2897 else if (TARGET_MIPS16
2898 && code1
== SYMBOL_REF
2899 && SYMBOL_REF_FLAG (op1
)
2900 && (XSTR (op1
, 0)[0] != '*'
2901 || strncmp (XSTR (op1
, 0) + 1,
2903 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2905 /* This can occur when reloading the address of a GP
2906 relative symbol on the mips16. */
2907 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2912 mips_count_memory_refs (op1
, 2);
2914 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2915 /* We deliberately remove the 'a' from '%1', so that we don't
2916 have to add SIGN_EXTEND support to print_operand_address.
2917 print_operand will just call print_operand_address in this
2918 case, so there is no problem. */
2921 ret
= "dla\t%0,%a1";
2926 else if (code0
== MEM
)
2930 int regno1
= REGNO (op1
) + subreg_offset1
;
2932 if (FP_REG_P (regno1
))
2935 else if (ALL_COP_REG_P (regno1
) && TARGET_64BIT
)
2937 static char retval
[] = "sdc_\t%1,%0";
2939 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2942 else if (TARGET_64BIT
)
2945 #ifdef TARGET_FP_CALL_32
2946 if (FP_CALL_GP_REG_P (regno1
))
2947 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2953 else if (double_memory_operand (op0
, GET_MODE (op0
)))
2954 ret
= "sw\t%1,%0\n\tsw\t%D1,%D0";
2957 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
2958 || (code1
== CONST_DOUBLE
2959 && op1
== CONST0_RTX (GET_MODE (op1
))))
2961 || double_memory_operand (op0
, GET_MODE (op0
))))
2966 ret
= "sw\t%.,%0\n\tsw\t%.,%D0";
2970 mips_count_memory_refs (op0
, 2);
2972 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2974 size_t i
= strlen (ret
);
2976 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2979 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2980 ret
= volatile_buffer
;
2986 abort_with_insn (insn
, "bad move");
2990 if (delay
!= DELAY_NONE
)
2991 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2997 mips_rtx_costs (x
, code
, outer_code
, total
)
2999 int code
, outer_code
;
3002 enum machine_mode mode
= GET_MODE (x
);
3007 if (! TARGET_MIPS16
)
3009 /* Always return 0, since we don't have different sized insns,
3010 hence different costs according to Richard Kenner. */
3015 if (outer_code
== SET
)
3017 if (INTVAL (x
) >= 0 && INTVAL (x
) < 0x100)
3019 else if ((INTVAL (x
) >= 0 && INTVAL (x
) < 0x10000)
3020 || (INTVAL (x
) < 0 && INTVAL (x
) > -0x100))
3021 *total
= COSTS_N_INSNS (1);
3023 *total
= COSTS_N_INSNS (2);
3027 /* A PLUS could be an address. We don't want to force an address
3028 to use a register, so accept any signed 16 bit value without
3030 if (outer_code
== PLUS
3031 && INTVAL (x
) >= -0x8000 && INTVAL (x
) < 0x8000)
3037 /* A number between 1 and 8 inclusive is efficient for a shift.
3038 Otherwise, we will need an extended instruction. */
3039 if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
3040 || outer_code
== LSHIFTRT
)
3042 if (INTVAL (x
) >= 1 && INTVAL (x
) <= 8)
3045 *total
= COSTS_N_INSNS (1);
3049 /* We can use cmpi for an xor with an unsigned 16 bit value. */
3050 if (outer_code
== XOR
3051 && INTVAL (x
) >= 0 && INTVAL (x
) < 0x10000)
3057 /* We may be able to use slt or sltu for a comparison with a
3058 signed 16 bit value. (The boundary conditions aren't quite
3059 right, but this is just a heuristic anyhow.) */
3060 if ((outer_code
== LT
|| outer_code
== LE
3061 || outer_code
== GE
|| outer_code
== GT
3062 || outer_code
== LTU
|| outer_code
== LEU
3063 || outer_code
== GEU
|| outer_code
== GTU
)
3064 && INTVAL (x
) >= -0x8000 && INTVAL (x
) < 0x8000)
3070 /* Equality comparisons with 0 are cheap. */
3071 if ((outer_code
== EQ
|| outer_code
== NE
)
3075 /* Otherwise, work out the cost to load the value into a
3077 if (INTVAL (x
) >= 0 && INTVAL (x
) < 0x100)
3078 *total
= COSTS_N_INSNS (1);
3079 else if ((INTVAL (x
) >= 0 && INTVAL (x
) < 0x10000)
3080 || (INTVAL (x
) < 0 && INTVAL (x
) > -0x100))
3081 *total
= COSTS_N_INSNS (2);
3083 *total
= COSTS_N_INSNS (3);
3087 *total
= COSTS_N_INSNS (2);
3092 rtx offset
= const0_rtx
;
3093 rtx symref
= eliminate_constant_term (XEXP (x
, 0), &offset
);
3095 if (TARGET_MIPS16
&& mips16_gp_offset_p (x
))
3097 /* Treat this like a signed 16 bit CONST_INT. */
3098 if (outer_code
== PLUS
)
3100 else if (outer_code
== SET
)
3101 *total
= COSTS_N_INSNS (1);
3103 *total
= COSTS_N_INSNS (2);
3107 if (GET_CODE (symref
) == LABEL_REF
)
3108 *total
= COSTS_N_INSNS (2);
3109 else if (GET_CODE (symref
) != SYMBOL_REF
)
3110 *total
= COSTS_N_INSNS (4);
3111 else if (INTVAL (offset
) < -32768 || INTVAL (offset
) > 32767)
3112 *total
= COSTS_N_INSNS (2);
3114 *total
= COSTS_N_INSNS (SYMBOL_REF_FLAG (symref
) ? 1 : 2);
3120 *total
= COSTS_N_INSNS (SYMBOL_REF_FLAG (x
) ? 1 : 2);
3128 *total
= COSTS_N_INSNS (4);
3132 split_double (x
, &high
, &low
);
3133 *total
= COSTS_N_INSNS ((high
== CONST0_RTX (GET_MODE (high
))
3134 || low
== CONST0_RTX (GET_MODE (low
)))
3141 int num_words
= (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
) ? 2 : 1;
3142 if (simple_memory_operand (x
, mode
))
3143 *total
= COSTS_N_INSNS (num_words
);
3145 *total
= COSTS_N_INSNS (2*num_words
);
3150 *total
= COSTS_N_INSNS (6);
3154 *total
= COSTS_N_INSNS ((mode
== DImode
&& !TARGET_64BIT
) ? 2 : 1);
3160 if (mode
== DImode
&& !TARGET_64BIT
)
3162 *total
= COSTS_N_INSNS (2);
3170 if (mode
== DImode
&& !TARGET_64BIT
)
3172 *total
= COSTS_N_INSNS ((GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3179 if (mode
== SFmode
|| mode
== DFmode
)
3180 *total
= COSTS_N_INSNS (1);
3182 *total
= COSTS_N_INSNS (4);
3187 if (mode
== SFmode
|| mode
== DFmode
)
3189 if (TUNE_MIPS3000
|| TUNE_MIPS3900
)
3190 *total
= COSTS_N_INSNS (2);
3191 else if (TUNE_MIPS6000
)
3192 *total
= COSTS_N_INSNS (3);
3194 *total
= COSTS_N_INSNS (6);
3197 if (mode
== DImode
&& !TARGET_64BIT
)
3199 *total
= COSTS_N_INSNS (4);
3205 if (mode
== DImode
&& !TARGET_64BIT
)
3218 *total
= COSTS_N_INSNS (4);
3219 else if (TUNE_MIPS6000
3222 *total
= COSTS_N_INSNS (5);
3224 *total
= COSTS_N_INSNS (7);
3233 *total
= COSTS_N_INSNS (5);
3234 else if (TUNE_MIPS6000
3237 *total
= COSTS_N_INSNS (6);
3239 *total
= COSTS_N_INSNS (8);
3244 *total
= COSTS_N_INSNS (12);
3245 else if (TUNE_MIPS3900
)
3246 *total
= COSTS_N_INSNS (2);
3247 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
3248 *total
= COSTS_N_INSNS ((mode
== DImode
) ? 4 : 3);
3249 else if (TUNE_MIPS6000
)
3250 *total
= COSTS_N_INSNS (17);
3251 else if (TUNE_MIPS5000
)
3252 *total
= COSTS_N_INSNS (5);
3254 *total
= COSTS_N_INSNS (10);
3263 *total
= COSTS_N_INSNS (12);
3264 else if (TUNE_MIPS6000
)
3265 *total
= COSTS_N_INSNS (15);
3266 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
3267 *total
= COSTS_N_INSNS (30);
3269 *total
= COSTS_N_INSNS (23);
3277 *total
= COSTS_N_INSNS (19);
3278 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
3279 *total
= COSTS_N_INSNS (59);
3280 else if (TUNE_MIPS6000
)
3281 *total
= COSTS_N_INSNS (16);
3283 *total
= COSTS_N_INSNS (36);
3292 *total
= COSTS_N_INSNS (35);
3293 else if (TUNE_MIPS6000
)
3294 *total
= COSTS_N_INSNS (38);
3295 else if (TUNE_MIPS5000
)
3296 *total
= COSTS_N_INSNS (36);
3297 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
3298 *total
= COSTS_N_INSNS ((mode
== SImode
) ? 42 : 74);
3300 *total
= COSTS_N_INSNS (69);
3304 /* A sign extend from SImode to DImode in 64 bit mode is often
3305 zero instructions, because the result can often be used
3306 directly by another instruction; we'll call it one. */
3307 if (TARGET_64BIT
&& mode
== DImode
3308 && GET_MODE (XEXP (x
, 0)) == SImode
)
3309 *total
= COSTS_N_INSNS (1);
3311 *total
= COSTS_N_INSNS (2);
3315 if (TARGET_64BIT
&& mode
== DImode
3316 && GET_MODE (XEXP (x
, 0)) == SImode
)
3317 *total
= COSTS_N_INSNS (2);
3319 *total
= COSTS_N_INSNS (1);
3327 /* Provide the costs of an addressing mode that contains ADDR.
3328 If ADDR is not a valid address, its cost is irrelevant. */
3331 mips_address_cost (addr
)
3334 switch (GET_CODE (addr
))
3347 rtx offset
= const0_rtx
;
3348 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
3349 if (GET_CODE (addr
) == LABEL_REF
)
3352 if (GET_CODE (addr
) != SYMBOL_REF
)
3355 if (! SMALL_INT (offset
))
3359 /* ... fall through ... */
3362 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
3366 register rtx plus0
= XEXP (addr
, 0);
3367 register rtx plus1
= XEXP (addr
, 1);
3369 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
3370 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
3372 if (GET_CODE (plus0
) != REG
)
3375 switch (GET_CODE (plus1
))
3378 return SMALL_INT (plus1
) ? 1 : 2;
3385 return mips_address_cost (plus1
) + 1;
3399 /* Return nonzero if X is an address which needs a temporary register when
3400 reloaded while generating PIC code. */
3403 pic_address_needs_scratch (x
)
3406 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3407 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3408 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3409 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3410 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3416 /* Make normal rtx_code into something we can index from an array */
3418 static enum internal_test
3419 map_test_to_internal_test (test_code
)
3420 enum rtx_code test_code
;
3422 enum internal_test test
= ITEST_MAX
;
3426 case EQ
: test
= ITEST_EQ
; break;
3427 case NE
: test
= ITEST_NE
; break;
3428 case GT
: test
= ITEST_GT
; break;
3429 case GE
: test
= ITEST_GE
; break;
3430 case LT
: test
= ITEST_LT
; break;
3431 case LE
: test
= ITEST_LE
; break;
3432 case GTU
: test
= ITEST_GTU
; break;
3433 case GEU
: test
= ITEST_GEU
; break;
3434 case LTU
: test
= ITEST_LTU
; break;
3435 case LEU
: test
= ITEST_LEU
; break;
3443 /* Generate the code to compare two integer values. The return value is:
3444 (reg:SI xx) The pseudo register the comparison is in
3445 0 No register, generate a simple branch.
3447 ??? This is called with result nonzero by the Scond patterns in
3448 mips.md. These patterns are called with a target in the mode of
3449 the Scond instruction pattern. Since this must be a constant, we
3450 must use SImode. This means that if RESULT is nonzero, it will
3451 always be an SImode register, even if TARGET_64BIT is true. We
3452 cope with this by calling convert_move rather than emit_move_insn.
3453 This will sometimes lead to an unnecessary extension of the result;
3465 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
3466 enum rtx_code test_code
; /* relational test (EQ, etc) */
3467 rtx result
; /* result to store comp. or 0 if branch */
3468 rtx cmp0
; /* first operand to compare */
3469 rtx cmp1
; /* second operand to compare */
3470 int *p_invert
; /* NULL or ptr to hold whether branch needs */
3471 /* to reverse its test */
3475 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
3476 int const_low
; /* low bound of constant we can accept */
3477 int const_high
; /* high bound of constant we can accept */
3478 int const_add
; /* constant to add (convert LE -> LT) */
3479 int reverse_regs
; /* reverse registers in test */
3480 int invert_const
; /* != 0 if invert value if cmp1 is constant */
3481 int invert_reg
; /* != 0 if invert value if cmp1 is register */
3482 int unsignedp
; /* != 0 for unsigned comparisons. */
3485 static const struct cmp_info info
[ (int)ITEST_MAX
] = {
3487 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3488 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3489 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3490 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3491 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3492 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3493 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3494 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3495 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3496 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3499 enum internal_test test
;
3500 enum machine_mode mode
;
3501 const struct cmp_info
*p_info
;
3508 test
= map_test_to_internal_test (test_code
);
3509 if (test
== ITEST_MAX
)
3512 p_info
= &info
[(int) test
];
3513 eqne_p
= (p_info
->test_code
== XOR
);
3515 mode
= GET_MODE (cmp0
);
3516 if (mode
== VOIDmode
)
3517 mode
= GET_MODE (cmp1
);
3519 /* Eliminate simple branches */
3520 branch_p
= (result
== 0);
3523 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
3525 /* Comparisons against zero are simple branches */
3526 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0
3527 && (! TARGET_MIPS16
|| eqne_p
))
3530 /* Test for beq/bne. */
3531 if (eqne_p
&& ! TARGET_MIPS16
)
3535 /* allocate a pseudo to calculate the value in. */
3536 result
= gen_reg_rtx (mode
);
3539 /* Make sure we can handle any constants given to us. */
3540 if (GET_CODE (cmp0
) == CONST_INT
)
3541 cmp0
= force_reg (mode
, cmp0
);
3543 if (GET_CODE (cmp1
) == CONST_INT
)
3545 HOST_WIDE_INT value
= INTVAL (cmp1
);
3547 if (value
< p_info
->const_low
3548 || value
> p_info
->const_high
3549 /* ??? Why? And why wasn't the similar code below modified too? */
3551 && HOST_BITS_PER_WIDE_INT
< 64
3552 && p_info
->const_add
!= 0
3553 && ((p_info
->unsignedp
3554 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
3555 > (unsigned HOST_WIDE_INT
) INTVAL (cmp1
))
3556 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
3557 != (p_info
->const_add
> 0))))
3558 cmp1
= force_reg (mode
, cmp1
);
3561 /* See if we need to invert the result. */
3562 invert
= (GET_CODE (cmp1
) == CONST_INT
3563 ? p_info
->invert_const
: p_info
->invert_reg
);
3565 if (p_invert
!= (int *)0)
3571 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3572 Comparison between two registers, may involve switching operands. */
3573 if (GET_CODE (cmp1
) == CONST_INT
)
3575 if (p_info
->const_add
!= 0)
3577 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
3579 /* If modification of cmp1 caused overflow,
3580 we would get the wrong answer if we follow the usual path;
3581 thus, x > 0xffffffffU would turn into x > 0U. */
3582 if ((p_info
->unsignedp
3583 ? (unsigned HOST_WIDE_INT
) new >
3584 (unsigned HOST_WIDE_INT
) INTVAL (cmp1
)
3585 : new > INTVAL (cmp1
))
3586 != (p_info
->const_add
> 0))
3588 /* This test is always true, but if INVERT is true then
3589 the result of the test needs to be inverted so 0 should
3590 be returned instead. */
3591 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
3595 cmp1
= GEN_INT (new);
3599 else if (p_info
->reverse_regs
)
3606 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
3610 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
3611 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
3614 if (test
== ITEST_NE
)
3616 if (! TARGET_MIPS16
)
3618 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
3619 if (p_invert
!= NULL
)
3625 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3626 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
3631 else if (test
== ITEST_EQ
)
3633 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3634 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
3642 if (! TARGET_MIPS16
)
3646 /* The value is in $24. Copy it to another register, so
3647 that reload doesn't think it needs to store the $24 and
3648 the input to the XOR in the same location. */
3649 reg2
= gen_reg_rtx (mode
);
3650 emit_move_insn (reg2
, reg
);
3652 one
= force_reg (mode
, const1_rtx
);
3654 convert_move (result
, gen_rtx (XOR
, mode
, reg
, one
), 0);
3660 /* Work out how to check a floating-point condition. We need a
3661 separate comparison instruction (C.cond.fmt), followed by a
3662 branch or conditional move. Given that IN_CODE is the
3663 required condition, set *CMP_CODE to the C.cond.fmt code
3664 and *action_code to the branch or move code. */
3667 get_float_compare_codes (in_code
, cmp_code
, action_code
)
3668 enum rtx_code in_code
, *cmp_code
, *action_code
;
3677 *cmp_code
= reverse_condition_maybe_unordered (in_code
);
3682 *cmp_code
= in_code
;
3688 /* Emit the common code for doing conditional branches.
3689 operand[0] is the label to jump to.
3690 The comparison operands are saved away by cmp{si,di,sf,df}. */
3693 gen_conditional_branch (operands
, test_code
)
3695 enum rtx_code test_code
;
3697 enum cmp_type type
= branch_type
;
3698 rtx cmp0
= branch_cmp
[0];
3699 rtx cmp1
= branch_cmp
[1];
3700 enum machine_mode mode
;
3701 enum rtx_code cmp_code
;
3710 mode
= type
== CMP_SI
? SImode
: DImode
;
3712 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
3720 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
3721 /* We don't want to build a comparison against a nonzero
3723 cmp1
= force_reg (mode
, cmp1
);
3730 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
3732 reg
= gen_reg_rtx (CCmode
);
3734 get_float_compare_codes (test_code
, &cmp_code
, &test_code
);
3735 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3736 gen_rtx (cmp_code
, CCmode
, cmp0
, cmp1
)));
3745 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
3748 /* Generate the branch. */
3750 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
3759 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
3760 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3761 gen_rtx (test_code
, mode
,
3766 /* Emit the common code for conditional moves. OPERANDS is the array
3767 of operands passed to the conditional move defined_expand. */
3770 gen_conditional_move (operands
)
3773 rtx op0
= branch_cmp
[0];
3774 rtx op1
= branch_cmp
[1];
3775 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3776 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
3777 enum rtx_code move_code
= NE
;
3778 enum machine_mode op_mode
= GET_MODE (operands
[0]);
3779 enum machine_mode cmp_mode
;
3782 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3801 op0
= force_reg (mode
, branch_cmp
[1]);
3802 op1
= branch_cmp
[0];
3806 op0
= force_reg (mode
, branch_cmp
[1]);
3807 op1
= branch_cmp
[0];
3818 op0
= force_reg (mode
, branch_cmp
[1]);
3819 op1
= branch_cmp
[0];
3823 op0
= force_reg (mode
, branch_cmp
[1]);
3824 op1
= branch_cmp
[0];
3832 get_float_compare_codes (cmp_code
, &cmp_code
, &move_code
);
3834 if (mode
== SImode
|| mode
== DImode
)
3836 else if (mode
== SFmode
|| mode
== DFmode
)
3841 cmp_reg
= gen_reg_rtx (cmp_mode
);
3842 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
3843 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
3845 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
3846 gen_rtx_IF_THEN_ELSE (op_mode
,
3847 gen_rtx (move_code
, VOIDmode
,
3849 CONST0_RTX (SImode
)),
3850 operands
[2], operands
[3])));
3853 /* Emit the common code for conditional moves. OPERANDS is the array
3854 of operands passed to the conditional move defined_expand. */
3857 mips_gen_conditional_trap (operands
)
3861 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3862 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3864 /* MIPS conditional trap machine instructions don't have GT or LE
3865 flavors, so we must invert the comparison and convert to LT and
3866 GE, respectively. */
3869 case GT
: cmp_code
= LT
; break;
3870 case LE
: cmp_code
= GE
; break;
3871 case GTU
: cmp_code
= LTU
; break;
3872 case LEU
: cmp_code
= GEU
; break;
3875 if (cmp_code
== GET_CODE (operands
[0]))
3877 op0
= force_reg (mode
, branch_cmp
[0]);
3878 op1
= branch_cmp
[1];
3882 op0
= force_reg (mode
, branch_cmp
[1]);
3883 op1
= branch_cmp
[0];
3885 if (GET_CODE (op1
) == CONST_INT
&& ! SMALL_INT (op1
))
3886 op1
= force_reg (mode
, op1
);
3888 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3889 gen_rtx (cmp_code
, GET_MODE (operands
[0]), op0
, op1
),
3893 /* Return true if operand OP is a condition code register.
3894 Only for use during or after reload. */
3897 fcc_register_operand (op
, mode
)
3899 enum machine_mode mode
;
3901 return ((mode
== VOIDmode
|| mode
== GET_MODE (op
))
3902 && (reload_in_progress
|| reload_completed
)
3903 && (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
3904 && ST_REG_P (true_regnum (op
)));
3907 /* Emit code to move general operand SRC into condition-code
3908 register DEST. SCRATCH is a scratch TFmode float register.
3915 where FP1 and FP2 are single-precision float registers
3916 taken from SCRATCH. */
3919 mips_emit_fcc_reload (dest
, src
, scratch
)
3920 rtx dest
, src
, scratch
;
3924 /* Change the source to SFmode. */
3925 if (GET_CODE (src
) == MEM
)
3926 src
= adjust_address (src
, SFmode
, 0);
3927 else if (GET_CODE (src
) == REG
|| GET_CODE (src
) == SUBREG
)
3928 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
3930 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
3931 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + FP_INC
);
3933 emit_move_insn (copy_rtx (fp1
), src
);
3934 emit_move_insn (copy_rtx (fp2
), CONST0_RTX (SFmode
));
3935 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
3938 /* Emit code to change the current function's return address to
3939 ADDRESS. SCRATCH is available as a scratch register, if needed.
3940 ADDRESS and SCRATCH are both word-mode GPRs. */
3943 mips_set_return_address (address
, scratch
)
3944 rtx address
, scratch
;
3946 HOST_WIDE_INT gp_offset
;
3948 compute_frame_size (get_frame_size ());
3949 if (((cfun
->machine
->frame
.mask
>> 31) & 1) == 0)
3951 gp_offset
= cfun
->machine
->frame
.gp_sp_offset
;
3953 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3954 if (gp_offset
< 32768)
3955 scratch
= plus_constant (stack_pointer_rtx
, gp_offset
);
3958 emit_move_insn (scratch
, GEN_INT (gp_offset
));
3959 if (Pmode
== DImode
)
3960 emit_insn (gen_adddi3 (scratch
, scratch
, stack_pointer_rtx
));
3962 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
3965 emit_move_insn (gen_rtx_MEM (GET_MODE (address
), scratch
), address
);
3968 /* Write a loop to move a constant number of bytes.
3969 Generate load/stores as follows:
3975 temp<last> = src[MAX_MOVE_REGS-1];
3979 dest[MAX_MOVE_REGS-1] = temp<last>;
3980 src += MAX_MOVE_REGS;
3981 dest += MAX_MOVE_REGS;
3982 } while (src != final);
3984 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3985 registers are needed.
3987 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3988 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3989 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3991 #define MAX_MOVE_REGS 4
3992 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3995 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
3996 rtx dest_reg
; /* register holding destination address */
3997 rtx src_reg
; /* register holding source address */
3998 unsigned int bytes
; /* # bytes to move */
3999 int align
; /* alignment */
4000 rtx orig_dest
; /* original dest */
4001 rtx orig_src
; /* original source for making a reg note */
4003 rtx dest_mem
= replace_equiv_address (orig_dest
, dest_reg
);
4004 rtx src_mem
= replace_equiv_address (orig_src
, src_reg
);
4005 rtx align_rtx
= GEN_INT (align
);
4011 if (bytes
< (unsigned)2 * MAX_MOVE_BYTES
)
4014 leftover
= bytes
% MAX_MOVE_BYTES
;
4017 label
= gen_label_rtx ();
4018 final_src
= gen_reg_rtx (Pmode
);
4019 bytes_rtx
= GEN_INT (bytes
);
4023 if (Pmode
== DImode
)
4025 emit_insn (gen_movdi (final_src
, bytes_rtx
));
4026 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
4030 emit_insn (gen_movsi (final_src
, bytes_rtx
));
4031 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
4036 if (Pmode
== DImode
)
4037 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
4039 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
4044 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
4045 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
4047 if (Pmode
== DImode
)
4049 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
4050 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
4051 emit_insn (gen_cmpdi (src_reg
, final_src
));
4055 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
4056 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
4057 emit_insn (gen_cmpsi (src_reg
, final_src
));
4060 emit_jump_insn (gen_bne (label
));
4063 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
4067 /* Use a library function to move some bytes. */
4070 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
4075 /* We want to pass the size as Pmode, which will normally be SImode
4076 but will be DImode if we are using 64 bit longs and pointers. */
4077 if (GET_MODE (bytes_rtx
) != VOIDmode
4078 && GET_MODE (bytes_rtx
) != (unsigned) Pmode
)
4079 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
4081 #ifdef TARGET_MEM_FUNCTIONS
4082 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
4083 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
4084 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
4085 TREE_UNSIGNED (sizetype
)),
4086 TYPE_MODE (sizetype
));
4088 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
4089 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
4090 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
4091 TREE_UNSIGNED (integer_type_node
)),
4092 TYPE_MODE (integer_type_node
));
4096 /* Expand string/block move operations.
4098 operands[0] is the pointer to the destination.
4099 operands[1] is the pointer to the source.
4100 operands[2] is the number of bytes to move.
4101 operands[3] is the alignment. */
4104 expand_block_move (operands
)
4107 rtx bytes_rtx
= operands
[2];
4108 rtx align_rtx
= operands
[3];
4109 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
4110 unsigned HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
4111 unsigned int align
= INTVAL (align_rtx
);
4112 rtx orig_src
= operands
[1];
4113 rtx orig_dest
= operands
[0];
4117 if (constp
&& bytes
== 0)
4120 if (align
> (unsigned) UNITS_PER_WORD
)
4121 align
= UNITS_PER_WORD
;
4123 /* Move the address into scratch registers. */
4124 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
4125 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
4128 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
4130 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
4131 && align
== (unsigned) UNITS_PER_WORD
)
4132 move_by_pieces (orig_dest
, orig_src
, bytes
, align
* BITS_PER_WORD
);
4134 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
)
4135 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
4137 replace_equiv_address (orig_src
,
4139 bytes_rtx
, align_rtx
));
4141 else if (constp
&& align
>= (unsigned) UNITS_PER_WORD
&& optimize
)
4142 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
4144 else if (constp
&& optimize
)
4146 /* If the alignment is not word aligned, generate a test at
4147 runtime, to see whether things wound up aligned, and we
4148 can use the faster lw/sw instead ulw/usw. */
4150 rtx temp
= gen_reg_rtx (Pmode
);
4151 rtx aligned_label
= gen_label_rtx ();
4152 rtx join_label
= gen_label_rtx ();
4153 int leftover
= bytes
% MAX_MOVE_BYTES
;
4157 if (Pmode
== DImode
)
4159 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
4160 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
4161 emit_insn (gen_cmpdi (temp
, const0_rtx
));
4165 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
4166 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
4167 emit_insn (gen_cmpsi (temp
, const0_rtx
));
4170 emit_jump_insn (gen_beq (aligned_label
));
4172 /* Unaligned loop. */
4173 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
4174 emit_jump_insn (gen_jump (join_label
));
4178 emit_label (aligned_label
);
4179 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
4181 emit_label (join_label
);
4183 /* Bytes at the end of the loop. */
4185 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
4187 replace_equiv_address (orig_src
,
4194 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
4197 /* Emit load/stores for a small constant block_move.
4199 operands[0] is the memory address of the destination.
4200 operands[1] is the memory address of the source.
4201 operands[2] is the number of bytes to move.
4202 operands[3] is the alignment.
4203 operands[4] is a temp register.
4204 operands[5] is a temp register.
4206 operands[3+num_regs] is the last temp register.
4208 The block move type can be one of the following:
4209 BLOCK_MOVE_NORMAL Do all of the block move.
4210 BLOCK_MOVE_NOT_LAST Do all but the last store.
4211 BLOCK_MOVE_LAST Do just the last store. */
4214 output_block_move (insn
, operands
, num_regs
, move_type
)
4218 enum block_move_type move_type
;
4220 rtx dest_reg
= XEXP (operands
[0], 0);
4221 rtx src_reg
= XEXP (operands
[1], 0);
4222 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
4223 int align
= INTVAL (operands
[3]);
4226 int use_lwl_lwr
= 0;
4227 int last_operand
= num_regs
+ 4;
4233 const char *load
; /* load insn without nop */
4234 const char *load_nop
; /* load insn with trailing nop */
4235 const char *store
; /* store insn */
4236 const char *final
; /* if last_store used: NULL or swr */
4237 const char *last_store
; /* last store instruction */
4238 int offset
; /* current offset */
4239 enum machine_mode mode
; /* mode to use on (MEM) */
4242 /* ??? Detect a bug in GCC, where it can give us a register
4243 the same as one of the addressing registers and reduce
4244 the number of registers available. */
4245 for (i
= 4; i
< last_operand
&& safe_regs
< (int) ARRAY_SIZE (xoperands
); i
++)
4246 if (! reg_mentioned_p (operands
[i
], operands
[0])
4247 && ! reg_mentioned_p (operands
[i
], operands
[1]))
4248 xoperands
[safe_regs
++] = operands
[i
];
4250 if (safe_regs
< last_operand
)
4252 xoperands
[0] = operands
[0];
4253 xoperands
[1] = operands
[1];
4254 xoperands
[2] = operands
[2];
4255 xoperands
[3] = operands
[3];
4256 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
4259 /* If we are given global or static addresses, and we would be
4260 emitting a few instructions, try to save time by using a
4261 temporary register for the pointer. */
4262 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
4263 an ldl/ldr instruction pair. We play it safe, and always move
4264 constant addresses into registers when generating N32/N64 code, just
4265 in case we might emit an unaligned load instruction. */
4266 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
4267 || mips_abi
== ABI_MEABI
4268 || mips_abi
== ABI_N32
4269 || mips_abi
== ABI_64
))
4271 if (CONSTANT_P (src_reg
))
4274 mips_count_memory_refs (operands
[1], 1);
4276 src_reg
= operands
[3 + num_regs
--];
4277 if (move_type
!= BLOCK_MOVE_LAST
)
4279 xoperands
[1] = operands
[1];
4280 xoperands
[0] = src_reg
;
4281 if (Pmode
== DImode
)
4282 output_asm_insn ("dla\t%0,%1", xoperands
);
4284 output_asm_insn ("la\t%0,%1", xoperands
);
4288 if (CONSTANT_P (dest_reg
))
4291 mips_count_memory_refs (operands
[0], 1);
4293 dest_reg
= operands
[3 + num_regs
--];
4294 if (move_type
!= BLOCK_MOVE_LAST
)
4296 xoperands
[1] = operands
[0];
4297 xoperands
[0] = dest_reg
;
4298 if (Pmode
== DImode
)
4299 output_asm_insn ("dla\t%0,%1", xoperands
);
4301 output_asm_insn ("la\t%0,%1", xoperands
);
4306 /* ??? We really shouldn't get any LO_SUM addresses here, because they
4307 are not offsettable, however, offsettable_address_p says they are
4308 offsettable. I think this is a bug in offsettable_address_p.
4309 For expediency, we fix this by just loading the address into a register
4310 if we happen to get one. */
4312 if (GET_CODE (src_reg
) == LO_SUM
)
4314 src_reg
= operands
[3 + num_regs
--];
4315 if (move_type
!= BLOCK_MOVE_LAST
)
4317 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
4318 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
4319 xoperands
[0] = src_reg
;
4320 if (Pmode
== DImode
)
4321 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
4323 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
4327 if (GET_CODE (dest_reg
) == LO_SUM
)
4329 dest_reg
= operands
[3 + num_regs
--];
4330 if (move_type
!= BLOCK_MOVE_LAST
)
4332 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
4333 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
4334 xoperands
[0] = dest_reg
;
4335 if (Pmode
== DImode
)
4336 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
4338 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
4342 if (num_regs
> (int) ARRAY_SIZE (load_store
))
4343 num_regs
= ARRAY_SIZE (load_store
);
4345 else if (num_regs
< 1)
4346 abort_with_insn (insn
,
4347 "cannot do block move, not enough scratch registers");
4351 load_store
[num
].offset
= offset
;
4353 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
4355 load_store
[num
].load
= "ld\t%0,%1";
4356 load_store
[num
].load_nop
= "ld\t%0,%1%#";
4357 load_store
[num
].store
= "sd\t%0,%1";
4358 load_store
[num
].last_store
= "sd\t%0,%1";
4359 load_store
[num
].final
= 0;
4360 load_store
[num
].mode
= DImode
;
4365 /* ??? Fails because of a MIPS assembler bug? */
4366 else if (TARGET_64BIT
&& bytes
>= 8
4370 if (BYTES_BIG_ENDIAN
)
4372 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
4373 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
4374 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
4375 load_store
[num
].last_store
= "sdr\t%0,%2";
4376 load_store
[num
].final
= "sdl\t%0,%1";
4380 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
4381 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
4382 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
4383 load_store
[num
].last_store
= "sdr\t%0,%1";
4384 load_store
[num
].final
= "sdl\t%0,%2";
4387 load_store
[num
].mode
= DImode
;
4393 else if (bytes
>= 4 && align
>= 4)
4395 load_store
[num
].load
= "lw\t%0,%1";
4396 load_store
[num
].load_nop
= "lw\t%0,%1%#";
4397 load_store
[num
].store
= "sw\t%0,%1";
4398 load_store
[num
].last_store
= "sw\t%0,%1";
4399 load_store
[num
].final
= 0;
4400 load_store
[num
].mode
= SImode
;
4409 if (BYTES_BIG_ENDIAN
)
4411 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
4412 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
4413 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
4414 load_store
[num
].last_store
= "swr\t%0,%2";
4415 load_store
[num
].final
= "swl\t%0,%1";
4419 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
4420 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
4421 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
4422 load_store
[num
].last_store
= "swr\t%0,%1";
4423 load_store
[num
].final
= "swl\t%0,%2";
4426 load_store
[num
].mode
= SImode
;
4432 else if (bytes
>= 2 && align
>= 2)
4434 load_store
[num
].load
= "lh\t%0,%1";
4435 load_store
[num
].load_nop
= "lh\t%0,%1%#";
4436 load_store
[num
].store
= "sh\t%0,%1";
4437 load_store
[num
].last_store
= "sh\t%0,%1";
4438 load_store
[num
].final
= 0;
4439 load_store
[num
].mode
= HImode
;
4445 load_store
[num
].load
= "lb\t%0,%1";
4446 load_store
[num
].load_nop
= "lb\t%0,%1%#";
4447 load_store
[num
].store
= "sb\t%0,%1";
4448 load_store
[num
].last_store
= "sb\t%0,%1";
4449 load_store
[num
].final
= 0;
4450 load_store
[num
].mode
= QImode
;
4455 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
4457 dslots_load_total
++;
4458 dslots_load_filled
++;
4460 if (CONSTANT_P (src_reg
))
4461 mips_count_memory_refs (src_reg
, 1);
4463 if (CONSTANT_P (dest_reg
))
4464 mips_count_memory_refs (dest_reg
, 1);
4467 /* Emit load/stores now if we have run out of registers or are
4468 at the end of the move. */
4470 if (++num
== num_regs
|| bytes
== 0)
4472 /* If only load/store, we need a NOP after the load. */
4475 load_store
[0].load
= load_store
[0].load_nop
;
4476 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
4477 dslots_load_filled
--;
4480 if (move_type
!= BLOCK_MOVE_LAST
)
4482 for (i
= 0; i
< num
; i
++)
4486 if (!operands
[i
+ 4])
4489 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
4490 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
4491 REGNO (operands
[i
+ 4]));
4493 offset
= load_store
[i
].offset
;
4494 xoperands
[0] = operands
[i
+ 4];
4495 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4496 plus_constant (src_reg
, offset
));
4501 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4503 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4504 plus_constant (src_reg
,
4509 output_asm_insn (load_store
[i
].load
, xoperands
);
4513 for (i
= 0; i
< num
; i
++)
4515 int last_p
= (i
== num
-1 && bytes
== 0);
4516 int offset
= load_store
[i
].offset
;
4518 xoperands
[0] = operands
[i
+ 4];
4519 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4520 plus_constant (dest_reg
, offset
));
4525 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4526 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4527 plus_constant (dest_reg
,
4532 if (move_type
== BLOCK_MOVE_NORMAL
)
4533 output_asm_insn (load_store
[i
].store
, xoperands
);
4535 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
4538 output_asm_insn (load_store
[i
].store
, xoperands
);
4540 else if (load_store
[i
].final
!= 0)
4541 output_asm_insn (load_store
[i
].final
, xoperands
);
4545 output_asm_insn (load_store
[i
].last_store
, xoperands
);
4548 num
= 0; /* reset load_store */
4556 /* Argument support functions. */
4558 /* Initialize CUMULATIVE_ARGS for a function. */
4561 init_cumulative_args (cum
, fntype
, libname
)
4562 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
4563 tree fntype
; /* tree ptr for function decl */
4564 rtx libname ATTRIBUTE_UNUSED
; /* SYMBOL_REF of library name or 0 */
4566 static CUMULATIVE_ARGS zero_cum
;
4567 tree param
, next_param
;
4569 if (TARGET_DEBUG_E_MODE
)
4572 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
4575 fputc ('\n', stderr
);
4579 tree ret_type
= TREE_TYPE (fntype
);
4580 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
4581 tree_code_name
[(int)TREE_CODE (fntype
)],
4582 tree_code_name
[(int)TREE_CODE (ret_type
)]);
4587 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4589 /* Determine if this function has variable arguments. This is
4590 indicated by the last argument being 'void_type_mode' if there
4591 are no variable arguments. The standard MIPS calling sequence
4592 passes all arguments in the general purpose registers in this case. */
4594 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
4595 param
!= 0; param
= next_param
)
4597 next_param
= TREE_CHAIN (param
);
4598 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
4599 cum
->gp_reg_found
= 1;
4604 mips_arg_info (cum
, mode
, type
, named
, info
)
4605 const CUMULATIVE_ARGS
*cum
;
4606 enum machine_mode mode
;
4609 struct mips_arg_info
*info
;
4612 unsigned int num_words
, max_regs
;
4614 info
->struct_p
= (type
!= 0
4615 && (TREE_CODE (type
) == RECORD_TYPE
4616 || TREE_CODE (type
) == UNION_TYPE
4617 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
4619 /* Decide whether this argument should go in a floating-point register,
4620 assuming one is free. Later code checks for availablity. */
4622 info
->fpr_p
= false;
4623 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4624 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
4630 info
->fpr_p
= (!cum
->gp_reg_found
&& cum
->arg_number
< 2);
4638 /* The MIPS eabi says only structures containing doubles get
4639 passed in a fp register, so force a structure containing
4640 a float to be passed in the integer registers. */
4641 info
->fpr_p
= (named
&& !(mode
== SFmode
&& info
->struct_p
));
4645 info
->fpr_p
= named
;
4650 /* Now decide whether the argument must go in an even-numbered register. */
4655 /* Under the O64 ABI, the second float argument goes in $f13 if it
4656 is a double, but $f14 if it is a single. Otherwise, on a
4657 32-bit double-float machine, each FP argument must start in a
4658 new register pair. */
4659 even_reg_p
= (GET_MODE_SIZE (mode
) > UNITS_PER_HWFPVALUE
4660 || (mips_abi
== ABI_O64
&& mode
== SFmode
)
4663 else if (!TARGET_64BIT
|| LONG_DOUBLE_TYPE_SIZE
== 128)
4665 if (GET_MODE_CLASS (mode
) == MODE_INT
4666 || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4667 even_reg_p
= (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
);
4669 else if (type
!= NULL_TREE
&& TYPE_ALIGN (type
) > BITS_PER_WORD
)
4673 /* Set REG_OFFSET to the register count we're interested in.
4674 The EABI allocates the floating-point registers separately,
4675 but the other ABIs allocate them like integer registers. */
4676 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4681 info
->reg_offset
+= info
->reg_offset
& 1;
4683 /* The alignment applied to registers is also applied to stack arguments. */
4684 info
->stack_offset
= cum
->stack_words
;
4686 info
->stack_offset
+= info
->stack_offset
& 1;
4688 if (mode
== BLKmode
)
4689 info
->num_bytes
= int_size_in_bytes (type
);
4691 info
->num_bytes
= GET_MODE_SIZE (mode
);
4693 num_words
= (info
->num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4694 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4696 /* Partition the argument between registers and stack. */
4697 info
->reg_words
= MIN (num_words
, max_regs
);
4698 info
->stack_words
= num_words
- info
->reg_words
;
4702 /* Advance the argument to the next argument position. */
4705 function_arg_advance (cum
, mode
, type
, named
)
4706 CUMULATIVE_ARGS
*cum
; /* current arg information */
4707 enum machine_mode mode
; /* current arg mode */
4708 tree type
; /* type of the argument or 0 if lib support */
4709 int named
; /* whether or not the argument was named */
4711 struct mips_arg_info info
;
4713 mips_arg_info (cum
, mode
, type
, named
, &info
);
4715 /* The following is a hack in order to pass 1 byte structures
4716 the same way that the MIPS compiler does (namely by passing
4717 the structure in the high byte or half word of the register).
4718 This also makes varargs work. If we have such a structure,
4719 we save the adjustment RTL, and the call define expands will
4720 emit them. For the VOIDmode argument (argument after the
4721 last real argument), pass back a parallel vector holding each
4722 of the adjustments. */
4724 /* ??? This scheme requires everything smaller than the word size to
4725 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4726 that would mean every int needs to be shifted left, which is very
4727 inefficient. Let's not carry this compatibility to the 64 bit
4728 calling convention for now. */
4731 && info
.reg_words
== 1
4732 && info
.num_bytes
< UNITS_PER_WORD
4734 && mips_abi
!= ABI_EABI
4735 && mips_abi
!= ABI_MEABI
)
4737 rtx amount
= GEN_INT (BITS_PER_WORD
- info
.num_bytes
* BITS_PER_UNIT
);
4738 rtx reg
= gen_rtx_REG (word_mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4741 cum
->adjust
[cum
->num_adjusts
++] = PATTERN (gen_ashldi3 (reg
, reg
, amount
));
4743 cum
->adjust
[cum
->num_adjusts
++] = PATTERN (gen_ashlsi3 (reg
, reg
, amount
));
4747 cum
->gp_reg_found
= true;
4749 /* See the comment above the cumulative args structure in mips.h
4750 for an explanation of what this code does. It assumes the O32
4751 ABI, which passes at most 2 arguments in float registers. */
4752 if (cum
->arg_number
< 2 && info
.fpr_p
)
4753 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
4755 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4756 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4757 else if (info
.reg_words
> 0)
4758 cum
->num_fprs
+= FP_INC
;
4760 if (info
.stack_words
> 0)
4761 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4766 /* Return an RTL expression containing the register for the given mode,
4767 or 0 if the argument is to be passed on the stack. */
4770 function_arg (cum
, mode
, type
, named
)
4771 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4772 enum machine_mode mode
; /* current arg mode */
4773 tree type
; /* type of the argument or 0 if lib support */
4774 int named
; /* != 0 for normal args, == 0 for ... args */
4776 struct mips_arg_info info
;
4778 /* We will be called with a mode of VOIDmode after the last argument
4779 has been seen. Whatever we return will be passed to the call
4780 insn. If we need any shifts for small structures, return them in
4781 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4782 mode. Otherwise, if we need a mips16 fp_code, return a REG
4783 with the code stored as the mode. */
4784 if (mode
== VOIDmode
)
4786 if (cum
->num_adjusts
> 0)
4787 return gen_rtx_PARALLEL ((enum machine_mode
) cum
->fp_code
,
4788 gen_rtvec_v (cum
->num_adjusts
,
4789 (rtx
*) cum
->adjust
));
4791 else if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4792 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4798 mips_arg_info (cum
, mode
, type
, named
, &info
);
4800 /* Return straight away if the whole argument is passed on the stack. */
4801 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4805 && TREE_CODE (type
) == RECORD_TYPE
4806 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
4807 && TYPE_SIZE_UNIT (type
)
4808 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
4812 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4813 structure contains a double in its entirety, then that 64 bit
4814 chunk is passed in a floating point register. */
4817 /* First check to see if there is any such field. */
4818 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4819 if (TREE_CODE (field
) == FIELD_DECL
4820 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4821 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4822 && host_integerp (bit_position (field
), 0)
4823 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4828 /* Now handle the special case by returning a PARALLEL
4829 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4830 chunks are passed in registers. */
4832 HOST_WIDE_INT bitpos
;
4835 /* assign_parms checks the mode of ENTRY_PARM, so we must
4836 use the actual mode here. */
4837 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4840 field
= TYPE_FIELDS (type
);
4841 for (i
= 0; i
< info
.reg_words
; i
++)
4845 for (; field
; field
= TREE_CHAIN (field
))
4846 if (TREE_CODE (field
) == FIELD_DECL
4847 && int_bit_position (field
) >= bitpos
)
4851 && int_bit_position (field
) == bitpos
4852 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4853 && !TARGET_SOFT_FLOAT
4854 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4855 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4857 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4860 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4861 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4863 bitpos
+= BITS_PER_WORD
;
4869 if (mips_abi
== ABI_MEABI
&& info
.fpr_p
&& !cum
->prototype
)
4871 /* To make K&R varargs work we need to pass floating
4872 point arguments in both integer and FP registers. */
4873 return gen_rtx_PARALLEL
4876 gen_rtx_EXPR_LIST (VOIDmode
,
4881 gen_rtx_EXPR_LIST (VOIDmode
,
4889 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
4891 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4895 function_arg_partial_nregs (cum
, mode
, type
, named
)
4896 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4897 enum machine_mode mode
; /* current arg mode */
4898 tree type
; /* type of the argument or 0 if lib support */
4899 int named
; /* != 0 for normal args, == 0 for ... args */
4901 struct mips_arg_info info
;
4903 mips_arg_info (cum
, mode
, type
, named
, &info
);
4904 return info
.stack_words
> 0 ? info
.reg_words
: 0;
4908 mips_setup_incoming_varargs (cum
, mode
, type
, no_rtl
)
4909 const CUMULATIVE_ARGS
*cum
;
4910 enum machine_mode mode
;
4914 CUMULATIVE_ARGS local_cum
;
4915 int gp_saved
, fp_saved
;
4917 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
4920 /* The caller has advanced CUM up to, but not beyond, the last named
4921 argument. Advance a local copy of CUM past the last "real" named
4922 argument, to find out how many registers are left over. */
4925 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
4927 /* Found out how many registers we need to save. */
4928 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4929 fp_saved
= (EABI_FLOAT_VARARGS_P
4930 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4939 ptr
= virtual_incoming_args_rtx
;
4940 if (mips_abi
== ABI_EABI
)
4941 ptr
= plus_constant (ptr
, -gp_saved
* UNITS_PER_WORD
);
4942 mem
= gen_rtx_MEM (BLKmode
, ptr
);
4944 /* va_arg is an array access in this case, which causes
4945 it to get MEM_IN_STRUCT_P set. We must set it here
4946 so that the insn scheduler won't assume that these
4947 stores can't possibly overlap with the va_arg loads. */
4948 if (mips_abi
!= ABI_EABI
&& BYTES_BIG_ENDIAN
)
4949 MEM_SET_IN_STRUCT_P (mem
, 1);
4951 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
, mem
,
4952 gp_saved
, gp_saved
* UNITS_PER_WORD
);
4956 /* We can't use move_block_from_reg, because it will use
4958 enum machine_mode mode
;
4961 /* Set OFF to the offset from virtual_incoming_args_rtx of
4962 the first float register. The FP save area lies below
4963 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4964 off
= -gp_saved
* UNITS_PER_WORD
;
4965 off
&= ~(UNITS_PER_FPVALUE
- 1);
4966 off
-= fp_saved
* UNITS_PER_FPREG
;
4968 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4970 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
4972 rtx ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4973 emit_move_insn (gen_rtx_MEM (mode
, ptr
),
4974 gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4975 off
+= UNITS_PER_HWFPVALUE
;
4979 return (gp_saved
* UNITS_PER_WORD
) + (fp_saved
* UNITS_PER_FPREG
);
4982 /* Create the va_list data type.
4983 We keep 3 pointers, and two offsets.
4984 Two pointers are to the overflow area, which starts at the CFA.
4985 One of these is constant, for addressing into the GPR save area below it.
4986 The other is advanced up the stack through the overflow region.
4987 The third pointer is to the GPR save area. Since the FPR save area
4988 is just below it, we can address FPR slots off this pointer.
4989 We also keep two one-byte offsets, which are to be subtracted from the
4990 constant pointers to yield addresses in the GPR and FPR save areas.
4991 These are downcounted as float or non-float arguments are used,
4992 and when they get to zero, the argument must be obtained from the
4994 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4995 pointer is enough. It's started at the GPR save area, and is
4997 Note that the GPR save area is not constant size, due to optimization
4998 in the prologue. Hence, we can't use a design with two pointers
4999 and two offsets, although we could have designed this with two pointers
5000 and three offsets. */
5004 mips_build_va_list ()
5006 if (EABI_FLOAT_VARARGS_P
)
5008 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, record
;
5010 record
= make_node (RECORD_TYPE
);
5012 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
5014 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
5016 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
5018 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
5019 unsigned_char_type_node
);
5020 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
5021 unsigned_char_type_node
);
5024 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5025 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5026 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5027 DECL_FIELD_CONTEXT (f_goff
) = record
;
5028 DECL_FIELD_CONTEXT (f_foff
) = record
;
5030 TYPE_FIELDS (record
) = f_ovfl
;
5031 TREE_CHAIN (f_ovfl
) = f_gtop
;
5032 TREE_CHAIN (f_gtop
) = f_ftop
;
5033 TREE_CHAIN (f_ftop
) = f_goff
;
5034 TREE_CHAIN (f_goff
) = f_foff
;
5036 layout_type (record
);
5040 return ptr_type_node
;
5043 /* Implement va_start. stdarg_p is always 1. */
5046 mips_va_start (valist
, nextarg
)
5050 const CUMULATIVE_ARGS
*cum
= ¤t_function_args_info
;
5052 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
5053 since the stack is aligned for a pair of argument-passing slots,
5054 and the beginning of a variable argument list may be an odd slot,
5055 we have to decrease its alignment. */
5056 if (cfun
&& cfun
->emit
->regno_pointer_align
)
5057 while (((current_function_pretend_args_size
* BITS_PER_UNIT
)
5058 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) - 1)) != 0)
5059 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) /= 2;
5061 if (mips_abi
== ABI_EABI
)
5063 int gpr_save_area_size
;
5066 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5068 if (EABI_FLOAT_VARARGS_P
)
5070 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5071 tree ovfl
, gtop
, ftop
, goff
, foff
;
5074 int fpr_save_area_size
;
5076 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5077 f_gtop
= TREE_CHAIN (f_ovfl
);
5078 f_ftop
= TREE_CHAIN (f_gtop
);
5079 f_goff
= TREE_CHAIN (f_ftop
);
5080 f_foff
= TREE_CHAIN (f_goff
);
5082 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
5083 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
5084 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
5085 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
5086 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
5088 /* Emit code to initialize OVFL, which points to the next varargs
5089 stack argument. CUM->STACK_WORDS gives the number of stack
5090 words used by named arguments. */
5091 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5092 if (cum
->stack_words
> 0)
5093 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
5094 build_int_2 (cum
->stack_words
* UNITS_PER_WORD
, 0));
5095 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5096 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5098 /* Emit code to initialize GTOP, the top of the GPR save area. */
5099 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5100 t
= build (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5101 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5103 /* Emit code to initialize FTOP, the top of the FPR save area.
5104 This address is gpr_save_area_bytes below GTOP, rounded
5105 down to the next fp-aligned boundary. */
5106 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5107 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5108 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
5110 t
= build (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
5111 build_int_2 (-fpr_offset
, -1));
5112 t
= build (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5113 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5115 /* Emit code to initialize GOFF, the offset from GTOP of the
5116 next GPR argument. */
5117 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5118 build_int_2 (gpr_save_area_size
, 0));
5119 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5121 /* Likewise emit code to initialize FOFF, the offset from FTOP
5122 of the next FPR argument. */
5124 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5125 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5126 build_int_2 (fpr_save_area_size
, 0));
5127 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5131 /* Everything is in the GPR save area, or in the overflow
5132 area which is contiguous with it. */
5133 nextarg
= plus_constant (nextarg
, -gpr_save_area_size
);
5134 std_expand_builtin_va_start (valist
, nextarg
);
5138 std_expand_builtin_va_start (valist
, nextarg
);
5141 /* Implement va_arg. */
5144 mips_va_arg (valist
, type
)
5147 HOST_WIDE_INT size
, rsize
;
5151 size
= int_size_in_bytes (type
);
5152 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5154 if (mips_abi
== ABI_EABI
)
5160 = function_arg_pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5164 size
= POINTER_SIZE
/ BITS_PER_UNIT
;
5165 rsize
= UNITS_PER_WORD
;
5168 addr_rtx
= gen_reg_rtx (Pmode
);
5170 if (!EABI_FLOAT_VARARGS_P
)
5172 /* Case of all args in a merged stack. No need to check bounds,
5173 just advance valist along the stack. */
5178 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
)
5180 /* Align the pointer using: ap = (ap + align - 1) & -align,
5181 where align is 2 * UNITS_PER_WORD. */
5182 t
= build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
5183 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
5184 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5185 build_int_2 (-2 * UNITS_PER_WORD
, -1));
5186 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
5187 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5190 /* Emit code to set addr_rtx to the valist, and postincrement
5191 the valist by the size of the argument, rounded up to the
5193 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (gpr
), gpr
,
5195 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5197 emit_move_insn (addr_rtx
, r
);
5199 /* Flush the POSTINCREMENT. */
5204 /* Not a simple merged stack. */
5206 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5207 tree ovfl
, top
, off
;
5208 rtx lab_over
= NULL_RTX
, lab_false
;
5209 HOST_WIDE_INT osize
;
5211 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5212 f_gtop
= TREE_CHAIN (f_ovfl
);
5213 f_ftop
= TREE_CHAIN (f_gtop
);
5214 f_goff
= TREE_CHAIN (f_ftop
);
5215 f_foff
= TREE_CHAIN (f_goff
);
5217 /* We maintain separate pointers and offsets for floating-point
5218 and integer arguments, but we need similar code in both cases.
5221 TOP be the top of the register save area;
5222 OFF be the offset from TOP of the next register;
5223 ADDR_RTX be the address of the argument; and
5224 RSIZE be the number of bytes used to store the argument
5225 when it's in the register save area
5226 OSIZE be the number of bytes used to store it when it's
5227 in the stack overflow area
5228 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
5230 The code we want is:
5232 1: off &= -rsize; // round down
5235 4: addr_rtx = top - off;
5240 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
5241 10: addr_rtx = ovfl + PADDING;
5245 [1] and [9] can sometimes be optimized away. */
5247 lab_false
= gen_label_rtx ();
5248 lab_over
= gen_label_rtx ();
5250 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
5252 if (TREE_CODE (type
) == REAL_TYPE
)
5254 top
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
5255 off
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
5257 /* When floating-point registers are saved to the stack,
5258 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
5259 of the float's precision. */
5260 rsize
= UNITS_PER_HWFPVALUE
;
5264 top
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
5265 off
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
5266 if (rsize
> UNITS_PER_WORD
)
5268 /* [1] Emit code for: off &= -rsize. */
5269 t
= build (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
5270 build_int_2 (-rsize
, -1));
5271 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
5272 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5275 /* Every overflow argument must take up at least UNITS_PER_WORD
5276 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
5277 than that, such as in the combination -mgp64 -msingle-float
5278 -fshort-double. Doubles passed in registers will then take
5279 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
5280 take up UNITS_PER_WORD bytes. */
5281 osize
= MAX (rsize
, UNITS_PER_WORD
);
5283 /* [2] Emit code to branch if off == 0. */
5284 r
= expand_expr (off
, NULL_RTX
, TYPE_MODE (TREE_TYPE (off
)),
5286 emit_cmp_and_jump_insns (r
, const0_rtx
, EQ
, const1_rtx
, GET_MODE (r
),
5289 /* [4] Emit code for: addr_rtx = top - off. */
5290 t
= build (MINUS_EXPR
, TREE_TYPE (top
), top
, off
);
5291 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5293 emit_move_insn (addr_rtx
, r
);
5295 /* [5] Emit code for: off -= rsize. */
5296 t
= build (MINUS_EXPR
, TREE_TYPE (off
), off
, build_int_2 (rsize
, 0));
5297 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
5298 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5300 /* [7] Emit code to jump over the else clause, then the label
5303 emit_jump (lab_over
);
5305 emit_label (lab_false
);
5307 if (osize
> UNITS_PER_WORD
)
5309 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
5310 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
,
5311 build_int_2 (osize
- 1, 0));
5312 t
= build (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
,
5313 build_int_2 (-osize
, -1));
5314 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5315 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5318 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
5319 post-increment ovfl by osize. On big-endian machines,
5320 the argument has OSIZE - RSIZE bytes of leading padding. */
5321 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
,
5323 if (BYTES_BIG_ENDIAN
&& osize
> rsize
)
5324 t
= build (PLUS_EXPR
, TREE_TYPE (t
), t
,
5325 build_int_2 (osize
- rsize
, 0));
5326 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5328 emit_move_insn (addr_rtx
, r
);
5331 emit_label (lab_over
);
5333 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
5334 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
5337 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5338 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
5339 set_mem_alias_set (r
, get_varargs_alias_set ());
5340 emit_move_insn (addr_rtx
, r
);
5349 /* ??? The original va-mips.h did always align, despite the fact
5350 that alignments <= UNITS_PER_WORD are preserved by the va_arg
5351 increment mechanism. */
5353 if ((mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
5354 && TYPE_ALIGN (type
) > 64)
5356 else if (TARGET_64BIT
)
5358 else if (TYPE_ALIGN (type
) > 32)
5363 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
5364 build_int_2 (align
- 1, 0));
5365 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
5366 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5367 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5369 /* Everything past the alignment is standard. */
5370 return std_expand_builtin_va_arg (valist
, type
);
5374 /* Abort after printing out a specific insn. */
5377 abort_with_insn (insn
, reason
)
5386 /* Set up globals to generate code for the ISA or processor
5387 described by INFO. */
5390 mips_set_architecture (info
)
5391 const struct mips_cpu_info
*info
;
5395 mips_arch_info
= info
;
5396 mips_arch
= info
->cpu
;
5397 mips_isa
= info
->isa
;
5402 /* Likewise for tuning. */
5405 mips_set_tune (info
)
5406 const struct mips_cpu_info
*info
;
5410 mips_tune_info
= info
;
5411 mips_tune
= info
->cpu
;
5416 /* Set up the threshold for data to go into the small data area, instead
5417 of the normal data area, and detect any conflicts in the switches. */
5422 int i
, start
, regno
;
5423 enum machine_mode mode
;
5425 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
5427 if (mips_section_threshold
<= 0)
5428 target_flags
&= ~MASK_GPOPT
;
5430 target_flags
|= MASK_GPOPT
;
5432 /* If both single-float and soft-float are set, then clear the one that
5433 was set by TARGET_DEFAULT, leaving the one that was set by the
5434 user. We assume here that the specs prevent both being set by the
5436 #ifdef TARGET_DEFAULT
5437 if (TARGET_SINGLE_FLOAT
&& TARGET_SOFT_FLOAT
)
5438 target_flags
&= ~((TARGET_DEFAULT
) & (MASK_SOFT_FLOAT
| MASK_SINGLE_FLOAT
));
5441 /* Interpret -mabi. */
5442 mips_abi
= MIPS_ABI_DEFAULT
;
5443 if (mips_abi_string
!= 0)
5445 if (strcmp (mips_abi_string
, "32") == 0)
5447 else if (strcmp (mips_abi_string
, "o64") == 0)
5449 else if (strcmp (mips_abi_string
, "n32") == 0)
5451 else if (strcmp (mips_abi_string
, "64") == 0)
5453 else if (strcmp (mips_abi_string
, "eabi") == 0)
5454 mips_abi
= ABI_EABI
;
5455 else if (strcmp (mips_abi_string
, "meabi") == 0)
5456 mips_abi
= ABI_MEABI
;
5458 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string
);
5461 /* The following code determines the architecture and register size.
5462 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5463 The GAS and GCC code should be kept in sync as much as possible. */
5465 if (mips_arch_string
!= 0)
5466 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
5468 if (mips_tune_string
!= 0)
5469 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
5471 if (mips_isa_string
!= 0)
5473 /* Handle -mipsN. */
5475 if (strcmp (mips_isa_string
, "16") == 0)
5477 /* -mips16 specifies an ASE rather than a processor, so don't
5478 change mips_arch here. -mno-mips16 overrides -mips16. */
5479 if (mips_no_mips16_string
== NULL
)
5480 target_flags
|= MASK_MIPS16
;
5484 char *whole_isa_str
= concat ("mips", mips_isa_string
, NULL
);
5485 const struct mips_cpu_info
*isa_info
;
5487 isa_info
= mips_parse_cpu ("-mips option", whole_isa_str
);
5488 free (whole_isa_str
);
5490 /* -march takes precedence over -mipsN, since it is more descriptive.
5491 There's no harm in specifying both as long as the ISA levels
5493 if (mips_arch_info
!= 0 && mips_isa
!= isa_info
->isa
)
5494 error ("-mips%s conflicts with the other architecture options, which specify a MIPS%d processor",
5495 mips_isa_string
, mips_isa
);
5497 /* Set architecture based on the given option. */
5498 mips_set_architecture (isa_info
);
5502 if (mips_arch_info
== 0)
5504 #ifdef MIPS_CPU_STRING_DEFAULT
5505 mips_set_architecture (mips_parse_cpu ("default CPU",
5506 MIPS_CPU_STRING_DEFAULT
));
5508 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
5512 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
5513 error ("-march=%s is not compatible with the selected ABI",
5514 mips_arch_info
->name
);
5516 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5517 if (mips_tune_info
== 0)
5518 mips_set_tune (mips_arch_info
);
5520 if ((target_flags_explicit
& MASK_64BIT
) != 0)
5522 /* The user specified the size of the integer registers. Make sure
5523 it agrees with the ABI and ISA. */
5524 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
5525 error ("-mgp64 used with a 32-bit processor");
5526 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
5527 error ("-mgp32 used with a 64-bit ABI");
5528 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
5529 error ("-mgp64 used with a 32-bit ABI");
5533 /* Infer the integer register size from the ABI and processor.
5534 Restrict ourselves to 32-bit registers if that's all the
5535 processor has, or if the ABI cannot handle 64-bit registers. */
5536 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
5537 target_flags
&= ~MASK_64BIT
;
5539 target_flags
|= MASK_64BIT
;
5542 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
5544 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5545 only one right answer here. */
5546 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
5547 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5548 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
5549 error ("unsupported combination: %s", "-mgp32 -mfp64");
5550 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
5551 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5555 /* -msingle-float selects 32-bit float registers. Otherwise the
5556 float registers should be the same size as the integer ones. */
5557 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
5558 target_flags
|= MASK_FLOAT64
;
5560 target_flags
&= ~MASK_FLOAT64
;
5563 /* End of code shared with GAS. */
5565 if ((target_flags_explicit
& MASK_LONG64
) == 0)
5567 /* If no type size setting options (-mlong64,-mint64,-mlong32)
5568 were used, then set the type sizes. In the EABI in 64 bit mode,
5569 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
5571 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
5572 target_flags
|= MASK_LONG64
;
5574 target_flags
&= ~MASK_LONG64
;
5577 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5578 && (target_flags_explicit
& MASK_SOFT_FLOAT
) == 0)
5580 /* For some configurations, it is useful to have -march control
5581 the default setting of MASK_SOFT_FLOAT. */
5582 switch ((int) mips_arch
)
5584 case PROCESSOR_R4100
:
5585 case PROCESSOR_R4120
:
5586 target_flags
|= MASK_SOFT_FLOAT
;
5590 target_flags
&= ~MASK_SOFT_FLOAT
;
5595 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
5596 flag_pcc_struct_return
= 0;
5598 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
5600 /* If neither -mbranch-likely nor -mno-branch-likely was given
5601 on the command line, set MASK_BRANCHLIKELY based on the target
5604 By default, we enable use of Branch Likely instructions on
5605 all architectures which support them except for MIPS32 and MIPS64
5606 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
5609 The MIPS32 and MIPS64 architecture specifications say "Software
5610 is strongly encouraged to avoid use of Branch Likely
5611 instructions, as they will be removed from a future revision
5612 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5613 issue those instructions unless instructed to do so by
5615 if (ISA_HAS_BRANCHLIKELY
&& !(ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64
))
5616 target_flags
|= MASK_BRANCHLIKELY
;
5618 target_flags
&= ~MASK_BRANCHLIKELY
;
5620 if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
5621 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
5623 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5624 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5625 /* ??? -non_shared turns off pic code generation, but this is not
5627 if (TARGET_ABICALLS
)
5629 mips_abicalls
= MIPS_ABICALLS_YES
;
5631 if (mips_section_threshold
> 0)
5632 warning ("-G is incompatible with PIC code which is the default");
5635 mips_abicalls
= MIPS_ABICALLS_NO
;
5637 /* -membedded-pic is a form of PIC code suitable for embedded
5638 systems. All calls are made using PC relative addressing, and
5639 all data is addressed using the $gp register. This requires gas,
5640 which does most of the work, and GNU ld, which automatically
5641 expands PC relative calls which are out of range into a longer
5642 instruction sequence. All gcc really does differently is
5643 generate a different sequence for a switch. */
5644 if (TARGET_EMBEDDED_PIC
)
5647 if (TARGET_ABICALLS
)
5648 warning ("-membedded-pic and -mabicalls are incompatible");
5651 warning ("-G and -membedded-pic are incompatible");
5653 /* Setting mips_section_threshold is not required, because gas
5654 will force everything to be GP addressable anyhow, but
5655 setting it will cause gcc to make better estimates of the
5656 number of instructions required to access a particular data
5658 mips_section_threshold
= 0x7fffffff;
5661 /* This optimization requires a linker that can support a R_MIPS_LO16
5662 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5663 GNU ld has this support, but not all other MIPS linkers do, so we enable
5664 this optimization only if the user requests it, or if GNU ld is the
5665 standard linker for this configuration. */
5666 /* ??? This does not work when target addresses are DImode.
5667 This is because we are missing DImode high/lo_sum patterns. */
5668 if (TARGET_GAS
&& ! TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
5670 mips_split_addresses
= 1;
5672 mips_split_addresses
= 0;
5674 /* -mrnames says to use the MIPS software convention for register
5675 names instead of the hardware names (ie, $a0 instead of $4).
5676 We do this by switching the names in mips_reg_names, which the
5677 reg_names points into via the REGISTER_NAMES macro. */
5679 if (TARGET_NAME_REGS
)
5680 memcpy (mips_reg_names
, mips_sw_reg_names
, sizeof (mips_reg_names
));
5682 /* When compiling for the mips16, we can not use floating point. We
5683 record the original hard float value in mips16_hard_float. */
5686 if (TARGET_SOFT_FLOAT
)
5687 mips16_hard_float
= 0;
5689 mips16_hard_float
= 1;
5690 target_flags
|= MASK_SOFT_FLOAT
;
5692 /* Don't run the scheduler before reload, since it tends to
5693 increase register pressure. */
5694 flag_schedule_insns
= 0;
5697 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5698 to avoid using up another bit in target_flags. */
5699 if (mips_entry_string
!= NULL
)
5701 if (*mips_entry_string
!= '\0')
5702 error ("invalid option `entry%s'", mips_entry_string
);
5704 if (! TARGET_MIPS16
)
5705 warning ("-mentry is only meaningful with -mips-16");
5710 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5711 attributes can access it. */
5717 real_format_for_mode
[SFmode
- QFmode
] = &mips_single_format
;
5718 real_format_for_mode
[DFmode
- QFmode
] = &mips_double_format
;
5719 #ifdef MIPS_TFMODE_FORMAT
5720 real_format_for_mode
[TFmode
- QFmode
] = &MIPS_TFMODE_FORMAT
;
5722 real_format_for_mode
[TFmode
- QFmode
] = &mips_quad_format
;
5725 mips_print_operand_punct
['?'] = 1;
5726 mips_print_operand_punct
['#'] = 1;
5727 mips_print_operand_punct
['&'] = 1;
5728 mips_print_operand_punct
['!'] = 1;
5729 mips_print_operand_punct
['*'] = 1;
5730 mips_print_operand_punct
['@'] = 1;
5731 mips_print_operand_punct
['.'] = 1;
5732 mips_print_operand_punct
['('] = 1;
5733 mips_print_operand_punct
[')'] = 1;
5734 mips_print_operand_punct
['['] = 1;
5735 mips_print_operand_punct
[']'] = 1;
5736 mips_print_operand_punct
['<'] = 1;
5737 mips_print_operand_punct
['>'] = 1;
5738 mips_print_operand_punct
['{'] = 1;
5739 mips_print_operand_punct
['}'] = 1;
5740 mips_print_operand_punct
['^'] = 1;
5741 mips_print_operand_punct
['$'] = 1;
5742 mips_print_operand_punct
['+'] = 1;
5743 mips_print_operand_punct
['~'] = 1;
5745 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
5746 mips_char_to_class
['e'] = M16_NA_REGS
;
5747 mips_char_to_class
['t'] = T_REG
;
5748 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
5749 mips_char_to_class
['h'] = HI_REG
;
5750 mips_char_to_class
['l'] = LO_REG
;
5751 mips_char_to_class
['a'] = HILO_REG
;
5752 mips_char_to_class
['x'] = MD_REGS
;
5753 mips_char_to_class
['b'] = ALL_REGS
;
5754 mips_char_to_class
['y'] = GR_REGS
;
5755 mips_char_to_class
['z'] = ST_REGS
;
5756 mips_char_to_class
['B'] = COP0_REGS
;
5757 mips_char_to_class
['C'] = COP2_REGS
;
5758 mips_char_to_class
['D'] = COP3_REGS
;
5760 /* Set up array to map GCC register number to debug register number.
5761 Ignore the special purpose register numbers. */
5763 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5764 mips_dbx_regno
[i
] = -1;
5766 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
5767 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
5768 mips_dbx_regno
[i
] = i
+ start
;
5770 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
5771 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
5772 mips_dbx_regno
[i
] = i
+ start
;
5774 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
5775 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
5777 /* Set up array giving whether a given register can hold a given mode.
5778 At present, restrict ints from being in FP registers, because reload
5779 is a little enthusiastic about storing extra values in FP registers,
5780 and this is not good for things like OS kernels. Also, due to the
5781 mandatory delay, it is as fast to load from cached memory as to move
5782 from the FP register. */
5784 for (mode
= VOIDmode
;
5785 mode
!= MAX_MACHINE_MODE
;
5786 mode
= (enum machine_mode
) ((int)mode
+ 1))
5788 register int size
= GET_MODE_SIZE (mode
);
5789 register enum mode_class
class = GET_MODE_CLASS (mode
);
5791 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
5798 temp
= (regno
== FPSW_REGNUM
);
5800 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
5801 || FP_REG_P (regno
));
5804 else if (GP_REG_P (regno
))
5805 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
5807 else if (FP_REG_P (regno
))
5808 temp
= (((regno
% FP_INC
) == 0
5809 /* I think this change is OK regardless of abi, but
5810 I'm being cautions untill I can test this more.
5811 HARD_REGNO_MODE_OK is about whether or not you
5812 can move to and from a register without changing
5813 the value, not about whether math works on the
5815 || (mips_abi
== ABI_MEABI
&& size
<= 4))
5816 && (((class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
5817 && size
<= UNITS_PER_FPVALUE
)
5818 /* Allow integer modes that fit into a single
5819 register. We need to put integers into FPRs
5820 when using instructions like cvt and trunc. */
5821 || (class == MODE_INT
&& size
<= UNITS_PER_FPREG
)
5822 /* Allow TFmode for CCmode reloads. */
5823 || (ISA_HAS_8CC
&& mode
== TFmode
)));
5825 else if (MD_REG_P (regno
))
5826 temp
= (class == MODE_INT
5827 && (size
<= UNITS_PER_WORD
5828 || (regno
== MD_REG_FIRST
5829 && size
== 2 * UNITS_PER_WORD
)));
5831 else if (ALL_COP_REG_P (regno
))
5832 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
5836 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
5840 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5841 initialized yet, so we can't use that here. */
5842 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
5844 /* Provide default values for align_* for 64-bit targets. */
5845 if (TARGET_64BIT
&& !TARGET_MIPS16
)
5847 if (align_loops
== 0)
5849 if (align_jumps
== 0)
5851 if (align_functions
== 0)
5852 align_functions
= 8;
5855 /* Function to allocate machine-dependent function status. */
5856 init_machine_status
= &mips_init_machine_status
;
5859 /* Implement CONDITIONAL_REGISTER_USAGE. */
5862 mips_conditional_register_usage ()
5864 if (!TARGET_HARD_FLOAT
)
5868 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
5869 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5870 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5871 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5873 else if (! ISA_HAS_8CC
)
5877 /* We only have a single condition code register. We
5878 implement this by hiding all the condition code registers,
5879 and generating RTL that refers directly to ST_REG_FIRST. */
5880 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5881 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5883 /* In mips16 mode, we permit the $t temporary registers to be used
5884 for reload. We prohibit the unused $s registers, since they
5885 are caller saved, and saving them via a mips16 register would
5886 probably waste more time than just reloading the value. */
5889 fixed_regs
[18] = call_used_regs
[18] = 1;
5890 fixed_regs
[19] = call_used_regs
[19] = 1;
5891 fixed_regs
[20] = call_used_regs
[20] = 1;
5892 fixed_regs
[21] = call_used_regs
[21] = 1;
5893 fixed_regs
[22] = call_used_regs
[22] = 1;
5894 fixed_regs
[23] = call_used_regs
[23] = 1;
5895 fixed_regs
[26] = call_used_regs
[26] = 1;
5896 fixed_regs
[27] = call_used_regs
[27] = 1;
5897 fixed_regs
[30] = call_used_regs
[30] = 1;
5899 /* fp20-23 are now caller saved. */
5900 if (mips_abi
== ABI_64
)
5903 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
5904 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5906 /* odd registers from fp21 to fp31 are now caller saved. */
5907 if (mips_abi
== ABI_N32
|| mips_abi
== ABI_MEABI
)
5910 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
5911 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5915 /* Allocate a chunk of memory for per-function machine-dependent data. */
5916 static struct machine_function
*
5917 mips_init_machine_status ()
5919 return ((struct machine_function
*)
5920 ggc_alloc_cleared (sizeof (struct machine_function
)));
5923 /* On the mips16, we want to allocate $24 (T_REG) before other
5924 registers for instructions for which it is possible. This helps
5925 avoid shuffling registers around in order to set up for an xor,
5926 encouraging the compiler to use a cmp instead. */
5929 mips_order_regs_for_local_alloc ()
5933 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5934 reg_alloc_order
[i
] = i
;
5938 /* It really doesn't matter where we put register 0, since it is
5939 a fixed register anyhow. */
5940 reg_alloc_order
[0] = 24;
5941 reg_alloc_order
[24] = 0;
5946 /* The MIPS debug format wants all automatic variables and arguments
5947 to be in terms of the virtual frame pointer (stack pointer before
5948 any adjustment in the function), while the MIPS 3.0 linker wants
5949 the frame pointer to be the stack pointer after the initial
5950 adjustment. So, we do the adjustment here. The arg pointer (which
5951 is eliminated) points to the virtual frame pointer, while the frame
5952 pointer (which may be eliminated) points to the stack pointer after
5953 the initial adjustments. */
5956 mips_debugger_offset (addr
, offset
)
5958 HOST_WIDE_INT offset
;
5960 rtx offset2
= const0_rtx
;
5961 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5964 offset
= INTVAL (offset2
);
5966 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5967 || reg
== hard_frame_pointer_rtx
)
5969 HOST_WIDE_INT frame_size
= (!cfun
->machine
->frame
.initialized
)
5970 ? compute_frame_size (get_frame_size ())
5971 : cfun
->machine
->frame
.total_size
;
5973 /* MIPS16 frame is smaller */
5974 if (frame_pointer_needed
&& TARGET_MIPS16
)
5975 frame_size
-= current_function_outgoing_args_size
;
5977 offset
= offset
- frame_size
;
5980 /* sdbout_parms does not want this to crash for unrecognized cases. */
5982 else if (reg
!= arg_pointer_rtx
)
5983 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer");
5989 /* A C compound statement to output to stdio stream STREAM the
5990 assembler syntax for an instruction operand X. X is an RTL
5993 CODE is a value that can be used to specify one of several ways
5994 of printing the operand. It is used when identical operands
5995 must be printed differently depending on the context. CODE
5996 comes from the `%' specification that was used to request
5997 printing of the operand. If the specification was just `%DIGIT'
5998 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5999 is the ASCII code for LTR.
6001 If X is a register, this macro should print the register's name.
6002 The names can be found in an array `reg_names' whose type is
6003 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
6005 When the machine description has a specification `%PUNCT' (a `%'
6006 followed by a punctuation character), this macro is called with
6007 a null pointer for X and the punctuation character for CODE.
6009 The MIPS specific codes are:
6011 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
6012 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
6013 'd' output integer constant in decimal,
6014 'z' if the operand is 0, use $0 instead of normal operand.
6015 'D' print second part of double-word register or memory operand.
6016 'L' print low-order register of double-word register operand.
6017 'M' print high-order register of double-word register operand.
6018 'C' print part of opcode for a branch condition.
6019 'F' print part of opcode for a floating-point branch condition.
6020 'N' print part of opcode for a branch condition, inverted.
6021 'W' print part of opcode for a floating-point branch condition, inverted.
6022 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
6023 'B' print 'z' for EQ, 'n' for NE
6024 'b' print 'n' for EQ, 'z' for NE
6025 'T' print 'f' for EQ, 't' for NE
6026 't' print 't' for EQ, 'f' for NE
6027 'Z' print register and a comma, but print nothing for $fcc0
6028 '(' Turn on .set noreorder
6029 ')' Turn on .set reorder
6030 '[' Turn on .set noat
6032 '<' Turn on .set nomacro
6033 '>' Turn on .set macro
6034 '{' Turn on .set volatile (not GAS)
6035 '}' Turn on .set novolatile (not GAS)
6036 '&' Turn on .set noreorder if filling delay slots
6037 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
6038 '!' Turn on .set nomacro if filling delay slots
6039 '#' Print nop if in a .set noreorder section.
6040 '?' Print 'l' if we are to use a branch likely instead of normal branch.
6041 '@' Print the name of the assembler temporary register (at or $1).
6042 '.' Print the name of the register with a hard-wired zero (zero or $0).
6043 '^' Print the name of the pic call-through register (t9 or $25).
6044 '$' Print the name of the stack pointer register (sp or $29).
6045 '+' Print the name of the gp register (gp or $28).
6046 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
6049 print_operand (file
, op
, letter
)
6050 FILE *file
; /* file to write to */
6051 rtx op
; /* operand to print */
6052 int letter
; /* %<letter> or 0 */
6054 register enum rtx_code code
;
6056 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
6061 if (mips_branch_likely
)
6066 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
6070 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
6074 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
6078 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
6082 fputs (reg_names
[GP_REG_FIRST
+ 28], file
);
6086 if (final_sequence
!= 0 && set_noreorder
++ == 0)
6087 fputs (".set\tnoreorder\n\t", file
);
6091 if (final_sequence
!= 0)
6093 if (set_noreorder
++ == 0)
6094 fputs (".set\tnoreorder\n\t", file
);
6096 if (set_nomacro
++ == 0)
6097 fputs (".set\tnomacro\n\t", file
);
6102 if (final_sequence
!= 0 && set_nomacro
++ == 0)
6103 fputs ("\n\t.set\tnomacro", file
);
6107 if (set_noreorder
!= 0)
6108 fputs ("\n\tnop", file
);
6109 else if (TARGET_STATS
)
6110 fputs ("\n\t#nop", file
);
6115 if (set_noreorder
++ == 0)
6116 fputs (".set\tnoreorder\n\t", file
);
6120 if (set_noreorder
== 0)
6121 error ("internal error: %%) found without a %%( in assembler pattern");
6123 else if (--set_noreorder
== 0)
6124 fputs ("\n\t.set\treorder", file
);
6129 if (set_noat
++ == 0)
6130 fputs (".set\tnoat\n\t", file
);
6135 error ("internal error: %%] found without a %%[ in assembler pattern");
6136 else if (--set_noat
== 0)
6137 fputs ("\n\t.set\tat", file
);
6142 if (set_nomacro
++ == 0)
6143 fputs (".set\tnomacro\n\t", file
);
6147 if (set_nomacro
== 0)
6148 error ("internal error: %%> found without a %%< in assembler pattern");
6149 else if (--set_nomacro
== 0)
6150 fputs ("\n\t.set\tmacro", file
);
6155 if (set_volatile
++ == 0)
6156 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
6160 if (set_volatile
== 0)
6161 error ("internal error: %%} found without a %%{ in assembler pattern");
6162 else if (--set_volatile
== 0)
6163 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
6169 if (align_labels_log
> 0)
6170 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
6175 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
6184 error ("PRINT_OPERAND null pointer");
6188 code
= GET_CODE (op
);
6190 if (code
== SIGN_EXTEND
)
6191 op
= XEXP (op
, 0), code
= GET_CODE (op
);
6196 case EQ
: fputs ("eq", file
); break;
6197 case NE
: fputs ("ne", file
); break;
6198 case GT
: fputs ("gt", file
); break;
6199 case GE
: fputs ("ge", file
); break;
6200 case LT
: fputs ("lt", file
); break;
6201 case LE
: fputs ("le", file
); break;
6202 case GTU
: fputs ("gtu", file
); break;
6203 case GEU
: fputs ("geu", file
); break;
6204 case LTU
: fputs ("ltu", file
); break;
6205 case LEU
: fputs ("leu", file
); break;
6207 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
6210 else if (letter
== 'N')
6213 case EQ
: fputs ("ne", file
); break;
6214 case NE
: fputs ("eq", file
); break;
6215 case GT
: fputs ("le", file
); break;
6216 case GE
: fputs ("lt", file
); break;
6217 case LT
: fputs ("ge", file
); break;
6218 case LE
: fputs ("gt", file
); break;
6219 case GTU
: fputs ("leu", file
); break;
6220 case GEU
: fputs ("ltu", file
); break;
6221 case LTU
: fputs ("geu", file
); break;
6222 case LEU
: fputs ("gtu", file
); break;
6224 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
6227 else if (letter
== 'F')
6230 case EQ
: fputs ("c1f", file
); break;
6231 case NE
: fputs ("c1t", file
); break;
6233 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%F");
6236 else if (letter
== 'W')
6239 case EQ
: fputs ("c1t", file
); break;
6240 case NE
: fputs ("c1f", file
); break;
6242 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%W");
6245 else if (letter
== 'S')
6249 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
6250 assemble_name (file
, buffer
);
6253 else if (letter
== 'Z')
6255 register int regnum
;
6260 regnum
= REGNO (op
);
6261 if (! ST_REG_P (regnum
))
6264 if (regnum
!= ST_REG_FIRST
)
6265 fprintf (file
, "%s,", reg_names
[regnum
]);
6268 else if (code
== REG
|| code
== SUBREG
)
6270 register int regnum
;
6273 regnum
= REGNO (op
);
6275 regnum
= true_regnum (op
);
6277 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
6278 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
6282 fprintf (file
, "%s", reg_names
[regnum
]);
6285 else if (code
== MEM
)
6288 output_address (plus_constant (XEXP (op
, 0), 4));
6290 output_address (XEXP (op
, 0));
6293 else if (code
== CONST_DOUBLE
6294 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
6298 real_to_decimal (s
, CONST_DOUBLE_REAL_VALUE (op
), sizeof (s
), 0, 1);
6302 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
6303 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
6305 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
6306 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
6308 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
6309 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
6311 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
6312 fputs (reg_names
[GP_REG_FIRST
], file
);
6314 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
6315 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
6317 else if (letter
== 'B')
6318 fputs (code
== EQ
? "z" : "n", file
);
6319 else if (letter
== 'b')
6320 fputs (code
== EQ
? "n" : "z", file
);
6321 else if (letter
== 'T')
6322 fputs (code
== EQ
? "f" : "t", file
);
6323 else if (letter
== 't')
6324 fputs (code
== EQ
? "t" : "f", file
);
6326 else if (code
== CONST
&& GET_CODE (XEXP (op
, 0)) == REG
)
6328 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
6329 print_operand (file
, XEXP (op
, 0), letter
);
6332 else if (TARGET_MIPS16
&& code
== CONST
&& mips16_gp_offset_p (op
))
6334 fputs ("%gprel(", file
);
6335 mips16_output_gp_offset (file
, op
);
6340 output_addr_const (file
, op
);
6343 /* A C compound statement to output to stdio stream STREAM the
6344 assembler syntax for an instruction operand that is a memory
6345 reference whose address is ADDR. ADDR is an RTL expression. */
6348 print_operand_address (file
, addr
)
6353 error ("PRINT_OPERAND_ADDRESS, null pointer");
6356 switch (GET_CODE (addr
))
6359 if (! TARGET_MIPS16
&& REGNO (addr
) == ARG_POINTER_REGNUM
)
6360 abort_with_insn (addr
, "arg pointer not eliminated");
6362 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
6367 register rtx arg0
= XEXP (addr
, 0);
6368 register rtx arg1
= XEXP (addr
, 1);
6370 if (! mips_split_addresses
)
6371 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
6373 if (GET_CODE (arg0
) != REG
)
6374 abort_with_insn (addr
,
6375 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
6377 fprintf (file
, "%%lo(");
6378 print_operand_address (file
, arg1
);
6379 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
6385 register rtx reg
= 0;
6386 register rtx offset
= 0;
6387 register rtx arg0
= XEXP (addr
, 0);
6388 register rtx arg1
= XEXP (addr
, 1);
6390 if (GET_CODE (arg0
) == REG
)
6394 if (GET_CODE (offset
) == REG
)
6395 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
6398 else if (GET_CODE (arg1
) == REG
)
6399 reg
= arg1
, offset
= arg0
;
6400 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
6402 output_addr_const (file
, addr
);
6406 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
6408 if (! CONSTANT_P (offset
))
6409 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
6411 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
6412 abort_with_insn (addr
, "arg pointer not eliminated");
6415 && GET_CODE (offset
) == CONST
6416 && mips16_gp_offset_p (offset
))
6418 fputs ("%gprel(", file
);
6419 mips16_output_gp_offset (file
, offset
);
6423 output_addr_const (file
, offset
);
6424 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
6432 output_addr_const (file
, addr
);
6436 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
6441 /* Target hook for assembling integer objects. It appears that the Irix
6442 6 assembler can't handle 64-bit decimal integers, so avoid printing
6443 such an integer here. */
6446 mips_assemble_integer (x
, size
, aligned_p
)
6451 if ((TARGET_64BIT
|| TARGET_GAS
) && size
== 8 && aligned_p
)
6453 fputs ("\t.dword\t", asm_out_file
);
6454 if (HOST_BITS_PER_WIDE_INT
< 64 || GET_CODE (x
) != CONST_INT
)
6455 output_addr_const (asm_out_file
, x
);
6457 print_operand (asm_out_file
, x
, 'X');
6458 fputc ('\n', asm_out_file
);
6461 return default_assemble_integer (x
, size
, aligned_p
);
6464 /* If optimizing for the global pointer, keep track of all of the externs, so
6465 that at the end of the file, we can emit the appropriate .extern
6466 declaration for them, before writing out the text section. We assume all
6467 names passed to us are in the permanent obstack, so they will be valid at
6468 the end of the compilation.
6470 If we have -G 0, or the extern size is unknown, or the object is in a user
6471 specified section that is not .sbss/.sdata, don't bother emitting the
6472 .externs. In the case of user specified sections this behavior is
6473 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6476 mips_output_external (file
, decl
, name
)
6477 FILE *file ATTRIBUTE_UNUSED
;
6481 register struct extern_list
*p
;
6486 && TREE_CODE (decl
) != FUNCTION_DECL
6487 && !DECL_COMDAT (decl
)
6488 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
6489 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
6490 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
6491 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
6493 p
= (struct extern_list
*) xmalloc (sizeof (struct extern_list
));
6494 p
->next
= extern_head
;
6500 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6501 if (TREE_CODE (decl
) == FUNCTION_DECL
6502 /* ??? Don't include alloca, since gcc will always expand it
6503 inline. If we don't do this, the C++ library fails to build. */
6504 && strcmp (name
, "alloca")
6505 /* ??? Don't include __builtin_next_arg, because then gcc will not
6506 bootstrap under Irix 5.1. */
6507 && strcmp (name
, "__builtin_next_arg"))
6509 p
= (struct extern_list
*) xmalloc (sizeof (struct extern_list
));
6510 p
->next
= extern_head
;
6520 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6522 mips_output_external_libcall (file
, name
)
6523 FILE *file ATTRIBUTE_UNUSED
;
6526 register struct extern_list
*p
;
6528 p
= (struct extern_list
*) xmalloc (sizeof (struct extern_list
));
6529 p
->next
= extern_head
;
6538 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6539 for .file's that start within a function. If we are smuggling stabs, try to
6540 put out a MIPS ECOFF file and a stab. */
6543 mips_output_filename (stream
, name
)
6547 static int first_time
= 1;
6548 char ltext_label_name
[100];
6550 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6552 if (write_symbols
== DWARF2_DEBUG
)
6554 else if (first_time
)
6558 current_function_file
= name
;
6559 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6560 /* This tells mips-tfile that stabs will follow. */
6561 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
6562 fprintf (stream
, "\t#@stabs\n");
6565 else if (write_symbols
== DBX_DEBUG
)
6567 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
6568 fprintf (stream
, "%s", ASM_STABS_OP
);
6569 output_quoted_string (stream
, name
);
6570 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
6573 else if (name
!= current_function_file
6574 && strcmp (name
, current_function_file
) != 0)
6576 if (inside_function
&& !TARGET_GAS
)
6578 if (!file_in_function_warning
)
6580 file_in_function_warning
= 1;
6581 ignore_line_number
= 1;
6582 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6588 current_function_file
= name
;
6589 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6594 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6595 as well as a .loc, since it is possible that MIPS ECOFF might not be
6596 able to represent the location for inlines that come from a different
6600 mips_output_lineno (stream
, line
)
6604 if (write_symbols
== DBX_DEBUG
)
6607 fprintf (stream
, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6608 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
6609 LOCAL_LABEL_PREFIX
, sym_lineno
);
6613 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
6614 (ignore_line_number
) ? "#" : "",
6615 num_source_filenames
, line
);
6617 LABEL_AFTER_LOC (stream
);
6621 /* Output an ASCII string, in a space-saving way. */
6624 mips_output_ascii (stream
, string_param
, len
)
6626 const char *string_param
;
6631 register const unsigned char *string
=
6632 (const unsigned char *)string_param
;
6634 fprintf (stream
, "\t.ascii\t\"");
6635 for (i
= 0; i
< len
; i
++)
6637 register int c
= string
[i
];
6643 putc ('\\', stream
);
6648 case TARGET_NEWLINE
:
6649 fputs ("\\n", stream
);
6651 && (((c
= string
[i
+1]) >= '\040' && c
<= '~')
6652 || c
== TARGET_TAB
))
6653 cur_pos
= 32767; /* break right here */
6659 fputs ("\\t", stream
);
6664 fputs ("\\f", stream
);
6669 fputs ("\\b", stream
);
6674 fputs ("\\r", stream
);
6679 if (c
>= ' ' && c
< 0177)
6686 fprintf (stream
, "\\%03o", c
);
6691 if (cur_pos
> 72 && i
+1 < len
)
6694 fprintf (stream
, "\"\n\t.ascii\t\"");
6697 fprintf (stream
, "\"\n");
6700 /* If defined, a C statement to be executed just prior to the output of
6701 assembler code for INSN, to modify the extracted operands so they will be
6704 Here the argument OPVEC is the vector containing the operands extracted
6705 from INSN, and NOPERANDS is the number of elements of the vector which
6706 contain meaningful data for this insn. The contents of this vector are
6707 what will be used to convert the insn template into assembler code, so you
6708 can change the assembler output by changing the contents of the vector.
6710 We use it to check if the current insn needs a nop in front of it because
6711 of load delays, and also to update the delay slot statistics. */
6713 /* ??? There is no real need for this function, because it never actually
6714 emits a NOP anymore. */
6717 final_prescan_insn (insn
, opvec
, noperands
)
6719 rtx opvec
[] ATTRIBUTE_UNUSED
;
6720 int noperands ATTRIBUTE_UNUSED
;
6722 if (dslots_number_nops
> 0)
6724 rtx pattern
= PATTERN (insn
);
6725 int length
= get_attr_length (insn
);
6727 /* Do we need to emit a NOP? */
6729 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
6730 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
6731 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
6732 || (mips_load_reg4
!= 0
6733 && reg_mentioned_p (mips_load_reg4
, pattern
)))
6734 fputs ("\t#nop\n", asm_out_file
);
6737 dslots_load_filled
++;
6739 while (--dslots_number_nops
> 0)
6740 fputs ("\t#nop\n", asm_out_file
);
6749 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
6750 dslots_jump_total
++;
6753 /* Output at beginning of assembler file.
6755 If we are optimizing to use the global pointer, create a temporary file to
6756 hold all of the text stuff, and write it out to the end. This is needed
6757 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6758 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6759 processed, it generates a two instruction sequence. */
6762 mips_asm_file_start (stream
)
6765 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
6767 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6768 inside of a .set noreorder section jumps to a label outside of the .set
6769 noreorder section. Revision 2.20 just set nobopt silently rather than
6772 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
6773 fprintf (stream
, "\t.set\tnobopt\n");
6777 #if defined(OBJECT_FORMAT_ELF) && !(TARGET_IRIX5 || TARGET_IRIX6)
6778 /* Generate a special section to describe the ABI switches used to
6779 produce the resultant binary. This used to be done by the assembler
6780 setting bits in the ELF header's flags field, but we have run out of
6781 bits. GDB needs this information in order to be able to correctly
6782 debug these binaries. See the function mips_gdbarch_init() in
6783 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6784 causes unnecessary IRIX 6 ld warnings. */
6785 const char * abi_string
= NULL
;
6789 case ABI_32
: abi_string
= "abi32"; break;
6790 case ABI_N32
: abi_string
= "abiN32"; break;
6791 case ABI_64
: abi_string
= "abi64"; break;
6792 case ABI_O64
: abi_string
= "abiO64"; break;
6793 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
6794 case ABI_MEABI
:abi_string
= TARGET_64BIT
? "meabi64" : "meabi32"; break;
6798 /* Note - we use fprintf directly rather than called named_section()
6799 because in this way we can avoid creating an allocated section. We
6800 do not want this section to take up any space in the running
6802 fprintf (stream
, "\t.section .mdebug.%s\n", abi_string
);
6804 /* Restore the default section. */
6805 fprintf (stream
, "\t.previous\n");
6811 /* Generate the pseudo ops that System V.4 wants. */
6812 #ifndef ABICALLS_ASM_OP
6813 #define ABICALLS_ASM_OP "\t.abicalls"
6815 if (TARGET_ABICALLS
)
6816 /* ??? but do not want this (or want pic0) if -non-shared? */
6817 fprintf (stream
, "%s\n", ABICALLS_ASM_OP
);
6820 fprintf (stream
, "\t.set\tmips16\n");
6822 /* This code exists so that we can put all externs before all symbol
6823 references. This is necessary for the MIPS assembler's global pointer
6824 optimizations to work. */
6825 if (TARGET_FILE_SWITCHING
)
6827 asm_out_data_file
= stream
;
6828 asm_out_text_file
= tmpfile ();
6831 asm_out_data_file
= asm_out_text_file
= stream
;
6833 if (flag_verbose_asm
)
6834 fprintf (stream
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6836 mips_section_threshold
, mips_arch_info
->name
, mips_isa
);
6839 /* If we are optimizing the global pointer, emit the text section now and any
6840 small externs which did not have .comm, etc that are needed. Also, give a
6841 warning if the data area is more than 32K and -pic because 3 instructions
6842 are needed to reference the data pointers. */
6845 mips_asm_file_end (file
)
6849 struct extern_list
*p
;
6855 for (p
= extern_head
; p
!= 0; p
= p
->next
)
6857 name_tree
= get_identifier (p
->name
);
6859 /* Positively ensure only one .extern for any given symbol. */
6860 if (! TREE_ASM_WRITTEN (name_tree
))
6862 TREE_ASM_WRITTEN (name_tree
) = 1;
6863 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6865 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
6869 fputs ("\t.extern\t", file
);
6870 assemble_name (file
, p
->name
);
6871 fprintf (file
, ", %d\n", p
->size
);
6877 if (TARGET_FILE_SWITCHING
)
6879 fprintf (file
, "\n\t.text\n");
6880 copy_file_data (file
, asm_out_text_file
);
6885 copy_file_data (to
, from
)
6892 fatal_io_error ("can't rewind temp file");
6894 while ((len
= fread (buffer
, 1, sizeof (buffer
), from
)) > 0)
6895 if (fwrite (buffer
, 1, len
, to
) != len
)
6896 fatal_io_error ("can't write to output file");
6899 fatal_io_error ("can't read from temp file");
6902 fatal_io_error ("can't close temp file");
6905 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6906 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6909 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
6912 const char *init_string
;
6913 const char *final_string
;
6916 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
6917 assemble_name (stream
, name
);
6918 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
6922 tree name_tree
= get_identifier (name
);
6923 TREE_ASM_WRITTEN (name_tree
) = 1;
6927 /* Return the bytes needed to compute the frame pointer from the current
6930 Mips stack frames look like:
6932 Before call After call
6933 +-----------------------+ +-----------------------+
6936 | caller's temps. | | caller's temps. |
6938 +-----------------------+ +-----------------------+
6940 | arguments on stack. | | arguments on stack. |
6942 +-----------------------+ +-----------------------+
6943 | 4 words to save | | 4 words to save |
6944 | arguments passed | | arguments passed |
6945 | in registers, even | | in registers, even |
6946 SP->| if not passed. | VFP->| if not passed. |
6947 +-----------------------+ +-----------------------+
6949 | fp register save |
6951 +-----------------------+
6953 | gp register save |
6955 +-----------------------+
6959 +-----------------------+
6961 | alloca allocations |
6963 +-----------------------+
6965 | GP save for V.4 abi |
6967 +-----------------------+
6969 | arguments on stack |
6971 +-----------------------+
6973 | arguments passed |
6974 | in registers, even |
6975 low SP->| if not passed. |
6976 memory +-----------------------+
6981 compute_frame_size (size
)
6982 HOST_WIDE_INT size
; /* # of var. bytes allocated */
6985 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6986 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6987 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6988 HOST_WIDE_INT extra_size
; /* # extra bytes */
6989 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6990 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6991 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6992 long mask
; /* mask of saved gp registers */
6993 long fmask
; /* mask of saved fp registers */
7000 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
7001 var_size
= MIPS_STACK_ALIGN (size
);
7002 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
7004 /* The MIPS 3.0 linker does not like functions that dynamically
7005 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7006 looks like we are trying to create a second frame pointer to the
7007 function, so allocate some stack space to make it happy. */
7009 if (args_size
== 0 && current_function_calls_alloca
)
7010 args_size
= 4 * UNITS_PER_WORD
;
7012 total_size
= var_size
+ args_size
+ extra_size
;
7013 return_type
= DECL_RESULT (current_function_decl
);
7015 /* Calculate space needed for gp registers. */
7016 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
7018 /* $18 is a special case on the mips16. It may be used to call
7019 a function which returns a floating point value, but it is
7020 marked in call_used_regs. $31 is also a special case. When
7021 not using -mentry, it will be used to copy a return value
7022 into the floating point registers if the return value is
7024 if (MUST_SAVE_REGISTER (regno
)
7026 && regno
== GP_REG_FIRST
+ 18
7027 && regs_ever_live
[regno
])
7029 && regno
== GP_REG_FIRST
+ 31
7030 && mips16_hard_float
7032 && ! aggregate_value_p (return_type
)
7033 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
7034 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
))
7036 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
7037 mask
|= 1L << (regno
- GP_REG_FIRST
);
7039 /* The entry and exit pseudo instructions can not save $17
7040 without also saving $16. */
7042 && regno
== GP_REG_FIRST
+ 17
7043 && ! MUST_SAVE_REGISTER (GP_REG_FIRST
+ 16))
7045 gp_reg_size
+= UNITS_PER_WORD
;
7051 /* We need to restore these for the handler. */
7052 if (current_function_calls_eh_return
)
7057 regno
= EH_RETURN_DATA_REGNO (i
);
7058 if (regno
== INVALID_REGNUM
)
7060 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
7061 mask
|= 1L << (regno
- GP_REG_FIRST
);
7065 /* This loop must iterate over the same space as its companion in
7066 save_restore_insns. */
7067 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
7068 regno
>= FP_REG_FIRST
;
7071 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
7073 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
7074 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
7078 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
7079 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
7081 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
7082 for leaf routines (total_size == extra_size) to save the gp reg.
7083 The gp reg is callee saved in the 64 bit ABI, so all routines must
7084 save the gp reg. This is not a leaf routine if -p, because of the
7086 if (total_size
== extra_size
7087 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
|| mips_abi
== ABI_EABI
)
7088 && ! current_function_profile
)
7089 total_size
= extra_size
= 0;
7090 else if (TARGET_ABICALLS
)
7092 /* Add the context-pointer to the saved registers. */
7093 gp_reg_size
+= UNITS_PER_WORD
;
7094 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
7095 total_size
-= gp_reg_rounded
;
7096 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
7097 total_size
+= gp_reg_rounded
;
7100 /* Add in space reserved on the stack by the callee for storing arguments
7101 passed in registers. */
7102 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
7103 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
7105 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
7106 if (mips_entry
&& total_size
> 0 && total_size
< 32)
7109 /* Save other computed information. */
7110 cfun
->machine
->frame
.total_size
= total_size
;
7111 cfun
->machine
->frame
.var_size
= var_size
;
7112 cfun
->machine
->frame
.args_size
= args_size
;
7113 cfun
->machine
->frame
.extra_size
= extra_size
;
7114 cfun
->machine
->frame
.gp_reg_size
= gp_reg_size
;
7115 cfun
->machine
->frame
.fp_reg_size
= fp_reg_size
;
7116 cfun
->machine
->frame
.mask
= mask
;
7117 cfun
->machine
->frame
.fmask
= fmask
;
7118 cfun
->machine
->frame
.initialized
= reload_completed
;
7119 cfun
->machine
->frame
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
7120 cfun
->machine
->frame
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
7124 unsigned long offset
;
7126 /* When using mips_entry, the registers are always saved at the
7127 top of the stack. */
7129 offset
= (args_size
+ extra_size
+ var_size
7130 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
7132 offset
= total_size
- GET_MODE_SIZE (gpr_mode
);
7134 cfun
->machine
->frame
.gp_sp_offset
= offset
;
7135 cfun
->machine
->frame
.gp_save_offset
= offset
- total_size
;
7139 cfun
->machine
->frame
.gp_sp_offset
= 0;
7140 cfun
->machine
->frame
.gp_save_offset
= 0;
7145 unsigned long offset
= (args_size
+ extra_size
+ var_size
7146 + gp_reg_rounded
+ fp_reg_size
7147 - FP_INC
* UNITS_PER_FPREG
);
7148 cfun
->machine
->frame
.fp_sp_offset
= offset
;
7149 cfun
->machine
->frame
.fp_save_offset
= offset
- total_size
;
7153 cfun
->machine
->frame
.fp_sp_offset
= 0;
7154 cfun
->machine
->frame
.fp_save_offset
= 0;
7157 /* Ok, we're done. */
7161 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
7162 pointer, argument pointer, or return address pointer. TO is either
7163 the stack pointer or hard frame pointer. */
7166 mips_initial_elimination_offset (from
, to
)
7171 /* Set OFFSET to the offset from the stack pointer. */
7174 case FRAME_POINTER_REGNUM
:
7178 case ARG_POINTER_REGNUM
:
7179 compute_frame_size (get_frame_size ());
7180 offset
= cfun
->machine
->frame
.total_size
;
7181 if (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
|| mips_abi
== ABI_MEABI
)
7182 offset
-= current_function_pretend_args_size
;
7185 case RETURN_ADDRESS_POINTER_REGNUM
:
7186 compute_frame_size (get_frame_size ());
7187 offset
= cfun
->machine
->frame
.gp_sp_offset
;
7188 if (BYTES_BIG_ENDIAN
)
7189 offset
+= UNITS_PER_WORD
- (POINTER_SIZE
/ BITS_PER_UNIT
);
7196 if (TARGET_MIPS16
&& to
== HARD_FRAME_POINTER_REGNUM
)
7197 offset
-= current_function_outgoing_args_size
;
7202 /* Common code to emit the insns (or to write the instructions to a file)
7203 to save/restore registers.
7205 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
7206 is not modified within save_restore_insns. */
7208 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
7210 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
7211 and return an rtl expression for the register.
7213 This function is a subroutine of save_restore_insns. It is used when
7214 OFFSET is too large to add in a single instruction. */
7217 mips_add_large_offset_to_sp (offset
)
7218 HOST_WIDE_INT offset
;
7220 rtx reg
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
7221 rtx offset_rtx
= GEN_INT (offset
);
7223 emit_move_insn (reg
, offset_rtx
);
7224 if (Pmode
== DImode
)
7225 emit_insn (gen_adddi3 (reg
, reg
, stack_pointer_rtx
));
7227 emit_insn (gen_addsi3 (reg
, reg
, stack_pointer_rtx
));
7231 /* Make INSN frame related and note that it performs the frame-related
7232 operation DWARF_PATTERN. */
7235 mips_annotate_frame_insn (insn
, dwarf_pattern
)
7236 rtx insn
, dwarf_pattern
;
7238 RTX_FRAME_RELATED_P (insn
) = 1;
7239 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7244 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
7245 The expression should only be used to store single registers. */
7248 mips_frame_set (mode
, regno
, offset
)
7249 enum machine_mode mode
;
7253 rtx address
= plus_constant (stack_pointer_rtx
, offset
);
7254 rtx set
= gen_rtx_SET (mode
,
7255 gen_rtx_MEM (mode
, address
),
7256 gen_rtx_REG (mode
, regno
));
7257 RTX_FRAME_RELATED_P (set
) = 1;
7262 /* Emit a move instruction that stores REG in MEM. Make the instruction
7263 frame related and note that it stores REG at (SP + OFFSET). This
7264 function may be asked to store an FPR pair. */
7267 mips_emit_frame_related_store (mem
, reg
, offset
)
7270 HOST_WIDE_INT offset
;
7274 if (GET_MODE (reg
) == DFmode
&& ! TARGET_FLOAT64
)
7276 /* Two registers are being stored, so the frame-related expression
7277 must be a PARALLEL rtx with one SET for each register. The
7278 higher numbered register is stored in the lower address on
7279 big-endian targets. */
7280 int regno1
= TARGET_BIG_ENDIAN
? REGNO (reg
) + 1 : REGNO (reg
);
7281 int regno2
= TARGET_BIG_ENDIAN
? REGNO (reg
) : REGNO (reg
) + 1;
7282 rtx set1
= mips_frame_set (SFmode
, regno1
, offset
);
7283 rtx set2
= mips_frame_set (SFmode
, regno2
, offset
+ UNITS_PER_FPREG
);
7284 dwarf_expr
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set1
, set2
));
7287 dwarf_expr
= mips_frame_set (GET_MODE (reg
), REGNO (reg
), offset
);
7289 mips_annotate_frame_insn (emit_move_insn (mem
, reg
), dwarf_expr
);
7293 save_restore_insns (store_p
, large_reg
, large_offset
)
7294 int store_p
; /* true if this is prologue */
7295 rtx large_reg
; /* register holding large offset constant or NULL */
7296 long large_offset
; /* large constant offset value */
7298 long mask
= cfun
->machine
->frame
.mask
;
7299 long fmask
= cfun
->machine
->frame
.fmask
;
7300 long real_mask
= mask
;
7303 HOST_WIDE_INT base_offset
;
7304 HOST_WIDE_INT gp_offset
;
7305 HOST_WIDE_INT fp_offset
;
7306 HOST_WIDE_INT end_offset
;
7308 if (frame_pointer_needed
7309 && ! BITSET_P (mask
, HARD_FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
7312 /* Do not restore GP under certain conditions. */
7315 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
7316 mask
&= ~(1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
));
7318 if (mask
== 0 && fmask
== 0)
7321 /* Save registers starting from high to low. The debuggers prefer at least
7322 the return register be stored at func+4, and also it allows us not to
7323 need a nop in the epilog if at least one register is reloaded in
7324 addition to return address. */
7326 /* Save GP registers if needed. */
7329 /* Pick which pointer to use as a base register. For small frames, just
7330 use the stack pointer. Otherwise, use a temporary register. Save 2
7331 cycles if the save area is near the end of a large frame, by reusing
7332 the constant created in the prologue/epilogue to adjust the stack
7335 gp_offset
= cfun
->machine
->frame
.gp_sp_offset
;
7337 = gp_offset
- (cfun
->machine
->frame
.gp_reg_size
7338 - GET_MODE_SIZE (gpr_mode
));
7340 if (gp_offset
< 0 || end_offset
< 0)
7342 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
7343 (long) gp_offset
, (long) end_offset
);
7345 /* If we see a large frame in mips16 mode, we save the registers
7346 before adjusting the stack pointer, and load them afterward. */
7347 else if (TARGET_MIPS16
&& large_offset
> 32767)
7348 base_reg_rtx
= stack_pointer_rtx
, base_offset
= large_offset
;
7350 else if (gp_offset
< 32768)
7351 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
7353 else if (large_reg
!= 0
7354 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
7355 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
7357 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
7358 base_offset
= large_offset
;
7359 if (Pmode
== DImode
)
7360 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
7362 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
7366 base_offset
= gp_offset
;
7367 base_reg_rtx
= mips_add_large_offset_to_sp (base_offset
);
7370 /* When we restore the registers in MIPS16 mode, then if we are
7371 using a frame pointer, and this is not a large frame, the
7372 current stack pointer will be offset by
7373 current_function_outgoing_args_size. Doing it this way lets
7374 us avoid offsetting the frame pointer before copying it into
7375 the stack pointer; there is no instruction to set the stack
7376 pointer to the sum of a register and a constant. */
7379 && frame_pointer_needed
7380 && large_offset
<= 32767)
7381 base_offset
+= current_function_outgoing_args_size
;
7383 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
7385 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
7389 = gen_rtx (MEM
, gpr_mode
,
7390 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
7391 GEN_INT (gp_offset
- base_offset
)));
7393 if (! current_function_calls_eh_return
)
7394 RTX_UNCHANGING_P (mem_rtx
) = 1;
7396 /* The mips16 does not have an instruction to load
7397 $31, so we load $7 instead, and work things out
7398 in mips_expand_epilogue. */
7399 if (TARGET_MIPS16
&& ! store_p
&& regno
== GP_REG_FIRST
+ 31)
7400 reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 7);
7401 /* The mips16 sometimes needs to save $18. */
7402 else if (TARGET_MIPS16
7403 && regno
!= GP_REG_FIRST
+ 31
7404 && ! M16_REG_P (regno
))
7407 reg_rtx
= gen_rtx (REG
, gpr_mode
, 6);
7410 reg_rtx
= gen_rtx (REG
, gpr_mode
, 3);
7411 emit_move_insn (reg_rtx
,
7412 gen_rtx (REG
, gpr_mode
, regno
));
7416 reg_rtx
= gen_rtx (REG
, gpr_mode
, regno
);
7419 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, gp_offset
);
7422 emit_move_insn (reg_rtx
, mem_rtx
);
7424 && regno
!= GP_REG_FIRST
+ 31
7425 && ! M16_REG_P (regno
))
7426 emit_move_insn (gen_rtx (REG
, gpr_mode
, regno
),
7430 /* If the restore is being supressed, still take into account
7431 the offset at which it is stored. */
7432 if (BITSET_P (real_mask
, regno
- GP_REG_FIRST
))
7433 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
7437 base_reg_rtx
= 0, base_offset
= 0;
7439 /* Save floating point registers if needed. */
7442 /* Pick which pointer to use as a base register. */
7443 fp_offset
= cfun
->machine
->frame
.fp_sp_offset
;
7444 end_offset
= fp_offset
- (cfun
->machine
->frame
.fp_reg_size
7445 - UNITS_PER_HWFPVALUE
);
7447 if (fp_offset
< 0 || end_offset
< 0)
7449 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
7450 (long) fp_offset
, (long) end_offset
);
7452 else if (fp_offset
< 32768)
7453 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
7455 else if (base_reg_rtx
!= 0
7456 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
7457 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
7458 ; /* already set up for gp registers above */
7460 else if (large_reg
!= 0
7461 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
7462 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
7464 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
7465 base_offset
= large_offset
;
7466 if (Pmode
== DImode
)
7467 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
7469 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
7473 base_offset
= fp_offset
;
7474 base_reg_rtx
= mips_add_large_offset_to_sp (fp_offset
);
7477 /* This loop must iterate over the same space as its companion in
7478 compute_frame_size. */
7479 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
7480 regno
>= FP_REG_FIRST
;
7482 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
7484 enum machine_mode sz
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
7485 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
7486 rtx mem_rtx
= gen_rtx (MEM
, sz
,
7487 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
7490 if (! current_function_calls_eh_return
)
7491 RTX_UNCHANGING_P (mem_rtx
) = 1;
7494 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, fp_offset
);
7496 emit_move_insn (reg_rtx
, mem_rtx
);
7498 fp_offset
-= UNITS_PER_HWFPVALUE
;
7503 /* Set up the stack and frame (if desired) for the function. */
7506 mips_output_function_prologue (file
, size
)
7508 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7510 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7513 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
7515 /* ??? When is this really needed? At least the GNU assembler does not
7516 need the source filename more than once in the file, beyond what is
7517 emitted by the debug information. */
7519 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
7521 #ifdef SDB_DEBUGGING_INFO
7522 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
7523 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
7526 /* In mips16 mode, we may need to generate a 32 bit to handle
7527 floating point arguments. The linker will arrange for any 32 bit
7528 functions to call this stub, which will then jump to the 16 bit
7530 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
7531 && current_function_args_info
.fp_code
!= 0)
7532 build_mips16_function_stub (file
);
7534 inside_function
= 1;
7536 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7537 /* Get the function name the same way that toplev.c does before calling
7538 assemble_start_function. This is needed so that the name used here
7539 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7540 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7542 if (!flag_inhibit_size_directive
)
7544 fputs ("\t.ent\t", file
);
7545 assemble_name (file
, fnname
);
7549 assemble_name (file
, fnname
);
7550 fputs (":\n", file
);
7553 if (!flag_inhibit_size_directive
)
7555 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7557 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7558 (reg_names
[(frame_pointer_needed
)
7559 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
7560 ((frame_pointer_needed
&& TARGET_MIPS16
)
7561 ? ((long) tsize
- current_function_outgoing_args_size
)
7563 reg_names
[GP_REG_FIRST
+ 31],
7564 cfun
->machine
->frame
.var_size
,
7565 cfun
->machine
->frame
.num_gp
,
7566 cfun
->machine
->frame
.num_fp
,
7567 current_function_outgoing_args_size
,
7568 cfun
->machine
->frame
.extra_size
);
7570 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7571 fprintf (file
, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7572 cfun
->machine
->frame
.mask
,
7573 cfun
->machine
->frame
.gp_save_offset
,
7574 cfun
->machine
->frame
.fmask
,
7575 cfun
->machine
->frame
.fp_save_offset
);
7578 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7579 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7582 if (mips_entry
&& ! mips_can_use_return_insn ())
7584 int save16
= BITSET_P (cfun
->machine
->frame
.mask
, 16);
7585 int save17
= BITSET_P (cfun
->machine
->frame
.mask
, 17);
7586 int save31
= BITSET_P (cfun
->machine
->frame
.mask
, 31);
7590 /* Look through the initial insns to see if any of them store
7591 the function parameters into the incoming parameter storage
7592 area. If they do, we delete the insn, and save the register
7593 using the entry pseudo-instruction instead. We don't try to
7594 look past a label, jump, or call. */
7595 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
7597 rtx note
, set
, src
, dest
, base
, offset
;
7600 if (GET_CODE (insn
) == CODE_LABEL
7601 || GET_CODE (insn
) == JUMP_INSN
7602 || GET_CODE (insn
) == CALL_INSN
)
7604 if (GET_CODE (insn
) != INSN
)
7606 set
= PATTERN (insn
);
7607 if (GET_CODE (set
) != SET
)
7610 /* An insn storing a function parameter will still have a
7611 REG_EQUIV note on it mentioning the argument pointer. */
7612 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
7613 if (note
== NULL_RTX
)
7615 if (! reg_mentioned_p (arg_pointer_rtx
, XEXP (note
, 0)))
7618 src
= SET_SRC (set
);
7619 if (GET_CODE (src
) != REG
7620 || REGNO (src
) < GP_REG_FIRST
+ 4
7621 || REGNO (src
) > GP_REG_FIRST
+ 7)
7624 dest
= SET_DEST (set
);
7625 if (GET_CODE (dest
) != MEM
)
7627 if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned) UNITS_PER_WORD
)
7629 else if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned)2 * UNITS_PER_WORD
7630 && REGNO (src
) < GP_REG_FIRST
+ 7)
7634 offset
= const0_rtx
;
7635 base
= eliminate_constant_term (XEXP (dest
, 0), &offset
);
7636 if (GET_CODE (base
) != REG
7637 || GET_CODE (offset
) != CONST_INT
)
7639 if (REGNO (base
) == (unsigned) STACK_POINTER_REGNUM
7640 && INTVAL (offset
) == tsize
+ (REGNO (src
) - 4) * UNITS_PER_WORD
)
7642 else if (REGNO (base
) == (unsigned) HARD_FRAME_POINTER_REGNUM
7645 + (REGNO (src
) - 4) * UNITS_PER_WORD
7646 - current_function_outgoing_args_size
)))
7651 /* This insn stores a parameter onto the stack, in the same
7652 location where the entry pseudo-instruction will put it.
7653 Delete the insn, and arrange to tell the entry
7654 instruction to save the register. */
7655 PUT_CODE (insn
, NOTE
);
7656 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
7657 NOTE_SOURCE_FILE (insn
) = 0;
7659 hireg
= (REGNO (src
)
7660 + HARD_REGNO_NREGS (REGNO (src
), GET_MODE (dest
))
7662 if (hireg
> savearg
)
7666 /* If this is a varargs function, we need to save all the
7667 registers onto the stack anyhow. */
7668 if (current_function_stdarg
)
7669 savearg
= GP_REG_FIRST
+ 7;
7671 fprintf (file
, "\tentry\t");
7674 if (savearg
== GP_REG_FIRST
+ 4)
7675 fprintf (file
, "%s", reg_names
[savearg
]);
7677 fprintf (file
, "%s-%s", reg_names
[GP_REG_FIRST
+ 4],
7678 reg_names
[savearg
]);
7680 if (save16
|| save17
)
7683 fprintf (file
, ",");
7684 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 16]);
7686 fprintf (file
, "-%s", reg_names
[GP_REG_FIRST
+ 17]);
7690 if (savearg
> 0 || save16
|| save17
)
7691 fprintf (file
, ",");
7692 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 31]);
7694 fprintf (file
, "\n");
7697 if (TARGET_ABICALLS
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
7699 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7701 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7702 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
7705 fprintf (file
, "\t%s\t%s,%s,%ld\n",
7706 (Pmode
== DImode
? "dsubu" : "subu"),
7707 sp_str
, sp_str
, (long) tsize
);
7708 fprintf (file
, "\t.cprestore %ld\n", cfun
->machine
->frame
.args_size
);
7711 if (dwarf2out_do_frame ())
7712 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
7716 /* Expand the prologue into a bunch of separate insns. */
7719 mips_expand_prologue ()
7722 HOST_WIDE_INT tsize
;
7724 int last_arg_is_vararg_marker
= 0;
7725 tree fndecl
= current_function_decl
;
7726 tree fntype
= TREE_TYPE (fndecl
);
7727 tree fnargs
= DECL_ARGUMENTS (fndecl
);
7732 CUMULATIVE_ARGS args_so_far
;
7733 rtx reg_18_save
= NULL_RTX
;
7734 int store_args_on_stack
= (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
7735 && (! mips_entry
|| mips_can_use_return_insn ());
7737 /* If struct value address is treated as the first argument, make it so. */
7738 if (aggregate_value_p (DECL_RESULT (fndecl
))
7739 && ! current_function_returns_pcc_struct
7740 && struct_value_incoming_rtx
== 0)
7742 tree type
= build_pointer_type (fntype
);
7743 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
7745 DECL_ARG_TYPE (function_result_decl
) = type
;
7746 TREE_CHAIN (function_result_decl
) = fnargs
;
7747 fnargs
= function_result_decl
;
7750 /* For arguments passed in registers, find the register number
7751 of the first argument in the variable part of the argument list,
7752 otherwise GP_ARG_LAST+1. Note also if the last argument is
7753 the varargs special argument, and treat it as part of the
7756 This is only needed if store_args_on_stack is true. */
7758 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, current_function_decl
);
7759 regno
= GP_ARG_FIRST
;
7761 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
7763 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
7764 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
7767 if (TREE_ADDRESSABLE (passed_type
))
7769 passed_type
= build_pointer_type (passed_type
);
7770 passed_mode
= Pmode
;
7773 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
7775 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
7776 next_arg
= TREE_CHAIN (cur_arg
);
7778 if (entry_parm
&& store_args_on_stack
)
7781 && DECL_NAME (cur_arg
)
7782 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7783 "__builtin_va_alist"))
7784 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7787 last_arg_is_vararg_marker
= 1;
7788 if (GET_CODE (entry_parm
) == REG
)
7789 regno
= REGNO (entry_parm
);
7791 regno
= GP_ARG_LAST
+ 1;
7798 if (GET_CODE (entry_parm
) != REG
)
7801 /* passed in a register, so will get homed automatically */
7802 if (GET_MODE (entry_parm
) == BLKmode
)
7803 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
7805 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
7807 regno
= REGNO (entry_parm
) + words
- 1;
7812 regno
= GP_ARG_LAST
+1;
7817 /* In order to pass small structures by value in registers compatibly with
7818 the MIPS compiler, we need to shift the value into the high part of the
7819 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7820 adjustments to be made as the next_arg_reg variable, so we split up the
7821 insns, and emit them separately. */
7823 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
7824 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
7826 rtvec adjust
= XVEC (next_arg_reg
, 0);
7827 int num
= GET_NUM_ELEM (adjust
);
7829 for (i
= 0; i
< num
; i
++)
7833 pattern
= RTVEC_ELT (adjust
, i
);
7834 if (GET_CODE (pattern
) != SET
7835 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
7836 abort_with_insn (pattern
, "insn is not a shift");
7837 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
7839 insn
= emit_insn (pattern
);
7841 /* Global life information isn't valid at this point, so we
7842 can't check whether these shifts are actually used. Mark
7843 them MAYBE_DEAD so that flow2 will remove them, and not
7844 complain about dead code in the prologue. */
7845 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, NULL_RTX
,
7850 tsize
= compute_frame_size (get_frame_size ());
7852 /* If this function is a varargs function, store any registers that
7853 would normally hold arguments ($4 - $7) on the stack. */
7854 if (store_args_on_stack
7855 && ((TYPE_ARG_TYPES (fntype
) != 0
7856 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
7858 || last_arg_is_vararg_marker
))
7860 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
7861 rtx ptr
= stack_pointer_rtx
;
7863 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7864 if (TARGET_ABICALLS
)
7867 for (; regno
<= GP_ARG_LAST
; regno
++)
7870 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
7871 emit_move_insn (gen_rtx (MEM
, gpr_mode
, ptr
),
7872 gen_rtx (REG
, gpr_mode
, regno
));
7874 offset
+= GET_MODE_SIZE (gpr_mode
);
7878 /* If we are using the entry pseudo instruction, it will
7879 automatically subtract 32 from the stack pointer, so we don't
7880 need to. The entry pseudo instruction is emitted by
7881 function_prologue. */
7882 if (mips_entry
&& ! mips_can_use_return_insn ())
7884 if (tsize
> 0 && tsize
<= 32 && frame_pointer_needed
)
7888 /* If we are using a frame pointer with a small stack frame,
7889 we need to initialize it here since it won't be done
7891 if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7893 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7894 if (Pmode
== DImode
)
7895 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7899 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7903 else if (Pmode
== DImode
)
7904 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7905 stack_pointer_rtx
));
7907 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7908 stack_pointer_rtx
));
7910 RTX_FRAME_RELATED_P (insn
) = 1;
7913 /* We may need to save $18, if it is used to call a function
7914 which may return a floating point value. Set up a sequence
7915 of instructions to do so. Later on we emit them at the right
7917 if (TARGET_MIPS16
&& BITSET_P (cfun
->machine
->frame
.mask
, 18))
7919 rtx reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 3);
7920 long gp_offset
, base_offset
;
7922 gp_offset
= cfun
->machine
->frame
.gp_sp_offset
;
7923 if (BITSET_P (cfun
->machine
->frame
.mask
, 16))
7924 gp_offset
-= UNITS_PER_WORD
;
7925 if (BITSET_P (cfun
->machine
->frame
.mask
, 17))
7926 gp_offset
-= UNITS_PER_WORD
;
7927 if (BITSET_P (cfun
->machine
->frame
.mask
, 31))
7928 gp_offset
-= UNITS_PER_WORD
;
7930 base_offset
= tsize
;
7934 emit_move_insn (reg_rtx
,
7935 gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 18));
7936 emit_move_insn (gen_rtx (MEM
, gpr_mode
,
7937 gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
,
7941 reg_18_save
= get_insns ();
7950 if (reg_18_save
!= NULL_RTX
)
7951 emit_insn (reg_18_save
);
7957 rtx tsize_rtx
= GEN_INT (tsize
);
7959 /* If we are doing svr4-abi, sp move is done by
7960 function_prologue. In mips16 mode with a large frame, we
7961 save the registers before adjusting the stack. */
7962 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7963 && (!TARGET_MIPS16
|| tsize
<= 32767))
7965 rtx adjustment_rtx
, insn
, dwarf_pattern
;
7969 adjustment_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
7970 emit_move_insn (adjustment_rtx
, tsize_rtx
);
7973 adjustment_rtx
= tsize_rtx
;
7975 if (Pmode
== DImode
)
7976 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7979 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7982 dwarf_pattern
= gen_rtx_SET (Pmode
, stack_pointer_rtx
,
7983 plus_constant (stack_pointer_rtx
,
7986 mips_annotate_frame_insn (insn
, dwarf_pattern
);
7990 save_restore_insns (1, tmp_rtx
, tsize
);
7991 else if (reg_18_save
!= NULL_RTX
)
7992 emit_insn (reg_18_save
);
7994 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
8000 if (!frame_pointer_needed
)
8003 reg_rtx
= gen_rtx (REG
, Pmode
, 3);
8004 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8005 emit_move_insn (reg_rtx
, tsize_rtx
);
8006 if (Pmode
== DImode
)
8007 emit_insn (gen_subdi3 (hard_frame_pointer_rtx
,
8008 hard_frame_pointer_rtx
,
8011 emit_insn (gen_subsi3 (hard_frame_pointer_rtx
,
8012 hard_frame_pointer_rtx
,
8014 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8017 if (frame_pointer_needed
)
8021 /* On the mips16, we encourage the use of unextended
8022 instructions when using the frame pointer by pointing the
8023 frame pointer ahead of the argument space allocated on
8025 if ((! TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
8029 /* In this case, we have already copied the stack
8030 pointer into the frame pointer, above. We need only
8031 adjust for the outgoing argument size. */
8032 if (current_function_outgoing_args_size
!= 0)
8034 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
8035 if (Pmode
== DImode
)
8036 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8037 hard_frame_pointer_rtx
,
8040 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
8041 hard_frame_pointer_rtx
,
8045 else if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
8047 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
8048 if (Pmode
== DImode
)
8049 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8053 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
8057 else if (Pmode
== DImode
)
8058 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
8059 stack_pointer_rtx
));
8061 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
8062 stack_pointer_rtx
));
8065 RTX_FRAME_RELATED_P (insn
) = 1;
8068 if (TARGET_ABICALLS
&& (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
8069 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
8070 gen_rtx_REG (DImode
, 25)));
8073 /* If we are profiling, make sure no instructions are scheduled before
8074 the call to mcount. */
8076 if (current_function_profile
)
8077 emit_insn (gen_blockage ());
8080 /* Do any necessary cleanup after a function to restore stack, frame,
8083 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
8084 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
8087 mips_output_function_epilogue (file
, size
)
8088 FILE *file ATTRIBUTE_UNUSED
;
8089 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
8091 const char *fnname
= ""; /* FIXME: Correct initialisation? */
8094 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8095 /* Get the function name the same way that toplev.c does before calling
8096 assemble_start_function. This is needed so that the name used here
8097 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8098 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8100 if (!flag_inhibit_size_directive
)
8102 fputs ("\t.end\t", file
);
8103 assemble_name (file
, fnname
);
8110 int num_gp_regs
= cfun
->machine
->frame
.gp_reg_size
/ 4;
8111 int num_fp_regs
= cfun
->machine
->frame
.fp_reg_size
/ 8;
8112 int num_regs
= num_gp_regs
+ num_fp_regs
;
8113 const char *name
= fnname
;
8118 dslots_load_total
+= num_regs
;
8121 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
8122 name
, frame_pointer_needed
? 'y' : 'n',
8123 (cfun
->machine
->frame
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
8124 current_function_calls_alloca
? 'y' : 'n',
8125 current_function_calls_setjmp
? 'y' : 'n',
8126 cfun
->machine
->frame
.total_size
,
8127 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
8128 dslots_load_total
, dslots_load_filled
,
8129 dslots_jump_total
, dslots_jump_filled
,
8130 num_refs
[0], num_refs
[1], num_refs
[2]);
8132 fputc ('\n', stderr
);
8135 /* Reset state info for each function. */
8136 inside_function
= 0;
8137 ignore_line_number
= 0;
8138 dslots_load_total
= 0;
8139 dslots_jump_total
= 0;
8140 dslots_load_filled
= 0;
8141 dslots_jump_filled
= 0;
8148 while (string_constants
!= NULL
)
8150 struct string_constant
*next
;
8152 next
= string_constants
->next
;
8153 free (string_constants
);
8154 string_constants
= next
;
8157 /* If any following function uses the same strings as this one, force
8158 them to refer those strings indirectly. Nearby functions could
8159 refer them using pc-relative addressing, but it isn't safe in
8160 general. For instance, some functions may be placed in sections
8161 other than .text, and we don't know whether they be close enough
8162 to this one. In large files, even other .text functions can be
8164 for (string
= mips16_strings
; string
!= 0; string
= XEXP (string
, 1))
8165 SYMBOL_REF_FLAG (XEXP (string
, 0)) = 0;
8166 free_EXPR_LIST_list (&mips16_strings
);
8168 /* Restore the output file if optimizing the GP (optimizing the GP causes
8169 the text to be diverted to a tempfile, so that data decls come before
8170 references to the data). */
8171 if (TARGET_FILE_SWITCHING
)
8173 asm_out_file
= asm_out_data_file
;
8178 /* Expand the epilogue into a bunch of separate insns. */
8181 mips_expand_epilogue ()
8183 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
8184 rtx tsize_rtx
= GEN_INT (tsize
);
8185 rtx tmp_rtx
= (rtx
)0;
8187 if (mips_can_use_return_insn ())
8189 emit_jump_insn (gen_return ());
8193 if (mips_entry
&& ! mips_can_use_return_insn ())
8196 if (tsize
> 32767 && ! TARGET_MIPS16
)
8198 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
8199 emit_move_insn (tmp_rtx
, tsize_rtx
);
8200 tsize_rtx
= tmp_rtx
;
8205 long orig_tsize
= tsize
;
8207 if (frame_pointer_needed
)
8209 emit_insn (gen_blockage ());
8211 /* On the mips16, the frame pointer is offset from the stack
8212 pointer by current_function_outgoing_args_size. We
8213 account for that by changing tsize. Note that this can
8214 actually make tsize negative. */
8217 tsize
-= current_function_outgoing_args_size
;
8219 /* If we have a large frame, it's easier to add to $6
8220 than to $sp, since the mips16 has no instruction to
8221 add a register to $sp. */
8222 if (orig_tsize
> 32767)
8224 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
8226 emit_move_insn (g6_rtx
, GEN_INT (tsize
));
8227 if (Pmode
== DImode
)
8228 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8229 hard_frame_pointer_rtx
,
8232 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
8233 hard_frame_pointer_rtx
,
8238 if (tsize
&& tsize
!= orig_tsize
)
8239 tsize_rtx
= GEN_INT (tsize
);
8242 if (Pmode
== DImode
)
8243 emit_insn (gen_movdi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
8245 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
8248 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
8249 are going to restore it, then we must emit a blockage insn to
8250 prevent the scheduler from moving the restore out of the epilogue. */
8251 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
8252 && (cfun
->machine
->frame
.mask
8253 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
8254 emit_insn (gen_blockage ());
8256 save_restore_insns (0, tmp_rtx
, orig_tsize
);
8258 /* In mips16 mode with a large frame, we adjust the stack
8259 pointer before restoring the registers. In this case, we
8260 should always be using a frame pointer, so everything should
8261 have been handled above. */
8262 if (tsize
> 32767 && TARGET_MIPS16
)
8265 if (current_function_calls_eh_return
)
8267 rtx eh_ofs
= EH_RETURN_STACKADJ_RTX
;
8268 if (Pmode
== DImode
)
8269 emit_insn (gen_adddi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
8271 emit_insn (gen_addsi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
8275 emit_insn (gen_blockage ());
8277 if (tsize
!= 0 || current_function_calls_eh_return
)
8281 if (Pmode
== DImode
)
8282 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8285 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8290 /* We need to work around not being able to add a register
8291 to the stack pointer directly. Use register $6 as an
8292 intermediate step. */
8294 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
8296 if (Pmode
== DImode
)
8298 emit_insn (gen_movdi (g6_rtx
, stack_pointer_rtx
));
8299 emit_insn (gen_adddi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
8300 emit_insn (gen_movdi (stack_pointer_rtx
, g6_rtx
));
8304 emit_insn (gen_movsi (g6_rtx
, stack_pointer_rtx
));
8305 emit_insn (gen_addsi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
8306 emit_insn (gen_movsi (stack_pointer_rtx
, g6_rtx
));
8313 /* The mips16 loads the return address into $7, not $31. */
8314 if (TARGET_MIPS16
&& (cfun
->machine
->frame
.mask
& RA_MASK
) != 0)
8315 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
8316 GP_REG_FIRST
+ 7)));
8318 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
8319 GP_REG_FIRST
+ 31)));
8322 /* Return nonzero if this function is known to have a null epilogue.
8323 This allows the optimizer to omit jumps to jumps if no stack
8327 mips_can_use_return_insn ()
8331 if (! reload_completed
)
8334 if (regs_ever_live
[31] || current_function_profile
)
8337 return_type
= DECL_RESULT (current_function_decl
);
8339 /* In mips16 mode, a function which returns a floating point value
8340 needs to arrange to copy the return value into the floating point
8343 && mips16_hard_float
8344 && ! aggregate_value_p (return_type
)
8345 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
8346 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
8349 if (cfun
->machine
->frame
.initialized
)
8350 return cfun
->machine
->frame
.total_size
== 0;
8352 return compute_frame_size (get_frame_size ()) == 0;
8355 /* Returns nonzero if X contains a SYMBOL_REF. */
8358 symbolic_expression_p (x
)
8361 if (GET_CODE (x
) == SYMBOL_REF
)
8364 if (GET_CODE (x
) == CONST
)
8365 return symbolic_expression_p (XEXP (x
, 0));
8367 if (GET_RTX_CLASS (GET_CODE (x
)) == '1')
8368 return symbolic_expression_p (XEXP (x
, 0));
8370 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
8371 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
8372 return (symbolic_expression_p (XEXP (x
, 0))
8373 || symbolic_expression_p (XEXP (x
, 1)));
8378 /* Choose the section to use for the constant rtx expression X that has
8382 mips_select_rtx_section (mode
, x
, align
)
8383 enum machine_mode mode
;
8385 unsigned HOST_WIDE_INT align
;
8389 /* In mips16 mode, the constant table always goes in the same section
8390 as the function, so that constants can be loaded using PC relative
8392 function_section (current_function_decl
);
8394 else if (TARGET_EMBEDDED_DATA
)
8396 /* For embedded applications, always put constants in read-only data,
8397 in order to reduce RAM usage. */
8398 mergeable_constant_section (mode
, align
, 0);
8402 /* For hosted applications, always put constants in small data if
8403 possible, as this gives the best performance. */
8404 /* ??? Consider using mergable small data sections. */
8406 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
8407 && mips_section_threshold
> 0)
8408 SMALL_DATA_SECTION ();
8409 else if (flag_pic
&& symbolic_expression_p (x
))
8411 if (targetm
.have_named_sections
)
8412 named_section (NULL_TREE
, ".data.rel.ro", 3);
8417 mergeable_constant_section (mode
, align
, 0);
8421 /* Choose the section to use for DECL. RELOC is true if its value contains
8422 any relocatable expression.
8424 Some of the logic used here needs to be replicated in
8425 mips_encode_section_info so that references to these symbols are
8426 done correctly. Specifically, at least all symbols assigned here
8427 to rom (.text and/or .rodata) must not be referenced via
8428 mips_encode_section_info with %gprel, as the rom might be too far
8431 If you need to make a change here, you probably should check
8432 mips_encode_section_info to see if it needs a similar change.
8434 ??? This would be fixed by implementing targetm.is_small_data_p. */
8437 mips_select_section (decl
, reloc
, align
)
8440 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
;
8442 int size
= int_size_in_bytes (TREE_TYPE (decl
));
8444 if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
8445 && TREE_CODE (decl
) == STRING_CST
8446 && !flag_writable_strings
)
8447 /* For embedded position independent code, put constant strings in the
8448 text section, because the data section is limited to 64K in size.
8449 For mips16 code, put strings in the text section so that a PC
8450 relative load instruction can be used to get their address. */
8452 else if (TARGET_EMBEDDED_DATA
)
8454 /* For embedded applications, always put an object in read-only data
8455 if possible, in order to reduce RAM usage. */
8457 if (((TREE_CODE (decl
) == VAR_DECL
8458 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
8459 && DECL_INITIAL (decl
)
8460 && (DECL_INITIAL (decl
) == error_mark_node
8461 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8462 /* Deal with calls from output_constant_def_contents. */
8463 || (TREE_CODE (decl
) != VAR_DECL
8464 && (TREE_CODE (decl
) != STRING_CST
8465 || !flag_writable_strings
)))
8466 && ! (flag_pic
&& reloc
))
8467 readonly_data_section ();
8468 else if (size
> 0 && size
<= mips_section_threshold
)
8469 SMALL_DATA_SECTION ();
8475 /* For hosted applications, always put an object in small data if
8476 possible, as this gives the best performance. */
8478 if (size
> 0 && size
<= mips_section_threshold
)
8479 SMALL_DATA_SECTION ();
8480 else if (((TREE_CODE (decl
) == VAR_DECL
8481 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
8482 && DECL_INITIAL (decl
)
8483 && (DECL_INITIAL (decl
) == error_mark_node
8484 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8485 /* Deal with calls from output_constant_def_contents. */
8486 || (TREE_CODE (decl
) != VAR_DECL
8487 && (TREE_CODE (decl
) != STRING_CST
8488 || !flag_writable_strings
)))
8489 && ! (flag_pic
&& reloc
))
8490 readonly_data_section ();
8496 /* When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
8499 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
8500 symbols which are not in the .text section.
8502 When generating mips16 code, SYMBOL_REF_FLAG is set for string
8503 constants which are put in the .text section. We also record the
8504 total length of all such strings; this total is used to decide
8505 whether we need to split the constant table, and need not be
8508 When not mips16 code nor embedded PIC, if a symbol is in a
8509 gp addressable section, SYMBOL_REF_FLAG is set prevent gcc from
8510 splitting the reference so that gas can generate a gp relative
8513 When TARGET_EMBEDDED_DATA is set, we assume that all const
8514 variables will be stored in ROM, which is too far from %gp to use
8515 %gprel addressing. Note that (1) we include "extern const"
8516 variables in this, which mips_select_section doesn't, and (2) we
8517 can't always tell if they're really const (they might be const C++
8518 objects with non-const constructors), so we err on the side of
8519 caution and won't use %gprel anyway (otherwise we'd have to defer
8520 this decision to the linker/loader). The handling of extern consts
8521 is why the DECL_INITIAL macros differ from mips_select_section. */
8524 mips_encode_section_info (decl
, rtl
, first
)
8531 if (first
&& TREE_CODE (decl
) == STRING_CST
8532 && ! flag_writable_strings
8533 /* If this string is from a function, and the function will
8534 go in a gnu linkonce section, then we can't directly
8535 access the string. This gets an assembler error
8536 "unsupported PC relative reference to different section".
8537 If we modify SELECT_SECTION to put it in function_section
8538 instead of text_section, it still fails because
8539 DECL_SECTION_NAME isn't set until assemble_start_function.
8540 If we fix that, it still fails because strings are shared
8541 among multiple functions, and we have cross section
8542 references again. We force it to work by putting string
8543 addresses in the constant pool and indirecting. */
8544 && (! current_function_decl
8545 || ! DECL_ONE_ONLY (current_function_decl
)))
8549 symref
= XEXP (rtl
, 0);
8550 mips16_strings
= alloc_EXPR_LIST (0, symref
, mips16_strings
);
8551 SYMBOL_REF_FLAG (symref
) = 1;
8552 mips_string_length
+= TREE_STRING_LENGTH (decl
);
8556 if (TARGET_EMBEDDED_DATA
8557 && (TREE_CODE (decl
) == VAR_DECL
8558 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
))
8559 && (!DECL_INITIAL (decl
)
8560 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8562 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 0;
8565 else if (TARGET_EMBEDDED_PIC
)
8567 if (TREE_CODE (decl
) == VAR_DECL
)
8568 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8569 else if (TREE_CODE (decl
) == FUNCTION_DECL
)
8570 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 0;
8571 else if (TREE_CODE (decl
) == STRING_CST
8572 && ! flag_writable_strings
)
8573 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 0;
8575 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8578 else if (TREE_CODE (decl
) == VAR_DECL
8579 && DECL_SECTION_NAME (decl
) != NULL_TREE
8580 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
8582 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
8585 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8588 /* We can not perform GP optimizations on variables which are in
8589 specific sections, except for .sdata and .sbss which are
8591 else if (TARGET_GP_OPT
&& TREE_CODE (decl
) == VAR_DECL
8592 && DECL_SECTION_NAME (decl
) == NULL_TREE
8593 && ! (TARGET_MIPS16
&& TREE_PUBLIC (decl
)
8594 && (DECL_COMMON (decl
)
8595 || DECL_ONE_ONLY (decl
)
8596 || DECL_WEAK (decl
))))
8598 int size
= int_size_in_bytes (TREE_TYPE (decl
));
8600 if (size
> 0 && size
<= mips_section_threshold
)
8601 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8606 /* Return register to use for a function return value with VALTYPE for
8607 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8610 mips_function_value (valtype
, func
, mode
)
8612 tree func ATTRIBUTE_UNUSED
;
8613 enum machine_mode mode
;
8615 int reg
= GP_RETURN
;
8616 enum mode_class mclass
;
8621 mode
= TYPE_MODE (valtype
);
8622 unsignedp
= TREE_UNSIGNED (valtype
);
8624 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8625 the mode just as PROMOTE_MODE does. */
8626 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
8628 mclass
= GET_MODE_CLASS (mode
);
8630 if (mclass
== MODE_FLOAT
&& GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
8633 else if (mclass
== MODE_FLOAT
&& mode
== TFmode
)
8634 /* long doubles are really split between f0 and f2, not f1. Eek.
8635 Use DImode for each component, since GCC wants integer modes
8637 return gen_rtx_PARALLEL
8640 gen_rtx_EXPR_LIST (VOIDmode
,
8641 gen_rtx_REG (DImode
, FP_RETURN
),
8643 gen_rtx_EXPR_LIST (VOIDmode
,
8644 gen_rtx_REG (DImode
, FP_RETURN
+ 2),
8645 GEN_INT (GET_MODE_SIZE (mode
) / 2))));
8648 else if (mclass
== MODE_COMPLEX_FLOAT
8649 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)
8651 enum machine_mode cmode
= GET_MODE_INNER (mode
);
8653 return gen_rtx_PARALLEL
8656 gen_rtx_EXPR_LIST (VOIDmode
,
8657 gen_rtx_REG (cmode
, FP_RETURN
),
8659 gen_rtx_EXPR_LIST (VOIDmode
,
8660 gen_rtx_REG (cmode
, FP_RETURN
+ FP_INC
),
8661 GEN_INT (GET_MODE_SIZE (cmode
)))));
8664 else if (valtype
&& TREE_CODE (valtype
) == RECORD_TYPE
8665 && mips_abi
!= ABI_32
8666 && mips_abi
!= ABI_O64
8667 && mips_abi
!= ABI_EABI
)
8669 /* A struct with only one or two floating point fields is returned in
8670 the floating point registers. */
8671 tree field
, fields
[2];
8674 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
8675 field
= TREE_CHAIN (field
))
8677 if (TREE_CODE (field
) != FIELD_DECL
)
8680 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
8683 fields
[i
++] = field
;
8686 /* Must check i, so that we reject structures with no elements. */
8691 /* The structure has DImode, but we don't allow DImode values
8692 in FP registers, so we use a PARALLEL even though it isn't
8693 strictly necessary. */
8694 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
8696 return gen_rtx_PARALLEL
8699 gen_rtx_EXPR_LIST (VOIDmode
,
8700 gen_rtx_REG (field_mode
,
8707 enum machine_mode first_mode
8708 = TYPE_MODE (TREE_TYPE (fields
[0]));
8709 enum machine_mode second_mode
8710 = TYPE_MODE (TREE_TYPE (fields
[1]));
8711 HOST_WIDE_INT first_offset
= int_byte_position (fields
[0]);
8712 HOST_WIDE_INT second_offset
= int_byte_position (fields
[1]);
8714 return gen_rtx_PARALLEL
8717 gen_rtx_EXPR_LIST (VOIDmode
,
8718 gen_rtx_REG (first_mode
,
8720 GEN_INT (first_offset
)),
8721 gen_rtx_EXPR_LIST (VOIDmode
,
8722 gen_rtx_REG (second_mode
,
8724 GEN_INT (second_offset
))));
8729 return gen_rtx_REG (mode
, reg
);
8732 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8733 nonzero when an argument must be passed by reference. */
8736 function_arg_pass_by_reference (cum
, mode
, type
, named
)
8737 const CUMULATIVE_ARGS
*cum
;
8738 enum machine_mode mode
;
8740 int named ATTRIBUTE_UNUSED
;
8744 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
8747 /* We must pass by reference if we would be both passing in registers
8748 and the stack. This is because any subsequent partial arg would be
8749 handled incorrectly in this case.
8751 ??? This is really a kludge. We should either fix GCC so that such
8752 a situation causes an abort and then do something in the MIPS port
8753 to prevent it, or add code to function.c to properly handle the case. */
8754 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8755 here hopefully is not relevant to mips_va_arg. */
8756 if (cum
&& MUST_PASS_IN_STACK (mode
, type
)
8757 && mips_abi
!= ABI_MEABI
8758 && FUNCTION_ARG (*cum
, mode
, type
, named
) != 0)
8761 /* Otherwise, we only do this if EABI is selected. */
8762 if (mips_abi
!= ABI_EABI
)
8765 /* ??? How should SCmode be handled? */
8766 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
8769 size
= int_size_in_bytes (type
);
8770 return size
== -1 || size
> UNITS_PER_WORD
;
8773 /* Return the class of registers for which a mode change from FROM to TO
8776 In little-endian mode, the hi-lo registers are numbered backwards,
8777 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
8780 Similarly, when using paired floating-point registers, the first
8781 register holds the low word, regardless of endianness. So in big
8782 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
8785 Also, loading a 32-bit value into a 64-bit floating-point register
8786 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8787 We can't allow 64-bit float registers to change from a 32-bit
8788 mode to a 64-bit mode. */
8791 mips_cannot_change_mode_class (from
, to
, class)
8792 enum machine_mode from
, to
;
8793 enum reg_class
class;
8795 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
8797 if (TARGET_BIG_ENDIAN
)
8798 return reg_classes_intersect_p (FP_REGS
, class);
8800 return reg_classes_intersect_p (HI_AND_FP_REGS
, class);
8801 return reg_classes_intersect_p (HI_REG
, class);
8806 /* This function returns the register class required for a secondary
8807 register when copying between one of the registers in CLASS, and X,
8808 using MODE. If IN_P is nonzero, the copy is going from X to the
8809 register, otherwise the register is the source. A return value of
8810 NO_REGS means that no secondary register is required. */
8813 mips_secondary_reload_class (class, mode
, x
, in_p
)
8814 enum reg_class
class;
8815 enum machine_mode mode
;
8819 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
8823 if (GET_CODE (x
) == SIGN_EXTEND
)
8829 /* We may be called with reg_renumber NULL from regclass.
8830 ??? This is probably a bug. */
8832 regno
= true_regnum (x
);
8835 while (GET_CODE (x
) == SUBREG
)
8837 off
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
8838 GET_MODE (SUBREG_REG (x
)),
8844 if (GET_CODE (x
) == REG
)
8845 regno
= REGNO (x
) + off
;
8848 /* 64-bit floating-point registers don't store 32-bit values
8849 in sign-extended form. The only way we can reload
8850 (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
8851 an integer register using a 32-bit move. */
8852 if (FP_REG_P (regno
))
8853 return (class == GR_REGS
? NO_REGS
: GR_REGS
);
8855 /* For the same reason, we can only reload (sign_extend:DI FOO) into
8856 a floating-point register when FOO is an integer register. */
8857 if (class == FP_REGS
)
8858 return (GP_REG_P (regno
) ? NO_REGS
: GR_REGS
);
8861 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
8862 regno
= true_regnum (x
);
8864 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
8866 /* We always require a general register when copying anything to
8867 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8868 to a general register, or when copying from register 0. */
8869 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
8872 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8873 ? NO_REGS
: gr_regs
);
8874 else if (regno
== HILO_REGNUM
)
8877 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8878 ? NO_REGS
: gr_regs
);
8880 /* Copying from HI or LO to anywhere other than a general register
8881 requires a general register. */
8882 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
8884 if (TARGET_MIPS16
&& in_p
)
8886 /* We can't really copy to HI or LO at all in mips16 mode. */
8889 return gp_reg_p
? NO_REGS
: gr_regs
;
8891 if (MD_REG_P (regno
))
8893 if (TARGET_MIPS16
&& ! in_p
)
8895 /* We can't really copy to HI or LO at all in mips16 mode. */
8898 return class == gr_regs
? NO_REGS
: gr_regs
;
8901 /* We can only copy a value to a condition code register from a
8902 floating point register, and even then we require a scratch
8903 floating point register. We can only copy a value out of a
8904 condition code register into a general register. */
8905 if (class == ST_REGS
)
8909 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8911 if (ST_REG_P (regno
))
8915 return class == GR_REGS
? NO_REGS
: GR_REGS
;
8918 if (class == FP_REGS
)
8920 if (GET_CODE (x
) == MEM
)
8922 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8925 else if (CONSTANT_P (x
) && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
8927 /* We can use the l.s and l.d macros to load floating-point
8928 constants. ??? For l.s, we could probably get better
8929 code by returning GR_REGS here. */
8932 else if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
8934 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8937 else if (FP_REG_P (regno
))
8939 /* In this case we can use mov.s or mov.d. */
8944 /* Otherwise, we need to reload through an integer register. */
8949 /* In mips16 mode, going between memory and anything but M16_REGS
8950 requires an M16_REG. */
8953 if (class != M16_REGS
&& class != M16_NA_REGS
)
8961 /* The stack pointer isn't a valid operand to an add instruction,
8962 so we need to load it into M16_REGS first. This can happen as
8963 a result of register elimination and form_sum converting
8964 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8965 need an extra register if the dest is the same as the other
8966 register. In that case, we can't fix the problem by loading SP
8967 into the dest first. */
8968 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == REG
8969 && GET_CODE (XEXP (x
, 1)) == REG
8970 && (XEXP (x
, 0) == stack_pointer_rtx
8971 || XEXP (x
, 1) == stack_pointer_rtx
))
8972 return (class == M16_REGS
? M16_NA_REGS
: M16_REGS
);
8974 if (class == M16_REGS
|| class == M16_NA_REGS
)
8983 /* This function returns the maximum number of consecutive registers
8984 needed to represent mode MODE in registers of class CLASS. */
8987 mips_class_max_nregs (class, mode
)
8988 enum reg_class
class;
8989 enum machine_mode mode
;
8991 if (class == FP_REGS
)
8994 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8998 mips_valid_pointer_mode (mode
)
8999 enum machine_mode mode
;
9001 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9005 /* For each mips16 function which refers to GP relative symbols, we
9006 use a pseudo register, initialized at the start of the function, to
9007 hold the $gp value. */
9010 mips16_gp_pseudo_reg ()
9012 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
9017 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
9018 RTX_UNCHANGING_P (cfun
->machine
->mips16_gp_pseudo_rtx
) = 1;
9020 /* We want to initialize this to a value which gcc will believe
9022 const_gp
= gen_rtx (CONST
, Pmode
,
9023 gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 28));
9026 emit_move_insn (cfun
->machine
->mips16_gp_pseudo_rtx
,
9028 insn
= get_insns ();
9031 push_topmost_sequence ();
9032 /* We need to emit the initialization after the FUNCTION_BEG
9033 note, so that it will be integrated. */
9034 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
9035 if (GET_CODE (scan
) == NOTE
9036 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
9038 if (scan
== NULL_RTX
)
9039 scan
= get_insns ();
9040 insn
= emit_insn_after (insn
, scan
);
9041 pop_topmost_sequence ();
9044 return cfun
->machine
->mips16_gp_pseudo_rtx
;
9047 /* Return an RTX which represents the signed 16 bit offset from the
9048 $gp register for the given symbol. This is only used on the
9052 mips16_gp_offset (sym
)
9057 if (GET_CODE (sym
) != SYMBOL_REF
9058 || ! SYMBOL_REF_FLAG (sym
))
9061 /* We use a special identifier to represent the value of the gp
9063 gp
= get_identifier ("__mips16_gp_value");
9065 return gen_rtx (CONST
, Pmode
,
9066 gen_rtx (MINUS
, Pmode
, sym
,
9067 gen_rtx (SYMBOL_REF
, Pmode
,
9068 IDENTIFIER_POINTER (gp
))));
9071 /* Return nonzero if the given RTX represents a signed 16 bit offset
9072 from the $gp register. */
9075 mips16_gp_offset_p (x
)
9078 if (GET_CODE (x
) == CONST
)
9081 /* It's OK to add a small integer value to a gp offset. */
9082 if (GET_CODE (x
) == PLUS
)
9084 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
9085 && SMALL_INT (XEXP (x
, 1)))
9086 return mips16_gp_offset_p (XEXP (x
, 0));
9087 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
9088 && SMALL_INT (XEXP (x
, 0)))
9089 return mips16_gp_offset_p (XEXP (x
, 1));
9093 /* Make sure it is in the form SYM - __mips16_gp_value. */
9094 return (GET_CODE (x
) == MINUS
9095 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
9096 && SYMBOL_REF_FLAG (XEXP (x
, 0))
9097 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
9098 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0);
9101 /* Output a GP offset. We don't want to print the subtraction of
9102 __mips16_gp_value; it is implicitly represented by the %gprel which
9103 should have been printed by the caller. */
9106 mips16_output_gp_offset (file
, x
)
9110 if (GET_CODE (x
) == CONST
)
9113 if (GET_CODE (x
) == PLUS
)
9115 mips16_output_gp_offset (file
, XEXP (x
, 0));
9117 mips16_output_gp_offset (file
, XEXP (x
, 1));
9121 if (GET_CODE (x
) == MINUS
9122 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
9123 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0)
9125 mips16_output_gp_offset (file
, XEXP (x
, 0));
9129 output_addr_const (file
, x
);
9132 /* Validate a constant for the mips16. This rejects general symbolic
9133 addresses, which must be loaded from memory. If ADDR is nonzero,
9134 this should reject anything which is not a legal address. If
9135 ADDEND is nonzero, this is being added to something else. */
9138 mips16_constant (x
, mode
, addr
, addend
)
9140 enum machine_mode mode
;
9144 while (GET_CODE (x
) == CONST
)
9147 switch (GET_CODE (x
))
9153 return (mips16_constant (XEXP (x
, 0), mode
, addr
, 1)
9154 && mips16_constant (XEXP (x
, 1), mode
, addr
, 1));
9157 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
9159 if (CONSTANT_POOL_ADDRESS_P (x
))
9162 /* If we aren't looking for a memory address, we can accept a GP
9163 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
9164 knows how to handle this. We can always accept a string
9165 constant, which is the other case in which SYMBOL_REF_FLAG
9169 && SYMBOL_REF_FLAG (x
)
9170 && mode
== (enum machine_mode
) Pmode
)
9173 /* We can accept a string constant, which will have
9174 SYMBOL_REF_FLAG set but must be recognized by name to
9175 distinguish from a GP accessible symbol. The name of a
9176 string constant will have been generated by
9177 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
9178 if (SYMBOL_REF_FLAG (x
))
9180 const char *name
= XSTR (x
, 0);
9182 return (name
[0] == '*'
9183 && strncmp (name
+ 1, LOCAL_LABEL_PREFIX
,
9184 sizeof LOCAL_LABEL_PREFIX
- 1) == 0);
9190 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
9195 if (addr
&& ! addend
)
9197 return INTVAL (x
) > - 0x10000 && INTVAL (x
) <= 0xffff;
9200 /* We need to treat $gp as a legitimate constant, because
9201 mips16_gp_pseudo_reg assumes that. */
9202 return REGNO (x
) == GP_REG_FIRST
+ 28;
9206 /* Write out code to move floating point arguments in or out of
9207 general registers. Output the instructions to FILE. FP_CODE is
9208 the code describing which arguments are present (see the comment at
9209 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
9210 we are copying from the floating point registers. */
9213 mips16_fp_args (file
, fp_code
, from_fp_p
)
9222 /* This code only works for the original 32 bit ABI and the O64 ABI. */
9223 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
9230 gparg
= GP_ARG_FIRST
;
9231 fparg
= FP_ARG_FIRST
;
9232 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
9236 if ((fparg
& 1) != 0)
9238 fprintf (file
, "\t%s\t%s,%s\n", s
,
9239 reg_names
[gparg
], reg_names
[fparg
]);
9241 else if ((f
& 3) == 2)
9244 fprintf (file
, "\td%s\t%s,%s\n", s
,
9245 reg_names
[gparg
], reg_names
[fparg
]);
9248 if ((fparg
& 1) != 0)
9250 if (TARGET_BIG_ENDIAN
)
9251 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
9252 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
9253 reg_names
[gparg
+ 1], reg_names
[fparg
]);
9255 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
9256 reg_names
[gparg
], reg_names
[fparg
], s
,
9257 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
9270 /* Build a mips16 function stub. This is used for functions which
9271 take aruments in the floating point registers. It is 32 bit code
9272 that moves the floating point args into the general registers, and
9273 then jumps to the 16 bit code. */
9276 build_mips16_function_stub (file
)
9280 char *secname
, *stubname
;
9281 tree stubid
, stubdecl
;
9285 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9286 secname
= (char *) alloca (strlen (fnname
) + 20);
9287 sprintf (secname
, ".mips16.fn.%s", fnname
);
9288 stubname
= (char *) alloca (strlen (fnname
) + 20);
9289 sprintf (stubname
, "__fn_stub_%s", fnname
);
9290 stubid
= get_identifier (stubname
);
9291 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
9292 build_function_type (void_type_node
, NULL_TREE
));
9293 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
9295 fprintf (file
, "\t# Stub function for %s (", current_function_name
);
9297 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
9299 fprintf (file
, "%s%s",
9300 need_comma
? ", " : "",
9301 (f
& 3) == 1 ? "float" : "double");
9304 fprintf (file
, ")\n");
9306 fprintf (file
, "\t.set\tnomips16\n");
9307 function_section (stubdecl
);
9308 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
9310 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
9311 within a .ent, and we can not emit another .ent. */
9312 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9313 fputs ("\t.ent\t", file
);
9314 assemble_name (file
, stubname
);
9318 assemble_name (file
, stubname
);
9319 fputs (":\n", file
);
9321 /* We don't want the assembler to insert any nops here. */
9322 fprintf (file
, "\t.set\tnoreorder\n");
9324 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
9326 fprintf (asm_out_file
, "\t.set\tnoat\n");
9327 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
9328 assemble_name (file
, fnname
);
9329 fprintf (file
, "\n");
9330 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
9331 fprintf (asm_out_file
, "\t.set\tat\n");
9333 /* Unfortunately, we can't fill the jump delay slot. We can't fill
9334 with one of the mfc1 instructions, because the result is not
9335 available for one instruction, so if the very first instruction
9336 in the function refers to the register, it will see the wrong
9338 fprintf (file
, "\tnop\n");
9340 fprintf (file
, "\t.set\treorder\n");
9342 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9343 fputs ("\t.end\t", file
);
9344 assemble_name (file
, stubname
);
9348 fprintf (file
, "\t.set\tmips16\n");
9350 function_section (current_function_decl
);
9353 /* We keep a list of functions for which we have already built stubs
9354 in build_mips16_call_stub. */
9358 struct mips16_stub
*next
;
9363 static struct mips16_stub
*mips16_stubs
;
9365 /* Build a call stub for a mips16 call. A stub is needed if we are
9366 passing any floating point values which should go into the floating
9367 point registers. If we are, and the call turns out to be to a 32
9368 bit function, the stub will be used to move the values into the
9369 floating point registers before calling the 32 bit function. The
9370 linker will magically adjust the function call to either the 16 bit
9371 function or the 32 bit stub, depending upon where the function call
9372 is actually defined.
9374 Similarly, we need a stub if the return value might come back in a
9375 floating point register.
9377 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
9378 (RETVAL is NULL if this is call rather than call_value). FP_CODE
9379 is the code built by function_arg. This function returns a nonzero
9380 value if it builds the call instruction itself. */
9383 build_mips16_call_stub (retval
, fnmem
, arg_size
, fp_code
)
9392 char *secname
, *stubname
;
9393 struct mips16_stub
*l
;
9394 tree stubid
, stubdecl
;
9398 /* We don't need to do anything if we aren't in mips16 mode, or if
9399 we were invoked with the -msoft-float option. */
9400 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
9403 /* Figure out whether the value might come back in a floating point
9405 fpret
= (retval
!= 0
9406 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
9407 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
9409 /* We don't need to do anything if there were no floating point
9410 arguments and the value will not be returned in a floating point
9412 if (fp_code
== 0 && ! fpret
)
9415 if (GET_CODE (fnmem
) != MEM
)
9417 fn
= XEXP (fnmem
, 0);
9419 /* We don't need to do anything if this is a call to a special
9420 mips16 support function. */
9421 if (GET_CODE (fn
) == SYMBOL_REF
9422 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
9425 /* This code will only work for o32 and o64 abis. The other ABI's
9426 require more sophisticated support. */
9427 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
9430 /* We can only handle SFmode and DFmode floating point return
9432 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
9435 /* If we're calling via a function pointer, then we must always call
9436 via a stub. There are magic stubs provided in libgcc.a for each
9437 of the required cases. Each of them expects the function address
9438 to arrive in register $2. */
9440 if (GET_CODE (fn
) != SYMBOL_REF
)
9444 rtx stub_fn
, stub_mem
, insn
;
9446 /* ??? If this code is modified to support other ABI's, we need
9447 to handle PARALLEL return values here. */
9449 sprintf (buf
, "__mips16_call_stub_%s%d",
9451 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
9454 id
= get_identifier (buf
);
9455 stub_fn
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (id
));
9456 stub_mem
= gen_rtx (MEM
, Pmode
, stub_fn
);
9458 emit_move_insn (gen_rtx (REG
, Pmode
, 2), fn
);
9460 if (retval
== NULL_RTX
)
9461 insn
= gen_call_internal0 (stub_mem
, arg_size
,
9462 gen_rtx (REG
, SImode
,
9463 GP_REG_FIRST
+ 31));
9465 insn
= gen_call_value_internal0 (retval
, stub_mem
, arg_size
,
9466 gen_rtx (REG
, SImode
,
9467 GP_REG_FIRST
+ 31));
9468 insn
= emit_call_insn (insn
);
9470 /* Put the register usage information on the CALL. */
9471 if (GET_CODE (insn
) != CALL_INSN
)
9473 CALL_INSN_FUNCTION_USAGE (insn
) =
9474 gen_rtx (EXPR_LIST
, VOIDmode
,
9475 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, Pmode
, 2)),
9476 CALL_INSN_FUNCTION_USAGE (insn
));
9478 /* If we are handling a floating point return value, we need to
9479 save $18 in the function prologue. Putting a note on the
9480 call will mean that regs_ever_live[$18] will be true if the
9481 call is not eliminated, and we can check that in the prologue
9484 CALL_INSN_FUNCTION_USAGE (insn
) =
9485 gen_rtx (EXPR_LIST
, VOIDmode
,
9486 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
9487 CALL_INSN_FUNCTION_USAGE (insn
));
9489 /* Return 1 to tell the caller that we've generated the call
9494 /* We know the function we are going to call. If we have already
9495 built a stub, we don't need to do anything further. */
9497 fnname
= XSTR (fn
, 0);
9498 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
9499 if (strcmp (l
->name
, fnname
) == 0)
9504 /* Build a special purpose stub. When the linker sees a
9505 function call in mips16 code, it will check where the target
9506 is defined. If the target is a 32 bit call, the linker will
9507 search for the section defined here. It can tell which
9508 symbol this section is associated with by looking at the
9509 relocation information (the name is unreliable, since this
9510 might be a static function). If such a section is found, the
9511 linker will redirect the call to the start of the magic
9514 If the function does not return a floating point value, the
9515 special stub section is named
9518 If the function does return a floating point value, the stub
9520 .mips16.call.fp.FNNAME
9523 secname
= (char *) alloca (strlen (fnname
) + 40);
9524 sprintf (secname
, ".mips16.call.%s%s",
9527 stubname
= (char *) alloca (strlen (fnname
) + 20);
9528 sprintf (stubname
, "__call_stub_%s%s",
9531 stubid
= get_identifier (stubname
);
9532 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
9533 build_function_type (void_type_node
, NULL_TREE
));
9534 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
9536 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
9538 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
9542 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
9544 fprintf (asm_out_file
, "%s%s",
9545 need_comma
? ", " : "",
9546 (f
& 3) == 1 ? "float" : "double");
9549 fprintf (asm_out_file
, ")\n");
9551 fprintf (asm_out_file
, "\t.set\tnomips16\n");
9552 assemble_start_function (stubdecl
, stubname
);
9554 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9555 fputs ("\t.ent\t", asm_out_file
);
9556 assemble_name (asm_out_file
, stubname
);
9557 fputs ("\n", asm_out_file
);
9559 assemble_name (asm_out_file
, stubname
);
9560 fputs (":\n", asm_out_file
);
9563 /* We build the stub code by hand. That's the only way we can
9564 do it, since we can't generate 32 bit code during a 16 bit
9567 /* We don't want the assembler to insert any nops here. */
9568 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
9570 mips16_fp_args (asm_out_file
, fp_code
, 0);
9574 fprintf (asm_out_file
, "\t.set\tnoat\n");
9575 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
9577 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
9578 fprintf (asm_out_file
, "\t.set\tat\n");
9579 /* Unfortunately, we can't fill the jump delay slot. We
9580 can't fill with one of the mtc1 instructions, because the
9581 result is not available for one instruction, so if the
9582 very first instruction in the function refers to the
9583 register, it will see the wrong value. */
9584 fprintf (asm_out_file
, "\tnop\n");
9588 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
9589 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
9590 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
9591 /* As above, we can't fill the delay slot. */
9592 fprintf (asm_out_file
, "\tnop\n");
9593 if (GET_MODE (retval
) == SFmode
)
9594 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9595 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
9598 if (TARGET_BIG_ENDIAN
)
9600 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9601 reg_names
[GP_REG_FIRST
+ 2],
9602 reg_names
[FP_REG_FIRST
+ 1]);
9603 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9604 reg_names
[GP_REG_FIRST
+ 3],
9605 reg_names
[FP_REG_FIRST
+ 0]);
9609 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9610 reg_names
[GP_REG_FIRST
+ 2],
9611 reg_names
[FP_REG_FIRST
+ 0]);
9612 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9613 reg_names
[GP_REG_FIRST
+ 3],
9614 reg_names
[FP_REG_FIRST
+ 1]);
9617 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
9618 /* As above, we can't fill the delay slot. */
9619 fprintf (asm_out_file
, "\tnop\n");
9622 fprintf (asm_out_file
, "\t.set\treorder\n");
9624 #ifdef ASM_DECLARE_FUNCTION_SIZE
9625 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
9628 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9629 fputs ("\t.end\t", asm_out_file
);
9630 assemble_name (asm_out_file
, stubname
);
9631 fputs ("\n", asm_out_file
);
9634 fprintf (asm_out_file
, "\t.set\tmips16\n");
9636 /* Record this stub. */
9637 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
9638 l
->name
= xstrdup (fnname
);
9640 l
->next
= mips16_stubs
;
9644 /* If we expect a floating point return value, but we've built a
9645 stub which does not expect one, then we're in trouble. We can't
9646 use the existing stub, because it won't handle the floating point
9647 value. We can't build a new stub, because the linker won't know
9648 which stub to use for the various calls in this object file.
9649 Fortunately, this case is illegal, since it means that a function
9650 was declared in two different ways in a single compilation. */
9651 if (fpret
&& ! l
->fpret
)
9652 error ("can not handle inconsistent calls to `%s'", fnname
);
9654 /* If we are calling a stub which handles a floating point return
9655 value, we need to arrange to save $18 in the prologue. We do
9656 this by marking the function call as using the register. The
9657 prologue will later see that it is used, and emit code to save
9664 if (retval
== NULL_RTX
)
9665 insn
= gen_call_internal0 (fnmem
, arg_size
,
9666 gen_rtx (REG
, SImode
,
9667 GP_REG_FIRST
+ 31));
9669 insn
= gen_call_value_internal0 (retval
, fnmem
, arg_size
,
9670 gen_rtx (REG
, SImode
,
9671 GP_REG_FIRST
+ 31));
9672 insn
= emit_call_insn (insn
);
9674 if (GET_CODE (insn
) != CALL_INSN
)
9677 CALL_INSN_FUNCTION_USAGE (insn
) =
9678 gen_rtx (EXPR_LIST
, VOIDmode
,
9679 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
9680 CALL_INSN_FUNCTION_USAGE (insn
));
9682 /* Return 1 to tell the caller that we've generated the call
9687 /* Return 0 to let the caller generate the call insn. */
9691 /* This function looks through the code for a function, and tries to
9692 optimize the usage of the $gp register. We arrange to copy $gp
9693 into a pseudo-register, and then let gcc's normal reload handling
9694 deal with the pseudo-register. Unfortunately, if reload choose to
9695 put the pseudo-register into a call-clobbered register, it will
9696 emit saves and restores for that register around any function
9697 calls. We don't need the saves, and it's faster to copy $gp than
9698 to do an actual restore. ??? This still means that we waste a
9701 This is an optimization, and the code which gcc has actually
9702 generated is correct, so we do not need to catch all cases. */
9705 mips16_optimize_gp (first
)
9708 rtx gpcopy
, slot
, insn
;
9710 /* Look through the instructions. Set GPCOPY to the register which
9711 holds a copy of $gp. Set SLOT to the stack slot where it is
9712 saved. If we find an instruction which sets GPCOPY to anything
9713 other than $gp or SLOT, then we can't use it. If we find an
9714 instruction which sets SLOT to anything other than GPCOPY, we
9719 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9723 if (! INSN_P (insn
))
9726 set
= PATTERN (insn
);
9728 /* We know that all references to memory will be inside a SET,
9729 because there is no other way to access memory on the mips16.
9730 We don't have to worry about a PARALLEL here, because the
9731 mips.md file will never generate them for memory references. */
9732 if (GET_CODE (set
) != SET
)
9735 if (gpcopy
== NULL_RTX
9736 && GET_CODE (SET_SRC (set
)) == CONST
9737 && GET_CODE (XEXP (SET_SRC (set
), 0)) == REG
9738 && REGNO (XEXP (SET_SRC (set
), 0)) == GP_REG_FIRST
+ 28
9739 && GET_CODE (SET_DEST (set
)) == REG
9740 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9741 gpcopy
= SET_DEST (set
);
9742 else if (slot
== NULL_RTX
9743 && gpcopy
!= NULL_RTX
9744 && GET_CODE (SET_DEST (set
)) == MEM
9745 && GET_CODE (SET_SRC (set
)) == REG
9746 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
)
9747 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9751 offset
= const0_rtx
;
9752 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9753 if (GET_CODE (base
) == REG
9754 && (REGNO (base
) == STACK_POINTER_REGNUM
9755 || REGNO (base
) == FRAME_POINTER_REGNUM
))
9756 slot
= SET_DEST (set
);
9758 else if (gpcopy
!= NULL_RTX
9759 && (GET_CODE (SET_DEST (set
)) == REG
9760 || GET_CODE (SET_DEST (set
)) == SUBREG
)
9761 && reg_overlap_mentioned_p (SET_DEST (set
), gpcopy
)
9762 && (GET_CODE (SET_DEST (set
)) != REG
9763 || REGNO (SET_DEST (set
)) != REGNO (gpcopy
)
9764 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
9765 || ((GET_CODE (SET_SRC (set
)) != CONST
9766 || GET_CODE (XEXP (SET_SRC (set
), 0)) != REG
9767 || (REGNO (XEXP (SET_SRC (set
), 0))
9768 != GP_REG_FIRST
+ 28))
9769 && ! rtx_equal_p (SET_SRC (set
), slot
))))
9771 else if (slot
!= NULL_RTX
9772 && GET_CODE (SET_DEST (set
)) == MEM
9773 && rtx_equal_p (SET_DEST (set
), slot
)
9774 && (GET_CODE (SET_SRC (set
)) != REG
9775 || REGNO (SET_SRC (set
)) != REGNO (gpcopy
)))
9779 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9780 different optimization. Any time we find a copy of $28 into a
9781 register, followed by an add of a symbol_ref to that register, we
9782 convert it to load the value from the constant table instead.
9783 The copy and add will take six bytes, just as the load and
9784 constant table entry will take six bytes. However, it is
9785 possible that the constant table entry will be shared.
9787 This could be a peephole optimization, but I don't know if the
9788 peephole code can call force_const_mem.
9790 Using the same register for the copy of $28 and the add of the
9791 symbol_ref is actually pretty likely, since the add instruction
9792 requires the destination and the first addend to be the same
9795 if (insn
!= NULL_RTX
|| gpcopy
== NULL_RTX
|| slot
== NULL_RTX
)
9799 /* This optimization is only reasonable if the constant table
9800 entries are only 4 bytes. */
9801 if (Pmode
!= SImode
)
9804 for (insn
= first
; insn
!= NULL_RTX
; insn
= next
)
9811 next
= NEXT_INSN (next
);
9813 while (next
!= NULL_RTX
9814 && (GET_CODE (next
) == NOTE
9815 || (GET_CODE (next
) == INSN
9816 && (GET_CODE (PATTERN (next
)) == USE
9817 || GET_CODE (PATTERN (next
)) == CLOBBER
))));
9819 if (next
== NULL_RTX
)
9822 if (! INSN_P (insn
))
9825 if (! INSN_P (next
))
9828 set1
= PATTERN (insn
);
9829 if (GET_CODE (set1
) != SET
)
9831 set2
= PATTERN (next
);
9832 if (GET_CODE (set2
) != SET
)
9835 if (GET_CODE (SET_DEST (set1
)) == REG
9836 && GET_CODE (SET_SRC (set1
)) == CONST
9837 && GET_CODE (XEXP (SET_SRC (set1
), 0)) == REG
9838 && REGNO (XEXP (SET_SRC (set1
), 0)) == GP_REG_FIRST
+ 28
9839 && rtx_equal_p (SET_DEST (set1
), SET_DEST (set2
))
9840 && GET_CODE (SET_SRC (set2
)) == PLUS
9841 && rtx_equal_p (SET_DEST (set1
), XEXP (SET_SRC (set2
), 0))
9842 && mips16_gp_offset_p (XEXP (SET_SRC (set2
), 1))
9843 && GET_CODE (XEXP (XEXP (SET_SRC (set2
), 1), 0)) == MINUS
)
9847 /* We've found a case we can change to load from the
9850 sym
= XEXP (XEXP (XEXP (SET_SRC (set2
), 1), 0), 0);
9851 if (GET_CODE (sym
) != SYMBOL_REF
)
9853 emit_insn_after (gen_rtx (SET
, VOIDmode
, SET_DEST (set1
),
9854 force_const_mem (Pmode
, sym
)),
9857 PUT_CODE (insn
, NOTE
);
9858 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9859 NOTE_SOURCE_FILE (insn
) = 0;
9861 PUT_CODE (next
, NOTE
);
9862 NOTE_LINE_NUMBER (next
) = NOTE_INSN_DELETED
;
9863 NOTE_SOURCE_FILE (next
) = 0;
9870 /* We can safely remove all assignments to SLOT from GPCOPY, and
9871 replace all assignments from SLOT to GPCOPY with assignments from
9874 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9878 if (! INSN_P (insn
))
9881 set
= PATTERN (insn
);
9882 if (GET_CODE (set
) != SET
9883 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
)
9886 if (GET_CODE (SET_DEST (set
)) == MEM
9887 && rtx_equal_p (SET_DEST (set
), slot
)
9888 && GET_CODE (SET_SRC (set
)) == REG
9889 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
))
9891 PUT_CODE (insn
, NOTE
);
9892 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9893 NOTE_SOURCE_FILE (insn
) = 0;
9895 else if (GET_CODE (SET_DEST (set
)) == REG
9896 && REGNO (SET_DEST (set
)) == REGNO (gpcopy
)
9897 && GET_CODE (SET_SRC (set
)) == MEM
9898 && rtx_equal_p (SET_SRC (set
), slot
))
9900 emit_insn_after (gen_rtx (SET
, Pmode
, SET_DEST (set
),
9901 gen_rtx (CONST
, Pmode
,
9902 gen_rtx (REG
, Pmode
,
9903 GP_REG_FIRST
+ 28))),
9905 PUT_CODE (insn
, NOTE
);
9906 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9907 NOTE_SOURCE_FILE (insn
) = 0;
9912 /* We keep a list of constants we which we have to add to internal
9913 constant tables in the middle of large functions. */
9917 struct constant
*next
;
9920 enum machine_mode mode
;
9923 /* Add a constant to the list in *PCONSTANTS. */
9926 add_constant (pconstants
, val
, mode
)
9927 struct constant
**pconstants
;
9929 enum machine_mode mode
;
9933 for (c
= *pconstants
; c
!= NULL
; c
= c
->next
)
9934 if (mode
== c
->mode
&& rtx_equal_p (val
, c
->value
))
9937 c
= (struct constant
*) xmalloc (sizeof *c
);
9940 c
->label
= gen_label_rtx ();
9941 c
->next
= *pconstants
;
9946 /* Dump out the constants in CONSTANTS after INSN. */
9949 dump_constants (constants
, insn
)
9950 struct constant
*constants
;
9961 struct constant
*next
;
9963 switch (GET_MODE_SIZE (c
->mode
))
9970 insn
= emit_insn_after (gen_align_2 (), insn
);
9975 insn
= emit_insn_after (gen_align_4 (), insn
);
9980 insn
= emit_insn_after (gen_align_8 (), insn
);
9985 insn
= emit_label_after (c
->label
, insn
);
9990 r
= gen_consttable_qi (c
->value
);
9993 r
= gen_consttable_hi (c
->value
);
9996 r
= gen_consttable_si (c
->value
);
9999 r
= gen_consttable_sf (c
->value
);
10002 r
= gen_consttable_di (c
->value
);
10005 r
= gen_consttable_df (c
->value
);
10011 insn
= emit_insn_after (r
, insn
);
10018 emit_barrier_after (insn
);
10021 /* Find the symbol in an address expression. */
10024 mips_find_symbol (addr
)
10027 if (GET_CODE (addr
) == MEM
)
10028 addr
= XEXP (addr
, 0);
10029 while (GET_CODE (addr
) == CONST
)
10030 addr
= XEXP (addr
, 0);
10031 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
10033 if (GET_CODE (addr
) == PLUS
)
10037 l1
= mips_find_symbol (XEXP (addr
, 0));
10038 l2
= mips_find_symbol (XEXP (addr
, 1));
10039 if (l1
!= NULL_RTX
&& l2
== NULL_RTX
)
10041 else if (l1
== NULL_RTX
&& l2
!= NULL_RTX
)
10047 /* Exported to toplev.c.
10049 Do a final pass over the function, just before delayed branch
10053 machine_dependent_reorg (first
)
10056 int insns_len
, max_internal_pool_size
, pool_size
, addr
, first_constant_ref
;
10058 struct constant
*constants
;
10060 if (! TARGET_MIPS16
)
10063 /* If $gp is used, try to remove stores, and replace loads with
10064 copies from $gp. */
10066 mips16_optimize_gp (first
);
10068 /* Scan the function looking for PC relative loads which may be out
10069 of range. All such loads will either be from the constant table,
10070 or be getting the address of a constant string. If the size of
10071 the function plus the size of the constant table is less than
10072 0x8000, then all loads are in range. */
10075 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
10077 insns_len
+= get_attr_length (insn
);
10079 /* ??? We put switch tables in .text, but we don't define
10080 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
10081 compute their lengths correctly. */
10082 if (GET_CODE (insn
) == JUMP_INSN
)
10086 body
= PATTERN (insn
);
10087 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
10088 insns_len
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
10089 * GET_MODE_SIZE (GET_MODE (body
)));
10090 insns_len
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
10094 /* Store the original value of insns_len in cfun->machine, so
10095 that simple_memory_operand can look at it. */
10096 cfun
->machine
->insns_len
= insns_len
;
10098 pool_size
= get_pool_size ();
10099 if (insns_len
+ pool_size
+ mips_string_length
< 0x8000)
10102 /* Loop over the insns and figure out what the maximum internal pool
10104 max_internal_pool_size
= 0;
10105 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
10107 if (GET_CODE (insn
) == INSN
10108 && GET_CODE (PATTERN (insn
)) == SET
)
10112 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
10113 if (src
== NULL_RTX
)
10115 if (CONSTANT_POOL_ADDRESS_P (src
))
10116 max_internal_pool_size
+= GET_MODE_SIZE (get_pool_mode (src
));
10117 else if (SYMBOL_REF_FLAG (src
))
10118 max_internal_pool_size
+= GET_MODE_SIZE (Pmode
);
10124 first_constant_ref
= -1;
10126 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
10128 if (GET_CODE (insn
) == INSN
10129 && GET_CODE (PATTERN (insn
)) == SET
)
10132 enum machine_mode mode
= VOIDmode
;
10135 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
10136 if (src
!= NULL_RTX
&& CONSTANT_POOL_ADDRESS_P (src
))
10138 /* ??? This is very conservative, which means that we
10139 will generate too many copies of the constant table.
10140 The only solution would seem to be some form of
10142 if (((insns_len
- addr
)
10143 + max_internal_pool_size
10144 + get_pool_offset (src
))
10147 val
= get_pool_constant (src
);
10148 mode
= get_pool_mode (src
);
10150 max_internal_pool_size
-= GET_MODE_SIZE (get_pool_mode (src
));
10152 else if (src
!= NULL_RTX
&& SYMBOL_REF_FLAG (src
))
10154 /* Including all of mips_string_length is conservative,
10155 and so is including all of max_internal_pool_size. */
10156 if (((insns_len
- addr
)
10157 + max_internal_pool_size
10159 + mips_string_length
)
10165 max_internal_pool_size
-= Pmode
;
10168 if (val
!= NULL_RTX
)
10172 /* This PC relative load is out of range. ??? In the
10173 case of a string constant, we are only guessing that
10174 it is range, since we don't know the offset of a
10175 particular string constant. */
10177 lab
= add_constant (&constants
, val
, mode
);
10178 newsrc
= gen_rtx (MEM
, mode
,
10179 gen_rtx (LABEL_REF
, VOIDmode
, lab
));
10180 RTX_UNCHANGING_P (newsrc
) = 1;
10181 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
10182 SET_DEST (PATTERN (insn
)),
10184 INSN_CODE (insn
) = -1;
10186 if (first_constant_ref
< 0)
10187 first_constant_ref
= addr
;
10191 addr
+= get_attr_length (insn
);
10193 /* ??? We put switch tables in .text, but we don't define
10194 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
10195 compute their lengths correctly. */
10196 if (GET_CODE (insn
) == JUMP_INSN
)
10200 body
= PATTERN (insn
);
10201 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
10202 addr
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
10203 * GET_MODE_SIZE (GET_MODE (body
)));
10204 addr
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
10207 if (GET_CODE (insn
) == BARRIER
)
10209 /* Output any constants we have accumulated. Note that we
10210 don't need to change ADDR, since its only use is
10211 subtraction from INSNS_LEN, and both would be changed by
10213 ??? If the instructions up to the next barrier reuse a
10214 constant, it would often be better to continue
10216 if (constants
!= NULL
)
10217 dump_constants (constants
, insn
);
10219 first_constant_ref
= -1;
10222 if (constants
!= NULL
10223 && (NEXT_INSN (insn
) == NULL
10224 || (first_constant_ref
>= 0
10225 && (((addr
- first_constant_ref
)
10226 + 2 /* for alignment */
10227 + 2 /* for a short jump insn */
10231 /* If we haven't had a barrier within 0x8000 bytes of a
10232 constant reference or we are at the end of the function,
10233 emit a barrier now. */
10235 rtx label
, jump
, barrier
;
10237 label
= gen_label_rtx ();
10238 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
10239 JUMP_LABEL (jump
) = label
;
10240 LABEL_NUSES (label
) = 1;
10241 barrier
= emit_barrier_after (jump
);
10242 emit_label_after (label
, barrier
);
10243 first_constant_ref
= -1;
10247 /* ??? If we output all references to a constant in internal
10248 constants table, we don't need to output the constant in the real
10249 constant table, but we have no way to prevent that. */
10252 /* Return nonzero if X is a SIGN or ZERO extend operator. */
10254 extend_operator (x
, mode
)
10256 enum machine_mode mode ATTRIBUTE_UNUSED
;
10258 enum rtx_code code
= GET_CODE (x
);
10259 return code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
;
10262 /* Accept any operator that can be used to shift the high half of the
10263 input value to the lower half, suitable for truncation. The
10264 remainder (the lower half of the input, and the upper half of the
10265 output) will be discarded. */
10267 highpart_shift_operator (x
, mode
)
10269 enum machine_mode mode ATTRIBUTE_UNUSED
;
10271 enum rtx_code code
= GET_CODE (x
);
10272 return (code
== LSHIFTRT
10273 || code
== ASHIFTRT
10274 || code
== ROTATERT
10275 || code
== ROTATE
);
10278 /* Return a number assessing the cost of moving a register in class
10279 FROM to class TO. The classes are expressed using the enumeration
10280 values such as `GENERAL_REGS'. A value of 2 is the default; other
10281 values are interpreted relative to that.
10283 It is not required that the cost always equal 2 when FROM is the
10284 same as TO; on some machines it is expensive to move between
10285 registers if they are not general registers.
10287 If reload sees an insn consisting of a single `set' between two
10288 hard registers, and if `REGISTER_MOVE_COST' applied to their
10289 classes returns a value of 2, reload does not check to ensure that
10290 the constraints of the insn are met. Setting a cost of other than
10291 2 will allow reload to verify that the constraints are met. You
10292 should do this if the `movM' pattern's constraints do not allow
10295 ??? We make make the cost of moving from HI/LO/HILO/MD into general
10296 registers the same as for one of moving general registers to
10297 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
10298 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
10299 isn't clear if it is wise. And it might not work in all cases. We
10300 could solve the DImode LO reg problem by using a multiply, just
10301 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10302 problem by using divide instructions. divu puts the remainder in
10303 the HI reg, so doing a divide by -1 will move the value in the HI
10304 reg for all values except -1. We could handle that case by using a
10305 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10306 a compare/branch to test the input value to see which instruction
10307 we need to use. This gets pretty messy, but it is feasible. */
10310 mips_register_move_cost (mode
, to
, from
)
10311 enum machine_mode mode ATTRIBUTE_UNUSED
;
10312 enum reg_class to
, from
;
10314 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
10316 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
10318 else if (GR_REG_CLASS_P (from
))
10320 if (to
== M16_REGS
)
10322 else if (to
== M16_NA_REGS
)
10324 else if (GR_REG_CLASS_P (to
))
10331 else if (to
== FP_REGS
)
10333 else if (to
== HI_REG
|| to
== LO_REG
|| to
== MD_REGS
10341 else if (COP_REG_CLASS_P (to
))
10345 } /* GR_REG_CLASS_P (from) */
10346 else if (from
== FP_REGS
)
10348 if (GR_REG_CLASS_P (to
))
10350 else if (to
== FP_REGS
)
10352 else if (to
== ST_REGS
)
10354 } /* from == FP_REGS */
10355 else if (from
== HI_REG
|| from
== LO_REG
|| from
== MD_REGS
10356 || from
== HILO_REG
)
10358 if (GR_REG_CLASS_P (to
))
10365 } /* from == HI_REG, etc. */
10366 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
10368 else if (COP_REG_CLASS_P (from
))
10371 } /* COP_REG_CLASS_P (from) */
10378 /* Return the length of INSN. LENGTH is the initial length computed by
10379 attributes in the machine-description file. */
10382 mips_adjust_insn_length (insn
, length
)
10386 /* A unconditional jump has an unfilled delay slot if it is not part
10387 of a sequence. A conditional jump normally has a delay slot, but
10388 does not on MIPS16. */
10389 if (simplejump_p (insn
)
10390 || (!TARGET_MIPS16
&& (GET_CODE (insn
) == JUMP_INSN
10391 || GET_CODE (insn
) == CALL_INSN
)))
10394 /* All MIPS16 instructions are a measly two bytes. */
10401 /* Output assembly instructions to peform a conditional branch.
10403 INSN is the branch instruction. OPERANDS[0] is the condition.
10404 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
10405 of the first operand to the condition. If TWO_OPERANDS_P is
10406 nonzero the comparison takes two operands; OPERANDS[3] will be the
10409 If INVERTED_P is nonzero we are to branch if the condition does
10410 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
10412 LENGTH is the length (in bytes) of the sequence we are to generate.
10413 That tells us whether to generate a simple conditional branch, or a
10414 reversed conditional branch around a `jr' instruction. */
10416 mips_output_conditional_branch (insn
,
10424 int two_operands_p
;
10429 static char buffer
[200];
10430 /* The kind of comparison we are doing. */
10431 enum rtx_code code
= GET_CODE (operands
[0]);
10432 /* Nonzero if the opcode for the comparison needs a `z' indicating
10433 that it is a comparision against zero. */
10435 /* A string to use in the assembly output to represent the first
10437 const char *op1
= "%z2";
10438 /* A string to use in the assembly output to represent the second
10439 operand. Use the hard-wired zero register if there's no second
10441 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
10442 /* The operand-printing string for the comparison. */
10443 const char *const comp
= (float_p
? "%F0" : "%C0");
10444 /* The operand-printing string for the inverted comparison. */
10445 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
10447 /* The MIPS processors (for levels of the ISA at least two), have
10448 "likely" variants of each branch instruction. These instructions
10449 annul the instruction in the delay slot if the branch is not
10451 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
10453 if (!two_operands_p
)
10455 /* To compute whether than A > B, for example, we normally
10456 subtract B from A and then look at the sign bit. But, if we
10457 are doing an unsigned comparison, and B is zero, we don't
10458 have to do the subtraction. Instead, we can just check to
10459 see if A is nonzero. Thus, we change the CODE here to
10460 reflect the simpler comparison operation. */
10472 /* A condition which will always be true. */
10478 /* A condition which will always be false. */
10484 /* Not a special case. */
10489 /* Relative comparisons are always done against zero. But
10490 equality comparisons are done between two operands, and therefore
10491 do not require a `z' in the assembly language output. */
10492 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
10493 /* For comparisons against zero, the zero is not provided
10498 /* Begin by terminating the buffer. That way we can always use
10499 strcat to add to it. */
10506 /* Just a simple conditional branch. */
10508 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1",
10509 inverted_p
? inverted_comp
: comp
);
10511 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1",
10512 inverted_p
? inverted_comp
: comp
,
10513 need_z_p
? "z" : "",
10523 /* Generate a reversed conditional branch around ` j'
10536 If the original branch was a likely branch, the delay slot
10537 must be executed only if the branch is taken, so generate:
10549 When generating non-embedded PIC, instead of:
10562 rtx target
= gen_label_rtx ();
10564 orig_target
= operands
[1];
10565 operands
[1] = target
;
10566 /* Generate the reversed comparison. This takes four
10569 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
10570 inverted_p
? comp
: inverted_comp
);
10572 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
10573 inverted_p
? comp
: inverted_comp
,
10574 need_z_p
? "z" : "",
10577 output_asm_insn (buffer
, operands
);
10579 if (length
!= 16 && length
!= 28 && ! mips_branch_likely
)
10581 /* Output delay slot instruction. */
10582 rtx insn
= final_sequence
;
10583 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
10585 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
10588 output_asm_insn ("%#", 0);
10591 output_asm_insn ("j\t%0", &orig_target
);
10594 if (Pmode
== DImode
)
10595 output_asm_insn ("%[dla\t%@,%0\n\tjr\t%@%]", &orig_target
);
10597 output_asm_insn ("%[la\t%@,%0\n\tjr\t%@%]", &orig_target
);
10600 if (length
!= 16 && length
!= 28 && mips_branch_likely
)
10602 /* Output delay slot instruction. */
10603 rtx insn
= final_sequence
;
10604 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
10606 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
10609 output_asm_insn ("%#", 0);
10611 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
10612 CODE_LABEL_NUMBER (target
));
10617 /* We do not currently use this code. It handles jumps to
10618 arbitrary locations, using `jr', even across a 256MB boundary.
10619 We could add a -mhuge switch, and then use this code instead of
10620 the `j' alternative above when -mhuge was used. */
10625 /* Generate a reversed conditional branch around a `jr'
10639 Not pretty, but allows a conditional branch anywhere in the
10640 32-bit address space. If the original branch is annulled,
10641 then the instruction in the delay slot should be executed
10642 only if the branch is taken. The la instruction is really
10643 a macro which will usually take eight bytes, but sometimes
10644 takes only four, if the instruction to which we're jumping
10645 gets its own entry in the global pointer table, which will
10646 happen if its a case label. The assembler will then
10647 generate only a four-byte sequence, rather than eight, and
10648 there seems to be no way to tell it not to. Thus, we can't
10649 just use a `.+x' addressing form; we don't know what value
10652 So, we resort to using the explicit relocation syntax
10653 available in the assembler and do:
10655 lw $at,%got_page(target)($gp)
10656 daddiu $at,$at,%got_ofst(target)
10658 That way, this always takes up eight bytes, and we can use
10659 the `.+x' form. Of course, these explicit machinations
10660 with relocation will not work with old assemblers. Then
10661 again, neither do out-of-range branches, so we haven't lost
10664 /* The target of the reversed branch. */
10665 const char *const target
10666 = ((mips_branch_likely
|| length
== 20) ? ".+20" : ".+16");
10667 const char *at_register
= mips_reg_names
[ASSEMBLER_SCRATCH_REGNUM
];
10668 const char *gp_register
= mips_reg_names
[PIC_OFFSET_TABLE_REGNUM
];
10671 strcpy (buffer
, "%(%<%[");
10672 c
= strchr (buffer
, '\0');
10673 /* Generate the reversed comparision. This takes four
10676 sprintf (c
, "%%*b%s\t%%Z2%s",
10677 inverted_p
? comp
: inverted_comp
,
10680 sprintf (c
, "%%*b%s%s\t%s%s,%s",
10681 inverted_p
? comp
: inverted_comp
,
10682 need_z_p
? "z" : "",
10686 c
= strchr (buffer
, '\0');
10687 /* Generate the load-address, and jump. This takes twelve
10688 bytes, for a total of 16. */
10690 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10697 /* The delay slot was unfilled. Since we're inside
10698 .noreorder, the assembler will not fill in the NOP for
10699 us, so we must do it ourselves. */
10700 strcat (buffer
, "\n\tnop");
10701 strcat (buffer
, "%]%>%)");
10714 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10715 with a final "000" replaced by "k". Ignore case.
10717 Note: this function is shared between GCC and GAS. */
10720 mips_strict_matching_cpu_name_p (canonical
, given
)
10721 const char *canonical
, *given
;
10723 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
10724 given
++, canonical
++;
10726 return ((*given
== 0 && *canonical
== 0)
10727 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
10731 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10732 CPU name. We've traditionally allowed a lot of variation here.
10734 Note: this function is shared between GCC and GAS. */
10737 mips_matching_cpu_name_p (canonical
, given
)
10738 const char *canonical
, *given
;
10740 /* First see if the name matches exactly, or with a final "000"
10741 turned into "k". */
10742 if (mips_strict_matching_cpu_name_p (canonical
, given
))
10745 /* If not, try comparing based on numerical designation alone.
10746 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10747 if (TOLOWER (*given
) == 'r')
10749 if (!ISDIGIT (*given
))
10752 /* Skip over some well-known prefixes in the canonical name,
10753 hoping to find a number there too. */
10754 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
10756 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
10758 else if (TOLOWER (canonical
[0]) == 'r')
10761 return mips_strict_matching_cpu_name_p (canonical
, given
);
10765 /* Parse an option that takes the name of a processor as its argument.
10766 OPTION is the name of the option and CPU_STRING is the argument.
10767 Return the corresponding processor enumeration if the CPU_STRING is
10768 recognized, otherwise report an error and return null.
10770 A similar function exists in GAS. */
10772 static const struct mips_cpu_info
*
10773 mips_parse_cpu (option
, cpu_string
)
10774 const char *option
, *cpu_string
;
10776 const struct mips_cpu_info
*p
;
10779 /* In the past, we allowed upper-case CPU names, but it doesn't
10780 work well with the multilib machinery. */
10781 for (s
= cpu_string
; *s
!= 0; s
++)
10784 warning ("the cpu name must be lower case");
10788 /* 'from-abi' selects the most compatible architecture for the given
10789 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10790 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10791 version. Look first at the -mgp options, if given, otherwise base
10792 the choice on MASK_64BIT in TARGET_DEFAULT. */
10793 if (strcasecmp (cpu_string
, "from-abi") == 0)
10794 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
10795 : ABI_NEEDS_64BIT_REGS
? 3
10796 : (TARGET_64BIT
? 3 : 1));
10798 /* 'default' has traditionally been a no-op. Probably not very useful. */
10799 if (strcasecmp (cpu_string
, "default") == 0)
10802 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
10803 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
10806 error ("bad value (%s) for %s", cpu_string
, option
);
10811 /* Return the processor associated with the given ISA level, or null
10812 if the ISA isn't valid. */
10814 static const struct mips_cpu_info
*
10815 mips_cpu_info_from_isa (isa
)
10818 const struct mips_cpu_info
*p
;
10820 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
10827 /* Adjust the cost of INSN based on the relationship between INSN that
10828 is dependent on DEP_INSN through the dependence LINK. The default
10829 is to make no adjustment to COST.
10831 On the MIPS, ignore the cost of anti- and output-dependencies. */
10833 mips_adjust_cost (insn
, link
, dep
, cost
)
10834 rtx insn ATTRIBUTE_UNUSED
;
10836 rtx dep ATTRIBUTE_UNUSED
;
10839 if (REG_NOTE_KIND (link
) != 0)
10840 return 0; /* Anti or output dependence. */
10844 /* ??? This could be replaced with the default elf version if
10845 TARGET_IS_SMALL_DATA_P is set properly. */
10848 mips_unique_section (decl
, reloc
)
10852 int len
, size
, sec
;
10853 const char *name
, *prefix
;
10855 static const char *const prefixes
[4][2] = {
10856 { ".text.", ".gnu.linkonce.t." },
10857 { ".rodata.", ".gnu.linkonce.r." },
10858 { ".data.", ".gnu.linkonce.d." },
10859 { ".sdata.", ".gnu.linkonce.s." }
10862 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
10863 name
= (* targetm
.strip_name_encoding
) (name
);
10864 size
= int_size_in_bytes (TREE_TYPE (decl
));
10866 /* Determine the base section we are interested in:
10867 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10868 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10870 else if (DECL_INITIAL (decl
) == 0
10871 || DECL_INITIAL (decl
) == error_mark_node
)
10873 else if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
10874 && TREE_CODE (decl
) == STRING_CST
10875 && !flag_writable_strings
)
10877 /* For embedded position independent code, put constant
10878 strings in the text section, because the data section
10879 is limited to 64K in size. For mips16 code, put
10880 strings in the text section so that a PC relative load
10881 instruction can be used to get their address. */
10884 else if (TARGET_EMBEDDED_DATA
)
10886 /* For embedded applications, always put an object in
10887 read-only data if possible, in order to reduce RAM
10890 if (decl_readonly_section (decl
, reloc
))
10892 else if (size
> 0 && size
<= mips_section_threshold
)
10899 /* For hosted applications, always put an object in
10900 small data if possible, as this gives the best
10903 if (size
> 0 && size
<= mips_section_threshold
)
10905 else if (decl_readonly_section (decl
, reloc
))
10911 prefix
= prefixes
[sec
][DECL_ONE_ONLY (decl
)];
10912 len
= strlen (name
) + strlen (prefix
);
10913 string
= alloca (len
+ 1);
10914 sprintf (string
, "%s%s", prefix
, name
);
10916 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
10920 mips_hard_regno_nregs (regno
, mode
)
10922 enum machine_mode mode
;
10924 if (! FP_REG_P (regno
))
10925 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
10927 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
10931 mips_return_in_memory (type
)
10934 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10935 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10936 structures are returned in a register. Objects with varying size
10937 must still be returned in memory, of course. */
10939 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
10940 return (TYPE_MODE (type
) == BLKmode
);
10942 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
10943 || (int_size_in_bytes (type
) == -1));
10951 case PROCESSOR_R3000
: return 1;
10952 case PROCESSOR_R5400
: return 2;
10953 case PROCESSOR_R5500
: return 2;
10963 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
10964 processors that have a DFA pipeline description. */
10967 mips_use_dfa_pipeline_interface ()
10971 case PROCESSOR_R5400
:
10972 case PROCESSOR_R5500
:
10973 case PROCESSOR_SR71000
:
10983 mips_emit_prefetch (operands
)
10986 /* For the mips32/64 architectures the hint fields are arranged
10987 by operation (load/store) and locality (normal/streamed/retained).
10988 Irritatingly, numbers 2 and 3 are reserved leaving no simple
10989 algorithm for figuring the hint. */
10991 int write
= INTVAL (operands
[1]);
10992 int locality
= INTVAL (operands
[2]);
10994 static const char * const alt
[2][4] = {
11009 return alt
[write
][locality
];
11014 #ifdef TARGET_IRIX6
11015 /* Output assembly to switch to section NAME with attribute FLAGS. */
11018 iris6_asm_named_section_1 (name
, flags
, align
)
11020 unsigned int flags
;
11021 unsigned int align
;
11023 unsigned int sh_type
, sh_flags
, sh_entsize
;
11026 if (!(flags
& SECTION_DEBUG
))
11027 sh_flags
|= 2; /* SHF_ALLOC */
11028 if (flags
& SECTION_WRITE
)
11029 sh_flags
|= 1; /* SHF_WRITE */
11030 if (flags
& SECTION_CODE
)
11031 sh_flags
|= 4; /* SHF_EXECINSTR */
11032 if (flags
& SECTION_SMALL
)
11033 sh_flags
|= 0x10000000; /* SHF_MIPS_GPREL */
11034 if (strcmp (name
, ".debug_frame") == 0)
11035 sh_flags
|= 0x08000000; /* SHF_MIPS_NOSTRIP */
11036 if (flags
& SECTION_DEBUG
)
11037 sh_type
= 0x7000001e; /* SHT_MIPS_DWARF */
11038 else if (flags
& SECTION_BSS
)
11039 sh_type
= 8; /* SHT_NOBITS */
11041 sh_type
= 1; /* SHT_PROGBITS */
11043 if (flags
& SECTION_CODE
)
11048 fprintf (asm_out_file
, "\t.section %s,%#x,%#x,%u,%u\n",
11049 name
, sh_type
, sh_flags
, sh_entsize
, align
);
11053 iris6_asm_named_section (name
, flags
)
11055 unsigned int flags
;
11057 if (TARGET_FILE_SWITCHING
&& (flags
& SECTION_CODE
))
11058 asm_out_file
= asm_out_text_file
;
11059 iris6_asm_named_section_1 (name
, flags
, 0);
11062 /* In addition to emitting a .align directive, record the maximum
11063 alignment requested for the current section. */
11065 struct iris_section_align_entry
11069 unsigned int flags
;
11072 static htab_t iris_section_align_htab
;
11073 static FILE *iris_orig_asm_out_file
;
11076 iris_section_align_entry_eq (p1
, p2
)
11080 const struct iris_section_align_entry
*old
= p1
;
11081 const char *new = p2
;
11083 return strcmp (old
->name
, new) == 0;
11087 iris_section_align_entry_hash (p
)
11090 const struct iris_section_align_entry
*old
= p
;
11091 return htab_hash_string (old
->name
);
11095 iris6_asm_output_align (file
, log
)
11099 const char *section
= current_section_name ();
11100 struct iris_section_align_entry
**slot
, *entry
;
11105 slot
= (struct iris_section_align_entry
**)
11106 htab_find_slot_with_hash (iris_section_align_htab
, section
,
11107 htab_hash_string (section
), INSERT
);
11111 entry
= (struct iris_section_align_entry
*)
11112 xmalloc (sizeof (struct iris_section_align_entry
));
11114 entry
->name
= section
;
11116 entry
->flags
= current_section_flags ();
11118 else if (entry
->log
< log
)
11121 fprintf (file
, "\t.align\t%u\n", log
);
11124 /* The Iris assembler does not record alignment from .align directives,
11125 but takes it from the first .section directive seen. Play yet more
11126 file switching games so that we can emit a .section directive at the
11127 beginning of the file with the proper alignment attached. */
11130 iris6_asm_file_start (stream
)
11133 mips_asm_file_start (stream
);
11135 iris_orig_asm_out_file
= asm_out_file
;
11136 stream
= tmpfile ();
11137 asm_out_file
= stream
;
11138 asm_out_data_file
= stream
;
11139 if (! TARGET_FILE_SWITCHING
)
11140 asm_out_text_file
= stream
;
11142 iris_section_align_htab
= htab_create (31, iris_section_align_entry_hash
,
11143 iris_section_align_entry_eq
, NULL
);
11147 iris6_section_align_1 (slot
, data
)
11149 void *data ATTRIBUTE_UNUSED
;
11151 const struct iris_section_align_entry
*entry
11152 = *(const struct iris_section_align_entry
**) slot
;
11154 iris6_asm_named_section_1 (entry
->name
, entry
->flags
, 1 << entry
->log
);
11159 iris6_asm_file_end (stream
)
11162 /* Emit section directives with the proper alignment at the top of the
11163 real output file. */
11164 asm_out_file
= iris_orig_asm_out_file
;
11165 htab_traverse (iris_section_align_htab
, iris6_section_align_1
, NULL
);
11167 /* Copy the data emitted to the temp file to the real output file. */
11168 copy_file_data (asm_out_file
, stream
);
11170 mips_asm_file_end (stream
);
11172 #endif /* TARGET_IRIX6 */
11174 #include "gt-mips.h"