1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Maximum size we are allowed to grow the stack in a single operation.
49 If we want more, we must do it in increments of at most this size.
50 If this value is 0, we don't check at all. */
51 const char * mcore_stack_increment_string
= 0;
52 int mcore_stack_increment
= STACK_UNITS_MAXSTEP
;
54 /* For dumping information about frame sizes. */
55 char * mcore_current_function_name
= 0;
56 long mcore_current_compilation_timestamp
= 0;
58 /* Global variables for machine-dependent things. */
60 /* Saved operands from the last compare to use when we generate an scc
65 /* Provides the class number of the smallest class containing
67 const int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
69 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
70 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
71 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
72 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
73 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
76 /* Provide reg_class from a letter such as appears in the machine
78 const enum reg_class reg_class_from_letter
[] =
80 /* a */ LRW_REGS
, /* b */ ONLYR1_REGS
, /* c */ C_REGS
, /* d */ NO_REGS
,
81 /* e */ NO_REGS
, /* f */ NO_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
82 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ NO_REGS
, /* l */ NO_REGS
,
83 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
84 /* q */ NO_REGS
, /* r */ GENERAL_REGS
, /* s */ NO_REGS
, /* t */ NO_REGS
,
85 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ NO_REGS
, /* x */ ALL_REGS
,
86 /* y */ NO_REGS
, /* z */ NO_REGS
91 int arg_size
; /* stdarg spills (bytes) */
92 int reg_size
; /* non-volatile reg saves (bytes) */
93 int reg_mask
; /* non-volatile reg saves */
94 int local_size
; /* locals */
95 int outbound_size
; /* arg overflow on calls out */
99 /* Describe the steps we'll use to grow it. */
100 #define MAX_STACK_GROWS 4 /* gives us some spare space */
101 int growth
[MAX_STACK_GROWS
];
119 static void output_stack_adjust
PARAMS ((int, int));
120 static int calc_live_regs
PARAMS ((int *));
121 static int const_ok_for_mcore
PARAMS ((int));
122 static int try_constant_tricks
PARAMS ((long, int *, int *));
123 static const char * output_inline_const
PARAMS ((enum machine_mode
, rtx
*));
124 static void block_move_sequence
PARAMS ((rtx
, rtx
, rtx
, rtx
, int, int, int));
125 static void layout_mcore_frame
PARAMS ((struct mcore_frame
*));
126 static cond_type is_cond_candidate
PARAMS ((rtx
));
127 static rtx emit_new_cond_insn
PARAMS ((rtx
, int));
128 static rtx conditionalize_block
PARAMS ((rtx
));
129 static void conditionalize_optimization
PARAMS ((rtx
));
130 static rtx handle_structs_in_regs
PARAMS ((enum machine_mode
, tree
, int));
131 static void mcore_mark_dllexport
PARAMS ((tree
));
132 static void mcore_mark_dllimport
PARAMS ((tree
));
133 static int mcore_dllexport_p
PARAMS ((tree
));
134 static int mcore_dllimport_p
PARAMS ((tree
));
135 const struct attribute_spec mcore_attribute_table
[];
136 static tree mcore_handle_naked_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
137 #ifdef OBJECT_FORMAT_ELF
138 static void mcore_asm_named_section
PARAMS ((const char *,
141 static void mcore_unique_section
PARAMS ((tree
, int));
142 static void mcore_encode_section_info
PARAMS ((tree
, rtx
, int));
143 static const char *mcore_strip_name_encoding
PARAMS ((const char *));
144 static int mcore_const_costs
PARAMS ((rtx
, RTX_CODE
));
145 static int mcore_and_cost
PARAMS ((rtx
));
146 static int mcore_ior_cost
PARAMS ((rtx
));
147 static bool mcore_rtx_costs
PARAMS ((rtx
, int, int, int *));
149 /* Initialize the GCC target structure. */
150 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
151 #undef TARGET_MERGE_DECL_ATTRIBUTES
152 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
155 #ifdef OBJECT_FORMAT_ELF
156 #undef TARGET_ASM_UNALIGNED_HI_OP
157 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
158 #undef TARGET_ASM_UNALIGNED_SI_OP
159 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
162 #undef TARGET_ATTRIBUTE_TABLE
163 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
164 #undef TARGET_ASM_UNIQUE_SECTION
165 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
166 #undef TARGET_ENCODE_SECTION_INFO
167 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
168 #undef TARGET_STRIP_NAME_ENCODING
169 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
171 #undef TARGET_RTX_COSTS
172 #define TARGET_RTX_COSTS mcore_rtx_costs
173 #undef TARGET_ADDRESS_COST
174 #define TARGET_ADDRESS_COST hook_int_rtx_0
176 struct gcc_target targetm
= TARGET_INITIALIZER
;
178 /* Adjust the stack and return the number of bytes taken to do it. */
180 output_stack_adjust (direction
, size
)
184 /* If extending stack a lot, we do it incrementally. */
185 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
187 rtx tmp
= gen_rtx (REG
, SImode
, 1);
189 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
192 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
193 memref
= gen_rtx (MEM
, SImode
, stack_pointer_rtx
);
194 MEM_VOLATILE_P (memref
) = 1;
195 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
196 size
-= mcore_stack_increment
;
198 while (size
> mcore_stack_increment
);
200 /* SIZE is now the residual for the last adjustment,
201 which doesn't require a probe. */
207 rtx val
= GEN_INT (size
);
211 rtx nval
= gen_rtx (REG
, SImode
, 1);
212 emit_insn (gen_movsi (nval
, val
));
217 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
219 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
225 /* Work out the registers which need to be saved,
226 both as a mask and a count. */
229 calc_live_regs (count
)
233 int live_regs_mask
= 0;
237 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
239 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
242 live_regs_mask
|= (1 << reg
);
246 return live_regs_mask
;
249 /* Print the operand address in x to the stream. */
252 mcore_print_operand_address (stream
, x
)
256 switch (GET_CODE (x
))
259 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
264 rtx base
= XEXP (x
, 0);
265 rtx index
= XEXP (x
, 1);
267 if (GET_CODE (base
) != REG
)
269 /* Ensure that BASE is a register (one of them must be). */
275 switch (GET_CODE (index
))
278 fprintf (stream
, "(%s,%d)", reg_names
[REGNO(base
)],
292 output_addr_const (stream
, x
);
297 /* Print operand x (an rtx) in assembler syntax to file stream
298 according to modifier code.
300 'R' print the next register or memory location along, ie the lsw in
302 'O' print a constant without the #
303 'M' print a constant as its negative
304 'P' print log2 of a power of two
305 'Q' print log2 of an inverse of a power of two
306 'U' print register for ldm/stm instruction
307 'X' print byte number for xtrbN instruction. */
310 mcore_print_operand (stream
, x
, code
)
319 fprintf (asm_out_file
, "32");
321 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
324 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
)));
327 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
330 fprintf (asm_out_file
, "%d", INTVAL (x
));
333 fprintf (asm_out_file
, "%d", - INTVAL (x
));
336 /* Next location along in memory or register. */
337 switch (GET_CODE (x
))
340 fputs (reg_names
[REGNO (x
) + 1], (stream
));
343 mcore_print_operand_address
344 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
351 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
352 reg_names
[REGNO (x
) + 3]);
355 fprintf (asm_out_file
, "0x%x", INTVAL (x
));
358 fprintf (asm_out_file
, "%d", 3 - INTVAL (x
) / 8);
362 switch (GET_CODE (x
))
365 fputs (reg_names
[REGNO (x
)], (stream
));
368 output_address (XEXP (x
, 0));
371 output_addr_const (stream
, x
);
378 /* What does a constant cost ? */
381 mcore_const_costs (exp
, code
)
386 int val
= INTVAL (exp
);
388 /* Easy constants. */
389 if ( CONST_OK_FOR_I (val
)
390 || CONST_OK_FOR_M (val
)
391 || CONST_OK_FOR_N (val
)
392 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
395 && ( CONST_OK_FOR_M (~val
)
396 || CONST_OK_FOR_N (~val
)))
398 else if (code
== PLUS
399 && ( CONST_OK_FOR_I (-val
)
400 || CONST_OK_FOR_M (-val
)
401 || CONST_OK_FOR_N (-val
)))
407 /* What does an and instruction cost - we do this b/c immediates may
408 have been relaxed. We want to ensure that cse will cse relaxed immeds
409 out. Otherwise we'll get bad code (multiple reloads of the same const). */
417 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
420 val
= INTVAL (XEXP (x
, 1));
422 /* Do it directly. */
423 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
425 /* Takes one instruction to load. */
426 else if (const_ok_for_mcore (val
))
428 /* Takes two instructions to load. */
429 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
432 /* Takes a lrw to load. */
436 /* What does an or cost - see and_cost(). */
444 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
447 val
= INTVAL (XEXP (x
, 1));
449 /* Do it directly with bclri. */
450 if (CONST_OK_FOR_M (val
))
452 /* Takes one instruction to load. */
453 else if (const_ok_for_mcore (val
))
455 /* Takes two instructions to load. */
456 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
459 /* Takes a lrw to load. */
464 mcore_rtx_costs (x
, code
, outer_code
, total
)
466 int code
, outer_code
;
472 *total
= mcore_const_costs (x
, outer_code
);
484 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
488 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
497 *total
= COSTS_N_INSNS (100);
505 /* Check to see if a comparison against a constant can be made more efficient
506 by incrementing/decrementing the constant to get one that is more efficient
510 mcore_modify_comparison (code
)
513 rtx op1
= arch_compare_op1
;
515 if (GET_CODE (op1
) == CONST_INT
)
517 int val
= INTVAL (op1
);
522 if (CONST_OK_FOR_J (val
+ 1))
524 arch_compare_op1
= GEN_INT (val
+ 1);
537 /* Prepare the operands for a comparison. */
540 mcore_gen_compare_reg (code
)
543 rtx op0
= arch_compare_op0
;
544 rtx op1
= arch_compare_op1
;
545 rtx cc_reg
= gen_rtx (REG
, CCmode
, CC_REG
);
547 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
548 op1
= force_reg (SImode
, op1
);
550 /* cmpnei: 0-31 (K immediate)
551 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
554 case EQ
: /* Use inverted condition, cmpne. */
558 case NE
: /* Use normal condition, cmpne. */
559 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
560 op1
= force_reg (SImode
, op1
);
563 case LE
: /* Use inverted condition, reversed cmplt. */
567 case GT
: /* Use normal condition, reversed cmplt. */
568 if (GET_CODE (op1
) == CONST_INT
)
569 op1
= force_reg (SImode
, op1
);
572 case GE
: /* Use inverted condition, cmplt. */
576 case LT
: /* Use normal condition, cmplt. */
577 if (GET_CODE (op1
) == CONST_INT
&&
578 /* covered by btsti x,31 */
580 ! CONST_OK_FOR_J (INTVAL (op1
)))
581 op1
= force_reg (SImode
, op1
);
584 case GTU
: /* Use inverted condition, cmple. */
585 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) == 0)
587 /* Unsigned > 0 is the same as != 0, but we need
588 to invert the condition, so we want to set
589 code = EQ. This cannot be done however, as the
590 mcore does not support such a test. Instead we
591 cope with this case in the "bgtu" pattern itself
592 so we should never reach this point. */
600 case LEU
: /* Use normal condition, reversed cmphs. */
601 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
602 op1
= force_reg (SImode
, op1
);
605 case LTU
: /* Use inverted condition, cmphs. */
609 case GEU
: /* Use normal condition, cmphs. */
610 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
611 op1
= force_reg (SImode
, op1
);
618 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
, gen_rtx (code
, CCmode
, op0
, op1
)));
625 mcore_symbolic_address_p (x
)
628 switch (GET_CODE (x
))
635 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
636 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
637 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
644 mcore_call_address_operand (x
, mode
)
646 enum machine_mode mode
;
648 return register_operand (x
, mode
) || CONSTANT_P (x
);
651 /* Functions to output assembly code for a function call. */
654 mcore_output_call (operands
, index
)
658 static char buffer
[20];
659 rtx addr
= operands
[index
];
665 if (mcore_current_function_name
== 0)
668 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
672 sprintf (buffer
, "jsr\t%%%d", index
);
678 if (mcore_current_function_name
== 0)
681 if (GET_CODE (addr
) != SYMBOL_REF
)
684 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, XSTR (addr
, 0), 0);
687 sprintf (buffer
, "jbsr\t%%%d", index
);
693 /* Can we load a constant with a single instruction ? */
696 const_ok_for_mcore (value
)
699 if (value
>= 0 && value
<= 127)
702 /* Try exact power of two. */
703 if ((value
& (value
- 1)) == 0)
706 /* Try exact power of two - 1. */
707 if ((value
& (value
+ 1)) == 0)
713 /* Can we load a constant inline with up to 2 instructions ? */
716 mcore_const_ok_for_inline (value
)
721 return try_constant_tricks (value
, & x
, & y
) > 0;
724 /* Are we loading the constant using a not ? */
727 mcore_const_trick_uses_not (value
)
732 return try_constant_tricks (value
, & x
, & y
) == 2;
735 /* Try tricks to load a constant inline and return the trick number if
736 success (0 is non-inlinable).
739 1: single instruction (do the usual thing)
740 2: single insn followed by a 'not'
741 3: single insn followed by a subi
742 4: single insn followed by an addi
743 5: single insn followed by rsubi
744 6: single insn followed by bseti
745 7: single insn followed by bclri
746 8: single insn followed by rotli
747 9: single insn followed by lsli
748 10: single insn followed by ixh
749 11: single insn followed by ixw. */
752 try_constant_tricks (value
, x
, y
)
758 unsigned bit
, shf
, rot
;
760 if (const_ok_for_mcore (value
))
761 return 1; /* Do the usual thing. */
765 if (const_ok_for_mcore (~value
))
771 for (i
= 1; i
<= 32; i
++)
773 if (const_ok_for_mcore (value
- i
))
781 if (const_ok_for_mcore (value
+ i
))
792 for (i
= 0; i
<= 31; i
++)
794 if (const_ok_for_mcore (i
- value
))
802 if (const_ok_for_mcore (value
& ~bit
))
810 if (const_ok_for_mcore (value
| bit
))
824 for (i
= 1; i
< 31; i
++)
828 /* MCore has rotate left. */
832 rot
|= c
; /* Simulate rotate. */
834 if (const_ok_for_mcore (rot
))
843 shf
= 0; /* Can't use logical shift, low order bit is one. */
847 if (shf
!= 0 && const_ok_for_mcore (shf
))
856 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
863 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
875 /* Check whether reg is dead at first. This is done by searching ahead
876 for either the next use (i.e., reg is live), a death note, or a set of
877 reg. Don't just use dead_or_set_p() since reload does not always mark
878 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
879 can ignore subregs by extracting the actual register. BRC */
882 mcore_is_dead (first
, reg
)
888 /* For mcore, subregs can't live independently of their parent regs. */
889 if (GET_CODE (reg
) == SUBREG
)
890 reg
= SUBREG_REG (reg
);
892 /* Dies immediately. */
893 if (dead_or_set_p (first
, reg
))
896 /* Look for conclusive evidence of live/death, otherwise we have
897 to assume that it is live. */
898 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
900 if (GET_CODE (insn
) == JUMP_INSN
)
901 return 0; /* We lose track, assume it is alive. */
903 else if (GET_CODE(insn
) == CALL_INSN
)
905 /* Call's might use it for target or register parms. */
906 if (reg_referenced_p (reg
, PATTERN (insn
))
907 || find_reg_fusage (insn
, USE
, reg
))
909 else if (dead_or_set_p (insn
, reg
))
912 else if (GET_CODE (insn
) == INSN
)
914 if (reg_referenced_p (reg
, PATTERN (insn
)))
916 else if (dead_or_set_p (insn
, reg
))
921 /* No conclusive evidence either way, we can not take the chance
922 that control flow hid the use from us -- "I'm not dead yet". */
927 /* Count the number of ones in mask. */
930 mcore_num_ones (mask
)
933 /* A trick to count set bits recently posted on comp.compilers. */
934 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
935 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
936 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
937 mask
= ((mask
>> 8) + mask
);
939 return (mask
+ (mask
>> 16)) & 0xff;
942 /* Count the number of zeros in mask. */
945 mcore_num_zeros (mask
)
948 return 32 - mcore_num_ones (mask
);
951 /* Determine byte being masked. */
954 mcore_byte_offset (mask
)
957 if (mask
== 0x00ffffffL
)
959 else if (mask
== 0xff00ffffL
)
961 else if (mask
== 0xffff00ffL
)
963 else if (mask
== 0xffffff00L
)
969 /* Determine halfword being masked. */
972 mcore_halfword_offset (mask
)
975 if (mask
== 0x0000ffffL
)
977 else if (mask
== 0xffff0000L
)
983 /* Output a series of bseti's corresponding to mask. */
986 mcore_output_bseti (dst
, mask
)
993 out_operands
[0] = dst
;
995 for (bit
= 0; bit
< 32; bit
++)
997 if ((mask
& 0x1) == 0x1)
999 out_operands
[1] = GEN_INT (bit
);
1001 output_asm_insn ("bseti\t%0,%1", out_operands
);
1009 /* Output a series of bclri's corresponding to mask. */
1012 mcore_output_bclri (dst
, mask
)
1016 rtx out_operands
[2];
1019 out_operands
[0] = dst
;
1021 for (bit
= 0; bit
< 32; bit
++)
1023 if ((mask
& 0x1) == 0x0)
1025 out_operands
[1] = GEN_INT (bit
);
1027 output_asm_insn ("bclri\t%0,%1", out_operands
);
1036 /* Output a conditional move of two constants that are +/- 1 within each
1037 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1038 really worth the effort. */
1041 mcore_output_cmov (operands
, cmp_t
, test
)
1048 rtx out_operands
[4];
1050 out_operands
[0] = operands
[0];
1052 /* Check to see which constant is loadable. */
1053 if (const_ok_for_mcore (INTVAL (operands
[1])))
1055 out_operands
[1] = operands
[1];
1056 out_operands
[2] = operands
[2];
1058 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1060 out_operands
[1] = operands
[2];
1061 out_operands
[2] = operands
[1];
1063 /* Complement test since constants are swapped. */
1064 cmp_t
= (cmp_t
== 0);
1066 load_value
= INTVAL (out_operands
[1]);
1067 adjust_value
= INTVAL (out_operands
[2]);
1069 /* First output the test if folded into the pattern. */
1072 output_asm_insn (test
, operands
);
1074 /* Load the constant - for now, only support constants that can be
1075 generated with a single instruction. maybe add general inlinable
1076 constants later (this will increase the # of patterns since the
1077 instruction sequence has a different length attribute). */
1078 if (load_value
>= 0 && load_value
<= 127)
1079 output_asm_insn ("movi\t%0,%1", out_operands
);
1080 else if ((load_value
& (load_value
- 1)) == 0)
1081 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1082 else if ((load_value
& (load_value
+ 1)) == 0)
1083 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1085 /* Output the constant adjustment. */
1086 if (load_value
> adjust_value
)
1089 output_asm_insn ("decf\t%0", out_operands
);
1091 output_asm_insn ("dect\t%0", out_operands
);
1096 output_asm_insn ("incf\t%0", out_operands
);
1098 output_asm_insn ("inct\t%0", out_operands
);
1104 /* Outputs the peephole for moving a constant that gets not'ed followed
1105 by an and (i.e. combine the not and the and into andn). BRC */
1108 mcore_output_andn (insn
, operands
)
1109 rtx insn ATTRIBUTE_UNUSED
;
1113 rtx out_operands
[3];
1114 const char * load_op
;
1117 if (try_constant_tricks (INTVAL (operands
[1]), &x
, &y
) != 2)
1120 out_operands
[0] = operands
[0];
1121 out_operands
[1] = GEN_INT(x
);
1122 out_operands
[2] = operands
[2];
1124 if (x
>= 0 && x
<= 127)
1125 load_op
= "movi\t%0,%1";
1127 /* Try exact power of two. */
1128 else if ((x
& (x
- 1)) == 0)
1129 load_op
= "bgeni\t%0,%P1";
1131 /* Try exact power of two - 1. */
1132 else if ((x
& (x
+ 1)) == 0)
1133 load_op
= "bmaski\t%0,%N1";
1136 load_op
= "BADMOVI\t%0,%1";
1138 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1139 output_asm_insn (buf
, out_operands
);
1144 /* Output an inline constant. */
1147 output_inline_const (mode
, operands
)
1148 enum machine_mode mode
;
1153 rtx out_operands
[3];
1156 const char *dst_fmt
;
1159 value
= INTVAL (operands
[1]);
1161 if ((trick_no
= try_constant_tricks (value
, &x
, &y
)) == 0)
1163 /* lrw's are handled separately: Large inlinable constants
1164 never get turned into lrw's. Our caller uses try_constant_tricks
1165 to back off to an lrw rather than calling this routine. */
1172 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1173 out_operands
[0] = operands
[0];
1174 out_operands
[1] = GEN_INT (x
);
1177 out_operands
[2] = GEN_INT (y
);
1179 /* Select dst format based on mode. */
1180 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1185 if (x
>= 0 && x
<= 127)
1186 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1188 /* Try exact power of two. */
1189 else if ((x
& (x
- 1)) == 0)
1190 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1192 /* Try exact power of two - 1. */
1193 else if ((x
& (x
+ 1)) == 0)
1194 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1197 sprintf (load_op
, "BADMOVI\t%s,%%1", dst_fmt
);
1202 strcpy (buf
, load_op
);
1205 sprintf (buf
, "%s\n\tnot\t%s\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1208 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1211 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1214 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1215 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1218 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1221 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1224 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1227 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1230 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %d 0x%x", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1233 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %d 0x%x", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1239 output_asm_insn (buf
, out_operands
);
1244 /* Output a move of a word or less value. */
1247 mcore_output_move (insn
, operands
, mode
)
1248 rtx insn ATTRIBUTE_UNUSED
;
1250 enum machine_mode mode ATTRIBUTE_UNUSED
;
1252 rtx dst
= operands
[0];
1253 rtx src
= operands
[1];
1255 if (GET_CODE (dst
) == REG
)
1257 if (GET_CODE (src
) == REG
)
1259 if (REGNO (src
) == CC_REG
) /* r-c */
1262 return "mov\t%0,%1"; /* r-r*/
1264 else if (GET_CODE (src
) == MEM
)
1266 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1267 return "lrw\t%0,[%1]"; /* a-R */
1269 return "ldw\t%0,%1"; /* r-m */
1271 else if (GET_CODE (src
) == CONST_INT
)
1275 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1276 return "movi\t%0,%1";
1277 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1278 return "bgeni\t%0,%P1\t// %1 %x1";
1279 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1280 return "bmaski\t%0,%N1\t// %1 %x1";
1281 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1282 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1284 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1287 return "lrw\t%0, %1"; /* Into the literal pool. */
1289 else if (GET_CODE (dst
) == MEM
) /* m-r */
1290 return "stw\t%1,%0";
1295 /* Outputs a constant inline -- regardless of the cost.
1296 Useful for things where we've gotten into trouble and think we'd
1297 be doing an lrw into r15 (forbidden). This lets us get out of
1298 that pickle even after register allocation. */
1301 mcore_output_inline_const_forced (insn
, operands
, mode
)
1302 rtx insn ATTRIBUTE_UNUSED
;
1304 enum machine_mode mode ATTRIBUTE_UNUSED
;
1306 unsigned long value
= INTVAL (operands
[1]);
1307 unsigned long ovalue
= value
;
1316 if (mcore_const_ok_for_inline (value
))
1317 return output_inline_const (SImode
, operands
);
1319 for (i
= 0; (unsigned) i
< ARRAY_SIZE (part
); i
++)
1322 part
[i
].low
= (value
& 0x1F);
1323 value
-= part
[i
].low
;
1325 if (mcore_const_ok_for_inline (value
))
1332 while ((value
& 1) == 0)
1338 if (mcore_const_ok_for_inline (value
))
1343 /* 5 bits per iteration, a maximum of 5 times == 25 bits and leaves
1344 7 bits left in the constant -- which we know we can cover with
1345 a movi. The final value can't be zero otherwise we'd have stopped
1346 in the previous iteration. */
1347 if (value
== 0 || ! mcore_const_ok_for_inline (value
))
1350 /* Now, work our way backwards emitting the constant. */
1352 /* Emit the value that remains -- it will be nonzero. */
1353 operands
[1] = GEN_INT (value
);
1354 output_asm_insn (output_inline_const (SImode
, operands
), operands
);
1358 /* Shift anything we've already loaded. */
1361 operands
[2] = GEN_INT (part
[i
].shift
);
1362 output_asm_insn ("lsli %0,%2", operands
);
1363 value
<<= part
[i
].shift
;
1366 /* Add anything we need into the low 5 bits. */
1367 if (part
[i
].low
!= 0)
1369 operands
[2] = GEN_INT (part
[i
].low
);
1370 output_asm_insn ("addi %0,%2", operands
);
1371 value
+= part
[i
].low
;
1377 if (value
!= ovalue
) /* sanity */
1380 /* We've output all the instructions. */
1384 /* Return a sequence of instructions to perform DI or DF move.
1385 Since the MCORE cannot move a DI or DF in one instruction, we have
1386 to take care when we see overlapping source and dest registers. */
1389 mcore_output_movedouble (operands
, mode
)
1391 enum machine_mode mode ATTRIBUTE_UNUSED
;
1393 rtx dst
= operands
[0];
1394 rtx src
= operands
[1];
1396 if (GET_CODE (dst
) == REG
)
1398 if (GET_CODE (src
) == REG
)
1400 int dstreg
= REGNO (dst
);
1401 int srcreg
= REGNO (src
);
1403 /* Ensure the second source not overwritten. */
1404 if (srcreg
+ 1 == dstreg
)
1405 return "mov %R0,%R1\n\tmov %0,%1";
1407 return "mov %0,%1\n\tmov %R0,%R1";
1409 else if (GET_CODE (src
) == MEM
)
1411 rtx memexp
= memexp
= XEXP (src
, 0);
1412 int dstreg
= REGNO (dst
);
1415 if (GET_CODE (memexp
) == LABEL_REF
)
1416 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1417 else if (GET_CODE (memexp
) == REG
)
1418 basereg
= REGNO (memexp
);
1419 else if (GET_CODE (memexp
) == PLUS
)
1421 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1422 basereg
= REGNO (XEXP (memexp
, 0));
1423 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1424 basereg
= REGNO (XEXP (memexp
, 1));
1431 /* ??? length attribute is wrong here. */
1432 if (dstreg
== basereg
)
1434 /* Just load them in reverse order. */
1435 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1437 /* XXX: alternative: move basereg to basereg+1
1438 and then fall through. */
1441 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1443 else if (GET_CODE (src
) == CONST_INT
)
1445 if (TARGET_LITTLE_END
)
1447 if (CONST_OK_FOR_I (INTVAL (src
)))
1448 output_asm_insn ("movi %0,%1", operands
);
1449 else if (CONST_OK_FOR_M (INTVAL (src
)))
1450 output_asm_insn ("bgeni %0,%P1", operands
);
1451 else if (INTVAL (src
) == -1)
1452 output_asm_insn ("bmaski %0,32", operands
);
1453 else if (CONST_OK_FOR_N (INTVAL (src
)))
1454 output_asm_insn ("bmaski %0,%N1", operands
);
1458 if (INTVAL (src
) < 0)
1459 return "bmaski %R0,32";
1461 return "movi %R0,0";
1465 if (CONST_OK_FOR_I (INTVAL (src
)))
1466 output_asm_insn ("movi %R0,%1", operands
);
1467 else if (CONST_OK_FOR_M (INTVAL (src
)))
1468 output_asm_insn ("bgeni %R0,%P1", operands
);
1469 else if (INTVAL (src
) == -1)
1470 output_asm_insn ("bmaski %R0,32", operands
);
1471 else if (CONST_OK_FOR_N (INTVAL (src
)))
1472 output_asm_insn ("bmaski %R0,%N1", operands
);
1476 if (INTVAL (src
) < 0)
1477 return "bmaski %0,32";
1485 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1486 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1491 /* Predicates used by the templates. */
1493 /* Nonzero if OP can be source of a simple move operation. */
1496 mcore_general_movsrc_operand (op
, mode
)
1498 enum machine_mode mode
;
1500 /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
1501 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1504 return general_operand (op
, mode
);
1507 /* Nonzero if OP can be destination of a simple move operation. */
1510 mcore_general_movdst_operand (op
, mode
)
1512 enum machine_mode mode
;
1514 if (GET_CODE (op
) == REG
&& REGNO (op
) == CC_REG
)
1517 return general_operand (op
, mode
);
1520 /* Nonzero if OP is a normal arithmetic register. */
1523 mcore_arith_reg_operand (op
, mode
)
1525 enum machine_mode mode
;
1527 if (! register_operand (op
, mode
))
1530 if (GET_CODE (op
) == SUBREG
)
1531 op
= SUBREG_REG (op
);
1533 if (GET_CODE (op
) == REG
)
1534 return REGNO (op
) != CC_REG
;
1539 /* Nonzero if OP should be recognized during reload for an ixh/ixw
1540 operand. See the ixh/ixw patterns. */
1543 mcore_reload_operand (op
, mode
)
1545 enum machine_mode mode
;
1547 if (mcore_arith_reg_operand (op
, mode
))
1550 if (! reload_in_progress
)
1553 return GET_CODE (op
) == MEM
;
1556 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1559 mcore_arith_J_operand (op
, mode
)
1561 enum machine_mode mode
;
1563 if (register_operand (op
, mode
))
1566 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (op
)))
1572 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1575 mcore_arith_K_operand (op
, mode
)
1577 enum machine_mode mode
;
1579 if (register_operand (op
, mode
))
1582 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
1588 /* Nonzero if OP is a valid source operand for a shift or rotate insn. */
1591 mcore_arith_K_operand_not_0 (op
, mode
)
1593 enum machine_mode mode
;
1595 if (register_operand (op
, mode
))
1598 if ( GET_CODE (op
) == CONST_INT
1599 && CONST_OK_FOR_K (INTVAL (op
))
1600 && INTVAL (op
) != 0)
1607 mcore_arith_K_S_operand (op
, mode
)
1609 enum machine_mode mode
;
1611 if (register_operand (op
, mode
))
1614 if (GET_CODE (op
) == CONST_INT
)
1616 if (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_M (~INTVAL (op
)))
1624 mcore_arith_S_operand (op
)
1627 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1634 mcore_arith_M_operand (op
, mode
)
1636 enum machine_mode mode
;
1638 if (register_operand (op
, mode
))
1641 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
1647 /* Nonzero if OP is a valid source operand for loading. */
1650 mcore_arith_imm_operand (op
, mode
)
1652 enum machine_mode mode
;
1654 if (register_operand (op
, mode
))
1657 if (GET_CODE (op
) == CONST_INT
&& const_ok_for_mcore (INTVAL (op
)))
1664 mcore_arith_any_imm_operand (op
, mode
)
1666 enum machine_mode mode
;
1668 if (register_operand (op
, mode
))
1671 if (GET_CODE (op
) == CONST_INT
)
1677 /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */
1680 mcore_arith_O_operand (op
, mode
)
1682 enum machine_mode mode
;
1684 if (register_operand (op
, mode
))
1687 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_O (INTVAL (op
)))
1693 /* Nonzero if OP is a valid source operand for a btsti. */
1696 mcore_literal_K_operand (op
, mode
)
1698 enum machine_mode mode ATTRIBUTE_UNUSED
;
1700 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
1706 /* Nonzero if OP is a valid source operand for an add/sub insn. */
1709 mcore_addsub_operand (op
, mode
)
1711 enum machine_mode mode
;
1713 if (register_operand (op
, mode
))
1716 if (GET_CODE (op
) == CONST_INT
)
1720 /* The following is removed because it precludes large constants from being
1721 returned as valid source operands for and add/sub insn. While large
1722 constants may not directly be used in an add/sub, they may if first loaded
1723 into a register. Thus, this predicate should indicate that they are valid,
1724 and the constraint in mcore.md should control whether an additional load to
1725 register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
1727 if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
1735 /* Nonzero if OP is a valid source operand for a compare operation. */
1738 mcore_compare_operand (op
, mode
)
1740 enum machine_mode mode
;
1742 if (register_operand (op
, mode
))
1745 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
1751 /* Expand insert bit field. BRC */
1754 mcore_expand_insv (operands
)
1757 int width
= INTVAL (operands
[1]);
1758 int posn
= INTVAL (operands
[2]);
1760 rtx mreg
, sreg
, ereg
;
1762 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1763 for width==1 must be removed. Look around line 368. This is something
1764 we really want the md part to do. */
1765 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1767 /* Do directly with bseti or bclri. */
1768 /* RBE: 2/97 consider only low bit of constant. */
1769 if ((INTVAL(operands
[3])&1) == 0)
1771 mask
= ~(1 << posn
);
1772 emit_insn (gen_rtx (SET
, SImode
, operands
[0],
1773 gen_rtx (AND
, SImode
, operands
[0], GEN_INT (mask
))));
1778 emit_insn (gen_rtx (SET
, SImode
, operands
[0],
1779 gen_rtx (IOR
, SImode
, operands
[0], GEN_INT (mask
))));
1785 /* Look at some bit-field placements that we aren't interested
1786 in handling ourselves, unless specifically directed to do so. */
1787 if (! TARGET_W_FIELD
)
1788 return 0; /* Generally, give up about now. */
1790 if (width
== 8 && posn
% 8 == 0)
1791 /* Byte sized and aligned; let caller break it up. */
1794 if (width
== 16 && posn
% 16 == 0)
1795 /* Short sized and aligned; let caller break it up. */
1798 /* The general case - we can do this a little bit better than what the
1799 machine independent part tries. This will get rid of all the subregs
1800 that mess up constant folding in combine when working with relaxed
1803 /* If setting the entire field, do it directly. */
1804 if (GET_CODE (operands
[3]) == CONST_INT
&&
1805 INTVAL (operands
[3]) == ((1 << width
) - 1))
1807 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1808 emit_insn (gen_rtx (SET
, SImode
, operands
[0],
1809 gen_rtx (IOR
, SImode
, operands
[0], mreg
)));
1813 /* Generate the clear mask. */
1814 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1816 /* Clear the field, to overlay it later with the source. */
1817 emit_insn (gen_rtx (SET
, SImode
, operands
[0],
1818 gen_rtx (AND
, SImode
, operands
[0], mreg
)));
1820 /* If the source is constant 0, we've nothing to add back. */
1821 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1824 /* XXX: Should we worry about more games with constant values?
1825 We've covered the high profile: set/clear single-bit and many-bit
1826 fields. How often do we see "arbitrary bit pattern" constants? */
1827 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1829 /* Extract src as same width as dst (needed for signed values). We
1830 always have to do this since we widen everything to SImode.
1831 We don't have to mask if we're shifting this up against the
1832 MSB of the register (e.g., the shift will push out any hi-order
1834 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1836 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1837 emit_insn (gen_rtx (SET
, SImode
, sreg
,
1838 gen_rtx (AND
, SImode
, sreg
, ereg
)));
1841 /* Insert source value in dest. */
1843 emit_insn (gen_rtx (SET
, SImode
, sreg
,
1844 gen_rtx (ASHIFT
, SImode
, sreg
, GEN_INT (posn
))));
1846 emit_insn (gen_rtx (SET
, SImode
, operands
[0],
1847 gen_rtx (IOR
, SImode
, operands
[0], sreg
)));
1852 /* Return 1 if OP is a load multiple operation. It is known to be a
1853 PARALLEL and the first section will be tested. */
1855 mcore_load_multiple_operation (op
, mode
)
1857 enum machine_mode mode ATTRIBUTE_UNUSED
;
1859 int count
= XVECLEN (op
, 0);
1864 /* Perform a quick check so we don't blow up below. */
1866 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
1867 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
1868 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
1871 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
1872 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
1874 for (i
= 1; i
< count
; i
++)
1876 rtx elt
= XVECEXP (op
, 0, i
);
1878 if (GET_CODE (elt
) != SET
1879 || GET_CODE (SET_DEST (elt
)) != REG
1880 || GET_MODE (SET_DEST (elt
)) != SImode
1881 || REGNO (SET_DEST (elt
)) != (unsigned) (dest_regno
+ i
)
1882 || GET_CODE (SET_SRC (elt
)) != MEM
1883 || GET_MODE (SET_SRC (elt
)) != SImode
1884 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
1885 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
1886 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
1887 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
1894 /* Similar, but tests for store multiple. */
1897 mcore_store_multiple_operation (op
, mode
)
1899 enum machine_mode mode ATTRIBUTE_UNUSED
;
1901 int count
= XVECLEN (op
, 0);
1906 /* Perform a quick check so we don't blow up below. */
1908 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
1909 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
1910 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
1913 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
1914 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
1916 for (i
= 1; i
< count
; i
++)
1918 rtx elt
= XVECEXP (op
, 0, i
);
1920 if (GET_CODE (elt
) != SET
1921 || GET_CODE (SET_SRC (elt
)) != REG
1922 || GET_MODE (SET_SRC (elt
)) != SImode
1923 || REGNO (SET_SRC (elt
)) != (unsigned) (src_regno
+ i
)
1924 || GET_CODE (SET_DEST (elt
)) != MEM
1925 || GET_MODE (SET_DEST (elt
)) != SImode
1926 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
1927 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
1928 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
1929 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
1936 /* ??? Block move stuff stolen from m88k. This code has not been
1937 verified for correctness. */
1939 /* Emit code to perform a block move. Choose the best method.
1941 OPERANDS[0] is the destination.
1942 OPERANDS[1] is the source.
1943 OPERANDS[2] is the size.
1944 OPERANDS[3] is the alignment safe to use. */
1946 /* Emit code to perform a block move with an offset sequence of ldw/st
1947 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1948 known constants. DEST and SRC are registers. OFFSET is the known
1949 starting point for the output pattern. */
1951 static const enum machine_mode mode_from_align
[] =
1953 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1954 VOIDmode
, VOIDmode
, VOIDmode
, DImode
1958 block_move_sequence (dest
, dst_mem
, src
, src_mem
, size
, align
, offset
)
1966 enum machine_mode mode
[2];
1971 int offset_ld
= offset
;
1972 int offset_st
= offset
;
1974 active
[0] = active
[1] = FALSE
;
1976 /* Establish parameters for the first load and for the second load if
1977 it is known to be the same mode as the first. */
1978 amount
[0] = amount
[1] = align
;
1980 mode
[0] = mode_from_align
[align
];
1982 temp
[0] = gen_reg_rtx (mode
[0]);
1984 if (size
>= 2 * align
)
1987 temp
[1] = gen_reg_rtx (mode
[1]);
1999 /* Change modes as the sequence tails off. */
2000 if (size
< amount
[next
])
2002 amount
[next
] = (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
2003 mode
[next
] = mode_from_align
[amount
[next
]];
2004 temp
[next
] = gen_reg_rtx (mode
[next
]);
2007 size
-= amount
[next
];
2008 srcp
= gen_rtx (MEM
,
2010 MEM_IN_STRUCT_P (src_mem
) ? mode
[next
] : BLKmode
,
2014 gen_rtx (PLUS
, Pmode
, src
,
2015 gen_rtx (CONST_INT
, SImode
, offset_ld
)));
2017 RTX_UNCHANGING_P (srcp
) = RTX_UNCHANGING_P (src_mem
);
2018 MEM_VOLATILE_P (srcp
) = MEM_VOLATILE_P (src_mem
);
2019 MEM_IN_STRUCT_P (srcp
) = 1;
2020 emit_insn (gen_rtx (SET
, VOIDmode
, temp
[next
], srcp
));
2021 offset_ld
+= amount
[next
];
2022 active
[next
] = TRUE
;
2027 active
[phase
] = FALSE
;
2029 dstp
= gen_rtx (MEM
,
2031 MEM_IN_STRUCT_P (dst_mem
) ? mode
[phase
] : BLKmode
,
2035 gen_rtx (PLUS
, Pmode
, dest
,
2036 gen_rtx (CONST_INT
, SImode
, offset_st
)));
2038 RTX_UNCHANGING_P (dstp
) = RTX_UNCHANGING_P (dst_mem
);
2039 MEM_VOLATILE_P (dstp
) = MEM_VOLATILE_P (dst_mem
);
2040 MEM_IN_STRUCT_P (dstp
) = 1;
2041 emit_insn (gen_rtx (SET
, VOIDmode
, dstp
, temp
[phase
]));
2042 offset_st
+= amount
[phase
];
2045 while (active
[next
]);
2049 mcore_expand_block_move (dst_mem
, src_mem
, operands
)
2054 int align
= INTVAL (operands
[3]);
2057 if (GET_CODE (operands
[2]) == CONST_INT
)
2059 bytes
= INTVAL (operands
[2]);
2066 /* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before
2067 we give up and go to memcpy. */
2068 if ((align
== 4 && (bytes
<= 4*4
2069 || ((bytes
& 01) == 0 && bytes
<= 8*4)
2070 || ((bytes
& 03) == 0 && bytes
<= 16*4)))
2071 || (align
== 2 && bytes
<= 4*2)
2072 || (align
== 1 && bytes
<= 4*1))
2074 block_move_sequence (operands
[0], dst_mem
, operands
[1], src_mem
,
2080 /* If we get here, just use the library routine. */
2081 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0, VOIDmode
, 3,
2082 operands
[0], Pmode
, operands
[1], Pmode
, operands
[2],
2087 /* Code to generate prologue and epilogue sequences. */
2088 static int number_of_regs_before_varargs
;
2090 /* Set by SETUP_INCOMING_VARARGS to indicate to prolog that this is
2091 for a varargs function. */
2092 static int current_function_anonymous_args
;
2094 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
2095 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
2096 #define ADDI_REACH (32) /* Maximum addi operand. */
2099 layout_mcore_frame (infp
)
2100 struct mcore_frame
* infp
;
2109 unsigned int growths
;
2112 /* Might have to spill bytes to re-assemble a big argument that
2113 was passed partially in registers and partially on the stack. */
2114 nbytes
= current_function_pretend_args_size
;
2116 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
2117 if (current_function_anonymous_args
)
2118 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
2120 infp
->arg_size
= nbytes
;
2122 /* How much space to save non-volatile registers we stomp. */
2123 infp
->reg_mask
= calc_live_regs (& n
);
2124 infp
->reg_size
= n
* 4;
2126 /* And the rest of it... locals and space for overflowed outbounds. */
2127 infp
->local_size
= get_frame_size ();
2128 infp
->outbound_size
= current_function_outgoing_args_size
;
2130 /* Make sure we have a whole number of words for the locals. */
2131 if (infp
->local_size
% STACK_BYTES
)
2132 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
2134 /* Only thing we know we have to pad is the outbound space, since
2135 we've aligned our locals assuming that base of locals is aligned. */
2136 infp
->pad_local
= 0;
2138 infp
->pad_outbound
= 0;
2139 if (infp
->outbound_size
% STACK_BYTES
)
2140 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
2142 /* Now we see how we want to stage the prologue so that it does
2143 the most appropriate stack growth and register saves to either:
2145 (2) reduce instruction space, or
2146 (3) reduce stack space. */
2147 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
2148 infp
->growth
[i
] = 0;
2150 regarg
= infp
->reg_size
+ infp
->arg_size
;
2151 localregarg
= infp
->local_size
+ regarg
;
2152 localreg
= infp
->local_size
+ infp
->reg_size
;
2153 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
2156 /* XXX: Consider one where we consider localregarg + outbound too! */
2158 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
2159 use stw's with offsets and buy the frame in one shot. */
2160 if (localregarg
<= ADDI_REACH
2161 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
2163 /* Make sure we'll be aligned. */
2164 if (localregarg
% STACK_BYTES
)
2165 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
2167 step
= localregarg
+ infp
->pad_reg
;
2168 infp
->reg_offset
= infp
->local_size
;
2170 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
2173 infp
->reg_offset
+= outbounds
;
2177 infp
->arg_offset
= step
- 4;
2178 infp
->growth
[growths
++] = step
;
2179 infp
->reg_growth
= growths
;
2180 infp
->local_growth
= growths
;
2182 /* If we haven't already folded it in. */
2184 infp
->growth
[growths
++] = outbounds
;
2189 /* Frame can't be done with a single subi, but can be done with 2
2190 insns. If the 'stm' is getting <= 2 registers, we use stw's and
2191 shift some of the stack purchase into the first subi, so both are
2192 single instructions. */
2193 if (localregarg
<= STORE_REACH
2194 && (infp
->local_size
> ADDI_REACH
)
2195 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
2199 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
2200 if (localregarg
% STACK_BYTES
)
2201 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
2203 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
2204 step
= ADDI_REACH
; /* As much up front as we can. */
2208 /* XXX: Consider whether step will still be aligned; we believe so. */
2209 infp
->arg_offset
= step
- 4;
2210 infp
->growth
[growths
++] = step
;
2211 infp
->reg_growth
= growths
;
2212 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
2215 /* Can we fold in any space required for outbounds? */
2216 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
2222 /* Get the rest of the locals in place. */
2224 infp
->growth
[growths
++] = step
;
2225 infp
->local_growth
= growths
;
2230 /* Finish off if we need to do so. */
2232 infp
->growth
[growths
++] = outbounds
;
2237 /* Registers + args is nicely aligned, so we'll buy that in one shot.
2238 Then we buy the rest of the frame in 1 or 2 steps depending on
2239 whether we need a frame pointer. */
2240 if ((regarg
% STACK_BYTES
) == 0)
2242 infp
->growth
[growths
++] = regarg
;
2243 infp
->reg_growth
= growths
;
2244 infp
->arg_offset
= regarg
- 4;
2245 infp
->reg_offset
= 0;
2247 if (infp
->local_size
% STACK_BYTES
)
2248 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
2250 step
= infp
->local_size
+ infp
->pad_local
;
2252 if (!frame_pointer_needed
)
2258 infp
->growth
[growths
++] = step
;
2259 infp
->local_growth
= growths
;
2261 /* If there's any left to be done. */
2263 infp
->growth
[growths
++] = outbounds
;
2268 /* XXX: optimizations that we'll want to play with....
2269 -- regarg is not aligned, but it's a small number of registers;
2270 use some of localsize so that regarg is aligned and then
2271 save the registers. */
2273 /* Simple encoding; plods down the stack buying the pieces as it goes.
2274 -- does not optimize space consumption.
2275 -- does not attempt to optimize instruction counts.
2276 -- but it is safe for all alignments. */
2277 if (regarg
% STACK_BYTES
!= 0)
2278 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
2280 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
2281 infp
->reg_growth
= growths
;
2282 infp
->arg_offset
= infp
->growth
[0] - 4;
2283 infp
->reg_offset
= 0;
2285 if (frame_pointer_needed
)
2287 if (infp
->local_size
% STACK_BYTES
!= 0)
2288 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
2290 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
2291 infp
->local_growth
= growths
;
2293 infp
->growth
[growths
++] = outbounds
;
2297 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
2298 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
2300 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
2301 infp
->local_growth
= growths
;
2304 /* Anything else that we've forgotten?, plus a few consistency checks. */
2306 assert (infp
->reg_offset
>= 0);
2307 assert (growths
<= MAX_STACK_GROWS
);
2309 for (i
= 0; i
< growths
; i
++)
2311 if (infp
->growth
[i
] % STACK_BYTES
)
2313 fprintf (stderr
,"stack growth of %d is not %d aligned\n",
2314 infp
->growth
[i
], STACK_BYTES
);
2320 /* Define the offset between two registers, one to be eliminated, and
2321 the other its replacement, at the start of a routine. */
2324 mcore_initial_elimination_offset (from
, to
)
2330 struct mcore_frame fi
;
2332 layout_mcore_frame (& fi
);
2335 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
2337 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
2339 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
2342 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
2343 return above_frame
+ below_frame
;
2345 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
2353 /* Keep track of some information about varargs for the prolog. */
2356 mcore_setup_incoming_varargs (args_so_far
, mode
, type
, ptr_pretend_size
)
2357 CUMULATIVE_ARGS args_so_far
;
2358 enum machine_mode mode
;
2360 int * ptr_pretend_size ATTRIBUTE_UNUSED
;
2362 current_function_anonymous_args
= 1;
2364 /* We need to know how many argument registers are used before
2365 the varargs start, so that we can push the remaining argument
2366 registers during the prologue. */
2367 number_of_regs_before_varargs
= args_so_far
+ mcore_num_arg_regs (mode
, type
);
2369 /* There is a bug somwehere in the arg handling code.
2370 Until I can find it this workaround always pushes the
2371 last named argument onto the stack. */
2372 number_of_regs_before_varargs
= args_so_far
;
2374 /* The last named argument may be split between argument registers
2375 and the stack. Allow for this here. */
2376 if (number_of_regs_before_varargs
> NPARM_REGS
)
2377 number_of_regs_before_varargs
= NPARM_REGS
;
2381 mcore_expand_prolog ()
2383 struct mcore_frame fi
;
2384 int space_allocated
= 0;
2387 /* Find out what we're doing. */
2388 layout_mcore_frame (&fi
);
2390 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
2391 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
2395 /* Emit a symbol for this routine's frame size. */
2398 x
= DECL_RTL (current_function_decl
);
2400 if (GET_CODE (x
) != MEM
)
2405 if (GET_CODE (x
) != SYMBOL_REF
)
2408 if (mcore_current_function_name
)
2409 free (mcore_current_function_name
);
2411 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
2413 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
2415 if (current_function_calls_alloca
)
2416 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
2419 We're looking at how the 8byte alignment affects stack layout
2420 and where we had to pad things. This emits information we can
2421 extract which tells us about frame sizes and the like. */
2422 fprintf (asm_out_file
,
2423 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2424 mcore_current_function_name
,
2425 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
2426 fi
.local_size
, fi
.outbound_size
,
2427 frame_pointer_needed
);
2430 if (mcore_naked_function_p ())
2433 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2434 output_stack_adjust (-1, fi
.growth
[growth
++]); /* grows it */
2436 /* If we have a parameter passed partially in regs and partially in memory,
2437 the registers will have been stored to memory already in function.c. So
2438 we only need to do something here for varargs functions. */
2439 if (fi
.arg_size
!= 0 && current_function_pretend_args_size
== 0)
2442 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
2443 int remaining
= fi
.arg_size
;
2445 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2447 emit_insn (gen_movsi
2448 (gen_rtx (MEM
, SImode
,
2449 plus_constant (stack_pointer_rtx
, offset
)),
2450 gen_rtx (REG
, SImode
, rn
)));
2454 /* Do we need another stack adjustment before we do the register saves? */
2455 if (growth
< fi
.reg_growth
)
2456 output_stack_adjust (-1, fi
.growth
[growth
++]); /* grows it */
2458 if (fi
.reg_size
!= 0)
2461 int offs
= fi
.reg_offset
;
2463 for (i
= 15; i
>= 0; i
--)
2465 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2469 while (fi
.reg_mask
& (1 << first_reg
))
2473 emit_insn (gen_store_multiple (gen_rtx (MEM
, SImode
, stack_pointer_rtx
),
2474 gen_rtx (REG
, SImode
, first_reg
),
2475 GEN_INT (16 - first_reg
)));
2477 i
-= (15 - first_reg
);
2478 offs
+= (16 - first_reg
) * 4;
2480 else if (fi
.reg_mask
& (1 << i
))
2482 emit_insn (gen_movsi
2483 (gen_rtx (MEM
, SImode
,
2484 plus_constant (stack_pointer_rtx
, offs
)),
2485 gen_rtx (REG
, SImode
, i
)));
2491 /* Figure the locals + outbounds. */
2492 if (frame_pointer_needed
)
2494 /* If we haven't already purchased to 'fp'. */
2495 if (growth
< fi
.local_growth
)
2496 output_stack_adjust (-1, fi
.growth
[growth
++]); /* grows it */
2498 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2500 /* ... and then go any remaining distance for outbounds, etc. */
2501 if (fi
.growth
[growth
])
2502 output_stack_adjust (-1, fi
.growth
[growth
++]);
2506 if (growth
< fi
.local_growth
)
2507 output_stack_adjust (-1, fi
.growth
[growth
++]); /* grows it */
2508 if (fi
.growth
[growth
])
2509 output_stack_adjust (-1, fi
.growth
[growth
++]);
2514 mcore_expand_epilog ()
2516 struct mcore_frame fi
;
2519 int growth
= MAX_STACK_GROWS
- 1 ;
2522 /* Find out what we're doing. */
2523 layout_mcore_frame(&fi
);
2525 if (mcore_naked_function_p ())
2528 /* If we had a frame pointer, restore the sp from that. */
2529 if (frame_pointer_needed
)
2531 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2532 growth
= fi
.local_growth
- 1;
2536 /* XXX: while loop should accumulate and do a single sell. */
2537 while (growth
>= fi
.local_growth
)
2539 if (fi
.growth
[growth
] != 0)
2540 output_stack_adjust (1, fi
.growth
[growth
]);
2545 /* Make sure we've shrunk stack back to the point where the registers
2546 were laid down. This is typically 0/1 iterations. Then pull the
2547 register save information back off the stack. */
2548 while (growth
>= fi
.reg_growth
)
2549 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2551 offs
= fi
.reg_offset
;
2553 for (i
= 15; i
>= 0; i
--)
2555 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2559 /* Find the starting register. */
2562 while (fi
.reg_mask
& (1 << first_reg
))
2567 emit_insn (gen_load_multiple (gen_rtx (REG
, SImode
, first_reg
),
2568 gen_rtx (MEM
, SImode
, stack_pointer_rtx
),
2569 GEN_INT (16 - first_reg
)));
2571 i
-= (15 - first_reg
);
2572 offs
+= (16 - first_reg
) * 4;
2574 else if (fi
.reg_mask
& (1 << i
))
2576 emit_insn (gen_movsi
2577 (gen_rtx (REG
, SImode
, i
),
2578 gen_rtx (MEM
, SImode
,
2579 plus_constant (stack_pointer_rtx
, offs
))));
2584 /* Give back anything else. */
2585 /* XXX: Should accumuate total and then give it back. */
2587 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2590 /* This code is borrowed from the SH port. */
2592 /* The MCORE cannot load a large constant into a register, constants have to
2593 come from a pc relative load. The reference of a pc relative load
2594 instruction must be less than 1k infront of the instruction. This
2595 means that we often have to dump a constant inside a function, and
2596 generate code to branch around it.
2598 It is important to minimize this, since the branches will slow things
2599 down and make things bigger.
2601 Worst case code looks like:
2617 We fix this by performing a scan before scheduling, which notices which
2618 instructions need to have their operands fetched from the constant table
2619 and builds the table.
2623 scan, find an instruction which needs a pcrel move. Look forward, find the
2624 last barrier which is within MAX_COUNT bytes of the requirement.
2625 If there isn't one, make one. Process all the instructions between
2626 the find and the barrier.
2628 In the above example, we can tell that L3 is within 1k of L1, so
2629 the first move can be shrunk from the 2 insn+constant sequence into
2630 just 1 insn, and the constant moved to L3 to make:
2640 Then the second move becomes the target for the shortening process. */
2644 rtx value
; /* Value in table. */
2645 rtx label
; /* Label of value. */
2648 /* The maximum number of constants that can fit into one pool, since
2649 the pc relative range is 0...1020 bytes and constants are at least 4
2650 bytes long. We subtact 4 from the range to allow for the case where
2651 we need to add a branch/align before the constant pool. */
2653 #define MAX_COUNT 1016
2654 #define MAX_POOL_SIZE (MAX_COUNT/4)
2655 static pool_node pool_vector
[MAX_POOL_SIZE
];
2656 static int pool_size
;
2658 /* Dump out any constants accumulated in the final pass. These
2659 will only be labels. */
2662 mcore_output_jump_label_table ()
2668 fprintf (asm_out_file
, "\t.align 2\n");
2670 for (i
= 0; i
< pool_size
; i
++)
2672 pool_node
* p
= pool_vector
+ i
;
2674 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2676 output_asm_insn (".long %0", &p
->value
);
2685 /* Check whether insn is a candidate for a conditional. */
2688 is_cond_candidate (insn
)
2691 /* The only things we conditionalize are those that can be directly
2692 changed into a conditional. Only bother with SImode items. If
2693 we wanted to be a little more aggressive, we could also do other
2694 modes such as DImode with reg-reg move or load 0. */
2695 if (GET_CODE (insn
) == INSN
)
2697 rtx pat
= PATTERN (insn
);
2700 if (GET_CODE (pat
) != SET
)
2703 dst
= XEXP (pat
, 0);
2705 if ((GET_CODE (dst
) != REG
&&
2706 GET_CODE (dst
) != SUBREG
) ||
2707 GET_MODE (dst
) != SImode
)
2710 src
= XEXP (pat
, 1);
2712 if ((GET_CODE (src
) == REG
||
2713 (GET_CODE (src
) == SUBREG
&&
2714 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2715 GET_MODE (src
) == SImode
)
2716 return COND_MOV_INSN
;
2717 else if (GET_CODE (src
) == CONST_INT
&&
2719 return COND_CLR_INSN
;
2720 else if (GET_CODE (src
) == PLUS
&&
2721 (GET_CODE (XEXP (src
, 0)) == REG
||
2722 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2723 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2724 GET_MODE (XEXP (src
, 0)) == SImode
&&
2725 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2726 INTVAL (XEXP (src
, 1)) == 1)
2727 return COND_INC_INSN
;
2728 else if (((GET_CODE (src
) == MINUS
&&
2729 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2730 INTVAL( XEXP (src
, 1)) == 1) ||
2731 (GET_CODE (src
) == PLUS
&&
2732 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2733 INTVAL (XEXP (src
, 1)) == -1)) &&
2734 (GET_CODE (XEXP (src
, 0)) == REG
||
2735 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2736 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2737 GET_MODE (XEXP (src
, 0)) == SImode
)
2738 return COND_DEC_INSN
;
2740 /* some insns that we don't bother with:
2741 (set (rx:DI) (ry:DI))
2742 (set (rx:DI) (const_int 0))
2746 else if (GET_CODE (insn
) == JUMP_INSN
&&
2747 GET_CODE (PATTERN (insn
)) == SET
&&
2748 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2749 return COND_BRANCH_INSN
;
2754 /* Emit a conditional version of insn and replace the old insn with the
2755 new one. Return the new insn if emitted. */
2758 emit_new_cond_insn (insn
, cond
)
2766 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2769 pat
= PATTERN (insn
);
2771 if (GET_CODE (insn
) == INSN
)
2773 dst
= SET_DEST (pat
);
2774 src
= SET_SRC (pat
);
2778 dst
= JUMP_LABEL (insn
);
2787 c_insn
= gen_movt0 (dst
, src
, dst
);
2789 c_insn
= gen_movt0 (dst
, dst
, src
);
2794 c_insn
= gen_incscc (dst
, dst
);
2796 c_insn
= gen_incscc_false (dst
, dst
);
2801 c_insn
= gen_decscc (dst
, dst
);
2803 c_insn
= gen_decscc_false (dst
, dst
);
2806 case COND_BRANCH_INSN
:
2808 c_insn
= gen_branch_true (dst
);
2810 c_insn
= gen_branch_false (dst
);
2817 /* Only copy the notes if they exist. */
2818 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2820 /* We really don't need to bother with the notes and links at this
2821 point, but go ahead and save the notes. This will help is_dead()
2822 when applying peepholes (links don't matter since they are not
2823 used any more beyond this point for the mcore). */
2824 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2827 if (num
== COND_BRANCH_INSN
)
2829 /* For jumps, we need to be a little bit careful and emit the new jump
2830 before the old one and to update the use count for the target label.
2831 This way, the barrier following the old (uncond) jump will get
2832 deleted, but the label won't. */
2833 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2835 ++ LABEL_NUSES (dst
);
2837 JUMP_LABEL (c_insn
) = dst
;
2840 c_insn
= emit_insn_after (c_insn
, insn
);
2847 /* Attempt to change a basic block into a series of conditional insns. This
2848 works by taking the branch at the end of the 1st block and scanning for the
2849 end of the 2nd block. If all instructions in the 2nd block have cond.
2850 versions and the label at the start of block 3 is the same as the target
2851 from the branch at block 1, then conditionalize all insn in block 2 using
2852 the inverse condition of the branch at block 1. (Note I'm bending the
2853 definition of basic block here.)
2857 bt L2 <-- end of block 1 (delete)
2860 br L3 <-- end of block 2
2862 L2: ... <-- start of block 3 (NUSES==1)
2873 we can delete the L2 label if NUSES==1 and re-apply the optimization
2874 starting at the last instruction of block 2. This may allow an entire
2875 if-then-else statement to be conditionalized. BRC */
2877 conditionalize_block (first
)
2882 rtx end_blk_1_br
= 0;
2883 rtx end_blk_2_insn
= 0;
2884 rtx start_blk_3_lab
= 0;
2890 /* Check that the first insn is a candidate conditional jump. This is
2891 the one that we'll eliminate. If not, advance to the next insn to
2893 if (GET_CODE (first
) != JUMP_INSN
||
2894 GET_CODE (PATTERN (first
)) != SET
||
2895 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2896 return NEXT_INSN (first
);
2898 /* Extract some information we need. */
2899 end_blk_1_br
= first
;
2900 br_pat
= PATTERN (end_blk_1_br
);
2902 /* Complement the condition since we use the reverse cond. for the insns. */
2903 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2905 /* Determine what kind of branch we have. */
2906 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2908 /* A normal branch, so extract label out of first arm. */
2909 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2913 /* An inverse branch, so extract the label out of the 2nd arm
2914 and complement the condition. */
2916 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2919 /* Scan forward for the start of block 2: it must start with a
2920 label and that label must be the same as the branch target
2921 label from block 1. We don't care about whether block 2 actually
2922 ends with a branch or a label (an uncond. branch is
2923 conditionalizable). */
2924 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2928 code
= GET_CODE (insn
);
2930 /* Look for the label at the start of block 3. */
2931 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2934 /* Skip barriers, notes, and conditionalizable insns. If the
2935 insn is not conditionalizable or makes this optimization fail,
2936 just return the next insn so we can start over from that point. */
2937 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2938 return NEXT_INSN (insn
);
2940 /* Remember the last real insn before the label (ie end of block 2). */
2941 if (code
== JUMP_INSN
|| code
== INSN
)
2944 end_blk_2_insn
= insn
;
2951 /* It is possible for this optimization to slow performance if the blocks
2952 are long. This really depends upon whether the branch is likely taken
2953 or not. If the branch is taken, we slow performance in many cases. But,
2954 if the branch is not taken, we always help performance (for a single
2955 block, but for a double block (i.e. when the optimization is re-applied)
2956 this is not true since the 'right thing' depends on the overall length of
2957 the collapsed block). As a compromise, don't apply this optimization on
2958 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2959 the best threshold depends on the latencies of the instructions (i.e.,
2960 the branch penalty). */
2961 if (optimize
> 1 && blk_size
> 2)
2964 /* At this point, we've found the start of block 3 and we know that
2965 it is the destination of the branch from block 1. Also, all
2966 instructions in the block 2 are conditionalizable. So, apply the
2967 conditionalization and delete the branch. */
2968 start_blk_3_lab
= insn
;
2970 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2971 insn
= NEXT_INSN (insn
))
2975 if (INSN_DELETED_P (insn
))
2978 /* Try to form a conditional variant of the instruction and emit it. */
2979 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2981 if (end_blk_2_insn
== insn
)
2982 end_blk_2_insn
= newinsn
;
2988 /* Note whether we will delete the label starting blk 3 when the jump
2989 gets deleted. If so, we want to re-apply this optimization at the
2990 last real instruction right before the label. */
2991 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2993 start_blk_3_lab
= 0;
2996 /* ??? we probably should redistribute the death notes for this insn, esp.
2997 the death of cc, but it doesn't really matter this late in the game.
2998 The peepholes all use is_dead() which will find the correct death
2999 regardless of whether there is a note. */
3000 delete_insn (end_blk_1_br
);
3002 if (! start_blk_3_lab
)
3003 return end_blk_2_insn
;
3005 /* Return the insn right after the label at the start of block 3. */
3006 return NEXT_INSN (start_blk_3_lab
);
3009 /* Apply the conditionalization of blocks optimization. This is the
3010 outer loop that traverses through the insns scanning for a branch
3011 that signifies an opportunity to apply the optimization. Note that
3012 this optimization is applied late. If we could apply it earlier,
3013 say before cse 2, it may expose more optimization opportunities.
3014 but, the pay back probably isn't really worth the effort (we'd have
3015 to update all reg/flow/notes/links/etc to make it work - and stick it
3016 in before cse 2). */
3019 conditionalize_optimization (first
)
3024 for (insn
= first
; insn
; insn
= conditionalize_block (insn
))
3028 static int saved_warn_return_type
= -1;
3029 static int saved_warn_return_type_count
= 0;
3031 /* This function is called from toplev.c before reorg. */
3034 mcore_dependent_reorg (first
)
3037 /* Reset this variable. */
3038 current_function_anonymous_args
= 0;
3040 /* Restore the warn_return_type if it has been altered. */
3041 if (saved_warn_return_type
!= -1)
3043 /* Only restore the value if we have reached another function.
3044 The test of warn_return_type occurs in final_function () in
3045 c-decl.c a long time after the code for the function is generated,
3046 so we need a counter to tell us when we have finished parsing that
3047 function and can restore the flag. */
3048 if (--saved_warn_return_type_count
== 0)
3050 warn_return_type
= saved_warn_return_type
;
3051 saved_warn_return_type
= -1;
3058 /* Conditionalize blocks where we can. */
3059 conditionalize_optimization (first
);
3061 /* Literal pool generation is now pushed off until the assembler. */
3065 /* Return the reg_class to use when reloading the rtx X into the class
3068 /* If the input is (PLUS REG CONSTANT) representing a stack slot address,
3069 then we want to restrict the class to LRW_REGS since that ensures that
3070 will be able to safely load the constant.
3072 If the input is a constant that should be loaded with mvir1, then use
3075 ??? We don't handle the case where we have (PLUS REG CONSTANT) and
3076 the constant should be loaded with mvir1, because that can lead to cases
3077 where an instruction needs two ONLYR1_REGS reloads. */
3079 mcore_reload_class (x
, class)
3081 enum reg_class
class;
3083 enum reg_class new_class
;
3085 if (class == GENERAL_REGS
&& CONSTANT_P (x
)
3086 && (GET_CODE (x
) != CONST_INT
3087 || ( ! CONST_OK_FOR_I (INTVAL (x
))
3088 && ! CONST_OK_FOR_M (INTVAL (x
))
3089 && ! CONST_OK_FOR_N (INTVAL (x
)))))
3090 new_class
= LRW_REGS
;
3097 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
3098 register. Note that the current version doesn't worry about whether
3099 they are the same mode or note (e.g., a QImode in r2 matches an HImode
3100 in r2 matches an SImode in r2. Might think in the future about whether
3101 we want to be able to say something about modes. */
3103 mcore_is_same_reg (x
, y
)
3107 /* Strip any and all of the subreg wrappers. */
3108 while (GET_CODE (x
) == SUBREG
)
3111 while (GET_CODE (y
) == SUBREG
)
3114 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
3121 mcore_override_options ()
3123 if (mcore_stack_increment_string
)
3125 mcore_stack_increment
= atoi (mcore_stack_increment_string
);
3127 if (mcore_stack_increment
< 0
3128 || (mcore_stack_increment
== 0
3129 && (mcore_stack_increment_string
[0] != '0'
3130 || mcore_stack_increment_string
[1] != 0)))
3131 error ("invalid option `-mstack-increment=%s'",
3132 mcore_stack_increment_string
);
3135 /* Only the m340 supports little endian code. */
3136 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
3137 target_flags
|= M340_BIT
;
3141 mcore_must_pass_on_stack (mode
, type
)
3142 enum machine_mode mode ATTRIBUTE_UNUSED
;
3148 /* If the argugment can have its address taken, it must
3149 be placed on the stack. */
3150 if (TREE_ADDRESSABLE (type
))
3156 /* Compute the number of word sized registers needed to
3157 hold a function argument of mode MODE and type TYPE. */
3159 mcore_num_arg_regs (mode
, type
)
3160 enum machine_mode mode
;
3165 if (MUST_PASS_IN_STACK (mode
, type
))
3168 if (type
&& mode
== BLKmode
)
3169 size
= int_size_in_bytes (type
);
3171 size
= GET_MODE_SIZE (mode
);
3173 return ROUND_ADVANCE (size
);
3177 handle_structs_in_regs (mode
, type
, reg
)
3178 enum machine_mode mode
;
3184 /* The MCore ABI defines that a structure whoes size is not a whole multiple
3185 of bytes is passed packed into registers (or spilled onto the stack if
3186 not enough registers are available) with the last few bytes of the
3187 structure being packed, left-justified, into the last register/stack slot.
3188 GCC handles this correctly if the last word is in a stack slot, but we
3189 have to generate a special, PARALLEL RTX if the last word is in an
3190 argument register. */
3192 && TYPE_MODE (type
) == BLKmode
3193 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
3194 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
3195 && (size
% UNITS_PER_WORD
!= 0)
3196 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
3198 rtx arg_regs
[NPARM_REGS
];
3203 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
3206 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
3207 GEN_INT (nregs
* UNITS_PER_WORD
));
3211 /* We assume here that NPARM_REGS == 6. The assert checks this. */
3212 assert (ARRAY_SIZE (arg_regs
) == 6);
3213 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
3214 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
3216 result
= gen_rtx_PARALLEL (mode
, rtvec
);
3220 return gen_rtx_REG (mode
, reg
);
3224 mcore_function_value (valtype
, func
)
3226 tree func ATTRIBUTE_UNUSED
;
3228 enum machine_mode mode
;
3231 mode
= TYPE_MODE (valtype
);
3233 PROMOTE_MODE (mode
, unsigned_p
, NULL
);
3235 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
3238 /* Define where to put the arguments to a function.
3239 Value is zero to push the argument on the stack,
3240 or a hard register in which to store the argument.
3242 MODE is the argument's machine mode.
3243 TYPE is the data type of the argument (as a tree).
3244 This is null for libcalls where that information may
3246 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3247 the preceding args and about the function being called.
3248 NAMED is nonzero if this argument is a named parameter
3249 (otherwise it is an extra parameter matching an ellipsis).
3251 On MCore the first args are normally in registers
3252 and the rest are pushed. Any arg that starts within the first
3253 NPARM_REGS words is at least partially passed in a register unless
3254 its data type forbids. */
3256 mcore_function_arg (cum
, mode
, type
, named
)
3257 CUMULATIVE_ARGS cum
;
3258 enum machine_mode mode
;
3267 if (MUST_PASS_IN_STACK (mode
, type
))
3270 arg_reg
= ROUND_REG (cum
, mode
);
3272 if (arg_reg
< NPARM_REGS
)
3273 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
3278 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
3279 Returns the number of argument registers required to hold *part* of
3280 a parameter of machine mode MODE and type TYPE (which may be NULL if
3281 the type is not known). If the argument fits entirly in the argument
3282 registers, or entirely on the stack, then 0 is returned. CUM is the
3283 number of argument registers already used by earlier parameters to
3286 mcore_function_arg_partial_nregs (cum
, mode
, type
, named
)
3287 CUMULATIVE_ARGS cum
;
3288 enum machine_mode mode
;
3292 int reg
= ROUND_REG (cum
, mode
);
3297 if (MUST_PASS_IN_STACK (mode
, type
))
3300 /* REG is not the *hardware* register number of the register that holds
3301 the argument, it is the *argument* register number. So for example,
3302 the first argument to a function goes in argument register 0, which
3303 translates (for the MCore) into hardware register 2. The second
3304 argument goes into argument register 1, which translates into hardware
3305 register 3, and so on. NPARM_REGS is the number of argument registers
3306 supported by the target, not the maximum hardware register number of
3308 if (reg
>= NPARM_REGS
)
3311 /* If the argument fits entirely in registers, return 0. */
3312 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
3315 /* The argument overflows the number of available argument registers.
3316 Compute how many argument registers have not yet been assigned to
3317 hold an argument. */
3318 reg
= NPARM_REGS
- reg
;
3320 /* Return partially in registers and partially on the stack. */
3324 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
3326 mcore_dllexport_name_p (symbol
)
3327 const char * symbol
;
3329 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
3332 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
3334 mcore_dllimport_name_p (symbol
)
3335 const char * symbol
;
3337 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
3340 /* Mark a DECL as being dllexport'd. */
3342 mcore_mark_dllexport (decl
)
3345 const char * oldname
;
3350 rtlname
= XEXP (DECL_RTL (decl
), 0);
3352 if (GET_CODE (rtlname
) == SYMBOL_REF
)
3353 oldname
= XSTR (rtlname
, 0);
3354 else if ( GET_CODE (rtlname
) == MEM
3355 && GET_CODE (XEXP (rtlname
, 0)) == SYMBOL_REF
)
3356 oldname
= XSTR (XEXP (rtlname
, 0), 0);
3360 if (mcore_dllexport_name_p (oldname
))
3361 return; /* Already done. */
3363 newname
= alloca (strlen (oldname
) + 4);
3364 sprintf (newname
, "@e.%s", oldname
);
3366 /* We pass newname through get_identifier to ensure it has a unique
3367 address. RTL processing can sometimes peek inside the symbol ref
3368 and compare the string's addresses to see if two symbols are
3370 /* ??? At least I think that's why we do this. */
3371 idp
= get_identifier (newname
);
3373 XEXP (DECL_RTL (decl
), 0) =
3374 gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (idp
));
3377 /* Mark a DECL as being dllimport'd. */
3379 mcore_mark_dllimport (decl
)
3382 const char * oldname
;
3388 rtlname
= XEXP (DECL_RTL (decl
), 0);
3390 if (GET_CODE (rtlname
) == SYMBOL_REF
)
3391 oldname
= XSTR (rtlname
, 0);
3392 else if ( GET_CODE (rtlname
) == MEM
3393 && GET_CODE (XEXP (rtlname
, 0)) == SYMBOL_REF
)
3394 oldname
= XSTR (XEXP (rtlname
, 0), 0);
3398 if (mcore_dllexport_name_p (oldname
))
3399 abort (); /* This shouldn't happen. */
3400 else if (mcore_dllimport_name_p (oldname
))
3401 return; /* Already done. */
3403 /* ??? One can well ask why we're making these checks here,
3404 and that would be a good question. */
3406 /* Imported variables can't be initialized. */
3407 if (TREE_CODE (decl
) == VAR_DECL
3408 && !DECL_VIRTUAL_P (decl
)
3409 && DECL_INITIAL (decl
))
3411 error_with_decl (decl
, "initialized variable `%s' is marked dllimport");
3415 /* `extern' needn't be specified with dllimport.
3416 Specify `extern' now and hope for the best. Sigh. */
3417 if (TREE_CODE (decl
) == VAR_DECL
3418 /* ??? Is this test for vtables needed? */
3419 && !DECL_VIRTUAL_P (decl
))
3421 DECL_EXTERNAL (decl
) = 1;
3422 TREE_PUBLIC (decl
) = 1;
3425 newname
= alloca (strlen (oldname
) + 11);
3426 sprintf (newname
, "@i.__imp_%s", oldname
);
3428 /* We pass newname through get_identifier to ensure it has a unique
3429 address. RTL processing can sometimes peek inside the symbol ref
3430 and compare the string's addresses to see if two symbols are
3432 /* ??? At least I think that's why we do this. */
3433 idp
= get_identifier (newname
);
3435 newrtl
= gen_rtx (MEM
, Pmode
,
3436 gen_rtx (SYMBOL_REF
, Pmode
,
3437 IDENTIFIER_POINTER (idp
)));
3438 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3442 mcore_dllexport_p (decl
)
3445 if ( TREE_CODE (decl
) != VAR_DECL
3446 && TREE_CODE (decl
) != FUNCTION_DECL
)
3449 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
3453 mcore_dllimport_p (decl
)
3456 if ( TREE_CODE (decl
) != VAR_DECL
3457 && TREE_CODE (decl
) != FUNCTION_DECL
)
3460 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
3463 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3464 install some info in the .drective (PE) or .exports (ELF) sections. */
3467 mcore_encode_section_info (decl
, rtl
, first
)
3469 rtx rtl ATTRIBUTE_UNUSED
;
3470 int first ATTRIBUTE_UNUSED
;
3472 /* Mark the decl so we can tell from the rtl whether the object is
3473 dllexport'd or dllimport'd. */
3474 if (mcore_dllexport_p (decl
))
3475 mcore_mark_dllexport (decl
);
3476 else if (mcore_dllimport_p (decl
))
3477 mcore_mark_dllimport (decl
);
3479 /* It might be that DECL has already been marked as dllimport, but
3480 a subsequent definition nullified that. The attribute is gone
3481 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3482 else if ((TREE_CODE (decl
) == FUNCTION_DECL
3483 || TREE_CODE (decl
) == VAR_DECL
)
3484 && DECL_RTL (decl
) != NULL_RTX
3485 && GET_CODE (DECL_RTL (decl
)) == MEM
3486 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
3487 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
3488 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3490 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3491 tree idp
= get_identifier (oldname
+ 9);
3492 rtx newrtl
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (idp
));
3494 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3496 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3497 ??? We leave these alone for now. */
3501 /* Undo the effects of the above. */
3504 mcore_strip_name_encoding (str
)
3507 return str
+ (str
[0] == '@' ? 3 : 0);
3510 /* MCore specific attribute support.
3511 dllexport - for exporting a function/variable that will live in a dll
3512 dllimport - for importing a function/variable from a dll
3513 naked - do not create a function prologue/epilogue. */
3515 const struct attribute_spec mcore_attribute_table
[] =
3517 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3518 { "dllexport", 0, 0, true, false, false, NULL
},
3519 { "dllimport", 0, 0, true, false, false, NULL
},
3520 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
},
3521 { NULL
, 0, 0, false, false, false, NULL
}
3524 /* Handle a "naked" attribute; arguments as in
3525 struct attribute_spec.handler. */
3527 mcore_handle_naked_attribute (node
, name
, args
, flags
, no_add_attrs
)
3530 tree args ATTRIBUTE_UNUSED
;
3531 int flags ATTRIBUTE_UNUSED
;
3534 if (TREE_CODE (*node
) == FUNCTION_DECL
)
3536 /* PR14310 - don't complain about lack of return statement
3537 in naked functions. The solution here is a gross hack
3538 but this is the only way to solve the problem without
3539 adding a new feature to GCC. I did try submitting a patch
3540 that would add such a new feature, but it was (rightfully)
3541 rejected on the grounds that it was creeping featurism,
3542 so hence this code. */
3543 if (warn_return_type
)
3545 saved_warn_return_type
= warn_return_type
;
3546 warn_return_type
= 0;
3547 saved_warn_return_type_count
= 2;
3549 else if (saved_warn_return_type_count
)
3550 saved_warn_return_type_count
= 2;
3554 warning ("`%s' attribute only applies to functions",
3555 IDENTIFIER_POINTER (name
));
3556 *no_add_attrs
= true;
3562 /* ??? It looks like this is PE specific? Oh well, this is what the
3563 old code did as well. */
3566 mcore_unique_section (decl
, reloc
)
3568 int reloc ATTRIBUTE_UNUSED
;
3573 const char * prefix
;
3575 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3577 /* Strip off any encoding in name. */
3578 name
= (* targetm
.strip_name_encoding
) (name
);
3580 /* The object is put in, for example, section .text$foo.
3581 The linker will then ultimately place them in .text
3582 (everything from the $ on is stripped). */
3583 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3585 /* For compatibility with EPOC, we ignore the fact that the
3586 section might have relocs against it. */
3587 else if (decl_readonly_section (decl
, 0))
3592 len
= strlen (name
) + strlen (prefix
);
3593 string
= alloca (len
+ 1);
3595 sprintf (string
, "%s%s", prefix
, name
);
3597 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3601 mcore_naked_function_p ()
3603 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3606 #ifdef OBJECT_FORMAT_ELF
3608 mcore_asm_named_section (name
, flags
)
3610 unsigned int flags ATTRIBUTE_UNUSED
;
3612 fprintf (asm_out_file
, "\t.section %s\n", name
);
3614 #endif /* OBJECT_FORMAT_ELF */