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* target.h (encode_section_info): Add new argument carrying
[official-gcc.git] / gcc / config / m32r / m32r.c
bloba4e2ea2ba653b3b8151cbfa2103f0d1c3dd8a38f
1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "tree.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "output.h"
34 #include "insn-attr.h"
35 #include "flags.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "ggc.h"
41 #include "tm_p.h"
42 #include "target.h"
43 #include "target-def.h"
44
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
47 rtx m32r_compare_op0, m32r_compare_op1;
48
49 /* Array of valid operand punctuation characters. */
50 char m32r_punct_chars[256];
51
52 /* Selected code model. */
53 const char * m32r_model_string = M32R_MODEL_DEFAULT;
54 enum m32r_model m32r_model;
55
56 /* Selected SDA support. */
57 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
58 enum m32r_sdata m32r_sdata;
59
60 /* Scheduler support */
61 static int m32r_sched_odd_word_p;
62
63 /* Machine-specific symbol_ref flags. */
64 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
65 #define SYMBOL_REF_MODEL(X) \
66 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
67
68 /* For string literals, etc. */
69 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
70
71 /* Forward declaration. */
72 static void init_reg_tables PARAMS ((void));
73 static void block_move_call PARAMS ((rtx, rtx, rtx));
74 static int m32r_is_insn PARAMS ((rtx));
75 const struct attribute_spec m32r_attribute_table[];
76 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
77 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
78 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
79
80 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
81 static int m32r_adjust_priority PARAMS ((rtx, int));
82 static void m32r_sched_init PARAMS ((FILE *, int, int));
83 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
84 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
85 static int m32r_issue_rate PARAMS ((void));
86
87 static void m32r_encode_section_info PARAMS ((tree, rtx, int));
88 static bool m32r_in_small_data_p PARAMS ((tree));
89 static void init_idents PARAMS ((void));
90 static bool m32r_rtx_costs PARAMS ((rtx, int, int, int *));
91 \f
92 /* Initialize the GCC target structure. */
93 #undef TARGET_ATTRIBUTE_TABLE
94 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
95
96 #undef TARGET_ASM_ALIGNED_HI_OP
97 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
98 #undef TARGET_ASM_ALIGNED_SI_OP
99 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
100
101 #undef TARGET_ASM_FUNCTION_PROLOGUE
102 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
103 #undef TARGET_ASM_FUNCTION_EPILOGUE
104 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
105
106 #undef TARGET_SCHED_ADJUST_COST
107 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
108 #undef TARGET_SCHED_ADJUST_PRIORITY
109 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
110 #undef TARGET_SCHED_ISSUE_RATE
111 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
112 #undef TARGET_SCHED_VARIABLE_ISSUE
113 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
114 #undef TARGET_SCHED_INIT
115 #define TARGET_SCHED_INIT m32r_sched_init
116 #undef TARGET_SCHED_REORDER
117 #define TARGET_SCHED_REORDER m32r_sched_reorder
118
119 #undef TARGET_ENCODE_SECTION_INFO
120 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
121 #undef TARGET_IN_SMALL_DATA_P
122 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
123
124 #undef TARGET_RTX_COSTS
125 #define TARGET_RTX_COSTS m32r_rtx_costs
126 #undef TARGET_ADDRESS_COST
127 #define TARGET_ADDRESS_COST hook_int_rtx_0
128
129 struct gcc_target targetm = TARGET_INITIALIZER;
130 \f
131 /* Called by OVERRIDE_OPTIONS to initialize various things. */
132
133 void
134 m32r_init ()
135 {
136 init_reg_tables ();
137
138 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
139 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
140 m32r_punct_chars['#'] = 1;
141 m32r_punct_chars['@'] = 1; /* ??? no longer used */
142
143 /* Provide default value if not specified. */
144 if (!g_switch_set)
145 g_switch_value = SDATA_DEFAULT_SIZE;
146
147 if (strcmp (m32r_model_string, "small") == 0)
148 m32r_model = M32R_MODEL_SMALL;
149 else if (strcmp (m32r_model_string, "medium") == 0)
150 m32r_model = M32R_MODEL_MEDIUM;
151 else if (strcmp (m32r_model_string, "large") == 0)
152 m32r_model = M32R_MODEL_LARGE;
153 else
154 error ("bad value (%s) for -mmodel switch", m32r_model_string);
155
156 if (strcmp (m32r_sdata_string, "none") == 0)
157 m32r_sdata = M32R_SDATA_NONE;
158 else if (strcmp (m32r_sdata_string, "sdata") == 0)
159 m32r_sdata = M32R_SDATA_SDATA;
160 else if (strcmp (m32r_sdata_string, "use") == 0)
161 m32r_sdata = M32R_SDATA_USE;
162 else
163 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
164 }
165
166 /* Vectors to keep interesting information about registers where it can easily
167 be got. We use to use the actual mode value as the bit number, but there
168 is (or may be) more than 32 modes now. Instead we use two tables: one
169 indexed by hard register number, and one indexed by mode. */
170
171 /* The purpose of m32r_mode_class is to shrink the range of modes so that
172 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
173 mapped into one m32r_mode_class mode. */
174
175 enum m32r_mode_class
176 {
177 C_MODE,
178 S_MODE, D_MODE, T_MODE, O_MODE,
179 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
180 };
181
182 /* Modes for condition codes. */
183 #define C_MODES (1 << (int) C_MODE)
184
185 /* Modes for single-word and smaller quantities. */
186 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
187
188 /* Modes for double-word and smaller quantities. */
189 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
190
191 /* Modes for quad-word and smaller quantities. */
192 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
193
194 /* Modes for accumulators. */
195 #define A_MODES (1 << (int) A_MODE)
196
197 /* Value is 1 if register/mode pair is acceptable on arc. */
198
199 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
200 {
201 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
202 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
203 S_MODES, C_MODES, A_MODES, A_MODES
204 };
205
206 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
207
208 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
209
210 static void
211 init_reg_tables ()
212 {
213 int i;
214
215 for (i = 0; i < NUM_MACHINE_MODES; i++)
216 {
217 switch (GET_MODE_CLASS (i))
218 {
219 case MODE_INT:
220 case MODE_PARTIAL_INT:
221 case MODE_COMPLEX_INT:
222 if (GET_MODE_SIZE (i) <= 4)
223 m32r_mode_class[i] = 1 << (int) S_MODE;
224 else if (GET_MODE_SIZE (i) == 8)
225 m32r_mode_class[i] = 1 << (int) D_MODE;
226 else if (GET_MODE_SIZE (i) == 16)
227 m32r_mode_class[i] = 1 << (int) T_MODE;
228 else if (GET_MODE_SIZE (i) == 32)
229 m32r_mode_class[i] = 1 << (int) O_MODE;
230 else
231 m32r_mode_class[i] = 0;
232 break;
233 case MODE_FLOAT:
234 case MODE_COMPLEX_FLOAT:
235 if (GET_MODE_SIZE (i) <= 4)
236 m32r_mode_class[i] = 1 << (int) SF_MODE;
237 else if (GET_MODE_SIZE (i) == 8)
238 m32r_mode_class[i] = 1 << (int) DF_MODE;
239 else if (GET_MODE_SIZE (i) == 16)
240 m32r_mode_class[i] = 1 << (int) TF_MODE;
241 else if (GET_MODE_SIZE (i) == 32)
242 m32r_mode_class[i] = 1 << (int) OF_MODE;
243 else
244 m32r_mode_class[i] = 0;
245 break;
246 case MODE_CC:
247 default:
248 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
249 we must explicitly check for them here. */
250 if (i == (int) CCmode)
251 m32r_mode_class[i] = 1 << (int) C_MODE;
252 else
253 m32r_mode_class[i] = 0;
254 break;
255 }
256 }
257
258 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
259 {
260 if (GPR_P (i))
261 m32r_regno_reg_class[i] = GENERAL_REGS;
262 else if (i == ARG_POINTER_REGNUM)
263 m32r_regno_reg_class[i] = GENERAL_REGS;
264 else
265 m32r_regno_reg_class[i] = NO_REGS;
266 }
267 }
268 \f
269 /* M32R specific attribute support.
270
271 interrupt - for interrupt functions
272
273 model - select code model used to access object
274
275 small: addresses use 24 bits, use bl to make calls
276 medium: addresses use 32 bits, use bl to make calls
277 large: addresses use 32 bits, use seth/add3/jl to make calls
278
279 Grep for MODEL in m32r.h for more info.
280 */
281
282 static tree small_ident1;
283 static tree small_ident2;
284 static tree medium_ident1;
285 static tree medium_ident2;
286 static tree large_ident1;
287 static tree large_ident2;
288
289 static void
290 init_idents ()
291 {
292 if (small_ident1 == 0)
293 {
294 small_ident1 = get_identifier ("small");
295 small_ident2 = get_identifier ("__small__");
296 medium_ident1 = get_identifier ("medium");
297 medium_ident2 = get_identifier ("__medium__");
298 large_ident1 = get_identifier ("large");
299 large_ident2 = get_identifier ("__large__");
300 }
301 }
302
303 const struct attribute_spec m32r_attribute_table[] =
304 {
305 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
306 { "interrupt", 0, 0, true, false, false, NULL },
307 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
308 { NULL, 0, 0, false, false, false, NULL }
309 };
310
311
312 /* Handle an "model" attribute; arguments as in
313 struct attribute_spec.handler. */
314 static tree
315 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
316 tree *node ATTRIBUTE_UNUSED;
317 tree name;
318 tree args;
319 int flags ATTRIBUTE_UNUSED;
320 bool *no_add_attrs;
321 {
322 tree arg;
323
324 init_idents ();
325 arg = TREE_VALUE (args);
326
327 if (arg != small_ident1
328 && arg != small_ident2
329 && arg != medium_ident1
330 && arg != medium_ident2
331 && arg != large_ident1
332 && arg != large_ident2)
333 {
334 warning ("invalid argument of `%s' attribute",
335 IDENTIFIER_POINTER (name));
336 *no_add_attrs = true;
337 }
338
339 return NULL_TREE;
340 }
341 \f
342 /* Encode section information of DECL, which is either a VAR_DECL,
343 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
344
345 For the M32R we want to record:
346
347 - whether the object lives in .sdata/.sbss.
348 - what code model should be used to access the object
349 */
350
351 static void
352 m32r_encode_section_info (decl, rtl, first)
353 tree decl;
354 rtx rtl;
355 int first;
356 {
357 int extra_flags = 0;
358 tree model_attr;
359 enum m32r_model model;
360
361 default_encode_section_info (decl, rtl, first);
362
363 if (!DECL_P (decl))
364 return;
365
366 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
367 if (model_attr)
368 {
369 tree id;
370
371 init_idents ();
372
373 id = TREE_VALUE (TREE_VALUE (model_attr));
374
375 if (id == small_ident1 || id == small_ident2)
376 model = M32R_MODEL_SMALL;
377 else if (id == medium_ident1 || id == medium_ident2)
378 model = M32R_MODEL_MEDIUM;
379 else if (id == large_ident1 || id == large_ident2)
380 model = M32R_MODEL_LARGE;
381 else
382 abort (); /* shouldn't happen */
383 }
384 else
385 {
386 if (TARGET_MODEL_SMALL)
387 model = M32R_MODEL_SMALL;
388 else if (TARGET_MODEL_MEDIUM)
389 model = M32R_MODEL_MEDIUM;
390 else if (TARGET_MODEL_LARGE)
391 model = M32R_MODEL_LARGE;
392 else
393 abort (); /* shouldn't happen */
394 }
395 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
396
397 if (extra_flags)
398 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
399 }
400
401 /* Only mark the object as being small data area addressable if
402 it hasn't been explicitly marked with a code model.
403
404 The user can explicitly put an object in the small data area with the
405 section attribute. If the object is in sdata/sbss and marked with a
406 code model do both [put the object in .sdata and mark it as being
407 addressed with a specific code model - don't mark it as being addressed
408 with an SDA reloc though]. This is ok and might be useful at times. If
409 the object doesn't fit the linker will give an error. */
410
411 static bool
412 m32r_in_small_data_p (decl)
413 tree decl;
414 {
415 tree section;
416
417 if (TREE_CODE (decl) != VAR_DECL)
418 return false;
419
420 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
421 return false;
422
423 section = DECL_SECTION_NAME (decl);
424 if (section)
425 {
426 char *name = (char *) TREE_STRING_POINTER (section);
427 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
428 return true;
429 }
430 else
431 {
432 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
433 {
434 int size = int_size_in_bytes (TREE_TYPE (decl));
435
436 if (size > 0 && size <= g_switch_value)
437 return true;
438 }
439 }
440
441 return false;
442 }
443
444 /* Do anything needed before RTL is emitted for each function. */
445
446 void
447 m32r_init_expanders ()
448 {
449 /* ??? At one point there was code here. The function is left in
450 to make it easy to experiment. */
451 }
452 \f
453 /* Acceptable arguments to the call insn. */
454
455 int
456 call_address_operand (op, mode)
457 rtx op;
458 enum machine_mode mode;
459 {
460 return symbolic_operand (op, mode);
461
462 /* Constants and values in registers are not OK, because
463 the m32r BL instruction can only support PC relative branching. */
464 }
465
466 int
467 call_operand (op, mode)
468 rtx op;
469 enum machine_mode mode;
470 {
471 if (GET_CODE (op) != MEM)
472 return 0;
473 op = XEXP (op, 0);
474 return call_address_operand (op, mode);
475 }
476
477 /* Returns 1 if OP is a symbol reference. */
478
479 int
480 symbolic_operand (op, mode)
481 rtx op;
482 enum machine_mode mode ATTRIBUTE_UNUSED;
483 {
484 switch (GET_CODE (op))
485 {
486 case SYMBOL_REF:
487 case LABEL_REF:
488 case CONST :
489 return 1;
490
491 default:
492 return 0;
493 }
494 }
495
496 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
497
498 int
499 small_data_operand (op, mode)
500 rtx op;
501 enum machine_mode mode ATTRIBUTE_UNUSED;
502 {
503 if (! TARGET_SDATA_USE)
504 return 0;
505
506 if (GET_CODE (op) == SYMBOL_REF)
507 return SYMBOL_REF_SMALL_P (op);
508
509 if (GET_CODE (op) == CONST
510 && GET_CODE (XEXP (op, 0)) == PLUS
511 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
512 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
513 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
514 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
515
516 return 0;
517 }
518
519 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
520
521 int
522 addr24_operand (op, mode)
523 rtx op;
524 enum machine_mode mode ATTRIBUTE_UNUSED;
525 {
526 rtx sym;
527
528 if (GET_CODE (op) == LABEL_REF)
529 return TARGET_ADDR24;
530
531 if (GET_CODE (op) == SYMBOL_REF)
532 sym = op;
533 else if (GET_CODE (op) == CONST
534 && GET_CODE (XEXP (op, 0)) == PLUS
535 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
536 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
537 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
538 sym = XEXP (XEXP (op, 0), 0);
539 else
540 return 0;
541
542 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
543 return 1;
544
545 if (TARGET_ADDR24
546 && (CONSTANT_POOL_ADDRESS_P (sym)
547 || LIT_NAME_P (XSTR (sym, 0))))
548 return 1;
549
550 return 0;
551 }
552
553 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
554
555 int
556 addr32_operand (op, mode)
557 rtx op;
558 enum machine_mode mode;
559 {
560 rtx sym;
561
562 if (GET_CODE (op) == LABEL_REF)
563 return TARGET_ADDR32;
564
565 if (GET_CODE (op) == SYMBOL_REF)
566 sym = op;
567 else if (GET_CODE (op) == CONST
568 && GET_CODE (XEXP (op, 0)) == PLUS
569 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
570 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
571 sym = XEXP (XEXP (op, 0), 0);
572 else
573 return 0;
574
575 return (! addr24_operand (sym, mode)
576 && ! small_data_operand (sym, mode));
577 }
578
579 /* Return 1 if OP is a function that can be called with the `bl' insn. */
580
581 int
582 call26_operand (op, mode)
583 rtx op;
584 enum machine_mode mode ATTRIBUTE_UNUSED;
585 {
586 if (GET_CODE (op) == SYMBOL_REF)
587 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
588
589 return TARGET_CALL26;
590 }
591
592 /* Returns 1 if OP is an acceptable operand for seth/add3. */
593
594 int
595 seth_add3_operand (op, mode)
596 rtx op;
597 enum machine_mode mode ATTRIBUTE_UNUSED;
598 {
599 if (GET_CODE (op) == SYMBOL_REF
600 || GET_CODE (op) == LABEL_REF)
601 return 1;
602
603 if (GET_CODE (op) == CONST
604 && GET_CODE (XEXP (op, 0)) == PLUS
605 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
606 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
607 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
608 return 1;
609
610 return 0;
611 }
612
613 /* Return true if OP is a signed 8 bit immediate value. */
614
615 int
616 int8_operand (op, mode)
617 rtx op;
618 enum machine_mode mode ATTRIBUTE_UNUSED;
619 {
620 if (GET_CODE (op) != CONST_INT)
621 return 0;
622 return INT8_P (INTVAL (op));
623 }
624
625 /* Return true if OP is a signed 16 bit immediate value
626 useful in comparisons. */
627
628 int
629 cmp_int16_operand (op, mode)
630 rtx op;
631 enum machine_mode mode ATTRIBUTE_UNUSED;
632 {
633 if (GET_CODE (op) != CONST_INT)
634 return 0;
635 return CMP_INT16_P (INTVAL (op));
636 }
637
638 /* Return true if OP is an unsigned 16 bit immediate value. */
639
640 int
641 uint16_operand (op, mode)
642 rtx op;
643 enum machine_mode mode ATTRIBUTE_UNUSED;
644 {
645 if (GET_CODE (op) != CONST_INT)
646 return 0;
647 return UINT16_P (INTVAL (op));
648 }
649
650 /* Return true if OP is a register or signed 16 bit value. */
651
652 int
653 reg_or_int16_operand (op, mode)
654 rtx op;
655 enum machine_mode mode;
656 {
657 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
658 return register_operand (op, mode);
659 if (GET_CODE (op) != CONST_INT)
660 return 0;
661 return INT16_P (INTVAL (op));
662 }
663
664 /* Return true if OP is a register or an unsigned 16 bit value. */
665
666 int
667 reg_or_uint16_operand (op, mode)
668 rtx op;
669 enum machine_mode mode;
670 {
671 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
672 return register_operand (op, mode);
673 if (GET_CODE (op) != CONST_INT)
674 return 0;
675 return UINT16_P (INTVAL (op));
676 }
677
678 /* Return true if OP is a register or an integer value that can be
679 used is SEQ/SNE. We can use either XOR of the value or ADD of
680 the negative of the value for the constant. Don't allow 0,
681 because that is special cased. */
682
683 int
684 reg_or_eq_int16_operand (op, mode)
685 rtx op;
686 enum machine_mode mode;
687 {
688 HOST_WIDE_INT value;
689
690 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
691 return register_operand (op, mode);
692
693 if (GET_CODE (op) != CONST_INT)
694 return 0;
695
696 value = INTVAL (op);
697 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
698 }
699
700 /* Return true if OP is a register or signed 16 bit value for compares. */
701
702 int
703 reg_or_cmp_int16_operand (op, mode)
704 rtx op;
705 enum machine_mode mode;
706 {
707 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
708 return register_operand (op, mode);
709 if (GET_CODE (op) != CONST_INT)
710 return 0;
711 return CMP_INT16_P (INTVAL (op));
712 }
713
714 /* Return true if OP is a register or the constant 0. */
715
716 int
717 reg_or_zero_operand (op, mode)
718 rtx op;
719 enum machine_mode mode;
720 {
721 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
722 return register_operand (op, mode);
723
724 if (GET_CODE (op) != CONST_INT)
725 return 0;
726
727 return INTVAL (op) == 0;
728 }
729
730 /* Return true if OP is a const_int requiring two instructions to load. */
731
732 int
733 two_insn_const_operand (op, mode)
734 rtx op;
735 enum machine_mode mode ATTRIBUTE_UNUSED;
736 {
737 if (GET_CODE (op) != CONST_INT)
738 return 0;
739 if (INT16_P (INTVAL (op))
740 || UINT24_P (INTVAL (op))
741 || UPPER16_P (INTVAL (op)))
742 return 0;
743 return 1;
744 }
745
746 /* Return true if OP is an acceptable argument for a single word
747 move source. */
748
749 int
750 move_src_operand (op, mode)
751 rtx op;
752 enum machine_mode mode;
753 {
754 switch (GET_CODE (op))
755 {
756 case SYMBOL_REF :
757 case CONST :
758 return addr24_operand (op, mode);
759 case CONST_INT :
760 /* ??? We allow more cse opportunities if we only allow constants
761 loadable with one insn, and split the rest into two. The instances
762 where this would help should be rare and the current way is
763 simpler. */
764 if (HOST_BITS_PER_WIDE_INT > 32)
765 {
766 HOST_WIDE_INT rest = INTVAL (op) >> 31;
767 return (rest == 0 || rest == -1);
768 }
769 else
770 return 1;
771 case LABEL_REF :
772 return TARGET_ADDR24;
773 case CONST_DOUBLE :
774 if (mode == SFmode)
775 return 1;
776 else if (mode == SImode)
777 {
778 /* Large unsigned constants are represented as const_double's. */
779 unsigned HOST_WIDE_INT low, high;
780
781 low = CONST_DOUBLE_LOW (op);
782 high = CONST_DOUBLE_HIGH (op);
783 return high == 0 && low <= (unsigned) 0xffffffff;
784 }
785 else
786 return 0;
787 case REG :
788 return register_operand (op, mode);
789 case SUBREG :
790 /* (subreg (mem ...) ...) can occur here if the inner part was once a
791 pseudo-reg and is now a stack slot. */
792 if (GET_CODE (SUBREG_REG (op)) == MEM)
793 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
794 else
795 return register_operand (op, mode);
796 case MEM :
797 if (GET_CODE (XEXP (op, 0)) == PRE_INC
798 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
799 return 0; /* loads can't do pre-{inc,dec} */
800 return address_operand (XEXP (op, 0), mode);
801 default :
802 return 0;
803 }
804 }
805
806 /* Return true if OP is an acceptable argument for a double word
807 move source. */
808
809 int
810 move_double_src_operand (op, mode)
811 rtx op;
812 enum machine_mode mode;
813 {
814 switch (GET_CODE (op))
815 {
816 case CONST_INT :
817 case CONST_DOUBLE :
818 return 1;
819 case REG :
820 return register_operand (op, mode);
821 case SUBREG :
822 /* (subreg (mem ...) ...) can occur here if the inner part was once a
823 pseudo-reg and is now a stack slot. */
824 if (GET_CODE (SUBREG_REG (op)) == MEM)
825 return move_double_src_operand (SUBREG_REG (op), mode);
826 else
827 return register_operand (op, mode);
828 case MEM :
829 /* Disallow auto inc/dec for now. */
830 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
831 || GET_CODE (XEXP (op, 0)) == PRE_INC)
832 return 0;
833 return address_operand (XEXP (op, 0), mode);
834 default :
835 return 0;
836 }
837 }
838
839 /* Return true if OP is an acceptable argument for a move destination. */
840
841 int
842 move_dest_operand (op, mode)
843 rtx op;
844 enum machine_mode mode;
845 {
846 switch (GET_CODE (op))
847 {
848 case REG :
849 return register_operand (op, mode);
850 case SUBREG :
851 /* (subreg (mem ...) ...) can occur here if the inner part was once a
852 pseudo-reg and is now a stack slot. */
853 if (GET_CODE (SUBREG_REG (op)) == MEM)
854 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
855 else
856 return register_operand (op, mode);
857 case MEM :
858 if (GET_CODE (XEXP (op, 0)) == POST_INC)
859 return 0; /* stores can't do post inc */
860 return address_operand (XEXP (op, 0), mode);
861 default :
862 return 0;
863 }
864 }
865
866 /* Return 1 if OP is a DImode const we want to handle inline.
867 This must match the code in the movdi pattern.
868 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
869
870 int
871 easy_di_const (op)
872 rtx op;
873 {
874 rtx high_rtx, low_rtx;
875 HOST_WIDE_INT high, low;
876
877 split_double (op, &high_rtx, &low_rtx);
878 high = INTVAL (high_rtx);
879 low = INTVAL (low_rtx);
880 /* Pick constants loadable with 2 16 bit `ldi' insns. */
881 if (high >= -128 && high <= 127
882 && low >= -128 && low <= 127)
883 return 1;
884 return 0;
885 }
886
887 /* Return 1 if OP is a DFmode const we want to handle inline.
888 This must match the code in the movdf pattern.
889 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
890
891 int
892 easy_df_const (op)
893 rtx op;
894 {
895 REAL_VALUE_TYPE r;
896 long l[2];
897
898 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
899 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
900 if (l[0] == 0 && l[1] == 0)
901 return 1;
902 if ((l[0] & 0xffff) == 0 && l[1] == 0)
903 return 1;
904 return 0;
905 }
906
907 /* Return 1 if OP is an EQ or NE comparison operator. */
908
909 int
910 eqne_comparison_operator (op, mode)
911 rtx op;
912 enum machine_mode mode ATTRIBUTE_UNUSED;
913 {
914 enum rtx_code code = GET_CODE (op);
915
916 if (GET_RTX_CLASS (code) != '<')
917 return 0;
918 return (code == EQ || code == NE);
919 }
920
921 /* Return 1 if OP is a signed comparison operator. */
922
923 int
924 signed_comparison_operator (op, mode)
925 rtx op;
926 enum machine_mode mode ATTRIBUTE_UNUSED;
927 {
928 enum rtx_code code = GET_CODE (op);
929
930 if (GET_RTX_CLASS (code) != '<')
931 return 0;
932 return (code == EQ || code == NE
933 || code == LT || code == LE || code == GT || code == GE);
934 }
935
936 /* Return 1 if OP is (mem (reg ...)).
937 This is used in insn length calcs. */
938
939 int
940 memreg_operand (op, mode)
941 rtx op;
942 enum machine_mode mode ATTRIBUTE_UNUSED;
943 {
944 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
945 }
946
947 /* Return true if OP is an acceptable input argument for a zero/sign extend
948 operation. */
949
950 int
951 extend_operand (op, mode)
952 rtx op;
953 enum machine_mode mode;
954 {
955 rtx addr;
956
957 switch (GET_CODE (op))
958 {
959 case REG :
960 case SUBREG :
961 return register_operand (op, mode);
962
963 case MEM :
964 addr = XEXP (op, 0);
965 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
966 return 0; /* loads can't do pre inc/pre dec */
967
968 return address_operand (addr, mode);
969
970 default :
971 return 0;
972 }
973 }
974
975 /* Return nonzero if the operand is an insn that is a small insn.
976 Allow const_int 0 as well, which is a placeholder for NOP slots. */
977
978 int
979 small_insn_p (op, mode)
980 rtx op;
981 enum machine_mode mode ATTRIBUTE_UNUSED;
982 {
983 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
984 return 1;
985
986 if (! INSN_P (op))
987 return 0;
988
989 return get_attr_length (op) == 2;
990 }
991
992 /* Return nonzero if the operand is an insn that is a large insn. */
993
994 int
995 large_insn_p (op, mode)
996 rtx op;
997 enum machine_mode mode ATTRIBUTE_UNUSED;
998 {
999 if (! INSN_P (op))
1000 return 0;
1001
1002 return get_attr_length (op) != 2;
1003 }
1004
1005 \f
1006 /* Comparisons. */
1007
1008 /* X and Y are two things to compare using CODE. Emit the compare insn and
1009 return the rtx for compare [arg0 of the if_then_else].
1010 If need_compare is true then the comparison insn must be generated, rather
1011 than being susummed into the following branch instruction. */
1012
1013 rtx
1014 gen_compare (code, x, y, need_compare)
1015 enum rtx_code code;
1016 rtx x, y;
1017 int need_compare;
1018 {
1019 enum rtx_code compare_code, branch_code;
1020 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1021 int must_swap = 0;
1022
1023 switch (code)
1024 {
1025 case EQ: compare_code = EQ; branch_code = NE; break;
1026 case NE: compare_code = EQ; branch_code = EQ; break;
1027 case LT: compare_code = LT; branch_code = NE; break;
1028 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1029 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1030 case GE: compare_code = LT; branch_code = EQ; break;
1031 case LTU: compare_code = LTU; branch_code = NE; break;
1032 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1033 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1034 case GEU: compare_code = LTU; branch_code = EQ; break;
1035
1036 default:
1037 abort ();
1038 }
1039
1040 if (need_compare)
1041 {
1042 switch (compare_code)
1043 {
1044 case EQ:
1045 if (GET_CODE (y) == CONST_INT
1046 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1047 && y != const0_rtx)
1048 {
1049 rtx tmp = gen_reg_rtx (SImode);
1050
1051 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1052 x = tmp;
1053 y = const0_rtx;
1054 }
1055 else if (CONSTANT_P (y)) /* reg equal to const. */
1056 {
1057 rtx tmp = force_reg (GET_MODE (x), y);
1058 y = tmp;
1059 }
1060
1061 if (register_operand (y, SImode) /* reg equal to reg. */
1062 || y == const0_rtx) /* req equal to zero. */
1063 {
1064 emit_insn (gen_cmp_eqsi_insn (x, y));
1065
1066 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1067 }
1068 break;
1069
1070 case LT:
1071 if (register_operand (y, SImode)
1072 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1073 {
1074 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1075
1076 switch (code)
1077 {
1078 case LT:
1079 emit_insn (gen_cmp_ltsi_insn (x, y));
1080 code = EQ;
1081 break;
1082 case LE:
1083 if (y == const0_rtx)
1084 tmp = const1_rtx;
1085 else
1086 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1087 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1088 code = EQ;
1089 break;
1090 case GT:
1091 if (GET_CODE (y) == CONST_INT)
1092 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1093 else
1094 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1095 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1096 code = NE;
1097 break;
1098 case GE:
1099 emit_insn (gen_cmp_ltsi_insn (x, y));
1100 code = NE;
1101 break;
1102 default:
1103 abort ();
1104 }
1105
1106 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1107 }
1108 break;
1109
1110 case LTU:
1111 if (register_operand (y, SImode)
1112 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1113 {
1114 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1115
1116 switch (code)
1117 {
1118 case LTU:
1119 emit_insn (gen_cmp_ltusi_insn (x, y));
1120 code = EQ;
1121 break;
1122 case LEU:
1123 if (y == const0_rtx)
1124 tmp = const1_rtx;
1125 else
1126 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1127 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1128 code = EQ;
1129 break;
1130 case GTU:
1131 if (GET_CODE (y) == CONST_INT)
1132 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1133 else
1134 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1135 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1136 code = NE;
1137 break;
1138 case GEU:
1139 emit_insn (gen_cmp_ltusi_insn (x, y));
1140 code = NE;
1141 break;
1142 default:
1143 abort();
1144 }
1145
1146 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1147 }
1148 break;
1149
1150 default:
1151 abort();
1152 }
1153 }
1154 else
1155 {
1156 /* reg/reg equal comparison */
1157 if (compare_code == EQ
1158 && register_operand (y, SImode))
1159 return gen_rtx (code, CCmode, x, y);
1160
1161 /* reg/zero signed comparison */
1162 if ((compare_code == EQ || compare_code == LT)
1163 && y == const0_rtx)
1164 return gen_rtx (code, CCmode, x, y);
1165
1166 /* reg/smallconst equal comparison */
1167 if (compare_code == EQ
1168 && GET_CODE (y) == CONST_INT
1169 && CMP_INT16_P (INTVAL (y)))
1170 {
1171 rtx tmp = gen_reg_rtx (SImode);
1172 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1173 return gen_rtx (code, CCmode, tmp, const0_rtx);
1174 }
1175
1176 /* reg/const equal comparison */
1177 if (compare_code == EQ
1178 && CONSTANT_P (y))
1179 {
1180 rtx tmp = force_reg (GET_MODE (x), y);
1181 return gen_rtx (code, CCmode, x, tmp);
1182 }
1183 }
1184
1185 if (CONSTANT_P (y))
1186 {
1187 if (must_swap)
1188 y = force_reg (GET_MODE (x), y);
1189 else
1190 {
1191 int ok_const =
1192 (code == LTU || code == LEU || code == GTU || code == GEU)
1193 ? uint16_operand (y, GET_MODE (y))
1194 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1195
1196 if (! ok_const)
1197 y = force_reg (GET_MODE (x), y);
1198 }
1199 }
1200
1201 switch (compare_code)
1202 {
1203 case EQ :
1204 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1205 break;
1206 case LT :
1207 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1208 break;
1209 case LTU :
1210 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1211 break;
1212
1213 default:
1214 abort ();
1215 }
1216
1217 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1218 }
1219 \f
1220 /* Split a 2 word move (DI or DF) into component parts. */
1221
1222 rtx
1223 gen_split_move_double (operands)
1224 rtx operands[];
1225 {
1226 enum machine_mode mode = GET_MODE (operands[0]);
1227 rtx dest = operands[0];
1228 rtx src = operands[1];
1229 rtx val;
1230
1231 /* We might have (SUBREG (MEM)) here, so just get rid of the
1232 subregs to make this code simpler. It is safe to call
1233 alter_subreg any time after reload. */
1234 if (GET_CODE (dest) == SUBREG)
1235 alter_subreg (&dest);
1236 if (GET_CODE (src) == SUBREG)
1237 alter_subreg (&src);
1238
1239 start_sequence ();
1240 if (GET_CODE (dest) == REG)
1241 {
1242 int dregno = REGNO (dest);
1243
1244 /* reg = reg */
1245 if (GET_CODE (src) == REG)
1246 {
1247 int sregno = REGNO (src);
1248
1249 int reverse = (dregno == sregno + 1);
1250
1251 /* We normally copy the low-numbered register first. However, if
1252 the first register operand 0 is the same as the second register of
1253 operand 1, we must copy in the opposite order. */
1254 emit_insn (gen_rtx_SET (VOIDmode,
1255 operand_subword (dest, reverse, TRUE, mode),
1256 operand_subword (src, reverse, TRUE, mode)));
1257
1258 emit_insn (gen_rtx_SET (VOIDmode,
1259 operand_subword (dest, !reverse, TRUE, mode),
1260 operand_subword (src, !reverse, TRUE, mode)));
1261 }
1262
1263 /* reg = constant */
1264 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1265 {
1266 rtx words[2];
1267 split_double (src, &words[0], &words[1]);
1268 emit_insn (gen_rtx_SET (VOIDmode,
1269 operand_subword (dest, 0, TRUE, mode),
1270 words[0]));
1271
1272 emit_insn (gen_rtx_SET (VOIDmode,
1273 operand_subword (dest, 1, TRUE, mode),
1274 words[1]));
1275 }
1276
1277 /* reg = mem */
1278 else if (GET_CODE (src) == MEM)
1279 {
1280 /* If the high-address word is used in the address, we must load it
1281 last. Otherwise, load it first. */
1282 int reverse
1283 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1284
1285 /* We used to optimize loads from single registers as
1286
1287 ld r1,r3+; ld r2,r3
1288
1289 if r3 were not used subsequently. However, the REG_NOTES aren't
1290 propigated correctly by the reload phase, and it can cause bad
1291 code to be generated. We could still try:
1292
1293 ld r1,r3+; ld r2,r3; addi r3,-4
1294
1295 which saves 2 bytes and doesn't force longword alignment. */
1296 emit_insn (gen_rtx_SET (VOIDmode,
1297 operand_subword (dest, reverse, TRUE, mode),
1298 adjust_address (src, SImode,
1299 reverse * UNITS_PER_WORD)));
1300
1301 emit_insn (gen_rtx_SET (VOIDmode,
1302 operand_subword (dest, !reverse, TRUE, mode),
1303 adjust_address (src, SImode,
1304 !reverse * UNITS_PER_WORD)));
1305 }
1306
1307 else
1308 abort ();
1309 }
1310
1311 /* mem = reg */
1312 /* We used to optimize loads from single registers as
1313
1314 st r1,r3; st r2,+r3
1315
1316 if r3 were not used subsequently. However, the REG_NOTES aren't
1317 propigated correctly by the reload phase, and it can cause bad
1318 code to be generated. We could still try:
1319
1320 st r1,r3; st r2,+r3; addi r3,-4
1321
1322 which saves 2 bytes and doesn't force longword alignment. */
1323 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1324 {
1325 emit_insn (gen_rtx_SET (VOIDmode,
1326 adjust_address (dest, SImode, 0),
1327 operand_subword (src, 0, TRUE, mode)));
1328
1329 emit_insn (gen_rtx_SET (VOIDmode,
1330 adjust_address (dest, SImode, UNITS_PER_WORD),
1331 operand_subword (src, 1, TRUE, mode)));
1332 }
1333
1334 else
1335 abort ();
1336
1337 val = get_insns ();
1338 end_sequence ();
1339 return val;
1340 }
1341
1342 \f
1343 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1344
1345 int
1346 function_arg_partial_nregs (cum, mode, type, named)
1347 CUMULATIVE_ARGS *cum;
1348 enum machine_mode mode;
1349 tree type;
1350 int named ATTRIBUTE_UNUSED;
1351 {
1352 int ret;
1353 unsigned int size =
1354 (((mode == BLKmode && type)
1355 ? (unsigned int) int_size_in_bytes (type)
1356 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1357 / UNITS_PER_WORD;
1358
1359 if (*cum >= M32R_MAX_PARM_REGS)
1360 ret = 0;
1361 else if (*cum + size > M32R_MAX_PARM_REGS)
1362 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1363 else
1364 ret = 0;
1365
1366 return ret;
1367 }
1368
1369 /* Do any needed setup for a variadic function. For the M32R, we must
1370 create a register parameter block, and then copy any anonymous arguments
1371 in registers to memory.
1372
1373 CUM has not been updated for the last named argument which has type TYPE
1374 and mode MODE, and we rely on this fact. */
1375
1376 void
1377 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1378 CUMULATIVE_ARGS *cum;
1379 enum machine_mode mode;
1380 tree type;
1381 int *pretend_size;
1382 int no_rtl;
1383 {
1384 int first_anon_arg;
1385
1386 if (no_rtl)
1387 return;
1388
1389 /* All BLKmode values are passed by reference. */
1390 if (mode == BLKmode)
1391 abort ();
1392
1393 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1394 + ROUND_ADVANCE_ARG (mode, type));
1395
1396 if (first_anon_arg < M32R_MAX_PARM_REGS)
1397 {
1398 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1399 int first_reg_offset = first_anon_arg;
1400 /* Size in words to "pretend" allocate. */
1401 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1402 rtx regblock;
1403
1404 regblock = gen_rtx_MEM (BLKmode,
1405 plus_constant (arg_pointer_rtx,
1406 FIRST_PARM_OFFSET (0)));
1407 set_mem_alias_set (regblock, get_varargs_alias_set ());
1408 move_block_from_reg (first_reg_offset, regblock,
1409 size, size * UNITS_PER_WORD);
1410
1411 *pretend_size = (size * UNITS_PER_WORD);
1412 }
1413 }
1414
1415 \f
1416 /* Implement `va_arg'. */
1417
1418 rtx
1419 m32r_va_arg (valist, type)
1420 tree valist, type;
1421 {
1422 HOST_WIDE_INT size, rsize;
1423 tree t;
1424 rtx addr_rtx;
1425
1426 size = int_size_in_bytes (type);
1427 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1428
1429 if (size > 8)
1430 {
1431 tree type_ptr, type_ptr_ptr;
1432
1433 /* Pass by reference. */
1434
1435 type_ptr = build_pointer_type (type);
1436 type_ptr_ptr = build_pointer_type (type_ptr);
1437
1438 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1439 build_int_2 (UNITS_PER_WORD, 0));
1440 TREE_SIDE_EFFECTS (t) = 1;
1441 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1442 TREE_SIDE_EFFECTS (t) = 1;
1443 t = build1 (INDIRECT_REF, type_ptr, t);
1444
1445 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1446 }
1447 else
1448 {
1449 /* Pass by value. */
1450
1451 if (size < UNITS_PER_WORD)
1452 {
1453 /* Care for bigendian correction on the aligned address. */
1454 t = build (PLUS_EXPR, ptr_type_node, valist,
1455 build_int_2 (rsize - size, 0));
1456 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1457 addr_rtx = copy_to_reg (addr_rtx);
1458
1459 /* Increment AP. */
1460 t = build (PLUS_EXPR, va_list_type_node, valist,
1461 build_int_2 (rsize, 0));
1462 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1463 TREE_SIDE_EFFECTS (t) = 1;
1464 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1465 }
1466 else
1467 {
1468 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1469 build_int_2 (rsize, 0));
1470 TREE_SIDE_EFFECTS (t) = 1;
1471 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1472 }
1473 }
1474
1475 return addr_rtx;
1476 }
1477 \f
1478 static int
1479 m32r_adjust_cost (insn, link, dep_insn, cost)
1480 rtx insn ATTRIBUTE_UNUSED;
1481 rtx link ATTRIBUTE_UNUSED;
1482 rtx dep_insn ATTRIBUTE_UNUSED;
1483 int cost;
1484 {
1485 return cost;
1486 }
1487
1488 \f
1489 /* Return true if INSN is real instruction bearing insn. */
1490
1491 static int
1492 m32r_is_insn (insn)
1493 rtx insn;
1494 {
1495 return (INSN_P (insn)
1496 && GET_CODE (PATTERN (insn)) != USE
1497 && GET_CODE (PATTERN (insn)) != CLOBBER
1498 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1499 }
1500
1501 /* Increase the priority of long instructions so that the
1502 short instructions are scheduled ahead of the long ones. */
1503
1504 static int
1505 m32r_adjust_priority (insn, priority)
1506 rtx insn;
1507 int priority;
1508 {
1509 if (m32r_is_insn (insn)
1510 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1511 priority <<= 3;
1512
1513 return priority;
1514 }
1515
1516 \f
1517 /* Initialize for scheduling a group of instructions. */
1518
1519 static void
1520 m32r_sched_init (stream, verbose, max_ready)
1521 FILE * stream ATTRIBUTE_UNUSED;
1522 int verbose ATTRIBUTE_UNUSED;
1523 int max_ready ATTRIBUTE_UNUSED;
1524 {
1525 m32r_sched_odd_word_p = FALSE;
1526 }
1527
1528 \f
1529 /* Reorder the schedulers priority list if needed */
1530
1531 static int
1532 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1533 FILE * stream;
1534 int verbose;
1535 rtx * ready;
1536 int *n_readyp;
1537 int clock ATTRIBUTE_UNUSED;
1538 {
1539 int n_ready = *n_readyp;
1540
1541 if (TARGET_DEBUG)
1542 return m32r_issue_rate ();
1543
1544 if (verbose <= 7)
1545 stream = (FILE *)0;
1546
1547 if (stream)
1548 fprintf (stream,
1549 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1550 n_ready,
1551 (m32r_sched_odd_word_p) ? "odd" : "even");
1552
1553 if (n_ready > 1)
1554 {
1555 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1556 rtx * long_tail = long_head;
1557 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1558 rtx * short_tail = short_head;
1559 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1560 rtx * new_tail = new_head + (n_ready - 1);
1561 int i;
1562
1563 /* Loop through the instructions, classifing them as short/long. Try
1564 to keep 2 short together and/or 1 long. Note, the ready list is
1565 actually ordered backwards, so keep it in that manner. */
1566 for (i = n_ready-1; i >= 0; i--)
1567 {
1568 rtx insn = ready[i];
1569
1570 if (! m32r_is_insn (insn))
1571 {
1572 /* Dump all current short/long insns just in case. */
1573 while (long_head != long_tail)
1574 *new_tail-- = *long_head++;
1575
1576 while (short_head != short_tail)
1577 *new_tail-- = *short_head++;
1578
1579 *new_tail-- = insn;
1580 if (stream)
1581 fprintf (stream,
1582 ";;\t\t::: Skipping non instruction %d\n",
1583 INSN_UID (insn));
1584
1585 }
1586
1587 else
1588 {
1589 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1590 *long_tail++ = insn;
1591
1592 else
1593 *short_tail++ = insn;
1594 }
1595 }
1596
1597 /* If we are on an odd word, emit a single short instruction if
1598 we can */
1599 if (m32r_sched_odd_word_p && short_head != short_tail)
1600 *new_tail-- = *short_head++;
1601
1602 /* Now dump out all of the long instructions */
1603 while (long_head != long_tail)
1604 *new_tail-- = *long_head++;
1605
1606 /* Now dump out all of the short instructions */
1607 while (short_head != short_tail)
1608 *new_tail-- = *short_head++;
1609
1610 if (new_tail+1 != new_head)
1611 abort ();
1612
1613 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1614 if (stream)
1615 {
1616 int i;
1617 fprintf (stream, ";;\t\t::: New ready list: ");
1618 for (i = 0; i < n_ready; i++)
1619 {
1620 rtx insn = ready[i];
1621
1622 fprintf (stream, " %d", INSN_UID (ready[i]));
1623
1624 if (! m32r_is_insn (insn))
1625 fputs ("(?)", stream);
1626
1627 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1628 fputs ("(l)", stream);
1629
1630 else
1631 fputs ("(s)", stream);
1632 }
1633
1634 fprintf (stream, "\n");
1635 }
1636 }
1637 return m32r_issue_rate ();
1638 }
1639
1640 /* Indicate how many instructions can be issued at the same time.
1641 This is sort of a lie. The m32r can issue only 1 long insn at
1642 once, but it can issue 2 short insns. The default therefore is
1643 set at 2, but this can be overridden by the command line option
1644 -missue-rate=1 */
1645 static int
1646 m32r_issue_rate ()
1647 {
1648 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1649 }
1650
1651 /* If we have a machine that can issue a variable # of instructions
1652 per cycle, indicate how many more instructions can be issued
1653 after the current one. */
1654 static int
1655 m32r_variable_issue (stream, verbose, insn, how_many)
1656 FILE * stream;
1657 int verbose;
1658 rtx insn;
1659 int how_many;
1660 {
1661 int orig_odd_word_p = m32r_sched_odd_word_p;
1662 int short_p = FALSE;
1663
1664 how_many--;
1665 if (how_many > 0 && !TARGET_DEBUG)
1666 {
1667 if (! m32r_is_insn (insn))
1668 how_many++;
1669
1670 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1671 {
1672 how_many = 0;
1673 m32r_sched_odd_word_p = 0;
1674 }
1675 else
1676 {
1677 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1678 short_p = TRUE;
1679 }
1680 }
1681
1682 if (verbose > 7 && stream)
1683 fprintf (stream,
1684 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1685 short_p ? "short" : "long",
1686 INSN_UID (insn),
1687 orig_odd_word_p ? "odd" : "even",
1688 how_many);
1689
1690 return how_many;
1691 }
1692 \f
1693 /* Cost functions. */
1694
1695 static bool
1696 m32r_rtx_costs (x, code, outer_code, total)
1697 rtx x;
1698 int code, outer_code ATTRIBUTE_UNUSED;
1699 int *total;
1700 {
1701 switch (code)
1702 {
1703 /* Small integers are as cheap as registers. 4 byte values can be
1704 fetched as immediate constants - let's give that the cost of an
1705 extra insn. */
1706 case CONST_INT:
1707 if (INT16_P (INTVAL (x)))
1708 {
1709 *total = 0;
1710 return true;
1711 }
1712 /* FALLTHRU */
1713
1714 case CONST:
1715 case LABEL_REF:
1716 case SYMBOL_REF:
1717 *total = COSTS_N_INSNS (1);
1718 return true;
1719
1720 case CONST_DOUBLE:
1721 {
1722 rtx high, low;
1723 split_double (x, &high, &low);
1724 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1725 + !INT16_P (INTVAL (low)));
1726 return true;
1727 }
1728
1729 case MULT:
1730 *total = COSTS_N_INSNS (3);
1731 return true;
1732
1733 case DIV:
1734 case UDIV:
1735 case MOD:
1736 case UMOD:
1737 *total = COSTS_N_INSNS (10);
1738 return true;
1739
1740 default:
1741 return false;
1742 }
1743 }
1744 \f
1745 /* Type of function DECL.
1746
1747 The result is cached. To reset the cache at the end of a function,
1748 call with DECL = NULL_TREE. */
1749
1750 enum m32r_function_type
1751 m32r_compute_function_type (decl)
1752 tree decl;
1753 {
1754 /* Cached value. */
1755 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1756 /* Last function we were called for. */
1757 static tree last_fn = NULL_TREE;
1758
1759 /* Resetting the cached value? */
1760 if (decl == NULL_TREE)
1761 {
1762 fn_type = M32R_FUNCTION_UNKNOWN;
1763 last_fn = NULL_TREE;
1764 return fn_type;
1765 }
1766
1767 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1768 return fn_type;
1769
1770 /* Compute function type. */
1771 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1772 ? M32R_FUNCTION_INTERRUPT
1773 : M32R_FUNCTION_NORMAL);
1774
1775 last_fn = decl;
1776 return fn_type;
1777 }
1778 \f/* Function prologue/epilogue handlers. */
1779
1780 /* M32R stack frames look like:
1781
1782 Before call After call
1783 +-----------------------+ +-----------------------+
1784 | | | |
1785 high | local variables, | | local variables, |
1786 mem | reg save area, etc. | | reg save area, etc. |
1787 | | | |
1788 +-----------------------+ +-----------------------+
1789 | | | |
1790 | arguments on stack. | | arguments on stack. |
1791 | | | |
1792 SP+0->+-----------------------+ +-----------------------+
1793 | reg parm save area, |
1794 | only created for |
1795 | variable argument |
1796 | functions |
1797 +-----------------------+
1798 | previous frame ptr |
1799 +-----------------------+
1800 | |
1801 | register save area |
1802 | |
1803 +-----------------------+
1804 | return address |
1805 +-----------------------+
1806 | |
1807 | local variables |
1808 | |
1809 +-----------------------+
1810 | |
1811 | alloca allocations |
1812 | |
1813 +-----------------------+
1814 | |
1815 low | arguments on stack |
1816 memory | |
1817 SP+0->+-----------------------+
1818
1819 Notes:
1820 1) The "reg parm save area" does not exist for non variable argument fns.
1821 2) The "reg parm save area" can be eliminated completely if we saved regs
1822 containing anonymous args separately but that complicates things too
1823 much (so it's not done).
1824 3) The return address is saved after the register save area so as to have as
1825 many insns as possible between the restoration of `lr' and the `jmp lr'.
1826 */
1827
1828 /* Structure to be filled in by m32r_compute_frame_size with register
1829 save masks, and offsets for the current function. */
1830 struct m32r_frame_info
1831 {
1832 unsigned int total_size; /* # bytes that the entire frame takes up */
1833 unsigned int extra_size; /* # bytes of extra stuff */
1834 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1835 unsigned int args_size; /* # bytes that outgoing arguments take up */
1836 unsigned int reg_size; /* # bytes needed to store regs */
1837 unsigned int var_size; /* # bytes that variables take up */
1838 unsigned int gmask; /* mask of saved gp registers */
1839 unsigned int save_fp; /* nonzero if fp must be saved */
1840 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1841 int initialized; /* nonzero if frame size already calculated */
1842 };
1843
1844 /* Current frame information calculated by m32r_compute_frame_size. */
1845 static struct m32r_frame_info current_frame_info;
1846
1847 /* Zero structure to initialize current_frame_info. */
1848 static struct m32r_frame_info zero_frame_info;
1849
1850 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1851 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1852
1853 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1854 The return address and frame pointer are treated separately.
1855 Don't consider them here. */
1856 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1857 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1858 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1859
1860 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1861 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1862
1863 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1864 #define LONG_INSN_SIZE 4 /* size of long instructions */
1865
1866 /* Return the bytes needed to compute the frame pointer from the current
1867 stack pointer.
1868
1869 SIZE is the size needed for local variables. */
1870
1871 unsigned int
1872 m32r_compute_frame_size (size)
1873 int size; /* # of var. bytes allocated. */
1874 {
1875 int regno;
1876 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1877 unsigned int reg_size, frame_size;
1878 unsigned int gmask;
1879 enum m32r_function_type fn_type;
1880 int interrupt_p;
1881
1882 var_size = M32R_STACK_ALIGN (size);
1883 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1884 pretend_size = current_function_pretend_args_size;
1885 extra_size = FIRST_PARM_OFFSET (0);
1886 total_size = extra_size + pretend_size + args_size + var_size;
1887 reg_size = 0;
1888 gmask = 0;
1889
1890 /* See if this is an interrupt handler. Call used registers must be saved
1891 for them too. */
1892 fn_type = m32r_compute_function_type (current_function_decl);
1893 interrupt_p = M32R_INTERRUPT_P (fn_type);
1894
1895 /* Calculate space needed for registers. */
1896
1897 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1898 {
1899 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1900 {
1901 reg_size += UNITS_PER_WORD;
1902 gmask |= 1 << regno;
1903 }
1904 }
1905
1906 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1907 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1908
1909 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1910 * UNITS_PER_WORD);
1911 total_size += reg_size;
1912
1913 /* ??? Not sure this is necessary, and I don't think the epilogue
1914 handler will do the right thing if this changes total_size. */
1915 total_size = M32R_STACK_ALIGN (total_size);
1916
1917 frame_size = total_size - (pretend_size + reg_size);
1918
1919 /* Save computed information. */
1920 current_frame_info.total_size = total_size;
1921 current_frame_info.extra_size = extra_size;
1922 current_frame_info.pretend_size = pretend_size;
1923 current_frame_info.var_size = var_size;
1924 current_frame_info.args_size = args_size;
1925 current_frame_info.reg_size = reg_size;
1926 current_frame_info.gmask = gmask;
1927 current_frame_info.initialized = reload_completed;
1928
1929 /* Ok, we're done. */
1930 return total_size;
1931 }
1932 \f
1933 /* When the `length' insn attribute is used, this macro specifies the
1934 value to be assigned to the address of the first insn in a
1935 function. If not specified, 0 is used. */
1936
1937 int
1938 m32r_first_insn_address ()
1939 {
1940 if (! current_frame_info.initialized)
1941 m32r_compute_frame_size (get_frame_size ());
1942
1943 return 0;
1944 }
1945 \f
1946 /* Expand the m32r prologue as a series of insns. */
1947
1948 void
1949 m32r_expand_prologue ()
1950 {
1951 int regno;
1952 int frame_size;
1953 unsigned int gmask;
1954
1955 if (! current_frame_info.initialized)
1956 m32r_compute_frame_size (get_frame_size ());
1957
1958 gmask = current_frame_info.gmask;
1959
1960 /* These cases shouldn't happen. Catch them now. */
1961 if (current_frame_info.total_size == 0 && gmask)
1962 abort ();
1963
1964 /* Allocate space for register arguments if this is a variadic function. */
1965 if (current_frame_info.pretend_size != 0)
1966 {
1967 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1968 the wrong result on a 64-bit host. */
1969 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1970 emit_insn (gen_addsi3 (stack_pointer_rtx,
1971 stack_pointer_rtx,
1972 GEN_INT (-pretend_size)));
1973 }
1974
1975 /* Save any registers we need to and set up fp. */
1976
1977 if (current_frame_info.save_fp)
1978 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1979
1980 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1981
1982 /* Save any needed call-saved regs (and call-used if this is an
1983 interrupt handler). */
1984 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1985 {
1986 if ((gmask & (1 << regno)) != 0)
1987 emit_insn (gen_movsi_push (stack_pointer_rtx,
1988 gen_rtx_REG (Pmode, regno)));
1989 }
1990
1991 if (current_frame_info.save_lr)
1992 emit_insn (gen_movsi_push (stack_pointer_rtx,
1993 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1994
1995 /* Allocate the stack frame. */
1996 frame_size = (current_frame_info.total_size
1997 - (current_frame_info.pretend_size
1998 + current_frame_info.reg_size));
1999
2000 if (frame_size == 0)
2001 ; /* nothing to do */
2002 else if (frame_size <= 32768)
2003 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2004 GEN_INT (-frame_size)));
2005 else
2006 {
2007 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2008 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2009 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2010 }
2011
2012 if (frame_pointer_needed)
2013 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2014
2015 if (current_function_profile)
2016 emit_insn (gen_blockage ());
2017 }
2018
2019 \f
2020 /* Set up the stack and frame pointer (if desired) for the function.
2021 Note, if this is changed, you need to mirror the changes in
2022 m32r_compute_frame_size which calculates the prolog size. */
2023
2024 static void
2025 m32r_output_function_prologue (file, size)
2026 FILE * file;
2027 HOST_WIDE_INT size;
2028 {
2029 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2030
2031 /* If this is an interrupt handler, mark it as such. */
2032 if (M32R_INTERRUPT_P (fn_type))
2033 {
2034 fprintf (file, "\t%s interrupt handler\n",
2035 ASM_COMMENT_START);
2036 }
2037
2038 if (! current_frame_info.initialized)
2039 m32r_compute_frame_size (size);
2040
2041 /* This is only for the human reader. */
2042 fprintf (file,
2043 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2044 ASM_COMMENT_START,
2045 current_frame_info.var_size,
2046 current_frame_info.reg_size / 4,
2047 current_frame_info.args_size,
2048 current_frame_info.extra_size);
2049 }
2050 \f
2051 /* Do any necessary cleanup after a function to restore stack, frame,
2052 and regs. */
2053
2054 static void
2055 m32r_output_function_epilogue (file, size)
2056 FILE * file;
2057 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2058 {
2059 int regno;
2060 int noepilogue = FALSE;
2061 int total_size;
2062 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2063
2064 /* This is only for the human reader. */
2065 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2066
2067 if (!current_frame_info.initialized)
2068 abort ();
2069 total_size = current_frame_info.total_size;
2070
2071 if (total_size == 0)
2072 {
2073 rtx insn = get_last_insn ();
2074
2075 /* If the last insn was a BARRIER, we don't have to write any code
2076 because a jump (aka return) was put there. */
2077 if (GET_CODE (insn) == NOTE)
2078 insn = prev_nonnote_insn (insn);
2079 if (insn && GET_CODE (insn) == BARRIER)
2080 noepilogue = TRUE;
2081 }
2082
2083 if (!noepilogue)
2084 {
2085 unsigned int var_size = current_frame_info.var_size;
2086 unsigned int args_size = current_frame_info.args_size;
2087 unsigned int gmask = current_frame_info.gmask;
2088 int can_trust_sp_p = !current_function_calls_alloca;
2089 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2090 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2091
2092 /* The first thing to do is point the sp at the bottom of the register
2093 save area. */
2094 if (can_trust_sp_p)
2095 {
2096 unsigned int reg_offset = var_size + args_size;
2097 if (reg_offset == 0)
2098 ; /* nothing to do */
2099 else if (reg_offset < 128)
2100 fprintf (file, "\taddi %s,%s%d\n",
2101 sp_str, IMMEDIATE_PREFIX, reg_offset);
2102 else if (reg_offset < 32768)
2103 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2104 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2105 else
2106 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2107 reg_names[PROLOGUE_TMP_REGNUM],
2108 IMMEDIATE_PREFIX, reg_offset,
2109 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2110 }
2111 else if (frame_pointer_needed)
2112 {
2113 unsigned int reg_offset = var_size + args_size;
2114 if (reg_offset == 0)
2115 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2116 else if (reg_offset < 32768)
2117 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2118 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2119 else
2120 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2121 reg_names[PROLOGUE_TMP_REGNUM],
2122 IMMEDIATE_PREFIX, reg_offset,
2123 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2124 }
2125 else
2126 abort ();
2127
2128 if (current_frame_info.save_lr)
2129 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2130
2131 /* Restore any saved registers, in reverse order of course. */
2132 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2133 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2134 {
2135 if ((gmask & (1L << regno)) != 0)
2136 fprintf (file, "\tpop %s\n", reg_names[regno]);
2137 }
2138
2139 if (current_frame_info.save_fp)
2140 fprintf (file, "\tpop %s\n", fp_str);
2141
2142 /* Remove varargs area if present. */
2143 if (current_frame_info.pretend_size != 0)
2144 fprintf (file, "\taddi %s,%s%d\n",
2145 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2146
2147 /* Emit the return instruction. */
2148 if (M32R_INTERRUPT_P (fn_type))
2149 fprintf (file, "\trte\n");
2150 else
2151 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2152 }
2153
2154 #if 0 /* no longer needed */
2155 /* Ensure the function cleanly ends on a 32 bit boundary. */
2156 fprintf (file, "\t.fillinsn\n");
2157 #endif
2158
2159 /* Reset state info for each function. */
2160 current_frame_info = zero_frame_info;
2161 m32r_compute_function_type (NULL_TREE);
2162 }
2163 \f
2164 /* Return nonzero if this function is known to have a null or 1 instruction
2165 epilogue. */
2166
2167 int
2168 direct_return ()
2169 {
2170 if (!reload_completed)
2171 return FALSE;
2172
2173 if (! current_frame_info.initialized)
2174 m32r_compute_frame_size (get_frame_size ());
2175
2176 return current_frame_info.total_size == 0;
2177 }
2178
2179 \f
2180 /* PIC */
2181
2182 /* Emit special PIC prologues and epilogues. */
2183
2184 void
2185 m32r_finalize_pic ()
2186 {
2187 /* nothing to do */
2188 }
2189 \f
2190 /* Nested function support. */
2191
2192 /* Emit RTL insns to initialize the variable parts of a trampoline.
2193 FNADDR is an RTX for the address of the function's pure code.
2194 CXT is an RTX for the static chain value for the function. */
2195
2196 void
2197 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2198 rtx tramp ATTRIBUTE_UNUSED;
2199 rtx fnaddr ATTRIBUTE_UNUSED;
2200 rtx cxt ATTRIBUTE_UNUSED;
2201 {
2202 }
2203 \f
2204 /* Set the cpu type and print out other fancy things,
2205 at the top of the file. */
2206
2207 void
2208 m32r_asm_file_start (file)
2209 FILE * file;
2210 {
2211 if (flag_verbose_asm)
2212 fprintf (file, "%s M32R/D special options: -G %d\n",
2213 ASM_COMMENT_START, g_switch_value);
2214 }
2215 \f
2216 /* Print operand X (an rtx) in assembler syntax to file FILE.
2217 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2218 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2219
2220 void
2221 m32r_print_operand (file, x, code)
2222 FILE * file;
2223 rtx x;
2224 int code;
2225 {
2226 rtx addr;
2227
2228 switch (code)
2229 {
2230 /* The 's' and 'p' codes are used by output_block_move() to
2231 indicate post-increment 's'tores and 'p're-increment loads. */
2232 case 's':
2233 if (GET_CODE (x) == REG)
2234 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2235 else
2236 output_operand_lossage ("invalid operand to %%s code");
2237 return;
2238
2239 case 'p':
2240 if (GET_CODE (x) == REG)
2241 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2242 else
2243 output_operand_lossage ("invalid operand to %%p code");
2244 return;
2245
2246 case 'R' :
2247 /* Write second word of DImode or DFmode reference,
2248 register or memory. */
2249 if (GET_CODE (x) == REG)
2250 fputs (reg_names[REGNO (x)+1], file);
2251 else if (GET_CODE (x) == MEM)
2252 {
2253 fprintf (file, "@(");
2254 /* Handle possible auto-increment. Since it is pre-increment and
2255 we have already done it, we can just use an offset of four. */
2256 /* ??? This is taken from rs6000.c I think. I don't think it is
2257 currently necessary, but keep it around. */
2258 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2259 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2260 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2261 else
2262 output_address (plus_constant (XEXP (x, 0), 4));
2263 fputc (')', file);
2264 }
2265 else
2266 output_operand_lossage ("invalid operand to %%R code");
2267 return;
2268
2269 case 'H' : /* High word */
2270 case 'L' : /* Low word */
2271 if (GET_CODE (x) == REG)
2272 {
2273 /* L = least significant word, H = most significant word */
2274 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2275 fputs (reg_names[REGNO (x)], file);
2276 else
2277 fputs (reg_names[REGNO (x)+1], file);
2278 }
2279 else if (GET_CODE (x) == CONST_INT
2280 || GET_CODE (x) == CONST_DOUBLE)
2281 {
2282 rtx first, second;
2283
2284 split_double (x, &first, &second);
2285 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2286 code == 'L' ? INTVAL (first) : INTVAL (second));
2287 }
2288 else
2289 output_operand_lossage ("invalid operand to %%H/%%L code");
2290 return;
2291
2292 case 'A' :
2293 {
2294 char str[30];
2295
2296 if (GET_CODE (x) != CONST_DOUBLE
2297 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2298 fatal_insn ("bad insn for 'A'", x);
2299
2300 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2301 fprintf (file, "%s", str);
2302 return;
2303 }
2304
2305 case 'B' : /* Bottom half */
2306 case 'T' : /* Top half */
2307 /* Output the argument to a `seth' insn (sets the Top half-word).
2308 For constants output arguments to a seth/or3 pair to set Top and
2309 Bottom halves. For symbols output arguments to a seth/add3 pair to
2310 set Top and Bottom halves. The difference exists because for
2311 constants seth/or3 is more readable but for symbols we need to use
2312 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2313 switch (GET_CODE (x))
2314 {
2315 case CONST_INT :
2316 case CONST_DOUBLE :
2317 {
2318 rtx first, second;
2319
2320 split_double (x, &first, &second);
2321 x = WORDS_BIG_ENDIAN ? second : first;
2322 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2323 (code == 'B'
2324 ? INTVAL (x) & 0xffff
2325 : (INTVAL (x) >> 16) & 0xffff));
2326 }
2327 return;
2328 case CONST :
2329 case SYMBOL_REF :
2330 if (code == 'B'
2331 && small_data_operand (x, VOIDmode))
2332 {
2333 fputs ("sda(", file);
2334 output_addr_const (file, x);
2335 fputc (')', file);
2336 return;
2337 }
2338 /* fall through */
2339 case LABEL_REF :
2340 fputs (code == 'T' ? "shigh(" : "low(", file);
2341 output_addr_const (file, x);
2342 fputc (')', file);
2343 return;
2344 default :
2345 output_operand_lossage ("invalid operand to %%T/%%B code");
2346 return;
2347 }
2348 break;
2349
2350 case 'U' :
2351 /* ??? wip */
2352 /* Output a load/store with update indicator if appropriate. */
2353 if (GET_CODE (x) == MEM)
2354 {
2355 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2356 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2357 fputs (".a", file);
2358 }
2359 else
2360 output_operand_lossage ("invalid operand to %%U code");
2361 return;
2362
2363 case 'N' :
2364 /* Print a constant value negated. */
2365 if (GET_CODE (x) == CONST_INT)
2366 output_addr_const (file, GEN_INT (- INTVAL (x)));
2367 else
2368 output_operand_lossage ("invalid operand to %%N code");
2369 return;
2370
2371 case 'X' :
2372 /* Print a const_int in hex. Used in comments. */
2373 if (GET_CODE (x) == CONST_INT)
2374 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2375 return;
2376
2377 case '#' :
2378 fputs (IMMEDIATE_PREFIX, file);
2379 return;
2380
2381 #if 0 /* ??? no longer used */
2382 case '@' :
2383 fputs (reg_names[SDA_REGNUM], file);
2384 return;
2385 #endif
2386
2387 case 0 :
2388 /* Do nothing special. */
2389 break;
2390
2391 default :
2392 /* Unknown flag. */
2393 output_operand_lossage ("invalid operand output code");
2394 }
2395
2396 switch (GET_CODE (x))
2397 {
2398 case REG :
2399 fputs (reg_names[REGNO (x)], file);
2400 break;
2401
2402 case MEM :
2403 addr = XEXP (x, 0);
2404 if (GET_CODE (addr) == PRE_INC)
2405 {
2406 if (GET_CODE (XEXP (addr, 0)) != REG)
2407 fatal_insn ("pre-increment address is not a register", x);
2408
2409 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2410 }
2411 else if (GET_CODE (addr) == PRE_DEC)
2412 {
2413 if (GET_CODE (XEXP (addr, 0)) != REG)
2414 fatal_insn ("pre-decrement address is not a register", x);
2415
2416 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2417 }
2418 else if (GET_CODE (addr) == POST_INC)
2419 {
2420 if (GET_CODE (XEXP (addr, 0)) != REG)
2421 fatal_insn ("post-increment address is not a register", x);
2422
2423 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2424 }
2425 else
2426 {
2427 fputs ("@(", file);
2428 output_address (XEXP (x, 0));
2429 fputc (')', file);
2430 }
2431 break;
2432
2433 case CONST_DOUBLE :
2434 /* We handle SFmode constants here as output_addr_const doesn't. */
2435 if (GET_MODE (x) == SFmode)
2436 {
2437 REAL_VALUE_TYPE d;
2438 long l;
2439
2440 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2441 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2442 fprintf (file, "0x%08lx", l);
2443 break;
2444 }
2445
2446 /* Fall through. Let output_addr_const deal with it. */
2447
2448 default :
2449 output_addr_const (file, x);
2450 break;
2451 }
2452 }
2453
2454 /* Print a memory address as an operand to reference that memory location. */
2455
2456 void
2457 m32r_print_operand_address (file, addr)
2458 FILE * file;
2459 rtx addr;
2460 {
2461 register rtx base;
2462 register rtx index = 0;
2463 int offset = 0;
2464
2465 switch (GET_CODE (addr))
2466 {
2467 case REG :
2468 fputs (reg_names[REGNO (addr)], file);
2469 break;
2470
2471 case PLUS :
2472 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2473 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2474 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2475 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2476 else
2477 base = XEXP (addr, 0), index = XEXP (addr, 1);
2478 if (GET_CODE (base) == REG)
2479 {
2480 /* Print the offset first (if present) to conform to the manual. */
2481 if (index == 0)
2482 {
2483 if (offset != 0)
2484 fprintf (file, "%d,", offset);
2485 fputs (reg_names[REGNO (base)], file);
2486 }
2487 /* The chip doesn't support this, but left in for generality. */
2488 else if (GET_CODE (index) == REG)
2489 fprintf (file, "%s,%s",
2490 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2491 /* Not sure this can happen, but leave in for now. */
2492 else if (GET_CODE (index) == SYMBOL_REF)
2493 {
2494 output_addr_const (file, index);
2495 fputc (',', file);
2496 fputs (reg_names[REGNO (base)], file);
2497 }
2498 else
2499 fatal_insn ("bad address", addr);
2500 }
2501 else if (GET_CODE (base) == LO_SUM)
2502 {
2503 if (index != 0
2504 || GET_CODE (XEXP (base, 0)) != REG)
2505 abort ();
2506 if (small_data_operand (XEXP (base, 1), VOIDmode))
2507 fputs ("sda(", file);
2508 else
2509 fputs ("low(", file);
2510 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2511 fputs ("),", file);
2512 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2513 }
2514 else
2515 fatal_insn ("bad address", addr);
2516 break;
2517
2518 case LO_SUM :
2519 if (GET_CODE (XEXP (addr, 0)) != REG)
2520 fatal_insn ("lo_sum not of register", addr);
2521 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2522 fputs ("sda(", file);
2523 else
2524 fputs ("low(", file);
2525 output_addr_const (file, XEXP (addr, 1));
2526 fputs ("),", file);
2527 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2528 break;
2529
2530 case PRE_INC : /* Assume SImode */
2531 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2532 break;
2533
2534 case PRE_DEC : /* Assume SImode */
2535 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2536 break;
2537
2538 case POST_INC : /* Assume SImode */
2539 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2540 break;
2541
2542 default :
2543 output_addr_const (file, addr);
2544 break;
2545 }
2546 }
2547
2548 /* Return true if the operands are the constants 0 and 1. */
2549 int
2550 zero_and_one (operand1, operand2)
2551 rtx operand1;
2552 rtx operand2;
2553 {
2554 return
2555 GET_CODE (operand1) == CONST_INT
2556 && GET_CODE (operand2) == CONST_INT
2557 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2558 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2559 }
2560
2561 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2562 int
2563 conditional_move_operand (operand, mode)
2564 rtx operand;
2565 enum machine_mode mode;
2566 {
2567 /* Only defined for simple integers so far... */
2568 if (mode != SImode && mode != HImode && mode != QImode)
2569 return FALSE;
2570
2571 /* At the moment we can hanndle moving registers and loading constants. */
2572 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2573
2574 switch (GET_CODE (operand))
2575 {
2576 case REG:
2577 return 1;
2578
2579 case CONST_INT:
2580 return INT8_P (INTVAL (operand));
2581
2582 default:
2583 #if 0
2584 fprintf (stderr, "Test for cond move op of type: %s\n",
2585 GET_RTX_NAME (GET_CODE (operand)));
2586 #endif
2587 return 0;
2588 }
2589 }
2590
2591 /* Return true if the code is a test of the carry bit */
2592 int
2593 carry_compare_operand (op, mode)
2594 rtx op;
2595 enum machine_mode mode ATTRIBUTE_UNUSED;
2596 {
2597 rtx x;
2598
2599 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2600 return FALSE;
2601
2602 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2603 return FALSE;
2604
2605 x = XEXP (op, 0);
2606 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2607 return FALSE;
2608
2609 x = XEXP (op, 1);
2610 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2611 return FALSE;
2612
2613 return TRUE;
2614 }
2615
2616 /* Generate the correct assembler code to handle the conditional loading of a
2617 value into a register. It is known that the operands satisfy the
2618 conditional_move_operand() function above. The destination is operand[0].
2619 The condition is operand [1]. The 'true' value is operand [2] and the
2620 'false' value is operand [3]. */
2621 char *
2622 emit_cond_move (operands, insn)
2623 rtx * operands;
2624 rtx insn ATTRIBUTE_UNUSED;
2625 {
2626 static char buffer [100];
2627 const char * dest = reg_names [REGNO (operands [0])];
2628
2629 buffer [0] = 0;
2630
2631 /* Destination must be a register. */
2632 if (GET_CODE (operands [0]) != REG)
2633 abort();
2634 if (! conditional_move_operand (operands [2], SImode))
2635 abort();
2636 if (! conditional_move_operand (operands [3], SImode))
2637 abort();
2638
2639 /* Check to see if the test is reversed. */
2640 if (GET_CODE (operands [1]) == NE)
2641 {
2642 rtx tmp = operands [2];
2643 operands [2] = operands [3];
2644 operands [3] = tmp;
2645 }
2646
2647 sprintf (buffer, "mvfc %s, cbr", dest);
2648
2649 /* If the true value was '0' then we need to invert the results of the move. */
2650 if (INTVAL (operands [2]) == 0)
2651 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2652 dest, dest);
2653
2654 return buffer;
2655 }
2656
2657 /* Returns true if the registers contained in the two
2658 rtl expressions are different. */
2659 int
2660 m32r_not_same_reg (a, b)
2661 rtx a;
2662 rtx b;
2663 {
2664 int reg_a = -1;
2665 int reg_b = -2;
2666
2667 while (GET_CODE (a) == SUBREG)
2668 a = SUBREG_REG (a);
2669
2670 if (GET_CODE (a) == REG)
2671 reg_a = REGNO (a);
2672
2673 while (GET_CODE (b) == SUBREG)
2674 b = SUBREG_REG (b);
2675
2676 if (GET_CODE (b) == REG)
2677 reg_b = REGNO (b);
2678
2679 return reg_a != reg_b;
2680 }
2681
2682 \f
2683 /* Use a library function to move some bytes. */
2684 static void
2685 block_move_call (dest_reg, src_reg, bytes_rtx)
2686 rtx dest_reg;
2687 rtx src_reg;
2688 rtx bytes_rtx;
2689 {
2690 /* We want to pass the size as Pmode, which will normally be SImode
2691 but will be DImode if we are using 64 bit longs and pointers. */
2692 if (GET_MODE (bytes_rtx) != VOIDmode
2693 && GET_MODE (bytes_rtx) != Pmode)
2694 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2695
2696 #ifdef TARGET_MEM_FUNCTIONS
2697 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2698 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2699 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2700 TREE_UNSIGNED (sizetype)),
2701 TYPE_MODE (sizetype));
2702 #else
2703 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2704 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2705 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2706 TREE_UNSIGNED (integer_type_node)),
2707 TYPE_MODE (integer_type_node));
2708 #endif
2709 }
2710
2711 /* The maximum number of bytes to copy using pairs of load/store instructions.
2712 If a block is larger than this then a loop will be generated to copy
2713 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2714 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2715 string copy in it. */
2716 #define MAX_MOVE_BYTES 32
2717
2718 /* Expand string/block move operations.
2719
2720 operands[0] is the pointer to the destination.
2721 operands[1] is the pointer to the source.
2722 operands[2] is the number of bytes to move.
2723 operands[3] is the alignment. */
2724
2725 void
2726 m32r_expand_block_move (operands)
2727 rtx operands[];
2728 {
2729 rtx orig_dst = operands[0];
2730 rtx orig_src = operands[1];
2731 rtx bytes_rtx = operands[2];
2732 rtx align_rtx = operands[3];
2733 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2734 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2735 int align = INTVAL (align_rtx);
2736 int leftover;
2737 rtx src_reg;
2738 rtx dst_reg;
2739
2740 if (constp && bytes <= 0)
2741 return;
2742
2743 /* Move the address into scratch registers. */
2744 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2745 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2746
2747 if (align > UNITS_PER_WORD)
2748 align = UNITS_PER_WORD;
2749
2750 /* If we prefer size over speed, always use a function call.
2751 If we do not know the size, use a function call.
2752 If the blocks are not word aligned, use a function call. */
2753 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2754 {
2755 block_move_call (dst_reg, src_reg, bytes_rtx);
2756 return;
2757 }
2758
2759 leftover = bytes % MAX_MOVE_BYTES;
2760 bytes -= leftover;
2761
2762 /* If necessary, generate a loop to handle the bulk of the copy. */
2763 if (bytes)
2764 {
2765 rtx label = NULL_RTX;
2766 rtx final_src = NULL_RTX;
2767 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2768 rtx rounded_total = GEN_INT (bytes);
2769
2770 /* If we are going to have to perform this loop more than
2771 once, then generate a label and compute the address the
2772 source register will contain upon completion of the final
2773 itteration. */
2774 if (bytes > MAX_MOVE_BYTES)
2775 {
2776 final_src = gen_reg_rtx (Pmode);
2777
2778 if (INT16_P(bytes))
2779 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2780 else
2781 {
2782 emit_insn (gen_movsi (final_src, rounded_total));
2783 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2784 }
2785
2786 label = gen_label_rtx ();
2787 emit_label (label);
2788 }
2789
2790 /* It is known that output_block_move() will update src_reg to point
2791 to the word after the end of the source block, and dst_reg to point
2792 to the last word of the destination block, provided that the block
2793 is MAX_MOVE_BYTES long. */
2794 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2795 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2796
2797 if (bytes > MAX_MOVE_BYTES)
2798 {
2799 emit_insn (gen_cmpsi (src_reg, final_src));
2800 emit_jump_insn (gen_bne (label));
2801 }
2802 }
2803
2804 if (leftover)
2805 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2806 }
2807
2808 \f
2809 /* Emit load/stores for a small constant word aligned block_move.
2810
2811 operands[0] is the memory address of the destination.
2812 operands[1] is the memory address of the source.
2813 operands[2] is the number of bytes to move.
2814 operands[3] is a temp register.
2815 operands[4] is a temp register. */
2816
2817 void
2818 m32r_output_block_move (insn, operands)
2819 rtx insn ATTRIBUTE_UNUSED;
2820 rtx operands[];
2821 {
2822 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2823 int first_time;
2824 int got_extra = 0;
2825
2826 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2827 abort ();
2828
2829 /* We do not have a post-increment store available, so the first set of
2830 stores are done without any increment, then the remaining ones can use
2831 the pre-increment addressing mode.
2832
2833 Note: expand_block_move() also relies upon this behavior when building
2834 loops to copy large blocks. */
2835 first_time = 1;
2836
2837 while (bytes > 0)
2838 {
2839 if (bytes >= 8)
2840 {
2841 if (first_time)
2842 {
2843 output_asm_insn ("ld\t%3, %p1", operands);
2844 output_asm_insn ("ld\t%4, %p1", operands);
2845 output_asm_insn ("st\t%3, @%0", operands);
2846 output_asm_insn ("st\t%4, %s0", operands);
2847 }
2848 else
2849 {
2850 output_asm_insn ("ld\t%3, %p1", operands);
2851 output_asm_insn ("ld\t%4, %p1", operands);
2852 output_asm_insn ("st\t%3, %s0", operands);
2853 output_asm_insn ("st\t%4, %s0", operands);
2854 }
2855
2856 bytes -= 8;
2857 }
2858 else if (bytes >= 4)
2859 {
2860 if (bytes > 4)
2861 got_extra = 1;
2862
2863 output_asm_insn ("ld\t%3, %p1", operands);
2864
2865 if (got_extra)
2866 output_asm_insn ("ld\t%4, %p1", operands);
2867
2868 if (first_time)
2869 output_asm_insn ("st\t%3, @%0", operands);
2870 else
2871 output_asm_insn ("st\t%3, %s0", operands);
2872
2873 bytes -= 4;
2874 }
2875 else
2876 {
2877 /* Get the entire next word, even though we do not want all of it.
2878 The saves us from doing several smaller loads, and we assume that
2879 we cannot cause a page fault when at least part of the word is in
2880 valid memory [since we don't get called if things aren't properly
2881 aligned]. */
2882 int dst_offset = first_time ? 0 : 4;
2883 int last_shift;
2884 rtx my_operands[3];
2885
2886 /* If got_extra is true then we have already loaded
2887 the next word as part of loading and storing the previous word. */
2888 if (! got_extra)
2889 output_asm_insn ("ld\t%4, @%1", operands);
2890
2891 if (bytes >= 2)
2892 {
2893 bytes -= 2;
2894
2895 output_asm_insn ("sra3\t%3, %4, #16", operands);
2896 my_operands[0] = operands[3];
2897 my_operands[1] = GEN_INT (dst_offset);
2898 my_operands[2] = operands[0];
2899 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2900
2901 /* If there is a byte left to store then increment the
2902 destination address and shift the contents of the source
2903 register down by 8 bits. We could not do the address
2904 increment in the store half word instruction, because it does
2905 not have an auto increment mode. */
2906 if (bytes > 0) /* assert (bytes == 1) */
2907 {
2908 dst_offset += 2;
2909 last_shift = 8;
2910 }
2911 }
2912 else
2913 last_shift = 24;
2914
2915 if (bytes > 0)
2916 {
2917 my_operands[0] = operands[4];
2918 my_operands[1] = GEN_INT (last_shift);
2919 output_asm_insn ("srai\t%0, #%1", my_operands);
2920 my_operands[0] = operands[4];
2921 my_operands[1] = GEN_INT (dst_offset);
2922 my_operands[2] = operands[0];
2923 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2924 }
2925
2926 bytes = 0;
2927 }
2928
2929 first_time = 0;
2930 }
2931 }
2932
2933 /* Return true if op is an integer constant, less than or equal to
2934 MAX_MOVE_BYTES. */
2935 int
2936 m32r_block_immediate_operand (op, mode)
2937 rtx op;
2938 enum machine_mode mode ATTRIBUTE_UNUSED;
2939 {
2940 if (GET_CODE (op) != CONST_INT
2941 || INTVAL (op) > MAX_MOVE_BYTES
2942 || INTVAL (op) <= 0)
2943 return 0;
2944
2945 return 1;
2946 }
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