| blob | cb3b8c66d152eb958a2cfbcfb8f8bf906a3df1d7 |
1 2024-01-24 Martin Jambor <mjambor@suse.cz>
3 PR ipa/108007
4 PR ipa/112616
5 * cgraph.h (cgraph_edge): Add a parameter to
6 redirect_call_stmt_to_callee.
7 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
8 parameter to modify_call.
9 (ipa_release_ssas_in_hash): Declare.
10 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
11 parameter killed_ssas, pass it to padjs->modify_call.
12 * ipa-param-manipulation.cc (purge_all_uses): New function.
13 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
14 Instead of substituting uses, invoke purge_all_uses. If
15 hash of killed SSAs has not been provided, create a temporary one
16 and release SSAs that have been added to it.
17 (compare_ssa_versions): New function.
18 (ipa_release_ssas_in_hash): Likewise.
19 * tree-inline.cc (redirect_all_calls): Create
20 id->killed_new_ssa_names earlier, pass it to edge redirection,
21 adjust a comment.
22 (copy_body): Release SSAs in id->killed_new_ssa_names.
24 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
26 PR target/113486
27 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
28 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
30 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
32 PR target/113095
33 * config/riscv/sfb.md: New splitters to rewrite single bit
34 sign extension as the condition to SFB instructions.
36 2024-01-24 Jan Hubicka <jh@suse.cz>
38 PR middle-end/88345
39 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
40 (fmin-function-alignment): New parameter.
41 * doc/invoke.texi: (-fmin-function-alignment): Document.
42 (-falign-functions,-falign-loops,-falign-labels): Mention that
43 aglinments are ignored in cold code.
44 * varasm.cc (assemble_start_function): Handle min-function-alignment.
46 2024-01-24 Tamar Christina <tamar.christina@arm.com>
48 PR target/109636
49 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
50 mulv2di3): Remove.
51 * config/aarch64/iterators.md (VQDIV): Remove.
52 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
53 SVE_I_SIMD_DI): New.
54 (VPRED, sve_lane_con): Add V4SI and V2DI.
55 * config/aarch64/aarch64-sve.md (<optab><mode>3,
56 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
57 (mul<mode>3): New, split from <optab><mode>3.
58 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
59 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
60 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
61 SVE_FULL_HSDI_SIMD_DI.
63 2024-01-24 Tamar Christina <tamar.christina@arm.com>
65 PR tree-optimization/113552
66 * config/aarch64/aarch64.cc
67 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
69 2024-01-24 Martin Jambor <mjambor@suse.cz>
71 PR ipa/113490
72 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
73 count is equal or greater than the limit. Use the limit from the
74 callee.
76 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
78 * configure.ac: Detect the explicit relocs support for
79 mips, and define C macro MIPS_EXPLICIT_RELOCS.
80 * config.in: Regenerated.
81 * configure: Regenerated.
82 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
83 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
84 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
85 !TARGET_EXPLICIT_RELOCS instead of just set it.
86 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
87 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
88 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
89 and define -m(no-)explicit-relocs as aliases.
91 2024-01-24 Alex Coplan <alex.coplan@arm.com>
93 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
94 to 1.
95 (-mlate-ldp-fusion): Likewise.
97 2024-01-24 Tamar Christina <tamar.christina@arm.com>
99 * tree-vect-loop.cc (vect_get_vect_def,
100 vect_create_epilog_for_reduction): Rename main_exit_p to
101 last_val_reduc_p.
103 2024-01-24 Tamar Christina <tamar.christina@arm.com>
105 PR tree-optimization/113364
106 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
107 early exits then we must reduce from the first offset for all of them.
109 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
111 PR target/113495
112 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
113 (get_regno): Ditto.
114 (get_bb_index): Ditto.
115 (pre_vsetvl::compute_avl_def_data): Ditto.
116 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
117 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
119 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
120 Richard Sandiford <richard.sandiford@arm.com>
122 PR target/100942
123 * ccmp.cc (ccmp_candidate_p): Add outer argument.
124 Allow if the outer is true and the lhs is used more
125 than once.
126 (expand_ccmp_expr): Update call to ccmp_candidate_p.
127 * expr.h (expand_expr_real_gassign): Declare.
128 * expr.cc (expand_expr_real_gassign): New function, split out from...
129 (expand_expr_real_1): ...here.
130 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
132 2024-01-23 Alex Coplan <alex.coplan@arm.com>
134 PR target/113089
135 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
136 (fixup_debug_use): New.
137 (fixup_debug_uses_trailing_add): New.
138 (fixup_debug_uses): New. Use it ...
139 (ldp_bb_info::fuse_pair): ... here.
140 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
141 fix up debug uses of the base register that are affected by
142 folding in the trailing add insn.
144 2024-01-23 Alex Coplan <alex.coplan@arm.com>
146 PR target/113089
147 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
148 Update trailing nondebug uses of the base register in the case
149 of cancelling writeback.
151 2024-01-23 Alex Coplan <alex.coplan@arm.com>
153 PR target/113089
154 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
155 (debug_insn_use_iterator): New.
156 (set_info::first_debug_insn_use): New.
157 (set_info::debug_insn_uses): New.
158 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
159 (set_info::first_debug_insn_use): New.
160 (set_info::debug_insn_uses): New.
162 2024-01-23 Alex Coplan <alex.coplan@arm.com>
164 PR target/113356
165 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
166 Don't record hazards against the opposite insn in the pair.
168 2024-01-23 Alex Coplan <alex.coplan@arm.com>
170 PR target/113070
171 * config/aarch64/aarch64-ldp-fusion.cc
172 (struct stp_change_builder): New.
173 (decide_stp_strategy): Reanme to ...
174 (try_repurpose_store): ... this.
175 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
176 construct stp changes. Fix up uses when inserting new stp insns.
178 2024-01-23 Alex Coplan <alex.coplan@arm.com>
180 PR target/113070
181 * rtl-ssa.h: Include hash-set.h.
182 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
183 new_sets parameter and use it to keep track of new user-created sets.
184 (function_info::apply_changes_to_insn): Also call add_def on new sets.
185 (function_info::change_insns): Add hash_set to keep track of new
186 user-created defs. Plumb it through.
187 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
188 apply_changes_to_insn.
190 2024-01-23 Alex Coplan <alex.coplan@arm.com>
192 PR target/113070
193 * rtl-ssa/accesses.cc (function_info::create_use): New.
194 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
195 Ensure new uses end up referring to permanent defs.
196 * rtl-ssa/functions.h (function_info::create_use): Declare.
198 2024-01-23 Alex Coplan <alex.coplan@arm.com>
200 PR target/113070
201 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
202 to finalize_new_accesses from the backwards placement loop, run it
203 forwards in a separate loop.
205 2024-01-23 Richard Biener <rguenther@suse.de>
207 PR tree-optimization/113552
208 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
209 floor_log2 instead of exact_log2 on the number of calls.
211 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
212 Jakub Jelinek <jakub@redhat.com>
214 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
215 decl.
217 2024-01-23 Richard Biener <rguenther@suse.de>
219 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
220 Separate single and multi-exit case when creating PHIs between
221 the main and epilogue.
223 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
225 PR target/112989
226 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
227 MODE_single variants of functions that don't take tuple arguments.
229 2024-01-23 Alex Coplan <alex.coplan@arm.com>
231 PR target/113114
232 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
233 Don't assert recog success, just punt if the writeback pair
234 isn't recognized.
236 2024-01-23 Jakub Jelinek <jakub@redhat.com>
238 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
239 ATTRIBUTE_UNUSED to decl.
241 2024-01-23 Richard Biener <rguenther@suse.de>
243 PR debug/107058
244 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
245 handle unexpected but bogus DIE contexts when not checking
246 enabled.
248 2024-01-23 Jakub Jelinek <jakub@redhat.com>
250 PR tree-optimization/113462
251 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
252 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
253 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
254 sizes between 129 and 8192 bytes.
256 2024-01-23 Xi Ruoyao <xry111@xry111.site>
258 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
259 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
260 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
261 (loongarch_call_tls_get_addr): Do not split symbols of
262 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
263 EXPLICIT_RELOCS_AUTO.
265 2024-01-23 Richard Biener <rguenther@suse.de>
267 * alias.cc (known_base_value_p): Remove.
268 (find_base_value): Remove PLUS/MINUS handling
269 when both operands are not CONST_INT_P.
271 2024-01-23 Richard Biener <rguenther@suse.de>
273 PR rtl-optimization/113255
274 * alias.cc (find_base_term): Remove PLUS/MINUS handling
275 when both operands are not CONST_INT_P.
277 2024-01-23 Richard Biener <rguenther@suse.de>
279 PR debug/112718
280 * dwarf2out.cc (dwarf2out_finish): Reset all type units
281 for the fat part of an LTO compile.
283 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
285 * doc/sourcebuild.texi: Add attributes for keywords.
287 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
289 PR c++/90463
290 * doc/invoke.texi (Warning Options): Correct lists of options
291 enabled by -Wall and -Wextra by checking against common.opt
292 and c-family/c.opt.
294 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
296 PR target/113030
297 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
298 instead of cpu_optaliases.
299 (check_arch): Use arch_opt_alias instead of arch_optaliases.
301 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
303 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
304 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
305 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
307 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
309 PR target/109092
310 * config/riscv/riscv.md: Use reg instead of subreg.
312 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
314 PR other/111966
315 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
316 to match the compiler default.
317 (simple_object_copy_lto_debug_sections): Never unlink the outfile
318 on error as the caller does so.
319 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
320 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
322 2024-01-22 Richard Biener <rguenther@suse.de>
324 PR tree-optimization/113373
325 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
326 Create LC PHIs in the exit blocks where necessary.
327 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
328 to handle missing LC PHIs.
329 (find_connected_edge): Remove.
330 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
332 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
334 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
336 2024-01-22 xuli <xuli1@eswincomputing.com>
338 PR target/113420
339 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
340 (registered_function::overloaded_hash):refactor.
341 (resolve_overloaded_builtin):avoid internal ICE.
343 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
345 PR target/82420
346 PR target/111279
347 * calls.cc (emit_library_call_value_1): Pass valid TYPE
348 to emit_push_insn.
349 * expr.cc (emit_push_insn): Likewise.
351 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
353 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
354 correcction version of last change.
356 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
358 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
359 fix bugs in signature.
361 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
362 Richard Biener <rguenther@suse.de>
364 PR rtl-optimization/111267
365 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
366 profitable_p method to likely_profitable_p.
367 (try_fwprop_subst_node): Update call to likely_profitable_p.
368 Only bail-out early when !prop.likely_profitable_p for instructions
369 that are not single sets. When comparing costs, bail-out if the
370 cost is unchanged and !prop.likely_profitable_p.
372 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
374 PR c++/90464
375 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
376 isn't enabled by -Wunused unless -Wextra is provided, and that
377 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
378 -Wunused doesn't enable -Wunused-* options documented as behaving
379 otherwise, and list them explicitly.
381 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
383 PR c/109708
384 * doc/invoke.texi (Warning Options): Fix broken example and
385 clean up/reorganize the others. Also describe what the short-form
386 options mean.
388 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
390 PR c/102998
391 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
392 (Warning Options): Correct/edit discussion of -Warray-parameter
393 to make the first example less confusing, and fill in missing info.
395 2024-01-20 Jakub Jelinek <jakub@redhat.com>
397 PR tree-optimization/113462
398 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
399 Handle rhs1 INTEGER_CST like SSA_NAME.
401 2024-01-20 Jakub Jelinek <jakub@redhat.com>
403 PR tree-optimization/113491
404 * tree-switch-conversion.cc (switch_conversion::build_constructors):
405 If elt.index has precision higher than sizetype, fold_convert it to
406 sizetype.
407 (switch_conversion::array_value_type): Return type if type is
408 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
409 (switch_conversion::build_arrays): Use unsigned_type_for rather than
410 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
411 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
412 higher than sizetype, use sizetype as tidx type and fold_convert the
413 subtraction to sizetype.
415 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
417 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
418 (riscv_vector_mode_supported_any_target_p): Ditto.
420 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
422 PR target/110934
423 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
424 (TARGET_ZERO_CALL_USED_REGS): Define.
426 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
428 PR target/108640
429 * config/m68k/m68k.cc (output_andsi3): Use QImode for
430 address adjusted for 1-byte RMW access.
431 (output_iorsi3): Likewise.
432 (output_xorsi3): Likewise.
434 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
436 * doc/invoke.texi (RISC-V Options): Add list of supported
437 extensions.
439 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
441 PR target/113495
442 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
443 (RVV_VUNDEF): Ditto.
444 * config/riscv/riscv-vsetvl.cc: Add timevar.
446 2024-01-19 Richard Biener <rguenther@suse.de>
448 PR debug/113488
449 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
450 an early DIE but there should be, do not pretend there is.
452 2024-01-19 Richard Biener <rguenther@suse.de>
454 PR tree-optimization/113494
455 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
456 Handle endless loop on exit. Handle re-allocated PHI.
458 2024-01-19 Jakub Jelinek <jakub@redhat.com>
460 PR tree-optimization/113464
461 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
462 optimize loads into GIMPLE_ASM stmts.
464 2024-01-19 Jakub Jelinek <jakub@redhat.com>
466 PR tree-optimization/113463
467 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
468 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
469 lhs.
471 2024-01-19 Jakub Jelinek <jakub@redhat.com>
473 PR tree-optimization/113459
474 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
475 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
476 of SCALAR_INT_TYPE_MODE if type has BLKmode.
477 (vn_reference_lookup_3): Likewise. Formatting fix.
479 2024-01-19 Jakub Jelinek <jakub@redhat.com>
480 Richard Biener <rguenther@suse.de>
482 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
483 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
484 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
485 but adjust_address also for BLKmode mode and MEM op0.
487 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
489 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
490 extensions.
492 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
494 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
496 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
498 * common/config/riscv/riscv-common.cc
499 (riscv_subset_list::parse_std_ext): Remove.
500 (riscv_subset_list::parse_multiletter_ext): Remove.
501 * config/riscv/riscv-subset.h
502 (riscv_subset_list::parse_std_ext): Remove.
503 (riscv_subset_list::parse_multiletter_ext): Remove.
505 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
507 * common/config/riscv/riscv-common.cc
508 (riscv_subset_list::parse_single_std_ext): New parameter.
509 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
510 (riscv_subset_list::parse_single_ext): Ditto.
511 (riscv_subset_list::parse): Relax the order for the input of ISA
512 string.
513 * config/riscv/riscv-subset.h
514 (riscv_subset_list::parse_single_std_ext): New parameter.
515 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
516 (riscv_subset_list::parse_single_ext): Ditto.
518 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
520 * common/config/riscv/riscv-common.cc
521 (riscv_subset_list::parse_base_ext): New.
522 (riscv_subset_list::parse): Extract part of logic into
523 riscv_subset_list::parse_base_ext.
524 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
525 New.
527 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
529 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
530 sorry message.
532 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
534 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
535 UNSPEC_CLMUL_VC.
537 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
539 PR c/110029
540 * doc/extend.texi (Common Variable Attributes): Explain what
541 happens when multiple variables with cleanups are in the same scope.
543 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
545 PR ipa/108470
546 * doc/extend.texi (Common Function Attributes): Document that
547 noinline also disables some interprocedural optimizations and
548 improve flow to the part about using inline asm instead to
549 disable calls from being optimized away completely. Remove the
550 sentence that says noipa is mainly for internal compiler testing.
552 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
554 PR tree-optimization/69807
555 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
557 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
559 PR target/108521
560 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
561 from x86 Windows Options.
563 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
565 PR c/107942
566 * doc/extend.texi (C Extensions): Add new section to menu.
567 (Function Attributes): Move dangling index entries to....
568 (Const and Volatile Functions): New section.
570 2024-01-18 David Malcolm <dmalcolm@redhat.com>
572 PR middle-end/112684
573 * toplev.cc (toplev::main): Don't ICE in
574 -fdiagnostics-generate-patch when exiting after options,
575 since no edit context will have been created.
577 2024-01-18 Richard Biener <rguenther@suse.de>
579 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
580 operands vector.
582 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
584 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
585 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
587 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
588 Jin Ma <jinma@linux.alibaba.com>
589 Xianmiao Qu <cooper.qu@linux.alibaba.com>
590 Christoph Müllner <christoph.muellner@vrull.eu>
592 * config/riscv/thead.cc
593 (th_asm_output_opcode): Rewrite some instructions.
595 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
596 Jin Ma <jinma@linux.alibaba.com>
597 Xianmiao Qu <cooper.qu@linux.alibaba.com>
598 Christoph Müllner <christoph.muellner@vrull.eu>
600 * config/riscv/riscv.md (none,thv,rvv): New attribute.
601 (no,yes): Add an attribute to disable alternative
602 for xtheadvector or RVV1.0.
603 * config/riscv/vector.md:
604 Disable alternatives that destination register overlaps
605 source register group for xtheadvector.
607 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
608 Jin Ma <jinma@linux.alibaba.com>
609 Xianmiao Qu <cooper.qu@linux.alibaba.com>
610 Christoph Müllner <christoph.muellner@vrull.eu>
612 * config/riscv/riscv-vector-builtins-bases.cc
613 (class th_loadstore_width): Define new builtin bases.
614 (class th_extract): Define new builtin bases.
615 (BASE): Define new builtin bases.
616 * config/riscv/riscv-vector-builtins-bases.h:
617 Define new builtin class.
618 * config/riscv/riscv-vector-builtins-shapes.cc
619 (struct th_loadstore_width_def): Define new builtin shapes.
620 (struct th_indexed_loadstore_width_def):
621 Define new builtin shapes.
622 (struct th_extract_def): Define new builtin shapes.
623 (SHAPE): Define new builtin shapes.
624 * config/riscv/riscv-vector-builtins-shapes.h:
625 Define new builtin shapes.
626 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
627 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
628 * config/riscv/riscv-vector-builtins.h
629 (enum required_ext): Add new XTheadVector member.
630 (struct function_group_info): Likewise.
631 * config/riscv/t-riscv:
632 Add thead-vector-builtins-functions.def
633 * config/riscv/thead-vector.md
634 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
635 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
636 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
637 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
638 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
639 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
640 (@pred_th_extract<mode>): Likewise.
641 (*pred_th_extract<mode>): Likewise.
642 * config/riscv/thead-vector-builtins-functions.def: New file.
644 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
645 Jin Ma <jinma@linux.alibaba.com>
646 Xianmiao Qu <cooper.qu@linux.alibaba.com>
647 Christoph Müllner <christoph.muellner@vrull.eu>
649 * config.gcc: Add files for XTheadVector intrinsics.
650 * config/riscv/autovec.md: Guard XTheadVector.
651 * config/riscv/predicates.md: Disable immediate vl
652 for XTheadVector.
653 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
654 Add pragma for XTheadVector.
655 * config/riscv/riscv-string.cc (riscv_expand_block_move):
656 Guard XTheadVector.
657 * config/riscv/riscv-v.cc (vls_mode_valid_p):
658 Avoid autovec.
659 * config/riscv/riscv-vector-builtins-bases.cc:
660 Do not normalize vsetvl instructions for XTheadVector.
661 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
662 New check type function.
663 (build_one): Adjust for XTheadVector.
664 * config/riscv/riscv-vector-switch.def (ENTRY):
665 Disable fractional mode for the XTheadVector extension.
666 (TUPLE_ENTRY): Likewise.
667 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
668 Guard XTheadVector.
669 (riscv_preferred_simd_mode): Likewsie.
670 (riscv_autovectorize_vector_modes): Likewise.
671 (riscv_vector_mode_supported_any_target_p): Likewise.
672 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
673 * config/riscv/thead.cc (th_asm_output_opcode):
674 Rewrite vsetvl instructions.
675 * config/riscv/vector.md:
676 Include thead-vector.md and change fractional LMUL
677 into 1 for vbool.
678 * config/riscv/riscv_th_vector.h: New file.
679 * config/riscv/thead-vector.md: New file.
681 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
682 Jin Ma <jinma@linux.alibaba.com>
683 Xianmiao Qu <cooper.qu@linux.alibaba.com>
684 Christoph Müllner <christoph.muellner@vrull.eu>
686 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
687 Add new function to add assembler insn code prefix/suffix.
688 (th_asm_output_opcode):
689 Add Thead function to add assembler insn code prefix/suffix.
690 * config/riscv/riscv.cc (riscv_asm_output_opcode):
691 Implement function to add assembler insn code prefix/suffix.
692 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
693 Add new function to add assembler insn code prefix/suffix.
694 * config/riscv/thead.cc (th_asm_output_opcode):
695 Implement Thead function to add assembler insn code
696 prefix/suffix.
698 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
699 Jin Ma <jinma@linux.alibaba.com>
700 Xianmiao Qu <cooper.qu@linux.alibaba.com>
701 Christoph Müllner <christoph.muellner@vrull.eu>
703 * common/config/riscv/riscv-common.cc
704 (riscv_subset_list::parse): Add new vendor extension.
705 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
706 Add test marco.
707 * config/riscv/riscv.opt: Add new mask.
709 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
711 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
712 to be conditional on macosx-version-min.
714 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
716 * config/darwin.cc (darwin_objc1_section): Use the correct
717 meta-data version for constant strings.
718 (machopic_select_section): Assert if we fail to handle CFString
719 sections as Obejctive-C meta-data or drectly.
721 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
723 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
724 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
725 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
726 versions when the object format is Mach-O.
728 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
730 PR target/105522
731 * config/darwin.cc (machopic_select_section): Handle C and C++
732 CFStrings.
733 (darwin_rename_builtins): Move this out of the CFString code.
734 (darwin_libc_has_function): Likewise.
735 (darwin_build_constant_cfstring): Create an anonymous var to
736 hold each CFString.
737 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
738 CFstrings.
740 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
742 PR bootstrap/113445
743 * haifa-sched.cc (dep_list_size): Make global.
744 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
745 * sched-int.h (dep_list_size): Declare.
747 2024-01-18 Martin Jambor <mjambor@suse.cz>
749 PR tree-optimization/110422
750 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
751 gotos.
753 2024-01-18 Richard Biener <rguenther@suse.de>
755 PR tree-optimization/113475
756 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
757 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
758 (phi_analyzer::~phi_analyzer): Deallocate and free collected
759 phi_grous.
760 (phi_analyzer::process_phi): Record allocated phi_groups.
762 2024-01-18 Richard Biener <rguenther@suse.de>
764 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
765 storage for gvec_oprnds elements.
767 2024-01-18 Richard Biener <rguenther@suse.de>
769 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
770 prefer all later exits we can handle.
771 (vect_analyze_loop_form): Free the allocated loop body.
772 Adjust comments.
774 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
776 * config/avr/avr-log.cc: Tabify.
778 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
780 * config/riscv/autovec.md: Support vi variant.
782 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
784 * config/avr/avr-devices.cc: Tabify.
786 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
788 * config/avr/avr-c.cc: Tabify.
790 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
792 * config/avr/driver-avr.cc: Tabify.
794 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
796 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
798 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
800 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
802 2024-01-18 Jakub Jelinek <jakub@redhat.com>
804 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
805 minline-strcmp, minline-strncmp, minline-strlen,
806 -param=riscv-vector-abi): Remove Bool keywords.
808 2024-01-18 Jakub Jelinek <jakub@redhat.com>
810 PR target/113122
811 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
812 support. Add missing space after , in emitted assembly in some
813 cases. Formatting fixes.
815 2024-01-18 Xi Ruoyao <xry111@xry111.site>
817 * config/loongarch/loongarch.md (movsi_internal): Remove
818 constraint z.
820 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
822 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
823 in the diagnostic, and capitalize the device name.
824 (print_mcu): Generate specs such that:
825 <*check_rodata_in_ram>: New.
826 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
827 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
828 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
830 2024-01-18 Jakub Jelinek <jakub@redhat.com>
832 PR other/113399
833 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
834 Common and Optimization.
836 2024-01-18 Richard Biener <rguenther@suse.de>
838 PR tree-optimization/113431
839 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
840 When there is an invariant load we might not preserve
841 scalar order.
843 2024-01-18 Richard Biener <rguenther@suse.de>
845 PR tree-optimization/113374
846 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
847 * tree-vect-loop.cc (move_early_exit_stmts): Update
848 virtual LC PHIs.
849 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
850 Refactor. Preserve virtual LC PHIs on all exits.
852 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
854 * config/loongarch/loongarch.cc (loongarch_split_symbol):
855 Assign the '/u' attribute to the mem.
857 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
859 PR middle-end/110847
860 * doc/invoke.texi (Option Summary): Document negative forms of
861 -Wtsan and -Wxor-used-as-pow.
862 (Warning Options): Likewise.
864 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
866 PR target/113429
867 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
869 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
871 * doc/extend.texi (Common Function Attributes): Re-alphabetize
872 the table.
873 (Common Variable Attributes): Likewise.
874 (Common Type Attributes): Likewise.
876 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
878 PR middle-end/111659
879 * doc/extend.texi (Common Variable Attributes): Fix long lines
880 in documentation of strict_flex_array + other minor copy-editing.
881 Add a cross-reference to -Wstrict-flex-arrays.
882 * doc/invoke.texi (Option Summary): Fix whitespace in tables
883 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
884 (C Dialect Options): Combine the docs for the two
885 -fstrict-flex-arrays forms into a single entry. Note this option
886 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
887 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
888 Minor copy-editing. Add cross references to the strict_flex_array
889 attribute and -fstrict-flex-arrays option. Add note that this
890 option depends on -ftree-vrp.
892 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
894 PR target/113221
895 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
896 only allow REG operands instead of allowing all.
898 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
900 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
901 Remove redundant checks in else condition for readablity.
902 (earliest_fuse_vsetvl_info) Print iteration count in debug
903 prints.
904 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
905 dump details in certain cases.
907 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
909 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
910 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
911 * config/riscv/riscv-vsetvl.cc
912 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
913 (pass_vsetvl::execute): Use vsetvl_strategy.
915 2024-01-17 Jan Hubicka <jh@suse.cz>
917 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
918 accidental hack reseting offset.
920 2024-01-17 Jan Hubicka <jh@suse.cz>
922 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
923 handling of X86_TUNE_AVOID_512FMA_CHAINS.
925 2024-01-17 Jan Hubicka <jh@suse.cz>
926 Jakub Jelinek <jakub@redhat.com>
928 PR tree-optimization/110852
929 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
930 binary operations
931 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
932 PRED_COMBINED_VALUE_PREDICTIONS_PHI
933 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
934 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
936 2024-01-17 Jakub Jelinek <jakub@redhat.com>
938 PR tree-optimization/113421
939 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
940 comment.
941 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
942 formatting. Start at vop rather than cvop even if stmt is a store
943 and needs_operand_addr.
945 2024-01-17 Jakub Jelinek <jakub@redhat.com>
947 PR middle-end/113410
948 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
949 If access_nelts is integral with larger precision than sizetype,
950 fold_convert it to sizetype.
952 2024-01-17 Jakub Jelinek <jakub@redhat.com>
954 PR tree-optimization/113408
955 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
956 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
957 to handle_cast.
959 2024-01-17 Jakub Jelinek <jakub@redhat.com>
961 PR middle-end/113406
962 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
963 regardless of whether is_gimple_reg_type (restype) or not.
965 2024-01-17 Jakub Jelinek <jakub@redhat.com>
967 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
968 funcions -> functions, and use were instead of was.
969 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
970 and guaranteee -> guarantee.
971 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
973 2024-01-17 Jakub Jelinek <jakub@redhat.com>
975 PR middle-end/113409
976 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
977 INTEGER_TYPE.
978 (omp_extract_for_data): Use build_bitint_type rather than
979 build_nonstandard_integer_type if either iter_type or loop->v type
980 is BITINT_TYPE.
981 * omp-expand.cc (expand_omp_for_generic,
982 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
983 BITINT_TYPE like INTEGER_TYPE.
985 2024-01-17 Richard Biener <rguenther@suse.de>
987 PR tree-optimization/113371
988 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
989 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
990 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
991 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
993 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
995 PR rtl-optimization/96388
996 PR rtl-optimization/111554
997 * sched-deps.cc (find_inc): Avoid exponential behavior.
999 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1001 PR c/111693
1002 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
1003 from C++ Language Options to Warning Options. Add entry for
1004 -Wuse-after-free.
1005 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
1006 from here....
1007 (Warning Options): ...to here. Minor copy-editing to fix typo
1008 and grammar.
1010 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
1012 * config/mips/mips.cc (mips_compute_frame_info): If another
1013 register is used as global_pointer, mark $GP live false.
1015 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1017 PR target/112973
1018 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
1019 give the section a light copy-editing pass.
1021 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
1023 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
1024 * config/aarch64/aarch64-tune.md: Regenerated.
1025 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
1027 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
1029 PR target/112573
1030 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
1031 badly formed CONST expressions.
1033 2024-01-16 Daniel Cederman <cederman@gaisler.com>
1035 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
1037 2024-01-16 Daniel Cederman <cederman@gaisler.com>
1039 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
1040 * config/sparc/sync.md (membar_storeload): Turn into named insn
1041 and add GR712RC errata workaround.
1042 (membar_v8): Add GR712RC errata workaround.
1044 2024-01-16 Andreas Larsson <andreas@gaisler.com>
1046 * config/sparc/sync.md (*membar_storeload_leon3): Remove
1047 (*membar_storeload): Enable for LEON
1049 2024-01-16 Jakub Jelinek <jakub@redhat.com>
1051 PR tree-optimization/113372
1052 PR middle-end/90348
1053 PR middle-end/110115
1054 PR middle-end/111422
1055 * cfgexpand.cc (add_scope_conflicts_2): New function.
1056 (add_scope_conflicts_1): Use it.
1058 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
1060 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
1061 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
1062 * doc/avr-mmcu.texi: Regenerate.
1064 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
1066 PR tree-optimization/113091
1067 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
1068 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
1069 scalar use with new function.
1070 (vect_bb_slp_mark_live_stmts): New function as entry to existing
1071 overriden functions with same name.
1072 (vect_slp_analyze_operations): Call new entry function to mark
1073 live statements.
1075 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1077 PR target/113404
1078 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
1079 for RVV in big-endian mode.
1081 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
1083 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
1084 (riscv_pass_in_vector_p): Delete.
1085 (riscv_init_cumulative_args): Delete the checking.
1086 (riscv_get_arg_info): Delete the checking.
1087 (riscv_function_value): Delete the checking.
1088 * config/riscv/riscv.h: Delete the member for checking.
1090 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
1092 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
1094 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
1096 * config.gcc: Include riscv_bitmanip.h.
1097 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
1098 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
1099 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
1100 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
1101 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
1102 * config/riscv/riscv-ftypes.def (2): New ftypes.
1103 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
1104 (RISCV_BUILTIN_NO_PREFIX): Likewise.
1105 * config/riscv/riscv_bitmanip.h: New file.
1107 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
1109 * config.gcc: Include riscv_crypto.h.
1110 * config/riscv/riscv_crypto.h: New file.
1112 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
1114 PR middle-end/113354
1115 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
1116 in the insn if the corresponding operand does not require hard
1117 register anymore.
1119 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
1121 PR target/107201
1122 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
1123 * config/avr/driver-avr.cc (avr_no_devlib): New function.
1124 (avr_devicespecs_file): Use it to remove -nodevicelib from the
1125 options for cores only.
1126 * config/avr/avr-arch.h (avr_get_parch): New prototype.
1127 * config/avr/avr-devices.cc (avr_get_parch): New function.
1129 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1131 PR target/113247
1132 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
1133 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
1134 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
1136 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1138 PR target/113281
1139 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
1140 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
1141 * config/riscv/riscv-vector-costs.h: New function.
1143 2024-01-15 Richard Biener <rguenther@suse.de>
1145 PR tree-optimization/113385
1146 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1147 First redirect, then split the exit edge.
1149 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1151 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
1152 Remove m_num_vector_iterations.
1153 * config/riscv/riscv-vector-costs.h: Ditto.
1155 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
1157 PR target/113156
1158 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
1159 (-mbranch-cost): Set "Optimization" flag.
1161 2024-01-15 Jakub Jelinek <jakub@redhat.com>
1163 PR tree-optimization/113370
1164 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
1165 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
1166 set it to just prec % limb_prec.
1168 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1170 PR target/113393
1171 * config/riscv/vector.md: Fix ternary attributes.
1173 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
1175 PR target/112944
1176 * configure.ac [target=avr]: Check availability of emulations
1177 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
1178 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
1179 * configure: Regenerate.
1180 * config.in: Regenerate.
1181 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
1182 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
1183 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
1184 * config/avr/avr-arch.h (enum avr_device_specific_features):
1185 Add AVR_ISA_FLMAP.
1186 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
1187 AVR_ISA_FLMAP.
1188 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
1189 (avr_set_core_architecture): Set avr_arch_index.
1190 (have_avrxmega2_flmap, have_avrxmega4_flmap)
1191 (have_avrxmega3_rodata_in_flash): Set new static const bool according
1192 to configure results.
1193 (avr_rodata_in_flash_p): New function using them.
1194 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
1195 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
1196 (avr_asm_named_section): Track avr_has_rodata_p.
1197 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
1198 and not avr_rodata_in_flash_p ().
1199 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
1200 (LINK_SPEC): Add %(link_rodata_in_ram).
1201 (LINK_ARCH_SPEC): Remove.
1202 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
1203 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
1204 const bool according to configure results.
1205 (diagnose_mrodata_in_ram): New function.
1206 (print_mcu): Generate specs with the following changes:
1207 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
1208 need to extend avr/specs.h each time we add a new bell or whistle.
1209 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
1210 -m[no-]rodata-in-ram.
1211 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
1212 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
1213 <*cpp>: Add %(cpp_rodata_in_ram).
1214 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
1215 requested.
1216 <*self_spec>: Add -mflmap or %<mflmap as needed.
1218 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
1220 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
1221 not the GPR iterator. Adjust pattern name and mode attribute
1222 accordingly.
1224 2024-01-13 Jakub Jelinek <jakub@redhat.com>
1226 PR tree-optimization/113361
1227 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
1228 Fix up determination of the type for > limb_prec constants.
1230 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
1232 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
1233 Add web-link to the avr-gcc wiki.
1235 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
1237 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
1238 documentation for a version without argument, which is not supported.
1240 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1242 * config/arm/arm_neon.h
1243 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
1244 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
1245 (vld1_f16_x4, vld1_f32_x4): New.
1246 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
1247 (vld1_bf16_x4): New.
1248 (vld1q_types_x4): Updated to use vld1q_x4
1249 from arm_neon_builtins.def
1250 * config/arm/arm_neon_builtins.def
1251 (vld1_x4): Updated entries.
1252 (vld1q_x4): New entries, but comes from the old vld1_x4
1253 * config/arm/neon.md
1254 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
1256 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1258 * config/arm/arm_neon.h
1259 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
1260 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
1261 (vld1_f16_x3, vld1_f32_x3): New.
1262 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
1263 (vld1_bf16_x3): New.
1264 (vld1q_types_x3): Updated to use vld1q_x3 from
1265 arm_neon_builtins.def
1266 * config/arm/arm_neon_builtins.def
1267 (vld1_x3): Updated entries.
1268 (vld1q_x3): New entries, but comes from the old vld1_x2
1269 * config/arm/neon.md
1270 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
1272 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1274 * config/arm/arm_neon.h
1275 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
1276 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
1277 (vld1_f16_x2, vld1_f32_x2): New.
1278 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
1279 (vld1_bf16_x2): New.
1280 (vld1q_types_x2): Updated to use vld1q_x2 from
1281 arm_neon_builtins.def
1282 * config/arm/arm_neon_builtins.def
1283 (vld1_x2): Updated entries.
1284 (vld1q_x2): New entries, but comes from the old vld1_x2
1285 * config/arm/neon.md
1286 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
1287 neon_vld1_x2<mode>.
1289 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1291 * config/arm/arm_neon.h
1292 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
1293 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
1294 (vst1q_f16_x4, vst1q_f32_x4): New.
1295 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
1296 (vst1q_bf16_x4): New.
1297 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
1298 * config/arm/neon.md
1299 (neon_vst1q_x4<mode>): New.
1300 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
1301 * config/arm/unspecs.md
1302 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
1304 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1306 * config/arm/arm_neon.h
1307 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
1308 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
1309 (vst1q_f16_x3, vst1q_f32_x3): New.
1310 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
1311 (vst1q_bf16_x3): New.
1312 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
1313 * config/arm/neon.md
1314 (neon_vst1q_x3<mode>): New.
1315 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
1316 * config/arm/unspecs.md
1317 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
1319 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1321 * config/arm/arm_neon.h
1322 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
1323 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
1324 (vst1q_f16_x2, vst1q_f32_x2): New.
1325 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
1326 (vst1q_bf16_x2): New.
1327 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
1328 * config/arm/neon.md
1329 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
1330 neon_vst1_x2<mode>.
1331 * config/arm/iterators.md
1332 (VMEMX2): New mode iterator.
1333 (VMEMX2_q): New mode attribute.
1335 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1337 * config/arm/arm_neon.h
1338 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
1339 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
1340 (vst1_f16_x4, vst1_f32_x4): New.
1341 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
1342 (vst1_bf16_x4): New.
1343 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
1344 * config/arm/neon.md (vst1_x4<mode>): New.
1346 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1348 * config/arm/arm_neon.h
1349 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
1350 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
1351 (vst1_f16_x3, vst1_f32_x3): New.
1352 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
1353 (vst1_bf16_x3): New.
1354 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
1355 * config/arm/neon.md (vst1_x3<mode>): New.
1357 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1359 * config/arm/arm_neon.h
1360 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
1361 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
1362 (vst1_f16_x2, vst1_f32_x2): New.
1363 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
1364 (vst1_bf16_x2): New.
1365 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
1366 * config/arm/neon.md (vst1_x2<mode>): New.
1368 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1370 * config/arm/arm_neon.h
1371 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
1372 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
1373 (vld1q_f16_x4, vld1q_f32_x4): New.
1374 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
1375 (vld1q_bf16_x4): New.
1376 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
1377 * config/arm/neon.md
1378 (neon_vld1_x4<mode>): New.
1379 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
1380 * config/arm/unspecs.md
1381 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
1383 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1385 * config/arm/arm_neon.h
1386 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
1387 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
1388 (vld1q_f16_x3, vld1q_f32_x3): New.
1389 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
1390 (vld1q_bf16_x3): New.
1391 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
1392 * config/arm/neon.md
1393 (neon_vld1_x3<mode>): New.
1394 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
1395 * config/arm/unspecs.md
1396 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
1398 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1400 * config/arm/arm_neon.h
1401 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
1402 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
1403 (vld1q_f16_x2, vld1q_f32_x2): New.
1404 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
1405 (vld1q_bf16_x2): New.
1406 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
1407 * config/arm/neon.md (vld1_x2<mode>): New.
1409 2024-01-12 Tamar Christina <tamar.christina@arm.com>
1411 PR tree-optimization/113287
1412 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
1414 2024-01-12 Tamar Christina <tamar.christina@arm.com>
1416 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
1417 * tree-vect-loop.cc (vect_transform_loop): Likewise.
1419 2024-01-12 Tamar Christina <tamar.christina@arm.com>
1421 PR tree-optimization/113178
1422 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
1423 alternate exits.
1425 2024-01-12 Tamar Christina <tamar.christina@arm.com>
1427 PR tree-optimization/113237
1428 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
1429 existing LCSSA variable for exit when all exits are early break.
1431 2024-01-12 Tamar Christina <tamar.christina@arm.com>
1433 PR tree-optimization/113137
1434 PR tree-optimization/113136
1435 PR tree-optimization/113172
1436 PR tree-optimization/113178
1437 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1438 Maintain PHIs on inverted loops.
1439 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
1440 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
1441 latch.
1442 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
1444 2024-01-12 Tamar Christina <tamar.christina@arm.com>
1446 PR tree-optimization/113135
1447 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
1448 dependency analysis.
1450 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
1452 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
1453 diagnostics class member name for abort of error.
1455 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
1457 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
1458 format string to %s argument.
1460 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
1461 Jakub Jelinek <jakub@redhat.com>
1463 PR middle-end/113182
1464 * varasm.cc (process_pending_assemble_externals,
1465 assemble_external_libcall): Use targetm.strip_name_encoding
1466 before calling get_identifier.
1468 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
1470 PR target/113196
1471 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
1472 New member variable.
1473 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
1474 Declare.
1475 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
1476 * config/aarch64/aarch64-simd.md
1477 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
1478 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
1479 zip2 for zero-extends to...
1480 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
1481 instruction. Fix big-endian handling.
1482 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
1483 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
1484 zip1 for zero-extends to...
1485 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
1486 Fix big-endian handling.
1487 (*aarch64_zip1_uxtl): New pattern.
1488 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
1489 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
1490 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
1491 (aarch64_gen_shareable_zero): Use it.
1492 (aarch64_split_simd_shift_p): New function.
1494 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
1496 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
1497 (function_beg_insn): New macro.
1498 * function.cc (expand_function_start): Initialize function_beg_insn.
1500 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
1502 PR target/112989
1503 * config/aarch64/aarch64-sve-builtins.h
1504 (function_builder::m_overload_names): Replace with...
1505 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
1506 new global.
1507 (add_overloaded_function): Update accordingly, using get_identifier
1508 to get a GGC-friendly record of the name.
1510 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
1512 PR target/112989
1513 * config/aarch64/aarch64-sve-builtins.def: Don't include
1514 aarch64-sve-builtins-sme.def.
1515 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
1516 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
1517 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
1518 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
1519 requires AARCH64_FL_SME2.
1520 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
1521 AARCH64_FL_SME adjustment here.
1522 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
1523 include SME intrinsics.
1524 (sme_function_groups): New array.
1525 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
1526 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
1528 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1530 PR target/113281
1531 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
1532 (struct cpu_vector_cost): Add regmove struct.
1533 (get_vector_costs): Export as global.
1534 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
1535 (costs::add_stmt_cost): Ditto.
1536 * config/riscv/riscv.cc (get_common_costs): Export global function.
1538 2024-01-12 Jakub Jelinek <jakub@redhat.com>
1540 PR tree-optimization/113334
1541 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
1542 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
1543 to determine if number should be extended by all ones rather than zero
1544 extended.
1546 2024-01-12 Jakub Jelinek <jakub@redhat.com>
1548 PR tree-optimization/113330
1549 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
1550 too large size.
1552 2024-01-12 Jakub Jelinek <jakub@redhat.com>
1554 PR tree-optimization/113323
1555 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
1556 check for lhs being large/huge _BitInt not in m_names.
1558 2024-01-12 Jakub Jelinek <jakub@redhat.com>
1560 PR tree-optimization/113316
1561 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
1562 uninitialized large/huge _BitInt arguments to calls.
1564 2024-01-12 Jakub Jelinek <jakub@redhat.com>
1566 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
1567 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
1568 CEIL (TYPE_PRECISION (t), limb_prec).
1569 (bitint_large_huge::handle_cast): Likewise.
1571 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
1573 PR sanitizer/113284
1574 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1575 Use assemble_function_label_final () for Power ELF V1 ABI.
1576 * output.h (assemble_function_label_final): New function.
1577 * varasm.cc (assemble_function_label_raw): Use
1578 assemble_function_label_final ().
1579 (assemble_function_label_final): New function.
1581 2024-01-12 Richard Biener <rguenther@suse.de>
1583 PR middle-end/113344
1584 * match.pd ((double)float CMP (double)float -> float CMP float):
1585 Perform result type check only for vectors.
1586 * fold-const.cc (fold_binary_loc): Likewise.
1588 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
1590 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
1591 (usdot_prod<mode>): Ditto.
1592 (sdot_prod<mode>): Ditto.
1593 (udot_prod<mode>): Ditto.
1595 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
1597 PR target/113288
1598 * config/i386/i386-c.cc (ix86_target_macros_internal):
1599 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
1601 2024-01-12 Richard Biener <rguenther@suse.de>
1603 PR target/112280
1604 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
1605 Do not generate code when d.testing_p.
1607 2024-01-12 liuhongt <hongtao.liu@intel.com>
1609 PR target/113039
1610 * doc/invoke.texi (fcf-protection=): Update documents.
1612 2024-01-12 Pan Li <pan2.li@intel.com>
1614 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
1615 comments of predicate func riscv_v_ext_mode_p.
1617 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
1619 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
1620 Modify ABI-name length of vfloat16m8_t
1622 2024-01-12 Li Wei <liwei@loongson.cn>
1624 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
1625 Adjust.
1627 2024-01-12 Li Wei <liwei@loongson.cn>
1629 * config/loongarch/loongarch.md (add<mode>3): Removed.
1630 (*addsi3): New.
1631 (addsi3): Ditto.
1632 (adddi3): Ditto.
1633 (*addsi3_extended): Removed.
1634 (addsi3_extended): New.
1636 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
1638 * config/riscv/thead.md: Add limits for splits.
1640 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
1642 PR middle-end/113322
1643 * expr.cc (do_store_flag): Don't try single bit tests with
1644 comparison on vector types.
1646 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
1648 PR tree-optimization/113301
1649 * match.pd (`1/x`): Delay signed case until late.
1651 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
1653 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
1654 and -msp8 to...
1655 (AVR Internal Options): ...this new @subsubsection.
1657 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
1659 PR rtl-optimization/112918
1660 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
1661 (in_class_p): Restrict condition for narrowing class in case of
1662 allow_all_reload_class_changes_p.
1663 (process_alt_operands): Try to match operand without and with
1664 narrowing reg class. Discourage narrowing the class. Finish insn
1665 matching only if there is no class narrowing.
1666 (curr_insn_transform): Pass true to in_class_p for reg operand win.
1668 2024-01-11 Richard Biener <rguenther@suse.de>
1670 PR tree-optimization/112505
1671 * tree-vect-loop.cc (vectorizable_induction): Reject
1672 bit-precision induction.
1674 2024-01-11 Richard Biener <rguenther@suse.de>
1676 PR tree-optimization/113126
1677 * match.pd ((double)float CMP (double)float -> float CMP float):
1678 Make sure the boolean type is the same.
1679 * fold-const.cc (fold_binary_loc): Likewise.
1681 2024-01-11 Richard Biener <rguenther@suse.de>
1683 PR tree-optimization/112636
1684 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
1685 estimate_numbers_of_iterations before querying
1686 get_max_loop_iterations_int.
1687 (pass_ch::execute): Initialize SCEV and loops appropriately.
1689 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
1691 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
1692 Reduced Tiny.
1693 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
1694 * doc/extend.texi (AVR Variable Attributes): Improve documentation
1695 of io, io_low and address attributes.
1696 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
1697 * doc/avr-mmcu.texi: Rebuild.
1699 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
1701 PR target/113233
1702 * config/loongarch/genopts/loongarch.opt.in: Mark options with
1703 the "Save" property.
1704 * config/loongarch/loongarch.opt: Same.
1705 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
1706 according to la_target.
1707 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
1708 RESTORE} for the la_target structure; Rename option conditions
1709 to have the same "la_" prefix.
1710 * config/loongarch/loongarch.h: Same.
1712 2024-01-11 Pan Li <pan2.li@intel.com>
1714 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
1715 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
1717 2024-01-11 Alex Coplan <alex.coplan@arm.com>
1719 PR target/113077
1720 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
1721 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
1722 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
1723 synthesize these if needed. Update caller ...
1724 (ldp_bb_info::fuse_pair): ... here.
1725 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
1726 and either insn is frame-related.
1727 (find_trailing_add): Punt on frame-related insns.
1728 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
1729 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
1731 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
1733 * config/mips/mips.cc (mips_start_function_definition):
1734 Add ATTRIBUTE_UNUSED.
1736 2024-01-11 Richard Biener <rguenther@suse.de>
1738 PR middle-end/112740
1739 * expr.cc (store_constructor): Check the integer vector
1740 mask has a single bit per element before using sign-extension
1741 to expand an uniform vector.
1743 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1745 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
1746 preempt VLS on unknown NITERS loop.
1748 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
1750 * doc/invoke.texi: Add -mevex512.
1752 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
1754 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
1755 (*nor<mode>3): Likewise.
1756 (nor<mode>3): Likewise.
1757 (*negsi2_extended): New template.
1758 (*<optab>si3_internal): Likewise.
1759 (*one_cmplsi2_internal): Likewise.
1760 (*norsi3_internal): Likewise.
1761 (*<optab>nsi_internal): Likewise.
1762 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
1763 modified bit operation to make the optimization work.
1765 2024-01-11 liuhongt <hongtao.liu@intel.com>
1767 PR target/104401
1768 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
1770 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1772 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
1773 (get_vector_costs): Ditto.
1774 (riscv_builtin_vectorization_cost): Ditto.
1776 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1778 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
1780 2024-01-10 Antoni Boucher <bouanto@zoho.com>
1782 PR jit/111396
1783 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
1784 ipa_free_size_summary.
1785 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
1786 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
1787 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
1788 * ipa-prop.h (ipa_prop_cc_finalize): New function.
1789 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
1790 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
1791 ipa_sra_cc_finalize): New functions.
1792 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
1793 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
1794 ipa_sra_cc_finalize
1795 Include ipa-utils.h.
1797 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
1799 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
1800 (th_int_get_save_adjustment): Likewise.
1801 (th_int_adjust_cfi_prologue): Likewise.
1802 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
1803 (TH_INT_INTERRUPT): New macro.
1804 (riscv_expand_prologue): Add the processing of XTheadInt.
1805 (riscv_expand_epilogue): Likewise.
1806 * config/riscv/riscv.h (BITSET_P): Moved to here.
1807 * config/riscv/riscv.md: New unspec.
1808 * config/riscv/thead.cc (th_int_get_mask): New function.
1809 (th_int_get_save_adjustment): Likewise.
1810 (th_int_adjust_cfi_prologue): Likewise.
1811 * config/riscv/thead.md (th_int_push): New pattern.
1812 (th_int_pop): new pattern.
1814 2024-01-10 Tamar Christina <tamar.christina@arm.com>
1816 PR tree-optimization/112468
1817 * doc/sourcebuild.texi: Document ifn_copysign.
1818 * match.pd: Only apply transformation if target supports the IFN.
1820 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
1822 PR tree-optimization/112581
1823 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
1824 mark_ssa_maybe_undefs.
1825 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
1826 variables can not be reassociated.
1827 (init_range_entry): Check for uninitialized variables too.
1828 (init_reassoc): Call mark_ssa_maybe_undefs.
1830 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
1832 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
1833 Also handle sign extension.
1835 2024-01-10 Alex Coplan <alex.coplan@arm.com>
1837 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
1838 to 0.
1839 (-mlate-ldp-fusion): Likewise.
1841 2024-01-10 Tamar Christina <tamar.christina@arm.com>
1843 PR tree-optimization/113287
1844 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
1845 instead of using BRANCH_EDGE to determine true edge.
1847 2024-01-10 Richard Biener <rguenther@suse.de>
1849 PR tree-optimization/113078
1850 * tree-vect-loop.cc (check_reduction_path): Canonicalize
1851 .COND_SUB to .COND_ADD.
1853 2024-01-10 David Malcolm <dmalcolm@redhat.com>
1855 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
1856 Handle prefix mappings before calling find_opt.
1857 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
1858 "-fno-"-prefixed command-line option.
1859 * opts-common.cc (get_option_prefix_remapping): New.
1860 * opts.h (get_option_prefix_remapping): New decl.
1862 2024-01-10 David Malcolm <dmalcolm@redhat.com>
1864 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
1865 m_urlifier to pp_output_formatted_text.
1866 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
1867 (obstack_append_string): New overload, taking a length.
1868 (urlify_quoted_string): Pass in an obstack ptr, rather than using
1869 that of the pp's buffer. Generalize to handle trailing text in
1870 the buffer beyond the run of quoted text.
1871 (class quoting_info): New.
1872 (on_begin_quote): New.
1873 (on_end_quote): New.
1874 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
1875 it to calls to on_begin_quote and on_end_quote.
1876 (struct auto_obstack): New.
1877 (quoting_info::handle_phase_3): New.
1878 (pp_output_formatted_text): Add urlifier param. Use it if there
1879 is deferred urlification. Delete m_quotes.
1880 (selftest::pp_printf_with_urlifier): Pass urlifier to
1881 pp_output_formatted_text.
1882 (selftest::test_urlification): Update results for the existing
1883 case of quoted text stradding chunks; add more such test cases.
1884 * pretty-print.h (class quoting_info): New forward decl.
1885 (chunk_info::m_quotes): New field.
1886 (pp_output_formatted_text): Add optional urlifier param.
1888 2024-01-10 David Malcolm <dmalcolm@redhat.com>
1890 * pretty-print.cc (selftest::test_pp_format): Add selftest
1891 coverage for numbered args.
1893 2024-01-10 Tamar Christina <tamar.christina@arm.com>
1895 PR tree-optimization/113144
1896 PR tree-optimization/113145
1897 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1898 Update all BB that the original exits dominated.
1900 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
1902 * dwarf2out.cc (modified_type_die): Extend the support of reverse
1903 storage order to enumeration types if -gstrict-dwarf is not passed.
1904 (gen_enumeration_type_die): Add REVERSE parameter and generate the
1905 DIE immediately after the existing one if it is true.
1906 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
1907 call to gen_enumeration_type_die.
1908 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
1909 first recursive call as well as the call to gen_tagged_type_die.
1910 (gen_type_die): Add REVERSE parameter and pass it in the call to
1911 gen_type_die_with_usage.
1913 2024-01-10 Jakub Jelinek <jakub@redhat.com>
1915 PR tree-optimization/113120
1916 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
1917 with root->size TYPE_PRECISION don't build anything new.
1918 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
1919 rather than build_nonstandard_integer_type.
1921 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
1923 * config/i386/i386.opt: Adjust document.
1924 * doc/invoke.texi: Add description for
1925 -mapx-inline-asm-use-gpr32.
1927 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1929 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
1930 (avg<v_double_trunc>3_floor): New pattern.
1931 (<u>avg<v_double_trunc>3_ceil): Remove.
1932 (avg<v_double_trunc>3_ceil): New pattern.
1933 (uavg<mode>3_floor): Ditto.
1934 (uavg<mode>3_ceil): Ditto.
1935 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
1936 (enum insn_type): Ditto.
1937 * config/riscv/riscv-v.cc: Ditto.
1938 * config/riscv/vector-iterators.md (ashiftrt): Remove.
1939 (ASHIFTRT): Ditto.
1940 * config/riscv/vector.md: Add VLS modes.
1942 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
1944 PR target/111480
1945 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
1946 (vczlsbb_char): New int attribute.
1947 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
1948 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
1949 (*vctzlsbb_zext_<mode>): Rename to ...
1950 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
1951 cover vclzlsbb.
1953 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
1955 PR target/112606
1956 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
1957 of the last argument from altivec_register_operand to any_operand. If
1958 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
1959 otherwise if it doesn't satisfy altivec_register_operand, force it to
1960 REG using copy_to_mode_reg.
1962 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
1964 PR middle-end/113100
1965 * builtins.cc (expand_builtin_stack_address): Guard stack point
1966 adjustment with SPARC_STACK_BOUNDARY_HACK.
1968 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
1970 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
1971 argument string definitions.
1972 * config/loongarch/loongarch-str.h: Same.
1973 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
1974 as aliases to -mexplicit-relocs={always,none}
1975 * config/loongarch/loongarch.opt: Regenerate.
1976 * config/loongarch/loongarch.cc: Same.
1978 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
1980 * config/loongarch/loongarch-def.h: Define constants with
1981 enums instead of Macros.
1983 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
1985 * config/loongarch/genopts/loongarch-strings: Rename.
1986 * config/loongarch/genopts/loongarch.opt.in: Same.
1987 * config/loongarch/loongarch-cpu.cc: Same.
1988 * config/loongarch/loongarch-def.cc: Same.
1989 * config/loongarch/loongarch-def.h: Same.
1990 * config/loongarch/loongarch-opts.cc: Same.
1991 * config/loongarch/loongarch-opts.h: Same.
1992 * config/loongarch/loongarch-str.h: Same.
1993 * config/loongarch/loongarch.opt: Same.
1995 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
1997 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
1998 variable with the common la_ prefix.
1999 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
2000 flags as saved using TargetVariable.
2001 * config/loongarch/loongarch.opt: Same.
2002 * config/loongarch/loongarch-def.h: Define evolution_set to
2003 mark changes to the -march default.
2004 * config/loongarch/loongarch-driver.cc: Same.
2005 * config/loongarch/loongarch-opts.cc: Same.
2006 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
2007 conditions around the la_target structure.
2008 * config/loongarch/loongarch.cc: Same.
2009 * config/loongarch/loongarch.md: Same.
2010 * config/loongarch/loongarch-builtins.cc: Same.
2011 * config/loongarch/loongarch-c.cc: Same.
2012 * config/loongarch/lasx.md: Same.
2013 * config/loongarch/lsx.md: Same.
2014 * config/loongarch/sync.md: Same.
2016 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
2018 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
2019 no less.
2021 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
2023 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
2025 2024-01-09 Tamar Christina <tamar.christina@arm.com>
2027 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
2028 restart_loop.
2029 (vectorizable_live_operation): Likewise.
2031 2024-01-09 Tamar Christina <tamar.christina@arm.com>
2033 PR tree-optimization/113199
2034 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
2035 BIT_FIELD_REF.
2037 2024-01-09 Jakub Jelinek <jakub@redhat.com>
2039 PR target/113270
2040 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
2041 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
2042 GTY(()) declaration before the definition, drop GTY(()) drom the
2043 definition.
2045 2024-01-09 Richard Biener <rguenther@suse.de>
2047 PR tree-optimization/113026
2048 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
2049 redundant and wrong niter bound setting. Move niter
2050 bound adjustment down.
2052 2024-01-09 Tamar Christina <tamar.christina@arm.com>
2054 PR middle-end/113163
2055 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
2056 Reject non-linear inductions that aren't supported.
2058 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
2060 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
2061 left shift implementation strategies.
2062 (arc_shift_info): Type for each entry of the shift strategy table.
2063 (arc_shift_context_idx): Return a integer value for each code
2064 generation context, used as an index
2065 (arc_ashl_alg): Table indexed by context and shifted bit count.
2066 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
2067 left shift implementation.
2068 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
2069 provide accurate costs, when optimizing for speed or size.
2071 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2073 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
2075 2024-01-09 Julian Brown <julian@codesourcery.com>
2077 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
2078 processed out before gimplification.
2079 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
2080 * tree.def (OMP_ARRAY_SECTION): New tree code.
2082 2024-01-09 Jakub Jelinek <jakub@redhat.com>
2084 PR tree-optimization/113210
2085 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
2086 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
2087 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
2088 minus 1.
2090 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
2092 PR rtl-optimization/113140
2093 * reorg.cc (fill_slots_from_thread): If we are to branch after the
2094 last instruction of the function, create an end label.
2096 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
2097 Hongtao Liu <hongtao.liu@intel.com>
2099 PR target/112992
2100 * config/i386/i386-expand.cc
2101 (ix86_convert_const_wide_int_to_broadcast): Allow call to
2102 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
2103 (ix86_broadcast_from_constant): Revert recent change; Return a
2104 suitable MEMREF independently of mode/target combinations.
2105 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
2106 to decide whether expansion is possible/preferrable. Only try
2107 forcing DImode constants to memory (and trying again) if calling
2108 ix86_expand_vector_init_duplicate fails with an DImode immediate
2109 constant.
2110 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
2111 V4SImode for suitable immediate constants.
2112 <case E_V4DImode>: Try using V8SImode for suitable constants.
2113 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
2114 <case E_V2HImode>: Likewise.
2115 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
2116 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
2117 <label widen>: Handle CONT_INTs via simplify_binary_operation.
2118 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
2119 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
2120 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
2121 (ix86_expand_vector_init): Move try using a broadcast for all_same
2122 with ix86_expand_vector_init_duplicate before using constant pool.
2124 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
2126 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
2128 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
2130 * config/arm/arm-cpus.in (cortex-m52): New cpu.
2131 * config/arm/arm-tables.opt: Regenerate.
2132 * config/arm/arm-tune.md: Regenerate.
2134 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
2136 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
2137 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
2138 (@vec_concatz<mode>): New insn pattern.
2139 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
2140 Handle VALS containing two vectors.
2142 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2144 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
2145 (vundefined): Ditto.
2147 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
2149 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2150 Add new function_base for crypto vector.
2151 (class bitmanip): Ditto.
2152 (class b_reverse):Ditto.
2153 (class vwsll): Ditto.
2154 (class clmul): Ditto.
2155 (class vg_nhab): Ditto.
2156 (class crypto_vv):Ditto.
2157 (class crypto_vi):Ditto.
2158 (class vaeskf2_vsm3c):Ditto.
2159 (class vsm3me): Ditto.
2160 (BASE): Add BASE declaration for crypto vector.
2161 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2162 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2163 Add crypto vector intrinsic definition.
2164 (vbrev): Ditto.
2165 (vclz): Ditto.
2166 (vctz): Ditto.
2167 (vwsll): Ditto.
2168 (vandn): Ditto.
2169 (vbrev8): Ditto.
2170 (vrev8): Ditto.
2171 (vrol): Ditto.
2172 (vror): Ditto.
2173 (vclmul): Ditto.
2174 (vclmulh): Ditto.
2175 (vghsh): Ditto.
2176 (vgmul): Ditto.
2177 (vaesef): Ditto.
2178 (vaesem): Ditto.
2179 (vaesdf): Ditto.
2180 (vaesdm): Ditto.
2181 (vaesz): Ditto.
2182 (vaeskf1): Ditto.
2183 (vaeskf2): Ditto.
2184 (vsha2ms): Ditto.
2185 (vsha2ch): Ditto.
2186 (vsha2cl): Ditto.
2187 (vsm4k): Ditto.
2188 (vsm4r): Ditto.
2189 (vsm3me): Ditto.
2190 (vsm3c): Ditto.
2191 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2192 Add new function_shape for crypto vector.
2193 (struct crypto_vi_def): Ditto.
2194 (struct crypto_vv_no_op_type_def): Ditto.
2195 (SHAPE): Add SHAPE declaration of crypto vector.
2196 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2197 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2198 Add new data type for crypto vector.
2199 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2200 (vuint32mf2_t): Ditto.
2201 (vuint32m1_t): Ditto.
2202 (vuint32m2_t): Ditto.
2203 (vuint32m4_t): Ditto.
2204 (vuint32m8_t): Ditto.
2205 (vuint64m1_t): Ditto.
2206 (vuint64m2_t): Ditto.
2207 (vuint64m4_t): Ditto.
2208 (vuint64m8_t): Ditto.
2209 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2210 Add new data struct for crypto vector.
2211 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2212 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2213 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2215 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
2217 PR sanitizer/113251
2218 * varasm.cc (assemble_function_label_raw): Do not call
2219 asan_function_start () without the current function.
2221 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
2223 PR target/113225
2224 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
2225 extern and kernel_helper attributed function decls.
2227 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
2229 * btfout.cc (output_btf_strs): Changed.
2231 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
2233 * config/gcn/mkoffload.cc (main): Handle gfx1100
2234 when setting the default XNACK.
2236 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
2238 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
2239 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
2240 (ASM_SPEC): Handle gfx1100.
2241 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
2242 (enum gcn_isa): Add ISA_RDNA3.
2243 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
2244 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
2245 * config/gcn/gcn.cc (gcn_option_override,
2246 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
2247 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
2248 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
2249 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
2250 with gfx1100.
2251 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
2252 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
2253 __gfx1100__.
2254 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
2255 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
2256 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
2257 (isa_has_combined_avgprs, main): Handle gfx1100.
2258 * config/gcn/t-omp-device (isa): Add gfx1100.
2260 2024-01-08 Richard Biener <rguenther@suse.de>
2262 * doc/invoke.texi (-mmovbe): Clarify.
2264 2024-01-08 Richard Biener <rguenther@suse.de>
2266 PR tree-optimization/113026
2267 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
2268 Avoid an epilog in more cases.
2269 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
2270 epilogues niter upper bounds and estimates.
2272 2024-01-08 Jakub Jelinek <jakub@redhat.com>
2274 PR tree-optimization/113228
2275 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
2277 2024-01-08 Jakub Jelinek <jakub@redhat.com>
2279 PR tree-optimization/113120
2280 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
2281 large _BitInt zero INTEGER_CST PHI argument.
2283 2024-01-08 Jakub Jelinek <jakub@redhat.com>
2285 PR tree-optimization/113119
2286 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
2287 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
2288 is before REALPART_EXPR.
2290 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
2292 PR target/112952
2293 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
2294 range when diagnosing attribute "io" and "io_low" are out of range.
2295 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
2296 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
2297 in contexts other than static storage.
2298 (avr_asm_output_aligned_decl_common): Move output of decls with
2299 attribute "address", "io", and "io_low" to...
2300 (avr_output_addr_attrib): ...this new function.
2301 (avr_asm_asm_output_aligned_bss): Remove output for decls with
2302 attribute "address", "io", and "io_low".
2303 (avr_encode_section_info): Rectify handling of decls with attribute
2304 "address", "io", and "io_low".
2306 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
2308 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
2309 (elf_flags): Remove XNACK from the default value.
2310 (main): Set a default XNACK according to the arch.
2312 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
2314 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
2315 (process_asm): Don't count avgprs.
2317 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
2319 * config/i386/i386.opt: Add supported sub-features.
2320 * doc/extend.texi: Add description for target attribute.
2322 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
2324 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
2326 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
2327 Uros Bizjak <ubizjak@gmail.com>
2329 PR target/113231
2330 * config/i386/i386-features.cc (compute_convert_gain): Include
2331 the overhead of explicit load and store (movd) instructions when
2332 converting non-store scalar operations with memory destinations.
2333 Various indentation whitespace fixes.
2335 2024-01-07 Tamar Christina <tamar.christina@arm.com>
2337 * config/arm/neon.md (cbranch<mode>4): New.
2339 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2341 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
2343 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
2345 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
2347 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2349 PR target/113248
2350 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
2351 Update the MAX_SEW.
2353 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2355 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
2356 (variable_vectorized_p): Teach loop invariant.
2357 (has_unexpected_spills_p): Ditto.
2359 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2361 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
2362 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
2363 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
2365 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
2367 PR target/113104
2368 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
2369 (aarch64-vect-compare-costs): ...this.
2370 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
2371 Replace with...
2372 (-param=aarch64-vect-compare-costs=): ...this new param.
2373 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
2374 Don't disable it when vectorizing for Advanced SIMD only.
2375 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
2376 whenever aarch64_vect_compare_costs is true.
2378 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
2380 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
2381 Modify the method of determining the memory offset of [x]vld/[x]vst.
2382 (lasx_mxst_<lasxfmt_f>): Likewise.
2383 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
2384 (loongarch_address_insns): Likewise.
2385 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
2386 (lsx_st_<lsxfmt_f>): Likewise.
2387 * config/loongarch/predicates.md (aq10b_operand): Likewise.
2388 (aq10h_operand): Likewise.
2389 (aq10w_operand): Likewise.
2390 (aq10d_operand): Likewise.
2392 2024-01-05 Alex Coplan <alex.coplan@arm.com>
2394 PR target/113217
2395 * config/aarch64/aarch64-ldp-fusion.cc
2396 (ldp_bb_info::try_fuse_pair): If the second access can throw,
2397 narrow the move range to exactly that insn.
2399 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
2401 * asan.cc (asan_function_start): Drop switch_to_section ().
2402 (asan_emit_stack_protection): Set .LASANPC alignment.
2403 * config/i386/i386.cc: Use assemble_function_label_raw ()
2404 instead of ASM_OUTPUT_LABEL ().
2405 * config/s390/s390.cc (s390_asm_output_function_label):
2406 Likewise.
2407 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
2408 * final.cc (final_start_function_1): Drop
2409 asan_function_start ().
2410 * output.h (assemble_function_label_raw): New function.
2411 * varasm.cc (assemble_function_label_raw): Likewise.
2413 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
2415 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
2416 Use ASM_OUTPUT_FUNCTION_LABEL ().
2417 * config/alpha/alpha.cc (alpha_start_function): Likewise.
2418 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2419 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
2420 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2421 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2422 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
2423 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2424 * config/ia64/ia64.cc (ia64_start_function): Likewise.
2425 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
2426 Likewise.
2427 * config/microblaze/microblaze.cc (microblaze_function_prologue):
2428 Likewise.
2429 * config/mips/mips.cc (mips_start_unique_function): Return the
2430 tree.
2431 (mips_start_function_definition): Use
2432 ASM_OUTPUT_FUNCTION_LABEL ().
2433 (mips_finish_stub): Pass the tree to
2434 mips_start_function_definition ().
2435 (mips16_build_function_stub): Likewise.
2436 (mips16_build_call_stub): Likewise.
2437 (mips_output_function_prologue): Likewise.
2438 * config/pa/pa.cc (pa_output_function_label): Use
2439 ASM_OUTPUT_FUNCTION_LABEL ().
2440 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
2441 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
2442 Likewise.
2443 (rs6000_xcoff_declare_function_name): Likewise.
2445 2024-01-05 Jakub Jelinek <jakub@redhat.com>
2447 PR tree-optimization/113201
2448 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
2449 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
2451 2024-01-05 Jakub Jelinek <jakub@redhat.com>
2453 PR tree-optimization/90693
2454 * tree-ssa-math-opts.cc (match_single_bit_test): If
2455 tree_expr_nonzero_p (arg), remember it in the second argument to
2456 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
2457 arg ^ (arg - 1) > arg - 1.
2458 * internal-fn.cc (expand_POPCOUNT): If second argument to
2459 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
2460 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
2462 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
2464 * config/riscv/riscv-v.cc (expand_load_store):
2465 Remove `value`.
2466 (expand_cond_len_op): Ditto.
2467 (expand_gather_scatter): Ditto.
2468 (expand_lanes_load_store): Ditto.
2469 (expand_fold_extract_last): Ditto.
2471 2024-01-05 Pan Li <pan2.li@intel.com>
2473 Revert:
2474 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
2476 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2477 Add new function_base for crypto vector.
2478 (class bitmanip): Ditto.
2479 (class b_reverse):Ditto.
2480 (class vwsll): Ditto.
2481 (class clmul): Ditto.
2482 (class vg_nhab): Ditto.
2483 (class crypto_vv):Ditto.
2484 (class crypto_vi):Ditto.
2485 (class vaeskf2_vsm3c):Ditto.
2486 (class vsm3me): Ditto.
2487 (BASE): Add BASE declaration for crypto vector.
2488 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2489 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2490 Add crypto vector intrinsic definition.
2491 (vbrev): Ditto.
2492 (vclz): Ditto.
2493 (vctz): Ditto.
2494 (vwsll): Ditto.
2495 (vandn): Ditto.
2496 (vbrev8): Ditto.
2497 (vrev8): Ditto.
2498 (vrol): Ditto.
2499 (vror): Ditto.
2500 (vclmul): Ditto.
2501 (vclmulh): Ditto.
2502 (vghsh): Ditto.
2503 (vgmul): Ditto.
2504 (vaesef): Ditto.
2505 (vaesem): Ditto.
2506 (vaesdf): Ditto.
2507 (vaesdm): Ditto.
2508 (vaesz): Ditto.
2509 (vaeskf1): Ditto.
2510 (vaeskf2): Ditto.
2511 (vsha2ms): Ditto.
2512 (vsha2ch): Ditto.
2513 (vsha2cl): Ditto.
2514 (vsm4k): Ditto.
2515 (vsm4r): Ditto.
2516 (vsm3me): Ditto.
2517 (vsm3c): Ditto.
2518 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2519 Add new function_shape for crypto vector.
2520 (struct crypto_vi_def): Ditto.
2521 (struct crypto_vv_no_op_type_def): Ditto.
2522 (SHAPE): Add SHAPE declaration of crypto vector.
2523 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2524 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2525 Add new data type for crypto vector.
2526 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2527 (vuint32mf2_t): Ditto.
2528 (vuint32m1_t): Ditto.
2529 (vuint32m2_t): Ditto.
2530 (vuint32m4_t): Ditto.
2531 (vuint32m8_t): Ditto.
2532 (vuint64m1_t): Ditto.
2533 (vuint64m2_t): Ditto.
2534 (vuint64m4_t): Ditto.
2535 (vuint64m8_t): Ditto.
2536 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2537 Add new data struct for crypto vector.
2538 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2539 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2540 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2542 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
2544 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2545 Add new function_base for crypto vector.
2546 (class bitmanip): Ditto.
2547 (class b_reverse):Ditto.
2548 (class vwsll): Ditto.
2549 (class clmul): Ditto.
2550 (class vg_nhab): Ditto.
2551 (class crypto_vv):Ditto.
2552 (class crypto_vi):Ditto.
2553 (class vaeskf2_vsm3c):Ditto.
2554 (class vsm3me): Ditto.
2555 (BASE): Add BASE declaration for crypto vector.
2556 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2557 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2558 Add crypto vector intrinsic definition.
2559 (vbrev): Ditto.
2560 (vclz): Ditto.
2561 (vctz): Ditto.
2562 (vwsll): Ditto.
2563 (vandn): Ditto.
2564 (vbrev8): Ditto.
2565 (vrev8): Ditto.
2566 (vrol): Ditto.
2567 (vror): Ditto.
2568 (vclmul): Ditto.
2569 (vclmulh): Ditto.
2570 (vghsh): Ditto.
2571 (vgmul): Ditto.
2572 (vaesef): Ditto.
2573 (vaesem): Ditto.
2574 (vaesdf): Ditto.
2575 (vaesdm): Ditto.
2576 (vaesz): Ditto.
2577 (vaeskf1): Ditto.
2578 (vaeskf2): Ditto.
2579 (vsha2ms): Ditto.
2580 (vsha2ch): Ditto.
2581 (vsha2cl): Ditto.
2582 (vsm4k): Ditto.
2583 (vsm4r): Ditto.
2584 (vsm3me): Ditto.
2585 (vsm3c): Ditto.
2586 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2587 Add new function_shape for crypto vector.
2588 (struct crypto_vi_def): Ditto.
2589 (struct crypto_vv_no_op_type_def): Ditto.
2590 (SHAPE): Add SHAPE declaration of crypto vector.
2591 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2592 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2593 Add new data type for crypto vector.
2594 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2595 (vuint32mf2_t): Ditto.
2596 (vuint32m1_t): Ditto.
2597 (vuint32m2_t): Ditto.
2598 (vuint32m4_t): Ditto.
2599 (vuint32m8_t): Ditto.
2600 (vuint64m1_t): Ditto.
2601 (vuint64m2_t): Ditto.
2602 (vuint64m4_t): Ditto.
2603 (vuint64m8_t): Ditto.
2604 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2605 Add new data struct for crypto vector.
2606 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2607 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2608 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2610 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2612 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2614 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
2616 PR tree-optimization/113186
2617 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
2618 Match `^` with the `==` for 1bit integral types.
2619 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
2620 integral types.
2622 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2624 * toplev.cc (general_init): Pass lang_mask to urlifier.
2626 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2628 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
2629 param.
2630 (diagnostic_context::make_option_url): Update for lang_mask param.
2631 * gcc-urlifier.cc: Include "opts.h" and "options.h".
2632 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
2633 (gcc_urlifier::m_lang_mask): New field.
2634 (doc_urls): Make static.
2635 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
2636 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2637 Look for an option by name before trying a binary search in
2638 doc_urls.
2639 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2640 (gcc_urlifier::get_url_suffix_for_option): New.
2641 (make_gcc_urlifier): Add lang_mask param.
2642 (selftest::gcc_urlifier_cc_tests): Update for above changes.
2643 Verify that a URL is found for "-fpack-struct".
2644 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
2645 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
2646 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
2647 to make_gcc_urlifier.
2648 * opts-diagnostic.h (get_option_url): Add lang_mask param.
2649 * opts.cc (get_option_html_page): Remove special-casing for
2650 analyzer and LTO.
2651 (get_option_url_suffix): New.
2652 (get_option_url): Reimplement.
2653 (selftest::test_get_option_html_page): Rename to...
2654 (selftest::test_get_option_url_suffix): ...this and update for
2655 above changes.
2656 (selftest::opts_cc_tests): Update for renaming.
2657 * opts.h: Include "rich-location.h".
2658 (get_option_url_suffix): New decl.
2660 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2662 * Makefile.in (ALL_OPT_URL_FILES): New.
2663 (GCC_OBJS): Add options-urls.o.
2664 (OBJS): Likewise.
2665 (OBJS-libcommon): Likewise.
2666 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
2667 inputs to opt-gather.awk.
2668 (options-urls.cc): New Makefile target.
2669 * opt-functions.awk (url_suffix): New function.
2670 (lang_url_suffix): New function.
2671 * options-urls-cc-gen.awk: New file.
2672 * opts.h (get_opt_url_suffix): New decl.
2674 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2676 * params.opt.urls: New file, autogenerated by
2677 regenerate-opt-urls.py.
2679 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2681 * common.opt.urls: New file, autogenerated by
2682 regenerate-opt-urls.py.
2683 * config/aarch64/aarch64.opt.urls: Likewise.
2684 * config/alpha/alpha.opt.urls: Likewise.
2685 * config/alpha/elf.opt.urls: Likewise.
2686 * config/arc/arc-tables.opt.urls: Likewise.
2687 * config/arc/arc.opt.urls: Likewise.
2688 * config/arm/arm-tables.opt.urls: Likewise.
2689 * config/arm/arm.opt.urls: Likewise.
2690 * config/arm/vxworks.opt.urls: Likewise.
2691 * config/avr/avr.opt.urls: Likewise.
2692 * config/bpf/bpf.opt.urls: Likewise.
2693 * config/c6x/c6x-tables.opt.urls: Likewise.
2694 * config/c6x/c6x.opt.urls: Likewise.
2695 * config/cris/cris.opt.urls: Likewise.
2696 * config/cris/elf.opt.urls: Likewise.
2697 * config/csky/csky.opt.urls: Likewise.
2698 * config/csky/csky_tables.opt.urls: Likewise.
2699 * config/darwin.opt.urls: Likewise.
2700 * config/dragonfly.opt.urls: Likewise.
2701 * config/epiphany/epiphany.opt.urls: Likewise.
2702 * config/fr30/fr30.opt.urls: Likewise.
2703 * config/freebsd.opt.urls: Likewise.
2704 * config/frv/frv.opt.urls: Likewise.
2705 * config/ft32/ft32.opt.urls: Likewise.
2706 * config/fused-madd.opt.urls: Likewise.
2707 * config/g.opt.urls: Likewise.
2708 * config/gcn/gcn.opt.urls: Likewise.
2709 * config/gnu-user.opt.urls: Likewise.
2710 * config/h8300/h8300.opt.urls: Likewise.
2711 * config/hpux11.opt.urls: Likewise.
2712 * config/i386/cygming.opt.urls: Likewise.
2713 * config/i386/cygwin.opt.urls: Likewise.
2714 * config/i386/djgpp.opt.urls: Likewise.
2715 * config/i386/i386.opt.urls: Likewise.
2716 * config/i386/mingw-w64.opt.urls: Likewise.
2717 * config/i386/mingw.opt.urls: Likewise.
2718 * config/i386/nto.opt.urls: Likewise.
2719 * config/ia64/ia64.opt.urls: Likewise.
2720 * config/ia64/ilp32.opt.urls: Likewise.
2721 * config/ia64/vms.opt.urls: Likewise.
2722 * config/iq2000/iq2000.opt.urls: Likewise.
2723 * config/linux-android.opt.urls: Likewise.
2724 * config/linux.opt.urls: Likewise.
2725 * config/lm32/lm32.opt.urls: Likewise.
2726 * config/loongarch/loongarch.opt.urls: Likewise.
2727 * config/lynx.opt.urls: Likewise.
2728 * config/m32c/m32c.opt.urls: Likewise.
2729 * config/m32r/m32r.opt.urls: Likewise.
2730 * config/m68k/ieee.opt.urls: Likewise.
2731 * config/m68k/m68k-tables.opt.urls: Likewise.
2732 * config/m68k/m68k.opt.urls: Likewise.
2733 * config/m68k/uclinux.opt.urls: Likewise.
2734 * config/mcore/mcore.opt.urls: Likewise.
2735 * config/microblaze/microblaze.opt.urls: Likewise.
2736 * config/mips/mips-tables.opt.urls: Likewise.
2737 * config/mips/mips.opt.urls: Likewise.
2738 * config/mips/sde.opt.urls: Likewise.
2739 * config/mmix/mmix.opt.urls: Likewise.
2740 * config/mn10300/mn10300.opt.urls: Likewise.
2741 * config/moxie/moxie.opt.urls: Likewise.
2742 * config/msp430/msp430.opt.urls: Likewise.
2743 * config/nds32/nds32-elf.opt.urls: Likewise.
2744 * config/nds32/nds32-linux.opt.urls: Likewise.
2745 * config/nds32/nds32.opt.urls: Likewise.
2746 * config/netbsd-elf.opt.urls: Likewise.
2747 * config/netbsd.opt.urls: Likewise.
2748 * config/nios2/elf.opt.urls: Likewise.
2749 * config/nios2/nios2.opt.urls: Likewise.
2750 * config/nvptx/nvptx-gen.opt.urls: Likewise.
2751 * config/nvptx/nvptx.opt.urls: Likewise.
2752 * config/openbsd.opt.urls: Likewise.
2753 * config/or1k/elf.opt.urls: Likewise.
2754 * config/or1k/or1k.opt.urls: Likewise.
2755 * config/pa/pa-hpux.opt.urls: Likewise.
2756 * config/pa/pa-hpux1010.opt.urls: Likewise.
2757 * config/pa/pa-hpux1111.opt.urls: Likewise.
2758 * config/pa/pa-hpux1131.opt.urls: Likewise.
2759 * config/pa/pa.opt.urls: Likewise.
2760 * config/pa/pa64-hpux.opt.urls: Likewise.
2761 * config/pdp11/pdp11.opt.urls: Likewise.
2762 * config/pru/pru.opt.urls: Likewise.
2763 * config/riscv/riscv.opt.urls: Likewise.
2764 * config/rl78/rl78.opt.urls: Likewise.
2765 * config/rpath.opt.urls: Likewise.
2766 * config/rs6000/476.opt.urls: Likewise.
2767 * config/rs6000/aix64.opt.urls: Likewise.
2768 * config/rs6000/darwin.opt.urls: Likewise.
2769 * config/rs6000/linux64.opt.urls: Likewise.
2770 * config/rs6000/rs6000-tables.opt.urls: Likewise.
2771 * config/rs6000/rs6000.opt.urls: Likewise.
2772 * config/rs6000/sysv4.opt.urls: Likewise.
2773 * config/rtems.opt.urls: Likewise.
2774 * config/rx/elf.opt.urls: Likewise.
2775 * config/rx/rx.opt.urls: Likewise.
2776 * config/s390/s390.opt.urls: Likewise.
2777 * config/s390/tpf.opt.urls: Likewise.
2778 * config/sh/sh.opt.urls: Likewise.
2779 * config/sh/superh.opt.urls: Likewise.
2780 * config/sol2.opt.urls: Likewise.
2781 * config/sparc/long-double-switch.opt.urls: Likewise.
2782 * config/sparc/sparc.opt.urls: Likewise.
2783 * config/stormy16/stormy16.opt.urls: Likewise.
2784 * config/v850/v850.opt.urls: Likewise.
2785 * config/vax/elf.opt.urls: Likewise.
2786 * config/vax/vax.opt.urls: Likewise.
2787 * config/visium/visium.opt.urls: Likewise.
2788 * config/vms/vms.opt.urls: Likewise.
2789 * config/vxworks-smp.opt.urls: Likewise.
2790 * config/vxworks.opt.urls: Likewise.
2791 * config/xtensa/elf.opt.urls: Likewise.
2792 * config/xtensa/uclinux.opt.urls: Likewise.
2793 * config/xtensa/xtensa.opt.urls: Likewise.
2794 * config/bfin/bfin.opt.urls: New file.
2796 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2798 * Makefile.in (OPT_URLS_HTML_DEPS): New.
2799 (regenerate-opt-urls): New target.
2800 (regenerate-opt-urls-unit-test): New target.
2801 * doc/options.texi (Option properties): Add UrlSuffix and
2802 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
2803 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
2804 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
2805 and Makefile.in's OPT_URLS_HTML_DEPS.
2806 (Anatomy of a Target Back End): Add
2807 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
2808 * regenerate-opt-urls.py: New file.
2810 2024-01-04 David Malcolm <dmalcolm@redhat.com>
2812 * diagnostic-format-sarif.cc
2813 (sarif_builder::make_logical_location_object): Convert to...
2814 (make_sarif_logical_location_object): ...this.
2815 (sarif_builder::set_any_logical_locs_arr): Update for above
2816 change.
2817 (sarif_builder::make_thread_flow_location_object): Call
2818 maybe_add_sarif_properties on each diagnostic_event.
2819 * diagnostic-format-sarif.h (class logical_location): New forward
2820 decl.
2821 (make_sarif_logical_location_object): New decl.
2822 * diagnostic-path.h (class sarif_object): New forward decl.
2823 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
2825 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
2826 Patrick Lin <patrick@andestech.com>
2827 Rufus Chen <rufus@andestech.com>
2828 Monk Chiang <monk.chiang@sifive.com>
2830 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
2831 with Nan-boxing value.
2832 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
2834 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
2835 Jeff Law <jlaw@ventanamicro.com>
2837 PR rtl-optimization/104914
2838 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
2839 a sign or zero extension is only required if the modified field
2840 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
2841 targets, don't refer to the temporarily incorrectly extended value
2842 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
2844 2024-01-04 Pan Li <pan2.li@intel.com>
2846 Revert:
2847 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2849 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2851 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2853 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2855 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
2857 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
2858 offset of fcsr.
2860 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2862 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
2863 (compute_nregs_for_mode): Refine LMUL.
2864 (max_number_of_live_regs): Ditto.
2865 (compute_estimated_lmul): Ditto.
2866 (has_unexpected_spills_p): Ditto.
2868 2024-01-04 Li Wei <liwei@loongson.cn>
2870 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
2871 Remove useless forward declaration.
2872 (loongarch_is_even_extraction): Remove useless forward declaration.
2873 (loongarch_try_expand_lsx_vshuf_const): Removed.
2874 (loongarch_expand_vec_perm_const_1): Merged.
2875 (loongarch_is_double_duplicate): Removed.
2876 (loongarch_is_center_extraction): Ditto.
2877 (loongarch_is_reversing_permutation): Ditto.
2878 (loongarch_is_di_misalign_extract): Ditto.
2879 (loongarch_is_si_misalign_extract): Ditto.
2880 (loongarch_is_lasx_lowpart_extract): Ditto.
2881 (loongarch_is_op_reverse_perm): Ditto.
2882 (loongarch_is_single_op_perm): Ditto.
2883 (loongarch_is_divisible_perm): Ditto.
2884 (loongarch_is_triple_stride_extract): Ditto.
2885 (loongarch_expand_vec_perm_const_2): Merged.
2886 (loongarch_expand_vec_perm_const): New.
2887 (loongarch_vectorize_vec_perm_const): Adjust.
2889 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
2891 * omp-general.cc: Fix comment typos and misplaced/confusing
2892 comments. Delete redundant include of omp-general.h.
2894 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
2896 PR rtl-optimization/104914
2897 * config/mips/mips.md (insqisi_extended): New patterns.
2898 (inshisi_extended): Ditto.
2900 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
2902 * config/mips/mips.cc (mips_insn_cost): New function.
2904 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
2906 * config/mips/mips.md (perf_ratio): New attribute.
2908 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2910 PR target/113206
2911 PR target/113209
2912 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
2913 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
2914 blocks belong to infinite loop.
2915 (pre_vsetvl::emit_vsetvl): Remove fake edges.
2916 * config/riscv/t-riscv: Add a new include file.
2918 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2920 * config/riscv/vector.md: Fix indent.
2922 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
2924 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
2925 OMP_CLAUSE__SIMDUID_.
2926 * tree.cc (omp_clause_num_ops): Update position of entry for
2927 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
2928 (omp_clause_code_name): Likewise.
2930 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
2932 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
2933 printing of FUNC_MAP/IND_FUNC_MAP labels.
2935 2024-01-03 Jakub Jelinek <jakub@redhat.com>
2937 * gcc.cc (process_command): Update copyright notice dates.
2938 * gcov-dump.cc (print_version): Ditto.
2939 * gcov.cc (print_version): Ditto.
2940 * gcov-tool.cc (print_version): Ditto.
2941 * gengtype.cc (create_file): Ditto.
2942 * doc/cpp.texi: Bump @copying's copyright year.
2943 * doc/cppinternals.texi: Ditto.
2944 * doc/gcc.texi: Ditto.
2945 * doc/gccint.texi: Ditto.
2946 * doc/gcov.texi: Ditto.
2947 * doc/install.texi: Ditto.
2948 * doc/invoke.texi: Ditto.
2950 2024-01-03 Xi Ruoyao <xry111@xry111.site>
2952 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
2953 (fmin<mode>3): Likewise.
2954 (reduc_fmax_scal_<mode>3): New define_expand.
2955 (reduc_fmin_scal_<mode>3): Likewise.
2957 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2959 PR target/113112
2960 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
2961 (max_number_of_live_regs): Ditto.
2962 (has_unexpected_spills_p): Ditto.
2964 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
2965 Jin Ma <jinma@linux.alibaba.com>
2966 Xianmiao Qu <cooper.qu@linux.alibaba.com>
2967 Christoph Müllner <christoph.muellner@vrull.eu>
2969 * config/riscv/vector.md:
2970 Use vector_length_operand for vsetvl patterns.
2972 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2974 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
2975 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
2977 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
2979 * config/aarch64/aarch64-tuning-flags.def
2980 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
2981 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
2982 * config/aarch64/aarch64.cc
2983 (aarch64_override_options_internal): Set
2984 param_fully_pipelined_fma according to tuning option.
2985 * config/aarch64/tuning_models/ampere1.h: Add
2986 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
2987 * config/aarch64/tuning_models/ampere1a.h: Likewise.
2988 * config/aarch64/tuning_models/ampere1b.h: Likewise.
2990 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
2992 * config/riscv/vector-crypto.md: Modify copyright year.
2994 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2996 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
2998 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
3000 * config.in: Regenerate.
3001 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
3002 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
3003 Added TLS Le Relax support.
3004 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
3005 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
3006 * configure: Regenerate.
3007 * configure.ac: Check if binutils supports TLS le relax.
3009 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
3011 * config/riscv/iterators.md: Add rotate insn name.
3012 * config/riscv/riscv.md: Add new insns name for crypto vector.
3013 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
3014 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
3015 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
3017 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3019 PR target/113112
3020 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
3021 pointer type liveness count.
3022 \f
3023 Copyright (C) 2024 Free Software Foundation, Inc.
3025 Copying and distribution of this file, with or without modification,
3026 are permitted in any medium without royalty provided the copyright
3027 notice and this notice are preserved.