1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
56 /* This is used for communication between ASM_OUTPUT_LABEL and
57 ASM_OUTPUT_LABELREF. */
58 int ia64_asm_output_label
= 0;
60 /* Define the information needed to generate branch and scc insns. This is
61 stored from the compare operation. */
62 struct rtx_def
* ia64_compare_op0
;
63 struct rtx_def
* ia64_compare_op1
;
65 /* Register names for ia64_expand_prologue. */
66 static const char * const ia64_reg_numbers
[96] =
67 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
68 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
69 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
70 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
71 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
72 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
73 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
74 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
75 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
76 "r104","r105","r106","r107","r108","r109","r110","r111",
77 "r112","r113","r114","r115","r116","r117","r118","r119",
78 "r120","r121","r122","r123","r124","r125","r126","r127"};
80 /* ??? These strings could be shared with REGISTER_NAMES. */
81 static const char * const ia64_input_reg_names
[8] =
82 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
84 /* ??? These strings could be shared with REGISTER_NAMES. */
85 static const char * const ia64_local_reg_names
[80] =
86 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
87 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
88 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
89 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
90 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
91 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
92 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
93 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
94 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
95 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_output_reg_names
[8] =
99 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
101 /* String used with the -mfixed-range= option. */
102 const char *ia64_fixed_range_string
;
104 /* Determines whether we use adds, addl, or movl to generate our
105 TLS immediate offsets. */
106 int ia64_tls_size
= 22;
108 /* String used with the -mtls-size= option. */
109 const char *ia64_tls_size_string
;
111 /* Which cpu are we scheduling for. */
112 enum processor_type ia64_tune
;
114 /* String used with the -tune= option. */
115 const char *ia64_tune_string
;
117 /* Determines whether we run our final scheduling pass or not. We always
118 avoid the normal second scheduling pass. */
119 static int ia64_flag_schedule_insns2
;
121 /* Determines whether we run variable tracking in machine dependent
123 static int ia64_flag_var_tracking
;
125 /* Variables which are this size or smaller are put in the sdata/sbss
128 unsigned int ia64_section_threshold
;
130 /* The following variable is used by the DFA insn scheduler. The value is
131 TRUE if we do insn bundling instead of insn scheduling. */
134 /* Structure to be filled in by ia64_compute_frame_size with register
135 save masks and offsets for the current function. */
137 struct ia64_frame_info
139 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
140 the caller's scratch area. */
141 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
142 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
143 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
144 HARD_REG_SET mask
; /* mask of saved registers. */
145 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
146 registers or long-term scratches. */
147 int n_spilled
; /* number of spilled registers. */
148 int reg_fp
; /* register for fp. */
149 int reg_save_b0
; /* save register for b0. */
150 int reg_save_pr
; /* save register for prs. */
151 int reg_save_ar_pfs
; /* save register for ar.pfs. */
152 int reg_save_ar_unat
; /* save register for ar.unat. */
153 int reg_save_ar_lc
; /* save register for ar.lc. */
154 int reg_save_gp
; /* save register for gp. */
155 int n_input_regs
; /* number of input registers used. */
156 int n_local_regs
; /* number of local registers used. */
157 int n_output_regs
; /* number of output registers used. */
158 int n_rotate_regs
; /* number of rotating registers used. */
160 char need_regstk
; /* true if a .regstk directive needed. */
161 char initialized
; /* true if the data is finalized. */
164 /* Current frame information calculated by ia64_compute_frame_size. */
165 static struct ia64_frame_info current_frame_info
;
167 static int ia64_first_cycle_multipass_dfa_lookahead (void);
168 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
169 static void ia64_init_dfa_pre_cycle_insn (void);
170 static rtx
ia64_dfa_pre_cycle_insn (void);
171 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
172 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
173 static rtx
gen_tls_get_addr (void);
174 static rtx
gen_thread_pointer (void);
175 static rtx
ia64_expand_tls_address (enum tls_model
, rtx
, rtx
);
176 static int find_gr_spill (int);
177 static int next_scratch_gr_reg (void);
178 static void mark_reg_gr_used_mask (rtx
, void *);
179 static void ia64_compute_frame_size (HOST_WIDE_INT
);
180 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
181 static void finish_spill_pointers (void);
182 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
183 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
184 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
185 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
186 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
187 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
189 static enum machine_mode
hfa_element_mode (tree
, bool);
190 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
192 static bool ia64_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
194 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
196 static bool ia64_function_ok_for_sibcall (tree
, tree
);
197 static bool ia64_return_in_memory (tree
, tree
);
198 static bool ia64_rtx_costs (rtx
, int, int, int *);
199 static void fix_range (const char *);
200 static struct machine_function
* ia64_init_machine_status (void);
201 static void emit_insn_group_barriers (FILE *);
202 static void emit_all_insn_group_barriers (FILE *);
203 static void final_emit_insn_group_barriers (FILE *);
204 static void emit_predicate_relation_info (void);
205 static void ia64_reorg (void);
206 static bool ia64_in_small_data_p (tree
);
207 static void process_epilogue (void);
208 static int process_set (FILE *, rtx
);
210 static rtx
ia64_expand_fetch_and_op (optab
, enum machine_mode
, tree
, rtx
);
211 static rtx
ia64_expand_op_and_fetch (optab
, enum machine_mode
, tree
, rtx
);
212 static rtx
ia64_expand_compare_and_swap (enum machine_mode
, enum machine_mode
,
214 static rtx
ia64_expand_lock_test_and_set (enum machine_mode
, tree
, rtx
);
215 static rtx
ia64_expand_lock_release (enum machine_mode
, tree
, rtx
);
216 static bool ia64_assemble_integer (rtx
, unsigned int, int);
217 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
218 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
219 static void ia64_output_function_end_prologue (FILE *);
221 static int ia64_issue_rate (void);
222 static int ia64_adjust_cost (rtx
, rtx
, rtx
, int);
223 static void ia64_sched_init (FILE *, int, int);
224 static void ia64_sched_finish (FILE *, int);
225 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
226 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
227 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
228 static int ia64_variable_issue (FILE *, int, rtx
, int);
230 static struct bundle_state
*get_free_bundle_state (void);
231 static void free_bundle_state (struct bundle_state
*);
232 static void initiate_bundle_states (void);
233 static void finish_bundle_states (void);
234 static unsigned bundle_state_hash (const void *);
235 static int bundle_state_eq_p (const void *, const void *);
236 static int insert_bundle_state (struct bundle_state
*);
237 static void initiate_bundle_state_table (void);
238 static void finish_bundle_state_table (void);
239 static int try_issue_nops (struct bundle_state
*, int);
240 static int try_issue_insn (struct bundle_state
*, rtx
);
241 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
242 static int get_max_pos (state_t
);
243 static int get_template (state_t
, int);
245 static rtx
get_next_important_insn (rtx
, rtx
);
246 static void bundling (FILE *, int, rtx
, rtx
);
248 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
249 HOST_WIDE_INT
, tree
);
250 static void ia64_file_start (void);
252 static void ia64_select_rtx_section (enum machine_mode
, rtx
,
253 unsigned HOST_WIDE_INT
);
254 static void ia64_rwreloc_select_section (tree
, int, unsigned HOST_WIDE_INT
)
256 static void ia64_rwreloc_unique_section (tree
, int)
258 static void ia64_rwreloc_select_rtx_section (enum machine_mode
, rtx
,
259 unsigned HOST_WIDE_INT
)
261 static unsigned int ia64_section_type_flags (tree
, const char *, int);
262 static void ia64_hpux_add_extern_decl (tree decl
)
264 static void ia64_hpux_file_end (void)
266 static void ia64_init_libfuncs (void)
268 static void ia64_hpux_init_libfuncs (void)
270 static void ia64_sysv4_init_libfuncs (void)
272 static void ia64_vms_init_libfuncs (void)
275 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
276 static void ia64_encode_section_info (tree
, rtx
, int);
277 static rtx
ia64_struct_value_rtx (tree
, int);
278 static tree
ia64_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
279 static bool ia64_scalar_mode_supported_p (enum machine_mode mode
);
280 static bool ia64_vector_mode_supported_p (enum machine_mode mode
);
283 /* Table of valid machine attributes. */
284 static const struct attribute_spec ia64_attribute_table
[] =
286 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
287 { "syscall_linkage", 0, 0, false, true, true, NULL
},
288 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
},
289 { NULL
, 0, 0, false, false, false, NULL
}
292 /* Initialize the GCC target structure. */
293 #undef TARGET_ATTRIBUTE_TABLE
294 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
296 #undef TARGET_INIT_BUILTINS
297 #define TARGET_INIT_BUILTINS ia64_init_builtins
299 #undef TARGET_EXPAND_BUILTIN
300 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
302 #undef TARGET_ASM_BYTE_OP
303 #define TARGET_ASM_BYTE_OP "\tdata1\t"
304 #undef TARGET_ASM_ALIGNED_HI_OP
305 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
306 #undef TARGET_ASM_ALIGNED_SI_OP
307 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
308 #undef TARGET_ASM_ALIGNED_DI_OP
309 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
310 #undef TARGET_ASM_UNALIGNED_HI_OP
311 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
312 #undef TARGET_ASM_UNALIGNED_SI_OP
313 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
314 #undef TARGET_ASM_UNALIGNED_DI_OP
315 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
316 #undef TARGET_ASM_INTEGER
317 #define TARGET_ASM_INTEGER ia64_assemble_integer
319 #undef TARGET_ASM_FUNCTION_PROLOGUE
320 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
321 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
322 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
323 #undef TARGET_ASM_FUNCTION_EPILOGUE
324 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
326 #undef TARGET_IN_SMALL_DATA_P
327 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
329 #undef TARGET_SCHED_ADJUST_COST
330 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
331 #undef TARGET_SCHED_ISSUE_RATE
332 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
333 #undef TARGET_SCHED_VARIABLE_ISSUE
334 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
335 #undef TARGET_SCHED_INIT
336 #define TARGET_SCHED_INIT ia64_sched_init
337 #undef TARGET_SCHED_FINISH
338 #define TARGET_SCHED_FINISH ia64_sched_finish
339 #undef TARGET_SCHED_REORDER
340 #define TARGET_SCHED_REORDER ia64_sched_reorder
341 #undef TARGET_SCHED_REORDER2
342 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
344 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
345 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
347 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
348 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
350 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
351 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
352 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
353 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
355 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
356 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
357 ia64_first_cycle_multipass_dfa_lookahead_guard
359 #undef TARGET_SCHED_DFA_NEW_CYCLE
360 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
362 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
363 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
364 #undef TARGET_PASS_BY_REFERENCE
365 #define TARGET_PASS_BY_REFERENCE ia64_pass_by_reference
366 #undef TARGET_ARG_PARTIAL_BYTES
367 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
369 #undef TARGET_ASM_OUTPUT_MI_THUNK
370 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
371 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
372 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
374 #undef TARGET_ASM_FILE_START
375 #define TARGET_ASM_FILE_START ia64_file_start
377 #undef TARGET_RTX_COSTS
378 #define TARGET_RTX_COSTS ia64_rtx_costs
379 #undef TARGET_ADDRESS_COST
380 #define TARGET_ADDRESS_COST hook_int_rtx_0
382 #undef TARGET_MACHINE_DEPENDENT_REORG
383 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
385 #undef TARGET_ENCODE_SECTION_INFO
386 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
388 #undef TARGET_SECTION_TYPE_FLAGS
389 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
391 /* ??? ABI doesn't allow us to define this. */
393 #undef TARGET_PROMOTE_FUNCTION_ARGS
394 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
397 /* ??? ABI doesn't allow us to define this. */
399 #undef TARGET_PROMOTE_FUNCTION_RETURN
400 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
403 /* ??? Investigate. */
405 #undef TARGET_PROMOTE_PROTOTYPES
406 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
409 #undef TARGET_STRUCT_VALUE_RTX
410 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
411 #undef TARGET_RETURN_IN_MEMORY
412 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
413 #undef TARGET_SETUP_INCOMING_VARARGS
414 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
415 #undef TARGET_STRICT_ARGUMENT_NAMING
416 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
417 #undef TARGET_MUST_PASS_IN_STACK
418 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
420 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
421 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
423 #undef TARGET_UNWIND_EMIT
424 #define TARGET_UNWIND_EMIT process_for_unwind_directive
426 #undef TARGET_SCALAR_MODE_SUPPORTED_P
427 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
428 #undef TARGET_VECTOR_MODE_SUPPORTED_P
429 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
431 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
432 in an order different from the specified program order. */
433 #undef TARGET_RELAXED_ORDERING
434 #define TARGET_RELAXED_ORDERING true
436 struct gcc_target targetm
= TARGET_INITIALIZER
;
440 ADDR_AREA_NORMAL
, /* normal address area */
441 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
445 static GTY(()) tree small_ident1
;
446 static GTY(()) tree small_ident2
;
451 if (small_ident1
== 0)
453 small_ident1
= get_identifier ("small");
454 small_ident2
= get_identifier ("__small__");
458 /* Retrieve the address area that has been chosen for the given decl. */
460 static ia64_addr_area
461 ia64_get_addr_area (tree decl
)
465 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
471 id
= TREE_VALUE (TREE_VALUE (model_attr
));
472 if (id
== small_ident1
|| id
== small_ident2
)
473 return ADDR_AREA_SMALL
;
475 return ADDR_AREA_NORMAL
;
479 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
,
480 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
482 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
484 tree arg
, decl
= *node
;
487 arg
= TREE_VALUE (args
);
488 if (arg
== small_ident1
|| arg
== small_ident2
)
490 addr_area
= ADDR_AREA_SMALL
;
494 warning ("invalid argument of %qs attribute",
495 IDENTIFIER_POINTER (name
));
496 *no_add_attrs
= true;
499 switch (TREE_CODE (decl
))
502 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
504 && !TREE_STATIC (decl
))
506 error ("%Jan address area attribute cannot be specified for "
507 "local variables", decl
, decl
);
508 *no_add_attrs
= true;
510 area
= ia64_get_addr_area (decl
);
511 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
513 error ("%Jaddress area of '%s' conflicts with previous "
514 "declaration", decl
, decl
);
515 *no_add_attrs
= true;
520 error ("%Jaddress area attribute cannot be specified for functions",
522 *no_add_attrs
= true;
526 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
527 *no_add_attrs
= true;
535 ia64_encode_addr_area (tree decl
, rtx symbol
)
539 flags
= SYMBOL_REF_FLAGS (symbol
);
540 switch (ia64_get_addr_area (decl
))
542 case ADDR_AREA_NORMAL
: break;
543 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
546 SYMBOL_REF_FLAGS (symbol
) = flags
;
550 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
552 default_encode_section_info (decl
, rtl
, first
);
554 /* Careful not to prod global register variables. */
555 if (TREE_CODE (decl
) == VAR_DECL
556 && GET_CODE (DECL_RTL (decl
)) == MEM
557 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
558 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
559 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
562 /* Implement CONST_OK_FOR_LETTER_P. */
565 ia64_const_ok_for_letter_p (HOST_WIDE_INT value
, char c
)
570 return CONST_OK_FOR_I (value
);
572 return CONST_OK_FOR_J (value
);
574 return CONST_OK_FOR_K (value
);
576 return CONST_OK_FOR_L (value
);
578 return CONST_OK_FOR_M (value
);
580 return CONST_OK_FOR_N (value
);
582 return CONST_OK_FOR_O (value
);
584 return CONST_OK_FOR_P (value
);
590 /* Implement CONST_DOUBLE_OK_FOR_LETTER_P. */
593 ia64_const_double_ok_for_letter_p (rtx value
, char c
)
598 return CONST_DOUBLE_OK_FOR_G (value
);
604 /* Implement EXTRA_CONSTRAINT. */
607 ia64_extra_constraint (rtx value
, char c
)
612 /* Non-volatile memory for FP_REG loads/stores. */
613 return memory_operand(value
, VOIDmode
) && !MEM_VOLATILE_P (value
);
616 /* 1..4 for shladd arguments. */
617 return (GET_CODE (value
) == CONST_INT
618 && INTVAL (value
) >= 1 && INTVAL (value
) <= 4);
621 /* Non-post-inc memory for asms and other unsavory creatures. */
622 return (GET_CODE (value
) == MEM
623 && GET_RTX_CLASS (GET_CODE (XEXP (value
, 0))) != RTX_AUTOINC
624 && (reload_in_progress
|| memory_operand (value
, VOIDmode
)));
627 /* Symbol ref to small-address-area. */
628 return (GET_CODE (value
) == SYMBOL_REF
629 && SYMBOL_REF_SMALL_ADDR_P (value
));
633 return value
== CONST0_RTX (GET_MODE (value
));
636 /* An integer vector, such that conversion to an integer yields a
637 value appropriate for an integer 'J' constraint. */
638 if (GET_CODE (value
) == CONST_VECTOR
639 && GET_MODE_CLASS (GET_MODE (value
)) == MODE_VECTOR_INT
)
641 value
= simplify_subreg (DImode
, value
, GET_MODE (value
), 0);
642 return ia64_const_ok_for_letter_p (INTVAL (value
), 'J');
647 /* A V2SF vector containing elements that satisfy 'G'. */
649 (GET_CODE (value
) == CONST_VECTOR
650 && GET_MODE (value
) == V2SFmode
651 && ia64_const_double_ok_for_letter_p (XVECEXP (value
, 0, 0), 'G')
652 && ia64_const_double_ok_for_letter_p (XVECEXP (value
, 0, 1), 'G'));
659 /* Return 1 if the operands of a move are ok. */
662 ia64_move_ok (rtx dst
, rtx src
)
664 /* If we're under init_recog_no_volatile, we'll not be able to use
665 memory_operand. So check the code directly and don't worry about
666 the validity of the underlying address, which should have been
667 checked elsewhere anyway. */
668 if (GET_CODE (dst
) != MEM
)
670 if (GET_CODE (src
) == MEM
)
672 if (register_operand (src
, VOIDmode
))
675 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
676 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
677 return src
== const0_rtx
;
679 return GET_CODE (src
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (src
);
683 addp4_optimize_ok (rtx op1
, rtx op2
)
685 return (basereg_operand (op1
, GET_MODE(op1
)) !=
686 basereg_operand (op2
, GET_MODE(op2
)));
689 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
690 Return the length of the field, or <= 0 on failure. */
693 ia64_depz_field_mask (rtx rop
, rtx rshift
)
695 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
696 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
698 /* Get rid of the zero bits we're shifting in. */
701 /* We must now have a solid block of 1's at bit 0. */
702 return exact_log2 (op
+ 1);
705 /* Expand a symbolic constant load. */
708 ia64_expand_load_address (rtx dest
, rtx src
)
710 if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (src
))
712 if (GET_CODE (dest
) != REG
)
715 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
716 having to pointer-extend the value afterward. Other forms of address
717 computation below are also more natural to compute as 64-bit quantities.
718 If we've been given an SImode destination register, change it. */
719 if (GET_MODE (dest
) != Pmode
)
720 dest
= gen_rtx_REG (Pmode
, REGNO (dest
));
722 if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_ADDR_P (src
))
724 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
727 else if (TARGET_AUTO_PIC
)
729 emit_insn (gen_load_gprel64 (dest
, src
));
732 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
734 emit_insn (gen_load_fptr (dest
, src
));
737 else if (sdata_symbolic_operand (src
, VOIDmode
))
739 emit_insn (gen_load_gprel (dest
, src
));
743 if (GET_CODE (src
) == CONST
744 && GET_CODE (XEXP (src
, 0)) == PLUS
745 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
746 && (INTVAL (XEXP (XEXP (src
, 0), 1)) & 0x3fff) != 0)
748 rtx sym
= XEXP (XEXP (src
, 0), 0);
749 HOST_WIDE_INT ofs
, hi
, lo
;
751 /* Split the offset into a sign extended 14-bit low part
752 and a complementary high part. */
753 ofs
= INTVAL (XEXP (XEXP (src
, 0), 1));
754 lo
= ((ofs
& 0x3fff) ^ 0x2000) - 0x2000;
757 ia64_expand_load_address (dest
, plus_constant (sym
, hi
));
758 emit_insn (gen_adddi3 (dest
, dest
, GEN_INT (lo
)));
764 tmp
= gen_rtx_HIGH (Pmode
, src
);
765 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
766 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
768 tmp
= gen_rtx_LO_SUM (GET_MODE (dest
), dest
, src
);
769 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
773 static GTY(()) rtx gen_tls_tga
;
775 gen_tls_get_addr (void)
778 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
782 static GTY(()) rtx thread_pointer_rtx
;
784 gen_thread_pointer (void)
786 if (!thread_pointer_rtx
)
787 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
788 return thread_pointer_rtx
;
792 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
)
794 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
799 case TLS_MODEL_GLOBAL_DYNAMIC
:
802 tga_op1
= gen_reg_rtx (Pmode
);
803 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
804 tga_op1
= gen_const_mem (Pmode
, tga_op1
);
806 tga_op2
= gen_reg_rtx (Pmode
);
807 emit_insn (gen_load_ltoff_dtprel (tga_op2
, op1
));
808 tga_op2
= gen_const_mem (Pmode
, tga_op2
);
810 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
811 LCT_CONST
, Pmode
, 2, tga_op1
,
812 Pmode
, tga_op2
, Pmode
);
814 insns
= get_insns ();
817 if (GET_MODE (op0
) != Pmode
)
819 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
822 case TLS_MODEL_LOCAL_DYNAMIC
:
823 /* ??? This isn't the completely proper way to do local-dynamic
824 If the call to __tls_get_addr is used only by a single symbol,
825 then we should (somehow) move the dtprel to the second arg
826 to avoid the extra add. */
829 tga_op1
= gen_reg_rtx (Pmode
);
830 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
831 tga_op1
= gen_const_mem (Pmode
, tga_op1
);
833 tga_op2
= const0_rtx
;
835 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
836 LCT_CONST
, Pmode
, 2, tga_op1
,
837 Pmode
, tga_op2
, Pmode
);
839 insns
= get_insns ();
842 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
844 tmp
= gen_reg_rtx (Pmode
);
845 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
847 if (!register_operand (op0
, Pmode
))
848 op0
= gen_reg_rtx (Pmode
);
851 emit_insn (gen_load_dtprel (op0
, op1
));
852 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
855 emit_insn (gen_add_dtprel (op0
, tmp
, op1
));
858 case TLS_MODEL_INITIAL_EXEC
:
859 tmp
= gen_reg_rtx (Pmode
);
860 emit_insn (gen_load_ltoff_tprel (tmp
, op1
));
861 tmp
= gen_const_mem (Pmode
, tmp
);
862 tmp
= force_reg (Pmode
, tmp
);
864 if (!register_operand (op0
, Pmode
))
865 op0
= gen_reg_rtx (Pmode
);
866 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
869 case TLS_MODEL_LOCAL_EXEC
:
870 if (!register_operand (op0
, Pmode
))
871 op0
= gen_reg_rtx (Pmode
);
874 emit_insn (gen_load_tprel (op0
, op1
));
875 emit_insn (gen_adddi3 (op0
, gen_thread_pointer (), op0
));
878 emit_insn (gen_add_tprel (op0
, gen_thread_pointer (), op1
));
887 if (GET_MODE (orig_op0
) == Pmode
)
889 return gen_lowpart (GET_MODE (orig_op0
), op0
);
893 ia64_expand_move (rtx op0
, rtx op1
)
895 enum machine_mode mode
= GET_MODE (op0
);
897 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
898 op1
= force_reg (mode
, op1
);
900 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
902 enum tls_model tls_kind
;
903 if (GET_CODE (op1
) == SYMBOL_REF
904 && (tls_kind
= SYMBOL_REF_TLS_MODEL (op1
)))
905 return ia64_expand_tls_address (tls_kind
, op0
, op1
);
907 if (!TARGET_NO_PIC
&& reload_completed
)
909 ia64_expand_load_address (op0
, op1
);
917 /* Split a move from OP1 to OP0 conditional on COND. */
920 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
922 rtx insn
, first
= get_last_insn ();
924 emit_move_insn (op0
, op1
);
926 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
928 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
932 /* Split a post-reload TImode or TFmode reference into two DImode
933 components. This is made extra difficult by the fact that we do
934 not get any scratch registers to work with, because reload cannot
935 be prevented from giving us a scratch that overlaps the register
936 pair involved. So instead, when addressing memory, we tweak the
937 pointer register up and back down with POST_INCs. Or up and not
938 back down when we can get away with it.
940 REVERSED is true when the loads must be done in reversed order
941 (high word first) for correctness. DEAD is true when the pointer
942 dies with the second insn we generate and therefore the second
943 address must not carry a postmodify.
945 May return an insn which is to be emitted after the moves. */
948 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
952 switch (GET_CODE (in
))
955 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
956 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
961 /* Cannot occur reversed. */
962 if (reversed
) abort ();
964 if (GET_MODE (in
) != TFmode
)
965 split_double (in
, &out
[0], &out
[1]);
967 /* split_double does not understand how to split a TFmode
968 quantity into a pair of DImode constants. */
971 unsigned HOST_WIDE_INT p
[2];
972 long l
[4]; /* TFmode is 128 bits */
974 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
975 real_to_target (l
, &r
, TFmode
);
977 if (FLOAT_WORDS_BIG_ENDIAN
)
979 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
980 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
984 p
[0] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
985 p
[1] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
987 out
[0] = GEN_INT (p
[0]);
988 out
[1] = GEN_INT (p
[1]);
994 rtx base
= XEXP (in
, 0);
997 switch (GET_CODE (base
))
1002 out
[0] = adjust_automodify_address
1003 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1004 out
[1] = adjust_automodify_address
1005 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1009 /* Reversal requires a pre-increment, which can only
1010 be done as a separate insn. */
1011 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1012 out
[0] = adjust_automodify_address
1013 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1014 out
[1] = adjust_address (in
, DImode
, 0);
1019 if (reversed
|| dead
) abort ();
1020 /* Just do the increment in two steps. */
1021 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1022 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1026 if (reversed
|| dead
) abort ();
1027 /* Add 8, subtract 24. */
1028 base
= XEXP (base
, 0);
1029 out
[0] = adjust_automodify_address
1030 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1031 out
[1] = adjust_automodify_address
1033 gen_rtx_POST_MODIFY (Pmode
, base
, plus_constant (base
, -24)),
1038 if (reversed
|| dead
) abort ();
1039 /* Extract and adjust the modification. This case is
1040 trickier than the others, because we might have an
1041 index register, or we might have a combined offset that
1042 doesn't fit a signed 9-bit displacement field. We can
1043 assume the incoming expression is already legitimate. */
1044 offset
= XEXP (base
, 1);
1045 base
= XEXP (base
, 0);
1047 out
[0] = adjust_automodify_address
1048 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1050 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1052 /* Can't adjust the postmodify to match. Emit the
1053 original, then a separate addition insn. */
1054 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1055 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1057 else if (GET_CODE (XEXP (offset
, 1)) != CONST_INT
)
1059 else if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1061 /* Again the postmodify cannot be made to match, but
1062 in this case it's more efficient to get rid of the
1063 postmodify entirely and fix up with an add insn. */
1064 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1065 fixup
= gen_adddi3 (base
, base
,
1066 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1070 /* Combined offset still fits in the displacement field.
1071 (We cannot overflow it at the high end.) */
1072 out
[1] = adjust_automodify_address
1074 gen_rtx_POST_MODIFY (Pmode
, base
,
1075 gen_rtx_PLUS (Pmode
, base
,
1076 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1094 /* Split a TImode or TFmode move instruction after reload.
1095 This is used by *movtf_internal and *movti_internal. */
1097 ia64_split_tmode_move (rtx operands
[])
1099 rtx in
[2], out
[2], insn
;
1102 bool reversed
= false;
1104 /* It is possible for reload to decide to overwrite a pointer with
1105 the value it points to. In that case we have to do the loads in
1106 the appropriate order so that the pointer is not destroyed too
1107 early. Also we must not generate a postmodify for that second
1108 load, or rws_access_regno will abort. */
1109 if (GET_CODE (operands
[1]) == MEM
1110 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1112 rtx base
= XEXP (operands
[1], 0);
1113 while (GET_CODE (base
) != REG
)
1114 base
= XEXP (base
, 0);
1116 if (REGNO (base
) == REGNO (operands
[0]))
1120 /* Another reason to do the moves in reversed order is if the first
1121 element of the target register pair is also the second element of
1122 the source register pair. */
1123 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1124 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1127 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1128 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1130 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1131 if (GET_CODE (EXP) == MEM \
1132 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1133 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1134 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1135 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1136 XEXP (XEXP (EXP, 0), 0), \
1139 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1140 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1141 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1143 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1144 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1145 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1148 emit_insn (fixup
[0]);
1150 emit_insn (fixup
[1]);
1152 #undef MAYBE_ADD_REG_INC_NOTE
1155 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1156 through memory plus an extra GR scratch register. Except that you can
1157 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1158 SECONDARY_RELOAD_CLASS, but not both.
1160 We got into problems in the first place by allowing a construct like
1161 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1162 This solution attempts to prevent this situation from occurring. When
1163 we see something like the above, we spill the inner register to memory. */
1166 spill_xfmode_operand (rtx in
, int force
)
1168 if (GET_CODE (in
) == SUBREG
1169 && GET_MODE (SUBREG_REG (in
)) == TImode
1170 && GET_CODE (SUBREG_REG (in
)) == REG
)
1172 rtx memt
= assign_stack_temp (TImode
, 16, 0);
1173 emit_move_insn (memt
, SUBREG_REG (in
));
1174 return adjust_address (memt
, XFmode
, 0);
1176 else if (force
&& GET_CODE (in
) == REG
)
1178 rtx memx
= assign_stack_temp (XFmode
, 16, 0);
1179 emit_move_insn (memx
, in
);
1186 /* Emit comparison instruction if necessary, returning the expression
1187 that holds the compare result in the proper mode. */
1189 static GTY(()) rtx cmptf_libfunc
;
1192 ia64_expand_compare (enum rtx_code code
, enum machine_mode mode
)
1194 rtx op0
= ia64_compare_op0
, op1
= ia64_compare_op1
;
1197 /* If we have a BImode input, then we already have a compare result, and
1198 do not need to emit another comparison. */
1199 if (GET_MODE (op0
) == BImode
)
1201 if ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1206 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1207 magic number as its third argument, that indicates what to do.
1208 The return value is an integer to be compared against zero. */
1209 else if (GET_MODE (op0
) == TFmode
)
1212 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1218 enum rtx_code ncode
;
1220 if (!cmptf_libfunc
|| GET_MODE (op1
) != TFmode
)
1224 /* 1 = equal, 0 = not equal. Equality operators do
1225 not raise FP_INVALID when given an SNaN operand. */
1226 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1227 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1228 /* isunordered() from C99. */
1229 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1230 case ORDERED
: magic
= QCMP_UNORD
; ncode
= EQ
; break;
1231 /* Relational operators raise FP_INVALID when given
1233 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1234 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1235 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1236 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1237 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1238 Expanders for buneq etc. weuld have to be added to ia64.md
1239 for this to be useful. */
1245 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1246 op0
, TFmode
, op1
, TFmode
,
1247 GEN_INT (magic
), DImode
);
1248 cmp
= gen_reg_rtx (BImode
);
1249 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1250 gen_rtx_fmt_ee (ncode
, BImode
,
1253 insns
= get_insns ();
1256 emit_libcall_block (insns
, cmp
, cmp
,
1257 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
));
1262 cmp
= gen_reg_rtx (BImode
);
1263 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1264 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
)));
1268 return gen_rtx_fmt_ee (code
, mode
, cmp
, const0_rtx
);
1271 /* Generate an integral vector comparison. */
1274 ia64_expand_vecint_compare (enum rtx_code code
, enum machine_mode mode
,
1275 rtx dest
, rtx op0
, rtx op1
)
1277 bool negate
= false;
1312 rtx w0h
, w0l
, w1h
, w1l
, ch
, cl
;
1313 enum machine_mode wmode
;
1314 rtx (*unpack_l
) (rtx
, rtx
, rtx
);
1315 rtx (*unpack_h
) (rtx
, rtx
, rtx
);
1316 rtx (*pack
) (rtx
, rtx
, rtx
);
1318 /* We don't have native unsigned comparisons, but we can generate
1319 them better than generic code can. */
1321 if (mode
== V2SImode
)
1323 else if (mode
== V8QImode
)
1326 pack
= gen_pack2_sss
;
1327 unpack_l
= gen_unpack1_l
;
1328 unpack_h
= gen_unpack1_h
;
1330 else if (mode
== V4HImode
)
1333 pack
= gen_pack4_sss
;
1334 unpack_l
= gen_unpack2_l
;
1335 unpack_h
= gen_unpack2_h
;
1340 /* Unpack into wider vectors, zero extending the elements. */
1342 w0l
= gen_reg_rtx (wmode
);
1343 w0h
= gen_reg_rtx (wmode
);
1344 w1l
= gen_reg_rtx (wmode
);
1345 w1h
= gen_reg_rtx (wmode
);
1346 emit_insn (unpack_l (gen_lowpart (mode
, w0l
), op0
, CONST0_RTX (mode
)));
1347 emit_insn (unpack_h (gen_lowpart (mode
, w0h
), op0
, CONST0_RTX (mode
)));
1348 emit_insn (unpack_l (gen_lowpart (mode
, w1l
), op1
, CONST0_RTX (mode
)));
1349 emit_insn (unpack_h (gen_lowpart (mode
, w1h
), op1
, CONST0_RTX (mode
)));
1351 /* Compare in the wider mode. */
1353 cl
= gen_reg_rtx (wmode
);
1354 ch
= gen_reg_rtx (wmode
);
1355 code
= signed_condition (code
);
1356 ia64_expand_vecint_compare (code
, wmode
, cl
, w0l
, w1l
);
1357 negate
= ia64_expand_vecint_compare (code
, wmode
, ch
, w0h
, w1h
);
1359 /* Repack into a single narrower vector. */
1361 emit_insn (pack (dest
, cl
, ch
));
1369 x
= gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
1370 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1376 ia64_expand_vcondu_v2si (enum rtx_code code
, rtx operands
[])
1378 rtx dl
, dh
, bl
, bh
, op1l
, op1h
, op2l
, op2h
, op4l
, op4h
, op5l
, op5h
, x
;
1380 /* In this case, we extract the two SImode quantities and generate
1381 normal comparisons for each of them. */
1383 op1l
= gen_lowpart (SImode
, operands
[1]);
1384 op2l
= gen_lowpart (SImode
, operands
[2]);
1385 op4l
= gen_lowpart (SImode
, operands
[4]);
1386 op5l
= gen_lowpart (SImode
, operands
[5]);
1388 op1h
= gen_reg_rtx (SImode
);
1389 op2h
= gen_reg_rtx (SImode
);
1390 op4h
= gen_reg_rtx (SImode
);
1391 op5h
= gen_reg_rtx (SImode
);
1393 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op1h
),
1394 gen_lowpart (DImode
, operands
[1]), GEN_INT (32)));
1395 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op2h
),
1396 gen_lowpart (DImode
, operands
[2]), GEN_INT (32)));
1397 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op4h
),
1398 gen_lowpart (DImode
, operands
[4]), GEN_INT (32)));
1399 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op5h
),
1400 gen_lowpart (DImode
, operands
[5]), GEN_INT (32)));
1402 bl
= gen_reg_rtx (BImode
);
1403 x
= gen_rtx_fmt_ee (code
, BImode
, op4l
, op5l
);
1404 emit_insn (gen_rtx_SET (VOIDmode
, bl
, x
));
1406 bh
= gen_reg_rtx (BImode
);
1407 x
= gen_rtx_fmt_ee (code
, BImode
, op4h
, op5h
);
1408 emit_insn (gen_rtx_SET (VOIDmode
, bh
, x
));
1410 /* With the results of the comparisons, emit conditional moves. */
1412 dl
= gen_reg_rtx (SImode
);
1413 x
= gen_rtx_IF_THEN_ELSE (SImode
, bl
, op1l
, op2l
);
1414 emit_insn (gen_rtx_SET (VOIDmode
, dl
, x
));
1416 dh
= gen_reg_rtx (SImode
);
1417 x
= gen_rtx_IF_THEN_ELSE (SImode
, bh
, op1h
, op2h
);
1418 emit_insn (gen_rtx_SET (VOIDmode
, dh
, x
));
1420 /* Merge the two partial results back into a vector. */
1422 x
= gen_rtx_VEC_CONCAT (V2SImode
, dl
, dh
);
1423 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1426 /* Emit an integral vector conditional move. */
1429 ia64_expand_vecint_cmov (rtx operands
[])
1431 enum machine_mode mode
= GET_MODE (operands
[0]);
1432 enum rtx_code code
= GET_CODE (operands
[3]);
1436 /* Since we don't have unsigned V2SImode comparisons, it's more efficient
1437 to special-case them entirely. */
1438 if (mode
== V2SImode
1439 && (code
== GTU
|| code
== GEU
|| code
== LEU
|| code
== LTU
))
1441 ia64_expand_vcondu_v2si (code
, operands
);
1445 cmp
= gen_reg_rtx (mode
);
1446 negate
= ia64_expand_vecint_compare (code
, mode
, cmp
,
1447 operands
[4], operands
[5]);
1449 ot
= operands
[1+negate
];
1450 of
= operands
[2-negate
];
1452 if (ot
== CONST0_RTX (mode
))
1454 if (of
== CONST0_RTX (mode
))
1456 emit_move_insn (operands
[0], ot
);
1460 x
= gen_rtx_NOT (mode
, cmp
);
1461 x
= gen_rtx_AND (mode
, x
, of
);
1462 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1464 else if (of
== CONST0_RTX (mode
))
1466 x
= gen_rtx_AND (mode
, cmp
, ot
);
1467 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1473 t
= gen_reg_rtx (mode
);
1474 x
= gen_rtx_AND (mode
, cmp
, operands
[1+negate
]);
1475 emit_insn (gen_rtx_SET (VOIDmode
, t
, x
));
1477 f
= gen_reg_rtx (mode
);
1478 x
= gen_rtx_NOT (mode
, cmp
);
1479 x
= gen_rtx_AND (mode
, x
, operands
[2-negate
]);
1480 emit_insn (gen_rtx_SET (VOIDmode
, f
, x
));
1482 x
= gen_rtx_IOR (mode
, t
, f
);
1483 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1487 /* Emit an integral vector min or max operation. Return true if all done. */
1490 ia64_expand_vecint_minmax (enum rtx_code code
, enum machine_mode mode
,
1495 /* These four combinations are supported directly. */
1496 if (mode
== V8QImode
&& (code
== UMIN
|| code
== UMAX
))
1498 if (mode
== V4HImode
&& (code
== SMIN
|| code
== SMAX
))
1501 /* Everything else implemented via vector comparisons. */
1502 xops
[0] = operands
[0];
1503 xops
[4] = xops
[1] = operands
[1];
1504 xops
[5] = xops
[2] = operands
[2];
1523 xops
[3] = gen_rtx_fmt_ee (code
, VOIDmode
, operands
[1], operands
[2]);
1525 ia64_expand_vecint_cmov (xops
);
1529 /* Emit the appropriate sequence for a call. */
1532 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
1537 addr
= XEXP (addr
, 0);
1538 addr
= convert_memory_address (DImode
, addr
);
1539 b0
= gen_rtx_REG (DImode
, R_BR (0));
1541 /* ??? Should do this for functions known to bind local too. */
1542 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
1545 insn
= gen_sibcall_nogp (addr
);
1547 insn
= gen_call_nogp (addr
, b0
);
1549 insn
= gen_call_value_nogp (retval
, addr
, b0
);
1550 insn
= emit_call_insn (insn
);
1555 insn
= gen_sibcall_gp (addr
);
1557 insn
= gen_call_gp (addr
, b0
);
1559 insn
= gen_call_value_gp (retval
, addr
, b0
);
1560 insn
= emit_call_insn (insn
);
1562 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
1566 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
1570 ia64_reload_gp (void)
1574 if (current_frame_info
.reg_save_gp
)
1575 tmp
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_gp
);
1578 HOST_WIDE_INT offset
;
1580 offset
= (current_frame_info
.spill_cfa_off
1581 + current_frame_info
.spill_size
);
1582 if (frame_pointer_needed
)
1584 tmp
= hard_frame_pointer_rtx
;
1589 tmp
= stack_pointer_rtx
;
1590 offset
= current_frame_info
.total_size
- offset
;
1593 if (CONST_OK_FOR_I (offset
))
1594 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1595 tmp
, GEN_INT (offset
)));
1598 emit_move_insn (pic_offset_table_rtx
, GEN_INT (offset
));
1599 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1600 pic_offset_table_rtx
, tmp
));
1603 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
1606 emit_move_insn (pic_offset_table_rtx
, tmp
);
1610 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
1611 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
1614 bool is_desc
= false;
1616 /* If we find we're calling through a register, then we're actually
1617 calling through a descriptor, so load up the values. */
1618 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
1623 /* ??? We are currently constrained to *not* use peep2, because
1624 we can legitimately change the global lifetime of the GP
1625 (in the form of killing where previously live). This is
1626 because a call through a descriptor doesn't use the previous
1627 value of the GP, while a direct call does, and we do not
1628 commit to either form until the split here.
1630 That said, this means that we lack precise life info for
1631 whether ADDR is dead after this call. This is not terribly
1632 important, since we can fix things up essentially for free
1633 with the POST_DEC below, but it's nice to not use it when we
1634 can immediately tell it's not necessary. */
1635 addr_dead_p
= ((noreturn_p
|| sibcall_p
1636 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
1638 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
1640 /* Load the code address into scratch_b. */
1641 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
1642 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1643 emit_move_insn (scratch_r
, tmp
);
1644 emit_move_insn (scratch_b
, scratch_r
);
1646 /* Load the GP address. If ADDR is not dead here, then we must
1647 revert the change made above via the POST_INCREMENT. */
1649 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
1652 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1653 emit_move_insn (pic_offset_table_rtx
, tmp
);
1660 insn
= gen_sibcall_nogp (addr
);
1662 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
1664 insn
= gen_call_nogp (addr
, retaddr
);
1665 emit_call_insn (insn
);
1667 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
1671 /* Begin the assembly file. */
1674 ia64_file_start (void)
1676 default_file_start ();
1677 emit_safe_across_calls ();
1681 emit_safe_across_calls (void)
1683 unsigned int rs
, re
;
1690 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
1694 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
1698 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
1702 fputc (',', asm_out_file
);
1704 fprintf (asm_out_file
, "p%u", rs
);
1706 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
1710 fputc ('\n', asm_out_file
);
1713 /* Helper function for ia64_compute_frame_size: find an appropriate general
1714 register to spill some special register to. SPECIAL_SPILL_MASK contains
1715 bits in GR0 to GR31 that have already been allocated by this routine.
1716 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1719 find_gr_spill (int try_locals
)
1723 /* If this is a leaf function, first try an otherwise unused
1724 call-clobbered register. */
1725 if (current_function_is_leaf
)
1727 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1728 if (! regs_ever_live
[regno
]
1729 && call_used_regs
[regno
]
1730 && ! fixed_regs
[regno
]
1731 && ! global_regs
[regno
]
1732 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1734 current_frame_info
.gr_used_mask
|= 1 << regno
;
1741 regno
= current_frame_info
.n_local_regs
;
1742 /* If there is a frame pointer, then we can't use loc79, because
1743 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1744 reg_name switching code in ia64_expand_prologue. */
1745 if (regno
< (80 - frame_pointer_needed
))
1747 current_frame_info
.n_local_regs
= regno
+ 1;
1748 return LOC_REG (0) + regno
;
1752 /* Failed to find a general register to spill to. Must use stack. */
1756 /* In order to make for nice schedules, we try to allocate every temporary
1757 to a different register. We must of course stay away from call-saved,
1758 fixed, and global registers. We must also stay away from registers
1759 allocated in current_frame_info.gr_used_mask, since those include regs
1760 used all through the prologue.
1762 Any register allocated here must be used immediately. The idea is to
1763 aid scheduling, not to solve data flow problems. */
1765 static int last_scratch_gr_reg
;
1768 next_scratch_gr_reg (void)
1772 for (i
= 0; i
< 32; ++i
)
1774 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
1775 if (call_used_regs
[regno
]
1776 && ! fixed_regs
[regno
]
1777 && ! global_regs
[regno
]
1778 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1780 last_scratch_gr_reg
= regno
;
1785 /* There must be _something_ available. */
1789 /* Helper function for ia64_compute_frame_size, called through
1790 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1793 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
1795 unsigned int regno
= REGNO (reg
);
1798 unsigned int i
, n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
1799 for (i
= 0; i
< n
; ++i
)
1800 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
1804 /* Returns the number of bytes offset between the frame pointer and the stack
1805 pointer for the current function. SIZE is the number of bytes of space
1806 needed for local variables. */
1809 ia64_compute_frame_size (HOST_WIDE_INT size
)
1811 HOST_WIDE_INT total_size
;
1812 HOST_WIDE_INT spill_size
= 0;
1813 HOST_WIDE_INT extra_spill_size
= 0;
1814 HOST_WIDE_INT pretend_args_size
;
1817 int spilled_gr_p
= 0;
1818 int spilled_fr_p
= 0;
1822 if (current_frame_info
.initialized
)
1825 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
1826 CLEAR_HARD_REG_SET (mask
);
1828 /* Don't allocate scratches to the return register. */
1829 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
1831 /* Don't allocate scratches to the EH scratch registers. */
1832 if (cfun
->machine
->ia64_eh_epilogue_sp
)
1833 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
1834 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
1835 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
1837 /* Find the size of the register stack frame. We have only 80 local
1838 registers, because we reserve 8 for the inputs and 8 for the
1841 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1842 since we'll be adjusting that down later. */
1843 regno
= LOC_REG (78) + ! frame_pointer_needed
;
1844 for (; regno
>= LOC_REG (0); regno
--)
1845 if (regs_ever_live
[regno
])
1847 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
1849 /* For functions marked with the syscall_linkage attribute, we must mark
1850 all eight input registers as in use, so that locals aren't visible to
1853 if (cfun
->machine
->n_varargs
> 0
1854 || lookup_attribute ("syscall_linkage",
1855 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
1856 current_frame_info
.n_input_regs
= 8;
1859 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
1860 if (regs_ever_live
[regno
])
1862 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
1865 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
1866 if (regs_ever_live
[regno
])
1868 i
= regno
- OUT_REG (0) + 1;
1870 /* When -p profiling, we need one output register for the mcount argument.
1871 Likewise for -a profiling for the bb_init_func argument. For -ax
1872 profiling, we need two output registers for the two bb_init_trace_func
1874 if (current_function_profile
)
1876 current_frame_info
.n_output_regs
= i
;
1878 /* ??? No rotating register support yet. */
1879 current_frame_info
.n_rotate_regs
= 0;
1881 /* Discover which registers need spilling, and how much room that
1882 will take. Begin with floating point and general registers,
1883 which will always wind up on the stack. */
1885 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
1886 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1888 SET_HARD_REG_BIT (mask
, regno
);
1894 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1895 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1897 SET_HARD_REG_BIT (mask
, regno
);
1903 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
1904 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1906 SET_HARD_REG_BIT (mask
, regno
);
1911 /* Now come all special registers that might get saved in other
1912 general registers. */
1914 if (frame_pointer_needed
)
1916 current_frame_info
.reg_fp
= find_gr_spill (1);
1917 /* If we did not get a register, then we take LOC79. This is guaranteed
1918 to be free, even if regs_ever_live is already set, because this is
1919 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
1920 as we don't count loc79 above. */
1921 if (current_frame_info
.reg_fp
== 0)
1923 current_frame_info
.reg_fp
= LOC_REG (79);
1924 current_frame_info
.n_local_regs
++;
1928 if (! current_function_is_leaf
)
1930 /* Emit a save of BR0 if we call other functions. Do this even
1931 if this function doesn't return, as EH depends on this to be
1932 able to unwind the stack. */
1933 SET_HARD_REG_BIT (mask
, BR_REG (0));
1935 current_frame_info
.reg_save_b0
= find_gr_spill (1);
1936 if (current_frame_info
.reg_save_b0
== 0)
1942 /* Similarly for ar.pfs. */
1943 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
1944 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
1945 if (current_frame_info
.reg_save_ar_pfs
== 0)
1947 extra_spill_size
+= 8;
1951 /* Similarly for gp. Note that if we're calling setjmp, the stacked
1952 registers are clobbered, so we fall back to the stack. */
1953 current_frame_info
.reg_save_gp
1954 = (current_function_calls_setjmp
? 0 : find_gr_spill (1));
1955 if (current_frame_info
.reg_save_gp
== 0)
1957 SET_HARD_REG_BIT (mask
, GR_REG (1));
1964 if (regs_ever_live
[BR_REG (0)] && ! call_used_regs
[BR_REG (0)])
1966 SET_HARD_REG_BIT (mask
, BR_REG (0));
1971 if (regs_ever_live
[AR_PFS_REGNUM
])
1973 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
1974 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
1975 if (current_frame_info
.reg_save_ar_pfs
== 0)
1977 extra_spill_size
+= 8;
1983 /* Unwind descriptor hackery: things are most efficient if we allocate
1984 consecutive GR save registers for RP, PFS, FP in that order. However,
1985 it is absolutely critical that FP get the only hard register that's
1986 guaranteed to be free, so we allocated it first. If all three did
1987 happen to be allocated hard regs, and are consecutive, rearrange them
1988 into the preferred order now. */
1989 if (current_frame_info
.reg_fp
!= 0
1990 && current_frame_info
.reg_save_b0
== current_frame_info
.reg_fp
+ 1
1991 && current_frame_info
.reg_save_ar_pfs
== current_frame_info
.reg_fp
+ 2)
1993 current_frame_info
.reg_save_b0
= current_frame_info
.reg_fp
;
1994 current_frame_info
.reg_save_ar_pfs
= current_frame_info
.reg_fp
+ 1;
1995 current_frame_info
.reg_fp
= current_frame_info
.reg_fp
+ 2;
1998 /* See if we need to store the predicate register block. */
1999 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2000 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2002 if (regno
<= PR_REG (63))
2004 SET_HARD_REG_BIT (mask
, PR_REG (0));
2005 current_frame_info
.reg_save_pr
= find_gr_spill (1);
2006 if (current_frame_info
.reg_save_pr
== 0)
2008 extra_spill_size
+= 8;
2012 /* ??? Mark them all as used so that register renaming and such
2013 are free to use them. */
2014 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2015 regs_ever_live
[regno
] = 1;
2018 /* If we're forced to use st8.spill, we're forced to save and restore
2019 ar.unat as well. The check for existing liveness allows inline asm
2020 to touch ar.unat. */
2021 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2022 || regs_ever_live
[AR_UNAT_REGNUM
])
2024 regs_ever_live
[AR_UNAT_REGNUM
] = 1;
2025 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2026 current_frame_info
.reg_save_ar_unat
= find_gr_spill (spill_size
== 0);
2027 if (current_frame_info
.reg_save_ar_unat
== 0)
2029 extra_spill_size
+= 8;
2034 if (regs_ever_live
[AR_LC_REGNUM
])
2036 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2037 current_frame_info
.reg_save_ar_lc
= find_gr_spill (spill_size
== 0);
2038 if (current_frame_info
.reg_save_ar_lc
== 0)
2040 extra_spill_size
+= 8;
2045 /* If we have an odd number of words of pretend arguments written to
2046 the stack, then the FR save area will be unaligned. We round the
2047 size of this area up to keep things 16 byte aligned. */
2049 pretend_args_size
= IA64_STACK_ALIGN (current_function_pretend_args_size
);
2051 pretend_args_size
= current_function_pretend_args_size
;
2053 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2054 + current_function_outgoing_args_size
);
2055 total_size
= IA64_STACK_ALIGN (total_size
);
2057 /* We always use the 16-byte scratch area provided by the caller, but
2058 if we are a leaf function, there's no one to which we need to provide
2060 if (current_function_is_leaf
)
2061 total_size
= MAX (0, total_size
- 16);
2063 current_frame_info
.total_size
= total_size
;
2064 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2065 current_frame_info
.spill_size
= spill_size
;
2066 current_frame_info
.extra_spill_size
= extra_spill_size
;
2067 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2068 current_frame_info
.n_spilled
= n_spilled
;
2069 current_frame_info
.initialized
= reload_completed
;
2072 /* Compute the initial difference between the specified pair of registers. */
2075 ia64_initial_elimination_offset (int from
, int to
)
2077 HOST_WIDE_INT offset
;
2079 ia64_compute_frame_size (get_frame_size ());
2082 case FRAME_POINTER_REGNUM
:
2083 if (to
== HARD_FRAME_POINTER_REGNUM
)
2085 if (current_function_is_leaf
)
2086 offset
= -current_frame_info
.total_size
;
2088 offset
= -(current_frame_info
.total_size
2089 - current_function_outgoing_args_size
- 16);
2091 else if (to
== STACK_POINTER_REGNUM
)
2093 if (current_function_is_leaf
)
2096 offset
= 16 + current_function_outgoing_args_size
;
2102 case ARG_POINTER_REGNUM
:
2103 /* Arguments start above the 16 byte save area, unless stdarg
2104 in which case we store through the 16 byte save area. */
2105 if (to
== HARD_FRAME_POINTER_REGNUM
)
2106 offset
= 16 - current_function_pretend_args_size
;
2107 else if (to
== STACK_POINTER_REGNUM
)
2108 offset
= (current_frame_info
.total_size
2109 + 16 - current_function_pretend_args_size
);
2121 /* If there are more than a trivial number of register spills, we use
2122 two interleaved iterators so that we can get two memory references
2125 In order to simplify things in the prologue and epilogue expanders,
2126 we use helper functions to fix up the memory references after the
2127 fact with the appropriate offsets to a POST_MODIFY memory mode.
2128 The following data structure tracks the state of the two iterators
2129 while insns are being emitted. */
2131 struct spill_fill_data
2133 rtx init_after
; /* point at which to emit initializations */
2134 rtx init_reg
[2]; /* initial base register */
2135 rtx iter_reg
[2]; /* the iterator registers */
2136 rtx
*prev_addr
[2]; /* address of last memory use */
2137 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2138 HOST_WIDE_INT prev_off
[2]; /* last offset */
2139 int n_iter
; /* number of iterators in use */
2140 int next_iter
; /* next iterator to use */
2141 unsigned int save_gr_used_mask
;
2144 static struct spill_fill_data spill_fill_data
;
2147 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2151 spill_fill_data
.init_after
= get_last_insn ();
2152 spill_fill_data
.init_reg
[0] = init_reg
;
2153 spill_fill_data
.init_reg
[1] = init_reg
;
2154 spill_fill_data
.prev_addr
[0] = NULL
;
2155 spill_fill_data
.prev_addr
[1] = NULL
;
2156 spill_fill_data
.prev_insn
[0] = NULL
;
2157 spill_fill_data
.prev_insn
[1] = NULL
;
2158 spill_fill_data
.prev_off
[0] = cfa_off
;
2159 spill_fill_data
.prev_off
[1] = cfa_off
;
2160 spill_fill_data
.next_iter
= 0;
2161 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2163 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2164 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2166 int regno
= next_scratch_gr_reg ();
2167 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2168 current_frame_info
.gr_used_mask
|= 1 << regno
;
2173 finish_spill_pointers (void)
2175 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2179 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
2181 int iter
= spill_fill_data
.next_iter
;
2182 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2183 rtx disp_rtx
= GEN_INT (disp
);
2186 if (spill_fill_data
.prev_addr
[iter
])
2188 if (CONST_OK_FOR_N (disp
))
2190 *spill_fill_data
.prev_addr
[iter
]
2191 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2192 gen_rtx_PLUS (DImode
,
2193 spill_fill_data
.iter_reg
[iter
],
2195 REG_NOTES (spill_fill_data
.prev_insn
[iter
])
2196 = gen_rtx_EXPR_LIST (REG_INC
, spill_fill_data
.iter_reg
[iter
],
2197 REG_NOTES (spill_fill_data
.prev_insn
[iter
]));
2201 /* ??? Could use register post_modify for loads. */
2202 if (! CONST_OK_FOR_I (disp
))
2204 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2205 emit_move_insn (tmp
, disp_rtx
);
2208 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2209 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2212 /* Micro-optimization: if we've created a frame pointer, it's at
2213 CFA 0, which may allow the real iterator to be initialized lower,
2214 slightly increasing parallelism. Also, if there are few saves
2215 it may eliminate the iterator entirely. */
2217 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2218 && frame_pointer_needed
)
2220 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2221 set_mem_alias_set (mem
, get_varargs_alias_set ());
2229 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2230 spill_fill_data
.init_reg
[iter
]);
2235 if (! CONST_OK_FOR_I (disp
))
2237 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2238 emit_move_insn (tmp
, disp_rtx
);
2242 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2243 spill_fill_data
.init_reg
[iter
],
2250 /* Careful for being the first insn in a sequence. */
2251 if (spill_fill_data
.init_after
)
2252 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2255 rtx first
= get_insns ();
2257 insn
= emit_insn_before (seq
, first
);
2259 insn
= emit_insn (seq
);
2261 spill_fill_data
.init_after
= insn
;
2263 /* If DISP is 0, we may or may not have a further adjustment
2264 afterward. If we do, then the load/store insn may be modified
2265 to be a post-modify. If we don't, then this copy may be
2266 eliminated by copyprop_hardreg_forward, which makes this
2267 insn garbage, which runs afoul of the sanity check in
2268 propagate_one_insn. So mark this insn as legal to delete. */
2270 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
2274 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
2276 /* ??? Not all of the spills are for varargs, but some of them are.
2277 The rest of the spills belong in an alias set of their own. But
2278 it doesn't actually hurt to include them here. */
2279 set_mem_alias_set (mem
, get_varargs_alias_set ());
2281 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
2282 spill_fill_data
.prev_off
[iter
] = cfa_off
;
2284 if (++iter
>= spill_fill_data
.n_iter
)
2286 spill_fill_data
.next_iter
= iter
;
2292 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
2295 int iter
= spill_fill_data
.next_iter
;
2298 mem
= spill_restore_mem (reg
, cfa_off
);
2299 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
2300 spill_fill_data
.prev_insn
[iter
] = insn
;
2307 RTX_FRAME_RELATED_P (insn
) = 1;
2309 /* Don't even pretend that the unwind code can intuit its way
2310 through a pair of interleaved post_modify iterators. Just
2311 provide the correct answer. */
2313 if (frame_pointer_needed
)
2315 base
= hard_frame_pointer_rtx
;
2320 base
= stack_pointer_rtx
;
2321 off
= current_frame_info
.total_size
- cfa_off
;
2325 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2326 gen_rtx_SET (VOIDmode
,
2327 gen_rtx_MEM (GET_MODE (reg
),
2328 plus_constant (base
, off
)),
2335 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
2337 int iter
= spill_fill_data
.next_iter
;
2340 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
2341 GEN_INT (cfa_off
)));
2342 spill_fill_data
.prev_insn
[iter
] = insn
;
2345 /* Wrapper functions that discards the CONST_INT spill offset. These
2346 exist so that we can give gr_spill/gr_fill the offset they need and
2347 use a consistent function interface. */
2350 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2352 return gen_movdi (dest
, src
);
2356 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2358 return gen_fr_spill (dest
, src
);
2362 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2364 return gen_fr_restore (dest
, src
);
2367 /* Called after register allocation to add any instructions needed for the
2368 prologue. Using a prologue insn is favored compared to putting all of the
2369 instructions in output_function_prologue(), since it allows the scheduler
2370 to intermix instructions with the saves of the caller saved registers. In
2371 some cases, it might be necessary to emit a barrier instruction as the last
2372 insn to prevent such scheduling.
2374 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2375 so that the debug info generation code can handle them properly.
2377 The register save area is layed out like so:
2379 [ varargs spill area ]
2380 [ fr register spill area ]
2381 [ br register spill area ]
2382 [ ar register spill area ]
2383 [ pr register spill area ]
2384 [ gr register spill area ] */
2386 /* ??? Get inefficient code when the frame size is larger than can fit in an
2387 adds instruction. */
2390 ia64_expand_prologue (void)
2392 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
2393 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
2396 ia64_compute_frame_size (get_frame_size ());
2397 last_scratch_gr_reg
= 15;
2399 /* If there is no epilogue, then we don't need some prologue insns.
2400 We need to avoid emitting the dead prologue insns, because flow
2401 will complain about them. */
2407 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
2408 if ((e
->flags
& EDGE_FAKE
) == 0
2409 && (e
->flags
& EDGE_FALLTHRU
) != 0)
2411 epilogue_p
= (e
!= NULL
);
2416 /* Set the local, input, and output register names. We need to do this
2417 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2418 half. If we use in/loc/out register names, then we get assembler errors
2419 in crtn.S because there is no alloc insn or regstk directive in there. */
2420 if (! TARGET_REG_NAMES
)
2422 int inputs
= current_frame_info
.n_input_regs
;
2423 int locals
= current_frame_info
.n_local_regs
;
2424 int outputs
= current_frame_info
.n_output_regs
;
2426 for (i
= 0; i
< inputs
; i
++)
2427 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
2428 for (i
= 0; i
< locals
; i
++)
2429 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
2430 for (i
= 0; i
< outputs
; i
++)
2431 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
2434 /* Set the frame pointer register name. The regnum is logically loc79,
2435 but of course we'll not have allocated that many locals. Rather than
2436 worrying about renumbering the existing rtxs, we adjust the name. */
2437 /* ??? This code means that we can never use one local register when
2438 there is a frame pointer. loc79 gets wasted in this case, as it is
2439 renamed to a register that will never be used. See also the try_locals
2440 code in find_gr_spill. */
2441 if (current_frame_info
.reg_fp
)
2443 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
2444 reg_names
[HARD_FRAME_POINTER_REGNUM
]
2445 = reg_names
[current_frame_info
.reg_fp
];
2446 reg_names
[current_frame_info
.reg_fp
] = tmp
;
2449 /* We don't need an alloc instruction if we've used no outputs or locals. */
2450 if (current_frame_info
.n_local_regs
== 0
2451 && current_frame_info
.n_output_regs
== 0
2452 && current_frame_info
.n_input_regs
<= current_function_args_info
.int_regs
2453 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2455 /* If there is no alloc, but there are input registers used, then we
2456 need a .regstk directive. */
2457 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
2458 ar_pfs_save_reg
= NULL_RTX
;
2462 current_frame_info
.need_regstk
= 0;
2464 if (current_frame_info
.reg_save_ar_pfs
)
2465 regno
= current_frame_info
.reg_save_ar_pfs
;
2467 regno
= next_scratch_gr_reg ();
2468 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
2470 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
2471 GEN_INT (current_frame_info
.n_input_regs
),
2472 GEN_INT (current_frame_info
.n_local_regs
),
2473 GEN_INT (current_frame_info
.n_output_regs
),
2474 GEN_INT (current_frame_info
.n_rotate_regs
)));
2475 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_pfs
!= 0);
2478 /* Set up frame pointer, stack pointer, and spill iterators. */
2480 n_varargs
= cfun
->machine
->n_varargs
;
2481 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
2482 stack_pointer_rtx
, 0);
2484 if (frame_pointer_needed
)
2486 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2487 RTX_FRAME_RELATED_P (insn
) = 1;
2490 if (current_frame_info
.total_size
!= 0)
2492 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
2495 if (CONST_OK_FOR_I (- current_frame_info
.total_size
))
2496 offset
= frame_size_rtx
;
2499 regno
= next_scratch_gr_reg ();
2500 offset
= gen_rtx_REG (DImode
, regno
);
2501 emit_move_insn (offset
, frame_size_rtx
);
2504 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
2505 stack_pointer_rtx
, offset
));
2507 if (! frame_pointer_needed
)
2509 RTX_FRAME_RELATED_P (insn
) = 1;
2510 if (GET_CODE (offset
) != CONST_INT
)
2513 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2514 gen_rtx_SET (VOIDmode
,
2516 gen_rtx_PLUS (DImode
,
2523 /* ??? At this point we must generate a magic insn that appears to
2524 modify the stack pointer, the frame pointer, and all spill
2525 iterators. This would allow the most scheduling freedom. For
2526 now, just hard stop. */
2527 emit_insn (gen_blockage ());
2530 /* Must copy out ar.unat before doing any integer spills. */
2531 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2533 if (current_frame_info
.reg_save_ar_unat
)
2535 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2538 alt_regno
= next_scratch_gr_reg ();
2539 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2540 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2543 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2544 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
2545 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_unat
!= 0);
2547 /* Even if we're not going to generate an epilogue, we still
2548 need to save the register so that EH works. */
2549 if (! epilogue_p
&& current_frame_info
.reg_save_ar_unat
)
2550 emit_insn (gen_prologue_use (ar_unat_save_reg
));
2553 ar_unat_save_reg
= NULL_RTX
;
2555 /* Spill all varargs registers. Do this before spilling any GR registers,
2556 since we want the UNAT bits for the GR registers to override the UNAT
2557 bits from varargs, which we don't care about. */
2560 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
2562 reg
= gen_rtx_REG (DImode
, regno
);
2563 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
2566 /* Locate the bottom of the register save area. */
2567 cfa_off
= (current_frame_info
.spill_cfa_off
2568 + current_frame_info
.spill_size
2569 + current_frame_info
.extra_spill_size
);
2571 /* Save the predicate register block either in a register or in memory. */
2572 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2574 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2575 if (current_frame_info
.reg_save_pr
!= 0)
2577 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2578 insn
= emit_move_insn (alt_reg
, reg
);
2580 /* ??? Denote pr spill/fill by a DImode move that modifies all
2581 64 hard registers. */
2582 RTX_FRAME_RELATED_P (insn
) = 1;
2584 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2585 gen_rtx_SET (VOIDmode
, alt_reg
, reg
),
2588 /* Even if we're not going to generate an epilogue, we still
2589 need to save the register so that EH works. */
2591 emit_insn (gen_prologue_use (alt_reg
));
2595 alt_regno
= next_scratch_gr_reg ();
2596 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2597 insn
= emit_move_insn (alt_reg
, reg
);
2598 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2603 /* Handle AR regs in numerical order. All of them get special handling. */
2604 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
2605 && current_frame_info
.reg_save_ar_unat
== 0)
2607 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2608 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
2612 /* The alloc insn already copied ar.pfs into a general register. The
2613 only thing we have to do now is copy that register to a stack slot
2614 if we'd not allocated a local register for the job. */
2615 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
2616 && current_frame_info
.reg_save_ar_pfs
== 0)
2618 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2619 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
2623 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2625 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2626 if (current_frame_info
.reg_save_ar_lc
!= 0)
2628 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2629 insn
= emit_move_insn (alt_reg
, reg
);
2630 RTX_FRAME_RELATED_P (insn
) = 1;
2632 /* Even if we're not going to generate an epilogue, we still
2633 need to save the register so that EH works. */
2635 emit_insn (gen_prologue_use (alt_reg
));
2639 alt_regno
= next_scratch_gr_reg ();
2640 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2641 emit_move_insn (alt_reg
, reg
);
2642 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2647 if (current_frame_info
.reg_save_gp
)
2649 insn
= emit_move_insn (gen_rtx_REG (DImode
,
2650 current_frame_info
.reg_save_gp
),
2651 pic_offset_table_rtx
);
2652 /* We don't know for sure yet if this is actually needed, since
2653 we've not split the PIC call patterns. If all of the calls
2654 are indirect, and not followed by any uses of the gp, then
2655 this save is dead. Allow it to go away. */
2657 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, REG_NOTES (insn
));
2660 /* We should now be at the base of the gr/br/fr spill area. */
2661 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2662 + current_frame_info
.spill_size
))
2665 /* Spill all general registers. */
2666 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
2667 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2669 reg
= gen_rtx_REG (DImode
, regno
);
2670 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
2674 /* Handle BR0 specially -- it may be getting stored permanently in
2675 some GR register. */
2676 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2678 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2679 if (current_frame_info
.reg_save_b0
!= 0)
2681 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2682 insn
= emit_move_insn (alt_reg
, reg
);
2683 RTX_FRAME_RELATED_P (insn
) = 1;
2685 /* Even if we're not going to generate an epilogue, we still
2686 need to save the register so that EH works. */
2688 emit_insn (gen_prologue_use (alt_reg
));
2692 alt_regno
= next_scratch_gr_reg ();
2693 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2694 emit_move_insn (alt_reg
, reg
);
2695 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2700 /* Spill the rest of the BR registers. */
2701 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2702 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2704 alt_regno
= next_scratch_gr_reg ();
2705 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2706 reg
= gen_rtx_REG (DImode
, regno
);
2707 emit_move_insn (alt_reg
, reg
);
2708 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2712 /* Align the frame and spill all FR registers. */
2713 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2714 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2718 reg
= gen_rtx_REG (XFmode
, regno
);
2719 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
2723 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2726 finish_spill_pointers ();
2729 /* Called after register allocation to add any instructions needed for the
2730 epilogue. Using an epilogue insn is favored compared to putting all of the
2731 instructions in output_function_prologue(), since it allows the scheduler
2732 to intermix instructions with the saves of the caller saved registers. In
2733 some cases, it might be necessary to emit a barrier instruction as the last
2734 insn to prevent such scheduling. */
2737 ia64_expand_epilogue (int sibcall_p
)
2739 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
2740 int regno
, alt_regno
, cfa_off
;
2742 ia64_compute_frame_size (get_frame_size ());
2744 /* If there is a frame pointer, then we use it instead of the stack
2745 pointer, so that the stack pointer does not need to be valid when
2746 the epilogue starts. See EXIT_IGNORE_STACK. */
2747 if (frame_pointer_needed
)
2748 setup_spill_pointers (current_frame_info
.n_spilled
,
2749 hard_frame_pointer_rtx
, 0);
2751 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
2752 current_frame_info
.total_size
);
2754 if (current_frame_info
.total_size
!= 0)
2756 /* ??? At this point we must generate a magic insn that appears to
2757 modify the spill iterators and the frame pointer. This would
2758 allow the most scheduling freedom. For now, just hard stop. */
2759 emit_insn (gen_blockage ());
2762 /* Locate the bottom of the register save area. */
2763 cfa_off
= (current_frame_info
.spill_cfa_off
2764 + current_frame_info
.spill_size
2765 + current_frame_info
.extra_spill_size
);
2767 /* Restore the predicate registers. */
2768 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2770 if (current_frame_info
.reg_save_pr
!= 0)
2771 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2774 alt_regno
= next_scratch_gr_reg ();
2775 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2776 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2779 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2780 emit_move_insn (reg
, alt_reg
);
2783 /* Restore the application registers. */
2785 /* Load the saved unat from the stack, but do not restore it until
2786 after the GRs have been restored. */
2787 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2789 if (current_frame_info
.reg_save_ar_unat
!= 0)
2791 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2794 alt_regno
= next_scratch_gr_reg ();
2795 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2796 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2797 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
2802 ar_unat_save_reg
= NULL_RTX
;
2804 if (current_frame_info
.reg_save_ar_pfs
!= 0)
2806 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_pfs
);
2807 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2808 emit_move_insn (reg
, alt_reg
);
2810 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2812 alt_regno
= next_scratch_gr_reg ();
2813 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2814 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2816 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2817 emit_move_insn (reg
, alt_reg
);
2820 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2822 if (current_frame_info
.reg_save_ar_lc
!= 0)
2823 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2826 alt_regno
= next_scratch_gr_reg ();
2827 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2828 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2831 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2832 emit_move_insn (reg
, alt_reg
);
2835 /* We should now be at the base of the gr/br/fr spill area. */
2836 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2837 + current_frame_info
.spill_size
))
2840 /* The GP may be stored on the stack in the prologue, but it's
2841 never restored in the epilogue. Skip the stack slot. */
2842 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
2845 /* Restore all general registers. */
2846 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
2847 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2849 reg
= gen_rtx_REG (DImode
, regno
);
2850 do_restore (gen_gr_restore
, reg
, cfa_off
);
2854 /* Restore the branch registers. Handle B0 specially, as it may
2855 have gotten stored in some GR register. */
2856 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2858 if (current_frame_info
.reg_save_b0
!= 0)
2859 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2862 alt_regno
= next_scratch_gr_reg ();
2863 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2864 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2867 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2868 emit_move_insn (reg
, alt_reg
);
2871 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2872 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2874 alt_regno
= next_scratch_gr_reg ();
2875 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2876 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2878 reg
= gen_rtx_REG (DImode
, regno
);
2879 emit_move_insn (reg
, alt_reg
);
2882 /* Restore floating point registers. */
2883 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2884 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2888 reg
= gen_rtx_REG (XFmode
, regno
);
2889 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
2893 /* Restore ar.unat for real. */
2894 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2896 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2897 emit_move_insn (reg
, ar_unat_save_reg
);
2900 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2903 finish_spill_pointers ();
2905 if (current_frame_info
.total_size
|| cfun
->machine
->ia64_eh_epilogue_sp
)
2907 /* ??? At this point we must generate a magic insn that appears to
2908 modify the spill iterators, the stack pointer, and the frame
2909 pointer. This would allow the most scheduling freedom. For now,
2911 emit_insn (gen_blockage ());
2914 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2915 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
2916 else if (frame_pointer_needed
)
2918 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
2919 RTX_FRAME_RELATED_P (insn
) = 1;
2921 else if (current_frame_info
.total_size
)
2923 rtx offset
, frame_size_rtx
;
2925 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
2926 if (CONST_OK_FOR_I (current_frame_info
.total_size
))
2927 offset
= frame_size_rtx
;
2930 regno
= next_scratch_gr_reg ();
2931 offset
= gen_rtx_REG (DImode
, regno
);
2932 emit_move_insn (offset
, frame_size_rtx
);
2935 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2938 RTX_FRAME_RELATED_P (insn
) = 1;
2939 if (GET_CODE (offset
) != CONST_INT
)
2942 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2943 gen_rtx_SET (VOIDmode
,
2945 gen_rtx_PLUS (DImode
,
2952 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2953 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
2956 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
2959 int fp
= GR_REG (2);
2960 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
2961 first available call clobbered register. If there was a frame_pointer
2962 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
2963 so we have to make sure we're using the string "r2" when emitting
2964 the register name for the assembler. */
2965 if (current_frame_info
.reg_fp
&& current_frame_info
.reg_fp
== GR_REG (2))
2966 fp
= HARD_FRAME_POINTER_REGNUM
;
2968 /* We must emit an alloc to force the input registers to become output
2969 registers. Otherwise, if the callee tries to pass its parameters
2970 through to another call without an intervening alloc, then these
2972 /* ??? We don't need to preserve all input registers. We only need to
2973 preserve those input registers used as arguments to the sibling call.
2974 It is unclear how to compute that number here. */
2975 if (current_frame_info
.n_input_regs
!= 0)
2977 rtx n_inputs
= GEN_INT (current_frame_info
.n_input_regs
);
2978 insn
= emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
2979 const0_rtx
, const0_rtx
,
2980 n_inputs
, const0_rtx
));
2981 RTX_FRAME_RELATED_P (insn
) = 1;
2986 /* Return 1 if br.ret can do all the work required to return from a
2990 ia64_direct_return (void)
2992 if (reload_completed
&& ! frame_pointer_needed
)
2994 ia64_compute_frame_size (get_frame_size ());
2996 return (current_frame_info
.total_size
== 0
2997 && current_frame_info
.n_spilled
== 0
2998 && current_frame_info
.reg_save_b0
== 0
2999 && current_frame_info
.reg_save_pr
== 0
3000 && current_frame_info
.reg_save_ar_pfs
== 0
3001 && current_frame_info
.reg_save_ar_unat
== 0
3002 && current_frame_info
.reg_save_ar_lc
== 0);
3007 /* Return the magic cookie that we use to hold the return address
3008 during early compilation. */
3011 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
3015 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
3018 /* Split this value after reload, now that we know where the return
3019 address is saved. */
3022 ia64_split_return_addr_rtx (rtx dest
)
3026 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3028 if (current_frame_info
.reg_save_b0
!= 0)
3029 src
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3035 /* Compute offset from CFA for BR0. */
3036 /* ??? Must be kept in sync with ia64_expand_prologue. */
3037 off
= (current_frame_info
.spill_cfa_off
3038 + current_frame_info
.spill_size
);
3039 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3040 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3043 /* Convert CFA offset to a register based offset. */
3044 if (frame_pointer_needed
)
3045 src
= hard_frame_pointer_rtx
;
3048 src
= stack_pointer_rtx
;
3049 off
+= current_frame_info
.total_size
;
3052 /* Load address into scratch register. */
3053 if (CONST_OK_FOR_I (off
))
3054 emit_insn (gen_adddi3 (dest
, src
, GEN_INT (off
)));
3057 emit_move_insn (dest
, GEN_INT (off
));
3058 emit_insn (gen_adddi3 (dest
, src
, dest
));
3061 src
= gen_rtx_MEM (Pmode
, dest
);
3065 src
= gen_rtx_REG (DImode
, BR_REG (0));
3067 emit_move_insn (dest
, src
);
3071 ia64_hard_regno_rename_ok (int from
, int to
)
3073 /* Don't clobber any of the registers we reserved for the prologue. */
3074 if (to
== current_frame_info
.reg_fp
3075 || to
== current_frame_info
.reg_save_b0
3076 || to
== current_frame_info
.reg_save_pr
3077 || to
== current_frame_info
.reg_save_ar_pfs
3078 || to
== current_frame_info
.reg_save_ar_unat
3079 || to
== current_frame_info
.reg_save_ar_lc
)
3082 if (from
== current_frame_info
.reg_fp
3083 || from
== current_frame_info
.reg_save_b0
3084 || from
== current_frame_info
.reg_save_pr
3085 || from
== current_frame_info
.reg_save_ar_pfs
3086 || from
== current_frame_info
.reg_save_ar_unat
3087 || from
== current_frame_info
.reg_save_ar_lc
)
3090 /* Don't use output registers outside the register frame. */
3091 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
3094 /* Retain even/oddness on predicate register pairs. */
3095 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
3096 return (from
& 1) == (to
& 1);
3101 /* Target hook for assembling integer objects. Handle word-sized
3102 aligned objects and detect the cases when @fptr is needed. */
3105 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3107 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
3108 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3109 && GET_CODE (x
) == SYMBOL_REF
3110 && SYMBOL_REF_FUNCTION_P (x
))
3112 static const char * const directive
[2][2] = {
3113 /* 64-bit pointer */ /* 32-bit pointer */
3114 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3115 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3117 fputs (directive
[(aligned_p
!= 0)][POINTER_SIZE
== 32], asm_out_file
);
3118 output_addr_const (asm_out_file
, x
);
3119 fputs (")\n", asm_out_file
);
3122 return default_assemble_integer (x
, size
, aligned_p
);
3125 /* Emit the function prologue. */
3128 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3130 int mask
, grsave
, grsave_prev
;
3132 if (current_frame_info
.need_regstk
)
3133 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3134 current_frame_info
.n_input_regs
,
3135 current_frame_info
.n_local_regs
,
3136 current_frame_info
.n_output_regs
,
3137 current_frame_info
.n_rotate_regs
);
3139 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3142 /* Emit the .prologue directive. */
3145 grsave
= grsave_prev
= 0;
3146 if (current_frame_info
.reg_save_b0
!= 0)
3149 grsave
= grsave_prev
= current_frame_info
.reg_save_b0
;
3151 if (current_frame_info
.reg_save_ar_pfs
!= 0
3152 && (grsave_prev
== 0
3153 || current_frame_info
.reg_save_ar_pfs
== grsave_prev
+ 1))
3156 if (grsave_prev
== 0)
3157 grsave
= current_frame_info
.reg_save_ar_pfs
;
3158 grsave_prev
= current_frame_info
.reg_save_ar_pfs
;
3160 if (current_frame_info
.reg_fp
!= 0
3161 && (grsave_prev
== 0
3162 || current_frame_info
.reg_fp
== grsave_prev
+ 1))
3165 if (grsave_prev
== 0)
3166 grsave
= HARD_FRAME_POINTER_REGNUM
;
3167 grsave_prev
= current_frame_info
.reg_fp
;
3169 if (current_frame_info
.reg_save_pr
!= 0
3170 && (grsave_prev
== 0
3171 || current_frame_info
.reg_save_pr
== grsave_prev
+ 1))
3174 if (grsave_prev
== 0)
3175 grsave
= current_frame_info
.reg_save_pr
;
3178 if (mask
&& TARGET_GNU_AS
)
3179 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3180 ia64_dbx_register_number (grsave
));
3182 fputs ("\t.prologue\n", file
);
3184 /* Emit a .spill directive, if necessary, to relocate the base of
3185 the register spill area. */
3186 if (current_frame_info
.spill_cfa_off
!= -16)
3187 fprintf (file
, "\t.spill %ld\n",
3188 (long) (current_frame_info
.spill_cfa_off
3189 + current_frame_info
.spill_size
));
3192 /* Emit the .body directive at the scheduled end of the prologue. */
3195 ia64_output_function_end_prologue (FILE *file
)
3197 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3200 fputs ("\t.body\n", file
);
3203 /* Emit the function epilogue. */
3206 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
3207 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3211 if (current_frame_info
.reg_fp
)
3213 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3214 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3215 = reg_names
[current_frame_info
.reg_fp
];
3216 reg_names
[current_frame_info
.reg_fp
] = tmp
;
3218 if (! TARGET_REG_NAMES
)
3220 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
3221 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
3222 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
3223 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
3224 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
3225 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
3228 current_frame_info
.initialized
= 0;
3232 ia64_dbx_register_number (int regno
)
3234 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3235 from its home at loc79 to something inside the register frame. We
3236 must perform the same renumbering here for the debug info. */
3237 if (current_frame_info
.reg_fp
)
3239 if (regno
== HARD_FRAME_POINTER_REGNUM
)
3240 regno
= current_frame_info
.reg_fp
;
3241 else if (regno
== current_frame_info
.reg_fp
)
3242 regno
= HARD_FRAME_POINTER_REGNUM
;
3245 if (IN_REGNO_P (regno
))
3246 return 32 + regno
- IN_REG (0);
3247 else if (LOC_REGNO_P (regno
))
3248 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
3249 else if (OUT_REGNO_P (regno
))
3250 return (32 + current_frame_info
.n_input_regs
3251 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
3257 ia64_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
3259 rtx addr_reg
, eight
= GEN_INT (8);
3261 /* The Intel assembler requires that the global __ia64_trampoline symbol
3262 be declared explicitly */
3265 static bool declared_ia64_trampoline
= false;
3267 if (!declared_ia64_trampoline
)
3269 declared_ia64_trampoline
= true;
3270 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
3271 "__ia64_trampoline");
3275 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3276 addr
= convert_memory_address (Pmode
, addr
);
3277 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
3278 static_chain
= convert_memory_address (Pmode
, static_chain
);
3280 /* Load up our iterator. */
3281 addr_reg
= gen_reg_rtx (Pmode
);
3282 emit_move_insn (addr_reg
, addr
);
3284 /* The first two words are the fake descriptor:
3285 __ia64_trampoline, ADDR+16. */
3286 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3287 gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline"));
3288 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3290 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3291 copy_to_reg (plus_constant (addr
, 16)));
3292 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3294 /* The third word is the target descriptor. */
3295 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), fnaddr
);
3296 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3298 /* The fourth word is the static chain. */
3299 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), static_chain
);
3302 /* Do any needed setup for a variadic function. CUM has not been updated
3303 for the last named argument which has type TYPE and mode MODE.
3305 We generate the actual spill instructions during prologue generation. */
3308 ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3309 tree type
, int * pretend_size
,
3310 int second_time ATTRIBUTE_UNUSED
)
3312 CUMULATIVE_ARGS next_cum
= *cum
;
3314 /* Skip the current argument. */
3315 ia64_function_arg_advance (&next_cum
, mode
, type
, 1);
3317 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
3319 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
3320 *pretend_size
= n
* UNITS_PER_WORD
;
3321 cfun
->machine
->n_varargs
= n
;
3325 /* Check whether TYPE is a homogeneous floating point aggregate. If
3326 it is, return the mode of the floating point type that appears
3327 in all leafs. If it is not, return VOIDmode.
3329 An aggregate is a homogeneous floating point aggregate is if all
3330 fields/elements in it have the same floating point type (e.g,
3331 SFmode). 128-bit quad-precision floats are excluded.
3333 Variable sized aggregates should never arrive here, since we should
3334 have already decided to pass them by reference. Top-level zero-sized
3335 aggregates are excluded because our parallels crash the middle-end. */
3337 static enum machine_mode
3338 hfa_element_mode (tree type
, bool nested
)
3340 enum machine_mode element_mode
= VOIDmode
;
3341 enum machine_mode mode
;
3342 enum tree_code code
= TREE_CODE (type
);
3343 int know_element_mode
= 0;
3346 if (!nested
&& (!TYPE_SIZE (type
) || integer_zerop (TYPE_SIZE (type
))))
3351 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
3352 case BOOLEAN_TYPE
: case CHAR_TYPE
: case POINTER_TYPE
:
3353 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
3354 case FILE_TYPE
: case LANG_TYPE
: case FUNCTION_TYPE
:
3357 /* Fortran complex types are supposed to be HFAs, so we need to handle
3358 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3361 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
3362 && TYPE_MODE (type
) != TCmode
)
3363 return GET_MODE_INNER (TYPE_MODE (type
));
3368 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3369 mode if this is contained within an aggregate. */
3370 if (nested
&& TYPE_MODE (type
) != TFmode
)
3371 return TYPE_MODE (type
);
3376 return hfa_element_mode (TREE_TYPE (type
), 1);
3380 case QUAL_UNION_TYPE
:
3381 for (t
= TYPE_FIELDS (type
); t
; t
= TREE_CHAIN (t
))
3383 if (TREE_CODE (t
) != FIELD_DECL
)
3386 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
3387 if (know_element_mode
)
3389 if (mode
!= element_mode
)
3392 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3396 know_element_mode
= 1;
3397 element_mode
= mode
;
3400 return element_mode
;
3403 /* If we reach here, we probably have some front-end specific type
3404 that the backend doesn't know about. This can happen via the
3405 aggregate_value_p call in init_function_start. All we can do is
3406 ignore unknown tree types. */
3413 /* Return the number of words required to hold a quantity of TYPE and MODE
3414 when passed as an argument. */
3416 ia64_function_arg_words (tree type
, enum machine_mode mode
)
3420 if (mode
== BLKmode
)
3421 words
= int_size_in_bytes (type
);
3423 words
= GET_MODE_SIZE (mode
);
3425 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
3428 /* Return the number of registers that should be skipped so the current
3429 argument (described by TYPE and WORDS) will be properly aligned.
3431 Integer and float arguments larger than 8 bytes start at the next
3432 even boundary. Aggregates larger than 8 bytes start at the next
3433 even boundary if the aggregate has 16 byte alignment. Note that
3434 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3435 but are still to be aligned in registers.
3437 ??? The ABI does not specify how to handle aggregates with
3438 alignment from 9 to 15 bytes, or greater than 16. We handle them
3439 all as if they had 16 byte alignment. Such aggregates can occur
3440 only if gcc extensions are used. */
3442 ia64_function_arg_offset (CUMULATIVE_ARGS
*cum
, tree type
, int words
)
3444 if ((cum
->words
& 1) == 0)
3448 && TREE_CODE (type
) != INTEGER_TYPE
3449 && TREE_CODE (type
) != REAL_TYPE
)
3450 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
3455 /* Return rtx for register where argument is passed, or zero if it is passed
3457 /* ??? 128-bit quad-precision floats are always passed in general
3461 ia64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
3462 int named
, int incoming
)
3464 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
3465 int words
= ia64_function_arg_words (type
, mode
);
3466 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3467 enum machine_mode hfa_mode
= VOIDmode
;
3469 /* If all argument slots are used, then it must go on the stack. */
3470 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3473 /* Check for and handle homogeneous FP aggregates. */
3475 hfa_mode
= hfa_element_mode (type
, 0);
3477 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3478 and unprototyped hfas are passed specially. */
3479 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3483 int fp_regs
= cum
->fp_regs
;
3484 int int_regs
= cum
->words
+ offset
;
3485 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3489 /* If prototyped, pass it in FR regs then GR regs.
3490 If not prototyped, pass it in both FR and GR regs.
3492 If this is an SFmode aggregate, then it is possible to run out of
3493 FR regs while GR regs are still left. In that case, we pass the
3494 remaining part in the GR regs. */
3496 /* Fill the FP regs. We do this always. We stop if we reach the end
3497 of the argument, the last FP register, or the last argument slot. */
3499 byte_size
= ((mode
== BLKmode
)
3500 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3501 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3503 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3504 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
3506 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3507 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
3511 args_byte_size
+= hfa_size
;
3515 /* If no prototype, then the whole thing must go in GR regs. */
3516 if (! cum
->prototype
)
3518 /* If this is an SFmode aggregate, then we might have some left over
3519 that needs to go in GR regs. */
3520 else if (byte_size
!= offset
)
3521 int_regs
+= offset
/ UNITS_PER_WORD
;
3523 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3525 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
3527 enum machine_mode gr_mode
= DImode
;
3528 unsigned int gr_size
;
3530 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3531 then this goes in a GR reg left adjusted/little endian, right
3532 adjusted/big endian. */
3533 /* ??? Currently this is handled wrong, because 4-byte hunks are
3534 always right adjusted/little endian. */
3537 /* If we have an even 4 byte hunk because the aggregate is a
3538 multiple of 4 bytes in size, then this goes in a GR reg right
3539 adjusted/little endian. */
3540 else if (byte_size
- offset
== 4)
3543 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3544 gen_rtx_REG (gr_mode
, (basereg
3548 gr_size
= GET_MODE_SIZE (gr_mode
);
3550 if (gr_size
== UNITS_PER_WORD
3551 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
3553 else if (gr_size
> UNITS_PER_WORD
)
3554 int_regs
+= gr_size
/ UNITS_PER_WORD
;
3556 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3559 /* Integral and aggregates go in general registers. If we have run out of
3560 FR registers, then FP values must also go in general registers. This can
3561 happen when we have a SFmode HFA. */
3562 else if (mode
== TFmode
|| mode
== TCmode
3563 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3565 int byte_size
= ((mode
== BLKmode
)
3566 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3567 if (BYTES_BIG_ENDIAN
3568 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
3569 && byte_size
< UNITS_PER_WORD
3572 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3573 gen_rtx_REG (DImode
,
3574 (basereg
+ cum
->words
3577 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
3580 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3584 /* If there is a prototype, then FP values go in a FR register when
3585 named, and in a GR register when unnamed. */
3586 else if (cum
->prototype
)
3589 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
3590 /* In big-endian mode, an anonymous SFmode value must be represented
3591 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3592 the value into the high half of the general register. */
3593 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
3594 return gen_rtx_PARALLEL (mode
,
3596 gen_rtx_EXPR_LIST (VOIDmode
,
3597 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
3600 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3602 /* If there is no prototype, then FP values go in both FR and GR
3606 /* See comment above. */
3607 enum machine_mode inner_mode
=
3608 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
3610 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3611 gen_rtx_REG (mode
, (FR_ARG_FIRST
3614 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3615 gen_rtx_REG (inner_mode
,
3616 (basereg
+ cum
->words
3620 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
3624 /* Return number of bytes, at the beginning of the argument, that must be
3625 put in registers. 0 is the argument is entirely in registers or entirely
3629 ia64_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3630 tree type
, bool named ATTRIBUTE_UNUSED
)
3632 int words
= ia64_function_arg_words (type
, mode
);
3633 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3635 /* If all argument slots are used, then it must go on the stack. */
3636 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3639 /* It doesn't matter whether the argument goes in FR or GR regs. If
3640 it fits within the 8 argument slots, then it goes entirely in
3641 registers. If it extends past the last argument slot, then the rest
3642 goes on the stack. */
3644 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
3647 return (MAX_ARGUMENT_SLOTS
- cum
->words
- offset
) * UNITS_PER_WORD
;
3650 /* Update CUM to point after this argument. This is patterned after
3651 ia64_function_arg. */
3654 ia64_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3655 tree type
, int named
)
3657 int words
= ia64_function_arg_words (type
, mode
);
3658 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3659 enum machine_mode hfa_mode
= VOIDmode
;
3661 /* If all arg slots are already full, then there is nothing to do. */
3662 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
3665 cum
->words
+= words
+ offset
;
3667 /* Check for and handle homogeneous FP aggregates. */
3669 hfa_mode
= hfa_element_mode (type
, 0);
3671 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3672 and unprototyped hfas are passed specially. */
3673 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3675 int fp_regs
= cum
->fp_regs
;
3676 /* This is the original value of cum->words + offset. */
3677 int int_regs
= cum
->words
- words
;
3678 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3682 /* If prototyped, pass it in FR regs then GR regs.
3683 If not prototyped, pass it in both FR and GR regs.
3685 If this is an SFmode aggregate, then it is possible to run out of
3686 FR regs while GR regs are still left. In that case, we pass the
3687 remaining part in the GR regs. */
3689 /* Fill the FP regs. We do this always. We stop if we reach the end
3690 of the argument, the last FP register, or the last argument slot. */
3692 byte_size
= ((mode
== BLKmode
)
3693 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3694 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3696 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3697 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
3700 args_byte_size
+= hfa_size
;
3704 cum
->fp_regs
= fp_regs
;
3707 /* Integral and aggregates go in general registers. So do TFmode FP values.
3708 If we have run out of FR registers, then other FP values must also go in
3709 general registers. This can happen when we have a SFmode HFA. */
3710 else if (mode
== TFmode
|| mode
== TCmode
3711 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3712 cum
->int_regs
= cum
->words
;
3714 /* If there is a prototype, then FP values go in a FR register when
3715 named, and in a GR register when unnamed. */
3716 else if (cum
->prototype
)
3719 cum
->int_regs
= cum
->words
;
3721 /* ??? Complex types should not reach here. */
3722 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3724 /* If there is no prototype, then FP values go in both FR and GR
3728 /* ??? Complex types should not reach here. */
3729 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3730 cum
->int_regs
= cum
->words
;
3734 /* Arguments with alignment larger than 8 bytes start at the next even
3735 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
3736 even though their normal alignment is 8 bytes. See ia64_function_arg. */
3739 ia64_function_arg_boundary (enum machine_mode mode
, tree type
)
3742 if (mode
== TFmode
&& TARGET_HPUX
&& TARGET_ILP32
)
3743 return PARM_BOUNDARY
* 2;
3747 if (TYPE_ALIGN (type
) > PARM_BOUNDARY
)
3748 return PARM_BOUNDARY
* 2;
3750 return PARM_BOUNDARY
;
3753 if (GET_MODE_BITSIZE (mode
) > PARM_BOUNDARY
)
3754 return PARM_BOUNDARY
* 2;
3756 return PARM_BOUNDARY
;
3759 /* Variable sized types are passed by reference. */
3760 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3763 ia64_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3764 enum machine_mode mode ATTRIBUTE_UNUSED
,
3765 tree type
, bool named ATTRIBUTE_UNUSED
)
3767 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
3770 /* True if it is OK to do sibling call optimization for the specified
3771 call expression EXP. DECL will be the called function, or NULL if
3772 this is an indirect call. */
3774 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3776 /* We can't perform a sibcall if the current function has the syscall_linkage
3778 if (lookup_attribute ("syscall_linkage",
3779 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
3782 /* We must always return with our current GP. This means we can
3783 only sibcall to functions defined in the current module. */
3784 return decl
&& (*targetm
.binds_local_p
) (decl
);
3788 /* Implement va_arg. */
3791 ia64_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
3793 /* Variable sized types are passed by reference. */
3794 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
3796 tree ptrtype
= build_pointer_type (type
);
3797 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
3798 return build_va_arg_indirect_ref (addr
);
3801 /* Aggregate arguments with alignment larger than 8 bytes start at
3802 the next even boundary. Integer and floating point arguments
3803 do so if they are larger than 8 bytes, whether or not they are
3804 also aligned larger than 8 bytes. */
3805 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
3806 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3808 tree t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
3809 build_int_cst (NULL_TREE
, 2 * UNITS_PER_WORD
- 1));
3810 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3811 build_int_cst (NULL_TREE
, -2 * UNITS_PER_WORD
));
3812 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
3813 gimplify_and_add (t
, pre_p
);
3816 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
3819 /* Return 1 if function return value returned in memory. Return 0 if it is
3823 ia64_return_in_memory (tree valtype
, tree fntype ATTRIBUTE_UNUSED
)
3825 enum machine_mode mode
;
3826 enum machine_mode hfa_mode
;
3827 HOST_WIDE_INT byte_size
;
3829 mode
= TYPE_MODE (valtype
);
3830 byte_size
= GET_MODE_SIZE (mode
);
3831 if (mode
== BLKmode
)
3833 byte_size
= int_size_in_bytes (valtype
);
3838 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
3840 hfa_mode
= hfa_element_mode (valtype
, 0);
3841 if (hfa_mode
!= VOIDmode
)
3843 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3845 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
3850 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
3856 /* Return rtx for register that holds the function return value. */
3859 ia64_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3861 enum machine_mode mode
;
3862 enum machine_mode hfa_mode
;
3864 mode
= TYPE_MODE (valtype
);
3865 hfa_mode
= hfa_element_mode (valtype
, 0);
3867 if (hfa_mode
!= VOIDmode
)
3875 hfa_size
= GET_MODE_SIZE (hfa_mode
);
3876 byte_size
= ((mode
== BLKmode
)
3877 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
3879 for (i
= 0; offset
< byte_size
; i
++)
3881 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3882 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
3886 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3888 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
3889 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
3892 bool need_parallel
= false;
3894 /* In big-endian mode, we need to manage the layout of aggregates
3895 in the registers so that we get the bits properly aligned in
3896 the highpart of the registers. */
3897 if (BYTES_BIG_ENDIAN
3898 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
3899 need_parallel
= true;
3901 /* Something like struct S { long double x; char a[0] } is not an
3902 HFA structure, and therefore doesn't go in fp registers. But
3903 the middle-end will give it XFmode anyway, and XFmode values
3904 don't normally fit in integer registers. So we need to smuggle
3905 the value inside a parallel. */
3906 else if (mode
== XFmode
|| mode
== XCmode
)
3907 need_parallel
= true;
3917 bytesize
= int_size_in_bytes (valtype
);
3918 for (i
= 0; offset
< bytesize
; i
++)
3920 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3921 gen_rtx_REG (DImode
,
3924 offset
+= UNITS_PER_WORD
;
3926 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3929 return gen_rtx_REG (mode
, GR_RET_FIRST
);
3933 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3934 We need to emit DTP-relative relocations. */
3937 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3941 fputs ("\tdata8.ua\t@dtprel(", file
);
3942 output_addr_const (file
, x
);
3946 /* Print a memory address as an operand to reference that memory location. */
3948 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
3949 also call this from ia64_print_operand for memory addresses. */
3952 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
3953 rtx address ATTRIBUTE_UNUSED
)
3957 /* Print an operand to an assembler instruction.
3958 C Swap and print a comparison operator.
3959 D Print an FP comparison operator.
3960 E Print 32 - constant, for SImode shifts as extract.
3961 e Print 64 - constant, for DImode rotates.
3962 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3963 a floating point register emitted normally.
3964 I Invert a predicate register by adding 1.
3965 J Select the proper predicate register for a condition.
3966 j Select the inverse predicate register for a condition.
3967 O Append .acq for volatile load.
3968 P Postincrement of a MEM.
3969 Q Append .rel for volatile store.
3970 S Shift amount for shladd instruction.
3971 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3972 for Intel assembler.
3973 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3974 for Intel assembler.
3975 r Print register name, or constant 0 as r0. HP compatibility for
3977 v Print vector constant value as an 8-byte integer value. */
3980 ia64_print_operand (FILE * file
, rtx x
, int code
)
3987 /* Handled below. */
3992 enum rtx_code c
= swap_condition (GET_CODE (x
));
3993 fputs (GET_RTX_NAME (c
), file
);
3998 switch (GET_CODE (x
))
4010 str
= GET_RTX_NAME (GET_CODE (x
));
4017 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
4021 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
4025 if (x
== CONST0_RTX (GET_MODE (x
)))
4026 str
= reg_names
[FR_REG (0)];
4027 else if (x
== CONST1_RTX (GET_MODE (x
)))
4028 str
= reg_names
[FR_REG (1)];
4029 else if (GET_CODE (x
) == REG
)
4030 str
= reg_names
[REGNO (x
)];
4037 fputs (reg_names
[REGNO (x
) + 1], file
);
4043 unsigned int regno
= REGNO (XEXP (x
, 0));
4044 if (GET_CODE (x
) == EQ
)
4048 fputs (reg_names
[regno
], file
);
4053 if (MEM_VOLATILE_P (x
))
4054 fputs(".acq", file
);
4059 HOST_WIDE_INT value
;
4061 switch (GET_CODE (XEXP (x
, 0)))
4067 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
4068 if (GET_CODE (x
) == CONST_INT
)
4070 else if (GET_CODE (x
) == REG
)
4072 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
4080 value
= GET_MODE_SIZE (GET_MODE (x
));
4084 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
4088 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
4093 if (MEM_VOLATILE_P (x
))
4094 fputs(".rel", file
);
4098 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
4102 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4104 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
4110 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4112 const char *prefix
= "0x";
4113 if (INTVAL (x
) & 0x80000000)
4115 fprintf (file
, "0xffffffff");
4118 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
4124 /* If this operand is the constant zero, write it as register zero.
4125 Any register, zero, or CONST_INT value is OK here. */
4126 if (GET_CODE (x
) == REG
)
4127 fputs (reg_names
[REGNO (x
)], file
);
4128 else if (x
== CONST0_RTX (GET_MODE (x
)))
4130 else if (GET_CODE (x
) == CONST_INT
)
4131 output_addr_const (file
, x
);
4133 output_operand_lossage ("invalid %%r value");
4137 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
4138 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
4145 /* For conditional branches, returns or calls, substitute
4146 sptk, dptk, dpnt, or spnt for %s. */
4147 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
4150 int pred_val
= INTVAL (XEXP (x
, 0));
4152 /* Guess top and bottom 10% statically predicted. */
4153 if (pred_val
< REG_BR_PROB_BASE
/ 50)
4155 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
4157 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98)
4162 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
4167 fputs (which
, file
);
4172 x
= current_insn_predicate
;
4175 unsigned int regno
= REGNO (XEXP (x
, 0));
4176 if (GET_CODE (x
) == EQ
)
4178 fprintf (file
, "(%s) ", reg_names
[regno
]);
4183 output_operand_lossage ("ia64_print_operand: unknown code");
4187 switch (GET_CODE (x
))
4189 /* This happens for the spill/restore instructions. */
4194 /* ... fall through ... */
4197 fputs (reg_names
[REGNO (x
)], file
);
4202 rtx addr
= XEXP (x
, 0);
4203 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
4204 addr
= XEXP (addr
, 0);
4205 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
4210 output_addr_const (file
, x
);
4217 /* Compute a (partial) cost for rtx X. Return true if the complete
4218 cost has been computed, and false if subexpressions should be
4219 scanned. In either case, *TOTAL contains the cost result. */
4220 /* ??? This is incomplete. */
4223 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4231 *total
= CONST_OK_FOR_J (INTVAL (x
)) ? 0 : COSTS_N_INSNS (1);
4234 if (CONST_OK_FOR_I (INTVAL (x
)))
4236 else if (CONST_OK_FOR_J (INTVAL (x
)))
4239 *total
= COSTS_N_INSNS (1);
4242 if (CONST_OK_FOR_K (INTVAL (x
)) || CONST_OK_FOR_L (INTVAL (x
)))
4245 *total
= COSTS_N_INSNS (1);
4250 *total
= COSTS_N_INSNS (1);
4256 *total
= COSTS_N_INSNS (3);
4260 /* For multiplies wider than HImode, we have to go to the FPU,
4261 which normally involves copies. Plus there's the latency
4262 of the multiply itself, and the latency of the instructions to
4263 transfer integer regs to FP regs. */
4264 /* ??? Check for FP mode. */
4265 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
4266 *total
= COSTS_N_INSNS (10);
4268 *total
= COSTS_N_INSNS (2);
4276 *total
= COSTS_N_INSNS (1);
4283 /* We make divide expensive, so that divide-by-constant will be
4284 optimized to a multiply. */
4285 *total
= COSTS_N_INSNS (60);
4293 /* Calculate the cost of moving data from a register in class FROM to
4294 one in class TO, using MODE. */
4297 ia64_register_move_cost (enum machine_mode mode
, enum reg_class from
,
4300 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4301 if (to
== ADDL_REGS
)
4303 if (from
== ADDL_REGS
)
4306 /* All costs are symmetric, so reduce cases by putting the
4307 lower number class as the destination. */
4310 enum reg_class tmp
= to
;
4311 to
= from
, from
= tmp
;
4314 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4315 so that we get secondary memory reloads. Between FR_REGS,
4316 we have to make this at least as expensive as MEMORY_MOVE_COST
4317 to avoid spectacularly poor register class preferencing. */
4320 if (to
!= GR_REGS
|| from
!= GR_REGS
)
4321 return MEMORY_MOVE_COST (mode
, to
, 0);
4329 /* Moving between PR registers takes two insns. */
4330 if (from
== PR_REGS
)
4332 /* Moving between PR and anything but GR is impossible. */
4333 if (from
!= GR_REGS
)
4334 return MEMORY_MOVE_COST (mode
, to
, 0);
4338 /* Moving between BR and anything but GR is impossible. */
4339 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
4340 return MEMORY_MOVE_COST (mode
, to
, 0);
4345 /* Moving between AR and anything but GR is impossible. */
4346 if (from
!= GR_REGS
)
4347 return MEMORY_MOVE_COST (mode
, to
, 0);
4352 case GR_AND_FR_REGS
:
4353 case GR_AND_BR_REGS
:
4364 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on CLASS
4365 to use when copying X into that class. */
4368 ia64_preferred_reload_class (rtx x
, enum reg_class
class)
4373 /* Don't allow volatile mem reloads into floating point registers.
4374 This is defined to force reload to choose the r/m case instead
4375 of the f/f case when reloading (set (reg fX) (mem/v)). */
4376 if (MEM_P (x
) && MEM_VOLATILE_P (x
))
4379 /* Force all unrecognized constants into the constant pool. */
4397 /* This function returns the register class required for a secondary
4398 register when copying between one of the registers in CLASS, and X,
4399 using MODE. A return value of NO_REGS means that no secondary register
4403 ia64_secondary_reload_class (enum reg_class
class,
4404 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4408 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
4409 regno
= true_regnum (x
);
4416 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4417 interaction. We end up with two pseudos with overlapping lifetimes
4418 both of which are equiv to the same constant, and both which need
4419 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4420 changes depending on the path length, which means the qty_first_reg
4421 check in make_regs_eqv can give different answers at different times.
4422 At some point I'll probably need a reload_indi pattern to handle
4425 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4426 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4427 non-general registers for good measure. */
4428 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
4431 /* This is needed if a pseudo used as a call_operand gets spilled to a
4433 if (GET_CODE (x
) == MEM
)
4438 /* Need to go through general registers to get to other class regs. */
4439 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
4442 /* This can happen when a paradoxical subreg is an operand to the
4444 /* ??? This shouldn't be necessary after instruction scheduling is
4445 enabled, because paradoxical subregs are not accepted by
4446 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4447 stop the paradoxical subreg stupidity in the *_operand functions
4449 if (GET_CODE (x
) == MEM
4450 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
4451 || GET_MODE (x
) == QImode
))
4454 /* This can happen because of the ior/and/etc patterns that accept FP
4455 registers as operands. If the third operand is a constant, then it
4456 needs to be reloaded into a FP register. */
4457 if (GET_CODE (x
) == CONST_INT
)
4460 /* This can happen because of register elimination in a muldi3 insn.
4461 E.g. `26107 * (unsigned long)&u'. */
4462 if (GET_CODE (x
) == PLUS
)
4467 /* ??? This happens if we cse/gcse a BImode value across a call,
4468 and the function has a nonlocal goto. This is because global
4469 does not allocate call crossing pseudos to hard registers when
4470 current_function_has_nonlocal_goto is true. This is relatively
4471 common for C++ programs that use exceptions. To reproduce,
4472 return NO_REGS and compile libstdc++. */
4473 if (GET_CODE (x
) == MEM
)
4476 /* This can happen when we take a BImode subreg of a DImode value,
4477 and that DImode value winds up in some non-GR register. */
4478 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
4490 /* Emit text to declare externally defined variables and functions, because
4491 the Intel assembler does not support undefined externals. */
4494 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
4496 int save_referenced
;
4498 /* GNU as does not need anything here, but the HP linker does need
4499 something for external functions. */
4503 || TREE_CODE (decl
) != FUNCTION_DECL
4504 || strstr (name
, "__builtin_") == name
))
4507 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4508 the linker when we do this, so we need to be careful not to do this for
4509 builtin functions which have no library equivalent. Unfortunately, we
4510 can't tell here whether or not a function will actually be called by
4511 expand_expr, so we pull in library functions even if we may not need
4513 if (! strcmp (name
, "__builtin_next_arg")
4514 || ! strcmp (name
, "alloca")
4515 || ! strcmp (name
, "__builtin_constant_p")
4516 || ! strcmp (name
, "__builtin_args_info"))
4520 ia64_hpux_add_extern_decl (decl
);
4523 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4525 save_referenced
= TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
));
4526 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4527 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
4528 (*targetm
.asm_out
.globalize_label
) (file
, name
);
4529 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)) = save_referenced
;
4533 /* Parse the -mfixed-range= option string. */
4536 fix_range (const char *const_str
)
4539 char *str
, *dash
, *comma
;
4541 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4542 REG2 are either register names or register numbers. The effect
4543 of this option is to mark the registers in the range from REG1 to
4544 REG2 as ``fixed'' so they won't be used by the compiler. This is
4545 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4547 i
= strlen (const_str
);
4548 str
= (char *) alloca (i
+ 1);
4549 memcpy (str
, const_str
, i
+ 1);
4553 dash
= strchr (str
, '-');
4556 warning ("value of -mfixed-range must have form REG1-REG2");
4561 comma
= strchr (dash
+ 1, ',');
4565 first
= decode_reg_name (str
);
4568 warning ("unknown register name: %s", str
);
4572 last
= decode_reg_name (dash
+ 1);
4575 warning ("unknown register name: %s", dash
+ 1);
4583 warning ("%s-%s is an empty range", str
, dash
+ 1);
4587 for (i
= first
; i
<= last
; ++i
)
4588 fixed_regs
[i
] = call_used_regs
[i
] = 1;
4598 static struct machine_function
*
4599 ia64_init_machine_status (void)
4601 return ggc_alloc_cleared (sizeof (struct machine_function
));
4604 /* Handle TARGET_OPTIONS switches. */
4607 ia64_override_options (void)
4611 const char *const name
; /* processor name or nickname. */
4612 const enum processor_type processor
;
4614 const processor_alias_table
[] =
4616 {"itanium", PROCESSOR_ITANIUM
},
4617 {"itanium1", PROCESSOR_ITANIUM
},
4618 {"merced", PROCESSOR_ITANIUM
},
4619 {"itanium2", PROCESSOR_ITANIUM2
},
4620 {"mckinley", PROCESSOR_ITANIUM2
},
4623 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
4626 if (TARGET_AUTO_PIC
)
4627 target_flags
|= MASK_CONST_GP
;
4629 if (TARGET_INLINE_FLOAT_DIV_LAT
&& TARGET_INLINE_FLOAT_DIV_THR
)
4631 if ((target_flags_explicit
& MASK_INLINE_FLOAT_DIV_LAT
)
4632 && (target_flags_explicit
& MASK_INLINE_FLOAT_DIV_THR
))
4634 warning ("cannot optimize floating point division for both latency and throughput");
4635 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4639 if (target_flags_explicit
& MASK_INLINE_FLOAT_DIV_THR
)
4640 target_flags
&= ~MASK_INLINE_FLOAT_DIV_LAT
;
4642 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4646 if (TARGET_INLINE_INT_DIV_LAT
&& TARGET_INLINE_INT_DIV_THR
)
4648 if ((target_flags_explicit
& MASK_INLINE_INT_DIV_LAT
)
4649 && (target_flags_explicit
& MASK_INLINE_INT_DIV_THR
))
4651 warning ("cannot optimize integer division for both latency and throughput");
4652 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4656 if (target_flags_explicit
& MASK_INLINE_INT_DIV_THR
)
4657 target_flags
&= ~MASK_INLINE_INT_DIV_LAT
;
4659 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4663 if (TARGET_INLINE_SQRT_LAT
&& TARGET_INLINE_SQRT_THR
)
4665 if ((target_flags_explicit
& MASK_INLINE_SQRT_LAT
)
4666 && (target_flags_explicit
& MASK_INLINE_SQRT_THR
))
4668 warning ("cannot optimize square root for both latency and throughput");
4669 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4673 if (target_flags_explicit
& MASK_INLINE_SQRT_THR
)
4674 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4676 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4680 if (TARGET_INLINE_SQRT_LAT
)
4682 warning ("not yet implemented: latency-optimized inline square root");
4683 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4686 if (ia64_fixed_range_string
)
4687 fix_range (ia64_fixed_range_string
);
4689 if (ia64_tls_size_string
)
4692 unsigned long tmp
= strtoul (ia64_tls_size_string
, &end
, 10);
4693 if (*end
|| (tmp
!= 14 && tmp
!= 22 && tmp
!= 64))
4694 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string
);
4696 ia64_tls_size
= tmp
;
4699 if (!ia64_tune_string
)
4700 ia64_tune_string
= "itanium2";
4702 for (i
= 0; i
< pta_size
; i
++)
4703 if (! strcmp (ia64_tune_string
, processor_alias_table
[i
].name
))
4705 ia64_tune
= processor_alias_table
[i
].processor
;
4710 error ("bad value (%s) for -tune= switch", ia64_tune_string
);
4712 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
4713 flag_schedule_insns_after_reload
= 0;
4715 /* Variable tracking should be run after all optimizations which change order
4716 of insns. It also needs a valid CFG. */
4717 ia64_flag_var_tracking
= flag_var_tracking
;
4718 flag_var_tracking
= 0;
4720 ia64_section_threshold
= g_switch_set
? g_switch_value
: IA64_DEFAULT_GVALUE
;
4722 init_machine_status
= ia64_init_machine_status
;
4725 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
4726 static enum attr_type
ia64_safe_type (rtx
);
4728 static enum attr_itanium_class
4729 ia64_safe_itanium_class (rtx insn
)
4731 if (recog_memoized (insn
) >= 0)
4732 return get_attr_itanium_class (insn
);
4734 return ITANIUM_CLASS_UNKNOWN
;
4737 static enum attr_type
4738 ia64_safe_type (rtx insn
)
4740 if (recog_memoized (insn
) >= 0)
4741 return get_attr_type (insn
);
4743 return TYPE_UNKNOWN
;
4746 /* The following collection of routines emit instruction group stop bits as
4747 necessary to avoid dependencies. */
4749 /* Need to track some additional registers as far as serialization is
4750 concerned so we can properly handle br.call and br.ret. We could
4751 make these registers visible to gcc, but since these registers are
4752 never explicitly used in gcc generated code, it seems wasteful to
4753 do so (plus it would make the call and return patterns needlessly
4755 #define REG_RP (BR_REG (0))
4756 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4757 /* This is used for volatile asms which may require a stop bit immediately
4758 before and after them. */
4759 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4760 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4761 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4763 /* For each register, we keep track of how it has been written in the
4764 current instruction group.
4766 If a register is written unconditionally (no qualifying predicate),
4767 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4769 If a register is written if its qualifying predicate P is true, we
4770 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4771 may be written again by the complement of P (P^1) and when this happens,
4772 WRITE_COUNT gets set to 2.
4774 The result of this is that whenever an insn attempts to write a register
4775 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4777 If a predicate register is written by a floating-point insn, we set
4778 WRITTEN_BY_FP to true.
4780 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4781 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4783 struct reg_write_state
4785 unsigned int write_count
: 2;
4786 unsigned int first_pred
: 16;
4787 unsigned int written_by_fp
: 1;
4788 unsigned int written_by_and
: 1;
4789 unsigned int written_by_or
: 1;
4792 /* Cumulative info for the current instruction group. */
4793 struct reg_write_state rws_sum
[NUM_REGS
];
4794 /* Info for the current instruction. This gets copied to rws_sum after a
4795 stop bit is emitted. */
4796 struct reg_write_state rws_insn
[NUM_REGS
];
4798 /* Indicates whether this is the first instruction after a stop bit,
4799 in which case we don't need another stop bit. Without this, we hit
4800 the abort in ia64_variable_issue when scheduling an alloc. */
4801 static int first_instruction
;
4803 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4804 RTL for one instruction. */
4807 unsigned int is_write
: 1; /* Is register being written? */
4808 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
4809 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
4810 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
4811 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
4812 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
4815 static void rws_update (struct reg_write_state
*, int, struct reg_flags
, int);
4816 static int rws_access_regno (int, struct reg_flags
, int);
4817 static int rws_access_reg (rtx
, struct reg_flags
, int);
4818 static void update_set_flags (rtx
, struct reg_flags
*, int *, rtx
*);
4819 static int set_src_needs_barrier (rtx
, struct reg_flags
, int, rtx
);
4820 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
4821 static void init_insn_group_barriers (void);
4822 static int group_barrier_needed_p (rtx
);
4823 static int safe_group_barrier_needed_p (rtx
);
4825 /* Update *RWS for REGNO, which is being written by the current instruction,
4826 with predicate PRED, and associated register flags in FLAGS. */
4829 rws_update (struct reg_write_state
*rws
, int regno
, struct reg_flags flags
, int pred
)
4832 rws
[regno
].write_count
++;
4834 rws
[regno
].write_count
= 2;
4835 rws
[regno
].written_by_fp
|= flags
.is_fp
;
4836 /* ??? Not tracking and/or across differing predicates. */
4837 rws
[regno
].written_by_and
= flags
.is_and
;
4838 rws
[regno
].written_by_or
= flags
.is_or
;
4839 rws
[regno
].first_pred
= pred
;
4842 /* Handle an access to register REGNO of type FLAGS using predicate register
4843 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4844 a dependency with an earlier instruction in the same group. */
4847 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
4849 int need_barrier
= 0;
4851 if (regno
>= NUM_REGS
)
4854 if (! PR_REGNO_P (regno
))
4855 flags
.is_and
= flags
.is_or
= 0;
4861 /* One insn writes same reg multiple times? */
4862 if (rws_insn
[regno
].write_count
> 0)
4865 /* Update info for current instruction. */
4866 rws_update (rws_insn
, regno
, flags
, pred
);
4867 write_count
= rws_sum
[regno
].write_count
;
4869 switch (write_count
)
4872 /* The register has not been written yet. */
4873 rws_update (rws_sum
, regno
, flags
, pred
);
4877 /* The register has been written via a predicate. If this is
4878 not a complementary predicate, then we need a barrier. */
4879 /* ??? This assumes that P and P+1 are always complementary
4880 predicates for P even. */
4881 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4883 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4885 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
4887 rws_update (rws_sum
, regno
, flags
, pred
);
4891 /* The register has been unconditionally written already. We
4893 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4895 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4899 rws_sum
[regno
].written_by_and
= flags
.is_and
;
4900 rws_sum
[regno
].written_by_or
= flags
.is_or
;
4909 if (flags
.is_branch
)
4911 /* Branches have several RAW exceptions that allow to avoid
4914 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
4915 /* RAW dependencies on branch regs are permissible as long
4916 as the writer is a non-branch instruction. Since we
4917 never generate code that uses a branch register written
4918 by a branch instruction, handling this case is
4922 if (REGNO_REG_CLASS (regno
) == PR_REGS
4923 && ! rws_sum
[regno
].written_by_fp
)
4924 /* The predicates of a branch are available within the
4925 same insn group as long as the predicate was written by
4926 something other than a floating-point instruction. */
4930 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4932 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4935 switch (rws_sum
[regno
].write_count
)
4938 /* The register has not been written yet. */
4942 /* The register has been written via a predicate. If this is
4943 not a complementary predicate, then we need a barrier. */
4944 /* ??? This assumes that P and P+1 are always complementary
4945 predicates for P even. */
4946 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
4951 /* The register has been unconditionally written already. We
4961 return need_barrier
;
4965 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
4967 int regno
= REGNO (reg
);
4968 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
4971 return rws_access_regno (regno
, flags
, pred
);
4974 int need_barrier
= 0;
4976 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
4977 return need_barrier
;
4981 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
4982 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
4985 update_set_flags (rtx x
, struct reg_flags
*pflags
, int *ppred
, rtx
*pcond
)
4987 rtx src
= SET_SRC (x
);
4991 switch (GET_CODE (src
))
4997 if (SET_DEST (x
) == pc_rtx
)
4998 /* X is a conditional branch. */
5002 int is_complemented
= 0;
5004 /* X is a conditional move. */
5005 rtx cond
= XEXP (src
, 0);
5006 if (GET_CODE (cond
) == EQ
)
5007 is_complemented
= 1;
5008 cond
= XEXP (cond
, 0);
5009 if (GET_CODE (cond
) != REG
5010 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5013 if (XEXP (src
, 1) == SET_DEST (x
)
5014 || XEXP (src
, 2) == SET_DEST (x
))
5016 /* X is a conditional move that conditionally writes the
5019 /* We need another complement in this case. */
5020 if (XEXP (src
, 1) == SET_DEST (x
))
5021 is_complemented
= ! is_complemented
;
5023 *ppred
= REGNO (cond
);
5024 if (is_complemented
)
5028 /* ??? If this is a conditional write to the dest, then this
5029 instruction does not actually read one source. This probably
5030 doesn't matter, because that source is also the dest. */
5031 /* ??? Multiple writes to predicate registers are allowed
5032 if they are all AND type compares, or if they are all OR
5033 type compares. We do not generate such instructions
5036 /* ... fall through ... */
5039 if (COMPARISON_P (src
)
5040 && GET_MODE_CLASS (GET_MODE (XEXP (src
, 0))) == MODE_FLOAT
)
5041 /* Set pflags->is_fp to 1 so that we know we're dealing
5042 with a floating point comparison when processing the
5043 destination of the SET. */
5046 /* Discover if this is a parallel comparison. We only handle
5047 and.orcm and or.andcm at present, since we must retain a
5048 strict inverse on the predicate pair. */
5049 else if (GET_CODE (src
) == AND
)
5051 else if (GET_CODE (src
) == IOR
)
5058 /* Subroutine of rtx_needs_barrier; this function determines whether the
5059 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5060 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5064 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
, rtx cond
)
5066 int need_barrier
= 0;
5068 rtx src
= SET_SRC (x
);
5070 if (GET_CODE (src
) == CALL
)
5071 /* We don't need to worry about the result registers that
5072 get written by subroutine call. */
5073 return rtx_needs_barrier (src
, flags
, pred
);
5074 else if (SET_DEST (x
) == pc_rtx
)
5076 /* X is a conditional branch. */
5077 /* ??? This seems redundant, as the caller sets this bit for
5079 flags
.is_branch
= 1;
5080 return rtx_needs_barrier (src
, flags
, pred
);
5083 need_barrier
= rtx_needs_barrier (src
, flags
, pred
);
5085 /* This instruction unconditionally uses a predicate register. */
5087 need_barrier
|= rws_access_reg (cond
, flags
, 0);
5090 if (GET_CODE (dst
) == ZERO_EXTRACT
)
5092 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
5093 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
5094 dst
= XEXP (dst
, 0);
5096 return need_barrier
;
5099 /* Handle an access to rtx X of type FLAGS using predicate register
5100 PRED. Return 1 if this access creates a dependency with an earlier
5101 instruction in the same group. */
5104 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
5107 int is_complemented
= 0;
5108 int need_barrier
= 0;
5109 const char *format_ptr
;
5110 struct reg_flags new_flags
;
5118 switch (GET_CODE (x
))
5121 update_set_flags (x
, &new_flags
, &pred
, &cond
);
5122 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
, cond
);
5123 if (GET_CODE (SET_SRC (x
)) != CALL
)
5125 new_flags
.is_write
= 1;
5126 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
5131 new_flags
.is_write
= 0;
5132 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5134 /* Avoid multiple register writes, in case this is a pattern with
5135 multiple CALL rtx. This avoids an abort in rws_access_reg. */
5136 if (! flags
.is_sibcall
&& ! rws_insn
[REG_AR_CFM
].write_count
)
5138 new_flags
.is_write
= 1;
5139 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
5140 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
5141 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5146 /* X is a predicated instruction. */
5148 cond
= COND_EXEC_TEST (x
);
5151 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
5153 if (GET_CODE (cond
) == EQ
)
5154 is_complemented
= 1;
5155 cond
= XEXP (cond
, 0);
5156 if (GET_CODE (cond
) != REG
5157 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5159 pred
= REGNO (cond
);
5160 if (is_complemented
)
5163 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
5164 return need_barrier
;
5168 /* Clobber & use are for earlier compiler-phases only. */
5173 /* We always emit stop bits for traditional asms. We emit stop bits
5174 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5175 if (GET_CODE (x
) != ASM_OPERANDS
5176 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
5178 /* Avoid writing the register multiple times if we have multiple
5179 asm outputs. This avoids an abort in rws_access_reg. */
5180 if (! rws_insn
[REG_VOLATILE
].write_count
)
5182 new_flags
.is_write
= 1;
5183 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
5188 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5189 We cannot just fall through here since then we would be confused
5190 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5191 traditional asms unlike their normal usage. */
5193 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
5194 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
5199 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5201 rtx pat
= XVECEXP (x
, 0, i
);
5202 switch (GET_CODE (pat
))
5205 update_set_flags (pat
, &new_flags
, &pred
, &cond
);
5206 need_barrier
|= set_src_needs_barrier (pat
, new_flags
,
5213 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5224 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5226 rtx pat
= XVECEXP (x
, 0, i
);
5227 if (GET_CODE (pat
) == SET
)
5229 if (GET_CODE (SET_SRC (pat
)) != CALL
)
5231 new_flags
.is_write
= 1;
5232 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
5236 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
5237 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5245 if (REGNO (x
) == AR_UNAT_REGNUM
)
5247 for (i
= 0; i
< 64; ++i
)
5248 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
5251 need_barrier
= rws_access_reg (x
, flags
, pred
);
5255 /* Find the regs used in memory address computation. */
5256 new_flags
.is_write
= 0;
5257 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5260 case CONST_INT
: case CONST_DOUBLE
: case CONST_VECTOR
:
5261 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
5264 /* Operators with side-effects. */
5265 case POST_INC
: case POST_DEC
:
5266 if (GET_CODE (XEXP (x
, 0)) != REG
)
5269 new_flags
.is_write
= 0;
5270 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5271 new_flags
.is_write
= 1;
5272 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5276 if (GET_CODE (XEXP (x
, 0)) != REG
)
5279 new_flags
.is_write
= 0;
5280 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5281 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5282 new_flags
.is_write
= 1;
5283 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5286 /* Handle common unary and binary ops for efficiency. */
5287 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
5288 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
5289 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
5290 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5291 case NE
: case EQ
: case GE
: case GT
: case LE
:
5292 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
5293 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5294 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5297 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
5298 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
5299 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
5300 case SQRT
: case FFS
: case POPCOUNT
:
5301 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5305 /* VEC_SELECT's second argument is a PARALLEL with integers that
5306 describe the elements selected. On ia64, those integers are
5307 always constants. Avoid walking the PARALLEL so that we don't
5308 get confused with "normal" parallels and abort. */
5309 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5313 switch (XINT (x
, 1))
5315 case UNSPEC_LTOFF_DTPMOD
:
5316 case UNSPEC_LTOFF_DTPREL
:
5318 case UNSPEC_LTOFF_TPREL
:
5320 case UNSPEC_PRED_REL_MUTEX
:
5321 case UNSPEC_PIC_CALL
:
5323 case UNSPEC_FETCHADD_ACQ
:
5324 case UNSPEC_BSP_VALUE
:
5325 case UNSPEC_FLUSHRS
:
5326 case UNSPEC_BUNDLE_SELECTOR
:
5329 case UNSPEC_GR_SPILL
:
5330 case UNSPEC_GR_RESTORE
:
5332 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
5333 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
5335 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5336 new_flags
.is_write
= (XINT (x
, 1) == UNSPEC_GR_SPILL
);
5337 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
5342 case UNSPEC_FR_SPILL
:
5343 case UNSPEC_FR_RESTORE
:
5344 case UNSPEC_GETF_EXP
:
5345 case UNSPEC_SETF_EXP
:
5347 case UNSPEC_FR_SQRT_RECIP_APPROX
:
5348 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5351 case UNSPEC_FR_RECIP_APPROX
:
5353 case UNSPEC_COPYSIGN
:
5354 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5355 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5358 case UNSPEC_CMPXCHG_ACQ
:
5359 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5360 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
5368 case UNSPEC_VOLATILE
:
5369 switch (XINT (x
, 1))
5372 /* Alloc must always be the first instruction of a group.
5373 We force this by always returning true. */
5374 /* ??? We might get better scheduling if we explicitly check for
5375 input/local/output register dependencies, and modify the
5376 scheduler so that alloc is always reordered to the start of
5377 the current group. We could then eliminate all of the
5378 first_instruction code. */
5379 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5381 new_flags
.is_write
= 1;
5382 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5385 case UNSPECV_SET_BSP
:
5389 case UNSPECV_BLOCKAGE
:
5390 case UNSPECV_INSN_GROUP_BARRIER
:
5392 case UNSPECV_PSAC_ALL
:
5393 case UNSPECV_PSAC_NORMAL
:
5402 new_flags
.is_write
= 0;
5403 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
5404 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5406 new_flags
.is_write
= 1;
5407 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5408 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5412 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
5413 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5414 switch (format_ptr
[i
])
5416 case '0': /* unused field */
5417 case 'i': /* integer */
5418 case 'n': /* note */
5419 case 'w': /* wide integer */
5420 case 's': /* pointer to string */
5421 case 'S': /* optional pointer to string */
5425 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
5430 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
5431 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
5440 return need_barrier
;
5443 /* Clear out the state for group_barrier_needed_p at the start of a
5444 sequence of insns. */
5447 init_insn_group_barriers (void)
5449 memset (rws_sum
, 0, sizeof (rws_sum
));
5450 first_instruction
= 1;
5453 /* Given the current state, recorded by previous calls to this function,
5454 determine whether a group barrier (a stop bit) is necessary before INSN.
5455 Return nonzero if so. */
5458 group_barrier_needed_p (rtx insn
)
5461 int need_barrier
= 0;
5462 struct reg_flags flags
;
5464 memset (&flags
, 0, sizeof (flags
));
5465 switch (GET_CODE (insn
))
5471 /* A barrier doesn't imply an instruction group boundary. */
5475 memset (rws_insn
, 0, sizeof (rws_insn
));
5479 flags
.is_branch
= 1;
5480 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
5481 memset (rws_insn
, 0, sizeof (rws_insn
));
5483 /* Don't bundle a call following another call. */
5484 if ((pat
= prev_active_insn (insn
))
5485 && GET_CODE (pat
) == CALL_INSN
)
5491 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
5495 flags
.is_branch
= 1;
5497 /* Don't bundle a jump following a call. */
5498 if ((pat
= prev_active_insn (insn
))
5499 && GET_CODE (pat
) == CALL_INSN
)
5507 if (GET_CODE (PATTERN (insn
)) == USE
5508 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5509 /* Don't care about USE and CLOBBER "insns"---those are used to
5510 indicate to the optimizer that it shouldn't get rid of
5511 certain operations. */
5514 pat
= PATTERN (insn
);
5516 /* Ug. Hack hacks hacked elsewhere. */
5517 switch (recog_memoized (insn
))
5519 /* We play dependency tricks with the epilogue in order
5520 to get proper schedules. Undo this for dv analysis. */
5521 case CODE_FOR_epilogue_deallocate_stack
:
5522 case CODE_FOR_prologue_allocate_stack
:
5523 pat
= XVECEXP (pat
, 0, 0);
5526 /* The pattern we use for br.cloop confuses the code above.
5527 The second element of the vector is representative. */
5528 case CODE_FOR_doloop_end_internal
:
5529 pat
= XVECEXP (pat
, 0, 1);
5532 /* Doesn't generate code. */
5533 case CODE_FOR_pred_rel_mutex
:
5534 case CODE_FOR_prologue_use
:
5541 memset (rws_insn
, 0, sizeof (rws_insn
));
5542 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
5544 /* Check to see if the previous instruction was a volatile
5547 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
5554 if (first_instruction
&& INSN_P (insn
)
5555 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
5556 && GET_CODE (PATTERN (insn
)) != USE
5557 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5560 first_instruction
= 0;
5563 return need_barrier
;
5566 /* Like group_barrier_needed_p, but do not clobber the current state. */
5569 safe_group_barrier_needed_p (rtx insn
)
5571 struct reg_write_state rws_saved
[NUM_REGS
];
5572 int saved_first_instruction
;
5575 memcpy (rws_saved
, rws_sum
, NUM_REGS
* sizeof *rws_saved
);
5576 saved_first_instruction
= first_instruction
;
5578 t
= group_barrier_needed_p (insn
);
5580 memcpy (rws_sum
, rws_saved
, NUM_REGS
* sizeof *rws_saved
);
5581 first_instruction
= saved_first_instruction
;
5586 /* Scan the current function and insert stop bits as necessary to
5587 eliminate dependencies. This function assumes that a final
5588 instruction scheduling pass has been run which has already
5589 inserted most of the necessary stop bits. This function only
5590 inserts new ones at basic block boundaries, since these are
5591 invisible to the scheduler. */
5594 emit_insn_group_barriers (FILE *dump
)
5598 int insns_since_last_label
= 0;
5600 init_insn_group_barriers ();
5602 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5604 if (GET_CODE (insn
) == CODE_LABEL
)
5606 if (insns_since_last_label
)
5608 insns_since_last_label
= 0;
5610 else if (GET_CODE (insn
) == NOTE
5611 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
5613 if (insns_since_last_label
)
5615 insns_since_last_label
= 0;
5617 else if (GET_CODE (insn
) == INSN
5618 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
5619 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
5621 init_insn_group_barriers ();
5624 else if (INSN_P (insn
))
5626 insns_since_last_label
= 1;
5628 if (group_barrier_needed_p (insn
))
5633 fprintf (dump
, "Emitting stop before label %d\n",
5634 INSN_UID (last_label
));
5635 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
5638 init_insn_group_barriers ();
5646 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5647 This function has to emit all necessary group barriers. */
5650 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
5654 init_insn_group_barriers ();
5656 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5658 if (GET_CODE (insn
) == BARRIER
)
5660 rtx last
= prev_active_insn (insn
);
5664 if (GET_CODE (last
) == JUMP_INSN
5665 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
5666 last
= prev_active_insn (last
);
5667 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
5668 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
5670 init_insn_group_barriers ();
5672 else if (INSN_P (insn
))
5674 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
5675 init_insn_group_barriers ();
5676 else if (group_barrier_needed_p (insn
))
5678 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5679 init_insn_group_barriers ();
5680 group_barrier_needed_p (insn
);
5688 /* Instruction scheduling support. */
5690 #define NR_BUNDLES 10
5692 /* A list of names of all available bundles. */
5694 static const char *bundle_name
[NR_BUNDLES
] =
5700 #if NR_BUNDLES == 10
5710 /* Nonzero if we should insert stop bits into the schedule. */
5712 int ia64_final_schedule
= 0;
5714 /* Codes of the corresponding queried units: */
5716 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
5717 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
5719 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
5720 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
5722 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
5724 /* The following variable value is an insn group barrier. */
5726 static rtx dfa_stop_insn
;
5728 /* The following variable value is the last issued insn. */
5730 static rtx last_scheduled_insn
;
5732 /* The following variable value is size of the DFA state. */
5734 static size_t dfa_state_size
;
5736 /* The following variable value is pointer to a DFA state used as
5737 temporary variable. */
5739 static state_t temp_dfa_state
= NULL
;
5741 /* The following variable value is DFA state after issuing the last
5744 static state_t prev_cycle_state
= NULL
;
5746 /* The following array element values are TRUE if the corresponding
5747 insn requires to add stop bits before it. */
5749 static char *stops_p
;
5751 /* The following variable is used to set up the mentioned above array. */
5753 static int stop_before_p
= 0;
5755 /* The following variable value is length of the arrays `clocks' and
5758 static int clocks_length
;
5760 /* The following array element values are cycles on which the
5761 corresponding insn will be issued. The array is used only for
5766 /* The following array element values are numbers of cycles should be
5767 added to improve insn scheduling for MM_insns for Itanium1. */
5769 static int *add_cycles
;
5771 static rtx
ia64_single_set (rtx
);
5772 static void ia64_emit_insn_before (rtx
, rtx
);
5774 /* Map a bundle number to its pseudo-op. */
5777 get_bundle_name (int b
)
5779 return bundle_name
[b
];
5783 /* Return the maximum number of instructions a cpu can issue. */
5786 ia64_issue_rate (void)
5791 /* Helper function - like single_set, but look inside COND_EXEC. */
5794 ia64_single_set (rtx insn
)
5796 rtx x
= PATTERN (insn
), ret
;
5797 if (GET_CODE (x
) == COND_EXEC
)
5798 x
= COND_EXEC_CODE (x
);
5799 if (GET_CODE (x
) == SET
)
5802 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5803 Although they are not classical single set, the second set is there just
5804 to protect it from moving past FP-relative stack accesses. */
5805 switch (recog_memoized (insn
))
5807 case CODE_FOR_prologue_allocate_stack
:
5808 case CODE_FOR_epilogue_deallocate_stack
:
5809 ret
= XVECEXP (x
, 0, 0);
5813 ret
= single_set_2 (insn
, x
);
5820 /* Adjust the cost of a scheduling dependency. Return the new cost of
5821 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5824 ia64_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5826 enum attr_itanium_class dep_class
;
5827 enum attr_itanium_class insn_class
;
5829 if (REG_NOTE_KIND (link
) != REG_DEP_OUTPUT
)
5832 insn_class
= ia64_safe_itanium_class (insn
);
5833 dep_class
= ia64_safe_itanium_class (dep_insn
);
5834 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
5835 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
5841 /* Like emit_insn_before, but skip cycle_display notes.
5842 ??? When cycle display notes are implemented, update this. */
5845 ia64_emit_insn_before (rtx insn
, rtx before
)
5847 emit_insn_before (insn
, before
);
5850 /* The following function marks insns who produce addresses for load
5851 and store insns. Such insns will be placed into M slots because it
5852 decrease latency time for Itanium1 (see function
5853 `ia64_produce_address_p' and the DFA descriptions). */
5856 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
5858 rtx insn
, link
, next
, next_tail
;
5860 next_tail
= NEXT_INSN (tail
);
5861 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
5864 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
5866 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
5868 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
5870 next
= XEXP (link
, 0);
5871 if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_ST
5872 || ia64_safe_itanium_class (next
) == ITANIUM_CLASS_STF
)
5873 && ia64_st_address_bypass_p (insn
, next
))
5875 else if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_LD
5876 || ia64_safe_itanium_class (next
)
5877 == ITANIUM_CLASS_FLD
)
5878 && ia64_ld_address_bypass_p (insn
, next
))
5881 insn
->call
= link
!= 0;
5885 /* We're beginning a new block. Initialize data structures as necessary. */
5888 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
5889 int sched_verbose ATTRIBUTE_UNUSED
,
5890 int max_ready ATTRIBUTE_UNUSED
)
5892 #ifdef ENABLE_CHECKING
5895 if (reload_completed
)
5896 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
5897 insn
!= current_sched_info
->next_tail
;
5898 insn
= NEXT_INSN (insn
))
5899 if (SCHED_GROUP_P (insn
))
5902 last_scheduled_insn
= NULL_RTX
;
5903 init_insn_group_barriers ();
5906 /* We are about to being issuing insns for this clock cycle.
5907 Override the default sort algorithm to better slot instructions. */
5910 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
5911 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
,
5915 int n_ready
= *pn_ready
;
5916 rtx
*e_ready
= ready
+ n_ready
;
5920 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
5922 if (reorder_type
== 0)
5924 /* First, move all USEs, CLOBBERs and other crud out of the way. */
5926 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
5927 if (insnp
< e_ready
)
5930 enum attr_type t
= ia64_safe_type (insn
);
5931 if (t
== TYPE_UNKNOWN
)
5933 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
5934 || asm_noperands (PATTERN (insn
)) >= 0)
5936 rtx lowest
= ready
[n_asms
];
5937 ready
[n_asms
] = insn
;
5943 rtx highest
= ready
[n_ready
- 1];
5944 ready
[n_ready
- 1] = insn
;
5951 if (n_asms
< n_ready
)
5953 /* Some normal insns to process. Skip the asms. */
5957 else if (n_ready
> 0)
5961 if (ia64_final_schedule
)
5964 int nr_need_stop
= 0;
5966 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
5967 if (safe_group_barrier_needed_p (*insnp
))
5970 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
5972 if (reorder_type
== 0)
5975 /* Move down everything that needs a stop bit, preserving
5977 while (insnp
-- > ready
+ deleted
)
5978 while (insnp
>= ready
+ deleted
)
5981 if (! safe_group_barrier_needed_p (insn
))
5983 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
5994 /* We are about to being issuing insns for this clock cycle. Override
5995 the default sort algorithm to better slot instructions. */
5998 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
6001 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
6002 pn_ready
, clock_var
, 0);
6005 /* Like ia64_sched_reorder, but called after issuing each insn.
6006 Override the default sort algorithm to better slot instructions. */
6009 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
6010 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
6011 int *pn_ready
, int clock_var
)
6013 if (ia64_tune
== PROCESSOR_ITANIUM
&& reload_completed
&& last_scheduled_insn
)
6014 clocks
[INSN_UID (last_scheduled_insn
)] = clock_var
;
6015 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
6019 /* We are about to issue INSN. Return the number of insns left on the
6020 ready queue that can be issued this cycle. */
6023 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
6024 int sched_verbose ATTRIBUTE_UNUSED
,
6025 rtx insn ATTRIBUTE_UNUSED
,
6026 int can_issue_more ATTRIBUTE_UNUSED
)
6028 last_scheduled_insn
= insn
;
6029 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
6030 if (reload_completed
)
6032 if (group_barrier_needed_p (insn
))
6034 if (GET_CODE (insn
) == CALL_INSN
)
6035 init_insn_group_barriers ();
6036 stops_p
[INSN_UID (insn
)] = stop_before_p
;
6042 /* We are choosing insn from the ready queue. Return nonzero if INSN
6046 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
6048 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6050 return (!reload_completed
6051 || !safe_group_barrier_needed_p (insn
));
6054 /* The following variable value is pseudo-insn used by the DFA insn
6055 scheduler to change the DFA state when the simulated clock is
6058 static rtx dfa_pre_cycle_insn
;
6060 /* We are about to being issuing INSN. Return nonzero if we cannot
6061 issue it on given cycle CLOCK and return zero if we should not sort
6062 the ready queue on the next clock start. */
6065 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
6066 int clock
, int *sort_p
)
6068 int setup_clocks_p
= FALSE
;
6070 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6072 if ((reload_completed
&& safe_group_barrier_needed_p (insn
))
6073 || (last_scheduled_insn
6074 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
6075 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6076 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
6078 init_insn_group_barriers ();
6079 if (verbose
&& dump
)
6080 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
6081 last_clock
== clock
? " + cycle advance" : "");
6083 if (last_clock
== clock
)
6085 state_transition (curr_state
, dfa_stop_insn
);
6086 if (TARGET_EARLY_STOP_BITS
)
6087 *sort_p
= (last_scheduled_insn
== NULL_RTX
6088 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
6093 else if (reload_completed
)
6094 setup_clocks_p
= TRUE
;
6095 if (GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6096 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)
6097 state_reset (curr_state
);
6100 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
6101 state_transition (curr_state
, dfa_stop_insn
);
6102 state_transition (curr_state
, dfa_pre_cycle_insn
);
6103 state_transition (curr_state
, NULL
);
6106 else if (reload_completed
)
6107 setup_clocks_p
= TRUE
;
6108 if (setup_clocks_p
&& ia64_tune
== PROCESSOR_ITANIUM
6109 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6110 && asm_noperands (PATTERN (insn
)) < 0)
6112 enum attr_itanium_class c
= ia64_safe_itanium_class (insn
);
6114 if (c
!= ITANIUM_CLASS_MMMUL
&& c
!= ITANIUM_CLASS_MMSHF
)
6119 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6120 if (REG_NOTE_KIND (link
) == 0)
6122 enum attr_itanium_class dep_class
;
6123 rtx dep_insn
= XEXP (link
, 0);
6125 dep_class
= ia64_safe_itanium_class (dep_insn
);
6126 if ((dep_class
== ITANIUM_CLASS_MMMUL
6127 || dep_class
== ITANIUM_CLASS_MMSHF
)
6128 && last_clock
- clocks
[INSN_UID (dep_insn
)] < 4
6130 || last_clock
- clocks
[INSN_UID (dep_insn
)] < d
))
6131 d
= last_clock
- clocks
[INSN_UID (dep_insn
)];
6134 add_cycles
[INSN_UID (insn
)] = 3 - d
;
6142 /* The following page contains abstract data `bundle states' which are
6143 used for bundling insns (inserting nops and template generation). */
6145 /* The following describes state of insn bundling. */
6149 /* Unique bundle state number to identify them in the debugging
6152 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
6153 /* number nops before and after the insn */
6154 short before_nops_num
, after_nops_num
;
6155 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
6157 int cost
; /* cost of the state in cycles */
6158 int accumulated_insns_num
; /* number of all previous insns including
6159 nops. L is considered as 2 insns */
6160 int branch_deviation
; /* deviation of previous branches from 3rd slots */
6161 struct bundle_state
*next
; /* next state with the same insn_num */
6162 struct bundle_state
*originator
; /* originator (previous insn state) */
6163 /* All bundle states are in the following chain. */
6164 struct bundle_state
*allocated_states_chain
;
6165 /* The DFA State after issuing the insn and the nops. */
6169 /* The following is map insn number to the corresponding bundle state. */
6171 static struct bundle_state
**index_to_bundle_states
;
6173 /* The unique number of next bundle state. */
6175 static int bundle_states_num
;
6177 /* All allocated bundle states are in the following chain. */
6179 static struct bundle_state
*allocated_bundle_states_chain
;
6181 /* All allocated but not used bundle states are in the following
6184 static struct bundle_state
*free_bundle_state_chain
;
6187 /* The following function returns a free bundle state. */
6189 static struct bundle_state
*
6190 get_free_bundle_state (void)
6192 struct bundle_state
*result
;
6194 if (free_bundle_state_chain
!= NULL
)
6196 result
= free_bundle_state_chain
;
6197 free_bundle_state_chain
= result
->next
;
6201 result
= xmalloc (sizeof (struct bundle_state
));
6202 result
->dfa_state
= xmalloc (dfa_state_size
);
6203 result
->allocated_states_chain
= allocated_bundle_states_chain
;
6204 allocated_bundle_states_chain
= result
;
6206 result
->unique_num
= bundle_states_num
++;
6211 /* The following function frees given bundle state. */
6214 free_bundle_state (struct bundle_state
*state
)
6216 state
->next
= free_bundle_state_chain
;
6217 free_bundle_state_chain
= state
;
6220 /* Start work with abstract data `bundle states'. */
6223 initiate_bundle_states (void)
6225 bundle_states_num
= 0;
6226 free_bundle_state_chain
= NULL
;
6227 allocated_bundle_states_chain
= NULL
;
6230 /* Finish work with abstract data `bundle states'. */
6233 finish_bundle_states (void)
6235 struct bundle_state
*curr_state
, *next_state
;
6237 for (curr_state
= allocated_bundle_states_chain
;
6239 curr_state
= next_state
)
6241 next_state
= curr_state
->allocated_states_chain
;
6242 free (curr_state
->dfa_state
);
6247 /* Hash table of the bundle states. The key is dfa_state and insn_num
6248 of the bundle states. */
6250 static htab_t bundle_state_table
;
6252 /* The function returns hash of BUNDLE_STATE. */
6255 bundle_state_hash (const void *bundle_state
)
6257 const struct bundle_state
*state
= (struct bundle_state
*) bundle_state
;
6260 for (result
= i
= 0; i
< dfa_state_size
; i
++)
6261 result
+= (((unsigned char *) state
->dfa_state
) [i
]
6262 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
6263 return result
+ state
->insn_num
;
6266 /* The function returns nonzero if the bundle state keys are equal. */
6269 bundle_state_eq_p (const void *bundle_state_1
, const void *bundle_state_2
)
6271 const struct bundle_state
* state1
= (struct bundle_state
*) bundle_state_1
;
6272 const struct bundle_state
* state2
= (struct bundle_state
*) bundle_state_2
;
6274 return (state1
->insn_num
== state2
->insn_num
6275 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
6276 dfa_state_size
) == 0);
6279 /* The function inserts the BUNDLE_STATE into the hash table. The
6280 function returns nonzero if the bundle has been inserted into the
6281 table. The table contains the best bundle state with given key. */
6284 insert_bundle_state (struct bundle_state
*bundle_state
)
6288 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, 1);
6289 if (*entry_ptr
== NULL
)
6291 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
6292 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
6293 *entry_ptr
= (void *) bundle_state
;
6296 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
6297 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
6298 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
6299 > bundle_state
->accumulated_insns_num
6300 || (((struct bundle_state
*)
6301 *entry_ptr
)->accumulated_insns_num
6302 == bundle_state
->accumulated_insns_num
6303 && ((struct bundle_state
*)
6304 *entry_ptr
)->branch_deviation
6305 > bundle_state
->branch_deviation
))))
6308 struct bundle_state temp
;
6310 temp
= *(struct bundle_state
*) *entry_ptr
;
6311 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
6312 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
6313 *bundle_state
= temp
;
6318 /* Start work with the hash table. */
6321 initiate_bundle_state_table (void)
6323 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
6327 /* Finish work with the hash table. */
6330 finish_bundle_state_table (void)
6332 htab_delete (bundle_state_table
);
6337 /* The following variable is a insn `nop' used to check bundle states
6338 with different number of inserted nops. */
6340 static rtx ia64_nop
;
6342 /* The following function tries to issue NOPS_NUM nops for the current
6343 state without advancing processor cycle. If it failed, the
6344 function returns FALSE and frees the current state. */
6347 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
6351 for (i
= 0; i
< nops_num
; i
++)
6352 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
6354 free_bundle_state (curr_state
);
6360 /* The following function tries to issue INSN for the current
6361 state without advancing processor cycle. If it failed, the
6362 function returns FALSE and frees the current state. */
6365 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
6367 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
6369 free_bundle_state (curr_state
);
6375 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6376 starting with ORIGINATOR without advancing processor cycle. If
6377 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6378 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6379 If it was successful, the function creates new bundle state and
6380 insert into the hash table and into `index_to_bundle_states'. */
6383 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
6384 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
6386 struct bundle_state
*curr_state
;
6388 curr_state
= get_free_bundle_state ();
6389 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
6390 curr_state
->insn
= insn
;
6391 curr_state
->insn_num
= originator
->insn_num
+ 1;
6392 curr_state
->cost
= originator
->cost
;
6393 curr_state
->originator
= originator
;
6394 curr_state
->before_nops_num
= before_nops_num
;
6395 curr_state
->after_nops_num
= 0;
6396 curr_state
->accumulated_insns_num
6397 = originator
->accumulated_insns_num
+ before_nops_num
;
6398 curr_state
->branch_deviation
= originator
->branch_deviation
;
6399 if (insn
== NULL_RTX
)
6401 else if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
6403 if (GET_MODE (insn
) == TImode
)
6405 if (!try_issue_nops (curr_state
, before_nops_num
))
6407 if (!try_issue_insn (curr_state
, insn
))
6409 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
6410 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
6411 && curr_state
->accumulated_insns_num
% 3 != 0)
6413 free_bundle_state (curr_state
);
6417 else if (GET_MODE (insn
) != TImode
)
6419 if (!try_issue_nops (curr_state
, before_nops_num
))
6421 if (!try_issue_insn (curr_state
, insn
))
6423 curr_state
->accumulated_insns_num
++;
6424 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6425 || asm_noperands (PATTERN (insn
)) >= 0)
6427 if (ia64_safe_type (insn
) == TYPE_L
)
6428 curr_state
->accumulated_insns_num
++;
6432 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
6433 state_transition (curr_state
->dfa_state
, NULL
);
6435 if (!try_issue_nops (curr_state
, before_nops_num
))
6437 if (!try_issue_insn (curr_state
, insn
))
6439 curr_state
->accumulated_insns_num
++;
6440 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6441 || asm_noperands (PATTERN (insn
)) >= 0)
6443 /* Finish bundle containing asm insn. */
6444 curr_state
->after_nops_num
6445 = 3 - curr_state
->accumulated_insns_num
% 3;
6446 curr_state
->accumulated_insns_num
6447 += 3 - curr_state
->accumulated_insns_num
% 3;
6449 else if (ia64_safe_type (insn
) == TYPE_L
)
6450 curr_state
->accumulated_insns_num
++;
6452 if (ia64_safe_type (insn
) == TYPE_B
)
6453 curr_state
->branch_deviation
6454 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
6455 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
6457 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
6460 struct bundle_state
*curr_state1
;
6461 struct bundle_state
*allocated_states_chain
;
6463 curr_state1
= get_free_bundle_state ();
6464 dfa_state
= curr_state1
->dfa_state
;
6465 allocated_states_chain
= curr_state1
->allocated_states_chain
;
6466 *curr_state1
= *curr_state
;
6467 curr_state1
->dfa_state
= dfa_state
;
6468 curr_state1
->allocated_states_chain
= allocated_states_chain
;
6469 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
6471 curr_state
= curr_state1
;
6473 if (!try_issue_nops (curr_state
,
6474 3 - curr_state
->accumulated_insns_num
% 3))
6476 curr_state
->after_nops_num
6477 = 3 - curr_state
->accumulated_insns_num
% 3;
6478 curr_state
->accumulated_insns_num
6479 += 3 - curr_state
->accumulated_insns_num
% 3;
6481 if (!insert_bundle_state (curr_state
))
6482 free_bundle_state (curr_state
);
6486 /* The following function returns position in the two window bundle
6490 get_max_pos (state_t state
)
6492 if (cpu_unit_reservation_p (state
, pos_6
))
6494 else if (cpu_unit_reservation_p (state
, pos_5
))
6496 else if (cpu_unit_reservation_p (state
, pos_4
))
6498 else if (cpu_unit_reservation_p (state
, pos_3
))
6500 else if (cpu_unit_reservation_p (state
, pos_2
))
6502 else if (cpu_unit_reservation_p (state
, pos_1
))
6508 /* The function returns code of a possible template for given position
6509 and state. The function should be called only with 2 values of
6510 position equal to 3 or 6. */
6513 get_template (state_t state
, int pos
)
6518 if (cpu_unit_reservation_p (state
, _0mii_
))
6520 else if (cpu_unit_reservation_p (state
, _0mmi_
))
6522 else if (cpu_unit_reservation_p (state
, _0mfi_
))
6524 else if (cpu_unit_reservation_p (state
, _0mmf_
))
6526 else if (cpu_unit_reservation_p (state
, _0bbb_
))
6528 else if (cpu_unit_reservation_p (state
, _0mbb_
))
6530 else if (cpu_unit_reservation_p (state
, _0mib_
))
6532 else if (cpu_unit_reservation_p (state
, _0mmb_
))
6534 else if (cpu_unit_reservation_p (state
, _0mfb_
))
6536 else if (cpu_unit_reservation_p (state
, _0mlx_
))
6541 if (cpu_unit_reservation_p (state
, _1mii_
))
6543 else if (cpu_unit_reservation_p (state
, _1mmi_
))
6545 else if (cpu_unit_reservation_p (state
, _1mfi_
))
6547 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
6549 else if (cpu_unit_reservation_p (state
, _1bbb_
))
6551 else if (cpu_unit_reservation_p (state
, _1mbb_
))
6553 else if (cpu_unit_reservation_p (state
, _1mib_
))
6555 else if (cpu_unit_reservation_p (state
, _1mmb_
))
6557 else if (cpu_unit_reservation_p (state
, _1mfb_
))
6559 else if (cpu_unit_reservation_p (state
, _1mlx_
))
6568 /* The following function returns an insn important for insn bundling
6569 followed by INSN and before TAIL. */
6572 get_next_important_insn (rtx insn
, rtx tail
)
6574 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
6576 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6577 && GET_CODE (PATTERN (insn
)) != USE
6578 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6583 /* The following function does insn bundling. Bundling means
6584 inserting templates and nop insns to fit insn groups into permitted
6585 templates. Instruction scheduling uses NDFA (non-deterministic
6586 finite automata) encoding informations about the templates and the
6587 inserted nops. Nondeterminism of the automata permits follows
6588 all possible insn sequences very fast.
6590 Unfortunately it is not possible to get information about inserting
6591 nop insns and used templates from the automata states. The
6592 automata only says that we can issue an insn possibly inserting
6593 some nops before it and using some template. Therefore insn
6594 bundling in this function is implemented by using DFA
6595 (deterministic finite automata). We follows all possible insn
6596 sequences by inserting 0-2 nops (that is what the NDFA describe for
6597 insn scheduling) before/after each insn being bundled. We know the
6598 start of simulated processor cycle from insn scheduling (insn
6599 starting a new cycle has TImode).
6601 Simple implementation of insn bundling would create enormous
6602 number of possible insn sequences satisfying information about new
6603 cycle ticks taken from the insn scheduling. To make the algorithm
6604 practical we use dynamic programming. Each decision (about
6605 inserting nops and implicitly about previous decisions) is described
6606 by structure bundle_state (see above). If we generate the same
6607 bundle state (key is automaton state after issuing the insns and
6608 nops for it), we reuse already generated one. As consequence we
6609 reject some decisions which cannot improve the solution and
6610 reduce memory for the algorithm.
6612 When we reach the end of EBB (extended basic block), we choose the
6613 best sequence and then, moving back in EBB, insert templates for
6614 the best alternative. The templates are taken from querying
6615 automaton state for each insn in chosen bundle states.
6617 So the algorithm makes two (forward and backward) passes through
6618 EBB. There is an additional forward pass through EBB for Itanium1
6619 processor. This pass inserts more nops to make dependency between
6620 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6623 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
6625 struct bundle_state
*curr_state
, *next_state
, *best_state
;
6626 rtx insn
, next_insn
;
6628 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
6629 int pos
= 0, max_pos
, template0
, template1
;
6632 enum attr_type type
;
6635 /* Count insns in the EBB. */
6636 for (insn
= NEXT_INSN (prev_head_insn
);
6637 insn
&& insn
!= tail
;
6638 insn
= NEXT_INSN (insn
))
6644 dfa_clean_insn_cache ();
6645 initiate_bundle_state_table ();
6646 index_to_bundle_states
= xmalloc ((insn_num
+ 2)
6647 * sizeof (struct bundle_state
*));
6648 /* First (forward) pass -- generation of bundle states. */
6649 curr_state
= get_free_bundle_state ();
6650 curr_state
->insn
= NULL
;
6651 curr_state
->before_nops_num
= 0;
6652 curr_state
->after_nops_num
= 0;
6653 curr_state
->insn_num
= 0;
6654 curr_state
->cost
= 0;
6655 curr_state
->accumulated_insns_num
= 0;
6656 curr_state
->branch_deviation
= 0;
6657 curr_state
->next
= NULL
;
6658 curr_state
->originator
= NULL
;
6659 state_reset (curr_state
->dfa_state
);
6660 index_to_bundle_states
[0] = curr_state
;
6662 /* Shift cycle mark if it is put on insn which could be ignored. */
6663 for (insn
= NEXT_INSN (prev_head_insn
);
6665 insn
= NEXT_INSN (insn
))
6667 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6668 || GET_CODE (PATTERN (insn
)) == USE
6669 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6670 && GET_MODE (insn
) == TImode
)
6672 PUT_MODE (insn
, VOIDmode
);
6673 for (next_insn
= NEXT_INSN (insn
);
6675 next_insn
= NEXT_INSN (next_insn
))
6676 if (INSN_P (next_insn
)
6677 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
6678 && GET_CODE (PATTERN (next_insn
)) != USE
6679 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
6681 PUT_MODE (next_insn
, TImode
);
6685 /* Froward pass: generation of bundle states. */
6686 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6691 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6692 || GET_CODE (PATTERN (insn
)) == USE
6693 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6695 type
= ia64_safe_type (insn
);
6696 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6698 index_to_bundle_states
[insn_num
] = NULL
;
6699 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
6701 curr_state
= next_state
)
6703 pos
= curr_state
->accumulated_insns_num
% 3;
6704 next_state
= curr_state
->next
;
6705 /* We must fill up the current bundle in order to start a
6706 subsequent asm insn in a new bundle. Asm insn is always
6707 placed in a separate bundle. */
6709 = (next_insn
!= NULL_RTX
6710 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
6711 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
6712 /* We may fill up the current bundle if it is the cycle end
6713 without a group barrier. */
6715 = (only_bundle_end_p
|| next_insn
== NULL_RTX
6716 || (GET_MODE (next_insn
) == TImode
6717 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
6718 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
6720 /* We need to insert 2 nops for cases like M_MII. To
6721 guarantee issuing all insns on the same cycle for
6722 Itanium 1, we need to issue 2 nops after the first M
6723 insn (MnnMII where n is a nop insn). */
6724 || ((type
== TYPE_M
|| type
== TYPE_A
)
6725 && ia64_tune
== PROCESSOR_ITANIUM
6726 && !bundle_end_p
&& pos
== 1))
6727 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
6729 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
6731 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
6734 if (index_to_bundle_states
[insn_num
] == NULL
)
6736 for (curr_state
= index_to_bundle_states
[insn_num
];
6738 curr_state
= curr_state
->next
)
6739 if (verbose
>= 2 && dump
)
6741 /* This structure is taken from generated code of the
6742 pipeline hazard recognizer (see file insn-attrtab.c).
6743 Please don't forget to change the structure if a new
6744 automaton is added to .md file. */
6747 unsigned short one_automaton_state
;
6748 unsigned short oneb_automaton_state
;
6749 unsigned short two_automaton_state
;
6750 unsigned short twob_automaton_state
;
6755 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6756 curr_state
->unique_num
,
6757 (curr_state
->originator
== NULL
6758 ? -1 : curr_state
->originator
->unique_num
),
6760 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6761 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6762 (ia64_tune
== PROCESSOR_ITANIUM
6763 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6764 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6768 if (index_to_bundle_states
[insn_num
] == NULL
)
6769 /* We should find a solution because the 2nd insn scheduling has
6772 /* Find a state corresponding to the best insn sequence. */
6774 for (curr_state
= index_to_bundle_states
[insn_num
];
6776 curr_state
= curr_state
->next
)
6777 /* We are just looking at the states with fully filled up last
6778 bundle. The first we prefer insn sequences with minimal cost
6779 then with minimal inserted nops and finally with branch insns
6780 placed in the 3rd slots. */
6781 if (curr_state
->accumulated_insns_num
% 3 == 0
6782 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
6783 || (best_state
->cost
== curr_state
->cost
6784 && (curr_state
->accumulated_insns_num
6785 < best_state
->accumulated_insns_num
6786 || (curr_state
->accumulated_insns_num
6787 == best_state
->accumulated_insns_num
6788 && curr_state
->branch_deviation
6789 < best_state
->branch_deviation
)))))
6790 best_state
= curr_state
;
6791 /* Second (backward) pass: adding nops and templates. */
6792 insn_num
= best_state
->before_nops_num
;
6793 template0
= template1
= -1;
6794 for (curr_state
= best_state
;
6795 curr_state
->originator
!= NULL
;
6796 curr_state
= curr_state
->originator
)
6798 insn
= curr_state
->insn
;
6799 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6800 || asm_noperands (PATTERN (insn
)) >= 0);
6802 if (verbose
>= 2 && dump
)
6806 unsigned short one_automaton_state
;
6807 unsigned short oneb_automaton_state
;
6808 unsigned short two_automaton_state
;
6809 unsigned short twob_automaton_state
;
6814 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6815 curr_state
->unique_num
,
6816 (curr_state
->originator
== NULL
6817 ? -1 : curr_state
->originator
->unique_num
),
6819 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6820 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6821 (ia64_tune
== PROCESSOR_ITANIUM
6822 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6823 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6826 /* Find the position in the current bundle window. The window can
6827 contain at most two bundles. Two bundle window means that
6828 the processor will make two bundle rotation. */
6829 max_pos
= get_max_pos (curr_state
->dfa_state
);
6831 /* The following (negative template number) means that the
6832 processor did one bundle rotation. */
6833 || (max_pos
== 3 && template0
< 0))
6835 /* We are at the end of the window -- find template(s) for
6839 template0
= get_template (curr_state
->dfa_state
, 3);
6842 template1
= get_template (curr_state
->dfa_state
, 3);
6843 template0
= get_template (curr_state
->dfa_state
, 6);
6846 if (max_pos
> 3 && template1
< 0)
6847 /* It may happen when we have the stop inside a bundle. */
6851 template1
= get_template (curr_state
->dfa_state
, 3);
6855 /* Emit nops after the current insn. */
6856 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
6859 emit_insn_after (nop
, insn
);
6865 /* We are at the start of a bundle: emit the template
6866 (it should be defined). */
6869 b
= gen_bundle_selector (GEN_INT (template0
));
6870 ia64_emit_insn_before (b
, nop
);
6871 /* If we have two bundle window, we make one bundle
6872 rotation. Otherwise template0 will be undefined
6873 (negative value). */
6874 template0
= template1
;
6878 /* Move the position backward in the window. Group barrier has
6879 no slot. Asm insn takes all bundle. */
6880 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
6881 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6882 && asm_noperands (PATTERN (insn
)) < 0)
6884 /* Long insn takes 2 slots. */
6885 if (ia64_safe_type (insn
) == TYPE_L
)
6890 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
6891 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6892 && asm_noperands (PATTERN (insn
)) < 0)
6894 /* The current insn is at the bundle start: emit the
6898 b
= gen_bundle_selector (GEN_INT (template0
));
6899 ia64_emit_insn_before (b
, insn
);
6900 b
= PREV_INSN (insn
);
6902 /* See comment above in analogous place for emitting nops
6904 template0
= template1
;
6907 /* Emit nops after the current insn. */
6908 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
6911 ia64_emit_insn_before (nop
, insn
);
6912 nop
= PREV_INSN (insn
);
6919 /* See comment above in analogous place for emitting nops
6923 b
= gen_bundle_selector (GEN_INT (template0
));
6924 ia64_emit_insn_before (b
, insn
);
6925 b
= PREV_INSN (insn
);
6927 template0
= template1
;
6932 if (ia64_tune
== PROCESSOR_ITANIUM
)
6933 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
6934 Itanium1 has a strange design, if the distance between an insn
6935 and dependent MM-insn is less 4 then we have a 6 additional
6936 cycles stall. So we make the distance equal to 4 cycles if it
6938 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6943 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6944 || GET_CODE (PATTERN (insn
)) == USE
6945 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6947 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6948 if (INSN_UID (insn
) < clocks_length
&& add_cycles
[INSN_UID (insn
)])
6949 /* We found a MM-insn which needs additional cycles. */
6955 /* Now we are searching for a template of the bundle in
6956 which the MM-insn is placed and the position of the
6957 insn in the bundle (0, 1, 2). Also we are searching
6958 for that there is a stop before the insn. */
6959 last
= prev_active_insn (insn
);
6960 pred_stop_p
= recog_memoized (last
) == CODE_FOR_insn_group_barrier
;
6962 last
= prev_active_insn (last
);
6964 for (;; last
= prev_active_insn (last
))
6965 if (recog_memoized (last
) == CODE_FOR_bundle_selector
)
6967 template0
= XINT (XVECEXP (PATTERN (last
), 0, 0), 0);
6969 /* The insn is in MLX bundle. Change the template
6970 onto MFI because we will add nops before the
6971 insn. It simplifies subsequent code a lot. */
6973 = gen_bundle_selector (const2_rtx
); /* -> MFI */
6976 else if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
6977 && (ia64_safe_itanium_class (last
)
6978 != ITANIUM_CLASS_IGNORE
))
6980 /* Some check of correctness: the stop is not at the
6981 bundle start, there are no more 3 insns in the bundle,
6982 and the MM-insn is not at the start of bundle with
6984 if ((pred_stop_p
&& n
== 0) || n
> 2
6985 || (template0
== 9 && n
!= 0))
6987 /* Put nops after the insn in the bundle. */
6988 for (j
= 3 - n
; j
> 0; j
--)
6989 ia64_emit_insn_before (gen_nop (), insn
);
6990 /* It takes into account that we will add more N nops
6991 before the insn lately -- please see code below. */
6992 add_cycles
[INSN_UID (insn
)]--;
6993 if (!pred_stop_p
|| add_cycles
[INSN_UID (insn
)])
6994 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6997 add_cycles
[INSN_UID (insn
)]--;
6998 for (i
= add_cycles
[INSN_UID (insn
)]; i
> 0; i
--)
7000 /* Insert "MII;" template. */
7001 ia64_emit_insn_before (gen_bundle_selector (const0_rtx
),
7003 ia64_emit_insn_before (gen_nop (), insn
);
7004 ia64_emit_insn_before (gen_nop (), insn
);
7007 /* To decrease code size, we use "MI;I;"
7009 ia64_emit_insn_before
7010 (gen_insn_group_barrier (GEN_INT (3)), insn
);
7013 ia64_emit_insn_before (gen_nop (), insn
);
7014 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7017 /* Put the MM-insn in the same slot of a bundle with the
7018 same template as the original one. */
7019 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0
)),
7021 /* To put the insn in the same slot, add necessary number
7023 for (j
= n
; j
> 0; j
--)
7024 ia64_emit_insn_before (gen_nop (), insn
);
7025 /* Put the stop if the original bundle had it. */
7027 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7031 free (index_to_bundle_states
);
7032 finish_bundle_state_table ();
7034 dfa_clean_insn_cache ();
7037 /* The following function is called at the end of scheduling BB or
7038 EBB. After reload, it inserts stop bits and does insn bundling. */
7041 ia64_sched_finish (FILE *dump
, int sched_verbose
)
7044 fprintf (dump
, "// Finishing schedule.\n");
7045 if (!reload_completed
)
7047 if (reload_completed
)
7049 final_emit_insn_group_barriers (dump
);
7050 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
7051 current_sched_info
->next_tail
);
7052 if (sched_verbose
&& dump
)
7053 fprintf (dump
, "// finishing %d-%d\n",
7054 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
7055 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
7061 /* The following function inserts stop bits in scheduled BB or EBB. */
7064 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
7067 int need_barrier_p
= 0;
7068 rtx prev_insn
= NULL_RTX
;
7070 init_insn_group_barriers ();
7072 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7073 insn
!= current_sched_info
->next_tail
;
7074 insn
= NEXT_INSN (insn
))
7076 if (GET_CODE (insn
) == BARRIER
)
7078 rtx last
= prev_active_insn (insn
);
7082 if (GET_CODE (last
) == JUMP_INSN
7083 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
7084 last
= prev_active_insn (last
);
7085 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7086 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
7088 init_insn_group_barriers ();
7090 prev_insn
= NULL_RTX
;
7092 else if (INSN_P (insn
))
7094 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
7096 init_insn_group_barriers ();
7098 prev_insn
= NULL_RTX
;
7100 else if (need_barrier_p
|| group_barrier_needed_p (insn
))
7102 if (TARGET_EARLY_STOP_BITS
)
7107 last
!= current_sched_info
->prev_head
;
7108 last
= PREV_INSN (last
))
7109 if (INSN_P (last
) && GET_MODE (last
) == TImode
7110 && stops_p
[INSN_UID (last
)])
7112 if (last
== current_sched_info
->prev_head
)
7114 last
= prev_active_insn (last
);
7116 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7117 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7119 init_insn_group_barriers ();
7120 for (last
= NEXT_INSN (last
);
7122 last
= NEXT_INSN (last
))
7124 group_barrier_needed_p (last
);
7128 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7130 init_insn_group_barriers ();
7132 group_barrier_needed_p (insn
);
7133 prev_insn
= NULL_RTX
;
7135 else if (recog_memoized (insn
) >= 0)
7137 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
7138 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
7139 || asm_noperands (PATTERN (insn
)) >= 0);
7146 /* If the following function returns TRUE, we will use the the DFA
7150 ia64_first_cycle_multipass_dfa_lookahead (void)
7152 return (reload_completed
? 6 : 4);
7155 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7158 ia64_init_dfa_pre_cycle_insn (void)
7160 if (temp_dfa_state
== NULL
)
7162 dfa_state_size
= state_size ();
7163 temp_dfa_state
= xmalloc (dfa_state_size
);
7164 prev_cycle_state
= xmalloc (dfa_state_size
);
7166 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
7167 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
7168 recog_memoized (dfa_pre_cycle_insn
);
7169 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7170 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
7171 recog_memoized (dfa_stop_insn
);
7174 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7175 used by the DFA insn scheduler. */
7178 ia64_dfa_pre_cycle_insn (void)
7180 return dfa_pre_cycle_insn
;
7183 /* The following function returns TRUE if PRODUCER (of type ilog or
7184 ld) produces address for CONSUMER (of type st or stf). */
7187 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
7191 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7193 dest
= ia64_single_set (producer
);
7194 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7195 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7197 if (GET_CODE (reg
) == SUBREG
)
7198 reg
= SUBREG_REG (reg
);
7199 dest
= ia64_single_set (consumer
);
7200 if (dest
== NULL_RTX
|| (mem
= SET_DEST (dest
)) == NULL_RTX
7201 || GET_CODE (mem
) != MEM
)
7203 return reg_mentioned_p (reg
, mem
);
7206 /* The following function returns TRUE if PRODUCER (of type ilog or
7207 ld) produces address for CONSUMER (of type ld or fld). */
7210 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
7212 rtx dest
, src
, reg
, mem
;
7214 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7216 dest
= ia64_single_set (producer
);
7217 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7218 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7220 if (GET_CODE (reg
) == SUBREG
)
7221 reg
= SUBREG_REG (reg
);
7222 src
= ia64_single_set (consumer
);
7223 if (src
== NULL_RTX
|| (mem
= SET_SRC (src
)) == NULL_RTX
)
7225 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
7226 mem
= XVECEXP (mem
, 0, 0);
7227 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
7228 mem
= XEXP (mem
, 0);
7230 /* Note that LO_SUM is used for GOT loads. */
7231 if (GET_CODE (mem
) != LO_SUM
&& GET_CODE (mem
) != MEM
)
7234 return reg_mentioned_p (reg
, mem
);
7237 /* The following function returns TRUE if INSN produces address for a
7238 load/store insn. We will place such insns into M slot because it
7239 decreases its latency time. */
7242 ia64_produce_address_p (rtx insn
)
7248 /* Emit pseudo-ops for the assembler to describe predicate relations.
7249 At present this assumes that we only consider predicate pairs to
7250 be mutex, and that the assembler can deduce proper values from
7251 straight-line code. */
7254 emit_predicate_relation_info (void)
7258 FOR_EACH_BB_REVERSE (bb
)
7261 rtx head
= BB_HEAD (bb
);
7263 /* We only need such notes at code labels. */
7264 if (GET_CODE (head
) != CODE_LABEL
)
7266 if (GET_CODE (NEXT_INSN (head
)) == NOTE
7267 && NOTE_LINE_NUMBER (NEXT_INSN (head
)) == NOTE_INSN_BASIC_BLOCK
)
7268 head
= NEXT_INSN (head
);
7270 for (r
= PR_REG (0); r
< PR_REG (64); r
+= 2)
7271 if (REGNO_REG_SET_P (bb
->global_live_at_start
, r
))
7273 rtx p
= gen_rtx_REG (BImode
, r
);
7274 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
7275 if (head
== BB_END (bb
))
7281 /* Look for conditional calls that do not return, and protect predicate
7282 relations around them. Otherwise the assembler will assume the call
7283 returns, and complain about uses of call-clobbered predicates after
7285 FOR_EACH_BB_REVERSE (bb
)
7287 rtx insn
= BB_HEAD (bb
);
7291 if (GET_CODE (insn
) == CALL_INSN
7292 && GET_CODE (PATTERN (insn
)) == COND_EXEC
7293 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
7295 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
7296 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
7297 if (BB_HEAD (bb
) == insn
)
7299 if (BB_END (bb
) == insn
)
7303 if (insn
== BB_END (bb
))
7305 insn
= NEXT_INSN (insn
);
7310 /* Perform machine dependent operations on the rtl chain INSNS. */
7315 /* We are freeing block_for_insn in the toplev to keep compatibility
7316 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7317 compute_bb_for_insn ();
7319 /* If optimizing, we'll have split before scheduling. */
7321 split_all_insns (0);
7323 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7324 non-optimizing bootstrap. */
7325 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
7327 if (ia64_flag_schedule_insns2
)
7329 timevar_push (TV_SCHED2
);
7330 ia64_final_schedule
= 1;
7332 initiate_bundle_states ();
7333 ia64_nop
= make_insn_raw (gen_nop ());
7334 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
7335 recog_memoized (ia64_nop
);
7336 clocks_length
= get_max_uid () + 1;
7337 stops_p
= xcalloc (1, clocks_length
);
7338 if (ia64_tune
== PROCESSOR_ITANIUM
)
7340 clocks
= xcalloc (clocks_length
, sizeof (int));
7341 add_cycles
= xcalloc (clocks_length
, sizeof (int));
7343 if (ia64_tune
== PROCESSOR_ITANIUM2
)
7345 pos_1
= get_cpu_unit_code ("2_1");
7346 pos_2
= get_cpu_unit_code ("2_2");
7347 pos_3
= get_cpu_unit_code ("2_3");
7348 pos_4
= get_cpu_unit_code ("2_4");
7349 pos_5
= get_cpu_unit_code ("2_5");
7350 pos_6
= get_cpu_unit_code ("2_6");
7351 _0mii_
= get_cpu_unit_code ("2b_0mii.");
7352 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
7353 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
7354 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
7355 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
7356 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
7357 _0mib_
= get_cpu_unit_code ("2b_0mib.");
7358 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
7359 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
7360 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
7361 _1mii_
= get_cpu_unit_code ("2b_1mii.");
7362 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
7363 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
7364 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
7365 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
7366 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
7367 _1mib_
= get_cpu_unit_code ("2b_1mib.");
7368 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
7369 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
7370 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
7374 pos_1
= get_cpu_unit_code ("1_1");
7375 pos_2
= get_cpu_unit_code ("1_2");
7376 pos_3
= get_cpu_unit_code ("1_3");
7377 pos_4
= get_cpu_unit_code ("1_4");
7378 pos_5
= get_cpu_unit_code ("1_5");
7379 pos_6
= get_cpu_unit_code ("1_6");
7380 _0mii_
= get_cpu_unit_code ("1b_0mii.");
7381 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
7382 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
7383 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
7384 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
7385 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
7386 _0mib_
= get_cpu_unit_code ("1b_0mib.");
7387 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
7388 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
7389 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
7390 _1mii_
= get_cpu_unit_code ("1b_1mii.");
7391 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
7392 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
7393 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
7394 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
7395 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
7396 _1mib_
= get_cpu_unit_code ("1b_1mib.");
7397 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
7398 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
7399 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
7401 schedule_ebbs (dump_file
);
7402 finish_bundle_states ();
7403 if (ia64_tune
== PROCESSOR_ITANIUM
)
7409 emit_insn_group_barriers (dump_file
);
7411 ia64_final_schedule
= 0;
7412 timevar_pop (TV_SCHED2
);
7415 emit_all_insn_group_barriers (dump_file
);
7417 /* A call must not be the last instruction in a function, so that the
7418 return address is still within the function, so that unwinding works
7419 properly. Note that IA-64 differs from dwarf2 on this point. */
7420 if (flag_unwind_tables
|| (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7425 insn
= get_last_insn ();
7426 if (! INSN_P (insn
))
7427 insn
= prev_active_insn (insn
);
7428 /* Skip over insns that expand to nothing. */
7429 while (GET_CODE (insn
) == INSN
&& get_attr_empty (insn
) == EMPTY_YES
)
7431 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
7432 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
7434 insn
= prev_active_insn (insn
);
7436 if (GET_CODE (insn
) == CALL_INSN
)
7439 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7440 emit_insn (gen_break_f ());
7441 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7445 emit_predicate_relation_info ();
7447 if (ia64_flag_var_tracking
)
7449 timevar_push (TV_VAR_TRACKING
);
7450 variable_tracking_main ();
7451 timevar_pop (TV_VAR_TRACKING
);
7455 /* Return true if REGNO is used by the epilogue. */
7458 ia64_epilogue_uses (int regno
)
7463 /* With a call to a function in another module, we will write a new
7464 value to "gp". After returning from such a call, we need to make
7465 sure the function restores the original gp-value, even if the
7466 function itself does not use the gp anymore. */
7467 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
7469 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7470 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7471 /* For functions defined with the syscall_linkage attribute, all
7472 input registers are marked as live at all function exits. This
7473 prevents the register allocator from using the input registers,
7474 which in turn makes it possible to restart a system call after
7475 an interrupt without having to save/restore the input registers.
7476 This also prevents kernel data from leaking to application code. */
7477 return lookup_attribute ("syscall_linkage",
7478 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
7481 /* Conditional return patterns can't represent the use of `b0' as
7482 the return address, so we force the value live this way. */
7486 /* Likewise for ar.pfs, which is used by br.ret. */
7494 /* Return true if REGNO is used by the frame unwinder. */
7497 ia64_eh_uses (int regno
)
7499 if (! reload_completed
)
7502 if (current_frame_info
.reg_save_b0
7503 && regno
== current_frame_info
.reg_save_b0
)
7505 if (current_frame_info
.reg_save_pr
7506 && regno
== current_frame_info
.reg_save_pr
)
7508 if (current_frame_info
.reg_save_ar_pfs
7509 && regno
== current_frame_info
.reg_save_ar_pfs
)
7511 if (current_frame_info
.reg_save_ar_unat
7512 && regno
== current_frame_info
.reg_save_ar_unat
)
7514 if (current_frame_info
.reg_save_ar_lc
7515 && regno
== current_frame_info
.reg_save_ar_lc
)
7521 /* Return true if this goes in small data/bss. */
7523 /* ??? We could also support own long data here. Generating movl/add/ld8
7524 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7525 code faster because there is one less load. This also includes incomplete
7526 types which can't go in sdata/sbss. */
7529 ia64_in_small_data_p (tree exp
)
7531 if (TARGET_NO_SDATA
)
7534 /* We want to merge strings, so we never consider them small data. */
7535 if (TREE_CODE (exp
) == STRING_CST
)
7538 /* Functions are never small data. */
7539 if (TREE_CODE (exp
) == FUNCTION_DECL
)
7542 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
7544 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
7546 if (strcmp (section
, ".sdata") == 0
7547 || strncmp (section
, ".sdata.", 7) == 0
7548 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
7549 || strcmp (section
, ".sbss") == 0
7550 || strncmp (section
, ".sbss.", 6) == 0
7551 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0)
7556 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
7558 /* If this is an incomplete type with size 0, then we can't put it
7559 in sdata because it might be too big when completed. */
7560 if (size
> 0 && size
<= ia64_section_threshold
)
7567 /* Output assembly directives for prologue regions. */
7569 /* The current basic block number. */
7571 static bool last_block
;
7573 /* True if we need a copy_state command at the start of the next block. */
7575 static bool need_copy_state
;
7577 /* The function emits unwind directives for the start of an epilogue. */
7580 process_epilogue (void)
7582 /* If this isn't the last block of the function, then we need to label the
7583 current state, and copy it back in at the start of the next block. */
7587 fprintf (asm_out_file
, "\t.label_state %d\n",
7588 ++cfun
->machine
->state_num
);
7589 need_copy_state
= true;
7592 fprintf (asm_out_file
, "\t.restore sp\n");
7595 /* This function processes a SET pattern looking for specific patterns
7596 which result in emitting an assembly directive required for unwinding. */
7599 process_set (FILE *asm_out_file
, rtx pat
)
7601 rtx src
= SET_SRC (pat
);
7602 rtx dest
= SET_DEST (pat
);
7603 int src_regno
, dest_regno
;
7605 /* Look for the ALLOC insn. */
7606 if (GET_CODE (src
) == UNSPEC_VOLATILE
7607 && XINT (src
, 1) == UNSPECV_ALLOC
7608 && GET_CODE (dest
) == REG
)
7610 dest_regno
= REGNO (dest
);
7612 /* If this is the final destination for ar.pfs, then this must
7613 be the alloc in the prologue. */
7614 if (dest_regno
== current_frame_info
.reg_save_ar_pfs
)
7615 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
7616 ia64_dbx_register_number (dest_regno
));
7619 /* This must be an alloc before a sibcall. We must drop the
7620 old frame info. The easiest way to drop the old frame
7621 info is to ensure we had a ".restore sp" directive
7622 followed by a new prologue. If the procedure doesn't
7623 have a memory-stack frame, we'll issue a dummy ".restore
7625 if (current_frame_info
.total_size
== 0 && !frame_pointer_needed
)
7626 /* if haven't done process_epilogue() yet, do it now */
7627 process_epilogue ();
7628 fprintf (asm_out_file
, "\t.prologue\n");
7633 /* Look for SP = .... */
7634 if (GET_CODE (dest
) == REG
&& REGNO (dest
) == STACK_POINTER_REGNUM
)
7636 if (GET_CODE (src
) == PLUS
)
7638 rtx op0
= XEXP (src
, 0);
7639 rtx op1
= XEXP (src
, 1);
7640 if (op0
== dest
&& GET_CODE (op1
) == CONST_INT
)
7642 if (INTVAL (op1
) < 0)
7643 fprintf (asm_out_file
, "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
7646 process_epilogue ();
7651 else if (GET_CODE (src
) == REG
7652 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
)
7653 process_epilogue ();
7660 /* Register move we need to look at. */
7661 if (GET_CODE (dest
) == REG
&& GET_CODE (src
) == REG
)
7663 src_regno
= REGNO (src
);
7664 dest_regno
= REGNO (dest
);
7669 /* Saving return address pointer. */
7670 if (dest_regno
!= current_frame_info
.reg_save_b0
)
7672 fprintf (asm_out_file
, "\t.save rp, r%d\n",
7673 ia64_dbx_register_number (dest_regno
));
7677 if (dest_regno
!= current_frame_info
.reg_save_pr
)
7679 fprintf (asm_out_file
, "\t.save pr, r%d\n",
7680 ia64_dbx_register_number (dest_regno
));
7683 case AR_UNAT_REGNUM
:
7684 if (dest_regno
!= current_frame_info
.reg_save_ar_unat
)
7686 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
7687 ia64_dbx_register_number (dest_regno
));
7691 if (dest_regno
!= current_frame_info
.reg_save_ar_lc
)
7693 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
7694 ia64_dbx_register_number (dest_regno
));
7697 case STACK_POINTER_REGNUM
:
7698 if (dest_regno
!= HARD_FRAME_POINTER_REGNUM
7699 || ! frame_pointer_needed
)
7701 fprintf (asm_out_file
, "\t.vframe r%d\n",
7702 ia64_dbx_register_number (dest_regno
));
7706 /* Everything else should indicate being stored to memory. */
7711 /* Memory store we need to look at. */
7712 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
7718 if (GET_CODE (XEXP (dest
, 0)) == REG
)
7720 base
= XEXP (dest
, 0);
7723 else if (GET_CODE (XEXP (dest
, 0)) == PLUS
7724 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
)
7726 base
= XEXP (XEXP (dest
, 0), 0);
7727 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
7732 if (base
== hard_frame_pointer_rtx
)
7734 saveop
= ".savepsp";
7737 else if (base
== stack_pointer_rtx
)
7742 src_regno
= REGNO (src
);
7746 if (current_frame_info
.reg_save_b0
!= 0)
7748 fprintf (asm_out_file
, "\t%s rp, %ld\n", saveop
, off
);
7752 if (current_frame_info
.reg_save_pr
!= 0)
7754 fprintf (asm_out_file
, "\t%s pr, %ld\n", saveop
, off
);
7758 if (current_frame_info
.reg_save_ar_lc
!= 0)
7760 fprintf (asm_out_file
, "\t%s ar.lc, %ld\n", saveop
, off
);
7764 if (current_frame_info
.reg_save_ar_pfs
!= 0)
7766 fprintf (asm_out_file
, "\t%s ar.pfs, %ld\n", saveop
, off
);
7769 case AR_UNAT_REGNUM
:
7770 if (current_frame_info
.reg_save_ar_unat
!= 0)
7772 fprintf (asm_out_file
, "\t%s ar.unat, %ld\n", saveop
, off
);
7779 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
7780 1 << (src_regno
- GR_REG (4)));
7788 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
7789 1 << (src_regno
- BR_REG (1)));
7796 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
7797 1 << (src_regno
- FR_REG (2)));
7800 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7801 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7802 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7803 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7804 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
7805 1 << (src_regno
- FR_REG (12)));
7817 /* This function looks at a single insn and emits any directives
7818 required to unwind this insn. */
7820 process_for_unwind_directive (FILE *asm_out_file
, rtx insn
)
7822 if (flag_unwind_tables
7823 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7827 if (GET_CODE (insn
) == NOTE
7828 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
7830 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
7832 /* Restore unwind state from immediately before the epilogue. */
7833 if (need_copy_state
)
7835 fprintf (asm_out_file
, "\t.body\n");
7836 fprintf (asm_out_file
, "\t.copy_state %d\n",
7837 cfun
->machine
->state_num
);
7838 need_copy_state
= false;
7842 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
7845 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
7847 pat
= XEXP (pat
, 0);
7849 pat
= PATTERN (insn
);
7851 switch (GET_CODE (pat
))
7854 process_set (asm_out_file
, pat
);
7860 int limit
= XVECLEN (pat
, 0);
7861 for (par_index
= 0; par_index
< limit
; par_index
++)
7863 rtx x
= XVECEXP (pat
, 0, par_index
);
7864 if (GET_CODE (x
) == SET
)
7865 process_set (asm_out_file
, x
);
7878 ia64_init_builtins (void)
7880 tree psi_type_node
= build_pointer_type (integer_type_node
);
7881 tree pdi_type_node
= build_pointer_type (long_integer_type_node
);
7883 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
7884 tree si_ftype_psi_si_si
7885 = build_function_type_list (integer_type_node
,
7886 psi_type_node
, integer_type_node
,
7887 integer_type_node
, NULL_TREE
);
7889 /* __sync_val_compare_and_swap_di */
7890 tree di_ftype_pdi_di_di
7891 = build_function_type_list (long_integer_type_node
,
7892 pdi_type_node
, long_integer_type_node
,
7893 long_integer_type_node
, NULL_TREE
);
7894 /* __sync_bool_compare_and_swap_di */
7895 tree si_ftype_pdi_di_di
7896 = build_function_type_list (integer_type_node
,
7897 pdi_type_node
, long_integer_type_node
,
7898 long_integer_type_node
, NULL_TREE
);
7899 /* __sync_synchronize */
7900 tree void_ftype_void
7901 = build_function_type (void_type_node
, void_list_node
);
7903 /* __sync_lock_test_and_set_si */
7904 tree si_ftype_psi_si
7905 = build_function_type_list (integer_type_node
,
7906 psi_type_node
, integer_type_node
, NULL_TREE
);
7908 /* __sync_lock_test_and_set_di */
7909 tree di_ftype_pdi_di
7910 = build_function_type_list (long_integer_type_node
,
7911 pdi_type_node
, long_integer_type_node
,
7914 /* __sync_lock_release_si */
7916 = build_function_type_list (void_type_node
, psi_type_node
, NULL_TREE
);
7918 /* __sync_lock_release_di */
7920 = build_function_type_list (void_type_node
, pdi_type_node
, NULL_TREE
);
7925 /* The __fpreg type. */
7926 fpreg_type
= make_node (REAL_TYPE
);
7927 /* ??? The back end should know to load/save __fpreg variables using
7928 the ldf.fill and stf.spill instructions. */
7929 TYPE_PRECISION (fpreg_type
) = 80;
7930 layout_type (fpreg_type
);
7931 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
7933 /* The __float80 type. */
7934 float80_type
= make_node (REAL_TYPE
);
7935 TYPE_PRECISION (float80_type
) = 80;
7936 layout_type (float80_type
);
7937 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
7939 /* The __float128 type. */
7942 tree float128_type
= make_node (REAL_TYPE
);
7943 TYPE_PRECISION (float128_type
) = 128;
7944 layout_type (float128_type
);
7945 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
7948 /* Under HPUX, this is a synonym for "long double". */
7949 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
7952 #define def_builtin(name, type, code) \
7953 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, \
7956 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si
,
7957 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
);
7958 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di
,
7959 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
);
7960 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si
,
7961 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
);
7962 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di
,
7963 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
);
7965 def_builtin ("__sync_synchronize", void_ftype_void
,
7966 IA64_BUILTIN_SYNCHRONIZE
);
7968 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si
,
7969 IA64_BUILTIN_LOCK_TEST_AND_SET_SI
);
7970 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di
,
7971 IA64_BUILTIN_LOCK_TEST_AND_SET_DI
);
7972 def_builtin ("__sync_lock_release_si", void_ftype_psi
,
7973 IA64_BUILTIN_LOCK_RELEASE_SI
);
7974 def_builtin ("__sync_lock_release_di", void_ftype_pdi
,
7975 IA64_BUILTIN_LOCK_RELEASE_DI
);
7977 def_builtin ("__builtin_ia64_bsp",
7978 build_function_type (ptr_type_node
, void_list_node
),
7981 def_builtin ("__builtin_ia64_flushrs",
7982 build_function_type (void_type_node
, void_list_node
),
7983 IA64_BUILTIN_FLUSHRS
);
7985 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si
,
7986 IA64_BUILTIN_FETCH_AND_ADD_SI
);
7987 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si
,
7988 IA64_BUILTIN_FETCH_AND_SUB_SI
);
7989 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si
,
7990 IA64_BUILTIN_FETCH_AND_OR_SI
);
7991 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si
,
7992 IA64_BUILTIN_FETCH_AND_AND_SI
);
7993 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si
,
7994 IA64_BUILTIN_FETCH_AND_XOR_SI
);
7995 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si
,
7996 IA64_BUILTIN_FETCH_AND_NAND_SI
);
7998 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si
,
7999 IA64_BUILTIN_ADD_AND_FETCH_SI
);
8000 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si
,
8001 IA64_BUILTIN_SUB_AND_FETCH_SI
);
8002 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si
,
8003 IA64_BUILTIN_OR_AND_FETCH_SI
);
8004 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si
,
8005 IA64_BUILTIN_AND_AND_FETCH_SI
);
8006 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si
,
8007 IA64_BUILTIN_XOR_AND_FETCH_SI
);
8008 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si
,
8009 IA64_BUILTIN_NAND_AND_FETCH_SI
);
8011 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di
,
8012 IA64_BUILTIN_FETCH_AND_ADD_DI
);
8013 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di
,
8014 IA64_BUILTIN_FETCH_AND_SUB_DI
);
8015 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di
,
8016 IA64_BUILTIN_FETCH_AND_OR_DI
);
8017 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di
,
8018 IA64_BUILTIN_FETCH_AND_AND_DI
);
8019 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di
,
8020 IA64_BUILTIN_FETCH_AND_XOR_DI
);
8021 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di
,
8022 IA64_BUILTIN_FETCH_AND_NAND_DI
);
8024 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di
,
8025 IA64_BUILTIN_ADD_AND_FETCH_DI
);
8026 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di
,
8027 IA64_BUILTIN_SUB_AND_FETCH_DI
);
8028 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di
,
8029 IA64_BUILTIN_OR_AND_FETCH_DI
);
8030 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di
,
8031 IA64_BUILTIN_AND_AND_FETCH_DI
);
8032 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di
,
8033 IA64_BUILTIN_XOR_AND_FETCH_DI
);
8034 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di
,
8035 IA64_BUILTIN_NAND_AND_FETCH_DI
);
8040 /* Expand fetch_and_op intrinsics. The basic code sequence is:
8048 cmpxchgsz.acq tmp = [ptr], tmp
8049 } while (tmp != ret)
8053 ia64_expand_fetch_and_op (optab binoptab
, enum machine_mode mode
,
8054 tree arglist
, rtx target
)
8056 rtx ret
, label
, tmp
, ccv
, insn
, mem
, value
;
8059 arg0
= TREE_VALUE (arglist
);
8060 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8061 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
8062 #ifdef POINTERS_EXTEND_UNSIGNED
8063 if (GET_MODE(mem
) != Pmode
)
8064 mem
= convert_memory_address (Pmode
, mem
);
8066 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8068 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8069 MEM_VOLATILE_P (mem
) = 1;
8071 if (target
&& register_operand (target
, mode
))
8074 ret
= gen_reg_rtx (mode
);
8076 emit_insn (gen_mf ());
8078 /* Special case for fetchadd instructions. */
8079 if (binoptab
== add_optab
&& fetchadd_operand (value
, VOIDmode
))
8082 insn
= gen_fetchadd_acq_si (ret
, mem
, value
);
8084 insn
= gen_fetchadd_acq_di (ret
, mem
, value
);
8089 tmp
= gen_reg_rtx (mode
);
8090 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8091 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8092 emit_move_insn (tmp
, mem
);
8094 label
= gen_label_rtx ();
8096 emit_move_insn (ret
, tmp
);
8097 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8099 /* Perform the specific operation. Special case NAND by noticing
8100 one_cmpl_optab instead. */
8101 if (binoptab
== one_cmpl_optab
)
8103 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8104 binoptab
= and_optab
;
8106 tmp
= expand_binop (mode
, binoptab
, tmp
, value
, tmp
, 1, OPTAB_WIDEN
);
8109 insn
= gen_cmpxchg_acq_si (tmp
, mem
, tmp
, ccv
);
8111 insn
= gen_cmpxchg_acq_di (tmp
, mem
, tmp
, ccv
);
8114 emit_cmp_and_jump_insns (tmp
, ret
, NE
, 0, mode
, 1, label
);
8119 /* Expand op_and_fetch intrinsics. The basic code sequence is:
8126 ret = tmp <op> value;
8127 cmpxchgsz.acq tmp = [ptr], ret
8128 } while (tmp != old)
8132 ia64_expand_op_and_fetch (optab binoptab
, enum machine_mode mode
,
8133 tree arglist
, rtx target
)
8135 rtx old
, label
, tmp
, ret
, ccv
, insn
, mem
, value
;
8138 arg0
= TREE_VALUE (arglist
);
8139 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8140 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
8141 #ifdef POINTERS_EXTEND_UNSIGNED
8142 if (GET_MODE(mem
) != Pmode
)
8143 mem
= convert_memory_address (Pmode
, mem
);
8146 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8148 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8149 MEM_VOLATILE_P (mem
) = 1;
8151 if (target
&& ! register_operand (target
, mode
))
8154 emit_insn (gen_mf ());
8155 tmp
= gen_reg_rtx (mode
);
8156 old
= gen_reg_rtx (mode
);
8157 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8158 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8160 emit_move_insn (tmp
, mem
);
8162 label
= gen_label_rtx ();
8164 emit_move_insn (old
, tmp
);
8165 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8167 /* Perform the specific operation. Special case NAND by noticing
8168 one_cmpl_optab instead. */
8169 if (binoptab
== one_cmpl_optab
)
8171 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8172 binoptab
= and_optab
;
8174 ret
= expand_binop (mode
, binoptab
, tmp
, value
, target
, 1, OPTAB_WIDEN
);
8177 insn
= gen_cmpxchg_acq_si (tmp
, mem
, ret
, ccv
);
8179 insn
= gen_cmpxchg_acq_di (tmp
, mem
, ret
, ccv
);
8182 emit_cmp_and_jump_insns (tmp
, old
, NE
, 0, mode
, 1, label
);
8187 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8191 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8194 For bool_ it's the same except return ret == oldval.
8198 ia64_expand_compare_and_swap (enum machine_mode rmode
, enum machine_mode mode
,
8199 int boolp
, tree arglist
, rtx target
)
8201 tree arg0
, arg1
, arg2
;
8202 rtx mem
, old
, new, ccv
, tmp
, insn
;
8204 arg0
= TREE_VALUE (arglist
);
8205 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8206 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8207 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8208 old
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8209 new = expand_expr (arg2
, NULL_RTX
, mode
, 0);
8211 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8212 MEM_VOLATILE_P (mem
) = 1;
8214 if (GET_MODE (old
) != mode
)
8215 old
= convert_to_mode (mode
, old
, /*unsignedp=*/1);
8216 if (GET_MODE (new) != mode
)
8217 new = convert_to_mode (mode
, new, /*unsignedp=*/1);
8219 if (! register_operand (old
, mode
))
8220 old
= copy_to_mode_reg (mode
, old
);
8221 if (! register_operand (new, mode
))
8222 new = copy_to_mode_reg (mode
, new);
8224 if (! boolp
&& target
&& register_operand (target
, mode
))
8227 tmp
= gen_reg_rtx (mode
);
8229 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8230 convert_move (ccv
, old
, /*unsignedp=*/1);
8231 emit_insn (gen_mf ());
8233 insn
= gen_cmpxchg_acq_si (tmp
, mem
, new, ccv
);
8235 insn
= gen_cmpxchg_acq_di (tmp
, mem
, new, ccv
);
8241 target
= gen_reg_rtx (rmode
);
8242 return emit_store_flag_force (target
, EQ
, tmp
, old
, mode
, 1, 1);
8248 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8251 ia64_expand_lock_test_and_set (enum machine_mode mode
, tree arglist
,
8255 rtx mem
, new, ret
, insn
;
8257 arg0
= TREE_VALUE (arglist
);
8258 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8259 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8260 new = expand_expr (arg1
, NULL_RTX
, mode
, 0);
8262 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8263 MEM_VOLATILE_P (mem
) = 1;
8264 if (! register_operand (new, mode
))
8265 new = copy_to_mode_reg (mode
, new);
8267 if (target
&& register_operand (target
, mode
))
8270 ret
= gen_reg_rtx (mode
);
8273 insn
= gen_xchgsi (ret
, mem
, new);
8275 insn
= gen_xchgdi (ret
, mem
, new);
8281 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8284 ia64_expand_lock_release (enum machine_mode mode
, tree arglist
,
8285 rtx target ATTRIBUTE_UNUSED
)
8290 arg0
= TREE_VALUE (arglist
);
8291 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8293 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8294 MEM_VOLATILE_P (mem
) = 1;
8296 emit_move_insn (mem
, const0_rtx
);
8302 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8303 enum machine_mode mode ATTRIBUTE_UNUSED
,
8304 int ignore ATTRIBUTE_UNUSED
)
8306 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8307 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8308 tree arglist
= TREE_OPERAND (exp
, 1);
8309 enum machine_mode rmode
= VOIDmode
;
8313 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8314 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8319 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8320 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8321 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8322 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8323 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8324 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8325 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8326 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8327 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8328 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8329 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8330 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8331 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8332 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8336 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8341 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8346 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8347 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8348 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8349 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8350 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8351 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8352 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8353 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8354 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8355 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8356 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8357 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8358 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8359 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8369 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8370 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8371 return ia64_expand_compare_and_swap (rmode
, mode
, 1, arglist
,
8374 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8375 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8376 return ia64_expand_compare_and_swap (rmode
, mode
, 0, arglist
,
8379 case IA64_BUILTIN_SYNCHRONIZE
:
8380 emit_insn (gen_mf ());
8383 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8384 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8385 return ia64_expand_lock_test_and_set (mode
, arglist
, target
);
8387 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8388 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8389 return ia64_expand_lock_release (mode
, arglist
, target
);
8391 case IA64_BUILTIN_BSP
:
8392 if (! target
|| ! register_operand (target
, DImode
))
8393 target
= gen_reg_rtx (DImode
);
8394 emit_insn (gen_bsp_value (target
));
8395 #ifdef POINTERS_EXTEND_UNSIGNED
8396 target
= convert_memory_address (ptr_mode
, target
);
8400 case IA64_BUILTIN_FLUSHRS
:
8401 emit_insn (gen_flushrs ());
8404 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8405 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8406 return ia64_expand_fetch_and_op (add_optab
, mode
, arglist
, target
);
8408 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8409 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8410 return ia64_expand_fetch_and_op (sub_optab
, mode
, arglist
, target
);
8412 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8413 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8414 return ia64_expand_fetch_and_op (ior_optab
, mode
, arglist
, target
);
8416 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8417 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8418 return ia64_expand_fetch_and_op (and_optab
, mode
, arglist
, target
);
8420 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8421 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8422 return ia64_expand_fetch_and_op (xor_optab
, mode
, arglist
, target
);
8424 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8425 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8426 return ia64_expand_fetch_and_op (one_cmpl_optab
, mode
, arglist
, target
);
8428 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8429 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8430 return ia64_expand_op_and_fetch (add_optab
, mode
, arglist
, target
);
8432 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8433 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8434 return ia64_expand_op_and_fetch (sub_optab
, mode
, arglist
, target
);
8436 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8437 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8438 return ia64_expand_op_and_fetch (ior_optab
, mode
, arglist
, target
);
8440 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8441 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8442 return ia64_expand_op_and_fetch (and_optab
, mode
, arglist
, target
);
8444 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8445 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8446 return ia64_expand_op_and_fetch (xor_optab
, mode
, arglist
, target
);
8448 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8449 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8450 return ia64_expand_op_and_fetch (one_cmpl_optab
, mode
, arglist
, target
);
8459 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8460 most significant bits of the stack slot. */
8463 ia64_hpux_function_arg_padding (enum machine_mode mode
, tree type
)
8465 /* Exception to normal case for structures/unions/etc. */
8467 if (type
&& AGGREGATE_TYPE_P (type
)
8468 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
8471 /* Fall back to the default. */
8472 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8475 /* Linked list of all external functions that are to be emitted by GCC.
8476 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8477 order to avoid putting out names that are never really used. */
8479 struct extern_func_list
GTY(())
8481 struct extern_func_list
*next
;
8485 static GTY(()) struct extern_func_list
*extern_func_head
;
8488 ia64_hpux_add_extern_decl (tree decl
)
8490 struct extern_func_list
*p
= ggc_alloc (sizeof (struct extern_func_list
));
8493 p
->next
= extern_func_head
;
8494 extern_func_head
= p
;
8497 /* Print out the list of used global functions. */
8500 ia64_hpux_file_end (void)
8502 struct extern_func_list
*p
;
8504 for (p
= extern_func_head
; p
; p
= p
->next
)
8506 tree decl
= p
->decl
;
8507 tree id
= DECL_ASSEMBLER_NAME (decl
);
8512 if (!TREE_ASM_WRITTEN (decl
) && TREE_SYMBOL_REFERENCED (id
))
8514 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8516 TREE_ASM_WRITTEN (decl
) = 1;
8517 (*targetm
.asm_out
.globalize_label
) (asm_out_file
, name
);
8518 fputs (TYPE_ASM_OP
, asm_out_file
);
8519 assemble_name (asm_out_file
, name
);
8520 fprintf (asm_out_file
, "," TYPE_OPERAND_FMT
"\n", "function");
8524 extern_func_head
= 0;
8527 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
8528 modes of word_mode and larger. Rename the TFmode libfuncs using the
8529 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
8530 backward compatibility. */
8533 ia64_init_libfuncs (void)
8535 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
8536 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
8537 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
8538 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
8540 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
8541 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
8542 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
8543 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
8544 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
8546 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
8547 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
8548 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
8549 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
8550 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
8551 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
8553 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
8554 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
8555 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
8556 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
8558 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
8559 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
8562 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8565 ia64_hpux_init_libfuncs (void)
8567 ia64_init_libfuncs ();
8569 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
8570 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
8571 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
8573 /* ia64_expand_compare uses this. */
8574 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
8576 /* These should never be used. */
8577 set_optab_libfunc (eq_optab
, TFmode
, 0);
8578 set_optab_libfunc (ne_optab
, TFmode
, 0);
8579 set_optab_libfunc (gt_optab
, TFmode
, 0);
8580 set_optab_libfunc (ge_optab
, TFmode
, 0);
8581 set_optab_libfunc (lt_optab
, TFmode
, 0);
8582 set_optab_libfunc (le_optab
, TFmode
, 0);
8585 /* Rename the division and modulus functions in VMS. */
8588 ia64_vms_init_libfuncs (void)
8590 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
8591 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
8592 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
8593 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
8594 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
8595 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
8596 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
8597 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
8600 /* Rename the TFmode libfuncs available from soft-fp in glibc using
8601 the HPUX conventions. */
8604 ia64_sysv4_init_libfuncs (void)
8606 ia64_init_libfuncs ();
8608 /* These functions are not part of the HPUX TFmode interface. We
8609 use them instead of _U_Qfcmp, which doesn't work the way we
8611 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
8612 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
8613 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
8614 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
8615 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
8616 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
8618 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
8619 glibc doesn't have them. */
8622 /* Switch to the section to which we should output X. The only thing
8623 special we do here is to honor small data. */
8626 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
8627 unsigned HOST_WIDE_INT align
)
8629 if (GET_MODE_SIZE (mode
) > 0
8630 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
)
8633 default_elf_select_rtx_section (mode
, x
, align
);
8636 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8637 Pretend flag_pic is always set. */
8640 ia64_rwreloc_select_section (tree exp
, int reloc
, unsigned HOST_WIDE_INT align
)
8642 default_elf_select_section_1 (exp
, reloc
, align
, true);
8646 ia64_rwreloc_unique_section (tree decl
, int reloc
)
8648 default_unique_section_1 (decl
, reloc
, true);
8652 ia64_rwreloc_select_rtx_section (enum machine_mode mode
, rtx x
,
8653 unsigned HOST_WIDE_INT align
)
8655 int save_pic
= flag_pic
;
8657 ia64_select_rtx_section (mode
, x
, align
);
8658 flag_pic
= save_pic
;
8661 #ifndef TARGET_RWRELOC
8662 #define TARGET_RWRELOC flag_pic
8666 ia64_section_type_flags (tree decl
, const char *name
, int reloc
)
8668 unsigned int flags
= 0;
8670 if (strcmp (name
, ".sdata") == 0
8671 || strncmp (name
, ".sdata.", 7) == 0
8672 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
8673 || strncmp (name
, ".sdata2.", 8) == 0
8674 || strncmp (name
, ".gnu.linkonce.s2.", 17) == 0
8675 || strcmp (name
, ".sbss") == 0
8676 || strncmp (name
, ".sbss.", 6) == 0
8677 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
8678 flags
= SECTION_SMALL
;
8680 flags
|= default_section_type_flags_1 (decl
, name
, reloc
, TARGET_RWRELOC
);
8684 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8685 structure type and that the address of that type should be passed
8686 in out0, rather than in r8. */
8689 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
8691 tree ret_type
= TREE_TYPE (fntype
);
8693 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8694 as the structure return address parameter, if the return value
8695 type has a non-trivial copy constructor or destructor. It is not
8696 clear if this same convention should be used for other
8697 programming languages. Until G++ 3.4, we incorrectly used r8 for
8698 these return values. */
8699 return (abi_version_at_least (2)
8701 && TYPE_MODE (ret_type
) == BLKmode
8702 && TREE_ADDRESSABLE (ret_type
)
8703 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
8706 /* Output the assembler code for a thunk function. THUNK_DECL is the
8707 declaration for the thunk function itself, FUNCTION is the decl for
8708 the target function. DELTA is an immediate constant offset to be
8709 added to THIS. If VCALL_OFFSET is nonzero, the word at
8710 *(*this + vcall_offset) should be added to THIS. */
8713 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8714 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8717 rtx
this, insn
, funexp
;
8718 unsigned int this_parmno
;
8719 unsigned int this_regno
;
8721 reload_completed
= 1;
8722 epilogue_completed
= 1;
8724 reset_block_changes ();
8726 /* Set things up as ia64_expand_prologue might. */
8727 last_scratch_gr_reg
= 15;
8729 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
8730 current_frame_info
.spill_cfa_off
= -16;
8731 current_frame_info
.n_input_regs
= 1;
8732 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
8734 /* Mark the end of the (empty) prologue. */
8735 emit_note (NOTE_INSN_PROLOGUE_END
);
8737 /* Figure out whether "this" will be the first parameter (the
8738 typical case) or the second parameter (as happens when the
8739 virtual function returns certain class objects). */
8741 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
8743 this_regno
= IN_REG (this_parmno
);
8744 if (!TARGET_REG_NAMES
)
8745 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
8747 this = gen_rtx_REG (Pmode
, this_regno
);
8750 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
8751 REG_POINTER (tmp
) = 1;
8752 if (delta
&& CONST_OK_FOR_I (delta
))
8754 emit_insn (gen_ptr_extend_plus_imm (this, tmp
, GEN_INT (delta
)));
8758 emit_insn (gen_ptr_extend (this, tmp
));
8761 /* Apply the constant offset, if required. */
8764 rtx delta_rtx
= GEN_INT (delta
);
8766 if (!CONST_OK_FOR_I (delta
))
8768 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8769 emit_move_insn (tmp
, delta_rtx
);
8772 emit_insn (gen_adddi3 (this, this, delta_rtx
));
8775 /* Apply the offset from the vtable, if required. */
8778 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8779 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8783 rtx t
= gen_rtx_REG (ptr_mode
, 2);
8784 REG_POINTER (t
) = 1;
8785 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this));
8786 if (CONST_OK_FOR_I (vcall_offset
))
8788 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
,
8793 emit_insn (gen_ptr_extend (tmp
, t
));
8796 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8800 if (!CONST_OK_FOR_J (vcall_offset
))
8802 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
8803 emit_move_insn (tmp2
, vcall_offset_rtx
);
8804 vcall_offset_rtx
= tmp2
;
8806 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
8810 emit_move_insn (gen_rtx_REG (ptr_mode
, 2),
8811 gen_rtx_MEM (ptr_mode
, tmp
));
8813 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
8815 emit_insn (gen_adddi3 (this, this, tmp
));
8818 /* Generate a tail call to the target function. */
8819 if (! TREE_USED (function
))
8821 assemble_external (function
);
8822 TREE_USED (function
) = 1;
8824 funexp
= XEXP (DECL_RTL (function
), 0);
8825 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8826 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
8827 insn
= get_last_insn ();
8828 SIBLING_CALL_P (insn
) = 1;
8830 /* Code generation for calls relies on splitting. */
8831 reload_completed
= 1;
8832 epilogue_completed
= 1;
8833 try_split (PATTERN (insn
), insn
, 0);
8837 /* Run just enough of rest_of_compilation to get the insns emitted.
8838 There's not really enough bulk here to make other passes such as
8839 instruction scheduling worth while. Note that use_thunk calls
8840 assemble_start_function and assemble_end_function. */
8842 insn_locators_initialize ();
8843 emit_all_insn_group_barriers (NULL
);
8844 insn
= get_insns ();
8845 shorten_branches (insn
);
8846 final_start_function (insn
, file
, 1);
8847 final (insn
, file
, 1, 0);
8848 final_end_function ();
8850 reload_completed
= 0;
8851 epilogue_completed
= 0;
8855 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8858 ia64_struct_value_rtx (tree fntype
,
8859 int incoming ATTRIBUTE_UNUSED
)
8861 if (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
))
8863 return gen_rtx_REG (Pmode
, GR_REG (8));
8867 ia64_scalar_mode_supported_p (enum machine_mode mode
)
8892 ia64_vector_mode_supported_p (enum machine_mode mode
)
8909 #include "gt-ia64.h"