[AArch64] Handle more SVE predicate constants
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / peel_ind_2.c
blobe792cdf2cad297e7044fdecd576343c9ac212078
1 /* { dg-do compile } */
2 /* Pick an arbitrary target for which unaligned accesses are more
3 expensive. */
4 /* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx" } */
6 #define N 512
7 #define START 7
8 #define END 22
10 int x[N] __attribute__((aligned(32)));
12 void __attribute__((noinline, noclone))
13 foo (void)
15 for (unsigned int i = START; i < END; ++i)
16 x[i] = i;
19 /* We should operate on aligned vectors. */
20 /* { dg-final { scan-assembler {\t(adrp|adr)\tx[0-9]+, x\n} } } */
21 /* We should unroll the loop three times. */
22 /* { dg-final { scan-assembler-times "\tst1w\t" 3 } } */
23 /* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.s, vl7\n.*\teor\tp[0-7]\.b, (p[0-7])/z, (\1\.b, \2\.b|\2\.b, \1\.b)\n} } } */