1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2014 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "diagnostic-core.h"
29 #include "stor-layout.h"
32 #include "insn-config.h"
34 #include "insn-codes.h"
37 #include "langhooks.h"
39 #include "basic-block.h"
44 struct target_expmed default_target_expmed
;
46 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
49 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
50 unsigned HOST_WIDE_INT
,
51 unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
,
54 static void store_fixed_bit_field_1 (rtx
, unsigned HOST_WIDE_INT
,
55 unsigned HOST_WIDE_INT
,
57 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
58 unsigned HOST_WIDE_INT
,
59 unsigned HOST_WIDE_INT
,
60 unsigned HOST_WIDE_INT
,
62 static rtx
extract_fixed_bit_field (machine_mode
, rtx
,
63 unsigned HOST_WIDE_INT
,
64 unsigned HOST_WIDE_INT
, rtx
, int, bool);
65 static rtx
extract_fixed_bit_field_1 (machine_mode
, rtx
,
66 unsigned HOST_WIDE_INT
,
67 unsigned HOST_WIDE_INT
, rtx
, int, bool);
68 static rtx
lshift_value (machine_mode
, unsigned HOST_WIDE_INT
, int);
69 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
70 unsigned HOST_WIDE_INT
, int, bool);
71 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, machine_mode
, rtx_code_label
*);
72 static rtx
expand_smod_pow2 (machine_mode
, rtx
, HOST_WIDE_INT
);
73 static rtx
expand_sdiv_pow2 (machine_mode
, rtx
, HOST_WIDE_INT
);
75 /* Return a constant integer mask value of mode MODE with BITSIZE ones
76 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
77 The mask is truncated if necessary to the width of mode MODE. The
78 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
81 mask_rtx (machine_mode mode
, int bitpos
, int bitsize
, bool complement
)
83 return immed_wide_int_const
84 (wi::shifted_mask (bitpos
, bitsize
, complement
,
85 GET_MODE_PRECISION (mode
)), mode
);
88 /* Test whether a value is zero of a power of two. */
89 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
90 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
92 struct init_expmed_rtl
113 rtx pow2
[MAX_BITS_PER_WORD
];
114 rtx cint
[MAX_BITS_PER_WORD
];
118 init_expmed_one_conv (struct init_expmed_rtl
*all
, machine_mode to_mode
,
119 machine_mode from_mode
, bool speed
)
121 int to_size
, from_size
;
124 to_size
= GET_MODE_PRECISION (to_mode
);
125 from_size
= GET_MODE_PRECISION (from_mode
);
127 /* Most partial integers have a precision less than the "full"
128 integer it requires for storage. In case one doesn't, for
129 comparison purposes here, reduce the bit size by one in that
131 if (GET_MODE_CLASS (to_mode
) == MODE_PARTIAL_INT
132 && exact_log2 (to_size
) != -1)
134 if (GET_MODE_CLASS (from_mode
) == MODE_PARTIAL_INT
135 && exact_log2 (from_size
) != -1)
138 /* Assume cost of zero-extend and sign-extend is the same. */
139 which
= (to_size
< from_size
? all
->trunc
: all
->zext
);
141 PUT_MODE (all
->reg
, from_mode
);
142 set_convert_cost (to_mode
, from_mode
, speed
, set_src_cost (which
, speed
));
146 init_expmed_one_mode (struct init_expmed_rtl
*all
,
147 machine_mode mode
, int speed
)
149 int m
, n
, mode_bitsize
;
150 machine_mode mode_from
;
152 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
154 PUT_MODE (all
->reg
, mode
);
155 PUT_MODE (all
->plus
, mode
);
156 PUT_MODE (all
->neg
, mode
);
157 PUT_MODE (all
->mult
, mode
);
158 PUT_MODE (all
->sdiv
, mode
);
159 PUT_MODE (all
->udiv
, mode
);
160 PUT_MODE (all
->sdiv_32
, mode
);
161 PUT_MODE (all
->smod_32
, mode
);
162 PUT_MODE (all
->wide_trunc
, mode
);
163 PUT_MODE (all
->shift
, mode
);
164 PUT_MODE (all
->shift_mult
, mode
);
165 PUT_MODE (all
->shift_add
, mode
);
166 PUT_MODE (all
->shift_sub0
, mode
);
167 PUT_MODE (all
->shift_sub1
, mode
);
168 PUT_MODE (all
->zext
, mode
);
169 PUT_MODE (all
->trunc
, mode
);
171 set_add_cost (speed
, mode
, set_src_cost (all
->plus
, speed
));
172 set_neg_cost (speed
, mode
, set_src_cost (all
->neg
, speed
));
173 set_mul_cost (speed
, mode
, set_src_cost (all
->mult
, speed
));
174 set_sdiv_cost (speed
, mode
, set_src_cost (all
->sdiv
, speed
));
175 set_udiv_cost (speed
, mode
, set_src_cost (all
->udiv
, speed
));
177 set_sdiv_pow2_cheap (speed
, mode
, (set_src_cost (all
->sdiv_32
, speed
)
178 <= 2 * add_cost (speed
, mode
)));
179 set_smod_pow2_cheap (speed
, mode
, (set_src_cost (all
->smod_32
, speed
)
180 <= 4 * add_cost (speed
, mode
)));
182 set_shift_cost (speed
, mode
, 0, 0);
184 int cost
= add_cost (speed
, mode
);
185 set_shiftadd_cost (speed
, mode
, 0, cost
);
186 set_shiftsub0_cost (speed
, mode
, 0, cost
);
187 set_shiftsub1_cost (speed
, mode
, 0, cost
);
190 n
= MIN (MAX_BITS_PER_WORD
, mode_bitsize
);
191 for (m
= 1; m
< n
; m
++)
193 XEXP (all
->shift
, 1) = all
->cint
[m
];
194 XEXP (all
->shift_mult
, 1) = all
->pow2
[m
];
196 set_shift_cost (speed
, mode
, m
, set_src_cost (all
->shift
, speed
));
197 set_shiftadd_cost (speed
, mode
, m
, set_src_cost (all
->shift_add
, speed
));
198 set_shiftsub0_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub0
, speed
));
199 set_shiftsub1_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub1
, speed
));
202 if (SCALAR_INT_MODE_P (mode
))
204 for (mode_from
= MIN_MODE_INT
; mode_from
<= MAX_MODE_INT
;
205 mode_from
= (machine_mode
)(mode_from
+ 1))
206 init_expmed_one_conv (all
, mode
, mode_from
, speed
);
208 if (GET_MODE_CLASS (mode
) == MODE_INT
)
210 machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
211 if (wider_mode
!= VOIDmode
)
213 PUT_MODE (all
->zext
, wider_mode
);
214 PUT_MODE (all
->wide_mult
, wider_mode
);
215 PUT_MODE (all
->wide_lshr
, wider_mode
);
216 XEXP (all
->wide_lshr
, 1) = GEN_INT (mode_bitsize
);
218 set_mul_widen_cost (speed
, wider_mode
,
219 set_src_cost (all
->wide_mult
, speed
));
220 set_mul_highpart_cost (speed
, mode
,
221 set_src_cost (all
->wide_trunc
, speed
));
229 struct init_expmed_rtl all
;
230 machine_mode mode
= QImode
;
233 memset (&all
, 0, sizeof all
);
234 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
236 all
.pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
237 all
.cint
[m
] = GEN_INT (m
);
240 /* Avoid using hard regs in ways which may be unsupported. */
241 all
.reg
= gen_rtx_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
242 all
.plus
= gen_rtx_PLUS (mode
, all
.reg
, all
.reg
);
243 all
.neg
= gen_rtx_NEG (mode
, all
.reg
);
244 all
.mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
245 all
.sdiv
= gen_rtx_DIV (mode
, all
.reg
, all
.reg
);
246 all
.udiv
= gen_rtx_UDIV (mode
, all
.reg
, all
.reg
);
247 all
.sdiv_32
= gen_rtx_DIV (mode
, all
.reg
, all
.pow2
[5]);
248 all
.smod_32
= gen_rtx_MOD (mode
, all
.reg
, all
.pow2
[5]);
249 all
.zext
= gen_rtx_ZERO_EXTEND (mode
, all
.reg
);
250 all
.wide_mult
= gen_rtx_MULT (mode
, all
.zext
, all
.zext
);
251 all
.wide_lshr
= gen_rtx_LSHIFTRT (mode
, all
.wide_mult
, all
.reg
);
252 all
.wide_trunc
= gen_rtx_TRUNCATE (mode
, all
.wide_lshr
);
253 all
.shift
= gen_rtx_ASHIFT (mode
, all
.reg
, all
.reg
);
254 all
.shift_mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
255 all
.shift_add
= gen_rtx_PLUS (mode
, all
.shift_mult
, all
.reg
);
256 all
.shift_sub0
= gen_rtx_MINUS (mode
, all
.shift_mult
, all
.reg
);
257 all
.shift_sub1
= gen_rtx_MINUS (mode
, all
.reg
, all
.shift_mult
);
258 all
.trunc
= gen_rtx_TRUNCATE (mode
, all
.reg
);
260 for (speed
= 0; speed
< 2; speed
++)
262 crtl
->maybe_hot_insn_p
= speed
;
263 set_zero_cost (speed
, set_src_cost (const0_rtx
, speed
));
265 for (mode
= MIN_MODE_INT
; mode
<= MAX_MODE_INT
;
266 mode
= (machine_mode
)(mode
+ 1))
267 init_expmed_one_mode (&all
, mode
, speed
);
269 if (MIN_MODE_PARTIAL_INT
!= VOIDmode
)
270 for (mode
= MIN_MODE_PARTIAL_INT
; mode
<= MAX_MODE_PARTIAL_INT
;
271 mode
= (machine_mode
)(mode
+ 1))
272 init_expmed_one_mode (&all
, mode
, speed
);
274 if (MIN_MODE_VECTOR_INT
!= VOIDmode
)
275 for (mode
= MIN_MODE_VECTOR_INT
; mode
<= MAX_MODE_VECTOR_INT
;
276 mode
= (machine_mode
)(mode
+ 1))
277 init_expmed_one_mode (&all
, mode
, speed
);
280 if (alg_hash_used_p ())
282 struct alg_hash_entry
*p
= alg_hash_entry_ptr (0);
283 memset (p
, 0, sizeof (*p
) * NUM_ALG_HASH_ENTRIES
);
286 set_alg_hash_used_p (true);
287 default_rtl_profile ();
289 ggc_free (all
.trunc
);
290 ggc_free (all
.shift_sub1
);
291 ggc_free (all
.shift_sub0
);
292 ggc_free (all
.shift_add
);
293 ggc_free (all
.shift_mult
);
294 ggc_free (all
.shift
);
295 ggc_free (all
.wide_trunc
);
296 ggc_free (all
.wide_lshr
);
297 ggc_free (all
.wide_mult
);
299 ggc_free (all
.smod_32
);
300 ggc_free (all
.sdiv_32
);
309 /* Return an rtx representing minus the value of X.
310 MODE is the intended mode of the result,
311 useful if X is a CONST_INT. */
314 negate_rtx (machine_mode mode
, rtx x
)
316 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
319 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
324 /* Return an rtx representing value of X with reverse storage order.
325 MODE is the intended mode of the result,
326 useful if X is a CONST_INT. */
329 flip_storage_order (enum machine_mode mode
, rtx x
)
331 enum machine_mode int_mode
;
337 if (SCALAR_INT_MODE_P (mode
))
341 int_mode
= int_mode_for_mode (mode
);
342 gcc_assert (int_mode
!= BLKmode
);
343 x
= gen_lowpart (int_mode
, x
);
346 result
= simplify_unary_operation (BSWAP
, int_mode
, x
, int_mode
);
348 result
= expand_unop (int_mode
, bswap_optab
, x
, NULL_RTX
, 1);
350 if (int_mode
!= mode
)
351 result
= gen_lowpart (mode
, result
);
356 /* Adjust bitfield memory MEM so that it points to the first unit of mode
357 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
358 If MODE is BLKmode, return a reference to every byte in the bitfield.
359 Set *NEW_BITNUM to the bit position of the field within the new memory. */
362 narrow_bit_field_mem (rtx mem
, machine_mode mode
,
363 unsigned HOST_WIDE_INT bitsize
,
364 unsigned HOST_WIDE_INT bitnum
,
365 unsigned HOST_WIDE_INT
*new_bitnum
)
369 *new_bitnum
= bitnum
% BITS_PER_UNIT
;
370 HOST_WIDE_INT offset
= bitnum
/ BITS_PER_UNIT
;
371 HOST_WIDE_INT size
= ((*new_bitnum
+ bitsize
+ BITS_PER_UNIT
- 1)
373 return adjust_bitfield_address_size (mem
, mode
, offset
, size
);
377 unsigned int unit
= GET_MODE_BITSIZE (mode
);
378 *new_bitnum
= bitnum
% unit
;
379 HOST_WIDE_INT offset
= (bitnum
- *new_bitnum
) / BITS_PER_UNIT
;
380 return adjust_bitfield_address (mem
, mode
, offset
);
384 /* The caller wants to perform insertion or extraction PATTERN on a
385 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
386 BITREGION_START and BITREGION_END are as for store_bit_field
387 and FIELDMODE is the natural mode of the field.
389 Search for a mode that is compatible with the memory access
390 restrictions and (where applicable) with a register insertion or
391 extraction. Return the new memory on success, storing the adjusted
392 bit position in *NEW_BITNUM. Return null otherwise. */
395 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern
,
396 rtx op0
, HOST_WIDE_INT bitsize
,
397 HOST_WIDE_INT bitnum
,
398 unsigned HOST_WIDE_INT bitregion_start
,
399 unsigned HOST_WIDE_INT bitregion_end
,
400 machine_mode fieldmode
,
401 unsigned HOST_WIDE_INT
*new_bitnum
)
403 bit_field_mode_iterator
iter (bitsize
, bitnum
, bitregion_start
,
404 bitregion_end
, MEM_ALIGN (op0
),
405 MEM_VOLATILE_P (op0
));
406 machine_mode best_mode
;
407 if (iter
.next_mode (&best_mode
))
409 /* We can use a memory in BEST_MODE. See whether this is true for
410 any wider modes. All other things being equal, we prefer to
411 use the widest mode possible because it tends to expose more
412 CSE opportunities. */
413 if (!iter
.prefer_smaller_modes ())
415 /* Limit the search to the mode required by the corresponding
416 register insertion or extraction instruction, if any. */
417 machine_mode limit_mode
= word_mode
;
418 extraction_insn insn
;
419 if (get_best_reg_extraction_insn (&insn
, pattern
,
420 GET_MODE_BITSIZE (best_mode
),
422 limit_mode
= insn
.field_mode
;
424 machine_mode wider_mode
;
425 while (iter
.next_mode (&wider_mode
)
426 && GET_MODE_SIZE (wider_mode
) <= GET_MODE_SIZE (limit_mode
))
427 best_mode
= wider_mode
;
429 return narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
,
435 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
436 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
437 offset is then BITNUM / BITS_PER_UNIT. */
440 lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum
,
441 unsigned HOST_WIDE_INT bitsize
,
442 machine_mode struct_mode
)
444 if (BYTES_BIG_ENDIAN
)
445 return (bitnum
% BITS_PER_UNIT
== 0
446 && (bitnum
+ bitsize
== GET_MODE_BITSIZE (struct_mode
)
447 || (bitnum
+ bitsize
) % BITS_PER_WORD
== 0));
449 return bitnum
% BITS_PER_WORD
== 0;
452 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
453 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
454 Return false if the access would touch memory outside the range
455 BITREGION_START to BITREGION_END for conformance to the C++ memory
459 strict_volatile_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
460 unsigned HOST_WIDE_INT bitnum
,
461 machine_mode fieldmode
,
462 unsigned HOST_WIDE_INT bitregion_start
,
463 unsigned HOST_WIDE_INT bitregion_end
)
465 unsigned HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (fieldmode
);
467 /* -fstrict-volatile-bitfields must be enabled and we must have a
470 || !MEM_VOLATILE_P (op0
)
471 || flag_strict_volatile_bitfields
<= 0)
474 /* Non-integral modes likely only happen with packed structures.
476 if (!SCALAR_INT_MODE_P (fieldmode
))
479 /* The bit size must not be larger than the field mode, and
480 the field mode must not be larger than a word. */
481 if (bitsize
> modesize
|| modesize
> BITS_PER_WORD
)
484 /* Check for cases of unaligned fields that must be split. */
485 if (bitnum
% BITS_PER_UNIT
+ bitsize
> modesize
487 && bitnum
% GET_MODE_ALIGNMENT (fieldmode
) + bitsize
> modesize
))
490 /* Check for cases where the C++ memory model applies. */
491 if (bitregion_end
!= 0
492 && (bitnum
- bitnum
% modesize
< bitregion_start
493 || bitnum
- bitnum
% modesize
+ modesize
- 1 > bitregion_end
))
499 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
500 bit number BITNUM can be treated as a simple value of mode MODE. */
503 simple_mem_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
504 unsigned HOST_WIDE_INT bitnum
, machine_mode mode
)
507 && bitnum
% BITS_PER_UNIT
== 0
508 && bitsize
== GET_MODE_BITSIZE (mode
)
509 && (!SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
510 || (bitnum
% GET_MODE_ALIGNMENT (mode
) == 0
511 && MEM_ALIGN (op0
) >= GET_MODE_ALIGNMENT (mode
))));
514 /* Try to use instruction INSV to store VALUE into a field of OP0.
515 BITSIZE and BITNUM are as for store_bit_field. */
518 store_bit_field_using_insv (const extraction_insn
*insv
, rtx op0
,
519 unsigned HOST_WIDE_INT bitsize
,
520 unsigned HOST_WIDE_INT bitnum
,
523 struct expand_operand ops
[4];
526 rtx_insn
*last
= get_last_insn ();
527 bool copy_back
= false;
529 machine_mode op_mode
= insv
->field_mode
;
530 unsigned int unit
= GET_MODE_BITSIZE (op_mode
);
531 if (bitsize
== 0 || bitsize
> unit
)
535 /* Get a reference to the first byte of the field. */
536 xop0
= narrow_bit_field_mem (xop0
, insv
->struct_mode
, bitsize
, bitnum
,
540 /* Convert from counting within OP0 to counting in OP_MODE. */
541 if (BYTES_BIG_ENDIAN
)
542 bitnum
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
544 /* If xop0 is a register, we need it in OP_MODE
545 to make it acceptable to the format of insv. */
546 if (GET_CODE (xop0
) == SUBREG
)
547 /* We can't just change the mode, because this might clobber op0,
548 and we will need the original value of op0 if insv fails. */
549 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
550 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
551 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
554 /* If the destination is a paradoxical subreg such that we need a
555 truncate to the inner mode, perform the insertion on a temporary and
556 truncate the result to the original destination. Note that we can't
557 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
558 X) 0)) is (reg:N X). */
559 if (GET_CODE (xop0
) == SUBREG
560 && REG_P (SUBREG_REG (xop0
))
561 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0
)),
564 rtx tem
= gen_reg_rtx (op_mode
);
565 emit_move_insn (tem
, xop0
);
570 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
571 "backwards" from the size of the unit we are inserting into.
572 Otherwise, we count bits from the most significant on a
573 BYTES/BITS_BIG_ENDIAN machine. */
575 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
576 bitnum
= unit
- bitsize
- bitnum
;
578 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
580 if (GET_MODE (value
) != op_mode
)
582 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
584 /* Optimization: Don't bother really extending VALUE
585 if it has all the bits we will actually use. However,
586 if we must narrow it, be sure we do it correctly. */
588 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (op_mode
))
592 tmp
= simplify_subreg (op_mode
, value1
, GET_MODE (value
), 0);
594 tmp
= simplify_gen_subreg (op_mode
,
595 force_reg (GET_MODE (value
),
597 GET_MODE (value
), 0);
601 value1
= gen_lowpart (op_mode
, value1
);
603 else if (CONST_INT_P (value
))
604 value1
= gen_int_mode (INTVAL (value
), op_mode
);
606 /* Parse phase is supposed to make VALUE's data type
607 match that of the component reference, which is a type
608 at least as wide as the field; so VALUE should have
609 a mode that corresponds to that type. */
610 gcc_assert (CONSTANT_P (value
));
613 create_fixed_operand (&ops
[0], xop0
);
614 create_integer_operand (&ops
[1], bitsize
);
615 create_integer_operand (&ops
[2], bitnum
);
616 create_input_operand (&ops
[3], value1
, op_mode
);
617 if (maybe_expand_insn (insv
->icode
, 4, ops
))
620 convert_move (op0
, xop0
, true);
623 delete_insns_since (last
);
627 /* A subroutine of store_bit_field, with the same arguments. Return true
628 if the operation could be implemented.
630 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
631 no other way of implementing the operation. If FALLBACK_P is false,
632 return false instead. */
635 store_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
636 unsigned HOST_WIDE_INT bitnum
,
637 unsigned HOST_WIDE_INT bitregion_start
,
638 unsigned HOST_WIDE_INT bitregion_end
,
639 machine_mode fieldmode
,
640 rtx value
, bool reverse
, bool fallback_p
)
645 while (GET_CODE (op0
) == SUBREG
)
647 /* The following line once was done only if WORDS_BIG_ENDIAN,
648 but I think that is a mistake. WORDS_BIG_ENDIAN is
649 meaningful at a much higher level; when structures are copied
650 between memory and regs, the higher-numbered regs
651 always get higher addresses. */
652 int inner_mode_size
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)));
653 int outer_mode_size
= GET_MODE_SIZE (GET_MODE (op0
));
656 /* Paradoxical subregs need special handling on big endian machines. */
657 if (SUBREG_BYTE (op0
) == 0 && inner_mode_size
< outer_mode_size
)
659 int difference
= inner_mode_size
- outer_mode_size
;
661 if (WORDS_BIG_ENDIAN
)
662 byte_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
663 if (BYTES_BIG_ENDIAN
)
664 byte_offset
+= difference
% UNITS_PER_WORD
;
667 byte_offset
= SUBREG_BYTE (op0
);
669 bitnum
+= byte_offset
* BITS_PER_UNIT
;
670 op0
= SUBREG_REG (op0
);
673 /* No action is needed if the target is a register and if the field
674 lies completely outside that register. This can occur if the source
675 code contains an out-of-bounds access to a small array. */
676 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
679 /* Use vec_set patterns for inserting parts of vectors whenever
681 if (VECTOR_MODE_P (GET_MODE (op0
))
683 && optab_handler (vec_set_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
684 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
685 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
686 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
688 struct expand_operand ops
[3];
689 machine_mode outermode
= GET_MODE (op0
);
690 machine_mode innermode
= GET_MODE_INNER (outermode
);
691 enum insn_code icode
= optab_handler (vec_set_optab
, outermode
);
692 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
694 create_fixed_operand (&ops
[0], op0
);
695 create_input_operand (&ops
[1], value
, innermode
);
696 create_integer_operand (&ops
[2], pos
);
697 if (maybe_expand_insn (icode
, 3, ops
))
701 /* If the target is a register, overwriting the entire object, or storing
702 a full-word or multi-word field can be done with just a SUBREG. */
704 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
705 && ((bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)) && bitnum
== 0)
706 || (bitsize
% BITS_PER_WORD
== 0 && bitnum
% BITS_PER_WORD
== 0)))
708 /* Use the subreg machinery either to narrow OP0 to the required
709 words or to cope with mode punning between equal-sized modes.
710 In the latter case, use subreg on the rhs side, not lhs. */
713 if (bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
715 sub
= simplify_gen_subreg (GET_MODE (op0
), value
, fieldmode
, 0);
719 sub
= flip_storage_order (GET_MODE (op0
), sub
);
720 emit_move_insn (op0
, sub
);
726 sub
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
727 bitnum
/ BITS_PER_UNIT
);
731 value
= flip_storage_order (fieldmode
, value
);
732 emit_move_insn (sub
, value
);
738 /* If the target is memory, storing any naturally aligned field can be
739 done with a simple store. For targets that support fast unaligned
740 memory, any naturally sized, unit aligned field can be done directly. */
741 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, fieldmode
))
743 op0
= adjust_bitfield_address (op0
, fieldmode
, bitnum
/ BITS_PER_UNIT
);
745 value
= flip_storage_order (fieldmode
, value
);
746 emit_move_insn (op0
, value
);
750 /* Make sure we are playing with integral modes. Pun with subregs
751 if we aren't. This must come after the entire register case above,
752 since that case is valid for any mode. The following cases are only
753 valid for integral modes. */
755 machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
756 if (imode
!= GET_MODE (op0
))
759 op0
= adjust_bitfield_address_size (op0
, imode
, 0, MEM_SIZE (op0
));
762 gcc_assert (imode
!= BLKmode
);
763 op0
= gen_lowpart (imode
, op0
);
768 /* Storing an lsb-aligned field in a register
769 can be done with a movstrict instruction. */
773 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
774 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
775 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
777 struct expand_operand ops
[2];
778 enum insn_code icode
= optab_handler (movstrict_optab
, fieldmode
);
780 unsigned HOST_WIDE_INT subreg_off
;
782 if (GET_CODE (arg0
) == SUBREG
)
784 /* Else we've got some float mode source being extracted into
785 a different float mode destination -- this combination of
786 subregs results in Severe Tire Damage. */
787 gcc_assert (GET_MODE (SUBREG_REG (arg0
)) == fieldmode
788 || GET_MODE_CLASS (fieldmode
) == MODE_INT
789 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
790 arg0
= SUBREG_REG (arg0
);
793 subreg_off
= bitnum
/ BITS_PER_UNIT
;
794 if (validate_subreg (fieldmode
, GET_MODE (arg0
), arg0
, subreg_off
))
796 arg0
= gen_rtx_SUBREG (fieldmode
, arg0
, subreg_off
);
798 create_fixed_operand (&ops
[0], arg0
);
799 /* Shrink the source operand to FIELDMODE. */
800 create_convert_operand_to (&ops
[1], value
, fieldmode
, false);
801 if (maybe_expand_insn (icode
, 2, ops
))
806 /* Handle fields bigger than a word. */
808 if (bitsize
> BITS_PER_WORD
)
810 /* Here we transfer the words of the field
811 in the order least significant first.
812 This is because the most significant word is the one which may
814 However, only do that if the value is not BLKmode. */
816 const bool backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
817 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
821 /* This is the mode we must force value to, so that there will be enough
822 subwords to extract. Note that fieldmode will often (always?) be
823 VOIDmode, because that is what store_field uses to indicate that this
824 is a bit field, but passing VOIDmode to operand_subword_force
826 fieldmode
= GET_MODE (value
);
827 if (fieldmode
== VOIDmode
)
828 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
830 last
= get_last_insn ();
831 for (i
= 0; i
< nwords
; i
++)
833 /* If I is 0, use the low-order word in both field and target;
834 if I is 1, use the next to lowest word; and so on. */
835 unsigned int wordnum
= (backwards
836 ? GET_MODE_SIZE (fieldmode
) / UNITS_PER_WORD
839 unsigned int bit_offset
= (backwards
^ reverse
840 ? MAX ((int) bitsize
- ((int) i
+ 1)
843 : (int) i
* BITS_PER_WORD
);
844 rtx value_word
= operand_subword_force (value
, wordnum
, fieldmode
);
845 unsigned HOST_WIDE_INT new_bitsize
=
846 MIN (BITS_PER_WORD
, bitsize
- i
* BITS_PER_WORD
);
848 /* If the remaining chunk doesn't have full wordsize we have
849 to make sure that for big endian machines the higher order
851 if (new_bitsize
< BITS_PER_WORD
&& BYTES_BIG_ENDIAN
&& !backwards
)
852 value_word
= simplify_expand_binop (word_mode
, lshr_optab
,
854 GEN_INT (BITS_PER_WORD
859 if (!store_bit_field_1 (op0
, new_bitsize
,
861 bitregion_start
, bitregion_end
,
863 value_word
, reverse
, fallback_p
))
865 delete_insns_since (last
);
872 /* If VALUE has a floating-point or complex mode, access it as an
873 integer of the corresponding size. This can occur on a machine
874 with 64 bit registers that uses SFmode for float. It can also
875 occur for unaligned float or complex fields. */
877 if (GET_MODE (value
) != VOIDmode
878 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
879 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
881 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
882 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
885 /* If OP0 is a multi-word register, narrow it to the affected word.
886 If the region spans two words, defer to store_split_bit_field. */
887 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
889 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
890 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
892 bitnum
%= BITS_PER_WORD
;
893 if (bitnum
+ bitsize
> BITS_PER_WORD
)
898 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
899 bitregion_end
, value
, reverse
);
904 /* From here on we can assume that the field to be stored in fits
905 within a word. If the destination is a register, it too fits
908 extraction_insn insv
;
911 && get_best_reg_extraction_insn (&insv
, EP_insv
,
912 GET_MODE_BITSIZE (GET_MODE (op0
)),
914 && store_bit_field_using_insv (&insv
, op0
, bitsize
, bitnum
, value
))
917 /* If OP0 is a memory, try copying it to a register and seeing if a
918 cheap register alternative is available. */
919 if (MEM_P (op0
) && !reverse
)
921 if (get_best_mem_extraction_insn (&insv
, EP_insv
, bitsize
, bitnum
,
923 && store_bit_field_using_insv (&insv
, op0
, bitsize
, bitnum
, value
))
926 rtx_insn
*last
= get_last_insn ();
928 /* Try loading part of OP0 into a register, inserting the bitfield
929 into that, and then copying the result back to OP0. */
930 unsigned HOST_WIDE_INT bitpos
;
931 rtx xop0
= adjust_bit_field_mem_for_reg (EP_insv
, op0
, bitsize
, bitnum
,
932 bitregion_start
, bitregion_end
,
936 rtx tempreg
= copy_to_reg (xop0
);
937 if (store_bit_field_1 (tempreg
, bitsize
, bitpos
,
938 bitregion_start
, bitregion_end
,
939 fieldmode
, orig_value
, reverse
, false))
941 emit_move_insn (xop0
, tempreg
);
944 delete_insns_since (last
);
951 store_fixed_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
952 bitregion_end
, value
, reverse
);
956 /* Generate code to store value from rtx VALUE
957 into a bit-field within structure STR_RTX
958 containing BITSIZE bits starting at bit BITNUM.
960 BITREGION_START is bitpos of the first bitfield in this region.
961 BITREGION_END is the bitpos of the ending bitfield in this region.
962 These two fields are 0, if the C++ memory model does not apply,
963 or we are not interested in keeping track of bitfield regions.
965 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
967 If REVERSE is true, the store is to be done in reverse order. */
970 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
971 unsigned HOST_WIDE_INT bitnum
,
972 unsigned HOST_WIDE_INT bitregion_start
,
973 unsigned HOST_WIDE_INT bitregion_end
,
974 machine_mode fieldmode
,
975 rtx value
, bool reverse
)
977 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
978 if (strict_volatile_bitfield_p (str_rtx
, bitsize
, bitnum
, fieldmode
,
979 bitregion_start
, bitregion_end
))
981 /* Storing any naturally aligned field can be done with a simple
982 store. For targets that support fast unaligned memory, any
983 naturally sized, unit aligned field can be done directly. */
984 if (simple_mem_bitfield_p (str_rtx
, bitsize
, bitnum
, fieldmode
))
986 str_rtx
= adjust_bitfield_address (str_rtx
, fieldmode
,
987 bitnum
/ BITS_PER_UNIT
);
989 value
= flip_storage_order (fieldmode
, value
);
990 emit_move_insn (str_rtx
, value
);
994 str_rtx
= narrow_bit_field_mem (str_rtx
, fieldmode
, bitsize
, bitnum
,
996 /* Explicitly override the C/C++ memory model; ignore the
997 bit range so that we can do the access in the mode mandated
998 by -fstrict-volatile-bitfields instead. */
999 store_fixed_bit_field_1 (str_rtx
, bitsize
, bitnum
, value
, reverse
);
1005 /* Under the C++0x memory model, we must not touch bits outside the
1006 bit region. Adjust the address to start at the beginning of the
1008 if (MEM_P (str_rtx
) && bitregion_start
> 0)
1010 machine_mode bestmode
;
1011 HOST_WIDE_INT offset
, size
;
1013 gcc_assert ((bitregion_start
% BITS_PER_UNIT
) == 0);
1015 offset
= bitregion_start
/ BITS_PER_UNIT
;
1016 bitnum
-= bitregion_start
;
1017 size
= (bitnum
+ bitsize
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
1018 bitregion_end
-= bitregion_start
;
1019 bitregion_start
= 0;
1020 bestmode
= get_best_mode (bitsize
, bitnum
,
1021 bitregion_start
, bitregion_end
,
1022 MEM_ALIGN (str_rtx
), VOIDmode
,
1023 MEM_VOLATILE_P (str_rtx
));
1024 str_rtx
= adjust_bitfield_address_size (str_rtx
, bestmode
, offset
, size
);
1027 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
,
1028 bitregion_start
, bitregion_end
,
1029 fieldmode
, value
, reverse
, true))
1033 /* Use shifts and boolean operations to store VALUE into a bit field of
1034 width BITSIZE in OP0, starting at bit BITNUM.
1036 If REVERSE is true, the store is to be done in reverse order. */
1039 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1040 unsigned HOST_WIDE_INT bitnum
,
1041 unsigned HOST_WIDE_INT bitregion_start
,
1042 unsigned HOST_WIDE_INT bitregion_end
,
1043 rtx value
, bool reverse
)
1045 /* There is a case not handled here:
1046 a structure with a known alignment of just a halfword
1047 and a field split across two aligned halfwords within the structure.
1048 Or likewise a structure with a known alignment of just a byte
1049 and a field split across two bytes.
1050 Such cases are not supposed to be able to occur. */
1054 machine_mode mode
= GET_MODE (op0
);
1055 if (GET_MODE_BITSIZE (mode
) == 0
1056 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
1058 mode
= get_best_mode (bitsize
, bitnum
, bitregion_start
, bitregion_end
,
1059 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
1061 if (mode
== VOIDmode
)
1063 /* The only way this should occur is if the field spans word
1065 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
1066 bitregion_end
, value
, reverse
);
1070 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
1073 store_fixed_bit_field_1 (op0
, bitsize
, bitnum
, value
, reverse
);
1076 /* Helper function for store_fixed_bit_field, stores
1077 the bit field always using the MODE of OP0. */
1080 store_fixed_bit_field_1 (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1081 unsigned HOST_WIDE_INT bitnum
,
1082 rtx value
, bool reverse
)
1089 mode
= GET_MODE (op0
);
1090 gcc_assert (SCALAR_INT_MODE_P (mode
));
1092 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1093 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1095 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1096 /* BITNUM is the distance between our msb
1097 and that of the containing datum.
1098 Convert it to the distance from the lsb. */
1099 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1101 /* Now BITNUM is always the distance between our lsb
1104 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1105 we must first convert its mode to MODE. */
1107 if (CONST_INT_P (value
))
1109 unsigned HOST_WIDE_INT v
= UINTVAL (value
);
1111 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1112 v
&= ((unsigned HOST_WIDE_INT
) 1 << bitsize
) - 1;
1116 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
1117 && v
== ((unsigned HOST_WIDE_INT
) 1 << bitsize
) - 1)
1118 || (bitsize
== HOST_BITS_PER_WIDE_INT
1119 && v
== (unsigned HOST_WIDE_INT
) -1))
1122 value
= lshift_value (mode
, v
, bitnum
);
1126 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
1127 && bitnum
+ bitsize
!= GET_MODE_BITSIZE (mode
));
1129 if (GET_MODE (value
) != mode
)
1130 value
= convert_to_mode (mode
, value
, 1);
1133 value
= expand_binop (mode
, and_optab
, value
,
1134 mask_rtx (mode
, 0, bitsize
, 0),
1135 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1137 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
1138 bitnum
, NULL_RTX
, 1);
1142 value
= flip_storage_order (mode
, value
);
1144 /* Now clear the chosen bits in OP0,
1145 except that if VALUE is -1 we need not bother. */
1146 /* We keep the intermediates in registers to allow CSE to combine
1147 consecutive bitfield assignments. */
1149 temp
= force_reg (mode
, op0
);
1153 rtx mask
= mask_rtx (mode
, bitnum
, bitsize
, 1);
1155 mask
= flip_storage_order (mode
, mask
);
1156 temp
= expand_binop (mode
, and_optab
, temp
, mask
,
1157 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1158 temp
= force_reg (mode
, temp
);
1161 /* Now logical-or VALUE into OP0, unless it is zero. */
1165 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
1166 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1167 temp
= force_reg (mode
, temp
);
1172 op0
= copy_rtx (op0
);
1173 emit_move_insn (op0
, temp
);
1177 /* Store a bit field that is split across multiple accessible memory objects.
1179 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1180 BITSIZE is the field width; BITPOS the position of its first bit
1182 VALUE is the value to store.
1184 If REVERSE is true, the store is to be done in reverse order.
1186 This does not yet handle fields wider than BITS_PER_WORD. */
1189 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1190 unsigned HOST_WIDE_INT bitpos
,
1191 unsigned HOST_WIDE_INT bitregion_start
,
1192 unsigned HOST_WIDE_INT bitregion_end
,
1193 rtx value
, bool reverse
)
1195 unsigned int unit
, total_bits
, bitsdone
= 0;
1197 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1199 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1200 unit
= BITS_PER_WORD
;
1202 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1204 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1205 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1206 again, and we will mutually recurse forever. */
1207 if (MEM_P (op0
) && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0)
1208 unit
= MIN (unit
, GET_MODE_BITSIZE (GET_MODE (op0
)));
1210 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1211 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1212 that VALUE might be a floating-point constant. */
1213 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1215 rtx word
= gen_lowpart_common (word_mode
, value
);
1217 if (word
&& (value
!= word
))
1220 value
= gen_lowpart_common (word_mode
,
1221 force_reg (GET_MODE (value
) != VOIDmode
1223 : word_mode
, value
));
1226 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
1228 while (bitsdone
< bitsize
)
1230 unsigned HOST_WIDE_INT thissize
;
1231 unsigned HOST_WIDE_INT thispos
;
1232 unsigned HOST_WIDE_INT offset
;
1235 offset
= (bitpos
+ bitsdone
) / unit
;
1236 thispos
= (bitpos
+ bitsdone
) % unit
;
1238 /* When region of bytes we can touch is restricted, decrease
1239 UNIT close to the end of the region as needed. If op0 is a REG
1240 or SUBREG of REG, don't do this, as there can't be data races
1241 on a register and we can expand shorter code in some cases. */
1243 && unit
> BITS_PER_UNIT
1244 && bitpos
+ bitsdone
- thispos
+ unit
> bitregion_end
+ 1
1246 && (GET_CODE (op0
) != SUBREG
|| !REG_P (SUBREG_REG (op0
))))
1252 /* THISSIZE must not overrun a word boundary. Otherwise,
1253 store_fixed_bit_field will call us again, and we will mutually
1255 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1256 thissize
= MIN (thissize
, unit
- thispos
);
1258 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1260 /* Fetch successively less significant portions. */
1261 if (CONST_INT_P (value
))
1262 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1263 >> (bitsize
- bitsdone
- thissize
))
1264 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1265 /* Likewise, but the source is little-endian. */
1267 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1268 bitsize
- bitsdone
- thissize
,
1269 NULL_RTX
, 1, false);
1272 int total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
1273 /* The args are chosen so that the last part includes the
1274 lsb. Give extract_bit_field the value it needs (with
1275 endianness compensation) to fetch the piece we want. */
1276 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1277 total_bits
- bitsize
+ bitsdone
,
1278 NULL_RTX
, 1, false);
1283 /* Fetch successively more significant portions. */
1284 if (CONST_INT_P (value
))
1285 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1287 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1288 /* Likewise, but the source is big-endian. */
1290 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1291 total_bits
- bitsdone
- thissize
,
1292 NULL_RTX
, 1, false);
1294 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1295 bitsdone
, NULL_RTX
, 1, false);
1298 /* If OP0 is a register, then handle OFFSET here.
1300 When handling multiword bitfields, extract_bit_field may pass
1301 down a word_mode SUBREG of a larger REG for a bitfield that actually
1302 crosses a word boundary. Thus, for a SUBREG, we must find
1303 the current word starting from the base register. */
1304 if (GET_CODE (op0
) == SUBREG
)
1306 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
)
1307 + (offset
* unit
/ BITS_PER_WORD
);
1308 machine_mode sub_mode
= GET_MODE (SUBREG_REG (op0
));
1309 if (sub_mode
!= BLKmode
&& GET_MODE_SIZE (sub_mode
) < UNITS_PER_WORD
)
1310 word
= word_offset
? const0_rtx
: op0
;
1312 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1313 GET_MODE (SUBREG_REG (op0
)));
1314 offset
&= BITS_PER_WORD
/ unit
- 1;
1316 else if (REG_P (op0
))
1318 machine_mode op0_mode
= GET_MODE (op0
);
1319 if (op0_mode
!= BLKmode
&& GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
)
1320 word
= offset
? const0_rtx
: op0
;
1322 word
= operand_subword_force (op0
, offset
* unit
/ BITS_PER_WORD
,
1324 offset
&= BITS_PER_WORD
/ unit
- 1;
1329 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1330 it is just an out-of-bounds access. Ignore it. */
1331 if (word
!= const0_rtx
)
1332 store_fixed_bit_field (word
, thissize
, offset
* unit
+ thispos
,
1333 bitregion_start
, bitregion_end
, part
,
1335 bitsdone
+= thissize
;
1339 /* A subroutine of extract_bit_field_1 that converts return value X
1340 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1341 to extract_bit_field. */
1344 convert_extracted_bit_field (rtx x
, machine_mode mode
,
1345 machine_mode tmode
, bool unsignedp
)
1347 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1350 /* If the x mode is not a scalar integral, first convert to the
1351 integer mode of that size and then access it as a floating-point
1352 value via a SUBREG. */
1353 if (!SCALAR_INT_MODE_P (tmode
))
1357 smode
= mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1358 x
= convert_to_mode (smode
, x
, unsignedp
);
1359 x
= force_reg (smode
, x
);
1360 return gen_lowpart (tmode
, x
);
1363 return convert_to_mode (tmode
, x
, unsignedp
);
1366 /* Try to use an ext(z)v pattern to extract a field from OP0.
1367 Return the extracted value on success, otherwise return null.
1368 EXT_MODE is the mode of the extraction and the other arguments
1369 are as for extract_bit_field. */
1372 extract_bit_field_using_extv (const extraction_insn
*extv
, rtx op0
,
1373 unsigned HOST_WIDE_INT bitsize
,
1374 unsigned HOST_WIDE_INT bitnum
,
1375 int unsignedp
, rtx target
,
1376 machine_mode mode
, machine_mode tmode
)
1378 struct expand_operand ops
[4];
1379 rtx spec_target
= target
;
1380 rtx spec_target_subreg
= 0;
1381 machine_mode ext_mode
= extv
->field_mode
;
1382 unsigned unit
= GET_MODE_BITSIZE (ext_mode
);
1384 if (bitsize
== 0 || unit
< bitsize
)
1388 /* Get a reference to the first byte of the field. */
1389 op0
= narrow_bit_field_mem (op0
, extv
->struct_mode
, bitsize
, bitnum
,
1393 /* Convert from counting within OP0 to counting in EXT_MODE. */
1394 if (BYTES_BIG_ENDIAN
)
1395 bitnum
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1397 /* If op0 is a register, we need it in EXT_MODE to make it
1398 acceptable to the format of ext(z)v. */
1399 if (GET_CODE (op0
) == SUBREG
&& GET_MODE (op0
) != ext_mode
)
1401 if (REG_P (op0
) && GET_MODE (op0
) != ext_mode
)
1402 op0
= gen_lowpart_SUBREG (ext_mode
, op0
);
1405 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1406 "backwards" from the size of the unit we are extracting from.
1407 Otherwise, we count bits from the most significant on a
1408 BYTES/BITS_BIG_ENDIAN machine. */
1410 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1411 bitnum
= unit
- bitsize
- bitnum
;
1414 target
= spec_target
= gen_reg_rtx (tmode
);
1416 if (GET_MODE (target
) != ext_mode
)
1418 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1419 between the mode of the extraction (word_mode) and the target
1420 mode. Instead, create a temporary and use convert_move to set
1423 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target
), ext_mode
))
1425 target
= gen_lowpart (ext_mode
, target
);
1426 if (GET_MODE_PRECISION (ext_mode
)
1427 > GET_MODE_PRECISION (GET_MODE (spec_target
)))
1428 spec_target_subreg
= target
;
1431 target
= gen_reg_rtx (ext_mode
);
1434 create_output_operand (&ops
[0], target
, ext_mode
);
1435 create_fixed_operand (&ops
[1], op0
);
1436 create_integer_operand (&ops
[2], bitsize
);
1437 create_integer_operand (&ops
[3], bitnum
);
1438 if (maybe_expand_insn (extv
->icode
, 4, ops
))
1440 target
= ops
[0].value
;
1441 if (target
== spec_target
)
1443 if (target
== spec_target_subreg
)
1445 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1450 /* A subroutine of extract_bit_field, with the same arguments.
1451 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1452 if we can find no other means of implementing the operation.
1453 if FALLBACK_P is false, return NULL instead. */
1456 extract_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1457 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1458 machine_mode mode
, machine_mode tmode
,
1459 bool reverse
, bool fallback_p
)
1462 machine_mode int_mode
;
1465 if (tmode
== VOIDmode
)
1468 while (GET_CODE (op0
) == SUBREG
)
1470 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1471 op0
= SUBREG_REG (op0
);
1474 /* If we have an out-of-bounds access to a register, just return an
1475 uninitialized register of the required mode. This can occur if the
1476 source code contains an out-of-bounds access to a small array. */
1477 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
1478 return gen_reg_rtx (tmode
);
1481 && mode
== GET_MODE (op0
)
1483 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1486 op0
= flip_storage_order (mode
, op0
);
1487 /* We're trying to extract a full register from itself. */
1491 /* See if we can get a better vector mode before extracting. */
1492 if (VECTOR_MODE_P (GET_MODE (op0
))
1494 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1496 machine_mode new_mode
;
1498 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1499 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1500 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1501 new_mode
= MIN_MODE_VECTOR_FRACT
;
1502 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1503 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1504 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1505 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1506 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1507 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1509 new_mode
= MIN_MODE_VECTOR_INT
;
1511 for (; new_mode
!= VOIDmode
; new_mode
= GET_MODE_WIDER_MODE (new_mode
))
1512 if (GET_MODE_SIZE (new_mode
) == GET_MODE_SIZE (GET_MODE (op0
))
1513 && targetm
.vector_mode_supported_p (new_mode
))
1515 if (new_mode
!= VOIDmode
)
1516 op0
= gen_lowpart (new_mode
, op0
);
1519 /* Use vec_extract patterns for extracting parts of vectors whenever
1521 if (VECTOR_MODE_P (GET_MODE (op0
))
1523 && optab_handler (vec_extract_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
1524 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1525 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1527 struct expand_operand ops
[3];
1528 machine_mode outermode
= GET_MODE (op0
);
1529 machine_mode innermode
= GET_MODE_INNER (outermode
);
1530 enum insn_code icode
= optab_handler (vec_extract_optab
, outermode
);
1531 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1533 create_output_operand (&ops
[0], target
, innermode
);
1534 create_input_operand (&ops
[1], op0
, outermode
);
1535 create_integer_operand (&ops
[2], pos
);
1536 if (maybe_expand_insn (icode
, 3, ops
))
1538 target
= ops
[0].value
;
1539 if (GET_MODE (target
) != mode
)
1540 return gen_lowpart (tmode
, target
);
1545 /* Make sure we are playing with integral modes. Pun with subregs
1548 machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1549 if (imode
!= GET_MODE (op0
))
1552 op0
= adjust_bitfield_address_size (op0
, imode
, 0, MEM_SIZE (op0
));
1553 else if (imode
!= BLKmode
)
1555 op0
= gen_lowpart (imode
, op0
);
1557 /* If we got a SUBREG, force it into a register since we
1558 aren't going to be able to do another SUBREG on it. */
1559 if (GET_CODE (op0
) == SUBREG
)
1560 op0
= force_reg (imode
, op0
);
1562 else if (REG_P (op0
))
1565 imode
= smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0
)),
1567 reg
= gen_reg_rtx (imode
);
1568 subreg
= gen_lowpart_SUBREG (GET_MODE (op0
), reg
);
1569 emit_move_insn (subreg
, op0
);
1571 bitnum
+= SUBREG_BYTE (subreg
) * BITS_PER_UNIT
;
1575 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (op0
));
1576 rtx mem
= assign_stack_temp (GET_MODE (op0
), size
);
1577 emit_move_insn (mem
, op0
);
1578 op0
= adjust_bitfield_address_size (mem
, BLKmode
, 0, size
);
1583 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1584 If that's wrong, the solution is to test for it and set TARGET to 0
1587 /* Get the mode of the field to use for atomic access or subreg
1590 if (SCALAR_INT_MODE_P (tmode
))
1592 machine_mode try_mode
= mode_for_size (bitsize
,
1593 GET_MODE_CLASS (tmode
), 0);
1594 if (try_mode
!= BLKmode
)
1597 gcc_assert (mode1
!= BLKmode
);
1599 /* Extraction of a full MODE1 value can be done with a subreg as long
1600 as the least significant bit of the value is the least significant
1601 bit of either OP0 or a word of OP0. */
1604 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
1605 && bitsize
== GET_MODE_BITSIZE (mode1
)
1606 && TRULY_NOOP_TRUNCATION_MODES_P (mode1
, GET_MODE (op0
)))
1608 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1609 bitnum
/ BITS_PER_UNIT
);
1611 return convert_extracted_bit_field (sub
, mode
, tmode
, unsignedp
);
1614 /* Extraction of a full MODE1 value can be done with a load as long as
1615 the field is on a byte boundary and is sufficiently aligned. */
1616 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, mode1
))
1618 op0
= adjust_bitfield_address (op0
, mode1
, bitnum
/ BITS_PER_UNIT
);
1620 op0
= flip_storage_order (mode1
, op0
);
1621 return convert_extracted_bit_field (op0
, mode
, tmode
, unsignedp
);
1624 /* Handle fields bigger than a word. */
1626 if (bitsize
> BITS_PER_WORD
)
1628 /* Here we transfer the words of the field
1629 in the order least significant first.
1630 This is because the most significant word is the one which may
1631 be less than full. */
1633 const bool backwards
= WORDS_BIG_ENDIAN
;
1634 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1638 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1639 target
= gen_reg_rtx (mode
);
1641 /* Indicate for flow that the entire target reg is being set. */
1642 emit_clobber (target
);
1644 last
= get_last_insn ();
1645 for (i
= 0; i
< nwords
; i
++)
1647 /* If I is 0, use the low-order word in both field and target;
1648 if I is 1, use the next to lowest word; and so on. */
1649 /* Word number in TARGET to use. */
1650 unsigned int wordnum
1652 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1654 /* Offset from start of field in OP0. */
1655 unsigned int bit_offset
= (backwards
^ reverse
1656 ? MAX ((int) bitsize
- ((int) i
+ 1)
1659 : (int) i
* BITS_PER_WORD
);
1660 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1662 = extract_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
1663 bitsize
- i
* BITS_PER_WORD
),
1664 bitnum
+ bit_offset
, 1, target_part
,
1665 mode
, word_mode
, reverse
, fallback_p
);
1667 gcc_assert (target_part
);
1670 delete_insns_since (last
);
1674 if (result_part
!= target_part
)
1675 emit_move_insn (target_part
, result_part
);
1680 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1681 need to be zero'd out. */
1682 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1684 unsigned int i
, total_words
;
1686 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1687 for (i
= nwords
; i
< total_words
; i
++)
1689 (operand_subword (target
,
1690 backwards
? total_words
- i
- 1 : i
,
1697 /* Signed bit field: sign-extend with two arithmetic shifts. */
1698 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1699 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1700 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1701 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1704 /* If OP0 is a multi-word register, narrow it to the affected word.
1705 If the region spans two words, defer to extract_split_bit_field. */
1706 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1708 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
1709 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1710 bitnum
%= BITS_PER_WORD
;
1711 if (bitnum
+ bitsize
> BITS_PER_WORD
)
1715 target
= extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
,
1717 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1721 /* From here on we know the desired field is smaller than a word.
1722 If OP0 is a register, it too fits within a word. */
1723 enum extraction_pattern pattern
= unsignedp
? EP_extzv
: EP_extv
;
1724 extraction_insn extv
;
1727 /* ??? We could limit the structure size to the part of OP0 that
1728 contains the field, with appropriate checks for endianness
1729 and TRULY_NOOP_TRUNCATION. */
1730 && get_best_reg_extraction_insn (&extv
, pattern
,
1731 GET_MODE_BITSIZE (GET_MODE (op0
)),
1734 rtx result
= extract_bit_field_using_extv (&extv
, op0
, bitsize
, bitnum
,
1735 unsignedp
, target
, mode
,
1741 /* If OP0 is a memory, try copying it to a register and seeing if a
1742 cheap register alternative is available. */
1743 if (MEM_P (op0
) & !reverse
)
1745 if (get_best_mem_extraction_insn (&extv
, pattern
, bitsize
, bitnum
,
1748 rtx result
= extract_bit_field_using_extv (&extv
, op0
, bitsize
,
1756 rtx_insn
*last
= get_last_insn ();
1758 /* Try loading part of OP0 into a register and extracting the
1759 bitfield from that. */
1760 unsigned HOST_WIDE_INT bitpos
;
1761 rtx xop0
= adjust_bit_field_mem_for_reg (pattern
, op0
, bitsize
, bitnum
,
1762 0, 0, tmode
, &bitpos
);
1765 xop0
= copy_to_reg (xop0
);
1766 rtx result
= extract_bit_field_1 (xop0
, bitsize
, bitpos
,
1768 mode
, tmode
, reverse
, false);
1771 delete_insns_since (last
);
1778 /* Find a correspondingly-sized integer field, so we can apply
1779 shifts and masks to it. */
1780 int_mode
= int_mode_for_mode (tmode
);
1781 if (int_mode
== BLKmode
)
1782 int_mode
= int_mode_for_mode (mode
);
1783 /* Should probably push op0 out to memory and then do a load. */
1784 gcc_assert (int_mode
!= BLKmode
);
1786 target
= extract_fixed_bit_field (int_mode
, op0
, bitsize
, bitnum
,
1787 target
, unsignedp
, reverse
);
1788 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1791 /* Generate code to extract a byte-field from STR_RTX
1792 containing BITSIZE bits, starting at BITNUM,
1793 and put it in TARGET if possible (if TARGET is nonzero).
1794 Regardless of TARGET, we return the rtx for where the value is placed.
1796 STR_RTX is the structure containing the byte (a REG or MEM).
1797 UNSIGNEDP is nonzero if this is an unsigned bit field.
1798 MODE is the natural mode of the field value once extracted.
1799 TMODE is the mode the caller would like the value to have;
1800 but the value may be returned with type MODE instead.
1802 If REVERSE is true, the extraction is to be done in reverse order.
1804 If a TARGET is specified and we can store in it at no extra cost,
1805 we do so, and return TARGET.
1806 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1807 if they are equally easy. */
1810 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1811 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1812 machine_mode mode
, machine_mode tmode
, bool reverse
)
1816 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1817 if (GET_MODE_BITSIZE (GET_MODE (str_rtx
)) > 0)
1818 mode1
= GET_MODE (str_rtx
);
1819 else if (target
&& GET_MODE_BITSIZE (GET_MODE (target
)) > 0)
1820 mode1
= GET_MODE (target
);
1824 if (strict_volatile_bitfield_p (str_rtx
, bitsize
, bitnum
, mode1
, 0, 0))
1828 /* Extraction of a full MODE1 value can be done with a load as long as
1829 the field is on a byte boundary and is sufficiently aligned. */
1830 if (simple_mem_bitfield_p (str_rtx
, bitsize
, bitnum
, mode1
))
1832 result
= adjust_bitfield_address (str_rtx
, mode1
,
1833 bitnum
/ BITS_PER_UNIT
);
1835 result
= flip_storage_order (mode1
, result
);
1839 str_rtx
= narrow_bit_field_mem (str_rtx
, mode1
, bitsize
, bitnum
,
1841 result
= extract_fixed_bit_field_1 (mode
, str_rtx
, bitsize
, bitnum
,
1842 target
, unsignedp
, reverse
);
1845 return convert_extracted_bit_field (result
, mode
, tmode
, unsignedp
);
1848 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
,
1849 target
, mode
, tmode
, reverse
, true);
1852 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1853 from bit BITNUM of OP0.
1855 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1856 If REVERSE is true, the extraction is to be done in reverse order.
1858 If TARGET is nonzero, attempts to store the value there
1859 and return TARGET, but this is not guaranteed.
1860 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1863 extract_fixed_bit_field (machine_mode tmode
, rtx op0
,
1864 unsigned HOST_WIDE_INT bitsize
,
1865 unsigned HOST_WIDE_INT bitnum
, rtx target
,
1866 int unsignedp
, bool reverse
)
1871 = get_best_mode (bitsize
, bitnum
, 0, 0, MEM_ALIGN (op0
), word_mode
,
1872 MEM_VOLATILE_P (op0
));
1874 if (mode
== VOIDmode
)
1875 /* The only way this should occur is if the field spans word
1877 return extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
,
1880 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
1883 return extract_fixed_bit_field_1 (tmode
, op0
, bitsize
, bitnum
,
1884 target
, unsignedp
, reverse
);
1887 /* Helper function for extract_fixed_bit_field, extracts
1888 the bit field always using the MODE of OP0. */
1891 extract_fixed_bit_field_1 (machine_mode tmode
, rtx op0
,
1892 unsigned HOST_WIDE_INT bitsize
,
1893 unsigned HOST_WIDE_INT bitnum
, rtx target
,
1894 int unsignedp
, bool reverse
)
1896 machine_mode mode
= GET_MODE (op0
);
1897 gcc_assert (SCALAR_INT_MODE_P (mode
));
1899 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1900 for invalid input, such as extract equivalent of f5 from
1901 gcc.dg/pr48335-2.c. */
1903 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1904 /* BITNUM is the distance between our msb and that of OP0.
1905 Convert it to the distance from the lsb. */
1906 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1908 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1909 We have reduced the big-endian case to the little-endian case. */
1911 op0
= flip_storage_order (mode
, op0
);
1917 /* If the field does not already start at the lsb,
1918 shift it so it does. */
1919 /* Maybe propagate the target for the shift. */
1920 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1923 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, bitnum
, subtarget
, 1);
1925 /* Convert the value to the desired mode. */
1927 op0
= convert_to_mode (tmode
, op0
, 1);
1929 /* Unless the msb of the field used to be the msb when we shifted,
1930 mask out the upper bits. */
1932 if (GET_MODE_BITSIZE (mode
) != bitnum
+ bitsize
)
1933 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1934 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1935 target
, 1, OPTAB_LIB_WIDEN
);
1939 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1940 then arithmetic-shift its lsb to the lsb of the word. */
1941 op0
= force_reg (mode
, op0
);
1943 /* Find the narrowest integer mode that contains the field. */
1945 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1946 mode
= GET_MODE_WIDER_MODE (mode
))
1947 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitnum
)
1949 op0
= convert_to_mode (mode
, op0
, 0);
1956 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitnum
))
1958 int amount
= GET_MODE_BITSIZE (mode
) - (bitsize
+ bitnum
);
1959 /* Maybe propagate the target for the shift. */
1960 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1961 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1964 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1965 GET_MODE_BITSIZE (mode
) - bitsize
, target
, 0);
1968 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1972 lshift_value (machine_mode mode
, unsigned HOST_WIDE_INT value
,
1975 return immed_wide_int_const (wi::lshift (value
, bitpos
), mode
);
1978 /* Extract a bit field that is split across two words
1979 and return an RTX for the result.
1981 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1982 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1983 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1985 If REVERSE is true, the extraction is to be done in reverse order. */
1988 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1989 unsigned HOST_WIDE_INT bitpos
, int unsignedp
,
1993 unsigned int bitsdone
= 0;
1994 rtx result
= NULL_RTX
;
1997 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1999 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
2000 unit
= BITS_PER_WORD
;
2002 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
2004 while (bitsdone
< bitsize
)
2006 unsigned HOST_WIDE_INT thissize
;
2008 unsigned HOST_WIDE_INT thispos
;
2009 unsigned HOST_WIDE_INT offset
;
2011 offset
= (bitpos
+ bitsdone
) / unit
;
2012 thispos
= (bitpos
+ bitsdone
) % unit
;
2014 /* THISSIZE must not overrun a word boundary. Otherwise,
2015 extract_fixed_bit_field will call us again, and we will mutually
2017 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
2018 thissize
= MIN (thissize
, unit
- thispos
);
2020 /* If OP0 is a register, then handle OFFSET here.
2022 When handling multiword bitfields, extract_bit_field may pass
2023 down a word_mode SUBREG of a larger REG for a bitfield that actually
2024 crosses a word boundary. Thus, for a SUBREG, we must find
2025 the current word starting from the base register. */
2026 if (GET_CODE (op0
) == SUBREG
)
2028 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
2029 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
2030 GET_MODE (SUBREG_REG (op0
)));
2033 else if (REG_P (op0
))
2035 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
2041 /* Extract the parts in bit-counting order,
2042 whose meaning is determined by BYTES_PER_UNIT.
2043 OFFSET is in UNITs, and UNIT is in bits. */
2044 part
= extract_fixed_bit_field (word_mode
, word
, thissize
,
2045 offset
* unit
+ thispos
, 0, 1, reverse
);
2046 bitsdone
+= thissize
;
2048 /* Shift this part into place for the result. */
2049 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
2051 if (bitsize
!= bitsdone
)
2052 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2053 bitsize
- bitsdone
, 0, 1);
2057 if (bitsdone
!= thissize
)
2058 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2059 bitsdone
- thissize
, 0, 1);
2065 /* Combine the parts with bitwise or. This works
2066 because we extracted each part as an unsigned bit field. */
2067 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2073 /* Unsigned bit field: we are done. */
2076 /* Signed bit field: sign-extend with two arithmetic shifts. */
2077 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2078 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
2079 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2080 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
2083 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2084 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2085 MODE, fill the upper bits with zeros. Fail if the layout of either
2086 mode is unknown (as for CC modes) or if the extraction would involve
2087 unprofitable mode punning. Return the value on success, otherwise
2090 This is different from gen_lowpart* in these respects:
2092 - the returned value must always be considered an rvalue
2094 - when MODE is wider than SRC_MODE, the extraction involves
2097 - when MODE is smaller than SRC_MODE, the extraction involves
2098 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2100 In other words, this routine performs a computation, whereas the
2101 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2105 extract_low_bits (machine_mode mode
, machine_mode src_mode
, rtx src
)
2107 machine_mode int_mode
, src_int_mode
;
2109 if (mode
== src_mode
)
2112 if (CONSTANT_P (src
))
2114 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2115 fails, it will happily create (subreg (symbol_ref)) or similar
2117 unsigned int byte
= subreg_lowpart_offset (mode
, src_mode
);
2118 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
2122 if (GET_MODE (src
) == VOIDmode
2123 || !validate_subreg (mode
, src_mode
, src
, byte
))
2126 src
= force_reg (GET_MODE (src
), src
);
2127 return gen_rtx_SUBREG (mode
, src
, byte
);
2130 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
2133 if (GET_MODE_BITSIZE (mode
) == GET_MODE_BITSIZE (src_mode
)
2134 && MODES_TIEABLE_P (mode
, src_mode
))
2136 rtx x
= gen_lowpart_common (mode
, src
);
2141 src_int_mode
= int_mode_for_mode (src_mode
);
2142 int_mode
= int_mode_for_mode (mode
);
2143 if (src_int_mode
== BLKmode
|| int_mode
== BLKmode
)
2146 if (!MODES_TIEABLE_P (src_int_mode
, src_mode
))
2148 if (!MODES_TIEABLE_P (int_mode
, mode
))
2151 src
= gen_lowpart (src_int_mode
, src
);
2152 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2153 src
= gen_lowpart (mode
, src
);
2157 /* Add INC into TARGET. */
2160 expand_inc (rtx target
, rtx inc
)
2162 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2164 target
, 0, OPTAB_LIB_WIDEN
);
2165 if (value
!= target
)
2166 emit_move_insn (target
, value
);
2169 /* Subtract DEC from TARGET. */
2172 expand_dec (rtx target
, rtx dec
)
2174 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2176 target
, 0, OPTAB_LIB_WIDEN
);
2177 if (value
!= target
)
2178 emit_move_insn (target
, value
);
2181 /* Output a shift instruction for expression code CODE,
2182 with SHIFTED being the rtx for the value to shift,
2183 and AMOUNT the rtx for the amount to shift by.
2184 Store the result in the rtx TARGET, if that is convenient.
2185 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2186 Return the rtx for where the value is. */
2189 expand_shift_1 (enum tree_code code
, machine_mode mode
, rtx shifted
,
2190 rtx amount
, rtx target
, int unsignedp
)
2193 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2194 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2195 optab lshift_optab
= ashl_optab
;
2196 optab rshift_arith_optab
= ashr_optab
;
2197 optab rshift_uns_optab
= lshr_optab
;
2198 optab lrotate_optab
= rotl_optab
;
2199 optab rrotate_optab
= rotr_optab
;
2200 machine_mode op1_mode
;
2201 machine_mode scalar_mode
= mode
;
2203 bool speed
= optimize_insn_for_speed_p ();
2205 if (VECTOR_MODE_P (mode
))
2206 scalar_mode
= GET_MODE_INNER (mode
);
2208 op1_mode
= GET_MODE (op1
);
2210 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2211 shift amount is a vector, use the vector/vector shift patterns. */
2212 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2214 lshift_optab
= vashl_optab
;
2215 rshift_arith_optab
= vashr_optab
;
2216 rshift_uns_optab
= vlshr_optab
;
2217 lrotate_optab
= vrotl_optab
;
2218 rrotate_optab
= vrotr_optab
;
2221 /* Previously detected shift-counts computed by NEGATE_EXPR
2222 and shifted in the other direction; but that does not work
2225 if (SHIFT_COUNT_TRUNCATED
)
2227 if (CONST_INT_P (op1
)
2228 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2229 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (scalar_mode
)))
2230 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2231 % GET_MODE_BITSIZE (scalar_mode
));
2232 else if (GET_CODE (op1
) == SUBREG
2233 && subreg_lowpart_p (op1
)
2234 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1
)))
2235 && SCALAR_INT_MODE_P (GET_MODE (op1
)))
2236 op1
= SUBREG_REG (op1
);
2239 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2240 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2241 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2244 && CONST_INT_P (op1
)
2245 && IN_RANGE (INTVAL (op1
), GET_MODE_BITSIZE (scalar_mode
) / 2 + left
,
2246 GET_MODE_BITSIZE (scalar_mode
) - 1))
2248 op1
= GEN_INT (GET_MODE_BITSIZE (scalar_mode
) - INTVAL (op1
));
2250 code
= left
? LROTATE_EXPR
: RROTATE_EXPR
;
2253 if (op1
== const0_rtx
)
2256 /* Check whether its cheaper to implement a left shift by a constant
2257 bit count by a sequence of additions. */
2258 if (code
== LSHIFT_EXPR
2259 && CONST_INT_P (op1
)
2261 && INTVAL (op1
) < GET_MODE_PRECISION (scalar_mode
)
2262 && INTVAL (op1
) < MAX_BITS_PER_WORD
2263 && (shift_cost (speed
, mode
, INTVAL (op1
))
2264 > INTVAL (op1
) * add_cost (speed
, mode
))
2265 && shift_cost (speed
, mode
, INTVAL (op1
)) != MAX_COST
)
2268 for (i
= 0; i
< INTVAL (op1
); i
++)
2270 temp
= force_reg (mode
, shifted
);
2271 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2272 unsignedp
, OPTAB_LIB_WIDEN
);
2277 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2279 enum optab_methods methods
;
2282 methods
= OPTAB_DIRECT
;
2283 else if (attempt
== 1)
2284 methods
= OPTAB_WIDEN
;
2286 methods
= OPTAB_LIB_WIDEN
;
2290 /* Widening does not work for rotation. */
2291 if (methods
== OPTAB_WIDEN
)
2293 else if (methods
== OPTAB_LIB_WIDEN
)
2295 /* If we have been unable to open-code this by a rotation,
2296 do it as the IOR of two shifts. I.e., to rotate A
2298 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2299 where C is the bitsize of A.
2301 It is theoretically possible that the target machine might
2302 not be able to perform either shift and hence we would
2303 be making two libcalls rather than just the one for the
2304 shift (similarly if IOR could not be done). We will allow
2305 this extremely unlikely lossage to avoid complicating the
2308 rtx subtarget
= target
== shifted
? 0 : target
;
2309 rtx new_amount
, other_amount
;
2313 if (op1
== const0_rtx
)
2315 else if (CONST_INT_P (op1
))
2316 other_amount
= GEN_INT (GET_MODE_BITSIZE (scalar_mode
)
2321 = simplify_gen_unary (NEG
, GET_MODE (op1
),
2322 op1
, GET_MODE (op1
));
2323 HOST_WIDE_INT mask
= GET_MODE_PRECISION (scalar_mode
) - 1;
2325 = simplify_gen_binary (AND
, GET_MODE (op1
), other_amount
,
2326 gen_int_mode (mask
, GET_MODE (op1
)));
2329 shifted
= force_reg (mode
, shifted
);
2331 temp
= expand_shift_1 (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2332 mode
, shifted
, new_amount
, 0, 1);
2333 temp1
= expand_shift_1 (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2334 mode
, shifted
, other_amount
,
2336 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2337 unsignedp
, methods
);
2340 temp
= expand_binop (mode
,
2341 left
? lrotate_optab
: rrotate_optab
,
2342 shifted
, op1
, target
, unsignedp
, methods
);
2345 temp
= expand_binop (mode
,
2346 left
? lshift_optab
: rshift_uns_optab
,
2347 shifted
, op1
, target
, unsignedp
, methods
);
2349 /* Do arithmetic shifts.
2350 Also, if we are going to widen the operand, we can just as well
2351 use an arithmetic right-shift instead of a logical one. */
2352 if (temp
== 0 && ! rotate
2353 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2355 enum optab_methods methods1
= methods
;
2357 /* If trying to widen a log shift to an arithmetic shift,
2358 don't accept an arithmetic shift of the same size. */
2360 methods1
= OPTAB_MUST_WIDEN
;
2362 /* Arithmetic shift */
2364 temp
= expand_binop (mode
,
2365 left
? lshift_optab
: rshift_arith_optab
,
2366 shifted
, op1
, target
, unsignedp
, methods1
);
2369 /* We used to try extzv here for logical right shifts, but that was
2370 only useful for one machine, the VAX, and caused poor code
2371 generation there for lshrdi3, so the code was deleted and a
2372 define_expand for lshrsi3 was added to vax.md. */
2379 /* Output a shift instruction for expression code CODE,
2380 with SHIFTED being the rtx for the value to shift,
2381 and AMOUNT the amount to shift by.
2382 Store the result in the rtx TARGET, if that is convenient.
2383 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2384 Return the rtx for where the value is. */
2387 expand_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2388 int amount
, rtx target
, int unsignedp
)
2390 return expand_shift_1 (code
, mode
,
2391 shifted
, GEN_INT (amount
), target
, unsignedp
);
2394 /* Output a shift instruction for expression code CODE,
2395 with SHIFTED being the rtx for the value to shift,
2396 and AMOUNT the tree for the amount to shift by.
2397 Store the result in the rtx TARGET, if that is convenient.
2398 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2399 Return the rtx for where the value is. */
2402 expand_variable_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2403 tree amount
, rtx target
, int unsignedp
)
2405 return expand_shift_1 (code
, mode
,
2406 shifted
, expand_normal (amount
), target
, unsignedp
);
2410 /* Indicates the type of fixup needed after a constant multiplication.
2411 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2412 the result should be negated, and ADD_VARIANT means that the
2413 multiplicand should be added to the result. */
2414 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2416 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2417 const struct mult_cost
*, machine_mode mode
);
2418 static bool choose_mult_variant (machine_mode
, HOST_WIDE_INT
,
2419 struct algorithm
*, enum mult_variant
*, int);
2420 static rtx
expand_mult_const (machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2421 const struct algorithm
*, enum mult_variant
);
2422 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2423 static rtx
extract_high_half (machine_mode
, rtx
);
2424 static rtx
expmed_mult_highpart (machine_mode
, rtx
, rtx
, rtx
, int, int);
2425 static rtx
expmed_mult_highpart_optab (machine_mode
, rtx
, rtx
, rtx
,
2427 /* Compute and return the best algorithm for multiplying by T.
2428 The algorithm must cost less than cost_limit
2429 If retval.cost >= COST_LIMIT, no algorithm was found and all
2430 other field of the returned struct are undefined.
2431 MODE is the machine mode of the multiplication. */
2434 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2435 const struct mult_cost
*cost_limit
, machine_mode mode
)
2438 struct algorithm
*alg_in
, *best_alg
;
2439 struct mult_cost best_cost
;
2440 struct mult_cost new_limit
;
2441 int op_cost
, op_latency
;
2442 unsigned HOST_WIDE_INT orig_t
= t
;
2443 unsigned HOST_WIDE_INT q
;
2444 int maxm
, hash_index
;
2445 bool cache_hit
= false;
2446 enum alg_code cache_alg
= alg_zero
;
2447 bool speed
= optimize_insn_for_speed_p ();
2449 struct alg_hash_entry
*entry_ptr
;
2451 /* Indicate that no algorithm is yet found. If no algorithm
2452 is found, this value will be returned and indicate failure. */
2453 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2454 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2456 if (cost_limit
->cost
< 0
2457 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2460 /* Be prepared for vector modes. */
2461 imode
= GET_MODE_INNER (mode
);
2462 if (imode
== VOIDmode
)
2465 maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (imode
));
2467 /* Restrict the bits of "t" to the multiplication's mode. */
2468 t
&= GET_MODE_MASK (imode
);
2470 /* t == 1 can be done in zero cost. */
2474 alg_out
->cost
.cost
= 0;
2475 alg_out
->cost
.latency
= 0;
2476 alg_out
->op
[0] = alg_m
;
2480 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2484 if (MULT_COST_LESS (cost_limit
, zero_cost (speed
)))
2489 alg_out
->cost
.cost
= zero_cost (speed
);
2490 alg_out
->cost
.latency
= zero_cost (speed
);
2491 alg_out
->op
[0] = alg_zero
;
2496 /* We'll be needing a couple extra algorithm structures now. */
2498 alg_in
= XALLOCA (struct algorithm
);
2499 best_alg
= XALLOCA (struct algorithm
);
2500 best_cost
= *cost_limit
;
2502 /* Compute the hash index. */
2503 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2505 /* See if we already know what to do for T. */
2506 entry_ptr
= alg_hash_entry_ptr (hash_index
);
2507 if (entry_ptr
->t
== t
2508 && entry_ptr
->mode
== mode
2509 && entry_ptr
->mode
== mode
2510 && entry_ptr
->speed
== speed
2511 && entry_ptr
->alg
!= alg_unknown
)
2513 cache_alg
= entry_ptr
->alg
;
2515 if (cache_alg
== alg_impossible
)
2517 /* The cache tells us that it's impossible to synthesize
2518 multiplication by T within entry_ptr->cost. */
2519 if (!CHEAPER_MULT_COST (&entry_ptr
->cost
, cost_limit
))
2520 /* COST_LIMIT is at least as restrictive as the one
2521 recorded in the hash table, in which case we have no
2522 hope of synthesizing a multiplication. Just
2526 /* If we get here, COST_LIMIT is less restrictive than the
2527 one recorded in the hash table, so we may be able to
2528 synthesize a multiplication. Proceed as if we didn't
2529 have the cache entry. */
2533 if (CHEAPER_MULT_COST (cost_limit
, &entry_ptr
->cost
))
2534 /* The cached algorithm shows that this multiplication
2535 requires more cost than COST_LIMIT. Just return. This
2536 way, we don't clobber this cache entry with
2537 alg_impossible but retain useful information. */
2549 goto do_alg_addsub_t_m2
;
2551 case alg_add_factor
:
2552 case alg_sub_factor
:
2553 goto do_alg_addsub_factor
;
2556 goto do_alg_add_t2_m
;
2559 goto do_alg_sub_t2_m
;
2567 /* If we have a group of zero bits at the low-order part of T, try
2568 multiplying by the remaining bits and then doing a shift. */
2573 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2577 /* The function expand_shift will choose between a shift and
2578 a sequence of additions, so the observed cost is given as
2579 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2580 op_cost
= m
* add_cost (speed
, mode
);
2581 if (shift_cost (speed
, mode
, m
) < op_cost
)
2582 op_cost
= shift_cost (speed
, mode
, m
);
2583 new_limit
.cost
= best_cost
.cost
- op_cost
;
2584 new_limit
.latency
= best_cost
.latency
- op_cost
;
2585 synth_mult (alg_in
, q
, &new_limit
, mode
);
2587 alg_in
->cost
.cost
+= op_cost
;
2588 alg_in
->cost
.latency
+= op_cost
;
2589 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2591 struct algorithm
*x
;
2592 best_cost
= alg_in
->cost
;
2593 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2594 best_alg
->log
[best_alg
->ops
] = m
;
2595 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2598 /* See if treating ORIG_T as a signed number yields a better
2599 sequence. Try this sequence only for a negative ORIG_T
2600 as it would be useless for a non-negative ORIG_T. */
2601 if ((HOST_WIDE_INT
) orig_t
< 0)
2603 /* Shift ORIG_T as follows because a right shift of a
2604 negative-valued signed type is implementation
2606 q
= ~(~orig_t
>> m
);
2607 /* The function expand_shift will choose between a shift
2608 and a sequence of additions, so the observed cost is
2609 given as MIN (m * add_cost(speed, mode),
2610 shift_cost(speed, mode, m)). */
2611 op_cost
= m
* add_cost (speed
, mode
);
2612 if (shift_cost (speed
, mode
, m
) < op_cost
)
2613 op_cost
= shift_cost (speed
, mode
, m
);
2614 new_limit
.cost
= best_cost
.cost
- op_cost
;
2615 new_limit
.latency
= best_cost
.latency
- op_cost
;
2616 synth_mult (alg_in
, q
, &new_limit
, mode
);
2618 alg_in
->cost
.cost
+= op_cost
;
2619 alg_in
->cost
.latency
+= op_cost
;
2620 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2622 struct algorithm
*x
;
2623 best_cost
= alg_in
->cost
;
2624 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2625 best_alg
->log
[best_alg
->ops
] = m
;
2626 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2634 /* If we have an odd number, add or subtract one. */
2637 unsigned HOST_WIDE_INT w
;
2640 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2642 /* If T was -1, then W will be zero after the loop. This is another
2643 case where T ends with ...111. Handling this with (T + 1) and
2644 subtract 1 produces slightly better code and results in algorithm
2645 selection much faster than treating it like the ...0111 case
2649 /* Reject the case where t is 3.
2650 Thus we prefer addition in that case. */
2653 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2655 op_cost
= add_cost (speed
, mode
);
2656 new_limit
.cost
= best_cost
.cost
- op_cost
;
2657 new_limit
.latency
= best_cost
.latency
- op_cost
;
2658 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2660 alg_in
->cost
.cost
+= op_cost
;
2661 alg_in
->cost
.latency
+= op_cost
;
2662 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2664 struct algorithm
*x
;
2665 best_cost
= alg_in
->cost
;
2666 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2667 best_alg
->log
[best_alg
->ops
] = 0;
2668 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2673 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2675 op_cost
= add_cost (speed
, mode
);
2676 new_limit
.cost
= best_cost
.cost
- op_cost
;
2677 new_limit
.latency
= best_cost
.latency
- op_cost
;
2678 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2680 alg_in
->cost
.cost
+= op_cost
;
2681 alg_in
->cost
.latency
+= op_cost
;
2682 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2684 struct algorithm
*x
;
2685 best_cost
= alg_in
->cost
;
2686 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2687 best_alg
->log
[best_alg
->ops
] = 0;
2688 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2692 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2693 quickly with a - a * n for some appropriate constant n. */
2694 m
= exact_log2 (-orig_t
+ 1);
2695 if (m
>= 0 && m
< maxm
)
2697 op_cost
= shiftsub1_cost (speed
, mode
, m
);
2698 new_limit
.cost
= best_cost
.cost
- op_cost
;
2699 new_limit
.latency
= best_cost
.latency
- op_cost
;
2700 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
,
2703 alg_in
->cost
.cost
+= op_cost
;
2704 alg_in
->cost
.latency
+= op_cost
;
2705 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2707 struct algorithm
*x
;
2708 best_cost
= alg_in
->cost
;
2709 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2710 best_alg
->log
[best_alg
->ops
] = m
;
2711 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2719 /* Look for factors of t of the form
2720 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2721 If we find such a factor, we can multiply by t using an algorithm that
2722 multiplies by q, shift the result by m and add/subtract it to itself.
2724 We search for large factors first and loop down, even if large factors
2725 are less probable than small; if we find a large factor we will find a
2726 good sequence quickly, and therefore be able to prune (by decreasing
2727 COST_LIMIT) the search. */
2729 do_alg_addsub_factor
:
2730 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2732 unsigned HOST_WIDE_INT d
;
2734 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2735 if (t
% d
== 0 && t
> d
&& m
< maxm
2736 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2738 /* If the target has a cheap shift-and-add instruction use
2739 that in preference to a shift insn followed by an add insn.
2740 Assume that the shift-and-add is "atomic" with a latency
2741 equal to its cost, otherwise assume that on superscalar
2742 hardware the shift may be executed concurrently with the
2743 earlier steps in the algorithm. */
2744 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2745 if (shiftadd_cost (speed
, mode
, m
) < op_cost
)
2747 op_cost
= shiftadd_cost (speed
, mode
, m
);
2748 op_latency
= op_cost
;
2751 op_latency
= add_cost (speed
, mode
);
2753 new_limit
.cost
= best_cost
.cost
- op_cost
;
2754 new_limit
.latency
= best_cost
.latency
- op_latency
;
2755 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2757 alg_in
->cost
.cost
+= op_cost
;
2758 alg_in
->cost
.latency
+= op_latency
;
2759 if (alg_in
->cost
.latency
< op_cost
)
2760 alg_in
->cost
.latency
= op_cost
;
2761 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2763 struct algorithm
*x
;
2764 best_cost
= alg_in
->cost
;
2765 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2766 best_alg
->log
[best_alg
->ops
] = m
;
2767 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2769 /* Other factors will have been taken care of in the recursion. */
2773 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2774 if (t
% d
== 0 && t
> d
&& m
< maxm
2775 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2777 /* If the target has a cheap shift-and-subtract insn use
2778 that in preference to a shift insn followed by a sub insn.
2779 Assume that the shift-and-sub is "atomic" with a latency
2780 equal to it's cost, otherwise assume that on superscalar
2781 hardware the shift may be executed concurrently with the
2782 earlier steps in the algorithm. */
2783 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2784 if (shiftsub0_cost (speed
, mode
, m
) < op_cost
)
2786 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2787 op_latency
= op_cost
;
2790 op_latency
= add_cost (speed
, mode
);
2792 new_limit
.cost
= best_cost
.cost
- op_cost
;
2793 new_limit
.latency
= best_cost
.latency
- op_latency
;
2794 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2796 alg_in
->cost
.cost
+= op_cost
;
2797 alg_in
->cost
.latency
+= op_latency
;
2798 if (alg_in
->cost
.latency
< op_cost
)
2799 alg_in
->cost
.latency
= op_cost
;
2800 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2802 struct algorithm
*x
;
2803 best_cost
= alg_in
->cost
;
2804 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2805 best_alg
->log
[best_alg
->ops
] = m
;
2806 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2814 /* Try shift-and-add (load effective address) instructions,
2815 i.e. do a*3, a*5, a*9. */
2822 if (m
>= 0 && m
< maxm
)
2824 op_cost
= shiftadd_cost (speed
, mode
, m
);
2825 new_limit
.cost
= best_cost
.cost
- op_cost
;
2826 new_limit
.latency
= best_cost
.latency
- op_cost
;
2827 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2829 alg_in
->cost
.cost
+= op_cost
;
2830 alg_in
->cost
.latency
+= op_cost
;
2831 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2833 struct algorithm
*x
;
2834 best_cost
= alg_in
->cost
;
2835 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2836 best_alg
->log
[best_alg
->ops
] = m
;
2837 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2847 if (m
>= 0 && m
< maxm
)
2849 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2850 new_limit
.cost
= best_cost
.cost
- op_cost
;
2851 new_limit
.latency
= best_cost
.latency
- op_cost
;
2852 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2854 alg_in
->cost
.cost
+= op_cost
;
2855 alg_in
->cost
.latency
+= op_cost
;
2856 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2858 struct algorithm
*x
;
2859 best_cost
= alg_in
->cost
;
2860 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2861 best_alg
->log
[best_alg
->ops
] = m
;
2862 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2870 /* If best_cost has not decreased, we have not found any algorithm. */
2871 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2873 /* We failed to find an algorithm. Record alg_impossible for
2874 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2875 we are asked to find an algorithm for T within the same or
2876 lower COST_LIMIT, we can immediately return to the
2879 entry_ptr
->mode
= mode
;
2880 entry_ptr
->speed
= speed
;
2881 entry_ptr
->alg
= alg_impossible
;
2882 entry_ptr
->cost
= *cost_limit
;
2886 /* Cache the result. */
2890 entry_ptr
->mode
= mode
;
2891 entry_ptr
->speed
= speed
;
2892 entry_ptr
->alg
= best_alg
->op
[best_alg
->ops
];
2893 entry_ptr
->cost
.cost
= best_cost
.cost
;
2894 entry_ptr
->cost
.latency
= best_cost
.latency
;
2897 /* If we are getting a too long sequence for `struct algorithm'
2898 to record, make this search fail. */
2899 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2902 /* Copy the algorithm from temporary space to the space at alg_out.
2903 We avoid using structure assignment because the majority of
2904 best_alg is normally undefined, and this is a critical function. */
2905 alg_out
->ops
= best_alg
->ops
+ 1;
2906 alg_out
->cost
= best_cost
;
2907 memcpy (alg_out
->op
, best_alg
->op
,
2908 alg_out
->ops
* sizeof *alg_out
->op
);
2909 memcpy (alg_out
->log
, best_alg
->log
,
2910 alg_out
->ops
* sizeof *alg_out
->log
);
2913 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2914 Try three variations:
2916 - a shift/add sequence based on VAL itself
2917 - a shift/add sequence based on -VAL, followed by a negation
2918 - a shift/add sequence based on VAL - 1, followed by an addition.
2920 Return true if the cheapest of these cost less than MULT_COST,
2921 describing the algorithm in *ALG and final fixup in *VARIANT. */
2924 choose_mult_variant (machine_mode mode
, HOST_WIDE_INT val
,
2925 struct algorithm
*alg
, enum mult_variant
*variant
,
2928 struct algorithm alg2
;
2929 struct mult_cost limit
;
2931 bool speed
= optimize_insn_for_speed_p ();
2933 /* Fail quickly for impossible bounds. */
2937 /* Ensure that mult_cost provides a reasonable upper bound.
2938 Any constant multiplication can be performed with less
2939 than 2 * bits additions. */
2940 op_cost
= 2 * GET_MODE_UNIT_BITSIZE (mode
) * add_cost (speed
, mode
);
2941 if (mult_cost
> op_cost
)
2942 mult_cost
= op_cost
;
2944 *variant
= basic_variant
;
2945 limit
.cost
= mult_cost
;
2946 limit
.latency
= mult_cost
;
2947 synth_mult (alg
, val
, &limit
, mode
);
2949 /* This works only if the inverted value actually fits in an
2951 if (HOST_BITS_PER_INT
>= GET_MODE_UNIT_BITSIZE (mode
))
2953 op_cost
= neg_cost (speed
, mode
);
2954 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2956 limit
.cost
= alg
->cost
.cost
- op_cost
;
2957 limit
.latency
= alg
->cost
.latency
- op_cost
;
2961 limit
.cost
= mult_cost
- op_cost
;
2962 limit
.latency
= mult_cost
- op_cost
;
2965 synth_mult (&alg2
, -val
, &limit
, mode
);
2966 alg2
.cost
.cost
+= op_cost
;
2967 alg2
.cost
.latency
+= op_cost
;
2968 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2969 *alg
= alg2
, *variant
= negate_variant
;
2972 /* This proves very useful for division-by-constant. */
2973 op_cost
= add_cost (speed
, mode
);
2974 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2976 limit
.cost
= alg
->cost
.cost
- op_cost
;
2977 limit
.latency
= alg
->cost
.latency
- op_cost
;
2981 limit
.cost
= mult_cost
- op_cost
;
2982 limit
.latency
= mult_cost
- op_cost
;
2985 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2986 alg2
.cost
.cost
+= op_cost
;
2987 alg2
.cost
.latency
+= op_cost
;
2988 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2989 *alg
= alg2
, *variant
= add_variant
;
2991 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2994 /* A subroutine of expand_mult, used for constant multiplications.
2995 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2996 convenient. Use the shift/add sequence described by ALG and apply
2997 the final fixup specified by VARIANT. */
3000 expand_mult_const (machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
3001 rtx target
, const struct algorithm
*alg
,
3002 enum mult_variant variant
)
3004 HOST_WIDE_INT val_so_far
;
3010 /* Avoid referencing memory over and over and invalid sharing
3012 op0
= force_reg (mode
, op0
);
3014 /* ACCUM starts out either as OP0 or as a zero, depending on
3015 the first operation. */
3017 if (alg
->op
[0] == alg_zero
)
3019 accum
= copy_to_mode_reg (mode
, CONST0_RTX (mode
));
3022 else if (alg
->op
[0] == alg_m
)
3024 accum
= copy_to_mode_reg (mode
, op0
);
3030 for (opno
= 1; opno
< alg
->ops
; opno
++)
3032 int log
= alg
->log
[opno
];
3033 rtx shift_subtarget
= optimize
? 0 : accum
;
3035 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
3038 rtx accum_target
= optimize
? 0 : accum
;
3041 switch (alg
->op
[opno
])
3044 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3045 /* REG_EQUAL note will be attached to the following insn. */
3046 emit_move_insn (accum
, tem
);
3051 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
3052 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
3053 add_target
? add_target
: accum_target
);
3054 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
3058 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
3059 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
3060 add_target
? add_target
: accum_target
);
3061 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
3065 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
3066 log
, shift_subtarget
, 0);
3067 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
3068 add_target
? add_target
: accum_target
);
3069 val_so_far
= (val_so_far
<< log
) + 1;
3073 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
3074 log
, shift_subtarget
, 0);
3075 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
3076 add_target
? add_target
: accum_target
);
3077 val_so_far
= (val_so_far
<< log
) - 1;
3080 case alg_add_factor
:
3081 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3082 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
3083 add_target
? add_target
: accum_target
);
3084 val_so_far
+= val_so_far
<< log
;
3087 case alg_sub_factor
:
3088 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3089 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
3091 ? add_target
: (optimize
? 0 : tem
)));
3092 val_so_far
= (val_so_far
<< log
) - val_so_far
;
3099 if (SCALAR_INT_MODE_P (mode
))
3101 /* Write a REG_EQUAL note on the last insn so that we can cse
3102 multiplication sequences. Note that if ACCUM is a SUBREG,
3103 we've set the inner register and must properly indicate that. */
3104 tem
= op0
, nmode
= mode
;
3105 accum_inner
= accum
;
3106 if (GET_CODE (accum
) == SUBREG
)
3108 accum_inner
= SUBREG_REG (accum
);
3109 nmode
= GET_MODE (accum_inner
);
3110 tem
= gen_lowpart (nmode
, op0
);
3113 insn
= get_last_insn ();
3114 set_dst_reg_note (insn
, REG_EQUAL
,
3115 gen_rtx_MULT (nmode
, tem
,
3116 gen_int_mode (val_so_far
, nmode
)),
3121 if (variant
== negate_variant
)
3123 val_so_far
= -val_so_far
;
3124 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
3126 else if (variant
== add_variant
)
3128 val_so_far
= val_so_far
+ 1;
3129 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3132 /* Compare only the bits of val and val_so_far that are significant
3133 in the result mode, to avoid sign-/zero-extension confusion. */
3134 nmode
= GET_MODE_INNER (mode
);
3135 if (nmode
== VOIDmode
)
3137 val
&= GET_MODE_MASK (nmode
);
3138 val_so_far
&= GET_MODE_MASK (nmode
);
3139 gcc_assert (val
== val_so_far
);
3144 /* Perform a multiplication and return an rtx for the result.
3145 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3146 TARGET is a suggestion for where to store the result (an rtx).
3148 We check specially for a constant integer as OP1.
3149 If you want this check for OP0 as well, then before calling
3150 you should swap the two operands if OP0 would be constant. */
3153 expand_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3156 enum mult_variant variant
;
3157 struct algorithm algorithm
;
3160 bool speed
= optimize_insn_for_speed_p ();
3161 bool do_trapv
= flag_trapv
&& SCALAR_INT_MODE_P (mode
) && !unsignedp
;
3163 if (CONSTANT_P (op0
))
3170 /* For vectors, there are several simplifications that can be made if
3171 all elements of the vector constant are identical. */
3173 if (GET_CODE (op1
) == CONST_VECTOR
)
3175 int i
, n
= CONST_VECTOR_NUNITS (op1
);
3176 scalar_op1
= CONST_VECTOR_ELT (op1
, 0);
3177 for (i
= 1; i
< n
; ++i
)
3178 if (!rtx_equal_p (scalar_op1
, CONST_VECTOR_ELT (op1
, i
)))
3182 if (INTEGRAL_MODE_P (mode
))
3185 HOST_WIDE_INT coeff
;
3189 if (op1
== CONST0_RTX (mode
))
3191 if (op1
== CONST1_RTX (mode
))
3193 if (op1
== CONSTM1_RTX (mode
))
3194 return expand_unop (mode
, do_trapv
? negv_optab
: neg_optab
,
3200 /* If mode is integer vector mode, check if the backend supports
3201 vector lshift (by scalar or vector) at all. If not, we can't use
3202 synthetized multiply. */
3203 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
3204 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
3205 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
)
3208 /* These are the operations that are potentially turned into
3209 a sequence of shifts and additions. */
3210 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
3212 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3213 less than or equal in size to `unsigned int' this doesn't matter.
3214 If the mode is larger than `unsigned int', then synth_mult works
3215 only if the constant value exactly fits in an `unsigned int' without
3216 any truncation. This means that multiplying by negative values does
3217 not work; results are off by 2^32 on a 32 bit machine. */
3218 if (CONST_INT_P (scalar_op1
))
3220 coeff
= INTVAL (scalar_op1
);
3223 #if TARGET_SUPPORTS_WIDE_INT
3224 else if (CONST_WIDE_INT_P (scalar_op1
))
3226 else if (CONST_DOUBLE_AS_INT_P (scalar_op1
))
3229 int shift
= wi::exact_log2 (std::make_pair (scalar_op1
, mode
));
3230 /* Perfect power of 2 (other than 1, which is handled above). */
3232 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3233 shift
, target
, unsignedp
);
3240 /* We used to test optimize here, on the grounds that it's better to
3241 produce a smaller program when -O is not used. But this causes
3242 such a terrible slowdown sometimes that it seems better to always
3245 /* Special case powers of two. */
3246 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
)
3247 && !(is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
))
3248 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3249 floor_log2 (coeff
), target
, unsignedp
);
3251 fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3253 /* Attempt to handle multiplication of DImode values by negative
3254 coefficients, by performing the multiplication by a positive
3255 multiplier and then inverting the result. */
3256 if (is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
)
3258 /* Its safe to use -coeff even for INT_MIN, as the
3259 result is interpreted as an unsigned coefficient.
3260 Exclude cost of op0 from max_cost to match the cost
3261 calculation of the synth_mult. */
3262 coeff
= -(unsigned HOST_WIDE_INT
) coeff
;
3263 max_cost
= (set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
)
3264 - neg_cost (speed
, mode
));
3268 /* Special case powers of two. */
3269 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3271 rtx temp
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
3272 floor_log2 (coeff
), target
, unsignedp
);
3273 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3276 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3279 rtx temp
= expand_mult_const (mode
, op0
, coeff
, NULL_RTX
,
3280 &algorithm
, variant
);
3281 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3286 /* Exclude cost of op0 from max_cost to match the cost
3287 calculation of the synth_mult. */
3288 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
);
3289 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3290 return expand_mult_const (mode
, op0
, coeff
, target
,
3291 &algorithm
, variant
);
3295 /* Expand x*2.0 as x+x. */
3296 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1
))
3299 REAL_VALUE_FROM_CONST_DOUBLE (d
, scalar_op1
);
3301 if (REAL_VALUES_EQUAL (d
, dconst2
))
3303 op0
= force_reg (GET_MODE (op0
), op0
);
3304 return expand_binop (mode
, add_optab
, op0
, op0
,
3305 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3310 /* This used to use umul_optab if unsigned, but for non-widening multiply
3311 there is no difference between signed and unsigned. */
3312 op0
= expand_binop (mode
, do_trapv
? smulv_optab
: smul_optab
,
3313 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3318 /* Return a cost estimate for multiplying a register by the given
3319 COEFFicient in the given MODE and SPEED. */
3322 mult_by_coeff_cost (HOST_WIDE_INT coeff
, machine_mode mode
, bool speed
)
3325 struct algorithm algorithm
;
3326 enum mult_variant variant
;
3328 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3329 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, fake_reg
), speed
);
3330 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3331 return algorithm
.cost
.cost
;
3336 /* Perform a widening multiplication and return an rtx for the result.
3337 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3338 TARGET is a suggestion for where to store the result (an rtx).
3339 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3340 or smul_widen_optab.
3342 We check specially for a constant integer as OP1, comparing the
3343 cost of a widening multiply against the cost of a sequence of shifts
3347 expand_widening_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3348 int unsignedp
, optab this_optab
)
3350 bool speed
= optimize_insn_for_speed_p ();
3353 if (CONST_INT_P (op1
)
3354 && GET_MODE (op0
) != VOIDmode
3355 && (cop1
= convert_modes (mode
, GET_MODE (op0
), op1
,
3356 this_optab
== umul_widen_optab
))
3357 && CONST_INT_P (cop1
)
3358 && (INTVAL (cop1
) >= 0
3359 || HWI_COMPUTABLE_MODE_P (mode
)))
3361 HOST_WIDE_INT coeff
= INTVAL (cop1
);
3363 enum mult_variant variant
;
3364 struct algorithm algorithm
;
3366 /* Special case powers of two. */
3367 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3369 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3370 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3371 floor_log2 (coeff
), target
, unsignedp
);
3374 /* Exclude cost of op0 from max_cost to match the cost
3375 calculation of the synth_mult. */
3376 max_cost
= mul_widen_cost (speed
, mode
);
3377 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3380 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3381 return expand_mult_const (mode
, op0
, coeff
, target
,
3382 &algorithm
, variant
);
3385 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3386 unsignedp
, OPTAB_LIB_WIDEN
);
3389 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3390 replace division by D, and put the least significant N bits of the result
3391 in *MULTIPLIER_PTR and return the most significant bit.
3393 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3394 needed precision is in PRECISION (should be <= N).
3396 PRECISION should be as small as possible so this function can choose
3397 multiplier more freely.
3399 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3400 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3402 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3403 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3405 unsigned HOST_WIDE_INT
3406 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3407 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3408 int *post_shift_ptr
, int *lgup_ptr
)
3410 int lgup
, post_shift
;
3413 /* lgup = ceil(log2(divisor)); */
3414 lgup
= ceil_log2 (d
);
3416 gcc_assert (lgup
<= n
);
3419 pow2
= n
+ lgup
- precision
;
3421 /* mlow = 2^(N + lgup)/d */
3422 wide_int val
= wi::set_bit_in_zero (pow
, HOST_BITS_PER_DOUBLE_INT
);
3423 wide_int mlow
= wi::udiv_trunc (val
, d
);
3425 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3426 val
|= wi::set_bit_in_zero (pow2
, HOST_BITS_PER_DOUBLE_INT
);
3427 wide_int mhigh
= wi::udiv_trunc (val
, d
);
3429 /* If precision == N, then mlow, mhigh exceed 2^N
3430 (but they do not exceed 2^(N+1)). */
3432 /* Reduce to lowest terms. */
3433 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3435 unsigned HOST_WIDE_INT ml_lo
= wi::extract_uhwi (mlow
, 1,
3436 HOST_BITS_PER_WIDE_INT
);
3437 unsigned HOST_WIDE_INT mh_lo
= wi::extract_uhwi (mhigh
, 1,
3438 HOST_BITS_PER_WIDE_INT
);
3442 mlow
= wi::uhwi (ml_lo
, HOST_BITS_PER_DOUBLE_INT
);
3443 mhigh
= wi::uhwi (mh_lo
, HOST_BITS_PER_DOUBLE_INT
);
3446 *post_shift_ptr
= post_shift
;
3448 if (n
< HOST_BITS_PER_WIDE_INT
)
3450 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3451 *multiplier_ptr
= mhigh
.to_uhwi () & mask
;
3452 return mhigh
.to_uhwi () >= mask
;
3456 *multiplier_ptr
= mhigh
.to_uhwi ();
3457 return wi::extract_uhwi (mhigh
, HOST_BITS_PER_WIDE_INT
, 1);
3461 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3462 congruent to 1 (mod 2**N). */
3464 static unsigned HOST_WIDE_INT
3465 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3467 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3469 /* The algorithm notes that the choice y = x satisfies
3470 x*y == 1 mod 2^3, since x is assumed odd.
3471 Each iteration doubles the number of bits of significance in y. */
3473 unsigned HOST_WIDE_INT mask
;
3474 unsigned HOST_WIDE_INT y
= x
;
3477 mask
= (n
== HOST_BITS_PER_WIDE_INT
3478 ? ~(unsigned HOST_WIDE_INT
) 0
3479 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3483 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3489 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3490 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3491 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3492 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3495 The result is put in TARGET if that is convenient.
3497 MODE is the mode of operation. */
3500 expand_mult_highpart_adjust (machine_mode mode
, rtx adj_operand
, rtx op0
,
3501 rtx op1
, rtx target
, int unsignedp
)
3504 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3506 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3507 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3508 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3510 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3513 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3514 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3515 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3516 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3522 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3525 extract_high_half (machine_mode mode
, rtx op
)
3527 machine_mode wider_mode
;
3529 if (mode
== word_mode
)
3530 return gen_highpart (mode
, op
);
3532 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3534 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3535 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3536 GET_MODE_BITSIZE (mode
), 0, 1);
3537 return convert_modes (mode
, wider_mode
, op
, 0);
3540 /* Like expmed_mult_highpart, but only consider using a multiplication
3541 optab. OP1 is an rtx for the constant operand. */
3544 expmed_mult_highpart_optab (machine_mode mode
, rtx op0
, rtx op1
,
3545 rtx target
, int unsignedp
, int max_cost
)
3547 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3548 machine_mode wider_mode
;
3552 bool speed
= optimize_insn_for_speed_p ();
3554 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3556 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3557 size
= GET_MODE_BITSIZE (mode
);
3559 /* Firstly, try using a multiplication insn that only generates the needed
3560 high part of the product, and in the sign flavor of unsignedp. */
3561 if (mul_highpart_cost (speed
, mode
) < max_cost
)
3563 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3564 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3565 unsignedp
, OPTAB_DIRECT
);
3570 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3571 Need to adjust the result after the multiplication. */
3572 if (size
- 1 < BITS_PER_WORD
3573 && (mul_highpart_cost (speed
, mode
)
3574 + 2 * shift_cost (speed
, mode
, size
-1)
3575 + 4 * add_cost (speed
, mode
) < max_cost
))
3577 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3578 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3579 unsignedp
, OPTAB_DIRECT
);
3581 /* We used the wrong signedness. Adjust the result. */
3582 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3586 /* Try widening multiplication. */
3587 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3588 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3589 && mul_widen_cost (speed
, wider_mode
) < max_cost
)
3591 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3592 unsignedp
, OPTAB_WIDEN
);
3594 return extract_high_half (mode
, tem
);
3597 /* Try widening the mode and perform a non-widening multiplication. */
3598 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3599 && size
- 1 < BITS_PER_WORD
3600 && (mul_cost (speed
, wider_mode
) + shift_cost (speed
, mode
, size
-1)
3606 /* We need to widen the operands, for example to ensure the
3607 constant multiplier is correctly sign or zero extended.
3608 Use a sequence to clean-up any instructions emitted by
3609 the conversions if things don't work out. */
3611 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3612 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3613 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3614 unsignedp
, OPTAB_WIDEN
);
3615 insns
= get_insns ();
3621 return extract_high_half (mode
, tem
);
3625 /* Try widening multiplication of opposite signedness, and adjust. */
3626 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3627 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3628 && size
- 1 < BITS_PER_WORD
3629 && (mul_widen_cost (speed
, wider_mode
)
3630 + 2 * shift_cost (speed
, mode
, size
-1)
3631 + 4 * add_cost (speed
, mode
) < max_cost
))
3633 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3634 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3637 tem
= extract_high_half (mode
, tem
);
3638 /* We used the wrong signedness. Adjust the result. */
3639 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3647 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3648 putting the high half of the result in TARGET if that is convenient,
3649 and return where the result is. If the operation can not be performed,
3652 MODE is the mode of operation and result.
3654 UNSIGNEDP nonzero means unsigned multiply.
3656 MAX_COST is the total allowed cost for the expanded RTL. */
3659 expmed_mult_highpart (machine_mode mode
, rtx op0
, rtx op1
,
3660 rtx target
, int unsignedp
, int max_cost
)
3662 machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3663 unsigned HOST_WIDE_INT cnst1
;
3665 bool sign_adjust
= false;
3666 enum mult_variant variant
;
3667 struct algorithm alg
;
3669 bool speed
= optimize_insn_for_speed_p ();
3671 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3672 /* We can't support modes wider than HOST_BITS_PER_INT. */
3673 gcc_assert (HWI_COMPUTABLE_MODE_P (mode
));
3675 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3677 /* We can't optimize modes wider than BITS_PER_WORD.
3678 ??? We might be able to perform double-word arithmetic if
3679 mode == word_mode, however all the cost calculations in
3680 synth_mult etc. assume single-word operations. */
3681 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3682 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3683 unsignedp
, max_cost
);
3685 extra_cost
= shift_cost (speed
, mode
, GET_MODE_BITSIZE (mode
) - 1);
3687 /* Check whether we try to multiply by a negative constant. */
3688 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3691 extra_cost
+= add_cost (speed
, mode
);
3694 /* See whether shift/add multiplication is cheap enough. */
3695 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3696 max_cost
- extra_cost
))
3698 /* See whether the specialized multiplication optabs are
3699 cheaper than the shift/add version. */
3700 tem
= expmed_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3701 alg
.cost
.cost
+ extra_cost
);
3705 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3706 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3707 tem
= extract_high_half (mode
, tem
);
3709 /* Adjust result for signedness. */
3711 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3715 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3716 unsignedp
, max_cost
);
3720 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3723 expand_smod_pow2 (machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3725 rtx result
, temp
, shift
;
3726 rtx_code_label
*label
;
3728 int prec
= GET_MODE_PRECISION (mode
);
3730 logd
= floor_log2 (d
);
3731 result
= gen_reg_rtx (mode
);
3733 /* Avoid conditional branches when they're expensive. */
3734 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3735 && optimize_insn_for_speed_p ())
3737 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3741 HOST_WIDE_INT masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3742 signmask
= force_reg (mode
, signmask
);
3743 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3745 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3746 which instruction sequence to use. If logical right shifts
3747 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3748 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3750 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3751 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3752 || (set_src_cost (temp
, optimize_insn_for_speed_p ())
3753 > COSTS_N_INSNS (2)))
3755 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3756 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3757 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3758 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3759 temp
= expand_binop (mode
, and_optab
, temp
,
3760 gen_int_mode (masklow
, mode
),
3761 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3762 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3763 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3764 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3765 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3769 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3770 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3771 signmask
= force_reg (mode
, signmask
);
3773 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3774 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3775 temp
= expand_binop (mode
, and_optab
, temp
,
3776 gen_int_mode (masklow
, mode
),
3777 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3778 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3779 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3785 /* Mask contains the mode's signbit and the significant bits of the
3786 modulus. By including the signbit in the operation, many targets
3787 can avoid an explicit compare operation in the following comparison
3789 wide_int mask
= wi::mask (logd
, false, prec
);
3790 mask
= wi::set_bit (mask
, prec
- 1);
3792 temp
= expand_binop (mode
, and_optab
, op0
,
3793 immed_wide_int_const (mask
, mode
),
3794 result
, 1, OPTAB_LIB_WIDEN
);
3796 emit_move_insn (result
, temp
);
3798 label
= gen_label_rtx ();
3799 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3801 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3802 0, OPTAB_LIB_WIDEN
);
3804 mask
= wi::mask (logd
, true, prec
);
3805 temp
= expand_binop (mode
, ior_optab
, temp
,
3806 immed_wide_int_const (mask
, mode
),
3807 result
, 1, OPTAB_LIB_WIDEN
);
3808 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3809 0, OPTAB_LIB_WIDEN
);
3811 emit_move_insn (result
, temp
);
3816 /* Expand signed division of OP0 by a power of two D in mode MODE.
3817 This routine is only called for positive values of D. */
3820 expand_sdiv_pow2 (machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3823 rtx_code_label
*label
;
3826 logd
= floor_log2 (d
);
3829 && BRANCH_COST (optimize_insn_for_speed_p (),
3832 temp
= gen_reg_rtx (mode
);
3833 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3834 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3835 0, OPTAB_LIB_WIDEN
);
3836 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3839 #ifdef HAVE_conditional_move
3840 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3846 temp2
= copy_to_mode_reg (mode
, op0
);
3847 temp
= expand_binop (mode
, add_optab
, temp2
, gen_int_mode (d
- 1, mode
),
3848 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3849 temp
= force_reg (mode
, temp
);
3851 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3852 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3853 mode
, temp
, temp2
, mode
, 0);
3856 rtx_insn
*seq
= get_insns ();
3859 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, logd
, NULL_RTX
, 0);
3865 if (BRANCH_COST (optimize_insn_for_speed_p (),
3868 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3870 temp
= gen_reg_rtx (mode
);
3871 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3872 if (GET_MODE_BITSIZE (mode
) >= BITS_PER_WORD
3873 || shift_cost (optimize_insn_for_speed_p (), mode
, ushift
)
3874 > COSTS_N_INSNS (1))
3875 temp
= expand_binop (mode
, and_optab
, temp
, gen_int_mode (d
- 1, mode
),
3876 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3878 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3879 ushift
, NULL_RTX
, 1);
3880 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3881 0, OPTAB_LIB_WIDEN
);
3882 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3885 label
= gen_label_rtx ();
3886 temp
= copy_to_mode_reg (mode
, op0
);
3887 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3888 expand_inc (temp
, gen_int_mode (d
- 1, mode
));
3890 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3893 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3894 if that is convenient, and returning where the result is.
3895 You may request either the quotient or the remainder as the result;
3896 specify REM_FLAG nonzero to get the remainder.
3898 CODE is the expression code for which kind of division this is;
3899 it controls how rounding is done. MODE is the machine mode to use.
3900 UNSIGNEDP nonzero means do unsigned division. */
3902 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3903 and then correct it by or'ing in missing high bits
3904 if result of ANDI is nonzero.
3905 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3906 This could optimize to a bfexts instruction.
3907 But C doesn't use these operations, so their optimizations are
3909 /* ??? For modulo, we don't actually need the highpart of the first product,
3910 the low part will do nicely. And for small divisors, the second multiply
3911 can also be a low-part only multiply or even be completely left out.
3912 E.g. to calculate the remainder of a division by 3 with a 32 bit
3913 multiply, multiply with 0x55555556 and extract the upper two bits;
3914 the result is exact for inputs up to 0x1fffffff.
3915 The input range can be reduced by using cross-sum rules.
3916 For odd divisors >= 3, the following table gives right shift counts
3917 so that if a number is shifted by an integer multiple of the given
3918 amount, the remainder stays the same:
3919 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3920 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3921 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3922 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3923 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3925 Cross-sum rules for even numbers can be derived by leaving as many bits
3926 to the right alone as the divisor has zeros to the right.
3927 E.g. if x is an unsigned 32 bit number:
3928 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3932 expand_divmod (int rem_flag
, enum tree_code code
, machine_mode mode
,
3933 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3935 machine_mode compute_mode
;
3937 rtx quotient
= 0, remainder
= 0;
3941 optab optab1
, optab2
;
3942 int op1_is_constant
, op1_is_pow2
= 0;
3943 int max_cost
, extra_cost
;
3944 static HOST_WIDE_INT last_div_const
= 0;
3945 bool speed
= optimize_insn_for_speed_p ();
3947 op1_is_constant
= CONST_INT_P (op1
);
3948 if (op1_is_constant
)
3950 unsigned HOST_WIDE_INT ext_op1
= UINTVAL (op1
);
3952 ext_op1
&= GET_MODE_MASK (mode
);
3953 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3954 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3958 This is the structure of expand_divmod:
3960 First comes code to fix up the operands so we can perform the operations
3961 correctly and efficiently.
3963 Second comes a switch statement with code specific for each rounding mode.
3964 For some special operands this code emits all RTL for the desired
3965 operation, for other cases, it generates only a quotient and stores it in
3966 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3967 to indicate that it has not done anything.
3969 Last comes code that finishes the operation. If QUOTIENT is set and
3970 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3971 QUOTIENT is not set, it is computed using trunc rounding.
3973 We try to generate special code for division and remainder when OP1 is a
3974 constant. If |OP1| = 2**n we can use shifts and some other fast
3975 operations. For other values of OP1, we compute a carefully selected
3976 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3979 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3980 half of the product. Different strategies for generating the product are
3981 implemented in expmed_mult_highpart.
3983 If what we actually want is the remainder, we generate that by another
3984 by-constant multiplication and a subtraction. */
3986 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3987 code below will malfunction if we are, so check here and handle
3988 the special case if so. */
3989 if (op1
== const1_rtx
)
3990 return rem_flag
? const0_rtx
: op0
;
3992 /* When dividing by -1, we could get an overflow.
3993 negv_optab can handle overflows. */
3994 if (! unsignedp
&& op1
== constm1_rtx
)
3998 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS (mode
) == MODE_INT
3999 ? negv_optab
: neg_optab
, op0
, target
, 0);
4003 /* Don't use the function value register as a target
4004 since we have to read it as well as write it,
4005 and function-inlining gets confused by this. */
4006 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
4007 /* Don't clobber an operand while doing a multi-step calculation. */
4008 || ((rem_flag
|| op1_is_constant
)
4009 && (reg_mentioned_p (target
, op0
)
4010 || (MEM_P (op0
) && MEM_P (target
))))
4011 || reg_mentioned_p (target
, op1
)
4012 || (MEM_P (op1
) && MEM_P (target
))))
4015 /* Get the mode in which to perform this computation. Normally it will
4016 be MODE, but sometimes we can't do the desired operation in MODE.
4017 If so, pick a wider mode in which we can do the operation. Convert
4018 to that mode at the start to avoid repeated conversions.
4020 First see what operations we need. These depend on the expression
4021 we are evaluating. (We assume that divxx3 insns exist under the
4022 same conditions that modxx3 insns and that these insns don't normally
4023 fail. If these assumptions are not correct, we may generate less
4024 efficient code in some cases.)
4026 Then see if we find a mode in which we can open-code that operation
4027 (either a division, modulus, or shift). Finally, check for the smallest
4028 mode for which we can do the operation with a library call. */
4030 /* We might want to refine this now that we have division-by-constant
4031 optimization. Since expmed_mult_highpart tries so many variants, it is
4032 not straightforward to generalize this. Maybe we should make an array
4033 of possible modes in init_expmed? Save this for GCC 2.7. */
4035 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
4036 ? (unsignedp
? lshr_optab
: ashr_optab
)
4037 : (unsignedp
? udiv_optab
: sdiv_optab
));
4038 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
4040 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
4042 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
4043 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
4044 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
4045 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
4048 if (compute_mode
== VOIDmode
)
4049 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
4050 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
4051 if (optab_libfunc (optab1
, compute_mode
)
4052 || optab_libfunc (optab2
, compute_mode
))
4055 /* If we still couldn't find a mode, use MODE, but expand_binop will
4057 if (compute_mode
== VOIDmode
)
4058 compute_mode
= mode
;
4060 if (target
&& GET_MODE (target
) == compute_mode
)
4063 tquotient
= gen_reg_rtx (compute_mode
);
4065 size
= GET_MODE_BITSIZE (compute_mode
);
4067 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
4068 (mode), and thereby get better code when OP1 is a constant. Do that
4069 later. It will require going over all usages of SIZE below. */
4070 size
= GET_MODE_BITSIZE (mode
);
4073 /* Only deduct something for a REM if the last divide done was
4074 for a different constant. Then set the constant of the last
4076 max_cost
= (unsignedp
4077 ? udiv_cost (speed
, compute_mode
)
4078 : sdiv_cost (speed
, compute_mode
));
4079 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
4080 && INTVAL (op1
) == last_div_const
))
4081 max_cost
-= (mul_cost (speed
, compute_mode
)
4082 + add_cost (speed
, compute_mode
));
4084 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
4086 /* Now convert to the best mode to use. */
4087 if (compute_mode
!= mode
)
4089 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
4090 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
4092 /* convert_modes may have placed op1 into a register, so we
4093 must recompute the following. */
4094 op1_is_constant
= CONST_INT_P (op1
);
4095 op1_is_pow2
= (op1_is_constant
4096 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4098 && EXACT_POWER_OF_2_OR_ZERO_P (-UINTVAL (op1
))))));
4101 /* If one of the operands is a volatile MEM, copy it into a register. */
4103 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
4104 op0
= force_reg (compute_mode
, op0
);
4105 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
4106 op1
= force_reg (compute_mode
, op1
);
4108 /* If we need the remainder or if OP1 is constant, we need to
4109 put OP0 in a register in case it has any queued subexpressions. */
4110 if (rem_flag
|| op1_is_constant
)
4111 op0
= force_reg (compute_mode
, op0
);
4113 last
= get_last_insn ();
4115 /* Promote floor rounding to trunc rounding for unsigned operations. */
4118 if (code
== FLOOR_DIV_EXPR
)
4119 code
= TRUNC_DIV_EXPR
;
4120 if (code
== FLOOR_MOD_EXPR
)
4121 code
= TRUNC_MOD_EXPR
;
4122 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
4123 code
= TRUNC_DIV_EXPR
;
4126 if (op1
!= const0_rtx
)
4129 case TRUNC_MOD_EXPR
:
4130 case TRUNC_DIV_EXPR
:
4131 if (op1_is_constant
)
4135 unsigned HOST_WIDE_INT mh
, ml
;
4136 int pre_shift
, post_shift
;
4138 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
4139 & GET_MODE_MASK (compute_mode
));
4141 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4143 pre_shift
= floor_log2 (d
);
4146 unsigned HOST_WIDE_INT mask
4147 = ((unsigned HOST_WIDE_INT
) 1 << pre_shift
) - 1;
4149 = expand_binop (compute_mode
, and_optab
, op0
,
4150 gen_int_mode (mask
, compute_mode
),
4154 return gen_lowpart (mode
, remainder
);
4156 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4157 pre_shift
, tquotient
, 1);
4159 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4161 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
4163 /* Most significant bit of divisor is set; emit an scc
4165 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4166 compute_mode
, 1, 1);
4170 /* Find a suitable multiplier and right shift count
4171 instead of multiplying with D. */
4173 mh
= choose_multiplier (d
, size
, size
,
4174 &ml
, &post_shift
, &dummy
);
4176 /* If the suggested multiplier is more than SIZE bits,
4177 we can do better for even divisors, using an
4178 initial right shift. */
4179 if (mh
!= 0 && (d
& 1) == 0)
4181 pre_shift
= floor_log2 (d
& -d
);
4182 mh
= choose_multiplier (d
>> pre_shift
, size
,
4184 &ml
, &post_shift
, &dummy
);
4194 if (post_shift
- 1 >= BITS_PER_WORD
)
4198 = (shift_cost (speed
, compute_mode
, post_shift
- 1)
4199 + shift_cost (speed
, compute_mode
, 1)
4200 + 2 * add_cost (speed
, compute_mode
));
4201 t1
= expmed_mult_highpart
4203 gen_int_mode (ml
, compute_mode
),
4204 NULL_RTX
, 1, max_cost
- extra_cost
);
4207 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
4210 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
,
4211 t2
, 1, NULL_RTX
, 1);
4212 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
4215 quotient
= expand_shift
4216 (RSHIFT_EXPR
, compute_mode
, t4
,
4217 post_shift
- 1, tquotient
, 1);
4223 if (pre_shift
>= BITS_PER_WORD
4224 || post_shift
>= BITS_PER_WORD
)
4228 (RSHIFT_EXPR
, compute_mode
, op0
,
4229 pre_shift
, NULL_RTX
, 1);
4231 = (shift_cost (speed
, compute_mode
, pre_shift
)
4232 + shift_cost (speed
, compute_mode
, post_shift
));
4233 t2
= expmed_mult_highpart
4235 gen_int_mode (ml
, compute_mode
),
4236 NULL_RTX
, 1, max_cost
- extra_cost
);
4239 quotient
= expand_shift
4240 (RSHIFT_EXPR
, compute_mode
, t2
,
4241 post_shift
, tquotient
, 1);
4245 else /* Too wide mode to use tricky code */
4248 insn
= get_last_insn ();
4250 set_dst_reg_note (insn
, REG_EQUAL
,
4251 gen_rtx_UDIV (compute_mode
, op0
, op1
),
4254 else /* TRUNC_DIV, signed */
4256 unsigned HOST_WIDE_INT ml
;
4257 int lgup
, post_shift
;
4259 HOST_WIDE_INT d
= INTVAL (op1
);
4260 unsigned HOST_WIDE_INT abs_d
;
4262 /* Since d might be INT_MIN, we have to cast to
4263 unsigned HOST_WIDE_INT before negating to avoid
4264 undefined signed overflow. */
4266 ? (unsigned HOST_WIDE_INT
) d
4267 : - (unsigned HOST_WIDE_INT
) d
);
4269 /* n rem d = n rem -d */
4270 if (rem_flag
&& d
< 0)
4273 op1
= gen_int_mode (abs_d
, compute_mode
);
4279 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4281 else if (HOST_BITS_PER_WIDE_INT
>= size
4282 && abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4284 /* This case is not handled correctly below. */
4285 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4286 compute_mode
, 1, 1);
4290 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4292 ? smod_pow2_cheap (speed
, compute_mode
)
4293 : sdiv_pow2_cheap (speed
, compute_mode
))
4294 /* We assume that cheap metric is true if the
4295 optab has an expander for this mode. */
4296 && ((optab_handler ((rem_flag
? smod_optab
4299 != CODE_FOR_nothing
)
4300 || (optab_handler (sdivmod_optab
,
4302 != CODE_FOR_nothing
)))
4304 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4308 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4310 return gen_lowpart (mode
, remainder
);
4313 if (sdiv_pow2_cheap (speed
, compute_mode
)
4314 && ((optab_handler (sdiv_optab
, compute_mode
)
4315 != CODE_FOR_nothing
)
4316 || (optab_handler (sdivmod_optab
, compute_mode
)
4317 != CODE_FOR_nothing
)))
4318 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4320 gen_int_mode (abs_d
,
4324 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4326 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4327 negate the quotient. */
4330 insn
= get_last_insn ();
4332 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4333 << (HOST_BITS_PER_WIDE_INT
- 1)))
4334 set_dst_reg_note (insn
, REG_EQUAL
,
4335 gen_rtx_DIV (compute_mode
, op0
,
4341 quotient
= expand_unop (compute_mode
, neg_optab
,
4342 quotient
, quotient
, 0);
4345 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4347 choose_multiplier (abs_d
, size
, size
- 1,
4348 &ml
, &post_shift
, &lgup
);
4349 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4353 if (post_shift
>= BITS_PER_WORD
4354 || size
- 1 >= BITS_PER_WORD
)
4357 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4358 + shift_cost (speed
, compute_mode
, size
- 1)
4359 + add_cost (speed
, compute_mode
));
4360 t1
= expmed_mult_highpart
4361 (compute_mode
, op0
, gen_int_mode (ml
, compute_mode
),
4362 NULL_RTX
, 0, max_cost
- extra_cost
);
4366 (RSHIFT_EXPR
, compute_mode
, t1
,
4367 post_shift
, NULL_RTX
, 0);
4369 (RSHIFT_EXPR
, compute_mode
, op0
,
4370 size
- 1, NULL_RTX
, 0);
4373 = force_operand (gen_rtx_MINUS (compute_mode
,
4378 = force_operand (gen_rtx_MINUS (compute_mode
,
4386 if (post_shift
>= BITS_PER_WORD
4387 || size
- 1 >= BITS_PER_WORD
)
4390 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4391 mlr
= gen_int_mode (ml
, compute_mode
);
4392 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4393 + shift_cost (speed
, compute_mode
, size
- 1)
4394 + 2 * add_cost (speed
, compute_mode
));
4395 t1
= expmed_mult_highpart (compute_mode
, op0
, mlr
,
4397 max_cost
- extra_cost
);
4400 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4404 (RSHIFT_EXPR
, compute_mode
, t2
,
4405 post_shift
, NULL_RTX
, 0);
4407 (RSHIFT_EXPR
, compute_mode
, op0
,
4408 size
- 1, NULL_RTX
, 0);
4411 = force_operand (gen_rtx_MINUS (compute_mode
,
4416 = force_operand (gen_rtx_MINUS (compute_mode
,
4421 else /* Too wide mode to use tricky code */
4424 insn
= get_last_insn ();
4426 set_dst_reg_note (insn
, REG_EQUAL
,
4427 gen_rtx_DIV (compute_mode
, op0
, op1
),
4433 delete_insns_since (last
);
4436 case FLOOR_DIV_EXPR
:
4437 case FLOOR_MOD_EXPR
:
4438 /* We will come here only for signed operations. */
4439 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4441 unsigned HOST_WIDE_INT mh
, ml
;
4442 int pre_shift
, lgup
, post_shift
;
4443 HOST_WIDE_INT d
= INTVAL (op1
);
4447 /* We could just as easily deal with negative constants here,
4448 but it does not seem worth the trouble for GCC 2.6. */
4449 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4451 pre_shift
= floor_log2 (d
);
4454 unsigned HOST_WIDE_INT mask
4455 = ((unsigned HOST_WIDE_INT
) 1 << pre_shift
) - 1;
4456 remainder
= expand_binop
4457 (compute_mode
, and_optab
, op0
,
4458 gen_int_mode (mask
, compute_mode
),
4459 remainder
, 0, OPTAB_LIB_WIDEN
);
4461 return gen_lowpart (mode
, remainder
);
4463 quotient
= expand_shift
4464 (RSHIFT_EXPR
, compute_mode
, op0
,
4465 pre_shift
, tquotient
, 0);
4471 mh
= choose_multiplier (d
, size
, size
- 1,
4472 &ml
, &post_shift
, &lgup
);
4475 if (post_shift
< BITS_PER_WORD
4476 && size
- 1 < BITS_PER_WORD
)
4479 (RSHIFT_EXPR
, compute_mode
, op0
,
4480 size
- 1, NULL_RTX
, 0);
4481 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4482 NULL_RTX
, 0, OPTAB_WIDEN
);
4483 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4484 + shift_cost (speed
, compute_mode
, size
- 1)
4485 + 2 * add_cost (speed
, compute_mode
));
4486 t3
= expmed_mult_highpart
4487 (compute_mode
, t2
, gen_int_mode (ml
, compute_mode
),
4488 NULL_RTX
, 1, max_cost
- extra_cost
);
4492 (RSHIFT_EXPR
, compute_mode
, t3
,
4493 post_shift
, NULL_RTX
, 1);
4494 quotient
= expand_binop (compute_mode
, xor_optab
,
4495 t4
, t1
, tquotient
, 0,
4503 rtx nsign
, t1
, t2
, t3
, t4
;
4504 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4505 op0
, constm1_rtx
), NULL_RTX
);
4506 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4508 nsign
= expand_shift
4509 (RSHIFT_EXPR
, compute_mode
, t2
,
4510 size
- 1, NULL_RTX
, 0);
4511 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4513 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4518 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4520 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4529 delete_insns_since (last
);
4531 /* Try using an instruction that produces both the quotient and
4532 remainder, using truncation. We can easily compensate the quotient
4533 or remainder to get floor rounding, once we have the remainder.
4534 Notice that we compute also the final remainder value here,
4535 and return the result right away. */
4536 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4537 target
= gen_reg_rtx (compute_mode
);
4542 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4543 quotient
= gen_reg_rtx (compute_mode
);
4548 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4549 remainder
= gen_reg_rtx (compute_mode
);
4552 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4553 quotient
, remainder
, 0))
4555 /* This could be computed with a branch-less sequence.
4556 Save that for later. */
4558 rtx_code_label
*label
= gen_label_rtx ();
4559 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4560 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4561 NULL_RTX
, 0, OPTAB_WIDEN
);
4562 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4563 expand_dec (quotient
, const1_rtx
);
4564 expand_inc (remainder
, op1
);
4566 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4569 /* No luck with division elimination or divmod. Have to do it
4570 by conditionally adjusting op0 *and* the result. */
4572 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
4576 quotient
= gen_reg_rtx (compute_mode
);
4577 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4578 label1
= gen_label_rtx ();
4579 label2
= gen_label_rtx ();
4580 label3
= gen_label_rtx ();
4581 label4
= gen_label_rtx ();
4582 label5
= gen_label_rtx ();
4583 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4584 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4585 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4586 quotient
, 0, OPTAB_LIB_WIDEN
);
4587 if (tem
!= quotient
)
4588 emit_move_insn (quotient
, tem
);
4589 emit_jump_insn (gen_jump (label5
));
4591 emit_label (label1
);
4592 expand_inc (adjusted_op0
, const1_rtx
);
4593 emit_jump_insn (gen_jump (label4
));
4595 emit_label (label2
);
4596 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4597 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4598 quotient
, 0, OPTAB_LIB_WIDEN
);
4599 if (tem
!= quotient
)
4600 emit_move_insn (quotient
, tem
);
4601 emit_jump_insn (gen_jump (label5
));
4603 emit_label (label3
);
4604 expand_dec (adjusted_op0
, const1_rtx
);
4605 emit_label (label4
);
4606 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4607 quotient
, 0, OPTAB_LIB_WIDEN
);
4608 if (tem
!= quotient
)
4609 emit_move_insn (quotient
, tem
);
4610 expand_dec (quotient
, const1_rtx
);
4611 emit_label (label5
);
4619 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4622 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4623 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4624 floor_log2 (d
), tquotient
, 1);
4625 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4626 gen_int_mode (d
- 1, compute_mode
),
4627 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4628 t3
= gen_reg_rtx (compute_mode
);
4629 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4630 compute_mode
, 1, 1);
4633 rtx_code_label
*lab
;
4634 lab
= gen_label_rtx ();
4635 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4636 expand_inc (t1
, const1_rtx
);
4641 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4647 /* Try using an instruction that produces both the quotient and
4648 remainder, using truncation. We can easily compensate the
4649 quotient or remainder to get ceiling rounding, once we have the
4650 remainder. Notice that we compute also the final remainder
4651 value here, and return the result right away. */
4652 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4653 target
= gen_reg_rtx (compute_mode
);
4657 remainder
= (REG_P (target
)
4658 ? target
: gen_reg_rtx (compute_mode
));
4659 quotient
= gen_reg_rtx (compute_mode
);
4663 quotient
= (REG_P (target
)
4664 ? target
: gen_reg_rtx (compute_mode
));
4665 remainder
= gen_reg_rtx (compute_mode
);
4668 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4671 /* This could be computed with a branch-less sequence.
4672 Save that for later. */
4673 rtx_code_label
*label
= gen_label_rtx ();
4674 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4675 compute_mode
, label
);
4676 expand_inc (quotient
, const1_rtx
);
4677 expand_dec (remainder
, op1
);
4679 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4682 /* No luck with division elimination or divmod. Have to do it
4683 by conditionally adjusting op0 *and* the result. */
4685 rtx_code_label
*label1
, *label2
;
4686 rtx adjusted_op0
, tem
;
4688 quotient
= gen_reg_rtx (compute_mode
);
4689 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4690 label1
= gen_label_rtx ();
4691 label2
= gen_label_rtx ();
4692 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4693 compute_mode
, label1
);
4694 emit_move_insn (quotient
, const0_rtx
);
4695 emit_jump_insn (gen_jump (label2
));
4697 emit_label (label1
);
4698 expand_dec (adjusted_op0
, const1_rtx
);
4699 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4700 quotient
, 1, OPTAB_LIB_WIDEN
);
4701 if (tem
!= quotient
)
4702 emit_move_insn (quotient
, tem
);
4703 expand_inc (quotient
, const1_rtx
);
4704 emit_label (label2
);
4709 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4710 && INTVAL (op1
) >= 0)
4712 /* This is extremely similar to the code for the unsigned case
4713 above. For 2.7 we should merge these variants, but for
4714 2.6.1 I don't want to touch the code for unsigned since that
4715 get used in C. The signed case will only be used by other
4719 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4720 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4721 floor_log2 (d
), tquotient
, 0);
4722 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4723 gen_int_mode (d
- 1, compute_mode
),
4724 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4725 t3
= gen_reg_rtx (compute_mode
);
4726 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4727 compute_mode
, 1, 1);
4730 rtx_code_label
*lab
;
4731 lab
= gen_label_rtx ();
4732 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4733 expand_inc (t1
, const1_rtx
);
4738 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4744 /* Try using an instruction that produces both the quotient and
4745 remainder, using truncation. We can easily compensate the
4746 quotient or remainder to get ceiling rounding, once we have the
4747 remainder. Notice that we compute also the final remainder
4748 value here, and return the result right away. */
4749 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4750 target
= gen_reg_rtx (compute_mode
);
4753 remainder
= (REG_P (target
)
4754 ? target
: gen_reg_rtx (compute_mode
));
4755 quotient
= gen_reg_rtx (compute_mode
);
4759 quotient
= (REG_P (target
)
4760 ? target
: gen_reg_rtx (compute_mode
));
4761 remainder
= gen_reg_rtx (compute_mode
);
4764 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4767 /* This could be computed with a branch-less sequence.
4768 Save that for later. */
4770 rtx_code_label
*label
= gen_label_rtx ();
4771 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4772 compute_mode
, label
);
4773 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4774 NULL_RTX
, 0, OPTAB_WIDEN
);
4775 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4776 expand_inc (quotient
, const1_rtx
);
4777 expand_dec (remainder
, op1
);
4779 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4782 /* No luck with division elimination or divmod. Have to do it
4783 by conditionally adjusting op0 *and* the result. */
4785 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
4789 quotient
= gen_reg_rtx (compute_mode
);
4790 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4791 label1
= gen_label_rtx ();
4792 label2
= gen_label_rtx ();
4793 label3
= gen_label_rtx ();
4794 label4
= gen_label_rtx ();
4795 label5
= gen_label_rtx ();
4796 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4797 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4798 compute_mode
, label1
);
4799 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4800 quotient
, 0, OPTAB_LIB_WIDEN
);
4801 if (tem
!= quotient
)
4802 emit_move_insn (quotient
, tem
);
4803 emit_jump_insn (gen_jump (label5
));
4805 emit_label (label1
);
4806 expand_dec (adjusted_op0
, const1_rtx
);
4807 emit_jump_insn (gen_jump (label4
));
4809 emit_label (label2
);
4810 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4811 compute_mode
, label3
);
4812 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4813 quotient
, 0, OPTAB_LIB_WIDEN
);
4814 if (tem
!= quotient
)
4815 emit_move_insn (quotient
, tem
);
4816 emit_jump_insn (gen_jump (label5
));
4818 emit_label (label3
);
4819 expand_inc (adjusted_op0
, const1_rtx
);
4820 emit_label (label4
);
4821 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4822 quotient
, 0, OPTAB_LIB_WIDEN
);
4823 if (tem
!= quotient
)
4824 emit_move_insn (quotient
, tem
);
4825 expand_inc (quotient
, const1_rtx
);
4826 emit_label (label5
);
4831 case EXACT_DIV_EXPR
:
4832 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4834 HOST_WIDE_INT d
= INTVAL (op1
);
4835 unsigned HOST_WIDE_INT ml
;
4839 pre_shift
= floor_log2 (d
& -d
);
4840 ml
= invert_mod2n (d
>> pre_shift
, size
);
4841 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4842 pre_shift
, NULL_RTX
, unsignedp
);
4843 quotient
= expand_mult (compute_mode
, t1
,
4844 gen_int_mode (ml
, compute_mode
),
4847 insn
= get_last_insn ();
4848 set_dst_reg_note (insn
, REG_EQUAL
,
4849 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4850 compute_mode
, op0
, op1
),
4855 case ROUND_DIV_EXPR
:
4856 case ROUND_MOD_EXPR
:
4860 rtx_code_label
*label
;
4861 label
= gen_label_rtx ();
4862 quotient
= gen_reg_rtx (compute_mode
);
4863 remainder
= gen_reg_rtx (compute_mode
);
4864 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4867 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4868 quotient
, 1, OPTAB_LIB_WIDEN
);
4869 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4870 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4871 remainder
, 1, OPTAB_LIB_WIDEN
);
4873 tem
= plus_constant (compute_mode
, op1
, -1);
4874 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
, 1, NULL_RTX
, 1);
4875 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4876 expand_inc (quotient
, const1_rtx
);
4877 expand_dec (remainder
, op1
);
4882 rtx abs_rem
, abs_op1
, tem
, mask
;
4883 rtx_code_label
*label
;
4884 label
= gen_label_rtx ();
4885 quotient
= gen_reg_rtx (compute_mode
);
4886 remainder
= gen_reg_rtx (compute_mode
);
4887 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4890 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4891 quotient
, 0, OPTAB_LIB_WIDEN
);
4892 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4893 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4894 remainder
, 0, OPTAB_LIB_WIDEN
);
4896 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4897 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4898 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4900 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4901 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4902 NULL_RTX
, 0, OPTAB_WIDEN
);
4903 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4904 size
- 1, NULL_RTX
, 0);
4905 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4906 NULL_RTX
, 0, OPTAB_WIDEN
);
4907 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4908 NULL_RTX
, 0, OPTAB_WIDEN
);
4909 expand_inc (quotient
, tem
);
4910 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4911 NULL_RTX
, 0, OPTAB_WIDEN
);
4912 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4913 NULL_RTX
, 0, OPTAB_WIDEN
);
4914 expand_dec (remainder
, tem
);
4917 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4925 if (target
&& GET_MODE (target
) != compute_mode
)
4930 /* Try to produce the remainder without producing the quotient.
4931 If we seem to have a divmod pattern that does not require widening,
4932 don't try widening here. We should really have a WIDEN argument
4933 to expand_twoval_binop, since what we'd really like to do here is
4934 1) try a mod insn in compute_mode
4935 2) try a divmod insn in compute_mode
4936 3) try a div insn in compute_mode and multiply-subtract to get
4938 4) try the same things with widening allowed. */
4940 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4943 ((optab_handler (optab2
, compute_mode
)
4944 != CODE_FOR_nothing
)
4945 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4948 /* No luck there. Can we do remainder and divide at once
4949 without a library call? */
4950 remainder
= gen_reg_rtx (compute_mode
);
4951 if (! expand_twoval_binop ((unsignedp
4955 NULL_RTX
, remainder
, unsignedp
))
4960 return gen_lowpart (mode
, remainder
);
4963 /* Produce the quotient. Try a quotient insn, but not a library call.
4964 If we have a divmod in this mode, use it in preference to widening
4965 the div (for this test we assume it will not fail). Note that optab2
4966 is set to the one of the two optabs that the call below will use. */
4968 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4969 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4971 ((optab_handler (optab2
, compute_mode
)
4972 != CODE_FOR_nothing
)
4973 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4977 /* No luck there. Try a quotient-and-remainder insn,
4978 keeping the quotient alone. */
4979 quotient
= gen_reg_rtx (compute_mode
);
4980 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4982 quotient
, NULL_RTX
, unsignedp
))
4986 /* Still no luck. If we are not computing the remainder,
4987 use a library call for the quotient. */
4988 quotient
= sign_expand_binop (compute_mode
,
4989 udiv_optab
, sdiv_optab
,
4991 unsignedp
, OPTAB_LIB_WIDEN
);
4998 if (target
&& GET_MODE (target
) != compute_mode
)
5003 /* No divide instruction either. Use library for remainder. */
5004 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
5006 unsignedp
, OPTAB_LIB_WIDEN
);
5007 /* No remainder function. Try a quotient-and-remainder
5008 function, keeping the remainder. */
5011 remainder
= gen_reg_rtx (compute_mode
);
5012 if (!expand_twoval_binop_libfunc
5013 (unsignedp
? udivmod_optab
: sdivmod_optab
,
5015 NULL_RTX
, remainder
,
5016 unsignedp
? UMOD
: MOD
))
5017 remainder
= NULL_RTX
;
5022 /* We divided. Now finish doing X - Y * (X / Y). */
5023 remainder
= expand_mult (compute_mode
, quotient
, op1
,
5024 NULL_RTX
, unsignedp
);
5025 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
5026 remainder
, target
, unsignedp
,
5031 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
5034 /* Return a tree node with data type TYPE, describing the value of X.
5035 Usually this is an VAR_DECL, if there is no obvious better choice.
5036 X may be an expression, however we only support those expressions
5037 generated by loop.c. */
5040 make_tree (tree type
, rtx x
)
5044 switch (GET_CODE (x
))
5047 case CONST_WIDE_INT
:
5048 t
= wide_int_to_tree (type
, std::make_pair (x
, TYPE_MODE (type
)));
5052 STATIC_ASSERT (HOST_BITS_PER_WIDE_INT
* 2 <= MAX_BITSIZE_MODE_ANY_INT
);
5053 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (x
) == VOIDmode
)
5054 t
= wide_int_to_tree (type
,
5055 wide_int::from_array (&CONST_DOUBLE_LOW (x
), 2,
5056 HOST_BITS_PER_WIDE_INT
* 2));
5061 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
5062 t
= build_real (type
, d
);
5069 int units
= CONST_VECTOR_NUNITS (x
);
5070 tree itype
= TREE_TYPE (type
);
5074 /* Build a tree with vector elements. */
5075 elts
= XALLOCAVEC (tree
, units
);
5076 for (i
= units
- 1; i
>= 0; --i
)
5078 rtx elt
= CONST_VECTOR_ELT (x
, i
);
5079 elts
[i
] = make_tree (itype
, elt
);
5082 return build_vector (type
, elts
);
5086 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5087 make_tree (type
, XEXP (x
, 1)));
5090 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5091 make_tree (type
, XEXP (x
, 1)));
5094 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
5097 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5098 make_tree (type
, XEXP (x
, 1)));
5101 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5102 make_tree (type
, XEXP (x
, 1)));
5105 t
= unsigned_type_for (type
);
5106 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5107 make_tree (t
, XEXP (x
, 0)),
5108 make_tree (type
, XEXP (x
, 1))));
5111 t
= signed_type_for (type
);
5112 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5113 make_tree (t
, XEXP (x
, 0)),
5114 make_tree (type
, XEXP (x
, 1))));
5117 if (TREE_CODE (type
) != REAL_TYPE
)
5118 t
= signed_type_for (type
);
5122 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5123 make_tree (t
, XEXP (x
, 0)),
5124 make_tree (t
, XEXP (x
, 1))));
5126 t
= unsigned_type_for (type
);
5127 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5128 make_tree (t
, XEXP (x
, 0)),
5129 make_tree (t
, XEXP (x
, 1))));
5133 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5134 GET_CODE (x
) == ZERO_EXTEND
);
5135 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5138 return make_tree (type
, XEXP (x
, 0));
5141 t
= SYMBOL_REF_DECL (x
);
5143 return fold_convert (type
, build_fold_addr_expr (t
));
5144 /* else fall through. */
5147 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5149 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5150 address mode to pointer mode. */
5151 if (POINTER_TYPE_P (type
))
5152 x
= convert_memory_address_addr_space
5153 (TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5155 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5156 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5157 t
->decl_with_rtl
.rtl
= x
;
5163 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5164 and returning TARGET.
5166 If TARGET is 0, a pseudo-register or constant is returned. */
5169 expand_and (machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5173 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5174 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5176 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5180 else if (tem
!= target
)
5181 emit_move_insn (target
, tem
);
5185 /* Helper function for emit_store_flag. */
5187 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5188 machine_mode mode
, machine_mode compare_mode
,
5189 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5190 machine_mode target_mode
)
5192 struct expand_operand ops
[4];
5193 rtx op0
, comparison
, subtarget
;
5195 machine_mode result_mode
= targetm
.cstore_mode (icode
);
5197 last
= get_last_insn ();
5198 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5199 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5202 delete_insns_since (last
);
5206 if (target_mode
== VOIDmode
)
5207 target_mode
= result_mode
;
5209 target
= gen_reg_rtx (target_mode
);
5211 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5213 create_output_operand (&ops
[0], optimize
? NULL_RTX
: target
, result_mode
);
5214 create_fixed_operand (&ops
[1], comparison
);
5215 create_fixed_operand (&ops
[2], x
);
5216 create_fixed_operand (&ops
[3], y
);
5217 if (!maybe_expand_insn (icode
, 4, ops
))
5219 delete_insns_since (last
);
5222 subtarget
= ops
[0].value
;
5224 /* If we are converting to a wider mode, first convert to
5225 TARGET_MODE, then normalize. This produces better combining
5226 opportunities on machines that have a SIGN_EXTRACT when we are
5227 testing a single bit. This mostly benefits the 68k.
5229 If STORE_FLAG_VALUE does not have the sign bit set when
5230 interpreted in MODE, we can do this conversion as unsigned, which
5231 is usually more efficient. */
5232 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (result_mode
))
5234 convert_move (target
, subtarget
,
5235 val_signbit_known_clear_p (result_mode
,
5238 result_mode
= target_mode
;
5243 /* If we want to keep subexpressions around, don't reuse our last
5248 /* Now normalize to the proper value in MODE. Sometimes we don't
5249 have to do anything. */
5250 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5252 /* STORE_FLAG_VALUE might be the most negative number, so write
5253 the comparison this way to avoid a compiler-time warning. */
5254 else if (- normalizep
== STORE_FLAG_VALUE
)
5255 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5257 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5258 it hard to use a value of just the sign bit due to ANSI integer
5259 constant typing rules. */
5260 else if (val_signbit_known_set_p (result_mode
, STORE_FLAG_VALUE
))
5261 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5262 GET_MODE_BITSIZE (result_mode
) - 1, subtarget
,
5266 gcc_assert (STORE_FLAG_VALUE
& 1);
5268 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5269 if (normalizep
== -1)
5270 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5273 /* If we were converting to a smaller mode, do the conversion now. */
5274 if (target_mode
!= result_mode
)
5276 convert_move (target
, op0
, 0);
5284 /* A subroutine of emit_store_flag only including "tricks" that do not
5285 need a recursive call. These are kept separate to avoid infinite
5289 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5290 machine_mode mode
, int unsignedp
, int normalizep
,
5291 machine_mode target_mode
)
5294 enum insn_code icode
;
5295 machine_mode compare_mode
;
5296 enum mode_class mclass
;
5297 enum rtx_code scode
;
5301 code
= unsigned_condition (code
);
5302 scode
= swap_condition (code
);
5304 /* If one operand is constant, make it the second one. Only do this
5305 if the other operand is not constant as well. */
5307 if (swap_commutative_operands_p (op0
, op1
))
5312 code
= swap_condition (code
);
5315 if (mode
== VOIDmode
)
5316 mode
= GET_MODE (op0
);
5318 /* For some comparisons with 1 and -1, we can convert this to
5319 comparisons with zero. This will often produce more opportunities for
5320 store-flag insns. */
5325 if (op1
== const1_rtx
)
5326 op1
= const0_rtx
, code
= LE
;
5329 if (op1
== constm1_rtx
)
5330 op1
= const0_rtx
, code
= LT
;
5333 if (op1
== const1_rtx
)
5334 op1
= const0_rtx
, code
= GT
;
5337 if (op1
== constm1_rtx
)
5338 op1
= const0_rtx
, code
= GE
;
5341 if (op1
== const1_rtx
)
5342 op1
= const0_rtx
, code
= NE
;
5345 if (op1
== const1_rtx
)
5346 op1
= const0_rtx
, code
= EQ
;
5352 /* If we are comparing a double-word integer with zero or -1, we can
5353 convert the comparison into one involving a single word. */
5354 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5355 && GET_MODE_CLASS (mode
) == MODE_INT
5356 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5358 if ((code
== EQ
|| code
== NE
)
5359 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5363 /* Do a logical OR or AND of the two words and compare the
5365 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5366 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5367 tem
= expand_binop (word_mode
,
5368 op1
== const0_rtx
? ior_optab
: and_optab
,
5369 op00
, op01
, NULL_RTX
, unsignedp
,
5373 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5374 unsignedp
, normalizep
);
5376 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5380 /* If testing the sign bit, can just test on high word. */
5381 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5382 subreg_highpart_offset (word_mode
,
5384 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5385 unsignedp
, normalizep
);
5392 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5395 target
= gen_reg_rtx (target_mode
);
5397 convert_move (target
, tem
,
5398 !val_signbit_known_set_p (word_mode
,
5399 (normalizep
? normalizep
5400 : STORE_FLAG_VALUE
)));
5405 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5406 complement of A (for GE) and shifting the sign bit to the low bit. */
5407 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5408 && GET_MODE_CLASS (mode
) == MODE_INT
5409 && (normalizep
|| STORE_FLAG_VALUE
== 1
5410 || val_signbit_p (mode
, STORE_FLAG_VALUE
)))
5417 /* If the result is to be wider than OP0, it is best to convert it
5418 first. If it is to be narrower, it is *incorrect* to convert it
5420 else if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5422 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5426 if (target_mode
!= mode
)
5430 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5431 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5432 ? 0 : subtarget
), 0);
5434 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5435 /* If we are supposed to produce a 0/1 value, we want to do
5436 a logical shift from the sign bit to the low-order bit; for
5437 a -1/0 value, we do an arithmetic shift. */
5438 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5439 GET_MODE_BITSIZE (mode
) - 1,
5440 subtarget
, normalizep
!= -1);
5442 if (mode
!= target_mode
)
5443 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5448 mclass
= GET_MODE_CLASS (mode
);
5449 for (compare_mode
= mode
; compare_mode
!= VOIDmode
;
5450 compare_mode
= GET_MODE_WIDER_MODE (compare_mode
))
5452 machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5453 icode
= optab_handler (cstore_optab
, optab_mode
);
5454 if (icode
!= CODE_FOR_nothing
)
5456 do_pending_stack_adjust ();
5457 tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5458 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5462 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5464 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5465 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5476 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5477 and storing in TARGET. Normally return TARGET.
5478 Return 0 if that cannot be done.
5480 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5481 it is VOIDmode, they cannot both be CONST_INT.
5483 UNSIGNEDP is for the case where we have to widen the operands
5484 to perform the operation. It says to use zero-extension.
5486 NORMALIZEP is 1 if we should convert the result to be either zero
5487 or one. Normalize is -1 if we should convert the result to be
5488 either zero or -1. If NORMALIZEP is zero, the result will be left
5489 "raw" out of the scc insn. */
5492 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5493 machine_mode mode
, int unsignedp
, int normalizep
)
5495 machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5496 enum rtx_code rcode
;
5501 /* If we compare constants, we shouldn't use a store-flag operation,
5502 but a constant load. We can get there via the vanilla route that
5503 usually generates a compare-branch sequence, but will in this case
5504 fold the comparison to a constant, and thus elide the branch. */
5505 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
5508 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5513 /* If we reached here, we can't do this with a scc insn, however there
5514 are some comparisons that can be done in other ways. Don't do any
5515 of these cases if branches are very cheap. */
5516 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5519 /* See what we need to return. We can only return a 1, -1, or the
5522 if (normalizep
== 0)
5524 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5525 normalizep
= STORE_FLAG_VALUE
;
5527 else if (val_signbit_p (mode
, STORE_FLAG_VALUE
))
5533 last
= get_last_insn ();
5535 /* If optimizing, use different pseudo registers for each insn, instead
5536 of reusing the same pseudo. This leads to better CSE, but slows
5537 down the compiler, since there are more pseudos */
5538 subtarget
= (!optimize
5539 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5540 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5542 /* For floating-point comparisons, try the reverse comparison or try
5543 changing the "orderedness" of the comparison. */
5544 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5546 enum rtx_code first_code
;
5549 rcode
= reverse_condition_maybe_unordered (code
);
5550 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5551 && (code
== ORDERED
|| code
== UNORDERED
5552 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5553 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5555 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5556 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5558 /* For the reverse comparison, use either an addition or a XOR. */
5560 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5561 optimize_insn_for_speed_p ()) == 0)
5563 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5564 STORE_FLAG_VALUE
, target_mode
);
5566 return expand_binop (target_mode
, add_optab
, tem
,
5567 gen_int_mode (normalizep
, target_mode
),
5568 target
, 0, OPTAB_WIDEN
);
5571 && rtx_cost (trueval
, XOR
, 1,
5572 optimize_insn_for_speed_p ()) == 0)
5574 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5575 normalizep
, target_mode
);
5577 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
5578 target
, INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5582 delete_insns_since (last
);
5584 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5585 if (code
== ORDERED
|| code
== UNORDERED
)
5588 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
5590 /* If there are no NaNs, the first comparison should always fall through.
5591 Effectively change the comparison to the other one. */
5592 if (!HONOR_NANS (mode
))
5594 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
5595 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
5599 #ifdef HAVE_conditional_move
5600 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5601 conditional move. */
5602 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
5603 normalizep
, target_mode
);
5608 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5609 tem
, const0_rtx
, GET_MODE (tem
), 0);
5611 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5612 trueval
, tem
, GET_MODE (tem
), 0);
5615 delete_insns_since (last
);
5622 /* The remaining tricks only apply to integer comparisons. */
5624 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5627 /* If this is an equality comparison of integers, we can try to exclusive-or
5628 (or subtract) the two operands and use a recursive call to try the
5629 comparison with zero. Don't do any of these cases if branches are
5632 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5634 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5638 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5641 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5642 mode
, unsignedp
, normalizep
);
5646 delete_insns_since (last
);
5649 /* For integer comparisons, try the reverse comparison. However, for
5650 small X and if we'd have anyway to extend, implementing "X != 0"
5651 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5652 rcode
= reverse_condition (code
);
5653 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5654 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5656 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5657 && op1
== const0_rtx
))
5659 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5660 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5662 /* Again, for the reverse comparison, use either an addition or a XOR. */
5664 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5665 optimize_insn_for_speed_p ()) == 0)
5667 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5668 STORE_FLAG_VALUE
, target_mode
);
5670 tem
= expand_binop (target_mode
, add_optab
, tem
,
5671 gen_int_mode (normalizep
, target_mode
),
5672 target
, 0, OPTAB_WIDEN
);
5675 && rtx_cost (trueval
, XOR
, 1,
5676 optimize_insn_for_speed_p ()) == 0)
5678 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5679 normalizep
, target_mode
);
5681 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5682 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5687 delete_insns_since (last
);
5690 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5691 the constant zero. Reject all other comparisons at this point. Only
5692 do LE and GT if branches are expensive since they are expensive on
5693 2-operand machines. */
5695 if (op1
!= const0_rtx
5696 || (code
!= EQ
&& code
!= NE
5697 && (BRANCH_COST (optimize_insn_for_speed_p (),
5698 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5701 /* Try to put the result of the comparison in the sign bit. Assume we can't
5702 do the necessary operation below. */
5706 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5707 the sign bit set. */
5711 /* This is destructive, so SUBTARGET can't be OP0. */
5712 if (rtx_equal_p (subtarget
, op0
))
5715 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5718 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5722 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5723 number of bits in the mode of OP0, minus one. */
5727 if (rtx_equal_p (subtarget
, op0
))
5730 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5731 GET_MODE_BITSIZE (mode
) - 1,
5733 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5737 if (code
== EQ
|| code
== NE
)
5739 /* For EQ or NE, one way to do the comparison is to apply an operation
5740 that converts the operand into a positive number if it is nonzero
5741 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5742 for NE we negate. This puts the result in the sign bit. Then we
5743 normalize with a shift, if needed.
5745 Two operations that can do the above actions are ABS and FFS, so try
5746 them. If that doesn't work, and MODE is smaller than a full word,
5747 we can use zero-extension to the wider mode (an unsigned conversion)
5748 as the operation. */
5750 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5751 that is compensated by the subsequent overflow when subtracting
5754 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5755 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5756 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5757 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5758 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5760 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5767 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5770 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5773 /* If we couldn't do it that way, for NE we can "or" the two's complement
5774 of the value with itself. For EQ, we take the one's complement of
5775 that "or", which is an extra insn, so we only handle EQ if branches
5780 || BRANCH_COST (optimize_insn_for_speed_p (),
5783 if (rtx_equal_p (subtarget
, op0
))
5786 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5787 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5790 if (tem
&& code
== EQ
)
5791 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5795 if (tem
&& normalizep
)
5796 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5797 GET_MODE_BITSIZE (mode
) - 1,
5798 subtarget
, normalizep
== 1);
5804 else if (GET_MODE (tem
) != target_mode
)
5806 convert_move (target
, tem
, 0);
5809 else if (!subtarget
)
5811 emit_move_insn (target
, tem
);
5816 delete_insns_since (last
);
5821 /* Like emit_store_flag, but always succeeds. */
5824 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5825 machine_mode mode
, int unsignedp
, int normalizep
)
5828 rtx_code_label
*label
;
5829 rtx trueval
, falseval
;
5831 /* First see if emit_store_flag can do the job. */
5832 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5837 target
= gen_reg_rtx (word_mode
);
5839 /* If this failed, we have to do this with set/compare/jump/set code.
5840 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5841 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
5843 && GET_MODE_CLASS (mode
) == MODE_INT
5846 && op1
== const0_rtx
)
5848 label
= gen_label_rtx ();
5849 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
,
5850 mode
, NULL_RTX
, NULL_RTX
, label
, -1);
5851 emit_move_insn (target
, trueval
);
5857 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5858 target
= gen_reg_rtx (GET_MODE (target
));
5860 /* Jump in the right direction if the target cannot implement CODE
5861 but can jump on its reverse condition. */
5862 falseval
= const0_rtx
;
5863 if (! can_compare_p (code
, mode
, ccp_jump
)
5864 && (! FLOAT_MODE_P (mode
)
5865 || code
== ORDERED
|| code
== UNORDERED
5866 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5867 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5869 enum rtx_code rcode
;
5870 if (FLOAT_MODE_P (mode
))
5871 rcode
= reverse_condition_maybe_unordered (code
);
5873 rcode
= reverse_condition (code
);
5875 /* Canonicalize to UNORDERED for the libcall. */
5876 if (can_compare_p (rcode
, mode
, ccp_jump
)
5877 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
5880 trueval
= const0_rtx
;
5885 emit_move_insn (target
, trueval
);
5886 label
= gen_label_rtx ();
5887 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5888 NULL_RTX
, label
, -1);
5890 emit_move_insn (target
, falseval
);
5896 /* Perform possibly multi-word comparison and conditional jump to LABEL
5897 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5898 now a thin wrapper around do_compare_rtx_and_jump. */
5901 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, machine_mode mode
,
5902 rtx_code_label
*label
)
5904 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
5905 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
,
5906 NULL_RTX
, NULL_RTX
, label
, -1);