gcc/ChangeLog

   1 2024-03-04  David Faust  <david.faust@oracle.com>
   2
   3         * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
   4         * config/bpf/bpf.cc (bpf_expand_setmem): New.
   5         * config/bpf/bpf.md (setmemdi): New define_expand.
   6
   7 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
   8
   9         PR rtl-optimization/113010
  10         * combine.cc (simplify_comparison): Guard the
  11         WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
  12         and initialize inner_mode.
  13
  14 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  15
  16         * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
  17         VMLALDAVAXQ_U cases.
  18         (VMLALDAVXQ): Remove iterator.
  19         (VMLALDAVXQ_P): Likewise.
  20         (VMLALDAVAXQ): Likewise.
  21         * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
  22         mode iterator attribute with V4BI mode.
  23         * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
  24         VMLALDAVAXQ_U): Remove unused unspecs.
  25
  26 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  27
  28         * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
  29         * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
  30         attribute.
  31         * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
  32         vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
  33         vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
  34         vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
  35         vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
  36         vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
  37         vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
  38         vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
  39         vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
  40         vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
  41
  42 2024-03-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  43
  44         * config/arm/arm.md (mve_unpredicated_insn): New attribute.
  45         * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
  46         (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
  47         (MVE_VPT_PREDICABLE_INSN_P): Likewise.
  48         * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
  49         * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
  50         (arm_vcx1q<a>v16qi): Likewise.
  51         (arm_vcx1qav16qi): Likewise.
  52         (arm_vcx1qv16qi): Likewise.
  53         (arm_vcx2q<a>_p_v16qi): Likewise.
  54         (arm_vcx2q<a>v16qi): Likewise.
  55         (arm_vcx2qav16qi): Likewise.
  56         (arm_vcx2qv16qi): Likewise.
  57         (arm_vcx3q<a>_p_v16qi): Likewise.
  58         (arm_vcx3q<a>v16qi): Likewise.
  59         (arm_vcx3qav16qi): Likewise.
  60         (arm_vcx3qv16qi): Likewise.
  61         (@mve_<mve_insn>q_<supf><mode>): Likewise.
  62         (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
  63         (@mve_<mve_insn>q_<supf>v4si): Likewise.
  64         (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
  65         (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
  66         (@mve_<mve_insn>q_f<mode>): Likewise.
  67         (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
  68         (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
  69         (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
  70         (@mve_<mve_insn>q_m_f<mode>): Likewise.
  71         (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
  72         (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
  73         (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
  74         (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
  75         (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
  76         (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
  77         (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
  78         (mve_v<absneg_str>q_f<mode>): Likewise.
  79         (mve_<mve_addsubmul>q<mode>): Likewise.
  80         (mve_<mve_addsubmul>q_f<mode>): Likewise.
  81         (mve_vadciq_<supf>v4si): Likewise.
  82         (mve_vadciq_m_<supf>v4si): Likewise.
  83         (mve_vadcq_<supf>v4si): Likewise.
  84         (mve_vadcq_m_<supf>v4si): Likewise.
  85         (mve_vandq_<supf><mode>): Likewise.
  86         (mve_vandq_f<mode>): Likewise.
  87         (mve_vandq_m_<supf><mode>): Likewise.
  88         (mve_vandq_m_f<mode>): Likewise.
  89         (mve_vandq_s<mode>): Likewise.
  90         (mve_vandq_u<mode>): Likewise.
  91         (mve_vbicq_<supf><mode>): Likewise.
  92         (mve_vbicq_f<mode>): Likewise.
  93         (mve_vbicq_m_<supf><mode>): Likewise.
  94         (mve_vbicq_m_f<mode>): Likewise.
  95         (mve_vbicq_m_n_<supf><mode>): Likewise.
  96         (mve_vbicq_n_<supf><mode>): Likewise.
  97         (mve_vbicq_s<mode>): Likewise.
  98         (mve_vbicq_u<mode>): Likewise.
  99         (@mve_vclzq_s<mode>): Likewise.
 100         (mve_vclzq_u<mode>): Likewise.
 101         (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
 102         (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
 103         (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
 104         (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
 105         (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
 106         (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
 107         (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
 108         (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
 109         (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
 110         (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
 111         (mve_vcvtaq_<supf><mode>): Likewise.
 112         (mve_vcvtaq_m_<supf><mode>): Likewise.
 113         (mve_vcvtbq_f16_f32v8hf): Likewise.
 114         (mve_vcvtbq_f32_f16v4sf): Likewise.
 115         (mve_vcvtbq_m_f16_f32v8hf): Likewise.
 116         (mve_vcvtbq_m_f32_f16v4sf): Likewise.
 117         (mve_vcvtmq_<supf><mode>): Likewise.
 118         (mve_vcvtmq_m_<supf><mode>): Likewise.
 119         (mve_vcvtnq_<supf><mode>): Likewise.
 120         (mve_vcvtnq_m_<supf><mode>): Likewise.
 121         (mve_vcvtpq_<supf><mode>): Likewise.
 122         (mve_vcvtpq_m_<supf><mode>): Likewise.
 123         (mve_vcvtq_from_f_<supf><mode>): Likewise.
 124         (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
 125         (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
 126         (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
 127         (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
 128         (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
 129         (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
 130         (mve_vcvtq_to_f_<supf><mode>): Likewise.
 131         (mve_vcvttq_f16_f32v8hf): Likewise.
 132         (mve_vcvttq_f32_f16v4sf): Likewise.
 133         (mve_vcvttq_m_f16_f32v8hf): Likewise.
 134         (mve_vcvttq_m_f32_f16v4sf): Likewise.
 135         (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
 136         (mve_vdwdupq_wb_u<mode>_insn): Likewise.
 137         (mve_veorq_s><mode>): Likewise.
 138         (mve_veorq_u><mode>): Likewise.
 139         (mve_veorq_f<mode>): Likewise.
 140         (mve_vidupq_m_wb_u<mode>_insn): Likewise.
 141         (mve_vidupq_u<mode>_insn): Likewise.
 142         (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
 143         (mve_viwdupq_wb_u<mode>_insn): Likewise.
 144         (mve_vldrbq_<supf><mode>): Likewise.
 145         (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
 146         (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
 147         (mve_vldrbq_z_<supf><mode>): Likewise.
 148         (mve_vldrdq_gather_base_<supf>v2di): Likewise.
 149         (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
 150         (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
 151         (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
 152         (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
 153         (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
 154         (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
 155         (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
 156         (mve_vldrhq_<supf><mode>): Likewise.
 157         (mve_vldrhq_fv8hf): Likewise.
 158         (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
 159         (mve_vldrhq_gather_offset_fv8hf): Likewise.
 160         (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
 161         (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
 162         (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
 163         (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
 164         (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
 165         (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
 166         (mve_vldrhq_z_<supf><mode>): Likewise.
 167         (mve_vldrhq_z_fv8hf): Likewise.
 168         (mve_vldrwq_<supf>v4si): Likewise.
 169         (mve_vldrwq_fv4sf): Likewise.
 170         (mve_vldrwq_gather_base_<supf>v4si): Likewise.
 171         (mve_vldrwq_gather_base_fv4sf): Likewise.
 172         (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
 173         (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
 174         (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
 175         (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
 176         (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
 177         (mve_vldrwq_gather_base_z_fv4sf): Likewise.
 178         (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
 179         (mve_vldrwq_gather_offset_fv4sf): Likewise.
 180         (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
 181         (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
 182         (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
 183         (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
 184         (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
 185         (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
 186         (mve_vldrwq_z_<supf>v4si): Likewise.
 187         (mve_vldrwq_z_fv4sf): Likewise.
 188         (mve_vmvnq_s<mode>): Likewise.
 189         (mve_vmvnq_u<mode>): Likewise.
 190         (mve_vornq_<supf><mode>): Likewise.
 191         (mve_vornq_f<mode>): Likewise.
 192         (mve_vornq_m_<supf><mode>): Likewise.
 193         (mve_vornq_m_f<mode>): Likewise.
 194         (mve_vornq_s<mode>): Likewise.
 195         (mve_vornq_u<mode>): Likewise.
 196         (mve_vorrq_<supf><mode>): Likewise.
 197         (mve_vorrq_f<mode>): Likewise.
 198         (mve_vorrq_m_<supf><mode>): Likewise.
 199         (mve_vorrq_m_f<mode>): Likewise.
 200         (mve_vorrq_m_n_<supf><mode>): Likewise.
 201         (mve_vorrq_n_<supf><mode>): Likewise.
 202         (mve_vorrq_s<mode>): Likewise.
 203         (mve_vorrq_s<mode>): Likewise.
 204         (mve_vsbciq_<supf>v4si): Likewise.
 205         (mve_vsbciq_m_<supf>v4si): Likewise.
 206         (mve_vsbcq_<supf>v4si): Likewise.
 207         (mve_vsbcq_m_<supf>v4si): Likewise.
 208         (mve_vshlcq_<supf><mode>): Likewise.
 209         (mve_vshlcq_m_<supf><mode>): Likewise.
 210         (mve_vshrq_m_n_<supf><mode>): Likewise.
 211         (mve_vshrq_n_<supf><mode>): Likewise.
 212         (mve_vstrbq_<supf><mode>): Likewise.
 213         (mve_vstrbq_p_<supf><mode>): Likewise.
 214         (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
 215         (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
 216         (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
 217         (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
 218         (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
 219         (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
 220         (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
 221         (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
 222         (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
 223         (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
 224         (mve_vstrhq_<supf><mode>): Likewise.
 225         (mve_vstrhq_fv8hf): Likewise.
 226         (mve_vstrhq_p_<supf><mode>): Likewise.
 227         (mve_vstrhq_p_fv8hf): Likewise.
 228         (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
 229         (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
 230         (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
 231         (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
 232         (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
 233         (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
 234         (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
 235         (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
 236         (mve_vstrwq_<supf>v4si): Likewise.
 237         (mve_vstrwq_fv4sf): Likewise.
 238         (mve_vstrwq_p_<supf>v4si): Likewise.
 239         (mve_vstrwq_p_fv4sf): Likewise.
 240         (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
 241         (mve_vstrwq_scatter_base_fv4sf): Likewise.
 242         (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
 243         (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
 244         (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
 245         (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
 246         (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
 247         (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
 248         (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
 249         (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
 250         (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
 251         (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
 252         (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
 253         (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
 254         (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
 255         (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
 256
 257 2024-03-04  Marek Polacek  <polacek@redhat.com>
 258
 259         * doc/extend.texi: Update [[gnu::no_dangling]].
 260
 261 2024-03-04  Andrew Stubbs  <ams@baylibre.com>
 262
 263         * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
 264         * expr.cc (store_constructor): Likewise.
 265         (do_store_flag): Likewise.
 266
 267 2024-03-04  Mark Wielaard  <mark@klomp.org>
 268
 269         * common.opt.urls: Regenerate.
 270         * config/avr/avr.opt.urls: Likewise.
 271         * config/i386/i386.opt.urls: Likewise.
 272         * config/pru/pru.opt.urls: Likewise.
 273         * config/riscv/riscv.opt.urls: Likewise.
 274         * config/rs6000/rs6000.opt.urls: Likewise.
 275
 276 2024-03-04  Richard Biener  <rguenther@suse.de>
 277
 278         PR tree-optimization/114197
 279         * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
 280         there are volatile bitfield accesses.
 281         (pass_if_conversion::execute): Throw away result if the
 282         if-converted and original loops are not nested as expected.
 283
 284 2024-03-04  Richard Biener  <rguenther@suse.de>
 285
 286         PR tree-optimization/114164
 287         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
 288         the code generated for mask argument setup is not supported.
 289
 290 2024-03-04  Richard Biener  <rguenther@suse.de>
 291
 292         PR tree-optimization/114203
 293         * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
 294         adjustment before making the result defined at zero.
 295
 296 2024-03-04  Richard Biener  <rguenther@suse.de>
 297
 298         PR tree-optimization/114192
 299         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
 300         appropriate def for the live out stmt in case of an alternate
 301         exit.
 302
 303 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
 304
 305         PR middle-end/114209
 306         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
 307         unshare_expr when creating a MEM_REF from MEM_REF.
 308         (bitint_large_huge::lower_stmt): Call unshare_expr.
 309
 310 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
 311
 312         PR target/114184
 313         * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
 314         is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
 315         register.
 316
 317 2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>
 318
 319         PR target/114187
 320         * simplify-rtx.cc (simplify_context::simplify_subreg): Call
 321         lowpart_subreg to perform type conversion, to avoid confusion
 322         over the offset to use in the call to simplify_reg_subreg.
 323
 324 2024-03-03  Greg McGary  <gkm@rivosinc.com>
 325
 326         PR rtl-optimization/113010
 327         * combine.cc (simplify_comparison): Simplify a SUBREG on
 328         WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
 329         MEM load.
 330
 331 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 332
 333         * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
 334         Use bool in place of int for boolean logic (if possible).
 335         Move declarations to definitions (if possible).
 336         * config/avr/avr.md: Use C++ comments.  Fix some indentation glitches.
 337         * config/avr/avr-dimode.md: Same.
 338         * config/avr/constraints.md: Same.
 339         * config/avr/predicates.md: Same.
 340
 341 2024-03-03  Uros Bizjak  <ubizjak@gmail.com>
 342
 343         PR target/113720
 344         * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
 345         (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
 346         simplify insn RTX using UMUL_HIGHPART rtx_code.
 347         (*umuldi3_highpart_const): Remove.
 348
 349 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 350
 351         PR target/114100
 352         * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
 353         * config/avr/avr.cc (_reg_unused_after): Make static.  And
 354         add 3rd argument to skip the current insn.
 355         (reg_unused_after): Adjust call of reg_unused_after.
 356         (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
 357         unneeded frame pointer adjustments.
 358
 359 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 360
 361         PR target/92729
 362         * config/avr/avr.md (define_attr "cc"): Remove.
 363         * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
 364         from prototype.
 365         * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
 366         its uses.  Add insn argument.
 367         (avr_out_plus_symbol): Remove pcc argument and its uses.
 368         (avr_out_plus): Remove pcc argument and its uses.
 369         Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
 370         (avr_out_round): Adjust call of avr_out_plus.
 371
 372 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 373
 374         * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
 375         from  r14-9273.
 376
 377 2024-03-03  Oleg Endo  <olegendo@gcc.gnu.org>
 378
 379         PR target/101737
 380         * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
 381         is not an insn, but e.g. a code label.
 382
 383 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
 384
 385         * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
 386         * config/avr/avr.cc: Use them instead of magic numbers when it
 387         means a register number.
 388
 389 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
 390
 391         * config/avr/avr.cc: Adjust some comments.
 392
 393 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
 394
 395         PR target/114100
 396         * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
 397         the low part of the frame pointer with 8-bit stack pointer.
 398
 399 2024-03-01  Patrick Palka  <ppalka@redhat.com>
 400
 401         PR c++/104919
 402         PR c++/106009
 403         * tree-inline.cc (remap_decl): Handle copy_decl returning the
 404         original decl.
 405         (remap_decls): Handle remap_decl returning the original decl.
 406         (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
 407         CONST_DECL.
 408
 409 2024-03-01  Jeff Law  <jlaw@ventanamicro.com>
 410
 411         * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
 412         type attribute.
 413         (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
 414         (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
 415         (movhi_internal, movqi_internal): Likewise.
 416         (movsf_softfloat, movsf_hardfloat): Likewise.
 417         (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
 418         (movdf_softfloat): Likewise.
 419
 420 2024-03-01  Marek Polacek  <polacek@redhat.com>
 421
 422         PR c++/110358
 423         PR c++/109642
 424         * doc/extend.texi: Document gnu::no_dangling.
 425         * doc/invoke.texi: Mention that gnu::no_dangling disables
 426         -Wdangling-reference.
 427
 428 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
 429
 430         * config/avr/avr.opt: Overhaul help screen.
 431
 432 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 433             Tobias Burnus  <tburnus@baylibre.com>
 434
 435         PR c++/110347
 436         * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
 437         lang_hooks.decls.omp_disregard_value_expr for
 438         (first)private in target regions.
 439
 440 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 441
 442         PR middle-end/114136
 443         * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
 444         n_named_args initially before INIT_CUMULATIVE_ARGS to
 445         structure_value_addr_parm rather than 0, after it don't modify
 446         it if strict_argument_naming and clear only if
 447         !pretend_outgoing_varargs_named.
 448
 449 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 450
 451         PR debug/114015
 452         * dwarf2out.cc (should_move_die_to_comdat): Return false for
 453         aggregates without DW_AT_byte_size attribute or with non-constant
 454         DW_AT_byte_size.
 455
 456 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
 457
 458         * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
 459         valid values for level.
 460
 461 2024-03-01  Richard Biener  <rguenther@suse.de>
 462
 463         PR middle-end/114070
 464         * match.pd ((c ? a : b) op d  -->  c ? (a op d) : (b op d)):
 465         Allow the folding if before lowering and the current IL
 466         isn't supported with vcond_mask.
 467
 468 2024-03-01  xuli  <xuli1@eswincomputing.com>
 469
 470         * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
 471         attribute to riscv_attribute_table.
 472         (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
 473         (riscv_fntype_abi): Add riscv_vector_cc attribute check.
 474         * doc/extend.texi: Add riscv_vector_cc attribute description.
 475
 476 2024-03-01  Pan Li  <pan2.li@intel.com>
 477
 478         PR target/112817
 479         * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
 480         RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
 481         * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
 482         (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
 483         * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
 484         comments for option replacement.
 485         * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
 486         riscv_autovec_preference to rvv_vector_bits.
 487         (vls_mode_valid_p): Ditto.
 488         (estimated_poly_value): Ditto.
 489         * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
 490         vector chunks and honor new option mrvv-vector-bits.
 491         (riscv_override_options_internal): Update comments and rename the
 492         vector chunks.
 493         * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
 494         internal option param=riscv-autovec-preference.
 495
 496 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 497
 498         * function.cc (assign_parms): Only call assign_parms_setup_varargs
 499         early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
 500
 501 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 502
 503         PR middle-end/114156
 504         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
 505         rhs1 of a VCE to have no underlying variable if it is a load and
 506         handle that case.
 507
 508 2024-02-29  David Malcolm  <dmalcolm@redhat.com>
 509
 510         PR analyzer/114159
 511         * function.cc (function_name): Make param const.
 512         * function.h (function_name): Likewise.
 513
 514 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
 515
 516         PR target/114100
 517         * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
 518         * config/avr/avr.opt (-mfuse-add=): New target option.
 519         * common/config/avr/avr-common.cc (avr_option_optimization_table)
 520         [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
 521         [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
 522         * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
 523         * config/avr/avr-protos.h (avr_split_tiny_move)
 524         (make_avr_pass_fuse_add): New protos.
 525         * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
 526         avr_split_tiny_move to split indirect memory accesses.
 527         (gen_move_clobbercc): New define_expand helper.
 528         * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
 529         (avr_pass_fuse_add): New class from rtl_opt_pass.
 530         (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
 531         (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
 532         (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
 533         of PLUS addressing for AVR_TINY.
 534         (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
 535         (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
 536         (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
 537
 538 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
 539
 540         PR target/114132
 541         * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
 542         * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
 543         (avr_function_arg): Set it.
 544         (avr_frame_pointer_required_p): Use it instead of .nregs.
 545
 546 2024-02-29  Andrew Pinski  <quic_apinski@quicinc.com>
 547
 548         PR target/108174
 549         * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
 550         static and mark with GTY.
 551
 552 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
 553
 554         * config/loongarch/loongarch.md
 555         (loongarch_<crc>_w_<size>_w_extended): New define_insn.
 556
 557 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
 558
 559         * config/loongarch/loongarch.md (CRC): New define_int_iterator.
 560         (crc): New define_int_attr.
 561         (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
 562         into ...
 563         (loongarch_<crc>_w_<size>_w): ... here.
 564
 565 2024-02-29  Kito Cheng  <kito.cheng@sifive.com>
 566
 567         PR target/114130
 568         * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
 569         extend the expected value if needed.
 570
 571 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 572
 573         * config.gcc (target_gtfiles): Change coreout to btfext-out.
 574         (extra_objs): Change coreout to btfext-out.
 575         * config/bpf/coreout.cc: Rename to btfext-out.cc.
 576         * config/bpf/btfext-out.cc: Add.
 577         * config/bpf/coreout.h: Rename to btfext-out.h.
 578         * config/bpf/btfext-out.h: Add.
 579         * config/bpf/core-builtins.cc: Change include.
 580         * config/bpf/core-builtins.h: Change include.
 581         * config/bpf/t-bpf: Accomodate renamed files.
 582
 583 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 584
 585         PR target/113453
 586         * config/bpf/bpf.cc (bpf_function_prologue): Define target
 587         hook.
 588         * config/bpf/coreout.cc (brf_ext_info_section)
 589         (btf_ext_info): Move from coreout.h
 590         (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
 591         (bpf_core_reloc): Rename to btf_ext_core_reloc.
 592         (btf_ext): Add static variable.
 593         (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
 594         (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
 595         (btf_ext_add_string, btf_funcinfo_type_callback)
 596         (btf_add_func_info_for, btf_validate_funcinfo)
 597         (btf_ext_info_len, output_btfext_func_info): Add function.
 598         (output_btfext_header, bpf_core_reloc_add)
 599         (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
 600         Change to support new structs.
 601         * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
 602         Move and change in coreout.cc.
 603         (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
 604
 605 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 606
 607         * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
 608         enabled by default for BPF.
 609         (bpf_file_end): Call BTF deallocation.
 610         (bpf_asm_init_sections): Correct condition.
 611         * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
 612         deallocation.
 613         (ctf_debuf_finish): Correct condition for calling
 614         ctf_debug_finalize.
 615
 616 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 617
 618         * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
 619         (traverse_btf_func_types): Define function.
 620         * ctfc.h (funcs_traverse_callback): Typedef for function
 621         prototype.
 622         (traverse_btf_func_types): Add prototype.
 623
 624 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 625
 626         * btfout.cc (btf_collect_dataset): Corrects BTF type id.
 627
 628 2024-02-28  Richard Biener  <rguenther@suse.de>
 629
 630         PR tree-optimization/113831
 631         PR tree-optimization/108355
 632         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
 633         PR113831 fix.
 634
 635 2024-02-28  Richard Biener  <rguenther@suse.de>
 636
 637         PR tree-optimization/114121
 638         * tree-ssa-sccvn.h (vn_reference_s::offset,
 639         vn_reference_s::max_size): New fields.
 640         (vn_reference_insert_pieces): Adjust prototype.
 641         * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
 642         * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
 643         size, allow using "don't know" state.
 644         (vn_walk_cb_data::finish): Pass along offset/max_size.
 645         (vn_reference_lookup_or_insert_for_pieces): Take offset and
 646         max_size as argument and use it.
 647         (vn_reference_lookup_3): Properly adjust offset and max_size
 648         according to the adjusted ao_ref.
 649         (vn_reference_lookup_pieces): Initialize offset and max_size.
 650         (vn_reference_lookup): Likewise.
 651         (vn_reference_lookup_call): Likewise.
 652         (vn_reference_insert): Likewise.
 653         (visit_reference_op_call): Likewise.
 654         (vn_reference_insert_pieces): Take offset and max_size
 655         as argument and use it.
 656
 657 2024-02-28  Juergen Christ  <jchrist@linux.ibm.com>
 658
 659         PR tree-optimization/114075
 660         * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
 661         point vectors
 662
 663 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
 664
 665         PR tree-optimization/114041
 666         * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
 667         INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
 668
 669 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
 670
 671         PR tree-optimization/113988
 672         * stor-layout.h (bitwise_mode_for_size): Declare.
 673         * stor-layout.cc (bitwise_mode_for_size): New function.
 674         * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
 675         Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
 676         Use BITS_PER_UNIT instead of 8.
 677
 678 2024-02-27  Uros Bizjak  <ubizjak@gmail.com>
 679
 680         PR target/113871
 681         * config/i386/mmx.md (V248FI): Add V2BF mode.
 682         (V24FI_32): Ditto.
 683
 684 2024-02-27  Eric Botcazou  <ebotcazou@adacore.com>
 685
 686         * tree-ssa-dse.cc (compute_trims): Fix description.  Return early
 687         if either ref->offset is not byte aligned or ref->size is not known
 688         to be equal to ref->max_size.
 689         (maybe_trim_complex_store): Fix description.
 690         (maybe_trim_constructor_store): Likewise.
 691         (maybe_trim_partially_dead_store): Likewise.
 692
 693 2024-02-27  Richard Earnshaw  <rearnsha@arm.com>
 694
 695         * config/arm/mmintrin.h: Warn if this header is included without
 696         defining __ENABLE_DEPRECATED_IWMMXT.
 697
 698 2024-02-27  Richard Biener  <rguenther@suse.de>
 699
 700         PR tree-optimization/114074
 701         * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
 702         * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
 703         Handle poly vs. non-poly multiplication correctly with respect
 704         to undefined behavior on overflow.
 705
 706 2024-02-27  Jakub Jelinek  <jakub@redhat.com>
 707
 708         PR rtl-optimization/114044
 709         * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
 710         DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
 711         * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
 712         expand_PARITY): Declare.
 713         * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
 714         expand_CTZ, expand_FFS, expand_PARITY): New functions.
 715         (expand_POPCOUNT): Use expand_bitquery.
 716
 717 2024-02-27  Richard Biener  <rguenther@suse.de>
 718
 719         PR tree-optimization/114081
 720         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 721         Perform manual dominator update for prologue peeling.
 722         (vect_do_peeling): Properly update dominators after adding the
 723         prologue-around guard.
 724
 725 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
 726
 727         * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
 728         (mstrict-X): Tag as "Optimization".
 729
 730 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
 731
 732         * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
 733         an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
 734
 735 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
 736             H.J. Lu  <hjl.tools@gmail.com>
 737
 738         PR rtl-optimization/113617
 739         * varasm.cc (default_elf_select_rtx_section): For
 740         references to private symbols in comdat sections
 741         use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
 742         or .rodata.<comdat> comdat sections.
 743
 744 2024-02-26  Richard Biener  <rguenther@suse.de>
 745
 746         PR tree-optimization/114099
 747         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 748         Create and fill in a needed virtual LC PHI for the alternate
 749         exits.  Remove code dealing with that missing.
 750
 751 2024-02-26  Richard Biener  <rguenther@suse.de>
 752
 753         PR tree-optimization/114068
 754         * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
 755         New function.
 756         (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
 757         on the main exit if needed.  Remove band-aid for the case
 758         it was missing.
 759
 760 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
 761
 762         PR target/114097
 763         * config/i386/i386-options.cc (ix86_set_func_type): Check
 764         interrupt instead of noreturn attribute.
 765
 766 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
 767
 768         * config/i386/i386.cc (ix86_bitint_type_info): Add support for
 769         !TARGET_64BIT.
 770
 771 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
 772
 773         PR tree-optimization/114090
 774         * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
 775         Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
 776         types.
 777         ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
 778
 779 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
 780
 781         PR middle-end/114084
 782         * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
 783         if all subtrees of var0 come from one of the op0 or op1 operands
 784         and all subtrees of con0 come from the other one.  Don't clear
 785         variables which are never used afterwards.
 786
 787 2024-02-26  Richard Biener  <rguenther@suse.de>
 788
 789         PR middle-end/114070
 790         * genmatch.cc (parser::parse_c_expr): Do not record operand
 791         lists but only mark operators used.
 792         * match.pd ((c ? a : b) op (c ? d : e)  -->  c ? (a op d) : (b op e)):
 793         Properly guard the case of tcc_comparison changing the VEC_COND
 794         value operand type.
 795
 796 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
 797
 798         PR target/114094
 799         * config/i386/i386.cc (x86_function_profiler): Add missing new-line
 800         to printed instruction.
 801
 802 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
 803
 804         PR target/114098
 805         * config/i386/amxtileintrin.h (_tile_loadconfig): Use
 806         __builtin_ia32_ldtilecfg.
 807         (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
 808         * config/i386/i386-builtin.def (BDESC): Add
 809         __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
 810         * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
 811         IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
 812         * config/i386/i386.md (ldtilecfg): New pattern.
 813         (sttilecfg): Likewise.
 814
 815 2024-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 816
 817         PR tree-optimization/113205
 818         * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
 819         the proposed layout if it does not allow a source partition with
 820         layout 2 to keep that layout.
 821
 822 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
 823
 824         * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
 825         * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
 826         * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
 827         * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
 828         (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
 829         * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
 830         macros.
 831         * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
 832         * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
 833         * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
 834         HOST_WIDE_INT_UC macros.
 835         * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
 836         * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
 837         * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
 838         * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
 839         macros.
 840         * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
 841         * config/i386/constraints.md (define_constraint "L"): Use
 842         HOST_WIDE_INT_C macro.
 843         * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
 844         macro.
 845         (movl + movb peephole2): Likewise.
 846         * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
 847         (const_32bit_mask): Likewise.
 848
 849 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
 850
 851         PR middle-end/114073
 852         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
 853         VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
 854         types like vector or complex types.
 855         (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
 856         types.  Fix up VIEW_CONVERT_EXPR handling.  Allow merging
 857         VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
 858
 859 2024-02-23  Robin Dapp  <rdapp@ventanamicro.com>
 860
 861         PR target/114028
 862         * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
 863         Return false if inner mode is already Pmode.
 864         (rvv_builder::is_all_same_sequence): New function.
 865         (expand_vec_init): Emit broadcast if sequence is all same.
 866
 867 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
 868
 869         PR target/113613
 870         * config/aarch64/aarch64-early-ra.cc
 871         (early_ra::m_current_region): New member variable.
 872         (early_ra::m_fpr_recency): Likewise.
 873         (early_ra::start_new_region): Bump m_current_region.
 874         (early_ra::allocate_colors): Prefer less recently used registers
 875         in the event of a tie.  Add a comment to explain why we prefer(ed)
 876         higher-numbered registers.
 877         (early_ra::find_oldest_color): Prefer less recently used registers
 878         here too.
 879         (early_ra::finalize_allocation): Update recency information for
 880         allocated registers.
 881         (early_ra::process_blocks): Initialize m_current_region and
 882         m_fpr_recency.
 883
 884 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
 885
 886         PR target/113295
 887         * config/aarch64/aarch64-early-ra.cc
 888         (early_ra::test_strictness): New enum.
 889         (early_ra::is_chain_candidate): Add a strictness parameter to
 890         control whether only correctness matters, or whether both correctness
 891         and heuristics should be used.  Handle multiple levels of equivalence.
 892         (early_ra::find_related_start): Update call accordingly.
 893         (early_ra::strided_polarity_pref): Likewise.
 894         (early_ra::form_chains): Likewise.
 895         (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
 896         correctness mode rather than trying to inline the test.
 897
 898 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
 899
 900         PR target/113295
 901         * config/aarch64/aarch64-early-ra.cc
 902         (early_ra::find_related_start): Account for definitions by shared
 903         registers when testing for a single register definition.
 904         (early_ra::accumulate_defs): New function.
 905         (early_ra::record_copy): If A shares B's register, fold A's
 906         definition information into B's.  Fold A's use information into B's.
 907
 908 2024-02-23  H.J. Lu  <hjl.tools@gmail.com>
 909
 910         * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
 911         if R_X86_64_CODE_6_GOTTPOFF is supported.
 912         * config.in: Regenerated.
 913         * configure: Likewise.
 914         * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
 915         UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
 916
 917 2024-02-23  Richard Earnshaw  <rearnsha@arm.com>
 918
 919         PR target/108120
 920         * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
 921         Gate with ARM_HAVE_NEON_<MODE>_ARITH.
 922
 923 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
 924
 925         PR rtl-optimization/114054
 926         * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
 927         temp variable instead of target parameter for result.
 928
 929 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
 930
 931         PR tree-optimization/114040
 932         * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
 933         Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
 934         probability from likely to unlikely.  When handling the true true
 935         store, first cast to limb_access_type and then to l's type.
 936
 937 2024-02-23  Richard Biener  <rguenther@suse.de>
 938
 939         PR target/90785
 940         * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
 941
 942 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
 943
 944         PR other/109668
 945         * config/riscv/arch-canonicalize: Move to python3
 946         * config/riscv/multilib-generator: Likewise
 947
 948 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
 949
 950         * doc/invoke.texi: Document -mcpu.
 951
 952 2024-02-23  Lulu Cheng  <chenglulu@loongson.cn>
 953
 954         * configure: Regenerate.
 955         * configure.ac: Add parameter "--fatal-warnings" to assemble
 956         when checking whether the assemble support conditional branch
 957         relaxation.
 958
 959 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
 960
 961         PR c/114007
 962         * doc/extend.texi: (__extension__): Remove comments about scope
 963         tokens vs. two colons.
 964
 965 2024-02-22  Andrew Pinski  <quic_apinski@quicinc.com>
 966
 967         PR tree-optimization/109804
 968         * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
 969         DEMANGLE_COMPONENT_UNNAMED_TYPE.
 970
 971 2024-02-22  Richard Biener  <rguenther@suse.de>
 972
 973         PR tree-optimization/114048
 974         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
 975         can also produce -1 off.
 976
 977 2024-02-22  Richard Biener  <rguenther@suse.de>
 978
 979         PR tree-optimization/114027
 980         * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
 981         condition reduction classification only for single-element
 982         chains.
 983
 984 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
 985
 986         PR ipa/111960
 987         * profile-count.h (profile_count::dump): Remove overload with
 988         char * first argument.
 989         * profile-count.cc (profile_count::dump): Change overload with char *
 990         first argument which uses sprintf into the overfload with FILE *
 991         first argument and use fprintf instead.  Remove overload which wrapped
 992         it.
 993
 994 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
 995
 996         PR tree-optimization/113993
 997         * tree-call-cdce.cc (get_no_error_domain): Handle
 998         BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}.  Handle
 999         BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
1000         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1001         the as the F128 suffixed cases, otherwise as non-suffixed ones.
1002         Handle BUILT_IN_{EXP,POW}10L for
1003         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1004         as (-inf, 4932).
1005
1006 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
1007
1008         PR tree-optimization/114038
1009         * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
1010         loop exit condition if end is divisible by limb_prec.
1011
1012 2024-02-22  YunQiang Su  <syq@gcc.gnu.org>
1013
1014         * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
1015         problem of mabi=, mno-flush-func, mexplicit-relocs;
1016         add missing leading - of mbranch-cost option.
1017         * config/mips/mips.opt.urls: Regenerate.
1018
1019 2024-02-22  Kewen Lin  <linkw@linux.ibm.com>
1020
1021         PR target/109987
1022         * config/rs6000/constraints.md (we): Update internal doc without
1023         referring to option -mpower9-vector.
1024         * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
1025         special handlings.
1026         * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
1027         OTHER_P8_VECTOR_MASKS): Merge to ...
1028         (OTHER_VSX_VECTOR_MASKS): ... here.
1029         * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
1030         some error message handlings and explicit option mask adjustments on
1031         explicit option power{8,9}-vector conflicting with other options.
1032         (rs6000_print_isa_options): Update comments.
1033         (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
1034         related array items and handlings.
1035         * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
1036         special handlings.
1037         * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
1038         WarnRemoved.
1039         * doc/extend.texi: Remove documentation referring to option
1040         -mpower8-vector.
1041         * doc/invoke.texi: Remove documentation for option
1042         -mpower{8,9}-vector and adjust some documentation referring to them.
1043         * doc/md.texi: Update documentation for constraint we.
1044         * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
1045
1046 2024-02-22  Pan Li  <pan2.li@intel.com>
1047
1048         PR target/114017
1049         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
1050         the version to 0.12.
1051
1052 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
1053
1054         * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
1055
1056 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
1057             Robin Dapp  <rdapp.gcc@gmail.com>
1058
1059         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1060         (generic_ooo_vec_load): Ditto
1061         (generic_ooo_vec_store): Ditto
1062         (generic_ooo_vec_loadstore_seg): Ditto
1063         (generic_ooo_vec_alu): Ditto
1064         (generic_ooo_vec_fcmp): Ditto
1065         (generic_ooo_vec_imul): Ditto
1066         (generic_ooo_vec_fadd): Ditto
1067         (generic_ooo_vec_fmul): Ditto
1068         (generic_ooo_crypto): Ditto
1069         (generic_ooo_perm): Ditto
1070         (generic_ooo_vec_reduction): Ditto
1071         (generic_ooo_vec_ordered_reduction): Ditto
1072         (generic_ooo_vec_idiv): Ditto
1073         (generic_ooo_vec_float_divsqrt): Ditto
1074         (generic_ooo_vec_mask): Ditto
1075         (generic_ooo_vec_vesetvl): Ditto
1076         (generic_ooo_vec_setrm): Ditto
1077         (generic_ooo_vec_readlen): Ditto
1078         * config/riscv/riscv.md: Include generic-vector-ooo
1079         * config/riscv/generic-vector-ooo.md: New file. To here
1080
1081 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
1082
1083         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1084         (generic_ooo_branch): Ditto
1085         * config/riscv/generic.md (generic_sfb_alu): Ditto
1086         (generic_fmul_half): Ditto
1087         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1088         * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
1089         (sifive_7_popcount): Ditto
1090         * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
1091         * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
1092         * config/riscv/vector.md: Change rdfrm to fmove
1093         * config/riscv/zc.md: Change pushpop to load/store
1094
1095 2024-02-21  Jonathan Wakely  <jwakely@redhat.com>
1096
1097         * doc/invoke.texi (Warning Options): Fix typos.
1098
1099 2024-02-21  David Faust  <david.faust@oracle.com>
1100
1101         * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
1102         * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
1103         * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
1104
1105 2024-02-21  Martin Jambor  <mjambor@suse.cz>
1106
1107         PR ipa/113476
1108         * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
1109         initializers in the contructor.
1110         (ipa_node_params::~ipa_node_params): Release lattices as a vector.
1111         * ipa-cp.h: New file.
1112         * ipa-cp.cc: Include sreal.h and ipa-cp.h.
1113         (ipcp_value_source): Move to ipa-cp.h.
1114         (ipcp_value_base): Likewise.
1115         (ipcp_value): Likewise.
1116         (ipcp_lattice): Likewise.
1117         (ipcp_agg_lattice): Likewise.
1118         (ipcp_bits_lattice): Likewise.
1119         (ipcp_vr_lattice): Likewise.
1120         (ipcp_param_lattices): Likewise.
1121         (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
1122         (ipa_value_from_jfunc): Adjust a check for empty lattices.
1123         (ipa_context_from_jfunc): Likewise.
1124         (ipa_agg_value_from_jfunc): Likewise.
1125         (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
1126         (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
1127         just in contiguous memory.
1128         (ipcp_store_vr_results): Adjust a check for empty lattices.
1129         * auto-profile.cc: Include sreal.h and ipa-cp.h.
1130         * cgraph.cc: Likewise.
1131         * cgraphclones.cc: Likewise.
1132         * cgraphunit.cc: Likewise.
1133         * config/aarch64/aarch64.cc: Likewise.
1134         * config/i386/i386-builtins.cc: Likewise.
1135         * config/i386/i386-expand.cc: Likewise.
1136         * config/i386/i386-features.cc: Likewise.
1137         * config/i386/i386-options.cc: Likewise.
1138         * config/i386/i386.cc: Likewise.
1139         * config/rs6000/rs6000.cc: Likewise.
1140         * config/s390/s390.cc: Likewise.
1141         * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
1142         files to be included in gtype-desc.cc.
1143         * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
1144         * ipa-devirt.cc: Likewise.
1145         * ipa-fnsummary.cc: Likewise.
1146         * ipa-icf.cc: Likewise.
1147         * ipa-inline-analysis.cc: Likewise.
1148         * ipa-inline-transform.cc: Likewise.
1149         * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
1150         * ipa-modref.cc: Include sreal.h and ipa-cp.h.
1151         * ipa-param-manipulation.cc: Likewise.
1152         * ipa-predicate.cc: Likewise.
1153         * ipa-profile.cc: Likewise.
1154         * ipa-prop.cc: Likewise.
1155         (ipa_node_params_t::duplicate): Assert new lattices remain empty
1156         instead of setting them to NULL.
1157         * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
1158         * ipa-split.cc: Likewise.
1159         * ipa-sra.cc: Likewise.
1160         * ipa-strub.cc: Likewise.
1161         * ipa-utils.cc: Likewise.
1162         * ipa.cc: Likewise.
1163         * toplev.cc: Likewise.
1164         * tree-ssa-ccp.cc: Likewise.
1165         * tree-ssa-sccvn.cc: Likewise.
1166         * tree-vrp.cc: Likewise.
1167
1168 2024-02-21  Tamar Christina  <tamar.christina@arm.com>
1169
1170         * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
1171         Armv8.7-a.
1172
1173 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1174
1175         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1176         Use aarch64_gen_compare_zero_and_branch rather than emitting
1177         a CBZ directly.
1178
1179 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1180
1181         * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
1182         Remove duplicated call.
1183
1184 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1185
1186         * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
1187         Check that each individual piece of state is shared in the same
1188         way, rather than using an aggregate check for PSTATE.ZA.
1189
1190 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1191
1192         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1193         In the code that commits a lazy save, only zero ZA if the function
1194         has ZA state.  Similarly zero ZT0 if the function has ZT0 state.
1195
1196 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1197
1198         * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
1199         directly inserting the associated sequence
1200         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1201         ...here instead.
1202
1203 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1204
1205         PR target/113995
1206         * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
1207         fold the SVE allocation into the initial allocation if the
1208         initial allocation includes a VG save.
1209
1210 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1211
1212         PR target/113220
1213         * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
1214         contain jumps even if called after initial RTL expansion.
1215         * mode-switching.cc: Include cfgbuild.h.
1216         (optimize_mode_switching): Allow the sequence returned by the
1217         emit hook to contain internal jumps.  Record which blocks
1218         contain such jumps and split the blocks at the end.
1219         * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
1220         non-debug insns when scanning the sequence.
1221
1222 2024-02-21  Tobias Burnus  <tburnus@baylibre.com>
1223
1224         * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
1225         * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
1226
1227 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
1228
1229         * doc/invoke.texi (-mmcu): Add information about MCU specs.
1230
1231 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
1232
1233         * doc/invoke.texi (-minrt): Clarify that main
1234         must take no arguments.
1235
1236 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
1237
1238         * config/avr/builtins.def: Use function prototypes of given size
1239         and signedness.
1240         * config/avr/avr.cc (avr_init_builtins): Adjust types required
1241         by builtins.def.
1242         * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
1243
1244 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
1245
1246         * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
1247         instead of @table.
1248
1249 2024-02-20  Will Hawkins  <hawkinsw@obs.cr>
1250
1251         * config/bpf/bpf.opt: Add help information for -mcpu.
1252
1253 2024-02-20  Richard Sandiford  <richard.sandiford@arm.com>
1254
1255         PR target/113805
1256         * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
1257         New pass.
1258         * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
1259         Declare.
1260         * config/aarch64/aarch64.md (is_call): New attribute.
1261         (*and<mode>3nr_compare0): Rename to...
1262         (@aarch64_and<mode>3nr_compare0): ...this.
1263         * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
1264         (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
1265         * config/aarch64/aarch64-speculation.cc: Update file comment to
1266         describe the new late pass.
1267         (aarch64_do_track_speculation): Handle is_call insns like other calls.
1268         (pass_track_speculation): Add an is_late member variable.
1269         (pass_track_speculation::gate): Run the late pass for streaming-
1270         compatible functions and the early pass for other functions.
1271         (make_pass_track_speculation): Update accordingly.
1272         (make_pass_late_track_speculation): New function.
1273         * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
1274         function.
1275         (aarch64_guard_switch_pstate_sm): Use it.
1276
1277 2024-02-19  Iain Sandoe  <iain@sandoe.co.uk>
1278
1279         * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
1280         Register these builtins with a pointer to uint64_t rather than unsigned
1281         DI mode.
1282
1283 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
1284
1285         PR target/113615
1286         * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
1287         Conditionalize on '!TARGET_RDNA2_PLUS'.
1288         * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
1289         (gcn_expand_reduc_scalar):
1290         'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
1291
1292 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
1293
1294         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
1295         '__gfx90a__' target CPU definition.  Add some safeguards for the future.
1296
1297 2024-02-19  Richard Biener  <rguenther@suse.de>
1298
1299         PR rtl-optimization/54052
1300         * rtl-ssa/blocks.cc (function_info::place_phis): Filter
1301         local defs by LR_OUT.
1302
1303 2024-02-19  Jakub Jelinek  <jakub@redhat.com>
1304
1305         PR tree-optimization/113967
1306         * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
1307         in condition that @rpos is multiple of vector element size.
1308
1309 2024-02-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1310
1311         PR target/113696
1312         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
1313         Suppress vsetvl fusion.
1314
1315 2024-02-18  H.J. Lu  <hjl.tools@gmail.com>
1316
1317         PR target/113912
1318         * config/i386/i386.cc (ix86_can_use_push2pop2): New.
1319         (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
1320         (ix86_emit_save_regs): Don't generate push2 if
1321         ix86_can_use_push2pop2 return false.
1322         (ix86_expand_epilogue): Don't generate pop2 if
1323         ix86_can_use_push2pop2 return false.
1324
1325 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
1326
1327         * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
1328         Note on complete device support.
1329
1330 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
1331
1332         * doc/extend.texi (AVR Function Attributes): Fuse description
1333         of "signal" and "interrupt" attribute.  Link pseudo instruction.
1334
1335 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
1336
1337         * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
1338         symbol type conversions.
1339         (__cacop_d): Likewise.
1340         (__cpucfg): Likewise.
1341         (__asrtle_d): Likewise.
1342         (__asrtgt_d): Likewise.
1343         (__lddir_d): Likewise.
1344         (__ldpte_d): Likewise.
1345         (__crc_w_b_w): Likewise.
1346         (__crc_w_h_w): Likewise.
1347         (__crc_w_w_w): Likewise.
1348         (__crc_w_d_w): Likewise.
1349         (__crcc_w_b_w): Likewise.
1350         (__crcc_w_h_w): Likewise.
1351         (__crcc_w_w_w): Likewise.
1352         (__crcc_w_d_w): Likewise.
1353         (__csrrd_w): Likewise.
1354         (__csrwr_w): Likewise.
1355         (__csrxchg_w): Likewise.
1356         (__csrrd_d): Likewise.
1357         (__csrwr_d): Likewise.
1358         (__csrxchg_d): Likewise.
1359         (__iocsrrd_b): Likewise.
1360         (__iocsrrd_h): Likewise.
1361         (__iocsrrd_w): Likewise.
1362         (__iocsrrd_d): Likewise.
1363         (__iocsrwr_b): Likewise.
1364         (__iocsrwr_h): Likewise.
1365         (__iocsrwr_w): Likewise.
1366         (__iocsrwr_d): Likewise.
1367         (__frecipe_s): Likewise.
1368         (__frecipe_d): Likewise.
1369         (__frsqrte_s): Likewise.
1370         (__frsqrte_d): Likewise.
1371
1372 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
1373
1374         * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
1375         function return value type to unsigned short.
1376
1377 2024-02-16  Edwin Lu  <ewlu@rivosinc.com>
1378
1379         * doc/sourcebuild.texi: add scan-assembler-bound
1380
1381 2024-02-16  Jason Merrill  <jason@redhat.com>
1382
1383         * gdbhooks.py: Fix regex syntax.
1384
1385 2024-02-16  Richard Biener  <rguenther@suse.de>
1386
1387         PR tree-optimization/113895
1388         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
1389         consistency checking when there are out-of-bound array
1390         accesses.  Allow -1 off when from an array reference with
1391         constant index.
1392
1393 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
1394
1395         PR target/106543
1396         * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
1397         pattern.
1398
1399 2024-02-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
1400
1401         * doc/sourcebuild.texi (Effective-Target Keywords, Other
1402         attribugs): Document linker_plugin.
1403         (Require Support): Document dg-require-linker-plugin.
1404
1405 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
1406
1407         PR target/109349
1408         * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
1409         * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
1410         (RISCV_MINOR_VERSION_BASE): Ditto.
1411         (RISCV_REVISION_VERSION_BASE): Ditto.
1412         * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
1413         rather than magic number.
1414         * config/riscv/riscv.h (riscv_arch_help): New.
1415         (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
1416         (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
1417         --print-supported-extensions.
1418         * config/riscv/riscv.opt (march=help): New.
1419         (print-supported-extensions): New.
1420         (-print-supported-extensions): New.
1421         * doc/invoke.texi (RISC-V Options): Document -march=help.
1422
1423 2024-02-16  Tejas Belagod  <tejas.belagod@arm.com>
1424
1425         PR target/113780
1426         * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
1427         for indirect calls with 4 or more arguments in pac-enabled functions.
1428
1429 2024-02-15  David Faust  <david.faust@oracle.com>
1430
1431         * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
1432         use ldxb instead of ldxh.
1433
1434 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
1435
1436         PR middle-end/113921
1437         * cfgrtl.h (prepend_insn_to_edge): New declaration.
1438         * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
1439         comment.
1440         (prepend_insn_to_edge): New function.
1441         * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
1442         insert_insn_on_edge.
1443
1444 2024-02-15  Richard Biener  <rguenther@suse.de>
1445
1446         PR tree-optimization/111156
1447         * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
1448         at the pattern stmt if any.
1449
1450 2024-02-15  Georg-Johann Lay  <avr@gjlay.de>
1451
1452         PR target/113927
1453         * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
1454         * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
1455         * config/avr/avr.cc (avr_adiw_reg_p): New function.
1456         (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
1457         Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
1458         * config/avr/avr.md: Same.
1459         (attr "isa") <tiny, no_tiny>: Remove.
1460         <adiw, no_adiw>: Add.
1461         (define_insn, define_insn_and_split): When an alternative has
1462         constraint "w", then set attribute "isa" to "adiw".
1463         * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
1464         Built-in define __AVR_HAVE_ADIW__.
1465         * doc/invoke.texi (AVR Options): Document it.
1466
1467 2024-02-15  Andrew Stubbs  <ams@baylibre.com>
1468
1469         * config/gcn/gcn-valu.md
1470         (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
1471         * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
1472         details are supported on RDNA devices.
1473
1474 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
1475
1476         PR middle-end/113508
1477         * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
1478         usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
1479         smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
1480         Add sentence about what the mode m is.
1481
1482 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
1483
1484         * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
1485         smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
1486         var.
1487
1488 2024-02-15  Richard Biener  <rguenther@suse.de>
1489
1490         * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
1491         stmts.
1492
1493 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
1494
1495         PR tree-optimization/113567
1496         * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
1497         _BitInt multiplication, division or modulo with
1498         SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
1499         force the affected inputs into a new SSA_NAME.
1500
1501 2024-02-14  Uros Bizjak  <ubizjak@gmail.com>
1502
1503         PR target/113871
1504         * config/i386/mmx.md (V248FI): New mode iterator.
1505         (V24FI_32): DItto.
1506         (vec_shl_<V248FI:mode>): New expander.
1507         (vec_shl_<V24FI_32:mode>): Ditto.
1508         (vec_shr_<V248FI:mode>): Ditto.
1509         (vec_shr_<V24FI_32:mode>): Ditto.
1510         * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
1511         (vec_shr_<V248FI:mode>): Ditto.
1512
1513 2024-02-14  Jan Hubicka  <jh@suse.cz>
1514
1515         PR tree-optimization/111054
1516         * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
1517
1518 2024-02-14  Tamar Christina  <tamar.christina@arm.com>
1519
1520         * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
1521
1522 2024-02-14  Richard Biener  <rguenther@suse.de>
1523
1524         PR tree-optimization/113910
1525         * bitmap.cc (bitmap_hash): Mix the full element "hash" to
1526         the hashval_t hash.
1527
1528 2024-02-14  Jakub Jelinek  <jakub@redhat.com>
1529
1530         * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
1531         (pp_integer_with_precision): For unsigned ptrdiff_t printing
1532         with u, o or x print ptrdiff_t argument converted to
1533         unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
1534
1535 2024-02-14  Richard Biener  <rguenther@suse.de>
1536
1537         PR middle-end/113576
1538         * expr.cc (do_store_flag): For vector bool compares of vectors
1539         with padding zero that.
1540         * dojump.cc (do_compare_and_jump): Likewise.
1541
1542 2024-02-14  Gerald Pfeifer  <gerald@pfeifer.com>
1543
1544         * doc/install.texi (Prerequisites): Update gettext link.
1545
1546 2024-02-13  H.J. Lu  <hjl.tools@gmail.com>
1547
1548         PR target/113876
1549         * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
1550         Return false if the incoming stack isn't 16-byte aligned.
1551
1552 2024-02-13  Tobias Burnus  <tburnus@baylibre.com>
1553
1554         PR middle-end/113904
1555         * omp-general.cc (struct omp_ts_info): Update for splitting of
1556         OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1557         * omp-selectors.h (enum omp_tp_type): Replace
1558         OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1559
1560 2024-02-13  Monk Chiang  <monk.chiang@sifive.com>
1561
1562         PR target/113742
1563         * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
1564         recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
1565
1566 2024-02-13  Richard Biener  <rguenther@suse.de>
1567
1568         PR tree-optimization/113895
1569         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1570         offset to discover constant array indices in bits, handle
1571         COMPONENT_REF to bitfields.
1572
1573 2024-02-13  Richard Biener  <rguenther@suse.de>
1574
1575         PR tree-optimization/113831
1576         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1577         typo in comment.
1578
1579 2024-02-13  Richard Biener  <rguenther@suse.de>
1580
1581         PR tree-optimization/113902
1582         * tree-vect-loop.cc (move_early_exit_stmts): Track
1583         last_seen_vuse for VUSE updating.
1584
1585 2024-02-13  Tamar Christina  <tamar.christina@arm.com>
1586
1587         PR tree-optimization/113734
1588         * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1589         an early break loop as partial.
1590
1591 2024-02-13  Richard Biener  <rguenther@suse.de>
1592
1593         PR tree-optimization/113898
1594         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1595         missing accumulated off adjustment.
1596
1597 2024-02-13  Jakub Jelinek  <jakub@redhat.com>
1598
1599         * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1600         instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1601         it against UINT_MAX and ULONG_MAX.
1602
1603 2024-02-13  David Malcolm  <dmalcolm@redhat.com>
1604
1605         * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1606         to...
1607         (emit_diagnostic_valist_meta): ...this.
1608         * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
1609         (emit_diagnostic_valist_meta): ...this.
1610
1611 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
1612
1613         PR tree-optimization/113849
1614         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
1615         fast path for widening casts where !m_upwards_2limb and lhs_type
1616         has precision which is a multiple of limb_prec.
1617
1618 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
1619
1620         PR c++/113674
1621         * attribs.cc (extract_attribute_substring): Remove.
1622         (lookup_scoped_attribute_spec): Don't call it.
1623
1624 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
1625
1626         * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
1627         and cast to fmt_size_t instead of %lu and cast to unsigned long.
1628
1629 2024-02-12  Christophe Lyon  <christophe.lyon@linaro.org>
1630
1631         * Makefile.in: Add no-info dependency.
1632         * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
1633         available.
1634         * configure: Regenerate.
1635
1636 2024-02-12  Iain Sandoe  <iain@sandoe.co.uk>
1637
1638         PR target/113855
1639         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
1640         available to all sub-targets.
1641         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1642         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1643
1644 2024-02-12  Richard Biener  <rguenther@suse.de>
1645
1646         PR tree-optimization/113831
1647         PR tree-optimization/108355
1648         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
1649         we see variable array indices and get_ref_base_and_extent
1650         can resolve those to constants fix up the ops to constants
1651         as well.
1652         (ao_ref_init_from_vn_reference): Use 'off' member for
1653         ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
1654         (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
1655
1656 2024-02-12  Pan Li  <pan2.li@intel.com>
1657
1658         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
1659         Replace args to arguments for misspelled term.
1660
1661 2024-02-12  Georg-Johann Lay  <avr@gjlay.de>
1662
1663         PR target/112944
1664         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
1665         <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
1666         when not linked with -mrodata-in-ram.
1667
1668 2024-02-12  Richard Biener  <rguenther@suse.de>
1669
1670         PR tree-optimization/113863
1671         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1672         Record crossed virtual PHIs.
1673         * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
1674         virtual PHIs.
1675
1676 2024-02-10  Marek Polacek  <polacek@redhat.com>
1677
1678         DR 2237
1679         PR c++/107126
1680         PR c++/97202
1681         * doc/invoke.texi: Document -Wtemplate-id-cdtor.
1682
1683 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
1684
1685         * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
1686         computation of idx for i == 4 of bitint_prec_huge.
1687
1688 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
1689
1690         PR middle-end/110754
1691         * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
1692         decls create PARM_DECL with pointer to original type, set
1693         TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
1694         DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
1695         (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
1696         wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
1697         (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
1698         of the var as argument.
1699
1700 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
1701
1702         * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
1703         size_t and precision 4 for ptrdiff_t.  Formatting fix.
1704         (pp_format): Document %{t,z}{d,i,u,o,x}.  Implement t and z modifiers.
1705         Formatting fixes.
1706         (test_pp_format): Test t and z modifiers.
1707         * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
1708
1709 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
1710
1711         * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
1712         sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
1713         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1714         * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
1715         and casts to fmt_size_t instead of "%ld" and casts to long.
1716         (print_value_expr_statistics, print_type_hash_statistics): Likewise.
1717         * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
1718         instead of "%lu" and casts to unsigned long.
1719         * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
1720         unsigned long.
1721         * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1722         and casts to fmt_size_t instead of "%ld" and casts to long.
1723         * cfgexpand.cc (dump_stack_var_partition): Use
1724         HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
1725         and casts to unsigned long.
1726         * gengtype.cc (adjust_field_rtx_def): Likewise.
1727         * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1728         and casts to fmt_size_t instead of "%ld" and casts to long.
1729         * postreload-gcse.cc (dump_hash_table): Likewise.
1730         * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
1731         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1732         (ggc_internal_alloc, ggc_free): Likewise.
1733         * genpreds.cc (write_lookup_constraint_1): Likewise.
1734         (write_insn_constraint_len): Likewise.
1735         * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
1736         and casts to fmt_size_t instead of "%ld" and casts to long.
1737         * varasm.cc (output_constant_pool_contents): Use
1738         HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
1739         * var-tracking.cc (dump_var): Likewise.
1740
1741 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
1742
1743         PR tree-optimization/113783
1744         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
1745         through VIEW_CONVERT_EXPR for final cast checks.  Handle
1746         VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
1747         INTEGER_TYPEs.
1748         (gimple_lower_bitint): Don't merge mergeable operations or other
1749         casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
1750         * expr.cc (expand_expr_real_1): Don't use convert_modes if either
1751         mode is BLKmode.
1752
1753 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
1754
1755         * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
1756         HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
1757         HOST_SIZE_T_PRINT_HEX_PURE): Define.
1758         * ira-conflicts.cc (build_conflict_bit_table): Use it.  Formatting
1759         fixes.
1760
1761 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
1762
1763         PR middle-end/113415
1764         * cfgexpand.cc (expand_asm_stmt): For asm goto, use
1765         duplicate_insn_chain to duplicate after_rtl_seq sequence instead
1766         of hand written loop with emit_insn of copy_insn and emit original
1767         after_rtl_seq on the last edge.
1768
1769 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
1770
1771         PR tree-optimization/113818
1772         * gimple-lower-bitint.cc (add_eh_edge): New function.
1773         (bitint_large_huge::handle_load,
1774         bitint_large_huge::lower_mergeable_stmt,
1775         bitint_large_huge::lower_muldiv_stmt): Use it.
1776
1777 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
1778
1779         PR tree-optimization/113774
1780         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
1781         emit any comparison if m_first and low + 1 is equal to
1782         m_upwards_2limb, simplify condition for that.  If not
1783         single_comparison, not m_first and we can prove that the idx <= low
1784         comparison will be always true, emit instead of idx <= low
1785         comparison low <= low such that cfg cleanup will optimize it at
1786         the end of the pass.
1787
1788 2024-02-08  Aldy Hernandez  <aldyh@redhat.com>
1789
1790         PR tree-optimization/113735
1791         * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
1792         limit_check().
1793
1794 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
1795
1796         * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
1797         (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
1798
1799 2024-02-08  H.J. Lu  <hjl.tools@gmail.com>
1800
1801         PR target/113711
1802         PR target/113733
1803         * config/i386/constraints.md: List all constraints with j prefix.
1804         (j>): Change auto-dec to auto-inc in documentation.
1805         (je): Changed to a memory constraint with APX NDD TLS operand
1806         check.
1807         (jM): New memory constraint for APX NDD instructions.
1808         (jO): Likewise.
1809         * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
1810         * config/i386/i386.cc (x86_poff_operand_p): Likewise.
1811         * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
1812         (*add<mode>_1[SWI48]): Use je and jM.
1813         (addsi_1_zext): Use jM.
1814         (*addv<dwi>4_doubleword_1[DWI]): Likewise.
1815         (*sub<mode>_1[SWI]): Use jM.
1816         (@add<mode>3_cc_overflow_1[SWI]): Likewise.
1817         (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
1818         (*and<dwi>3_doubleword): Likewise.
1819         (*anddi_1): Use jM.
1820         (*andsi_1_zext): Likewise.
1821         (*and<mode>_1[SWI24]): Likewise.
1822         (*<code><dwi>3_doubleword[any_or]): Use rjO
1823         (*code<mode>_1[any_or SWI248]): Use jM.
1824         (*<code>si_1_zext[zero_extend + any_or]): Likewise.
1825         * config/i386/predicates.md (apx_ndd_memory_operand): New.
1826         (apx_ndd_add_memory_operand): Likewise.
1827
1828 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
1829
1830         PR target/113824
1831         * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
1832         * doc/avr-mmcu.texi: Rebuild.
1833
1834 2024-02-08  Tamar Christina  <tamar.christina@arm.com>
1835
1836         PR tree-optimization/113808
1837         * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
1838         value cross iterations.
1839
1840 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
1841
1842         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
1843         defines __AVR_PM_BASE_ADDRESS__ if the core has it.
1844
1845 2024-02-08  Richard Biener  <rguenther@suse.de>
1846
1847         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1848         Revert last change to dr_may_alias_p.
1849
1850 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
1851
1852         * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
1853         cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
1854         Remove spec asm_misc.
1855         * config/avr/specs.h: Same.
1856
1857 2024-02-08  Pan Li  <pan2.li@intel.com>
1858
1859         PR target/113766
1860         * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
1861         sure the c.arg_num is >= 2 before checking.
1862         (struct build_frm_base): Ditto.
1863         (struct narrow_alu_def): Ditto.
1864
1865 2024-02-07  Richard Biener  <rguenther@suse.de>
1866
1867         PR tree-optimization/113796
1868         * tree-if-conv.cc (combine_blocks): Wipe range-info before
1869         replacing PHIs and inserting predicates.
1870
1871 2024-02-07  Roger Sayle  <roger@nextmovesoftware.com>
1872             Uros Bizjak  <ubizjak@gmail.com>
1873
1874         PR target/113690
1875         * config/i386/i386-features.cc (timode_convert_cst): New helper
1876         function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
1877         CONST_VECTOR.
1878         (timode_scalar_chain::convert_op): Use timode_convert_cst.
1879         (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
1880         Use timode_convert_cst.
1881
1882 2024-02-07  Victor Do Nascimento  <victor.donascimento@arm.com>
1883
1884         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1885         * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
1886         (AARCH64_FL_DEBUGv8p9): Likewise.
1887         (AARCH64_FL_FGT2): Likewise.Likewise.
1888         (AARCH64_FL_ITE): Likewise.
1889         (AARCH64_FL_PFAR): Likewise.
1890         (AARCH64_FL_PMUv3_ICNTR): Likewise.
1891         (AARCH64_FL_PMUv3_SS): Likewise.
1892         (AARCH64_FL_PMUv3p9): Likewise.
1893         (AARCH64_FL_RASv2): Likewise.
1894         (AARCH64_FL_S1PIE): Likewise.
1895         (AARCH64_FL_S1POE): Likewise.
1896         (AARCH64_FL_S2PIE): Likewise.
1897         (AARCH64_FL_S2POE): Likewise.
1898         (AARCH64_FL_SCTLR2): Likewise.
1899         (AARCH64_FL_SEBEP): Likewise.
1900         (AARCH64_FL_SPE_FDS): Likewise.
1901         (AARCH64_FL_TCR2): Likewise.
1902
1903 2024-02-07  Richard Biener  <rguenther@suse.de>
1904
1905         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1906         Only check whether reads are in-bound in places that are not safe.
1907         Fix dependence check.  Add missing newline.  Clarify comments.
1908
1909 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
1910
1911         PR tree-optimization/113750
1912         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
1913         for single predecessor when doing early break vect.
1914         * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
1915         after labels.
1916
1917 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
1918
1919         PR tree-optimization/113731
1920         * gimple-iterator.cc (gsi_move_before): Take new parameter for update
1921         method.
1922         * gimple-iterator.h (gsi_move_before): Default new param to
1923         GSI_SAME_STMT.
1924         * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
1925         GSI_NEW_STMT.
1926
1927 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
1928
1929         PR tree-optimization/113756
1930         * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
1931         use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
1932         of lh_bits value and mask.
1933
1934 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
1935
1936         PR tree-optimization/113753
1937         * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
1938         UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
1939         not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
1940         so that they start with r[half_blocks_needed] lowest bit.  Fix up
1941         computation of top mask for SIGNED.
1942
1943 2024-02-07  Pan Li  <pan2.li@intel.com>
1944
1945         PR target/113766
1946         * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
1947         the signature of func.
1948         * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
1949         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
1950         overloaded func with empty args error.
1951
1952 2024-02-06  H.J. Lu  <hjl.tools@gmail.com>
1953
1954         PR target/113689
1955         * config/i386/i386.cc (x86_64_select_profile_regnum): Return
1956         R10_REG after sorry.
1957
1958 2024-02-06  Andrew Carlotti  <andrew.carlotti@arm.com>
1959
1960         * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
1961         Move before new caller, and add ".default" suffix.
1962         (get_suffixed_assembler_name): New.
1963         (make_resolver_func): Use get_suffixed_assembler_name.
1964         (aarch64_generate_version_dispatcher_body): Redo name mangling.
1965
1966 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
1967
1968         PR target/113763
1969         * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
1970         element from std::pair<unsigned int, char> to an unnamed struct.
1971         Adjust uses of tile range variable.
1972
1973 2024-02-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1974
1975         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
1976         (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
1977
1978 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
1979
1980         PR sanitizer/110676
1981         * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
1982         reset maxlen to sizetype maximum.
1983
1984 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
1985
1986         PR tree-optimization/113736
1987         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
1988         var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
1989
1990 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
1991
1992         PR tree-optimization/113759
1993         * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
1994         or from_unsignedN differs from properties of typeN, update typeN
1995         to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
1996         uselessly convertible to typeN, convert it using fold_convert or
1997         build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
1998         (convert_plusminus_to_widen): Likewise.
1999
2000 2024-02-06  Tejas Belagod  <tejas.belagod@arm.com>
2001
2002         PR target/112577
2003         * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
2004         vector structure modes correctly.
2005
2006 2024-02-05  Christoph Müllner  <christoph.muellner@vrull.eu>
2007
2008         * config/riscv/thead.cc (th_print_operand_address): Fix compiler
2009         warning.
2010
2011 2024-02-05  H.J. Lu  <hjl.tools@gmail.com>
2012
2013         PR target/113689
2014         * config/i386/i386.cc (x86_64_select_profile_regnum): New.
2015         (x86_function_profiler): Call x86_64_select_profile_regnum to
2016         get a scratch register for large model profiling.
2017
2018 2024-02-05  Richard Ball  <richard.ball@arm.com>
2019
2020         * config/arm/arm.cc (arm_output_mi_thunk): Emit
2021         insn for bti_c when bti is enabled.
2022
2023 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
2024
2025         * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
2026         neg.
2027
2028 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
2029
2030         * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
2031         (neg<mode>2): Change the mode iterator from MSA to IMSA because
2032         in FP arithmetic we cannot use (0 - x) for -x.
2033         (neg<mode>2): New define_insn to implement FP vector negation,
2034         using a bnegi instruction to negate the sign bit.
2035
2036 2024-02-05  Richard Biener  <rguenther@suse.de>
2037
2038         PR tree-optimization/113707
2039         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
2040         checking the avail set treat out-of-region defines as
2041         available.
2042
2043 2024-02-05  Richard Biener  <rguenther@suse.de>
2044
2045         * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
2046         the default mode when building a pointer.
2047
2048 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
2049
2050         PR tree-optimization/113737
2051         * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
2052         has just a single label, remove it and make single successor edge
2053         EDGE_FALLTHRU.
2054
2055 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
2056
2057         PR target/113059
2058         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2059         Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
2060         df_analyze call.
2061
2062 2024-02-05  Richard Biener  <rguenther@suse.de>
2063
2064         PR target/113255
2065         * config/i386/i386-expand.cc
2066         (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
2067         Use a new pseudo for the skipped number of bytes.
2068
2069 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
2070
2071         * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
2072         * doc/invoke.texi (RISC-V Options): Add sifive-p450,
2073         sifive-p670.
2074
2075 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
2076
2077         * config/riscv/riscv.md: Include sifive-p400.md.
2078         * config/riscv/sifive-p400.md: New file.
2079         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2080         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2081         Add sifive_p400.
2082         * config/riscv/riscv.cc (sifive_p400_tune_info): New.
2083         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2084         * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2085
2086 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
2087
2088         * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
2089         Add missing ":SI" to the match_operator.
2090
2091 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
2092
2093         * config/xtensa/xtensa.md (SHI): New mode iterator.
2094         (2 split patterns related to constsynth):
2095         Change to also accept HImode operands.
2096
2097 2024-02-04  Jeff Law  <jlaw@ventanamicro.com>
2098
2099         * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
2100         similarly.
2101
2102 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
2103
2104         * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
2105         incorrect expand.
2106         * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
2107         (elmsgnbit): Likewise.
2108         (neg<mode:FVEC>2): New define_insn.
2109         * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
2110         are now instantiated in simd.md.
2111
2112 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
2113
2114         * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
2115         use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
2116         MAX_MACHINE_MODE.
2117
2118 2024-02-04  Li Wei  <liwei@loongson.cn>
2119
2120         * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
2121         (loongarch_expand_vselect_vconcat): Ditto.
2122         (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
2123         all 128-bit constant permutation situations.
2124         (loongarch_expand_lsx_shuffle): Adjust and rename function name.
2125         (loongarch_is_imm_set_shuffle): Renamed function name.
2126         (loongarch_expand_vec_perm_even_odd): Function forward declaration.
2127         (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
2128         extract-even and extract-odd permutations.
2129         (loongarch_is_odd_extraction): Delete.
2130         (loongarch_is_even_extraction): Ditto.
2131         (loongarch_expand_vec_perm_const): Adjust.
2132
2133 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
2134
2135         PR middle-end/113722
2136         * wide-int.cc (wi::bswap_large): Rename third argument from
2137         len to xlen and adjust use in safe_uhwi.  Add len variable, set
2138         it to BLOCKS_NEEDED (precision) and use it for clearing of val
2139         and as canonize argument.  Clear val using memset instead of
2140         a loop.
2141
2142 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
2143
2144         * ggc-common.cc (gt_pch_save): Allow addr to be equal to
2145         mmi.preferred_base + mmi.size - sizeof (void *).
2146
2147 2024-02-03  Xi Ruoyao  <xry111@xry111.site>
2148
2149         * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
2150         * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
2151         the ODR-violating locale declaration.
2152
2153 2024-02-02  Tamar Christina  <tamar.christina@arm.com>
2154
2155         PR tree-optimization/113588
2156         PR tree-optimization/113467
2157         * tree-vect-data-refs.cc
2158         (vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
2159         (vect_analyze_early_break_dependences): Update comments.
2160
2161 2024-02-02  John David Anglin  <danglin@gcc.gnu.org>
2162
2163         PR target/59778
2164         * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
2165         and PA_BUILTIN_SET_FPSR builtins.
2166         * (pa_builtins_icode): Declare.
2167         * (def_builtin, pa_fpu_init_builtins): New.
2168         * (pa_init_builtins): Initialize FPU builtins.
2169         * (pa_builtin_decl, pa_expand_builtin_1): New.
2170         * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
2171         PA_BUILTIN_SET_FPSR builtins.
2172         * (pa_atomic_assign_expand_fenv): New.
2173         * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
2174         UNSPECV constants.
2175         (get_fpsr, put_fpsr): New expanders.
2176         (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
2177         insn patterns.
2178
2179 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2180
2181         PR target/113697
2182         * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
2183
2184 2024-02-02  Jonathan Wakely  <jwakely@redhat.com>
2185
2186         * doc/extend.texi (Common Type Attributes): Fix typo in
2187         description of hardbool.
2188
2189 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
2190
2191         PR tree-optimization/113692
2192         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
2193         from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
2194         final_cast_p.
2195
2196 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
2197
2198         PR middle-end/113699
2199         * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
2200         uninitialized large/huge _BitInt SSA_NAME inputs.
2201
2202 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
2203
2204         PR middle-end/113705
2205         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
2206         around wi::to_wide in order to compare value in prec precision.
2207
2208 2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>
2209
2210         Revert:
2211         2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2212
2213         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2214
2215 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2216
2217         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2218
2219 2024-02-02  Pan Li  <pan2.li@intel.com>
2220
2221         * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
2222         (riscv_pass_by_reference): Ditto.
2223         (riscv_fntype_abi): Ditto.
2224
2225 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2226
2227         * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
2228         (pre_vsetvl::cleaup): Remove vsetvl_pre.
2229         (pre_vsetvl::remove_vsetvl_pre_insns): New function.
2230
2231 2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>
2232
2233         * config/loongarch/larchintrin.h
2234         (__frecipe_s): Update function return type.
2235         (__frecipe_d): Ditto.
2236         (__frsqrte_s): Ditto.
2237         (__frsqrte_d): Ditto.
2238
2239 2024-02-02  Li Wei  <liwei@loongson.cn>
2240
2241         * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
2242         (loongarch_vector_costs::add_stmt_cost): Adjust.
2243
2244 2024-02-02  Xi Ruoyao  <xry111@xry111.site>
2245
2246         * config/loongarch/loongarch.md (unspec): Add
2247         UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
2248         (la_pcrel64_two_parts): New define_insn.
2249         * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
2250         typo in the comment.
2251         (loongarch_call_tls_get_addr): If -mcmodel=extreme
2252         -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
2253         addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
2254         note to allow CSE addressing __tls_get_addr.
2255         (loongarch_legitimize_tls_address): If -mcmodel=extreme
2256         -mexplicit-relocs={always,auto}, address TLS IE symbols with
2257         la_pcrel64_two_parts.
2258         (loongarch_split_symbol): If -mcmodel=extreme
2259         -mexplicit-relocs={always,auto}, address symbols with
2260         la_pcrel64_two_parts.
2261         (loongarch_output_mi_thunk): Clean up unreachable code.  If
2262         -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
2263         thunks with la_pcrel64_two_parts.
2264
2265 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2266
2267         * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
2268         Add support for call36.
2269
2270 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2271
2272         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2273         When the code model of the symbol is extreme and -mexplicit-relocs=auto,
2274         the macro instruction loading symbol address is not applicable.
2275         (loongarch_call_tls_get_addr): Adjust code.
2276         (loongarch_legitimize_tls_address): Likewise.
2277
2278 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2279
2280         * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
2281         Add function declaration.
2282         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2283         For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
2284         is not allowed
2285         (loongarch_load_tls): Added macro support in extreme mode.
2286         (loongarch_call_tls_get_addr): Likewise.
2287         (loongarch_legitimize_tls_address): Likewise.
2288         (loongarch_force_address): Likewise.
2289         (loongarch_legitimize_move): Likewise.
2290         (loongarch_output_mi_thunk): Likewise.
2291         (loongarch_option_override_internal): Remove the code that detects
2292         explicit relocs status.
2293         (loongarch_handle_model_attribute): Likewise.
2294         * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
2295         * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
2296         (symbolic_off64_or_reg_operand): Likewise.
2297
2298 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2299
2300         * config/loongarch/loongarch.cc (loongarch_load_tls):
2301         Load all types of tls symbols through one function.
2302         (loongarch_got_load_tls_gd): Delete.
2303         (loongarch_got_load_tls_ld): Delete.
2304         (loongarch_got_load_tls_ie): Delete.
2305         (loongarch_got_load_tls_le): Delete.
2306         (loongarch_call_tls_get_addr): Modify the called function name.
2307         (loongarch_legitimize_tls_address): Likewise.
2308         * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
2309         (@load_tls<mode>): New template.
2310         (@got_load_tls_ld<mode>): Delete.
2311         (@got_load_tls_le<mode>): Delete.
2312         (@got_load_tls_ie<mode>): Delete.
2313
2314 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2315
2316         * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
2317         (loongarch_legitimize_address): Add logical transformation code.
2318
2319 2024-02-01  Marek Polacek  <polacek@redhat.com>
2320
2321         * doc/invoke.texi: Update -Wdangling-reference documentation.
2322
2323 2024-02-01  Uros Bizjak  <ubizjak@gmail.com>
2324
2325         PR target/113701
2326         * config/i386/i386.md (*cmp<dwi>_doubleword):
2327         Do not force SUBREG pieces to pseudos.
2328
2329 2024-02-01  John David Anglin  <danglin@gcc.gnu.org>
2330
2331         * config/pa/pa.md (atomic_storedi_1): Fix bug in
2332         alternative 1.
2333
2334 2024-02-01  Georg-Johann Lay  <avr@gjlay.de>
2335
2336         * config/avr/avr.cc: Tabify.
2337
2338 2024-02-01  Richard Ball  <richard.ball@arm.com>
2339
2340         PR tree-optimization/111268
2341         * tree-vect-slp.cc (vectorizable_slp_permutation_1):
2342         Add variable-length check for vector input arguments
2343         to a function.
2344
2345 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2346
2347         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
2348         hard-code number of SGPR/VGPR/AVGPR registers.
2349         * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
2350         SGPR/VGPR/AVGPR registers.
2351
2352 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
2353
2354         * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
2355         attribute, and include sifive-p600.md.
2356         * config/riscv/generic-ooo.md: Update type attribute.
2357         * config/riscv/generic.md: Update type attribute.
2358         * config/riscv/sifive-7.md: Update type attribute.
2359         * config/riscv/sifive-p600.md: New file.
2360         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2361         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2362         Add sifive_p600.
2363         * config/riscv/riscv.cc (sifive_p600_tune_info): New.
2364         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2365         * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2366
2367 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
2368
2369         * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
2370         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
2371         * config/riscv/riscv.opt: New macro for 7 new unprivileged
2372         extensions.
2373         * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
2374         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
2375
2376 2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
2377
2378         * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
2379         -static-libasan.  Add missing whitespace.
2380
2381 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2382
2383         * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
2384         (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
2385         Don't 'define_constants'.
2386
2387 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2388
2389         * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
2390
2391 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2392
2393         * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
2394         [TARGET_RDNA3]: Adjust.
2395
2396 2024-02-01  Richard Biener  <rguenther@suse.de>
2397
2398         PR tree-optimization/113693
2399         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
2400         data when available.
2401
2402 2024-02-01  Jakub Jelinek  <jakub@redhat.com>
2403             Jason Merrill  <jason@redhat.com>
2404
2405         PR c++/113531
2406         * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
2407         on variables which were promoted to TREE_STATIC.
2408
2409 2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
2410             Richard Biener  <rguenther@suse.de>
2411
2412         PR target/113560
2413         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
2414         information via tree_non_zero_bits to check if this operand
2415         is suitably extended for a widening (or highpart) multiplication.
2416         (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
2417         isn't already of the claimed type.
2418
2419 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2420
2421         Revert:
2422         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2423
2424         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2425         (generic_ooo_branch): ditto
2426         * config/riscv/generic.md (generic_sfb_alu): ditto
2427         (generic_fmul_half): ditto
2428         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2429         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2430         (sifive_7_popcount): ditto
2431         * config/riscv/vector.md: change rdfrm to fmove
2432         * config/riscv/zc.md: change pushpop to load/store
2433
2434 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2435
2436         Revert:
2437         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2438                     Robin Dapp  <rdapp.gcc@gmail.com>
2439
2440         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2441         (generic_ooo_vec_load): ditto
2442         (generic_ooo_vec_store): ditto
2443         (generic_ooo_vec_loadstore_seg): ditto
2444         (generic_ooo_vec_alu): ditto
2445         (generic_ooo_vec_fcmp): ditto
2446         (generic_ooo_vec_imul): ditto
2447         (generic_ooo_vec_fadd): ditto
2448         (generic_ooo_vec_fmul): ditto
2449         (generic_ooo_crypto): ditto
2450         (generic_ooo_perm): ditto
2451         (generic_ooo_vec_reduction): ditto
2452         (generic_ooo_vec_ordered_reduction): ditto
2453         (generic_ooo_vec_idiv): ditto
2454         (generic_ooo_vec_float_divsqrt): ditto
2455         (generic_ooo_vec_mask): ditto
2456         (generic_ooo_vec_vesetvl): ditto
2457         (generic_ooo_vec_setrm): ditto
2458         (generic_ooo_vec_readlen): ditto
2459         * config/riscv/riscv.md: include generic-vector-ooo
2460         * config/riscv/generic-vector-ooo.md: New file. to here
2461
2462 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2463
2464         Revert:
2465         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2466
2467         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2468
2469 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2470
2471         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2472
2473 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2474             Robin Dapp  <rdapp.gcc@gmail.com>
2475
2476         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2477         (generic_ooo_vec_load): ditto
2478         (generic_ooo_vec_store): ditto
2479         (generic_ooo_vec_loadstore_seg): ditto
2480         (generic_ooo_vec_alu): ditto
2481         (generic_ooo_vec_fcmp): ditto
2482         (generic_ooo_vec_imul): ditto
2483         (generic_ooo_vec_fadd): ditto
2484         (generic_ooo_vec_fmul): ditto
2485         (generic_ooo_crypto): ditto
2486         (generic_ooo_perm): ditto
2487         (generic_ooo_vec_reduction): ditto
2488         (generic_ooo_vec_ordered_reduction): ditto
2489         (generic_ooo_vec_idiv): ditto
2490         (generic_ooo_vec_float_divsqrt): ditto
2491         (generic_ooo_vec_mask): ditto
2492         (generic_ooo_vec_vesetvl): ditto
2493         (generic_ooo_vec_setrm): ditto
2494         (generic_ooo_vec_readlen): ditto
2495         * config/riscv/riscv.md: include generic-vector-ooo
2496         * config/riscv/generic-vector-ooo.md: New file. to here
2497
2498 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2499
2500         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2501         (generic_ooo_branch): ditto
2502         * config/riscv/generic.md (generic_sfb_alu): ditto
2503         (generic_fmul_half): ditto
2504         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2505         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2506         (sifive_7_popcount): ditto
2507         * config/riscv/vector.md: change rdfrm to fmove
2508         * config/riscv/zc.md: change pushpop to load/store
2509
2510 2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>
2511
2512         PR target/113657
2513         * config/aarch64/aarch64-simd.md (split for movv8di):
2514         For strict aligned mode, use DImode instead of TImode.
2515
2516 2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>
2517
2518         PR middle-end/113607
2519         * match.pd: Make sure else values match when folding a
2520         vec_cond into a conditional operation.
2521
2522 2024-01-31  Marek Polacek  <polacek@redhat.com>
2523
2524         * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2525
2526 2024-01-31  Tamar Christina  <tamar.christina@arm.com>
2527             Matthew Malcomson  <matthew.malcomson@arm.com>
2528
2529         PR sanitizer/112644
2530         * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
2531         memcmp.
2532         * builtins.cc (expand_builtin): Include HWASAN when checking for
2533         builtin inlining.
2534
2535 2024-01-31  Richard Biener  <rguenther@suse.de>
2536
2537         PR middle-end/110176
2538         * match.pd (zext (bool) <= (int) 4294967295u): Make sure
2539         to match INTEGER_CST only without outstanding conversion.
2540
2541 2024-01-31  Alex Coplan  <alex.coplan@arm.com>
2542
2543         PR target/111677
2544         * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
2545         V16QImode for the full 16-byte FPR saves in the vector PCS case.
2546
2547 2024-01-31  Richard Biener  <rguenther@suse.de>
2548
2549         PR tree-optimization/111444
2550         * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
2551         vn_reference_lookup_2 when optimistically skipping may-defs.
2552
2553 2024-01-31  Richard Biener  <rguenther@suse.de>
2554
2555         PR tree-optimization/113630
2556         * tree-ssa-pre.cc (compute_avail): Avoid registering a
2557         reference with a representation with not matching base
2558         access size.
2559
2560 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
2561
2562         PR rtl-optimization/113656
2563         * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
2564         <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
2565
2566 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
2567
2568         PR debug/113637
2569         * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2570         with BLKmode are larger than DWARF2_ADDR_SIZE.
2571
2572 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
2573
2574         PR tree-optimization/113639
2575         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2576         For VIEW_CONVERT_EXPR set rhs1 to its operand.
2577
2578 2024-01-31  Richard Biener  <rguenther@suse.de>
2579
2580         PR tree-optimization/113670
2581         * tree-vect-data-refs.cc (vect_check_gather_scatter):
2582         Make sure we can take the address of the reference base.
2583
2584 2024-01-31  Georg-Johann Lay  <avr@gjlay.de>
2585
2586         * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2587         ATA5835, ATtiny64AUTO, ATA5700M322.
2588         * doc/avr-mmcu.texi: Rebuild.
2589
2590 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
2591
2592         PR debug/113394
2593         * ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
2594         caller.
2595
2596 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
2597
2598         PR middle-end/112917
2599         PR middle-end/113100
2600         * builtins.cc (expand_builtin_stack_address): Use
2601         STACK_ADDRESS_OFFSET.
2602         * doc/extend.texi (__builtin_stack_address): Adjust.
2603         * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2604         * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2605         * doc/tm.texi: Rebuilt.
2606
2607 2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2608
2609         PR target/113495
2610         * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
2611         (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
2612         (pre_vsetvl::compute_transparent): New function.
2613         (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2614
2615 2024-01-30  Fangrui Song  <maskray@google.com>
2616
2617         PR target/105576
2618         * config/i386/constraints.md: Define constraint "Ws".
2619         * doc/md.texi: Document it.
2620
2621 2024-01-30  Marek Polacek  <polacek@redhat.com>
2622
2623         PR c++/110358
2624         PR c++/109640
2625         * doc/invoke.texi: Update -Wdangling-reference description.
2626
2627 2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
2628
2629         * config/xtensa/constraints.md (R, T, U):
2630         Change define_constraint to define_memory_constraint.
2631         * config/xtensa/predicates.md (move_operand): Don't check that a
2632         constant pool operand size is a multiple of UNITS_PER_WORD.
2633         * config/xtensa/xtensa.cc
2634         (xtensa_lra_p, TARGET_LRA_P): Remove.
2635         (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
2636         clause as it can no longer be true.
2637         (fixup_subreg_mem): Drop function.
2638         (xtensa_output_integer_literal_parts): Consider 16-bit wide
2639         constants.
2640         (xtensa_legitimate_constant_p): Add short-circuit path for
2641         integer load instructions. Don't check that mode size is
2642         at least UNITS_PER_WORD.
2643         * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
2644         rather reload_in_progress and reload_completed.
2645         (doloop_end): Drop operand 2.
2646         (movhi_internal): Add alternative loading constant from a
2647         literal pool.
2648         (define_split for DI register_operand): Don't limit to
2649         !TARGET_AUTO_LITPOOLS.
2650         * config/xtensa/xtensa.opt (mlra): Change to no effect.
2651
2652 2024-01-30  Pan Li  <pan2.li@intel.com>
2653
2654         * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
2655         calculate the gpr count required by vls mode.
2656         (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
2657         (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
2658         for vls mode.
2659         (riscv_get_arg_info): Add vls mode handling.
2660         (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
2661
2662 2024-01-30  Richard Biener  <rguenther@suse.de>
2663
2664         PR tree-optimization/113659
2665         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2666         Handle main exit without virtual use.
2667
2668 2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>
2669
2670         * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
2671
2672 2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>
2673
2674         PR libgcc/113403
2675         * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
2676         (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
2677         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
2678         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
2679         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
2680         * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
2681
2682 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
2683
2684         PR target/113623
2685         * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
2686         Mark all registers that occur in addresses as needing a GPR.
2687
2688 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
2689
2690         PR target/113636
2691         * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
2692         the containing insn as an extra parameter.  Reset debug instructions
2693         if they reference a register that is no longer used by real insns.
2694         (early_ra::apply_allocation): Update calls accordingly.
2695
2696 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
2697
2698         PR tree-optimization/113603
2699         * tree-ssa-strlen.cc (strlen_pass::handle_store): After
2700         count_nonzero_bytes call refetch si using get_strinfo in case it
2701         has been unshared in the meantime.
2702
2703 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
2704
2705         PR middle-end/101195
2706         * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
2707         fit into unsigned HOST_WIDE_INT, return constm1_rtx.
2708
2709 2024-01-30  Jin Ma  <jinma@linux.alibaba.com>
2710
2711         * config/riscv/thead.cc (th_print_operand_address): Change %ld
2712         to %lld.
2713
2714 2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
2715             Manolis Tsamis  <manolis.tsamis@vrull.eu>
2716             Philipp Tomsich  <philipp.tomsich@vrull.eu>
2717
2718         * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
2719         * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
2720         Likewise.
2721         * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
2722         Call on framework moved later.
2723
2724 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
2725
2726         * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
2727         instruction in naked function epilogues.
2728
2729 2024-01-29  YunQiang Su  <syq@gcc.gnu.org>
2730
2731         PR target/113655
2732         * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
2733         gcc_cv_as_mips_explicit_relocs.
2734         * configure: Regnerated.
2735
2736 2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>
2737
2738         PR target/108933
2739         * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
2740         Correct generated RTL.
2741         (arm_rev16si2_alt1): Correctly handle conditional execution.
2742         (arm_rev16si2_alt2): Likewise.
2743
2744 2024-01-29  Richard Biener  <rguenther@suse.de>
2745
2746         PR middle-end/113622
2747         * expr.cc (expand_assignment): Spill hard registers if
2748         we index them with a variable offset.
2749
2750 2024-01-29  Richard Biener  <rguenther@suse.de>
2751
2752         PR middle-end/113622
2753         * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
2754         Also allow DECL_HARD_REGISTER variables.
2755
2756 2024-01-29  Alex Coplan  <alex.coplan@arm.com>
2757
2758         PR target/113616
2759         * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
2760         Use iterate_safely when iterating over debug uses.
2761         (fixup_debug_uses): Likewise.
2762         (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
2763         over nondebug insns instead of manually maintaining the next insn.
2764         * iterator-utils.h (class safe_iterator): New.
2765         (iterate_safely): New.
2766
2767 2024-01-29  H.J. Lu  <hjl.tools@gmail.com>
2768
2769         PR target/38534
2770         * config/i386/i386-options.cc (ix86_set_func_type): Save
2771         callee-saved registers in noreturn functions for -O0/-Og.
2772
2773 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
2774
2775         PR target/113615
2776         * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
2777         define for !TARGET_RDNA2_PLUS.
2778
2779 2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
2780
2781         PR target/113281
2782         * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
2783         workaround for right shifts.
2784         (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
2785         (vect_determine_precisions_from_range): Be more selective about
2786         which codes can be narrowed based on their input and output ranges.
2787         For shifts, require at least one more bit of precision than the
2788         maximum shift amount.
2789
2790 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
2791
2792         * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
2793
2794 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
2795
2796         * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
2797         but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
2798         LLVM 13.0.1+.
2799
2800 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
2801
2802         PR other/111966
2803         * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
2804         (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
2805         (SET_SRAM_ECC_UNSET): ... this.
2806         (copy_early_debug_info): Remove gfx900 special case, now handled as
2807         part of the generic handling.
2808         (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
2809
2810 2024-01-29  Jakub Jelinek  <jakub@redhat.com>
2811
2812         PR tree-optimization/110603
2813         * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
2814         setting of pdata->maxlen to vr.upper_bound (which is unconditionally
2815         overwritten anyway).  Avoid creating invalid range with minlen
2816         larger than maxlen.  Formatting fix.
2817
2818 2024-01-29  Richard Biener  <rguenther@suse.de>
2819
2820         PR debug/103047
2821         * tree-inline.cc (initialize_inlined_parameters): Reverse
2822         the decl chain of inlined parameters.
2823
2824 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
2825
2826         * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
2827         alignment of CFString constants by setting DECL_USER_ALIGN.
2828
2829 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
2830             Jakub Jelinek   <jakub@redhat.com>
2831
2832         PR libgcc/113402
2833         * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
2834         and BUILT_IN_GCC_NESTED_PTR_DELETED.
2835         * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
2836         BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
2837         rename the library fallbacks to __gcc_nested_func_ptr_created and
2838         __gcc_nested_func_ptr_deleted.
2839         * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
2840         and __gcc_nested_func_ptr_deleted.
2841         * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
2842         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
2843         * tree.cc (build_common_builtin_nodes): Build the
2844         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
2845         builtins only for non-explicit.
2846
2847 2024-01-28  YunQiang Su  <syq@gcc.gnu.org>
2848
2849         * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
2850
2851 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
2852
2853         PR target/38534
2854         * config/i386/i386-options.cc (ix86_set_func_type): Don't
2855         save and restore callee saved registers for a noreturn function
2856         with nothrow or compiled with -fno-exceptions.
2857
2858 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
2859
2860         PR target/103503
2861         PR target/113312
2862         * config/i386/i386-expand.cc (ix86_expand_call): Replace
2863         no_caller_saved_registers check with call_saved_registers check.
2864         Clobber all registers that are not used by the callee with
2865         no_callee_saved_registers attribute.
2866         * config/i386/i386-options.cc (ix86_set_func_type): Set
2867         call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
2868         noreturn function.  Disallow no_callee_saved_registers with
2869         interrupt or no_caller_saved_registers attributes together.
2870         (ix86_set_current_function): Replace no_caller_saved_registers
2871         check with call_saved_registers check.
2872         (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
2873         (ix86_handle_call_saved_registers_attribute): This.
2874         (ix86_gnu_attributes): Add
2875         ix86_handle_call_saved_registers_attribute.
2876         * config/i386/i386.cc (ix86_conditional_register_usage): Replace
2877         no_caller_saved_registers check with call_saved_registers check.
2878         (ix86_function_ok_for_sibcall): Don't allow callee with
2879         no_callee_saved_registers attribute when the calling function
2880         has callee-saved registers.
2881         (ix86_comp_type_attributes): Also check
2882         no_callee_saved_registers.
2883         (ix86_epilogue_uses): Replace no_caller_saved_registers check
2884         with call_saved_registers check.
2885         (ix86_hard_regno_scratch_ok): Likewise.
2886         (ix86_save_reg): Replace no_caller_saved_registers check with
2887         call_saved_registers check.  Don't save any registers for
2888         TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
2889         TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
2890         no_callee_saved_registers attribute is called.
2891         (find_drap_reg): Replace no_caller_saved_registers check with
2892         call_saved_registers check.
2893         * config/i386/i386.h (call_saved_registers_type): New enum.
2894         (machine_function): Replace no_caller_saved_registers with
2895         call_saved_registers.
2896         * doc/extend.texi: Document no_callee_saved_registers attribute.
2897
2898 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
2899
2900         PR tree-optimization/113614
2901         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
2902         widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
2903         TRUNC_MOD_EXPR or FLOAT_EXPR uses.
2904
2905 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
2906
2907         PR tree-optimization/113568
2908         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
2909         For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
2910         in the widening extension checks.
2911
2912 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
2913
2914         * gimple-lower-bitint.cc (gimple_lower_bitint): For
2915         TDF_DETAILS dump mapping of SSA_NAMEs to decls.
2916
2917 2024-01-26  Hans-Peter Nilsson  <hp@axis.com>
2918
2919         * cgraphunit.cc (process_function_and_variable_attributes): Tweak
2920         the warning for an attribute-always_inline without inline declaration.
2921
2922 2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>
2923
2924         PR other/113575
2925         * genopinit.cc (main): Split init_all_optabs into functions
2926         of 1000 patterns each.
2927
2928 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
2929
2930         * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
2931         TM_MULTILIB_CONFIG.
2932         * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
2933         * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
2934         -march/-mtune.
2935
2936 2024-01-26  Andrew Stubbs  <ams@baylibre.com>
2937
2938         * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
2939         * config/gcn/gcn-valu.md (all_convert): New iterator.
2940         (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
2941         define_expand, and rename the old one to ...
2942         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
2943         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
2944         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
2945         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
2946         * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
2947         (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
2948         * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
2949         (<u>mulqihi3_scalar): Likewise.
2950
2951 2024-01-26  Richard Biener  <rguenther@suse.de>
2952
2953         PR tree-optimization/113602
2954         * tree-data-ref.cc (dr_analyze_innermost): Fail when
2955         the base object isn't addressable.
2956
2957 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
2958
2959         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
2960         "--amdhsa-code-object-version=" argument.
2961         (ASM_SPEC): Use it; replace previous version of it.
2962
2963 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2964
2965         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
2966         (pre_vsetvl::emit_vsetvl): Ditto.
2967
2968 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
2969
2970         * config/loongarch/lasx.md (vec_extract<mode>_0):
2971         New define_insn_and_split patten.
2972
2973 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
2974
2975         * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
2976
2977 2024-01-26  Li Wei  <liwei@loongson.cn>
2978
2979         * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
2980
2981 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2982
2983         PR target/113469
2984         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
2985
2986 2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>
2987
2988         PR target/100212
2989         * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
2990         undefined shift after the call to exact_log2.
2991
2992 2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>
2993
2994         PR target/100204
2995         * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
2996         before taking the negative of it.
2997
2998 2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>
2999
3000         PR target/113526
3001         * lra-constraints.cc (curr_insn_transform): Change class even for
3002         spilled pseudo successfully matched with with NO_REGS.
3003
3004 2024-01-25  Georg-Johann Lay  <avr@gjlay.de>
3005
3006         PR target/113601
3007         * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
3008
3009 2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
3010
3011         PR target/112987
3012         * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
3013         (aarch64_expand_epilogue): Use the new function.
3014         (aarch64_split_compare_and_swap): Likewise.
3015         (aarch64_split_atomic_op): Likewise.
3016
3017 2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>
3018
3019         PR middle-end/112971
3020         * fold-const.cc (simplify_const_binop): New function for binop
3021         simplification of two constant vectors when element-wise
3022         handling is not necessary.
3023         (const_binop): Call new function.
3024
3025 2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>
3026
3027         * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
3028         * config/riscv/constraints.md: Likewise.
3029         * config/riscv/corev.def: Likewise.
3030         * config/riscv/corev.md: Likewise.
3031         * config/riscv/predicates.md: Likewise.
3032         * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
3033         * config/riscv/riscv-ftypes.def: Likewise.
3034         * config/riscv/riscv.opt: Likewise.
3035         * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
3036         * doc/extend.texi: Add XCVbitmanip builtin documentation.
3037         * doc/sourcebuild.texi: Likewise.
3038
3039 2024-01-25  Tobias Burnus  <tburnus@baylibre.com>
3040
3041         * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
3042
3043 2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>
3044
3045         PR target/113538
3046         * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
3047         (riscv_fntype_abi): Ditto.
3048         * config/riscv/riscv.opt: Ditto.
3049
3050 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
3051
3052         PR middle-end/113574
3053         * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
3054         count against TYPE_PRECISION rather than TYPE_SIZE.
3055
3056 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
3057
3058         PR target/113572
3059         * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
3060         Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
3061
3062 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
3063
3064         PR target/113550
3065         * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
3066         whether each split instruction is a load that clobbers the source
3067         address.  Emit that instruction last if so.
3068
3069 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
3070
3071         PR target/113485
3072         * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
3073         pattern.
3074         (<optab><Vnarrowq><mode>2): Use it instead of generating a
3075         paradoxical subreg for the input.
3076
3077 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3078
3079         * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
3080         (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
3081         predecessors dump information.
3082
3083 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3084
3085         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
3086         redundant full available computation.
3087         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3088
3089 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
3090
3091         * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
3092         * doc/rtl.texi (CONST_VECTOR): Likewise.
3093
3094 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3095
3096         * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
3097         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
3098         (pass_vsetvl::execute): Ditto.
3099         * config/riscv/riscv.opt: Ditto.
3100
3101 2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>
3102
3103         * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
3104         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
3105
3106 2024-01-25  Richard Biener  <rguenther@suse.de>
3107
3108         PR tree-optimization/113576
3109         * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
3110         exits with may_be_zero niters when its the last one.
3111
3112 2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>
3113
3114         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3115         For symbols of type tls, non-zero Offset is not generated.
3116
3117 2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>
3118
3119         * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
3120         P9 with m32 and mpowerpc64.
3121
3122 2024-01-25  liuhongt  <hongtao.liu@intel.com>
3123
3124         * config/i386/i386-options.cc (ix86_option_override_internal):
3125         Enable -mlam=u57 by default when compiled with
3126         -fsanitize=hwaddress.
3127
3128 2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>
3129
3130         * common/config/riscv/riscv-common.cc (riscv_implied_info):
3131         Remove {"ztso", "a"}.
3132
3133 2024-01-24  Martin Jambor  <mjambor@suse.cz>
3134
3135         PR ipa/108007
3136         PR ipa/112616
3137         * cgraph.h (cgraph_edge): Add a parameter to
3138         redirect_call_stmt_to_callee.
3139         * ipa-param-manipulation.h (ipa_param_adjustments): Add a
3140         parameter to modify_call.
3141         (ipa_release_ssas_in_hash): Declare.
3142         * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
3143         parameter killed_ssas, pass it to padjs->modify_call.
3144         * ipa-param-manipulation.cc (purge_all_uses): New function.
3145         (ipa_param_adjustments::modify_call): New parameter killed_ssas.
3146         Instead of substituting uses, invoke purge_all_uses.  If
3147         hash of killed SSAs has not been provided, create a temporary one
3148         and release SSAs that have been added to it.
3149         (compare_ssa_versions): New function.
3150         (ipa_release_ssas_in_hash): Likewise.
3151         * tree-inline.cc (redirect_all_calls): Create
3152         id->killed_new_ssa_names earlier, pass it to edge redirection,
3153         adjust a comment.
3154         (copy_body): Release SSAs in id->killed_new_ssa_names.
3155
3156 2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>
3157
3158         PR target/113486
3159         * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
3160         TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
3161
3162 2024-01-24  Monk Chiang  <monk.chiang@sifive.com>
3163
3164         PR target/113095
3165         * config/riscv/sfb.md: New splitters to rewrite single bit
3166         sign extension as the condition to SFB instructions.
3167
3168 2024-01-24  Jan Hubicka  <jh@suse.cz>
3169
3170         PR middle-end/88345
3171         * common.opt: (flimit-function-alignment): Reorder alphabeticaly
3172         (fmin-function-alignment): New parameter.
3173         * doc/invoke.texi: (-fmin-function-alignment): Document.
3174         (-falign-functions,-falign-loops,-falign-labels): Mention that
3175         aglinments are ignored in cold code.
3176         * varasm.cc (assemble_start_function): Handle min-function-alignment.
3177
3178 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3179
3180         PR target/109636
3181         * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
3182         mulv2di3): Remove.
3183         * config/aarch64/iterators.md (VQDIV): Remove.
3184         (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
3185         SVE_I_SIMD_DI): New.
3186         (VPRED, sve_lane_con): Add V4SI and V2DI.
3187         * config/aarch64/aarch64-sve.md (<optab><mode>3,
3188         @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
3189         (mul<mode>3): New, split from <optab><mode>3.
3190         (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
3191         * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
3192         *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
3193         SVE_FULL_HSDI_SIMD_DI.
3194
3195 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3196
3197         PR tree-optimization/113552
3198         * config/aarch64/aarch64.cc
3199         (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
3200
3201 2024-01-24  Martin Jambor  <mjambor@suse.cz>
3202
3203         PR ipa/113490
3204         * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
3205         count is equal or greater than the limit.  Use the limit from the
3206         callee.
3207
3208 2024-01-24  YunQiang Su  <syq@gcc.gnu.org>
3209
3210         * configure.ac: Detect the explicit relocs support for
3211         mips, and define C macro MIPS_EXPLICIT_RELOCS.
3212         * config.in: Regenerated.
3213         * configure: Regenerated.
3214         * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
3215         * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
3216         * config/mips/mips.cc(mips_set_compression_mode): Sorry if
3217         !TARGET_EXPLICIT_RELOCS instead of just set it.
3218         * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
3219         TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
3220         * config/mips/mips.opt: Introduce -mexplicit-relocs= option
3221         and define -m(no-)explicit-relocs as aliases.
3222
3223 2024-01-24  Alex Coplan  <alex.coplan@arm.com>
3224
3225         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3226         to 1.
3227         (-mlate-ldp-fusion): Likewise.
3228
3229 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3230
3231         * tree-vect-loop.cc (vect_get_vect_def,
3232         vect_create_epilog_for_reduction): Rename main_exit_p to
3233         last_val_reduc_p.
3234
3235 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3236
3237         PR tree-optimization/113364
3238         * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
3239         early exits then we must reduce from the first offset for all of them.
3240
3241 2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3242
3243         PR target/113495
3244         * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
3245         (get_regno): Ditto.
3246         (get_bb_index): Ditto.
3247         (pre_vsetvl::compute_avl_def_data): Ditto.
3248         (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
3249         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3250
3251 2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
3252             Richard Sandiford  <richard.sandiford@arm.com>
3253
3254         PR target/100942
3255         * ccmp.cc (ccmp_candidate_p): Add outer argument.
3256         Allow if the outer is true and the lhs is used more
3257         than once.
3258         (expand_ccmp_expr): Update call to ccmp_candidate_p.
3259         * expr.h (expand_expr_real_gassign): Declare.
3260         * expr.cc (expand_expr_real_gassign): New function, split out from...
3261         (expand_expr_real_1): ...here.
3262         * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
3263
3264 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3265
3266         PR target/113089
3267         * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
3268         (fixup_debug_use): New.
3269         (fixup_debug_uses_trailing_add): New.
3270         (fixup_debug_uses): New. Use it ...
3271         (ldp_bb_info::fuse_pair): ... here.
3272         (try_promote_writeback): Call fixup_debug_uses_trailing_add to
3273         fix up debug uses of the base register that are affected by
3274         folding in the trailing add insn.
3275
3276 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3277
3278         PR target/113089
3279         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
3280         Update trailing nondebug uses of the base register in the case
3281         of cancelling writeback.
3282
3283 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3284
3285         PR target/113089
3286         * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
3287         (debug_insn_use_iterator): New.
3288         (set_info::first_debug_insn_use): New.
3289         (set_info::debug_insn_uses): New.
3290         * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
3291         (set_info::first_debug_insn_use): New.
3292         (set_info::debug_insn_uses): New.
3293
3294 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3295
3296         PR target/113356
3297         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
3298         Don't record hazards against the opposite insn in the pair.
3299
3300 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3301
3302         PR target/113070
3303         * config/aarch64/aarch64-ldp-fusion.cc
3304         (struct stp_change_builder): New.
3305         (decide_stp_strategy): Reanme to ...
3306         (try_repurpose_store): ... this.
3307         (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
3308         construct stp changes.  Fix up uses when inserting new stp insns.
3309
3310 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3311
3312         PR target/113070
3313         * rtl-ssa.h: Include hash-set.h.
3314         * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
3315         new_sets parameter and use it to keep track of new user-created sets.
3316         (function_info::apply_changes_to_insn): Also call add_def on new sets.
3317         (function_info::change_insns): Add hash_set to keep track of new
3318         user-created defs.  Plumb it through.
3319         * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
3320         apply_changes_to_insn.
3321
3322 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3323
3324         PR target/113070
3325         * rtl-ssa/accesses.cc (function_info::create_use): New.
3326         * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
3327         Ensure new uses end up referring to permanent defs.
3328         * rtl-ssa/functions.h (function_info::create_use): Declare.
3329
3330 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3331
3332         PR target/113070
3333         * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
3334         to finalize_new_accesses from the backwards placement loop, run it
3335         forwards in a separate loop.
3336
3337 2024-01-23  Richard Biener  <rguenther@suse.de>
3338
3339         PR tree-optimization/113552
3340         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
3341         floor_log2 instead of exact_log2 on the number of calls.
3342
3343 2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
3344             Jakub Jelinek  <jakub@redhat.com>
3345
3346         * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
3347         decl.
3348
3349 2024-01-23  Richard Biener  <rguenther@suse.de>
3350
3351         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3352         Separate single and multi-exit case when creating PHIs between
3353         the main and epilogue.
3354
3355 2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>
3356
3357         PR target/112989
3358         * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
3359         MODE_single variants of functions that don't take tuple arguments.
3360
3361 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3362
3363         PR target/113114
3364         * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
3365         Don't assert recog success, just punt if the writeback pair
3366         isn't recognized.
3367
3368 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
3369
3370         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
3371         ATTRIBUTE_UNUSED to decl.
3372
3373 2024-01-23  Richard Biener  <rguenther@suse.de>
3374
3375         PR debug/107058
3376         * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
3377         handle unexpected but bogus DIE contexts when not checking
3378         enabled.
3379
3380 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
3381
3382         PR tree-optimization/113462
3383         * fold-const.cc (native_interpret_int): Don't punt if total_bytes
3384         is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
3385         (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
3386         sizes between 129 and 8192 bytes.
3387
3388 2024-01-23  Xi Ruoyao  <xry111@xry111.site>
3389
3390         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3391         If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
3392         for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
3393         (loongarch_call_tls_get_addr): Do not split symbols of
3394         SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
3395         EXPLICIT_RELOCS_AUTO.
3396
3397 2024-01-23  Richard Biener  <rguenther@suse.de>
3398
3399         * alias.cc (known_base_value_p): Remove.
3400         (find_base_value): Remove PLUS/MINUS handling
3401         when both operands are not CONST_INT_P.
3402
3403 2024-01-23  Richard Biener  <rguenther@suse.de>
3404
3405         PR rtl-optimization/113255
3406         * alias.cc (find_base_term): Remove PLUS/MINUS handling
3407         when both operands are not CONST_INT_P.
3408
3409 2024-01-23  Richard Biener  <rguenther@suse.de>
3410
3411         PR debug/112718
3412         * dwarf2out.cc (dwarf2out_finish): Reset all type units
3413         for the fat part of an LTO compile.
3414
3415 2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>
3416
3417         * doc/sourcebuild.texi: Add attributes for keywords.
3418
3419 2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>
3420
3421         PR c++/90463
3422         * doc/invoke.texi (Warning Options): Correct lists of options
3423         enabled by -Wall and -Wextra by checking against common.opt
3424         and c-family/c.opt.
3425
3426 2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>
3427
3428         PR target/113030
3429         * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
3430         instead of cpu_optaliases.
3431         (check_arch): Use arch_opt_alias instead of arch_optaliases.
3432
3433 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3434
3435         * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
3436         * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
3437         * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
3438
3439 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3440
3441         PR target/109092
3442         * config/riscv/riscv.md: Use reg instead of subreg.
3443
3444 2024-01-22  Tobias Burnus  <tburnus@baylibre.com>
3445
3446         PR other/111966
3447         * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
3448         to match the compiler default.
3449         (simple_object_copy_lto_debug_sections): Never unlink the outfile
3450         on error as the caller does so.
3451         (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
3452         (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
3453
3454 2024-01-22  Richard Biener  <rguenther@suse.de>
3455
3456         PR tree-optimization/113373
3457         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3458         Create LC PHIs in the exit blocks where necessary.
3459         * tree-vect-loop.cc (vectorizable_live_operation): Do not try
3460         to handle missing LC PHIs.
3461         (find_connected_edge): Remove.
3462         (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
3463
3464 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3465
3466         * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
3467
3468 2024-01-22  xuli  <xuli1@eswincomputing.com>
3469
3470         PR target/113420
3471         * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
3472         (registered_function::overloaded_hash):refactor.
3473         (resolve_overloaded_builtin):avoid internal ICE.
3474
3475 2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>
3476
3477         PR target/82420
3478         PR target/111279
3479         * calls.cc (emit_library_call_value_1): Pass valid TYPE
3480         to emit_push_insn.
3481         * expr.cc (emit_push_insn): Likewise.
3482
3483 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
3484
3485         * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
3486         correcction version of last change.
3487
3488 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
3489
3490         * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
3491         fix bugs in signature.
3492
3493 2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
3494             Richard Biener  <rguenther@suse.de>
3495
3496         PR rtl-optimization/111267
3497         * fwprop.cc (fwprop_propagation::profitabe_p): Rename
3498         profitable_p method to likely_profitable_p.
3499         (try_fwprop_subst_node): Update call to likely_profitable_p.
3500         Only bail-out early when !prop.likely_profitable_p for instructions
3501         that are not single sets.  When comparing costs, bail-out if the
3502         cost is unchanged and !prop.likely_profitable_p.
3503
3504 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
3505
3506         PR c++/90464
3507         * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
3508         isn't enabled by -Wunused unless -Wextra is provided, and that
3509         -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
3510         -Wunused doesn't enable -Wunused-* options documented as behaving
3511         otherwise, and list them explicitly.
3512
3513 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
3514
3515         PR c/109708
3516         * doc/invoke.texi (Warning Options): Fix broken example and
3517         clean up/reorganize the others.  Also describe what the short-form
3518         options mean.
3519
3520 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
3521
3522         PR c/102998
3523         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
3524         (Warning Options): Correct/edit discussion of -Warray-parameter
3525         to make the first example less confusing, and fill in missing info.
3526
3527 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
3528
3529         PR tree-optimization/113462
3530         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
3531         Handle rhs1 INTEGER_CST like SSA_NAME.
3532
3533 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
3534
3535         PR tree-optimization/113491
3536         * tree-switch-conversion.cc (switch_conversion::build_constructors):
3537         If elt.index has precision higher than sizetype, fold_convert it to
3538         sizetype.
3539         (switch_conversion::array_value_type): Return type if type is
3540         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
3541         (switch_conversion::build_arrays): Use unsigned_type_for rather than
3542         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
3543         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
3544         higher than sizetype, use sizetype as tidx type and fold_convert the
3545         subtraction to sizetype.
3546
3547 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3548
3549         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
3550         (riscv_vector_mode_supported_any_target_p): Ditto.
3551
3552 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
3553
3554         PR target/110934
3555         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
3556         (TARGET_ZERO_CALL_USED_REGS): Define.
3557
3558 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
3559
3560         PR target/108640
3561         * config/m68k/m68k.cc (output_andsi3): Use QImode for
3562         address adjusted for 1-byte RMW access.
3563         (output_iorsi3): Likewise.
3564         (output_xorsi3): Likewise.
3565
3566 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3567
3568         * doc/invoke.texi (RISC-V Options): Add list of supported
3569         extensions.
3570
3571 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3572
3573         PR target/113495
3574         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3575         (RVV_VUNDEF): Ditto.
3576         * config/riscv/riscv-vsetvl.cc: Add timevar.
3577
3578 2024-01-19  Richard Biener  <rguenther@suse.de>
3579
3580         PR debug/113488
3581         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3582         an early DIE but there should be, do not pretend there is.
3583
3584 2024-01-19  Richard Biener  <rguenther@suse.de>
3585
3586         PR tree-optimization/113494
3587         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3588         Handle endless loop on exit.  Handle re-allocated PHI.
3589
3590 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3591
3592         PR tree-optimization/113464
3593         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3594         optimize loads into GIMPLE_ASM stmts.
3595
3596 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3597
3598         PR tree-optimization/113463
3599         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3600         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3601         lhs.
3602
3603 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3604
3605         PR tree-optimization/113459
3606         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
3607         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
3608         of SCALAR_INT_TYPE_MODE if type has BLKmode.
3609         (vn_reference_lookup_3): Likewise.  Formatting fix.
3610
3611 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3612             Richard Biener  <rguenther@suse.de>
3613
3614         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
3615         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
3616         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
3617         but adjust_address also for BLKmode mode and MEM op0.
3618
3619 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
3620
3621         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
3622         extensions.
3623
3624 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3625
3626         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
3627
3628 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3629
3630         * common/config/riscv/riscv-common.cc
3631         (riscv_subset_list::parse_std_ext): Remove.
3632         (riscv_subset_list::parse_multiletter_ext): Remove.
3633         * config/riscv/riscv-subset.h
3634         (riscv_subset_list::parse_std_ext): Remove.
3635         (riscv_subset_list::parse_multiletter_ext): Remove.
3636
3637 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3638
3639         * common/config/riscv/riscv-common.cc
3640         (riscv_subset_list::parse_single_std_ext): New parameter.
3641         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3642         (riscv_subset_list::parse_single_ext): Ditto.
3643         (riscv_subset_list::parse): Relax the order for the input of ISA
3644         string.
3645         * config/riscv/riscv-subset.h
3646         (riscv_subset_list::parse_single_std_ext): New parameter.
3647         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3648         (riscv_subset_list::parse_single_ext): Ditto.
3649
3650 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3651
3652         * common/config/riscv/riscv-common.cc
3653         (riscv_subset_list::parse_base_ext): New.
3654         (riscv_subset_list::parse): Extract part of logic into
3655         riscv_subset_list::parse_base_ext.
3656         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
3657         New.
3658
3659 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3660
3661         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
3662         sorry message.
3663
3664 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
3665
3666         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
3667         UNSPEC_CLMUL_VC.
3668
3669 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
3670
3671         PR c/110029
3672         * doc/extend.texi (Common Variable Attributes): Explain what
3673         happens when multiple variables with cleanups are in the same scope.
3674
3675 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
3676
3677         PR ipa/108470
3678         * doc/extend.texi (Common Function Attributes): Document that
3679         noinline also disables some interprocedural optimizations and
3680         improve flow to the part about using inline asm instead to
3681         disable calls from being optimized away completely.  Remove the
3682         sentence that says noipa is mainly for internal compiler testing.
3683
3684 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
3685
3686         PR tree-optimization/69807
3687         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
3688
3689 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
3690
3691         PR target/108521
3692         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
3693         from x86 Windows Options.
3694
3695 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
3696
3697         PR c/107942
3698         * doc/extend.texi (C Extensions): Add new section to menu.
3699         (Function Attributes):  Move dangling index entries to....
3700         (Const and Volatile Functions): New section.
3701
3702 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
3703
3704         PR middle-end/112684
3705         * toplev.cc (toplev::main): Don't ICE in
3706         -fdiagnostics-generate-patch when exiting after options,
3707         since no edit context will have been created.
3708
3709 2024-01-18  Richard Biener  <rguenther@suse.de>
3710
3711         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
3712         operands vector.
3713
3714 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
3715
3716         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
3717         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
3718
3719 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
3720             Jin Ma  <jinma@linux.alibaba.com>
3721             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
3722             Christoph Müllner  <christoph.muellner@vrull.eu>
3723
3724         * config/riscv/thead.cc
3725         (th_asm_output_opcode): Rewrite some instructions.
3726
3727 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
3728             Jin Ma  <jinma@linux.alibaba.com>
3729             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
3730             Christoph Müllner  <christoph.muellner@vrull.eu>
3731
3732         * config/riscv/riscv.md (none,thv,rvv): New attribute.
3733         (no,yes): Add an attribute to disable alternative
3734         for xtheadvector or RVV1.0.
3735         * config/riscv/vector.md:
3736         Disable alternatives that destination register overlaps
3737         source register group for xtheadvector.
3738
3739 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
3740             Jin Ma  <jinma@linux.alibaba.com>
3741             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
3742             Christoph Müllner  <christoph.muellner@vrull.eu>
3743
3744         * config/riscv/riscv-vector-builtins-bases.cc
3745         (class th_loadstore_width): Define new builtin bases.
3746         (class th_extract): Define new builtin bases.
3747         (BASE): Define new builtin bases.
3748         * config/riscv/riscv-vector-builtins-bases.h:
3749         Define new builtin class.
3750         * config/riscv/riscv-vector-builtins-shapes.cc
3751         (struct th_loadstore_width_def): Define new builtin shapes.
3752         (struct th_indexed_loadstore_width_def):
3753         Define new builtin shapes.
3754         (struct th_extract_def): Define new builtin shapes.
3755         (SHAPE): Define new builtin shapes.
3756         * config/riscv/riscv-vector-builtins-shapes.h:
3757         Define new builtin shapes.
3758         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
3759         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
3760         * config/riscv/riscv-vector-builtins.h
3761         (enum required_ext): Add new XTheadVector member.
3762         (struct function_group_info): Likewise.
3763         * config/riscv/t-riscv:
3764         Add thead-vector-builtins-functions.def
3765         * config/riscv/thead-vector.md
3766         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
3767         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
3768         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
3769         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
3770         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
3771         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
3772         (@pred_th_extract<mode>): Likewise.
3773         (*pred_th_extract<mode>): Likewise.
3774         * config/riscv/thead-vector-builtins-functions.def: New file.
3775
3776 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
3777             Jin Ma  <jinma@linux.alibaba.com>
3778             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
3779             Christoph Müllner  <christoph.muellner@vrull.eu>
3780
3781         * config.gcc:  Add files for XTheadVector intrinsics.
3782         * config/riscv/autovec.md: Guard XTheadVector.
3783         * config/riscv/predicates.md: Disable immediate vl
3784         for XTheadVector.
3785         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
3786         Add pragma for XTheadVector.
3787         * config/riscv/riscv-string.cc (riscv_expand_block_move):
3788         Guard XTheadVector.
3789         * config/riscv/riscv-v.cc (vls_mode_valid_p):
3790         Avoid autovec.
3791         * config/riscv/riscv-vector-builtins-bases.cc:
3792         Do not normalize vsetvl instructions for XTheadVector.
3793         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
3794         New check type function.
3795         (build_one): Adjust for XTheadVector.
3796         * config/riscv/riscv-vector-switch.def (ENTRY):
3797         Disable fractional mode for the XTheadVector extension.
3798         (TUPLE_ENTRY): Likewise.
3799         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
3800         Guard XTheadVector.
3801         (riscv_preferred_simd_mode): Likewsie.
3802         (riscv_autovectorize_vector_modes): Likewise.
3803         (riscv_vector_mode_supported_any_target_p): Likewise.
3804         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
3805         * config/riscv/thead.cc (th_asm_output_opcode):
3806         Rewrite vsetvl instructions.
3807         * config/riscv/vector.md:
3808         Include thead-vector.md and change fractional LMUL
3809         into 1 for vbool.
3810         * config/riscv/riscv_th_vector.h: New file.
3811         * config/riscv/thead-vector.md: New file.
3812
3813 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
3814             Jin Ma  <jinma@linux.alibaba.com>
3815             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
3816             Christoph Müllner  <christoph.muellner@vrull.eu>
3817
3818         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
3819         Add new function to add assembler insn code prefix/suffix.
3820         (th_asm_output_opcode):
3821         Add Thead function to add assembler insn code prefix/suffix.
3822         * config/riscv/riscv.cc (riscv_asm_output_opcode):
3823         Implement function to add assembler insn code prefix/suffix.
3824         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
3825         Add new function to add assembler insn code prefix/suffix.
3826         * config/riscv/thead.cc (th_asm_output_opcode):
3827         Implement Thead function to add assembler insn code
3828         prefix/suffix.
3829
3830 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
3831             Jin Ma  <jinma@linux.alibaba.com>
3832             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
3833             Christoph Müllner  <christoph.muellner@vrull.eu>
3834
3835         * common/config/riscv/riscv-common.cc
3836         (riscv_subset_list::parse): Add new vendor extension.
3837         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
3838         Add test marco.
3839         * config/riscv/riscv.opt:  Add new mask.
3840
3841 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
3842
3843         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
3844         to be conditional on macosx-version-min.
3845
3846 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
3847
3848         * config/darwin.cc (darwin_objc1_section): Use the correct
3849         meta-data version for constant strings.
3850         (machopic_select_section): Assert if we fail to handle CFString
3851         sections as Obejctive-C meta-data or drectly.
3852
3853 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
3854
3855         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
3856         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
3857         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
3858         versions when the object format is Mach-O.
3859
3860 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
3861
3862         PR target/105522
3863         * config/darwin.cc (machopic_select_section): Handle C and C++
3864         CFStrings.
3865         (darwin_rename_builtins): Move this out of the CFString code.
3866         (darwin_libc_has_function): Likewise.
3867         (darwin_build_constant_cfstring): Create an anonymous var to
3868         hold each CFString.
3869         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
3870         CFstrings.
3871
3872 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
3873
3874         PR bootstrap/113445
3875         * haifa-sched.cc (dep_list_size): Make global.
3876         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
3877         * sched-int.h (dep_list_size): Declare.
3878
3879 2024-01-18  Martin Jambor  <mjambor@suse.cz>
3880
3881         PR tree-optimization/110422
3882         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
3883         gotos.
3884
3885 2024-01-18  Richard Biener  <rguenther@suse.de>
3886
3887         PR tree-optimization/113475
3888         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
3889         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
3890         (phi_analyzer::~phi_analyzer): Deallocate and free collected
3891         phi_grous.
3892         (phi_analyzer::process_phi): Record allocated phi_groups.
3893
3894 2024-01-18  Richard Biener  <rguenther@suse.de>
3895
3896         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
3897         storage for gvec_oprnds elements.
3898
3899 2024-01-18  Richard Biener  <rguenther@suse.de>
3900
3901         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
3902         prefer all later exits we can handle.
3903         (vect_analyze_loop_form): Free the allocated loop body.
3904         Adjust comments.
3905
3906 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3907
3908         * config/avr/avr-log.cc: Tabify.
3909
3910 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3911
3912         * config/riscv/autovec.md: Support vi variant.
3913
3914 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3915
3916         * config/avr/avr-devices.cc: Tabify.
3917
3918 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3919
3920         * config/avr/avr-c.cc: Tabify.
3921
3922 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3923
3924         * config/avr/driver-avr.cc: Tabify.
3925
3926 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3927
3928         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
3929
3930 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3931
3932         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
3933
3934 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
3935
3936         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
3937         minline-strcmp, minline-strncmp, minline-strlen,
3938         -param=riscv-vector-abi): Remove Bool keywords.
3939
3940 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
3941
3942         PR target/113122
3943         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
3944         support.  Add missing space after , in emitted assembly in some
3945         cases.  Formatting fixes.
3946
3947 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
3948
3949         * config/loongarch/loongarch.md (movsi_internal): Remove
3950         constraint z.
3951
3952 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
3953
3954         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
3955         in the diagnostic, and capitalize the device name.
3956         (print_mcu): Generate specs such that:
3957         <*check_rodata_in_ram>: New.
3958         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
3959         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
3960         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
3961
3962 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
3963
3964         PR other/113399
3965         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
3966         Common and Optimization.
3967
3968 2024-01-18  Richard Biener  <rguenther@suse.de>
3969
3970         PR tree-optimization/113431
3971         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
3972         When there is an invariant load we might not preserve
3973         scalar order.
3974
3975 2024-01-18  Richard Biener  <rguenther@suse.de>
3976
3977         PR tree-optimization/113374
3978         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
3979         * tree-vect-loop.cc (move_early_exit_stmts): Update
3980         virtual LC PHIs.
3981         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3982         Refactor.  Preserve virtual LC PHIs on all exits.
3983
3984 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
3985
3986         * config/loongarch/loongarch.cc (loongarch_split_symbol):
3987         Assign the '/u' attribute to the mem.
3988
3989 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
3990
3991         PR middle-end/110847
3992         * doc/invoke.texi (Option Summary): Document negative forms of
3993         -Wtsan and -Wxor-used-as-pow.
3994         (Warning Options): Likewise.
3995
3996 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3997
3998         PR target/113429
3999         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
4000
4001 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
4002
4003         * doc/extend.texi (Common Function Attributes): Re-alphabetize
4004         the table.
4005         (Common Variable Attributes): Likewise.
4006         (Common Type Attributes): Likewise.
4007
4008 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
4009
4010         PR middle-end/111659
4011         * doc/extend.texi (Common Variable Attributes): Fix long lines
4012         in documentation of strict_flex_array + other minor copy-editing.
4013         Add a cross-reference to -Wstrict-flex-arrays.
4014         * doc/invoke.texi (Option Summary): Fix whitespace in tables
4015         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
4016         (C Dialect Options): Combine the docs for the two
4017         -fstrict-flex-arrays forms into a single entry.  Note this option
4018         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
4019         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
4020         Minor copy-editing.  Add cross references to the strict_flex_array
4021         attribute and -fstrict-flex-arrays option.  Add note that this
4022         option depends on -ftree-vrp.
4023
4024 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
4025
4026         PR target/113221
4027         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
4028         only allow REG operands instead of allowing all.
4029
4030 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
4031
4032         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
4033         Remove redundant checks in else condition for readablity.
4034         (earliest_fuse_vsetvl_info) Print iteration count in debug
4035         prints.
4036         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
4037         dump details in certain cases.
4038
4039 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
4040
4041         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
4042         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
4043         * config/riscv/riscv-vsetvl.cc
4044         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
4045         (pass_vsetvl::execute): Use vsetvl_strategy.
4046
4047 2024-01-17  Jan Hubicka  <jh@suse.cz>
4048
4049         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
4050         accidental hack reseting offset.
4051
4052 2024-01-17  Jan Hubicka  <jh@suse.cz>
4053
4054         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
4055         handling of X86_TUNE_AVOID_512FMA_CHAINS.
4056
4057 2024-01-17  Jan Hubicka  <jh@suse.cz>
4058             Jakub Jelinek  <jakub@redhat.com>
4059
4060         PR tree-optimization/110852
4061         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
4062         binary operations
4063         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
4064         PRED_COMBINED_VALUE_PREDICTIONS_PHI
4065         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
4066         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
4067
4068 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4069
4070         PR tree-optimization/113421
4071         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
4072         comment.
4073         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
4074         formatting.  Start at vop rather than cvop even if stmt is a store
4075         and needs_operand_addr.
4076
4077 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4078
4079         PR middle-end/113410
4080         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
4081         If access_nelts is integral with larger precision than sizetype,
4082         fold_convert it to sizetype.
4083
4084 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4085
4086         PR tree-optimization/113408
4087         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
4088         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
4089         to handle_cast.
4090
4091 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4092
4093         PR middle-end/113406
4094         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
4095         regardless of whether is_gimple_reg_type (restype) or not.
4096
4097 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4098
4099         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
4100         funcions -> functions, and use were instead of was.
4101         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
4102         and guaranteee -> guarantee.
4103         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
4104
4105 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4106
4107         PR middle-end/113409
4108         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
4109         INTEGER_TYPE.
4110         (omp_extract_for_data): Use build_bitint_type rather than
4111         build_nonstandard_integer_type if either iter_type or loop->v type
4112         is BITINT_TYPE.
4113         * omp-expand.cc (expand_omp_for_generic,
4114         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
4115         BITINT_TYPE like INTEGER_TYPE.
4116
4117 2024-01-17  Richard Biener  <rguenther@suse.de>
4118
4119         PR tree-optimization/113371
4120         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
4121         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4122         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
4123         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4124
4125 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
4126
4127         PR rtl-optimization/96388
4128         PR rtl-optimization/111554
4129         * sched-deps.cc (find_inc): Avoid exponential behavior.
4130
4131 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
4132
4133         PR c/111693
4134         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
4135         from C++ Language Options to Warning Options.  Add entry for
4136         -Wuse-after-free.
4137         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
4138         from here....
4139         (Warning Options): ...to here.  Minor copy-editing to fix typo
4140         and grammar.
4141
4142 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
4143
4144         * config/mips/mips.cc (mips_compute_frame_info): If another
4145         register is used as global_pointer, mark $GP live false.
4146
4147 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
4148
4149         PR target/112973
4150         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
4151         give the section a light copy-editing pass.
4152
4153 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
4154
4155         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
4156         * config/aarch64/aarch64-tune.md: Regenerated.
4157         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
4158
4159 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
4160
4161         PR target/112573
4162         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
4163         badly formed CONST expressions.
4164
4165 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
4166
4167         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
4168
4169 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
4170
4171         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
4172         * config/sparc/sync.md (membar_storeload): Turn into named insn
4173         and add GR712RC errata workaround.
4174         (membar_v8): Add GR712RC errata workaround.
4175
4176 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
4177
4178         * config/sparc/sync.md (*membar_storeload_leon3): Remove
4179         (*membar_storeload): Enable for LEON
4180
4181 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
4182
4183         PR tree-optimization/113372
4184         PR middle-end/90348
4185         PR middle-end/110115
4186         PR middle-end/111422
4187         * cfgexpand.cc (add_scope_conflicts_2): New function.
4188         (add_scope_conflicts_1): Use it.
4189
4190 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
4191
4192         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
4193         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
4194         * doc/avr-mmcu.texi: Regenerate.
4195
4196 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
4197
4198         PR tree-optimization/113091
4199         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
4200         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
4201         scalar use with new function.
4202         (vect_bb_slp_mark_live_stmts): New function as entry to existing
4203         overriden functions with same name.
4204         (vect_slp_analyze_operations): Call new entry function to mark
4205         live statements.
4206
4207 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4208
4209         PR target/113404
4210         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
4211         for RVV in big-endian mode.
4212
4213 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
4214
4215         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
4216         (riscv_pass_in_vector_p): Delete.
4217         (riscv_init_cumulative_args): Delete the checking.
4218         (riscv_get_arg_info): Delete the checking.
4219         (riscv_function_value): Delete the checking.
4220         * config/riscv/riscv.h: Delete the member for checking.
4221
4222 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
4223
4224         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
4225
4226 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
4227
4228         * config.gcc: Include riscv_bitmanip.h.
4229         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
4230         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
4231         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
4232         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
4233         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
4234         * config/riscv/riscv-ftypes.def (2): New ftypes.
4235         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
4236         (RISCV_BUILTIN_NO_PREFIX): Likewise.
4237         * config/riscv/riscv_bitmanip.h: New file.
4238
4239 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
4240
4241         * config.gcc: Include riscv_crypto.h.
4242         * config/riscv/riscv_crypto.h: New file.
4243
4244 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
4245
4246         PR middle-end/113354
4247         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
4248         in the insn if the corresponding operand does not require hard
4249         register anymore.
4250
4251 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
4252
4253         PR target/107201
4254         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
4255         * config/avr/driver-avr.cc (avr_no_devlib): New function.
4256         (avr_devicespecs_file): Use it to remove -nodevicelib from the
4257         options for cores only.
4258         * config/avr/avr-arch.h (avr_get_parch): New prototype.
4259         * config/avr/avr-devices.cc (avr_get_parch): New function.
4260
4261 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4262
4263         PR target/113247
4264         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
4265         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
4266         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
4267
4268 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4269
4270         PR target/113281
4271         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
4272         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
4273         * config/riscv/riscv-vector-costs.h: New function.
4274
4275 2024-01-15  Richard Biener  <rguenther@suse.de>
4276
4277         PR tree-optimization/113385
4278         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4279         First redirect, then split the exit edge.
4280
4281 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4282
4283         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
4284         Remove m_num_vector_iterations.
4285         * config/riscv/riscv-vector-costs.h: Ditto.
4286
4287 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
4288
4289         PR target/113156
4290         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
4291         (-mbranch-cost): Set "Optimization" flag.
4292
4293 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
4294
4295         PR tree-optimization/113370
4296         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
4297         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
4298         set it to just prec % limb_prec.
4299
4300 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4301
4302         PR target/113393
4303         * config/riscv/vector.md: Fix ternary attributes.
4304
4305 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
4306
4307         PR target/112944
4308         * configure.ac [target=avr]: Check availability of emulations
4309         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
4310         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
4311         * configure: Regenerate.
4312         * config.in: Regenerate.
4313         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
4314         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
4315         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
4316         * config/avr/avr-arch.h (enum avr_device_specific_features):
4317         Add AVR_ISA_FLMAP.
4318         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
4319         AVR_ISA_FLMAP.
4320         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
4321         (avr_set_core_architecture): Set avr_arch_index.
4322         (have_avrxmega2_flmap, have_avrxmega4_flmap)
4323         (have_avrxmega3_rodata_in_flash): Set new static const bool according
4324         to configure results.
4325         (avr_rodata_in_flash_p): New function using them.
4326         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
4327         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
4328         (avr_asm_named_section): Track avr_has_rodata_p.
4329         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
4330         and not avr_rodata_in_flash_p ().
4331         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
4332         (LINK_SPEC): Add %(link_rodata_in_ram).
4333         (LINK_ARCH_SPEC): Remove.
4334         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
4335         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
4336         const bool according to configure results.
4337         (diagnose_mrodata_in_ram): New function.
4338         (print_mcu): Generate specs with the following changes:
4339         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
4340         need to extend avr/specs.h each time we add a new bell or whistle.
4341         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
4342         -m[no-]rodata-in-ram.
4343         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
4344         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
4345         <*cpp>: Add %(cpp_rodata_in_ram).
4346         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
4347         requested.
4348         <*self_spec>: Add -mflmap or %<mflmap as needed.
4349
4350 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
4351
4352         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
4353         not the GPR iterator.  Adjust pattern name and mode attribute
4354         accordingly.
4355
4356 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
4357
4358         PR tree-optimization/113361
4359         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4360         Fix up determination of the type for > limb_prec constants.
4361
4362 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
4363
4364         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
4365         Add web-link to the avr-gcc wiki.
4366
4367 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
4368
4369         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
4370         documentation for a version without argument, which is not supported.
4371
4372 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4373
4374         * config/arm/arm_neon.h
4375         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
4376         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
4377         (vld1_f16_x4, vld1_f32_x4): New.
4378         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
4379         (vld1_bf16_x4): New.
4380         (vld1q_types_x4): Updated to use vld1q_x4
4381         from arm_neon_builtins.def
4382         * config/arm/arm_neon_builtins.def
4383         (vld1_x4): Updated entries.
4384         (vld1q_x4): New entries, but comes from the old vld1_x4
4385         * config/arm/neon.md
4386         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
4387
4388 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4389
4390         * config/arm/arm_neon.h
4391         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
4392         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
4393         (vld1_f16_x3, vld1_f32_x3): New.
4394         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
4395         (vld1_bf16_x3): New.
4396         (vld1q_types_x3): Updated to use vld1q_x3 from
4397         arm_neon_builtins.def
4398         * config/arm/arm_neon_builtins.def
4399         (vld1_x3): Updated entries.
4400         (vld1q_x3): New entries, but comes from the old vld1_x2
4401         * config/arm/neon.md
4402         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
4403
4404 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4405
4406         * config/arm/arm_neon.h
4407         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
4408         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
4409         (vld1_f16_x2, vld1_f32_x2): New.
4410         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
4411         (vld1_bf16_x2): New.
4412         (vld1q_types_x2): Updated to use vld1q_x2 from
4413         arm_neon_builtins.def
4414         * config/arm/arm_neon_builtins.def
4415         (vld1_x2): Updated entries.
4416         (vld1q_x2): New entries, but comes from the old vld1_x2
4417         * config/arm/neon.md
4418         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4419         neon_vld1_x2<mode>.
4420
4421 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4422
4423         * config/arm/arm_neon.h
4424         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
4425         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
4426         (vst1q_f16_x4, vst1q_f32_x4): New.
4427         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
4428         (vst1q_bf16_x4): New.
4429         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
4430         * config/arm/neon.md
4431         (neon_vst1q_x4<mode>): New.
4432         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
4433         * config/arm/unspecs.md
4434         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
4435
4436 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4437
4438         * config/arm/arm_neon.h
4439         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
4440         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
4441         (vst1q_f16_x3, vst1q_f32_x3): New.
4442         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
4443         (vst1q_bf16_x3): New.
4444         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
4445         * config/arm/neon.md
4446         (neon_vst1q_x3<mode>): New.
4447         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
4448         * config/arm/unspecs.md
4449         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
4450
4451 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4452
4453         * config/arm/arm_neon.h
4454         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
4455         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
4456         (vst1q_f16_x2, vst1q_f32_x2): New.
4457         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
4458         (vst1q_bf16_x2): New.
4459         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
4460         * config/arm/neon.md
4461         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4462         neon_vst1_x2<mode>.
4463         * config/arm/iterators.md
4464         (VMEMX2): New mode iterator.
4465         (VMEMX2_q): New mode attribute.
4466
4467 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4468
4469         * config/arm/arm_neon.h
4470         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
4471         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
4472         (vst1_f16_x4, vst1_f32_x4): New.
4473         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
4474         (vst1_bf16_x4): New.
4475         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
4476         * config/arm/neon.md (vst1_x4<mode>): New.
4477
4478 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4479
4480         * config/arm/arm_neon.h
4481         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
4482         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
4483         (vst1_f16_x3, vst1_f32_x3): New.
4484         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
4485         (vst1_bf16_x3): New.
4486         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
4487         * config/arm/neon.md (vst1_x3<mode>): New.
4488
4489 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4490
4491         * config/arm/arm_neon.h
4492         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
4493         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
4494         (vst1_f16_x2, vst1_f32_x2): New.
4495         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
4496         (vst1_bf16_x2): New.
4497         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
4498         * config/arm/neon.md (vst1_x2<mode>): New.
4499
4500 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4501
4502         * config/arm/arm_neon.h
4503         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
4504         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
4505         (vld1q_f16_x4, vld1q_f32_x4): New.
4506         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
4507         (vld1q_bf16_x4): New.
4508         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
4509         * config/arm/neon.md
4510         (neon_vld1_x4<mode>): New.
4511         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
4512         * config/arm/unspecs.md
4513         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
4514
4515 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4516
4517         * config/arm/arm_neon.h
4518         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
4519         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
4520         (vld1q_f16_x3, vld1q_f32_x3): New.
4521         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
4522         (vld1q_bf16_x3): New.
4523         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
4524         * config/arm/neon.md
4525         (neon_vld1_x3<mode>): New.
4526         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
4527         * config/arm/unspecs.md
4528         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
4529
4530 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4531
4532         * config/arm/arm_neon.h
4533         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
4534         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
4535         (vld1q_f16_x2, vld1q_f32_x2): New.
4536         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
4537         (vld1q_bf16_x2): New.
4538         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
4539         * config/arm/neon.md (vld1_x2<mode>): New.
4540
4541 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4542
4543         PR tree-optimization/113287
4544         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
4545
4546 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4547
4548         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
4549         * tree-vect-loop.cc (vect_transform_loop): Likewise.
4550
4551 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4552
4553         PR tree-optimization/113178
4554         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
4555         alternate exits.
4556
4557 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4558
4559         PR tree-optimization/113237
4560         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
4561         existing LCSSA variable for exit when all exits are early break.
4562
4563 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4564
4565         PR tree-optimization/113137
4566         PR tree-optimization/113136
4567         PR tree-optimization/113172
4568         PR tree-optimization/113178
4569         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4570         Maintain PHIs on inverted loops.
4571         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4572         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4573         latch.
4574         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4575
4576 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4577
4578         PR tree-optimization/113135
4579         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4580         dependency analysis.
4581
4582 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
4583
4584         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4585         diagnostics class member name for abort of error.
4586
4587 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
4588
4589         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4590         format string to %s argument.
4591
4592 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
4593             Jakub Jelinek  <jakub@redhat.com>
4594
4595         PR middle-end/113182
4596         * varasm.cc (process_pending_assemble_externals,
4597         assemble_external_libcall): Use targetm.strip_name_encoding
4598         before calling get_identifier.
4599
4600 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
4601
4602         PR target/113196
4603         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4604         New member variable.
4605         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4606         Declare.
4607         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
4608         * config/aarch64/aarch64-simd.md
4609         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
4610         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
4611         zip2 for zero-extends to...
4612         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
4613         instruction.  Fix big-endian handling.
4614         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
4615         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
4616         zip1 for zero-extends to...
4617         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
4618         Fix big-endian handling.
4619         (*aarch64_zip1_uxtl): New pattern.
4620         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
4621         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
4622         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
4623         (aarch64_gen_shareable_zero): Use it.
4624         (aarch64_split_simd_shift_p): New function.
4625
4626 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
4627
4628         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
4629         (function_beg_insn): New macro.
4630         * function.cc (expand_function_start): Initialize function_beg_insn.
4631
4632 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
4633
4634         PR target/112989
4635         * config/aarch64/aarch64-sve-builtins.h
4636         (function_builder::m_overload_names): Replace with...
4637         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
4638         new global.
4639         (add_overloaded_function): Update accordingly, using get_identifier
4640         to get a GGC-friendly record of the name.
4641
4642 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
4643
4644         PR target/112989
4645         * config/aarch64/aarch64-sve-builtins.def: Don't include
4646         aarch64-sve-builtins-sme.def.
4647         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
4648         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
4649         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
4650         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
4651         requires AARCH64_FL_SME2.
4652         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
4653         AARCH64_FL_SME adjustment here.
4654         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
4655         include SME intrinsics.
4656         (sme_function_groups): New array.
4657         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
4658         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
4659
4660 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4661
4662         PR target/113281
4663         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
4664         (struct cpu_vector_cost): Add regmove struct.
4665         (get_vector_costs): Export as global.
4666         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
4667         (costs::add_stmt_cost): Ditto.
4668         * config/riscv/riscv.cc (get_common_costs): Export global function.
4669
4670 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
4671
4672         PR tree-optimization/113334
4673         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
4674         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
4675         to determine if number should be extended by all ones rather than zero
4676         extended.
4677
4678 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
4679
4680         PR tree-optimization/113330
4681         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
4682         too large size.
4683
4684 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
4685
4686         PR tree-optimization/113323
4687         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
4688         check for lhs being large/huge _BitInt not in m_names.
4689
4690 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
4691
4692         PR tree-optimization/113316
4693         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
4694         uninitialized large/huge _BitInt arguments to calls.
4695
4696 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
4697
4698         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
4699         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
4700         CEIL (TYPE_PRECISION (t), limb_prec).
4701         (bitint_large_huge::handle_cast): Likewise.
4702
4703 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
4704
4705         PR sanitizer/113284
4706         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4707         Use assemble_function_label_final () for Power ELF V1 ABI.
4708         * output.h (assemble_function_label_final): New function.
4709         * varasm.cc (assemble_function_label_raw): Use
4710         assemble_function_label_final ().
4711         (assemble_function_label_final): New function.
4712
4713 2024-01-12  Richard Biener  <rguenther@suse.de>
4714
4715         PR middle-end/113344
4716         * match.pd ((double)float CMP (double)float -> float CMP float):
4717         Perform result type check only for vectors.
4718         * fold-const.cc (fold_binary_loc): Likewise.
4719
4720 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
4721
4722         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
4723         (usdot_prod<mode>): Ditto.
4724         (sdot_prod<mode>): Ditto.
4725         (udot_prod<mode>): Ditto.
4726
4727 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
4728
4729         PR target/113288
4730         * config/i386/i386-c.cc (ix86_target_macros_internal):
4731         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
4732
4733 2024-01-12  Richard Biener  <rguenther@suse.de>
4734
4735         PR target/112280
4736         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
4737         Do not generate code when d.testing_p.
4738
4739 2024-01-12  liuhongt  <hongtao.liu@intel.com>
4740
4741         PR target/113039
4742         * doc/invoke.texi (fcf-protection=): Update documents.
4743
4744 2024-01-12  Pan Li  <pan2.li@intel.com>
4745
4746         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
4747         comments of predicate func riscv_v_ext_mode_p.
4748
4749 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
4750
4751         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
4752                         Modify ABI-name length of vfloat16m8_t
4753
4754 2024-01-12  Li Wei  <liwei@loongson.cn>
4755
4756         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
4757         Adjust.
4758
4759 2024-01-12  Li Wei  <liwei@loongson.cn>
4760
4761         * config/loongarch/loongarch.md (add<mode>3): Removed.
4762         (*addsi3): New.
4763         (addsi3): Ditto.
4764         (adddi3): Ditto.
4765         (*addsi3_extended): Removed.
4766         (addsi3_extended): New.
4767
4768 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
4769
4770         * config/riscv/thead.md: Add limits for splits.
4771
4772 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
4773
4774         PR middle-end/113322
4775         * expr.cc (do_store_flag): Don't try single bit tests with
4776         comparison on vector types.
4777
4778 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
4779
4780         PR tree-optimization/113301
4781         * match.pd (`1/x`): Delay signed case until late.
4782
4783 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
4784
4785         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
4786         and -msp8 to...
4787         (AVR Internal Options): ...this new @subsubsection.
4788
4789 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
4790
4791         PR rtl-optimization/112918
4792         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
4793         (in_class_p): Restrict condition for narrowing class in case of
4794         allow_all_reload_class_changes_p.
4795         (process_alt_operands): Try to match operand without and with
4796         narrowing reg class.  Discourage narrowing the class.  Finish insn
4797         matching only if there is no class narrowing.
4798         (curr_insn_transform): Pass true to in_class_p for reg operand win.
4799
4800 2024-01-11  Richard Biener  <rguenther@suse.de>
4801
4802         PR tree-optimization/112505
4803         * tree-vect-loop.cc (vectorizable_induction): Reject
4804         bit-precision induction.
4805
4806 2024-01-11  Richard Biener  <rguenther@suse.de>
4807
4808         PR tree-optimization/113126
4809         * match.pd ((double)float CMP (double)float -> float CMP float):
4810         Make sure the boolean type is the same.
4811         * fold-const.cc (fold_binary_loc): Likewise.
4812
4813 2024-01-11  Richard Biener  <rguenther@suse.de>
4814
4815         PR tree-optimization/112636
4816         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
4817         estimate_numbers_of_iterations before querying
4818         get_max_loop_iterations_int.
4819         (pass_ch::execute): Initialize SCEV and loops appropriately.
4820
4821 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
4822
4823         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
4824         Reduced Tiny.
4825         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
4826         * doc/extend.texi (AVR Variable Attributes): Improve documentation
4827         of io, io_low and address attributes.
4828         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
4829         * doc/avr-mmcu.texi: Rebuild.
4830
4831 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
4832
4833         PR target/113233
4834         * config/loongarch/genopts/loongarch.opt.in: Mark options with
4835         the "Save" property.
4836         * config/loongarch/loongarch.opt: Same.
4837         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
4838         according to la_target.
4839         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
4840         RESTORE} for the la_target structure; Rename option conditions
4841         to have the same "la_" prefix.
4842         * config/loongarch/loongarch.h: Same.
4843
4844 2024-01-11  Pan Li  <pan2.li@intel.com>
4845
4846         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
4847         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
4848
4849 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
4850
4851         PR target/113077
4852         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
4853         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
4854         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
4855         synthesize these if needed.  Update caller ...
4856         (ldp_bb_info::fuse_pair): ... here.
4857         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
4858         and either insn is frame-related.
4859         (find_trailing_add): Punt on frame-related insns.
4860         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
4861         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
4862
4863 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
4864
4865         * config/mips/mips.cc (mips_start_function_definition):
4866         Add ATTRIBUTE_UNUSED.
4867
4868 2024-01-11  Richard Biener  <rguenther@suse.de>
4869
4870         PR middle-end/112740
4871         * expr.cc (store_constructor): Check the integer vector
4872         mask has a single bit per element before using sign-extension
4873         to expand an uniform vector.
4874
4875 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4876
4877         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
4878         preempt VLS on unknown NITERS loop.
4879
4880 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
4881
4882         * doc/invoke.texi: Add -mevex512.
4883
4884 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
4885
4886         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
4887         (*nor<mode>3): Likewise.
4888         (nor<mode>3): Likewise.
4889         (*negsi2_extended): New template.
4890         (*<optab>si3_internal): Likewise.
4891         (*one_cmplsi2_internal): Likewise.
4892         (*norsi3_internal): Likewise.
4893         (*<optab>nsi_internal): Likewise.
4894         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
4895         modified bit operation to make the optimization work.
4896
4897 2024-01-11  liuhongt  <hongtao.liu@intel.com>
4898
4899         PR target/104401
4900         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
4901
4902 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4903
4904         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
4905         (get_vector_costs): Ditto.
4906         (riscv_builtin_vectorization_cost): Ditto.
4907
4908 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4909
4910         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
4911
4912 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
4913
4914         PR jit/111396
4915         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
4916         ipa_free_size_summary.
4917         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
4918         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
4919         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
4920         * ipa-prop.h (ipa_prop_cc_finalize): New function.
4921         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
4922         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
4923         ipa_sra_cc_finalize): New functions.
4924         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
4925         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
4926         ipa_sra_cc_finalize
4927         Include ipa-utils.h.
4928
4929 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
4930
4931         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
4932         (th_int_get_save_adjustment): Likewise.
4933         (th_int_adjust_cfi_prologue): Likewise.
4934         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
4935         (TH_INT_INTERRUPT): New macro.
4936         (riscv_expand_prologue): Add the processing of XTheadInt.
4937         (riscv_expand_epilogue): Likewise.
4938         * config/riscv/riscv.h (BITSET_P): Moved to here.
4939         * config/riscv/riscv.md: New unspec.
4940         * config/riscv/thead.cc (th_int_get_mask): New function.
4941         (th_int_get_save_adjustment): Likewise.
4942         (th_int_adjust_cfi_prologue): Likewise.
4943         * config/riscv/thead.md (th_int_push): New pattern.
4944         (th_int_pop): new pattern.
4945
4946 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
4947
4948         PR tree-optimization/112468
4949         * doc/sourcebuild.texi: Document ifn_copysign.
4950         * match.pd: Only apply transformation if target supports the IFN.
4951
4952 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
4953
4954         PR tree-optimization/112581
4955         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
4956         mark_ssa_maybe_undefs.
4957         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
4958         variables can not be reassociated.
4959         (init_range_entry): Check for uninitialized variables too.
4960         (init_reassoc): Call mark_ssa_maybe_undefs.
4961
4962 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
4963
4964         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
4965         Also handle sign extension.
4966
4967 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
4968
4969         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4970         to 0.
4971         (-mlate-ldp-fusion): Likewise.
4972
4973 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
4974
4975         PR tree-optimization/113287
4976         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
4977         instead of using BRANCH_EDGE to determine true edge.
4978
4979 2024-01-10  Richard Biener  <rguenther@suse.de>
4980
4981         PR tree-optimization/113078
4982         * tree-vect-loop.cc (check_reduction_path): Canonicalize
4983         .COND_SUB to .COND_ADD.
4984
4985 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
4986
4987         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
4988         Handle prefix mappings before calling find_opt.
4989         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
4990         "-fno-"-prefixed command-line option.
4991         * opts-common.cc (get_option_prefix_remapping): New.
4992         * opts.h (get_option_prefix_remapping): New decl.
4993
4994 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
4995
4996         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
4997         m_urlifier to pp_output_formatted_text.
4998         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
4999         (obstack_append_string): New overload, taking a length.
5000         (urlify_quoted_string): Pass in an obstack ptr, rather than using
5001         that of the pp's buffer.  Generalize to handle trailing text in
5002         the buffer beyond the run of quoted text.
5003         (class quoting_info): New.
5004         (on_begin_quote): New.
5005         (on_end_quote): New.
5006         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
5007         it to calls to on_begin_quote and on_end_quote.
5008         (struct auto_obstack): New.
5009         (quoting_info::handle_phase_3): New.
5010         (pp_output_formatted_text): Add urlifier param.  Use it if there
5011         is deferred urlification.  Delete m_quotes.
5012         (selftest::pp_printf_with_urlifier): Pass urlifier to
5013         pp_output_formatted_text.
5014         (selftest::test_urlification): Update results for the existing
5015         case of quoted text stradding chunks; add more such test cases.
5016         * pretty-print.h (class quoting_info): New forward decl.
5017         (chunk_info::m_quotes): New field.
5018         (pp_output_formatted_text): Add optional urlifier param.
5019
5020 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
5021
5022         * pretty-print.cc (selftest::test_pp_format): Add selftest
5023         coverage for numbered args.
5024
5025 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
5026
5027         PR tree-optimization/113144
5028         PR tree-optimization/113145
5029         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5030         Update all BB that the original exits dominated.
5031
5032 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
5033
5034         * dwarf2out.cc (modified_type_die): Extend the support of reverse
5035         storage order to enumeration types if -gstrict-dwarf is not passed.
5036         (gen_enumeration_type_die): Add REVERSE parameter and generate the
5037         DIE immediately after the existing one if it is true.
5038         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
5039         call to gen_enumeration_type_die.
5040         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
5041         first recursive call as well as the call to gen_tagged_type_die.
5042         (gen_type_die): Add REVERSE parameter and pass it in the call to
5043         gen_type_die_with_usage.
5044
5045 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
5046
5047         PR tree-optimization/113120
5048         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
5049         with root->size TYPE_PRECISION don't build anything new.
5050         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
5051         rather than build_nonstandard_integer_type.
5052
5053 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
5054
5055         * config/i386/i386.opt: Adjust document.
5056         * doc/invoke.texi: Add description for
5057         -mapx-inline-asm-use-gpr32.
5058
5059 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5060
5061         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
5062         (avg<v_double_trunc>3_floor): New pattern.
5063         (<u>avg<v_double_trunc>3_ceil): Remove.
5064         (avg<v_double_trunc>3_ceil): New pattern.
5065         (uavg<mode>3_floor): Ditto.
5066         (uavg<mode>3_ceil): Ditto.
5067         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
5068         (enum insn_type): Ditto.
5069         * config/riscv/riscv-v.cc: Ditto.
5070         * config/riscv/vector-iterators.md (ashiftrt): Remove.
5071         (ASHIFTRT): Ditto.
5072         * config/riscv/vector.md: Add VLS modes.
5073
5074 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
5075
5076         PR target/111480
5077         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
5078         (vczlsbb_char): New int attribute.
5079         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
5080         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
5081         (*vctzlsbb_zext_<mode>): Rename to ...
5082         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
5083         cover vclzlsbb.
5084
5085 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
5086
5087         PR target/112606
5088         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
5089         of the last argument from altivec_register_operand to any_operand.  If
5090         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
5091         otherwise if it doesn't satisfy altivec_register_operand, force it to
5092         REG using copy_to_mode_reg.
5093
5094 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
5095
5096         PR middle-end/113100
5097         * builtins.cc (expand_builtin_stack_address): Guard stack point
5098         adjustment with SPARC_STACK_BOUNDARY_HACK.
5099
5100 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5101
5102         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
5103         argument string definitions.
5104         * config/loongarch/loongarch-str.h: Same.
5105         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
5106         as aliases to -mexplicit-relocs={always,none}
5107         * config/loongarch/loongarch.opt: Regenerate.
5108         * config/loongarch/loongarch.cc: Same.
5109
5110 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5111
5112         * config/loongarch/loongarch-def.h: Define constants with
5113         enums instead of Macros.
5114
5115 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5116
5117         * config/loongarch/genopts/loongarch-strings: Rename.
5118         * config/loongarch/genopts/loongarch.opt.in: Same.
5119         * config/loongarch/loongarch-cpu.cc: Same.
5120         * config/loongarch/loongarch-def.cc: Same.
5121         * config/loongarch/loongarch-def.h: Same.
5122         * config/loongarch/loongarch-opts.cc: Same.
5123         * config/loongarch/loongarch-opts.h: Same.
5124         * config/loongarch/loongarch-str.h: Same.
5125         * config/loongarch/loongarch.opt: Same.
5126
5127 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5128
5129         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
5130         variable with the common la_ prefix.
5131         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
5132         flags as saved using TargetVariable.
5133         * config/loongarch/loongarch.opt: Same.
5134         * config/loongarch/loongarch-def.h: Define evolution_set to
5135         mark changes to the -march default.
5136         * config/loongarch/loongarch-driver.cc: Same.
5137         * config/loongarch/loongarch-opts.cc: Same.
5138         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
5139         conditions around the la_target structure.
5140         * config/loongarch/loongarch.cc: Same.
5141         * config/loongarch/loongarch.md: Same.
5142         * config/loongarch/loongarch-builtins.cc: Same.
5143         * config/loongarch/loongarch-c.cc: Same.
5144         * config/loongarch/lasx.md: Same.
5145         * config/loongarch/lsx.md: Same.
5146         * config/loongarch/sync.md: Same.
5147
5148 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
5149
5150         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
5151         no less.
5152
5153 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
5154
5155         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
5156
5157 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
5158
5159         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
5160         restart_loop.
5161         (vectorizable_live_operation): Likewise.
5162
5163 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
5164
5165         PR tree-optimization/113199
5166         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
5167         BIT_FIELD_REF.
5168
5169 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
5170
5171         PR target/113270
5172         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
5173         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
5174         GTY(()) declaration before the definition, drop GTY(()) drom the
5175         definition.
5176
5177 2024-01-09  Richard Biener  <rguenther@suse.de>
5178
5179         PR tree-optimization/113026
5180         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
5181         redundant and wrong niter bound setting.  Move niter
5182         bound adjustment down.
5183
5184 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
5185
5186         PR middle-end/113163
5187         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
5188         Reject non-linear inductions that aren't supported.
5189
5190 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
5191
5192         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
5193         left shift implementation strategies.
5194         (arc_shift_info): Type for each entry of the shift strategy table.
5195         (arc_shift_context_idx): Return a integer value for each code
5196         generation context, used as an index
5197         (arc_ashl_alg): Table indexed by context and shifted bit count.
5198         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
5199         left shift implementation.
5200         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
5201         provide accurate costs, when optimizing for speed or size.
5202
5203 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5204
5205         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
5206
5207 2024-01-09  Julian Brown  <julian@codesourcery.com>
5208
5209         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
5210         processed out before gimplification.
5211         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
5212         * tree.def (OMP_ARRAY_SECTION): New tree code.
5213
5214 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
5215
5216         PR tree-optimization/113210
5217         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
5218         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
5219         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
5220         minus 1.
5221
5222 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
5223
5224         PR rtl-optimization/113140
5225         * reorg.cc (fill_slots_from_thread): If we are to branch after the
5226         last instruction of the function, create an end label.
5227
5228 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
5229             Hongtao Liu  <hongtao.liu@intel.com>
5230
5231         PR target/112992
5232         * config/i386/i386-expand.cc
5233         (ix86_convert_const_wide_int_to_broadcast): Allow call to
5234         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
5235         (ix86_broadcast_from_constant): Revert recent change; Return a
5236         suitable MEMREF independently of mode/target combinations.
5237         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
5238         to decide whether expansion is possible/preferrable.  Only try
5239         forcing DImode constants to memory (and trying again) if calling
5240         ix86_expand_vector_init_duplicate fails with an DImode immediate
5241         constant.
5242         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
5243         V4SImode for suitable immediate constants.
5244         <case E_V4DImode>: Try using V8SImode for suitable constants.
5245         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
5246         <case E_V2HImode>: Likewise.
5247         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
5248         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
5249         <label widen>: Handle CONT_INTs via simplify_binary_operation.
5250         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
5251         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
5252         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
5253         (ix86_expand_vector_init): Move try using a broadcast for all_same
5254         with ix86_expand_vector_init_duplicate before using constant pool.
5255
5256 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
5257
5258         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
5259
5260 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
5261
5262         * config/arm/arm-cpus.in (cortex-m52): New cpu.
5263         * config/arm/arm-tables.opt: Regenerate.
5264         * config/arm/arm-tune.md: Regenerate.
5265
5266 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
5267
5268         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
5269         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
5270         (@vec_concatz<mode>): New insn pattern.
5271         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
5272         Handle VALS containing two vectors.
5273
5274 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5275
5276         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
5277         (vundefined): Ditto.
5278
5279 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
5280
5281         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5282                                 Add new function_base for crypto vector.
5283         (class bitmanip): Ditto.
5284         (class b_reverse):Ditto.
5285         (class vwsll):   Ditto.
5286         (class clmul):   Ditto.
5287         (class vg_nhab):  Ditto.
5288         (class crypto_vv):Ditto.
5289         (class crypto_vi):Ditto.
5290         (class vaeskf2_vsm3c):Ditto.
5291         (class vsm3me): Ditto.
5292         (BASE): Add BASE declaration for crypto vector.
5293         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5294         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5295                                 Add crypto vector intrinsic definition.
5296         (vbrev): Ditto.
5297         (vclz): Ditto.
5298         (vctz): Ditto.
5299         (vwsll): Ditto.
5300         (vandn): Ditto.
5301         (vbrev8): Ditto.
5302         (vrev8): Ditto.
5303         (vrol): Ditto.
5304         (vror): Ditto.
5305         (vclmul): Ditto.
5306         (vclmulh): Ditto.
5307         (vghsh): Ditto.
5308         (vgmul): Ditto.
5309         (vaesef): Ditto.
5310         (vaesem): Ditto.
5311         (vaesdf): Ditto.
5312         (vaesdm): Ditto.
5313         (vaesz): Ditto.
5314         (vaeskf1): Ditto.
5315         (vaeskf2): Ditto.
5316         (vsha2ms): Ditto.
5317         (vsha2ch): Ditto.
5318         (vsha2cl): Ditto.
5319         (vsm4k): Ditto.
5320         (vsm4r): Ditto.
5321         (vsm3me): Ditto.
5322         (vsm3c): Ditto.
5323         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5324                                 Add new function_shape for crypto vector.
5325         (struct crypto_vi_def): Ditto.
5326         (struct crypto_vv_no_op_type_def): Ditto.
5327         (SHAPE): Add SHAPE declaration of crypto vector.
5328         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5329         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5330                                 Add new data type for crypto vector.
5331         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5332         (vuint32mf2_t): Ditto.
5333         (vuint32m1_t): Ditto.
5334         (vuint32m2_t): Ditto.
5335         (vuint32m4_t): Ditto.
5336         (vuint32m8_t): Ditto.
5337         (vuint64m1_t): Ditto.
5338         (vuint64m2_t): Ditto.
5339         (vuint64m4_t): Ditto.
5340         (vuint64m8_t): Ditto.
5341         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5342                                 Add new data struct for crypto vector.
5343         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5344         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5345         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5346
5347 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
5348
5349         PR sanitizer/113251
5350         * varasm.cc (assemble_function_label_raw): Do not call
5351         asan_function_start () without the current function.
5352
5353 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
5354
5355         PR target/113225
5356         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
5357         extern and kernel_helper attributed function decls.
5358
5359 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
5360
5361         * btfout.cc (output_btf_strs): Changed.
5362
5363 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
5364
5365         * config/gcn/mkoffload.cc (main): Handle gfx1100
5366         when setting the default XNACK.
5367
5368 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
5369
5370         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
5371         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
5372         (ASM_SPEC): Handle gfx1100.
5373         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
5374         (enum gcn_isa): Add ISA_RDNA3.
5375         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
5376         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5377         * config/gcn/gcn.cc (gcn_option_override,
5378         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
5379         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
5380         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5381         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
5382         with gfx1100.
5383         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
5384         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
5385         __gfx1100__.
5386         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5387         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
5388         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
5389         (isa_has_combined_avgprs, main): Handle gfx1100.
5390         * config/gcn/t-omp-device (isa): Add gfx1100.
5391
5392 2024-01-08  Richard Biener  <rguenther@suse.de>
5393
5394         * doc/invoke.texi (-mmovbe): Clarify.
5395
5396 2024-01-08  Richard Biener  <rguenther@suse.de>
5397
5398         PR tree-optimization/113026
5399         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
5400         Avoid an epilog in more cases.
5401         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
5402         epilogues niter upper bounds and estimates.
5403
5404 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
5405
5406         PR tree-optimization/113228
5407         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
5408
5409 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
5410
5411         PR tree-optimization/113120
5412         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
5413         large _BitInt zero INTEGER_CST PHI argument.
5414
5415 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
5416
5417         PR tree-optimization/113119
5418         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
5419         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
5420         is before REALPART_EXPR.
5421
5422 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
5423
5424         PR target/112952
5425         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
5426         range when diagnosing attribute "io" and "io_low" are out of range.
5427         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
5428         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
5429         in contexts other than static storage.
5430         (avr_asm_output_aligned_decl_common): Move output of decls with
5431         attribute "address", "io", and "io_low" to...
5432         (avr_output_addr_attrib): ...this new function.
5433         (avr_asm_asm_output_aligned_bss): Remove output for decls with
5434         attribute "address", "io", and "io_low".
5435         (avr_encode_section_info): Rectify handling of decls with attribute
5436         "address", "io", and "io_low".
5437
5438 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
5439
5440         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
5441         (elf_flags): Remove XNACK from the default value.
5442         (main): Set a default XNACK according to the arch.
5443
5444 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
5445
5446         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
5447         (process_asm): Don't count avgprs.
5448
5449 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
5450
5451         * config/i386/i386.opt: Add supported sub-features.
5452         * doc/extend.texi: Add description for target attribute.
5453
5454 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
5455
5456         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
5457
5458 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
5459             Uros Bizjak  <ubizjak@gmail.com>
5460
5461         PR target/113231
5462         * config/i386/i386-features.cc (compute_convert_gain): Include
5463         the overhead of explicit load and store (movd) instructions when
5464         converting non-store scalar operations with memory destinations.
5465         Various indentation whitespace fixes.
5466
5467 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
5468
5469         * config/arm/neon.md (cbranch<mode>4): New.
5470
5471 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5472
5473         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
5474
5475 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
5476
5477         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
5478
5479 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5480
5481         PR target/113248
5482         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
5483         Update the MAX_SEW.
5484
5485 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5486
5487         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
5488         (variable_vectorized_p): Teach loop invariant.
5489         (has_unexpected_spills_p): Ditto.
5490
5491 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5492
5493         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
5494         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
5495         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
5496
5497 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
5498
5499         PR target/113104
5500         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
5501         (aarch64-vect-compare-costs): ...this.
5502         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
5503         Replace with...
5504         (-param=aarch64-vect-compare-costs=): ...this new param.
5505         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
5506         Don't disable it when vectorizing for Advanced SIMD only.
5507         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
5508         whenever aarch64_vect_compare_costs is true.
5509
5510 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
5511
5512         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
5513         Modify the method of determining the memory offset of [x]vld/[x]vst.
5514         (lasx_mxst_<lasxfmt_f>): Likewise.
5515         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
5516         (loongarch_address_insns): Likewise.
5517         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
5518         (lsx_st_<lsxfmt_f>): Likewise.
5519         * config/loongarch/predicates.md (aq10b_operand): Likewise.
5520         (aq10h_operand): Likewise.
5521         (aq10w_operand): Likewise.
5522         (aq10d_operand): Likewise.
5523
5524 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
5525
5526         PR target/113217
5527         * config/aarch64/aarch64-ldp-fusion.cc
5528         (ldp_bb_info::try_fuse_pair): If the second access can throw,
5529         narrow the move range to exactly that insn.
5530
5531 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
5532
5533         * asan.cc (asan_function_start): Drop switch_to_section ().
5534         (asan_emit_stack_protection): Set .LASANPC alignment.
5535         * config/i386/i386.cc: Use assemble_function_label_raw ()
5536         instead of ASM_OUTPUT_LABEL ().
5537         * config/s390/s390.cc (s390_asm_output_function_label):
5538         Likewise.
5539         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
5540         * final.cc (final_start_function_1): Drop
5541         asan_function_start ().
5542         * output.h (assemble_function_label_raw): New function.
5543         * varasm.cc (assemble_function_label_raw): Likewise.
5544
5545 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
5546
5547         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
5548         Use ASM_OUTPUT_FUNCTION_LABEL ().
5549         * config/alpha/alpha.cc (alpha_start_function): Likewise.
5550         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5551         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
5552         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5553         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5554         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
5555         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5556         * config/ia64/ia64.cc (ia64_start_function): Likewise.
5557         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
5558         Likewise.
5559         * config/microblaze/microblaze.cc (microblaze_function_prologue):
5560         Likewise.
5561         * config/mips/mips.cc (mips_start_unique_function): Return the
5562         tree.
5563         (mips_start_function_definition): Use
5564         ASM_OUTPUT_FUNCTION_LABEL ().
5565         (mips_finish_stub): Pass the tree to
5566         mips_start_function_definition ().
5567         (mips16_build_function_stub): Likewise.
5568         (mips16_build_call_stub): Likewise.
5569         (mips_output_function_prologue): Likewise.
5570         * config/pa/pa.cc (pa_output_function_label): Use
5571         ASM_OUTPUT_FUNCTION_LABEL ().
5572         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5573         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5574         Likewise.
5575         (rs6000_xcoff_declare_function_name): Likewise.
5576
5577 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
5578
5579         PR tree-optimization/113201
5580         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5581         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5582
5583 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
5584
5585         PR tree-optimization/90693
5586         * tree-ssa-math-opts.cc (match_single_bit_test): If
5587         tree_expr_nonzero_p (arg), remember it in the second argument to
5588         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5589         arg ^ (arg - 1) > arg - 1.
5590         * internal-fn.cc (expand_POPCOUNT): If second argument to
5591         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5592         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5593
5594 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
5595
5596         * config/riscv/riscv-v.cc (expand_load_store):
5597         Remove `value`.
5598         (expand_cond_len_op): Ditto.
5599         (expand_gather_scatter): Ditto.
5600         (expand_lanes_load_store): Ditto.
5601         (expand_fold_extract_last): Ditto.
5602
5603 2024-01-05  Pan Li  <pan2.li@intel.com>
5604
5605         Revert:
5606         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
5607
5608         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5609                                 Add new function_base for crypto vector.
5610         (class bitmanip): Ditto.
5611         (class b_reverse):Ditto.
5612         (class vwsll):   Ditto.
5613         (class clmul):   Ditto.
5614         (class vg_nhab):  Ditto.
5615         (class crypto_vv):Ditto.
5616         (class crypto_vi):Ditto.
5617         (class vaeskf2_vsm3c):Ditto.
5618         (class vsm3me): Ditto.
5619         (BASE): Add BASE declaration for crypto vector.
5620         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5621         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5622                                 Add crypto vector intrinsic definition.
5623         (vbrev): Ditto.
5624         (vclz): Ditto.
5625         (vctz): Ditto.
5626         (vwsll): Ditto.
5627         (vandn): Ditto.
5628         (vbrev8): Ditto.
5629         (vrev8): Ditto.
5630         (vrol): Ditto.
5631         (vror): Ditto.
5632         (vclmul): Ditto.
5633         (vclmulh): Ditto.
5634         (vghsh): Ditto.
5635         (vgmul): Ditto.
5636         (vaesef): Ditto.
5637         (vaesem): Ditto.
5638         (vaesdf): Ditto.
5639         (vaesdm): Ditto.
5640         (vaesz): Ditto.
5641         (vaeskf1): Ditto.
5642         (vaeskf2): Ditto.
5643         (vsha2ms): Ditto.
5644         (vsha2ch): Ditto.
5645         (vsha2cl): Ditto.
5646         (vsm4k): Ditto.
5647         (vsm4r): Ditto.
5648         (vsm3me): Ditto.
5649         (vsm3c): Ditto.
5650         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5651                                 Add new function_shape for crypto vector.
5652         (struct crypto_vi_def): Ditto.
5653         (struct crypto_vv_no_op_type_def): Ditto.
5654         (SHAPE): Add SHAPE declaration of crypto vector.
5655         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5656         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5657                                 Add new data type for crypto vector.
5658         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5659         (vuint32mf2_t): Ditto.
5660         (vuint32m1_t): Ditto.
5661         (vuint32m2_t): Ditto.
5662         (vuint32m4_t): Ditto.
5663         (vuint32m8_t): Ditto.
5664         (vuint64m1_t): Ditto.
5665         (vuint64m2_t): Ditto.
5666         (vuint64m4_t): Ditto.
5667         (vuint64m8_t): Ditto.
5668         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5669                                 Add new data struct for crypto vector.
5670         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5671         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5672         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5673
5674 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
5675
5676         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5677                                 Add new function_base for crypto vector.
5678         (class bitmanip): Ditto.
5679         (class b_reverse):Ditto.
5680         (class vwsll):   Ditto.
5681         (class clmul):   Ditto.
5682         (class vg_nhab):  Ditto.
5683         (class crypto_vv):Ditto.
5684         (class crypto_vi):Ditto.
5685         (class vaeskf2_vsm3c):Ditto.
5686         (class vsm3me): Ditto.
5687         (BASE): Add BASE declaration for crypto vector.
5688         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5689         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5690                                 Add crypto vector intrinsic definition.
5691         (vbrev): Ditto.
5692         (vclz): Ditto.
5693         (vctz): Ditto.
5694         (vwsll): Ditto.
5695         (vandn): Ditto.
5696         (vbrev8): Ditto.
5697         (vrev8): Ditto.
5698         (vrol): Ditto.
5699         (vror): Ditto.
5700         (vclmul): Ditto.
5701         (vclmulh): Ditto.
5702         (vghsh): Ditto.
5703         (vgmul): Ditto.
5704         (vaesef): Ditto.
5705         (vaesem): Ditto.
5706         (vaesdf): Ditto.
5707         (vaesdm): Ditto.
5708         (vaesz): Ditto.
5709         (vaeskf1): Ditto.
5710         (vaeskf2): Ditto.
5711         (vsha2ms): Ditto.
5712         (vsha2ch): Ditto.
5713         (vsha2cl): Ditto.
5714         (vsm4k): Ditto.
5715         (vsm4r): Ditto.
5716         (vsm3me): Ditto.
5717         (vsm3c): Ditto.
5718         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5719                                 Add new function_shape for crypto vector.
5720         (struct crypto_vi_def): Ditto.
5721         (struct crypto_vv_no_op_type_def): Ditto.
5722         (SHAPE): Add SHAPE declaration of crypto vector.
5723         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5724         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5725                                 Add new data type for crypto vector.
5726         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5727         (vuint32mf2_t): Ditto.
5728         (vuint32m1_t): Ditto.
5729         (vuint32m2_t): Ditto.
5730         (vuint32m4_t): Ditto.
5731         (vuint32m8_t): Ditto.
5732         (vuint64m1_t): Ditto.
5733         (vuint64m2_t): Ditto.
5734         (vuint64m4_t): Ditto.
5735         (vuint64m8_t): Ditto.
5736         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5737                                 Add new data struct for crypto vector.
5738         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5739         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5740         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5741
5742 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5743
5744         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5745
5746 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
5747
5748         PR tree-optimization/113186
5749         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
5750         Match `^` with the `==` for 1bit integral types.
5751         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
5752         integral types.
5753
5754 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5755
5756         * toplev.cc (general_init): Pass lang_mask to urlifier.
5757
5758 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5759
5760         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
5761         param.
5762         (diagnostic_context::make_option_url): Update for lang_mask param.
5763         * gcc-urlifier.cc: Include "opts.h" and "options.h".
5764         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
5765         (gcc_urlifier::m_lang_mask): New field.
5766         (doc_urls): Make static.
5767         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
5768         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5769         Look for an option by name before trying a binary search in
5770         doc_urls.
5771         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5772         (gcc_urlifier::get_url_suffix_for_option): New.
5773         (make_gcc_urlifier): Add lang_mask param.
5774         (selftest::gcc_urlifier_cc_tests): Update for above changes.
5775         Verify that a URL is found for "-fpack-struct".
5776         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
5777         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
5778         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
5779         to make_gcc_urlifier.
5780         * opts-diagnostic.h (get_option_url): Add lang_mask param.
5781         * opts.cc (get_option_html_page): Remove special-casing for
5782         analyzer and LTO.
5783         (get_option_url_suffix): New.
5784         (get_option_url): Reimplement.
5785         (selftest::test_get_option_html_page): Rename to...
5786         (selftest::test_get_option_url_suffix): ...this and update for
5787         above changes.
5788         (selftest::opts_cc_tests): Update for renaming.
5789         * opts.h: Include "rich-location.h".
5790         (get_option_url_suffix): New decl.
5791
5792 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5793
5794         * Makefile.in (ALL_OPT_URL_FILES): New.
5795         (GCC_OBJS): Add options-urls.o.
5796         (OBJS): Likewise.
5797         (OBJS-libcommon): Likewise.
5798         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
5799         inputs to opt-gather.awk.
5800         (options-urls.cc): New Makefile target.
5801         * opt-functions.awk (url_suffix): New function.
5802         (lang_url_suffix): New function.
5803         * options-urls-cc-gen.awk: New file.
5804         * opts.h (get_opt_url_suffix): New decl.
5805
5806 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5807
5808         * params.opt.urls: New file, autogenerated by
5809         regenerate-opt-urls.py.
5810
5811 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5812
5813         * common.opt.urls: New file, autogenerated by
5814         regenerate-opt-urls.py.
5815         * config/aarch64/aarch64.opt.urls: Likewise.
5816         * config/alpha/alpha.opt.urls: Likewise.
5817         * config/alpha/elf.opt.urls: Likewise.
5818         * config/arc/arc-tables.opt.urls: Likewise.
5819         * config/arc/arc.opt.urls: Likewise.
5820         * config/arm/arm-tables.opt.urls: Likewise.
5821         * config/arm/arm.opt.urls: Likewise.
5822         * config/arm/vxworks.opt.urls: Likewise.
5823         * config/avr/avr.opt.urls: Likewise.
5824         * config/bpf/bpf.opt.urls: Likewise.
5825         * config/c6x/c6x-tables.opt.urls: Likewise.
5826         * config/c6x/c6x.opt.urls: Likewise.
5827         * config/cris/cris.opt.urls: Likewise.
5828         * config/cris/elf.opt.urls: Likewise.
5829         * config/csky/csky.opt.urls: Likewise.
5830         * config/csky/csky_tables.opt.urls: Likewise.
5831         * config/darwin.opt.urls: Likewise.
5832         * config/dragonfly.opt.urls: Likewise.
5833         * config/epiphany/epiphany.opt.urls: Likewise.
5834         * config/fr30/fr30.opt.urls: Likewise.
5835         * config/freebsd.opt.urls: Likewise.
5836         * config/frv/frv.opt.urls: Likewise.
5837         * config/ft32/ft32.opt.urls: Likewise.
5838         * config/fused-madd.opt.urls: Likewise.
5839         * config/g.opt.urls: Likewise.
5840         * config/gcn/gcn.opt.urls: Likewise.
5841         * config/gnu-user.opt.urls: Likewise.
5842         * config/h8300/h8300.opt.urls: Likewise.
5843         * config/hpux11.opt.urls: Likewise.
5844         * config/i386/cygming.opt.urls: Likewise.
5845         * config/i386/cygwin.opt.urls: Likewise.
5846         * config/i386/djgpp.opt.urls: Likewise.
5847         * config/i386/i386.opt.urls: Likewise.
5848         * config/i386/mingw-w64.opt.urls: Likewise.
5849         * config/i386/mingw.opt.urls: Likewise.
5850         * config/i386/nto.opt.urls: Likewise.
5851         * config/ia64/ia64.opt.urls: Likewise.
5852         * config/ia64/ilp32.opt.urls: Likewise.
5853         * config/ia64/vms.opt.urls: Likewise.
5854         * config/iq2000/iq2000.opt.urls: Likewise.
5855         * config/linux-android.opt.urls: Likewise.
5856         * config/linux.opt.urls: Likewise.
5857         * config/lm32/lm32.opt.urls: Likewise.
5858         * config/loongarch/loongarch.opt.urls: Likewise.
5859         * config/lynx.opt.urls: Likewise.
5860         * config/m32c/m32c.opt.urls: Likewise.
5861         * config/m32r/m32r.opt.urls: Likewise.
5862         * config/m68k/ieee.opt.urls: Likewise.
5863         * config/m68k/m68k-tables.opt.urls: Likewise.
5864         * config/m68k/m68k.opt.urls: Likewise.
5865         * config/m68k/uclinux.opt.urls: Likewise.
5866         * config/mcore/mcore.opt.urls: Likewise.
5867         * config/microblaze/microblaze.opt.urls: Likewise.
5868         * config/mips/mips-tables.opt.urls: Likewise.
5869         * config/mips/mips.opt.urls: Likewise.
5870         * config/mips/sde.opt.urls: Likewise.
5871         * config/mmix/mmix.opt.urls: Likewise.
5872         * config/mn10300/mn10300.opt.urls: Likewise.
5873         * config/moxie/moxie.opt.urls: Likewise.
5874         * config/msp430/msp430.opt.urls: Likewise.
5875         * config/nds32/nds32-elf.opt.urls: Likewise.
5876         * config/nds32/nds32-linux.opt.urls: Likewise.
5877         * config/nds32/nds32.opt.urls: Likewise.
5878         * config/netbsd-elf.opt.urls: Likewise.
5879         * config/netbsd.opt.urls: Likewise.
5880         * config/nios2/elf.opt.urls: Likewise.
5881         * config/nios2/nios2.opt.urls: Likewise.
5882         * config/nvptx/nvptx-gen.opt.urls: Likewise.
5883         * config/nvptx/nvptx.opt.urls: Likewise.
5884         * config/openbsd.opt.urls: Likewise.
5885         * config/or1k/elf.opt.urls: Likewise.
5886         * config/or1k/or1k.opt.urls: Likewise.
5887         * config/pa/pa-hpux.opt.urls: Likewise.
5888         * config/pa/pa-hpux1010.opt.urls: Likewise.
5889         * config/pa/pa-hpux1111.opt.urls: Likewise.
5890         * config/pa/pa-hpux1131.opt.urls: Likewise.
5891         * config/pa/pa.opt.urls: Likewise.
5892         * config/pa/pa64-hpux.opt.urls: Likewise.
5893         * config/pdp11/pdp11.opt.urls: Likewise.
5894         * config/pru/pru.opt.urls: Likewise.
5895         * config/riscv/riscv.opt.urls: Likewise.
5896         * config/rl78/rl78.opt.urls: Likewise.
5897         * config/rpath.opt.urls: Likewise.
5898         * config/rs6000/476.opt.urls: Likewise.
5899         * config/rs6000/aix64.opt.urls: Likewise.
5900         * config/rs6000/darwin.opt.urls: Likewise.
5901         * config/rs6000/linux64.opt.urls: Likewise.
5902         * config/rs6000/rs6000-tables.opt.urls: Likewise.
5903         * config/rs6000/rs6000.opt.urls: Likewise.
5904         * config/rs6000/sysv4.opt.urls: Likewise.
5905         * config/rtems.opt.urls: Likewise.
5906         * config/rx/elf.opt.urls: Likewise.
5907         * config/rx/rx.opt.urls: Likewise.
5908         * config/s390/s390.opt.urls: Likewise.
5909         * config/s390/tpf.opt.urls: Likewise.
5910         * config/sh/sh.opt.urls: Likewise.
5911         * config/sh/superh.opt.urls: Likewise.
5912         * config/sol2.opt.urls: Likewise.
5913         * config/sparc/long-double-switch.opt.urls: Likewise.
5914         * config/sparc/sparc.opt.urls: Likewise.
5915         * config/stormy16/stormy16.opt.urls: Likewise.
5916         * config/v850/v850.opt.urls: Likewise.
5917         * config/vax/elf.opt.urls: Likewise.
5918         * config/vax/vax.opt.urls: Likewise.
5919         * config/visium/visium.opt.urls: Likewise.
5920         * config/vms/vms.opt.urls: Likewise.
5921         * config/vxworks-smp.opt.urls: Likewise.
5922         * config/vxworks.opt.urls: Likewise.
5923         * config/xtensa/elf.opt.urls: Likewise.
5924         * config/xtensa/uclinux.opt.urls: Likewise.
5925         * config/xtensa/xtensa.opt.urls: Likewise.
5926         * config/bfin/bfin.opt.urls: New file.
5927
5928 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5929
5930         * Makefile.in (OPT_URLS_HTML_DEPS): New.
5931         (regenerate-opt-urls): New target.
5932         (regenerate-opt-urls-unit-test): New target.
5933         * doc/options.texi (Option properties): Add UrlSuffix and
5934         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
5935         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
5936         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
5937         and Makefile.in's OPT_URLS_HTML_DEPS.
5938         (Anatomy of a Target Back End): Add
5939         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
5940         * regenerate-opt-urls.py: New file.
5941
5942 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
5943
5944         * diagnostic-format-sarif.cc
5945         (sarif_builder::make_logical_location_object): Convert to...
5946         (make_sarif_logical_location_object): ...this.
5947         (sarif_builder::set_any_logical_locs_arr): Update for above
5948         change.
5949         (sarif_builder::make_thread_flow_location_object): Call
5950         maybe_add_sarif_properties on each diagnostic_event.
5951         * diagnostic-format-sarif.h (class logical_location): New forward
5952         decl.
5953         (make_sarif_logical_location_object): New decl.
5954         * diagnostic-path.h (class sarif_object): New forward decl.
5955         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
5956
5957 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
5958             Patrick Lin  <patrick@andestech.com>
5959             Rufus Chen  <rufus@andestech.com>
5960             Monk Chiang  <monk.chiang@sifive.com>
5961
5962         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
5963         with Nan-boxing value.
5964         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
5965
5966 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
5967             Jeff Law  <jlaw@ventanamicro.com>
5968
5969         PR rtl-optimization/104914
5970         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
5971         a sign or zero extension is only required if the modified field
5972         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
5973         targets, don't refer to the temporarily incorrectly extended value
5974         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
5975
5976 2024-01-04  Pan Li  <pan2.li@intel.com>
5977
5978         Revert:
5979         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5980
5981         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5982
5983 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5984
5985         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5986
5987 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
5988
5989         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
5990         offset of fcsr.
5991
5992 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5993
5994         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
5995         (compute_nregs_for_mode): Refine LMUL.
5996         (max_number_of_live_regs): Ditto.
5997         (compute_estimated_lmul): Ditto.
5998         (has_unexpected_spills_p): Ditto.
5999
6000 2024-01-04  Li Wei  <liwei@loongson.cn>
6001
6002         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
6003         Remove useless forward declaration.
6004         (loongarch_is_even_extraction): Remove useless forward declaration.
6005         (loongarch_try_expand_lsx_vshuf_const): Removed.
6006         (loongarch_expand_vec_perm_const_1): Merged.
6007         (loongarch_is_double_duplicate): Removed.
6008         (loongarch_is_center_extraction): Ditto.
6009         (loongarch_is_reversing_permutation): Ditto.
6010         (loongarch_is_di_misalign_extract): Ditto.
6011         (loongarch_is_si_misalign_extract): Ditto.
6012         (loongarch_is_lasx_lowpart_extract): Ditto.
6013         (loongarch_is_op_reverse_perm): Ditto.
6014         (loongarch_is_single_op_perm): Ditto.
6015         (loongarch_is_divisible_perm): Ditto.
6016         (loongarch_is_triple_stride_extract): Ditto.
6017         (loongarch_expand_vec_perm_const_2): Merged.
6018         (loongarch_expand_vec_perm_const): New.
6019         (loongarch_vectorize_vec_perm_const): Adjust.
6020
6021 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
6022
6023         * omp-general.cc: Fix comment typos and misplaced/confusing
6024         comments.  Delete redundant include of omp-general.h.
6025
6026 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
6027
6028         PR rtl-optimization/104914
6029         * config/mips/mips.md (insqisi_extended): New patterns.
6030         (inshisi_extended): Ditto.
6031
6032 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
6033
6034         * config/mips/mips.cc (mips_insn_cost): New function.
6035
6036 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
6037
6038         * config/mips/mips.md (perf_ratio): New attribute.
6039
6040 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6041
6042         PR target/113206
6043         PR target/113209
6044         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
6045         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
6046         blocks belong to infinite loop.
6047         (pre_vsetvl::emit_vsetvl): Remove fake edges.
6048         * config/riscv/t-riscv: Add a new include file.
6049
6050 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6051
6052         * config/riscv/vector.md: Fix indent.
6053
6054 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
6055
6056         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
6057         OMP_CLAUSE__SIMDUID_.
6058         * tree.cc (omp_clause_num_ops): Update position of entry for
6059         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
6060         (omp_clause_code_name): Likewise.
6061
6062 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
6063
6064         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
6065         printing of FUNC_MAP/IND_FUNC_MAP labels.
6066
6067 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
6068
6069         * gcc.cc (process_command): Update copyright notice dates.
6070         * gcov-dump.cc (print_version): Ditto.
6071         * gcov.cc (print_version): Ditto.
6072         * gcov-tool.cc (print_version): Ditto.
6073         * gengtype.cc (create_file): Ditto.
6074         * doc/cpp.texi: Bump @copying's copyright year.
6075         * doc/cppinternals.texi: Ditto.
6076         * doc/gcc.texi: Ditto.
6077         * doc/gccint.texi: Ditto.
6078         * doc/gcov.texi: Ditto.
6079         * doc/install.texi: Ditto.
6080         * doc/invoke.texi: Ditto.
6081
6082 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
6083
6084         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
6085         (fmin<mode>3): Likewise.
6086         (reduc_fmax_scal_<mode>3): New define_expand.
6087         (reduc_fmin_scal_<mode>3): Likewise.
6088
6089 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6090
6091         PR target/113112
6092         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
6093         (max_number_of_live_regs): Ditto.
6094         (has_unexpected_spills_p): Ditto.
6095
6096 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6097             Jin Ma  <jinma@linux.alibaba.com>
6098             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6099             Christoph Müllner  <christoph.muellner@vrull.eu>
6100
6101         * config/riscv/vector.md:
6102         Use vector_length_operand for vsetvl patterns.
6103
6104 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6105
6106         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
6107         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
6108
6109 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
6110
6111         * config/aarch64/aarch64-tuning-flags.def
6112         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
6113         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
6114         * config/aarch64/aarch64.cc
6115         (aarch64_override_options_internal): Set
6116         param_fully_pipelined_fma according to tuning option.
6117         * config/aarch64/tuning_models/ampere1.h: Add
6118         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
6119         * config/aarch64/tuning_models/ampere1a.h: Likewise.
6120         * config/aarch64/tuning_models/ampere1b.h: Likewise.
6121
6122 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
6123
6124         * config/riscv/vector-crypto.md: Modify copyright year.
6125
6126 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6127
6128         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
6129
6130 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
6131
6132         * config.in: Regenerate.
6133         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
6134         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
6135         Added TLS Le Relax support.
6136         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
6137         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
6138         * configure: Regenerate.
6139         * configure.ac: Check if binutils supports TLS le relax.
6140
6141 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
6142
6143         * config/riscv/iterators.md: Add rotate insn name.
6144         * config/riscv/riscv.md: Add new insns name for crypto vector.
6145         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
6146         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
6147         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
6148
6149 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6150
6151         PR target/113112
6152         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
6153         pointer type liveness count.
6154 \f
6155 Copyright (C) 2024 Free Software Foundation, Inc.
6156
6157 Copying and distribution of this file, with or without modification,
6158 are permitted in any medium without royalty provided the copyright
6159 notice and this notice are preserved.