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1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Configuration triples for ARM ports work as follows:
25 (This is a bit of a mess and needs some thought)
26 arm-*-*: little endian
27 armel-*-*: little endian
28 armeb-*-*: big endian
29 If a non-embedded environment (ie: "real" OS) is specified, `arm'
30 should default to that used by the OS.
31 */
33 #define TARGET_CPU_arm2 0x0000
34 #define TARGET_CPU_arm250 0x0000
35 #define TARGET_CPU_arm3 0x0000
36 #define TARGET_CPU_arm6 0x0001
37 #define TARGET_CPU_arm600 0x0001
38 #define TARGET_CPU_arm610 0x0002
39 #define TARGET_CPU_arm7 0x0001
40 #define TARGET_CPU_arm7m 0x0004
41 #define TARGET_CPU_arm7dm 0x0004
42 #define TARGET_CPU_arm7dmi 0x0004
43 #define TARGET_CPU_arm700 0x0001
44 #define TARGET_CPU_arm710 0x0002
45 #define TARGET_CPU_arm7100 0x0002
46 #define TARGET_CPU_arm7500 0x0002
47 #define TARGET_CPU_arm7500fe 0x1001
48 #define TARGET_CPU_arm7tdmi 0x0008
49 #define TARGET_CPU_arm8 0x0010
50 #define TARGET_CPU_arm810 0x0020
51 #define TARGET_CPU_strongarm 0x0040
52 #define TARGET_CPU_strongarm110 0x0040
53 /* Configure didn't specify */
54 #define TARGET_CPU_generic 0x8000
56 enum arm_cond_code
57 {
60 };
64 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
66 /* This is needed by the tail-calling peepholes */
69 \f
70 /* Just in case configure has failed to define anything. */
71 #ifndef TARGET_CPU_DEFAULT
72 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
73 #endif
75 /* If the configuration file doesn't specify the cpu, the subtarget may
76 override it. If it doesn't, then default to an ARM6. */
77 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
78 #undef TARGET_CPU_DEFAULT
79 #ifdef SUBTARGET_CPU_DEFAULT
80 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
81 #else
82 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
83 #endif
84 #endif
86 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
88 #else
89 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
91 #else
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
94 #else
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi
97 #else
98 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
100 #else
101 Unrecognized value in TARGET_CPU_DEFAULT.
102 #endif
103 #endif
104 #endif
105 #endif
106 #endif
108 #ifndef CPP_PREDEFINES
110 #endif
113 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
114 %(cpp_endian) %(subtarget_cpp_spec)"
116 /* Set the architecture define -- if -march= is set, then it overrides
117 the -mcpu= setting. */
119 %{m2:-D__arm2__ -D__ARM_ARCH_2__} \
120 %{m3:-D__arm2__ -D__ARM_ARCH_2__} \
121 %{m6:-D__arm6__ -D__ARM_ARCH_3__} \
122 %{march=arm2:-D__ARM_ARCH_2__} \
123 %{march=arm250:-D__ARM_ARCH_2__} \
124 %{march=arm3:-D__ARM_ARCH_2__} \
125 %{march=arm6:-D__ARM_ARCH_3__} \
126 %{march=arm600:-D__ARM_ARCH_3__} \
127 %{march=arm610:-D__ARM_ARCH_3__} \
128 %{march=arm7:-D__ARM_ARCH_3__} \
129 %{march=arm700:-D__ARM_ARCH_3__} \
130 %{march=arm710:-D__ARM_ARCH_3__} \
131 %{march=arm7100:-D__ARM_ARCH_3__} \
132 %{march=arm7500:-D__ARM_ARCH_3__} \
133 %{march=arm7500fe:-D__ARM_ARCH_3__} \
134 %{march=arm7m:-D__ARM_ARCH_3M__} \
135 %{march=arm7dm:-D__ARM_ARCH_3M__} \
136 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
137 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
138 %{march=arm8:-D__ARM_ARCH_4__} \
139 %{march=arm810:-D__ARM_ARCH_4__} \
140 %{march=strongarm:-D__ARM_ARCH_4__} \
141 %{march=strongarm110:-D__ARM_ARCH_4__} \
142 %{march=armv2:-D__ARM_ARCH_2__} \
143 %{march=armv2a:-D__ARM_ARCH_2__} \
144 %{march=armv3:-D__ARM_ARCH_3__} \
145 %{march=armv3m:-D__ARM_ARCH_3M__} \
146 %{march=armv4:-D__ARM_ARCH_4__} \
147 %{march=armv4t:-D__ARM_ARCH_4T__} \
148 %{!march=*: \
149 %{mcpu=arm2:-D__ARM_ARCH_2__} \
150 %{mcpu=arm250:-D__ARM_ARCH_2__} \
151 %{mcpu=arm3:-D__ARM_ARCH_2__} \
152 %{mcpu=arm6:-D__ARM_ARCH_3__} \
153 %{mcpu=arm600:-D__ARM_ARCH_3__} \
154 %{mcpu=arm610:-D__ARM_ARCH_3__} \
155 %{mcpu=arm7:-D__ARM_ARCH_3__} \
156 %{mcpu=arm700:-D__ARM_ARCH_3__} \
157 %{mcpu=arm710:-D__ARM_ARCH_3__} \
158 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
159 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
160 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
161 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
162 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
163 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
164 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
165 %{mcpu=arm8:-D__ARM_ARCH_4__} \
166 %{mcpu=arm810:-D__ARM_ARCH_4__} \
167 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
168 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
169 %{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}}} \
170 "
172 /* Define __APCS_26__ if the PC also contains the PSR */
173 /* This also examines deprecated -m[236] if neither of -mapcs-{26,32} is set,
174 ??? Delete this for 2.9. */
176 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
177 -D__APCS_32__} \
178 %{mapcs-26:-D__APCS_26__} \
179 %{!mapcs-32: %{!mapcs-26:%{m6:-D__APCS_32__} %{m2:-D__APCS_26__} \
180 %{m3:-D__APCS_26__} %{!m6:%{!m3:%{!m2:%(cpp_apcs_pc_default)}}}}} \
181 "
186 %{msoft-float:\
187 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
188 -D__SOFTFP__} \
189 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
190 "
192 /* Default is hard float, which doesn't define anything */
196 %{mbig-endian: \
197 %{mlittle-endian: \
198 %e-mbig-endian and -mlittle-endian may not be used together} \
199 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
200 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
201 "
203 /* Default is little endian, which doesn't define anything. */
206 /* Translate (for now) the old -m[236] option into the appropriate -mcpu=...
207 and -mapcs-xx equivalents.
208 ??? Remove support for this style in 2.9.*/
210 %{m2:-mcpu=arm2 -mapcs-26} \
211 %{m3:-mcpu=arm3 -mapcs-26} \
212 %{m6:-mcpu=arm6 -mapcs-32} \
213 "
215 /* This macro defines names of additional specifications to put in the specs
216 that can be used in various specifications like CC1_SPEC. Its definition
217 is an initializer with a subgrouping for each command option.
219 Each subgrouping contains a string constant, that defines the
220 specification name, and a string constant that used by the GNU CC driver
221 program.
223 Do not define this macro if it does not need to do anything. */
224 #define EXTRA_SPECS \
234 SUBTARGET_EXTRA_SPECS
236 #define SUBTARGET_EXTRA_SPECS
239 \f
240 /* Run-time Target Specification. */
241 #ifndef TARGET_VERSION
242 #define TARGET_VERSION \
244 #endif
246 /* Run-time compilation parameters selecting different hardware subsets. */
249 /* The floating point instruction architecture, can be 2 or 3 */
252 /* Nonzero if the function prologue (and epilogue) should obey
253 the ARM Procedure Call Standard. */
254 #define ARM_FLAG_APCS_FRAME (0x0001)
256 /* Nonzero if the function prologue should output the function name to enable
257 the post mortem debugger to print a backtrace (very useful on RISCOS,
258 unused on RISCiX). Specifying this flag also enables
259 -fno-omit-frame-pointer.
260 XXX Must still be implemented in the prologue. */
261 #define ARM_FLAG_POKE (0x0002)
263 /* Nonzero if floating point instructions are emulated by the FPE, in which
264 case instruction scheduling becomes very uninteresting. */
265 #define ARM_FLAG_FPE (0x0004)
267 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
268 of condition flags when returning from a branch & link (ie. a function) */
269 /* ********* DEPRECATED ******** */
270 #define ARM_FLAG_ARM6 (0x0008)
272 /* ********* DEPRECATED ******** */
273 #define ARM_FLAG_ARM3 (0x0010)
275 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
276 that assume restoration of the condition flags when returning from a
277 branch and link (ie a function). */
278 #define ARM_FLAG_APCS_32 (0x0020)
280 /* Nonzero if stack checking should be performed on entry to each function
281 which allocates temporary variables on the stack. */
282 #define ARM_FLAG_APCS_STACK (0x0040)
284 /* Nonzero if floating point parameters should be passed to functions in
285 floating point registers. */
286 #define ARM_FLAG_APCS_FLOAT (0x0080)
288 /* Nonzero if re-entrant, position independent code should be generated.
289 This is equivalent to -fpic. */
290 #define ARM_FLAG_APCS_REENT (0x0100)
292 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
293 loaded byte-at-a-time. */
294 #define ARM_FLAG_SHORT_BYTE (0x0200)
296 /* Nonzero if all floating point instructions are missing (and there is no
297 emulator either). Generate function calls for all ops in this case. */
298 #define ARM_FLAG_SOFT_FLOAT (0x0400)
300 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
301 #define ARM_FLAG_BIG_END (0x0800)
303 /* Nonzero if we should compile for Thumb interworking. */
304 #define ARM_FLAG_THUMB (0x1000)
306 /* Nonzero if we should have little-endian words even when compiling for
307 big-endian (for backwards compatibility with older versions of GCC). */
308 #define ARM_FLAG_LITTLE_WORDS (0x2000)
310 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
311 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
312 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
313 #define TARGET_6 (target_flags & ARM_FLAG_ARM6)
314 #define TARGET_3 (target_flags & ARM_FLAG_ARM3)
315 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
316 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
317 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
318 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
319 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
320 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
321 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
322 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
323 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
324 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
326 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
327 Bit 31 is reserved. See riscix.h. */
328 #ifndef SUBTARGET_SWITCHES
329 #define SUBTARGET_SWITCHES
330 #endif
332 #define TARGET_SWITCHES \
333 { \
361 SUBTARGET_SWITCHES \
363 }
365 #define TARGET_OPTIONS \
366 { \
371 }
373 /* arm_select[0] is reserved for the default cpu. */
374 struct arm_cpu_select
375 {
380 };
384 #ifndef PROCESSOR_DEFAULT
385 #define PROCESSOR_DEFAULT PROCESSOR_ARM2
386 #endif
388 #ifndef TARGET_CPU_DEFAULT
389 #define TARGET_CPU_DEFAULT ((char *) 0)
390 #endif
392 /* Which processor we are running on, for instruction scheduling
393 purposes. */
394 enum processor_type
395 {
396 PROCESSOR_ARM2,
397 PROCESSOR_ARM3,
398 PROCESSOR_ARM6,
399 PROCESSOR_ARM7,
400 PROCESSOR_ARM8,
401 PROCESSOR_STARM,
402 PROCESSOR_NONE /* NOTE: This must be last, since it doesn't
403 appear in the attr_cpu list */
404 };
406 /* Recast the cpu class to be the cpu attribute. */
407 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
411 enum prog_mode_type
412 {
413 prog_mode26,
414 prog_mode32
415 };
417 /* Recast the program mode class to be the prog_mode attribute */
418 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
422 /* What sort of floating point unit do we have? Hardware or software.
423 If software, is it issue 2 or issue 3? */
424 enum floating_point_type
425 {
426 FP_HARD,
427 FP_SOFT2,
428 FP_SOFT3
429 };
431 /* Recast the floating point class to be the floating point attribute. */
432 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
434 /* What type of floating point to tune for */
437 /* What type of floating point instructions are available */
440 /* Default floating point architecture. Override in sub-target if
441 necessary. */
442 #define FP_DEFAULT FP_SOFT2
444 /* Nonzero if the processor has a fast multiply insn, and one that does
445 a 64-bit multiply of two 32-bit values. */
448 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
451 #ifndef TARGET_DEFAULT
452 #define TARGET_DEFAULT 0
453 #endif
455 /* The frame pointer register used in gcc has nothing to do with debugging;
456 that is controlled by the APCS-FRAME option. */
457 /* Not fully implemented yet */
458 /* #define CAN_DEBUG_WITHOUT_FP 1 */
460 #define TARGET_MEM_FUNCTIONS 1
462 #define OVERRIDE_OPTIONS arm_override_options ()
463 \f
464 /* Target machine storage Layout. */
467 /* Define this macro if it is advisable to hold scalars in registers
468 in a wider mode than that declared by the program. In such cases,
469 the value is constrained to be within the bounds of the declared
470 type, but kept valid in the wider mode. The signedness of the
471 extension may differ from that of the type. */
473 /* It is far faster to zero extend chars than to sign extend them */
475 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
476 if (GET_MODE_CLASS (MODE) == MODE_INT \
477 && GET_MODE_SIZE (MODE) < 4) \
478 { \
479 if (MODE == QImode) \
480 UNSIGNEDP = 1; \
481 else if (MODE == HImode) \
482 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
483 (MODE) = SImode; \
484 }
486 /* Define this macro if the promotion described by `PROMOTE_MODE'
487 should also be done for outgoing function arguments. */
488 /* This is required to ensure that push insns always push a word. */
489 #define PROMOTE_FUNCTION_ARGS
491 /* Define for XFmode extended real floating point support.
492 This will automatically cause REAL_ARITHMETIC to be defined. */
493 /* For the ARM:
494 I think I have added all the code to make this work. Unfortunately,
495 early releases of the floating point emulation code on RISCiX used a
496 different format for extended precision numbers. On my RISCiX box there
497 is a bug somewhere which causes the machine to lock up when running enquire
498 with long doubles. There is the additional aspect that Norcroft C
499 treats long doubles as doubles and we ought to remain compatible.
500 Perhaps someone with an FPA coprocessor and not running RISCiX would like
501 to try this someday. */
502 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
504 /* Disable XFmode patterns in md file */
505 #define ENABLE_XF_PATTERNS 0
507 /* Define if you don't want extended real, but do want to use the
508 software floating point emulator for REAL_ARITHMETIC and
509 decimal <-> binary conversion. */
510 /* See comment above */
511 #define REAL_ARITHMETIC
513 /* Define this if most significant bit is lowest numbered
514 in instructions that operate on numbered bit-fields. */
515 #define BITS_BIG_ENDIAN 0
517 /* Define this if most significant byte of a word is the lowest numbered.
518 Most ARM processors are run in little endian mode, so that is the default.
519 If you want to have it run-time selectable, change the definition in a
520 cover file to be TARGET_BIG_ENDIAN. */
521 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
523 /* Define this if most significant word of a multiword number is the lowest
524 numbered.
525 This is always false, even when in big-endian mode. */
526 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
528 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
529 on processor pre-defineds when compiling libgcc2.c. */
530 #if defined(__ARMEB__) && !defined(__ARMWEL__)
531 #define LIBGCC2_WORDS_BIG_ENDIAN 1
532 #else
533 #define LIBGCC2_WORDS_BIG_ENDIAN 0
534 #endif
536 /* Define this if most significant word of doubles is the lowest numbered.
537 This is always true, even when in little-endian mode. */
538 #define FLOAT_WORDS_BIG_ENDIAN 1
540 /* Number of bits in an addressable storage unit */
541 #define BITS_PER_UNIT 8
543 #define BITS_PER_WORD 32
545 #define UNITS_PER_WORD 4
547 #define POINTER_SIZE 32
549 #define PARM_BOUNDARY 32
551 #define STACK_BOUNDARY 32
553 #define FUNCTION_BOUNDARY 32
555 #define EMPTY_FIELD_BOUNDARY 32
557 #define BIGGEST_ALIGNMENT 32
559 /* Make strings word-aligned so strcpy from constants will be faster. */
560 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
561 (TREE_CODE (EXP) == STRING_CST \
562 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
564 /* Every structures size must be a multiple of 32 bits. */
565 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
566 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
567 boundaries". */
568 #define STRUCTURE_SIZE_BOUNDARY 32
570 /* Non-zero if move instructions will actually fail to work
571 when given unaligned data. */
572 #define STRICT_ALIGNMENT 1
574 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
576 \f
577 /* Standard register usage. */
579 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
580 (S - saved over call).
582 r0 * argument word/integer result
583 r1-r3 argument word
585 r4-r8 S register variable
586 r9 S (rfp) register variable (real frame pointer)
588 r10 F S (sl) stack limit (not currently used)
589 r11 F S (fp) argument pointer
590 r12 (ip) temp workspace
591 r13 F S (sp) lower end of current stack frame
592 r14 (lr) link address/workspace
593 r15 F (pc) program counter
595 f0 floating point result
596 f1-f3 floating point scratch
598 f4-f7 S floating point variable
600 cc This is NOT a real register, but is used internally
601 to represent things that use or set the condition
602 codes.
603 sfp This isn't either. It is used during rtl generation
604 since the offset between the frame pointer and the
605 auto's isn't known until after register allocation.
606 afp Nor this, we only need this because of non-local
607 goto. Without it fp appears to be used and the
608 elimination code won't get rid of sfp. It tracks
609 fp exactly at all times.
611 *: See CONDITIONAL_REGISTER_USAGE */
613 /* The stack backtrace structure is as follows:
614 fp points to here: | save code pointer | [fp]
615 | return link value | [fp, #-4]
616 | return sp value | [fp, #-8]
617 | return fp value | [fp, #-12]
618 [| saved r10 value |]
619 [| saved r9 value |]
620 [| saved r8 value |]
621 [| saved r7 value |]
622 [| saved r6 value |]
623 [| saved r5 value |]
624 [| saved r4 value |]
625 [| saved r3 value |]
626 [| saved r2 value |]
627 [| saved r1 value |]
628 [| saved r0 value |]
629 [| saved f7 value |] three words
630 [| saved f6 value |] three words
631 [| saved f5 value |] three words
632 [| saved f4 value |] three words
633 r0-r3 are not normally saved in a C function. */
635 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
636 #define FIRST_PSEUDO_REGISTER 27
638 /* 1 for registers that have pervasive standard uses
639 and are not available for the register allocator. */
640 #define FIXED_REGISTERS \
641 { \
642 0,0,0,0,0,0,0,0, \
643 0,0,1,1,0,1,0,1, \
644 0,0,0,0,0,0,0,0, \
645 1,1,1 \
646 }
648 /* 1 for registers not available across function calls.
649 These must include the FIXED_REGISTERS and also any
650 registers that can be used without being saved.
651 The latter must include the registers where values are returned
652 and the register where structure-value addresses are passed.
653 Aside from that, you can include as many other registers as you like.
654 The CC is not preserved over function calls on the ARM 6, so it is
655 easier to assume this for all. SFP is preserved, since FP is. */
656 #define CALL_USED_REGISTERS \
657 { \
658 1,1,1,1,0,0,0,0, \
659 0,0,1,1,1,1,1,1, \
660 1,1,1,1,0,0,0,0, \
661 1,1,1 \
662 }
664 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
665 trampled. This effectively reduces the number of available registers by 1.
666 XXX It is a hack, I know.
667 XXX Is this still needed? */
668 #define CONDITIONAL_REGISTER_USAGE \
669 { \
670 if (obey_regdecls) \
671 fixed_regs[0] = 1; \
672 if (TARGET_SOFT_FLOAT) \
673 { \
674 int regno; \
675 for (regno = 16; regno < 24; ++regno) \
676 fixed_regs[regno] = call_used_regs[regno] = 1; \
677 } \
678 if (flag_pic) \
679 { \
680 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
681 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
682 } \
683 }
685 /* Return number of consecutive hard regs needed starting at reg REGNO
686 to hold something of mode MODE.
687 This is ordinarily the length in words of a value of mode MODE
688 but can be less for certain modes in special long registers.
690 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
691 mode. */
692 #define HARD_REGNO_NREGS(REGNO, MODE) \
693 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
694 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
695 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
697 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
698 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
699 regs holding FP. */
700 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
701 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
702 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
703 || REGNO == ARG_POINTER_REGNUM \
704 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
706 /* Value is 1 if it is a good idea to tie two pseudo registers
707 when one has mode MODE1 and one has mode MODE2.
708 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
709 for any hard reg, then this must be 0 for correct output. */
710 #define MODES_TIEABLE_P(MODE1, MODE2) \
711 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
713 /* Specify the registers used for certain standard purposes.
714 The values of these macros are register numbers. */
716 /* Define this if the program counter is overloaded on a register. */
717 #define PC_REGNUM 15
719 /* Register to use for pushing function arguments. */
720 #define STACK_POINTER_REGNUM 13
722 /* Base register for access to local variables of the function. */
723 #define FRAME_POINTER_REGNUM 25
725 /* Define this to be where the real frame pointer is if it is not possible to
726 work out the offset between the frame pointer and the automatic variables
727 until after register allocation has taken place. FRAME_POINTER_REGNUM
728 should point to a special register that we will make sure is eliminated. */
729 #define HARD_FRAME_POINTER_REGNUM 11
731 /* Value should be nonzero if functions must have frame pointers.
732 Zero means the frame pointer need not be set up (and parms may be accessed
733 via the stack pointer) in functions that seem suitable.
734 If we have to have a frame pointer we might as well make use of it.
735 APCS says that the frame pointer does not need to be pushed in leaf
736 functions. */
737 #define FRAME_POINTER_REQUIRED \
738 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
740 /* Base register for access to arguments of the function. */
741 #define ARG_POINTER_REGNUM 26
743 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
744 as an invisible last argument (possible since varargs don't exist in
745 Pascal), so the following is not true. */
746 #define STATIC_CHAIN_REGNUM 8
748 /* Register in which address to store a structure value
749 is passed to a function. */
750 #define STRUCT_VALUE_REGNUM 0
752 /* Internal, so that we don't need to refer to a raw number */
753 #define CC_REGNUM 24
755 /* The order in which register should be allocated. It is good to use ip
756 since no saving is required (though calls clobber it) and it never contains
757 function parameters. It is quite good to use lr since other calls may
758 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
759 least likely to contain a function parameter; in addition results are
760 returned in r0.
761 */
762 #define REG_ALLOC_ORDER \
763 { \
764 3, 2, 1, 0, 12, 14, 4, 5, \
765 6, 7, 8, 10, 9, 11, 13, 15, \
766 16, 17, 18, 19, 20, 21, 22, 23, \
767 24, 25 \
768 }
769 \f
770 /* Register and constant classes. */
772 /* Register classes: all ARM regs or all FPU regs---simple! */
773 enum reg_class
774 {
775 NO_REGS,
776 FPU_REGS,
777 GENERAL_REGS,
778 ALL_REGS,
779 LIM_REG_CLASSES
780 };
782 #define N_REG_CLASSES (int) LIM_REG_CLASSES
784 /* Give names of register classes as strings for dump file. */
785 #define REG_CLASS_NAMES \
786 { \
791 }
793 /* Define which registers fit in which classes.
794 This is an initializer for a vector of HARD_REG_SET
795 of length N_REG_CLASSES. */
796 #define REG_CLASS_CONTENTS \
797 { \
802 }
804 /* The same information, inverted:
805 Return the class number of the smallest class containing
806 reg number REGNO. This could be a conditional expression
807 or could index an array. */
808 #define REGNO_REG_CLASS(REGNO) \
809 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
810 || REGNO == ARG_POINTER_REGNUM) \
811 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
812 ? NO_REGS : FPU_REGS)
814 /* The class value for index registers, and the one for base regs. */
815 #define INDEX_REG_CLASS GENERAL_REGS
816 #define BASE_REG_CLASS GENERAL_REGS
818 /* Get reg_class from a letter such as appears in the machine description.
819 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
820 #define REG_CLASS_FROM_LETTER(C) \
823 /* The letters I, J, K, L and M in a register constraint string
824 can be used to stand for particular ranges of immediate operands.
825 This macro defines what the ranges are.
826 C is the letter, and VALUE is a constant value.
827 Return 1 if VALUE is in the range specified by C.
828 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
829 J: valid indexing constants.
830 K: ~value ok in rhs argument of data operand.
831 L: -value ok in rhs argument of data operand.
832 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
833 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
839 || (((VALUE) & ((VALUE) - 1)) == 0)) \
840 : 0)
842 /* For the ARM, `Q' means that this is a memory operand that is just
843 an offset from a register.
844 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
845 address. This means that the symbol is in the text segment and can be
846 accessed without using a load. */
848 #define EXTRA_CONSTRAINT(OP, C) \
851 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
852 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
854 : 0)
856 /* Constant letter 'G' for the FPU immediate constants.
857 'H' means the same constant negated. */
858 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
862 /* Given an rtx X being reloaded into a reg required to be
863 in class CLASS, return the class of reg to actually use.
864 In general this is just CLASS; but on some machines
865 in some cases it is preferable to use a more restrictive class. */
866 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
868 /* Return the register class of a scratch register needed to copy IN into
869 or out of a register in CLASS in MODE. If it can be done directly,
870 NO_REGS is returned. */
871 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
872 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
873 ? GENERAL_REGS : NO_REGS)
875 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
876 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
877 (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \
878 ? GENERAL_REGS : NO_REGS)
880 /* Return the maximum number of consecutive registers
881 needed to represent mode MODE in a register of class CLASS.
882 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
883 #define CLASS_MAX_NREGS(CLASS, MODE) \
884 ((CLASS) == FPU_REGS ? 1 \
885 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
887 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
888 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
889 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
890 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
891 ? 20 : 2)
892 \f
893 /* Stack layout; function entry, exit and calling. */
895 /* Define this if pushing a word on the stack
896 makes the stack pointer a smaller address. */
897 #define STACK_GROWS_DOWNWARD 1
899 /* Define this if the nominal address of the stack frame
900 is at the high-address end of the local variables;
901 that is, each additional local variable allocated
902 goes at a more negative offset in the frame. */
903 #define FRAME_GROWS_DOWNWARD 1
905 /* Offset within stack frame to start allocating local variables at.
906 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
907 first local allocated. Otherwise, it is the offset to the BEGINNING
908 of the first local allocated. */
909 #define STARTING_FRAME_OFFSET 0
911 /* If we generate an insn to push BYTES bytes,
912 this says how many the stack pointer really advances by. */
913 /* The push insns do not do this rounding implicitly. So don't define this. */
914 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
916 /* Define this if the maximum size of all the outgoing args is to be
917 accumulated and pushed during the prologue. The amount can be
918 found in the variable current_function_outgoing_args_size. */
919 #define ACCUMULATE_OUTGOING_ARGS
921 /* Offset of first parameter from the argument pointer register value. */
922 #define FIRST_PARM_OFFSET(FNDECL) 4
924 /* Value is the number of byte of arguments automatically
925 popped when returning from a subroutine call.
926 FUNDECL is the declaration node of the function (as a tree),
927 FUNTYPE is the data type of the function (as a tree),
928 or for a library call it is an identifier node for the subroutine name.
929 SIZE is the number of bytes of arguments passed on the stack.
931 On the ARM, the caller does not pop any of its arguments that were passed
932 on the stack. */
933 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
935 /* Define how to find the value returned by a function.
936 VALTYPE is the data type of the value (as a tree).
937 If the precise function being called is known, FUNC is its FUNCTION_DECL;
938 otherwise, FUNC is 0. */
939 #define FUNCTION_VALUE(VALTYPE, FUNC) \
940 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
941 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
942 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
944 /* Define how to find the value returned by a library function
945 assuming the value has mode MODE. */
946 #define LIBCALL_VALUE(MODE) \
947 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
948 ? gen_rtx (REG, MODE, 16) \
949 : gen_rtx (REG, MODE, 0))
951 /* 1 if N is a possible register number for a function value.
952 On the ARM, only r0 and f0 can return results. */
953 #define FUNCTION_VALUE_REGNO_P(REGNO) \
954 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
956 /* How large values are returned */
957 /* A C expression which can inhibit the returning of certain function values
958 in registers, based on the type of value. */
959 #define RETURN_IN_MEMORY(TYPE) \
960 (TYPE_MODE ((TYPE)) == BLKmode || \
961 (AGGREGATE_TYPE_P ((TYPE)) && arm_return_in_memory ((TYPE))))
963 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
964 values must be in memory. On the ARM, they need only do so if larger
965 than a word, or if they contain elements offset from zero in the struct. */
966 #define DEFAULT_PCC_STRUCT_RETURN 0
968 /* Define where to put the arguments to a function.
969 Value is zero to push the argument on the stack,
970 or a hard register in which to store the argument.
972 MODE is the argument's machine mode.
973 TYPE is the data type of the argument (as a tree).
974 This is null for libcalls where that information may
975 not be available.
976 CUM is a variable of type CUMULATIVE_ARGS which gives info about
977 the preceding args and about the function being called.
978 NAMED is nonzero if this argument is a named parameter
979 (otherwise it is an extra parameter matching an ellipsis).
981 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
982 other arguments are passed on the stack. If (NAMED == 0) (which happens
983 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
984 passed in the stack (function_prologue will indeed make it pass in the
985 stack if necessary). */
986 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
987 ((NAMED) \
988 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
989 : 0)
991 /* For an arg passed partly in registers and partly in memory,
992 this is the number of registers used.
993 For args passed entirely in registers or entirely in memory, zero. */
994 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
995 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
996 ? GET_MODE_SIZE (MODE) \
997 : int_size_in_bytes (TYPE)) \
998 ? 4 - (CUM) / 4 : 0)
1000 /* A C type for declaring a variable that is used as the first argument of
1001 `FUNCTION_ARG' and other related values. For some target machines, the
1002 type `int' suffices and can hold the number of bytes of argument so far.
1004 On the ARM, this is the number of bytes of arguments scanned so far. */
1005 #define CUMULATIVE_ARGS int
1007 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1008 for a call to a function whose data type is FNTYPE.
1009 For a library call, FNTYPE is 0.
1010 On the ARM, the offset starts at 0. */
1011 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1012 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1014 /* Update the data in CUM to advance over an argument
1015 of mode MODE and data type TYPE.
1016 (TYPE is null for libcalls where that information may not be available.) */
1017 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1018 (CUM) += ((MODE) != BLKmode \
1019 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1020 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1022 /* 1 if N is a possible register number for function argument passing.
1023 On the ARM, r0-r3 are used to pass args. */
1024 #define FUNCTION_ARG_REGNO_P(REGNO) \
1025 ((REGNO) >= 0 && (REGNO) <= 3)
1027 /* Perform any actions needed for a function that is receiving a variable
1028 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1029 of the current parameter. PRETEND_SIZE is a variable that should be set to
1030 the amount of stack that must be pushed by the prolog to pretend that our
1031 caller pushed it.
1033 Normally, this macro will push all remaining incoming registers on the
1034 stack and set PRETEND_SIZE to the length of the registers pushed.
1036 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1037 named arg and all anonymous args onto the stack.
1038 XXX I know the prologue shouldn't be pushing registers, but it is faster
1039 that way. */
1040 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1041 { \
1042 extern int current_function_anonymous_args; \
1043 current_function_anonymous_args = 1; \
1044 if ((CUM) < 16) \
1045 (PRETEND_SIZE) = 16 - (CUM); \
1046 }
1048 /* Generate assembly output for the start of a function. */
1049 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1050 output_func_prologue ((STREAM), (SIZE))
1052 /* Call the function profiler with a given profile label. The Acorn compiler
1053 puts this BEFORE the prolog but gcc puts it afterwards. The ``mov ip,lr''
1054 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
1055 to mind about this! */
1056 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1057 { \
1061 }
1063 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1064 the stack pointer does not matter. The value is tested only in
1065 functions that have frame pointers.
1066 No definition is equivalent to always zero.
1068 On the ARM, the function epilogue recovers the stack pointer from the
1069 frame. */
1070 #define EXIT_IGNORE_STACK 1
1072 /* Generate the assembly code for function exit. */
1073 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1074 output_func_epilogue ((STREAM), (SIZE))
1076 /* Determine if the epilogue should be output as RTL.
1077 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1078 #define USE_RETURN_INSN use_return_insn ()
1080 /* Definitions for register eliminations.
1082 This is an array of structures. Each structure initializes one pair
1083 of eliminable registers. The "from" register number is given first,
1084 followed by "to". Eliminations of the same "from" register are listed
1085 in order of preference.
1087 We have two registers that can be eliminated on the ARM. First, the
1088 arg pointer register can often be eliminated in favor of the stack
1089 pointer register. Secondly, the pseudo frame pointer register can always
1090 be eliminated; it is replaced with either the stack or the real frame
1091 pointer. */
1093 #define ELIMINABLE_REGS \
1094 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1095 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1096 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1097 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1099 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1100 Frame pointer elimination is automatically handled.
1102 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1103 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1104 pointer, we must eliminate FRAME_POINTER_REGNUM into
1105 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1106 #define CAN_ELIMINATE(FROM, TO) \
1107 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1109 /* Define the offset between two registers, one to be eliminated, and the other
1110 its replacement, at the start of a routine. */
1111 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1112 { \
1113 int volatile_func = arm_volatile_func (); \
1114 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1115 (OFFSET) = 0; \
1116 else if ((FROM) == FRAME_POINTER_REGNUM \
1117 && (TO) == STACK_POINTER_REGNUM) \
1118 (OFFSET) = (current_function_outgoing_args_size \
1119 + (get_frame_size () + 3 & ~3)); \
1120 else \
1121 { \
1122 int regno; \
1123 int offset = 12; \
1124 int saved_hard_reg = 0; \
1125 \
1126 if (! volatile_func) \
1127 { \
1128 for (regno = 0; regno <= 10; regno++) \
1129 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1130 saved_hard_reg = 1, offset += 4; \
1131 for (regno = 16; regno <=23; regno++) \
1132 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1133 offset += 12; \
1134 } \
1135 if ((FROM) == FRAME_POINTER_REGNUM) \
1136 (OFFSET) = -offset; \
1137 else \
1138 { \
1139 if (! frame_pointer_needed) \
1140 offset -= 16; \
1141 if (! volatile_func \
1142 && (regs_ever_live[14] || saved_hard_reg)) \
1143 offset += 4; \
1144 offset += current_function_outgoing_args_size; \
1145 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
1146 } \
1147 } \
1148 }
1150 /* Output assembler code for a block containing the constant parts
1151 of a trampoline, leaving space for the variable parts.
1153 On the ARM, (if r8 is the static chain regnum, and remembering that
1154 referencing pc adds an offset of 8) the trampoline looks like:
1155 ldr r8, [pc, #0]
1156 ldr pc, [pc]
1157 .word static chain value
1158 .word function's address
1159 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1160 #define TRAMPOLINE_TEMPLATE(FILE) \
1161 { \
1163 REGISTER_PREFIX, REGISTER_PREFIX); \
1165 REGISTER_PREFIX, REGISTER_PREFIX); \
1168 }
1170 /* Length in units of the trampoline for entering a nested function. */
1171 #define TRAMPOLINE_SIZE 16
1173 /* Alignment required for a trampoline in units. */
1174 #define TRAMPOLINE_ALIGN 4
1176 /* Emit RTL insns to initialize the variable parts of a trampoline.
1177 FNADDR is an RTX for the address of the function's pure code.
1178 CXT is an RTX for the static chain value for the function. */
1179 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1180 { \
1181 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
1182 (CXT)); \
1183 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
1184 (FNADDR)); \
1185 }
1187 \f
1188 /* Addressing modes, and classification of registers for them. */
1190 #define HAVE_POST_INCREMENT 1
1191 #define HAVE_PRE_INCREMENT 1
1192 #define HAVE_POST_DECREMENT 1
1193 #define HAVE_PRE_DECREMENT 1
1195 /* Macros to check register numbers against specific register classes. */
1197 /* These assume that REGNO is a hard or pseudo reg number.
1198 They give nonzero only if REGNO is a hard reg of the suitable class
1199 or a pseudo reg currently allocated to a suitable hard reg.
1200 Since they use reg_renumber, they are safe only once reg_renumber
1201 has been allocated, which happens in local-alloc.c.
1203 On the ARM, don't allow the pc to be used. */
1204 #define REGNO_OK_FOR_BASE_P(REGNO) \
1205 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1206 || (REGNO) == ARG_POINTER_REGNUM \
1207 || (unsigned) reg_renumber[(REGNO)] < 15 \
1208 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1209 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1210 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1211 REGNO_OK_FOR_BASE_P(REGNO)
1213 /* Maximum number of registers that can appear in a valid memory address.
1214 Shifts in addresses can't be by a register. */
1216 #define MAX_REGS_PER_ADDRESS 2
1218 /* Recognize any constant value that is a valid address. */
1219 /* XXX We can address any constant, eventually... */
1221 #ifdef AOF_ASSEMBLER
1223 #define CONSTANT_ADDRESS_P(X) \
1224 (GET_CODE (X) == SYMBOL_REF \
1225 && CONSTANT_POOL_ADDRESS_P (X))
1227 #else
1229 #define CONSTANT_ADDRESS_P(X) \
1230 (GET_CODE (X) == SYMBOL_REF \
1231 && (CONSTANT_POOL_ADDRESS_P (X) \
1232 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1236 /* Nonzero if the constant value X is a legitimate general operand.
1237 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1239 On the ARM, allow any integer (invalid ones are removed later by insn
1240 patterns), nice doubles and symbol_refs which refer to the function's
1241 constant pool XXX. */
1242 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1244 /* Symbols in the text segment can be accessed without indirecting via the
1245 constant pool; it may take an extra binary operation, but this is still
1246 faster than indirecting via memory. Don't do this when not optimizing,
1247 since we won't be calculating al of the offsets necessary to do this
1248 simplification. */
1249 /* This doesn't work with AOF syntax, since the string table may be in
1250 a different AREA. */
1251 #ifndef AOF_ASSEMBLER
1252 #define ENCODE_SECTION_INFO(decl) \
1253 { \
1254 if (optimize > 0 && TREE_CONSTANT (decl) \
1255 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1256 { \
1258 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1259 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1260 } \
1261 }
1262 #endif
1264 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1265 and check its validity for a certain class.
1266 We have two alternate definitions for each of them.
1267 The usual definition accepts all pseudo regs; the other rejects
1268 them unless they have been allocated suitable hard regs.
1269 The symbol REG_OK_STRICT causes the latter definition to be used. */
1270 #ifndef REG_OK_STRICT
1272 /* Nonzero if X is a hard reg that can be used as a base reg
1273 or if it is a pseudo reg. */
1274 #define REG_OK_FOR_BASE_P(X) \
1275 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1276 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1278 /* Nonzero if X is a hard reg that can be used as an index
1279 or if it is a pseudo reg. */
1280 #define REG_OK_FOR_INDEX_P(X) \
1281 REG_OK_FOR_BASE_P(X)
1283 #define REG_OK_FOR_PRE_POST_P(X) \
1284 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1285 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1287 #else
1289 /* Nonzero if X is a hard reg that can be used as a base reg. */
1290 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1292 /* Nonzero if X is a hard reg that can be used as an index. */
1293 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1295 #define REG_OK_FOR_PRE_POST_P(X) \
1296 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1297 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1298 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1299 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1301 #endif
1302 \f
1303 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1304 that is a valid memory address for an instruction.
1305 The MODE argument is the machine mode for the MEM expression
1306 that wants to use this address.
1308 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1309 #define BASE_REGISTER_RTX_P(X) \
1310 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1312 #define INDEX_REGISTER_RTX_P(X) \
1313 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1315 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1316 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1317 only be small constants. */
1318 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1319 do \
1320 { \
1321 HOST_WIDE_INT range; \
1322 enum rtx_code code = GET_CODE (INDEX); \
1323 \
1324 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1325 { \
1326 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1327 && INTVAL (INDEX) > -1024 \
1328 && (INTVAL (INDEX) & 3) == 0) \
1329 goto LABEL; \
1330 } \
1331 else \
1332 { \
1333 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1334 goto LABEL; \
1335 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1336 && (! arm_arch4 || (MODE) != HImode)) \
1337 { \
1338 rtx xiop0 = XEXP (INDEX, 0); \
1339 rtx xiop1 = XEXP (INDEX, 1); \
1340 if (INDEX_REGISTER_RTX_P (xiop0) \
1341 && power_of_two_operand (xiop1, SImode)) \
1342 goto LABEL; \
1343 if (INDEX_REGISTER_RTX_P (xiop1) \
1344 && power_of_two_operand (xiop0, SImode)) \
1345 goto LABEL; \
1346 } \
1347 if (GET_MODE_SIZE (MODE) <= 4 \
1348 && (code == LSHIFTRT || code == ASHIFTRT \
1349 || code == ASHIFT || code == ROTATERT) \
1350 && (! arm_arch4 || (MODE) != HImode)) \
1351 { \
1352 rtx op = XEXP (INDEX, 1); \
1353 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1354 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1355 && INTVAL (op) <= 31) \
1356 goto LABEL; \
1357 } \
1358 range = (MODE) == HImode ? (arm_arch4 ? 256 : 4095) : 4096; \
1359 if (code == CONST_INT && INTVAL (INDEX) < range \
1360 && INTVAL (INDEX) > -range) \
1361 goto LABEL; \
1362 } \
1363 } while (0)
1365 /* Jump to LABEL if X is a valid address RTX. This must also take
1366 REG_OK_STRICT into account when deciding about valid registers, but it uses
1367 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1368 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1369 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1370 refs must be forced though a static cell to ensure addressability. */
1371 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1372 { \
1373 if (BASE_REGISTER_RTX_P (X)) \
1374 goto LABEL; \
1375 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1376 && GET_CODE (XEXP (X, 0)) == REG \
1377 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1378 goto LABEL; \
1379 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1380 && (GET_CODE (X) == LABEL_REF \
1381 || (GET_CODE (X) == CONST \
1382 && GET_CODE (XEXP ((X), 0)) == PLUS \
1383 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1384 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1385 goto LABEL; \
1386 else if ((MODE) == TImode) \
1387 ; \
1388 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1389 { \
1390 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1391 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1392 { \
1393 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1394 if (val == 4 || val == -4 || val == -8) \
1395 goto LABEL; \
1396 } \
1397 } \
1398 else if (GET_CODE (X) == PLUS) \
1399 { \
1400 rtx xop0 = XEXP(X,0); \
1401 rtx xop1 = XEXP(X,1); \
1402 \
1403 if (BASE_REGISTER_RTX_P (xop0)) \
1404 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1405 else if (BASE_REGISTER_RTX_P (xop1)) \
1406 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1407 } \
1409 /* else if (GET_CODE (X) == MINUS) \
1410 { \
1411 rtx xop0 = XEXP (X,0); \
1412 rtx xop1 = XEXP (X,1); \
1413 \
1414 if (BASE_REGISTER_RTX_P (xop0)) \
1415 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1417 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1418 && GET_CODE (X) == SYMBOL_REF \
1419 && CONSTANT_POOL_ADDRESS_P (X)) \
1420 goto LABEL; \
1421 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1422 && (GET_MODE_SIZE (MODE) <= 4) \
1423 && GET_CODE (XEXP (X, 0)) == REG \
1424 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1425 goto LABEL; \
1426 }
1427 \f
1428 /* Try machine-dependent ways of modifying an illegitimate address
1429 to be legitimate. If we find one, return the new, valid address.
1430 This macro is used in only one place: `memory_address' in explow.c.
1432 OLDX is the address as it was before break_out_memory_refs was called.
1433 In some cases it is useful to look at this to decide what needs to be done.
1435 MODE and WIN are passed so that this macro can use
1436 GO_IF_LEGITIMATE_ADDRESS.
1438 It is always safe for this macro to do nothing. It exists to recognize
1439 opportunities to optimize the output.
1441 On the ARM, try to convert [REG, #BIGCONST]
1442 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1443 where VALIDCONST == 0 in case of TImode. */
1445 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1446 { \
1447 if (GET_CODE (X) == PLUS) \
1448 { \
1449 rtx xop0 = XEXP (X, 0); \
1450 rtx xop1 = XEXP (X, 1); \
1451 \
1452 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1453 xop0 = force_reg (SImode, xop0); \
1454 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1455 xop1 = force_reg (SImode, xop1); \
1456 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1457 { \
1458 HOST_WIDE_INT n, low_n; \
1459 rtx base_reg, val; \
1460 n = INTVAL (xop1); \
1461 \
1462 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1463 { \
1464 low_n = n & 0x0f; \
1465 n &= ~0x0f; \
1466 if (low_n > 4) \
1467 { \
1468 n += 16; \
1469 low_n -= 16; \
1470 } \
1471 } \
1472 else \
1473 { \
1474 low_n = ((MODE) == TImode ? 0 \
1475 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1476 n -= low_n; \
1477 } \
1478 base_reg = gen_reg_rtx (SImode); \
1479 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1480 GEN_INT (n)), NULL_RTX); \
1481 emit_move_insn (base_reg, val); \
1482 (X) = (low_n == 0 ? base_reg \
1483 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1484 } \
1485 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1486 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1487 } \
1488 else if (GET_CODE (X) == MINUS) \
1489 { \
1490 rtx xop0 = XEXP (X, 0); \
1491 rtx xop1 = XEXP (X, 1); \
1492 \
1493 if (CONSTANT_P (xop0)) \
1494 xop0 = force_reg (SImode, xop0); \
1495 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1496 xop1 = force_reg (SImode, xop1); \
1497 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1498 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1499 } \
1500 if (flag_pic) \
1501 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1502 if (memory_address_p (MODE, X)) \
1503 goto WIN; \
1504 }
1506 /* Go to LABEL if ADDR (a legitimate address expression)
1507 has an effect that depends on the machine mode it is used for. */
1508 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1509 { \
1510 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1511 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1512 goto LABEL; \
1513 }
1514 \f
1515 /* Specify the machine mode that this machine uses
1516 for the index in the tablejump instruction. */
1517 #define CASE_VECTOR_MODE SImode
1519 /* Define as C expression which evaluates to nonzero if the tablejump
1520 instruction expects the table to contain offsets from the address of the
1521 table.
1522 Do not define this if the table should contain absolute addresses. */
1523 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1525 /* Specify the tree operation to be used to convert reals to integers. */
1526 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1528 /* This is the kind of divide that is easiest to do in the general case. */
1529 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1531 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1532 unsigned is probably best, but may break some code. */
1533 #ifndef DEFAULT_SIGNED_CHAR
1534 #define DEFAULT_SIGNED_CHAR 0
1535 #endif
1537 /* Don't cse the address of the function being compiled. */
1538 #define NO_RECURSIVE_FUNCTION_CSE 1
1540 /* Max number of bytes we can move from memory to memory
1541 in one reasonably fast instruction. */
1542 #define MOVE_MAX 4
1544 /* Define if operations between registers always perform the operation
1545 on the full register even if a narrower mode is specified. */
1546 #define WORD_REGISTER_OPERATIONS
1548 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1549 will either zero-extend or sign-extend. The value of this macro should
1550 be the code that says which one of the two operations is implicitly
1551 done, NIL if none. */
1552 #define LOAD_EXTEND_OP(MODE) \
1553 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1554 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1556 /* Define this if zero-extension is slow (more than one real instruction).
1557 On the ARM, it is more than one instruction only if not fetching from
1558 memory. */
1559 /* #define SLOW_ZERO_EXTEND */
1561 /* Nonzero if access to memory by bytes is slow and undesirable. */
1562 #define SLOW_BYTE_ACCESS 0
1564 /* Immediate shift counts are truncated by the output routines (or was it
1565 the assembler?). Shift counts in a register are truncated by ARM. Note
1566 that the native compiler puts too large (> 32) immediate shift counts
1567 into a register and shifts by the register, letting the ARM decide what
1568 to do instead of doing that itself. */
1569 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1570 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1571 On the arm, Y in a register is used modulo 256 for the shift. Only for
1572 rotates is modulo 32 used. */
1573 /* #define SHIFT_COUNT_TRUNCATED 1 */
1575 /* All integers have the same format so truncation is easy. */
1576 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1578 /* Calling from registers is a massive pain. */
1579 #define NO_FUNCTION_CSE 1
1581 /* Chars and shorts should be passed as ints. */
1582 #define PROMOTE_PROTOTYPES 1
1584 /* The machine modes of pointers and functions */
1585 #define Pmode SImode
1586 #define FUNCTION_MODE Pmode
1588 /* The structure type of the machine dependent info field of insns
1589 No uses for this yet. */
1590 /* #define INSN_MACHINE_INFO struct machine_info */
1592 /* The relative costs of various types of constants. Note that cse.c defines
1593 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1594 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1595 case CONST_INT: \
1596 if (const_ok_for_arm (INTVAL (RTX))) \
1597 return (OUTER_CODE) == SET ? 2 : -1; \
1598 else if (OUTER_CODE == AND \
1599 && const_ok_for_arm (~INTVAL (RTX))) \
1600 return -1; \
1601 else if ((OUTER_CODE == COMPARE \
1602 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1603 && const_ok_for_arm (-INTVAL (RTX))) \
1604 return -1; \
1605 else \
1606 return 5; \
1607 case CONST: \
1608 case LABEL_REF: \
1609 case SYMBOL_REF: \
1610 return 6; \
1611 case CONST_DOUBLE: \
1612 if (const_double_rtx_ok_for_fpu (RTX)) \
1613 return (OUTER_CODE) == SET ? 2 : -1; \
1614 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1615 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1616 return -1; \
1617 return(7);
1619 #define ARM_FRAME_RTX(X) \
1620 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1621 || (X) == arg_pointer_rtx)
1623 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1624 default: \
1625 return arm_rtx_costs (X, CODE, OUTER_CODE);
1627 /* Moves to and from memory are quite expensive */
1628 #define MEMORY_MOVE_COST(MODE) 10
1630 /* All address computations that can be done are free, but rtx cost returns
1631 the same for practically all of them. So we weight the different types
1632 of address here in the order (most pref first):
1633 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1634 #define ADDRESS_COST(X) \
1635 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1636 || GET_CODE (X) == SYMBOL_REF) \
1637 ? 0 \
1638 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1639 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1640 ? 10 \
1641 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1642 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1647 ? 1 : 0)) \
1648 : 4)))))
1652 /* Try to generate sequences that don't involve branches, we can then use
1653 conditional instructions */
1654 #define BRANCH_COST 4
1656 /* A C statement to update the variable COST based on the relationship
1657 between INSN that is dependent on DEP through dependence LINK. */
1658 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1659 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1660 \f
1661 /* Position Independent Code. */
1662 /* We decide which register to use based on the compilation options and
1663 the assembler in use; this is more general than the APCS restriction of
1664 using sb (r9) all the time. */
1667 /* The register number of the register used to address a table of static
1668 data addresses in memory. */
1669 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1671 #define FINALIZE_PIC arm_finalize_pic ()
1673 #define LEGITIMATE_PIC_OPERAND_P(X) (! symbol_mentioned_p (X))
1676 \f
1677 /* Condition code information. */
1678 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1679 return the mode to be used for the comparison.
1680 CCFPEmode should be used with floating inequalities,
1681 CCFPmode should be used with floating equalities.
1682 CC_NOOVmode should be used with SImode integer equalities.
1683 CC_Zmode should be used if only the Z flag is set correctly
1684 CCmode should be used otherwise. */
1686 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1687 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1688 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1689 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1696 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1698 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1701 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1702 do \
1703 { \
1704 if (GET_CODE (OP1) == CONST_INT \
1705 && ! (const_ok_for_arm (INTVAL (OP1)) \
1706 || (const_ok_for_arm (- INTVAL (OP1))))) \
1707 { \
1708 rtx const_op = OP1; \
1709 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1710 } \
1711 } while (0)
1713 #define STORE_FLAG_VALUE 1
1715 /* Define the information needed to generate branch insns. This is
1716 stored from the compare operation. Note that we can't use "rtx" here
1717 since it hasn't been defined! */
1722 /* Define the codes that are matched by predicates in arm.c */
1723 #define PREDICATE_CODES \
1749 \f
1751 /* Gcc puts the pool in the wrong place for ARM, since we can only
1752 load addresses a limited distance around the pc. We do some
1753 special munging to move the constant pool values to the correct
1754 point in the code. */
1755 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1757 /* The pool is empty, since we have moved everything into the code. */
1758 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1759 goto JUMPTO
1761 /* Output an internal label definition. */
1762 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1763 do \
1764 { \
1765 char *s = (char *) alloca (40 + strlen (PREFIX)); \
1766 extern int arm_target_label, arm_ccfsm_state; \
1767 extern rtx arm_target_insn; \
1768 \
1769 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1771 { \
1772 arm_ccfsm_state = 0; \
1773 arm_target_insn = NULL; \
1774 } \
1775 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1776 ASM_OUTPUT_LABEL (STREAM, s); \
1777 } while (0)
1779 /* Output a push or a pop instruction (only used when profiling). */
1780 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1782 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
1784 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1786 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
1788 /* Target characters. */
1789 #define TARGET_BELL 007
1790 #define TARGET_BS 010
1791 #define TARGET_TAB 011
1792 #define TARGET_NEWLINE 012
1793 #define TARGET_VT 013
1794 #define TARGET_FF 014
1795 #define TARGET_CR 015
1796 \f
1797 /* Only perform branch elimination (by making instructions conditional) if
1798 we're optimising. Otherwise it's of no use anyway. */
1799 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1800 if (optimize) \
1801 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1803 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1805 /* Output an operand of an instruction. */
1806 #define PRINT_OPERAND(STREAM, X, CODE) \
1807 arm_print_operand (STREAM, X, CODE)
1809 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1810 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1811 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1812 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1813 ? ((~ (HOST_WIDE_INT) 0) \
1814 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1815 : 0))))
1817 /* Output the address of an operand. */
1818 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1819 { \
1820 int is_minus = GET_CODE (X) == MINUS; \
1821 \
1822 if (GET_CODE (X) == REG) \
1824 reg_names[REGNO (X)]); \
1825 else if (GET_CODE (X) == PLUS || is_minus) \
1826 { \
1827 rtx base = XEXP (X, 0); \
1828 rtx index = XEXP (X, 1); \
1829 char *base_reg_name; \
1830 HOST_WIDE_INT offset = 0; \
1831 if (GET_CODE (base) != REG) \
1832 { \
1834 rtx temp = base; \
1835 base = index; \
1836 index = temp; \
1837 } \
1838 base_reg_name = reg_names[REGNO (base)]; \
1839 switch (GET_CODE (index)) \
1840 { \
1841 case CONST_INT: \
1842 offset = INTVAL (index); \
1843 if (is_minus) \
1844 offset = -offset; \
1846 base_reg_name, offset); \
1847 break; \
1848 \
1849 case REG: \
1852 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1853 break; \
1854 \
1855 case MULT: \
1856 case ASHIFTRT: \
1857 case LSHIFTRT: \
1858 case ASHIFT: \
1859 case ROTATERT: \
1860 { \
1863 reg_names[REGNO (XEXP (index, 0))]); \
1866 break; \
1867 } \
1868 \
1869 default: \
1870 abort(); \
1871 } \
1872 } \
1873 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1874 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1875 { \
1876 extern int output_memory_reference_mode; \
1877 \
1878 if (GET_CODE (XEXP (X, 0)) != REG) \
1879 abort (); \
1880 \
1881 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1883 reg_names[REGNO (XEXP (X, 0))], \
1885 GET_MODE_SIZE (output_memory_reference_mode)); \
1886 else \
1888 reg_names[REGNO (XEXP (X, 0))], \
1890 GET_MODE_SIZE (output_memory_reference_mode)); \
1891 } \
1892 else output_addr_const(STREAM, X); \
1893 }
1895 /* Handles PIC addr specially */
1896 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
1897 { \
1898 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
1899 { \
1900 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
1902 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
1904 } \
1905 else output_addr_const(STREAM, X); \
1906 }
1908 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1909 Used for C++ multiple inheritance. */
1910 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1911 do { \
1912 int mi_delta = (DELTA); \
1914 int shift = 0; \
1915 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
1916 ? 1 : 0); \
1917 if (mi_delta < 0) mi_delta = -mi_delta; \
1918 while (mi_delta != 0) \
1919 { \
1920 if (mi_delta & (3 << shift) == 0) \
1921 shift += 2; \
1922 else \
1923 { \
1925 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
1926 REGISTER_PREFIX, reg_names[this_regno], \
1927 mi_delta & (0xff << shift)); \
1928 mi_delta &= ~(0xff << shift); \
1929 shift += 8; \
1930 } \
1931 } \
1933 assemble_name (FILE, \
1934 IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
1936 } while (0)
1938 /* A C expression whose value is RTL representing the value of the return
1939 address for the frame COUNT steps up from the current frame. */
1941 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1942 ((COUNT == 0) \
1943 ? gen_rtx (MEM, Pmode, plus_constant (FRAME, -4)) \
1944 : NULL_RTX)
1946 /* Used to mask out junk bits from the return address, such as
1947 processor state, interrupt status, condition codes and the like. */
1948 #define MASK_RETURN_ADDR \
1949 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
1950 in 26 bit mode, the condition codes must be masked out of the \
1951 return address. This does not apply to ARM6 and later processors \
1953 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
1955 /* Prototypes for arm.c -- actually, they aren't since the types aren't
1956 fully defined yet. */
1964 HOST_WIDE_INT, struct rtx_def *,
1971 enum machine_mode,
2017 union tree_node *,
2053 #ifdef AOF_ASSEMBLER
2061 #endif