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2014-11-06 Steve Ellcey <sellcey@imgtec.com>
[official-gcc.git] / gcc / config / mips / mips.h
blobdd67f11fe032e003c7d5feebb99018ca7aa100e1
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS32R3 (mips_isa == 34)
212 #define ISA_MIPS32R5 (mips_isa == 36)
213 #define ISA_MIPS64 (mips_isa == 64)
214 #define ISA_MIPS64R2 (mips_isa == 65)
215 #define ISA_MIPS64R3 (mips_isa == 66)
216 #define ISA_MIPS64R5 (mips_isa == 68)
217
218 /* Architecture target defines. */
219 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
220 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
221 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
222 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
223 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
224 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
225 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
226 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
227 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
228 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
229 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
230 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
231 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
232 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
233 || mips_arch == PROCESSOR_OCTEON2 \
234 || mips_arch == PROCESSOR_OCTEON3)
235 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
236 || mips_arch == PROCESSOR_OCTEON3)
237 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
238 || mips_arch == PROCESSOR_SB1A)
239 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
240 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
241
242 /* Scheduling target defines. */
243 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
244 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
245 || mips_tune == PROCESSOR_24KF2_1 \
246 || mips_tune == PROCESSOR_24KF1_1)
247 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
248 || mips_tune == PROCESSOR_74KF2_1 \
249 || mips_tune == PROCESSOR_74KF1_1 \
250 || mips_tune == PROCESSOR_74KF3_2)
251 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
252 || mips_tune == PROCESSOR_LOONGSON_2F)
253 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
254 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
255 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
256 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
257 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
258 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
259 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
260 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
261 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
262 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
263 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
264 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
265 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
266 || mips_tune == PROCESSOR_OCTEON2 \
267 || mips_tune == PROCESSOR_OCTEON3)
268 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
269 || mips_tune == PROCESSOR_SB1A)
270 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
271
272 /* Whether vector modes and intrinsics for ST Microelectronics
273 Loongson-2E/2F processors should be enabled. In o32 pairs of
274 floating-point registers provide 64-bit values. */
275 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
276 && (TARGET_LOONGSON_2EF \
277 || TARGET_LOONGSON_3A))
278
279 /* True if the pre-reload scheduler should try to create chains of
280 multiply-add or multiply-subtract instructions. For example,
281 suppose we have:
282
283 t1 = a * b
284 t2 = t1 + c * d
285 t3 = e * f
286 t4 = t3 - g * h
287
288 t1 will have a higher priority than t2 and t3 will have a higher
289 priority than t4. However, before reload, there is no dependence
290 between t1 and t3, and they can often have similar priorities.
291 The scheduler will then tend to prefer:
292
293 t1 = a * b
294 t3 = e * f
295 t2 = t1 + c * d
296 t4 = t3 - g * h
297
298 which stops us from making full use of macc/madd-style instructions.
299 This sort of situation occurs frequently in Fourier transforms and
300 in unrolled loops.
301
302 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
303 queue so that chained multiply-add and multiply-subtract instructions
304 appear ahead of any other instruction that is likely to clobber lo.
305 In the example above, if t2 and t3 become ready at the same time,
306 the code ensures that t2 is scheduled first.
307
308 Multiply-accumulate instructions are a bigger win for some targets
309 than others, so this macro is defined on an opt-in basis. */
310 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
311 || TUNE_MIPS4120 \
312 || TUNE_MIPS4130 \
313 || TUNE_24K \
314 || TUNE_P5600)
315
316 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
317 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
318
319 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
320 directly accessible, while the command-line options select
321 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
322 in use. */
323 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
324 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
325
326 /* False if SC acts as a memory barrier with respect to itself,
327 otherwise a SYNC will be emitted after SC for atomic operations
328 that require ordering between the SC and following loads and
329 stores. It does not tell anything about ordering of loads and
330 stores prior to and following the SC, only about the SC itself and
331 those loads and stores follow it. */
332 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
333
334 /* Define preprocessor macros for the -march and -mtune options.
335 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
336 processor. If INFO's canonical name is "foo", define PREFIX to
337 be "foo", and define an additional macro PREFIX_FOO. */
338 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
339 do \
340 { \
341 char *macro, *p; \
342 \
343 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
344 for (p = macro; *p != 0; p++) \
345 if (*p == '+') \
346 *p = 'P'; \
347 else \
348 *p = TOUPPER (*p); \
349 \
350 builtin_define (macro); \
351 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
352 free (macro); \
353 } \
354 while (0)
355
356 /* Target CPU builtins. */
357 #define TARGET_CPU_CPP_BUILTINS() \
358 do \
359 { \
360 builtin_assert ("machine=mips"); \
361 builtin_assert ("cpu=mips"); \
362 builtin_define ("__mips__"); \
363 builtin_define ("_mips"); \
364 \
365 /* We do this here because __mips is defined below and so we \
366 can't use builtin_define_std. We don't ever want to define \
367 "mips" for VxWorks because some of the VxWorks headers \
368 construct include filenames from a root directory macro, \
369 an architecture macro and a filename, where the architecture \
370 macro expands to 'mips'. If we define 'mips' to 1, the \
371 architecture macro expands to 1 as well. */ \
372 if (!flag_iso && !TARGET_VXWORKS) \
373 builtin_define ("mips"); \
374 \
375 if (TARGET_64BIT) \
376 builtin_define ("__mips64"); \
377 \
378 /* Treat _R3000 and _R4000 like register-size \
379 defines, which is how they've historically \
380 been used. */ \
381 if (TARGET_64BIT) \
382 { \
383 builtin_define_std ("R4000"); \
384 builtin_define ("_R4000"); \
385 } \
386 else \
387 { \
388 builtin_define_std ("R3000"); \
389 builtin_define ("_R3000"); \
390 } \
391 \
392 if (TARGET_FLOAT64) \
393 builtin_define ("__mips_fpr=64"); \
394 else \
395 builtin_define ("__mips_fpr=32"); \
396 \
397 if (mips_base_compression_flags & MASK_MIPS16) \
398 builtin_define ("__mips16"); \
399 \
400 if (TARGET_MIPS3D) \
401 builtin_define ("__mips3d"); \
402 \
403 if (TARGET_SMARTMIPS) \
404 builtin_define ("__mips_smartmips"); \
405 \
406 if (mips_base_compression_flags & MASK_MICROMIPS) \
407 builtin_define ("__mips_micromips"); \
408 \
409 if (TARGET_MCU) \
410 builtin_define ("__mips_mcu"); \
411 \
412 if (TARGET_EVA) \
413 builtin_define ("__mips_eva"); \
414 \
415 if (TARGET_DSP) \
416 { \
417 builtin_define ("__mips_dsp"); \
418 if (TARGET_DSPR2) \
419 { \
420 builtin_define ("__mips_dspr2"); \
421 builtin_define ("__mips_dsp_rev=2"); \
422 } \
423 else \
424 builtin_define ("__mips_dsp_rev=1"); \
425 } \
426 \
427 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
428 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
429 \
430 if (ISA_MIPS1) \
431 { \
432 builtin_define ("__mips=1"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
434 } \
435 else if (ISA_MIPS2) \
436 { \
437 builtin_define ("__mips=2"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
439 } \
440 else if (ISA_MIPS3) \
441 { \
442 builtin_define ("__mips=3"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
444 } \
445 else if (ISA_MIPS4) \
446 { \
447 builtin_define ("__mips=4"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
449 } \
450 else if (ISA_MIPS32) \
451 { \
452 builtin_define ("__mips=32"); \
453 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
454 } \
455 else if (ISA_MIPS32R2) \
456 { \
457 builtin_define ("__mips=32"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
459 } \
460 else if (ISA_MIPS32R3) \
461 { \
462 builtin_define ("__mips=32"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
464 } \
465 else if (ISA_MIPS32R5) \
466 { \
467 builtin_define ("__mips=32"); \
468 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
469 } \
470 else if (ISA_MIPS64) \
471 { \
472 builtin_define ("__mips=64"); \
473 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
474 } \
475 else if (ISA_MIPS64R2) \
476 { \
477 builtin_define ("__mips=64"); \
478 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
479 } \
480 else if (ISA_MIPS64R3) \
481 { \
482 builtin_define ("__mips=64"); \
483 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
484 } \
485 else if (ISA_MIPS64R5) \
486 { \
487 builtin_define ("__mips=64"); \
488 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
489 } \
490 if (mips_isa_rev > 0) \
491 builtin_define_with_int_value ("__mips_isa_rev", \
492 mips_isa_rev); \
493 \
494 switch (mips_abi) \
495 { \
496 case ABI_32: \
497 builtin_define ("_ABIO32=1"); \
498 builtin_define ("_MIPS_SIM=_ABIO32"); \
499 break; \
500 \
501 case ABI_N32: \
502 builtin_define ("_ABIN32=2"); \
503 builtin_define ("_MIPS_SIM=_ABIN32"); \
504 break; \
505 \
506 case ABI_64: \
507 builtin_define ("_ABI64=3"); \
508 builtin_define ("_MIPS_SIM=_ABI64"); \
509 break; \
510 \
511 case ABI_O64: \
512 builtin_define ("_ABIO64=4"); \
513 builtin_define ("_MIPS_SIM=_ABIO64"); \
514 break; \
515 } \
516 \
517 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
518 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
519 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
520 builtin_define_with_int_value ("_MIPS_FPSET", \
521 32 / MAX_FPRS_PER_FMT); \
522 \
523 /* These defines reflect the ABI in use, not whether the \
524 FPU is directly accessible. */ \
525 if (TARGET_NO_FLOAT) \
526 builtin_define ("__mips_no_float"); \
527 else if (TARGET_HARD_FLOAT_ABI) \
528 builtin_define ("__mips_hard_float"); \
529 else \
530 builtin_define ("__mips_soft_float"); \
531 \
532 if (TARGET_SINGLE_FLOAT) \
533 builtin_define ("__mips_single_float"); \
534 \
535 if (TARGET_PAIRED_SINGLE_FLOAT) \
536 builtin_define ("__mips_paired_single_float"); \
537 \
538 if (mips_abs == MIPS_IEEE_754_2008) \
539 builtin_define ("__mips_abs2008"); \
540 \
541 if (mips_nan == MIPS_IEEE_754_2008) \
542 builtin_define ("__mips_nan2008"); \
543 \
544 if (TARGET_BIG_ENDIAN) \
545 { \
546 builtin_define_std ("MIPSEB"); \
547 builtin_define ("_MIPSEB"); \
548 } \
549 else \
550 { \
551 builtin_define_std ("MIPSEL"); \
552 builtin_define ("_MIPSEL"); \
553 } \
554 \
555 /* Whether calls should go through $25. The separate __PIC__ \
556 macro indicates whether abicalls code might use a GOT. */ \
557 if (TARGET_ABICALLS) \
558 builtin_define ("__mips_abicalls"); \
559 \
560 /* Whether Loongson vector modes are enabled. */ \
561 if (TARGET_LOONGSON_VECTORS) \
562 builtin_define ("__mips_loongson_vector_rev"); \
563 \
564 /* Historical Octeon macro. */ \
565 if (TARGET_OCTEON) \
566 builtin_define ("__OCTEON__"); \
567 \
568 if (TARGET_SYNCI) \
569 builtin_define ("__mips_synci"); \
570 \
571 /* Macros dependent on the C dialect. */ \
572 if (preprocessing_asm_p ()) \
573 { \
574 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
575 builtin_define ("_LANGUAGE_ASSEMBLY"); \
576 } \
577 else if (c_dialect_cxx ()) \
578 { \
579 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
580 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
581 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
582 } \
583 else \
584 { \
585 builtin_define_std ("LANGUAGE_C"); \
586 builtin_define ("_LANGUAGE_C"); \
587 } \
588 if (c_dialect_objc ()) \
589 { \
590 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
591 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
592 /* Bizarre, but retained for backwards compatibility. */ \
593 builtin_define_std ("LANGUAGE_C"); \
594 builtin_define ("_LANGUAGE_C"); \
595 } \
596 \
597 if (mips_abi == ABI_EABI) \
598 builtin_define ("__mips_eabi"); \
599 \
600 if (TARGET_CACHE_BUILTIN) \
601 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
602 } \
603 while (0)
604
605 /* Default target_flags if no switches are specified */
606
607 #ifndef TARGET_DEFAULT
608 #define TARGET_DEFAULT 0
609 #endif
610
611 #ifndef TARGET_CPU_DEFAULT
612 #define TARGET_CPU_DEFAULT 0
613 #endif
614
615 #ifndef TARGET_ENDIAN_DEFAULT
616 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
617 #endif
618
619 #ifdef IN_LIBGCC2
620 #undef TARGET_64BIT
621 /* Make this compile time constant for libgcc2 */
622 #ifdef __mips64
623 #define TARGET_64BIT 1
624 #else
625 #define TARGET_64BIT 0
626 #endif
627 #endif /* IN_LIBGCC2 */
628
629 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
630 when compiled with hardware floating point. This is because MIPS16
631 code cannot save and restore the floating-point registers, which is
632 important if in a mixed MIPS16/non-MIPS16 environment. */
633
634 #ifdef IN_LIBGCC2
635 #if __mips_hard_float
636 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
637 #endif
638 #endif /* IN_LIBGCC2 */
639
640 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
641
642 #ifndef MULTILIB_ENDIAN_DEFAULT
643 #if TARGET_ENDIAN_DEFAULT == 0
644 #define MULTILIB_ENDIAN_DEFAULT "EL"
645 #else
646 #define MULTILIB_ENDIAN_DEFAULT "EB"
647 #endif
648 #endif
649
650 #ifndef MULTILIB_ISA_DEFAULT
651 #if MIPS_ISA_DEFAULT == 1
652 #define MULTILIB_ISA_DEFAULT "mips1"
653 #elif MIPS_ISA_DEFAULT == 2
654 #define MULTILIB_ISA_DEFAULT "mips2"
655 #elif MIPS_ISA_DEFAULT == 3
656 #define MULTILIB_ISA_DEFAULT "mips3"
657 #elif MIPS_ISA_DEFAULT == 4
658 #define MULTILIB_ISA_DEFAULT "mips4"
659 #elif MIPS_ISA_DEFAULT == 32
660 #define MULTILIB_ISA_DEFAULT "mips32"
661 #elif MIPS_ISA_DEFAULT == 33
662 #define MULTILIB_ISA_DEFAULT "mips32r2"
663 #elif MIPS_ISA_DEFAULT == 64
664 #define MULTILIB_ISA_DEFAULT "mips64"
665 #elif MIPS_ISA_DEFAULT == 65
666 #define MULTILIB_ISA_DEFAULT "mips64r2"
667 #else
668 #define MULTILIB_ISA_DEFAULT "mips1"
669 #endif
670 #endif
671
672 #ifndef MIPS_ABI_DEFAULT
673 #define MIPS_ABI_DEFAULT ABI_32
674 #endif
675
676 /* Use the most portable ABI flag for the ASM specs. */
677
678 #if MIPS_ABI_DEFAULT == ABI_32
679 #define MULTILIB_ABI_DEFAULT "mabi=32"
680 #elif MIPS_ABI_DEFAULT == ABI_O64
681 #define MULTILIB_ABI_DEFAULT "mabi=o64"
682 #elif MIPS_ABI_DEFAULT == ABI_N32
683 #define MULTILIB_ABI_DEFAULT "mabi=n32"
684 #elif MIPS_ABI_DEFAULT == ABI_64
685 #define MULTILIB_ABI_DEFAULT "mabi=64"
686 #elif MIPS_ABI_DEFAULT == ABI_EABI
687 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
688 #endif
689
690 #ifndef MULTILIB_DEFAULTS
691 #define MULTILIB_DEFAULTS \
692 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
693 #endif
694
695 /* We must pass -EL to the linker by default for little endian embedded
696 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
697 linker will default to using big-endian output files. The OUTPUT_FORMAT
698 line must be in the linker script, otherwise -EB/-EL will not work. */
699
700 #ifndef ENDIAN_SPEC
701 #if TARGET_ENDIAN_DEFAULT == 0
702 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
703 #else
704 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
705 #endif
706 #endif
707
708 /* A spec condition that matches all non-mips16 -mips arguments. */
709
710 #define MIPS_ISA_LEVEL_OPTION_SPEC \
711 "mips1|mips2|mips3|mips4|mips32*|mips64*"
712
713 /* A spec condition that matches all non-mips16 architecture arguments. */
714
715 #define MIPS_ARCH_OPTION_SPEC \
716 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
717
718 /* A spec that infers a -mips argument from an -march argument,
719 or injects the default if no architecture is specified. */
720
721 #define MIPS_ISA_LEVEL_SPEC \
722 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
723 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
724 %{march=mips2|march=r6000:-mips2} \
725 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
726 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
727 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
728 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
729 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
730 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
731 %{march=mips32r3: -mips32r3} \
732 %{march=mips32r5|march=p5600: -mips32r5} \
733 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
734 |march=xlr: -mips64} \
735 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
736 %{march=mips64r3: -mips64r3} \
737 %{march=mips64r5: -mips64r5} \
738 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
739
740 /* A spec that infers a -mhard-float or -msoft-float setting from an
741 -march argument. Note that soft-float and hard-float code are not
742 link-compatible. */
743
744 #define MIPS_ARCH_FLOAT_SPEC \
745 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
746 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
747 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
748 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
749 march=*: -mhard-float}"
750
751 /* A spec condition that matches 32-bit options. It only works if
752 MIPS_ISA_LEVEL_SPEC has been applied. */
753
754 #define MIPS_32BIT_OPTION_SPEC \
755 "mips1|mips2|mips32*|mgp32"
756
757 /* Infer a -msynci setting from a -mips argument, on the assumption that
758 -msynci is desired where possible. */
759 #define MIPS_ISA_SYNCI_SPEC \
760 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips64r2|mips64r3 \
761 |mips64r5:-msynci;:-mno-synci}}"
762
763 #if (MIPS_ABI_DEFAULT == ABI_O64 \
764 || MIPS_ABI_DEFAULT == ABI_N32 \
765 || MIPS_ABI_DEFAULT == ABI_64)
766 #define OPT_ARCH64 "mabi=32|mgp32:;"
767 #define OPT_ARCH32 "mabi=32|mgp32"
768 #else
769 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
770 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
771 #endif
772
773 /* Support for a compile-time default CPU, et cetera. The rules are:
774 --with-arch is ignored if -march is specified or a -mips is specified
775 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
776 --with-tune is ignored if -mtune is specified; likewise
777 --with-tune-32 and --with-tune-64.
778 --with-abi is ignored if -mabi is specified.
779 --with-float is ignored if -mhard-float or -msoft-float are
780 specified.
781 --with-nan is ignored if -mnan is specified.
782 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
783 specified. */
784 #define OPTION_DEFAULT_SPECS \
785 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
786 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
787 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
788 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
789 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
790 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
791 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
792 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
793 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
794 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
795 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
796 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
797 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
798 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
799
800 /* A spec that infers the -mdsp setting from an -march argument. */
801 #define BASE_DRIVER_SELF_SPECS \
802 "%{!mno-dsp: \
803 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
804 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
805
806 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
807
808 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
809 && ISA_HAS_COND_TRAP)
810
811 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
812
813 /* True if the ABI can only work with 64-bit integer registers. We
814 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
815 otherwise floating-point registers must also be 64-bit. */
816 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
817
818 /* Likewise for 32-bit regs. */
819 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
820
821 /* True if the file format uses 64-bit symbols. At present, this is
822 only true for n64, which uses 64-bit ELF. */
823 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
824
825 /* True if symbols are 64 bits wide. This is usually determined by
826 the ABI's file format, but it can be overridden by -msym32. Note that
827 overriding the size with -msym32 changes the ABI of relocatable objects,
828 although it doesn't change the ABI of a fully-linked object. */
829 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
830 && Pmode == DImode \
831 && !TARGET_SYM32)
832
833 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
834 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
835 || ISA_MIPS4 \
836 || ISA_MIPS64 \
837 || ISA_MIPS64R2 \
838 || ISA_MIPS64R3 \
839 || ISA_MIPS64R5)
840
841 /* ISA has branch likely instructions (e.g. mips2). */
842 /* Disable branchlikely for tx39 until compare rewrite. They haven't
843 been generated up to this point. */
844 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
845
846 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
847 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
848 || TARGET_MIPS5400 \
849 || TARGET_MIPS5500 \
850 || TARGET_MIPS5900 \
851 || TARGET_MIPS7000 \
852 || TARGET_MIPS9000 \
853 || TARGET_MAD \
854 || mips_isa_rev >= 1) \
855 && !TARGET_MIPS16)
856
857 /* ISA has a three-operand multiplication instruction. */
858 #define ISA_HAS_DMUL3 (TARGET_64BIT \
859 && TARGET_OCTEON \
860 && !TARGET_MIPS16)
861
862 /* ISA supports instructions DMULT and DMULTU. */
863 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
864
865 /* ISA supports instructions MULT and MULTU.
866 This is always true, but the macro is needed for ISA_HAS_<D>MULT
867 in mips.md. */
868 #define ISA_HAS_MULT (1)
869
870 /* ISA supports instructions DDIV and DDIVU. */
871 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
872
873 /* ISA supports instructions DIV and DIVU.
874 This is always true, but the macro is needed for ISA_HAS_<D>DIV
875 in mips.md. */
876 #define ISA_HAS_DIV (1)
877
878 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
879 || TARGET_LOONGSON_3A) \
880 && !TARGET_MIPS16)
881
882 /* ISA has the floating-point conditional move instructions introduced
883 in mips4. */
884 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
885 || mips_isa_rev >= 1) \
886 && !TARGET_MIPS5500 \
887 && !TARGET_MIPS16)
888
889 /* ISA has the integer conditional move instructions introduced in mips4 and
890 ST Loongson 2E/2F. */
891 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
892 || TARGET_MIPS5900 \
893 || TARGET_LOONGSON_2EF)
894
895 /* ISA has LDC1 and SDC1. */
896 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
897 && !TARGET_MIPS5900 \
898 && !TARGET_MIPS16)
899
900 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
901 branch on CC, and move (both FP and non-FP) on CC. */
902 #define ISA_HAS_8CC (ISA_MIPS4 || mips_isa_rev >= 1)
903
904 /* This is a catch all for other mips4 instructions: indexed load, the
905 FP madd and msub instructions, and the FP recip and recip sqrt
906 instructions. Note that this macro should only be used by other
907 ISA_HAS_* macros. */
908 #define ISA_HAS_FP4 ((ISA_MIPS4 \
909 || ISA_MIPS64 \
910 || mips_isa_rev >= 2) \
911 && !TARGET_MIPS16)
912
913 /* ISA has floating-point indexed load and store instructions
914 (LWXC1, LDXC1, SWXC1 and SDXC1). */
915 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
916
917 /* ISA has paired-single instructions. */
918 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 || mips_isa_rev >= 2)
919
920 /* ISA has conditional trap instructions. */
921 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
922 && !TARGET_MIPS16)
923
924 /* ISA has integer multiply-accumulate instructions, madd and msub. */
925 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1)
926
927 /* Integer multiply-accumulate instructions should be generated. */
928 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
929
930 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
931 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
932
933 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
934 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
935
936 /* ISA has floating-point nmadd and nmsub instructions
937 'd = -((a * b) [+-] c)'. */
938 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
939
940 /* ISA has floating-point nmadd and nmsub instructions
941 'c = -((a * b) [+-] c)'. */
942 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
943
944 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
945 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
946 doubles are stored in pairs of FPRs, so for safety's sake, we apply
947 this restriction to the MIPS IV ISA too. */
948 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
949 (((ISA_HAS_FP4 \
950 && ((MODE) == SFmode \
951 || ((TARGET_FLOAT64 \
952 || mips_isa_rev >= 2) \
953 && (MODE) == DFmode))) \
954 || (TARGET_SB1 \
955 && (MODE) == V2SFmode)) \
956 && !TARGET_MIPS16)
957
958 /* ISA has count leading zeroes/ones instruction (not implemented). */
959 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
960
961 /* ISA has three operand multiply instructions that put
962 the high part in an accumulator: mulhi or mulhiu. */
963 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
964 || TARGET_MIPS5500 \
965 || TARGET_SR71K) \
966 && !TARGET_MIPS16)
967
968 /* ISA has three operand multiply instructions that negate the
969 result and put the result in an accumulator. */
970 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
971 || TARGET_MIPS5500 \
972 || TARGET_SR71K) \
973 && !TARGET_MIPS16)
974
975 /* ISA has three operand multiply instructions that subtract the
976 result from a 4th operand and put the result in an accumulator. */
977 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
978 || TARGET_MIPS5500 \
979 || TARGET_SR71K) \
980 && !TARGET_MIPS16)
981
982 /* ISA has three operand multiply instructions that add the result
983 to a 4th operand and put the result in an accumulator. */
984 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
985 || TARGET_MIPS4130 \
986 || TARGET_MIPS5400 \
987 || TARGET_MIPS5500 \
988 || TARGET_SR71K) \
989 && !TARGET_MIPS16)
990
991 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
992 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
993 || TARGET_MIPS4130) \
994 && !TARGET_MIPS16)
995
996 /* ISA has the "ror" (rotate right) instructions. */
997 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
998 || TARGET_MIPS5400 \
999 || TARGET_MIPS5500 \
1000 || TARGET_SR71K \
1001 || TARGET_SMARTMIPS) \
1002 && !TARGET_MIPS16)
1003
1004 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1005 64-bit targets also provide DSBH and DSHD. */
1006 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1007
1008 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1009 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1010 || TARGET_LOONGSON_2EF \
1011 || TARGET_MIPS5900 \
1012 || mips_isa_rev >= 1) \
1013 && !TARGET_MIPS16)
1014
1015 /* ISA has data indexed prefetch instructions. This controls use of
1016 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1017 (prefx is a cop1x instruction, so can only be used if FP is
1018 enabled.) */
1019 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1020
1021 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1022 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1023 also requires TARGET_DOUBLE_FLOAT. */
1024 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1025
1026 /* ISA includes the MIPS32r2 seb and seh instructions. */
1027 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1028
1029 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1030 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1031
1032 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1033 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && mips_isa_rev >= 2)
1034
1035 /* ISA has lwxs instruction (load w/scaled index address. */
1036 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1037 && !TARGET_MIPS16)
1038
1039 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1040 #define ISA_HAS_LBX (TARGET_OCTEON2)
1041 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1042 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1043 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1044 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1045 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1046 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1047 && TARGET_64BIT)
1048
1049 /* The DSP ASE is available. */
1050 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1051
1052 /* Revision 2 of the DSP ASE is available. */
1053 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1054
1055 /* True if the result of a load is not available to the next instruction.
1056 A nop will then be needed between instructions like "lw $4,..."
1057 and "addiu $4,$4,1". */
1058 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1059 && !TARGET_MIPS3900 \
1060 && !TARGET_MIPS5900 \
1061 && !TARGET_MIPS16 \
1062 && !TARGET_MICROMIPS)
1063
1064 /* Likewise mtc1 and mfc1. */
1065 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1066 && !TARGET_MIPS5900 \
1067 && !TARGET_LOONGSON_2EF)
1068
1069 /* Likewise floating-point comparisons. */
1070 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1071 && !TARGET_MIPS5900 \
1072 && !TARGET_LOONGSON_2EF)
1073
1074 /* True if mflo and mfhi can be immediately followed by instructions
1075 which write to the HI and LO registers.
1076
1077 According to MIPS specifications, MIPS ISAs I, II, and III need
1078 (at least) two instructions between the reads of HI/LO and
1079 instructions which write them, and later ISAs do not. Contradicting
1080 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1081 the UM for the NEC Vr5000) document needing the instructions between
1082 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1083 MIPS64 and later ISAs to have the interlocks, plus any specific
1084 earlier-ISA CPUs for which CPU documentation declares that the
1085 instructions are really interlocked. */
1086 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1087 || TARGET_MIPS5500 \
1088 || TARGET_MIPS5900 \
1089 || TARGET_LOONGSON_2EF)
1090
1091 /* ISA includes synci, jr.hb and jalr.hb. */
1092 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1093
1094 /* ISA includes sync. */
1095 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1096 #define GENERATE_SYNC \
1097 (target_flags_explicit & MASK_LLSC \
1098 ? TARGET_LLSC && !TARGET_MIPS16 \
1099 : ISA_HAS_SYNC)
1100
1101 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1102 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1103 instructions. */
1104 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1105 #define GENERATE_LL_SC \
1106 (target_flags_explicit & MASK_LLSC \
1107 ? TARGET_LLSC && !TARGET_MIPS16 \
1108 : ISA_HAS_LL_SC)
1109
1110 #define ISA_HAS_SWAP (TARGET_XLP)
1111 #define ISA_HAS_LDADD (TARGET_XLP)
1112
1113 /* ISA includes the baddu instruction. */
1114 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1115
1116 /* ISA includes the bbit* instructions. */
1117 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1118
1119 /* ISA includes the cins instruction. */
1120 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1121
1122 /* ISA includes the exts instruction. */
1123 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1124
1125 /* ISA includes the seq and sne instructions. */
1126 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1127
1128 /* ISA includes the pop instruction. */
1129 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1130
1131 /* The CACHE instruction is available in non-MIPS16 code. */
1132 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1133
1134 /* The CACHE instruction is available. */
1135 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1136 \f
1137 /* Tell collect what flags to pass to nm. */
1138 #ifndef NM_FLAGS
1139 #define NM_FLAGS "-Bn"
1140 #endif
1141
1142 \f
1143 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1144 the assembler. It may be overridden by subtargets.
1145
1146 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1147 COFF debugging info. */
1148
1149 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1150 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1151 %{g} %{g0} %{g1} %{g2} %{g3} \
1152 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1153 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1154 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1155 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1156 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1157 #endif
1158
1159 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1160 overridden by subtargets. */
1161
1162 #ifndef SUBTARGET_ASM_SPEC
1163 #define SUBTARGET_ASM_SPEC ""
1164 #endif
1165
1166 #undef ASM_SPEC
1167 #define ASM_SPEC "\
1168 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1169 %{mips32*} %{mips64*} \
1170 %{mips16} %{mno-mips16:-no-mips16} \
1171 %{mmicromips} %{mno-micromips} \
1172 %{mips3d} %{mno-mips3d:-no-mips3d} \
1173 %{mdmx} %{mno-mdmx:-no-mdmx} \
1174 %{mdsp} %{mno-dsp} \
1175 %{mdspr2} %{mno-dspr2} \
1176 %{mmcu} %{mno-mcu} \
1177 %{meva} %{mno-eva} \
1178 %{mvirt} %{mno-virt} \
1179 %{mxpa} %{mno-xpa} \
1180 %{msmartmips} %{mno-smartmips} \
1181 %{mmt} %{mno-mt} \
1182 %{mfix-rm7000} %{mno-fix-rm7000} \
1183 %{mfix-vr4120} %{mfix-vr4130} \
1184 %{mfix-24k} \
1185 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1186 %(subtarget_asm_debugging_spec) \
1187 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1188 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1189 %{mfp32} %{mfp64} %{mnan=*} \
1190 %{mshared} %{mno-shared} \
1191 %{msym32} %{mno-sym32} \
1192 %{mtune=*} \
1193 %{mhard-float} %{msoft-float} \
1194 %{msingle-float} %{mdouble-float} \
1195 %(subtarget_asm_spec)"
1196
1197 /* Extra switches sometimes passed to the linker. */
1198
1199 #ifndef LINK_SPEC
1200 #define LINK_SPEC "\
1201 %(endian_spec) \
1202 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1203 %{shared}"
1204 #endif /* LINK_SPEC defined */
1205
1206
1207 /* Specs for the compiler proper */
1208
1209 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1210 overridden by subtargets. */
1211 #ifndef SUBTARGET_CC1_SPEC
1212 #define SUBTARGET_CC1_SPEC ""
1213 #endif
1214
1215 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1216
1217 #undef CC1_SPEC
1218 #define CC1_SPEC "\
1219 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1220 %(subtarget_cc1_spec)"
1221
1222 /* Preprocessor specs. */
1223
1224 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1225 overridden by subtargets. */
1226 #ifndef SUBTARGET_CPP_SPEC
1227 #define SUBTARGET_CPP_SPEC ""
1228 #endif
1229
1230 #define CPP_SPEC "%(subtarget_cpp_spec)"
1231
1232 /* This macro defines names of additional specifications to put in the specs
1233 that can be used in various specifications like CC1_SPEC. Its definition
1234 is an initializer with a subgrouping for each command option.
1235
1236 Each subgrouping contains a string constant, that defines the
1237 specification name, and a string constant that used by the GCC driver
1238 program.
1239
1240 Do not define this macro if it does not need to do anything. */
1241
1242 #define EXTRA_SPECS \
1243 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1244 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1245 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1246 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1247 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1248 { "endian_spec", ENDIAN_SPEC }, \
1249 SUBTARGET_EXTRA_SPECS
1250
1251 #ifndef SUBTARGET_EXTRA_SPECS
1252 #define SUBTARGET_EXTRA_SPECS
1253 #endif
1254 \f
1255 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1256 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1257
1258 #ifndef PREFERRED_DEBUGGING_TYPE
1259 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1260 #endif
1261
1262 /* The size of DWARF addresses should be the same as the size of symbols
1263 in the target file format. They shouldn't depend on things like -msym32,
1264 because many DWARF consumers do not allow the mixture of address sizes
1265 that one would then get from linking -msym32 code with -msym64 code.
1266
1267 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1268 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1269 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1270
1271 /* By default, turn on GDB extensions. */
1272 #define DEFAULT_GDB_EXTENSIONS 1
1273
1274 /* Registers may have a prefix which can be ignored when matching
1275 user asm and register definitions. */
1276 #ifndef REGISTER_PREFIX
1277 #define REGISTER_PREFIX "$"
1278 #endif
1279
1280 /* Local compiler-generated symbols must have a prefix that the assembler
1281 understands. By default, this is $, although some targets (e.g.,
1282 NetBSD-ELF) need to override this. */
1283
1284 #ifndef LOCAL_LABEL_PREFIX
1285 #define LOCAL_LABEL_PREFIX "$"
1286 #endif
1287
1288 /* By default on the mips, external symbols do not have an underscore
1289 prepended, but some targets (e.g., NetBSD) require this. */
1290
1291 #ifndef USER_LABEL_PREFIX
1292 #define USER_LABEL_PREFIX ""
1293 #endif
1294
1295 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1296 since the length can run past this up to a continuation point. */
1297 #undef DBX_CONTIN_LENGTH
1298 #define DBX_CONTIN_LENGTH 1500
1299
1300 /* How to renumber registers for dbx and gdb. */
1301 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1302
1303 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1304 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1305
1306 /* The DWARF 2 CFA column which tracks the return address. */
1307 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1308
1309 /* Before the prologue, RA lives in r31. */
1310 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1311
1312 /* Describe how we implement __builtin_eh_return. */
1313 #define EH_RETURN_DATA_REGNO(N) \
1314 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1315
1316 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1317
1318 #define EH_USES(N) mips_eh_uses (N)
1319
1320 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1321 The default for this in 64-bit mode is 8, which causes problems with
1322 SFmode register saves. */
1323 #define DWARF_CIE_DATA_ALIGNMENT -4
1324
1325 /* Correct the offset of automatic variables and arguments. Note that
1326 the MIPS debug format wants all automatic variables and arguments
1327 to be in terms of the virtual frame pointer (stack pointer before
1328 any adjustment in the function), while the MIPS 3.0 linker wants
1329 the frame pointer to be the stack pointer after the initial
1330 adjustment. */
1331
1332 #define DEBUGGER_AUTO_OFFSET(X) \
1333 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1334 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1335 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1336 \f
1337 /* Target machine storage layout */
1338
1339 #define BITS_BIG_ENDIAN 0
1340 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1341 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1342
1343 #define MAX_BITS_PER_WORD 64
1344
1345 /* Width of a word, in units (bytes). */
1346 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1347 #ifndef IN_LIBGCC2
1348 #define MIN_UNITS_PER_WORD 4
1349 #endif
1350
1351 /* For MIPS, width of a floating point register. */
1352 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1353
1354 /* The number of consecutive floating-point registers needed to store the
1355 largest format supported by the FPU. */
1356 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1357
1358 /* The number of consecutive floating-point registers needed to store the
1359 smallest format supported by the FPU. */
1360 #define MIN_FPRS_PER_FMT \
1361 (mips_isa_rev >= 1 ? 1 : MAX_FPRS_PER_FMT)
1362
1363 /* The largest size of value that can be held in floating-point
1364 registers and moved with a single instruction. */
1365 #define UNITS_PER_HWFPVALUE \
1366 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1367
1368 /* The largest size of value that can be held in floating-point
1369 registers. */
1370 #define UNITS_PER_FPVALUE \
1371 (TARGET_SOFT_FLOAT_ABI ? 0 \
1372 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1373 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1374
1375 /* The number of bytes in a double. */
1376 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1377
1378 /* Set the sizes of the core types. */
1379 #define SHORT_TYPE_SIZE 16
1380 #define INT_TYPE_SIZE 32
1381 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1382 #define LONG_LONG_TYPE_SIZE 64
1383
1384 #define FLOAT_TYPE_SIZE 32
1385 #define DOUBLE_TYPE_SIZE 64
1386 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1387
1388 /* Define the sizes of fixed-point types. */
1389 #define SHORT_FRACT_TYPE_SIZE 8
1390 #define FRACT_TYPE_SIZE 16
1391 #define LONG_FRACT_TYPE_SIZE 32
1392 #define LONG_LONG_FRACT_TYPE_SIZE 64
1393
1394 #define SHORT_ACCUM_TYPE_SIZE 16
1395 #define ACCUM_TYPE_SIZE 32
1396 #define LONG_ACCUM_TYPE_SIZE 64
1397 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1398 doesn't support 128-bit integers for MIPS32 currently. */
1399 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1400
1401 /* long double is not a fixed mode, but the idea is that, if we
1402 support long double, we also want a 128-bit integer type. */
1403 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1404
1405 /* Width in bits of a pointer. */
1406 #ifndef POINTER_SIZE
1407 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1408 #endif
1409
1410 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1411 #define PARM_BOUNDARY BITS_PER_WORD
1412
1413 /* Allocation boundary (in *bits*) for the code of a function. */
1414 #define FUNCTION_BOUNDARY 32
1415
1416 /* Alignment of field after `int : 0' in a structure. */
1417 #define EMPTY_FIELD_BOUNDARY 32
1418
1419 /* Every structure's size must be a multiple of this. */
1420 /* 8 is observed right on a DECstation and on riscos 4.02. */
1421 #define STRUCTURE_SIZE_BOUNDARY 8
1422
1423 /* There is no point aligning anything to a rounder boundary than this. */
1424 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1425
1426 /* All accesses must be aligned. */
1427 #define STRICT_ALIGNMENT 1
1428
1429 /* Define this if you wish to imitate the way many other C compilers
1430 handle alignment of bitfields and the structures that contain
1431 them.
1432
1433 The behavior is that the type written for a bit-field (`int',
1434 `short', or other integer type) imposes an alignment for the
1435 entire structure, as if the structure really did contain an
1436 ordinary field of that type. In addition, the bit-field is placed
1437 within the structure so that it would fit within such a field,
1438 not crossing a boundary for it.
1439
1440 Thus, on most machines, a bit-field whose type is written as `int'
1441 would not cross a four-byte boundary, and would force four-byte
1442 alignment for the whole structure. (The alignment used may not
1443 be four bytes; it is controlled by the other alignment
1444 parameters.)
1445
1446 If the macro is defined, its definition should be a C expression;
1447 a nonzero value for the expression enables this behavior. */
1448
1449 #define PCC_BITFIELD_TYPE_MATTERS 1
1450
1451 /* If defined, a C expression to compute the alignment given to a
1452 constant that is being placed in memory. CONSTANT is the constant
1453 and ALIGN is the alignment that the object would ordinarily have.
1454 The value of this macro is used instead of that alignment to align
1455 the object.
1456
1457 If this macro is not defined, then ALIGN is used.
1458
1459 The typical use of this macro is to increase alignment for string
1460 constants to be word aligned so that `strcpy' calls that copy
1461 constants can be done inline. */
1462
1463 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1464 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1465 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1466
1467 /* If defined, a C expression to compute the alignment for a static
1468 variable. TYPE is the data type, and ALIGN is the alignment that
1469 the object would ordinarily have. The value of this macro is used
1470 instead of that alignment to align the object.
1471
1472 If this macro is not defined, then ALIGN is used.
1473
1474 One use of this macro is to increase alignment of medium-size
1475 data to make it all fit in fewer cache lines. Another is to
1476 cause character arrays to be word-aligned so that `strcpy' calls
1477 that copy constants to character arrays can be done inline. */
1478
1479 #undef DATA_ALIGNMENT
1480 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1481 ((((ALIGN) < BITS_PER_WORD) \
1482 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1483 || TREE_CODE (TYPE) == UNION_TYPE \
1484 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1485
1486 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1487 character arrays to be word-aligned so that `strcpy' calls that copy
1488 constants to character arrays can be done inline, and 'strcmp' can be
1489 optimised to use word loads. */
1490 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1491 DATA_ALIGNMENT (TYPE, ALIGN)
1492
1493 #define PAD_VARARGS_DOWN \
1494 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1495
1496 /* Define if operations between registers always perform the operation
1497 on the full register even if a narrower mode is specified. */
1498 #define WORD_REGISTER_OPERATIONS
1499
1500 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1501 moves. All other references are zero extended. */
1502 #define LOAD_EXTEND_OP(MODE) \
1503 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1504 ? SIGN_EXTEND : ZERO_EXTEND)
1505
1506 /* Define this macro if it is advisable to hold scalars in registers
1507 in a wider mode than that declared by the program. In such cases,
1508 the value is constrained to be within the bounds of the declared
1509 type, but kept valid in the wider mode. The signedness of the
1510 extension may differ from that of the type. */
1511
1512 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1513 if (GET_MODE_CLASS (MODE) == MODE_INT \
1514 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1515 { \
1516 if ((MODE) == SImode) \
1517 (UNSIGNEDP) = 0; \
1518 (MODE) = Pmode; \
1519 }
1520
1521 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1522 Extensions of pointers to word_mode must be signed. */
1523 #define POINTERS_EXTEND_UNSIGNED false
1524
1525 /* Define if loading short immediate values into registers sign extends. */
1526 #define SHORT_IMMEDIATES_SIGN_EXTEND
1527
1528 /* The [d]clz instructions have the natural values at 0. */
1529
1530 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1531 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1532 \f
1533 /* Standard register usage. */
1534
1535 /* Number of hardware registers. We have:
1536
1537 - 32 integer registers
1538 - 32 floating point registers
1539 - 8 condition code registers
1540 - 2 accumulator registers (hi and lo)
1541 - 32 registers each for coprocessors 0, 2 and 3
1542 - 4 fake registers:
1543 - ARG_POINTER_REGNUM
1544 - FRAME_POINTER_REGNUM
1545 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1546 - CPRESTORE_SLOT_REGNUM
1547 - 2 dummy entries that were used at various times in the past.
1548 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1549 - 6 DSP control registers */
1550
1551 #define FIRST_PSEUDO_REGISTER 188
1552
1553 /* By default, fix the kernel registers ($26 and $27), the global
1554 pointer ($28) and the stack pointer ($29). This can change
1555 depending on the command-line options.
1556
1557 Regarding coprocessor registers: without evidence to the contrary,
1558 it's best to assume that each coprocessor register has a unique
1559 use. This can be overridden, in, e.g., mips_option_override or
1560 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1561 inappropriate for a particular target. */
1562
1563 #define FIXED_REGISTERS \
1564 { \
1565 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1570 /* COP0 registers */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 /* COP2 registers */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 /* COP3 registers */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 /* 6 DSP accumulator registers & 6 control registers */ \
1580 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1581 }
1582
1583
1584 /* Set up this array for o32 by default.
1585
1586 Note that we don't mark $31 as a call-clobbered register. The idea is
1587 that it's really the call instructions themselves which clobber $31.
1588 We don't care what the called function does with it afterwards.
1589
1590 This approach makes it easier to implement sibcalls. Unlike normal
1591 calls, sibcalls don't clobber $31, so the register reaches the
1592 called function in tact. EPILOGUE_USES says that $31 is useful
1593 to the called function. */
1594
1595 #define CALL_USED_REGISTERS \
1596 { \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1602 /* COP0 registers */ \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 /* COP2 registers */ \
1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1608 /* COP3 registers */ \
1609 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1611 /* 6 DSP accumulator registers & 6 control registers */ \
1612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1613 }
1614
1615
1616 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1617
1618 #define CALL_REALLY_USED_REGISTERS \
1619 { /* General registers. */ \
1620 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1621 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1622 /* Floating-point registers. */ \
1623 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1624 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1625 /* Others. */ \
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1627 /* COP0 registers */ \
1628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1630 /* COP2 registers */ \
1631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1633 /* COP3 registers */ \
1634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1636 /* 6 DSP accumulator registers & 6 control registers */ \
1637 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1638 }
1639
1640 /* Internal macros to classify a register number as to whether it's a
1641 general purpose register, a floating point register, a
1642 multiply/divide register, or a status register. */
1643
1644 #define GP_REG_FIRST 0
1645 #define GP_REG_LAST 31
1646 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1647 #define GP_DBX_FIRST 0
1648 #define K0_REG_NUM (GP_REG_FIRST + 26)
1649 #define K1_REG_NUM (GP_REG_FIRST + 27)
1650 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1651
1652 #define FP_REG_FIRST 32
1653 #define FP_REG_LAST 63
1654 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1655 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1656
1657 #define MD_REG_FIRST 64
1658 #define MD_REG_LAST 65
1659 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1660 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1661
1662 /* The DWARF 2 CFA column which tracks the return address from a
1663 signal handler context. This means that to maintain backwards
1664 compatibility, no hard register can be assigned this column if it
1665 would need to be handled by the DWARF unwinder. */
1666 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1667
1668 #define ST_REG_FIRST 67
1669 #define ST_REG_LAST 74
1670 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1671
1672
1673 /* FIXME: renumber. */
1674 #define COP0_REG_FIRST 80
1675 #define COP0_REG_LAST 111
1676 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1677
1678 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1679 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1680 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1681
1682 #define COP2_REG_FIRST 112
1683 #define COP2_REG_LAST 143
1684 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1685
1686 #define COP3_REG_FIRST 144
1687 #define COP3_REG_LAST 175
1688 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1689
1690 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1691 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1692 #define ALL_COP_REG_LAST COP3_REG_LAST
1693 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1694
1695 #define DSP_ACC_REG_FIRST 176
1696 #define DSP_ACC_REG_LAST 181
1697 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1698
1699 #define AT_REGNUM (GP_REG_FIRST + 1)
1700 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1701 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1702
1703 /* A few bitfield locations for the coprocessor registers. */
1704 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1705 the cause register for the EIC interrupt mode. */
1706 #define CAUSE_IPL 10
1707 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1708 #define SR_IPL 10
1709 /* Exception Level is at bit 1 of the status register. */
1710 #define SR_EXL 1
1711 /* Interrupt Enable is at bit 0 of the status register. */
1712 #define SR_IE 0
1713
1714 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1715 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1716 should be used instead. */
1717 #define FPSW_REGNUM ST_REG_FIRST
1718
1719 #define GP_REG_P(REGNO) \
1720 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1721 #define M16_REG_P(REGNO) \
1722 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1723 #define M16STORE_REG_P(REGNO) \
1724 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1725 #define FP_REG_P(REGNO) \
1726 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1727 #define MD_REG_P(REGNO) \
1728 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1729 #define ST_REG_P(REGNO) \
1730 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1731 #define COP0_REG_P(REGNO) \
1732 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1733 #define COP2_REG_P(REGNO) \
1734 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1735 #define COP3_REG_P(REGNO) \
1736 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1737 #define ALL_COP_REG_P(REGNO) \
1738 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1739 /* Test if REGNO is one of the 6 new DSP accumulators. */
1740 #define DSP_ACC_REG_P(REGNO) \
1741 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1742 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1743 #define ACC_REG_P(REGNO) \
1744 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1745
1746 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1747
1748 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1749 to initialize the mips16 gp pseudo register. */
1750 #define CONST_GP_P(X) \
1751 (GET_CODE (X) == CONST \
1752 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1753 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1754
1755 /* Return coprocessor number from register number. */
1756
1757 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1758 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1759 : COP3_REG_P (REGNO) ? '3' : '?')
1760
1761
1762 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1763
1764 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1765 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1766
1767 #define MODES_TIEABLE_P mips_modes_tieable_p
1768
1769 /* Register to use for pushing function arguments. */
1770 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1771
1772 /* These two registers don't really exist: they get eliminated to either
1773 the stack or hard frame pointer. */
1774 #define ARG_POINTER_REGNUM 77
1775 #define FRAME_POINTER_REGNUM 78
1776
1777 /* $30 is not available on the mips16, so we use $17 as the frame
1778 pointer. */
1779 #define HARD_FRAME_POINTER_REGNUM \
1780 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1781
1782 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1783 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1784
1785 /* Register in which static-chain is passed to a function. */
1786 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1787
1788 /* Registers used as temporaries in prologue/epilogue code:
1789
1790 - If a MIPS16 PIC function needs access to _gp, it first loads
1791 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1792
1793 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1794 register. The register must not conflict with MIPS16_PIC_TEMP.
1795
1796 - If we aren't generating MIPS16 code, the prologue can also use
1797 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1798
1799 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1800 register.
1801
1802 If we're generating MIPS16 code, these registers must come from the
1803 core set of 8. The prologue registers mustn't conflict with any
1804 incoming arguments, the static chain pointer, or the frame pointer.
1805 The epilogue temporary mustn't conflict with the return registers,
1806 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1807 or the EH data registers.
1808
1809 If we're generating interrupt handlers, we use K0 as a temporary register
1810 in prologue/epilogue code. */
1811
1812 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1813 #define MIPS_PROLOGUE_TEMP_REGNUM \
1814 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1815 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1816 (TARGET_MIPS16 \
1817 ? (gcc_unreachable (), INVALID_REGNUM) \
1818 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1819 #define MIPS_EPILOGUE_TEMP_REGNUM \
1820 (cfun->machine->interrupt_handler_p \
1821 ? K0_REG_NUM \
1822 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1823
1824 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1825 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1826 #define MIPS_PROLOGUE_TEMP2(MODE) \
1827 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1828 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1829
1830 /* Define this macro if it is as good or better to call a constant
1831 function address than to call an address kept in a register. */
1832 #define NO_FUNCTION_CSE 1
1833
1834 /* The ABI-defined global pointer. Sometimes we use a different
1835 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1836 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1837
1838 /* We normally use $28 as the global pointer. However, when generating
1839 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1840 register instead. They can then avoid saving and restoring $28
1841 and perhaps avoid using a frame at all.
1842
1843 When a leaf function uses something other than $28, mips_expand_prologue
1844 will modify pic_offset_table_rtx in place. Take the register number
1845 from there after reload. */
1846 #define PIC_OFFSET_TABLE_REGNUM \
1847 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1848 \f
1849 /* Define the classes of registers for register constraints in the
1850 machine description. Also define ranges of constants.
1851
1852 One of the classes must always be named ALL_REGS and include all hard regs.
1853 If there is more than one class, another class must be named NO_REGS
1854 and contain no registers.
1855
1856 The name GENERAL_REGS must be the name of a class (or an alias for
1857 another name such as ALL_REGS). This is the class of registers
1858 that is allowed by "g" or "r" in a register constraint.
1859 Also, registers outside this class are allocated only when
1860 instructions express preferences for them.
1861
1862 The classes must be numbered in nondecreasing order; that is,
1863 a larger-numbered class must never be contained completely
1864 in a smaller-numbered class.
1865
1866 For any two classes, it is very desirable that there be another
1867 class that represents their union. */
1868
1869 enum reg_class
1870 {
1871 NO_REGS, /* no registers in set */
1872 M16_STORE_REGS, /* microMIPS store registers */
1873 M16_REGS, /* mips16 directly accessible registers */
1874 M16_SP_REGS, /* mips16 + $sp */
1875 T_REG, /* mips16 T register ($24) */
1876 M16_T_REGS, /* mips16 registers plus T register */
1877 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1878 V1_REG, /* Register $v1 ($3) used for TLS access. */
1879 SPILL_REGS, /* All but $sp and call preserved regs are in here */
1880 LEA_REGS, /* Every GPR except $25 */
1881 GR_REGS, /* integer registers */
1882 FP_REGS, /* floating point registers */
1883 MD0_REG, /* first multiply/divide register */
1884 MD1_REG, /* second multiply/divide register */
1885 MD_REGS, /* multiply/divide registers (hi/lo) */
1886 COP0_REGS, /* generic coprocessor classes */
1887 COP2_REGS,
1888 COP3_REGS,
1889 ST_REGS, /* status registers (fp status) */
1890 DSP_ACC_REGS, /* DSP accumulator registers */
1891 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1892 FRAME_REGS, /* $arg and $frame */
1893 GR_AND_MD0_REGS, /* union classes */
1894 GR_AND_MD1_REGS,
1895 GR_AND_MD_REGS,
1896 GR_AND_ACC_REGS,
1897 ALL_REGS, /* all registers */
1898 LIM_REG_CLASSES /* max value + 1 */
1899 };
1900
1901 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1902
1903 #define GENERAL_REGS GR_REGS
1904
1905 /* An initializer containing the names of the register classes as C
1906 string constants. These names are used in writing some of the
1907 debugging dumps. */
1908
1909 #define REG_CLASS_NAMES \
1910 { \
1911 "NO_REGS", \
1912 "M16_STORE_REGS", \
1913 "M16_REGS", \
1914 "M16_SP_REGS", \
1915 "T_REG", \
1916 "M16_T_REGS", \
1917 "PIC_FN_ADDR_REG", \
1918 "V1_REG", \
1919 "SPILL_REGS", \
1920 "LEA_REGS", \
1921 "GR_REGS", \
1922 "FP_REGS", \
1923 "MD0_REG", \
1924 "MD1_REG", \
1925 "MD_REGS", \
1926 /* coprocessor registers */ \
1927 "COP0_REGS", \
1928 "COP2_REGS", \
1929 "COP3_REGS", \
1930 "ST_REGS", \
1931 "DSP_ACC_REGS", \
1932 "ACC_REGS", \
1933 "FRAME_REGS", \
1934 "GR_AND_MD0_REGS", \
1935 "GR_AND_MD1_REGS", \
1936 "GR_AND_MD_REGS", \
1937 "GR_AND_ACC_REGS", \
1938 "ALL_REGS" \
1939 }
1940
1941 /* An initializer containing the contents of the register classes,
1942 as integers which are bit masks. The Nth integer specifies the
1943 contents of class N. The way the integer MASK is interpreted is
1944 that register R is in the class if `MASK & (1 << R)' is 1.
1945
1946 When the machine has more than 32 registers, an integer does not
1947 suffice. Then the integers are replaced by sub-initializers,
1948 braced groupings containing several integers. Each
1949 sub-initializer must be suitable as an initializer for the type
1950 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1951
1952 #define REG_CLASS_CONTENTS \
1953 { \
1954 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1955 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
1956 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1957 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
1958 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1959 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1960 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1961 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1962 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
1963 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1964 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1965 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1966 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1967 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1968 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1969 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1970 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1971 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1972 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1973 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1974 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1975 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1976 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1977 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1978 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1979 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1980 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1981 }
1982
1983
1984 /* A C expression whose value is a register class containing hard
1985 register REGNO. In general there is more that one such class;
1986 choose a class which is "minimal", meaning that no smaller class
1987 also contains the register. */
1988
1989 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1990
1991 /* A macro whose definition is the name of the class to which a
1992 valid base register must belong. A base register is one used in
1993 an address which is the register value plus a displacement. */
1994
1995 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
1996
1997 /* A macro whose definition is the name of the class to which a
1998 valid index register must belong. An index register is one used
1999 in an address where its value is either multiplied by a scale
2000 factor or added to another register (as well as added to a
2001 displacement). */
2002
2003 #define INDEX_REG_CLASS NO_REGS
2004
2005 /* We generally want to put call-clobbered registers ahead of
2006 call-saved ones. (IRA expects this.) */
2007
2008 #define REG_ALLOC_ORDER \
2009 { /* Accumulator registers. When GPRs and accumulators have equal \
2010 cost, we generally prefer to use accumulators. For example, \
2011 a division of multiplication result is better allocated to LO, \
2012 so that we put the MFLO at the point of use instead of at the \
2013 point of definition. It's also needed if we're to take advantage \
2014 of the extra accumulators available with -mdspr2. In some cases, \
2015 it can also help to reduce register pressure. */ \
2016 64, 65,176,177,178,179,180,181, \
2017 /* Call-clobbered GPRs. */ \
2018 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2019 24, 25, 31, \
2020 /* The global pointer. This is call-clobbered for o32 and o64 \
2021 abicalls, call-saved for n32 and n64 abicalls, and a program \
2022 invariant otherwise. Putting it between the call-clobbered \
2023 and call-saved registers should cope with all eventualities. */ \
2024 28, \
2025 /* Call-saved GPRs. */ \
2026 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2027 /* GPRs that can never be exposed to the register allocator. */ \
2028 0, 26, 27, 29, \
2029 /* Call-clobbered FPRs. */ \
2030 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2031 48, 49, 50, 51, \
2032 /* FPRs that are usually call-saved. The odd ones are actually \
2033 call-clobbered for n32, but listing them ahead of the even \
2034 registers might encourage the register allocator to fragment \
2035 the available FPR pairs. We need paired FPRs to store long \
2036 doubles, so it isn't clear that using a different order \
2037 for n32 would be a win. */ \
2038 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2039 /* None of the remaining classes have defined call-saved \
2040 registers. */ \
2041 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2042 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2043 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2044 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2045 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2046 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2047 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2048 182,183,184,185,186,187 \
2049 }
2050
2051 /* True if VALUE is an unsigned 6-bit number. */
2052
2053 #define UIMM6_OPERAND(VALUE) \
2054 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2055
2056 /* True if VALUE is a signed 10-bit number. */
2057
2058 #define IMM10_OPERAND(VALUE) \
2059 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2060
2061 /* True if VALUE is a signed 16-bit number. */
2062
2063 #define SMALL_OPERAND(VALUE) \
2064 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2065
2066 /* True if VALUE is an unsigned 16-bit number. */
2067
2068 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2069 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2070
2071 /* True if VALUE can be loaded into a register using LUI. */
2072
2073 #define LUI_OPERAND(VALUE) \
2074 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2075 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2076
2077 /* Return a value X with the low 16 bits clear, and such that
2078 VALUE - X is a signed 16-bit value. */
2079
2080 #define CONST_HIGH_PART(VALUE) \
2081 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2082
2083 #define CONST_LOW_PART(VALUE) \
2084 ((VALUE) - CONST_HIGH_PART (VALUE))
2085
2086 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2087 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2088 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2089 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2090
2091 /* The HI and LO registers can only be reloaded via the general
2092 registers. Condition code registers can only be loaded to the
2093 general registers, and from the floating point registers. */
2094
2095 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2096 mips_secondary_reload_class (CLASS, MODE, X, true)
2097 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2098 mips_secondary_reload_class (CLASS, MODE, X, false)
2099
2100 /* Return the maximum number of consecutive registers
2101 needed to represent mode MODE in a register of class CLASS. */
2102
2103 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2104
2105 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2106 mips_cannot_change_mode_class (FROM, TO, CLASS)
2107 \f
2108 /* Stack layout; function entry, exit and calling. */
2109
2110 #define STACK_GROWS_DOWNWARD
2111
2112 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2113
2114 /* Size of the area allocated in the frame to save the GP. */
2115
2116 #define MIPS_GP_SAVE_AREA_SIZE \
2117 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2118
2119 /* The offset of the first local variable from the frame pointer. See
2120 mips_compute_frame_info for details about the frame layout. */
2121
2122 #define STARTING_FRAME_OFFSET \
2123 (FRAME_GROWS_DOWNWARD \
2124 ? 0 \
2125 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2126
2127 #define RETURN_ADDR_RTX mips_return_addr
2128
2129 /* Mask off the MIPS16 ISA bit in unwind addresses.
2130
2131 The reason for this is a little subtle. When unwinding a call,
2132 we are given the call's return address, which on most targets
2133 is the address of the following instruction. However, what we
2134 actually want to find is the EH region for the call itself.
2135 The target-independent unwind code therefore searches for "RA - 1".
2136
2137 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2138 RA - 1 is therefore the real (even-valued) start of the return
2139 instruction. EH region labels are usually odd-valued MIPS16 symbols
2140 too, so a search for an even address within a MIPS16 region would
2141 usually work.
2142
2143 However, there is an exception. If the end of an EH region is also
2144 the end of a function, the end label is allowed to be even. This is
2145 necessary because a following non-MIPS16 function may also need EH
2146 information for its first instruction.
2147
2148 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2149 non-ISA-encoded address. This probably isn't ideal, but it is
2150 the traditional (legacy) behavior. It is therefore only safe
2151 to search MIPS EH regions for an _odd-valued_ address.
2152
2153 Masking off the ISA bit means that the target-independent code
2154 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2155 #define MASK_RETURN_ADDR GEN_INT (-2)
2156
2157
2158 /* Similarly, don't use the least-significant bit to tell pointers to
2159 code from vtable index. */
2160
2161 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2162
2163 /* The eliminations to $17 are only used for mips16 code. See the
2164 definition of HARD_FRAME_POINTER_REGNUM. */
2165
2166 #define ELIMINABLE_REGS \
2167 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2168 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2169 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2170 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2171 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2172 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2173
2174 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2175 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2176
2177 /* Allocate stack space for arguments at the beginning of each function. */
2178 #define ACCUMULATE_OUTGOING_ARGS 1
2179
2180 /* The argument pointer always points to the first argument. */
2181 #define FIRST_PARM_OFFSET(FNDECL) 0
2182
2183 /* o32 and o64 reserve stack space for all argument registers. */
2184 #define REG_PARM_STACK_SPACE(FNDECL) \
2185 (TARGET_OLDABI \
2186 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2187 : 0)
2188
2189 /* Define this if it is the responsibility of the caller to
2190 allocate the area reserved for arguments passed in registers.
2191 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2192 of this macro is to determine whether the space is included in
2193 `crtl->outgoing_args_size'. */
2194 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2195
2196 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2197 \f
2198 /* Symbolic macros for the registers used to return integer and floating
2199 point values. */
2200
2201 #define GP_RETURN (GP_REG_FIRST + 2)
2202 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2203
2204 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2205
2206 /* Symbolic macros for the first/last argument registers. */
2207
2208 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2209 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2210 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2211 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2212
2213 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2214 are used for returning complex double values in soft-float code, so $6 is the
2215 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2216 $gp itself as the temporary. */
2217 #define POST_CALL_TMP_REG \
2218 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2219
2220 /* 1 if N is a possible register number for function argument passing.
2221 We have no FP argument registers when soft-float. When FP registers
2222 are 32 bits, we can't directly reference the odd numbered ones. */
2223
2224 #define FUNCTION_ARG_REGNO_P(N) \
2225 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2226 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2227 && !fixed_regs[N])
2228 \f
2229 /* This structure has to cope with two different argument allocation
2230 schemes. Most MIPS ABIs view the arguments as a structure, of which
2231 the first N words go in registers and the rest go on the stack. If I
2232 < N, the Ith word might go in Ith integer argument register or in a
2233 floating-point register. For these ABIs, we only need to remember
2234 the offset of the current argument into the structure.
2235
2236 The EABI instead allocates the integer and floating-point arguments
2237 separately. The first N words of FP arguments go in FP registers,
2238 the rest go on the stack. Likewise, the first N words of the other
2239 arguments go in integer registers, and the rest go on the stack. We
2240 need to maintain three counts: the number of integer registers used,
2241 the number of floating-point registers used, and the number of words
2242 passed on the stack.
2243
2244 We could keep separate information for the two ABIs (a word count for
2245 the standard ABIs, and three separate counts for the EABI). But it
2246 seems simpler to view the standard ABIs as forms of EABI that do not
2247 allocate floating-point registers.
2248
2249 So for the standard ABIs, the first N words are allocated to integer
2250 registers, and mips_function_arg decides on an argument-by-argument
2251 basis whether that argument should really go in an integer register,
2252 or in a floating-point one. */
2253
2254 typedef struct mips_args {
2255 /* Always true for varargs functions. Otherwise true if at least
2256 one argument has been passed in an integer register. */
2257 int gp_reg_found;
2258
2259 /* The number of arguments seen so far. */
2260 unsigned int arg_number;
2261
2262 /* The number of integer registers used so far. For all ABIs except
2263 EABI, this is the number of words that have been added to the
2264 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2265 unsigned int num_gprs;
2266
2267 /* For EABI, the number of floating-point registers used so far. */
2268 unsigned int num_fprs;
2269
2270 /* The number of words passed on the stack. */
2271 unsigned int stack_words;
2272
2273 /* On the mips16, we need to keep track of which floating point
2274 arguments were passed in general registers, but would have been
2275 passed in the FP regs if this were a 32-bit function, so that we
2276 can move them to the FP regs if we wind up calling a 32-bit
2277 function. We record this information in fp_code, encoded in base
2278 four. A zero digit means no floating point argument, a one digit
2279 means an SFmode argument, and a two digit means a DFmode argument,
2280 and a three digit is not used. The low order digit is the first
2281 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2282 an SFmode argument. ??? A more sophisticated approach will be
2283 needed if MIPS_ABI != ABI_32. */
2284 int fp_code;
2285
2286 /* True if the function has a prototype. */
2287 int prototype;
2288 } CUMULATIVE_ARGS;
2289
2290 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2291 for a call to a function whose data type is FNTYPE.
2292 For a library call, FNTYPE is 0. */
2293
2294 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2295 mips_init_cumulative_args (&CUM, FNTYPE)
2296
2297 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2298 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2299
2300 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2301 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2302
2303 /* True if using EABI and varargs can be passed in floating-point
2304 registers. Under these conditions, we need a more complex form
2305 of va_list, which tracks GPR, FPR and stack arguments separately. */
2306 #define EABI_FLOAT_VARARGS_P \
2307 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2308
2309 \f
2310 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2311
2312 /* Treat LOC as a byte offset from the stack pointer and round it up
2313 to the next fully-aligned offset. */
2314 #define MIPS_STACK_ALIGN(LOC) \
2315 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2316
2317 \f
2318 /* Output assembler code to FILE to increment profiler label # LABELNO
2319 for profiling a function entry. */
2320
2321 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2322
2323 /* The profiler preserves all interesting registers, including $31. */
2324 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2325
2326 /* No mips port has ever used the profiler counter word, so don't emit it
2327 or the label for it. */
2328
2329 #define NO_PROFILE_COUNTERS 1
2330
2331 /* Define this macro if the code for function profiling should come
2332 before the function prologue. Normally, the profiling code comes
2333 after. */
2334
2335 /* #define PROFILE_BEFORE_PROLOGUE */
2336
2337 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2338 the stack pointer does not matter. The value is tested only in
2339 functions that have frame pointers.
2340 No definition is equivalent to always zero. */
2341
2342 #define EXIT_IGNORE_STACK 1
2343
2344 \f
2345 /* Trampolines are a block of code followed by two pointers. */
2346
2347 #define TRAMPOLINE_SIZE \
2348 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2349
2350 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2351 pointers from a single LUI base. */
2352
2353 #define TRAMPOLINE_ALIGNMENT 64
2354
2355 /* mips_trampoline_init calls this library function to flush
2356 program and data caches. */
2357
2358 #ifndef CACHE_FLUSH_FUNC
2359 #define CACHE_FLUSH_FUNC "_flush_cache"
2360 #endif
2361
2362 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2363 /* Flush both caches. We need to flush the data cache in case \
2364 the system has a write-back cache. */ \
2365 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2366 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2367 GEN_INT (3), TYPE_MODE (integer_type_node))
2368
2369 \f
2370 /* Addressing modes, and classification of registers for them. */
2371
2372 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2373 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2374 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2375 \f
2376 /* Maximum number of registers that can appear in a valid memory address. */
2377
2378 #define MAX_REGS_PER_ADDRESS 1
2379
2380 /* Check for constness inline but use mips_legitimate_address_p
2381 to check whether a constant really is an address. */
2382
2383 #define CONSTANT_ADDRESS_P(X) \
2384 (CONSTANT_P (X) && memory_address_p (SImode, X))
2385
2386 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2387 'the start of the function that this code is output in'. */
2388
2389 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2390 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2391 asm_fprintf ((FILE), "%U%s", \
2392 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2393 else \
2394 asm_fprintf ((FILE), "%U%s", (NAME))
2395 \f
2396 /* Flag to mark a function decl symbol that requires a long call. */
2397 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2398 #define SYMBOL_REF_LONG_CALL_P(X) \
2399 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2400
2401 /* This flag marks functions that cannot be lazily bound. */
2402 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2403 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2404 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2405
2406 /* True if we're generating a form of MIPS16 code in which jump tables
2407 are stored in the text section and encoded as 16-bit PC-relative
2408 offsets. This is only possible when general text loads are allowed,
2409 since the table access itself will be an "lh" instruction. If the
2410 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2411 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2412
2413 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2414
2415 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2416
2417 /* Only use short offsets if their range will not overflow. */
2418 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2419 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2420 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2421 : SImode)
2422
2423 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2424
2425 /* Define this as 1 if `char' should by default be signed; else as 0. */
2426 #ifndef DEFAULT_SIGNED_CHAR
2427 #define DEFAULT_SIGNED_CHAR 1
2428 #endif
2429
2430 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2431 we generally don't want to use them for copying arbitrary data.
2432 A single N-word move is usually the same cost as N single-word moves. */
2433 #define MOVE_MAX UNITS_PER_WORD
2434 #define MAX_MOVE_MAX 8
2435
2436 /* Define this macro as a C expression which is nonzero if
2437 accessing less than a word of memory (i.e. a `char' or a
2438 `short') is no faster than accessing a word of memory, i.e., if
2439 such access require more than one instruction or if there is no
2440 difference in cost between byte and (aligned) word loads.
2441
2442 On RISC machines, it tends to generate better code to define
2443 this as 1, since it avoids making a QI or HI mode register.
2444
2445 But, generating word accesses for -mips16 is generally bad as shifts
2446 (often extended) would be needed for byte accesses. */
2447 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2448
2449 /* Standard MIPS integer shifts truncate the shift amount to the
2450 width of the shifted operand. However, Loongson vector shifts
2451 do not truncate the shift amount at all. */
2452 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2453
2454 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2455 is done just by pretending it is already truncated. */
2456 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2457 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2458
2459
2460 /* Specify the machine mode that pointers have.
2461 After generation of rtl, the compiler makes no further distinction
2462 between pointers and any other objects of this machine mode. */
2463
2464 #ifndef Pmode
2465 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2466 #endif
2467
2468 /* Give call MEMs SImode since it is the "most permissive" mode
2469 for both 32-bit and 64-bit targets. */
2470
2471 #define FUNCTION_MODE SImode
2472
2473 \f
2474 /* We allocate $fcc registers by hand and can't cope with moves of
2475 CCmode registers to and from pseudos (or memory). */
2476 #define AVOID_CCMODE_COPIES
2477
2478 /* A C expression for the cost of a branch instruction. A value of
2479 1 is the default; other values are interpreted relative to that. */
2480
2481 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2482 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2483
2484 /* The MIPS port has several functions that return an instruction count.
2485 Multiplying the count by this value gives the number of bytes that
2486 the instructions occupy. */
2487 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2488
2489 /* The length of a NOP in bytes. */
2490 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2491
2492 /* If defined, modifies the length assigned to instruction INSN as a
2493 function of the context in which it is used. LENGTH is an lvalue
2494 that contains the initially computed length of the insn and should
2495 be updated with the correct length of the insn. */
2496 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2497 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2498
2499 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2500 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2501 its operands. */
2502 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2503 "%*" OPCODE "%?\t" OPERANDS "%/"
2504
2505 /* Return an asm string that forces INSN to be treated as an absolute
2506 J or JAL instruction instead of an assembler macro. */
2507 #define MIPS_ABSOLUTE_JUMP(INSN) \
2508 (TARGET_ABICALLS_PIC2 \
2509 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2510 : INSN)
2511
2512 /* Return the asm template for a call. INSN is the instruction's mnemonic
2513 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2514 number of the target. SIZE_OPNO is the operand number of the argument size
2515 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2516 -1 and the call is indirect, use the function symbol from the call
2517 attributes to attach a R_MIPS_JALR relocation to the call.
2518
2519 When generating GOT code without explicit relocation operators,
2520 all calls should use assembly macros. Otherwise, all indirect
2521 calls should use "jr" or "jalr"; we will arrange to restore $gp
2522 afterwards if necessary. Finally, we can only generate direct
2523 calls for -mabicalls by temporarily switching to non-PIC mode.
2524
2525 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2526 instruction is in the delay slot of jal(r). */
2527 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2528 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2529 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2530 : REG_P (OPERANDS[TARGET_OPNO]) \
2531 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2532 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2533 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2534 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2535 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2536 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2537 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2538 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2539 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2540
2541 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2542 "jrc" when nop is in the delay slot of "jr". */
2543
2544 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2545 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2546 ? "%*j\t%" #OPNO "%/" \
2547 : REG_P (OPERANDS[OPNO]) \
2548 ? "%*jr%:\t%" #OPNO \
2549 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2550
2551 \f
2552 /* Control the assembler format that we output. */
2553
2554 /* Output to assembler file text saying following lines
2555 may contain character constants, extra white space, comments, etc. */
2556
2557 #ifndef ASM_APP_ON
2558 #define ASM_APP_ON " #APP\n"
2559 #endif
2560
2561 /* Output to assembler file text saying following lines
2562 no longer contain unusual constructs. */
2563
2564 #ifndef ASM_APP_OFF
2565 #define ASM_APP_OFF " #NO_APP\n"
2566 #endif
2567
2568 #define REGISTER_NAMES \
2569 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2570 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2571 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2572 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2573 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2574 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2575 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2576 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2577 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2578 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2579 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2580 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2581 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2582 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2583 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2584 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2585 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2586 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2587 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2588 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2589 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2590 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2591 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2592 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2593
2594 /* List the "software" names for each register. Also list the numerical
2595 names for $fp and $sp. */
2596
2597 #define ADDITIONAL_REGISTER_NAMES \
2598 { \
2599 { "$29", 29 + GP_REG_FIRST }, \
2600 { "$30", 30 + GP_REG_FIRST }, \
2601 { "at", 1 + GP_REG_FIRST }, \
2602 { "v0", 2 + GP_REG_FIRST }, \
2603 { "v1", 3 + GP_REG_FIRST }, \
2604 { "a0", 4 + GP_REG_FIRST }, \
2605 { "a1", 5 + GP_REG_FIRST }, \
2606 { "a2", 6 + GP_REG_FIRST }, \
2607 { "a3", 7 + GP_REG_FIRST }, \
2608 { "t0", 8 + GP_REG_FIRST }, \
2609 { "t1", 9 + GP_REG_FIRST }, \
2610 { "t2", 10 + GP_REG_FIRST }, \
2611 { "t3", 11 + GP_REG_FIRST }, \
2612 { "t4", 12 + GP_REG_FIRST }, \
2613 { "t5", 13 + GP_REG_FIRST }, \
2614 { "t6", 14 + GP_REG_FIRST }, \
2615 { "t7", 15 + GP_REG_FIRST }, \
2616 { "s0", 16 + GP_REG_FIRST }, \
2617 { "s1", 17 + GP_REG_FIRST }, \
2618 { "s2", 18 + GP_REG_FIRST }, \
2619 { "s3", 19 + GP_REG_FIRST }, \
2620 { "s4", 20 + GP_REG_FIRST }, \
2621 { "s5", 21 + GP_REG_FIRST }, \
2622 { "s6", 22 + GP_REG_FIRST }, \
2623 { "s7", 23 + GP_REG_FIRST }, \
2624 { "t8", 24 + GP_REG_FIRST }, \
2625 { "t9", 25 + GP_REG_FIRST }, \
2626 { "k0", 26 + GP_REG_FIRST }, \
2627 { "k1", 27 + GP_REG_FIRST }, \
2628 { "gp", 28 + GP_REG_FIRST }, \
2629 { "sp", 29 + GP_REG_FIRST }, \
2630 { "fp", 30 + GP_REG_FIRST }, \
2631 { "ra", 31 + GP_REG_FIRST } \
2632 }
2633
2634 #define DBR_OUTPUT_SEQEND(STREAM) \
2635 do \
2636 { \
2637 /* Undo the effect of '%*'. */ \
2638 mips_pop_asm_switch (&mips_nomacro); \
2639 mips_pop_asm_switch (&mips_noreorder); \
2640 /* Emit a blank line after the delay slot for emphasis. */ \
2641 fputs ("\n", STREAM); \
2642 } \
2643 while (0)
2644
2645 /* The MIPS implementation uses some labels for its own purpose. The
2646 following lists what labels are created, and are all formed by the
2647 pattern $L[a-z].*. The machine independent portion of GCC creates
2648 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2649
2650 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2651 $Lb[0-9]+ Begin blocks for MIPS debug support
2652 $Lc[0-9]+ Label for use in s<xx> operation.
2653 $Le[0-9]+ End blocks for MIPS debug support */
2654
2655 #undef ASM_DECLARE_OBJECT_NAME
2656 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2657 mips_declare_object (STREAM, NAME, "", ":\n")
2658
2659 /* Globalizing directive for a label. */
2660 #define GLOBAL_ASM_OP "\t.globl\t"
2661
2662 /* This says how to define a global common symbol. */
2663
2664 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2665
2666 /* This says how to define a local common symbol (i.e., not visible to
2667 linker). */
2668
2669 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2670 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2671 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2672 #endif
2673
2674 /* This says how to output an external. It would be possible not to
2675 output anything and let undefined symbol become external. However
2676 the assembler uses length information on externals to allocate in
2677 data/sdata bss/sbss, thereby saving exec time. */
2678
2679 #undef ASM_OUTPUT_EXTERNAL
2680 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2681 mips_output_external(STREAM,DECL,NAME)
2682
2683 /* This is how to declare a function name. The actual work of
2684 emitting the label is moved to function_prologue, so that we can
2685 get the line number correctly emitted before the .ent directive,
2686 and after any .file directives. Define as empty so that the function
2687 is not declared before the .ent directive elsewhere. */
2688
2689 #undef ASM_DECLARE_FUNCTION_NAME
2690 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2691
2692 /* This is how to store into the string LABEL
2693 the symbol_ref name of an internal numbered label where
2694 PREFIX is the class of label and NUM is the number within the class.
2695 This is suitable for output with `assemble_name'. */
2696
2697 #undef ASM_GENERATE_INTERNAL_LABEL
2698 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2699 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2700
2701 /* Print debug labels as "foo = ." rather than "foo:" because they should
2702 represent a byte pointer rather than an ISA-encoded address. This is
2703 particularly important for code like:
2704
2705 $LFBxxx = .
2706 .cfi_startproc
2707 ...
2708 .section .gcc_except_table,...
2709 ...
2710 .uleb128 foo-$LFBxxx
2711
2712 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2713 likewise a byte pointer rather than an ISA-encoded address.
2714
2715 At the time of writing, this hook is not used for the function end
2716 label:
2717
2718 $LFExxx:
2719 .end foo
2720
2721 But this doesn't matter, because GAS doesn't treat a pre-.end label
2722 as a MIPS16 one anyway. */
2723
2724 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2725 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2726
2727 /* This is how to output an element of a case-vector that is absolute. */
2728
2729 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2730 fprintf (STREAM, "\t%s\t%sL%d\n", \
2731 ptr_mode == DImode ? ".dword" : ".word", \
2732 LOCAL_LABEL_PREFIX, \
2733 VALUE)
2734
2735 /* This is how to output an element of a case-vector. We can make the
2736 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2737 is supported. */
2738
2739 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2740 do { \
2741 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2742 { \
2743 if (GET_MODE (BODY) == HImode) \
2744 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2745 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2746 else \
2747 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2748 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2749 } \
2750 else if (TARGET_GPWORD) \
2751 fprintf (STREAM, "\t%s\t%sL%d\n", \
2752 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2753 LOCAL_LABEL_PREFIX, VALUE); \
2754 else if (TARGET_RTP_PIC) \
2755 { \
2756 /* Make the entry relative to the start of the function. */ \
2757 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2758 fprintf (STREAM, "\t%s\t%sL%d-", \
2759 Pmode == DImode ? ".dword" : ".word", \
2760 LOCAL_LABEL_PREFIX, VALUE); \
2761 assemble_name (STREAM, XSTR (fnsym, 0)); \
2762 fprintf (STREAM, "\n"); \
2763 } \
2764 else \
2765 fprintf (STREAM, "\t%s\t%sL%d\n", \
2766 ptr_mode == DImode ? ".dword" : ".word", \
2767 LOCAL_LABEL_PREFIX, VALUE); \
2768 } while (0)
2769
2770 /* This is how to output an assembler line
2771 that says to advance the location counter
2772 to a multiple of 2**LOG bytes. */
2773
2774 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2775 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2776
2777 /* This is how to output an assembler line to advance the location
2778 counter by SIZE bytes. */
2779
2780 #undef ASM_OUTPUT_SKIP
2781 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2782 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2783
2784 /* This is how to output a string. */
2785 #undef ASM_OUTPUT_ASCII
2786 #define ASM_OUTPUT_ASCII mips_output_ascii
2787
2788 \f
2789 /* Default to -G 8 */
2790 #ifndef MIPS_DEFAULT_GVALUE
2791 #define MIPS_DEFAULT_GVALUE 8
2792 #endif
2793
2794 /* Define the strings to put out for each section in the object file. */
2795 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2796 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2797
2798 #undef READONLY_DATA_SECTION_ASM_OP
2799 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2800 \f
2801 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2802 do \
2803 { \
2804 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2805 TARGET_64BIT ? "daddiu" : "addiu", \
2806 reg_names[STACK_POINTER_REGNUM], \
2807 reg_names[STACK_POINTER_REGNUM], \
2808 TARGET_64BIT ? "sd" : "sw", \
2809 reg_names[REGNO], \
2810 reg_names[STACK_POINTER_REGNUM]); \
2811 } \
2812 while (0)
2813
2814 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2815 do \
2816 { \
2817 mips_push_asm_switch (&mips_noreorder); \
2818 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2819 TARGET_64BIT ? "ld" : "lw", \
2820 reg_names[REGNO], \
2821 reg_names[STACK_POINTER_REGNUM], \
2822 TARGET_64BIT ? "daddu" : "addu", \
2823 reg_names[STACK_POINTER_REGNUM], \
2824 reg_names[STACK_POINTER_REGNUM]); \
2825 mips_pop_asm_switch (&mips_noreorder); \
2826 } \
2827 while (0)
2828
2829 /* How to start an assembler comment.
2830 The leading space is important (the mips native assembler requires it). */
2831 #ifndef ASM_COMMENT_START
2832 #define ASM_COMMENT_START " #"
2833 #endif
2834 \f
2835 #undef SIZE_TYPE
2836 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2837
2838 #undef PTRDIFF_TYPE
2839 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2840
2841 /* The maximum number of bytes that can be copied by one iteration of
2842 a movmemsi loop; see mips_block_move_loop. */
2843 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2844 (UNITS_PER_WORD * 4)
2845
2846 /* The maximum number of bytes that can be copied by a straight-line
2847 implementation of movmemsi; see mips_block_move_straight. We want
2848 to make sure that any loop-based implementation will iterate at
2849 least twice. */
2850 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2851 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2852
2853 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2854 values were determined experimentally by benchmarking with CSiBE.
2855 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2856 for o32 where we have to restore $gp afterwards as well as make an
2857 indirect call), but in practice, bumping this up higher for
2858 TARGET_ABICALLS doesn't make much difference to code size. */
2859
2860 #define MIPS_CALL_RATIO 8
2861
2862 /* Any loop-based implementation of movmemsi will have at least
2863 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2864 moves, so allow individual copies of fewer elements.
2865
2866 When movmemsi is not available, use a value approximating
2867 the length of a memcpy call sequence, so that move_by_pieces
2868 will generate inline code if it is shorter than a function call.
2869 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2870 we'll have to generate a load/store pair for each, halve the
2871 value of MIPS_CALL_RATIO to take that into account. */
2872
2873 #define MOVE_RATIO(speed) \
2874 (HAVE_movmemsi \
2875 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2876 : MIPS_CALL_RATIO / 2)
2877
2878 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2879 of the length of a memset call, but use the default otherwise. */
2880
2881 #define CLEAR_RATIO(speed)\
2882 ((speed) ? 15 : MIPS_CALL_RATIO)
2883
2884 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2885 optimizing for size adjust the ratio to account for the overhead of
2886 loading the constant and replicating it across the word. */
2887
2888 #define SET_RATIO(speed) \
2889 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2890 \f
2891 /* Since the bits of the _init and _fini function is spread across
2892 many object files, each potentially with its own GP, we must assume
2893 we need to load our GP. We don't preserve $gp or $ra, since each
2894 init/fini chunk is supposed to initialize $gp, and crti/crtn
2895 already take care of preserving $ra and, when appropriate, $gp. */
2896 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2897 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2898 asm (SECTION_OP "\n\
2899 .set push\n\
2900 .set nomips16\n\
2901 .set noreorder\n\
2902 bal 1f\n\
2903 nop\n\
2904 1: .cpload $31\n\
2905 .set reorder\n\
2906 jal " USER_LABEL_PREFIX #FUNC "\n\
2907 .set pop\n\
2908 " TEXT_SECTION_ASM_OP);
2909 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2910 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2911 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2912 asm (SECTION_OP "\n\
2913 .set push\n\
2914 .set nomips16\n\
2915 .set noreorder\n\
2916 bal 1f\n\
2917 nop\n\
2918 1: .set reorder\n\
2919 .cpsetup $31, $2, 1b\n\
2920 jal " USER_LABEL_PREFIX #FUNC "\n\
2921 .set pop\n\
2922 " TEXT_SECTION_ASM_OP);
2923 #endif
2924
2925 #ifndef HAVE_AS_TLS
2926 #define HAVE_AS_TLS 0
2927 #endif
2928
2929 #ifndef HAVE_AS_NAN
2930 #define HAVE_AS_NAN 0
2931 #endif
2932
2933 #ifndef USED_FOR_TARGET
2934 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2935 struct mips_asm_switch {
2936 /* The FOO in the description above. */
2937 const char *name;
2938
2939 /* The current block nesting level, or 0 if we aren't in a block. */
2940 int nesting_level;
2941 };
2942
2943 extern const enum reg_class mips_regno_to_class[];
2944 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2945 extern const char *current_function_file; /* filename current function is in */
2946 extern int num_source_filenames; /* current .file # */
2947 extern struct mips_asm_switch mips_noreorder;
2948 extern struct mips_asm_switch mips_nomacro;
2949 extern struct mips_asm_switch mips_noat;
2950 extern int mips_dbx_regno[];
2951 extern int mips_dwarf_regno[];
2952 extern bool mips_split_p[];
2953 extern bool mips_split_hi_p[];
2954 extern bool mips_use_pcrel_pool_p[];
2955 extern const char *mips_lo_relocs[];
2956 extern const char *mips_hi_relocs[];
2957 extern enum processor mips_arch; /* which cpu to codegen for */
2958 extern enum processor mips_tune; /* which cpu to schedule for */
2959 extern int mips_isa; /* architectural level */
2960 extern int mips_isa_rev;
2961 extern const struct mips_cpu_info *mips_arch_info;
2962 extern const struct mips_cpu_info *mips_tune_info;
2963 extern unsigned int mips_base_compression_flags;
2964 extern GTY(()) struct target_globals *mips16_globals;
2965 #endif
2966
2967 /* Enable querying of DFA units. */
2968 #define CPU_UNITS_QUERY 1
2969
2970 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2971 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2972
2973 /* As on most targets, we want the .eh_frame section to be read-only where
2974 possible. And as on most targets, this means two things:
2975
2976 (a) Non-locally-binding pointers must have an indirect encoding,
2977 so that the addresses in the .eh_frame section itself become
2978 locally-binding.
2979
2980 (b) A shared library's .eh_frame section must encode locally-binding
2981 pointers in a relative (relocation-free) form.
2982
2983 However, MIPS has traditionally not allowed directives like:
2984
2985 .long x-.
2986
2987 in cases where "x" is in a different section, or is not defined in the
2988 same assembly file. We are therefore unable to emit the PC-relative
2989 form required by (b) at assembly time.
2990
2991 Fortunately, the linker is able to convert absolute addresses into
2992 PC-relative addresses on our behalf. Unfortunately, only certain
2993 versions of the linker know how to do this for indirect pointers,
2994 and for personality data. We must fall back on using writable
2995 .eh_frame sections for shared libraries if the linker does not
2996 support this feature. */
2997 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2998 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2999
3000 /* For switching between MIPS16 and non-MIPS16 modes. */
3001 #define SWITCHABLE_TARGET 1
3002
3003 /* Several named MIPS patterns depend on Pmode. These patterns have the
3004 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3005 Add the appropriate suffix to generator function NAME and invoke it
3006 with arguments ARGS. */
3007 #define PMODE_INSN(NAME, ARGS) \
3008 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3009
3010 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3011 need to change these from /lib and /usr/lib. */
3012 #if MIPS_ABI_DEFAULT == ABI_N32
3013 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3014 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3015 #elif MIPS_ABI_DEFAULT == ABI_64
3016 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3017 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3018 #endif
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