1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
76 ;; 13 This is a `eh_return' placeholder.
78 ;; For SSE/MMX support:
79 ;; 30 This is `fix', guaranteed to be truncating.
80 ;; 31 This is a `emms' operation.
81 ;; 32 This is a `maskmov' operation.
82 ;; 33 This is a `movmsk' operation.
83 ;; 34 This is a `non-temporal' move.
84 ;; 35 This is a `prefetch' operation.
85 ;; 36 This is used to distinguish COMISS from UCOMISS.
86 ;; 37 This is a `ldmxcsr' operation.
87 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
88 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
89 ;; 40 This is a `stmxcsr' operation.
90 ;; 41 This is a `shuffle' operation.
91 ;; 42 This is a `rcp' operation.
92 ;; 43 This is a `rsqsrt' operation.
93 ;; 44 This is a `sfence' operation.
94 ;; 45 This is a noop to prevent excessive combiner cleverness.
96 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
100 ;; Processor type. This attribute must exactly match the processor_type
101 ;; enumeration in i386.h.
102 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
103 (const (symbol_ref "ix86_cpu")))
105 ;; A basic instruction type. Refinements due to arguments to be
106 ;; provided in other attributes.
108 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx"
109 (const_string "other"))
111 ;; Main data type used by the insn
112 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
113 (const_string "unknown"))
115 ;; Set for i387 operations.
116 (define_attr "i387" ""
117 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
121 ;; The (bounding maximum) length of an instruction immediate.
122 (define_attr "length_immediate" ""
123 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
127 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
128 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
129 (eq_attr "type" "imov,test")
130 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
131 (eq_attr "type" "call")
132 (if_then_else (match_operand 0 "constant_call_address_operand" "")
135 (eq_attr "type" "callv")
136 (if_then_else (match_operand 1 "constant_call_address_operand" "")
139 (eq_attr "type" "ibr")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
142 (lt (minus (match_dup 0) (pc))
147 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
149 ;; The (bounding maximum) length of an instruction address.
150 (define_attr "length_address" ""
151 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
153 (and (eq_attr "type" "call")
154 (match_operand 1 "constant_call_address_operand" ""))
156 (and (eq_attr "type" "callv")
157 (match_operand 1 "constant_call_address_operand" ""))
160 (symbol_ref "ix86_attr_length_address_default (insn)")))
162 ;; Set when length prefix is used.
163 (define_attr "prefix_data16" ""
164 (if_then_else (eq_attr "mode" "HI")
168 ;; Set when string REP prefix is used.
169 (define_attr "prefix_rep" "" (const_int 0))
171 ;; Set when 0f opcode prefix is used.
172 (define_attr "prefix_0f" ""
173 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
177 ;; Set when modrm byte is used.
178 (define_attr "modrm" ""
179 (cond [(eq_attr "type" "str,cld")
183 (and (eq_attr "type" "incdec")
184 (ior (match_operand:SI 1 "register_operand" "")
185 (match_operand:HI 1 "register_operand" "")))
187 (and (eq_attr "type" "push")
188 (not (match_operand 1 "memory_operand" "")))
190 (and (eq_attr "type" "pop")
191 (not (match_operand 0 "memory_operand" "")))
193 (and (eq_attr "type" "imov")
194 (and (match_operand 0 "register_operand" "")
195 (match_operand 1 "immediate_operand" "")))
200 ;; The (bounding maximum) length of an instruction in bytes.
201 (define_attr "length" ""
202 (cond [(eq_attr "type" "other,multi")
205 (plus (plus (attr "modrm")
206 (plus (attr "prefix_0f")
209 (plus (attr "prefix_rep")
210 (plus (attr "prefix_data16")
211 (plus (attr "length_immediate")
212 (attr "length_address")))))))
214 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
215 ;; `store' if there is a simple memory reference therein, or `unknown'
216 ;; if the instruction is complex.
218 (define_attr "memory" "none,load,store,both,unknown"
219 (cond [(eq_attr "type" "other,multi,str")
220 (const_string "unknown")
221 (eq_attr "type" "lea,fcmov,fpspc,cld")
222 (const_string "none")
223 (eq_attr "type" "push")
224 (if_then_else (match_operand 1 "memory_operand" "")
225 (const_string "both")
226 (const_string "store"))
227 (eq_attr "type" "pop,setcc")
228 (if_then_else (match_operand 0 "memory_operand" "")
229 (const_string "both")
230 (const_string "load"))
231 (eq_attr "type" "icmp,test")
232 (if_then_else (ior (match_operand 0 "memory_operand" "")
233 (match_operand 1 "memory_operand" ""))
234 (const_string "load")
235 (const_string "none"))
236 (eq_attr "type" "ibr")
237 (if_then_else (match_operand 0 "memory_operand" "")
238 (const_string "load")
239 (const_string "none"))
240 (eq_attr "type" "call")
241 (if_then_else (match_operand 0 "constant_call_address_operand" "")
242 (const_string "none")
243 (const_string "load"))
244 (eq_attr "type" "callv")
245 (if_then_else (match_operand 1 "constant_call_address_operand" "")
246 (const_string "none")
247 (const_string "load"))
248 (and (eq_attr "type" "alu1,negnot")
249 (match_operand 1 "memory_operand" ""))
250 (const_string "both")
251 (and (match_operand 0 "memory_operand" "")
252 (match_operand 1 "memory_operand" ""))
253 (const_string "both")
254 (match_operand 0 "memory_operand" "")
255 (const_string "store")
256 (match_operand 1 "memory_operand" "")
257 (const_string "load")
258 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
259 (match_operand 2 "memory_operand" ""))
260 (const_string "load")
261 (and (eq_attr "type" "icmov")
262 (match_operand 3 "memory_operand" ""))
263 (const_string "load")
265 (const_string "none")))
267 ;; Indicates if an instruction has both an immediate and a displacement.
269 (define_attr "imm_disp" "false,true,unknown"
270 (cond [(eq_attr "type" "other,multi")
271 (const_string "unknown")
272 (and (eq_attr "type" "icmp,test,imov")
273 (and (match_operand 0 "memory_displacement_operand" "")
274 (match_operand 1 "immediate_operand" "")))
275 (const_string "true")
276 (and (eq_attr "type" "alu,ishift,imul,idiv")
277 (and (match_operand 0 "memory_displacement_operand" "")
278 (match_operand 2 "immediate_operand" "")))
279 (const_string "true")
281 (const_string "false")))
283 ;; Indicates if an FP operation has an integer source.
285 (define_attr "fp_int_src" "false,true"
286 (const_string "false"))
288 ;; Describe a user's asm statement.
289 (define_asm_attributes
290 [(set_attr "length" "128")
291 (set_attr "type" "multi")])
293 ;; Pentium Scheduling
295 ;; The Pentium is an in-order core with two integer pipelines.
297 ;; True for insns that behave like prefixed insns on the Pentium.
298 (define_attr "pent_prefix" "false,true"
299 (if_then_else (ior (eq_attr "prefix_0f" "1")
300 (ior (eq_attr "prefix_data16" "1")
301 (eq_attr "prefix_rep" "1")))
302 (const_string "true")
303 (const_string "false")))
305 ;; Categorize how an instruction slots.
307 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
308 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
309 ;; rules, because it results in noticeably better code on non-MMX Pentium
310 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
311 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
313 (define_attr "pent_pair" "uv,pu,pv,np"
314 (cond [(eq_attr "imm_disp" "true")
316 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
317 (and (eq_attr "type" "pop,push")
318 (eq_attr "memory" "!both")))
319 (if_then_else (eq_attr "pent_prefix" "true")
322 (eq_attr "type" "ibr")
324 (and (eq_attr "type" "ishift")
325 (match_operand 2 "const_int_operand" ""))
327 (and (eq_attr "type" "call")
328 (match_operand 0 "constant_call_address_operand" ""))
330 (and (eq_attr "type" "callv")
331 (match_operand 1 "constant_call_address_operand" ""))
334 (const_string "np")))
336 ;; Rough readiness numbers. Fine tuning happens in i386.c.
338 ;; u describes pipe U
339 ;; v describes pipe V
340 ;; uv describes either pipe U or V for those that can issue to either
341 ;; np describes not paring
343 ;; fpm describes fp insns of different types are not pipelined.
345 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
347 (define_function_unit "pent_np" 1 0
348 (and (eq_attr "cpu" "pentium")
349 (eq_attr "type" "imul"))
352 (define_function_unit "pent_mul" 1 1
353 (and (eq_attr "cpu" "pentium")
354 (eq_attr "type" "imul"))
357 ;; Rep movs takes minimally 12 cycles.
358 (define_function_unit "pent_np" 1 0
359 (and (eq_attr "cpu" "pentium")
360 (eq_attr "type" "str"))
363 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
364 (define_function_unit "pent_np" 1 0
365 (and (eq_attr "cpu" "pentium")
366 (eq_attr "type" "idiv"))
369 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
370 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
371 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
372 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
373 ; like normal fp operation and fist takes 6 cycles.
375 (define_function_unit "fpu" 1 0
376 (and (eq_attr "cpu" "pentium")
377 (and (eq_attr "type" "fmov")
378 (and (eq_attr "memory" "load,store")
379 (eq_attr "mode" "XF"))))
382 (define_function_unit "pent_np" 1 0
383 (and (eq_attr "cpu" "pentium")
384 (and (eq_attr "type" "fmov")
385 (and (eq_attr "memory" "load,store")
386 (eq_attr "mode" "XF"))))
389 (define_function_unit "fpu" 1 0
390 (and (eq_attr "cpu" "pentium")
391 (and (eq_attr "type" "fmov")
392 (ior (match_operand 1 "immediate_operand" "")
393 (eq_attr "memory" "store"))))
396 (define_function_unit "pent_np" 1 0
397 (and (eq_attr "cpu" "pentium")
398 (and (eq_attr "type" "fmov")
399 (ior (match_operand 1 "immediate_operand" "")
400 (eq_attr "memory" "store"))))
403 (define_function_unit "pent_np" 1 0
404 (and (eq_attr "cpu" "pentium")
405 (eq_attr "type" "cld"))
408 (define_function_unit "fpu" 1 0
409 (and (eq_attr "cpu" "pentium")
410 (and (eq_attr "type" "fmov")
411 (eq_attr "memory" "none,load")))
414 ; Read/Modify/Write instructions usually take 3 cycles.
415 (define_function_unit "pent_u" 1 0
416 (and (eq_attr "cpu" "pentium")
417 (and (eq_attr "type" "alu,alu1,ishift")
418 (and (eq_attr "pent_pair" "pu")
419 (eq_attr "memory" "both"))))
422 (define_function_unit "pent_uv" 2 0
423 (and (eq_attr "cpu" "pentium")
424 (and (eq_attr "type" "alu,alu1,ishift")
425 (and (eq_attr "pent_pair" "!np")
426 (eq_attr "memory" "both"))))
429 (define_function_unit "pent_np" 1 0
430 (and (eq_attr "cpu" "pentium")
431 (and (eq_attr "type" "alu,alu1,negnot,ishift")
432 (and (eq_attr "pent_pair" "np")
433 (eq_attr "memory" "both"))))
436 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
437 (define_function_unit "pent_u" 1 0
438 (and (eq_attr "cpu" "pentium")
439 (and (eq_attr "type" "alu,ishift")
440 (and (eq_attr "pent_pair" "pu")
441 (eq_attr "memory" "load,store"))))
444 (define_function_unit "pent_uv" 2 0
445 (and (eq_attr "cpu" "pentium")
446 (and (eq_attr "type" "alu,ishift")
447 (and (eq_attr "pent_pair" "!np")
448 (eq_attr "memory" "load,store"))))
451 (define_function_unit "pent_np" 1 0
452 (and (eq_attr "cpu" "pentium")
453 (and (eq_attr "type" "alu,ishift")
454 (and (eq_attr "pent_pair" "np")
455 (eq_attr "memory" "load,store"))))
458 ; Insns w/o memory operands and move instructions usually take one cycle.
459 (define_function_unit "pent_u" 1 0
460 (and (eq_attr "cpu" "pentium")
461 (eq_attr "pent_pair" "pu"))
464 (define_function_unit "pent_v" 1 0
465 (and (eq_attr "cpu" "pentium")
466 (eq_attr "pent_pair" "pv"))
469 (define_function_unit "pent_uv" 2 0
470 (and (eq_attr "cpu" "pentium")
471 (eq_attr "pent_pair" "!np"))
474 (define_function_unit "pent_np" 1 0
475 (and (eq_attr "cpu" "pentium")
476 (eq_attr "pent_pair" "np"))
479 ; Pairable insns only conflict with other non-pairable insns.
480 (define_function_unit "pent_np" 1 0
481 (and (eq_attr "cpu" "pentium")
482 (and (eq_attr "type" "alu,alu1,ishift")
483 (and (eq_attr "pent_pair" "!np")
484 (eq_attr "memory" "both"))))
486 [(eq_attr "pent_pair" "np")])
488 (define_function_unit "pent_np" 1 0
489 (and (eq_attr "cpu" "pentium")
490 (and (eq_attr "type" "alu,alu1,ishift")
491 (and (eq_attr "pent_pair" "!np")
492 (eq_attr "memory" "load,store"))))
494 [(eq_attr "pent_pair" "np")])
496 (define_function_unit "pent_np" 1 0
497 (and (eq_attr "cpu" "pentium")
498 (eq_attr "pent_pair" "!np"))
500 [(eq_attr "pent_pair" "np")])
502 ; Floating point instructions usually blocks cycle longer when combined with
503 ; integer instructions, because of the inpaired fxch instruction.
504 (define_function_unit "pent_np" 1 0
505 (and (eq_attr "cpu" "pentium")
506 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp"))
508 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp")])
510 (define_function_unit "fpu" 1 0
511 (and (eq_attr "cpu" "pentium")
512 (eq_attr "type" "fcmp,fxch,fsgn"))
515 ; Addition takes 3 cycles; assume other random cruft does as well.
516 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
517 (define_function_unit "fpu" 1 0
518 (and (eq_attr "cpu" "pentium")
519 (eq_attr "type" "fop,fop1"))
522 ; Multiplication takes 3 cycles and is only half pipelined.
523 (define_function_unit "fpu" 1 0
524 (and (eq_attr "cpu" "pentium")
525 (eq_attr "type" "fmul"))
528 (define_function_unit "pent_mul" 1 1
529 (and (eq_attr "cpu" "pentium")
530 (eq_attr "type" "fmul"))
533 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
534 ; They can overlap with integer insns. Only the last two cycles can overlap
535 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
536 ; Only last two cycles of fsin/fcos can overlap with other instructions.
537 (define_function_unit "fpu" 1 0
538 (and (eq_attr "cpu" "pentium")
539 (eq_attr "type" "fdiv"))
542 (define_function_unit "pent_mul" 1 1
543 (and (eq_attr "cpu" "pentium")
544 (eq_attr "type" "fdiv"))
547 (define_function_unit "fpu" 1 0
548 (and (eq_attr "cpu" "pentium")
549 (eq_attr "type" "fpspc"))
552 (define_function_unit "pent_mul" 1 1
553 (and (eq_attr "cpu" "pentium")
554 (eq_attr "type" "fpspc"))
557 ;; Pentium Pro/PII Scheduling
559 ;; The PPro has an out-of-order core, but the instruction decoders are
560 ;; naturally in-order and asymmetric. We get best performance by scheduling
561 ;; for the decoders, for in doing so we give the oo execution unit the
564 ;; Categorize how many uops an ia32 instruction evaluates to:
565 ;; one -- an instruction with 1 uop can be decoded by any of the
567 ;; few -- an instruction with 1 to 4 uops can be decoded only by
569 ;; many -- a complex instruction may take an unspecified number of
570 ;; cycles to decode in decoder 0.
572 (define_attr "ppro_uops" "one,few,many"
573 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
574 (const_string "many")
575 (eq_attr "type" "icmov,fcmov,str,cld")
577 (eq_attr "type" "imov")
578 (if_then_else (eq_attr "memory" "store,both")
580 (const_string "one"))
581 (eq_attr "memory" "!none")
584 (const_string "one")))
586 ;; Rough readiness numbers. Fine tuning happens in i386.c.
588 ;; p0 describes port 0.
589 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
590 ;; p2 describes port 2 for loads.
591 ;; p34 describes ports 3 and 4 for stores.
592 ;; fpu describes the fpu accessed via port 0.
593 ;; ??? It is less than clear if there are separate fadd and fmul units
594 ;; that could operate in parallel.
596 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
598 (define_function_unit "ppro_p0" 1 0
599 (and (eq_attr "cpu" "pentiumpro")
600 (eq_attr "type" "ishift,lea,ibr,cld"))
603 (define_function_unit "ppro_p0" 1 0
604 (and (eq_attr "cpu" "pentiumpro")
605 (eq_attr "type" "imul"))
608 ;; ??? Does the divider lock out the pipe while it works,
609 ;; or is there a disconnected unit?
610 (define_function_unit "ppro_p0" 1 0
611 (and (eq_attr "cpu" "pentiumpro")
612 (eq_attr "type" "idiv"))
615 (define_function_unit "ppro_p0" 1 0
616 (and (eq_attr "cpu" "pentiumpro")
617 (eq_attr "type" "fop,fop1,fsgn"))
620 (define_function_unit "ppro_p0" 1 0
621 (and (eq_attr "cpu" "pentiumpro")
622 (eq_attr "type" "fcmov"))
625 (define_function_unit "ppro_p0" 1 0
626 (and (eq_attr "cpu" "pentiumpro")
627 (eq_attr "type" "fcmp"))
630 (define_function_unit "ppro_p0" 1 0
631 (and (eq_attr "cpu" "pentiumpro")
632 (eq_attr "type" "fmov"))
635 (define_function_unit "ppro_p0" 1 0
636 (and (eq_attr "cpu" "pentiumpro")
637 (eq_attr "type" "fmul"))
640 (define_function_unit "ppro_p0" 1 0
641 (and (eq_attr "cpu" "pentiumpro")
642 (eq_attr "type" "fdiv,fpspc"))
645 (define_function_unit "ppro_p01" 2 0
646 (and (eq_attr "cpu" "pentiumpro")
647 (eq_attr "type" "!imov,fmov"))
650 (define_function_unit "ppro_p01" 2 0
651 (and (and (eq_attr "cpu" "pentiumpro")
652 (eq_attr "type" "imov,fmov"))
653 (eq_attr "memory" "none"))
656 (define_function_unit "ppro_p2" 1 0
657 (and (eq_attr "cpu" "pentiumpro")
658 (ior (eq_attr "type" "pop")
659 (eq_attr "memory" "load,both")))
662 (define_function_unit "ppro_p34" 1 0
663 (and (eq_attr "cpu" "pentiumpro")
664 (ior (eq_attr "type" "push")
665 (eq_attr "memory" "store,both")))
668 (define_function_unit "fpu" 1 0
669 (and (eq_attr "cpu" "pentiumpro")
670 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov"))
673 (define_function_unit "fpu" 1 0
674 (and (eq_attr "cpu" "pentiumpro")
675 (eq_attr "type" "fmul"))
678 (define_function_unit "fpu" 1 0
679 (and (eq_attr "cpu" "pentiumpro")
680 (eq_attr "type" "fdiv,fpspc"))
683 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
684 (define_function_unit "fpu" 1 0
685 (and (eq_attr "cpu" "pentiumpro")
686 (eq_attr "type" "imul"))
689 ;; AMD K6/K6-2 Scheduling
691 ;; The K6 has similar architecture to PPro. Important difference is, that
692 ;; there are only two decoders and they seems to be much slower than execution
693 ;; units. So we have to pay much more attention to proper decoding for
694 ;; schedulers. We share most of scheduler code for PPro in i386.c
696 ;; The fp unit is not pipelined and do one operation per two cycles including
699 ;; alu describes both ALU units (ALU-X and ALU-Y).
700 ;; alux describes X alu unit
701 ;; fpu describes FPU unit
702 ;; load describes load unit.
703 ;; branch describes branch unit.
704 ;; store decsribes store unit. This unit is not modelled completely and only
705 ;; used to model lea operation. Otherwise it lie outside of the critical
708 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
710 ;; The decoder specification is in the PPro section above!
712 ;; Shift instructions and certain arithmetic are issued only to X pipe.
713 (define_function_unit "k6_alux" 1 0
714 (and (eq_attr "cpu" "k6")
715 (eq_attr "type" "ishift,alu1,negnot,cld"))
718 ;; The QI mode arithmetic is issued to X pipe only.
719 (define_function_unit "k6_alux" 1 0
720 (and (eq_attr "cpu" "k6")
721 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
722 (match_operand:QI 0 "general_operand" "")))
725 (define_function_unit "k6_alu" 2 0
726 (and (eq_attr "cpu" "k6")
727 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
730 (define_function_unit "k6_alu" 2 0
731 (and (eq_attr "cpu" "k6")
732 (and (eq_attr "type" "imov")
733 (eq_attr "memory" "none")))
736 (define_function_unit "k6_branch" 1 0
737 (and (eq_attr "cpu" "k6")
738 (eq_attr "type" "call,callv,ibr"))
741 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
742 (define_function_unit "k6_load" 1 0
743 (and (eq_attr "cpu" "k6")
744 (ior (eq_attr "type" "pop")
745 (eq_attr "memory" "load,both")))
748 (define_function_unit "k6_load" 1 0
749 (and (eq_attr "cpu" "k6")
750 (and (eq_attr "type" "str")
751 (eq_attr "memory" "load,both")))
754 ;; Lea have two instructions, so latency is probably 2
755 (define_function_unit "k6_store" 1 0
756 (and (eq_attr "cpu" "k6")
757 (eq_attr "type" "lea"))
760 (define_function_unit "k6_store" 1 0
761 (and (eq_attr "cpu" "k6")
762 (eq_attr "type" "str"))
765 (define_function_unit "k6_store" 1 0
766 (and (eq_attr "cpu" "k6")
767 (ior (eq_attr "type" "push")
768 (eq_attr "memory" "store,both")))
771 (define_function_unit "k6_fpu" 1 1
772 (and (eq_attr "cpu" "k6")
773 (eq_attr "type" "fop,fop1,fmov,fcmp"))
776 (define_function_unit "k6_fpu" 1 1
777 (and (eq_attr "cpu" "k6")
778 (eq_attr "type" "fmul"))
782 (define_function_unit "k6_fpu" 1 1
783 (and (eq_attr "cpu" "k6")
784 (eq_attr "type" "fdiv,fpspc"))
787 (define_function_unit "k6_alu" 2 0
788 (and (eq_attr "cpu" "k6")
789 (eq_attr "type" "imul"))
792 (define_function_unit "k6_alux" 1 0
793 (and (eq_attr "cpu" "k6")
794 (eq_attr "type" "imul"))
798 (define_function_unit "k6_alu" 2 0
799 (and (eq_attr "cpu" "k6")
800 (eq_attr "type" "idiv"))
803 (define_function_unit "k6_alux" 1 0
804 (and (eq_attr "cpu" "k6")
805 (eq_attr "type" "idiv"))
808 ;; AMD Athlon Scheduling
810 ;; The Athlon does contain three pipelined FP units, three integer units and
811 ;; three address generation units.
813 ;; The predecode logic is determining boundaries of instructions in the 64
814 ;; byte cache line. So the cache line straddling problem of K6 might be issue
815 ;; here as well, but it is not noted in the documentation.
817 ;; Three DirectPath instructions decoders and only one VectorPath decoder
818 ;; is available. They can decode three DirectPath instructions or one VectorPath
819 ;; instruction per cycle.
820 ;; Decoded macro instructions are then passed to 72 entry instruction control
822 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
824 ;; The load/store queue unit is not attached to the schedulers but
825 ;; communicates with all the execution units seperately instead.
827 (define_attr "athlon_decode" "direct,vector"
828 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
829 (const_string "vector")
830 (and (eq_attr "type" "push")
831 (match_operand 1 "memory_operand" ""))
832 (const_string "vector")
833 (and (eq_attr "type" "fmov")
834 (and (eq_attr "memory" "load,store")
835 (eq_attr "mode" "XF")))
836 (const_string "vector")]
837 (const_string "direct")))
839 (define_function_unit "athlon_vectordec" 1 0
840 (and (eq_attr "cpu" "athlon")
841 (eq_attr "athlon_decode" "vector"))
844 (define_function_unit "athlon_directdec" 3 0
845 (and (eq_attr "cpu" "athlon")
846 (eq_attr "athlon_decode" "direct"))
849 (define_function_unit "athlon_vectordec" 1 0
850 (and (eq_attr "cpu" "athlon")
851 (eq_attr "athlon_decode" "direct"))
852 1 1 [(eq_attr "athlon_decode" "vector")])
854 (define_function_unit "athlon_ieu" 3 0
855 (and (eq_attr "cpu" "athlon")
856 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
859 (define_function_unit "athlon_ieu" 3 0
860 (and (eq_attr "cpu" "athlon")
861 (eq_attr "type" "str"))
864 (define_function_unit "athlon_ieu" 3 0
865 (and (eq_attr "cpu" "athlon")
866 (eq_attr "type" "imul"))
869 (define_function_unit "athlon_ieu" 3 0
870 (and (eq_attr "cpu" "athlon")
871 (eq_attr "type" "idiv"))
874 (define_function_unit "athlon_muldiv" 1 0
875 (and (eq_attr "cpu" "athlon")
876 (eq_attr "type" "imul"))
879 (define_function_unit "athlon_muldiv" 1 0
880 (and (eq_attr "cpu" "athlon")
881 (eq_attr "type" "idiv"))
884 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
885 (cond [(eq_attr "type" "fop,fop1,fcmp")
887 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
889 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
890 (const_string "store")
891 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
893 (and (eq_attr "type" "fmov")
894 (ior (match_operand:SI 1 "register_operand" "")
895 (match_operand 1 "immediate_operand" "")))
896 (const_string "store")
897 (eq_attr "type" "fmov")
898 (const_string "muladd")]
899 (const_string "none")))
901 ;; We use latencies 1 for definitions. This is OK to model colisions
902 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
904 ;; fsin, fcos: 96-192
906 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
907 (define_function_unit "athlon_fp" 3 0
908 (and (eq_attr "cpu" "athlon")
909 (eq_attr "type" "fpspc"))
912 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
913 (define_function_unit "athlon_fp" 3 0
914 (and (eq_attr "cpu" "athlon")
915 (eq_attr "type" "fdiv"))
918 (define_function_unit "athlon_fp" 3 0
919 (and (eq_attr "cpu" "athlon")
920 (eq_attr "type" "fop,fop1,fmul"))
923 ;; XFmode loads are slow.
924 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
925 ;; there are no dependent instructions.
927 (define_function_unit "athlon_fp" 3 0
928 (and (eq_attr "cpu" "athlon")
929 (and (eq_attr "type" "fmov")
930 (and (eq_attr "memory" "load")
931 (eq_attr "mode" "XF"))))
934 (define_function_unit "athlon_fp" 3 0
935 (and (eq_attr "cpu" "athlon")
936 (eq_attr "type" "fmov,fsgn"))
939 ;; fcmp and ftst instructions
940 (define_function_unit "athlon_fp" 3 0
941 (and (eq_attr "cpu" "athlon")
942 (and (eq_attr "type" "fcmp")
943 (eq_attr "athlon_decode" "direct")))
946 ;; fcmpi instructions.
947 (define_function_unit "athlon_fp" 3 0
948 (and (eq_attr "cpu" "athlon")
949 (and (eq_attr "type" "fcmp")
950 (eq_attr "athlon_decode" "vector")))
953 (define_function_unit "athlon_fp" 3 0
954 (and (eq_attr "cpu" "athlon")
955 (eq_attr "type" "fcmov"))
958 (define_function_unit "athlon_fp_mul" 1 0
959 (and (eq_attr "cpu" "athlon")
960 (eq_attr "athlon_fpunits" "mul"))
963 (define_function_unit "athlon_fp_add" 1 0
964 (and (eq_attr "cpu" "athlon")
965 (eq_attr "athlon_fpunits" "add"))
968 (define_function_unit "athlon_fp_muladd" 2 0
969 (and (eq_attr "cpu" "athlon")
970 (eq_attr "athlon_fpunits" "muladd,mul,add"))
973 (define_function_unit "athlon_fp_store" 1 0
974 (and (eq_attr "cpu" "athlon")
975 (eq_attr "athlon_fpunits" "store"))
978 ;; We don't need to model the Adress Generation Unit, since we don't model
979 ;; the re-order buffer yet and thus we never schedule more than three operations
980 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
981 ;; decoders independently on the functional units.
983 ;(define_function_unit "athlon_agu" 3 0
984 ; (and (eq_attr "cpu" "athlon")
985 ; (and (eq_attr "memory" "!none")
986 ; (eq_attr "athlon_fpunits" "none")))
989 ;; Model load unit to avoid too long sequences of loads. We don't need to
990 ;; model store queue, since it is hardly going to be bottleneck.
992 (define_function_unit "athlon_load" 2 0
993 (and (eq_attr "cpu" "athlon")
994 (eq_attr "memory" "load,both"))
998 ;; Compare instructions.
1000 ;; All compare insns have expanders that save the operands away without
1001 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1002 ;; after the cmp) will actually emit the cmpM.
1004 (define_expand "cmpdi"
1006 (compare:CC (match_operand:DI 0 "x86_64_general_operand" "")
1007 (match_operand:DI 1 "x86_64_general_operand" "")))]
1011 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1012 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1013 operands[0] = force_reg (DImode, operands[0]);
1014 ix86_compare_op0 = operands[0];
1015 ix86_compare_op1 = operands[1];
1019 (define_expand "cmpsi"
1021 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1022 (match_operand:SI 1 "general_operand" "")))]
1026 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1027 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1028 operands[0] = force_reg (SImode, operands[0]);
1029 ix86_compare_op0 = operands[0];
1030 ix86_compare_op1 = operands[1];
1034 (define_expand "cmphi"
1036 (compare:CC (match_operand:HI 0 "general_operand" "")
1037 (match_operand:HI 1 "general_operand" "")))]
1041 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1042 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1043 operands[0] = force_reg (HImode, operands[0]);
1044 ix86_compare_op0 = operands[0];
1045 ix86_compare_op1 = operands[1];
1049 (define_expand "cmpqi"
1051 (compare:CC (match_operand:QI 0 "general_operand" "")
1052 (match_operand:QI 1 "general_operand" "")))]
1053 "TARGET_QIMODE_MATH"
1056 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1057 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1058 operands[0] = force_reg (QImode, operands[0]);
1059 ix86_compare_op0 = operands[0];
1060 ix86_compare_op1 = operands[1];
1064 (define_insn "cmpdi_ccno_1_rex64"
1066 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
1067 (match_operand:DI 1 "const0_operand" "n,n")))]
1068 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
1070 test{q}\\t{%0, %0|%0, %0}
1071 cmp{q}\\t{%1, %0|%0, %1}"
1072 [(set_attr "type" "test,icmp")
1073 (set_attr "length_immediate" "0,1")
1074 (set_attr "mode" "DI")])
1076 (define_insn "*cmpdi_minus_1_rex64"
1078 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
1079 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
1081 "ix86_match_ccmode (insn, CCGOCmode)"
1082 "cmp{q}\\t{%1, %0|%0, %1}"
1083 [(set_attr "type" "icmp")
1084 (set_attr "mode" "DI")])
1086 (define_expand "cmpdi_1_rex64"
1088 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1089 (match_operand:DI 1 "general_operand" "")))]
1093 (define_insn "cmpdi_1_insn_rex64"
1095 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
1096 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
1097 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1098 "cmp{q}\\t{%1, %0|%0, %1}"
1099 [(set_attr "type" "icmp")
1100 (set_attr "mode" "DI")])
1103 (define_insn "*cmpsi_ccno_1"
1105 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1106 (match_operand:SI 1 "const0_operand" "n,n")))]
1107 "ix86_match_ccmode (insn, CCNOmode)"
1109 test{l}\\t{%0, %0|%0, %0}
1110 cmp{l}\\t{%1, %0|%0, %1}"
1111 [(set_attr "type" "test,icmp")
1112 (set_attr "length_immediate" "0,1")
1113 (set_attr "mode" "SI")])
1115 (define_insn "*cmpsi_minus_1"
1117 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1118 (match_operand:SI 1 "general_operand" "ri,mr"))
1120 "ix86_match_ccmode (insn, CCGOCmode)"
1121 "cmp{l}\\t{%1, %0|%0, %1}"
1122 [(set_attr "type" "icmp")
1123 (set_attr "mode" "SI")])
1125 (define_expand "cmpsi_1"
1127 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1128 (match_operand:SI 1 "general_operand" "ri,mr")))]
1132 (define_insn "*cmpsi_1_insn"
1134 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1135 (match_operand:SI 1 "general_operand" "ri,mr")))]
1136 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1137 && ix86_match_ccmode (insn, CCmode)"
1138 "cmp{l}\\t{%1, %0|%0, %1}"
1139 [(set_attr "type" "icmp")
1140 (set_attr "mode" "SI")])
1142 (define_insn "*cmphi_ccno_1"
1144 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1145 (match_operand:HI 1 "const0_operand" "n,n")))]
1146 "ix86_match_ccmode (insn, CCNOmode)"
1148 test{w}\\t{%0, %0|%0, %0}
1149 cmp{w}\\t{%1, %0|%0, %1}"
1150 [(set_attr "type" "test,icmp")
1151 (set_attr "length_immediate" "0,1")
1152 (set_attr "mode" "HI")])
1154 (define_insn "*cmphi_minus_1"
1156 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1157 (match_operand:HI 1 "general_operand" "ri,mr"))
1159 "ix86_match_ccmode (insn, CCGOCmode)"
1160 "cmp{w}\\t{%1, %0|%0, %1}"
1161 [(set_attr "type" "icmp")
1162 (set_attr "mode" "HI")])
1164 (define_insn "*cmphi_1"
1166 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1167 (match_operand:HI 1 "general_operand" "ri,mr")))]
1168 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1169 && ix86_match_ccmode (insn, CCmode)"
1170 "cmp{w}\\t{%1, %0|%0, %1}"
1171 [(set_attr "type" "icmp")
1172 (set_attr "mode" "HI")])
1174 (define_insn "*cmpqi_ccno_1"
1176 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1177 (match_operand:QI 1 "const0_operand" "n,n")))]
1178 "ix86_match_ccmode (insn, CCNOmode)"
1180 test{b}\\t{%0, %0|%0, %0}
1181 cmp{b}\\t{$0, %0|%0, 0}"
1182 [(set_attr "type" "test,icmp")
1183 (set_attr "length_immediate" "0,1")
1184 (set_attr "mode" "QI")])
1186 (define_insn "*cmpqi_1"
1188 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1189 (match_operand:QI 1 "general_operand" "qi,mq")))]
1190 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1191 && ix86_match_ccmode (insn, CCmode)"
1192 "cmp{b}\\t{%1, %0|%0, %1}"
1193 [(set_attr "type" "icmp")
1194 (set_attr "mode" "QI")])
1196 (define_insn "*cmpqi_minus_1"
1198 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1199 (match_operand:QI 1 "general_operand" "qi,mq"))
1201 "ix86_match_ccmode (insn, CCGOCmode)"
1202 "cmp{b}\\t{%1, %0|%0, %1}"
1203 [(set_attr "type" "icmp")
1204 (set_attr "mode" "QI")])
1206 (define_insn "*cmpqi_ext_1"
1209 (match_operand:QI 0 "general_operand" "Qm")
1212 (match_operand 1 "ext_register_operand" "Q")
1214 (const_int 8)) 0)))]
1215 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1216 "cmp{b}\\t{%h1, %0|%0, %h1}"
1217 [(set_attr "type" "icmp")
1218 (set_attr "mode" "QI")])
1220 (define_insn "*cmpqi_ext_1_rex64"
1223 (match_operand:QI 0 "ext_register_operand" "Q")
1226 (match_operand 1 "ext_register_operand" "Q")
1228 (const_int 8)) 0)))]
1229 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1230 "cmp{b}\\t{%h1, %0|%0, %h1}"
1231 [(set_attr "type" "icmp")
1232 (set_attr "mode" "QI")])
1234 (define_insn "*cmpqi_ext_2"
1239 (match_operand 0 "ext_register_operand" "Q")
1242 (match_operand:QI 1 "const0_operand" "n")))]
1243 "ix86_match_ccmode (insn, CCNOmode)"
1244 "test{b}\\t%h0, %h0"
1245 [(set_attr "type" "test")
1246 (set_attr "length_immediate" "0")
1247 (set_attr "mode" "QI")])
1249 (define_expand "cmpqi_ext_3"
1254 (match_operand 0 "ext_register_operand" "")
1257 (match_operand:QI 1 "general_operand" "")))]
1261 (define_insn "cmpqi_ext_3_insn"
1266 (match_operand 0 "ext_register_operand" "Q")
1269 (match_operand:QI 1 "general_operand" "Qmn")))]
1270 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1271 "cmp{b}\\t{%1, %h0|%h0, %1}"
1272 [(set_attr "type" "icmp")
1273 (set_attr "mode" "QI")])
1275 (define_insn "cmpqi_ext_3_insn_rex64"
1280 (match_operand 0 "ext_register_operand" "Q")
1283 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1284 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1285 "cmp{b}\\t{%1, %h0|%h0, %1}"
1286 [(set_attr "type" "icmp")
1287 (set_attr "mode" "QI")])
1289 (define_insn "*cmpqi_ext_4"
1294 (match_operand 0 "ext_register_operand" "Q")
1299 (match_operand 1 "ext_register_operand" "Q")
1301 (const_int 8)) 0)))]
1302 "ix86_match_ccmode (insn, CCmode)"
1303 "cmp{b}\\t{%h1, %h0|%h0, %h1}"
1304 [(set_attr "type" "icmp")
1305 (set_attr "mode" "QI")])
1307 ;; These implement float point compares.
1308 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1309 ;; which would allow mix and match FP modes on the compares. Which is what
1310 ;; the old patterns did, but with many more of them.
1312 (define_expand "cmpxf"
1314 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1315 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1316 "TARGET_80387 && !TARGET_64BIT"
1319 ix86_compare_op0 = operands[0];
1320 ix86_compare_op1 = operands[1];
1324 (define_expand "cmptf"
1326 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1327 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1331 ix86_compare_op0 = operands[0];
1332 ix86_compare_op1 = operands[1];
1336 (define_expand "cmpdf"
1338 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1339 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1340 "TARGET_80387 || TARGET_SSE2"
1343 ix86_compare_op0 = operands[0];
1344 ix86_compare_op1 = operands[1];
1348 (define_expand "cmpsf"
1350 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1351 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1352 "TARGET_80387 || TARGET_SSE"
1355 ix86_compare_op0 = operands[0];
1356 ix86_compare_op1 = operands[1];
1360 ;; FP compares, step 1:
1361 ;; Set the FP condition codes.
1363 ;; CCFPmode compare with exceptions
1364 ;; CCFPUmode compare with no exceptions
1366 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1367 ;; and that fp moves clobber the condition codes, and that there is
1368 ;; currently no way to describe this fact to reg-stack. So there are
1369 ;; no splitters yet for this.
1371 ;; %%% YIKES! This scheme does not retain a strong connection between
1372 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1373 ;; work! Only allow tos/mem with tos in op 0.
1375 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1376 ;; things aren't as bad as they sound...
1378 (define_insn "*cmpfp_0"
1379 [(set (match_operand:HI 0 "register_operand" "=a")
1381 [(compare:CCFP (match_operand 1 "register_operand" "f")
1382 (match_operand 2 "const0_operand" "X"))] 9))]
1384 && FLOAT_MODE_P (GET_MODE (operands[1]))
1385 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1388 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1389 return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
1391 return \"ftst\;fnstsw\\t%0\";
1393 [(set_attr "type" "multi")
1394 (set_attr "mode" "unknownfp")])
1396 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1397 ;; used to manage the reg stack popping would not be preserved.
1399 (define_insn "*cmpfp_2_sf"
1402 (match_operand:SF 0 "register_operand" "f")
1403 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1405 "* return output_fp_compare (insn, operands, 0, 0);"
1406 [(set_attr "type" "fcmp")
1407 (set_attr "mode" "SF")])
1409 (define_insn "*cmpfp_2_sf_1"
1410 [(set (match_operand:HI 0 "register_operand" "=a")
1413 (match_operand:SF 1 "register_operand" "f")
1414 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1416 "* return output_fp_compare (insn, operands, 2, 0);"
1417 [(set_attr "type" "fcmp")
1418 (set_attr "mode" "SF")])
1420 (define_insn "*cmpfp_2_df"
1423 (match_operand:DF 0 "register_operand" "f")
1424 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1426 "* return output_fp_compare (insn, operands, 0, 0);"
1427 [(set_attr "type" "fcmp")
1428 (set_attr "mode" "DF")])
1430 (define_insn "*cmpfp_2_df_1"
1431 [(set (match_operand:HI 0 "register_operand" "=a")
1434 (match_operand:DF 1 "register_operand" "f")
1435 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1437 "* return output_fp_compare (insn, operands, 2, 0);"
1438 [(set_attr "type" "multi")
1439 (set_attr "mode" "DF")])
1441 (define_insn "*cmpfp_2_xf"
1444 (match_operand:XF 0 "register_operand" "f")
1445 (match_operand:XF 1 "register_operand" "f")))]
1446 "TARGET_80387 && !TARGET_64BIT"
1447 "* return output_fp_compare (insn, operands, 0, 0);"
1448 [(set_attr "type" "fcmp")
1449 (set_attr "mode" "XF")])
1451 (define_insn "*cmpfp_2_tf"
1454 (match_operand:TF 0 "register_operand" "f")
1455 (match_operand:TF 1 "register_operand" "f")))]
1457 "* return output_fp_compare (insn, operands, 0, 0);"
1458 [(set_attr "type" "fcmp")
1459 (set_attr "mode" "XF")])
1461 (define_insn "*cmpfp_2_xf_1"
1462 [(set (match_operand:HI 0 "register_operand" "=a")
1465 (match_operand:XF 1 "register_operand" "f")
1466 (match_operand:XF 2 "register_operand" "f"))] 9))]
1467 "TARGET_80387 && !TARGET_64BIT"
1468 "* return output_fp_compare (insn, operands, 2, 0);"
1469 [(set_attr "type" "multi")
1470 (set_attr "mode" "XF")])
1472 (define_insn "*cmpfp_2_tf_1"
1473 [(set (match_operand:HI 0 "register_operand" "=a")
1476 (match_operand:TF 1 "register_operand" "f")
1477 (match_operand:TF 2 "register_operand" "f"))] 9))]
1479 "* return output_fp_compare (insn, operands, 2, 0);"
1480 [(set_attr "type" "multi")
1481 (set_attr "mode" "XF")])
1483 (define_insn "*cmpfp_2u"
1484 [(set (reg:CCFPU 18)
1486 (match_operand 0 "register_operand" "f")
1487 (match_operand 1 "register_operand" "f")))]
1489 && FLOAT_MODE_P (GET_MODE (operands[0]))
1490 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1491 "* return output_fp_compare (insn, operands, 0, 1);"
1492 [(set_attr "type" "fcmp")
1493 (set_attr "mode" "unknownfp")])
1495 (define_insn "*cmpfp_2u_1"
1496 [(set (match_operand:HI 0 "register_operand" "=a")
1499 (match_operand 1 "register_operand" "f")
1500 (match_operand 2 "register_operand" "f"))] 9))]
1502 && FLOAT_MODE_P (GET_MODE (operands[1]))
1503 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1504 "* return output_fp_compare (insn, operands, 2, 1);"
1505 [(set_attr "type" "multi")
1506 (set_attr "mode" "unknownfp")])
1508 ;; Patterns to match the SImode-in-memory ficom instructions.
1510 ;; %%% Play games with accepting gp registers, as otherwise we have to
1511 ;; force them to memory during rtl generation, which is no good. We
1512 ;; can get rid of this once we teach reload to do memory input reloads
1515 (define_insn "*ficom_1"
1518 (match_operand 0 "register_operand" "f,f")
1519 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1520 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1521 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1524 ;; Split the not-really-implemented gp register case into a
1525 ;; push-op-pop sequence.
1527 ;; %%% This is most efficient, but am I gonna get in trouble
1528 ;; for separating cc0_setter and cc0_user?
1533 (match_operand:SF 0 "register_operand" "")
1534 (float (match_operand:SI 1 "register_operand" ""))))]
1535 "0 && TARGET_80387 && reload_completed"
1536 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1537 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1538 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1539 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1540 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1541 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1543 ;; FP compares, step 2
1544 ;; Move the fpsw to ax.
1546 (define_insn "x86_fnstsw_1"
1547 [(set (match_operand:HI 0 "register_operand" "=a")
1548 (unspec:HI [(reg 18)] 9))]
1551 [(set_attr "length" "2")
1552 (set_attr "mode" "SI")
1553 (set_attr "i387" "1")
1554 (set_attr "ppro_uops" "few")])
1556 ;; FP compares, step 3
1557 ;; Get ax into flags, general case.
1559 (define_insn "x86_sahf_1"
1561 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1564 [(set_attr "length" "1")
1565 (set_attr "athlon_decode" "vector")
1566 (set_attr "mode" "SI")
1567 (set_attr "ppro_uops" "one")])
1569 ;; Pentium Pro can do steps 1 through 3 in one go.
1571 (define_insn "*cmpfp_i"
1573 (compare:CCFP (match_operand 0 "register_operand" "f")
1574 (match_operand 1 "register_operand" "f")))]
1575 "TARGET_80387 && TARGET_CMOVE
1576 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1577 && FLOAT_MODE_P (GET_MODE (operands[0]))
1578 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1579 "* return output_fp_compare (insn, operands, 1, 0);"
1580 [(set_attr "type" "fcmp")
1581 (set_attr "mode" "unknownfp")
1582 (set_attr "athlon_decode" "vector")])
1584 (define_insn "*cmpfp_i_sse"
1586 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1587 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1589 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1590 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1591 "* return output_fp_compare (insn, operands, 1, 0);"
1592 [(set_attr "type" "fcmp,sse")
1593 (set_attr "mode" "unknownfp")
1594 (set_attr "athlon_decode" "vector")])
1596 (define_insn "*cmpfp_i_sse_only"
1598 (compare:CCFP (match_operand 0 "register_operand" "x")
1599 (match_operand 1 "nonimmediate_operand" "xm")))]
1600 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1601 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1602 "* return output_fp_compare (insn, operands, 1, 0);"
1603 [(set_attr "type" "sse")
1604 (set_attr "mode" "unknownfp")
1605 (set_attr "athlon_decode" "vector")])
1607 (define_insn "*cmpfp_iu"
1608 [(set (reg:CCFPU 17)
1609 (compare:CCFPU (match_operand 0 "register_operand" "f")
1610 (match_operand 1 "register_operand" "f")))]
1611 "TARGET_80387 && TARGET_CMOVE
1612 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1613 && FLOAT_MODE_P (GET_MODE (operands[0]))
1614 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1615 "* return output_fp_compare (insn, operands, 1, 1);"
1616 [(set_attr "type" "fcmp")
1617 (set_attr "mode" "unknownfp")
1618 (set_attr "athlon_decode" "vector")])
1620 (define_insn "*cmpfp_iu_sse"
1621 [(set (reg:CCFPU 17)
1622 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1623 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1625 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1626 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1627 "* return output_fp_compare (insn, operands, 1, 1);"
1628 [(set_attr "type" "fcmp,sse")
1629 (set_attr "mode" "unknownfp")
1630 (set_attr "athlon_decode" "vector")])
1632 (define_insn "*cmpfp_iu_sse_only"
1633 [(set (reg:CCFPU 17)
1634 (compare:CCFPU (match_operand 0 "register_operand" "x")
1635 (match_operand 1 "nonimmediate_operand" "xm")))]
1636 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1637 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1638 "* return output_fp_compare (insn, operands, 1, 1);"
1639 [(set_attr "type" "sse")
1640 (set_attr "mode" "unknownfp")
1641 (set_attr "athlon_decode" "vector")])
1643 ;; Move instructions.
1645 ;; General case of fullword move.
1647 (define_expand "movsi"
1648 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1649 (match_operand:SI 1 "general_operand" ""))]
1651 "ix86_expand_move (SImode, operands); DONE;")
1653 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1656 ;; %%% We don't use a post-inc memory reference because x86 is not a
1657 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1658 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1659 ;; targets without our curiosities, and it is just as easy to represent
1660 ;; this differently.
1662 (define_insn "*pushsi2"
1663 [(set (match_operand:SI 0 "push_operand" "=<")
1664 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1667 [(set_attr "type" "push")
1668 (set_attr "mode" "SI")])
1670 ;; For 64BIT abi we always round up to 8 bytes.
1671 (define_insn "*pushsi2_rex64"
1672 [(set (match_operand:SI 0 "push_operand" "=X")
1673 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1676 [(set_attr "type" "push")
1677 (set_attr "mode" "SI")])
1679 (define_insn "*pushsi2_prologue"
1680 [(set (match_operand:SI 0 "push_operand" "=<")
1681 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1682 (set (reg:SI 6) (reg:SI 6))]
1685 [(set_attr "type" "push")
1686 (set_attr "mode" "SI")])
1688 (define_insn "*popsi1_epilogue"
1689 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1690 (mem:SI (reg:SI 7)))
1692 (plus:SI (reg:SI 7) (const_int 4)))
1693 (set (reg:SI 6) (reg:SI 6))]
1696 [(set_attr "type" "pop")
1697 (set_attr "mode" "SI")])
1699 (define_insn "popsi1"
1700 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1701 (mem:SI (reg:SI 7)))
1703 (plus:SI (reg:SI 7) (const_int 4)))]
1706 [(set_attr "type" "pop")
1707 (set_attr "mode" "SI")])
1709 (define_insn "*movsi_xor"
1710 [(set (match_operand:SI 0 "register_operand" "=r")
1711 (match_operand:SI 1 "const0_operand" "i"))
1712 (clobber (reg:CC 17))]
1713 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1714 "xor{l}\\t{%0, %0|%0, %0}"
1715 [(set_attr "type" "alu1")
1716 (set_attr "mode" "SI")
1717 (set_attr "length_immediate" "0")])
1719 (define_insn "*movsi_or"
1720 [(set (match_operand:SI 0 "register_operand" "=r")
1721 (match_operand:SI 1 "immediate_operand" "i"))
1722 (clobber (reg:CC 17))]
1723 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1724 && INTVAL (operands[1]) == -1
1725 && (TARGET_PENTIUM || optimize_size)"
1728 operands[1] = constm1_rtx;
1729 return \"or{l}\\t{%1, %0|%0, %1}\";
1731 [(set_attr "type" "alu1")
1732 (set_attr "mode" "SI")
1733 (set_attr "length_immediate" "1")])
1735 (define_insn "*movsi_1"
1736 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1737 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1738 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1741 switch (get_attr_type (insn))
1744 if (get_attr_mode (insn) == TImode)
1745 return \"movdqa\\t{%1, %0|%0, %1}\";
1746 return \"movd\\t{%1, %0|%0, %1}\";
1749 return \"movd\\t{%1, %0|%0, %1}\";
1752 return \"lea{l}\\t{%1, %0|%0, %1}\";
1755 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1757 return \"mov{l}\\t{%1, %0|%0, %1}\";
1761 (cond [(eq_attr "alternative" "4,5")
1762 (const_string "mmx")
1763 (eq_attr "alternative" "6,7,8")
1764 (const_string "sse")
1765 (and (ne (symbol_ref "flag_pic") (const_int 0))
1766 (match_operand:SI 1 "symbolic_operand" ""))
1767 (const_string "lea")
1769 (const_string "imov")))
1770 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1771 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1773 ;; Stores and loads of ax to arbitary constant address.
1774 ;; We fake an second form of instruction to force reload to load address
1775 ;; into register when rax is not available
1776 (define_insn "*movabssi_1_rex64"
1777 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1778 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1781 movabs{l}\\t{%1, %P0|%P0, %1}
1782 mov{l}\\t{%1, %a0|%a0, %1}
1783 movabs{l}\\t{%1, %a0|%a0, %1}"
1784 [(set_attr "type" "imov")
1785 (set_attr "modrm" "0,*,*")
1786 (set_attr "length_address" "8,0,0")
1787 (set_attr "length_immediate" "0,*,*")
1788 (set_attr "memory" "store")
1789 (set_attr "mode" "SI")])
1791 (define_insn "*movabssi_2_rex64"
1792 [(set (match_operand:SI 0 "register_operand" "=a,r")
1793 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1796 movabs{l}\\t{%P1, %0|%0, %P1}
1797 mov{l}\\t{%a1, %0|%0, %a1}"
1798 [(set_attr "type" "imov")
1799 (set_attr "modrm" "0,*")
1800 (set_attr "length_address" "8,0")
1801 (set_attr "length_immediate" "0")
1802 (set_attr "memory" "load")
1803 (set_attr "mode" "SI")])
1805 (define_insn "*swapsi"
1806 [(set (match_operand:SI 0 "register_operand" "+r")
1807 (match_operand:SI 1 "register_operand" "+r"))
1812 [(set_attr "type" "imov")
1813 (set_attr "pent_pair" "np")
1814 (set_attr "athlon_decode" "vector")
1815 (set_attr "mode" "SI")
1816 (set_attr "modrm" "0")
1817 (set_attr "ppro_uops" "few")])
1819 (define_expand "movhi"
1820 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1821 (match_operand:HI 1 "general_operand" ""))]
1823 "ix86_expand_move (HImode, operands); DONE;")
1825 (define_insn "*pushhi2"
1826 [(set (match_operand:HI 0 "push_operand" "=<,<")
1827 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1830 push{w}\\t{|WORD PTR }%1
1832 [(set_attr "type" "push")
1833 (set_attr "mode" "HI")])
1835 ;; For 64BIT abi we always round up to 8 bytes.
1836 (define_insn "*pushhi2_rex64"
1837 [(set (match_operand:HI 0 "push_operand" "=X")
1838 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1841 [(set_attr "type" "push")
1842 (set_attr "mode" "QI")])
1844 (define_insn "*movhi_1"
1845 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1846 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1847 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1850 switch (get_attr_type (insn))
1853 /* movzwl is faster than movw on p2 due to partial word stalls,
1854 though not as fast as an aligned movl. */
1855 return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
1857 if (get_attr_mode (insn) == MODE_SI)
1858 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1860 return \"mov{w}\\t{%1, %0|%0, %1}\";
1864 (cond [(and (eq_attr "alternative" "0,1")
1865 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1867 (eq (symbol_ref "TARGET_HIMODE_MATH")
1869 (const_string "imov")
1870 (and (eq_attr "alternative" "2,3,4")
1871 (match_operand:HI 1 "aligned_operand" ""))
1872 (const_string "imov")
1873 (and (ne (symbol_ref "TARGET_MOVX")
1875 (eq_attr "alternative" "0,1,3,4"))
1876 (const_string "imovx")
1878 (const_string "imov")))
1880 (cond [(eq_attr "type" "imovx")
1882 (and (eq_attr "alternative" "2,3,4")
1883 (match_operand:HI 1 "aligned_operand" ""))
1885 (and (eq_attr "alternative" "0,1")
1886 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1888 (eq (symbol_ref "TARGET_HIMODE_MATH")
1892 (const_string "HI")))
1893 (set_attr "modrm" "0,*,*,0,*,*")])
1895 ;; Stores and loads of ax to arbitary constant address.
1896 ;; We fake an second form of instruction to force reload to load address
1897 ;; into register when rax is not available
1898 (define_insn "*movabshi_1_rex64"
1899 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1900 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1903 movabs{w}\\t{%1, %P0|%P0, %1}
1904 mov{w}\\t{%1, %a0|%a0, %1}
1905 movabs{w}\\t{%1, %a0|%a0, %1}"
1906 [(set_attr "type" "imov")
1907 (set_attr "modrm" "0,*,*")
1908 (set_attr "length_address" "8,0,0")
1909 (set_attr "length_immediate" "0,*,*")
1910 (set_attr "memory" "store")
1911 (set_attr "mode" "HI")])
1913 (define_insn "*movabshi_2_rex64"
1914 [(set (match_operand:HI 0 "register_operand" "=a,r")
1915 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1918 movabs{w}\\t{%P1, %0|%0, %P1}
1919 mov{w}\\t{%a1, %0|%0, %a1}"
1920 [(set_attr "type" "imov")
1921 (set_attr "modrm" "0,*")
1922 (set_attr "length_address" "8,0")
1923 (set_attr "length_immediate" "0")
1924 (set_attr "memory" "load")
1925 (set_attr "mode" "HI")])
1927 (define_insn "*swaphi_1"
1928 [(set (match_operand:HI 0 "register_operand" "+r")
1929 (match_operand:HI 1 "register_operand" "+r"))
1932 "TARGET_PARTIAL_REG_STALL"
1934 [(set_attr "type" "imov")
1935 (set_attr "pent_pair" "np")
1936 (set_attr "mode" "HI")
1937 (set_attr "modrm" "0")
1938 (set_attr "ppro_uops" "few")])
1940 (define_insn "*swaphi_2"
1941 [(set (match_operand:HI 0 "register_operand" "+r")
1942 (match_operand:HI 1 "register_operand" "+r"))
1945 "! TARGET_PARTIAL_REG_STALL"
1946 "xchg{l}\\t%k1, %k0"
1947 [(set_attr "type" "imov")
1948 (set_attr "pent_pair" "np")
1949 (set_attr "mode" "SI")
1950 (set_attr "modrm" "0")
1951 (set_attr "ppro_uops" "few")])
1953 (define_expand "movstricthi"
1954 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1955 (match_operand:HI 1 "general_operand" ""))]
1956 "! TARGET_PARTIAL_REG_STALL"
1959 /* Don't generate memory->memory moves, go through a register */
1960 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1961 operands[1] = force_reg (HImode, operands[1]);
1964 (define_insn "*movstricthi_1"
1965 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1966 (match_operand:HI 1 "general_operand" "rn,m"))]
1967 "! TARGET_PARTIAL_REG_STALL
1968 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1969 "mov{w}\\t{%1, %0|%0, %1}"
1970 [(set_attr "type" "imov")
1971 (set_attr "mode" "HI")])
1973 (define_insn "*movstricthi_xor"
1974 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1975 (match_operand:HI 1 "const0_operand" "i"))
1976 (clobber (reg:CC 17))]
1977 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1978 "xor{w}\\t{%0, %0|%0, %0}"
1979 [(set_attr "type" "alu1")
1980 (set_attr "mode" "HI")
1981 (set_attr "length_immediate" "0")])
1983 (define_expand "movqi"
1984 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1985 (match_operand:QI 1 "general_operand" ""))]
1987 "ix86_expand_move (QImode, operands); DONE;")
1989 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1990 ;; "push a byte". But actually we use pushw, which has the effect
1991 ;; of rounding the amount pushed up to a halfword.
1993 (define_insn "*pushqi2"
1994 [(set (match_operand:QI 0 "push_operand" "=X,X")
1995 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1998 push{w}\\t{|word ptr }%1
2000 [(set_attr "type" "push")
2001 (set_attr "mode" "HI")])
2003 ;; For 64BIT abi we always round up to 8 bytes.
2004 (define_insn "*pushqi2_rex64"
2005 [(set (match_operand:QI 0 "push_operand" "=X")
2006 (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
2009 [(set_attr "type" "push")
2010 (set_attr "mode" "QI")])
2012 ;; Situation is quite tricky about when to choose full sized (SImode) move
2013 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2014 ;; partial register dependency machines (such as AMD Athlon), where QImode
2015 ;; moves issue extra dependency and for partial register stalls machines
2016 ;; that don't use QImode patterns (and QImode move cause stall on the next
2019 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2020 ;; register stall machines with, where we use QImode instructions, since
2021 ;; partial register stall can be caused there. Then we use movzx.
2022 (define_insn "*movqi_1"
2023 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2024 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2025 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2028 switch (get_attr_type (insn))
2031 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
2033 return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
2035 if (get_attr_mode (insn) == MODE_SI)
2036 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2038 return \"mov{b}\\t{%1, %0|%0, %1}\";
2042 (cond [(and (eq_attr "alternative" "3")
2043 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
2045 (eq (symbol_ref "TARGET_QIMODE_MATH")
2047 (const_string "imov")
2048 (eq_attr "alternative" "3,5")
2049 (const_string "imovx")
2050 (and (ne (symbol_ref "TARGET_MOVX")
2052 (eq_attr "alternative" "2"))
2053 (const_string "imovx")
2055 (const_string "imov")))
2057 (cond [(eq_attr "alternative" "3,4,5")
2059 (eq_attr "alternative" "6")
2061 (eq_attr "type" "imovx")
2063 (and (eq_attr "type" "imov")
2064 (and (eq_attr "alternative" "0,1,2")
2065 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2068 ;; Avoid partial register stalls when not using QImode arithmetic
2069 (and (eq_attr "type" "imov")
2070 (and (eq_attr "alternative" "0,1,2")
2071 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2073 (eq (symbol_ref "TARGET_QIMODE_MATH")
2077 (const_string "QI")))])
2079 (define_expand "reload_outqi"
2080 [(parallel [(match_operand:QI 0 "" "=m")
2081 (match_operand:QI 1 "register_operand" "r")
2082 (match_operand:QI 2 "register_operand" "=&q")])]
2087 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2089 if (reg_overlap_mentioned_p (op2, op0))
2091 if (! q_regs_operand (op1, QImode))
2093 emit_insn (gen_movqi (op2, op1));
2096 emit_insn (gen_movqi (op0, op1));
2100 (define_insn "*swapqi"
2101 [(set (match_operand:QI 0 "register_operand" "+r")
2102 (match_operand:QI 1 "register_operand" "+r"))
2107 [(set_attr "type" "imov")
2108 (set_attr "pent_pair" "np")
2109 (set_attr "mode" "QI")
2110 (set_attr "modrm" "0")
2111 (set_attr "ppro_uops" "few")])
2113 (define_expand "movstrictqi"
2114 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2115 (match_operand:QI 1 "general_operand" ""))]
2116 "! TARGET_PARTIAL_REG_STALL"
2119 /* Don't generate memory->memory moves, go through a register */
2120 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2121 operands[1] = force_reg (QImode, operands[1]);
2124 (define_insn "*movstrictqi_1"
2125 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2126 (match_operand:QI 1 "general_operand" "*qn,m"))]
2127 "! TARGET_PARTIAL_REG_STALL
2128 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2129 "mov{b}\\t{%1, %0|%0, %1}"
2130 [(set_attr "type" "imov")
2131 (set_attr "mode" "QI")])
2133 (define_insn "*movstrictqi_xor"
2134 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2135 (match_operand:QI 1 "const0_operand" "i"))
2136 (clobber (reg:CC 17))]
2137 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2138 "xor{b}\\t{%0, %0|%0, %0}"
2139 [(set_attr "type" "alu1")
2140 (set_attr "mode" "QI")
2141 (set_attr "length_immediate" "0")])
2143 (define_insn "*movsi_extv_1"
2144 [(set (match_operand:SI 0 "register_operand" "=R")
2145 (sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
2149 "movs{bl|x}\\t{%h1, %0|%0, %h1}"
2150 [(set_attr "type" "imovx")
2151 (set_attr "mode" "SI")])
2153 (define_insn "*movhi_extv_1"
2154 [(set (match_operand:HI 0 "register_operand" "=R")
2155 (sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
2159 "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
2160 [(set_attr "type" "imovx")
2161 (set_attr "mode" "SI")])
2163 (define_insn "*movqi_extv_1"
2164 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2165 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2171 switch (get_attr_type (insn))
2174 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2176 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2180 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2181 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2182 (ne (symbol_ref "TARGET_MOVX")
2184 (const_string "imovx")
2185 (const_string "imov")))
2187 (if_then_else (eq_attr "type" "imovx")
2189 (const_string "QI")))])
2191 (define_insn "*movqi_extv_1_rex64"
2192 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2193 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2199 switch (get_attr_type (insn))
2202 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2204 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2208 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2209 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2210 (ne (symbol_ref "TARGET_MOVX")
2212 (const_string "imovx")
2213 (const_string "imov")))
2215 (if_then_else (eq_attr "type" "imovx")
2217 (const_string "QI")))])
2219 ;; Stores and loads of ax to arbitary constant address.
2220 ;; We fake an second form of instruction to force reload to load address
2221 ;; into register when rax is not available
2222 (define_insn "*movabsqi_1_rex64"
2223 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2224 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2227 movabs{q}\\t{%1, %P0|%P0, %1}
2228 mov{q}\\t{%1, %a0|%a0, %1}
2229 movabs{q}\\t{%1, %a0|%a0, %1}"
2230 [(set_attr "type" "imov")
2231 (set_attr "modrm" "0,*,*")
2232 (set_attr "length_address" "8,0,0")
2233 (set_attr "length_immediate" "0,*,*")
2234 (set_attr "memory" "store")
2235 (set_attr "mode" "QI")])
2237 (define_insn "*movabsqi_2_rex64"
2238 [(set (match_operand:QI 0 "register_operand" "=a,r")
2239 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2242 movabs{q}\\t{%P1, %0|%0, %P1}
2243 mov{q}\\t{%a1, %0|%0, %a1}"
2244 [(set_attr "type" "imov")
2245 (set_attr "modrm" "0,*")
2246 (set_attr "length_address" "8,0")
2247 (set_attr "length_immediate" "0")
2248 (set_attr "memory" "load")
2249 (set_attr "mode" "QI")])
2251 (define_insn "*movsi_extzv_1"
2252 [(set (match_operand:SI 0 "register_operand" "=R")
2253 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2257 "movz{bl|x}\\t{%h1, %0|%0, %h1}"
2258 [(set_attr "type" "imovx")
2259 (set_attr "mode" "SI")])
2261 (define_insn "*movqi_extzv_2"
2262 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2263 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2269 switch (get_attr_type (insn))
2272 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2274 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2278 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2279 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2280 (ne (symbol_ref "TARGET_MOVX")
2282 (const_string "imovx")
2283 (const_string "imov")))
2285 (if_then_else (eq_attr "type" "imovx")
2287 (const_string "QI")))])
2289 (define_insn "*movqi_extzv_2_rex64"
2290 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2291 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2297 switch (get_attr_type (insn))
2300 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2302 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2306 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2307 (ne (symbol_ref "TARGET_MOVX")
2309 (const_string "imovx")
2310 (const_string "imov")))
2312 (if_then_else (eq_attr "type" "imovx")
2314 (const_string "QI")))])
2316 (define_insn "*movsi_insv_1"
2317 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2320 (match_operand:SI 1 "nonimmediate_operand" "Qm"))]
2322 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2323 [(set_attr "type" "imov")
2324 (set_attr "mode" "QI")])
2326 (define_insn "*movsi_insv_1_rex64"
2327 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2330 (match_operand:SI 1 "ext_register_operand" "Q"))]
2332 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2333 [(set_attr "type" "imov")
2334 (set_attr "mode" "QI")])
2336 (define_insn "*movqi_insv_2"
2337 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2340 (and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
2344 "mov{b}\\t{%h1, %h0|%h0, %h1}"
2345 [(set_attr "type" "imov")
2346 (set_attr "mode" "QI")])
2348 (define_expand "movdi"
2349 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2350 (match_operand:DI 1 "general_operand" ""))]
2352 "ix86_expand_move (DImode, operands); DONE;")
2354 (define_insn "*pushdi"
2355 [(set (match_operand:DI 0 "push_operand" "=<")
2356 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2360 (define_insn "pushdi2_rex64"
2361 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2362 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2367 [(set_attr "type" "push,multi")
2368 (set_attr "mode" "DI")])
2370 ;; Convert impossible pushes of immediate to existing instructions.
2371 ;; First try to get scratch register and go trought it. In case this
2372 ;; fails, push sign extended lower part first and then overwrite
2373 ;; upper part by 32bit move.
2375 [(match_scratch:DI 2 "r")
2376 (set (match_operand:DI 0 "push_operand" "")
2377 (match_operand:DI 1 "immediate_operand" ""))]
2378 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2379 && !x86_64_immediate_operand (operands[1], DImode)"
2380 [(set (match_dup 2) (match_dup 1))
2381 (set (match_dup 0) (match_dup 2))]
2384 ;; We need to define this as both peepholer and splitter for case
2385 ;; peephole2 pass is not run.
2387 [(set (match_operand:DI 0 "push_operand" "")
2388 (match_operand:DI 1 "immediate_operand" ""))]
2389 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2390 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2391 [(set (match_dup 0) (match_dup 1))
2392 (set (match_dup 2) (match_dup 3))]
2393 "split_di (operands + 1, 1, operands + 2, operands + 3);
2394 operands[1] = gen_lowpart (DImode, operands[2]);
2395 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2400 [(set (match_operand:DI 0 "push_operand" "")
2401 (match_operand:DI 1 "immediate_operand" ""))]
2402 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2403 && !symbolic_operand (operands[1], DImode)
2404 && !x86_64_immediate_operand (operands[1], DImode)"
2405 [(set (match_dup 0) (match_dup 1))
2406 (set (match_dup 2) (match_dup 3))]
2407 "split_di (operands + 1, 1, operands + 2, operands + 3);
2408 operands[1] = gen_lowpart (DImode, operands[2]);
2409 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2413 (define_insn "*pushdi2_prologue_rex64"
2414 [(set (match_operand:DI 0 "push_operand" "=<")
2415 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2416 (set (reg:DI 6) (reg:DI 6))]
2419 [(set_attr "type" "push")
2420 (set_attr "mode" "DI")])
2422 (define_insn "*popdi1_epilogue_rex64"
2423 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2424 (mem:DI (reg:DI 7)))
2426 (plus:DI (reg:DI 7) (const_int 8)))
2427 (set (reg:DI 6) (reg:DI 6))]
2430 [(set_attr "type" "pop")
2431 (set_attr "mode" "DI")])
2433 (define_insn "popdi1"
2434 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2435 (mem:DI (reg:DI 7)))
2437 (plus:DI (reg:DI 7) (const_int 8)))]
2440 [(set_attr "type" "pop")
2441 (set_attr "mode" "DI")])
2443 (define_insn "*movdi_xor_rex64"
2444 [(set (match_operand:DI 0 "register_operand" "=r")
2445 (match_operand:DI 1 "const0_operand" "i"))
2446 (clobber (reg:CC 17))]
2447 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
2449 "xor{l}\\t{%k0, %k0|%k0, %k0}"
2450 [(set_attr "type" "alu1")
2451 (set_attr "mode" "SI")
2452 (set_attr "length_immediate" "0")])
2454 (define_insn "*movdi_or_rex64"
2455 [(set (match_operand:DI 0 "register_operand" "=r")
2456 (match_operand:DI 1 "const_int_operand" "i"))
2457 (clobber (reg:CC 17))]
2458 "reload_completed && GET_CODE (operands[1]) == CONST_INT
2460 && INTVAL (operands[1]) == -1
2461 && (TARGET_PENTIUM || optimize_size)"
2464 operands[1] = constm1_rtx;
2465 return \"or{q}\\t{%1, %0|%0, %1}\";
2467 [(set_attr "type" "alu1")
2468 (set_attr "mode" "DI")
2469 (set_attr "length_immediate" "1")])
2471 (define_insn "*movdi_2"
2472 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2473 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2475 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2479 movq\\t{%1, %0|%0, %1}
2480 movq\\t{%1, %0|%0, %1}
2481 movq\\t{%1, %0|%0, %1}
2482 movdqa\\t{%1, %0|%0, %1}
2483 movq\\t{%1, %0|%0, %1}"
2484 [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
2485 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
2488 [(set (match_operand:DI 0 "push_operand" "")
2489 (match_operand:DI 1 "general_operand" ""))]
2490 "!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[1])"
2492 "ix86_split_long_move (operands); DONE;")
2494 ;; %%% This multiword shite has got to go.
2496 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2497 (match_operand:DI 1 "general_operand" ""))]
2498 "!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[0])
2499 && ! MMX_REG_P (operands[1])"
2501 "ix86_split_long_move (operands); DONE;")
2503 (define_insn "*movdi_1_rex64"
2504 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
2505 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
2506 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2510 switch (get_attr_type (insn))
2513 if (register_operand (operands[0], DImode)
2514 && register_operand (operands[1], DImode))
2515 return \"movdqa\\t{%1, %0|%0, %1}\";
2518 return \"movq\\t{%1, %0|%0, %1}\";
2522 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
2524 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2526 if (get_attr_mode (insn) == MODE_SI)
2527 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2528 else if (which_alternative == 2)
2529 return \"movabs{q}\\t{%1, %0|%0, %1}\";
2531 return \"mov{q}\\t{%1, %0|%0, %1}\";
2535 (cond [(eq_attr "alternative" "5,6")
2536 (const_string "mmx")
2537 (eq_attr "alternative" "7,8")
2538 (const_string "sse")
2539 (eq_attr "alternative" "4")
2540 (const_string "multi")
2541 (and (ne (symbol_ref "flag_pic") (const_int 0))
2542 (match_operand:DI 1 "symbolic_operand" ""))
2543 (const_string "lea")
2545 (const_string "imov")))
2546 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
2547 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
2548 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
2550 ;; Stores and loads of ax to arbitary constant address.
2551 ;; We fake an second form of instruction to force reload to load address
2552 ;; into register when rax is not available
2553 (define_insn "*movabsdi_1_rex64"
2554 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2555 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2558 movabs{q}\\t{%1, %P0|%P0, %1}
2559 mov{q}\\t{%1, %a0|%a0, %1}
2560 movabs{q}\\t{%1, %a0|%a0, %1}"
2561 [(set_attr "type" "imov")
2562 (set_attr "modrm" "0,*,*")
2563 (set_attr "length_address" "8,0,0")
2564 (set_attr "length_immediate" "0,*,*")
2565 (set_attr "memory" "store")
2566 (set_attr "mode" "DI")])
2568 (define_insn "*movabsdi_2_rex64"
2569 [(set (match_operand:DI 0 "register_operand" "=a,r")
2570 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2573 movabs{q}\\t{%P1, %0|%0, %P1}
2574 mov{q}\\t{%a1, %0|%0, %a1}"
2575 [(set_attr "type" "imov")
2576 (set_attr "modrm" "0,*")
2577 (set_attr "length_address" "8,0")
2578 (set_attr "length_immediate" "0")
2579 (set_attr "memory" "load")
2580 (set_attr "mode" "DI")])
2582 ;; Convert impossible stores of immediate to existing instructions.
2583 ;; First try to get scratch register and go trought it. In case this
2584 ;; fails, move by 32bit parts.
2586 [(match_scratch:DI 2 "r")
2587 (set (match_operand:DI 0 "memory_operand" "")
2588 (match_operand:DI 1 "immediate_operand" ""))]
2589 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2590 && !x86_64_immediate_operand (operands[1], DImode)"
2591 [(set (match_dup 2) (match_dup 1))
2592 (set (match_dup 0) (match_dup 2))]
2595 ;; We need to define this as both peepholer and splitter for case
2596 ;; peephole2 pass is not run.
2598 [(set (match_operand:DI 0 "memory_operand" "")
2599 (match_operand:DI 1 "immediate_operand" ""))]
2600 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2601 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2602 [(set (match_dup 2) (match_dup 3))
2603 (set (match_dup 4) (match_dup 5))]
2604 "split_di (operands, 2, operands + 2, operands + 4);")
2607 [(set (match_operand:DI 0 "memory_operand" "")
2608 (match_operand:DI 1 "immediate_operand" ""))]
2609 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2610 && !symbolic_operand (operands[1], DImode)
2611 && !x86_64_immediate_operand (operands[1], DImode)"
2612 [(set (match_dup 2) (match_dup 3))
2613 (set (match_dup 4) (match_dup 5))]
2614 "split_di (operands, 2, operands + 2, operands + 4);")
2616 (define_insn "*swapdi_rex64"
2617 [(set (match_operand:DI 0 "register_operand" "+r")
2618 (match_operand:DI 1 "register_operand" "+r"))
2623 [(set_attr "type" "imov")
2624 (set_attr "pent_pair" "np")
2625 (set_attr "athlon_decode" "vector")
2626 (set_attr "mode" "DI")
2627 (set_attr "modrm" "0")
2628 (set_attr "ppro_uops" "few")])
2631 (define_expand "movsf"
2632 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2633 (match_operand:SF 1 "general_operand" ""))]
2635 "ix86_expand_move (SFmode, operands); DONE;")
2637 (define_insn "*pushsf"
2638 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2639 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2643 switch (which_alternative)
2646 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2647 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2648 operands[2] = stack_pointer_rtx;
2649 operands[3] = GEN_INT (4);
2650 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2651 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2653 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2656 return \"push{l}\\t%1\";
2664 [(set_attr "type" "multi,push,multi")
2665 (set_attr "mode" "SF,SI,SF")])
2667 (define_insn "*pushsf_rex64"
2668 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2669 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2673 switch (which_alternative)
2676 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2677 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2678 operands[2] = stack_pointer_rtx;
2679 operands[3] = GEN_INT (8);
2680 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2681 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2683 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2686 return \"push{q}\\t%q1\";
2695 [(set_attr "type" "multi,push,multi")
2696 (set_attr "mode" "SF,DI,SF")])
2699 [(set (match_operand:SF 0 "push_operand" "")
2700 (match_operand:SF 1 "memory_operand" ""))]
2702 && GET_CODE (operands[1]) == MEM
2703 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2704 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2707 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2710 ;; %%% Kill this when call knows how to work this out.
2712 [(set (match_operand:SF 0 "push_operand" "")
2713 (match_operand:SF 1 "register_operand" ""))]
2714 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2715 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2716 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2719 [(set (match_operand:SF 0 "push_operand" "")
2720 (match_operand:SF 1 "register_operand" ""))]
2721 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2722 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2723 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2725 (define_insn "*movsf_1"
2726 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2727 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2728 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2729 && (reload_in_progress || reload_completed
2730 || GET_CODE (operands[1]) != CONST_DOUBLE
2731 || memory_operand (operands[0], SFmode))"
2734 switch (which_alternative)
2737 if (REG_P (operands[1])
2738 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2739 return \"fstp\\t%y0\";
2740 else if (STACK_TOP_P (operands[0]))
2741 return \"fld%z1\\t%y1\";
2743 return \"fst\\t%y0\";
2746 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2747 return \"fstp%z0\\t%y0\";
2749 return \"fst%z0\\t%y0\";
2752 switch (standard_80387_constant_p (operands[1]))
2763 return \"mov{l}\\t{%1, %0|%0, %1}\";
2765 return \"pxor\\t%0, %0\";
2767 if (TARGET_PARTIAL_REG_DEPENDENCY)
2768 return \"movaps\\t{%1, %0|%0, %1}\";
2770 return \"movss\\t{%1, %0|%0, %1}\";
2773 return \"movss\\t{%1, %0|%0, %1}\";
2779 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2780 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2782 (define_insn "*swapsf"
2783 [(set (match_operand:SF 0 "register_operand" "+f")
2784 (match_operand:SF 1 "register_operand" "+f"))
2787 "reload_completed || !TARGET_SSE2"
2790 if (STACK_TOP_P (operands[0]))
2791 return \"fxch\\t%1\";
2793 return \"fxch\\t%0\";
2795 [(set_attr "type" "fxch")
2796 (set_attr "mode" "SF")])
2798 (define_expand "movdf"
2799 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2800 (match_operand:DF 1 "general_operand" ""))]
2802 "ix86_expand_move (DFmode, operands); DONE;")
2804 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2805 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2806 ;; On the average, pushdf using integers can be still shorter. Allow this
2807 ;; pattern for optimize_size too.
2809 (define_insn "*pushdf_nointeger"
2810 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2811 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2812 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2815 switch (which_alternative)
2818 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2819 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2820 operands[2] = stack_pointer_rtx;
2821 operands[3] = GEN_INT (8);
2822 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2823 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2825 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2836 [(set_attr "type" "multi")
2837 (set_attr "mode" "DF,SI,SI,DF")])
2839 (define_insn "*pushdf_integer"
2840 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2841 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2842 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2845 switch (which_alternative)
2848 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2849 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2850 operands[2] = stack_pointer_rtx;
2851 operands[3] = GEN_INT (8);
2853 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2854 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2856 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2858 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2859 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2861 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2872 [(set_attr "type" "multi")
2873 (set_attr "mode" "DF,SI,DF")])
2875 ;; %%% Kill this when call knows how to work this out.
2877 [(set (match_operand:DF 0 "push_operand" "")
2878 (match_operand:DF 1 "register_operand" ""))]
2879 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2880 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2881 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2885 [(set (match_operand:DF 0 "push_operand" "")
2886 (match_operand:DF 1 "register_operand" ""))]
2887 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2888 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2889 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2893 [(set (match_operand:DF 0 "push_operand" "")
2894 (match_operand:DF 1 "general_operand" ""))]
2897 "ix86_split_long_move (operands); DONE;")
2899 ;; Moving is usually shorter when only FP registers are used. This separate
2900 ;; movdf pattern avoids the use of integer registers for FP operations
2901 ;; when optimizing for size.
2903 (define_insn "*movdf_nointeger"
2904 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2905 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2906 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2907 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2908 && (reload_in_progress || reload_completed
2909 || GET_CODE (operands[1]) != CONST_DOUBLE
2910 || memory_operand (operands[0], DFmode))"
2913 switch (which_alternative)
2916 if (REG_P (operands[1])
2917 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2918 return \"fstp\\t%y0\";
2919 else if (STACK_TOP_P (operands[0]))
2920 return \"fld%z1\\t%y1\";
2922 return \"fst\\t%y0\";
2925 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2926 return \"fstp%z0\\t%y0\";
2928 return \"fst%z0\\t%y0\";
2931 switch (standard_80387_constant_p (operands[1]))
2944 return \"pxor\\t%0, %0\";
2946 if (TARGET_PARTIAL_REG_DEPENDENCY)
2947 return \"movapd\\t{%1, %0|%0, %1}\";
2949 return \"movsd\\t{%1, %0|%0, %1}\";
2952 return \"movsd\\t{%1, %0|%0, %1}\";
2958 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2959 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2961 (define_insn "*movdf_integer"
2962 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2963 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2964 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2965 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2966 && (reload_in_progress || reload_completed
2967 || GET_CODE (operands[1]) != CONST_DOUBLE
2968 || memory_operand (operands[0], DFmode))"
2971 switch (which_alternative)
2974 if (REG_P (operands[1])
2975 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2976 return \"fstp\\t%y0\";
2977 else if (STACK_TOP_P (operands[0]))
2978 return \"fld%z1\\t%y1\";
2980 return \"fst\\t%y0\";
2983 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2984 return \"fstp%z0\\t%y0\";
2986 return \"fst%z0\\t%y0\";
2989 switch (standard_80387_constant_p (operands[1]))
3003 return \"pxor\\t%0, %0\";
3005 if (TARGET_PARTIAL_REG_DEPENDENCY)
3006 return \"movapd\\t{%1, %0|%0, %1}\";
3008 return \"movsd\\t{%1, %0|%0, %1}\";
3011 return \"movsd\\t{%1, %0|%0, %1}\";
3017 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
3018 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
3021 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3022 (match_operand:DF 1 "general_operand" ""))]
3024 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3025 && ! (ANY_FP_REG_P (operands[0]) ||
3026 (GET_CODE (operands[0]) == SUBREG
3027 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3028 && ! (ANY_FP_REG_P (operands[1]) ||
3029 (GET_CODE (operands[1]) == SUBREG
3030 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3032 "ix86_split_long_move (operands); DONE;")
3034 (define_insn "*swapdf"
3035 [(set (match_operand:DF 0 "register_operand" "+f")
3036 (match_operand:DF 1 "register_operand" "+f"))
3039 "reload_completed || !TARGET_SSE2"
3042 if (STACK_TOP_P (operands[0]))
3043 return \"fxch\\t%1\";
3045 return \"fxch\\t%0\";
3047 [(set_attr "type" "fxch")
3048 (set_attr "mode" "DF")])
3050 (define_expand "movxf"
3051 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3052 (match_operand:XF 1 "general_operand" ""))]
3054 "ix86_expand_move (XFmode, operands); DONE;")
3056 (define_expand "movtf"
3057 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3058 (match_operand:TF 1 "general_operand" ""))]
3060 "ix86_expand_move (TFmode, operands); DONE;")
3062 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3063 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
3064 ;; Pushing using integer instructions is longer except for constants
3065 ;; and direct memory references.
3066 ;; (assuming that any given constant is pushed only once, but this ought to be
3067 ;; handled elsewhere).
3069 (define_insn "*pushxf_nointeger"
3070 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3071 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3072 "optimize_size && !TARGET_64BIT"
3075 switch (which_alternative)
3078 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3079 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3080 operands[2] = stack_pointer_rtx;
3081 operands[3] = GEN_INT (12);
3082 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3083 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3085 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3095 [(set_attr "type" "multi")
3096 (set_attr "mode" "XF,SI,SI")])
3098 (define_insn "*pushtf_nointeger"
3099 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3100 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3104 switch (which_alternative)
3107 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3108 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3109 operands[2] = stack_pointer_rtx;
3110 operands[3] = GEN_INT (16);
3111 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3112 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3114 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3124 [(set_attr "type" "multi")
3125 (set_attr "mode" "XF,SI,SI")])
3127 (define_insn "*pushxf_integer"
3128 [(set (match_operand:XF 0 "push_operand" "=<,<")
3129 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3130 "!optimize_size && !TARGET_64BIT"
3133 switch (which_alternative)
3136 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3137 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3138 operands[2] = stack_pointer_rtx;
3139 operands[3] = GEN_INT (12);
3140 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3141 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3143 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3152 [(set_attr "type" "multi")
3153 (set_attr "mode" "XF,SI")])
3155 (define_insn "*pushtf_integer"
3156 [(set (match_operand:TF 0 "push_operand" "=<,<")
3157 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3161 switch (which_alternative)
3164 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3165 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3166 operands[2] = stack_pointer_rtx;
3167 operands[3] = GEN_INT (16);
3169 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3170 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3172 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3174 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3175 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3177 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3186 [(set_attr "type" "multi")
3187 (set_attr "mode" "XF,SI")])
3190 [(set (match_operand 0 "push_operand" "")
3191 (match_operand 1 "general_operand" ""))]
3193 && (GET_MODE (operands[0]) == XFmode
3194 || GET_MODE (operands[0]) == TFmode
3195 || GET_MODE (operands[0]) == DFmode)
3196 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3198 "ix86_split_long_move (operands); DONE;")
3201 [(set (match_operand:XF 0 "push_operand" "")
3202 (match_operand:XF 1 "register_operand" ""))]
3203 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3204 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3205 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3208 [(set (match_operand:TF 0 "push_operand" "")
3209 (match_operand:TF 1 "register_operand" ""))]
3210 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3211 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3212 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3215 [(set (match_operand:TF 0 "push_operand" "")
3216 (match_operand:TF 1 "register_operand" ""))]
3217 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3218 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3219 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3221 ;; Do not use integer registers when optimizing for size
3222 (define_insn "*movxf_nointeger"
3223 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3224 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3225 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3228 && (reload_in_progress || reload_completed
3229 || GET_CODE (operands[1]) != CONST_DOUBLE
3230 || memory_operand (operands[0], XFmode))"
3233 switch (which_alternative)
3236 if (REG_P (operands[1])
3237 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3238 return \"fstp\\t%y0\";
3239 else if (STACK_TOP_P (operands[0]))
3240 return \"fld%z1\\t%y1\";
3242 return \"fst\\t%y0\";
3245 /* There is no non-popping store to memory for XFmode. So if
3246 we need one, follow the store with a load. */
3247 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3248 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3250 return \"fstp%z0\\t%y0\";
3253 switch (standard_80387_constant_p (operands[1]))
3267 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3268 (set_attr "mode" "XF,XF,XF,SI,SI")])
3270 (define_insn "*movtf_nointeger"
3271 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3272 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3273 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3275 && (reload_in_progress || reload_completed
3276 || GET_CODE (operands[1]) != CONST_DOUBLE
3277 || memory_operand (operands[0], TFmode))"
3280 switch (which_alternative)
3283 if (REG_P (operands[1])
3284 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3285 return \"fstp\\t%y0\";
3286 else if (STACK_TOP_P (operands[0]))
3287 return \"fld%z1\\t%y1\";
3289 return \"fst\\t%y0\";
3292 /* There is no non-popping store to memory for XFmode. So if
3293 we need one, follow the store with a load. */
3294 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3295 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3297 return \"fstp%z0\\t%y0\";
3300 switch (standard_80387_constant_p (operands[1]))
3314 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3315 (set_attr "mode" "XF,XF,XF,SI,SI")])
3317 (define_insn "*movxf_integer"
3318 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3319 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3320 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3323 && (reload_in_progress || reload_completed
3324 || GET_CODE (operands[1]) != CONST_DOUBLE
3325 || memory_operand (operands[0], XFmode))"
3328 switch (which_alternative)
3331 if (REG_P (operands[1])
3332 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3333 return \"fstp\\t%y0\";
3334 else if (STACK_TOP_P (operands[0]))
3335 return \"fld%z1\\t%y1\";
3337 return \"fst\\t%y0\";
3340 /* There is no non-popping store to memory for XFmode. So if
3341 we need one, follow the store with a load. */
3342 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3343 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3345 return \"fstp%z0\\t%y0\";
3348 switch (standard_80387_constant_p (operands[1]))
3362 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3363 (set_attr "mode" "XF,XF,XF,SI,SI")])
3365 (define_insn "*movtf_integer"
3366 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3367 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3368 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3370 && (reload_in_progress || reload_completed
3371 || GET_CODE (operands[1]) != CONST_DOUBLE
3372 || memory_operand (operands[0], TFmode))"
3375 switch (which_alternative)
3378 if (REG_P (operands[1])
3379 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3380 return \"fstp\\t%y0\";
3381 else if (STACK_TOP_P (operands[0]))
3382 return \"fld%z1\\t%y1\";
3384 return \"fst\\t%y0\";
3387 /* There is no non-popping store to memory for XFmode. So if
3388 we need one, follow the store with a load. */
3389 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3390 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3392 return \"fstp%z0\\t%y0\";
3395 switch (standard_80387_constant_p (operands[1]))
3409 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3410 (set_attr "mode" "XF,XF,XF,SI,SI")])
3413 [(set (match_operand 0 "nonimmediate_operand" "")
3414 (match_operand 1 "general_operand" ""))]
3416 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3417 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3418 && ! (ANY_FP_REG_P (operands[0]) ||
3419 (GET_CODE (operands[0]) == SUBREG
3420 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3421 && ! (ANY_FP_REG_P (operands[1]) ||
3422 (GET_CODE (operands[1]) == SUBREG
3423 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3425 "ix86_split_long_move (operands); DONE;")
3428 [(set (match_operand 0 "register_operand" "")
3429 (match_operand 1 "memory_operand" ""))]
3431 && GET_CODE (operands[1]) == MEM
3432 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3433 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3434 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3435 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3436 && (!(SSE_REG_P (operands[0]) ||
3437 (GET_CODE (operands[0]) == SUBREG
3438 && SSE_REG_P (SUBREG_REG (operands[0]))))
3439 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3440 && (!(FP_REG_P (operands[0]) ||
3441 (GET_CODE (operands[0]) == SUBREG
3442 && FP_REG_P (SUBREG_REG (operands[0]))))
3443 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3446 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3448 (define_insn "swapxf"
3449 [(set (match_operand:XF 0 "register_operand" "+f")
3450 (match_operand:XF 1 "register_operand" "+f"))
3456 if (STACK_TOP_P (operands[0]))
3457 return \"fxch\\t%1\";
3459 return \"fxch\\t%0\";
3461 [(set_attr "type" "fxch")
3462 (set_attr "mode" "XF")])
3464 (define_insn "swaptf"
3465 [(set (match_operand:TF 0 "register_operand" "+f")
3466 (match_operand:TF 1 "register_operand" "+f"))
3472 if (STACK_TOP_P (operands[0]))
3473 return \"fxch\\t%1\";
3475 return \"fxch\\t%0\";
3477 [(set_attr "type" "fxch")
3478 (set_attr "mode" "XF")])
3480 ;; Zero extension instructions
3482 (define_expand "zero_extendhisi2"
3483 [(set (match_operand:SI 0 "register_operand" "")
3484 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3488 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3490 operands[1] = force_reg (HImode, operands[1]);
3491 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3496 (define_insn "zero_extendhisi2_and"
3497 [(set (match_operand:SI 0 "register_operand" "=r")
3498 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3499 (clobber (reg:CC 17))]
3500 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3502 [(set_attr "type" "alu1")
3503 (set_attr "mode" "SI")])
3506 [(set (match_operand:SI 0 "register_operand" "")
3507 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3508 (clobber (reg:CC 17))]
3509 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3510 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3511 (clobber (reg:CC 17))])]
3514 (define_insn "*zero_extendhisi2_movzwl"
3515 [(set (match_operand:SI 0 "register_operand" "=r")
3516 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3517 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3518 "movz{wl|x}\\t{%1, %0|%0, %1}"
3519 [(set_attr "type" "imovx")
3520 (set_attr "mode" "SI")])
3522 (define_expand "zero_extendqihi2"
3524 [(set (match_operand:HI 0 "register_operand" "")
3525 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3526 (clobber (reg:CC 17))])]
3530 (define_insn "*zero_extendqihi2_and"
3531 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3532 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3533 (clobber (reg:CC 17))]
3534 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3536 [(set_attr "type" "alu1")
3537 (set_attr "mode" "HI")])
3539 (define_insn "*zero_extendqihi2_movzbw_and"
3540 [(set (match_operand:HI 0 "register_operand" "=r,r")
3541 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3542 (clobber (reg:CC 17))]
3543 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3545 [(set_attr "type" "imovx,alu1")
3546 (set_attr "mode" "HI")])
3548 (define_insn "*zero_extendqihi2_movzbw"
3549 [(set (match_operand:HI 0 "register_operand" "=r")
3550 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3551 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3552 "movz{bw|x}\\t{%1, %0|%0, %1}"
3553 [(set_attr "type" "imovx")
3554 (set_attr "mode" "HI")])
3556 ;; For the movzbw case strip only the clobber
3558 [(set (match_operand:HI 0 "register_operand" "")
3559 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3560 (clobber (reg:CC 17))]
3562 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3563 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3564 [(set (match_operand:HI 0 "register_operand" "")
3565 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3567 ;; When source and destination does not overlap, clear destination
3568 ;; first and then do the movb
3570 [(set (match_operand:HI 0 "register_operand" "")
3571 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3572 (clobber (reg:CC 17))]
3574 && ANY_QI_REG_P (operands[0])
3575 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3576 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3577 [(set (match_dup 0) (const_int 0))
3578 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3579 "operands[2] = gen_lowpart (QImode, operands[0]);")
3581 ;; Rest is handled by single and.
3583 [(set (match_operand:HI 0 "register_operand" "")
3584 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3585 (clobber (reg:CC 17))]
3587 && true_regnum (operands[0]) == true_regnum (operands[1])"
3588 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3589 (clobber (reg:CC 17))])]
3592 (define_expand "zero_extendqisi2"
3594 [(set (match_operand:SI 0 "register_operand" "")
3595 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3596 (clobber (reg:CC 17))])]
3600 (define_insn "*zero_extendqisi2_and"
3601 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3602 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3603 (clobber (reg:CC 17))]
3604 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3606 [(set_attr "type" "alu1")
3607 (set_attr "mode" "SI")])
3609 (define_insn "*zero_extendqisi2_movzbw_and"
3610 [(set (match_operand:SI 0 "register_operand" "=r,r")
3611 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3612 (clobber (reg:CC 17))]
3613 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3615 [(set_attr "type" "imovx,alu1")
3616 (set_attr "mode" "SI")])
3618 (define_insn "*zero_extendqisi2_movzbw"
3619 [(set (match_operand:SI 0 "register_operand" "=r")
3620 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3621 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3622 "movz{bl|x}\\t{%1, %0|%0, %1}"
3623 [(set_attr "type" "imovx")
3624 (set_attr "mode" "SI")])
3626 ;; For the movzbl case strip only the clobber
3628 [(set (match_operand:SI 0 "register_operand" "")
3629 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3630 (clobber (reg:CC 17))]
3632 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3633 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3635 (zero_extend:SI (match_dup 1)))])
3637 ;; When source and destination does not overlap, clear destination
3638 ;; first and then do the movb
3640 [(set (match_operand:SI 0 "register_operand" "")
3641 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3642 (clobber (reg:CC 17))]
3644 && ANY_QI_REG_P (operands[0])
3645 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3646 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3647 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3648 [(set (match_dup 0) (const_int 0))
3649 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3650 "operands[2] = gen_lowpart (QImode, operands[0]);")
3652 ;; Rest is handled by single and.
3654 [(set (match_operand:SI 0 "register_operand" "")
3655 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3656 (clobber (reg:CC 17))]
3658 && true_regnum (operands[0]) == true_regnum (operands[1])"
3659 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3660 (clobber (reg:CC 17))])]
3663 ;; %%% Kill me once multi-word ops are sane.
3664 (define_expand "zero_extendsidi2"
3665 [(set (match_operand:DI 0 "register_operand" "=r")
3666 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3670 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3675 (define_insn "zero_extendsidi2_32"
3676 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3677 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3678 (clobber (reg:CC 17))]
3681 [(set_attr "mode" "SI")])
3683 (define_insn "zero_extendsidi2_rex64"
3684 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3685 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3688 mov\\t{%k1, %k0|%k0, %k1}
3690 [(set_attr "type" "imovx,imov")
3691 (set_attr "mode" "SI,DI")])
3694 [(set (match_operand:DI 0 "memory_operand" "")
3695 (zero_extend:DI (match_dup 0)))]
3697 [(set (match_dup 4) (const_int 0))]
3698 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3701 [(set (match_operand:DI 0 "register_operand" "")
3702 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3703 (clobber (reg:CC 17))]
3704 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
3706 [(set (match_dup 4) (const_int 0))]
3707 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3710 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3711 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3712 (clobber (reg:CC 17))]
3713 "reload_completed && !TARGET_64BIT"
3714 [(set (match_dup 3) (match_dup 1))
3715 (set (match_dup 4) (const_int 0))]
3716 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3718 (define_insn "zero_extendhidi2"
3719 [(set (match_operand:DI 0 "register_operand" "=r,r")
3720 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3723 movz{wl|x}\\t{%1, %k0|%k0, %1}
3724 movz{wq|x}\\t{%1, %0|%0, %1}"
3725 [(set_attr "type" "imovx")
3726 (set_attr "mode" "SI,DI")])
3728 (define_insn "zero_extendqidi2"
3729 [(set (match_operand:DI 0 "register_operand" "=r,r")
3730 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3733 movz{bl|x}\\t{%1, %k0|%k0, %1}
3734 movz{bq|x}\\t{%1, %0|%0, %1}"
3735 [(set_attr "type" "imovx")
3736 (set_attr "mode" "SI,DI")])
3738 ;; Sign extension instructions
3740 (define_expand "extendsidi2"
3741 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3742 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3743 (clobber (reg:CC 17))
3744 (clobber (match_scratch:SI 2 ""))])]
3750 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3755 (define_insn "*extendsidi2_1"
3756 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3757 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3758 (clobber (reg:CC 17))
3759 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3763 (define_insn "extendsidi2_rex64"
3764 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3765 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3769 movs{lq|x}\\t{%1,%0|%0, %1}"
3770 [(set_attr "type" "imovx")
3771 (set_attr "mode" "DI")
3772 (set_attr "prefix_0f" "0")
3773 (set_attr "modrm" "0,1")])
3775 (define_insn "extendhidi2"
3776 [(set (match_operand:DI 0 "register_operand" "=r")
3777 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3779 "movs{wq|x}\\t{%1,%0|%0, %1}"
3780 [(set_attr "type" "imovx")
3781 (set_attr "mode" "DI")])
3783 (define_insn "extendqidi2"
3784 [(set (match_operand:DI 0 "register_operand" "=r")
3785 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3787 "movs{bq|x}\\t{%1,%0|%0, %1}"
3788 [(set_attr "type" "imovx")
3789 (set_attr "mode" "DI")])
3791 ;; Extend to memory case when source register does die.
3793 [(set (match_operand:DI 0 "memory_operand" "")
3794 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3795 (clobber (reg:CC 17))
3796 (clobber (match_operand:SI 2 "register_operand" ""))]
3798 && dead_or_set_p (insn, operands[1])
3799 && !reg_mentioned_p (operands[1], operands[0]))"
3800 [(set (match_dup 3) (match_dup 1))
3801 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3802 (clobber (reg:CC 17))])
3803 (set (match_dup 4) (match_dup 1))]
3804 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3806 ;; Extend to memory case when source register does not die.
3808 [(set (match_operand:DI 0 "memory_operand" "")
3809 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3810 (clobber (reg:CC 17))
3811 (clobber (match_operand:SI 2 "register_operand" ""))]
3816 split_di (&operands[0], 1, &operands[3], &operands[4]);
3818 emit_move_insn (operands[3], operands[1]);
3820 /* Generate a cltd if possible and doing so it profitable. */
3821 if (true_regnum (operands[1]) == 0
3822 && true_regnum (operands[2]) == 1
3823 && (optimize_size || TARGET_USE_CLTD))
3825 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3829 emit_move_insn (operands[2], operands[1]);
3830 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3832 emit_move_insn (operands[4], operands[2]);
3836 ;; Extend to register case. Optimize case where source and destination
3837 ;; registers match and cases where we can use cltd.
3839 [(set (match_operand:DI 0 "register_operand" "")
3840 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3841 (clobber (reg:CC 17))
3842 (clobber (match_scratch:SI 2 ""))]
3847 split_di (&operands[0], 1, &operands[3], &operands[4]);
3849 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3850 emit_move_insn (operands[3], operands[1]);
3852 /* Generate a cltd if possible and doing so it profitable. */
3853 if (true_regnum (operands[3]) == 0
3854 && (optimize_size || TARGET_USE_CLTD))
3856 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3860 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3861 emit_move_insn (operands[4], operands[1]);
3863 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3867 (define_insn "extendhisi2"
3868 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3869 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3873 switch (get_attr_prefix_0f (insn))
3876 return \"{cwtl|cwde}\";
3878 return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
3881 [(set_attr "type" "imovx")
3882 (set_attr "mode" "SI")
3883 (set (attr "prefix_0f")
3884 ;; movsx is short decodable while cwtl is vector decoded.
3885 (if_then_else (and (eq_attr "cpu" "!k6")
3886 (eq_attr "alternative" "0"))
3888 (const_string "1")))
3890 (if_then_else (eq_attr "prefix_0f" "0")
3892 (const_string "1")))])
3894 (define_insn "*extendhisi2_zext"
3895 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3897 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3901 switch (get_attr_prefix_0f (insn))
3904 return \"{cwtl|cwde}\";
3906 return \"movs{wl|x}\\t{%1,%k0|%k0, %1}\";
3909 [(set_attr "type" "imovx")
3910 (set_attr "mode" "SI")
3911 (set (attr "prefix_0f")
3912 ;; movsx is short decodable while cwtl is vector decoded.
3913 (if_then_else (and (eq_attr "cpu" "!k6")
3914 (eq_attr "alternative" "0"))
3916 (const_string "1")))
3918 (if_then_else (eq_attr "prefix_0f" "0")
3920 (const_string "1")))])
3922 (define_insn "extendqihi2"
3923 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3924 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3928 switch (get_attr_prefix_0f (insn))
3931 return \"{cbtw|cbw}\";
3933 return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
3936 [(set_attr "type" "imovx")
3937 (set_attr "mode" "HI")
3938 (set (attr "prefix_0f")
3939 ;; movsx is short decodable while cwtl is vector decoded.
3940 (if_then_else (and (eq_attr "cpu" "!k6")
3941 (eq_attr "alternative" "0"))
3943 (const_string "1")))
3945 (if_then_else (eq_attr "prefix_0f" "0")
3947 (const_string "1")))])
3949 (define_insn "extendqisi2"
3950 [(set (match_operand:SI 0 "register_operand" "=r")
3951 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3953 "movs{bl|x}\\t{%1,%0|%0, %1}"
3954 [(set_attr "type" "imovx")
3955 (set_attr "mode" "SI")])
3957 (define_insn "*extendqisi2_zext"
3958 [(set (match_operand:DI 0 "register_operand" "=r")
3960 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3962 "movs{bl|x}\\t{%1,%k0|%k0, %1}"
3963 [(set_attr "type" "imovx")
3964 (set_attr "mode" "SI")])
3966 ;; Conversions between float and double.
3968 ;; These are all no-ops in the model used for the 80387. So just
3971 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3972 (define_insn "*dummy_extendsfdf2"
3973 [(set (match_operand:DF 0 "push_operand" "=<")
3974 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3979 [(set (match_operand:DF 0 "push_operand" "")
3980 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3981 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3982 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3983 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3986 [(set (match_operand:DF 0 "push_operand" "")
3987 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3988 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3989 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3990 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3992 (define_insn "*dummy_extendsfxf2"
3993 [(set (match_operand:XF 0 "push_operand" "=<")
3994 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3999 [(set (match_operand:XF 0 "push_operand" "")
4000 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
4001 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4002 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4003 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4005 (define_insn "*dummy_extendsftf2"
4006 [(set (match_operand:TF 0 "push_operand" "=<")
4007 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
4012 [(set (match_operand:TF 0 "push_operand" "")
4013 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4014 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4015 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4016 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
4019 [(set (match_operand:TF 0 "push_operand" "")
4020 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4021 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4022 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4023 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4025 (define_insn "*dummy_extenddfxf2"
4026 [(set (match_operand:XF 0 "push_operand" "=<")
4027 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4032 [(set (match_operand:XF 0 "push_operand" "")
4033 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
4034 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4035 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4036 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4038 (define_insn "*dummy_extenddftf2"
4039 [(set (match_operand:TF 0 "push_operand" "=<")
4040 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4045 [(set (match_operand:TF 0 "push_operand" "")
4046 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4047 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4048 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4049 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4052 [(set (match_operand:TF 0 "push_operand" "")
4053 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4054 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4055 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4056 (set (mem:TF (reg:DI 7)) (float_extend:XF (match_dup 1)))])
4058 (define_expand "extendsfdf2"
4059 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4060 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
4061 "TARGET_80387 || TARGET_SSE2"
4064 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4065 operands[1] = force_reg (SFmode, operands[1]);
4068 (define_insn "*extendsfdf2_1"
4069 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4070 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4071 "(TARGET_80387 || TARGET_SSE2)
4072 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4075 switch (which_alternative)
4078 if (REG_P (operands[1])
4079 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4080 return \"fstp\\t%y0\";
4081 else if (STACK_TOP_P (operands[0]))
4082 return \"fld%z1\\t%y1\";
4084 return \"fst\\t%y0\";
4087 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4088 return \"fstp%z0\\t%y0\";
4091 return \"fst%z0\\t%y0\";
4093 return \"cvtss2sd\\t{%1, %0|%0, %1}\";
4099 [(set_attr "type" "fmov,fmov,sse")
4100 (set_attr "mode" "SF,XF,DF")])
4102 (define_insn "*extendsfdf2_1_sse_only"
4103 [(set (match_operand:DF 0 "register_operand" "=Y")
4104 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4105 "!TARGET_80387 && TARGET_SSE2
4106 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4107 "cvtss2sd\\t{%1, %0|%0, %1}"
4108 [(set_attr "type" "sse")
4109 (set_attr "mode" "DF")])
4111 (define_expand "extendsfxf2"
4112 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4113 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4114 "TARGET_80387 && !TARGET_64BIT"
4117 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4118 operands[1] = force_reg (SFmode, operands[1]);
4121 (define_insn "*extendsfxf2_1"
4122 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4123 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4124 "TARGET_80387 && !TARGET_64BIT
4125 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4128 switch (which_alternative)
4131 if (REG_P (operands[1])
4132 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4133 return \"fstp\\t%y0\";
4134 else if (STACK_TOP_P (operands[0]))
4135 return \"fld%z1\\t%y1\";
4137 return \"fst\\t%y0\";
4140 /* There is no non-popping store to memory for XFmode. So if
4141 we need one, follow the store with a load. */
4142 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4143 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4145 return \"fstp%z0\\t%y0\";
4151 [(set_attr "type" "fmov")
4152 (set_attr "mode" "SF,XF")])
4154 (define_expand "extendsftf2"
4155 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4156 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4160 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4161 operands[1] = force_reg (SFmode, operands[1]);
4164 (define_insn "*extendsftf2_1"
4165 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4166 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4168 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4171 switch (which_alternative)
4174 if (REG_P (operands[1])
4175 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4176 return \"fstp\\t%y0\";
4177 else if (STACK_TOP_P (operands[0]))
4178 return \"fld%z1\\t%y1\";
4180 return \"fst\\t%y0\";
4183 /* There is no non-popping store to memory for XFmode. So if
4184 we need one, follow the store with a load. */
4185 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4186 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4188 return \"fstp%z0\\t%y0\";
4194 [(set_attr "type" "fmov")
4195 (set_attr "mode" "SF,XF")])
4197 (define_expand "extenddfxf2"
4198 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4199 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4200 "TARGET_80387 && !TARGET_64BIT"
4203 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4204 operands[1] = force_reg (DFmode, operands[1]);
4207 (define_insn "*extenddfxf2_1"
4208 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4209 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4210 "TARGET_80387 && !TARGET_64BIT
4211 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4214 switch (which_alternative)
4217 if (REG_P (operands[1])
4218 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4219 return \"fstp\\t%y0\";
4220 else if (STACK_TOP_P (operands[0]))
4221 return \"fld%z1\\t%y1\";
4223 return \"fst\\t%y0\";
4226 /* There is no non-popping store to memory for XFmode. So if
4227 we need one, follow the store with a load. */
4228 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4229 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4231 return \"fstp%z0\\t%y0\";
4237 [(set_attr "type" "fmov")
4238 (set_attr "mode" "DF,XF")])
4240 (define_expand "extenddftf2"
4241 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4242 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4246 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4247 operands[1] = force_reg (DFmode, operands[1]);
4250 (define_insn "*extenddftf2_1"
4251 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4252 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4254 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4257 switch (which_alternative)
4260 if (REG_P (operands[1])
4261 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4262 return \"fstp\\t%y0\";
4263 else if (STACK_TOP_P (operands[0]))
4264 return \"fld%z1\\t%y1\";
4266 return \"fst\\t%y0\";
4269 /* There is no non-popping store to memory for XFmode. So if
4270 we need one, follow the store with a load. */
4271 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4272 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4274 return \"fstp%z0\\t%y0\";
4280 [(set_attr "type" "fmov")
4281 (set_attr "mode" "DF,XF")])
4283 ;; %%% This seems bad bad news.
4284 ;; This cannot output into an f-reg because there is no way to be sure
4285 ;; of truncating in that case. Otherwise this is just like a simple move
4286 ;; insn. So we pretend we can output to a reg in order to get better
4287 ;; register preferencing, but we really use a stack slot.
4289 (define_expand "truncdfsf2"
4290 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4292 (match_operand:DF 1 "register_operand" "")))
4293 (clobber (match_dup 2))])]
4294 "TARGET_80387 || TARGET_SSE2"
4297 operands[2] = assign_386_stack_local (SFmode, 0);
4300 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4305 (define_insn "*truncdfsf2_1"
4306 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4308 (match_operand:DF 1 "register_operand" "f,f,f,f")))
4309 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4310 "TARGET_80387 && !TARGET_SSE2"
4313 switch (which_alternative)
4316 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4317 return \"fstp%z0\\t%y0\";
4319 return \"fst%z0\\t%y0\";
4324 [(set_attr "type" "fmov,multi,multi,multi")
4325 (set_attr "mode" "SF,SF,SF,SF")])
4327 (define_insn "*truncdfsf2_1_sse"
4328 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
4330 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
4331 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
4332 "TARGET_80387 && TARGET_SSE2"
4335 switch (which_alternative)
4338 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4339 return \"fstp%z0\\t%y0\";
4341 return \"fst%z0\\t%y0\";
4343 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4348 [(set_attr "type" "fmov,multi,multi,multi,sse")
4349 (set_attr "mode" "SF,SF,SF,SF,DF")])
4351 (define_insn "*truncdfsf2_2"
4352 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4354 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4355 "TARGET_80387 && TARGET_SSE2
4356 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4359 switch (which_alternative)
4362 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4364 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4365 return \"fstp%z0\\t%y0\";
4367 return \"fst%z0\\t%y0\";
4370 [(set_attr "type" "sse,fmov")
4371 (set_attr "mode" "DF,SF")])
4373 (define_insn "truncdfsf2_3"
4374 [(set (match_operand:SF 0 "memory_operand" "=m")
4376 (match_operand:DF 1 "register_operand" "f")))]
4380 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4381 return \"fstp%z0\\t%y0\";
4383 return \"fst%z0\\t%y0\";
4385 [(set_attr "type" "fmov")
4386 (set_attr "mode" "SF")])
4388 (define_insn "truncdfsf2_sse_only"
4389 [(set (match_operand:SF 0 "register_operand" "=Y")
4391 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4392 "!TARGET_80387 && TARGET_SSE2"
4393 "cvtsd2ss\\t{%1, %0|%0, %1}"
4394 [(set_attr "type" "sse")
4395 (set_attr "mode" "DF")])
4398 [(set (match_operand:SF 0 "memory_operand" "")
4400 (match_operand:DF 1 "register_operand" "")))
4401 (clobber (match_operand:SF 2 "memory_operand" ""))]
4403 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4407 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4409 (match_operand:DF 1 "nonimmediate_operand" "")))
4410 (clobber (match_operand 2 "" ""))]
4411 "TARGET_80387 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4412 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4416 [(set (match_operand:SF 0 "register_operand" "")
4418 (match_operand:DF 1 "register_operand" "")))
4419 (clobber (match_operand:SF 2 "memory_operand" ""))]
4420 "TARGET_80387 && reload_completed
4421 && FP_REG_P (operands[1])"
4422 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4423 (set (match_dup 0) (match_dup 2))]
4426 (define_expand "truncxfsf2"
4427 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4429 (match_operand:XF 1 "register_operand" "")))
4430 (clobber (match_dup 2))])]
4431 "TARGET_80387 && !TARGET_64BIT"
4432 "operands[2] = assign_386_stack_local (SFmode, 0);")
4434 (define_insn "*truncxfsf2_1"
4435 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4437 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4438 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4439 "TARGET_80387 && !TARGET_64BIT"
4442 switch (which_alternative)
4445 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4446 return \"fstp%z0\\t%y0\";
4448 return \"fst%z0\\t%y0\";
4453 [(set_attr "type" "fmov,multi,multi,multi")
4454 (set_attr "mode" "SF")])
4456 (define_insn "*truncxfsf2_2"
4457 [(set (match_operand:SF 0 "memory_operand" "=m")
4459 (match_operand:XF 1 "register_operand" "f")))]
4460 "TARGET_80387 && !TARGET_64BIT"
4463 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4464 return \"fstp%z0\\t%y0\";
4466 return \"fst%z0\\t%y0\";
4468 [(set_attr "type" "fmov")
4469 (set_attr "mode" "SF")])
4472 [(set (match_operand:SF 0 "memory_operand" "")
4474 (match_operand:XF 1 "register_operand" "")))
4475 (clobber (match_operand:SF 2 "memory_operand" ""))]
4477 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4481 [(set (match_operand:SF 0 "register_operand" "")
4483 (match_operand:XF 1 "register_operand" "")))
4484 (clobber (match_operand:SF 2 "memory_operand" ""))]
4485 "TARGET_80387 && reload_completed"
4486 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4487 (set (match_dup 0) (match_dup 2))]
4490 (define_expand "trunctfsf2"
4491 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4493 (match_operand:TF 1 "register_operand" "")))
4494 (clobber (match_dup 2))])]
4496 "operands[2] = assign_386_stack_local (SFmode, 0);")
4498 (define_insn "*trunctfsf2_1"
4499 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4501 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4502 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4506 switch (which_alternative)
4509 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4510 return \"fstp%z0\\t%y0\";
4512 return \"fst%z0\\t%y0\";
4517 [(set_attr "type" "fmov,multi,multi,multi")
4518 (set_attr "mode" "SF")])
4520 (define_insn "*trunctfsf2_2"
4521 [(set (match_operand:SF 0 "memory_operand" "=m")
4523 (match_operand:TF 1 "register_operand" "f")))]
4527 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4528 return \"fstp%z0\\t%y0\";
4530 return \"fst%z0\\t%y0\";
4532 [(set_attr "type" "fmov")
4533 (set_attr "mode" "SF")])
4536 [(set (match_operand:SF 0 "memory_operand" "")
4538 (match_operand:TF 1 "register_operand" "")))
4539 (clobber (match_operand:SF 2 "memory_operand" ""))]
4541 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4545 [(set (match_operand:SF 0 "register_operand" "")
4547 (match_operand:TF 1 "register_operand" "")))
4548 (clobber (match_operand:SF 2 "memory_operand" ""))]
4549 "TARGET_80387 && reload_completed"
4550 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4551 (set (match_dup 0) (match_dup 2))]
4555 (define_expand "truncxfdf2"
4556 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4558 (match_operand:XF 1 "register_operand" "")))
4559 (clobber (match_dup 2))])]
4560 "TARGET_80387 && !TARGET_64BIT"
4561 "operands[2] = assign_386_stack_local (DFmode, 0);")
4563 (define_insn "*truncxfdf2_1"
4564 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4566 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4567 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4568 "TARGET_80387 && !TARGET_64BIT"
4571 switch (which_alternative)
4574 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4575 return \"fstp%z0\\t%y0\";
4577 return \"fst%z0\\t%y0\";
4583 [(set_attr "type" "fmov,multi,multi,multi")
4584 (set_attr "mode" "DF")])
4586 (define_insn "*truncxfdf2_2"
4587 [(set (match_operand:DF 0 "memory_operand" "=m")
4589 (match_operand:XF 1 "register_operand" "f")))]
4590 "TARGET_80387 && !TARGET_64BIT"
4593 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4594 return \"fstp%z0\\t%y0\";
4596 return \"fst%z0\\t%y0\";
4598 [(set_attr "type" "fmov")
4599 (set_attr "mode" "DF")])
4602 [(set (match_operand:DF 0 "memory_operand" "")
4604 (match_operand:XF 1 "register_operand" "")))
4605 (clobber (match_operand:DF 2 "memory_operand" ""))]
4607 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4611 [(set (match_operand:DF 0 "register_operand" "")
4613 (match_operand:XF 1 "register_operand" "")))
4614 (clobber (match_operand:DF 2 "memory_operand" ""))]
4615 "TARGET_80387 && reload_completed"
4616 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4617 (set (match_dup 0) (match_dup 2))]
4620 (define_expand "trunctfdf2"
4621 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4623 (match_operand:TF 1 "register_operand" "")))
4624 (clobber (match_dup 2))])]
4626 "operands[2] = assign_386_stack_local (DFmode, 0);")
4628 (define_insn "*trunctfdf2_1"
4629 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4631 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4632 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4636 switch (which_alternative)
4639 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4640 return \"fstp%z0\\t%y0\";
4642 return \"fst%z0\\t%y0\";
4648 [(set_attr "type" "fmov,multi,multi,multi")
4649 (set_attr "mode" "DF")])
4651 (define_insn "*trunctfdf2_2"
4652 [(set (match_operand:DF 0 "memory_operand" "=m")
4654 (match_operand:TF 1 "register_operand" "f")))]
4658 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4659 return \"fstp%z0\\t%y0\";
4661 return \"fst%z0\\t%y0\";
4663 [(set_attr "type" "fmov")
4664 (set_attr "mode" "DF")])
4667 [(set (match_operand:DF 0 "memory_operand" "")
4669 (match_operand:TF 1 "register_operand" "")))
4670 (clobber (match_operand:DF 2 "memory_operand" ""))]
4672 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4676 [(set (match_operand:DF 0 "register_operand" "")
4678 (match_operand:TF 1 "register_operand" "")))
4679 (clobber (match_operand:DF 2 "memory_operand" ""))]
4680 "TARGET_80387 && reload_completed"
4681 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4682 (set (match_dup 0) (match_dup 2))]
4686 ;; %%% Break up all these bad boys.
4688 ;; Signed conversion to DImode.
4690 (define_expand "fix_truncxfdi2"
4691 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4692 (fix:DI (match_operand:XF 1 "register_operand" "")))
4693 (clobber (match_dup 2))
4694 (clobber (match_dup 3))
4695 (clobber (match_scratch:SI 4 ""))
4696 (clobber (match_scratch:XF 5 ""))])]
4697 "TARGET_80387 && !TARGET_64BIT"
4698 "operands[2] = assign_386_stack_local (SImode, 0);
4699 operands[3] = assign_386_stack_local (DImode, 1);")
4701 (define_expand "fix_trunctfdi2"
4702 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4703 (fix:DI (match_operand:TF 1 "register_operand" "")))
4704 (clobber (match_dup 2))
4705 (clobber (match_dup 3))
4706 (clobber (match_scratch:SI 4 ""))
4707 (clobber (match_scratch:TF 5 ""))])]
4709 "operands[2] = assign_386_stack_local (SImode, 0);
4710 operands[3] = assign_386_stack_local (DImode, 1);")
4712 (define_expand "fix_truncdfdi2"
4713 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4714 (fix:DI (match_operand:DF 1 "register_operand" "")))
4715 (clobber (match_dup 2))
4716 (clobber (match_dup 3))
4717 (clobber (match_scratch:SI 4 ""))
4718 (clobber (match_scratch:DF 5 ""))])]
4719 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4724 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4725 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4726 if (out != operands[0])
4727 emit_move_insn (operands[0], out);
4732 operands[2] = assign_386_stack_local (SImode, 0);
4733 operands[3] = assign_386_stack_local (DImode, 1);
4737 (define_expand "fix_truncsfdi2"
4738 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4739 (fix:DI (match_operand:SF 1 "register_operand" "")))
4740 (clobber (match_dup 2))
4741 (clobber (match_dup 3))
4742 (clobber (match_scratch:SI 4 ""))
4743 (clobber (match_scratch:SF 5 ""))])]
4744 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4749 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4750 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4751 if (out != operands[0])
4752 emit_move_insn (operands[0], out);
4757 operands[2] = assign_386_stack_local (SImode, 0);
4758 operands[3] = assign_386_stack_local (DImode, 1);
4762 (define_insn "*fix_truncdi_1"
4763 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4764 (fix:DI (match_operand 1 "register_operand" "f,f")))
4765 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4766 (clobber (match_operand:DI 3 "memory_operand" "=m,m"))
4767 (clobber (match_scratch:SI 4 "=&r,&r"))
4768 (clobber (match_scratch 5 "=&f,&f"))]
4769 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4770 && (!TARGET_SSE2 || !TARGET_64BIT
4771 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4772 "* return output_fix_trunc (insn, operands);"
4773 [(set_attr "type" "multi")])
4776 [(set (match_operand:DI 0 "register_operand" "")
4777 (fix:DI (match_operand 1 "register_operand" "")))
4778 (clobber (match_operand:SI 2 "memory_operand" ""))
4779 (clobber (match_operand:DI 3 "memory_operand" ""))
4780 (clobber (match_scratch:SI 4 ""))
4781 (clobber (match_scratch 5 ""))]
4782 "reload_completed && !reg_overlap_mentioned_p (operands[4], operands[3])"
4783 [(parallel [(set (match_dup 3) (fix:DI (match_dup 1)))
4784 (clobber (match_dup 2))
4785 (clobber (match_dup 3))
4786 (clobber (match_dup 4))
4787 (clobber (match_dup 5))])
4788 (set (match_dup 0) (match_dup 3))]
4791 ;; When SSE available, it is always faster to use it!
4792 (define_insn "fix_truncsfdi_sse"
4793 [(set (match_operand:DI 0 "register_operand" "=r")
4794 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4795 "TARGET_SSE && TARGET_64BIT"
4796 "cvttss2si{q}\\t{%1, %0|%0, %1}"
4797 [(set_attr "type" "sse")])
4799 (define_insn "fix_truncdfdi_sse"
4800 [(set (match_operand:DI 0 "register_operand" "=r")
4801 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4802 "TARGET_SSE2 && TARGET_64BIT"
4803 "cvttsd2si{q}\\t{%1, %0|%0, %1}"
4804 [(set_attr "type" "sse")])
4806 ;; Signed conversion to SImode.
4808 (define_expand "fix_truncxfsi2"
4809 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4810 (fix:SI (match_operand:XF 1 "register_operand" "")))
4811 (clobber (match_dup 2))
4812 (clobber (match_dup 3))
4813 (clobber (match_scratch:SI 4 ""))])]
4814 "TARGET_80387 && !TARGET_64BIT"
4815 "operands[2] = assign_386_stack_local (SImode, 0);
4816 operands[3] = assign_386_stack_local (SImode, 1);")
4818 (define_expand "fix_trunctfsi2"
4819 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4820 (fix:SI (match_operand:TF 1 "register_operand" "")))
4821 (clobber (match_dup 2))
4822 (clobber (match_dup 3))
4823 (clobber (match_scratch:SI 4 ""))])]
4825 "operands[2] = assign_386_stack_local (SImode, 0);
4826 operands[3] = assign_386_stack_local (SImode, 1);")
4828 (define_expand "fix_truncdfsi2"
4829 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4830 (fix:SI (match_operand:DF 1 "register_operand" "")))
4831 (clobber (match_dup 2))
4832 (clobber (match_dup 3))
4833 (clobber (match_scratch:SI 4 ""))])]
4834 "TARGET_80387 || TARGET_SSE2"
4839 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4840 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4841 if (out != operands[0])
4842 emit_move_insn (operands[0], out);
4847 operands[2] = assign_386_stack_local (SImode, 0);
4848 operands[3] = assign_386_stack_local (SImode, 1);
4852 (define_expand "fix_truncsfsi2"
4853 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4854 (fix:SI (match_operand:SF 1 "register_operand" "")))
4855 (clobber (match_dup 2))
4856 (clobber (match_dup 3))
4857 (clobber (match_scratch:SI 4 ""))])]
4858 "TARGET_80387 || TARGET_SSE"
4863 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4864 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4865 if (out != operands[0])
4866 emit_move_insn (operands[0], out);
4871 operands[2] = assign_386_stack_local (SImode, 0);
4872 operands[3] = assign_386_stack_local (SImode, 1);
4876 (define_insn "*fix_truncsi_1"
4877 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4878 (fix:SI (match_operand 1 "register_operand" "f,f")))
4879 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4880 (clobber (match_operand:SI 3 "memory_operand" "=m,m"))
4881 (clobber (match_scratch:SI 4 "=&r,r"))]
4882 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4883 && (!TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4884 "* return output_fix_trunc (insn, operands);"
4885 [(set_attr "type" "multi")])
4887 ;; When SSE available, it is always faster to use it!
4888 (define_insn "fix_truncsfsi_sse"
4889 [(set (match_operand:SI 0 "register_operand" "=r")
4890 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4892 "cvttss2si\\t{%1, %0|%0, %1}"
4893 [(set_attr "type" "sse")])
4895 (define_insn "fix_truncdfsi_sse"
4896 [(set (match_operand:SI 0 "register_operand" "=r")
4897 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4899 "cvttsd2si\\t{%1, %0|%0, %1}"
4900 [(set_attr "type" "sse")])
4903 [(set (match_operand:SI 0 "register_operand" "")
4904 (fix:SI (match_operand 1 "register_operand" "")))
4905 (clobber (match_operand:SI 2 "memory_operand" ""))
4906 (clobber (match_operand:SI 3 "memory_operand" ""))
4907 (clobber (match_scratch:SI 4 ""))]
4909 [(parallel [(set (match_dup 3) (fix:SI (match_dup 1)))
4910 (clobber (match_dup 2))
4911 (clobber (match_dup 3))
4912 (clobber (match_dup 4))])
4913 (set (match_dup 0) (match_dup 3))]
4916 ;; Signed conversion to HImode.
4918 (define_expand "fix_truncxfhi2"
4919 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4920 (fix:HI (match_operand:XF 1 "register_operand" "")))
4921 (clobber (match_dup 2))
4922 (clobber (match_dup 3))
4923 (clobber (match_scratch:SI 4 ""))])]
4924 "TARGET_80387 && !TARGET_64BIT"
4925 "operands[2] = assign_386_stack_local (SImode, 0);
4926 operands[3] = assign_386_stack_local (HImode, 1);")
4928 (define_expand "fix_trunctfhi2"
4929 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4930 (fix:HI (match_operand:TF 1 "register_operand" "")))
4931 (clobber (match_dup 2))
4932 (clobber (match_dup 3))
4933 (clobber (match_scratch:SI 4 ""))])]
4935 "operands[2] = assign_386_stack_local (SImode, 0);
4936 operands[3] = assign_386_stack_local (HImode, 1);")
4938 (define_expand "fix_truncdfhi2"
4939 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4940 (fix:HI (match_operand:DF 1 "register_operand" "")))
4941 (clobber (match_dup 2))
4942 (clobber (match_dup 3))
4943 (clobber (match_scratch:SI 4 ""))])]
4944 "TARGET_80387 && !TARGET_SSE2"
4945 "operands[2] = assign_386_stack_local (SImode, 0);
4946 operands[3] = assign_386_stack_local (HImode, 1);")
4948 (define_expand "fix_truncsfhi2"
4949 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4950 (fix:HI (match_operand:SF 1 "register_operand" "")))
4951 (clobber (match_dup 2))
4952 (clobber (match_dup 3))
4953 (clobber (match_scratch:SI 4 ""))])]
4954 "TARGET_80387 && !TARGET_SSE"
4955 "operands[2] = assign_386_stack_local (SImode, 0);
4956 operands[3] = assign_386_stack_local (HImode, 1);")
4958 (define_insn "*fix_trunchi_1"
4959 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4960 (fix:HI (match_operand 1 "register_operand" "f,f")))
4961 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4962 (clobber (match_operand:HI 3 "memory_operand" "=m,m"))
4963 (clobber (match_scratch:SI 4 "=&r,r"))]
4964 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4965 && (TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4966 "* return output_fix_trunc (insn, operands);"
4967 [(set_attr "type" "multi")])
4970 [(set (match_operand:HI 0 "register_operand" "")
4971 (fix:HI (match_operand 1 "register_operand" "")))
4972 (clobber (match_operand:SI 2 "memory_operand" ""))
4973 (clobber (match_operand:HI 3 "memory_operand" ""))
4974 (clobber (match_scratch:SI 4 ""))]
4976 [(parallel [(set (match_dup 3) (fix:HI (match_dup 1)))
4977 (clobber (match_dup 2))
4978 (clobber (match_dup 3))
4979 (clobber (match_dup 4))])
4980 (set (match_dup 0) (match_dup 3))]
4983 ;; %%% Kill these when reload knows how to do it.
4985 [(set (match_operand 0 "register_operand" "")
4986 (fix (match_operand 1 "register_operand" "")))]
4987 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[1]))
4988 && FP_REG_P (operands[1])"
4992 operands[2] = ix86_force_to_memory (GET_MODE (operands[0]), operands[0]);
4993 operands[2] = gen_rtx_FIX (GET_MODE (operands[2]), operands[1]);
4994 emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
4995 emit_move_insn (operands[0], operands[2]);
4996 ix86_free_from_memory (GET_MODE (operands[0]));
5001 (define_insn "x86_fnstcw_1"
5002 [(set (match_operand:HI 0 "memory_operand" "=m")
5003 (unspec:HI [(reg:HI 18)] 11))]
5006 [(set_attr "length" "2")
5007 (set_attr "mode" "HI")
5008 (set_attr "i387" "1")
5009 (set_attr "ppro_uops" "few")])
5011 (define_insn "x86_fldcw_1"
5013 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
5016 [(set_attr "length" "2")
5017 (set_attr "mode" "HI")
5018 (set_attr "i387" "1")
5019 (set_attr "athlon_decode" "vector")
5020 (set_attr "ppro_uops" "few")])
5022 ;; Conversion between fixed point and floating point.
5024 ;; Even though we only accept memory inputs, the backend _really_
5025 ;; wants to be able to do this between registers.
5027 (define_insn "floathisf2"
5028 [(set (match_operand:SF 0 "register_operand" "=f,f")
5029 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5030 "TARGET_80387 && !TARGET_SSE"
5034 [(set_attr "type" "fmov,multi")
5035 (set_attr "mode" "SF")
5036 (set_attr "fp_int_src" "true")])
5038 (define_expand "floatsisf2"
5039 [(set (match_operand:SF 0 "register_operand" "")
5040 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5041 "TARGET_SSE || TARGET_80387"
5044 (define_insn "*floatsisf2_i387"
5045 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5046 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5047 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5051 cvtsi2ss\\t{%1, %0|%0, %1}"
5052 [(set_attr "type" "fmov,multi,sse")
5053 (set_attr "mode" "SF")
5054 (set_attr "fp_int_src" "true")])
5056 (define_insn "*floatsisf2_sse"
5057 [(set (match_operand:SF 0 "register_operand" "=x")
5058 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5060 "cvtsi2ss\\t{%1, %0|%0, %1}"
5061 [(set_attr "type" "sse")
5062 (set_attr "mode" "SF")
5063 (set_attr "fp_int_src" "true")])
5065 (define_expand "floatdisf2"
5066 [(set (match_operand:SF 0 "register_operand" "")
5067 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
5068 "(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
5071 (define_insn "*floatdisf2_i387"
5072 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5073 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5074 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5078 cvtsi2ss{q}\\t{%1, %0|%0, %1}"
5079 [(set_attr "type" "fmov,multi,sse")
5080 (set_attr "mode" "SF")
5081 (set_attr "fp_int_src" "true")])
5083 (define_insn "*floatdisf2_sse"
5084 [(set (match_operand:SF 0 "register_operand" "=x")
5085 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5086 "TARGET_SSE && TARGET_64BIT"
5087 "cvtsi2ss{q}\\t{%1, %0|%0, %1}"
5088 [(set_attr "type" "sse")
5089 (set_attr "mode" "SF")
5090 (set_attr "fp_int_src" "true")])
5092 (define_insn "floathidf2"
5093 [(set (match_operand:DF 0 "register_operand" "=f,f")
5094 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5095 "TARGET_80387 && !TARGET_SSE2"
5099 [(set_attr "type" "fmov,multi")
5100 (set_attr "mode" "DF")
5101 (set_attr "fp_int_src" "true")])
5103 (define_expand "floatsidf2"
5104 [(set (match_operand:DF 0 "register_operand" "")
5105 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5109 (define_insn "*floatsidf2_i387"
5110 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5111 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5112 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5116 cvtsi2sd\\t{%1, %0|%0, %1}"
5117 [(set_attr "type" "fmov,multi,sse")
5118 (set_attr "mode" "DF")
5119 (set_attr "fp_int_src" "true")])
5121 (define_insn "*floatsidf2_sse"
5122 [(set (match_operand:DF 0 "register_operand" "=Y")
5123 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5125 "cvtsi2sd\\t{%1, %0|%0, %1}"
5126 [(set_attr "type" "sse")
5127 (set_attr "mode" "DF")
5128 (set_attr "fp_int_src" "true")])
5130 (define_expand "floatdidf2"
5131 [(set (match_operand:DF 0 "register_operand" "")
5132 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5133 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
5136 (define_insn "*floatdidf2_i387"
5137 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5138 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5139 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5143 cvtsi2sd{q}\\t{%1, %0|%0, %1}"
5144 [(set_attr "type" "fmov,multi,sse")
5145 (set_attr "mode" "DF")
5146 (set_attr "fp_int_src" "true")])
5148 (define_insn "*floatdidf2_sse"
5149 [(set (match_operand:DF 0 "register_operand" "=Y")
5150 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5152 "cvtsi2sd{q}\\t{%1, %0|%0, %1}"
5153 [(set_attr "type" "sse")
5154 (set_attr "mode" "DF")
5155 (set_attr "fp_int_src" "true")])
5157 (define_insn "floathixf2"
5158 [(set (match_operand:XF 0 "register_operand" "=f,f")
5159 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5160 "TARGET_80387 && !TARGET_64BIT"
5164 [(set_attr "type" "fmov,multi")
5165 (set_attr "mode" "XF")
5166 (set_attr "fp_int_src" "true")])
5168 (define_insn "floathitf2"
5169 [(set (match_operand:TF 0 "register_operand" "=f,f")
5170 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5175 [(set_attr "type" "fmov,multi")
5176 (set_attr "mode" "XF")
5177 (set_attr "fp_int_src" "true")])
5179 (define_insn "floatsixf2"
5180 [(set (match_operand:XF 0 "register_operand" "=f,f")
5181 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5182 "TARGET_80387 && !TARGET_64BIT"
5186 [(set_attr "type" "fmov,multi")
5187 (set_attr "mode" "XF")
5188 (set_attr "fp_int_src" "true")])
5190 (define_insn "floatsitf2"
5191 [(set (match_operand:TF 0 "register_operand" "=f,f")
5192 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5197 [(set_attr "type" "fmov,multi")
5198 (set_attr "mode" "XF")
5199 (set_attr "fp_int_src" "true")])
5201 (define_insn "floatdixf2"
5202 [(set (match_operand:XF 0 "register_operand" "=f,f")
5203 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5204 "TARGET_80387 && !TARGET_64BIT"
5208 [(set_attr "type" "fmov,multi")
5209 (set_attr "mode" "XF")
5210 (set_attr "fp_int_src" "true")])
5212 (define_insn "floatditf2"
5213 [(set (match_operand:TF 0 "register_operand" "=f,f")
5214 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5219 [(set_attr "type" "fmov,multi")
5220 (set_attr "mode" "XF")
5221 (set_attr "fp_int_src" "true")])
5223 ;; %%% Kill these when reload knows how to do it.
5225 [(set (match_operand 0 "register_operand" "")
5226 (float (match_operand 1 "register_operand" "")))]
5227 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5228 && FP_REG_P (operands[0])"
5232 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5233 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5234 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5235 ix86_free_from_memory (GET_MODE (operands[1]));
5241 ;; %%% splits for addsidi3
5242 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5243 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5244 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5246 (define_expand "adddi3"
5247 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5248 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5249 (match_operand:DI 2 "x86_64_general_operand" "")))
5250 (clobber (reg:CC 17))]
5252 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5254 (define_insn "*adddi3_1"
5255 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5256 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5257 (match_operand:DI 2 "general_operand" "roiF,riF")))
5258 (clobber (reg:CC 17))]
5263 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5264 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5265 (match_operand:DI 2 "general_operand" "")))
5266 (clobber (reg:CC 17))]
5267 "reload_completed && !TARGET_64BIT"
5268 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5269 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5270 (parallel [(set (match_dup 3)
5271 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5274 (clobber (reg:CC 17))])]
5275 "split_di (operands+0, 1, operands+0, operands+3);
5276 split_di (operands+1, 1, operands+1, operands+4);
5277 split_di (operands+2, 1, operands+2, operands+5);")
5279 (define_insn "*adddi3_carry_rex64"
5280 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5281 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
5282 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5283 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5284 (clobber (reg:CC 17))]
5285 "ix86_binary_operator_ok (PLUS, DImode, operands)"
5286 "adc{q}\\t{%2, %0|%0, %2}"
5287 [(set_attr "type" "alu")
5288 (set_attr "pent_pair" "pu")
5289 (set_attr "mode" "DI")
5290 (set_attr "ppro_uops" "few")])
5292 (define_insn "*adddi3_cc_rex64"
5293 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5294 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
5295 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5296 (plus:DI (match_dup 1) (match_dup 2)))]
5297 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5298 "add{q}\\t{%2, %0|%0, %2}"
5299 [(set_attr "type" "alu")
5300 (set_attr "mode" "DI")])
5302 (define_insn "*addsi3_carry"
5303 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5304 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5305 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5306 (match_operand:SI 2 "general_operand" "ri,rm")))
5307 (clobber (reg:CC 17))]
5308 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5309 "adc{l}\\t{%2, %0|%0, %2}"
5310 [(set_attr "type" "alu")
5311 (set_attr "pent_pair" "pu")
5312 (set_attr "mode" "SI")
5313 (set_attr "ppro_uops" "few")])
5315 (define_insn "*addsi3_carry_zext"
5316 [(set (match_operand:DI 0 "register_operand" "=r")
5318 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5319 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5320 (match_operand:SI 2 "general_operand" "rim"))))
5321 (clobber (reg:CC 17))]
5322 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5323 "adc{l}\\t{%2, %k0|%k0, %2}"
5324 [(set_attr "type" "alu")
5325 (set_attr "pent_pair" "pu")
5326 (set_attr "mode" "SI")
5327 (set_attr "ppro_uops" "few")])
5329 (define_insn "*addsi3_cc"
5330 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5331 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5332 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5333 (plus:SI (match_dup 1) (match_dup 2)))]
5334 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5335 "add{l}\\t{%2, %0|%0, %2}"
5336 [(set_attr "type" "alu")
5337 (set_attr "mode" "SI")])
5339 (define_insn "addqi3_cc"
5340 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5341 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5342 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5343 (plus:QI (match_dup 1) (match_dup 2)))]
5344 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5345 "add{b}\\t{%2, %0|%0, %2}"
5346 [(set_attr "type" "alu")
5347 (set_attr "mode" "QI")])
5349 (define_expand "addsi3"
5350 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5351 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5352 (match_operand:SI 2 "general_operand" "")))
5353 (clobber (reg:CC 17))])]
5355 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5357 (define_insn "*lea_1"
5358 [(set (match_operand:SI 0 "register_operand" "=r")
5359 (match_operand:SI 1 "address_operand" "p"))]
5361 "lea{l}\\t{%a1, %0|%0, %a1}"
5362 [(set_attr "type" "lea")
5363 (set_attr "mode" "SI")])
5365 (define_insn "*lea_1_rex64"
5366 [(set (match_operand:SI 0 "register_operand" "=r")
5367 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5369 "lea{l}\\t{%a1, %0|%0, %a1}"
5370 [(set_attr "type" "lea")
5371 (set_attr "mode" "SI")])
5373 (define_insn "*lea_1_zext"
5374 [(set (match_operand:DI 0 "register_operand" "=r")
5375 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5377 "lea{l}\\t{%a1, %k0|%k0, %a1}"
5378 [(set_attr "type" "lea")
5379 (set_attr "mode" "SI")])
5381 (define_insn "*lea_2_rex64"
5382 [(set (match_operand:DI 0 "register_operand" "=r")
5383 (match_operand:DI 1 "address_operand" "p"))]
5385 "lea{q}\\t{%a1, %0|%0, %a1}"
5386 [(set_attr "type" "lea")
5387 (set_attr "mode" "DI")])
5389 ;; The lea patterns for non-Pmodes needs to be matched by several
5390 ;; insns converted to real lea by splitters.
5392 (define_insn_and_split "*lea_general_1"
5393 [(set (match_operand 0 "register_operand" "=r")
5394 (plus (plus (match_operand 1 "register_operand" "r")
5395 (match_operand 2 "register_operand" "r"))
5396 (match_operand 3 "immediate_operand" "i")))]
5397 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5398 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5399 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5400 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5401 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5402 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5403 || GET_MODE (operands[3]) == VOIDmode)"
5405 "&& reload_completed"
5410 operands[0] = gen_lowpart (SImode, operands[0]);
5411 operands[1] = gen_lowpart (Pmode, operands[1]);
5412 operands[2] = gen_lowpart (Pmode, operands[2]);
5413 operands[3] = gen_lowpart (Pmode, operands[3]);
5414 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5416 if (Pmode != SImode)
5417 pat = gen_rtx_SUBREG (SImode, pat, 0);
5418 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5421 [(set_attr "type" "lea")
5422 (set_attr "mode" "SI")])
5424 (define_insn_and_split "*lea_general_1_zext"
5425 [(set (match_operand:DI 0 "register_operand" "=r")
5427 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
5428 (match_operand:SI 2 "register_operand" "r"))
5429 (match_operand:SI 3 "immediate_operand" "i"))))]
5432 "&& reload_completed"
5434 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5436 (match_dup 3)) 0)))]
5439 operands[1] = gen_lowpart (Pmode, operands[1]);
5440 operands[2] = gen_lowpart (Pmode, operands[2]);
5441 operands[3] = gen_lowpart (Pmode, operands[3]);
5443 [(set_attr "type" "lea")
5444 (set_attr "mode" "SI")])
5446 (define_insn_and_split "*lea_general_2"
5447 [(set (match_operand 0 "register_operand" "=r")
5448 (plus (mult (match_operand 1 "register_operand" "r")
5449 (match_operand 2 "const248_operand" "i"))
5450 (match_operand 3 "nonmemory_operand" "ri")))]
5451 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5452 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5453 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5454 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5455 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5456 || GET_MODE (operands[3]) == VOIDmode)"
5458 "&& reload_completed"
5463 operands[0] = gen_lowpart (SImode, operands[0]);
5464 operands[1] = gen_lowpart (Pmode, operands[1]);
5465 operands[3] = gen_lowpart (Pmode, operands[3]);
5466 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5468 if (Pmode != SImode)
5469 pat = gen_rtx_SUBREG (SImode, pat, 0);
5470 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5473 [(set_attr "type" "lea")
5474 (set_attr "mode" "SI")])
5476 (define_insn_and_split "*lea_general_2_zext"
5477 [(set (match_operand:DI 0 "register_operand" "=r")
5479 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5480 (match_operand:SI 2 "const248_operand" "n"))
5481 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5484 "&& reload_completed"
5486 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5488 (match_dup 3)) 0)))]
5491 operands[1] = gen_lowpart (Pmode, operands[1]);
5492 operands[3] = gen_lowpart (Pmode, operands[3]);
5494 [(set_attr "type" "lea")
5495 (set_attr "mode" "SI")])
5497 (define_insn_and_split "*lea_general_3"
5498 [(set (match_operand 0 "register_operand" "=r")
5499 (plus (plus (mult (match_operand 1 "register_operand" "r")
5500 (match_operand 2 "const248_operand" "i"))
5501 (match_operand 3 "register_operand" "r"))
5502 (match_operand 4 "immediate_operand" "i")))]
5503 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5504 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5505 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5506 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5507 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5509 "&& reload_completed"
5514 operands[0] = gen_lowpart (SImode, operands[0]);
5515 operands[1] = gen_lowpart (Pmode, operands[1]);
5516 operands[3] = gen_lowpart (Pmode, operands[3]);
5517 operands[4] = gen_lowpart (Pmode, operands[4]);
5518 pat = gen_rtx_PLUS (Pmode,
5519 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5523 if (Pmode != SImode)
5524 pat = gen_rtx_SUBREG (SImode, pat, 0);
5525 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5528 [(set_attr "type" "lea")
5529 (set_attr "mode" "SI")])
5531 (define_insn_and_split "*lea_general_3_zext"
5532 [(set (match_operand:DI 0 "register_operand" "=r")
5534 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5535 (match_operand:SI 2 "const248_operand" "n"))
5536 (match_operand:SI 3 "register_operand" "r"))
5537 (match_operand:SI 4 "immediate_operand" "i"))))]
5540 "&& reload_completed"
5542 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5545 (match_dup 4)) 0)))]
5548 operands[1] = gen_lowpart (Pmode, operands[1]);
5549 operands[3] = gen_lowpart (Pmode, operands[3]);
5550 operands[4] = gen_lowpart (Pmode, operands[4]);
5552 [(set_attr "type" "lea")
5553 (set_attr "mode" "SI")])
5555 (define_insn "*adddi_1_rex64"
5556 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5557 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5558 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5559 (clobber (reg:CC 17))]
5560 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5563 switch (get_attr_type (insn))
5566 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5567 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
5570 if (! rtx_equal_p (operands[0], operands[1]))
5572 if (operands[2] == const1_rtx)
5573 return \"inc{q}\\t%0\";
5574 else if (operands[2] == constm1_rtx)
5575 return \"dec{q}\\t%0\";
5580 if (! rtx_equal_p (operands[0], operands[1]))
5583 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5584 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5585 if (GET_CODE (operands[2]) == CONST_INT
5586 && (INTVAL (operands[2]) == 128
5587 || (INTVAL (operands[2]) < 0
5588 && INTVAL (operands[2]) != -128)))
5590 operands[2] = GEN_INT (-INTVAL (operands[2]));
5591 return \"sub{q}\\t{%2, %0|%0, %2}\";
5593 return \"add{q}\\t{%2, %0|%0, %2}\";
5597 (cond [(eq_attr "alternative" "2")
5598 (const_string "lea")
5599 ; Current assemblers are broken and do not allow @GOTOFF in
5600 ; ought but a memory context.
5601 (match_operand:DI 2 "pic_symbolic_operand" "")
5602 (const_string "lea")
5603 (match_operand:DI 2 "incdec_operand" "")
5604 (const_string "incdec")
5606 (const_string "alu")))
5607 (set_attr "mode" "DI")])
5609 ;; Convert lea to the lea pattern to avoid flags dependency.
5611 [(set (match_operand:DI 0 "register_operand" "")
5612 (plus:DI (match_operand:DI 1 "register_operand" "")
5613 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5614 (clobber (reg:CC 17))]
5615 "reload_completed && TARGET_64BIT
5616 && true_regnum (operands[0]) != true_regnum (operands[1])"
5618 (plus:DI (match_dup 1)
5622 (define_insn "*adddi_2_rex64"
5625 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5626 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5628 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5629 (plus:DI (match_dup 1) (match_dup 2)))]
5630 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5631 && ix86_binary_operator_ok (PLUS, DImode, operands)
5632 /* Current assemblers are broken and do not allow @GOTOFF in
5633 ought but a memory context. */
5634 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5637 switch (get_attr_type (insn))
5640 if (! rtx_equal_p (operands[0], operands[1]))
5642 if (operands[2] == const1_rtx)
5643 return \"inc{q}\\t%0\";
5644 else if (operands[2] == constm1_rtx)
5645 return \"dec{q}\\t%0\";
5650 if (! rtx_equal_p (operands[0], operands[1]))
5652 /* ???? We ought to handle there the 32bit case too
5653 - do we need new constrant? */
5654 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5655 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5656 if (GET_CODE (operands[2]) == CONST_INT
5657 && (INTVAL (operands[2]) == 128
5658 || (INTVAL (operands[2]) < 0
5659 && INTVAL (operands[2]) != -128)))
5661 operands[2] = GEN_INT (-INTVAL (operands[2]));
5662 return \"sub{q}\\t{%2, %0|%0, %2}\";
5664 return \"add{q}\\t{%2, %0|%0, %2}\";
5668 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5669 (const_string "incdec")
5670 (const_string "alu")))
5671 (set_attr "mode" "DI")])
5673 (define_insn "*adddi_3_rex64"
5675 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5676 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5677 (clobber (match_scratch:DI 0 "=r"))]
5679 && ix86_match_ccmode (insn, CCZmode)
5680 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5681 /* Current assemblers are broken and do not allow @GOTOFF in
5682 ought but a memory context. */
5683 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5686 switch (get_attr_type (insn))
5689 if (! rtx_equal_p (operands[0], operands[1]))
5691 if (operands[2] == const1_rtx)
5692 return \"inc{q}\\t%0\";
5693 else if (operands[2] == constm1_rtx)
5694 return \"dec{q}\\t%0\";
5699 if (! rtx_equal_p (operands[0], operands[1]))
5701 /* ???? We ought to handle there the 32bit case too
5702 - do we need new constrant? */
5703 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5704 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5705 if (GET_CODE (operands[2]) == CONST_INT
5706 && (INTVAL (operands[2]) == 128
5707 || (INTVAL (operands[2]) < 0
5708 && INTVAL (operands[2]) != -128)))
5710 operands[2] = GEN_INT (-INTVAL (operands[2]));
5711 return \"sub{q}\\t{%2, %0|%0, %2}\";
5713 return \"add{q}\\t{%2, %0|%0, %2}\";
5717 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5718 (const_string "incdec")
5719 (const_string "alu")))
5720 (set_attr "mode" "DI")])
5722 ; For comparisons against 1, -1 and 128, we may generate better code
5723 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5724 ; is matched then. We can't accept general immediate, because for
5725 ; case of overflows, the result is messed up.
5726 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5728 ; Also carry flag is reversed compared to cmp, so this converison is valid
5729 ; only for comparisons not depending on it.
5730 (define_insn "*adddi_4_rex64"
5732 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5733 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5734 (clobber (match_scratch:DI 0 "=rm"))]
5736 && ix86_match_ccmode (insn, CCGCmode)"
5739 switch (get_attr_type (insn))
5742 if (operands[2] == constm1_rtx)
5743 return \"inc{q}\\t%0\";
5744 else if (operands[2] == const1_rtx)
5745 return \"dec{q}\\t%0\";
5750 if (! rtx_equal_p (operands[0], operands[1]))
5752 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5753 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5754 if ((INTVAL (operands[2]) == -128
5755 || (INTVAL (operands[2]) > 0
5756 && INTVAL (operands[2]) != 128)))
5757 return \"sub{q}\\t{%2, %0|%0, %2}\";
5758 operands[2] = GEN_INT (-INTVAL (operands[2]));
5759 return \"add{q}\\t{%2, %0|%0, %2}\";
5763 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5764 (const_string "incdec")
5765 (const_string "alu")))
5766 (set_attr "mode" "DI")])
5768 (define_insn "*adddi_5_rex64"
5771 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5772 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5774 (clobber (match_scratch:DI 0 "=r"))]
5776 && ix86_match_ccmode (insn, CCGOCmode)
5777 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5778 /* Current assemblers are broken and do not allow @GOTOFF in
5779 ought but a memory context. */
5780 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5783 switch (get_attr_type (insn))
5786 if (! rtx_equal_p (operands[0], operands[1]))
5788 if (operands[2] == const1_rtx)
5789 return \"inc{q}\\t%0\";
5790 else if (operands[2] == constm1_rtx)
5791 return \"dec{q}\\t%0\";
5796 if (! rtx_equal_p (operands[0], operands[1]))
5798 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5799 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5800 if (GET_CODE (operands[2]) == CONST_INT
5801 && (INTVAL (operands[2]) == 128
5802 || (INTVAL (operands[2]) < 0
5803 && INTVAL (operands[2]) != -128)))
5805 operands[2] = GEN_INT (-INTVAL (operands[2]));
5806 return \"sub{q}\\t{%2, %0|%0, %2}\";
5808 return \"add{q}\\t{%2, %0|%0, %2}\";
5812 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5813 (const_string "incdec")
5814 (const_string "alu")))
5815 (set_attr "mode" "DI")])
5818 (define_insn "*addsi_1"
5819 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5820 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5821 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5822 (clobber (reg:CC 17))]
5823 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5826 switch (get_attr_type (insn))
5829 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5830 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
5833 if (! rtx_equal_p (operands[0], operands[1]))
5835 if (operands[2] == const1_rtx)
5836 return \"inc{l}\\t%0\";
5837 else if (operands[2] == constm1_rtx)
5838 return \"dec{l}\\t%0\";
5843 if (! rtx_equal_p (operands[0], operands[1]))
5846 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5847 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5848 if (GET_CODE (operands[2]) == CONST_INT
5849 && (INTVAL (operands[2]) == 128
5850 || (INTVAL (operands[2]) < 0
5851 && INTVAL (operands[2]) != -128)))
5853 operands[2] = GEN_INT (-INTVAL (operands[2]));
5854 return \"sub{l}\\t{%2, %0|%0, %2}\";
5856 return \"add{l}\\t{%2, %0|%0, %2}\";
5860 (cond [(eq_attr "alternative" "2")
5861 (const_string "lea")
5862 ; Current assemblers are broken and do not allow @GOTOFF in
5863 ; ought but a memory context.
5864 (match_operand:SI 2 "pic_symbolic_operand" "")
5865 (const_string "lea")
5866 (match_operand:SI 2 "incdec_operand" "")
5867 (const_string "incdec")
5869 (const_string "alu")))
5870 (set_attr "mode" "SI")])
5872 ;; Convert lea to the lea pattern to avoid flags dependency.
5874 [(set (match_operand 0 "register_operand" "")
5875 (plus (match_operand 1 "register_operand" "")
5876 (match_operand 2 "nonmemory_operand" "")))
5877 (clobber (reg:CC 17))]
5879 && true_regnum (operands[0]) != true_regnum (operands[1])"
5884 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5885 may confuse gen_lowpart. */
5886 if (GET_MODE (operands[0]) != Pmode)
5888 operands[1] = gen_lowpart (Pmode, operands[1]);
5889 operands[2] = gen_lowpart (Pmode, operands[2]);
5891 operands[0] = gen_lowpart (SImode, operands[0]);
5892 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5893 if (Pmode != SImode)
5894 pat = gen_rtx_SUBREG (SImode, pat, 0);
5895 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5899 ;; It may seem that nonimmediate operand is proper one for operand 1.
5900 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5901 ;; we take care in ix86_binary_operator_ok to not allow two memory
5902 ;; operands so proper swapping will be done in reload. This allow
5903 ;; patterns constructed from addsi_1 to match.
5904 (define_insn "addsi_1_zext"
5905 [(set (match_operand:DI 0 "register_operand" "=r,r")
5907 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5908 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5909 (clobber (reg:CC 17))]
5910 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5913 switch (get_attr_type (insn))
5916 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5917 return \"lea{l}\\t{%a2, %k0|%k0, %a2}\";
5920 if (operands[2] == const1_rtx)
5921 return \"inc{l}\\t%k0\";
5922 else if (operands[2] == constm1_rtx)
5923 return \"dec{l}\\t%k0\";
5928 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5929 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5930 if (GET_CODE (operands[2]) == CONST_INT
5931 && (INTVAL (operands[2]) == 128
5932 || (INTVAL (operands[2]) < 0
5933 && INTVAL (operands[2]) != -128)))
5935 operands[2] = GEN_INT (-INTVAL (operands[2]));
5936 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5938 return \"add{l}\\t{%2, %k0|%k0, %2}\";
5942 (cond [(eq_attr "alternative" "1")
5943 (const_string "lea")
5944 ; Current assemblers are broken and do not allow @GOTOFF in
5945 ; ought but a memory context.
5946 (match_operand:SI 2 "pic_symbolic_operand" "")
5947 (const_string "lea")
5948 (match_operand:SI 2 "incdec_operand" "")
5949 (const_string "incdec")
5951 (const_string "alu")))
5952 (set_attr "mode" "SI")])
5954 ;; Convert lea to the lea pattern to avoid flags dependency.
5956 [(set (match_operand:DI 0 "register_operand" "")
5958 (plus:SI (match_operand:SI 1 "register_operand" "")
5959 (match_operand:SI 2 "nonmemory_operand" ""))))
5960 (clobber (reg:CC 17))]
5962 && true_regnum (operands[0]) != true_regnum (operands[1])"
5964 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5967 operands[1] = gen_lowpart (Pmode, operands[1]);
5968 operands[2] = gen_lowpart (Pmode, operands[2]);
5971 (define_insn "*addsi_2"
5974 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5975 (match_operand:SI 2 "general_operand" "rmni,rni"))
5977 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5978 (plus:SI (match_dup 1) (match_dup 2)))]
5979 "ix86_match_ccmode (insn, CCGOCmode)
5980 && ix86_binary_operator_ok (PLUS, SImode, operands)
5981 /* Current assemblers are broken and do not allow @GOTOFF in
5982 ought but a memory context. */
5983 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5986 switch (get_attr_type (insn))
5989 if (! rtx_equal_p (operands[0], operands[1]))
5991 if (operands[2] == const1_rtx)
5992 return \"inc{l}\\t%0\";
5993 else if (operands[2] == constm1_rtx)
5994 return \"dec{l}\\t%0\";
5999 if (! rtx_equal_p (operands[0], operands[1]))
6001 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6002 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6003 if (GET_CODE (operands[2]) == CONST_INT
6004 && (INTVAL (operands[2]) == 128
6005 || (INTVAL (operands[2]) < 0
6006 && INTVAL (operands[2]) != -128)))
6008 operands[2] = GEN_INT (-INTVAL (operands[2]));
6009 return \"sub{l}\\t{%2, %0|%0, %2}\";
6011 return \"add{l}\\t{%2, %0|%0, %2}\";
6015 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6016 (const_string "incdec")
6017 (const_string "alu")))
6018 (set_attr "mode" "SI")])
6020 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6021 (define_insn "*addsi_2_zext"
6024 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6025 (match_operand:SI 2 "general_operand" "rmni"))
6027 (set (match_operand:DI 0 "register_operand" "=r")
6028 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6029 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6030 && ix86_binary_operator_ok (PLUS, SImode, operands)
6031 /* Current assemblers are broken and do not allow @GOTOFF in
6032 ought but a memory context. */
6033 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6036 switch (get_attr_type (insn))
6039 if (operands[2] == const1_rtx)
6040 return \"inc{l}\\t%k0\";
6041 else if (operands[2] == constm1_rtx)
6042 return \"dec{l}\\t%k0\";
6047 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6048 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6049 if (GET_CODE (operands[2]) == CONST_INT
6050 && (INTVAL (operands[2]) == 128
6051 || (INTVAL (operands[2]) < 0
6052 && INTVAL (operands[2]) != -128)))
6054 operands[2] = GEN_INT (-INTVAL (operands[2]));
6055 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6057 return \"add{l}\\t{%2, %k0|%k0, %2}\";
6061 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6062 (const_string "incdec")
6063 (const_string "alu")))
6064 (set_attr "mode" "SI")])
6066 (define_insn "*addsi_3"
6068 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6069 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6070 (clobber (match_scratch:SI 0 "=r"))]
6071 "ix86_match_ccmode (insn, CCZmode)
6072 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6073 /* Current assemblers are broken and do not allow @GOTOFF in
6074 ought but a memory context. */
6075 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6078 switch (get_attr_type (insn))
6081 if (! rtx_equal_p (operands[0], operands[1]))
6083 if (operands[2] == const1_rtx)
6084 return \"inc{l}\\t%0\";
6085 else if (operands[2] == constm1_rtx)
6086 return \"dec{l}\\t%0\";
6091 if (! rtx_equal_p (operands[0], operands[1]))
6093 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6094 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6095 if (GET_CODE (operands[2]) == CONST_INT
6096 && (INTVAL (operands[2]) == 128
6097 || (INTVAL (operands[2]) < 0
6098 && INTVAL (operands[2]) != -128)))
6100 operands[2] = GEN_INT (-INTVAL (operands[2]));
6101 return \"sub{l}\\t{%2, %0|%0, %2}\";
6103 return \"add{l}\\t{%2, %0|%0, %2}\";
6107 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6108 (const_string "incdec")
6109 (const_string "alu")))
6110 (set_attr "mode" "SI")])
6112 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6113 (define_insn "*addsi_3_zext"
6115 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6116 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6117 (set (match_operand:DI 0 "register_operand" "=r")
6118 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6119 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6120 && ix86_binary_operator_ok (PLUS, SImode, operands)
6121 /* Current assemblers are broken and do not allow @GOTOFF in
6122 ought but a memory context. */
6123 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6126 switch (get_attr_type (insn))
6129 if (operands[2] == const1_rtx)
6130 return \"inc{l}\\t%k0\";
6131 else if (operands[2] == constm1_rtx)
6132 return \"dec{l}\\t%k0\";
6137 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6138 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6139 if (GET_CODE (operands[2]) == CONST_INT
6140 && (INTVAL (operands[2]) == 128
6141 || (INTVAL (operands[2]) < 0
6142 && INTVAL (operands[2]) != -128)))
6144 operands[2] = GEN_INT (-INTVAL (operands[2]));
6145 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6147 return \"add{l}\\t{%2, %k0|%k0, %2}\";
6151 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6152 (const_string "incdec")
6153 (const_string "alu")))
6154 (set_attr "mode" "SI")])
6156 ; For comparisons agains 1, -1 and 128, we may generate better code
6157 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6158 ; is matched then. We can't accept general immediate, because for
6159 ; case of overflows, the result is messed up.
6160 ; This pattern also don't hold of 0x80000000, since the value overflows
6162 ; Also carry flag is reversed compared to cmp, so this converison is valid
6163 ; only for comparisons not depending on it.
6164 (define_insn "*addsi_4"
6166 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6167 (match_operand:SI 2 "const_int_operand" "n")))
6168 (clobber (match_scratch:SI 0 "=rm"))]
6169 "ix86_match_ccmode (insn, CCGCmode)
6170 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6173 switch (get_attr_type (insn))
6176 if (operands[2] == constm1_rtx)
6177 return \"inc{l}\\t%0\";
6178 else if (operands[2] == const1_rtx)
6179 return \"dec{l}\\t%0\";
6184 if (! rtx_equal_p (operands[0], operands[1]))
6186 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6187 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6188 if ((INTVAL (operands[2]) == -128
6189 || (INTVAL (operands[2]) > 0
6190 && INTVAL (operands[2]) != 128)))
6191 return \"sub{l}\\t{%2, %0|%0, %2}\";
6192 operands[2] = GEN_INT (-INTVAL (operands[2]));
6193 return \"add{l}\\t{%2, %0|%0, %2}\";
6197 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6198 (const_string "incdec")
6199 (const_string "alu")))
6200 (set_attr "mode" "SI")])
6202 (define_insn "*addsi_5"
6205 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6206 (match_operand:SI 2 "general_operand" "rmni"))
6208 (clobber (match_scratch:SI 0 "=r"))]
6209 "ix86_match_ccmode (insn, CCGOCmode)
6210 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6211 /* Current assemblers are broken and do not allow @GOTOFF in
6212 ought but a memory context. */
6213 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6216 switch (get_attr_type (insn))
6219 if (! rtx_equal_p (operands[0], operands[1]))
6221 if (operands[2] == const1_rtx)
6222 return \"inc{l}\\t%0\";
6223 else if (operands[2] == constm1_rtx)
6224 return \"dec{l}\\t%0\";
6229 if (! rtx_equal_p (operands[0], operands[1]))
6231 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6232 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6233 if (GET_CODE (operands[2]) == CONST_INT
6234 && (INTVAL (operands[2]) == 128
6235 || (INTVAL (operands[2]) < 0
6236 && INTVAL (operands[2]) != -128)))
6238 operands[2] = GEN_INT (-INTVAL (operands[2]));
6239 return \"sub{l}\\t{%2, %0|%0, %2}\";
6241 return \"add{l}\\t{%2, %0|%0, %2}\";
6245 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6246 (const_string "incdec")
6247 (const_string "alu")))
6248 (set_attr "mode" "SI")])
6250 (define_expand "addhi3"
6251 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6252 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6253 (match_operand:HI 2 "general_operand" "")))
6254 (clobber (reg:CC 17))])]
6255 "TARGET_HIMODE_MATH"
6256 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6258 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6259 ;; type optimizations enabled by define-splits. This is not important
6260 ;; for PII, and in fact harmful because of partial register stalls.
6262 (define_insn "*addhi_1_lea"
6263 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6264 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6265 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6266 (clobber (reg:CC 17))]
6267 "!TARGET_PARTIAL_REG_STALL
6268 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6271 switch (get_attr_type (insn))
6276 if (operands[2] == const1_rtx)
6277 return \"inc{w}\\t%0\";
6278 else if (operands[2] == constm1_rtx
6279 || (GET_CODE (operands[2]) == CONST_INT
6280 && INTVAL (operands[2]) == 65535))
6281 return \"dec{w}\\t%0\";
6285 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6286 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6287 if (GET_CODE (operands[2]) == CONST_INT
6288 && (INTVAL (operands[2]) == 128
6289 || (INTVAL (operands[2]) < 0
6290 && INTVAL (operands[2]) != -128)))
6292 operands[2] = GEN_INT (-INTVAL (operands[2]));
6293 return \"sub{w}\\t{%2, %0|%0, %2}\";
6295 return \"add{w}\\t{%2, %0|%0, %2}\";
6299 (if_then_else (eq_attr "alternative" "2")
6300 (const_string "lea")
6301 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6302 (const_string "incdec")
6303 (const_string "alu"))))
6304 (set_attr "mode" "HI,HI,SI")])
6306 (define_insn "*addhi_1"
6307 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6308 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6309 (match_operand:HI 2 "general_operand" "ri,rm")))
6310 (clobber (reg:CC 17))]
6311 "TARGET_PARTIAL_REG_STALL
6312 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6315 switch (get_attr_type (insn))
6318 if (operands[2] == const1_rtx)
6319 return \"inc{w}\\t%0\";
6320 else if (operands[2] == constm1_rtx
6321 || (GET_CODE (operands[2]) == CONST_INT
6322 && INTVAL (operands[2]) == 65535))
6323 return \"dec{w}\\t%0\";
6327 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6328 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6329 if (GET_CODE (operands[2]) == CONST_INT
6330 && (INTVAL (operands[2]) == 128
6331 || (INTVAL (operands[2]) < 0
6332 && INTVAL (operands[2]) != -128)))
6334 operands[2] = GEN_INT (-INTVAL (operands[2]));
6335 return \"sub{w}\\t{%2, %0|%0, %2}\";
6337 return \"add{w}\\t{%2, %0|%0, %2}\";
6341 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6342 (const_string "incdec")
6343 (const_string "alu")))
6344 (set_attr "mode" "HI")])
6346 (define_insn "*addhi_2"
6349 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6350 (match_operand:HI 2 "general_operand" "rmni,rni"))
6352 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6353 (plus:HI (match_dup 1) (match_dup 2)))]
6354 "ix86_match_ccmode (insn, CCGOCmode)
6355 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6358 switch (get_attr_type (insn))
6361 if (operands[2] == const1_rtx)
6362 return \"inc{w}\\t%0\";
6363 else if (operands[2] == constm1_rtx
6364 || (GET_CODE (operands[2]) == CONST_INT
6365 && INTVAL (operands[2]) == 65535))
6366 return \"dec{w}\\t%0\";
6370 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6371 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6372 if (GET_CODE (operands[2]) == CONST_INT
6373 && (INTVAL (operands[2]) == 128
6374 || (INTVAL (operands[2]) < 0
6375 && INTVAL (operands[2]) != -128)))
6377 operands[2] = GEN_INT (-INTVAL (operands[2]));
6378 return \"sub{w}\\t{%2, %0|%0, %2}\";
6380 return \"add{w}\\t{%2, %0|%0, %2}\";
6384 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6385 (const_string "incdec")
6386 (const_string "alu")))
6387 (set_attr "mode" "HI")])
6389 (define_insn "*addhi_3"
6391 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6392 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6393 (clobber (match_scratch:HI 0 "=r"))]
6394 "ix86_match_ccmode (insn, CCZmode)
6395 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6398 switch (get_attr_type (insn))
6401 if (operands[2] == const1_rtx)
6402 return \"inc{w}\\t%0\";
6403 else if (operands[2] == constm1_rtx
6404 || (GET_CODE (operands[2]) == CONST_INT
6405 && INTVAL (operands[2]) == 65535))
6406 return \"dec{w}\\t%0\";
6410 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6411 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6412 if (GET_CODE (operands[2]) == CONST_INT
6413 && (INTVAL (operands[2]) == 128
6414 || (INTVAL (operands[2]) < 0
6415 && INTVAL (operands[2]) != -128)))
6417 operands[2] = GEN_INT (-INTVAL (operands[2]));
6418 return \"sub{w}\\t{%2, %0|%0, %2}\";
6420 return \"add{w}\\t{%2, %0|%0, %2}\";
6424 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6425 (const_string "incdec")
6426 (const_string "alu")))
6427 (set_attr "mode" "HI")])
6429 ; See comments above addsi_3_imm for details.
6430 (define_insn "*addhi_4"
6432 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6433 (match_operand:HI 2 "const_int_operand" "n")))
6434 (clobber (match_scratch:HI 0 "=rm"))]
6435 "ix86_match_ccmode (insn, CCGCmode)
6436 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6439 switch (get_attr_type (insn))
6442 if (operands[2] == constm1_rtx
6443 || (GET_CODE (operands[2]) == CONST_INT
6444 && INTVAL (operands[2]) == 65535))
6445 return \"inc{w}\\t%0\";
6446 else if (operands[2] == const1_rtx)
6447 return \"dec{w}\\t%0\";
6452 if (! rtx_equal_p (operands[0], operands[1]))
6454 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6455 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6456 if ((INTVAL (operands[2]) == -128
6457 || (INTVAL (operands[2]) > 0
6458 && INTVAL (operands[2]) != 128)))
6459 return \"sub{w}\\t{%2, %0|%0, %2}\";
6460 operands[2] = GEN_INT (-INTVAL (operands[2]));
6461 return \"add{w}\\t{%2, %0|%0, %2}\";
6465 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6466 (const_string "incdec")
6467 (const_string "alu")))
6468 (set_attr "mode" "SI")])
6471 (define_insn "*addhi_5"
6474 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6475 (match_operand:HI 2 "general_operand" "rmni"))
6477 (clobber (match_scratch:HI 0 "=r"))]
6478 "ix86_match_ccmode (insn, CCGOCmode)
6479 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6482 switch (get_attr_type (insn))
6485 if (operands[2] == const1_rtx)
6486 return \"inc{w}\\t%0\";
6487 else if (operands[2] == constm1_rtx
6488 || (GET_CODE (operands[2]) == CONST_INT
6489 && INTVAL (operands[2]) == 65535))
6490 return \"dec{w}\\t%0\";
6494 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6495 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6496 if (GET_CODE (operands[2]) == CONST_INT
6497 && (INTVAL (operands[2]) == 128
6498 || (INTVAL (operands[2]) < 0
6499 && INTVAL (operands[2]) != -128)))
6501 operands[2] = GEN_INT (-INTVAL (operands[2]));
6502 return \"sub{w}\\t{%2, %0|%0, %2}\";
6504 return \"add{w}\\t{%2, %0|%0, %2}\";
6508 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6509 (const_string "incdec")
6510 (const_string "alu")))
6511 (set_attr "mode" "HI")])
6513 (define_expand "addqi3"
6514 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6515 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6516 (match_operand:QI 2 "general_operand" "")))
6517 (clobber (reg:CC 17))])]
6518 "TARGET_QIMODE_MATH"
6519 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6521 ;; %%% Potential partial reg stall on alternative 2. What to do?
6522 (define_insn "*addqi_1_lea"
6523 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6524 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6525 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6526 (clobber (reg:CC 17))]
6527 "!TARGET_PARTIAL_REG_STALL
6528 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6531 int widen = (which_alternative == 2);
6532 switch (get_attr_type (insn))
6537 if (operands[2] == const1_rtx)
6538 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6539 else if (operands[2] == constm1_rtx
6540 || (GET_CODE (operands[2]) == CONST_INT
6541 && INTVAL (operands[2]) == 255))
6542 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6546 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6547 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6548 if (GET_CODE (operands[2]) == CONST_INT
6549 && (INTVAL (operands[2]) == 128
6550 || (INTVAL (operands[2]) < 0
6551 && INTVAL (operands[2]) != -128)))
6553 operands[2] = GEN_INT (-INTVAL (operands[2]));
6555 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6557 return \"sub{b}\\t{%2, %0|%0, %2}\";
6560 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6562 return \"add{b}\\t{%2, %0|%0, %2}\";
6566 (if_then_else (eq_attr "alternative" "3")
6567 (const_string "lea")
6568 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6569 (const_string "incdec")
6570 (const_string "alu"))))
6571 (set_attr "mode" "QI,QI,SI,SI")])
6573 (define_insn "*addqi_1"
6574 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6575 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6576 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6577 (clobber (reg:CC 17))]
6578 "TARGET_PARTIAL_REG_STALL
6579 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6582 int widen = (which_alternative == 2);
6583 switch (get_attr_type (insn))
6586 if (operands[2] == const1_rtx)
6587 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6588 else if (operands[2] == constm1_rtx
6589 || (GET_CODE (operands[2]) == CONST_INT
6590 && INTVAL (operands[2]) == 255))
6591 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6595 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6596 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6597 if (GET_CODE (operands[2]) == CONST_INT
6598 && (INTVAL (operands[2]) == 128
6599 || (INTVAL (operands[2]) < 0
6600 && INTVAL (operands[2]) != -128)))
6602 operands[2] = GEN_INT (-INTVAL (operands[2]));
6604 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6606 return \"sub{b}\\t{%2, %0|%0, %2}\";
6609 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6611 return \"add{b}\\t{%2, %0|%0, %2}\";
6615 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6616 (const_string "incdec")
6617 (const_string "alu")))
6618 (set_attr "mode" "QI,QI,SI")])
6620 (define_insn "*addqi_2"
6623 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6624 (match_operand:QI 2 "general_operand" "qmni,qni"))
6626 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6627 (plus:QI (match_dup 1) (match_dup 2)))]
6628 "ix86_match_ccmode (insn, CCGOCmode)
6629 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6632 switch (get_attr_type (insn))
6635 if (operands[2] == const1_rtx)
6636 return \"inc{b}\\t%0\";
6637 else if (operands[2] == constm1_rtx
6638 || (GET_CODE (operands[2]) == CONST_INT
6639 && INTVAL (operands[2]) == 255))
6640 return \"dec{b}\\t%0\";
6644 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6645 if (GET_CODE (operands[2]) == CONST_INT
6646 && INTVAL (operands[2]) < 0)
6648 operands[2] = GEN_INT (-INTVAL (operands[2]));
6649 return \"sub{b}\\t{%2, %0|%0, %2}\";
6651 return \"add{b}\\t{%2, %0|%0, %2}\";
6655 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6656 (const_string "incdec")
6657 (const_string "alu")))
6658 (set_attr "mode" "QI")])
6660 (define_insn "*addqi_3"
6662 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6663 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6664 (clobber (match_scratch:QI 0 "=q"))]
6665 "ix86_match_ccmode (insn, CCZmode)
6666 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6669 switch (get_attr_type (insn))
6672 if (operands[2] == const1_rtx)
6673 return \"inc{b}\\t%0\";
6674 else if (operands[2] == constm1_rtx
6675 || (GET_CODE (operands[2]) == CONST_INT
6676 && INTVAL (operands[2]) == 255))
6677 return \"dec{b}\\t%0\";
6681 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6682 if (GET_CODE (operands[2]) == CONST_INT
6683 && INTVAL (operands[2]) < 0)
6685 operands[2] = GEN_INT (-INTVAL (operands[2]));
6686 return \"sub{b}\\t{%2, %0|%0, %2}\";
6688 return \"add{b}\\t{%2, %0|%0, %2}\";
6692 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6693 (const_string "incdec")
6694 (const_string "alu")))
6695 (set_attr "mode" "QI")])
6697 ; See comments above addsi_3_imm for details.
6698 (define_insn "*addqi_4"
6700 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6701 (match_operand:QI 2 "const_int_operand" "n")))
6702 (clobber (match_scratch:QI 0 "=qm"))]
6703 "ix86_match_ccmode (insn, CCGCmode)
6704 && (INTVAL (operands[2]) & 0xff) != 0x80"
6707 switch (get_attr_type (insn))
6710 if (operands[2] == constm1_rtx
6711 || (GET_CODE (operands[2]) == CONST_INT
6712 && INTVAL (operands[2]) == 255))
6713 return \"inc{b}\\t%0\";
6714 else if (operands[2] == const1_rtx)
6715 return \"dec{b}\\t%0\";
6720 if (! rtx_equal_p (operands[0], operands[1]))
6722 if (INTVAL (operands[2]) < 0)
6724 operands[2] = GEN_INT (-INTVAL (operands[2]));
6725 return \"add{b}\\t{%2, %0|%0, %2}\";
6727 return \"sub{b}\\t{%2, %0|%0, %2}\";
6731 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6732 (const_string "incdec")
6733 (const_string "alu")))
6734 (set_attr "mode" "QI")])
6737 (define_insn "*addqi_5"
6740 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6741 (match_operand:QI 2 "general_operand" "qmni"))
6743 (clobber (match_scratch:QI 0 "=q"))]
6744 "ix86_match_ccmode (insn, CCGOCmode)
6745 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6748 switch (get_attr_type (insn))
6751 if (operands[2] == const1_rtx)
6752 return \"inc{b}\\t%0\";
6753 else if (operands[2] == constm1_rtx
6754 || (GET_CODE (operands[2]) == CONST_INT
6755 && INTVAL (operands[2]) == 255))
6756 return \"dec{b}\\t%0\";
6760 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6761 if (GET_CODE (operands[2]) == CONST_INT
6762 && INTVAL (operands[2]) < 0)
6764 operands[2] = GEN_INT (-INTVAL (operands[2]));
6765 return \"sub{b}\\t{%2, %0|%0, %2}\";
6767 return \"add{b}\\t{%2, %0|%0, %2}\";
6771 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6772 (const_string "incdec")
6773 (const_string "alu")))
6774 (set_attr "mode" "QI")])
6777 (define_insn "addqi_ext_1"
6778 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6783 (match_operand 1 "ext_register_operand" "0")
6786 (match_operand:QI 2 "general_operand" "qmn")))
6787 (clobber (reg:CC 17))]
6791 switch (get_attr_type (insn))
6794 if (operands[2] == const1_rtx)
6795 return \"inc{b}\\t%h0\";
6796 else if (operands[2] == constm1_rtx
6797 || (GET_CODE (operands[2]) == CONST_INT
6798 && INTVAL (operands[2]) == 255))
6799 return \"dec{b}\\t%h0\";
6803 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6807 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6808 (const_string "incdec")
6809 (const_string "alu")))
6810 (set_attr "mode" "QI")])
6812 (define_insn "*addqi_ext_1_rex64"
6813 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6818 (match_operand 1 "ext_register_operand" "0")
6821 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6822 (clobber (reg:CC 17))]
6826 switch (get_attr_type (insn))
6829 if (operands[2] == const1_rtx)
6830 return \"inc{b}\\t%h0\";
6831 else if (operands[2] == constm1_rtx
6832 || (GET_CODE (operands[2]) == CONST_INT
6833 && INTVAL (operands[2]) == 255))
6834 return \"dec{b}\\t%h0\";
6838 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6842 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6843 (const_string "incdec")
6844 (const_string "alu")))
6845 (set_attr "mode" "QI")])
6847 (define_insn "*addqi_ext_2"
6848 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6853 (match_operand 1 "ext_register_operand" "%0")
6857 (match_operand 2 "ext_register_operand" "Q")
6860 (clobber (reg:CC 17))]
6862 "add{b}\\t{%h2, %h0|%h0, %h2}"
6863 [(set_attr "type" "alu")
6864 (set_attr "mode" "QI")])
6866 ;; The patterns that match these are at the end of this file.
6868 (define_expand "addxf3"
6869 [(set (match_operand:XF 0 "register_operand" "")
6870 (plus:XF (match_operand:XF 1 "register_operand" "")
6871 (match_operand:XF 2 "register_operand" "")))]
6872 "TARGET_80387 && !TARGET_64BIT"
6875 (define_expand "addtf3"
6876 [(set (match_operand:TF 0 "register_operand" "")
6877 (plus:TF (match_operand:TF 1 "register_operand" "")
6878 (match_operand:TF 2 "register_operand" "")))]
6882 (define_expand "adddf3"
6883 [(set (match_operand:DF 0 "register_operand" "")
6884 (plus:DF (match_operand:DF 1 "register_operand" "")
6885 (match_operand:DF 2 "nonimmediate_operand" "")))]
6886 "TARGET_80387 || TARGET_SSE2"
6889 (define_expand "addsf3"
6890 [(set (match_operand:SF 0 "register_operand" "")
6891 (plus:SF (match_operand:SF 1 "register_operand" "")
6892 (match_operand:SF 2 "nonimmediate_operand" "")))]
6893 "TARGET_80387 || TARGET_SSE"
6896 ;; Subtract instructions
6898 ;; %%% splits for subsidi3
6900 (define_expand "subdi3"
6901 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6902 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6903 (match_operand:DI 2 "x86_64_general_operand" "")))
6904 (clobber (reg:CC 17))])]
6906 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6908 (define_insn "*subdi3_1"
6909 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6910 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6911 (match_operand:DI 2 "general_operand" "roiF,riF")))
6912 (clobber (reg:CC 17))]
6917 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6918 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6919 (match_operand:DI 2 "general_operand" "")))
6920 (clobber (reg:CC 17))]
6921 "reload_completed && !TARGET_64BIT"
6922 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6923 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6924 (parallel [(set (match_dup 3)
6925 (minus:SI (match_dup 4)
6926 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6928 (clobber (reg:CC 17))])]
6929 "split_di (operands+0, 1, operands+0, operands+3);
6930 split_di (operands+1, 1, operands+1, operands+4);
6931 split_di (operands+2, 1, operands+2, operands+5);")
6933 (define_insn "subdi3_carry_rex64"
6934 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6935 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6936 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6937 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6938 (clobber (reg:CC 17))]
6939 "ix86_binary_operator_ok (MINUS, DImode, operands)"
6940 "sbb{q}\\t{%2, %0|%0, %2}"
6941 [(set_attr "type" "alu")
6942 (set_attr "pent_pair" "pu")
6943 (set_attr "ppro_uops" "few")
6944 (set_attr "mode" "DI")])
6946 (define_insn "*subdi_1_rex64"
6947 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6948 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6949 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6950 (clobber (reg:CC 17))]
6951 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6952 "sub{q}\\t{%2, %0|%0, %2}"
6953 [(set_attr "type" "alu")
6954 (set_attr "mode" "DI")])
6956 (define_insn "*subdi_2_rex64"
6959 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6960 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6962 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6963 (minus:DI (match_dup 1) (match_dup 2)))]
6964 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6965 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6966 "sub{q}\\t{%2, %0|%0, %2}"
6967 [(set_attr "type" "alu")
6968 (set_attr "mode" "DI")])
6970 (define_insn "*subdi_3_rex63"
6972 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6973 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6974 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6975 (minus:DI (match_dup 1) (match_dup 2)))]
6976 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6977 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6978 "sub{q}\\t{%2, %0|%0, %2}"
6979 [(set_attr "type" "alu")
6980 (set_attr "mode" "DI")])
6983 (define_insn "subsi3_carry"
6984 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6985 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6986 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6987 (match_operand:SI 2 "general_operand" "ri,rm"))))
6988 (clobber (reg:CC 17))]
6989 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6990 "sbb{l}\\t{%2, %0|%0, %2}"
6991 [(set_attr "type" "alu")
6992 (set_attr "pent_pair" "pu")
6993 (set_attr "ppro_uops" "few")
6994 (set_attr "mode" "SI")])
6996 (define_insn "subsi3_carry_zext"
6997 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6999 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
7000 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7001 (match_operand:SI 2 "general_operand" "ri,rm")))))
7002 (clobber (reg:CC 17))]
7003 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7004 "sbb{l}\\t{%2, %k0|%k0, %2}"
7005 [(set_attr "type" "alu")
7006 (set_attr "pent_pair" "pu")
7007 (set_attr "ppro_uops" "few")
7008 (set_attr "mode" "SI")])
7010 (define_expand "subsi3"
7011 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7012 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
7013 (match_operand:SI 2 "general_operand" "")))
7014 (clobber (reg:CC 17))])]
7016 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
7018 (define_insn "*subsi_1"
7019 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7020 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7021 (match_operand:SI 2 "general_operand" "ri,rm")))
7022 (clobber (reg:CC 17))]
7023 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7024 "sub{l}\\t{%2, %0|%0, %2}"
7025 [(set_attr "type" "alu")
7026 (set_attr "mode" "SI")])
7028 (define_insn "*subsi_1_zext"
7029 [(set (match_operand:DI 0 "register_operand" "=r")
7031 (minus:SI (match_operand:SI 1 "register_operand" "0")
7032 (match_operand:SI 2 "general_operand" "rim"))))
7033 (clobber (reg:CC 17))]
7034 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7035 "sub{l}\\t{%2, %k0|%k0, %2}"
7036 [(set_attr "type" "alu")
7037 (set_attr "mode" "SI")])
7039 (define_insn "*subsi_2"
7042 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7043 (match_operand:SI 2 "general_operand" "ri,rm"))
7045 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7046 (minus:SI (match_dup 1) (match_dup 2)))]
7047 "ix86_match_ccmode (insn, CCGOCmode)
7048 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7049 "sub{l}\\t{%2, %0|%0, %2}"
7050 [(set_attr "type" "alu")
7051 (set_attr "mode" "SI")])
7053 (define_insn "*subsi_2_zext"
7056 (minus:SI (match_operand:SI 1 "register_operand" "0")
7057 (match_operand:SI 2 "general_operand" "rim"))
7059 (set (match_operand:DI 0 "register_operand" "=r")
7061 (minus:SI (match_dup 1)
7063 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7064 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7065 "sub{l}\\t{%2, %k0|%k0, %2}"
7066 [(set_attr "type" "alu")
7067 (set_attr "mode" "SI")])
7069 (define_insn "*subsi_3"
7071 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7072 (match_operand:SI 2 "general_operand" "ri,rm")))
7073 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7074 (minus:SI (match_dup 1) (match_dup 2)))]
7075 "ix86_match_ccmode (insn, CCmode)
7076 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7077 "sub{l}\\t{%2, %0|%0, %2}"
7078 [(set_attr "type" "alu")
7079 (set_attr "mode" "SI")])
7081 (define_insn "*subsi_3_zext"
7083 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7084 (match_operand:SI 2 "general_operand" "rim")))
7085 (set (match_operand:DI 0 "register_operand" "=r")
7087 (minus:SI (match_dup 1)
7089 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7090 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7091 "sub{q}\\t{%2, %0|%0, %2}"
7092 [(set_attr "type" "alu")
7093 (set_attr "mode" "DI")])
7095 (define_expand "subhi3"
7096 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7097 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7098 (match_operand:HI 2 "general_operand" "")))
7099 (clobber (reg:CC 17))])]
7100 "TARGET_HIMODE_MATH"
7101 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7103 (define_insn "*subhi_1"
7104 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7105 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7106 (match_operand:HI 2 "general_operand" "ri,rm")))
7107 (clobber (reg:CC 17))]
7108 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7109 "sub{w}\\t{%2, %0|%0, %2}"
7110 [(set_attr "type" "alu")
7111 (set_attr "mode" "HI")])
7113 (define_insn "*subhi_2"
7116 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7117 (match_operand:HI 2 "general_operand" "ri,rm"))
7119 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7120 (minus:HI (match_dup 1) (match_dup 2)))]
7121 "ix86_match_ccmode (insn, CCGOCmode)
7122 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7123 "sub{w}\\t{%2, %0|%0, %2}"
7124 [(set_attr "type" "alu")
7125 (set_attr "mode" "HI")])
7127 (define_insn "*subhi_3"
7129 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7130 (match_operand:HI 2 "general_operand" "ri,rm")))
7131 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7132 (minus:HI (match_dup 1) (match_dup 2)))]
7133 "ix86_match_ccmode (insn, CCmode)
7134 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7135 "sub{w}\\t{%2, %0|%0, %2}"
7136 [(set_attr "type" "alu")
7137 (set_attr "mode" "HI")])
7139 (define_expand "subqi3"
7140 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7141 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7142 (match_operand:QI 2 "general_operand" "")))
7143 (clobber (reg:CC 17))])]
7144 "TARGET_QIMODE_MATH"
7145 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7147 (define_insn "*subqi_1"
7148 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7149 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7150 (match_operand:QI 2 "general_operand" "qn,qmn")))
7151 (clobber (reg:CC 17))]
7152 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7153 "sub{b}\\t{%2, %0|%0, %2}"
7154 [(set_attr "type" "alu")
7155 (set_attr "mode" "QI")])
7157 (define_insn "*subqi_2"
7160 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7161 (match_operand:QI 2 "general_operand" "qi,qm"))
7163 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7164 (minus:HI (match_dup 1) (match_dup 2)))]
7165 "ix86_match_ccmode (insn, CCGOCmode)
7166 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7167 "sub{b}\\t{%2, %0|%0, %2}"
7168 [(set_attr "type" "alu")
7169 (set_attr "mode" "QI")])
7171 (define_insn "*subqi_3"
7173 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7174 (match_operand:QI 2 "general_operand" "qi,qm")))
7175 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7176 (minus:HI (match_dup 1) (match_dup 2)))]
7177 "ix86_match_ccmode (insn, CCmode)
7178 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7179 "sub{b}\\t{%2, %0|%0, %2}"
7180 [(set_attr "type" "alu")
7181 (set_attr "mode" "QI")])
7183 ;; The patterns that match these are at the end of this file.
7185 (define_expand "subxf3"
7186 [(set (match_operand:XF 0 "register_operand" "")
7187 (minus:XF (match_operand:XF 1 "register_operand" "")
7188 (match_operand:XF 2 "register_operand" "")))]
7189 "TARGET_80387 && !TARGET_64BIT"
7192 (define_expand "subtf3"
7193 [(set (match_operand:TF 0 "register_operand" "")
7194 (minus:TF (match_operand:TF 1 "register_operand" "")
7195 (match_operand:TF 2 "register_operand" "")))]
7199 (define_expand "subdf3"
7200 [(set (match_operand:DF 0 "register_operand" "")
7201 (minus:DF (match_operand:DF 1 "register_operand" "")
7202 (match_operand:DF 2 "nonimmediate_operand" "")))]
7203 "TARGET_80387 || TARGET_SSE2"
7206 (define_expand "subsf3"
7207 [(set (match_operand:SF 0 "register_operand" "")
7208 (minus:SF (match_operand:SF 1 "register_operand" "")
7209 (match_operand:SF 2 "nonimmediate_operand" "")))]
7210 "TARGET_80387 || TARGET_SSE"
7213 ;; Multiply instructions
7215 (define_expand "muldi3"
7216 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7217 (mult:DI (match_operand:DI 1 "register_operand" "")
7218 (match_operand:DI 2 "x86_64_general_operand" "")))
7219 (clobber (reg:CC 17))])]
7223 (define_insn "*muldi3_1_rex64"
7224 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7225 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
7226 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7227 (clobber (reg:CC 17))]
7228 "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
7231 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7232 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7233 imul{q}\\t{%2, %0|%0, %2}"
7234 [(set_attr "type" "imul")
7235 (set_attr "prefix_0f" "0,0,1")
7236 (set_attr "mode" "DI")])
7238 (define_expand "mulsi3"
7239 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7240 (mult:SI (match_operand:SI 1 "register_operand" "")
7241 (match_operand:SI 2 "general_operand" "")))
7242 (clobber (reg:CC 17))])]
7246 (define_insn "*mulsi3_1"
7247 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7248 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7249 (match_operand:SI 2 "general_operand" "K,i,mr")))
7250 (clobber (reg:CC 17))]
7251 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7252 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7253 ; there are two ways of writing the exact same machine instruction
7254 ; in assembly language. One, for example, is:
7258 ; while the other is:
7260 ; imul $12, %eax, %eax
7262 ; The first is simply short-hand for the latter. But, some assemblers,
7263 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7265 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7266 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7267 imul{l}\\t{%2, %0|%0, %2}"
7268 [(set_attr "type" "imul")
7269 (set_attr "prefix_0f" "0,0,1")
7270 (set_attr "mode" "SI")])
7272 (define_insn "*mulsi3_1_zext"
7273 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7275 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7276 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7277 (clobber (reg:CC 17))]
7279 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7280 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7281 ; there are two ways of writing the exact same machine instruction
7282 ; in assembly language. One, for example, is:
7286 ; while the other is:
7288 ; imul $12, %eax, %eax
7290 ; The first is simply short-hand for the latter. But, some assemblers,
7291 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7293 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7294 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7295 imul{l}\\t{%2, %k0|%k0, %2}"
7296 [(set_attr "type" "imul")
7297 (set_attr "prefix_0f" "0,0,1")
7298 (set_attr "mode" "SI")])
7300 (define_expand "mulhi3"
7301 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7302 (mult:HI (match_operand:HI 1 "register_operand" "")
7303 (match_operand:HI 2 "general_operand" "")))
7304 (clobber (reg:CC 17))])]
7305 "TARGET_HIMODE_MATH"
7308 (define_insn "*mulhi3_1"
7309 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7310 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
7311 (match_operand:HI 2 "general_operand" "K,i,mr")))
7312 (clobber (reg:CC 17))]
7313 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7314 ; %%% There was a note about "Assembler has weird restrictions",
7315 ; concerning alternative 1 when op1 == op0. True?
7317 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7318 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7319 imul{w}\\t{%2, %0|%0, %2}"
7320 [(set_attr "type" "imul")
7321 (set_attr "prefix_0f" "0,0,1")
7322 (set_attr "mode" "HI")])
7324 (define_insn "mulqi3"
7325 [(set (match_operand:QI 0 "register_operand" "=a")
7326 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7327 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7328 (clobber (reg:CC 17))]
7329 "TARGET_QIMODE_MATH"
7331 [(set_attr "type" "imul")
7332 (set_attr "length_immediate" "0")
7333 (set_attr "mode" "QI")])
7335 (define_insn "umulqihi3"
7336 [(set (match_operand:HI 0 "register_operand" "=a")
7337 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7338 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7339 (clobber (reg:CC 17))]
7340 "TARGET_QIMODE_MATH"
7342 [(set_attr "type" "imul")
7343 (set_attr "length_immediate" "0")
7344 (set_attr "mode" "QI")])
7346 (define_insn "mulqihi3"
7347 [(set (match_operand:HI 0 "register_operand" "=a")
7348 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7349 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7350 (clobber (reg:CC 17))]
7351 "TARGET_QIMODE_MATH"
7353 [(set_attr "type" "imul")
7354 (set_attr "length_immediate" "0")
7355 (set_attr "mode" "QI")])
7357 (define_insn "umulditi3"
7358 [(set (match_operand:TI 0 "register_operand" "=A")
7359 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7360 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7361 (clobber (reg:CC 17))]
7364 [(set_attr "type" "imul")
7365 (set_attr "ppro_uops" "few")
7366 (set_attr "length_immediate" "0")
7367 (set_attr "mode" "DI")])
7369 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7370 (define_insn "umulsidi3"
7371 [(set (match_operand:DI 0 "register_operand" "=A")
7372 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7373 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7374 (clobber (reg:CC 17))]
7377 [(set_attr "type" "imul")
7378 (set_attr "ppro_uops" "few")
7379 (set_attr "length_immediate" "0")
7380 (set_attr "mode" "SI")])
7382 (define_insn "mulditi3"
7383 [(set (match_operand:TI 0 "register_operand" "=A")
7384 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7385 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7386 (clobber (reg:CC 17))]
7389 [(set_attr "type" "imul")
7390 (set_attr "length_immediate" "0")
7391 (set_attr "mode" "DI")])
7393 (define_insn "mulsidi3"
7394 [(set (match_operand:DI 0 "register_operand" "=A")
7395 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7396 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7397 (clobber (reg:CC 17))]
7400 [(set_attr "type" "imul")
7401 (set_attr "length_immediate" "0")
7402 (set_attr "mode" "SI")])
7404 (define_insn "*umuldi3_highpart_rex64"
7405 [(set (match_operand:DI 0 "register_operand" "=d")
7408 (mult:TI (zero_extend:TI
7409 (match_operand:DI 1 "register_operand" "%a"))
7411 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7413 (clobber (match_scratch:DI 3 "=a"))
7414 (clobber (reg:CC 17))]
7417 [(set_attr "type" "imul")
7418 (set_attr "ppro_uops" "few")
7419 (set_attr "length_immediate" "0")
7420 (set_attr "mode" "DI")])
7422 (define_insn "umulsi3_highpart"
7423 [(set (match_operand:SI 0 "register_operand" "=d")
7426 (mult:DI (zero_extend:DI
7427 (match_operand:SI 1 "register_operand" "%a"))
7429 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7431 (clobber (match_scratch:SI 3 "=a"))
7432 (clobber (reg:CC 17))]
7435 [(set_attr "type" "imul")
7436 (set_attr "ppro_uops" "few")
7437 (set_attr "length_immediate" "0")
7438 (set_attr "mode" "SI")])
7440 (define_insn "*umulsi3_highpart_zext"
7441 [(set (match_operand:DI 0 "register_operand" "=d")
7442 (zero_extend:DI (truncate:SI
7444 (mult:DI (zero_extend:DI
7445 (match_operand:SI 1 "register_operand" "%a"))
7447 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7449 (clobber (match_scratch:SI 3 "=a"))
7450 (clobber (reg:CC 17))]
7453 [(set_attr "type" "imul")
7454 (set_attr "ppro_uops" "few")
7455 (set_attr "length_immediate" "0")
7456 (set_attr "mode" "SI")])
7458 (define_insn "*smuldi3_highpart_rex64"
7459 [(set (match_operand:DI 0 "register_operand" "=d")
7462 (mult:TI (sign_extend:TI
7463 (match_operand:DI 1 "register_operand" "%a"))
7465 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7467 (clobber (match_scratch:DI 3 "=a"))
7468 (clobber (reg:CC 17))]
7471 [(set_attr "type" "imul")
7472 (set_attr "ppro_uops" "few")
7473 (set_attr "mode" "DI")])
7475 (define_insn "smulsi3_highpart"
7476 [(set (match_operand:SI 0 "register_operand" "=d")
7479 (mult:DI (sign_extend:DI
7480 (match_operand:SI 1 "register_operand" "%a"))
7482 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7484 (clobber (match_scratch:SI 3 "=a"))
7485 (clobber (reg:CC 17))]
7488 [(set_attr "type" "imul")
7489 (set_attr "ppro_uops" "few")
7490 (set_attr "mode" "SI")])
7492 (define_insn "*smulsi3_highpart_zext"
7493 [(set (match_operand:DI 0 "register_operand" "=d")
7494 (zero_extend:DI (truncate:SI
7496 (mult:DI (sign_extend:DI
7497 (match_operand:SI 1 "register_operand" "%a"))
7499 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7501 (clobber (match_scratch:SI 3 "=a"))
7502 (clobber (reg:CC 17))]
7505 [(set_attr "type" "imul")
7506 (set_attr "ppro_uops" "few")
7507 (set_attr "mode" "SI")])
7509 ;; The patterns that match these are at the end of this file.
7511 (define_expand "mulxf3"
7512 [(set (match_operand:XF 0 "register_operand" "")
7513 (mult:XF (match_operand:XF 1 "register_operand" "")
7514 (match_operand:XF 2 "register_operand" "")))]
7515 "TARGET_80387 && !TARGET_64BIT"
7518 (define_expand "multf3"
7519 [(set (match_operand:TF 0 "register_operand" "")
7520 (mult:TF (match_operand:TF 1 "register_operand" "")
7521 (match_operand:TF 2 "register_operand" "")))]
7525 (define_expand "muldf3"
7526 [(set (match_operand:DF 0 "register_operand" "")
7527 (mult:DF (match_operand:DF 1 "register_operand" "")
7528 (match_operand:DF 2 "nonimmediate_operand" "")))]
7529 "TARGET_80387 || TARGET_SSE2"
7532 (define_expand "mulsf3"
7533 [(set (match_operand:SF 0 "register_operand" "")
7534 (mult:SF (match_operand:SF 1 "register_operand" "")
7535 (match_operand:SF 2 "nonimmediate_operand" "")))]
7536 "TARGET_80387 || TARGET_SSE"
7539 ;; Divide instructions
7541 (define_insn "divqi3"
7542 [(set (match_operand:QI 0 "register_operand" "=a")
7543 (div:QI (match_operand:HI 1 "register_operand" "0")
7544 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7545 (clobber (reg:CC 17))]
7546 "TARGET_QIMODE_MATH"
7548 [(set_attr "type" "idiv")
7549 (set_attr "mode" "QI")
7550 (set_attr "ppro_uops" "few")])
7552 (define_insn "udivqi3"
7553 [(set (match_operand:QI 0 "register_operand" "=a")
7554 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7555 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7556 (clobber (reg:CC 17))]
7557 "TARGET_QIMODE_MATH"
7559 [(set_attr "type" "idiv")
7560 (set_attr "mode" "QI")
7561 (set_attr "ppro_uops" "few")])
7563 ;; The patterns that match these are at the end of this file.
7565 (define_expand "divxf3"
7566 [(set (match_operand:XF 0 "register_operand" "")
7567 (div:XF (match_operand:XF 1 "register_operand" "")
7568 (match_operand:XF 2 "register_operand" "")))]
7569 "TARGET_80387 && !TARGET_64BIT"
7572 (define_expand "divtf3"
7573 [(set (match_operand:TF 0 "register_operand" "")
7574 (div:TF (match_operand:TF 1 "register_operand" "")
7575 (match_operand:TF 2 "register_operand" "")))]
7579 (define_expand "divdf3"
7580 [(set (match_operand:DF 0 "register_operand" "")
7581 (div:DF (match_operand:DF 1 "register_operand" "")
7582 (match_operand:DF 2 "nonimmediate_operand" "")))]
7583 "TARGET_80387 || TARGET_SSE2"
7586 (define_expand "divsf3"
7587 [(set (match_operand:SF 0 "register_operand" "")
7588 (div:SF (match_operand:SF 1 "register_operand" "")
7589 (match_operand:SF 2 "nonimmediate_operand" "")))]
7590 "TARGET_80387 || TARGET_SSE"
7593 ;; Remainder instructions.
7595 (define_expand "divmoddi4"
7596 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7597 (div:DI (match_operand:DI 1 "register_operand" "")
7598 (match_operand:DI 2 "nonimmediate_operand" "")))
7599 (set (match_operand:DI 3 "register_operand" "")
7600 (mod:DI (match_dup 1) (match_dup 2)))
7601 (clobber (reg:CC 17))])]
7605 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7606 ;; Penalize eax case sligthly because it results in worse scheduling
7608 (define_insn "*divmoddi4_nocltd_rex64"
7609 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7610 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7611 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7612 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7613 (mod:DI (match_dup 2) (match_dup 3)))
7614 (clobber (reg:CC 17))]
7615 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7617 [(set_attr "type" "multi")])
7619 (define_insn "*divmoddi4_cltd_rex64"
7620 [(set (match_operand:DI 0 "register_operand" "=a")
7621 (div:DI (match_operand:DI 2 "register_operand" "a")
7622 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7623 (set (match_operand:DI 1 "register_operand" "=&d")
7624 (mod:DI (match_dup 2) (match_dup 3)))
7625 (clobber (reg:CC 17))]
7626 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7628 [(set_attr "type" "multi")])
7630 (define_insn "*divmoddi_noext_rex64"
7631 [(set (match_operand:DI 0 "register_operand" "=a")
7632 (div:DI (match_operand:DI 1 "register_operand" "0")
7633 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7634 (set (match_operand:DI 3 "register_operand" "=d")
7635 (mod:DI (match_dup 1) (match_dup 2)))
7636 (use (match_operand:DI 4 "register_operand" "3"))
7637 (clobber (reg:CC 17))]
7640 [(set_attr "type" "idiv")
7641 (set_attr "mode" "DI")
7642 (set_attr "ppro_uops" "few")])
7645 [(set (match_operand:DI 0 "register_operand" "")
7646 (div:DI (match_operand:DI 1 "register_operand" "")
7647 (match_operand:DI 2 "nonimmediate_operand" "")))
7648 (set (match_operand:DI 3 "register_operand" "")
7649 (mod:DI (match_dup 1) (match_dup 2)))
7650 (clobber (reg:CC 17))]
7651 "TARGET_64BIT && reload_completed"
7652 [(parallel [(set (match_dup 3)
7653 (ashiftrt:DI (match_dup 4) (const_int 63)))
7654 (clobber (reg:CC 17))])
7655 (parallel [(set (match_dup 0)
7656 (div:DI (reg:DI 0) (match_dup 2)))
7658 (mod:DI (reg:DI 0) (match_dup 2)))
7660 (clobber (reg:CC 17))])]
7663 /* Avoid use of cltd in favour of a mov+shift. */
7664 if (!TARGET_USE_CLTD && !optimize_size)
7666 if (true_regnum (operands[1]))
7667 emit_move_insn (operands[0], operands[1]);
7669 emit_move_insn (operands[3], operands[1]);
7670 operands[4] = operands[3];
7674 if (true_regnum (operands[1]))
7676 operands[4] = operands[1];
7681 (define_expand "divmodsi4"
7682 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7683 (div:SI (match_operand:SI 1 "register_operand" "")
7684 (match_operand:SI 2 "nonimmediate_operand" "")))
7685 (set (match_operand:SI 3 "register_operand" "")
7686 (mod:SI (match_dup 1) (match_dup 2)))
7687 (clobber (reg:CC 17))])]
7691 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7692 ;; Penalize eax case sligthly because it results in worse scheduling
7694 (define_insn "*divmodsi4_nocltd"
7695 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7696 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7697 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7698 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7699 (mod:SI (match_dup 2) (match_dup 3)))
7700 (clobber (reg:CC 17))]
7701 "!optimize_size && !TARGET_USE_CLTD"
7703 [(set_attr "type" "multi")])
7705 (define_insn "*divmodsi4_cltd"
7706 [(set (match_operand:SI 0 "register_operand" "=a")
7707 (div:SI (match_operand:SI 2 "register_operand" "a")
7708 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7709 (set (match_operand:SI 1 "register_operand" "=&d")
7710 (mod:SI (match_dup 2) (match_dup 3)))
7711 (clobber (reg:CC 17))]
7712 "optimize_size || TARGET_USE_CLTD"
7714 [(set_attr "type" "multi")])
7716 (define_insn "*divmodsi_noext"
7717 [(set (match_operand:SI 0 "register_operand" "=a")
7718 (div:SI (match_operand:SI 1 "register_operand" "0")
7719 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7720 (set (match_operand:SI 3 "register_operand" "=d")
7721 (mod:SI (match_dup 1) (match_dup 2)))
7722 (use (match_operand:SI 4 "register_operand" "3"))
7723 (clobber (reg:CC 17))]
7726 [(set_attr "type" "idiv")
7727 (set_attr "mode" "SI")
7728 (set_attr "ppro_uops" "few")])
7731 [(set (match_operand:SI 0 "register_operand" "")
7732 (div:SI (match_operand:SI 1 "register_operand" "")
7733 (match_operand:SI 2 "nonimmediate_operand" "")))
7734 (set (match_operand:SI 3 "register_operand" "")
7735 (mod:SI (match_dup 1) (match_dup 2)))
7736 (clobber (reg:CC 17))]
7738 [(parallel [(set (match_dup 3)
7739 (ashiftrt:SI (match_dup 4) (const_int 31)))
7740 (clobber (reg:CC 17))])
7741 (parallel [(set (match_dup 0)
7742 (div:SI (reg:SI 0) (match_dup 2)))
7744 (mod:SI (reg:SI 0) (match_dup 2)))
7746 (clobber (reg:CC 17))])]
7749 /* Avoid use of cltd in favour of a mov+shift. */
7750 if (!TARGET_USE_CLTD && !optimize_size)
7752 if (true_regnum (operands[1]))
7753 emit_move_insn (operands[0], operands[1]);
7755 emit_move_insn (operands[3], operands[1]);
7756 operands[4] = operands[3];
7760 if (true_regnum (operands[1]))
7762 operands[4] = operands[1];
7766 (define_insn "divmodhi4"
7767 [(set (match_operand:HI 0 "register_operand" "=a")
7768 (div:HI (match_operand:HI 1 "register_operand" "0")
7769 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7770 (set (match_operand:HI 3 "register_operand" "=&d")
7771 (mod:HI (match_dup 1) (match_dup 2)))
7772 (clobber (reg:CC 17))]
7773 "TARGET_HIMODE_MATH"
7774 "cwtd\;idiv{w}\\t%2"
7775 [(set_attr "type" "multi")
7776 (set_attr "length_immediate" "0")
7777 (set_attr "mode" "SI")])
7779 (define_insn "udivmoddi4"
7780 [(set (match_operand:DI 0 "register_operand" "=a")
7781 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7782 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7783 (set (match_operand:DI 3 "register_operand" "=&d")
7784 (umod:DI (match_dup 1) (match_dup 2)))
7785 (clobber (reg:CC 17))]
7787 "xor{q}\\t%3, %3\;div{q}\\t%2"
7788 [(set_attr "type" "multi")
7789 (set_attr "length_immediate" "0")
7790 (set_attr "mode" "DI")])
7792 (define_insn "*udivmoddi4_noext"
7793 [(set (match_operand:DI 0 "register_operand" "=a")
7794 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7795 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7796 (set (match_operand:DI 3 "register_operand" "=d")
7797 (umod:DI (match_dup 1) (match_dup 2)))
7799 (clobber (reg:CC 17))]
7802 [(set_attr "type" "idiv")
7803 (set_attr "ppro_uops" "few")
7804 (set_attr "mode" "DI")])
7807 [(set (match_operand:DI 0 "register_operand" "")
7808 (udiv:DI (match_operand:DI 1 "register_operand" "")
7809 (match_operand:DI 2 "nonimmediate_operand" "")))
7810 (set (match_operand:DI 3 "register_operand" "")
7811 (umod:DI (match_dup 1) (match_dup 2)))
7812 (clobber (reg:CC 17))]
7813 "reload_completed && TARGET_64BIT"
7814 [(set (match_dup 3) (const_int 0))
7815 (parallel [(set (match_dup 0)
7816 (udiv:DI (match_dup 1) (match_dup 2)))
7818 (umod:DI (match_dup 1) (match_dup 2)))
7820 (clobber (reg:CC 17))])]
7823 (define_insn "udivmodsi4"
7824 [(set (match_operand:SI 0 "register_operand" "=a")
7825 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7826 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7827 (set (match_operand:SI 3 "register_operand" "=&d")
7828 (umod:SI (match_dup 1) (match_dup 2)))
7829 (clobber (reg:CC 17))]
7831 "xor{l}\\t%3, %3\;div{l}\\t%2"
7832 [(set_attr "type" "multi")
7833 (set_attr "length_immediate" "0")
7834 (set_attr "mode" "SI")])
7836 (define_insn "*udivmodsi4_noext"
7837 [(set (match_operand:SI 0 "register_operand" "=a")
7838 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7839 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7840 (set (match_operand:SI 3 "register_operand" "=d")
7841 (umod:SI (match_dup 1) (match_dup 2)))
7843 (clobber (reg:CC 17))]
7846 [(set_attr "type" "idiv")
7847 (set_attr "ppro_uops" "few")
7848 (set_attr "mode" "SI")])
7851 [(set (match_operand:SI 0 "register_operand" "")
7852 (udiv:SI (match_operand:SI 1 "register_operand" "")
7853 (match_operand:SI 2 "nonimmediate_operand" "")))
7854 (set (match_operand:SI 3 "register_operand" "")
7855 (umod:SI (match_dup 1) (match_dup 2)))
7856 (clobber (reg:CC 17))]
7858 [(set (match_dup 3) (const_int 0))
7859 (parallel [(set (match_dup 0)
7860 (udiv:SI (match_dup 1) (match_dup 2)))
7862 (umod:SI (match_dup 1) (match_dup 2)))
7864 (clobber (reg:CC 17))])]
7867 (define_expand "udivmodhi4"
7868 [(set (match_dup 4) (const_int 0))
7869 (parallel [(set (match_operand:HI 0 "register_operand" "")
7870 (udiv:HI (match_operand:HI 1 "register_operand" "")
7871 (match_operand:HI 2 "nonimmediate_operand" "")))
7872 (set (match_operand:HI 3 "register_operand" "")
7873 (umod:HI (match_dup 1) (match_dup 2)))
7875 (clobber (reg:CC 17))])]
7876 "TARGET_HIMODE_MATH"
7877 "operands[4] = gen_reg_rtx (HImode);")
7879 (define_insn "*udivmodhi_noext"
7880 [(set (match_operand:HI 0 "register_operand" "=a")
7881 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7882 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7883 (set (match_operand:HI 3 "register_operand" "=d")
7884 (umod:HI (match_dup 1) (match_dup 2)))
7885 (use (match_operand:HI 4 "register_operand" "3"))
7886 (clobber (reg:CC 17))]
7889 [(set_attr "type" "idiv")
7890 (set_attr "mode" "HI")
7891 (set_attr "ppro_uops" "few")])
7893 ;; We can not use div/idiv for double division, because it causes
7894 ;; "division by zero" on the overflow and that's not what we expect
7895 ;; from truncate. Because true (non truncating) double division is
7896 ;; never generated, we can't create this insn anyway.
7899 ; [(set (match_operand:SI 0 "register_operand" "=a")
7901 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7903 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7904 ; (set (match_operand:SI 3 "register_operand" "=d")
7906 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7907 ; (clobber (reg:CC 17))]
7909 ; "div{l}\\t{%2, %0|%0, %2}"
7910 ; [(set_attr "type" "idiv")
7911 ; (set_attr "ppro_uops" "few")])
7913 ;;- Logical AND instructions
7915 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7916 ;; Note that this excludes ah.
7918 (define_insn "*testdi_1_rex64"
7921 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7922 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7924 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7926 test{l}\\t{%k1, %k0|%k0, %k1}
7927 test{l}\\t{%k1, %k0|%k0, %k1}
7928 test{q}\\t{%1, %0|%0, %1}
7929 test{q}\\t{%1, %0|%0, %1}
7930 test{q}\\t{%1, %0|%0, %1}"
7931 [(set_attr "type" "test")
7932 (set_attr "modrm" "0,1,0,1,1")
7933 (set_attr "mode" "SI,SI,DI,DI,DI")
7934 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7936 (define_insn "testsi_1"
7939 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7940 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7942 "ix86_match_ccmode (insn, CCNOmode)"
7943 "test{l}\\t{%1, %0|%0, %1}"
7944 [(set_attr "type" "test")
7945 (set_attr "modrm" "0,1,1")
7946 (set_attr "mode" "SI")
7947 (set_attr "pent_pair" "uv,np,uv")])
7949 (define_expand "testsi_ccno_1"
7952 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7953 (match_operand:SI 1 "nonmemory_operand" ""))
7958 (define_insn "*testhi_1"
7960 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7961 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7963 "ix86_match_ccmode (insn, CCNOmode)"
7964 "test{w}\\t{%1, %0|%0, %1}"
7965 [(set_attr "type" "test")
7966 (set_attr "modrm" "0,1,1")
7967 (set_attr "mode" "HI")
7968 (set_attr "pent_pair" "uv,np,uv")])
7970 (define_expand "testqi_ccz_1"
7972 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7973 (match_operand:QI 1 "nonmemory_operand" ""))
7978 (define_insn "*testqi_1"
7980 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7981 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7983 "ix86_match_ccmode (insn, CCNOmode)"
7986 if (which_alternative == 3)
7988 if (GET_CODE (operands[1]) == CONST_INT
7989 && (INTVAL (operands[1]) & 0xffffff00))
7990 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7991 return \"test{l}\\t{%1, %k0|%k0, %1}\";
7993 return \"test{b}\\t{%1, %0|%0, %1}\";
7995 [(set_attr "type" "test")
7996 (set_attr "modrm" "0,1,1,1")
7997 (set_attr "mode" "QI,QI,QI,SI")
7998 (set_attr "pent_pair" "uv,np,uv,np")])
8000 (define_expand "testqi_ext_ccno_0"
8005 (match_operand 0 "ext_register_operand" "")
8008 (match_operand 1 "const_int_operand" ""))
8013 (define_insn "*testqi_ext_0"
8018 (match_operand 0 "ext_register_operand" "Q")
8021 (match_operand 1 "const_int_operand" "n"))
8023 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
8024 && ix86_match_ccmode (insn, CCNOmode)"
8025 "test{b}\\t{%1, %h0|%h0, %1}"
8026 [(set_attr "type" "test")
8027 (set_attr "mode" "QI")
8028 (set_attr "length_immediate" "1")
8029 (set_attr "pent_pair" "np")])
8031 (define_insn "*testqi_ext_1"
8036 (match_operand 0 "ext_register_operand" "Q")
8040 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
8042 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8043 "test{b}\\t{%1, %h0|%h0, %1}"
8044 [(set_attr "type" "test")
8045 (set_attr "mode" "QI")])
8047 (define_insn "*testqi_ext_1_rex64"
8052 (match_operand 0 "ext_register_operand" "Q")
8056 (match_operand:QI 1 "ext_register_operand" "Q")))
8058 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8059 "test{b}\\t{%1, %h0|%h0, %1}"
8060 [(set_attr "type" "test")
8061 (set_attr "mode" "QI")])
8063 (define_insn "*testqi_ext_2"
8068 (match_operand 0 "ext_register_operand" "Q")
8072 (match_operand 1 "ext_register_operand" "Q")
8076 "ix86_match_ccmode (insn, CCNOmode)"
8077 "test{b}\\t{%h1, %h0|%h0, %h1}"
8078 [(set_attr "type" "test")
8079 (set_attr "mode" "QI")])
8081 ;; Combine likes to form bit extractions for some tests. Humor it.
8082 (define_insn "*testqi_ext_3"
8084 (compare (zero_extract:SI
8085 (match_operand 0 "nonimmediate_operand" "rm")
8086 (match_operand:SI 1 "const_int_operand" "")
8087 (match_operand:SI 2 "const_int_operand" ""))
8089 "ix86_match_ccmode (insn, CCNOmode)
8090 && (GET_MODE (operands[0]) == SImode
8091 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8092 || GET_MODE (operands[0]) == HImode
8093 || GET_MODE (operands[0]) == QImode)"
8096 (define_insn "*testqi_ext_3_rex64"
8098 (compare (zero_extract:DI
8099 (match_operand 0 "nonimmediate_operand" "rm")
8100 (match_operand:DI 1 "const_int_operand" "")
8101 (match_operand:DI 2 "const_int_operand" ""))
8103 "ix86_match_ccmode (insn, CCNOmode)
8105 && (GET_MODE (operands[0]) == SImode
8106 || GET_MODE (operands[0]) == DImode
8107 || GET_MODE (operands[0]) == HImode
8108 || GET_MODE (operands[0]) == QImode)"
8113 (compare (zero_extract
8114 (match_operand 0 "nonimmediate_operand" "rm")
8115 (match_operand 1 "const_int_operand" "")
8116 (match_operand 2 "const_int_operand" ""))
8118 "ix86_match_ccmode (insn, CCNOmode)"
8119 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8122 HOST_WIDE_INT len = INTVAL (operands[1]);
8123 HOST_WIDE_INT pos = INTVAL (operands[2]);
8125 enum machine_mode mode;
8127 mode = GET_MODE (operands[0]);
8128 if (GET_CODE (operands[0]) == MEM)
8130 /* ??? Combine likes to put non-volatile mem extractions in QImode
8131 no matter the size of the test. So find a mode that works. */
8132 if (! MEM_VOLATILE_P (operands[0]))
8134 mode = smallest_mode_for_size (pos + len, MODE_INT);
8135 operands[0] = change_address (operands[0], mode, NULL_RTX);
8138 else if (mode == HImode && pos + len <= 8)
8140 /* Small HImode tests can be converted to QImode. */
8142 operands[0] = gen_lowpart (QImode, operands[0]);
8145 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8146 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8148 operands[3] = gen_rtx_AND (mode, operands[0],
8149 GEN_INT (trunc_int_for_mode (mask, mode)));
8152 ;; %%% This used to optimize known byte-wide and operations to memory,
8153 ;; and sometimes to QImode registers. If this is considered useful,
8154 ;; it should be done with splitters.
8156 (define_expand "anddi3"
8157 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8158 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8159 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8160 (clobber (reg:CC 17))]
8162 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8164 (define_insn "*anddi_1_rex64"
8165 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8166 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8167 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8168 (clobber (reg:CC 17))]
8169 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8172 switch (get_attr_type (insn))
8176 enum machine_mode mode;
8178 if (GET_CODE (operands[2]) != CONST_INT)
8180 if (INTVAL (operands[2]) == 0xff)
8182 else if (INTVAL (operands[2]) == 0xffff)
8187 operands[1] = gen_lowpart (mode, operands[1]);
8189 return \"movz{bq|x}\\t{%1,%0|%0, %1}\";
8191 return \"movz{wq|x}\\t{%1,%0|%0, %1}\";
8195 if (! rtx_equal_p (operands[0], operands[1]))
8197 if (get_attr_mode (insn) == MODE_SI)
8198 return \"and{l}\\t{%k2, %k0|%k0, %k2}\";
8200 return \"and{q}\\t{%2, %0|%0, %2}\";
8203 [(set_attr "type" "alu,alu,alu,imovx")
8204 (set_attr "length_immediate" "*,*,*,0")
8205 (set_attr "mode" "SI,DI,DI,DI")])
8207 (define_insn "*anddi_2"
8209 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8210 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8212 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8213 (and:DI (match_dup 1) (match_dup 2)))]
8214 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8215 && ix86_binary_operator_ok (AND, DImode, operands)"
8217 and{l}\\t{%k2, %k0|%k0, %k2}
8218 and{q}\\t{%2, %0|%0, %2}
8219 and{q}\\t{%2, %0|%0, %2}"
8220 [(set_attr "type" "alu")
8221 (set_attr "mode" "SI,DI,DI")])
8223 (define_expand "andsi3"
8224 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8225 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8226 (match_operand:SI 2 "general_operand" "")))
8227 (clobber (reg:CC 17))]
8229 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8231 (define_insn "*andsi_1"
8232 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8233 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8234 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8235 (clobber (reg:CC 17))]
8236 "ix86_binary_operator_ok (AND, SImode, operands)"
8239 switch (get_attr_type (insn))
8243 enum machine_mode mode;
8245 if (GET_CODE (operands[2]) != CONST_INT)
8247 if (INTVAL (operands[2]) == 0xff)
8249 else if (INTVAL (operands[2]) == 0xffff)
8254 operands[1] = gen_lowpart (mode, operands[1]);
8256 return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
8258 return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
8262 if (! rtx_equal_p (operands[0], operands[1]))
8264 return \"and{l}\\t{%2, %0|%0, %2}\";
8267 [(set_attr "type" "alu,alu,imovx")
8268 (set_attr "length_immediate" "*,*,0")
8269 (set_attr "mode" "SI")])
8272 [(set (match_operand 0 "register_operand" "")
8274 (const_int -65536)))
8275 (clobber (reg:CC 17))]
8277 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8278 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
8279 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8280 "operands[1] = gen_lowpart (HImode, operands[0]);")
8283 [(set (match_operand 0 "q_regs_operand" "")
8286 (clobber (reg:CC 17))]
8287 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
8288 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8289 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
8290 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8291 "operands[1] = gen_lowpart (QImode, operands[0]);")
8294 [(set (match_operand 0 "register_operand" "")
8296 (const_int -65281)))
8297 (clobber (reg:CC 17))]
8298 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
8299 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8300 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
8301 && (! reload_completed || ANY_QI_REG_P (operands[0]))"
8302 [(parallel [(set (zero_extract:SI (match_dup 0)
8306 (zero_extract:SI (match_dup 0)
8309 (zero_extract:SI (match_dup 0)
8312 (clobber (reg:CC 17))])]
8313 "operands[0] = gen_lowpart (SImode, operands[0]);")
8315 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8316 (define_insn "*andsi_1_zext"
8317 [(set (match_operand:DI 0 "register_operand" "=r")
8319 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8320 (match_operand:SI 2 "general_operand" "rim"))))
8321 (clobber (reg:CC 17))]
8322 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8323 "and{l}\\t{%2, %k0|%k0, %2}"
8324 [(set_attr "type" "alu")
8325 (set_attr "mode" "SI")])
8327 (define_insn "*andsi_2"
8329 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8330 (match_operand:SI 2 "general_operand" "rim,ri"))
8332 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8333 (and:SI (match_dup 1) (match_dup 2)))]
8334 "ix86_match_ccmode (insn, CCNOmode)
8335 && ix86_binary_operator_ok (AND, SImode, operands)"
8336 "and{l}\\t{%2, %0|%0, %2}"
8337 [(set_attr "type" "alu")
8338 (set_attr "mode" "SI")])
8340 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8341 (define_insn "*andsi_2_zext"
8343 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8344 (match_operand:SI 2 "general_operand" "rim"))
8346 (set (match_operand:DI 0 "register_operand" "=r")
8347 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8348 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8349 && ix86_binary_operator_ok (AND, SImode, operands)"
8350 "and{l}\\t{%2, %k0|%k0, %2}"
8351 [(set_attr "type" "alu")
8352 (set_attr "mode" "SI")])
8354 (define_expand "andhi3"
8355 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8356 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8357 (match_operand:HI 2 "general_operand" "")))
8358 (clobber (reg:CC 17))]
8359 "TARGET_HIMODE_MATH"
8360 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8362 (define_insn "*andhi_1"
8363 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8364 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8365 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8366 (clobber (reg:CC 17))]
8367 "ix86_binary_operator_ok (AND, HImode, operands)"
8370 switch (get_attr_type (insn))
8373 if (GET_CODE (operands[2]) != CONST_INT)
8375 if (INTVAL (operands[2]) == 0xff)
8376 return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
8380 if (! rtx_equal_p (operands[0], operands[1]))
8383 return \"and{w}\\t{%2, %0|%0, %2}\";
8386 [(set_attr "type" "alu,alu,imovx")
8387 (set_attr "length_immediate" "*,*,0")
8388 (set_attr "mode" "HI,HI,SI")])
8390 (define_insn "*andhi_2"
8392 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8393 (match_operand:HI 2 "general_operand" "rim,ri"))
8395 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8396 (and:HI (match_dup 1) (match_dup 2)))]
8397 "ix86_match_ccmode (insn, CCNOmode)
8398 && ix86_binary_operator_ok (AND, HImode, operands)"
8399 "and{w}\\t{%2, %0|%0, %2}"
8400 [(set_attr "type" "alu")
8401 (set_attr "mode" "HI")])
8403 (define_expand "andqi3"
8404 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8405 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8406 (match_operand:QI 2 "general_operand" "")))
8407 (clobber (reg:CC 17))]
8408 "TARGET_QIMODE_MATH"
8409 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8411 ;; %%% Potential partial reg stall on alternative 2. What to do?
8412 (define_insn "*andqi_1"
8413 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8414 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8415 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8416 (clobber (reg:CC 17))]
8417 "ix86_binary_operator_ok (AND, QImode, operands)"
8419 and{b}\\t{%2, %0|%0, %2}
8420 and{b}\\t{%2, %0|%0, %2}
8421 and{l}\\t{%k2, %k0|%k0, %k2}"
8422 [(set_attr "type" "alu")
8423 (set_attr "mode" "QI,QI,SI")])
8425 (define_insn "*andqi_1_slp"
8426 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8427 (and:QI (match_dup 0)
8428 (match_operand:QI 1 "general_operand" "qi,qmi")))
8429 (clobber (reg:CC 17))]
8431 "and{b}\\t{%1, %0|%0, %1}"
8432 [(set_attr "type" "alu1")
8433 (set_attr "mode" "QI")])
8435 (define_insn "*andqi_2"
8438 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8439 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8441 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8442 (and:QI (match_dup 1) (match_dup 2)))]
8443 "ix86_match_ccmode (insn, CCNOmode)
8444 && ix86_binary_operator_ok (AND, QImode, operands)"
8447 if (which_alternative == 2)
8449 if (GET_CODE (operands[2]) == CONST_INT
8450 && (INTVAL (operands[2]) & 0xffffff00))
8451 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8452 return \"and{l}\\t{%2, %k0|%k0, %2}\";
8454 return \"and{b}\\t{%2, %0|%0, %2}\";
8456 [(set_attr "type" "alu")
8457 (set_attr "mode" "QI,QI,SI")])
8459 (define_insn "*andqi_2_slp"
8462 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8463 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8465 (set (strict_low_part (match_dup 0))
8466 (and:QI (match_dup 0) (match_dup 1)))]
8467 "ix86_match_ccmode (insn, CCNOmode)"
8468 "and{b}\\t{%1, %0|%0, %1}"
8469 [(set_attr "type" "alu1")
8470 (set_attr "mode" "QI")])
8472 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8473 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8474 ;; for a QImode operand, which of course failed.
8476 (define_insn "andqi_ext_0"
8477 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8482 (match_operand 1 "ext_register_operand" "0")
8485 (match_operand 2 "const_int_operand" "n")))
8486 (clobber (reg:CC 17))]
8487 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8488 "and{b}\\t{%2, %h0|%h0, %2}"
8489 [(set_attr "type" "alu")
8490 (set_attr "length_immediate" "1")
8491 (set_attr "mode" "QI")])
8493 ;; Generated by peephole translating test to and. This shows up
8494 ;; often in fp comparisons.
8496 (define_insn "*andqi_ext_0_cc"
8501 (match_operand 1 "ext_register_operand" "0")
8504 (match_operand 2 "const_int_operand" "n"))
8506 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8515 "ix86_match_ccmode (insn, CCNOmode)
8516 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8517 "and{b}\\t{%2, %h0|%h0, %2}"
8518 [(set_attr "type" "alu")
8519 (set_attr "length_immediate" "1")
8520 (set_attr "mode" "QI")])
8522 (define_insn "*andqi_ext_1"
8523 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8528 (match_operand 1 "ext_register_operand" "0")
8532 (match_operand:QI 2 "general_operand" "Qm"))))
8533 (clobber (reg:CC 17))]
8535 "and{b}\\t{%2, %h0|%h0, %2}"
8536 [(set_attr "type" "alu")
8537 (set_attr "length_immediate" "0")
8538 (set_attr "mode" "QI")])
8540 (define_insn "*andqi_ext_1_rex64"
8541 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8546 (match_operand 1 "ext_register_operand" "0")
8550 (match_operand:QI 2 "ext_register_operand" "Q"))))
8551 (clobber (reg:CC 17))]
8553 "and{b}\\t{%2, %h0|%h0, %2}"
8554 [(set_attr "type" "alu")
8555 (set_attr "length_immediate" "0")
8556 (set_attr "mode" "QI")])
8558 (define_insn "*andqi_ext_2"
8559 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8564 (match_operand 1 "ext_register_operand" "%0")
8568 (match_operand 2 "ext_register_operand" "Q")
8571 (clobber (reg:CC 17))]
8573 "and{b}\\t{%h2, %h0|%h0, %h2}"
8574 [(set_attr "type" "alu")
8575 (set_attr "length_immediate" "0")
8576 (set_attr "mode" "QI")])
8578 ;; Logical inclusive OR instructions
8580 ;; %%% This used to optimize known byte-wide and operations to memory.
8581 ;; If this is considered useful, it should be done with splitters.
8583 (define_expand "iordi3"
8584 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8585 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8586 (match_operand:DI 2 "x86_64_general_operand" "")))
8587 (clobber (reg:CC 17))]
8589 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8591 (define_insn "*iordi_1_rex64"
8592 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8593 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8594 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8595 (clobber (reg:CC 17))]
8597 && ix86_binary_operator_ok (IOR, DImode, operands)"
8598 "or{q}\\t{%2, %0|%0, %2}"
8599 [(set_attr "type" "alu")
8600 (set_attr "mode" "DI")])
8602 (define_insn "*iordi_2_rex64"
8604 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8605 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8607 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8608 (ior:DI (match_dup 1) (match_dup 2)))]
8610 && ix86_match_ccmode (insn, CCNOmode)
8611 && ix86_binary_operator_ok (IOR, DImode, operands)"
8612 "or{q}\\t{%2, %0|%0, %2}"
8613 [(set_attr "type" "alu")
8614 (set_attr "mode" "DI")])
8616 (define_insn "*iordi_3_rex64"
8618 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8619 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8621 (clobber (match_scratch:DI 0 "=r"))]
8623 && ix86_match_ccmode (insn, CCNOmode)
8624 && ix86_binary_operator_ok (IOR, DImode, operands)"
8625 "or{q}\\t{%2, %0|%0, %2}"
8626 [(set_attr "type" "alu")
8627 (set_attr "mode" "DI")])
8630 (define_expand "iorsi3"
8631 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8632 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8633 (match_operand:SI 2 "general_operand" "")))
8634 (clobber (reg:CC 17))]
8636 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8638 (define_insn "*iorsi_1"
8639 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8640 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8641 (match_operand:SI 2 "general_operand" "ri,rmi")))
8642 (clobber (reg:CC 17))]
8643 "ix86_binary_operator_ok (IOR, SImode, operands)"
8644 "or{l}\\t{%2, %0|%0, %2}"
8645 [(set_attr "type" "alu")
8646 (set_attr "mode" "SI")])
8648 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8649 (define_insn "*iorsi_1_zext"
8650 [(set (match_operand:DI 0 "register_operand" "=rm")
8652 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8653 (match_operand:SI 2 "general_operand" "rim"))))
8654 (clobber (reg:CC 17))]
8655 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8656 "or{l}\\t{%2, %k0|%k0, %2}"
8657 [(set_attr "type" "alu")
8658 (set_attr "mode" "SI")])
8660 (define_insn "*iorsi_1_zext_imm"
8661 [(set (match_operand:DI 0 "register_operand" "=rm")
8662 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8663 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8664 (clobber (reg:CC 17))]
8666 "or{l}\\t{%2, %k0|%k0, %2}"
8667 [(set_attr "type" "alu")
8668 (set_attr "mode" "SI")])
8670 (define_insn "*iorsi_2"
8672 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8673 (match_operand:SI 2 "general_operand" "rim,ri"))
8675 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8676 (ior:SI (match_dup 1) (match_dup 2)))]
8677 "ix86_match_ccmode (insn, CCNOmode)
8678 && ix86_binary_operator_ok (IOR, SImode, operands)"
8679 "or{l}\\t{%2, %0|%0, %2}"
8680 [(set_attr "type" "alu")
8681 (set_attr "mode" "SI")])
8683 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8684 ;; ??? Special case for immediate operand is missing - it is tricky.
8685 (define_insn "*iorsi_2_zext"
8687 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8688 (match_operand:SI 2 "general_operand" "rim"))
8690 (set (match_operand:DI 0 "register_operand" "=r")
8691 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8692 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8693 && ix86_binary_operator_ok (IOR, SImode, operands)"
8694 "or{l}\\t{%2, %k0|%k0, %2}"
8695 [(set_attr "type" "alu")
8696 (set_attr "mode" "SI")])
8698 (define_insn "*iorsi_2_zext_imm"
8700 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8701 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8703 (set (match_operand:DI 0 "register_operand" "=r")
8704 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8705 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8706 && ix86_binary_operator_ok (IOR, SImode, operands)"
8707 "or{l}\\t{%2, %k0|%k0, %2}"
8708 [(set_attr "type" "alu")
8709 (set_attr "mode" "SI")])
8711 (define_insn "*iorsi_3"
8713 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8714 (match_operand:SI 2 "general_operand" "rim"))
8716 (clobber (match_scratch:SI 0 "=r"))]
8717 "ix86_match_ccmode (insn, CCNOmode)
8718 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8719 "or{l}\\t{%2, %0|%0, %2}"
8720 [(set_attr "type" "alu")
8721 (set_attr "mode" "SI")])
8723 (define_expand "iorhi3"
8724 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8725 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8726 (match_operand:HI 2 "general_operand" "")))
8727 (clobber (reg:CC 17))]
8728 "TARGET_HIMODE_MATH"
8729 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8731 (define_insn "*iorhi_1"
8732 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8733 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8734 (match_operand:HI 2 "general_operand" "rmi,ri")))
8735 (clobber (reg:CC 17))]
8736 "ix86_binary_operator_ok (IOR, HImode, operands)"
8737 "or{w}\\t{%2, %0|%0, %2}"
8738 [(set_attr "type" "alu")
8739 (set_attr "mode" "HI")])
8741 (define_insn "*iorhi_2"
8743 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8744 (match_operand:HI 2 "general_operand" "rim,ri"))
8746 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8747 (ior:HI (match_dup 1) (match_dup 2)))]
8748 "ix86_match_ccmode (insn, CCNOmode)
8749 && ix86_binary_operator_ok (IOR, HImode, operands)"
8750 "or{w}\\t{%2, %0|%0, %2}"
8751 [(set_attr "type" "alu")
8752 (set_attr "mode" "HI")])
8754 (define_insn "*iorhi_3"
8756 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8757 (match_operand:HI 2 "general_operand" "rim"))
8759 (clobber (match_scratch:HI 0 "=r"))]
8760 "ix86_match_ccmode (insn, CCNOmode)
8761 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8762 "or{w}\\t{%2, %0|%0, %2}"
8763 [(set_attr "type" "alu")
8764 (set_attr "mode" "HI")])
8766 (define_expand "iorqi3"
8767 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8768 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8769 (match_operand:QI 2 "general_operand" "")))
8770 (clobber (reg:CC 17))]
8771 "TARGET_QIMODE_MATH"
8772 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8774 ;; %%% Potential partial reg stall on alternative 2. What to do?
8775 (define_insn "*iorqi_1"
8776 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8777 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8778 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8779 (clobber (reg:CC 17))]
8780 "ix86_binary_operator_ok (IOR, QImode, operands)"
8782 or{b}\\t{%2, %0|%0, %2}
8783 or{b}\\t{%2, %0|%0, %2}
8784 or{l}\\t{%k2, %k0|%k0, %k2}"
8785 [(set_attr "type" "alu")
8786 (set_attr "mode" "QI,QI,SI")])
8788 (define_insn "*iorqi_1_slp"
8789 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8790 (ior:QI (match_dup 0)
8791 (match_operand:QI 1 "general_operand" "qmi,qi")))
8792 (clobber (reg:CC 17))]
8794 "or{b}\\t{%1, %0|%0, %1}"
8795 [(set_attr "type" "alu1")
8796 (set_attr "mode" "QI")])
8798 (define_insn "*iorqi_2"
8800 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8801 (match_operand:QI 2 "general_operand" "qim,qi"))
8803 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8804 (ior:QI (match_dup 1) (match_dup 2)))]
8805 "ix86_match_ccmode (insn, CCNOmode)
8806 && ix86_binary_operator_ok (IOR, QImode, operands)"
8807 "or{b}\\t{%2, %0|%0, %2}"
8808 [(set_attr "type" "alu")
8809 (set_attr "mode" "QI")])
8811 (define_insn "*iorqi_2_slp"
8813 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8814 (match_operand:QI 1 "general_operand" "qim,qi"))
8816 (set (strict_low_part (match_dup 0))
8817 (ior:QI (match_dup 0) (match_dup 1)))]
8818 "ix86_match_ccmode (insn, CCNOmode)"
8819 "or{b}\\t{%1, %0|%0, %1}"
8820 [(set_attr "type" "alu1")
8821 (set_attr "mode" "QI")])
8823 (define_insn "*iorqi_3"
8825 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8826 (match_operand:QI 2 "general_operand" "qim"))
8828 (clobber (match_scratch:QI 0 "=q"))]
8829 "ix86_match_ccmode (insn, CCNOmode)
8830 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8831 "or{b}\\t{%2, %0|%0, %2}"
8832 [(set_attr "type" "alu")
8833 (set_attr "mode" "QI")])
8836 ;; Logical XOR instructions
8838 ;; %%% This used to optimize known byte-wide and operations to memory.
8839 ;; If this is considered useful, it should be done with splitters.
8841 (define_expand "xordi3"
8842 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8843 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8844 (match_operand:DI 2 "x86_64_general_operand" "")))
8845 (clobber (reg:CC 17))]
8847 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8849 (define_insn "*xordi_1_rex64"
8850 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8851 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8852 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8853 (clobber (reg:CC 17))]
8855 && ix86_binary_operator_ok (XOR, DImode, operands)"
8857 xor{q}\\t{%2, %0|%0, %2}
8858 xor{q}\\t{%2, %0|%0, %2}"
8859 [(set_attr "type" "alu")
8860 (set_attr "mode" "DI,DI")])
8862 (define_insn "*xordi_2_rex64"
8864 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8865 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8867 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8868 (xor:DI (match_dup 1) (match_dup 2)))]
8870 && ix86_match_ccmode (insn, CCNOmode)
8871 && ix86_binary_operator_ok (XOR, DImode, operands)"
8873 xor{q}\\t{%2, %0|%0, %2}
8874 xor{q}\\t{%2, %0|%0, %2}"
8875 [(set_attr "type" "alu")
8876 (set_attr "mode" "DI,DI")])
8878 (define_insn "*xordi_3_rex64"
8880 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8881 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8883 (clobber (match_scratch:DI 0 "=r"))]
8885 && ix86_match_ccmode (insn, CCNOmode)
8886 && ix86_binary_operator_ok (XOR, DImode, operands)"
8887 "xor{q}\\t{%2, %0|%0, %2}"
8888 [(set_attr "type" "alu")
8889 (set_attr "mode" "DI")])
8891 (define_expand "xorsi3"
8892 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8893 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8894 (match_operand:SI 2 "general_operand" "")))
8895 (clobber (reg:CC 17))]
8897 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8899 (define_insn "*xorsi_1"
8900 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8901 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8902 (match_operand:SI 2 "general_operand" "ri,rm")))
8903 (clobber (reg:CC 17))]
8904 "ix86_binary_operator_ok (XOR, SImode, operands)"
8905 "xor{l}\\t{%2, %0|%0, %2}"
8906 [(set_attr "type" "alu")
8907 (set_attr "mode" "SI")])
8909 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8910 ;; Add speccase for immediates
8911 (define_insn "*xorsi_1_zext"
8912 [(set (match_operand:DI 0 "register_operand" "=r")
8914 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8915 (match_operand:SI 2 "general_operand" "rim"))))
8916 (clobber (reg:CC 17))]
8917 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8918 "xor{l}\\t{%2, %k0|%k0, %2}"
8919 [(set_attr "type" "alu")
8920 (set_attr "mode" "SI")])
8922 (define_insn "*xorsi_1_zext_imm"
8923 [(set (match_operand:DI 0 "register_operand" "=r")
8924 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8925 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8926 (clobber (reg:CC 17))]
8927 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8928 "xor{l}\\t{%2, %k0|%k0, %2}"
8929 [(set_attr "type" "alu")
8930 (set_attr "mode" "SI")])
8932 (define_insn "*xorsi_2"
8934 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8935 (match_operand:SI 2 "general_operand" "rim,ri"))
8937 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8938 (xor:SI (match_dup 1) (match_dup 2)))]
8939 "ix86_match_ccmode (insn, CCNOmode)
8940 && ix86_binary_operator_ok (XOR, SImode, operands)"
8941 "xor{l}\\t{%2, %0|%0, %2}"
8942 [(set_attr "type" "alu")
8943 (set_attr "mode" "SI")])
8945 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8946 ;; ??? Special case for immediate operand is missing - it is tricky.
8947 (define_insn "*xorsi_2_zext"
8949 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8950 (match_operand:SI 2 "general_operand" "rim"))
8952 (set (match_operand:DI 0 "register_operand" "=r")
8953 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8954 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8955 && ix86_binary_operator_ok (XOR, SImode, operands)"
8956 "xor{l}\\t{%2, %k0|%k0, %2}"
8957 [(set_attr "type" "alu")
8958 (set_attr "mode" "SI")])
8960 (define_insn "*xorsi_2_zext_imm"
8962 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8963 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8965 (set (match_operand:DI 0 "register_operand" "=r")
8966 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8967 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8968 && ix86_binary_operator_ok (XOR, SImode, operands)"
8969 "xor{l}\\t{%2, %k0|%k0, %2}"
8970 [(set_attr "type" "alu")
8971 (set_attr "mode" "SI")])
8973 (define_insn "*xorsi_3"
8975 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8976 (match_operand:SI 2 "general_operand" "rim"))
8978 (clobber (match_scratch:SI 0 "=r"))]
8979 "ix86_match_ccmode (insn, CCNOmode)
8980 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8981 "xor{l}\\t{%2, %0|%0, %2}"
8982 [(set_attr "type" "alu")
8983 (set_attr "mode" "SI")])
8985 (define_expand "xorhi3"
8986 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8987 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8988 (match_operand:HI 2 "general_operand" "")))
8989 (clobber (reg:CC 17))]
8990 "TARGET_HIMODE_MATH"
8991 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8993 (define_insn "*xorhi_1"
8994 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8995 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8996 (match_operand:HI 2 "general_operand" "rmi,ri")))
8997 (clobber (reg:CC 17))]
8998 "ix86_binary_operator_ok (XOR, HImode, operands)"
8999 "xor{w}\\t{%2, %0|%0, %2}"
9000 [(set_attr "type" "alu")
9001 (set_attr "mode" "HI")])
9003 (define_insn "*xorhi_2"
9005 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9006 (match_operand:HI 2 "general_operand" "rim,ri"))
9008 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9009 (xor:HI (match_dup 1) (match_dup 2)))]
9010 "ix86_match_ccmode (insn, CCNOmode)
9011 && ix86_binary_operator_ok (XOR, HImode, operands)"
9012 "xor{w}\\t{%2, %0|%0, %2}"
9013 [(set_attr "type" "alu")
9014 (set_attr "mode" "HI")])
9016 (define_insn "*xorhi_3"
9018 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9019 (match_operand:HI 2 "general_operand" "rim"))
9021 (clobber (match_scratch:HI 0 "=r"))]
9022 "ix86_match_ccmode (insn, CCNOmode)
9023 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9024 "xor{w}\\t{%2, %0|%0, %2}"
9025 [(set_attr "type" "alu")
9026 (set_attr "mode" "HI")])
9028 (define_expand "xorqi3"
9029 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9030 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9031 (match_operand:QI 2 "general_operand" "")))
9032 (clobber (reg:CC 17))]
9033 "TARGET_QIMODE_MATH"
9034 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9036 ;; %%% Potential partial reg stall on alternative 2. What to do?
9037 (define_insn "*xorqi_1"
9038 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9039 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9040 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9041 (clobber (reg:CC 17))]
9042 "ix86_binary_operator_ok (XOR, QImode, operands)"
9044 xor{b}\\t{%2, %0|%0, %2}
9045 xor{b}\\t{%2, %0|%0, %2}
9046 xor{l}\\t{%k2, %k0|%k0, %k2}"
9047 [(set_attr "type" "alu")
9048 (set_attr "mode" "QI,QI,SI")])
9050 (define_insn "*xorqi_ext_1"
9051 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9055 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9058 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9061 (clobber (reg:CC 17))]
9063 "xor{b}\\t{%h2, %h0|%h0, %h2}"
9064 [(set_attr "type" "alu")
9065 (set_attr "length_immediate" "0")
9066 (set_attr "mode" "QI")])
9068 (define_insn "*xorqi_cc_1"
9071 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9072 (match_operand:QI 2 "general_operand" "qim,qi"))
9074 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9075 (xor:QI (match_dup 1) (match_dup 2)))]
9076 "ix86_match_ccmode (insn, CCNOmode)
9077 && ix86_binary_operator_ok (XOR, QImode, operands)"
9078 "xor{b}\\t{%2, %0|%0, %2}"
9079 [(set_attr "type" "alu")
9080 (set_attr "mode" "QI")])
9082 (define_insn "*xorqi_cc_2"
9085 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9086 (match_operand:QI 2 "general_operand" "qim"))
9088 (clobber (match_scratch:QI 0 "=q"))]
9089 "ix86_match_ccmode (insn, CCNOmode)
9090 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9091 "xor{b}\\t{%2, %0|%0, %2}"
9092 [(set_attr "type" "alu")
9093 (set_attr "mode" "QI")])
9095 (define_insn "*xorqi_cc_ext_1"
9100 (match_operand 1 "ext_register_operand" "0")
9103 (match_operand:QI 2 "general_operand" "qmn"))
9105 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9109 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9111 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9112 "xor{b}\\t{%2, %h0|%h0, %2}"
9113 [(set_attr "type" "alu")
9114 (set_attr "mode" "QI")])
9116 (define_insn "*xorqi_cc_ext_1_rex64"
9121 (match_operand 1 "ext_register_operand" "0")
9124 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9126 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9130 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9132 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9133 "xor{b}\\t{%2, %h0|%h0, %2}"
9134 [(set_attr "type" "alu")
9135 (set_attr "mode" "QI")])
9137 (define_expand "xorqi_cc_ext_1"
9143 (match_operand 1 "ext_register_operand" "")
9146 (match_operand:QI 2 "general_operand" ""))
9148 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9152 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9157 ;; Negation instructions
9159 (define_expand "negdi2"
9160 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9161 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9162 (clobber (reg:CC 17))])]
9164 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9166 (define_insn "*negdi2_1"
9167 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9168 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9169 (clobber (reg:CC 17))]
9171 && ix86_unary_operator_ok (NEG, DImode, operands)"
9175 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9176 (neg:DI (match_operand:DI 1 "general_operand" "")))
9177 (clobber (reg:CC 17))]
9182 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9183 (set (match_dup 0) (neg:SI (match_dup 2)))])
9186 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9189 (clobber (reg:CC 17))])
9192 (neg:SI (match_dup 1)))
9193 (clobber (reg:CC 17))])]
9194 "split_di (operands+1, 1, operands+2, operands+3);
9195 split_di (operands+0, 1, operands+0, operands+1);")
9197 (define_insn "*negdi2_1_rex64"
9198 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9199 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9200 (clobber (reg:CC 17))]
9201 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9203 [(set_attr "type" "negnot")
9204 (set_attr "mode" "DI")])
9206 ;; The problem with neg is that it does not perform (compare x 0),
9207 ;; it really performs (compare 0 x), which leaves us with the zero
9208 ;; flag being the only useful item.
9210 (define_insn "*negdi2_cmpz_rex64"
9212 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9214 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9215 (neg:DI (match_dup 1)))]
9216 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9218 [(set_attr "type" "negnot")
9219 (set_attr "mode" "DI")])
9222 (define_expand "negsi2"
9223 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9224 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9225 (clobber (reg:CC 17))])]
9227 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9229 (define_insn "*negsi2_1"
9230 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9231 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9232 (clobber (reg:CC 17))]
9233 "ix86_unary_operator_ok (NEG, SImode, operands)"
9235 [(set_attr "type" "negnot")
9236 (set_attr "mode" "SI")])
9238 ;; Combine is quite creative about this pattern.
9239 (define_insn "*negsi2_1_zext"
9240 [(set (match_operand:DI 0 "register_operand" "=r")
9241 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9244 (clobber (reg:CC 17))]
9245 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9247 [(set_attr "type" "negnot")
9248 (set_attr "mode" "SI")])
9250 ;; The problem with neg is that it does not perform (compare x 0),
9251 ;; it really performs (compare 0 x), which leaves us with the zero
9252 ;; flag being the only useful item.
9254 (define_insn "*negsi2_cmpz"
9256 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9258 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9259 (neg:SI (match_dup 1)))]
9260 "ix86_unary_operator_ok (NEG, SImode, operands)"
9262 [(set_attr "type" "negnot")
9263 (set_attr "mode" "SI")])
9265 (define_insn "*negsi2_cmpz_zext"
9267 (compare:CCZ (lshiftrt:DI
9269 (match_operand:DI 1 "register_operand" "0")
9273 (set (match_operand:DI 0 "register_operand" "=r")
9274 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9277 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9279 [(set_attr "type" "negnot")
9280 (set_attr "mode" "SI")])
9282 (define_expand "neghi2"
9283 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9284 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9285 (clobber (reg:CC 17))])]
9286 "TARGET_HIMODE_MATH"
9287 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9289 (define_insn "*neghi2_1"
9290 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9291 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9292 (clobber (reg:CC 17))]
9293 "ix86_unary_operator_ok (NEG, HImode, operands)"
9295 [(set_attr "type" "negnot")
9296 (set_attr "mode" "HI")])
9298 (define_insn "*neghi2_cmpz"
9300 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9302 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9303 (neg:HI (match_dup 1)))]
9304 "ix86_unary_operator_ok (NEG, HImode, operands)"
9306 [(set_attr "type" "negnot")
9307 (set_attr "mode" "HI")])
9309 (define_expand "negqi2"
9310 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9311 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9312 (clobber (reg:CC 17))])]
9313 "TARGET_QIMODE_MATH"
9314 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9316 (define_insn "*negqi2_1"
9317 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9318 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9319 (clobber (reg:CC 17))]
9320 "ix86_unary_operator_ok (NEG, QImode, operands)"
9322 [(set_attr "type" "negnot")
9323 (set_attr "mode" "QI")])
9325 (define_insn "*negqi2_cmpz"
9327 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9329 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9330 (neg:QI (match_dup 1)))]
9331 "ix86_unary_operator_ok (NEG, QImode, operands)"
9333 [(set_attr "type" "negnot")
9334 (set_attr "mode" "QI")])
9336 ;; Changing of sign for FP values is doable using integer unit too.
9338 (define_expand "negsf2"
9339 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9340 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9341 (clobber (reg:CC 17))])]
9345 /* In case operand is in memory, we will not use SSE. */
9346 if (memory_operand (operands[0], VOIDmode)
9347 && rtx_equal_p (operands[0], operands[1]))
9348 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9351 /* Using SSE is tricky, since we need bitwise negation of -0
9353 rtx reg = gen_reg_rtx (SFmode);
9354 rtx dest = operands[0];
9356 operands[1] = force_reg (SFmode, operands[1]);
9357 operands[0] = force_reg (SFmode, operands[0]);
9358 emit_move_insn (reg,
9359 gen_lowpart (SFmode,
9360 GEN_INT (trunc_int_for_mode (0x80000000,
9362 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9363 if (dest != operands[0])
9364 emit_move_insn (dest, operands[0]);
9368 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9370 (define_insn "negsf2_memory"
9371 [(set (match_operand:SF 0 "memory_operand" "=m")
9372 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9373 (clobber (reg:CC 17))]
9374 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9377 (define_insn "negsf2_ifs"
9378 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9379 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9380 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9381 (clobber (reg:CC 17))]
9383 && (reload_in_progress || reload_completed
9384 || (register_operand (operands[0], VOIDmode)
9385 && register_operand (operands[1], VOIDmode)))"
9389 [(set (match_operand:SF 0 "memory_operand" "")
9390 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9391 (use (match_operand:SF 2 "" ""))
9392 (clobber (reg:CC 17))]
9394 [(parallel [(set (match_dup 0)
9395 (neg:SF (match_dup 1)))
9396 (clobber (reg:CC 17))])])
9399 [(set (match_operand:SF 0 "register_operand" "")
9400 (neg:SF (match_operand:SF 1 "register_operand" "")))
9401 (use (match_operand:SF 2 "" ""))
9402 (clobber (reg:CC 17))]
9403 "reload_completed && !SSE_REG_P (operands[0])"
9404 [(parallel [(set (match_dup 0)
9405 (neg:SF (match_dup 1)))
9406 (clobber (reg:CC 17))])])
9409 [(set (match_operand:SF 0 "register_operand" "")
9410 (neg:SF (match_operand:SF 1 "register_operand" "")))
9411 (use (match_operand:SF 2 "register_operand" ""))
9412 (clobber (reg:CC 17))]
9413 "reload_completed && SSE_REG_P (operands[0])"
9414 [(set (subreg:TI (match_dup 0) 0)
9415 (xor:TI (subreg:TI (match_dup 1) 0)
9416 (subreg:TI (match_dup 2) 0)))]
9419 if (operands_match_p (operands[0], operands[2]))
9423 operands[1] = operands[2];
9429 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9430 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9432 (define_insn "*negsf2_if"
9433 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9434 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9435 (clobber (reg:CC 17))]
9436 "TARGET_80387 && !TARGET_SSE
9437 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9441 [(set (match_operand:SF 0 "register_operand" "")
9442 (neg:SF (match_operand:SF 1 "register_operand" "")))
9443 (clobber (reg:CC 17))]
9444 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9446 (neg:SF (match_dup 1)))]
9450 [(set (match_operand:SF 0 "register_operand" "")
9451 (neg:SF (match_operand:SF 1 "register_operand" "")))
9452 (clobber (reg:CC 17))]
9453 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9454 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9455 (clobber (reg:CC 17))])]
9456 "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9457 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9460 [(set (match_operand 0 "memory_operand" "")
9461 (neg (match_operand 1 "memory_operand" "")))
9462 (clobber (reg:CC 17))]
9463 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9464 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9465 (clobber (reg:CC 17))])]
9468 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9470 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9473 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9474 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9475 operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
9478 (define_expand "negdf2"
9479 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9480 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9481 (clobber (reg:CC 17))])]
9485 /* In case operand is in memory, we will not use SSE. */
9486 if (memory_operand (operands[0], VOIDmode)
9487 && rtx_equal_p (operands[0], operands[1]))
9488 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9491 /* Using SSE is tricky, since we need bitwise negation of -0
9493 rtx reg = gen_reg_rtx (DFmode);
9494 #if HOST_BITS_PER_WIDE_INT >= 64
9495 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9498 rtx imm = immed_double_const (0, 0x80000000, DImode);
9500 rtx dest = operands[0];
9502 operands[1] = force_reg (DFmode, operands[1]);
9503 operands[0] = force_reg (DFmode, operands[0]);
9504 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9505 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9506 if (dest != operands[0])
9507 emit_move_insn (dest, operands[0]);
9511 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9513 (define_insn "negdf2_memory"
9514 [(set (match_operand:DF 0 "memory_operand" "=m")
9515 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9516 (clobber (reg:CC 17))]
9517 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9520 (define_insn "negdf2_ifs"
9521 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9522 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9523 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9524 (clobber (reg:CC 17))]
9525 "TARGET_SSE2 && !TARGET_64BIT
9526 && (reload_in_progress || reload_completed
9527 || (register_operand (operands[0], VOIDmode)
9528 && register_operand (operands[1], VOIDmode)))"
9531 (define_insn "*negdf2_ifs_rex64"
9532 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9533 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9534 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9535 (clobber (reg:CC 17))]
9536 "TARGET_SSE2 && TARGET_64BIT
9537 && (reload_in_progress || reload_completed
9538 || (register_operand (operands[0], VOIDmode)
9539 && register_operand (operands[1], VOIDmode)))"
9543 [(set (match_operand:DF 0 "memory_operand" "")
9544 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9545 (use (match_operand:DF 2 "" ""))
9546 (clobber (reg:CC 17))]
9548 [(parallel [(set (match_dup 0)
9549 (neg:DF (match_dup 1)))
9550 (clobber (reg:CC 17))])])
9553 [(set (match_operand:DF 0 "register_operand" "")
9554 (neg:DF (match_operand:DF 1 "register_operand" "")))
9555 (use (match_operand:DF 2 "" ""))
9556 (clobber (reg:CC 17))]
9557 "reload_completed && !SSE_REG_P (operands[0])
9558 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9559 [(parallel [(set (match_dup 0)
9560 (neg:DF (match_dup 1)))
9561 (clobber (reg:CC 17))])])
9564 [(set (match_operand:DF 0 "register_operand" "")
9565 (neg:DF (match_operand:DF 1 "register_operand" "")))
9566 (use (match_operand:DF 2 "" ""))
9567 (clobber (reg:CC 17))]
9568 "reload_completed && GENERAL_REG_P (operands[0]) && TARGET_64BIT"
9569 [(parallel [(set (match_dup 0)
9570 (xor:DI (match_dup 1) (match_dup 2)))
9571 (clobber (reg:CC 17))])]
9572 "operands[0] = gen_lowpart (DImode, operands[0]);
9573 operands[1] = gen_lowpart (DImode, operands[1]);
9574 operands[2] = gen_lowpart (DImode, operands[2]);")
9577 [(set (match_operand:DF 0 "register_operand" "")
9578 (neg:DF (match_operand:DF 1 "register_operand" "")))
9579 (use (match_operand:DF 2 "register_operand" ""))
9580 (clobber (reg:CC 17))]
9581 "reload_completed && SSE_REG_P (operands[0])"
9582 [(set (subreg:TI (match_dup 0) 0)
9583 (xor:TI (subreg:TI (match_dup 1) 0)
9584 (subreg:TI (match_dup 2) 0)))]
9587 if (operands_match_p (operands[0], operands[2]))
9591 operands[1] = operands[2];
9596 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9597 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9599 (define_insn "*negdf2_if"
9600 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9601 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9602 (clobber (reg:CC 17))]
9603 "TARGET_80387 && !TARGET_64BIT
9604 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9607 ;; FIXME: We should to allow integer registers here. Problem is that
9608 ;; we need another scratch register to get constant from.
9609 ;; Forcing constant to mem if no register available in peep2 should be
9610 ;; safe even for PIC mode, because of RIP relative addressing.
9611 (define_insn "*negdf2_if_rex64"
9612 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9613 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9614 (clobber (reg:CC 17))]
9615 "TARGET_80387 && TARGET_64BIT
9616 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9620 [(set (match_operand:DF 0 "register_operand" "")
9621 (neg:DF (match_operand:DF 1 "register_operand" "")))
9622 (clobber (reg:CC 17))]
9623 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9625 (neg:DF (match_dup 1)))]
9629 [(set (match_operand:DF 0 "register_operand" "")
9630 (neg:DF (match_operand:DF 1 "register_operand" "")))
9631 (clobber (reg:CC 17))]
9632 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
9634 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9635 (clobber (reg:CC 17))])]
9636 "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9637 split_di (operands+0, 1, operands+2, operands+3);")
9639 (define_expand "negxf2"
9640 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9641 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9642 (clobber (reg:CC 17))])]
9643 "TARGET_80387 && !TARGET_64BIT"
9644 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9646 (define_expand "negtf2"
9647 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9648 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9649 (clobber (reg:CC 17))])]
9651 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9653 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9654 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9656 (define_insn "*negxf2_if"
9657 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9658 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9659 (clobber (reg:CC 17))]
9660 "TARGET_80387 && !TARGET_64BIT
9661 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9665 [(set (match_operand:XF 0 "register_operand" "")
9666 (neg:XF (match_operand:XF 1 "register_operand" "")))
9667 (clobber (reg:CC 17))]
9668 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9670 (neg:XF (match_dup 1)))]
9674 [(set (match_operand:XF 0 "register_operand" "")
9675 (neg:XF (match_operand:XF 1 "register_operand" "")))
9676 (clobber (reg:CC 17))]
9677 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9678 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9679 (clobber (reg:CC 17))])]
9680 "operands[1] = GEN_INT (0x8000);
9681 operands[0] = gen_rtx_REG (SImode,
9682 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9684 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9685 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9687 (define_insn "*negtf2_if"
9688 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9689 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9690 (clobber (reg:CC 17))]
9691 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9695 [(set (match_operand:TF 0 "register_operand" "")
9696 (neg:TF (match_operand:TF 1 "register_operand" "")))
9697 (clobber (reg:CC 17))]
9698 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9700 (neg:TF (match_dup 1)))]
9704 [(set (match_operand:TF 0 "register_operand" "")
9705 (neg:TF (match_operand:TF 1 "register_operand" "")))
9706 (clobber (reg:CC 17))]
9707 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9708 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9709 (clobber (reg:CC 17))])]
9710 "operands[1] = GEN_INT (0x8000);
9711 operands[0] = gen_rtx_REG (SImode,
9712 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9714 ;; Conditionize these after reload. If they matches before reload, we
9715 ;; lose the clobber and ability to use integer instructions.
9717 (define_insn "*negsf2_1"
9718 [(set (match_operand:SF 0 "register_operand" "=f")
9719 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9720 "TARGET_80387 && reload_completed"
9722 [(set_attr "type" "fsgn")
9723 (set_attr "mode" "SF")
9724 (set_attr "ppro_uops" "few")])
9726 (define_insn "*negdf2_1"
9727 [(set (match_operand:DF 0 "register_operand" "=f")
9728 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9729 "TARGET_80387 && reload_completed"
9731 [(set_attr "type" "fsgn")
9732 (set_attr "mode" "DF")
9733 (set_attr "ppro_uops" "few")])
9735 (define_insn "*negextendsfdf2"
9736 [(set (match_operand:DF 0 "register_operand" "=f")
9737 (neg:DF (float_extend:DF
9738 (match_operand:SF 1 "register_operand" "0"))))]
9741 [(set_attr "type" "fsgn")
9742 (set_attr "mode" "DF")
9743 (set_attr "ppro_uops" "few")])
9745 (define_insn "*negxf2_1"
9746 [(set (match_operand:XF 0 "register_operand" "=f")
9747 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9748 "TARGET_80387 && !TARGET_64BIT && reload_completed"
9750 [(set_attr "type" "fsgn")
9751 (set_attr "mode" "XF")
9752 (set_attr "ppro_uops" "few")])
9754 (define_insn "*negextenddfxf2"
9755 [(set (match_operand:XF 0 "register_operand" "=f")
9756 (neg:XF (float_extend:XF
9757 (match_operand:DF 1 "register_operand" "0"))))]
9758 "TARGET_80387 && !TARGET_64BIT"
9760 [(set_attr "type" "fsgn")
9761 (set_attr "mode" "XF")
9762 (set_attr "ppro_uops" "few")])
9764 (define_insn "*negextendsfxf2"
9765 [(set (match_operand:XF 0 "register_operand" "=f")
9766 (neg:XF (float_extend:XF
9767 (match_operand:SF 1 "register_operand" "0"))))]
9768 "TARGET_80387 && !TARGET_64BIT"
9770 [(set_attr "type" "fsgn")
9771 (set_attr "mode" "XF")
9772 (set_attr "ppro_uops" "few")])
9774 (define_insn "*negtf2_1"
9775 [(set (match_operand:TF 0 "register_operand" "=f")
9776 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9777 "TARGET_80387 && reload_completed"
9779 [(set_attr "type" "fsgn")
9780 (set_attr "mode" "XF")
9781 (set_attr "ppro_uops" "few")])
9783 (define_insn "*negextenddftf2"
9784 [(set (match_operand:TF 0 "register_operand" "=f")
9785 (neg:TF (float_extend:TF
9786 (match_operand:DF 1 "register_operand" "0"))))]
9789 [(set_attr "type" "fsgn")
9790 (set_attr "mode" "XF")
9791 (set_attr "ppro_uops" "few")])
9793 (define_insn "*negextendsftf2"
9794 [(set (match_operand:TF 0 "register_operand" "=f")
9795 (neg:TF (float_extend:TF
9796 (match_operand:SF 1 "register_operand" "0"))))]
9799 [(set_attr "type" "fsgn")
9800 (set_attr "mode" "XF")
9801 (set_attr "ppro_uops" "few")])
9803 ;; Absolute value instructions
9805 (define_expand "abssf2"
9806 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9807 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9808 (clobber (reg:CC 17))])]
9812 /* In case operand is in memory, we will not use SSE. */
9813 if (memory_operand (operands[0], VOIDmode)
9814 && rtx_equal_p (operands[0], operands[1]))
9815 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9818 /* Using SSE is tricky, since we need bitwise negation of -0
9820 rtx reg = gen_reg_rtx (SFmode);
9821 rtx dest = operands[0];
9823 operands[1] = force_reg (SFmode, operands[1]);
9824 operands[0] = force_reg (SFmode, operands[0]);
9825 emit_move_insn (reg,
9826 gen_lowpart (SFmode,
9827 GEN_INT (trunc_int_for_mode (0x80000000,
9829 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9830 if (dest != operands[0])
9831 emit_move_insn (dest, operands[0]);
9835 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9837 (define_insn "abssf2_memory"
9838 [(set (match_operand:SF 0 "memory_operand" "=m")
9839 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9840 (clobber (reg:CC 17))]
9841 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9844 (define_insn "abssf2_ifs"
9845 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9846 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9847 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9848 (clobber (reg:CC 17))]
9850 && (reload_in_progress || reload_completed
9851 || (register_operand (operands[0], VOIDmode)
9852 && register_operand (operands[1], VOIDmode)))"
9856 [(set (match_operand:SF 0 "memory_operand" "")
9857 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9858 (use (match_operand:SF 2 "" ""))
9859 (clobber (reg:CC 17))]
9861 [(parallel [(set (match_dup 0)
9862 (abs:SF (match_dup 1)))
9863 (clobber (reg:CC 17))])])
9866 [(set (match_operand:SF 0 "register_operand" "")
9867 (abs:SF (match_operand:SF 1 "register_operand" "")))
9868 (use (match_operand:SF 2 "" ""))
9869 (clobber (reg:CC 17))]
9870 "reload_completed && !SSE_REG_P (operands[0])"
9871 [(parallel [(set (match_dup 0)
9872 (abs:SF (match_dup 1)))
9873 (clobber (reg:CC 17))])])
9876 [(set (match_operand:SF 0 "register_operand" "")
9877 (abs:SF (match_operand:SF 1 "register_operand" "")))
9878 (use (match_operand:SF 2 "register_operand" ""))
9879 (clobber (reg:CC 17))]
9880 "reload_completed && SSE_REG_P (operands[0])"
9881 [(set (subreg:TI (match_dup 0) 0)
9882 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9883 (subreg:TI (match_dup 1) 0)))])
9885 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9886 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9888 (define_insn "*abssf2_if"
9889 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9890 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9891 (clobber (reg:CC 17))]
9892 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9896 [(set (match_operand:SF 0 "register_operand" "")
9897 (abs:SF (match_operand:SF 1 "register_operand" "")))
9898 (clobber (reg:CC 17))]
9899 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9901 (abs:SF (match_dup 1)))]
9905 [(set (match_operand:SF 0 "register_operand" "")
9906 (abs:SF (match_operand:SF 1 "register_operand" "")))
9907 (clobber (reg:CC 17))]
9908 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9909 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9910 (clobber (reg:CC 17))])]
9911 "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9912 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9915 [(set (match_operand 0 "memory_operand" "")
9916 (abs (match_operand 1 "memory_operand" "")))
9917 (clobber (reg:CC 17))]
9918 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9919 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9920 (clobber (reg:CC 17))])]
9923 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9925 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9928 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9929 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9930 operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
9933 (define_expand "absdf2"
9934 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9935 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9936 (clobber (reg:CC 17))])]
9940 /* In case operand is in memory, we will not use SSE. */
9941 if (memory_operand (operands[0], VOIDmode)
9942 && rtx_equal_p (operands[0], operands[1]))
9943 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9946 /* Using SSE is tricky, since we need bitwise negation of -0
9948 rtx reg = gen_reg_rtx (DFmode);
9949 #if HOST_BITS_PER_WIDE_INT >= 64
9950 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9953 rtx imm = immed_double_const (0, 0x80000000, DImode);
9955 rtx dest = operands[0];
9957 operands[1] = force_reg (DFmode, operands[1]);
9958 operands[0] = force_reg (DFmode, operands[0]);
9959 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9960 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9961 if (dest != operands[0])
9962 emit_move_insn (dest, operands[0]);
9966 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9968 (define_insn "absdf2_memory"
9969 [(set (match_operand:DF 0 "memory_operand" "=m")
9970 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9971 (clobber (reg:CC 17))]
9972 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9975 (define_insn "absdf2_ifs"
9976 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9977 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9978 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9979 (clobber (reg:CC 17))]
9980 "TARGET_SSE2 && !TARGET_64BIT
9981 && (reload_in_progress || reload_completed
9982 || (register_operand (operands[0], VOIDmode)
9983 && register_operand (operands[1], VOIDmode)))"
9986 (define_insn "*absdf2_ifs_rex64"
9987 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9988 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9989 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9990 (clobber (reg:CC 17))]
9991 "TARGET_SSE2 && TARGET_64BIT
9992 && (reload_in_progress || reload_completed
9993 || (register_operand (operands[0], VOIDmode)
9994 && register_operand (operands[1], VOIDmode)))"
9998 [(set (match_operand:DF 0 "memory_operand" "")
9999 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10000 (use (match_operand:DF 2 "" ""))
10001 (clobber (reg:CC 17))]
10003 [(parallel [(set (match_dup 0)
10004 (abs:DF (match_dup 1)))
10005 (clobber (reg:CC 17))])])
10008 [(set (match_operand:DF 0 "register_operand" "")
10009 (abs:DF (match_operand:DF 1 "register_operand" "")))
10010 (use (match_operand:DF 2 "" ""))
10011 (clobber (reg:CC 17))]
10012 "reload_completed && !SSE_REG_P (operands[0])"
10013 [(parallel [(set (match_dup 0)
10014 (abs:DF (match_dup 1)))
10015 (clobber (reg:CC 17))])])
10018 [(set (match_operand:DF 0 "register_operand" "")
10019 (abs:DF (match_operand:DF 1 "register_operand" "")))
10020 (use (match_operand:DF 2 "register_operand" ""))
10021 (clobber (reg:CC 17))]
10022 "reload_completed && SSE_REG_P (operands[0])"
10023 [(set (subreg:TI (match_dup 0) 0)
10024 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
10025 (subreg:TI (match_dup 1) 0)))])
10028 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10029 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10031 (define_insn "*absdf2_if"
10032 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10033 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10034 (clobber (reg:CC 17))]
10035 "TARGET_80387 && !TARGET_64BIT
10036 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10039 ;; FIXME: We should to allow integer registers here. Problem is that
10040 ;; we need another scratch register to get constant from.
10041 ;; Forcing constant to mem if no register available in peep2 should be
10042 ;; safe even for PIC mode, because of RIP relative addressing.
10043 (define_insn "*absdf2_if_rex64"
10044 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10045 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10046 (clobber (reg:CC 17))]
10047 "TARGET_80387 && TARGET_64BIT
10048 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10052 [(set (match_operand:DF 0 "register_operand" "")
10053 (abs:DF (match_operand:DF 1 "register_operand" "")))
10054 (clobber (reg:CC 17))]
10055 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10056 [(set (match_dup 0)
10057 (abs:DF (match_dup 1)))]
10061 [(set (match_operand:DF 0 "register_operand" "")
10062 (abs:DF (match_operand:DF 1 "register_operand" "")))
10063 (clobber (reg:CC 17))]
10064 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
10066 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10067 (clobber (reg:CC 17))])]
10068 "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
10069 split_di (operands+0, 1, operands+2, operands+3);")
10071 (define_expand "absxf2"
10072 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10073 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10074 (clobber (reg:CC 17))])]
10075 "TARGET_80387 && !TARGET_64BIT"
10076 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10078 (define_expand "abstf2"
10079 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10080 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10081 (clobber (reg:CC 17))])]
10083 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10085 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10086 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10088 (define_insn "*absxf2_if"
10089 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10090 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10091 (clobber (reg:CC 17))]
10092 "TARGET_80387 && !TARGET_64BIT
10093 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10097 [(set (match_operand:XF 0 "register_operand" "")
10098 (abs:XF (match_operand:XF 1 "register_operand" "")))
10099 (clobber (reg:CC 17))]
10100 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10101 [(set (match_dup 0)
10102 (abs:XF (match_dup 1)))]
10106 [(set (match_operand:XF 0 "register_operand" "")
10107 (abs:XF (match_operand:XF 1 "register_operand" "")))
10108 (clobber (reg:CC 17))]
10109 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10110 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10111 (clobber (reg:CC 17))])]
10112 "operands[1] = GEN_INT (~0x8000);
10113 operands[0] = gen_rtx_REG (SImode,
10114 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10116 (define_insn "*abstf2_if"
10117 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10118 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10119 (clobber (reg:CC 17))]
10120 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10124 [(set (match_operand:TF 0 "register_operand" "")
10125 (abs:TF (match_operand:TF 1 "register_operand" "")))
10126 (clobber (reg:CC 17))]
10127 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10128 [(set (match_dup 0)
10129 (abs:TF (match_dup 1)))]
10133 [(set (match_operand:TF 0 "register_operand" "")
10134 (abs:TF (match_operand:TF 1 "register_operand" "")))
10135 (clobber (reg:CC 17))]
10136 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10137 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10138 (clobber (reg:CC 17))])]
10139 "operands[1] = GEN_INT (~0x8000);
10140 operands[0] = gen_rtx_REG (SImode,
10141 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10143 (define_insn "*abssf2_1"
10144 [(set (match_operand:SF 0 "register_operand" "=f")
10145 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10146 "TARGET_80387 && reload_completed"
10148 [(set_attr "type" "fsgn")
10149 (set_attr "mode" "SF")])
10151 (define_insn "*absdf2_1"
10152 [(set (match_operand:DF 0 "register_operand" "=f")
10153 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10154 "TARGET_80387 && reload_completed"
10156 [(set_attr "type" "fsgn")
10157 (set_attr "mode" "DF")])
10159 (define_insn "*absextendsfdf2"
10160 [(set (match_operand:DF 0 "register_operand" "=f")
10161 (abs:DF (float_extend:DF
10162 (match_operand:SF 1 "register_operand" "0"))))]
10165 [(set_attr "type" "fsgn")
10166 (set_attr "mode" "DF")])
10168 (define_insn "*absxf2_1"
10169 [(set (match_operand:XF 0 "register_operand" "=f")
10170 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10171 "TARGET_80387 && !TARGET_64BIT && reload_completed"
10173 [(set_attr "type" "fsgn")
10174 (set_attr "mode" "DF")])
10176 (define_insn "*absextenddfxf2"
10177 [(set (match_operand:XF 0 "register_operand" "=f")
10178 (abs:XF (float_extend:XF
10179 (match_operand:DF 1 "register_operand" "0"))))]
10180 "TARGET_80387 && !TARGET_64BIT"
10182 [(set_attr "type" "fsgn")
10183 (set_attr "mode" "XF")])
10185 (define_insn "*absextendsfxf2"
10186 [(set (match_operand:XF 0 "register_operand" "=f")
10187 (abs:XF (float_extend:XF
10188 (match_operand:SF 1 "register_operand" "0"))))]
10189 "TARGET_80387 && !TARGET_64BIT"
10191 [(set_attr "type" "fsgn")
10192 (set_attr "mode" "XF")])
10194 (define_insn "*abstf2_1"
10195 [(set (match_operand:TF 0 "register_operand" "=f")
10196 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10197 "TARGET_80387 && reload_completed"
10199 [(set_attr "type" "fsgn")
10200 (set_attr "mode" "DF")])
10202 (define_insn "*absextenddftf2"
10203 [(set (match_operand:TF 0 "register_operand" "=f")
10204 (abs:TF (float_extend:TF
10205 (match_operand:DF 1 "register_operand" "0"))))]
10208 [(set_attr "type" "fsgn")
10209 (set_attr "mode" "XF")])
10211 (define_insn "*absextendsftf2"
10212 [(set (match_operand:TF 0 "register_operand" "=f")
10213 (abs:TF (float_extend:TF
10214 (match_operand:SF 1 "register_operand" "0"))))]
10217 [(set_attr "type" "fsgn")
10218 (set_attr "mode" "XF")])
10220 ;; One complement instructions
10222 (define_expand "one_cmpldi2"
10223 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10224 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10226 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10228 (define_insn "*one_cmpldi2_1_rex64"
10229 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10230 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10231 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10233 [(set_attr "type" "negnot")
10234 (set_attr "mode" "DI")])
10236 (define_insn "*one_cmpldi2_2_rex64"
10238 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10240 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10241 (not:DI (match_dup 1)))]
10242 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10243 && ix86_unary_operator_ok (NOT, DImode, operands)"
10245 [(set_attr "type" "alu1")
10246 (set_attr "mode" "DI")])
10250 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10252 (set (match_operand:DI 0 "nonimmediate_operand" "")
10253 (not:DI (match_dup 1)))]
10254 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10255 [(parallel [(set (reg:CCNO 17)
10256 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10259 (xor:DI (match_dup 1) (const_int -1)))])]
10262 (define_expand "one_cmplsi2"
10263 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10264 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10266 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10268 (define_insn "*one_cmplsi2_1"
10269 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10270 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10271 "ix86_unary_operator_ok (NOT, SImode, operands)"
10273 [(set_attr "type" "negnot")
10274 (set_attr "mode" "SI")])
10276 ;; ??? Currently never generated - xor is used instead.
10277 (define_insn "*one_cmplsi2_1_zext"
10278 [(set (match_operand:DI 0 "register_operand" "=r")
10279 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10280 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10282 [(set_attr "type" "negnot")
10283 (set_attr "mode" "SI")])
10285 (define_insn "*one_cmplsi2_2"
10287 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10289 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10290 (not:SI (match_dup 1)))]
10291 "ix86_match_ccmode (insn, CCNOmode)
10292 && ix86_unary_operator_ok (NOT, SImode, operands)"
10294 [(set_attr "type" "alu1")
10295 (set_attr "mode" "SI")])
10299 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10301 (set (match_operand:SI 0 "nonimmediate_operand" "")
10302 (not:SI (match_dup 1)))]
10303 "ix86_match_ccmode (insn, CCNOmode)"
10304 [(parallel [(set (reg:CCNO 17)
10305 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10308 (xor:SI (match_dup 1) (const_int -1)))])]
10311 ;; ??? Currently never generated - xor is used instead.
10312 (define_insn "*one_cmplsi2_2_zext"
10314 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10316 (set (match_operand:DI 0 "register_operand" "=r")
10317 (zero_extend:DI (not:SI (match_dup 1))))]
10318 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10319 && ix86_unary_operator_ok (NOT, SImode, operands)"
10321 [(set_attr "type" "alu1")
10322 (set_attr "mode" "SI")])
10326 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10328 (set (match_operand:DI 0 "register_operand" "")
10329 (zero_extend:DI (not:SI (match_dup 1))))]
10330 "ix86_match_ccmode (insn, CCNOmode)"
10331 [(parallel [(set (reg:CCNO 17)
10332 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10335 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10338 (define_expand "one_cmplhi2"
10339 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10340 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10341 "TARGET_HIMODE_MATH"
10342 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10344 (define_insn "*one_cmplhi2_1"
10345 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10346 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10347 "ix86_unary_operator_ok (NOT, HImode, operands)"
10349 [(set_attr "type" "negnot")
10350 (set_attr "mode" "HI")])
10352 (define_insn "*one_cmplhi2_2"
10354 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10356 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10357 (not:HI (match_dup 1)))]
10358 "ix86_match_ccmode (insn, CCNOmode)
10359 && ix86_unary_operator_ok (NEG, HImode, operands)"
10361 [(set_attr "type" "alu1")
10362 (set_attr "mode" "HI")])
10366 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10368 (set (match_operand:HI 0 "nonimmediate_operand" "")
10369 (not:HI (match_dup 1)))]
10370 "ix86_match_ccmode (insn, CCNOmode)"
10371 [(parallel [(set (reg:CCNO 17)
10372 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10375 (xor:HI (match_dup 1) (const_int -1)))])]
10378 ;; %%% Potential partial reg stall on alternative 1. What to do?
10379 (define_expand "one_cmplqi2"
10380 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10381 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10382 "TARGET_QIMODE_MATH"
10383 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10385 (define_insn "*one_cmplqi2_1"
10386 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10387 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10388 "ix86_unary_operator_ok (NOT, QImode, operands)"
10392 [(set_attr "type" "negnot")
10393 (set_attr "mode" "QI,SI")])
10395 (define_insn "*one_cmplqi2_2"
10397 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10399 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10400 (not:QI (match_dup 1)))]
10401 "ix86_match_ccmode (insn, CCNOmode)
10402 && ix86_unary_operator_ok (NOT, QImode, operands)"
10404 [(set_attr "type" "alu1")
10405 (set_attr "mode" "QI")])
10409 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10411 (set (match_operand:QI 0 "nonimmediate_operand" "")
10412 (not:QI (match_dup 1)))]
10413 "ix86_match_ccmode (insn, CCNOmode)"
10414 [(parallel [(set (reg:CCNO 17)
10415 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10418 (xor:QI (match_dup 1) (const_int -1)))])]
10421 ;; Arithmetic shift instructions
10423 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10424 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10425 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10426 ;; from the assembler input.
10428 ;; This instruction shifts the target reg/mem as usual, but instead of
10429 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10430 ;; is a left shift double, bits are taken from the high order bits of
10431 ;; reg, else if the insn is a shift right double, bits are taken from the
10432 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10433 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10435 ;; Since sh[lr]d does not change the `reg' operand, that is done
10436 ;; separately, making all shifts emit pairs of shift double and normal
10437 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10438 ;; support a 63 bit shift, each shift where the count is in a reg expands
10439 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10441 ;; If the shift count is a constant, we need never emit more than one
10442 ;; shift pair, instead using moves and sign extension for counts greater
10445 (define_expand "ashldi3"
10446 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10447 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10448 (match_operand:QI 2 "nonmemory_operand" "")))
10449 (clobber (reg:CC 17))])]
10453 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10455 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10458 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10462 (define_insn "*ashldi3_1_rex64"
10463 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10464 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10465 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10466 (clobber (reg:CC 17))]
10467 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10470 switch (get_attr_type (insn))
10473 if (operands[2] != const1_rtx)
10475 if (!rtx_equal_p (operands[0], operands[1]))
10477 return \"add{q}\\t{%0, %0|%0, %0}\";
10480 if (GET_CODE (operands[2]) != CONST_INT
10481 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10483 operands[1] = gen_rtx_MULT (DImode, operands[1],
10484 GEN_INT (1 << INTVAL (operands[2])));
10485 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
10488 if (REG_P (operands[2]))
10489 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10490 else if (GET_CODE (operands[2]) == CONST_INT
10491 && INTVAL (operands[2]) == 1
10492 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10493 return \"sal{q}\\t%0\";
10495 return \"sal{q}\\t{%2, %0|%0, %2}\";
10498 [(set (attr "type")
10499 (cond [(eq_attr "alternative" "1")
10500 (const_string "lea")
10501 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10503 (match_operand 0 "register_operand" ""))
10504 (match_operand 2 "const1_operand" ""))
10505 (const_string "alu")
10507 (const_string "ishift")))
10508 (set_attr "mode" "DI")])
10510 ;; Convert lea to the lea pattern to avoid flags dependency.
10512 [(set (match_operand:DI 0 "register_operand" "")
10513 (ashift:DI (match_operand:DI 1 "register_operand" "")
10514 (match_operand:QI 2 "immediate_operand" "")))
10515 (clobber (reg:CC 17))]
10518 && true_regnum (operands[0]) != true_regnum (operands[1])"
10519 [(set (match_dup 0)
10520 (mult:DI (match_dup 1)
10522 "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10525 ;; This pattern can't accept a variable shift count, since shifts by
10526 ;; zero don't affect the flags. We assume that shifts by constant
10527 ;; zero are optimized away.
10528 (define_insn "*ashldi3_cmp_rex64"
10531 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10532 (match_operand:QI 2 "immediate_operand" "e"))
10534 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10535 (ashift:DI (match_dup 1) (match_dup 2)))]
10536 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10537 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10540 switch (get_attr_type (insn))
10543 if (operands[2] != const1_rtx)
10545 return \"add{q}\\t{%0, %0|%0, %0}\";
10548 if (REG_P (operands[2]))
10549 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10550 else if (GET_CODE (operands[2]) == CONST_INT
10551 && INTVAL (operands[2]) == 1
10552 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10553 return \"sal{q}\\t%0\";
10555 return \"sal{q}\\t{%2, %0|%0, %2}\";
10558 [(set (attr "type")
10559 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10561 (match_operand 0 "register_operand" ""))
10562 (match_operand 2 "const1_operand" ""))
10563 (const_string "alu")
10565 (const_string "ishift")))
10566 (set_attr "mode" "DI")])
10568 (define_insn "ashldi3_1"
10569 [(set (match_operand:DI 0 "register_operand" "=r")
10570 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10571 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10572 (clobber (match_scratch:SI 3 "=&r"))
10573 (clobber (reg:CC 17))]
10574 "!TARGET_64BIT && TARGET_CMOVE"
10576 [(set_attr "type" "multi")])
10578 (define_insn "*ashldi3_2"
10579 [(set (match_operand:DI 0 "register_operand" "=r")
10580 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10581 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10582 (clobber (reg:CC 17))]
10585 [(set_attr "type" "multi")])
10588 [(set (match_operand:DI 0 "register_operand" "")
10589 (ashift:DI (match_operand:DI 1 "register_operand" "")
10590 (match_operand:QI 2 "nonmemory_operand" "")))
10591 (clobber (match_scratch:SI 3 ""))
10592 (clobber (reg:CC 17))]
10593 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10595 "ix86_split_ashldi (operands, operands[3]); DONE;")
10598 [(set (match_operand:DI 0 "register_operand" "")
10599 (ashift:DI (match_operand:DI 1 "register_operand" "")
10600 (match_operand:QI 2 "nonmemory_operand" "")))
10601 (clobber (reg:CC 17))]
10602 "!TARGET_64BIT && reload_completed"
10604 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10606 (define_insn "x86_shld_1"
10607 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10608 (ior:SI (ashift:SI (match_dup 0)
10609 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10610 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10611 (minus:QI (const_int 32) (match_dup 2)))))
10612 (clobber (reg:CC 17))]
10615 shld{l}\\t{%2, %1, %0|%0, %1, %2}
10616 shld{l}\\t{%s2%1, %0|%0, %1, %2}"
10617 [(set_attr "type" "ishift")
10618 (set_attr "prefix_0f" "1")
10619 (set_attr "mode" "SI")
10620 (set_attr "pent_pair" "np")
10621 (set_attr "athlon_decode" "vector")
10622 (set_attr "ppro_uops" "few")])
10624 (define_expand "x86_shift_adj_1"
10626 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10629 (set (match_operand:SI 0 "register_operand" "")
10630 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10631 (match_operand:SI 1 "register_operand" "")
10634 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10635 (match_operand:SI 3 "register_operand" "r")
10640 (define_expand "x86_shift_adj_2"
10641 [(use (match_operand:SI 0 "register_operand" ""))
10642 (use (match_operand:SI 1 "register_operand" ""))
10643 (use (match_operand:QI 2 "register_operand" ""))]
10647 rtx label = gen_label_rtx ();
10650 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10652 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10653 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10654 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10655 gen_rtx_LABEL_REF (VOIDmode, label),
10657 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10658 JUMP_LABEL (tmp) = label;
10660 emit_move_insn (operands[0], operands[1]);
10661 emit_move_insn (operands[1], const0_rtx);
10663 emit_label (label);
10664 LABEL_NUSES (label) = 1;
10669 (define_expand "ashlsi3"
10670 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10671 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10672 (match_operand:QI 2 "nonmemory_operand" "")))
10673 (clobber (reg:CC 17))]
10675 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10677 (define_insn "*ashlsi3_1"
10678 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10679 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10680 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10681 (clobber (reg:CC 17))]
10682 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10685 switch (get_attr_type (insn))
10688 if (operands[2] != const1_rtx)
10690 if (!rtx_equal_p (operands[0], operands[1]))
10692 return \"add{l}\\t{%0, %0|%0, %0}\";
10698 if (REG_P (operands[2]))
10699 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10700 else if (GET_CODE (operands[2]) == CONST_INT
10701 && INTVAL (operands[2]) == 1
10702 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10703 return \"sal{l}\\t%0\";
10705 return \"sal{l}\\t{%2, %0|%0, %2}\";
10708 [(set (attr "type")
10709 (cond [(eq_attr "alternative" "1")
10710 (const_string "lea")
10711 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10713 (match_operand 0 "register_operand" ""))
10714 (match_operand 2 "const1_operand" ""))
10715 (const_string "alu")
10717 (const_string "ishift")))
10718 (set_attr "mode" "SI")])
10720 ;; Convert lea to the lea pattern to avoid flags dependency.
10722 [(set (match_operand 0 "register_operand" "")
10723 (ashift (match_operand 1 "register_operand" "")
10724 (match_operand:QI 2 "const_int_operand" "")))
10725 (clobber (reg:CC 17))]
10727 && true_regnum (operands[0]) != true_regnum (operands[1])"
10732 operands[0] = gen_lowpart (SImode, operands[0]);
10733 operands[1] = gen_lowpart (Pmode, operands[1]);
10734 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10736 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10737 if (Pmode != SImode)
10738 pat = gen_rtx_SUBREG (SImode, pat, 0);
10739 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10743 (define_insn "*ashlsi3_1_zext"
10744 [(set (match_operand:DI 0 "register_operand" "=r,r")
10745 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10746 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10747 (clobber (reg:CC 17))]
10748 "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
10751 switch (get_attr_type (insn))
10754 if (operands[2] != const1_rtx)
10756 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10762 if (REG_P (operands[2]))
10763 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10764 else if (GET_CODE (operands[2]) == CONST_INT
10765 && INTVAL (operands[2]) == 1
10766 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10767 return \"sal{l}\\t%k0\";
10769 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10772 [(set (attr "type")
10773 (cond [(eq_attr "alternative" "1")
10774 (const_string "lea")
10775 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10777 (match_operand 2 "const1_operand" ""))
10778 (const_string "alu")
10780 (const_string "ishift")))
10781 (set_attr "mode" "SI")])
10783 ;; Convert lea to the lea pattern to avoid flags dependency.
10785 [(set (match_operand:DI 0 "register_operand" "")
10786 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10787 (match_operand:QI 2 "const_int_operand" ""))))
10788 (clobber (reg:CC 17))]
10790 && true_regnum (operands[0]) != true_regnum (operands[1])"
10791 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10794 operands[1] = gen_lowpart (Pmode, operands[1]);
10795 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10799 ;; This pattern can't accept a variable shift count, since shifts by
10800 ;; zero don't affect the flags. We assume that shifts by constant
10801 ;; zero are optimized away.
10802 (define_insn "*ashlsi3_cmp"
10805 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10806 (match_operand:QI 2 "immediate_operand" "I"))
10808 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10809 (ashift:SI (match_dup 1) (match_dup 2)))]
10810 "ix86_match_ccmode (insn, CCGOCmode)
10811 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10814 switch (get_attr_type (insn))
10817 if (operands[2] != const1_rtx)
10819 return \"add{l}\\t{%0, %0|%0, %0}\";
10822 if (REG_P (operands[2]))
10823 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10824 else if (GET_CODE (operands[2]) == CONST_INT
10825 && INTVAL (operands[2]) == 1
10826 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10827 return \"sal{l}\\t%0\";
10829 return \"sal{l}\\t{%2, %0|%0, %2}\";
10832 [(set (attr "type")
10833 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10835 (match_operand 0 "register_operand" ""))
10836 (match_operand 2 "const1_operand" ""))
10837 (const_string "alu")
10839 (const_string "ishift")))
10840 (set_attr "mode" "SI")])
10842 (define_insn "*ashlsi3_cmp_zext"
10845 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10846 (match_operand:QI 2 "immediate_operand" "I"))
10848 (set (match_operand:DI 0 "register_operand" "=r")
10849 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10850 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10851 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10854 switch (get_attr_type (insn))
10857 if (operands[2] != const1_rtx)
10859 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10862 if (REG_P (operands[2]))
10863 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10864 else if (GET_CODE (operands[2]) == CONST_INT
10865 && INTVAL (operands[2]) == 1
10866 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10867 return \"sal{l}\\t%k0\";
10869 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10872 [(set (attr "type")
10873 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10875 (match_operand 2 "const1_operand" ""))
10876 (const_string "alu")
10878 (const_string "ishift")))
10879 (set_attr "mode" "SI")])
10881 (define_expand "ashlhi3"
10882 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10883 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10884 (match_operand:QI 2 "nonmemory_operand" "")))
10885 (clobber (reg:CC 17))]
10886 "TARGET_HIMODE_MATH"
10887 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10889 (define_insn "*ashlhi3_1_lea"
10890 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10891 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10892 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10893 (clobber (reg:CC 17))]
10894 "!TARGET_PARTIAL_REG_STALL
10895 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10898 switch (get_attr_type (insn))
10903 if (operands[2] != const1_rtx)
10905 return \"add{w}\\t{%0, %0|%0, %0}\";
10908 if (REG_P (operands[2]))
10909 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10910 else if (GET_CODE (operands[2]) == CONST_INT
10911 && INTVAL (operands[2]) == 1
10912 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10913 return \"sal{w}\\t%0\";
10915 return \"sal{w}\\t{%2, %0|%0, %2}\";
10918 [(set (attr "type")
10919 (cond [(eq_attr "alternative" "1")
10920 (const_string "lea")
10921 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10923 (match_operand 0 "register_operand" ""))
10924 (match_operand 2 "const1_operand" ""))
10925 (const_string "alu")
10927 (const_string "ishift")))
10928 (set_attr "mode" "HI,SI")])
10930 (define_insn "*ashlhi3_1"
10931 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10932 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10933 (match_operand:QI 2 "nonmemory_operand" "cI")))
10934 (clobber (reg:CC 17))]
10935 "TARGET_PARTIAL_REG_STALL
10936 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10939 switch (get_attr_type (insn))
10942 if (operands[2] != const1_rtx)
10944 return \"add{w}\\t{%0, %0|%0, %0}\";
10947 if (REG_P (operands[2]))
10948 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10949 else if (GET_CODE (operands[2]) == CONST_INT
10950 && INTVAL (operands[2]) == 1
10951 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10952 return \"sal{w}\\t%0\";
10954 return \"sal{w}\\t{%2, %0|%0, %2}\";
10957 [(set (attr "type")
10958 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10960 (match_operand 0 "register_operand" ""))
10961 (match_operand 2 "const1_operand" ""))
10962 (const_string "alu")
10964 (const_string "ishift")))
10965 (set_attr "mode" "HI")])
10967 ;; This pattern can't accept a variable shift count, since shifts by
10968 ;; zero don't affect the flags. We assume that shifts by constant
10969 ;; zero are optimized away.
10970 (define_insn "*ashlhi3_cmp"
10973 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10974 (match_operand:QI 2 "immediate_operand" "I"))
10976 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10977 (ashift:HI (match_dup 1) (match_dup 2)))]
10978 "ix86_match_ccmode (insn, CCGOCmode)
10979 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10982 switch (get_attr_type (insn))
10985 if (operands[2] != const1_rtx)
10987 return \"add{w}\\t{%0, %0|%0, %0}\";
10990 if (REG_P (operands[2]))
10991 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10992 else if (GET_CODE (operands[2]) == CONST_INT
10993 && INTVAL (operands[2]) == 1
10994 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10995 return \"sal{w}\\t%0\";
10997 return \"sal{w}\\t{%2, %0|%0, %2}\";
11000 [(set (attr "type")
11001 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11003 (match_operand 0 "register_operand" ""))
11004 (match_operand 2 "const1_operand" ""))
11005 (const_string "alu")
11007 (const_string "ishift")))
11008 (set_attr "mode" "HI")])
11010 (define_expand "ashlqi3"
11011 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11012 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11013 (match_operand:QI 2 "nonmemory_operand" "")))
11014 (clobber (reg:CC 17))]
11015 "TARGET_QIMODE_MATH"
11016 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11018 ;; %%% Potential partial reg stall on alternative 2. What to do?
11020 (define_insn "*ashlqi3_1_lea"
11021 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11022 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11023 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11024 (clobber (reg:CC 17))]
11025 "!TARGET_PARTIAL_REG_STALL
11026 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11029 switch (get_attr_type (insn))
11034 if (operands[2] != const1_rtx)
11036 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11037 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
11039 return \"add{b}\\t{%0, %0|%0, %0}\";
11042 if (REG_P (operands[2]))
11044 if (get_attr_mode (insn) == MODE_SI)
11045 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
11047 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11049 else if (GET_CODE (operands[2]) == CONST_INT
11050 && INTVAL (operands[2]) == 1
11051 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11053 if (get_attr_mode (insn) == MODE_SI)
11054 return \"sal{l}\\t%0\";
11056 return \"sal{b}\\t%0\";
11060 if (get_attr_mode (insn) == MODE_SI)
11061 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
11063 return \"sal{b}\\t{%2, %0|%0, %2}\";
11067 [(set (attr "type")
11068 (cond [(eq_attr "alternative" "2")
11069 (const_string "lea")
11070 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11072 (match_operand 0 "register_operand" ""))
11073 (match_operand 2 "const1_operand" ""))
11074 (const_string "alu")
11076 (const_string "ishift")))
11077 (set_attr "mode" "QI,SI,SI")])
11079 (define_insn "*ashlqi3_1"
11080 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11081 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11082 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11083 (clobber (reg:CC 17))]
11084 "TARGET_PARTIAL_REG_STALL
11085 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11088 switch (get_attr_type (insn))
11091 if (operands[2] != const1_rtx)
11093 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11094 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
11096 return \"add{b}\\t{%0, %0|%0, %0}\";
11099 if (REG_P (operands[2]))
11101 if (get_attr_mode (insn) == MODE_SI)
11102 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
11104 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11106 else if (GET_CODE (operands[2]) == CONST_INT
11107 && INTVAL (operands[2]) == 1
11108 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11110 if (get_attr_mode (insn) == MODE_SI)
11111 return \"sal{l}\\t%0\";
11113 return \"sal{b}\\t%0\";
11117 if (get_attr_mode (insn) == MODE_SI)
11118 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
11120 return \"sal{b}\\t{%2, %0|%0, %2}\";
11124 [(set (attr "type")
11125 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11127 (match_operand 0 "register_operand" ""))
11128 (match_operand 2 "const1_operand" ""))
11129 (const_string "alu")
11131 (const_string "ishift")))
11132 (set_attr "mode" "QI,SI")])
11134 ;; This pattern can't accept a variable shift count, since shifts by
11135 ;; zero don't affect the flags. We assume that shifts by constant
11136 ;; zero are optimized away.
11137 (define_insn "*ashlqi3_cmp"
11140 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11141 (match_operand:QI 2 "immediate_operand" "I"))
11143 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11144 (ashift:QI (match_dup 1) (match_dup 2)))]
11145 "ix86_match_ccmode (insn, CCGOCmode)
11146 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11149 switch (get_attr_type (insn))
11152 if (operands[2] != const1_rtx)
11154 return \"add{b}\\t{%0, %0|%0, %0}\";
11157 if (REG_P (operands[2]))
11158 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11159 else if (GET_CODE (operands[2]) == CONST_INT
11160 && INTVAL (operands[2]) == 1
11161 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11162 return \"sal{b}\\t%0\";
11164 return \"sal{b}\\t{%2, %0|%0, %2}\";
11167 [(set (attr "type")
11168 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11170 (match_operand 0 "register_operand" ""))
11171 (match_operand 2 "const1_operand" ""))
11172 (const_string "alu")
11174 (const_string "ishift")))
11175 (set_attr "mode" "QI")])
11177 ;; See comment above `ashldi3' about how this works.
11179 (define_expand "ashrdi3"
11180 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11181 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11182 (match_operand:QI 2 "nonmemory_operand" "")))
11183 (clobber (reg:CC 17))])]
11187 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11189 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11192 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11196 (define_insn "ashrdi3_63_rex64"
11197 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11198 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11199 (match_operand:DI 2 "const_int_operand" "i,i")))
11200 (clobber (reg:CC 17))]
11201 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11202 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11205 sar{q}\\t{%2, %0|%0, %2}"
11206 [(set_attr "type" "imovx,ishift")
11207 (set_attr "prefix_0f" "0,*")
11208 (set_attr "length_immediate" "0,*")
11209 (set_attr "modrm" "0,1")
11210 (set_attr "mode" "DI")])
11212 (define_insn "*ashrdi3_1_one_bit_rex64"
11213 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11214 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11215 (match_operand:QI 2 "const_int_1_operand" "")))
11216 (clobber (reg:CC 17))]
11217 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11218 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11220 [(set_attr "type" "ishift")
11221 (set (attr "length")
11222 (if_then_else (match_operand:DI 0 "register_operand" "")
11224 (const_string "*")))])
11226 (define_insn "*ashrdi3_1_rex64"
11227 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11228 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11229 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11230 (clobber (reg:CC 17))]
11231 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11233 sar{q}\\t{%2, %0|%0, %2}
11234 sar{q}\\t{%b2, %0|%0, %b2}"
11235 [(set_attr "type" "ishift")
11236 (set_attr "mode" "DI")])
11238 ;; This pattern can't accept a variable shift count, since shifts by
11239 ;; zero don't affect the flags. We assume that shifts by constant
11240 ;; zero are optimized away.
11241 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11244 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11245 (match_operand:QI 2 "const_int_1_operand" ""))
11247 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11248 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11249 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11250 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11251 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11253 [(set_attr "type" "ishift")
11254 (set (attr "length")
11255 (if_then_else (match_operand:DI 0 "register_operand" "")
11257 (const_string "*")))])
11259 ;; This pattern can't accept a variable shift count, since shifts by
11260 ;; zero don't affect the flags. We assume that shifts by constant
11261 ;; zero are optimized away.
11262 (define_insn "*ashrdi3_cmp_rex64"
11265 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11266 (match_operand:QI 2 "const_int_operand" "n"))
11268 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11269 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11270 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11271 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11272 "sar{q}\\t{%2, %0|%0, %2}"
11273 [(set_attr "type" "ishift")
11274 (set_attr "mode" "DI")])
11277 (define_insn "ashrdi3_1"
11278 [(set (match_operand:DI 0 "register_operand" "=r")
11279 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11280 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11281 (clobber (match_scratch:SI 3 "=&r"))
11282 (clobber (reg:CC 17))]
11283 "!TARGET_64BIT && TARGET_CMOVE"
11285 [(set_attr "type" "multi")])
11287 (define_insn "*ashrdi3_2"
11288 [(set (match_operand:DI 0 "register_operand" "=r")
11289 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11290 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11291 (clobber (reg:CC 17))]
11294 [(set_attr "type" "multi")])
11297 [(set (match_operand:DI 0 "register_operand" "")
11298 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11299 (match_operand:QI 2 "nonmemory_operand" "")))
11300 (clobber (match_scratch:SI 3 ""))
11301 (clobber (reg:CC 17))]
11302 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11304 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11307 [(set (match_operand:DI 0 "register_operand" "")
11308 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11309 (match_operand:QI 2 "nonmemory_operand" "")))
11310 (clobber (reg:CC 17))]
11311 "!TARGET_64BIT && reload_completed"
11313 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11315 (define_insn "x86_shrd_1"
11316 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11317 (ior:SI (ashiftrt:SI (match_dup 0)
11318 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11319 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11320 (minus:QI (const_int 32) (match_dup 2)))))
11321 (clobber (reg:CC 17))]
11324 shrd{l}\\t{%2, %1, %0|%0, %1, %2}
11325 shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
11326 [(set_attr "type" "ishift")
11327 (set_attr "prefix_0f" "1")
11328 (set_attr "pent_pair" "np")
11329 (set_attr "ppro_uops" "few")
11330 (set_attr "mode" "SI")])
11332 (define_expand "x86_shift_adj_3"
11333 [(use (match_operand:SI 0 "register_operand" ""))
11334 (use (match_operand:SI 1 "register_operand" ""))
11335 (use (match_operand:QI 2 "register_operand" ""))]
11339 rtx label = gen_label_rtx ();
11342 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11344 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11345 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11346 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11347 gen_rtx_LABEL_REF (VOIDmode, label),
11349 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11350 JUMP_LABEL (tmp) = label;
11352 emit_move_insn (operands[0], operands[1]);
11353 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11355 emit_label (label);
11356 LABEL_NUSES (label) = 1;
11361 (define_insn "ashrsi3_31"
11362 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11363 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11364 (match_operand:SI 2 "const_int_operand" "i,i")))
11365 (clobber (reg:CC 17))]
11366 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11367 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11370 sar{l}\\t{%2, %0|%0, %2}"
11371 [(set_attr "type" "imovx,ishift")
11372 (set_attr "prefix_0f" "0,*")
11373 (set_attr "length_immediate" "0,*")
11374 (set_attr "modrm" "0,1")
11375 (set_attr "mode" "SI")])
11377 (define_insn "*ashrsi3_31_zext"
11378 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11379 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11380 (match_operand:SI 2 "const_int_operand" "i,i"))))
11381 (clobber (reg:CC 17))]
11382 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11383 && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11386 sar{l}\\t{%2, %k0|%k0, %2}"
11387 [(set_attr "type" "imovx,ishift")
11388 (set_attr "prefix_0f" "0,*")
11389 (set_attr "length_immediate" "0,*")
11390 (set_attr "modrm" "0,1")
11391 (set_attr "mode" "SI")])
11393 (define_expand "ashrsi3"
11394 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11395 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11396 (match_operand:QI 2 "nonmemory_operand" "")))
11397 (clobber (reg:CC 17))]
11399 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11401 (define_insn "*ashrsi3_1_one_bit"
11402 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11403 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11404 (match_operand:QI 2 "const_int_1_operand" "")))
11405 (clobber (reg:CC 17))]
11406 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11407 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11409 [(set_attr "type" "ishift")
11410 (set (attr "length")
11411 (if_then_else (match_operand:SI 0 "register_operand" "")
11413 (const_string "*")))])
11415 (define_insn "*ashrsi3_1_one_bit_zext"
11416 [(set (match_operand:DI 0 "register_operand" "=r")
11417 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11418 (match_operand:QI 2 "const_int_1_operand" ""))))
11419 (clobber (reg:CC 17))]
11420 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11421 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11423 [(set_attr "type" "ishift")
11424 (set_attr "length" "2")])
11426 (define_insn "*ashrsi3_1"
11427 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11428 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11429 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11430 (clobber (reg:CC 17))]
11431 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11433 sar{l}\\t{%2, %0|%0, %2}
11434 sar{l}\\t{%b2, %0|%0, %b2}"
11435 [(set_attr "type" "ishift")
11436 (set_attr "mode" "SI")])
11438 (define_insn "*ashrsi3_1_zext"
11439 [(set (match_operand:DI 0 "register_operand" "=r,r")
11440 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11441 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11442 (clobber (reg:CC 17))]
11443 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11445 sar{l}\\t{%2, %k0|%k0, %2}
11446 sar{l}\\t{%b2, %k0|%k0, %b2}"
11447 [(set_attr "type" "ishift")
11448 (set_attr "mode" "SI")])
11450 ;; This pattern can't accept a variable shift count, since shifts by
11451 ;; zero don't affect the flags. We assume that shifts by constant
11452 ;; zero are optimized away.
11453 (define_insn "*ashrsi3_one_bit_cmp"
11456 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11457 (match_operand:QI 2 "const_int_1_operand" ""))
11459 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11460 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11461 "ix86_match_ccmode (insn, CCGOCmode)
11462 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11463 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11465 [(set_attr "type" "ishift")
11466 (set (attr "length")
11467 (if_then_else (match_operand:SI 0 "register_operand" "")
11469 (const_string "*")))])
11471 (define_insn "*ashrsi3_one_bit_cmp_zext"
11474 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11475 (match_operand:QI 2 "const_int_1_operand" ""))
11477 (set (match_operand:DI 0 "register_operand" "=r")
11478 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11479 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11480 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11481 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11483 [(set_attr "type" "ishift")
11484 (set_attr "length" "2")])
11486 ;; This pattern can't accept a variable shift count, since shifts by
11487 ;; zero don't affect the flags. We assume that shifts by constant
11488 ;; zero are optimized away.
11489 (define_insn "*ashrsi3_cmp"
11492 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11493 (match_operand:QI 2 "immediate_operand" "I"))
11495 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11496 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11497 "ix86_match_ccmode (insn, CCGOCmode)
11498 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11499 "sar{l}\\t{%2, %0|%0, %2}"
11500 [(set_attr "type" "ishift")
11501 (set_attr "mode" "SI")])
11503 (define_insn "*ashrsi3_cmp_zext"
11506 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11507 (match_operand:QI 2 "immediate_operand" "I"))
11509 (set (match_operand:DI 0 "register_operand" "=r")
11510 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11511 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11512 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11513 "sar{l}\\t{%2, %k0|%k0, %2}"
11514 [(set_attr "type" "ishift")
11515 (set_attr "mode" "SI")])
11517 (define_expand "ashrhi3"
11518 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11519 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11520 (match_operand:QI 2 "nonmemory_operand" "")))
11521 (clobber (reg:CC 17))]
11522 "TARGET_HIMODE_MATH"
11523 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11525 (define_insn "*ashrhi3_1_one_bit"
11526 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11527 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11528 (match_operand:QI 2 "const_int_1_operand" "")))
11529 (clobber (reg:CC 17))]
11530 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11531 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11533 [(set_attr "type" "ishift")
11534 (set (attr "length")
11535 (if_then_else (match_operand 0 "register_operand" "")
11537 (const_string "*")))])
11539 (define_insn "*ashrhi3_1"
11540 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11541 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11542 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11543 (clobber (reg:CC 17))]
11544 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11546 sar{w}\\t{%2, %0|%0, %2}
11547 sar{w}\\t{%b2, %0|%0, %b2}"
11548 [(set_attr "type" "ishift")
11549 (set_attr "mode" "HI")])
11551 ;; This pattern can't accept a variable shift count, since shifts by
11552 ;; zero don't affect the flags. We assume that shifts by constant
11553 ;; zero are optimized away.
11554 (define_insn "*ashrhi3_one_bit_cmp"
11557 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11558 (match_operand:QI 2 "const_int_1_operand" ""))
11560 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11561 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11562 "ix86_match_ccmode (insn, CCGOCmode)
11563 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11564 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11566 [(set_attr "type" "ishift")
11567 (set (attr "length")
11568 (if_then_else (match_operand 0 "register_operand" "")
11570 (const_string "*")))])
11572 ;; This pattern can't accept a variable shift count, since shifts by
11573 ;; zero don't affect the flags. We assume that shifts by constant
11574 ;; zero are optimized away.
11575 (define_insn "*ashrhi3_cmp"
11578 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11579 (match_operand:QI 2 "immediate_operand" "I"))
11581 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11582 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11583 "ix86_match_ccmode (insn, CCGOCmode)
11584 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11585 "sar{w}\\t{%2, %0|%0, %2}"
11586 [(set_attr "type" "ishift")
11587 (set_attr "mode" "HI")])
11589 (define_expand "ashrqi3"
11590 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11591 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11592 (match_operand:QI 2 "nonmemory_operand" "")))
11593 (clobber (reg:CC 17))]
11594 "TARGET_QIMODE_MATH"
11595 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11597 (define_insn "*ashrqi3_1_one_bit"
11598 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11599 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11600 (match_operand:QI 2 "const_int_1_operand" "")))
11601 (clobber (reg:CC 17))]
11602 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11603 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11605 [(set_attr "type" "ishift")
11606 (set (attr "length")
11607 (if_then_else (match_operand 0 "register_operand" "")
11609 (const_string "*")))])
11611 (define_insn "*ashrqi3_1"
11612 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11613 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11614 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11615 (clobber (reg:CC 17))]
11616 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11618 sar{b}\\t{%2, %0|%0, %2}
11619 sar{b}\\t{%b2, %0|%0, %b2}"
11620 [(set_attr "type" "ishift")
11621 (set_attr "mode" "QI")])
11623 ;; This pattern can't accept a variable shift count, since shifts by
11624 ;; zero don't affect the flags. We assume that shifts by constant
11625 ;; zero are optimized away.
11626 (define_insn "*ashrqi3_one_bit_cmp"
11629 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11630 (match_operand:QI 2 "const_int_1_operand" "I"))
11632 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11633 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11634 "ix86_match_ccmode (insn, CCGOCmode)
11635 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11636 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11638 [(set_attr "type" "ishift")
11639 (set (attr "length")
11640 (if_then_else (match_operand 0 "register_operand" "")
11642 (const_string "*")))])
11644 ;; This pattern can't accept a variable shift count, since shifts by
11645 ;; zero don't affect the flags. We assume that shifts by constant
11646 ;; zero are optimized away.
11647 (define_insn "*ashrqi3_cmp"
11650 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11651 (match_operand:QI 2 "immediate_operand" "I"))
11653 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11654 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11655 "ix86_match_ccmode (insn, CCGOCmode)
11656 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11657 "sar{b}\\t{%2, %0|%0, %2}"
11658 [(set_attr "type" "ishift")
11659 (set_attr "mode" "QI")])
11661 ;; Logical shift instructions
11663 ;; See comment above `ashldi3' about how this works.
11665 (define_expand "lshrdi3"
11666 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11667 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11668 (match_operand:QI 2 "nonmemory_operand" "")))
11669 (clobber (reg:CC 17))])]
11673 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11675 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11678 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11682 (define_insn "*lshrdi3_1_one_bit_rex64"
11683 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11684 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11685 (match_operand:QI 2 "const_int_1_operand" "")))
11686 (clobber (reg:CC 17))]
11687 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11688 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11690 [(set_attr "type" "ishift")
11691 (set (attr "length")
11692 (if_then_else (match_operand:DI 0 "register_operand" "")
11694 (const_string "*")))])
11696 (define_insn "*lshrdi3_1_rex64"
11697 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11698 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11699 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11700 (clobber (reg:CC 17))]
11701 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11703 shr{q}\\t{%2, %0|%0, %2}
11704 shr{q}\\t{%b2, %0|%0, %b2}"
11705 [(set_attr "type" "ishift")
11706 (set_attr "mode" "DI")])
11708 ;; This pattern can't accept a variable shift count, since shifts by
11709 ;; zero don't affect the flags. We assume that shifts by constant
11710 ;; zero are optimized away.
11711 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11714 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11715 (match_operand:QI 2 "const_int_1_operand" ""))
11717 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11718 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11719 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11720 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11721 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11723 [(set_attr "type" "ishift")
11724 (set (attr "length")
11725 (if_then_else (match_operand:DI 0 "register_operand" "")
11727 (const_string "*")))])
11729 ;; This pattern can't accept a variable shift count, since shifts by
11730 ;; zero don't affect the flags. We assume that shifts by constant
11731 ;; zero are optimized away.
11732 (define_insn "*lshrdi3_cmp_rex64"
11735 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11736 (match_operand:QI 2 "const_int_operand" "e"))
11738 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11739 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11740 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11741 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11742 "shr{q}\\t{%2, %0|%0, %2}"
11743 [(set_attr "type" "ishift")
11744 (set_attr "mode" "DI")])
11746 (define_insn "lshrdi3_1"
11747 [(set (match_operand:DI 0 "register_operand" "=r")
11748 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11749 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11750 (clobber (match_scratch:SI 3 "=&r"))
11751 (clobber (reg:CC 17))]
11752 "!TARGET_64BIT && TARGET_CMOVE"
11754 [(set_attr "type" "multi")])
11756 (define_insn "*lshrdi3_2"
11757 [(set (match_operand:DI 0 "register_operand" "=r")
11758 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11759 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11760 (clobber (reg:CC 17))]
11763 [(set_attr "type" "multi")])
11766 [(set (match_operand:DI 0 "register_operand" "")
11767 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11768 (match_operand:QI 2 "nonmemory_operand" "")))
11769 (clobber (match_scratch:SI 3 ""))
11770 (clobber (reg:CC 17))]
11771 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11773 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11776 [(set (match_operand:DI 0 "register_operand" "")
11777 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11778 (match_operand:QI 2 "nonmemory_operand" "")))
11779 (clobber (reg:CC 17))]
11780 "!TARGET_64BIT && reload_completed"
11782 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11784 (define_expand "lshrsi3"
11785 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11786 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11787 (match_operand:QI 2 "nonmemory_operand" "")))
11788 (clobber (reg:CC 17))]
11790 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11792 (define_insn "*lshrsi3_1_one_bit"
11793 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11794 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11795 (match_operand:QI 2 "const_int_1_operand" "")))
11796 (clobber (reg:CC 17))]
11797 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11798 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11800 [(set_attr "type" "ishift")
11801 (set (attr "length")
11802 (if_then_else (match_operand:SI 0 "register_operand" "")
11804 (const_string "*")))])
11806 (define_insn "*lshrsi3_1_one_bit_zext"
11807 [(set (match_operand:DI 0 "register_operand" "=r")
11808 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11809 (match_operand:QI 2 "const_int_1_operand" "")))
11810 (clobber (reg:CC 17))]
11811 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11812 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11814 [(set_attr "type" "ishift")
11815 (set_attr "length" "2")])
11817 (define_insn "*lshrsi3_1"
11818 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11819 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11820 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11821 (clobber (reg:CC 17))]
11822 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11824 shr{l}\\t{%2, %0|%0, %2}
11825 shr{l}\\t{%b2, %0|%0, %b2}"
11826 [(set_attr "type" "ishift")
11827 (set_attr "mode" "SI")])
11829 (define_insn "*lshrsi3_1_zext"
11830 [(set (match_operand:DI 0 "register_operand" "=r,r")
11832 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11833 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11834 (clobber (reg:CC 17))]
11835 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11837 shr{l}\\t{%2, %k0|%k0, %2}
11838 shr{l}\\t{%b2, %k0|%k0, %b2}"
11839 [(set_attr "type" "ishift")
11840 (set_attr "mode" "SI")])
11842 ;; This pattern can't accept a variable shift count, since shifts by
11843 ;; zero don't affect the flags. We assume that shifts by constant
11844 ;; zero are optimized away.
11845 (define_insn "*lshrsi3_one_bit_cmp"
11848 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11849 (match_operand:QI 2 "const_int_1_operand" ""))
11851 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11852 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11853 "ix86_match_ccmode (insn, CCGOCmode)
11854 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11855 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11857 [(set_attr "type" "ishift")
11858 (set (attr "length")
11859 (if_then_else (match_operand:SI 0 "register_operand" "")
11861 (const_string "*")))])
11863 (define_insn "*lshrsi3_cmp_one_bit_zext"
11866 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11867 (match_operand:QI 2 "const_int_1_operand" ""))
11869 (set (match_operand:DI 0 "register_operand" "=r")
11870 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11871 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11872 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11873 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11875 [(set_attr "type" "ishift")
11876 (set_attr "length" "2")])
11878 ;; This pattern can't accept a variable shift count, since shifts by
11879 ;; zero don't affect the flags. We assume that shifts by constant
11880 ;; zero are optimized away.
11881 (define_insn "*lshrsi3_cmp"
11884 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11885 (match_operand:QI 2 "immediate_operand" "I"))
11887 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11888 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11889 "ix86_match_ccmode (insn, CCGOCmode)
11890 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11891 "shr{l}\\t{%2, %0|%0, %2}"
11892 [(set_attr "type" "ishift")
11893 (set_attr "mode" "SI")])
11895 (define_insn "*lshrsi3_cmp_zext"
11898 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11899 (match_operand:QI 2 "immediate_operand" "I"))
11901 (set (match_operand:DI 0 "register_operand" "=r")
11902 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11903 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11904 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11905 "shr{l}\\t{%2, %k0|%k0, %2}"
11906 [(set_attr "type" "ishift")
11907 (set_attr "mode" "SI")])
11909 (define_expand "lshrhi3"
11910 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11911 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11912 (match_operand:QI 2 "nonmemory_operand" "")))
11913 (clobber (reg:CC 17))]
11914 "TARGET_HIMODE_MATH"
11915 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11917 (define_insn "*lshrhi3_1_one_bit"
11918 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11919 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11920 (match_operand:QI 2 "const_int_1_operand" "")))
11921 (clobber (reg:CC 17))]
11922 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11923 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11925 [(set_attr "type" "ishift")
11926 (set (attr "length")
11927 (if_then_else (match_operand 0 "register_operand" "")
11929 (const_string "*")))])
11931 (define_insn "*lshrhi3_1"
11932 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11933 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11934 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11935 (clobber (reg:CC 17))]
11936 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11938 shr{w}\\t{%2, %0|%0, %2}
11939 shr{w}\\t{%b2, %0|%0, %b2}"
11940 [(set_attr "type" "ishift")
11941 (set_attr "mode" "HI")])
11943 ;; This pattern can't accept a variable shift count, since shifts by
11944 ;; zero don't affect the flags. We assume that shifts by constant
11945 ;; zero are optimized away.
11946 (define_insn "*lshrhi3_one_bit_cmp"
11949 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11950 (match_operand:QI 2 "const_int_1_operand" ""))
11952 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11953 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11954 "ix86_match_ccmode (insn, CCGOCmode)
11955 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11956 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11958 [(set_attr "type" "ishift")
11959 (set (attr "length")
11960 (if_then_else (match_operand:SI 0 "register_operand" "")
11962 (const_string "*")))])
11964 ;; This pattern can't accept a variable shift count, since shifts by
11965 ;; zero don't affect the flags. We assume that shifts by constant
11966 ;; zero are optimized away.
11967 (define_insn "*lshrhi3_cmp"
11970 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11971 (match_operand:QI 2 "immediate_operand" "I"))
11973 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11974 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11975 "ix86_match_ccmode (insn, CCGOCmode)
11976 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11977 "shr{w}\\t{%2, %0|%0, %2}"
11978 [(set_attr "type" "ishift")
11979 (set_attr "mode" "HI")])
11981 (define_expand "lshrqi3"
11982 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11983 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11984 (match_operand:QI 2 "nonmemory_operand" "")))
11985 (clobber (reg:CC 17))]
11986 "TARGET_QIMODE_MATH"
11987 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11989 (define_insn "*lshrqi3_1_one_bit"
11990 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11991 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11992 (match_operand:QI 2 "const_int_1_operand" "")))
11993 (clobber (reg:CC 17))]
11994 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11995 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11997 [(set_attr "type" "ishift")
11998 (set (attr "length")
11999 (if_then_else (match_operand 0 "register_operand" "")
12001 (const_string "*")))])
12003 (define_insn "*lshrqi3_1"
12004 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12005 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12006 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12007 (clobber (reg:CC 17))]
12008 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12010 shr{b}\\t{%2, %0|%0, %2}
12011 shr{b}\\t{%b2, %0|%0, %b2}"
12012 [(set_attr "type" "ishift")
12013 (set_attr "mode" "QI")])
12015 ;; This pattern can't accept a variable shift count, since shifts by
12016 ;; zero don't affect the flags. We assume that shifts by constant
12017 ;; zero are optimized away.
12018 (define_insn "*lshrqi2_one_bit_cmp"
12021 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12022 (match_operand:QI 2 "const_int_1_operand" ""))
12024 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12025 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12026 "ix86_match_ccmode (insn, CCGOCmode)
12027 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
12028 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12030 [(set_attr "type" "ishift")
12031 (set (attr "length")
12032 (if_then_else (match_operand:SI 0 "register_operand" "")
12034 (const_string "*")))])
12036 ;; This pattern can't accept a variable shift count, since shifts by
12037 ;; zero don't affect the flags. We assume that shifts by constant
12038 ;; zero are optimized away.
12039 (define_insn "*lshrqi2_cmp"
12042 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12043 (match_operand:QI 2 "immediate_operand" "I"))
12045 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12046 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12047 "ix86_match_ccmode (insn, CCGOCmode)
12048 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12049 "shr{b}\\t{%2, %0|%0, %2}"
12050 [(set_attr "type" "ishift")
12051 (set_attr "mode" "QI")])
12053 ;; Rotate instructions
12055 (define_expand "rotldi3"
12056 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12057 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12058 (match_operand:QI 2 "nonmemory_operand" "")))
12059 (clobber (reg:CC 17))]
12061 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12063 (define_insn "*rotlsi3_1_one_bit_rex64"
12064 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12065 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12066 (match_operand:QI 2 "const_int_1_operand" "")))
12067 (clobber (reg:CC 17))]
12068 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12069 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12071 [(set_attr "type" "ishift")
12072 (set (attr "length")
12073 (if_then_else (match_operand:DI 0 "register_operand" "")
12075 (const_string "*")))])
12077 (define_insn "*rotldi3_1_rex64"
12078 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12079 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12080 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12081 (clobber (reg:CC 17))]
12082 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12084 rol{q}\\t{%2, %0|%0, %2}
12085 rol{q}\\t{%b2, %0|%0, %b2}"
12086 [(set_attr "type" "ishift")
12087 (set_attr "mode" "DI")])
12089 (define_expand "rotlsi3"
12090 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12091 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12092 (match_operand:QI 2 "nonmemory_operand" "")))
12093 (clobber (reg:CC 17))]
12095 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12097 (define_insn "*rotlsi3_1_one_bit"
12098 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12099 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12100 (match_operand:QI 2 "const_int_1_operand" "")))
12101 (clobber (reg:CC 17))]
12102 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12103 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12105 [(set_attr "type" "ishift")
12106 (set (attr "length")
12107 (if_then_else (match_operand:SI 0 "register_operand" "")
12109 (const_string "*")))])
12111 (define_insn "*rotlsi3_1_one_bit_zext"
12112 [(set (match_operand:DI 0 "register_operand" "=r")
12114 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12115 (match_operand:QI 2 "const_int_1_operand" ""))))
12116 (clobber (reg:CC 17))]
12117 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12118 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12120 [(set_attr "type" "ishift")
12121 (set_attr "length" "2")])
12123 (define_insn "*rotlsi3_1"
12124 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12125 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12126 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12127 (clobber (reg:CC 17))]
12128 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12130 rol{l}\\t{%2, %0|%0, %2}
12131 rol{l}\\t{%b2, %0|%0, %b2}"
12132 [(set_attr "type" "ishift")
12133 (set_attr "mode" "SI")])
12135 (define_insn "*rotlsi3_1_zext"
12136 [(set (match_operand:DI 0 "register_operand" "=r,r")
12138 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12139 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12140 (clobber (reg:CC 17))]
12141 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12143 rol{l}\\t{%2, %k0|%k0, %2}
12144 rol{l}\\t{%b2, %k0|%k0, %b2}"
12145 [(set_attr "type" "ishift")
12146 (set_attr "mode" "SI")])
12148 (define_expand "rotlhi3"
12149 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12150 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12151 (match_operand:QI 2 "nonmemory_operand" "")))
12152 (clobber (reg:CC 17))]
12153 "TARGET_HIMODE_MATH"
12154 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12156 (define_insn "*rotlhi3_1_one_bit"
12157 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12158 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12159 (match_operand:QI 2 "const_int_1_operand" "")))
12160 (clobber (reg:CC 17))]
12161 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12162 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12164 [(set_attr "type" "ishift")
12165 (set (attr "length")
12166 (if_then_else (match_operand 0 "register_operand" "")
12168 (const_string "*")))])
12170 (define_insn "*rotlhi3_1"
12171 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12172 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12173 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12174 (clobber (reg:CC 17))]
12175 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12177 rol{w}\\t{%2, %0|%0, %2}
12178 rol{w}\\t{%b2, %0|%0, %b2}"
12179 [(set_attr "type" "ishift")
12180 (set_attr "mode" "HI")])
12182 (define_expand "rotlqi3"
12183 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12184 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12185 (match_operand:QI 2 "nonmemory_operand" "")))
12186 (clobber (reg:CC 17))]
12187 "TARGET_QIMODE_MATH"
12188 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12190 (define_insn "*rotlqi3_1_one_bit"
12191 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12192 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12193 (match_operand:QI 2 "const_int_1_operand" "")))
12194 (clobber (reg:CC 17))]
12195 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12196 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12198 [(set_attr "type" "ishift")
12199 (set (attr "length")
12200 (if_then_else (match_operand 0 "register_operand" "")
12202 (const_string "*")))])
12204 (define_insn "*rotlqi3_1"
12205 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12206 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12207 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12208 (clobber (reg:CC 17))]
12209 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12211 rol{b}\\t{%2, %0|%0, %2}
12212 rol{b}\\t{%b2, %0|%0, %b2}"
12213 [(set_attr "type" "ishift")
12214 (set_attr "mode" "QI")])
12216 (define_expand "rotrdi3"
12217 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12218 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12219 (match_operand:QI 2 "nonmemory_operand" "")))
12220 (clobber (reg:CC 17))]
12222 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12224 (define_insn "*rotrdi3_1_one_bit_rex64"
12225 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12226 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12227 (match_operand:QI 2 "const_int_1_operand" "")))
12228 (clobber (reg:CC 17))]
12229 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12230 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12232 [(set_attr "type" "ishift")
12233 (set (attr "length")
12234 (if_then_else (match_operand:DI 0 "register_operand" "")
12236 (const_string "*")))])
12238 (define_insn "*rotrdi3_1_rex64"
12239 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12240 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12241 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12242 (clobber (reg:CC 17))]
12243 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12245 ror{q}\\t{%2, %0|%0, %2}
12246 ror{q}\\t{%b2, %0|%0, %b2}"
12247 [(set_attr "type" "ishift")
12248 (set_attr "mode" "DI")])
12250 (define_expand "rotrsi3"
12251 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12252 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12253 (match_operand:QI 2 "nonmemory_operand" "")))
12254 (clobber (reg:CC 17))]
12256 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12258 (define_insn "*rotrsi3_1_one_bit"
12259 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12260 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12261 (match_operand:QI 2 "const_int_1_operand" "")))
12262 (clobber (reg:CC 17))]
12263 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12264 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12266 [(set_attr "type" "ishift")
12267 (set (attr "length")
12268 (if_then_else (match_operand:SI 0 "register_operand" "")
12270 (const_string "*")))])
12272 (define_insn "*rotrsi3_1_one_bit_zext"
12273 [(set (match_operand:DI 0 "register_operand" "=r")
12275 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12276 (match_operand:QI 2 "const_int_1_operand" ""))))
12277 (clobber (reg:CC 17))]
12278 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12279 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12281 [(set_attr "type" "ishift")
12282 (set (attr "length")
12283 (if_then_else (match_operand:SI 0 "register_operand" "")
12285 (const_string "*")))])
12287 (define_insn "*rotrsi3_1"
12288 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12289 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12290 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12291 (clobber (reg:CC 17))]
12292 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12294 ror{l}\\t{%2, %0|%0, %2}
12295 ror{l}\\t{%b2, %0|%0, %b2}"
12296 [(set_attr "type" "ishift")
12297 (set_attr "mode" "SI")])
12299 (define_insn "*rotrsi3_1_zext"
12300 [(set (match_operand:DI 0 "register_operand" "=r,r")
12302 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12303 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12304 (clobber (reg:CC 17))]
12305 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12307 ror{l}\\t{%2, %k0|%k0, %2}
12308 ror{l}\\t{%b2, %k0|%k0, %b2}"
12309 [(set_attr "type" "ishift")
12310 (set_attr "mode" "SI")])
12312 (define_expand "rotrhi3"
12313 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12314 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12315 (match_operand:QI 2 "nonmemory_operand" "")))
12316 (clobber (reg:CC 17))]
12317 "TARGET_HIMODE_MATH"
12318 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12320 (define_insn "*rotrhi3_one_bit"
12321 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12322 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12323 (match_operand:QI 2 "const_int_1_operand" "")))
12324 (clobber (reg:CC 17))]
12325 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12326 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12328 [(set_attr "type" "ishift")
12329 (set (attr "length")
12330 (if_then_else (match_operand 0 "register_operand" "")
12332 (const_string "*")))])
12334 (define_insn "*rotrhi3"
12335 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12336 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12337 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12338 (clobber (reg:CC 17))]
12339 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12341 ror{w}\\t{%2, %0|%0, %2}
12342 ror{w}\\t{%b2, %0|%0, %b2}"
12343 [(set_attr "type" "ishift")
12344 (set_attr "mode" "HI")])
12346 (define_expand "rotrqi3"
12347 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12348 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12349 (match_operand:QI 2 "nonmemory_operand" "")))
12350 (clobber (reg:CC 17))]
12351 "TARGET_QIMODE_MATH"
12352 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12354 (define_insn "*rotrqi3_1_one_bit"
12355 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12356 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12357 (match_operand:QI 2 "const_int_1_operand" "")))
12358 (clobber (reg:CC 17))]
12359 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12360 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12362 [(set_attr "type" "ishift")
12363 (set (attr "length")
12364 (if_then_else (match_operand 0 "register_operand" "")
12366 (const_string "*")))])
12368 (define_insn "*rotrqi3_1"
12369 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12370 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12371 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12372 (clobber (reg:CC 17))]
12373 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12375 ror{b}\\t{%2, %0|%0, %2}
12376 ror{b}\\t{%b2, %0|%0, %b2}"
12377 [(set_attr "type" "ishift")
12378 (set_attr "mode" "QI")])
12380 ;; Bit set / bit test instructions
12382 (define_expand "extv"
12383 [(set (match_operand:SI 0 "register_operand" "")
12384 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12385 (match_operand:SI 2 "immediate_operand" "")
12386 (match_operand:SI 3 "immediate_operand" "")))]
12390 /* Handle extractions from %ah et al. */
12391 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12394 /* From mips.md: extract_bit_field doesn't verify that our source
12395 matches the predicate, so check it again here. */
12396 if (! register_operand (operands[1], VOIDmode))
12400 (define_expand "extzv"
12401 [(set (match_operand:SI 0 "register_operand" "")
12402 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12403 (match_operand:SI 2 "immediate_operand" "")
12404 (match_operand:SI 3 "immediate_operand" "")))]
12408 /* Handle extractions from %ah et al. */
12409 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12412 /* From mips.md: extract_bit_field doesn't verify that our source
12413 matches the predicate, so check it again here. */
12414 if (! register_operand (operands[1], VOIDmode))
12418 (define_expand "insv"
12419 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12420 (match_operand:SI 1 "immediate_operand" "")
12421 (match_operand:SI 2 "immediate_operand" ""))
12422 (match_operand:SI 3 "register_operand" ""))]
12426 /* Handle extractions from %ah et al. */
12427 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12430 /* From mips.md: insert_bit_field doesn't verify that our source
12431 matches the predicate, so check it again here. */
12432 if (! register_operand (operands[0], VOIDmode))
12436 ;; %%% bts, btr, btc, bt.
12438 ;; Store-flag instructions.
12440 ;; For all sCOND expanders, also expand the compare or test insn that
12441 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12443 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12444 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12445 ;; way, which can later delete the movzx if only QImode is needed.
12447 (define_expand "seq"
12448 [(set (match_operand:SI 0 "register_operand" "")
12449 (eq:SI (reg:CC 17) (const_int 0)))]
12451 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12453 (define_expand "sne"
12454 [(set (match_operand:SI 0 "register_operand" "")
12455 (ne:SI (reg:CC 17) (const_int 0)))]
12457 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12459 (define_expand "sgt"
12460 [(set (match_operand:SI 0 "register_operand" "")
12461 (gt:SI (reg:CC 17) (const_int 0)))]
12463 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12465 (define_expand "sgtu"
12466 [(set (match_operand:SI 0 "register_operand" "")
12467 (gtu:SI (reg:CC 17) (const_int 0)))]
12469 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12471 (define_expand "slt"
12472 [(set (match_operand:SI 0 "register_operand" "")
12473 (lt:SI (reg:CC 17) (const_int 0)))]
12475 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12477 (define_expand "sltu"
12478 [(set (match_operand:SI 0 "register_operand" "")
12479 (ltu:SI (reg:CC 17) (const_int 0)))]
12481 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12483 (define_expand "sge"
12484 [(set (match_operand:SI 0 "register_operand" "")
12485 (ge:SI (reg:CC 17) (const_int 0)))]
12487 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12489 (define_expand "sgeu"
12490 [(set (match_operand:SI 0 "register_operand" "")
12491 (geu:SI (reg:CC 17) (const_int 0)))]
12493 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12495 (define_expand "sle"
12496 [(set (match_operand:SI 0 "register_operand" "")
12497 (le:SI (reg:CC 17) (const_int 0)))]
12499 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12501 (define_expand "sleu"
12502 [(set (match_operand:SI 0 "register_operand" "")
12503 (leu:SI (reg:CC 17) (const_int 0)))]
12505 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12507 (define_expand "sunordered"
12508 [(set (match_operand:SI 0 "register_operand" "")
12509 (unordered:SI (reg:CC 17) (const_int 0)))]
12510 "TARGET_80387 || TARGET_SSE"
12511 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12513 (define_expand "sordered"
12514 [(set (match_operand:SI 0 "register_operand" "")
12515 (ordered:SI (reg:CC 17) (const_int 0)))]
12517 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12519 (define_expand "suneq"
12520 [(set (match_operand:SI 0 "register_operand" "")
12521 (uneq:SI (reg:CC 17) (const_int 0)))]
12522 "TARGET_80387 || TARGET_SSE"
12523 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12525 (define_expand "sunge"
12526 [(set (match_operand:SI 0 "register_operand" "")
12527 (unge:SI (reg:CC 17) (const_int 0)))]
12528 "TARGET_80387 || TARGET_SSE"
12529 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12531 (define_expand "sungt"
12532 [(set (match_operand:SI 0 "register_operand" "")
12533 (ungt:SI (reg:CC 17) (const_int 0)))]
12534 "TARGET_80387 || TARGET_SSE"
12535 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12537 (define_expand "sunle"
12538 [(set (match_operand:SI 0 "register_operand" "")
12539 (unle:SI (reg:CC 17) (const_int 0)))]
12540 "TARGET_80387 || TARGET_SSE"
12541 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12543 (define_expand "sunlt"
12544 [(set (match_operand:SI 0 "register_operand" "")
12545 (unlt:SI (reg:CC 17) (const_int 0)))]
12546 "TARGET_80387 || TARGET_SSE"
12547 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12549 (define_expand "sltgt"
12550 [(set (match_operand:SI 0 "register_operand" "")
12551 (ltgt:SI (reg:CC 17) (const_int 0)))]
12552 "TARGET_80387 || TARGET_SSE"
12553 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12555 (define_insn "*setcc_1"
12556 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12557 (match_operator:QI 1 "ix86_comparison_operator"
12558 [(reg 17) (const_int 0)]))]
12561 [(set_attr "type" "setcc")
12562 (set_attr "mode" "QI")])
12564 (define_insn "setcc_2"
12565 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12566 (match_operator:QI 1 "ix86_comparison_operator"
12567 [(reg 17) (const_int 0)]))]
12570 [(set_attr "type" "setcc")
12571 (set_attr "mode" "QI")])
12573 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12574 ;; subsequent logical operations are used to imitate conditional moves.
12575 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12576 ;; it directly. Futher holding this value in pseudo register might bring
12577 ;; problem in implicit normalization in spill code.
12578 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12579 ;; instructions after reload by splitting the conditional move patterns.
12581 (define_insn "*sse_setccsf"
12582 [(set (match_operand:SF 0 "register_operand" "=x")
12583 (match_operator:SF 1 "sse_comparison_operator"
12584 [(match_operand:SF 2 "register_operand" "0")
12585 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12586 "TARGET_SSE && reload_completed"
12587 "cmp%D1ss\\t{%3, %0|%0, %3}"
12588 [(set_attr "type" "sse")
12589 (set_attr "mode" "SF")])
12591 (define_insn "*sse_setccdf"
12592 [(set (match_operand:DF 0 "register_operand" "=Y")
12593 (match_operator:DF 1 "sse_comparison_operator"
12594 [(match_operand:DF 2 "register_operand" "0")
12595 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12596 "TARGET_SSE2 && reload_completed"
12597 "cmp%D1sd\\t{%3, %0|%0, %3}"
12598 [(set_attr "type" "sse")
12599 (set_attr "mode" "DF")])
12601 ;; Basic conditional jump instructions.
12602 ;; We ignore the overflow flag for signed branch instructions.
12604 ;; For all bCOND expanders, also expand the compare or test insn that
12605 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12607 (define_expand "beq"
12609 (if_then_else (match_dup 1)
12610 (label_ref (match_operand 0 "" ""))
12613 "ix86_expand_branch (EQ, operands[0]); DONE;")
12615 (define_expand "bne"
12617 (if_then_else (match_dup 1)
12618 (label_ref (match_operand 0 "" ""))
12621 "ix86_expand_branch (NE, operands[0]); DONE;")
12623 (define_expand "bgt"
12625 (if_then_else (match_dup 1)
12626 (label_ref (match_operand 0 "" ""))
12629 "ix86_expand_branch (GT, operands[0]); DONE;")
12631 (define_expand "bgtu"
12633 (if_then_else (match_dup 1)
12634 (label_ref (match_operand 0 "" ""))
12637 "ix86_expand_branch (GTU, operands[0]); DONE;")
12639 (define_expand "blt"
12641 (if_then_else (match_dup 1)
12642 (label_ref (match_operand 0 "" ""))
12645 "ix86_expand_branch (LT, operands[0]); DONE;")
12647 (define_expand "bltu"
12649 (if_then_else (match_dup 1)
12650 (label_ref (match_operand 0 "" ""))
12653 "ix86_expand_branch (LTU, operands[0]); DONE;")
12655 (define_expand "bge"
12657 (if_then_else (match_dup 1)
12658 (label_ref (match_operand 0 "" ""))
12661 "ix86_expand_branch (GE, operands[0]); DONE;")
12663 (define_expand "bgeu"
12665 (if_then_else (match_dup 1)
12666 (label_ref (match_operand 0 "" ""))
12669 "ix86_expand_branch (GEU, operands[0]); DONE;")
12671 (define_expand "ble"
12673 (if_then_else (match_dup 1)
12674 (label_ref (match_operand 0 "" ""))
12677 "ix86_expand_branch (LE, operands[0]); DONE;")
12679 (define_expand "bleu"
12681 (if_then_else (match_dup 1)
12682 (label_ref (match_operand 0 "" ""))
12685 "ix86_expand_branch (LEU, operands[0]); DONE;")
12687 (define_expand "bunordered"
12689 (if_then_else (match_dup 1)
12690 (label_ref (match_operand 0 "" ""))
12692 "TARGET_80387 || TARGET_SSE"
12693 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12695 (define_expand "bordered"
12697 (if_then_else (match_dup 1)
12698 (label_ref (match_operand 0 "" ""))
12700 "TARGET_80387 || TARGET_SSE"
12701 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12703 (define_expand "buneq"
12705 (if_then_else (match_dup 1)
12706 (label_ref (match_operand 0 "" ""))
12708 "TARGET_80387 || TARGET_SSE"
12709 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12711 (define_expand "bunge"
12713 (if_then_else (match_dup 1)
12714 (label_ref (match_operand 0 "" ""))
12716 "TARGET_80387 || TARGET_SSE"
12717 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12719 (define_expand "bungt"
12721 (if_then_else (match_dup 1)
12722 (label_ref (match_operand 0 "" ""))
12724 "TARGET_80387 || TARGET_SSE"
12725 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12727 (define_expand "bunle"
12729 (if_then_else (match_dup 1)
12730 (label_ref (match_operand 0 "" ""))
12732 "TARGET_80387 || TARGET_SSE"
12733 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12735 (define_expand "bunlt"
12737 (if_then_else (match_dup 1)
12738 (label_ref (match_operand 0 "" ""))
12740 "TARGET_80387 || TARGET_SSE"
12741 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12743 (define_expand "bltgt"
12745 (if_then_else (match_dup 1)
12746 (label_ref (match_operand 0 "" ""))
12748 "TARGET_80387 || TARGET_SSE"
12749 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12751 (define_insn "*jcc_1"
12753 (if_then_else (match_operator 1 "ix86_comparison_operator"
12754 [(reg 17) (const_int 0)])
12755 (label_ref (match_operand 0 "" ""))
12759 [(set_attr "type" "ibr")
12760 (set (attr "prefix_0f")
12761 (if_then_else (and (ge (minus (match_dup 0) (pc))
12763 (lt (minus (match_dup 0) (pc))
12768 (define_insn "*jcc_2"
12770 (if_then_else (match_operator 1 "ix86_comparison_operator"
12771 [(reg 17) (const_int 0)])
12773 (label_ref (match_operand 0 "" ""))))]
12776 [(set_attr "type" "ibr")
12777 (set (attr "prefix_0f")
12778 (if_then_else (and (ge (minus (match_dup 0) (pc))
12780 (lt (minus (match_dup 0) (pc))
12785 ;; Define combination compare-and-branch fp compare instructions to use
12786 ;; during early optimization. Splitting the operation apart early makes
12787 ;; for bad code when we want to reverse the operation.
12789 (define_insn "*fp_jcc_1"
12791 (if_then_else (match_operator 0 "comparison_operator"
12792 [(match_operand 1 "register_operand" "f")
12793 (match_operand 2 "register_operand" "f")])
12794 (label_ref (match_operand 3 "" ""))
12796 (clobber (reg:CCFP 18))
12797 (clobber (reg:CCFP 17))]
12798 "TARGET_CMOVE && TARGET_80387
12799 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12800 && FLOAT_MODE_P (GET_MODE (operands[1]))
12801 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12804 (define_insn "*fp_jcc_1_sse"
12806 (if_then_else (match_operator 0 "comparison_operator"
12807 [(match_operand 1 "register_operand" "f#x,x#f")
12808 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12809 (label_ref (match_operand 3 "" ""))
12811 (clobber (reg:CCFP 18))
12812 (clobber (reg:CCFP 17))]
12814 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12815 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12818 (define_insn "*fp_jcc_1_sse_only"
12820 (if_then_else (match_operator 0 "comparison_operator"
12821 [(match_operand 1 "register_operand" "x")
12822 (match_operand 2 "nonimmediate_operand" "xm")])
12823 (label_ref (match_operand 3 "" ""))
12825 (clobber (reg:CCFP 18))
12826 (clobber (reg:CCFP 17))]
12827 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12828 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12831 (define_insn "*fp_jcc_2"
12833 (if_then_else (match_operator 0 "comparison_operator"
12834 [(match_operand 1 "register_operand" "f")
12835 (match_operand 2 "register_operand" "f")])
12837 (label_ref (match_operand 3 "" ""))))
12838 (clobber (reg:CCFP 18))
12839 (clobber (reg:CCFP 17))]
12840 "TARGET_CMOVE && TARGET_80387
12841 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12842 && FLOAT_MODE_P (GET_MODE (operands[1]))
12843 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12846 (define_insn "*fp_jcc_2_sse"
12848 (if_then_else (match_operator 0 "comparison_operator"
12849 [(match_operand 1 "register_operand" "f#x,x#f")
12850 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12852 (label_ref (match_operand 3 "" ""))))
12853 (clobber (reg:CCFP 18))
12854 (clobber (reg:CCFP 17))]
12856 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12857 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12860 (define_insn "*fp_jcc_2_sse_only"
12862 (if_then_else (match_operator 0 "comparison_operator"
12863 [(match_operand 1 "register_operand" "x")
12864 (match_operand 2 "nonimmediate_operand" "xm")])
12866 (label_ref (match_operand 3 "" ""))))
12867 (clobber (reg:CCFP 18))
12868 (clobber (reg:CCFP 17))]
12869 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12870 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12873 (define_insn "*fp_jcc_3"
12875 (if_then_else (match_operator 0 "comparison_operator"
12876 [(match_operand 1 "register_operand" "f")
12877 (match_operand 2 "nonimmediate_operand" "fm")])
12878 (label_ref (match_operand 3 "" ""))
12880 (clobber (reg:CCFP 18))
12881 (clobber (reg:CCFP 17))
12882 (clobber (match_scratch:HI 4 "=a"))]
12884 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12885 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12886 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12887 && SELECT_CC_MODE (GET_CODE (operands[0]),
12888 operands[1], operands[2]) == CCFPmode"
12891 (define_insn "*fp_jcc_4"
12893 (if_then_else (match_operator 0 "comparison_operator"
12894 [(match_operand 1 "register_operand" "f")
12895 (match_operand 2 "nonimmediate_operand" "fm")])
12897 (label_ref (match_operand 3 "" ""))))
12898 (clobber (reg:CCFP 18))
12899 (clobber (reg:CCFP 17))
12900 (clobber (match_scratch:HI 4 "=a"))]
12902 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12903 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12904 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12905 && SELECT_CC_MODE (GET_CODE (operands[0]),
12906 operands[1], operands[2]) == CCFPmode"
12909 (define_insn "*fp_jcc_5"
12911 (if_then_else (match_operator 0 "comparison_operator"
12912 [(match_operand 1 "register_operand" "f")
12913 (match_operand 2 "register_operand" "f")])
12914 (label_ref (match_operand 3 "" ""))
12916 (clobber (reg:CCFP 18))
12917 (clobber (reg:CCFP 17))
12918 (clobber (match_scratch:HI 4 "=a"))]
12920 && FLOAT_MODE_P (GET_MODE (operands[1]))
12921 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12924 (define_insn "*fp_jcc_6"
12926 (if_then_else (match_operator 0 "comparison_operator"
12927 [(match_operand 1 "register_operand" "f")
12928 (match_operand 2 "register_operand" "f")])
12930 (label_ref (match_operand 3 "" ""))))
12931 (clobber (reg:CCFP 18))
12932 (clobber (reg:CCFP 17))
12933 (clobber (match_scratch:HI 4 "=a"))]
12935 && FLOAT_MODE_P (GET_MODE (operands[1]))
12936 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12941 (if_then_else (match_operator 0 "comparison_operator"
12942 [(match_operand 1 "register_operand" "")
12943 (match_operand 2 "nonimmediate_operand" "")])
12944 (match_operand 3 "" "")
12945 (match_operand 4 "" "")))
12946 (clobber (reg:CCFP 18))
12947 (clobber (reg:CCFP 17))]
12952 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12953 operands[3], operands[4], NULL_RTX);
12959 (if_then_else (match_operator 0 "comparison_operator"
12960 [(match_operand 1 "register_operand" "")
12961 (match_operand 2 "nonimmediate_operand" "")])
12962 (match_operand 3 "" "")
12963 (match_operand 4 "" "")))
12964 (clobber (reg:CCFP 18))
12965 (clobber (reg:CCFP 17))
12966 (clobber (match_scratch:HI 5 "=a"))]
12969 (if_then_else (match_dup 6)
12974 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12975 operands[3], operands[4], operands[5]);
12979 ;; Unconditional and other jump instructions
12981 (define_insn "jump"
12983 (label_ref (match_operand 0 "" "")))]
12986 [(set_attr "type" "ibr")])
12988 (define_insn "indirect_jump"
12989 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
12992 [(set_attr "type" "ibr")
12993 (set_attr "length_immediate" "0")])
12995 (define_insn "tablejump"
12996 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
12997 (use (label_ref (match_operand 1 "" "")))]
13000 [(set_attr "type" "ibr")
13001 (set_attr "length_immediate" "0")])
13003 ;; Implement switch statements when generating PIC code. Switches are
13004 ;; implemented by `tablejump' when not using -fpic.
13006 ;; Emit code here to do the range checking and make the index zero based.
13008 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
13009 ;; two rules below:
13011 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
13013 ;; 1. An expression involving an external reference may only use the
13014 ;; addition operator, and only with an assembly-time constant.
13015 ;; The example above satisfies this because ".-.L2" is a constant.
13017 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
13018 ;; given the value of "GOT - .", where GOT is the actual address of
13019 ;; the Global Offset Table. Therefore, the .long above actually
13020 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
13021 ;; expression "GOT - .L2" by itself would generate an error from as(1).
13023 ;; The pattern below emits code that looks like this:
13026 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
13029 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
13030 ;; the addr_diff_vec is known to be part of this module.
13032 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
13033 ;; evaluates to just ".L2".
13035 (define_expand "casesi"
13036 [(set (match_dup 5)
13037 (match_operand:SI 0 "general_operand" ""))
13038 (parallel [(set (match_dup 6)
13039 (minus:SI (match_dup 5)
13040 (match_operand:SI 1 "general_operand" "")))
13041 (clobber (reg:CC 17))])
13043 (compare:CC (match_dup 6)
13044 (match_operand:SI 2 "general_operand" "")))
13046 (if_then_else (gtu (reg:CC 17)
13048 (label_ref (match_operand 4 "" ""))
13051 [(set (match_dup 7)
13052 (minus:SI (match_dup 8)
13053 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
13055 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
13056 (clobber (reg:CC 17))])
13057 (parallel [(set (pc) (match_dup 7))
13058 (use (label_ref (match_dup 3)))])]
13062 operands[5] = gen_reg_rtx (SImode);
13063 operands[6] = gen_reg_rtx (SImode);
13064 operands[7] = gen_reg_rtx (SImode);
13065 operands[8] = pic_offset_table_rtx;
13066 current_function_uses_pic_offset_table = 1;
13069 (define_insn "*tablejump_pic"
13070 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13071 (use (label_ref (match_operand 1 "" "")))]
13074 [(set_attr "type" "ibr")
13075 (set_attr "length_immediate" "0")])
13077 ;; Loop instruction
13079 ;; This is all complicated by the fact that since this is a jump insn
13080 ;; we must handle our own reloads.
13082 (define_expand "doloop_end"
13083 [(use (match_operand 0 "" "")) ; loop pseudo
13084 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13085 (use (match_operand 2 "" "")) ; max iterations
13086 (use (match_operand 3 "" "")) ; loop level
13087 (use (match_operand 4 "" ""))] ; label
13088 "TARGET_USE_LOOP && !TARGET_64BIT"
13091 /* Only use cloop on innermost loops. */
13092 if (INTVAL (operands[3]) > 1)
13094 if (GET_MODE (operands[0]) != SImode)
13096 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13101 (define_insn "doloop_end_internal"
13103 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13105 (label_ref (match_operand 0 "" ""))
13107 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13108 (plus:SI (match_dup 1)
13110 (clobber (match_scratch:SI 3 "=X,X,r"))
13111 (clobber (reg:CC 17))]
13112 "TARGET_USE_LOOP && !TARGET_64BIT"
13115 if (which_alternative != 0)
13117 if (get_attr_length (insn) == 2)
13118 return \"loop\\t%l0\";
13120 return \"dec{l}\\t%1\;jne\\t%l0\";
13122 [(set_attr "ppro_uops" "many")
13124 (if_then_else (and (eq_attr "alternative" "0")
13125 (and (ge (minus (match_dup 0) (pc))
13127 (lt (minus (match_dup 0) (pc))
13129 (const_string "ibr")
13130 (const_string "multi")))])
13134 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13136 (match_operand 0 "" "")
13139 (plus:SI (match_dup 1)
13141 (clobber (match_scratch:SI 2 ""))
13142 (clobber (reg:CC 17))]
13143 "TARGET_USE_LOOP && !TARGET_64BIT
13144 && reload_completed
13145 && REGNO (operands[1]) != 2"
13146 [(parallel [(set (reg:CCZ 17)
13147 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13149 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13150 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13157 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13159 (match_operand 0 "" "")
13161 (set (match_operand:SI 2 "nonimmediate_operand" "")
13162 (plus:SI (match_dup 1)
13164 (clobber (match_scratch:SI 3 ""))
13165 (clobber (reg:CC 17))]
13166 "TARGET_USE_LOOP && !TARGET_64BIT
13167 && reload_completed
13168 && (! REG_P (operands[2])
13169 || ! rtx_equal_p (operands[1], operands[2]))"
13170 [(set (match_dup 3) (match_dup 1))
13171 (parallel [(set (reg:CCZ 17)
13172 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13174 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13175 (set (match_dup 2) (match_dup 3))
13176 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13181 ;; Call instructions.
13183 ;; The predicates normally associated with named expanders are not properly
13184 ;; checked for calls. This is a bug in the generic code, but it isn't that
13185 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13187 ;; Call subroutine returning no value.
13189 (define_expand "call_pop"
13190 [(parallel [(call (match_operand:QI 0 "" "")
13191 (match_operand:SI 1 "" ""))
13193 (plus:SI (reg:SI 7)
13194 (match_operand:SI 3 "" "")))])]
13198 if (operands[3] == const0_rtx)
13200 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
13203 /* Static functions and indirect calls don't need
13204 current_function_uses_pic_offset_table. */
13206 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13207 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13208 current_function_uses_pic_offset_table = 1;
13209 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13210 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13215 (define_insn "*call_pop_0"
13216 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13217 (match_operand:SI 1 "" ""))
13218 (set (reg:SI 7) (plus:SI (reg:SI 7)
13219 (match_operand:SI 2 "immediate_operand" "")))]
13223 if (SIBLING_CALL_P (insn))
13224 return \"jmp\\t%P0\";
13226 return \"call\\t%P0\";
13228 [(set_attr "type" "call")])
13230 (define_insn "*call_pop_1"
13231 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13232 (match_operand:SI 1 "" ""))
13233 (set (reg:SI 7) (plus:SI (reg:SI 7)
13234 (match_operand:SI 2 "immediate_operand" "i")))]
13238 if (constant_call_address_operand (operands[0], Pmode))
13240 if (SIBLING_CALL_P (insn))
13241 return \"jmp\\t%P0\";
13243 return \"call\\t%P0\";
13245 if (SIBLING_CALL_P (insn))
13246 return \"jmp\\t%A0\";
13248 return \"call\\t%A0\";
13250 [(set_attr "type" "call")])
13252 (define_expand "call"
13253 [(call (match_operand:QI 0 "" "")
13254 (match_operand 1 "" ""))
13255 (use (match_operand 2 "" ""))]
13256 ;; Operand 1 not used on the i386.
13261 /* Static functions and indirect calls don't need
13262 current_function_uses_pic_offset_table. */
13264 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13265 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13266 current_function_uses_pic_offset_table = 1;
13268 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13269 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13270 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
13272 rtx reg = gen_rtx_REG (QImode, 0);
13273 emit_move_insn (reg, operands[2]);
13274 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13275 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13278 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13282 (define_expand "call_exp"
13283 [(call (match_operand:QI 0 "" "")
13284 (match_operand 1 "" ""))]
13288 (define_insn "*call_0"
13289 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13290 (match_operand 1 "" ""))]
13294 if (SIBLING_CALL_P (insn))
13295 return \"jmp\\t%P0\";
13297 return \"call\\t%P0\";
13299 [(set_attr "type" "call")])
13301 (define_insn "*call_1"
13302 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13303 (match_operand 1 "" ""))]
13307 if (constant_call_address_operand (operands[0], QImode))
13309 if (SIBLING_CALL_P (insn))
13310 return \"jmp\\t%P0\";
13312 return \"call\\t%P0\";
13314 if (SIBLING_CALL_P (insn))
13315 return \"jmp\\t%A0\";
13317 return \"call\\t%A0\";
13319 [(set_attr "type" "call")])
13321 (define_insn "*call_1_rex64"
13322 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13323 (match_operand 1 "" ""))]
13327 if (constant_call_address_operand (operands[0], QImode))
13329 if (SIBLING_CALL_P (insn))
13330 return \"jmp\\t%P0\";
13332 return \"call\\t%P0\";
13334 if (SIBLING_CALL_P (insn))
13335 return \"jmp\\t%A0\";
13337 return \"call\\t%A0\";
13339 [(set_attr "type" "call")])
13341 ;; Call subroutine, returning value in operand 0
13342 ;; (which must be a hard register).
13344 (define_expand "call_value_pop"
13345 [(parallel [(set (match_operand 0 "" "")
13346 (call (match_operand:QI 1 "" "")
13347 (match_operand:SI 2 "" "")))
13349 (plus:SI (reg:SI 7)
13350 (match_operand:SI 4 "" "")))])]
13354 if (operands[4] == const0_rtx)
13356 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
13360 /* Static functions and indirect calls don't need
13361 current_function_uses_pic_offset_table. */
13363 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13364 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13365 current_function_uses_pic_offset_table = 1;
13366 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13367 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13370 (define_expand "call_value"
13371 [(set (match_operand 0 "" "")
13372 (call (match_operand:QI 1 "" "")
13373 (match_operand:SI 2 "" "")))
13374 (use (match_operand:SI 3 "" ""))]
13375 ;; Operand 2 not used on the i386.
13380 /* Static functions and indirect calls don't need
13381 current_function_uses_pic_offset_table. */
13383 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13384 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13385 current_function_uses_pic_offset_table = 1;
13386 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13387 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13388 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
13390 rtx reg = gen_rtx_REG (QImode, 0);
13391 emit_move_insn (reg, operands[3]);
13392 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13394 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13397 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13402 (define_expand "call_value_exp"
13403 [(set (match_operand 0 "" "")
13404 (call (match_operand:QI 1 "" "")
13405 (match_operand:SI 2 "" "")))]
13409 ;; Call subroutine returning any type.
13411 (define_expand "untyped_call"
13412 [(parallel [(call (match_operand 0 "" "")
13414 (match_operand 1 "" "")
13415 (match_operand 2 "" "")])]
13421 /* In order to give reg-stack an easier job in validating two
13422 coprocessor registers as containing a possible return value,
13423 simply pretend the untyped call returns a complex long double
13426 emit_call_insn (TARGET_80387
13427 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13428 operands[0], const0_rtx,
13429 GEN_INT (SSE_REGPARM_MAX - 1))
13430 : gen_call (operands[0], const0_rtx,
13431 GEN_INT (SSE_REGPARM_MAX - 1)));
13433 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13435 rtx set = XVECEXP (operands[2], 0, i);
13436 emit_move_insn (SET_DEST (set), SET_SRC (set));
13439 /* The optimizer does not know that the call sets the function value
13440 registers we stored in the result block. We avoid problems by
13441 claiming that all hard registers are used and clobbered at this
13443 emit_insn (gen_blockage ());
13448 ;; Prologue and epilogue instructions
13450 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13451 ;; all of memory. This blocks insns from being moved across this point.
13453 (define_insn "blockage"
13454 [(unspec_volatile [(const_int 0)] 0)]
13457 [(set_attr "length" "0")])
13459 ;; Insn emitted into the body of a function to return from a function.
13460 ;; This is only done if the function's epilogue is known to be simple.
13461 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13463 (define_expand "return"
13465 "ix86_can_use_return_insn_p ()"
13468 if (current_function_pops_args)
13470 rtx popc = GEN_INT (current_function_pops_args);
13471 emit_jump_insn (gen_return_pop_internal (popc));
13476 (define_insn "return_internal"
13480 [(set_attr "length" "1")
13481 (set_attr "length_immediate" "0")
13482 (set_attr "modrm" "0")])
13484 (define_insn "return_pop_internal"
13486 (use (match_operand:SI 0 "const_int_operand" ""))]
13489 [(set_attr "length" "3")
13490 (set_attr "length_immediate" "2")
13491 (set_attr "modrm" "0")])
13493 (define_insn "return_indirect_internal"
13495 (use (match_operand:SI 0 "register_operand" "r"))]
13498 [(set_attr "type" "ibr")
13499 (set_attr "length_immediate" "0")])
13505 [(set_attr "length" "1")
13506 (set_attr "length_immediate" "0")
13507 (set_attr "modrm" "0")
13508 (set_attr "ppro_uops" "one")])
13510 (define_expand "prologue"
13513 "ix86_expand_prologue (); DONE;")
13515 (define_insn "prologue_set_got"
13516 [(set (match_operand:SI 0 "register_operand" "=r")
13517 (unspec_volatile:SI
13518 [(plus:SI (match_dup 0)
13519 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13520 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13521 (clobber (reg:CC 17))]
13525 if (GET_CODE (operands[2]) == LABEL_REF)
13526 operands[2] = XEXP (operands[2], 0);
13527 if (TARGET_DEEP_BRANCH_PREDICTION)
13528 return \"add{l}\\t{%1, %0|%0, %1}\";
13530 return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
13532 [(set_attr "type" "alu")
13533 ; Since this insn may have two constant operands, we must set the
13535 (set_attr "length_immediate" "4")
13536 (set_attr "mode" "SI")])
13538 (define_insn "prologue_get_pc"
13539 [(set (match_operand:SI 0 "register_operand" "=r")
13540 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13544 if (GET_CODE (operands[1]) == LABEL_REF)
13545 operands[1] = XEXP (operands[1], 0);
13546 output_asm_insn (\"call\\t%X1\", operands);
13547 if (! TARGET_DEEP_BRANCH_PREDICTION)
13549 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
13550 CODE_LABEL_NUMBER (operands[1]));
13554 [(set_attr "type" "multi")])
13556 (define_expand "epilogue"
13559 "ix86_expand_epilogue (1); DONE;")
13561 (define_expand "sibcall_epilogue"
13564 "ix86_expand_epilogue (0); DONE;")
13566 (define_expand "eh_return"
13567 [(use (match_operand 0 "register_operand" ""))
13568 (use (match_operand 1 "register_operand" ""))]
13572 rtx tmp, sa = operands[0], ra = operands[1];
13574 /* Tricky bit: we write the address of the handler to which we will
13575 be returning into someone else's stack frame, one word below the
13576 stack address we wish to restore. */
13577 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13578 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13579 tmp = gen_rtx_MEM (Pmode, tmp);
13580 emit_move_insn (tmp, ra);
13582 emit_insn (gen_eh_return_1 (sa));
13587 (define_insn_and_split "eh_return_1"
13588 [(unspec_volatile [(match_operand 0 "register_operand" "c")] 13)]
13593 "ix86_expand_epilogue (2); DONE;")
13595 (define_insn "leave"
13596 [(set (reg:SI 7) (reg:SI 6))
13597 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
13600 [(set_attr "length_immediate" "0")
13601 (set_attr "length" "1")
13602 (set_attr "modrm" "0")
13603 (set_attr "modrm" "0")
13604 (set_attr "athlon_decode" "vector")
13605 (set_attr "ppro_uops" "few")])
13607 (define_insn "leave_rex64"
13608 [(set (reg:DI 7) (reg:DI 6))
13609 (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))]
13612 [(set_attr "length_immediate" "0")
13613 (set_attr "length" "1")
13614 (set_attr "modrm" "0")
13615 (set_attr "modrm" "0")
13616 (set_attr "athlon_decode" "vector")
13617 (set_attr "ppro_uops" "few")])
13619 (define_expand "ffssi2"
13620 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13621 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13625 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13626 rtx in = operands[1];
13630 emit_move_insn (tmp, constm1_rtx);
13631 emit_insn (gen_ffssi_1 (out, in));
13632 emit_insn (gen_rtx_SET (VOIDmode, out,
13633 gen_rtx_IF_THEN_ELSE (SImode,
13634 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13638 emit_insn (gen_addsi3 (out, out, const1_rtx));
13639 emit_move_insn (operands[0], out);
13642 /* Pentium bsf instruction is extremly slow. The following code is
13643 recommended by the Intel Optimizing Manual as a reasonable replacement:
13647 MOV DWORD PTR [TEMP+4],ECX
13650 MOV DWORD PTR [TEMP],EAX
13651 FILD QWORD PTR [TEMP]
13652 FSTP QWORD PTR [TEMP]
13653 WAIT ; WAIT only needed for compatibility with
13654 ; earlier processors
13655 MOV ECX, DWORD PTR [TEMP+4]
13658 TEST EAX,EAX ; clear zero flag
13660 Following piece of code expand ffs to similar beast.
13663 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13665 rtx label = gen_label_rtx ();
13667 rtx mem = assign_386_stack_local (DImode, 0);
13668 rtx fptmp = gen_reg_rtx (DFmode);
13669 split_di (&mem, 1, &lo, &hi);
13671 emit_move_insn (out, const0_rtx);
13673 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
13675 emit_move_insn (hi, out);
13676 emit_insn (gen_subsi3 (out, out, in));
13677 emit_insn (gen_andsi3 (out, out, in));
13678 emit_move_insn (lo, out);
13679 emit_insn (gen_floatdidf2 (fptmp,mem));
13680 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13681 emit_move_insn (out, hi);
13682 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13683 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13685 emit_label (label);
13686 LABEL_NUSES (label) = 1;
13688 emit_move_insn (operands[0], out);
13692 emit_move_insn (tmp, const0_rtx);
13693 emit_insn (gen_ffssi_1 (out, in));
13694 emit_insn (gen_rtx_SET (VOIDmode,
13695 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13696 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13698 emit_insn (gen_negsi2 (tmp, tmp));
13699 emit_insn (gen_iorsi3 (out, out, tmp));
13700 emit_insn (gen_addsi3 (out, out, const1_rtx));
13701 emit_move_insn (operands[0], out);
13706 (define_insn "ffssi_1"
13708 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13710 (set (match_operand:SI 0 "register_operand" "=r")
13711 (unspec:SI [(match_dup 1)] 5))]
13713 "bsf{l}\\t{%1, %0|%0, %1}"
13714 [(set_attr "prefix_0f" "1")
13715 (set_attr "ppro_uops" "few")])
13717 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13718 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13720 ;; These patterns match the binary 387 instructions for addM3, subM3,
13721 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13722 ;; SFmode. The first is the normal insn, the second the same insn but
13723 ;; with one operand a conversion, and the third the same insn but with
13724 ;; the other operand a conversion. The conversion may be SFmode or
13725 ;; SImode if the target mode DFmode, but only SImode if the target mode
13728 ;; Gcc is slightly more smart about handling normal two address instructions
13729 ;; so use special patterns for add and mull.
13730 (define_insn "*fop_sf_comm"
13731 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13732 (match_operator:SF 3 "binary_fp_operator"
13733 [(match_operand:SF 1 "register_operand" "%0,0")
13734 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13735 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13736 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13737 "* return output_387_binary_op (insn, operands);"
13738 [(set (attr "type")
13739 (if_then_else (eq_attr "alternative" "1")
13740 (const_string "sse")
13741 (if_then_else (match_operand:SF 3 "mult_operator" "")
13742 (const_string "fmul")
13743 (const_string "fop"))))
13744 (set_attr "mode" "SF")])
13746 (define_insn "*fop_sf_comm_sse"
13747 [(set (match_operand:SF 0 "register_operand" "=x")
13748 (match_operator:SF 3 "binary_fp_operator"
13749 [(match_operand:SF 1 "register_operand" "%0")
13750 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13751 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13752 "* return output_387_binary_op (insn, operands);"
13753 [(set_attr "type" "sse")
13754 (set_attr "mode" "SF")])
13756 (define_insn "*fop_df_comm"
13757 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13758 (match_operator:DF 3 "binary_fp_operator"
13759 [(match_operand:DF 1 "register_operand" "%0,0")
13760 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13761 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13762 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13763 "* return output_387_binary_op (insn, operands);"
13764 [(set (attr "type")
13765 (if_then_else (eq_attr "alternative" "1")
13766 (const_string "sse")
13767 (if_then_else (match_operand:SF 3 "mult_operator" "")
13768 (const_string "fmul")
13769 (const_string "fop"))))
13770 (set_attr "mode" "DF")])
13772 (define_insn "*fop_df_comm_sse"
13773 [(set (match_operand:DF 0 "register_operand" "=Y")
13774 (match_operator:DF 3 "binary_fp_operator"
13775 [(match_operand:DF 1 "register_operand" "%0")
13776 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13778 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13779 "* return output_387_binary_op (insn, operands);"
13780 [(set_attr "type" "sse")
13781 (set_attr "mode" "DF")])
13783 (define_insn "*fop_xf_comm"
13784 [(set (match_operand:XF 0 "register_operand" "=f")
13785 (match_operator:XF 3 "binary_fp_operator"
13786 [(match_operand:XF 1 "register_operand" "%0")
13787 (match_operand:XF 2 "register_operand" "f")]))]
13788 "TARGET_80387 && !TARGET_64BIT
13789 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13790 "* return output_387_binary_op (insn, operands);"
13791 [(set (attr "type")
13792 (if_then_else (match_operand:XF 3 "mult_operator" "")
13793 (const_string "fmul")
13794 (const_string "fop")))
13795 (set_attr "mode" "XF")])
13797 (define_insn "*fop_tf_comm"
13798 [(set (match_operand:TF 0 "register_operand" "=f")
13799 (match_operator:TF 3 "binary_fp_operator"
13800 [(match_operand:TF 1 "register_operand" "%0")
13801 (match_operand:TF 2 "register_operand" "f")]))]
13802 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13803 "* return output_387_binary_op (insn, operands);"
13804 [(set (attr "type")
13805 (if_then_else (match_operand:TF 3 "mult_operator" "")
13806 (const_string "fmul")
13807 (const_string "fop")))
13808 (set_attr "mode" "XF")])
13810 (define_insn "*fop_sf_1"
13811 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13812 (match_operator:SF 3 "binary_fp_operator"
13813 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13814 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13815 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13816 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13817 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13818 "* return output_387_binary_op (insn, operands);"
13819 [(set (attr "type")
13820 (cond [(eq_attr "alternative" "2")
13821 (const_string "sse")
13822 (match_operand:SF 3 "mult_operator" "")
13823 (const_string "fmul")
13824 (match_operand:SF 3 "div_operator" "")
13825 (const_string "fdiv")
13827 (const_string "fop")))
13828 (set_attr "mode" "SF")])
13830 (define_insn "*fop_sf_1_sse"
13831 [(set (match_operand:SF 0 "register_operand" "=x")
13832 (match_operator:SF 3 "binary_fp_operator"
13833 [(match_operand:SF 1 "register_operand" "0")
13834 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13836 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13837 "* return output_387_binary_op (insn, operands);"
13838 [(set_attr "type" "sse")
13839 (set_attr "mode" "SF")])
13841 ;; ??? Add SSE splitters for these!
13842 (define_insn "*fop_sf_2"
13843 [(set (match_operand:SF 0 "register_operand" "=f,f")
13844 (match_operator:SF 3 "binary_fp_operator"
13845 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13846 (match_operand:SF 2 "register_operand" "0,0")]))]
13847 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13848 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13849 [(set (attr "type")
13850 (cond [(match_operand:SF 3 "mult_operator" "")
13851 (const_string "fmul")
13852 (match_operand:SF 3 "div_operator" "")
13853 (const_string "fdiv")
13855 (const_string "fop")))
13856 (set_attr "fp_int_src" "true")
13857 (set_attr "ppro_uops" "many")
13858 (set_attr "mode" "SI")])
13860 (define_insn "*fop_sf_3"
13861 [(set (match_operand:SF 0 "register_operand" "=f,f")
13862 (match_operator:SF 3 "binary_fp_operator"
13863 [(match_operand:SF 1 "register_operand" "0,0")
13864 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13865 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13866 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13867 [(set (attr "type")
13868 (cond [(match_operand:SF 3 "mult_operator" "")
13869 (const_string "fmul")
13870 (match_operand:SF 3 "div_operator" "")
13871 (const_string "fdiv")
13873 (const_string "fop")))
13874 (set_attr "fp_int_src" "true")
13875 (set_attr "ppro_uops" "many")
13876 (set_attr "mode" "SI")])
13878 (define_insn "*fop_df_1"
13879 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
13880 (match_operator:DF 3 "binary_fp_operator"
13881 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
13882 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
13883 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13884 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13885 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13886 "* return output_387_binary_op (insn, operands);"
13887 [(set (attr "type")
13888 (cond [(eq_attr "alternative" "2")
13889 (const_string "sse")
13890 (match_operand:DF 3 "mult_operator" "")
13891 (const_string "fmul")
13892 (match_operand:DF 3 "div_operator" "")
13893 (const_string "fdiv")
13895 (const_string "fop")))
13896 (set_attr "mode" "DF")])
13898 (define_insn "*fop_df_1_sse"
13899 [(set (match_operand:DF 0 "register_operand" "=Y")
13900 (match_operator:DF 3 "binary_fp_operator"
13901 [(match_operand:DF 1 "register_operand" "0")
13902 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13904 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13905 "* return output_387_binary_op (insn, operands);"
13906 [(set_attr "type" "sse")])
13908 ;; ??? Add SSE splitters for these!
13909 (define_insn "*fop_df_2"
13910 [(set (match_operand:DF 0 "register_operand" "=f,f")
13911 (match_operator:DF 3 "binary_fp_operator"
13912 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13913 (match_operand:DF 2 "register_operand" "0,0")]))]
13914 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13915 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13916 [(set (attr "type")
13917 (cond [(match_operand:DF 3 "mult_operator" "")
13918 (const_string "fmul")
13919 (match_operand:DF 3 "div_operator" "")
13920 (const_string "fdiv")
13922 (const_string "fop")))
13923 (set_attr "fp_int_src" "true")
13924 (set_attr "ppro_uops" "many")
13925 (set_attr "mode" "SI")])
13927 (define_insn "*fop_df_3"
13928 [(set (match_operand:DF 0 "register_operand" "=f,f")
13929 (match_operator:DF 3 "binary_fp_operator"
13930 [(match_operand:DF 1 "register_operand" "0,0")
13931 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13932 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13933 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13934 [(set (attr "type")
13935 (cond [(match_operand:DF 3 "mult_operator" "")
13936 (const_string "fmul")
13937 (match_operand:DF 3 "div_operator" "")
13938 (const_string "fdiv")
13940 (const_string "fop")))
13941 (set_attr "fp_int_src" "true")
13942 (set_attr "ppro_uops" "many")
13943 (set_attr "mode" "SI")])
13945 (define_insn "*fop_df_4"
13946 [(set (match_operand:DF 0 "register_operand" "=f,f")
13947 (match_operator:DF 3 "binary_fp_operator"
13948 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13949 (match_operand:DF 2 "register_operand" "0,f")]))]
13951 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13952 "* return output_387_binary_op (insn, operands);"
13953 [(set (attr "type")
13954 (cond [(match_operand:DF 3 "mult_operator" "")
13955 (const_string "fmul")
13956 (match_operand:DF 3 "div_operator" "")
13957 (const_string "fdiv")
13959 (const_string "fop")))
13960 (set_attr "mode" "SF")])
13962 (define_insn "*fop_df_5"
13963 [(set (match_operand:DF 0 "register_operand" "=f,f")
13964 (match_operator:DF 3 "binary_fp_operator"
13965 [(match_operand:DF 1 "register_operand" "0,f")
13967 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13968 "TARGET_80387 && !TARGET_SSE2"
13969 "* return output_387_binary_op (insn, operands);"
13970 [(set (attr "type")
13971 (cond [(match_operand:DF 3 "mult_operator" "")
13972 (const_string "fmul")
13973 (match_operand:DF 3 "div_operator" "")
13974 (const_string "fdiv")
13976 (const_string "fop")))
13977 (set_attr "mode" "SF")])
13979 (define_insn "*fop_xf_1"
13980 [(set (match_operand:XF 0 "register_operand" "=f,f")
13981 (match_operator:XF 3 "binary_fp_operator"
13982 [(match_operand:XF 1 "register_operand" "0,f")
13983 (match_operand:XF 2 "register_operand" "f,0")]))]
13984 "TARGET_80387 && !TARGET_64BIT
13985 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13986 "* return output_387_binary_op (insn, operands);"
13987 [(set (attr "type")
13988 (cond [(match_operand:XF 3 "mult_operator" "")
13989 (const_string "fmul")
13990 (match_operand:XF 3 "div_operator" "")
13991 (const_string "fdiv")
13993 (const_string "fop")))
13994 (set_attr "mode" "XF")])
13996 (define_insn "*fop_tf_1"
13997 [(set (match_operand:TF 0 "register_operand" "=f,f")
13998 (match_operator:TF 3 "binary_fp_operator"
13999 [(match_operand:TF 1 "register_operand" "0,f")
14000 (match_operand:TF 2 "register_operand" "f,0")]))]
14002 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14003 "* return output_387_binary_op (insn, operands);"
14004 [(set (attr "type")
14005 (cond [(match_operand:TF 3 "mult_operator" "")
14006 (const_string "fmul")
14007 (match_operand:TF 3 "div_operator" "")
14008 (const_string "fdiv")
14010 (const_string "fop")))
14011 (set_attr "mode" "XF")])
14013 (define_insn "*fop_xf_2"
14014 [(set (match_operand:XF 0 "register_operand" "=f,f")
14015 (match_operator:XF 3 "binary_fp_operator"
14016 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14017 (match_operand:XF 2 "register_operand" "0,0")]))]
14018 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14019 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14020 [(set (attr "type")
14021 (cond [(match_operand:XF 3 "mult_operator" "")
14022 (const_string "fmul")
14023 (match_operand:XF 3 "div_operator" "")
14024 (const_string "fdiv")
14026 (const_string "fop")))
14027 (set_attr "fp_int_src" "true")
14028 (set_attr "mode" "SI")
14029 (set_attr "ppro_uops" "many")])
14031 (define_insn "*fop_tf_2"
14032 [(set (match_operand:TF 0 "register_operand" "=f,f")
14033 (match_operator:TF 3 "binary_fp_operator"
14034 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14035 (match_operand:TF 2 "register_operand" "0,0")]))]
14036 "TARGET_80387 && TARGET_USE_FIOP"
14037 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14038 [(set (attr "type")
14039 (cond [(match_operand:TF 3 "mult_operator" "")
14040 (const_string "fmul")
14041 (match_operand:TF 3 "div_operator" "")
14042 (const_string "fdiv")
14044 (const_string "fop")))
14045 (set_attr "fp_int_src" "true")
14046 (set_attr "mode" "SI")
14047 (set_attr "ppro_uops" "many")])
14049 (define_insn "*fop_xf_3"
14050 [(set (match_operand:XF 0 "register_operand" "=f,f")
14051 (match_operator:XF 3 "binary_fp_operator"
14052 [(match_operand:XF 1 "register_operand" "0,0")
14053 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14054 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14055 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14056 [(set (attr "type")
14057 (cond [(match_operand:XF 3 "mult_operator" "")
14058 (const_string "fmul")
14059 (match_operand:XF 3 "div_operator" "")
14060 (const_string "fdiv")
14062 (const_string "fop")))
14063 (set_attr "fp_int_src" "true")
14064 (set_attr "mode" "SI")
14065 (set_attr "ppro_uops" "many")])
14067 (define_insn "*fop_tf_3"
14068 [(set (match_operand:TF 0 "register_operand" "=f,f")
14069 (match_operator:TF 3 "binary_fp_operator"
14070 [(match_operand:TF 1 "register_operand" "0,0")
14071 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14072 "TARGET_80387 && TARGET_USE_FIOP"
14073 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14074 [(set (attr "type")
14075 (cond [(match_operand:TF 3 "mult_operator" "")
14076 (const_string "fmul")
14077 (match_operand:TF 3 "div_operator" "")
14078 (const_string "fdiv")
14080 (const_string "fop")))
14081 (set_attr "fp_int_src" "true")
14082 (set_attr "mode" "SI")
14083 (set_attr "ppro_uops" "many")])
14085 (define_insn "*fop_xf_4"
14086 [(set (match_operand:XF 0 "register_operand" "=f,f")
14087 (match_operator:XF 3 "binary_fp_operator"
14088 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14089 (match_operand:XF 2 "register_operand" "0,f")]))]
14090 "TARGET_80387 && !TARGET_64BIT"
14091 "* return output_387_binary_op (insn, operands);"
14092 [(set (attr "type")
14093 (cond [(match_operand:XF 3 "mult_operator" "")
14094 (const_string "fmul")
14095 (match_operand:XF 3 "div_operator" "")
14096 (const_string "fdiv")
14098 (const_string "fop")))
14099 (set_attr "mode" "SF")])
14101 (define_insn "*fop_tf_4"
14102 [(set (match_operand:TF 0 "register_operand" "=f,f")
14103 (match_operator:TF 3 "binary_fp_operator"
14104 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14105 (match_operand:TF 2 "register_operand" "0,f")]))]
14107 "* return output_387_binary_op (insn, operands);"
14108 [(set (attr "type")
14109 (cond [(match_operand:TF 3 "mult_operator" "")
14110 (const_string "fmul")
14111 (match_operand:TF 3 "div_operator" "")
14112 (const_string "fdiv")
14114 (const_string "fop")))
14115 (set_attr "mode" "SF")])
14117 (define_insn "*fop_xf_5"
14118 [(set (match_operand:XF 0 "register_operand" "=f,f")
14119 (match_operator:XF 3 "binary_fp_operator"
14120 [(match_operand:XF 1 "register_operand" "0,f")
14122 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14123 "TARGET_80387 && !TARGET_64BIT"
14124 "* return output_387_binary_op (insn, operands);"
14125 [(set (attr "type")
14126 (cond [(match_operand:XF 3 "mult_operator" "")
14127 (const_string "fmul")
14128 (match_operand:XF 3 "div_operator" "")
14129 (const_string "fdiv")
14131 (const_string "fop")))
14132 (set_attr "mode" "SF")])
14134 (define_insn "*fop_tf_5"
14135 [(set (match_operand:TF 0 "register_operand" "=f,f")
14136 (match_operator:TF 3 "binary_fp_operator"
14137 [(match_operand:TF 1 "register_operand" "0,f")
14139 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14141 "* return output_387_binary_op (insn, operands);"
14142 [(set (attr "type")
14143 (cond [(match_operand:TF 3 "mult_operator" "")
14144 (const_string "fmul")
14145 (match_operand:TF 3 "div_operator" "")
14146 (const_string "fdiv")
14148 (const_string "fop")))
14149 (set_attr "mode" "SF")])
14151 (define_insn "*fop_xf_6"
14152 [(set (match_operand:XF 0 "register_operand" "=f,f")
14153 (match_operator:XF 3 "binary_fp_operator"
14154 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14155 (match_operand:XF 2 "register_operand" "0,f")]))]
14156 "TARGET_80387 && !TARGET_64BIT"
14157 "* return output_387_binary_op (insn, operands);"
14158 [(set (attr "type")
14159 (cond [(match_operand:XF 3 "mult_operator" "")
14160 (const_string "fmul")
14161 (match_operand:XF 3 "div_operator" "")
14162 (const_string "fdiv")
14164 (const_string "fop")))
14165 (set_attr "mode" "DF")])
14167 (define_insn "*fop_tf_6"
14168 [(set (match_operand:TF 0 "register_operand" "=f,f")
14169 (match_operator:TF 3 "binary_fp_operator"
14170 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14171 (match_operand:TF 2 "register_operand" "0,f")]))]
14173 "* return output_387_binary_op (insn, operands);"
14174 [(set (attr "type")
14175 (cond [(match_operand:TF 3 "mult_operator" "")
14176 (const_string "fmul")
14177 (match_operand:TF 3 "div_operator" "")
14178 (const_string "fdiv")
14180 (const_string "fop")))
14181 (set_attr "mode" "DF")])
14183 (define_insn "*fop_xf_7"
14184 [(set (match_operand:XF 0 "register_operand" "=f,f")
14185 (match_operator:XF 3 "binary_fp_operator"
14186 [(match_operand:XF 1 "register_operand" "0,f")
14188 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14189 "TARGET_80387 && !TARGET_64BIT"
14190 "* return output_387_binary_op (insn, operands);"
14191 [(set (attr "type")
14192 (cond [(match_operand:XF 3 "mult_operator" "")
14193 (const_string "fmul")
14194 (match_operand:XF 3 "div_operator" "")
14195 (const_string "fdiv")
14197 (const_string "fop")))
14198 (set_attr "mode" "DF")])
14200 (define_insn "*fop_tf_7"
14201 [(set (match_operand:TF 0 "register_operand" "=f,f")
14202 (match_operator:TF 3 "binary_fp_operator"
14203 [(match_operand:TF 1 "register_operand" "0,f")
14205 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14207 "* return output_387_binary_op (insn, operands);"
14208 [(set (attr "type")
14209 (cond [(match_operand:TF 3 "mult_operator" "")
14210 (const_string "fmul")
14211 (match_operand:TF 3 "div_operator" "")
14212 (const_string "fdiv")
14214 (const_string "fop")))
14215 (set_attr "mode" "DF")])
14218 [(set (match_operand 0 "register_operand" "")
14219 (match_operator 3 "binary_fp_operator"
14220 [(float (match_operand:SI 1 "register_operand" ""))
14221 (match_operand 2 "register_operand" "")]))]
14222 "TARGET_80387 && reload_completed
14223 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14227 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14228 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14229 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14230 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14231 GET_MODE (operands[3]),
14234 ix86_free_from_memory (GET_MODE (operands[1]));
14239 [(set (match_operand 0 "register_operand" "")
14240 (match_operator 3 "binary_fp_operator"
14241 [(match_operand 1 "register_operand" "")
14242 (float (match_operand:SI 2 "register_operand" ""))]))]
14243 "TARGET_80387 && reload_completed
14244 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14248 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14249 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14250 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14251 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14252 GET_MODE (operands[3]),
14255 ix86_free_from_memory (GET_MODE (operands[2]));
14259 ;; FPU special functions.
14261 (define_expand "sqrtsf2"
14262 [(set (match_operand:SF 0 "register_operand" "")
14263 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14264 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
14268 operands[1] = force_reg (SFmode, operands[1]);
14271 (define_insn "sqrtsf2_1"
14272 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14273 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14274 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14275 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
14278 sqrtss\\t{%1, %0|%0, %1}"
14279 [(set_attr "type" "fpspc,sse")
14280 (set_attr "mode" "SF,SF")
14281 (set_attr "athlon_decode" "direct,*")])
14283 (define_insn "sqrtsf2_1_sse_only"
14284 [(set (match_operand:SF 0 "register_operand" "=x")
14285 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14286 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14287 "sqrtss\\t{%1, %0|%0, %1}"
14288 [(set_attr "type" "sse")
14289 (set_attr "mode" "SF")
14290 (set_attr "athlon_decode" "*")])
14292 (define_insn "sqrtsf2_i387"
14293 [(set (match_operand:SF 0 "register_operand" "=f")
14294 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14295 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14296 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
14298 [(set_attr "type" "fpspc")
14299 (set_attr "mode" "SF")
14300 (set_attr "athlon_decode" "direct")])
14302 (define_expand "sqrtdf2"
14303 [(set (match_operand:DF 0 "register_operand" "")
14304 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14305 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
14309 operands[1] = force_reg (DFmode, operands[1]);
14312 (define_insn "sqrtdf2_1"
14313 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14314 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14315 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14316 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
14319 sqrtsd\\t{%1, %0|%0, %1}"
14320 [(set_attr "type" "fpspc,sse")
14321 (set_attr "mode" "DF,DF")
14322 (set_attr "athlon_decode" "direct,*")])
14324 (define_insn "sqrtdf2_1_sse_only"
14325 [(set (match_operand:DF 0 "register_operand" "=Y")
14326 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14327 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14328 "sqrtsd\\t{%1, %0|%0, %1}"
14329 [(set_attr "type" "sse")
14330 (set_attr "mode" "DF")
14331 (set_attr "athlon_decode" "*")])
14333 (define_insn "sqrtdf2_i387"
14334 [(set (match_operand:DF 0 "register_operand" "=f")
14335 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14336 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14337 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
14339 [(set_attr "type" "fpspc")
14340 (set_attr "mode" "DF")
14341 (set_attr "athlon_decode" "direct")])
14343 (define_insn "*sqrtextendsfdf2"
14344 [(set (match_operand:DF 0 "register_operand" "=f")
14345 (sqrt:DF (float_extend:DF
14346 (match_operand:SF 1 "register_operand" "0"))))]
14347 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
14349 [(set_attr "type" "fpspc")
14350 (set_attr "mode" "DF")
14351 (set_attr "athlon_decode" "direct")])
14353 (define_insn "sqrtxf2"
14354 [(set (match_operand:XF 0 "register_operand" "=f")
14355 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14356 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14357 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14359 [(set_attr "type" "fpspc")
14360 (set_attr "mode" "XF")
14361 (set_attr "athlon_decode" "direct")])
14363 (define_insn "sqrttf2"
14364 [(set (match_operand:TF 0 "register_operand" "=f")
14365 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14366 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14367 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14369 [(set_attr "type" "fpspc")
14370 (set_attr "mode" "XF")
14371 (set_attr "athlon_decode" "direct")])
14373 (define_insn "*sqrtextenddfxf2"
14374 [(set (match_operand:XF 0 "register_operand" "=f")
14375 (sqrt:XF (float_extend:XF
14376 (match_operand:DF 1 "register_operand" "0"))))]
14377 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14379 [(set_attr "type" "fpspc")
14380 (set_attr "mode" "XF")
14381 (set_attr "athlon_decode" "direct")])
14383 (define_insn "*sqrtextenddftf2"
14384 [(set (match_operand:TF 0 "register_operand" "=f")
14385 (sqrt:TF (float_extend:TF
14386 (match_operand:DF 1 "register_operand" "0"))))]
14387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14389 [(set_attr "type" "fpspc")
14390 (set_attr "mode" "XF")
14391 (set_attr "athlon_decode" "direct")])
14393 (define_insn "*sqrtextendsfxf2"
14394 [(set (match_operand:XF 0 "register_operand" "=f")
14395 (sqrt:XF (float_extend:XF
14396 (match_operand:SF 1 "register_operand" "0"))))]
14397 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14399 [(set_attr "type" "fpspc")
14400 (set_attr "mode" "XF")
14401 (set_attr "athlon_decode" "direct")])
14403 (define_insn "*sqrtextendsftf2"
14404 [(set (match_operand:TF 0 "register_operand" "=f")
14405 (sqrt:TF (float_extend:TF
14406 (match_operand:SF 1 "register_operand" "0"))))]
14407 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14409 [(set_attr "type" "fpspc")
14410 (set_attr "mode" "XF")
14411 (set_attr "athlon_decode" "direct")])
14413 (define_insn "sindf2"
14414 [(set (match_operand:DF 0 "register_operand" "=f")
14415 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
14416 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14417 && flag_unsafe_math_optimizations"
14419 [(set_attr "type" "fpspc")
14420 (set_attr "mode" "DF")])
14422 (define_insn "sinsf2"
14423 [(set (match_operand:SF 0 "register_operand" "=f")
14424 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
14425 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14426 && flag_unsafe_math_optimizations"
14428 [(set_attr "type" "fpspc")
14429 (set_attr "mode" "SF")])
14431 (define_insn "*sinextendsfdf2"
14432 [(set (match_operand:DF 0 "register_operand" "=f")
14433 (unspec:DF [(float_extend:DF
14434 (match_operand:SF 1 "register_operand" "0"))] 1))]
14435 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14436 && flag_unsafe_math_optimizations"
14438 [(set_attr "type" "fpspc")
14439 (set_attr "mode" "DF")])
14441 (define_insn "sinxf2"
14442 [(set (match_operand:XF 0 "register_operand" "=f")
14443 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14444 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14445 && flag_unsafe_math_optimizations"
14447 [(set_attr "type" "fpspc")
14448 (set_attr "mode" "XF")])
14450 (define_insn "sintf2"
14451 [(set (match_operand:TF 0 "register_operand" "=f")
14452 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
14453 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14454 && flag_unsafe_math_optimizations"
14456 [(set_attr "type" "fpspc")
14457 (set_attr "mode" "XF")])
14459 (define_insn "cosdf2"
14460 [(set (match_operand:DF 0 "register_operand" "=f")
14461 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
14462 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14463 && flag_unsafe_math_optimizations"
14465 [(set_attr "type" "fpspc")
14466 (set_attr "mode" "DF")])
14468 (define_insn "cossf2"
14469 [(set (match_operand:SF 0 "register_operand" "=f")
14470 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14471 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14472 && flag_unsafe_math_optimizations"
14474 [(set_attr "type" "fpspc")
14475 (set_attr "mode" "SF")])
14477 (define_insn "*cosextendsfdf2"
14478 [(set (match_operand:DF 0 "register_operand" "=f")
14479 (unspec:DF [(float_extend:DF
14480 (match_operand:SF 1 "register_operand" "0"))] 2))]
14481 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14482 && flag_unsafe_math_optimizations"
14484 [(set_attr "type" "fpspc")
14485 (set_attr "mode" "DF")])
14487 (define_insn "cosxf2"
14488 [(set (match_operand:XF 0 "register_operand" "=f")
14489 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14490 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14491 && flag_unsafe_math_optimizations"
14493 [(set_attr "type" "fpspc")
14494 (set_attr "mode" "XF")])
14496 (define_insn "costf2"
14497 [(set (match_operand:TF 0 "register_operand" "=f")
14498 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14499 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14500 && flag_unsafe_math_optimizations"
14502 [(set_attr "type" "fpspc")
14503 (set_attr "mode" "XF")])
14505 ;; Block operation instructions
14508 [(set (reg:SI 19) (const_int 0))]
14511 [(set_attr "type" "cld")])
14513 (define_expand "movstrsi"
14514 [(use (match_operand:BLK 0 "memory_operand" ""))
14515 (use (match_operand:BLK 1 "memory_operand" ""))
14516 (use (match_operand:SI 2 "nonmemory_operand" ""))
14517 (use (match_operand:SI 3 "const_int_operand" ""))]
14521 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14527 (define_expand "movstrdi"
14528 [(use (match_operand:BLK 0 "memory_operand" ""))
14529 (use (match_operand:BLK 1 "memory_operand" ""))
14530 (use (match_operand:DI 2 "nonmemory_operand" ""))
14531 (use (match_operand:DI 3 "const_int_operand" ""))]
14535 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14541 ;; Most CPUs don't like single string operations
14542 ;; Handle this case here to simplify previous expander.
14544 (define_expand "strmovdi_rex64"
14545 [(set (match_dup 2)
14546 (mem:DI (match_operand:DI 1 "register_operand" "")))
14547 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14549 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14550 (clobber (reg:CC 17))])
14551 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14552 (clobber (reg:CC 17))])]
14556 if (TARGET_SINGLE_STRINGOP || optimize_size)
14558 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14563 operands[2] = gen_reg_rtx (DImode);
14567 (define_expand "strmovsi"
14568 [(set (match_dup 2)
14569 (mem:SI (match_operand:SI 1 "register_operand" "")))
14570 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14572 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14573 (clobber (reg:CC 17))])
14574 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14575 (clobber (reg:CC 17))])]
14581 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14584 if (TARGET_SINGLE_STRINGOP || optimize_size)
14586 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14591 operands[2] = gen_reg_rtx (SImode);
14594 (define_expand "strmovsi_rex64"
14595 [(set (match_dup 2)
14596 (mem:SI (match_operand:DI 1 "register_operand" "")))
14597 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14599 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14600 (clobber (reg:CC 17))])
14601 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14602 (clobber (reg:CC 17))])]
14606 if (TARGET_SINGLE_STRINGOP || optimize_size)
14608 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14613 operands[2] = gen_reg_rtx (SImode);
14616 (define_expand "strmovhi"
14617 [(set (match_dup 2)
14618 (mem:HI (match_operand:SI 1 "register_operand" "")))
14619 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14621 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14622 (clobber (reg:CC 17))])
14623 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14624 (clobber (reg:CC 17))])]
14630 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14633 if (TARGET_SINGLE_STRINGOP || optimize_size)
14635 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14640 operands[2] = gen_reg_rtx (HImode);
14643 (define_expand "strmovhi_rex64"
14644 [(set (match_dup 2)
14645 (mem:HI (match_operand:DI 1 "register_operand" "")))
14646 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14648 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14649 (clobber (reg:CC 17))])
14650 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14651 (clobber (reg:CC 17))])]
14655 if (TARGET_SINGLE_STRINGOP || optimize_size)
14657 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14662 operands[2] = gen_reg_rtx (HImode);
14665 (define_expand "strmovqi"
14666 [(set (match_dup 2)
14667 (mem:QI (match_operand:SI 1 "register_operand" "")))
14668 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14670 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14671 (clobber (reg:CC 17))])
14672 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14673 (clobber (reg:CC 17))])]
14679 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14682 if (TARGET_SINGLE_STRINGOP || optimize_size)
14684 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14689 operands[2] = gen_reg_rtx (QImode);
14692 (define_expand "strmovqi_rex64"
14693 [(set (match_dup 2)
14694 (mem:QI (match_operand:DI 1 "register_operand" "")))
14695 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14697 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14698 (clobber (reg:CC 17))])
14699 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14700 (clobber (reg:CC 17))])]
14704 if (TARGET_SINGLE_STRINGOP || optimize_size)
14706 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14711 operands[2] = gen_reg_rtx (QImode);
14714 (define_insn "strmovdi_rex_1"
14715 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14716 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14717 (set (match_operand:DI 0 "register_operand" "=D")
14718 (plus:DI (match_dup 2)
14720 (set (match_operand:DI 1 "register_operand" "=S")
14721 (plus:DI (match_dup 3)
14724 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14726 [(set_attr "type" "str")
14727 (set_attr "mode" "DI")
14728 (set_attr "memory" "both")])
14730 (define_insn "strmovsi_1"
14731 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14732 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14733 (set (match_operand:SI 0 "register_operand" "=D")
14734 (plus:SI (match_dup 2)
14736 (set (match_operand:SI 1 "register_operand" "=S")
14737 (plus:SI (match_dup 3)
14740 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14742 [(set_attr "type" "str")
14743 (set_attr "mode" "SI")
14744 (set_attr "memory" "both")])
14746 (define_insn "strmovsi_rex_1"
14747 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14748 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14749 (set (match_operand:DI 0 "register_operand" "=D")
14750 (plus:DI (match_dup 2)
14752 (set (match_operand:DI 1 "register_operand" "=S")
14753 (plus:DI (match_dup 3)
14756 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14758 [(set_attr "type" "str")
14759 (set_attr "mode" "SI")
14760 (set_attr "memory" "both")])
14762 (define_insn "strmovhi_1"
14763 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14764 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14765 (set (match_operand:SI 0 "register_operand" "=D")
14766 (plus:SI (match_dup 2)
14768 (set (match_operand:SI 1 "register_operand" "=S")
14769 (plus:SI (match_dup 3)
14772 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14774 [(set_attr "type" "str")
14775 (set_attr "memory" "both")
14776 (set_attr "mode" "HI")])
14778 (define_insn "strmovhi_rex_1"
14779 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14780 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14781 (set (match_operand:DI 0 "register_operand" "=D")
14782 (plus:DI (match_dup 2)
14784 (set (match_operand:DI 1 "register_operand" "=S")
14785 (plus:DI (match_dup 3)
14788 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14790 [(set_attr "type" "str")
14791 (set_attr "memory" "both")
14792 (set_attr "mode" "HI")])
14794 (define_insn "strmovqi_1"
14795 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14796 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14797 (set (match_operand:SI 0 "register_operand" "=D")
14798 (plus:SI (match_dup 2)
14800 (set (match_operand:SI 1 "register_operand" "=S")
14801 (plus:SI (match_dup 3)
14804 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14806 [(set_attr "type" "str")
14807 (set_attr "memory" "both")
14808 (set_attr "mode" "QI")])
14810 (define_insn "strmovqi_rex_1"
14811 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14812 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14813 (set (match_operand:DI 0 "register_operand" "=D")
14814 (plus:DI (match_dup 2)
14816 (set (match_operand:DI 1 "register_operand" "=S")
14817 (plus:DI (match_dup 3)
14820 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14822 [(set_attr "type" "str")
14823 (set_attr "memory" "both")
14824 (set_attr "mode" "QI")])
14826 (define_insn "rep_movdi_rex64"
14827 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14828 (set (match_operand:DI 0 "register_operand" "=D")
14829 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14831 (match_operand:DI 3 "register_operand" "0")))
14832 (set (match_operand:DI 1 "register_operand" "=S")
14833 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14834 (match_operand:DI 4 "register_operand" "1")))
14835 (set (mem:BLK (match_dup 3))
14836 (mem:BLK (match_dup 4)))
14837 (use (match_dup 5))
14840 "rep\;movsq|rep movsq"
14841 [(set_attr "type" "str")
14842 (set_attr "prefix_rep" "1")
14843 (set_attr "memory" "both")
14844 (set_attr "mode" "DI")])
14846 (define_insn "rep_movsi"
14847 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14848 (set (match_operand:SI 0 "register_operand" "=D")
14849 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14851 (match_operand:SI 3 "register_operand" "0")))
14852 (set (match_operand:SI 1 "register_operand" "=S")
14853 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14854 (match_operand:SI 4 "register_operand" "1")))
14855 (set (mem:BLK (match_dup 3))
14856 (mem:BLK (match_dup 4)))
14857 (use (match_dup 5))
14860 "rep\;movsl|rep movsd"
14861 [(set_attr "type" "str")
14862 (set_attr "prefix_rep" "1")
14863 (set_attr "memory" "both")
14864 (set_attr "mode" "SI")])
14866 (define_insn "rep_movsi_rex64"
14867 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14868 (set (match_operand:DI 0 "register_operand" "=D")
14869 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14871 (match_operand:DI 3 "register_operand" "0")))
14872 (set (match_operand:DI 1 "register_operand" "=S")
14873 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14874 (match_operand:DI 4 "register_operand" "1")))
14875 (set (mem:BLK (match_dup 3))
14876 (mem:BLK (match_dup 4)))
14877 (use (match_dup 5))
14880 "rep\;movsl|rep movsd"
14881 [(set_attr "type" "str")
14882 (set_attr "prefix_rep" "1")
14883 (set_attr "memory" "both")
14884 (set_attr "mode" "SI")])
14886 (define_insn "rep_movqi"
14887 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14888 (set (match_operand:SI 0 "register_operand" "=D")
14889 (plus:SI (match_operand:SI 3 "register_operand" "0")
14890 (match_operand:SI 5 "register_operand" "2")))
14891 (set (match_operand:SI 1 "register_operand" "=S")
14892 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
14893 (set (mem:BLK (match_dup 3))
14894 (mem:BLK (match_dup 4)))
14895 (use (match_dup 5))
14898 "rep\;movsb|rep movsb"
14899 [(set_attr "type" "str")
14900 (set_attr "prefix_rep" "1")
14901 (set_attr "memory" "both")
14902 (set_attr "mode" "SI")])
14904 (define_insn "rep_movqi_rex64"
14905 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14906 (set (match_operand:DI 0 "register_operand" "=D")
14907 (plus:DI (match_operand:DI 3 "register_operand" "0")
14908 (match_operand:DI 5 "register_operand" "2")))
14909 (set (match_operand:DI 1 "register_operand" "=S")
14910 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
14911 (set (mem:BLK (match_dup 3))
14912 (mem:BLK (match_dup 4)))
14913 (use (match_dup 5))
14916 "rep\;movsb|rep movsb"
14917 [(set_attr "type" "str")
14918 (set_attr "prefix_rep" "1")
14919 (set_attr "memory" "both")
14920 (set_attr "mode" "SI")])
14922 (define_expand "clrstrsi"
14923 [(use (match_operand:BLK 0 "memory_operand" ""))
14924 (use (match_operand:SI 1 "nonmemory_operand" ""))
14925 (use (match_operand 2 "const_int_operand" ""))]
14929 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14935 (define_expand "clrstrdi"
14936 [(use (match_operand:BLK 0 "memory_operand" ""))
14937 (use (match_operand:DI 1 "nonmemory_operand" ""))
14938 (use (match_operand 2 "const_int_operand" ""))]
14942 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14948 ;; Most CPUs don't like single string operations
14949 ;; Handle this case here to simplify previous expander.
14951 (define_expand "strsetdi_rex64"
14952 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
14953 (match_operand:DI 1 "register_operand" ""))
14954 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14955 (clobber (reg:CC 17))])]
14959 if (TARGET_SINGLE_STRINGOP || optimize_size)
14961 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
14966 (define_expand "strsetsi"
14967 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
14968 (match_operand:SI 1 "register_operand" ""))
14969 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14970 (clobber (reg:CC 17))])]
14976 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
14979 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14981 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
14986 (define_expand "strsetsi_rex64"
14987 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
14988 (match_operand:SI 1 "register_operand" ""))
14989 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14990 (clobber (reg:CC 17))])]
14994 if (TARGET_SINGLE_STRINGOP || optimize_size)
14996 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15001 (define_expand "strsethi"
15002 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15003 (match_operand:HI 1 "register_operand" ""))
15004 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15005 (clobber (reg:CC 17))])]
15011 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15014 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15016 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15021 (define_expand "strsethi_rex64"
15022 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15023 (match_operand:HI 1 "register_operand" ""))
15024 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15025 (clobber (reg:CC 17))])]
15029 if (TARGET_SINGLE_STRINGOP || optimize_size)
15031 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15036 (define_expand "strsetqi"
15037 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15038 (match_operand:QI 1 "register_operand" ""))
15039 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15040 (clobber (reg:CC 17))])]
15046 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15049 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15051 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15056 (define_expand "strsetqi_rex64"
15057 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15058 (match_operand:QI 1 "register_operand" ""))
15059 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15060 (clobber (reg:CC 17))])]
15064 if (TARGET_SINGLE_STRINGOP || optimize_size)
15066 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15071 (define_insn "strsetdi_rex_1"
15072 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15073 (match_operand:SI 2 "register_operand" "a"))
15074 (set (match_operand:DI 0 "register_operand" "=D")
15075 (plus:DI (match_dup 1)
15078 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15080 [(set_attr "type" "str")
15081 (set_attr "memory" "store")
15082 (set_attr "mode" "DI")])
15084 (define_insn "strsetsi_1"
15085 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15086 (match_operand:SI 2 "register_operand" "a"))
15087 (set (match_operand:SI 0 "register_operand" "=D")
15088 (plus:SI (match_dup 1)
15091 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15093 [(set_attr "type" "str")
15094 (set_attr "memory" "store")
15095 (set_attr "mode" "SI")])
15097 (define_insn "strsetsi_rex_1"
15098 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15099 (match_operand:SI 2 "register_operand" "a"))
15100 (set (match_operand:DI 0 "register_operand" "=D")
15101 (plus:DI (match_dup 1)
15104 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15106 [(set_attr "type" "str")
15107 (set_attr "memory" "store")
15108 (set_attr "mode" "SI")])
15110 (define_insn "strsethi_1"
15111 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15112 (match_operand:HI 2 "register_operand" "a"))
15113 (set (match_operand:SI 0 "register_operand" "=D")
15114 (plus:SI (match_dup 1)
15117 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15119 [(set_attr "type" "str")
15120 (set_attr "memory" "store")
15121 (set_attr "mode" "HI")])
15123 (define_insn "strsethi_rex_1"
15124 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15125 (match_operand:HI 2 "register_operand" "a"))
15126 (set (match_operand:DI 0 "register_operand" "=D")
15127 (plus:DI (match_dup 1)
15130 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15132 [(set_attr "type" "str")
15133 (set_attr "memory" "store")
15134 (set_attr "mode" "HI")])
15136 (define_insn "strsetqi_1"
15137 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15138 (match_operand:QI 2 "register_operand" "a"))
15139 (set (match_operand:SI 0 "register_operand" "=D")
15140 (plus:SI (match_dup 1)
15143 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15145 [(set_attr "type" "str")
15146 (set_attr "memory" "store")
15147 (set_attr "mode" "QI")])
15149 (define_insn "strsetqi_rex_1"
15150 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15151 (match_operand:QI 2 "register_operand" "a"))
15152 (set (match_operand:DI 0 "register_operand" "=D")
15153 (plus:DI (match_dup 1)
15156 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15158 [(set_attr "type" "str")
15159 (set_attr "memory" "store")
15160 (set_attr "mode" "QI")])
15162 (define_insn "rep_stosdi_rex64"
15163 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15164 (set (match_operand:DI 0 "register_operand" "=D")
15165 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15167 (match_operand:DI 3 "register_operand" "0")))
15168 (set (mem:BLK (match_dup 3))
15170 (use (match_operand:DI 2 "register_operand" "a"))
15171 (use (match_dup 4))
15174 "rep\;stosq|rep stosq"
15175 [(set_attr "type" "str")
15176 (set_attr "prefix_rep" "1")
15177 (set_attr "memory" "store")
15178 (set_attr "mode" "DI")])
15180 (define_insn "rep_stossi"
15181 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15182 (set (match_operand:SI 0 "register_operand" "=D")
15183 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15185 (match_operand:SI 3 "register_operand" "0")))
15186 (set (mem:BLK (match_dup 3))
15188 (use (match_operand:SI 2 "register_operand" "a"))
15189 (use (match_dup 4))
15192 "rep\;stosl|rep stosd"
15193 [(set_attr "type" "str")
15194 (set_attr "prefix_rep" "1")
15195 (set_attr "memory" "store")
15196 (set_attr "mode" "SI")])
15198 (define_insn "rep_stossi_rex64"
15199 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15200 (set (match_operand:DI 0 "register_operand" "=D")
15201 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15203 (match_operand:DI 3 "register_operand" "0")))
15204 (set (mem:BLK (match_dup 3))
15206 (use (match_operand:SI 2 "register_operand" "a"))
15207 (use (match_dup 4))
15210 "rep\;stosl|rep stosd"
15211 [(set_attr "type" "str")
15212 (set_attr "prefix_rep" "1")
15213 (set_attr "memory" "store")
15214 (set_attr "mode" "SI")])
15216 (define_insn "rep_stosqi"
15217 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15218 (set (match_operand:SI 0 "register_operand" "=D")
15219 (plus:SI (match_operand:SI 3 "register_operand" "0")
15220 (match_operand:SI 4 "register_operand" "1")))
15221 (set (mem:BLK (match_dup 3))
15223 (use (match_operand:QI 2 "register_operand" "a"))
15224 (use (match_dup 4))
15227 "rep\;stosb|rep stosb"
15228 [(set_attr "type" "str")
15229 (set_attr "prefix_rep" "1")
15230 (set_attr "memory" "store")
15231 (set_attr "mode" "QI")])
15233 (define_insn "rep_stosqi_rex64"
15234 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15235 (set (match_operand:DI 0 "register_operand" "=D")
15236 (plus:DI (match_operand:DI 3 "register_operand" "0")
15237 (match_operand:DI 4 "register_operand" "1")))
15238 (set (mem:BLK (match_dup 3))
15240 (use (match_operand:QI 2 "register_operand" "a"))
15241 (use (match_dup 4))
15244 "rep\;stosb|rep stosb"
15245 [(set_attr "type" "str")
15246 (set_attr "prefix_rep" "1")
15247 (set_attr "memory" "store")
15248 (set_attr "mode" "QI")])
15250 (define_expand "cmpstrsi"
15251 [(set (match_operand:SI 0 "register_operand" "")
15252 (compare:SI (match_operand:BLK 1 "general_operand" "")
15253 (match_operand:BLK 2 "general_operand" "")))
15254 (use (match_operand 3 "general_operand" ""))
15255 (use (match_operand 4 "immediate_operand" ""))]
15259 rtx addr1, addr2, out, outlow, count, countreg, align;
15262 if (GET_CODE (out) != REG)
15263 out = gen_reg_rtx (SImode);
15265 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15266 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15268 count = operands[3];
15269 countreg = copy_to_mode_reg (Pmode, count);
15271 /* %%% Iff we are testing strict equality, we can use known alignment
15272 to good advantage. This may be possible with combine, particularly
15273 once cc0 is dead. */
15274 align = operands[4];
15276 emit_insn (gen_cld ());
15277 if (GET_CODE (count) == CONST_INT)
15279 if (INTVAL (count) == 0)
15281 emit_move_insn (operands[0], const0_rtx);
15285 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15286 addr1, addr2, countreg));
15288 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15289 addr1, addr2, countreg));
15295 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15296 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15297 addr1, addr2, countreg));
15301 emit_insn (gen_cmpsi_1 (countreg, countreg));
15302 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15303 addr1, addr2, countreg));
15307 outlow = gen_lowpart (QImode, out);
15308 emit_insn (gen_cmpintqi (outlow));
15309 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15311 if (operands[0] != out)
15312 emit_move_insn (operands[0], out);
15317 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15319 (define_expand "cmpintqi"
15320 [(set (match_dup 1)
15321 (gtu:QI (reg:CC 17) (const_int 0)))
15323 (ltu:QI (reg:CC 17) (const_int 0)))
15324 (parallel [(set (match_operand:QI 0 "register_operand" "")
15325 (minus:QI (match_dup 1)
15327 (clobber (reg:CC 17))])]
15329 "operands[1] = gen_reg_rtx (QImode);
15330 operands[2] = gen_reg_rtx (QImode);")
15332 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15333 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15335 (define_insn "cmpstrqi_nz_1"
15337 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15338 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15339 (use (match_operand:SI 6 "register_operand" "2"))
15340 (use (match_operand:SI 3 "immediate_operand" "i"))
15342 (clobber (match_operand:SI 0 "register_operand" "=S"))
15343 (clobber (match_operand:SI 1 "register_operand" "=D"))
15344 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15347 [(set_attr "type" "str")
15348 (set_attr "mode" "QI")
15349 (set_attr "prefix_rep" "1")])
15351 (define_insn "cmpstrqi_nz_rex_1"
15353 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15354 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15355 (use (match_operand:DI 6 "register_operand" "2"))
15356 (use (match_operand:SI 3 "immediate_operand" "i"))
15358 (clobber (match_operand:DI 0 "register_operand" "=S"))
15359 (clobber (match_operand:DI 1 "register_operand" "=D"))
15360 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15363 [(set_attr "type" "str")
15364 (set_attr "mode" "QI")
15365 (set_attr "prefix_rep" "1")])
15367 ;; The same, but the count is not known to not be zero.
15369 (define_insn "cmpstrqi_1"
15371 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15373 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15374 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15376 (use (match_operand:SI 3 "immediate_operand" "i"))
15379 (clobber (match_operand:SI 0 "register_operand" "=S"))
15380 (clobber (match_operand:SI 1 "register_operand" "=D"))
15381 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15384 [(set_attr "type" "str")
15385 (set_attr "mode" "QI")
15386 (set_attr "prefix_rep" "1")])
15388 (define_insn "cmpstrqi_rex_1"
15390 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15392 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15393 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15395 (use (match_operand:SI 3 "immediate_operand" "i"))
15398 (clobber (match_operand:DI 0 "register_operand" "=S"))
15399 (clobber (match_operand:DI 1 "register_operand" "=D"))
15400 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15403 [(set_attr "type" "str")
15404 (set_attr "mode" "QI")
15405 (set_attr "prefix_rep" "1")])
15407 (define_expand "strlensi"
15408 [(set (match_operand:SI 0 "register_operand" "")
15409 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15410 (match_operand:QI 2 "immediate_operand" "")
15411 (match_operand 3 "immediate_operand" "")] 0))]
15415 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15421 (define_expand "strlendi"
15422 [(set (match_operand:DI 0 "register_operand" "")
15423 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15424 (match_operand:QI 2 "immediate_operand" "")
15425 (match_operand 3 "immediate_operand" "")] 0))]
15429 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15435 (define_insn "strlenqi_1"
15436 [(set (match_operand:SI 0 "register_operand" "=&c")
15437 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15438 (match_operand:QI 2 "register_operand" "a")
15439 (match_operand:SI 3 "immediate_operand" "i")
15440 (match_operand:SI 4 "register_operand" "0")] 0))
15442 (clobber (match_operand:SI 1 "register_operand" "=D"))
15443 (clobber (reg:CC 17))]
15446 [(set_attr "type" "str")
15447 (set_attr "mode" "QI")
15448 (set_attr "prefix_rep" "1")])
15450 (define_insn "strlenqi_rex_1"
15451 [(set (match_operand:DI 0 "register_operand" "=&c")
15452 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15453 (match_operand:QI 2 "register_operand" "a")
15454 (match_operand:DI 3 "immediate_operand" "i")
15455 (match_operand:DI 4 "register_operand" "0")] 0))
15457 (clobber (match_operand:DI 1 "register_operand" "=D"))
15458 (clobber (reg:CC 17))]
15461 [(set_attr "type" "str")
15462 (set_attr "mode" "QI")
15463 (set_attr "prefix_rep" "1")])
15465 ;; Conditional move instructions.
15467 (define_expand "movdicc_rex64"
15468 [(set (match_operand:DI 0 "register_operand" "")
15469 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15470 (match_operand:DI 2 "x86_64_general_operand" "")
15471 (match_operand:DI 3 "x86_64_general_operand" "")))]
15473 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15475 (define_insn "x86_movdicc_0_m1_rex64"
15476 [(set (match_operand:DI 0 "register_operand" "=r")
15477 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15480 (clobber (reg:CC 17))]
15483 ; Since we don't have the proper number of operands for an alu insn,
15484 ; fill in all the blanks.
15485 [(set_attr "type" "alu")
15486 (set_attr "memory" "none")
15487 (set_attr "imm_disp" "false")
15488 (set_attr "mode" "DI")
15489 (set_attr "length_immediate" "0")])
15491 (define_insn "*movdicc_c_rex64"
15492 [(set (match_operand:DI 0 "register_operand" "=r,r")
15493 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15494 [(reg 17) (const_int 0)])
15495 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15496 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15497 "TARGET_64BIT && TARGET_CMOVE
15498 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15500 cmov%C1\\t{%2, %0|%0, %2}
15501 cmov%c1\\t{%3, %0|%0, %3}"
15502 [(set_attr "type" "icmov")
15503 (set_attr "mode" "DI")])
15505 (define_expand "movsicc"
15506 [(set (match_operand:SI 0 "register_operand" "")
15507 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15508 (match_operand:SI 2 "general_operand" "")
15509 (match_operand:SI 3 "general_operand" "")))]
15511 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15513 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15514 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15515 ;; So just document what we're doing explicitly.
15517 (define_insn "x86_movsicc_0_m1"
15518 [(set (match_operand:SI 0 "register_operand" "=r")
15519 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15522 (clobber (reg:CC 17))]
15525 ; Since we don't have the proper number of operands for an alu insn,
15526 ; fill in all the blanks.
15527 [(set_attr "type" "alu")
15528 (set_attr "memory" "none")
15529 (set_attr "imm_disp" "false")
15530 (set_attr "mode" "SI")
15531 (set_attr "length_immediate" "0")])
15533 (define_insn "*movsicc_noc"
15534 [(set (match_operand:SI 0 "register_operand" "=r,r")
15535 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15536 [(reg 17) (const_int 0)])
15537 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15538 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15540 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15542 cmov%C1\\t{%2, %0|%0, %2}
15543 cmov%c1\\t{%3, %0|%0, %3}"
15544 [(set_attr "type" "icmov")
15545 (set_attr "mode" "SI")])
15547 (define_expand "movhicc"
15548 [(set (match_operand:HI 0 "register_operand" "")
15549 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15550 (match_operand:HI 2 "nonimmediate_operand" "")
15551 (match_operand:HI 3 "nonimmediate_operand" "")))]
15552 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15553 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15555 (define_insn "*movhicc_noc"
15556 [(set (match_operand:HI 0 "register_operand" "=r,r")
15557 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15558 [(reg 17) (const_int 0)])
15559 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15560 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15562 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15564 cmov%C1\\t{%2, %0|%0, %2}
15565 cmov%c1\\t{%3, %0|%0, %3}"
15566 [(set_attr "type" "icmov")
15567 (set_attr "mode" "HI")])
15569 (define_expand "movsfcc"
15570 [(set (match_operand:SF 0 "register_operand" "")
15571 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15572 (match_operand:SF 2 "register_operand" "")
15573 (match_operand:SF 3 "register_operand" "")))]
15575 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15577 (define_insn "*movsfcc_1"
15578 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15579 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15580 [(reg 17) (const_int 0)])
15581 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15582 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15584 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15586 fcmov%F1\\t{%2, %0|%0, %2}
15587 fcmov%f1\\t{%3, %0|%0, %3}
15588 cmov%C1\\t{%2, %0|%0, %2}
15589 cmov%c1\\t{%3, %0|%0, %3}"
15590 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15591 (set_attr "mode" "SF,SF,SI,SI")])
15593 (define_expand "movdfcc"
15594 [(set (match_operand:DF 0 "register_operand" "")
15595 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15596 (match_operand:DF 2 "register_operand" "")
15597 (match_operand:DF 3 "register_operand" "")))]
15599 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15601 (define_insn "*movdfcc_1"
15602 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15603 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15604 [(reg 17) (const_int 0)])
15605 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15606 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15607 "TARGET_CMOVE && !TARGET_64BIT
15608 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15610 fcmov%F1\\t{%2, %0|%0, %2}
15611 fcmov%f1\\t{%3, %0|%0, %3}
15614 [(set_attr "type" "fcmov,fcmov,multi,multi")
15615 (set_attr "mode" "DF")])
15617 (define_insn "*movdfcc_1_rex64"
15618 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15619 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15620 [(reg 17) (const_int 0)])
15621 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15622 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15623 "TARGET_CMOVE && TARGET_64BIT
15624 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15626 fcmov%F1\\t{%2, %0|%0, %2}
15627 fcmov%f1\\t{%3, %0|%0, %3}
15628 cmov%C1\\t{%2, %0|%0, %2}
15629 cmov%c1\\t{%3, %0|%0, %3}"
15630 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15631 (set_attr "mode" "DF")])
15634 [(set (match_operand:DF 0 "register_operand" "")
15635 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15636 [(match_operand 4 "" "") (const_int 0)])
15637 (match_operand:DF 2 "nonimmediate_operand" "")
15638 (match_operand:DF 3 "nonimmediate_operand" "")))]
15639 "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
15640 [(set (match_dup 2)
15641 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15645 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15648 "split_di (operands+2, 1, operands+5, operands+6);
15649 split_di (operands+3, 1, operands+7, operands+8);
15650 split_di (operands, 1, operands+2, operands+3);")
15652 (define_expand "movxfcc"
15653 [(set (match_operand:XF 0 "register_operand" "")
15654 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15655 (match_operand:XF 2 "register_operand" "")
15656 (match_operand:XF 3 "register_operand" "")))]
15657 "TARGET_CMOVE && !TARGET_64BIT"
15658 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15660 (define_expand "movtfcc"
15661 [(set (match_operand:TF 0 "register_operand" "")
15662 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15663 (match_operand:TF 2 "register_operand" "")
15664 (match_operand:TF 3 "register_operand" "")))]
15666 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15668 (define_insn "*movxfcc_1"
15669 [(set (match_operand:XF 0 "register_operand" "=f,f")
15670 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15671 [(reg 17) (const_int 0)])
15672 (match_operand:XF 2 "register_operand" "f,0")
15673 (match_operand:XF 3 "register_operand" "0,f")))]
15674 "TARGET_CMOVE && !TARGET_64BIT"
15676 fcmov%F1\\t{%2, %0|%0, %2}
15677 fcmov%f1\\t{%3, %0|%0, %3}"
15678 [(set_attr "type" "fcmov")
15679 (set_attr "mode" "XF")])
15681 (define_insn "*movtfcc_1"
15682 [(set (match_operand:TF 0 "register_operand" "=f,f")
15683 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15684 [(reg 17) (const_int 0)])
15685 (match_operand:TF 2 "register_operand" "f,0")
15686 (match_operand:TF 3 "register_operand" "0,f")))]
15689 fcmov%F1\\t{%2, %0|%0, %2}
15690 fcmov%f1\\t{%3, %0|%0, %3}"
15691 [(set_attr "type" "fcmov")
15692 (set_attr "mode" "XF")])
15694 (define_expand "minsf3"
15696 (set (match_operand:SF 0 "register_operand" "")
15697 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15698 (match_operand:SF 2 "nonimmediate_operand" ""))
15701 (clobber (reg:CC 17))])]
15705 (define_insn "*minsf"
15706 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15707 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15708 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15711 (clobber (reg:CC 17))]
15712 "TARGET_SSE && TARGET_IEEE_FP"
15715 (define_insn "*minsf_nonieee"
15716 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15717 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15718 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15721 (clobber (reg:CC 17))]
15722 "TARGET_SSE && !TARGET_IEEE_FP"
15726 [(set (match_operand:SF 0 "register_operand" "")
15727 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15728 (match_operand:SF 2 "nonimmediate_operand" ""))
15731 (clobber (reg:CC 17))]
15732 "SSE_REG_P (operands[0]) && reload_completed"
15733 [(set (match_dup 0)
15734 (if_then_else:SF (lt (match_dup 1)
15739 ;; We can't represent the LT test directly. Do this by swapping the operands.
15741 [(set (match_operand:SF 0 "register_operand" "")
15742 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15743 (match_operand:SF 2 "register_operand" ""))
15746 (clobber (reg:CC 17))]
15747 "FP_REG_P (operands[0]) && reload_completed"
15748 [(set (reg:CCFP 17)
15749 (compare:CCFP (match_dup 2)
15752 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15756 (define_insn "*minsf_sse"
15757 [(set (match_operand:SF 0 "register_operand" "=x")
15758 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15759 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15762 "TARGET_SSE && reload_completed"
15763 "minss\\t{%2, %0|%0, %2}"
15764 [(set_attr "type" "sse")
15765 (set_attr "mode" "SF")])
15767 (define_expand "mindf3"
15769 (set (match_operand:DF 0 "register_operand" "")
15770 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15771 (match_operand:DF 2 "nonimmediate_operand" ""))
15774 (clobber (reg:CC 17))])]
15778 (define_insn "*mindf"
15779 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15780 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15781 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15784 (clobber (reg:CC 17))]
15785 "TARGET_SSE2 && TARGET_IEEE_FP"
15788 (define_insn "*mindf_nonieee"
15789 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15790 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
15791 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15794 (clobber (reg:CC 17))]
15795 "TARGET_SSE2 && !TARGET_IEEE_FP"
15799 [(set (match_operand:DF 0 "register_operand" "")
15800 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15801 (match_operand:DF 2 "nonimmediate_operand" ""))
15804 (clobber (reg:CC 17))]
15805 "SSE_REG_P (operands[0]) && reload_completed"
15806 [(set (match_dup 0)
15807 (if_then_else:DF (lt (match_dup 1)
15812 ;; We can't represent the LT test directly. Do this by swapping the operands.
15814 [(set (match_operand:DF 0 "register_operand" "")
15815 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15816 (match_operand:DF 2 "register_operand" ""))
15819 (clobber (reg:CC 17))]
15820 "FP_REG_P (operands[0]) && reload_completed"
15821 [(set (reg:CCFP 17)
15822 (compare:CCFP (match_dup 2)
15825 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
15829 (define_insn "*mindf_sse"
15830 [(set (match_operand:DF 0 "register_operand" "=Y")
15831 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
15832 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15835 "TARGET_SSE2 && reload_completed"
15836 "minsd\\t{%2, %0|%0, %2}"
15837 [(set_attr "type" "sse")
15838 (set_attr "mode" "DF")])
15840 (define_expand "maxsf3"
15842 (set (match_operand:SF 0 "register_operand" "")
15843 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15844 (match_operand:SF 2 "nonimmediate_operand" ""))
15847 (clobber (reg:CC 17))])]
15851 (define_insn "*maxsf"
15852 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15853 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
15854 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
15857 (clobber (reg:CC 17))]
15858 "TARGET_SSE && TARGET_IEEE_FP"
15861 (define_insn "*maxsf_nonieee"
15862 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15863 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
15864 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15867 (clobber (reg:CC 17))]
15868 "TARGET_SSE && !TARGET_IEEE_FP"
15872 [(set (match_operand:SF 0 "register_operand" "")
15873 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15874 (match_operand:SF 2 "nonimmediate_operand" ""))
15877 (clobber (reg:CC 17))]
15878 "SSE_REG_P (operands[0]) && reload_completed"
15879 [(set (match_dup 0)
15880 (if_then_else:SF (gt (match_dup 1)
15886 [(set (match_operand:SF 0 "register_operand" "")
15887 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15888 (match_operand:SF 2 "register_operand" ""))
15891 (clobber (reg:CC 17))]
15892 "FP_REG_P (operands[0]) && reload_completed"
15893 [(set (reg:CCFP 17)
15894 (compare:CCFP (match_dup 1)
15897 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
15901 (define_insn "*maxsf_sse"
15902 [(set (match_operand:SF 0 "register_operand" "=x")
15903 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
15904 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15907 "TARGET_SSE && reload_completed"
15908 "maxss\\t{%2, %0|%0, %2}"
15909 [(set_attr "type" "sse")
15910 (set_attr "mode" "SF")])
15912 (define_expand "maxdf3"
15914 (set (match_operand:DF 0 "register_operand" "")
15915 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15916 (match_operand:DF 2 "nonimmediate_operand" ""))
15919 (clobber (reg:CC 17))])]
15923 (define_insn "*maxdf"
15924 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15925 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15926 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
15929 (clobber (reg:CC 17))]
15930 "TARGET_SSE2 && TARGET_IEEE_FP"
15933 (define_insn "*maxdf_nonieee"
15934 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15935 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
15936 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15939 (clobber (reg:CC 17))]
15940 "TARGET_SSE2 && !TARGET_IEEE_FP"
15944 [(set (match_operand:DF 0 "register_operand" "")
15945 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15946 (match_operand:DF 2 "nonimmediate_operand" ""))
15949 (clobber (reg:CC 17))]
15950 "SSE_REG_P (operands[0]) && reload_completed"
15951 [(set (match_dup 0)
15952 (if_then_else:DF (gt (match_dup 1)
15958 [(set (match_operand:DF 0 "register_operand" "")
15959 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15960 (match_operand:DF 2 "register_operand" ""))
15963 (clobber (reg:CC 17))]
15964 "FP_REG_P (operands[0]) && reload_completed"
15965 [(set (reg:CCFP 17)
15966 (compare:CCFP (match_dup 1)
15969 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
15973 (define_insn "*maxdf_sse"
15974 [(set (match_operand:DF 0 "register_operand" "=Y")
15975 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
15976 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15979 "TARGET_SSE2 && reload_completed"
15980 "maxsd\\t{%2, %0|%0, %2}"
15981 [(set_attr "type" "sse")
15982 (set_attr "mode" "DF")])
15984 ;; Misc patterns (?)
15986 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
15987 ;; Otherwise there will be nothing to keep
15989 ;; [(set (reg ebp) (reg esp))]
15990 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
15991 ;; (clobber (eflags)]
15992 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
15994 ;; in proper program order.
15995 (define_expand "pro_epilogue_adjust_stack"
15996 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
15997 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
15998 (match_operand:SI 2 "immediate_operand" "i,i")))
15999 (set (match_operand:SI 3 "register_operand" "+r,r")
16001 (clobber (reg:CC 17))])]
16007 emit_insn (gen_pro_epilogue_adjust_stack_rex64 (operands[0], operands[1],
16008 operands[2], operands[3]));
16013 (define_insn "*pro_epilogue_adjust_stack_1"
16014 [(set (match_operand:SI 0 "register_operand" "=r,r")
16015 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16016 (match_operand:SI 2 "immediate_operand" "i,i")))
16017 (set (match_operand:SI 3 "register_operand" "+r,r")
16019 (clobber (reg:CC 17))]
16023 switch (get_attr_type (insn))
16026 return \"mov{l}\\t{%1, %0|%0, %1}\";
16029 if (GET_CODE (operands[2]) == CONST_INT
16030 && (INTVAL (operands[2]) == 128
16031 || (INTVAL (operands[2]) < 0
16032 && INTVAL (operands[2]) != -128)))
16034 operands[2] = GEN_INT (-INTVAL (operands[2]));
16035 return \"sub{l}\\t{%2, %0|%0, %2}\";
16037 return \"add{l}\\t{%2, %0|%0, %2}\";
16040 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16041 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
16047 [(set (attr "type")
16048 (cond [(eq_attr "alternative" "0")
16049 (const_string "alu")
16050 (match_operand:SI 2 "const0_operand" "")
16051 (const_string "imov")
16053 (const_string "lea")))
16054 (set_attr "mode" "SI")])
16056 (define_insn "pro_epilogue_adjust_stack_rex64"
16057 [(set (match_operand:DI 0 "register_operand" "=r,r")
16058 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16059 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16060 (set (match_operand:DI 3 "register_operand" "+r,r")
16062 (clobber (reg:CC 17))]
16066 switch (get_attr_type (insn))
16069 return \"mov{q}\\t{%1, %0|%0, %1}\";
16072 if (GET_CODE (operands[2]) == CONST_INT
16073 && (INTVAL (operands[2]) == 128
16074 || (INTVAL (operands[2]) < 0
16075 && INTVAL (operands[2]) != -128)))
16077 operands[2] = GEN_INT (-INTVAL (operands[2]));
16078 return \"sub{q}\\t{%2, %0|%0, %2}\";
16080 return \"add{q}\\t{%2, %0|%0, %2}\";
16083 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16084 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
16090 [(set (attr "type")
16091 (cond [(eq_attr "alternative" "0")
16092 (const_string "alu")
16093 (match_operand:DI 2 "const0_operand" "")
16094 (const_string "imov")
16096 (const_string "lea")))
16097 (set_attr "mode" "DI")])
16100 ;; Placeholder for the conditional moves. This one is split eighter to SSE
16101 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16102 ;; fact is that compares supported by the cmp??ss instructions are exactly
16103 ;; swapped of those supported by cmove sequence.
16104 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16105 ;; supported by i387 comparisons and we do need to emit two conditional moves
16108 (define_insn "sse_movsfcc"
16109 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16110 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16111 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16112 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16113 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16114 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16115 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16116 (clobber (reg:CC 17))]
16118 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16119 && (!TARGET_IEEE_FP
16120 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16123 (define_insn "sse_movsfcc_eq"
16124 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16125 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16126 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16127 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16128 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16129 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16130 (clobber (reg:CC 17))]
16132 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16135 (define_insn "sse_movdfcc"
16136 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16137 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16138 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16139 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16140 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16141 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16142 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16143 (clobber (reg:CC 17))]
16145 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16146 && (!TARGET_IEEE_FP
16147 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16150 (define_insn "sse_movdfcc_eq"
16151 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16152 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16153 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16154 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16155 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16156 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16157 (clobber (reg:CC 17))]
16159 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16162 ;; For non-sse moves just expand the usual cmove sequence.
16164 [(set (match_operand 0 "register_operand" "")
16165 (if_then_else (match_operator 1 "comparison_operator"
16166 [(match_operand 4 "nonimmediate_operand" "")
16167 (match_operand 5 "register_operand" "")])
16168 (match_operand 2 "nonimmediate_operand" "")
16169 (match_operand 3 "nonimmediate_operand" "")))
16170 (clobber (match_operand 6 "" ""))
16171 (clobber (reg:CC 17))]
16172 "!SSE_REG_P (operands[0]) && reload_completed
16173 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16177 ix86_compare_op0 = operands[5];
16178 ix86_compare_op1 = operands[4];
16179 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16180 VOIDmode, operands[5], operands[4]);
16181 ix86_expand_fp_movcc (operands);
16185 ;; Split SSE based conditional move into seqence:
16186 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16187 ;; and op2, op0 - zero op2 if comparison was false
16188 ;; nand op0, op3 - load op3 to op0 if comparison was false
16189 ;; or op2, op0 - get the non-zero one into the result.
16191 [(set (match_operand 0 "register_operand" "")
16192 (if_then_else (match_operator 1 "sse_comparison_operator"
16193 [(match_operand 4 "register_operand" "")
16194 (match_operand 5 "nonimmediate_operand" "")])
16195 (match_operand 2 "register_operand" "")
16196 (match_operand 3 "register_operand" "")))
16197 (clobber (match_operand 6 "" ""))
16198 (clobber (reg:CC 17))]
16199 "SSE_REG_P (operands[0]) && reload_completed"
16200 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16201 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16202 (subreg:TI (match_dup 4) 0)))
16203 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16204 (subreg:TI (match_dup 3) 0)))
16205 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16206 (subreg:TI (match_dup 7) 0)))]
16209 PUT_MODE (operands[1], GET_MODE (operands[0]));
16210 if (operands_match_p (operands[0], operands[4]))
16211 operands[6] = operands[4], operands[7] = operands[2];
16213 operands[6] = operands[2], operands[7] = operands[4];
16216 ;; Special case of conditional move we can handle effectivly.
16217 ;; Do not brother with the integer/floating point case, since these are
16218 ;; bot considerably slower, unlike in the generic case.
16219 (define_insn "*sse_movsfcc_const0_1"
16220 [(set (match_operand:SF 0 "register_operand" "=x")
16221 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16222 [(match_operand:SF 4 "register_operand" "0")
16223 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16224 (match_operand:SF 2 "register_operand" "x")
16225 (match_operand:SF 3 "const0_operand" "X")))]
16229 (define_insn "*sse_movsfcc_const0_2"
16230 [(set (match_operand:SF 0 "register_operand" "=x")
16231 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16232 [(match_operand:SF 4 "register_operand" "0")
16233 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16234 (match_operand:SF 2 "const0_operand" "x")
16235 (match_operand:SF 3 "register_operand" "X")))]
16239 (define_insn "*sse_movsfcc_const0_3"
16240 [(set (match_operand:SF 0 "register_operand" "=x")
16241 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16242 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16243 (match_operand:SF 5 "register_operand" "0")])
16244 (match_operand:SF 2 "register_operand" "x")
16245 (match_operand:SF 3 "const0_operand" "X")))]
16249 (define_insn "*sse_movsfcc_const0_4"
16250 [(set (match_operand:SF 0 "register_operand" "=x")
16251 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16252 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16253 (match_operand:SF 5 "register_operand" "0")])
16254 (match_operand:SF 2 "const0_operand" "x")
16255 (match_operand:SF 3 "register_operand" "X")))]
16259 (define_insn "*sse_movdfcc_const0_1"
16260 [(set (match_operand:SF 0 "register_operand" "=x")
16261 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16262 [(match_operand:SF 4 "register_operand" "0")
16263 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16264 (match_operand:SF 2 "register_operand" "x")
16265 (match_operand:SF 3 "const0_operand" "X")))]
16269 (define_insn "*sse_movdfcc_const0_2"
16270 [(set (match_operand:SF 0 "register_operand" "=x")
16271 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16272 [(match_operand:SF 4 "register_operand" "0")
16273 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16274 (match_operand:SF 2 "const0_operand" "x")
16275 (match_operand:SF 3 "register_operand" "X")))]
16279 (define_insn "*sse_movdfcc_const0_3"
16280 [(set (match_operand:SF 0 "register_operand" "=x")
16281 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16282 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16283 (match_operand:SF 5 "register_operand" "0")])
16284 (match_operand:SF 2 "register_operand" "x")
16285 (match_operand:SF 3 "const0_operand" "X")))]
16289 (define_insn "*sse_movdfcc_const0_4"
16290 [(set (match_operand:SF 0 "register_operand" "=x")
16291 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16292 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16293 (match_operand:SF 5 "register_operand" "0")])
16294 (match_operand:SF 2 "const0_operand" "x")
16295 (match_operand:SF 3 "register_operand" "X")))]
16300 [(set (match_operand 0 "register_operand" "")
16301 (if_then_else (match_operator 1 "comparison_operator"
16302 [(match_operand 4 "register_operand" "")
16303 (match_operand 5 "nonimmediate_operand" "")])
16304 (match_operand 2 "nonmemory_operand" "")
16305 (match_operand 3 "nonmemory_operand" "")))]
16306 "SSE_REG_P (operands[0]) && reload_completed
16307 && (const0_operand (operands[2], GET_MODE (operands[0]))
16308 || const0_operand (operands[3], GET_MODE (operands[0])))"
16309 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16310 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16311 (subreg:TI (match_dup 7) 0)))]
16314 PUT_MODE (operands[1], GET_MODE (operands[0]));
16315 if (!sse_comparison_operator (operands[1], VOIDmode))
16317 rtx tmp = operands[5];
16318 operands[5] = operands[4];
16320 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16322 if (const0_operand (operands[2], GET_MODE (operands[0])))
16324 operands[7] = operands[3];
16325 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16330 operands[7] = operands[2];
16331 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16335 (define_expand "allocate_stack_worker"
16336 [(match_operand:SI 0 "register_operand" "")]
16337 "TARGET_STACK_PROBE"
16341 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16343 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16347 (define_insn "allocate_stack_worker_1"
16348 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
16349 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16350 (clobber (match_dup 0))
16351 (clobber (reg:CC 17))]
16352 "TARGET_STACK_PROBE && !TARGET_64BIT"
16354 [(set_attr "type" "multi")
16355 (set_attr "length" "5")])
16357 (define_insn "allocate_stack_worker_rex64"
16358 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
16359 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16360 (clobber (match_dup 0))
16361 (clobber (reg:CC 17))]
16362 "TARGET_STACK_PROBE && TARGET_64BIT"
16364 [(set_attr "type" "multi")
16365 (set_attr "length" "5")])
16367 (define_expand "allocate_stack"
16368 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16369 (minus:SI (reg:SI 7)
16370 (match_operand:SI 1 "general_operand" "")))
16371 (clobber (reg:CC 17))])
16372 (parallel [(set (reg:SI 7)
16373 (minus:SI (reg:SI 7) (match_dup 1)))
16374 (clobber (reg:CC 17))])]
16375 "TARGET_STACK_PROBE"
16378 #ifdef CHECK_STACK_LIMIT
16379 if (GET_CODE (operands[1]) == CONST_INT
16380 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16381 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16385 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16388 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16392 (define_expand "builtin_setjmp_receiver"
16393 [(label_ref (match_operand 0 "" ""))]
16394 "flag_pic && !TARGET_64BIT"
16397 load_pic_register ();
16401 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16404 [(set (match_operand 0 "register_operand" "")
16405 (match_operator 3 "promotable_binary_operator"
16406 [(match_operand 1 "register_operand" "")
16407 (match_operand 2 "aligned_operand" "")]))
16408 (clobber (reg:CC 17))]
16409 "! TARGET_PARTIAL_REG_STALL && reload_completed
16410 && ((GET_MODE (operands[0]) == HImode
16411 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16412 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16413 || (GET_MODE (operands[0]) == QImode
16414 && (TARGET_PROMOTE_QImode || optimize_size)))"
16415 [(parallel [(set (match_dup 0)
16416 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16417 (clobber (reg:CC 17))])]
16418 "operands[0] = gen_lowpart (SImode, operands[0]);
16419 operands[1] = gen_lowpart (SImode, operands[1]);
16420 if (GET_CODE (operands[3]) != ASHIFT)
16421 operands[2] = gen_lowpart (SImode, operands[2]);
16422 PUT_MODE (operands[3], SImode);")
16426 (compare (and (match_operand 1 "aligned_operand" "")
16427 (match_operand 2 "const_int_operand" ""))
16429 (set (match_operand 0 "register_operand" "")
16430 (and (match_dup 1) (match_dup 2)))]
16431 "! TARGET_PARTIAL_REG_STALL && reload_completed
16432 && ix86_match_ccmode (insn, CCNOmode)
16433 && (GET_MODE (operands[0]) == HImode
16434 || (GET_MODE (operands[0]) == QImode
16435 && (TARGET_PROMOTE_QImode || optimize_size)))"
16436 [(parallel [(set (reg:CCNO 17)
16437 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16440 (and:SI (match_dup 1) (match_dup 2)))])]
16442 = GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
16443 & GET_MODE_MASK (GET_MODE (operands[0])),
16445 operands[0] = gen_lowpart (SImode, operands[0]);
16446 operands[1] = gen_lowpart (SImode, operands[1]);")
16450 (compare (and (match_operand 0 "aligned_operand" "")
16451 (match_operand 1 "const_int_operand" ""))
16453 "! TARGET_PARTIAL_REG_STALL && reload_completed
16454 && ix86_match_ccmode (insn, CCNOmode)
16455 && (GET_MODE (operands[0]) == HImode
16456 || (GET_MODE (operands[0]) == QImode
16457 && (TARGET_PROMOTE_QImode || optimize_size)))"
16458 [(set (reg:CCNO 17)
16459 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16462 = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
16463 & GET_MODE_MASK (GET_MODE (operands[0])),
16465 operands[0] = gen_lowpart (SImode, operands[0]);")
16468 [(set (match_operand 0 "register_operand" "")
16469 (neg (match_operand 1 "register_operand" "")))
16470 (clobber (reg:CC 17))]
16471 "! TARGET_PARTIAL_REG_STALL && reload_completed
16472 && (GET_MODE (operands[0]) == HImode
16473 || (GET_MODE (operands[0]) == QImode
16474 && (TARGET_PROMOTE_QImode || optimize_size)))"
16475 [(parallel [(set (match_dup 0)
16476 (neg:SI (match_dup 1)))
16477 (clobber (reg:CC 17))])]
16478 "operands[0] = gen_lowpart (SImode, operands[0]);
16479 operands[1] = gen_lowpart (SImode, operands[1]);")
16482 [(set (match_operand 0 "register_operand" "")
16483 (not (match_operand 1 "register_operand" "")))]
16484 "! TARGET_PARTIAL_REG_STALL && reload_completed
16485 && (GET_MODE (operands[0]) == HImode
16486 || (GET_MODE (operands[0]) == QImode
16487 && (TARGET_PROMOTE_QImode || optimize_size)))"
16488 [(set (match_dup 0)
16489 (not:SI (match_dup 1)))]
16490 "operands[0] = gen_lowpart (SImode, operands[0]);
16491 operands[1] = gen_lowpart (SImode, operands[1]);")
16494 [(set (match_operand 0 "register_operand" "")
16495 (if_then_else (match_operator 1 "comparison_operator"
16496 [(reg 17) (const_int 0)])
16497 (match_operand 2 "register_operand" "")
16498 (match_operand 3 "register_operand" "")))]
16499 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16500 && (GET_MODE (operands[0]) == HImode
16501 || (GET_MODE (operands[0]) == QImode
16502 && (TARGET_PROMOTE_QImode || optimize_size)))"
16503 [(set (match_dup 0)
16504 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16505 "operands[0] = gen_lowpart (SImode, operands[0]);
16506 operands[2] = gen_lowpart (SImode, operands[2]);
16507 operands[3] = gen_lowpart (SImode, operands[3]);")
16510 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16511 ;; transform a complex memory operation into two memory to register operations.
16513 ;; Don't push memory operands
16515 [(set (match_operand:SI 0 "push_operand" "")
16516 (match_operand:SI 1 "memory_operand" ""))
16517 (match_scratch:SI 2 "r")]
16518 "! optimize_size && ! TARGET_PUSH_MEMORY"
16519 [(set (match_dup 2) (match_dup 1))
16520 (set (match_dup 0) (match_dup 2))]
16524 [(set (match_operand:DI 0 "push_operand" "")
16525 (match_operand:DI 1 "memory_operand" ""))
16526 (match_scratch:DI 2 "r")]
16527 "! optimize_size && ! TARGET_PUSH_MEMORY"
16528 [(set (match_dup 2) (match_dup 1))
16529 (set (match_dup 0) (match_dup 2))]
16532 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16535 [(set (match_operand:SF 0 "push_operand" "")
16536 (match_operand:SF 1 "memory_operand" ""))
16537 (match_scratch:SF 2 "r")]
16538 "! optimize_size && ! TARGET_PUSH_MEMORY"
16539 [(set (match_dup 2) (match_dup 1))
16540 (set (match_dup 0) (match_dup 2))]
16544 [(set (match_operand:HI 0 "push_operand" "")
16545 (match_operand:HI 1 "memory_operand" ""))
16546 (match_scratch:HI 2 "r")]
16547 "! optimize_size && ! TARGET_PUSH_MEMORY"
16548 [(set (match_dup 2) (match_dup 1))
16549 (set (match_dup 0) (match_dup 2))]
16553 [(set (match_operand:QI 0 "push_operand" "")
16554 (match_operand:QI 1 "memory_operand" ""))
16555 (match_scratch:QI 2 "q")]
16556 "! optimize_size && ! TARGET_PUSH_MEMORY"
16557 [(set (match_dup 2) (match_dup 1))
16558 (set (match_dup 0) (match_dup 2))]
16561 ;; Don't move an immediate directly to memory when the instruction
16564 [(match_scratch:SI 1 "r")
16565 (set (match_operand:SI 0 "memory_operand" "")
16568 && ! TARGET_USE_MOV0
16569 && TARGET_SPLIT_LONG_MOVES
16570 && get_attr_length (insn) >= ix86_cost->large_insn
16571 && peep2_regno_dead_p (0, FLAGS_REG)"
16572 [(parallel [(set (match_dup 1) (const_int 0))
16573 (clobber (reg:CC 17))])
16574 (set (match_dup 0) (match_dup 1))]
16578 [(match_scratch:HI 1 "r")
16579 (set (match_operand:HI 0 "memory_operand" "")
16582 && ! TARGET_USE_MOV0
16583 && TARGET_SPLIT_LONG_MOVES
16584 && get_attr_length (insn) >= ix86_cost->large_insn
16585 && peep2_regno_dead_p (0, FLAGS_REG)"
16586 [(parallel [(set (match_dup 2) (const_int 0))
16587 (clobber (reg:CC 17))])
16588 (set (match_dup 0) (match_dup 1))]
16589 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16592 [(match_scratch:QI 1 "q")
16593 (set (match_operand:QI 0 "memory_operand" "")
16596 && ! TARGET_USE_MOV0
16597 && TARGET_SPLIT_LONG_MOVES
16598 && get_attr_length (insn) >= ix86_cost->large_insn
16599 && peep2_regno_dead_p (0, FLAGS_REG)"
16600 [(parallel [(set (match_dup 2) (const_int 0))
16601 (clobber (reg:CC 17))])
16602 (set (match_dup 0) (match_dup 1))]
16603 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16606 [(match_scratch:SI 2 "r")
16607 (set (match_operand:SI 0 "memory_operand" "")
16608 (match_operand:SI 1 "immediate_operand" ""))]
16610 && get_attr_length (insn) >= ix86_cost->large_insn
16611 && TARGET_SPLIT_LONG_MOVES"
16612 [(set (match_dup 2) (match_dup 1))
16613 (set (match_dup 0) (match_dup 2))]
16617 [(match_scratch:HI 2 "r")
16618 (set (match_operand:HI 0 "memory_operand" "")
16619 (match_operand:HI 1 "immediate_operand" ""))]
16620 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16621 && TARGET_SPLIT_LONG_MOVES"
16622 [(set (match_dup 2) (match_dup 1))
16623 (set (match_dup 0) (match_dup 2))]
16627 [(match_scratch:QI 2 "q")
16628 (set (match_operand:QI 0 "memory_operand" "")
16629 (match_operand:QI 1 "immediate_operand" ""))]
16630 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16631 && TARGET_SPLIT_LONG_MOVES"
16632 [(set (match_dup 2) (match_dup 1))
16633 (set (match_dup 0) (match_dup 2))]
16636 ;; Don't compare memory with zero, load and use a test instead.
16639 (compare (match_operand:SI 0 "memory_operand" "")
16641 (match_scratch:SI 3 "r")]
16642 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16643 [(set (match_dup 3) (match_dup 0))
16644 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16647 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16648 ;; Don't split NOTs with a displacement operand, because resulting XOR
16649 ;; will not be pariable anyway.
16651 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16652 ;; represented using a modRM byte. The XOR replacement is long decoded,
16653 ;; so this split helps here as well.
16655 ;; Note: Can't do this as a regular split because we can't get proper
16656 ;; lifetime information then.
16659 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
16660 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
16662 && peep2_regno_dead_p (0, FLAGS_REG)
16663 && ((TARGET_PENTIUM
16664 && (GET_CODE (operands[0]) != MEM
16665 || !memory_displacement_operand (operands[0], SImode)))
16666 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16667 [(parallel [(set (match_dup 0)
16668 (xor:SI (match_dup 1) (const_int -1)))
16669 (clobber (reg:CC 17))])]
16673 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
16674 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
16676 && peep2_regno_dead_p (0, FLAGS_REG)
16677 && ((TARGET_PENTIUM
16678 && (GET_CODE (operands[0]) != MEM
16679 || !memory_displacement_operand (operands[0], HImode)))
16680 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16681 [(parallel [(set (match_dup 0)
16682 (xor:HI (match_dup 1) (const_int -1)))
16683 (clobber (reg:CC 17))])]
16687 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
16688 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
16690 && peep2_regno_dead_p (0, FLAGS_REG)
16691 && ((TARGET_PENTIUM
16692 && (GET_CODE (operands[0]) != MEM
16693 || !memory_displacement_operand (operands[0], QImode)))
16694 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16695 [(parallel [(set (match_dup 0)
16696 (xor:QI (match_dup 1) (const_int -1)))
16697 (clobber (reg:CC 17))])]
16700 ;; Non pairable "test imm, reg" instructions can be translated to
16701 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16702 ;; byte opcode instead of two, have a short form for byte operands),
16703 ;; so do it for other CPUs as well. Given that the value was dead,
16704 ;; this should not create any new dependancies. Pass on the sub-word
16705 ;; versions if we're concerned about partial register stalls.
16709 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16710 (match_operand:SI 1 "immediate_operand" ""))
16712 "ix86_match_ccmode (insn, CCNOmode)
16713 && (true_regnum (operands[0]) != 0
16714 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
16715 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16717 [(set (reg:CCNO 17)
16718 (compare:CCNO (and:SI (match_dup 0)
16722 (and:SI (match_dup 0) (match_dup 1)))])]
16725 ;; We don't need to handle HImode case, because it will be promoted to SImode
16726 ;; on ! TARGET_PARTIAL_REG_STALL
16730 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16731 (match_operand:QI 1 "immediate_operand" ""))
16733 "! TARGET_PARTIAL_REG_STALL
16734 && ix86_match_ccmode (insn, CCNOmode)
16735 && true_regnum (operands[0]) != 0
16736 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16738 [(set (reg:CCNO 17)
16739 (compare:CCNO (and:QI (match_dup 0)
16743 (and:QI (match_dup 0) (match_dup 1)))])]
16751 (match_operand 0 "ext_register_operand" "q")
16754 (match_operand 1 "const_int_operand" "n"))
16756 "! TARGET_PARTIAL_REG_STALL
16757 && ix86_match_ccmode (insn, CCNOmode)
16758 && true_regnum (operands[0]) != 0
16759 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16760 [(parallel [(set (reg:CCNO 17)
16769 (set (zero_extract:SI (match_dup 0)
16780 ;; Don't do logical operations with memory inputs.
16782 [(match_scratch:SI 2 "r")
16783 (parallel [(set (match_operand:SI 0 "register_operand" "")
16784 (match_operator:SI 3 "arith_or_logical_operator"
16786 (match_operand:SI 1 "memory_operand" "")]))
16787 (clobber (reg:CC 17))])]
16788 "! optimize_size && ! TARGET_READ_MODIFY"
16789 [(set (match_dup 2) (match_dup 1))
16790 (parallel [(set (match_dup 0)
16791 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16792 (clobber (reg:CC 17))])]
16796 [(match_scratch:SI 2 "r")
16797 (parallel [(set (match_operand:SI 0 "register_operand" "")
16798 (match_operator:SI 3 "arith_or_logical_operator"
16799 [(match_operand:SI 1 "memory_operand" "")
16801 (clobber (reg:CC 17))])]
16802 "! optimize_size && ! TARGET_READ_MODIFY"
16803 [(set (match_dup 2) (match_dup 1))
16804 (parallel [(set (match_dup 0)
16805 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
16806 (clobber (reg:CC 17))])]
16809 ; Don't do logical operations with memory outputs
16811 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
16812 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
16813 ; the same decoder scheduling characteristics as the original.
16816 [(match_scratch:SI 2 "r")
16817 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16818 (match_operator:SI 3 "arith_or_logical_operator"
16820 (match_operand:SI 1 "nonmemory_operand" "")]))
16821 (clobber (reg:CC 17))])]
16822 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16823 [(set (match_dup 2) (match_dup 0))
16824 (parallel [(set (match_dup 2)
16825 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
16826 (clobber (reg:CC 17))])
16827 (set (match_dup 0) (match_dup 2))]
16831 [(match_scratch:SI 2 "r")
16832 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16833 (match_operator:SI 3 "arith_or_logical_operator"
16834 [(match_operand:SI 1 "nonmemory_operand" "")
16836 (clobber (reg:CC 17))])]
16837 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16838 [(set (match_dup 2) (match_dup 0))
16839 (parallel [(set (match_dup 2)
16840 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16841 (clobber (reg:CC 17))])
16842 (set (match_dup 0) (match_dup 2))]
16845 ;; Attempt to always use XOR for zeroing registers.
16847 [(set (match_operand 0 "register_operand" "")
16849 "(GET_MODE (operands[0]) == QImode
16850 || GET_MODE (operands[0]) == HImode
16851 || GET_MODE (operands[0]) == SImode
16852 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16853 && (! TARGET_USE_MOV0 || optimize_size)
16854 && peep2_regno_dead_p (0, FLAGS_REG)"
16855 [(parallel [(set (match_dup 0) (const_int 0))
16856 (clobber (reg:CC 17))])]
16857 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16858 true_regnum (operands[0]));")
16861 [(set (strict_low_part (match_operand 0 "register_operand" ""))
16863 "(GET_MODE (operands[0]) == QImode
16864 || GET_MODE (operands[0]) == HImode)
16865 && (! TARGET_USE_MOV0 || optimize_size)
16866 && peep2_regno_dead_p (0, FLAGS_REG)"
16867 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
16868 (clobber (reg:CC 17))])])
16870 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
16872 [(set (match_operand 0 "register_operand" "")
16874 "(GET_MODE (operands[0]) == HImode
16875 || GET_MODE (operands[0]) == SImode
16876 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16877 && (optimize_size || TARGET_PENTIUM)
16878 && peep2_regno_dead_p (0, FLAGS_REG)"
16879 [(parallel [(set (match_dup 0) (const_int -1))
16880 (clobber (reg:CC 17))])]
16881 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16882 true_regnum (operands[0]));")
16884 ;; Attempt to convert simple leas to adds. These can be created by
16887 [(set (match_operand:SI 0 "register_operand" "")
16888 (plus:SI (match_dup 0)
16889 (match_operand:SI 1 "nonmemory_operand" "")))]
16890 "peep2_regno_dead_p (0, FLAGS_REG)"
16891 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
16892 (clobber (reg:CC 17))])]
16896 [(set (match_operand:SI 0 "register_operand" "")
16897 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
16898 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
16899 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
16900 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
16901 (clobber (reg:CC 17))])]
16902 "operands[2] = gen_lowpart (SImode, operands[2]);")
16905 [(set (match_operand:DI 0 "register_operand" "")
16906 (plus:DI (match_dup 0)
16907 (match_operand:DI 1 "x86_64_general_operand" "")))]
16908 "peep2_regno_dead_p (0, FLAGS_REG)"
16909 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
16910 (clobber (reg:CC 17))])]
16914 [(set (match_operand:SI 0 "register_operand" "")
16915 (mult:SI (match_dup 0)
16916 (match_operand:SI 1 "const_int_operand" "")))]
16917 "exact_log2 (INTVAL (operands[1])) >= 0
16918 && peep2_regno_dead_p (0, FLAGS_REG)"
16919 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16920 (clobber (reg:CC 17))])]
16921 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16924 [(set (match_operand:DI 0 "register_operand" "")
16925 (mult:DI (match_dup 0)
16926 (match_operand:DI 1 "const_int_operand" "")))]
16927 "exact_log2 (INTVAL (operands[1])) >= 0
16928 && peep2_regno_dead_p (0, FLAGS_REG)"
16929 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
16930 (clobber (reg:CC 17))])]
16931 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16934 [(set (match_operand:SI 0 "register_operand" "")
16935 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
16936 (match_operand:DI 2 "const_int_operand" "")) 0))]
16937 "exact_log2 (INTVAL (operands[1])) >= 0
16938 && REGNO (operands[0]) == REGNO (operands[1])
16939 && peep2_regno_dead_p (0, FLAGS_REG)"
16940 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16941 (clobber (reg:CC 17))])]
16942 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
16944 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
16945 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
16946 ;; many CPUs it is also faster, since special hardware to avoid esp
16947 ;; dependancies is present.
16949 ;; While some of these converisons may be done using splitters, we use peepholes
16950 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
16952 ;; Convert prologue esp substractions to push.
16953 ;; We need register to push. In order to keep verify_flow_info happy we have
16955 ;; - use scratch and clobber it in order to avoid dependencies
16956 ;; - use already live register
16957 ;; We can't use the second way right now, since there is no reliable way how to
16958 ;; verify that given register is live. First choice will also most likely in
16959 ;; fewer dependencies. On the place of esp adjustments it is very likely that
16960 ;; call clobbered registers are dead. We may want to use base pointer as an
16961 ;; alternative when no register is available later.
16964 [(match_scratch:SI 0 "r")
16965 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
16966 (set (reg:SI 6) (reg:SI 6))
16967 (clobber (reg:CC 17))])]
16968 "optimize_size || !TARGET_SUB_ESP_4"
16969 [(clobber (match_dup 0))
16970 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16971 (set (reg:SI 6) (reg:SI 6))])])
16974 [(match_scratch:SI 0 "r")
16975 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
16976 (set (reg:SI 6) (reg:SI 6))
16977 (clobber (reg:CC 17))])]
16978 "optimize_size || !TARGET_SUB_ESP_8"
16979 [(clobber (match_dup 0))
16980 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16981 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16982 (set (reg:SI 6) (reg:SI 6))])])
16984 ;; Convert esp substractions to push.
16986 [(match_scratch:SI 0 "r")
16987 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
16988 (clobber (reg:CC 17))])]
16989 "optimize_size || !TARGET_SUB_ESP_4"
16990 [(clobber (match_dup 0))
16991 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
16994 [(match_scratch:SI 0 "r")
16995 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
16996 (clobber (reg:CC 17))])]
16997 "optimize_size || !TARGET_SUB_ESP_8"
16998 [(clobber (match_dup 0))
16999 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17000 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17002 ;; Convert epilogue deallocator to pop.
17004 [(match_scratch:SI 0 "r")
17005 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17006 (set (reg:SI 6) (reg:SI 6))
17007 (clobber (reg:CC 17))])]
17008 "optimize_size || !TARGET_ADD_ESP_4"
17009 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17010 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17011 (set (reg:SI 6) (reg:SI 6))])]
17014 ;; Two pops case is tricky, since pop causes dependency on destination register.
17015 ;; We use two registers if available.
17017 [(match_scratch:SI 0 "r")
17018 (match_scratch:SI 1 "r")
17019 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17020 (set (reg:SI 6) (reg:SI 6))
17021 (clobber (reg:CC 17))])]
17022 "optimize_size || !TARGET_ADD_ESP_8"
17023 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17024 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17025 (set (reg:SI 6) (reg:SI 6))])
17026 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17027 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17031 [(match_scratch:SI 0 "r")
17032 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17033 (set (reg:SI 6) (reg:SI 6))
17034 (clobber (reg:CC 17))])]
17036 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17037 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17038 (set (reg:SI 6) (reg:SI 6))])
17039 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17040 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17043 ;; Convert esp additions to pop.
17045 [(match_scratch:SI 0 "r")
17046 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17047 (clobber (reg:CC 17))])]
17049 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17050 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17053 ;; Two pops case is tricky, since pop causes dependency on destination register.
17054 ;; We use two registers if available.
17056 [(match_scratch:SI 0 "r")
17057 (match_scratch:SI 1 "r")
17058 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17059 (clobber (reg:CC 17))])]
17061 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17062 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17063 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17064 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17068 [(match_scratch:SI 0 "r")
17069 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17070 (clobber (reg:CC 17))])]
17072 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17073 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17074 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17075 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17078 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17079 ;; required and register dies.
17082 (compare (match_operand:SI 0 "register_operand" "")
17083 (match_operand:SI 1 "incdec_operand" "")))]
17084 "ix86_match_ccmode (insn, CCGCmode)
17085 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17086 [(parallel [(set (reg:CCGC 17)
17087 (compare:CCGC (match_dup 0)
17089 (clobber (match_dup 0))])]
17094 (compare (match_operand:HI 0 "register_operand" "")
17095 (match_operand:HI 1 "incdec_operand" "")))]
17096 "ix86_match_ccmode (insn, CCGCmode)
17097 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17098 [(parallel [(set (reg:CCGC 17)
17099 (compare:CCGC (match_dup 0)
17101 (clobber (match_dup 0))])]
17106 (compare (match_operand:QI 0 "register_operand" "")
17107 (match_operand:QI 1 "incdec_operand" "")))]
17108 "ix86_match_ccmode (insn, CCGCmode)
17109 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17110 [(parallel [(set (reg:CCGC 17)
17111 (compare:CCGC (match_dup 0)
17113 (clobber (match_dup 0))])]
17116 ;; Convert compares with 128 to shorter add -128
17119 (compare (match_operand:SI 0 "register_operand" "")
17121 "ix86_match_ccmode (insn, CCGCmode)
17122 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17123 [(parallel [(set (reg:CCGC 17)
17124 (compare:CCGC (match_dup 0)
17126 (clobber (match_dup 0))])]
17131 (compare (match_operand:HI 0 "register_operand" "")
17133 "ix86_match_ccmode (insn, CCGCmode)
17134 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17135 [(parallel [(set (reg:CCGC 17)
17136 (compare:CCGC (match_dup 0)
17138 (clobber (match_dup 0))])]
17142 [(match_scratch:DI 0 "r")
17143 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17144 (set (reg:DI 6) (reg:DI 6))
17145 (clobber (reg:CC 17))])]
17146 "optimize_size || !TARGET_SUB_ESP_4"
17147 [(clobber (match_dup 0))
17148 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17149 (set (reg:DI 6) (reg:DI 6))])])
17152 [(match_scratch:DI 0 "r")
17153 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17154 (set (reg:DI 6) (reg:DI 6))
17155 (clobber (reg:CC 17))])]
17156 "optimize_size || !TARGET_SUB_ESP_8"
17157 [(clobber (match_dup 0))
17158 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17159 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17160 (set (reg:DI 6) (reg:DI 6))])])
17162 ;; Convert esp substractions to push.
17164 [(match_scratch:DI 0 "r")
17165 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17166 (clobber (reg:CC 17))])]
17167 "optimize_size || !TARGET_SUB_ESP_4"
17168 [(clobber (match_dup 0))
17169 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17172 [(match_scratch:DI 0 "r")
17173 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17174 (clobber (reg:CC 17))])]
17175 "optimize_size || !TARGET_SUB_ESP_8"
17176 [(clobber (match_dup 0))
17177 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17178 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17180 ;; Convert epilogue deallocator to pop.
17182 [(match_scratch:DI 0 "r")
17183 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17184 (set (reg:DI 6) (reg:DI 6))
17185 (clobber (reg:CC 17))])]
17186 "optimize_size || !TARGET_ADD_ESP_4"
17187 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17188 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17189 (set (reg:DI 6) (reg:DI 6))])]
17192 ;; Two pops case is tricky, since pop causes dependency on destination register.
17193 ;; We use two registers if available.
17195 [(match_scratch:DI 0 "r")
17196 (match_scratch:DI 1 "r")
17197 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17198 (set (reg:DI 6) (reg:DI 6))
17199 (clobber (reg:CC 17))])]
17200 "optimize_size || !TARGET_ADD_ESP_8"
17201 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17202 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17203 (set (reg:DI 6) (reg:DI 6))])
17204 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17205 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17209 [(match_scratch:DI 0 "r")
17210 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17211 (set (reg:DI 6) (reg:DI 6))
17212 (clobber (reg:CC 17))])]
17214 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17215 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17216 (set (reg:DI 6) (reg:DI 6))])
17217 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17218 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17221 ;; Convert esp additions to pop.
17223 [(match_scratch:DI 0 "r")
17224 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17225 (clobber (reg:CC 17))])]
17227 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17228 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17231 ;; Two pops case is tricky, since pop causes dependency on destination register.
17232 ;; We use two registers if available.
17234 [(match_scratch:DI 0 "r")
17235 (match_scratch:DI 1 "r")
17236 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17237 (clobber (reg:CC 17))])]
17239 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17240 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17241 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17242 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17246 [(match_scratch:DI 0 "r")
17247 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17248 (clobber (reg:CC 17))])]
17250 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17251 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17252 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17253 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17256 ;; Call-value patterns last so that the wildcard operand does not
17257 ;; disrupt insn-recog's switch tables.
17259 (define_insn "*call_value_pop_0"
17260 [(set (match_operand 0 "" "")
17261 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17262 (match_operand:SI 2 "" "")))
17263 (set (reg:SI 7) (plus:SI (reg:SI 7)
17264 (match_operand:SI 3 "immediate_operand" "")))]
17268 if (SIBLING_CALL_P (insn))
17269 return \"jmp\\t%P1\";
17271 return \"call\\t%P1\";
17273 [(set_attr "type" "callv")])
17275 (define_insn "*call_value_pop_1"
17276 [(set (match_operand 0 "" "")
17277 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17278 (match_operand:SI 2 "" "")))
17279 (set (reg:SI 7) (plus:SI (reg:SI 7)
17280 (match_operand:SI 3 "immediate_operand" "i")))]
17284 if (constant_call_address_operand (operands[1], QImode))
17286 if (SIBLING_CALL_P (insn))
17287 return \"jmp\\t%P1\";
17289 return \"call\\t%P1\";
17291 if (SIBLING_CALL_P (insn))
17292 return \"jmp\\t%A1\";
17294 return \"call\\t%A1\";
17296 [(set_attr "type" "callv")])
17298 (define_insn "*call_value_0"
17299 [(set (match_operand 0 "" "")
17300 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17301 (match_operand:SI 2 "" "")))]
17305 if (SIBLING_CALL_P (insn))
17306 return \"jmp\\t%P1\";
17308 return \"call\\t%P1\";
17310 [(set_attr "type" "callv")])
17312 (define_insn "*call_value_0_rex64"
17313 [(set (match_operand 0 "" "")
17314 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17315 (match_operand:DI 2 "const_int_operand" "")))]
17319 if (SIBLING_CALL_P (insn))
17320 return \"jmp\\t%P1\";
17322 return \"call\\t%P1\";
17324 [(set_attr "type" "callv")])
17326 (define_insn "*call_value_1"
17327 [(set (match_operand 0 "" "")
17328 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17329 (match_operand:SI 2 "" "")))]
17333 if (constant_call_address_operand (operands[1], QImode))
17335 if (SIBLING_CALL_P (insn))
17336 return \"jmp\\t%P1\";
17338 return \"call\\t%P1\";
17340 if (SIBLING_CALL_P (insn))
17341 return \"jmp\\t%*%1\";
17343 return \"call\\t%*%1\";
17345 [(set_attr "type" "callv")])
17347 (define_insn "*call_value_1_rex64"
17348 [(set (match_operand 0 "" "")
17349 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17350 (match_operand:DI 2 "" "")))]
17354 if (constant_call_address_operand (operands[1], QImode))
17356 if (SIBLING_CALL_P (insn))
17357 return \"jmp\\t%P1\";
17359 return \"call\\t%P1\";
17361 if (SIBLING_CALL_P (insn))
17362 return \"jmp\\t%A1\";
17364 return \"call\\t%A1\";
17366 [(set_attr "type" "callv")])
17368 (define_insn "trap"
17369 [(trap_if (const_int 1) (const_int 5))]
17373 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17374 ;;; for the sake of bounds checking. By emitting bounds checks as
17375 ;;; conditional traps rather than as conditional jumps around
17376 ;;; unconditional traps we avoid introducing spurious basic-block
17377 ;;; boundaries and facilitate elimination of redundant checks. In
17378 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17381 ;;; FIXME: Static branch prediction rules for ix86 are such that
17382 ;;; forward conditional branches predict as untaken. As implemented
17383 ;;; below, pseudo conditional traps violate that rule. We should use
17384 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17385 ;;; section loaded at the end of the text segment and branch forward
17386 ;;; there on bounds-failure, and then jump back immediately (in case
17387 ;;; the system chooses to ignore bounds violations, or to report
17388 ;;; violations and continue execution).
17390 (define_expand "conditional_trap"
17391 [(trap_if (match_operator 0 "comparison_operator"
17392 [(match_dup 2) (const_int 0)])
17393 (match_operand 1 "const_int_operand" ""))]
17397 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17398 ix86_expand_compare (GET_CODE (operands[0]),
17405 [(trap_if (match_operator 0 "comparison_operator"
17406 [(reg 17) (const_int 0)])
17407 (match_operand 1 "const_int_operand" ""))]
17411 operands[2] = gen_label_rtx ();
17412 output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
17413 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
17414 CODE_LABEL_NUMBER (operands[2]));
17418 ;; Pentium III SIMD instructions.
17420 ;; Moves for SSE/MMX regs.
17422 (define_insn "movv4sf_internal"
17423 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17424 (match_operand:V4SF 1 "general_operand" "xm,x"))]
17426 ;; @@@ let's try to use movaps here.
17427 "movaps\\t{%1, %0|%0, %1}"
17428 [(set_attr "type" "sse")])
17430 (define_insn "movv4si_internal"
17431 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17432 (match_operand:V4SI 1 "general_operand" "xm,x"))]
17434 ;; @@@ let's try to use movaps here.
17435 "movaps\\t{%1, %0|%0, %1}"
17436 [(set_attr "type" "sse")])
17438 (define_insn "movv8qi_internal"
17439 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17440 (match_operand:V8QI 1 "general_operand" "ym,y"))]
17442 "movq\\t{%1, %0|%0, %1}"
17443 [(set_attr "type" "mmx")])
17445 (define_insn "movv4hi_internal"
17446 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17447 (match_operand:V4HI 1 "general_operand" "ym,y"))]
17449 "movq\\t{%1, %0|%0, %1}"
17450 [(set_attr "type" "mmx")])
17452 (define_insn "movv2si_internal"
17453 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17454 (match_operand:V2SI 1 "general_operand" "ym,y"))]
17456 "movq\\t{%1, %0|%0, %1}"
17457 [(set_attr "type" "mmx")])
17459 (define_expand "movti"
17460 [(set (match_operand:TI 0 "general_operand" "")
17461 (match_operand:TI 1 "general_operand" ""))]
17465 /* For constants other than zero into memory. We do not know how the
17466 instructions used to build constants modify the upper 64 bits
17467 of the register, once we have that information we may be able
17468 to handle some of them more efficiently. */
17469 if ((reload_in_progress | reload_completed) == 0
17470 && register_operand (operands[0], TImode)
17471 && CONSTANT_P (operands[1]))
17473 rtx addr = gen_reg_rtx (Pmode);
17475 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
17476 operands[1] = gen_rtx_MEM (TImode, addr);
17479 /* Make operand1 a register if it isn't already. */
17480 if ((reload_in_progress | reload_completed) == 0
17481 && !register_operand (operands[0], TImode)
17482 && !register_operand (operands[1], TImode)
17483 && operands[1] != CONST0_RTX (TImode))
17485 rtx temp = force_reg (TImode, operands[1]);
17486 emit_move_insn (operands[0], temp);
17491 (define_expand "movv4sf"
17492 [(set (match_operand:V4SF 0 "general_operand" "")
17493 (match_operand:V4SF 1 "general_operand" ""))]
17497 /* For constants other than zero into memory. We do not know how the
17498 instructions used to build constants modify the upper 64 bits
17499 of the register, once we have that information we may be able
17500 to handle some of them more efficiently. */
17501 if ((reload_in_progress | reload_completed) == 0
17502 && register_operand (operands[0], V4SFmode)
17503 && CONSTANT_P (operands[1]))
17505 rtx addr = gen_reg_rtx (Pmode);
17507 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
17508 operands[1] = gen_rtx_MEM (V4SFmode, addr);
17511 /* Make operand1 a register if it isn't already. */
17512 if ((reload_in_progress | reload_completed) == 0
17513 && !register_operand (operands[0], V4SFmode)
17514 && !register_operand (operands[1], V4SFmode)
17515 && operands[1] != CONST0_RTX (V4SFmode))
17517 rtx temp = force_reg (V4SFmode, operands[1]);
17518 emit_move_insn (operands[0], temp);
17523 (define_expand "movv4si"
17524 [(set (match_operand:V4SI 0 "general_operand" "")
17525 (match_operand:V4SI 1 "general_operand" ""))]
17529 /* For constants other than zero into memory. We do not know how the
17530 instructions used to build constants modify the upper 64 bits
17531 of the register, once we have that information we may be able
17532 to handle some of them more efficiently. */
17533 if ((reload_in_progress | reload_completed) == 0
17534 && register_operand (operands[0], V4SImode)
17535 && CONSTANT_P (operands[1]))
17537 rtx addr = gen_reg_rtx (Pmode);
17539 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
17540 operands[1] = gen_rtx_MEM (V4SImode, addr);
17543 /* Make operand1 a register if it isn't already. */
17544 if ((reload_in_progress | reload_completed) == 0
17545 && !register_operand (operands[0], V4SImode)
17546 && !register_operand (operands[1], V4SImode)
17547 && operands[1] != CONST0_RTX (V4SImode))
17549 rtx temp = force_reg (V4SImode, operands[1]);
17550 emit_move_insn (operands[0], temp);
17555 (define_expand "movv2si"
17556 [(set (match_operand:V2SI 0 "general_operand" "")
17557 (match_operand:V2SI 1 "general_operand" ""))]
17561 /* For constants other than zero into memory. We do not know how the
17562 instructions used to build constants modify the upper 64 bits
17563 of the register, once we have that information we may be able
17564 to handle some of them more efficiently. */
17565 if ((reload_in_progress | reload_completed) == 0
17566 && register_operand (operands[0], V2SImode)
17567 && CONSTANT_P (operands[1]))
17569 rtx addr = gen_reg_rtx (Pmode);
17571 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
17572 operands[1] = gen_rtx_MEM (V2SImode, addr);
17575 /* Make operand1 a register if it isn't already. */
17576 if ((reload_in_progress | reload_completed) == 0
17577 && !register_operand (operands[0], V2SImode)
17578 && !register_operand (operands[1], V2SImode)
17579 && operands[1] != CONST0_RTX (V2SImode))
17581 rtx temp = force_reg (V2SImode, operands[1]);
17582 emit_move_insn (operands[0], temp);
17587 (define_expand "movv4hi"
17588 [(set (match_operand:V4HI 0 "general_operand" "")
17589 (match_operand:V4HI 1 "general_operand" ""))]
17593 /* For constants other than zero into memory. We do not know how the
17594 instructions used to build constants modify the upper 64 bits
17595 of the register, once we have that information we may be able
17596 to handle some of them more efficiently. */
17597 if ((reload_in_progress | reload_completed) == 0
17598 && register_operand (operands[0], V4HImode)
17599 && CONSTANT_P (operands[1]))
17601 rtx addr = gen_reg_rtx (Pmode);
17603 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
17604 operands[1] = gen_rtx_MEM (V4HImode, addr);
17607 /* Make operand1 a register if it isn't already. */
17608 if ((reload_in_progress | reload_completed) == 0
17609 && !register_operand (operands[0], V4HImode)
17610 && !register_operand (operands[1], V4HImode)
17611 && operands[1] != CONST0_RTX (V4HImode))
17613 rtx temp = force_reg (V4HImode, operands[1]);
17614 emit_move_insn (operands[0], temp);
17619 (define_expand "movv8qi"
17620 [(set (match_operand:V8QI 0 "general_operand" "")
17621 (match_operand:V8QI 1 "general_operand" ""))]
17625 /* For constants other than zero into memory. We do not know how the
17626 instructions used to build constants modify the upper 64 bits
17627 of the register, once we have that information we may be able
17628 to handle some of them more efficiently. */
17629 if ((reload_in_progress | reload_completed) == 0
17630 && register_operand (operands[0], V8QImode)
17631 && CONSTANT_P (operands[1]))
17633 rtx addr = gen_reg_rtx (Pmode);
17635 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
17636 operands[1] = gen_rtx_MEM (V8QImode, addr);
17639 /* Make operand1 a register if it isn't already. */
17640 if ((reload_in_progress | reload_completed) == 0
17641 && !register_operand (operands[0], V8QImode)
17642 && !register_operand (operands[1], V8QImode)
17643 && operands[1] != CONST0_RTX (V8QImode))
17645 rtx temp = force_reg (V8QImode, operands[1]);
17646 emit_move_insn (operands[0], temp);
17651 (define_insn_and_split "*pushti"
17652 [(set (match_operand:TI 0 "push_operand" "=<")
17653 (match_operand:TI 1 "nonmemory_operand" "x"))]
17657 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17658 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17660 [(set_attr "type" "sse")])
17662 (define_insn_and_split "*pushv4sf"
17663 [(set (match_operand:V4SF 0 "push_operand" "=<")
17664 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17668 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17669 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17671 [(set_attr "type" "sse")])
17673 (define_insn_and_split "*pushv4si"
17674 [(set (match_operand:V4SI 0 "push_operand" "=<")
17675 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17679 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17680 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17682 [(set_attr "type" "sse")])
17684 (define_insn_and_split "*pushv2si"
17685 [(set (match_operand:V2SI 0 "push_operand" "=<")
17686 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17690 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17691 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17693 [(set_attr "type" "mmx")])
17695 (define_insn_and_split "*pushv4hi"
17696 [(set (match_operand:V4HI 0 "push_operand" "=<")
17697 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17701 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17702 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17704 [(set_attr "type" "mmx")])
17706 (define_insn_and_split "*pushv8qi"
17707 [(set (match_operand:V8QI 0 "push_operand" "=<")
17708 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17712 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17713 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17715 [(set_attr "type" "mmx")])
17717 (define_insn "movti_internal"
17718 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
17719 (match_operand:TI 1 "general_operand" "xm,x"))]
17722 movaps\\t{%1, %0|%0, %1}
17723 movaps\\t{%1, %0|%0, %1}"
17724 [(set_attr "type" "sse")])
17726 ;; These two patterns are useful for specifying exactly whether to use
17727 ;; movaps or movups
17728 (define_insn "sse_movaps"
17729 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17730 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
17733 movaps\\t{%1, %0|%0, %1}
17734 movaps\\t{%1, %0|%0, %1}"
17735 [(set_attr "type" "sse")])
17737 (define_insn "sse_movups"
17738 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17739 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
17742 movups\\t{%1, %0|%0, %1}
17743 movups\\t{%1, %0|%0, %1}"
17744 [(set_attr "type" "sse")])
17747 ;; SSE Strange Moves.
17749 (define_insn "sse_movmskps"
17750 [(set (match_operand:SI 0 "register_operand" "=r")
17751 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
17753 "movmskps\\t{%1, %0|%0, %1}"
17754 [(set_attr "type" "sse")])
17756 (define_insn "mmx_pmovmskb"
17757 [(set (match_operand:SI 0 "register_operand" "=r")
17758 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
17760 "pmovmskb\\t{%1, %0|%0, %1}"
17761 [(set_attr "type" "sse")])
17763 (define_insn "mmx_maskmovq"
17764 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17765 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17766 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17768 ;; @@@ check ordering of operands in intel/nonintel syntax
17769 "maskmovq\\t{%2, %1|%1, %2}"
17770 [(set_attr "type" "sse")])
17772 (define_insn "sse_movntv4sf"
17773 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17774 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17776 "movntps\\t{%1, %0|%0, %1}"
17777 [(set_attr "type" "sse")])
17779 (define_insn "sse_movntdi"
17780 [(set (match_operand:DI 0 "memory_operand" "=m")
17781 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
17783 "movntq\\t{%1, %0|%0, %1}"
17784 [(set_attr "type" "sse")])
17786 (define_insn "sse_movhlps"
17787 [(set (match_operand:V4SF 0 "register_operand" "=x")
17789 (match_operand:V4SF 1 "register_operand" "0")
17790 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17791 (parallel [(const_int 2)
17797 "movhlps\\t{%2, %0|%0, %2}"
17798 [(set_attr "type" "sse")])
17800 (define_insn "sse_movlhps"
17801 [(set (match_operand:V4SF 0 "register_operand" "=x")
17803 (match_operand:V4SF 1 "register_operand" "0")
17804 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17805 (parallel [(const_int 2)
17811 "movlhps\\t{%2, %0|%0, %2}"
17812 [(set_attr "type" "sse")])
17814 (define_insn "sse_movhps"
17815 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17817 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17818 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17820 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17821 "movhps\\t{%2, %0|%0, %2}"
17822 [(set_attr "type" "sse")])
17824 (define_insn "sse_movlps"
17825 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17827 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17828 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17830 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17831 "movlps\\t{%2, %0|%0, %2}"
17832 [(set_attr "type" "sse")])
17834 (define_insn "sse_loadss"
17835 [(set (match_operand:V4SF 0 "register_operand" "=x")
17837 (match_operand:V4SF 1 "memory_operand" "m")
17838 (vec_duplicate:V4SF (float:SF (const_int 0)))
17841 "movss\\t{%1, %0|%0, %1}"
17842 [(set_attr "type" "sse")])
17844 (define_insn "sse_movss"
17845 [(set (match_operand:V4SF 0 "register_operand" "=x")
17847 (match_operand:V4SF 1 "register_operand" "0")
17848 (match_operand:V4SF 2 "register_operand" "x")
17851 "movss\\t{%2, %0|%0, %2}"
17852 [(set_attr "type" "sse")])
17854 (define_insn "sse_storess"
17855 [(set (match_operand:SF 0 "memory_operand" "=m")
17857 (match_operand:V4SF 1 "register_operand" "x")
17858 (parallel [(const_int 0)])))]
17860 "movss\\t{%1, %0|%0, %1}"
17861 [(set_attr "type" "sse")])
17863 (define_insn "sse_shufps"
17864 [(set (match_operand:V4SF 0 "register_operand" "=x")
17865 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
17866 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
17867 (match_operand:SI 3 "immediate_operand" "i")] 41))]
17869 ;; @@@ check operand order for intel/nonintel syntax
17870 "shufps\\t{%3, %2, %0|%0, %2, %3}"
17871 [(set_attr "type" "sse")])
17876 (define_insn "addv4sf3"
17877 [(set (match_operand:V4SF 0 "register_operand" "=x")
17878 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17879 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17881 "addps\\t{%2, %0|%0, %2}"
17882 [(set_attr "type" "sse")])
17884 (define_insn "vmaddv4sf3"
17885 [(set (match_operand:V4SF 0 "register_operand" "=x")
17886 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17887 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17891 "addss\\t{%2, %0|%0, %2}"
17892 [(set_attr "type" "sse")])
17894 (define_insn "subv4sf3"
17895 [(set (match_operand:V4SF 0 "register_operand" "=x")
17896 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17897 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17899 "subps\\t{%2, %0|%0, %2}"
17900 [(set_attr "type" "sse")])
17902 (define_insn "vmsubv4sf3"
17903 [(set (match_operand:V4SF 0 "register_operand" "=x")
17904 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17905 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17909 "subss\\t{%2, %0|%0, %2}"
17910 [(set_attr "type" "sse")])
17912 (define_insn "mulv4sf3"
17913 [(set (match_operand:V4SF 0 "register_operand" "=x")
17914 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17915 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17917 "mulps\\t{%2, %0|%0, %2}"
17918 [(set_attr "type" "sse")])
17920 (define_insn "vmmulv4sf3"
17921 [(set (match_operand:V4SF 0 "register_operand" "=x")
17922 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17923 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17927 "mulss\\t{%2, %0|%0, %2}"
17928 [(set_attr "type" "sse")])
17930 (define_insn "divv4sf3"
17931 [(set (match_operand:V4SF 0 "register_operand" "=x")
17932 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17933 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17935 "divps\\t{%2, %0|%0, %2}"
17936 [(set_attr "type" "sse")])
17938 (define_insn "vmdivv4sf3"
17939 [(set (match_operand:V4SF 0 "register_operand" "=x")
17940 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17941 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17945 "divss\\t{%2, %0|%0, %2}"
17946 [(set_attr "type" "sse")])
17949 ;; SSE square root/reciprocal
17951 (define_insn "rcpv4sf2"
17952 [(set (match_operand:V4SF 0 "register_operand" "=x")
17953 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
17955 "rcpps\\t{%1, %0|%0, %1}"
17956 [(set_attr "type" "sse")])
17958 (define_insn "vmrcpv4sf2"
17959 [(set (match_operand:V4SF 0 "register_operand" "=x")
17960 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
17961 (match_operand:V4SF 2 "register_operand" "0")
17964 "rcpss\\t{%1, %0|%0, %1}"
17965 [(set_attr "type" "sse")])
17967 (define_insn "rsqrtv4sf2"
17968 [(set (match_operand:V4SF 0 "register_operand" "=x")
17969 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
17971 "rsqrtps\\t{%1, %0|%0, %1}"
17972 [(set_attr "type" "sse")])
17974 (define_insn "vmrsqrtv4sf2"
17975 [(set (match_operand:V4SF 0 "register_operand" "=x")
17976 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
17977 (match_operand:V4SF 2 "register_operand" "0")
17980 "rsqrtss\\t{%1, %0|%0, %1}"
17981 [(set_attr "type" "sse")])
17983 (define_insn "sqrtv4sf2"
17984 [(set (match_operand:V4SF 0 "register_operand" "=x")
17985 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
17987 "sqrtps\\t{%1, %0|%0, %1}"
17988 [(set_attr "type" "sse")])
17990 (define_insn "vmsqrtv4sf2"
17991 [(set (match_operand:V4SF 0 "register_operand" "=x")
17992 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
17993 (match_operand:V4SF 2 "register_operand" "0")
17996 "sqrtss\\t{%1, %0|%0, %1}"
17997 [(set_attr "type" "sse")])
18000 ;; SSE logical operations.
18002 ;; These are not called andti3 etc. because we really really don't want
18003 ;; the compiler to widen DImode ands to TImode ands and then try to move
18004 ;; into DImode subregs of SSE registers, and them together, and move out
18005 ;; of DImode subregs again!
18007 (define_insn "*sse_andti3_df_1"
18008 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18009 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18010 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18012 "andpd\\t{%2, %0|%0, %2}"
18013 [(set_attr "type" "sse")])
18015 (define_insn "*sse_andti3_df_2"
18016 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18017 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18018 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18020 "andpd\\t{%2, %0|%0, %2}"
18021 [(set_attr "type" "sse")])
18023 (define_insn "*sse_andti3_sf_1"
18024 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18025 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18026 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18028 "andps\\t{%2, %0|%0, %2}"
18029 [(set_attr "type" "sse")])
18031 (define_insn "*sse_andti3_sf_2"
18032 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18033 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18034 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18036 "andps\\t{%2, %0|%0, %2}"
18037 [(set_attr "type" "sse")])
18039 (define_insn "sse_andti3"
18040 [(set (match_operand:TI 0 "register_operand" "=x")
18041 (and:TI (match_operand:TI 1 "register_operand" "%0")
18042 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18043 "TARGET_SSE && !TARGET_SSE2"
18044 "andps\\t{%2, %0|%0, %2}"
18045 [(set_attr "type" "sse")])
18047 (define_insn "*sse_andti3_sse2"
18048 [(set (match_operand:TI 0 "register_operand" "=x")
18049 (and:TI (match_operand:TI 1 "register_operand" "%0")
18050 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18052 "pand\\t{%2, %0|%0, %2}"
18053 [(set_attr "type" "sse")])
18055 (define_insn "*sse_nandti3_df"
18056 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18057 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18058 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18060 "andnpd\\t{%2, %0|%0, %2}"
18061 [(set_attr "type" "sse")])
18063 (define_insn "*sse_nandti3_sf"
18064 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18065 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18066 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18068 "andnps\\t{%2, %0|%0, %2}"
18069 [(set_attr "type" "sse")])
18071 (define_insn "sse_nandti3"
18072 [(set (match_operand:TI 0 "register_operand" "=x")
18073 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18074 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18075 "TARGET_SSE && !TARGET_SSE2"
18076 "andnps\\t{%2, %0|%0, %2}"
18077 [(set_attr "type" "sse")])
18079 (define_insn "*sse_nandti3_sse2"
18080 [(set (match_operand:TI 0 "register_operand" "=x")
18081 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18082 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18084 "pnand\\t{%2, %0|%0, %2}"
18085 [(set_attr "type" "sse")])
18087 (define_insn "*sse_iorti3_df_1"
18088 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18089 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18090 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18092 "orpd\\t{%2, %0|%0, %2}"
18093 [(set_attr "type" "sse")])
18095 (define_insn "*sse_iorti3_df_2"
18096 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18097 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18098 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18100 "orpd\\t{%2, %0|%0, %2}"
18101 [(set_attr "type" "sse")])
18103 (define_insn "*sse_iorti3_sf_1"
18104 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18105 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18106 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18108 "orps\\t{%2, %0|%0, %2}"
18109 [(set_attr "type" "sse")])
18111 (define_insn "*sse_iorti3_sf_2"
18112 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18113 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18114 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18116 "orps\\t{%2, %0|%0, %2}"
18117 [(set_attr "type" "sse")])
18119 (define_insn "sse_iorti3"
18120 [(set (match_operand:TI 0 "register_operand" "=x")
18121 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18122 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18123 "TARGET_SSE && !TARGET_SSE2"
18124 "orps\\t{%2, %0|%0, %2}"
18125 [(set_attr "type" "sse")])
18127 (define_insn "*sse_iorti3_sse2"
18128 [(set (match_operand:TI 0 "register_operand" "=x")
18129 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18130 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18132 "por\\t{%2, %0|%0, %2}"
18133 [(set_attr "type" "sse")])
18135 (define_insn "*sse_xorti3_df_1"
18136 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18137 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18138 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18140 "xorpd\\t{%2, %0|%0, %2}"
18141 [(set_attr "type" "sse")])
18143 (define_insn "*sse_xorti3_df_2"
18144 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18145 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18146 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18148 "xorpd\\t{%2, %0|%0, %2}"
18149 [(set_attr "type" "sse")])
18151 (define_insn "*sse_xorti3_sf_1"
18152 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18153 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18154 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18156 "xorps\\t{%2, %0|%0, %2}"
18157 [(set_attr "type" "sse")])
18159 (define_insn "*sse_xorti3_sf_2"
18160 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18161 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18162 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18164 "xorps\\t{%2, %0|%0, %2}"
18165 [(set_attr "type" "sse")])
18167 (define_insn "sse_xorti3"
18168 [(set (match_operand:TI 0 "register_operand" "=x")
18169 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18170 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18171 "TARGET_SSE && !TARGET_SSE2"
18172 "xorps\\t{%2, %0|%0, %2}"
18173 [(set_attr "type" "sse")])
18175 (define_insn "*sse_xorti3_sse2"
18176 [(set (match_operand:TI 0 "register_operand" "=x")
18177 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18178 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18180 "pxor\\t{%2, %0|%0, %2}"
18181 [(set_attr "type" "sse")])
18183 ;; Use xor, but don't show input operands so they aren't live before
18185 (define_insn "sse_clrti"
18186 [(set (match_operand:TI 0 "register_operand" "=x")
18187 (unspec:TI [(const_int 0)] 45))]
18189 "xorps\\t{%0, %0|%0, %0}"
18190 [(set_attr "type" "sse")])
18193 ;; SSE mask-generating compares
18195 (define_insn "maskcmpv4sf3"
18196 [(set (match_operand:V4SI 0 "register_operand" "=x")
18197 (match_operator:V4SI 3 "sse_comparison_operator"
18198 [(match_operand:V4SF 1 "register_operand" "0")
18199 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
18201 "cmp%D3ps\\t{%2, %0|%0, %2}"
18202 [(set_attr "type" "sse")])
18204 (define_insn "maskncmpv4sf3"
18205 [(set (match_operand:V4SI 0 "register_operand" "=x")
18207 (match_operator:V4SI 3 "sse_comparison_operator"
18208 [(match_operand:V4SF 1 "register_operand" "0")
18209 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
18211 "cmpn%D3ps\\t{%2, %0|%0, %2}"
18212 [(set_attr "type" "sse")])
18214 (define_insn "vmmaskcmpv4sf3"
18215 [(set (match_operand:V4SI 0 "register_operand" "=x")
18217 (match_operator:V4SI 3 "sse_comparison_operator"
18218 [(match_operand:V4SF 1 "register_operand" "0")
18219 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
18223 "cmp%D3ss\\t{%2, %0|%0, %2}"
18224 [(set_attr "type" "sse")])
18226 (define_insn "vmmaskncmpv4sf3"
18227 [(set (match_operand:V4SI 0 "register_operand" "=x")
18230 (match_operator:V4SI 3 "sse_comparison_operator"
18231 [(match_operand:V4SF 1 "register_operand" "0")
18232 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
18233 (subreg:V4SI (match_dup 1) 0)
18236 "cmp%D3ss\\t{%2, %0|%0, %2}"
18237 [(set_attr "type" "sse")])
18239 (define_insn "sse_comi"
18240 [(set (reg:CCFP 17)
18241 (match_operator:CCFP 2 "sse_comparison_operator"
18243 (match_operand:V4SF 0 "register_operand" "x")
18244 (parallel [(const_int 0)]))
18246 (match_operand:V4SF 1 "register_operand" "x")
18247 (parallel [(const_int 0)]))]))]
18249 "comiss\\t{%2, %0|%0, %2}"
18250 [(set_attr "type" "sse")])
18252 (define_insn "sse_ucomi"
18253 [(set (reg:CCFPU 17)
18254 (match_operator:CCFPU 2 "sse_comparison_operator"
18256 (match_operand:V4SF 0 "register_operand" "x")
18257 (parallel [(const_int 0)]))
18259 (match_operand:V4SF 1 "register_operand" "x")
18260 (parallel [(const_int 0)]))]))]
18262 "ucomiss\\t{%2, %0|%0, %2}"
18263 [(set_attr "type" "sse")])
18268 (define_insn "sse_unpckhps"
18269 [(set (match_operand:V4SF 0 "register_operand" "=x")
18271 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18272 (parallel [(const_int 2)
18276 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18277 (parallel [(const_int 0)
18283 "unpckhps\\t{%2, %0|%0, %2}"
18284 [(set_attr "type" "sse")])
18286 (define_insn "sse_unpcklps"
18287 [(set (match_operand:V4SF 0 "register_operand" "=x")
18289 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18290 (parallel [(const_int 0)
18294 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18295 (parallel [(const_int 2)
18301 "unpcklps\\t{%2, %0|%0, %2}"
18302 [(set_attr "type" "sse")])
18307 (define_insn "smaxv4sf3"
18308 [(set (match_operand:V4SF 0 "register_operand" "=x")
18309 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18310 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18312 "maxps\\t{%2, %0|%0, %2}"
18313 [(set_attr "type" "sse")])
18315 (define_insn "vmsmaxv4sf3"
18316 [(set (match_operand:V4SF 0 "register_operand" "=x")
18317 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18318 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18322 "maxss\\t{%2, %0|%0, %2}"
18323 [(set_attr "type" "sse")])
18325 (define_insn "sminv4sf3"
18326 [(set (match_operand:V4SF 0 "register_operand" "=x")
18327 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18328 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18330 "minps\\t{%2, %0|%0, %2}"
18331 [(set_attr "type" "sse")])
18333 (define_insn "vmsminv4sf3"
18334 [(set (match_operand:V4SF 0 "register_operand" "=x")
18335 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18336 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18340 "minss\\t{%2, %0|%0, %2}"
18341 [(set_attr "type" "sse")])
18344 ;; SSE <-> integer/MMX conversions
18346 (define_insn "cvtpi2ps"
18347 [(set (match_operand:V4SF 0 "register_operand" "=x")
18348 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18349 (vec_duplicate:V4SF
18350 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
18353 "cvtpi2ps\\t{%2, %0|%0, %2}"
18354 [(set_attr "type" "sse")])
18356 (define_insn "cvtps2pi"
18357 [(set (match_operand:V2SI 0 "register_operand" "=y")
18358 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18363 "cvtps2pi\\t{%1, %0|%0, %1}"
18364 [(set_attr "type" "sse")])
18366 (define_insn "cvttps2pi"
18367 [(set (match_operand:V2SI 0 "register_operand" "=y")
18368 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18373 "cvttps2pi\\t{%1, %0|%0, %1}"
18374 [(set_attr "type" "sse")])
18376 (define_insn "cvtsi2ss"
18377 [(set (match_operand:V4SF 0 "register_operand" "=x")
18378 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18379 (vec_duplicate:V4SF
18380 (float:SF (match_operand:SI 2 "register_operand" "rm")))
18383 "cvtsi2ss\\t{%2, %0|%0, %2}"
18384 [(set_attr "type" "sse")])
18386 (define_insn "cvtss2si"
18387 [(set (match_operand:SI 0 "register_operand" "=y")
18388 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18389 (parallel [(const_int 0)])))]
18391 "cvtss2si\\t{%1, %0|%0, %1}"
18392 [(set_attr "type" "sse")])
18394 (define_insn "cvttss2si"
18395 [(set (match_operand:SI 0 "register_operand" "=y")
18396 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18397 (parallel [(const_int 0)])))]
18399 "cvttss2si\\t{%1, %0|%0, %1}"
18400 [(set_attr "type" "sse")])
18407 (define_insn "addv8qi3"
18408 [(set (match_operand:V8QI 0 "register_operand" "=y")
18409 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18410 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18412 "paddb\\t{%2, %0|%0, %2}"
18413 [(set_attr "type" "mmx")])
18415 (define_insn "addv4hi3"
18416 [(set (match_operand:V4HI 0 "register_operand" "=y")
18417 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18418 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18420 "paddw\\t{%2, %0|%0, %2}"
18421 [(set_attr "type" "mmx")])
18423 (define_insn "addv2si3"
18424 [(set (match_operand:V2SI 0 "register_operand" "=y")
18425 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18426 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18428 "paddd\\t{%2, %0|%0, %2}"
18429 [(set_attr "type" "mmx")])
18431 (define_insn "ssaddv8qi3"
18432 [(set (match_operand:V8QI 0 "register_operand" "=y")
18433 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18434 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18436 "paddsb\\t{%2, %0|%0, %2}"
18437 [(set_attr "type" "mmx")])
18439 (define_insn "ssaddv4hi3"
18440 [(set (match_operand:V4HI 0 "register_operand" "=y")
18441 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18442 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18444 "paddsw\\t{%2, %0|%0, %2}"
18445 [(set_attr "type" "mmx")])
18447 (define_insn "usaddv8qi3"
18448 [(set (match_operand:V8QI 0 "register_operand" "=y")
18449 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18450 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18452 "paddusb\\t{%2, %0|%0, %2}"
18453 [(set_attr "type" "mmx")])
18455 (define_insn "usaddv4hi3"
18456 [(set (match_operand:V4HI 0 "register_operand" "=y")
18457 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18458 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18460 "paddusw\\t{%2, %0|%0, %2}"
18461 [(set_attr "type" "mmx")])
18463 (define_insn "subv8qi3"
18464 [(set (match_operand:V8QI 0 "register_operand" "=y")
18465 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18466 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18468 "psubb\\t{%2, %0|%0, %2}"
18469 [(set_attr "type" "mmx")])
18471 (define_insn "subv4hi3"
18472 [(set (match_operand:V4HI 0 "register_operand" "=y")
18473 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18474 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18476 "psubw\\t{%2, %0|%0, %2}"
18477 [(set_attr "type" "mmx")])
18479 (define_insn "subv2si3"
18480 [(set (match_operand:V2SI 0 "register_operand" "=y")
18481 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18482 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18484 "psubd\\t{%2, %0|%0, %2}"
18485 [(set_attr "type" "mmx")])
18487 (define_insn "sssubv8qi3"
18488 [(set (match_operand:V8QI 0 "register_operand" "=y")
18489 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18490 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18492 "psubsb\\t{%2, %0|%0, %2}"
18493 [(set_attr "type" "mmx")])
18495 (define_insn "sssubv4hi3"
18496 [(set (match_operand:V4HI 0 "register_operand" "=y")
18497 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18498 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18500 "psubsw\\t{%2, %0|%0, %2}"
18501 [(set_attr "type" "mmx")])
18503 (define_insn "ussubv8qi3"
18504 [(set (match_operand:V8QI 0 "register_operand" "=y")
18505 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18506 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18508 "psubusb\\t{%2, %0|%0, %2}"
18509 [(set_attr "type" "mmx")])
18511 (define_insn "ussubv4hi3"
18512 [(set (match_operand:V4HI 0 "register_operand" "=y")
18513 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18514 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18516 "psubusw\\t{%2, %0|%0, %2}"
18517 [(set_attr "type" "mmx")])
18519 (define_insn "mulv4hi3"
18520 [(set (match_operand:V4HI 0 "register_operand" "=y")
18521 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18522 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18524 "pmullw\\t{%2, %0|%0, %2}"
18525 [(set_attr "type" "mmx")])
18527 (define_insn "smulv4hi3_highpart"
18528 [(set (match_operand:V4HI 0 "register_operand" "=y")
18531 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18532 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18535 "pmulhw\\t{%2, %0|%0, %2}"
18536 [(set_attr "type" "mmx")])
18538 (define_insn "umulv4hi3_highpart"
18539 [(set (match_operand:V4HI 0 "register_operand" "=y")
18542 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18543 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18546 "pmulhuw\\t{%2, %0|%0, %2}"
18547 [(set_attr "type" "mmx")])
18549 (define_insn "mmx_pmaddwd"
18550 [(set (match_operand:V2SI 0 "register_operand" "=y")
18553 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18554 (parallel [(const_int 0)
18556 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18557 (parallel [(const_int 0)
18560 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18561 (parallel [(const_int 1)
18563 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18564 (parallel [(const_int 1)
18565 (const_int 3)]))))))]
18567 "pmaddwd\\t{%2, %0|%0, %2}"
18568 [(set_attr "type" "mmx")])
18571 ;; MMX logical operations
18572 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18573 ;; normal code that also wants to use the FPU from getting broken.
18574 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18575 (define_insn "mmx_iordi3"
18576 [(set (match_operand:DI 0 "register_operand" "=y")
18578 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18579 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18581 "por\\t{%2, %0|%0, %2}"
18582 [(set_attr "type" "mmx")])
18584 (define_insn "mmx_xordi3"
18585 [(set (match_operand:DI 0 "register_operand" "=y")
18587 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18588 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18590 "pxor\\t{%2, %0|%0, %2}"
18591 [(set_attr "type" "mmx")])
18593 ;; Same as pxor, but don't show input operands so that we don't think
18595 (define_insn "mmx_clrdi"
18596 [(set (match_operand:DI 0 "register_operand" "=y")
18597 (unspec:DI [(const_int 0)] 45))]
18599 "pxor\\t{%0, %0|%0, %0}"
18600 [(set_attr "type" "mmx")])
18602 (define_insn "mmx_anddi3"
18603 [(set (match_operand:DI 0 "register_operand" "=y")
18605 [(and:DI (match_operand:DI 1 "register_operand" "0")
18606 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18608 "pand\\t{%2, %0|%0, %2}"
18609 [(set_attr "type" "mmx")])
18611 (define_insn "mmx_nanddi3"
18612 [(set (match_operand:DI 0 "register_operand" "=y")
18614 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18615 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18617 "pandn\\t{%2, %0|%0, %2}"
18618 [(set_attr "type" "mmx")])
18621 ;; MMX unsigned averages/sum of absolute differences
18623 (define_insn "mmx_uavgv8qi3"
18624 [(set (match_operand:V8QI 0 "register_operand" "=y")
18626 (plus:V8QI (plus:V8QI
18627 (match_operand:V8QI 1 "register_operand" "0")
18628 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18629 (vec_const:V8QI (parallel [(const_int 1)
18639 "pavgb\\t{%2, %0|%0, %2}"
18640 [(set_attr "type" "sse")])
18642 (define_insn "mmx_uavgv4hi3"
18643 [(set (match_operand:V4HI 0 "register_operand" "=y")
18645 (plus:V4HI (plus:V4HI
18646 (match_operand:V4HI 1 "register_operand" "0")
18647 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18648 (vec_const:V4HI (parallel [(const_int 1)
18654 "pavgw\\t{%2, %0|%0, %2}"
18655 [(set_attr "type" "sse")])
18657 (define_insn "mmx_psadbw"
18658 [(set (match_operand:V8QI 0 "register_operand" "=y")
18659 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18660 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
18662 "psadbw\\t{%2, %0|%0, %2}"
18663 [(set_attr "type" "sse")])
18666 ;; MMX insert/extract/shuffle
18668 (define_insn "mmx_pinsrw"
18669 [(set (match_operand:V4HI 0 "register_operand" "=y")
18670 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18671 (vec_duplicate:V4HI
18672 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18673 (match_operand:SI 3 "immediate_operand" "i")))]
18675 "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
18676 [(set_attr "type" "sse")])
18678 (define_insn "mmx_pextrw"
18679 [(set (match_operand:SI 0 "register_operand" "=r")
18680 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18682 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18684 "pextrw\\t{%2, %1, %0|%0, %1, %2}"
18685 [(set_attr "type" "sse")])
18687 (define_insn "mmx_pshufw"
18688 [(set (match_operand:V4HI 0 "register_operand" "=y")
18689 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18690 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18691 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18693 "pshufw\\t{%3, %2, %0|%0, %2, %3}"
18694 [(set_attr "type" "sse")])
18697 ;; MMX mask-generating comparisons
18699 (define_insn "eqv8qi3"
18700 [(set (match_operand:V8QI 0 "register_operand" "=y")
18701 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18702 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18704 "pcmpeqb\\t{%2, %0|%0, %2}"
18705 [(set_attr "type" "mmx")])
18707 (define_insn "eqv4hi3"
18708 [(set (match_operand:V4HI 0 "register_operand" "=y")
18709 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18710 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18712 "pcmpeqw\\t{%2, %0|%0, %2}"
18713 [(set_attr "type" "mmx")])
18715 (define_insn "eqv2si3"
18716 [(set (match_operand:V2SI 0 "register_operand" "=y")
18717 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18718 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18720 "pcmpeqd\\t{%2, %0|%0, %2}"
18721 [(set_attr "type" "mmx")])
18723 (define_insn "gtv8qi3"
18724 [(set (match_operand:V8QI 0 "register_operand" "=y")
18725 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
18726 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18728 "pcmpgtb\\t{%2, %0|%0, %2}"
18729 [(set_attr "type" "mmx")])
18731 (define_insn "gtv4hi3"
18732 [(set (match_operand:V4HI 0 "register_operand" "=y")
18733 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18734 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18736 "pcmpgtw\\t{%2, %0|%0, %2}"
18737 [(set_attr "type" "mmx")])
18739 (define_insn "gtv2si3"
18740 [(set (match_operand:V2SI 0 "register_operand" "=y")
18741 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18742 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18744 "pcmpgtd\\t{%2, %0|%0, %2}"
18745 [(set_attr "type" "mmx")])
18748 ;; MMX max/min insns
18750 (define_insn "umaxv8qi3"
18751 [(set (match_operand:V8QI 0 "register_operand" "=y")
18752 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
18753 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18755 "pmaxub\\t{%2, %0|%0, %2}"
18756 [(set_attr "type" "sse")])
18758 (define_insn "smaxv4hi3"
18759 [(set (match_operand:V4HI 0 "register_operand" "=y")
18760 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
18761 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18763 "pmaxsw\\t{%2, %0|%0, %2}"
18764 [(set_attr "type" "sse")])
18766 (define_insn "uminv8qi3"
18767 [(set (match_operand:V8QI 0 "register_operand" "=y")
18768 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
18769 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18771 "pminub\\t{%2, %0|%0, %2}"
18772 [(set_attr "type" "sse")])
18774 (define_insn "sminv4hi3"
18775 [(set (match_operand:V4HI 0 "register_operand" "=y")
18776 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
18777 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18779 "pminsw\\t{%2, %0|%0, %2}"
18780 [(set_attr "type" "sse")])
18785 (define_insn "ashrv4hi3"
18786 [(set (match_operand:V4HI 0 "register_operand" "=y")
18787 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18788 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18790 "psraw\\t{%2, %0|%0, %2}"
18791 [(set_attr "type" "mmx")])
18793 (define_insn "ashrv2si3"
18794 [(set (match_operand:V2SI 0 "register_operand" "=y")
18795 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18796 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18798 "psrad\\t{%2, %0|%0, %2}"
18799 [(set_attr "type" "mmx")])
18801 (define_insn "lshrv4hi3"
18802 [(set (match_operand:V4HI 0 "register_operand" "=y")
18803 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18804 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18806 "psrlw\\t{%2, %0|%0, %2}"
18807 [(set_attr "type" "mmx")])
18809 (define_insn "lshrv2si3"
18810 [(set (match_operand:V2SI 0 "register_operand" "=y")
18811 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18812 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18814 "psrld\\t{%2, %0|%0, %2}"
18815 [(set_attr "type" "mmx")])
18817 ;; See logical MMX insns.
18818 (define_insn "mmx_lshrdi3"
18819 [(set (match_operand:DI 0 "register_operand" "=y")
18821 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
18822 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18824 "psrlq\\t{%2, %0|%0, %2}"
18825 [(set_attr "type" "mmx")])
18827 (define_insn "ashlv4hi3"
18828 [(set (match_operand:V4HI 0 "register_operand" "=y")
18829 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
18830 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18832 "psllw\\t{%2, %0|%0, %2}"
18833 [(set_attr "type" "mmx")])
18835 (define_insn "ashlv2si3"
18836 [(set (match_operand:V2SI 0 "register_operand" "=y")
18837 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
18838 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18840 "pslld\\t{%2, %0|%0, %2}"
18841 [(set_attr "type" "mmx")])
18843 ;; See logical MMX insns.
18844 (define_insn "mmx_ashldi3"
18845 [(set (match_operand:DI 0 "register_operand" "=y")
18847 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
18848 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18850 "psllq\\t{%2, %0|%0, %2}"
18851 [(set_attr "type" "mmx")])
18854 ;; MMX pack/unpack insns.
18856 (define_insn "mmx_packsswb"
18857 [(set (match_operand:V8QI 0 "register_operand" "=y")
18859 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18860 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18862 "packsswb\\t{%2, %0|%0, %2}"
18863 [(set_attr "type" "mmx")])
18865 (define_insn "mmx_packssdw"
18866 [(set (match_operand:V4HI 0 "register_operand" "=y")
18868 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
18869 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
18871 "packssdw\\t{%2, %0|%0, %2}"
18872 [(set_attr "type" "mmx")])
18874 (define_insn "mmx_packuswb"
18875 [(set (match_operand:V8QI 0 "register_operand" "=y")
18877 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18878 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18880 "packuswb\\t{%2, %0|%0, %2}"
18881 [(set_attr "type" "mmx")])
18883 (define_insn "mmx_punpckhbw"
18884 [(set (match_operand:V8QI 0 "register_operand" "=y")
18886 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18887 (parallel [(const_int 4)
18895 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18896 (parallel [(const_int 0)
18906 "punpckhbw\\t{%2, %0|%0, %2}"
18907 [(set_attr "type" "mmx")])
18909 (define_insn "mmx_punpckhwd"
18910 [(set (match_operand:V4HI 0 "register_operand" "=y")
18912 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
18913 (parallel [(const_int 0)
18917 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
18918 (parallel [(const_int 2)
18924 "punpckhwd\\t{%2, %0|%0, %2}"
18925 [(set_attr "type" "mmx")])
18927 (define_insn "mmx_punpckhdq"
18928 [(set (match_operand:V2SI 0 "register_operand" "=y")
18930 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
18931 (parallel [(const_int 0)
18933 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
18934 (parallel [(const_int 1)
18938 "punpckhdq\\t{%2, %0|%0, %2}"
18939 [(set_attr "type" "mmx")])
18941 (define_insn "mmx_punpcklbw"
18942 [(set (match_operand:V8QI 0 "register_operand" "=y")
18944 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18945 (parallel [(const_int 0)
18953 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18954 (parallel [(const_int 4)
18964 "punpcklbw\\t{%2, %0|%0, %2}"
18965 [(set_attr "type" "mmx")])
18967 (define_insn "mmx_punpcklwd"
18968 [(set (match_operand:V4HI 0 "register_operand" "=y")
18970 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
18971 (parallel [(const_int 2)
18975 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
18976 (parallel [(const_int 0)
18982 "punpcklwd\\t{%2, %0|%0, %2}"
18983 [(set_attr "type" "mmx")])
18985 (define_insn "mmx_punpckldq"
18986 [(set (match_operand:V2SI 0 "register_operand" "=y")
18988 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
18989 (parallel [(const_int 1)
18991 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
18992 (parallel [(const_int 0)
18996 "punpckldq\\t{%2, %0|%0, %2}"
18997 [(set_attr "type" "mmx")])
19000 ;; Miscellaneous stuff
19002 (define_insn "emms"
19003 [(unspec_volatile [(const_int 0)] 31)
19004 (clobber (reg:XF 8))
19005 (clobber (reg:XF 9))
19006 (clobber (reg:XF 10))
19007 (clobber (reg:XF 11))
19008 (clobber (reg:XF 12))
19009 (clobber (reg:XF 13))
19010 (clobber (reg:XF 14))
19011 (clobber (reg:XF 15))
19012 (clobber (reg:DI 29))
19013 (clobber (reg:DI 30))
19014 (clobber (reg:DI 31))
19015 (clobber (reg:DI 32))
19016 (clobber (reg:DI 33))
19017 (clobber (reg:DI 34))
19018 (clobber (reg:DI 35))
19019 (clobber (reg:DI 36))]
19022 [(set_attr "type" "mmx")
19023 (set_attr "memory" "unknown")])
19025 (define_insn "ldmxcsr"
19026 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
19029 [(set_attr "type" "mmx")])
19031 (define_insn "stmxcsr"
19032 [(set (match_operand:SI 0 "memory_operand" "=m")
19033 (unspec_volatile:SI [(const_int 0)] 40))]
19036 [(set_attr "type" "mmx")])
19038 (define_expand "sfence"
19039 [(set (match_dup 0)
19040 (unspec:BLK [(match_dup 0)] 44))]
19044 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19045 MEM_VOLATILE_P (operands[0]) = 1;
19048 (define_insn "*sfence_insn"
19049 [(set (match_operand:BLK 0 "" "")
19050 (unspec:BLK [(match_dup 0)] 44))]
19053 [(set_attr "type" "sse")
19054 (set_attr "memory" "unknown")])
19056 (define_insn "prefetch"
19057 [(unspec [(match_operand:SI 0 "address_operand" "p")
19058 (match_operand:SI 1 "immediate_operand" "n")] 35)]
19062 switch (INTVAL (operands[1]))
19065 return \"prefetchnta\\t%a0\";
19067 return \"prefetcht0\\t%a0\";
19069 return \"prefetcht1\\t%a0\";
19071 return \"prefetcht2\\t%a0\";
19076 [(set_attr "type" "sse")])