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* alpha.h: NULL_PTR -> NULL.
[official-gcc.git] / gcc / config / arm / arm.h
blob61082c35e4a5056c5f9209a43fdab678d26d95c6
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef __ARM_H__
27 #define __ARM_H__
28
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
55
56 typedef enum arm_cond_code
57 {
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 }
61 arm_cc;
62
63 extern arm_cc arm_current_cc;
64 extern const char * arm_condition_codes[];
65
66 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
67
68 extern int arm_target_label;
69 extern int arm_ccfsm_state;
70 extern struct rtx_def * arm_target_insn;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75 /* Define the information needed to generate branch insns. This is
76 stored from the compare operation. Note that we can't use "rtx" here
77 since it hasn't been defined! */
78 extern struct rtx_def * arm_compare_op0;
79 extern struct rtx_def * arm_compare_op1;
80 /* The label of the current constant pool. */
81 extern struct rtx_def * pool_vector_label;
82 /* Set to 1 when a return insn is output, this means that the epilogue
83 is not needed. */
84 extern int return_used_this_function;
85 /* Nonzero if the prologue must setup `fp'. */
86 extern int current_function_anonymous_args;
87 \f
88 /* Just in case configure has failed to define anything. */
89 #ifndef TARGET_CPU_DEFAULT
90 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
91 #endif
92
93 /* If the configuration file doesn't specify the cpu, the subtarget may
94 override it. If it doesn't, then default to an ARM6. */
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
96 #undef TARGET_CPU_DEFAULT
97
98 #ifdef SUBTARGET_CPU_DEFAULT
99 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
100 #else
101 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
102 #endif
103 #endif
104
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
107 #else
108 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
109 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
110 #else
111 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
112 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
113 #else
114 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
115 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
116 #else
117 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
118 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
119 #else
120 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
121 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
122 #else
123 Unrecognized value in TARGET_CPU_DEFAULT.
124 #endif
125 #endif
126 #endif
127 #endif
128 #endif
129 #endif
130
131 #ifndef CPP_PREDEFINES
132 #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
133 #endif
134
135 #define CPP_SPEC "\
136 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
137 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
138
139 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
140
141 /* Set the architecture define -- if -march= is set, then it overrides
142 the -mcpu= setting. */
143 #define CPP_CPU_ARCH_SPEC "\
144 %{march=arm2:-D__ARM_ARCH_2__} \
145 %{march=arm250:-D__ARM_ARCH_2__} \
146 %{march=arm3:-D__ARM_ARCH_2__} \
147 %{march=arm6:-D__ARM_ARCH_3__} \
148 %{march=arm600:-D__ARM_ARCH_3__} \
149 %{march=arm610:-D__ARM_ARCH_3__} \
150 %{march=arm7:-D__ARM_ARCH_3__} \
151 %{march=arm700:-D__ARM_ARCH_3__} \
152 %{march=arm710:-D__ARM_ARCH_3__} \
153 %{march=arm720:-D__ARM_ARCH_3__} \
154 %{march=arm7100:-D__ARM_ARCH_3__} \
155 %{march=arm7500:-D__ARM_ARCH_3__} \
156 %{march=arm7500fe:-D__ARM_ARCH_3__} \
157 %{march=arm7m:-D__ARM_ARCH_3M__} \
158 %{march=arm7dm:-D__ARM_ARCH_3M__} \
159 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
160 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
161 %{march=arm8:-D__ARM_ARCH_4__} \
162 %{march=arm810:-D__ARM_ARCH_4__} \
163 %{march=arm9:-D__ARM_ARCH_4T__} \
164 %{march=arm920:-D__ARM_ARCH_4__} \
165 %{march=arm920t:-D__ARM_ARCH_4T__} \
166 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
167 %{march=strongarm:-D__ARM_ARCH_4__} \
168 %{march=strongarm110:-D__ARM_ARCH_4__} \
169 %{march=strongarm1100:-D__ARM_ARCH_4__} \
170 %{march=xscale:-D__ARM_ARCH_5TE__} \
171 %{march=xscale:-D__XSCALE__} \
172 %{march=armv2:-D__ARM_ARCH_2__} \
173 %{march=armv2a:-D__ARM_ARCH_2__} \
174 %{march=armv3:-D__ARM_ARCH_3__} \
175 %{march=armv3m:-D__ARM_ARCH_3M__} \
176 %{march=armv4:-D__ARM_ARCH_4__} \
177 %{march=armv4t:-D__ARM_ARCH_4T__} \
178 %{march=armv5:-D__ARM_ARCH_5__} \
179 %{march=armv5t:-D__ARM_ARCH_5T__} \
180 %{march=armv5e:-D__ARM_ARCH_5E__} \
181 %{march=armv5te:-D__ARM_ARCH_5TE__} \
182 %{!march=*: \
183 %{mcpu=arm2:-D__ARM_ARCH_2__} \
184 %{mcpu=arm250:-D__ARM_ARCH_2__} \
185 %{mcpu=arm3:-D__ARM_ARCH_2__} \
186 %{mcpu=arm6:-D__ARM_ARCH_3__} \
187 %{mcpu=arm600:-D__ARM_ARCH_3__} \
188 %{mcpu=arm610:-D__ARM_ARCH_3__} \
189 %{mcpu=arm7:-D__ARM_ARCH_3__} \
190 %{mcpu=arm700:-D__ARM_ARCH_3__} \
191 %{mcpu=arm710:-D__ARM_ARCH_3__} \
192 %{mcpu=arm720:-D__ARM_ARCH_3__} \
193 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
194 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
195 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
196 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
197 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
198 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
199 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm8:-D__ARM_ARCH_4__} \
201 %{mcpu=arm810:-D__ARM_ARCH_4__} \
202 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
203 %{mcpu=arm920:-D__ARM_ARCH_4__} \
204 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
205 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
206 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
207 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
208 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
209 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
210 %{mcpu=xscale:-D__XSCALE__} \
211 %{!mcpu*:%(cpp_cpu_arch_default)}} \
212 "
213
214 /* Define __APCS_26__ if the PC also contains the PSR */
215 #define CPP_APCS_PC_SPEC "\
216 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
217 -D__APCS_32__} \
218 %{mapcs-26:-D__APCS_26__} \
219 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
220 "
221
222 #ifndef CPP_APCS_PC_DEFAULT_SPEC
223 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
224 #endif
225
226 #define CPP_FLOAT_SPEC "\
227 %{msoft-float:\
228 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
229 -D__SOFTFP__} \
230 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
231 "
232
233 /* Default is hard float, which doesn't define anything */
234 #define CPP_FLOAT_DEFAULT_SPEC ""
235
236 #define CPP_ENDIAN_SPEC "\
237 %{mbig-endian: \
238 %{mlittle-endian: \
239 %e-mbig-endian and -mlittle-endian may not be used together} \
240 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
241 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
242 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
243 "
244
245 /* Default is little endian. */
246 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
247
248 /* Add a define for interworking. Needed when building libgcc.a.
249 This must define __THUMB_INTERWORK__ to the pre-processor if
250 interworking is enabled by default. */
251 #ifndef CPP_INTERWORK_DEFAULT_SPEC
252 #define CPP_INTERWORK_DEFAULT_SPEC ""
253 #endif
254
255 #define CPP_INTERWORK_SPEC " \
256 %{mthumb-interwork: \
257 %{mno-thumb-interwork: %eIncompatible interworking options} \
258 -D__THUMB_INTERWORK__} \
259 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
260 "
261
262 #define CC1_SPEC ""
263
264 /* This macro defines names of additional specifications to put in the specs
265 that can be used in various specifications like CC1_SPEC. Its definition
266 is an initializer with a subgrouping for each command option.
267
268 Each subgrouping contains a string constant, that defines the
269 specification name, and a string constant that used by the GNU CC driver
270 program.
271
272 Do not define this macro if it does not need to do anything. */
273 #define EXTRA_SPECS \
274 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
275 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
276 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
277 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
278 { "cpp_float", CPP_FLOAT_SPEC }, \
279 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
280 { "cpp_endian", CPP_ENDIAN_SPEC }, \
281 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
282 { "cpp_isa", CPP_ISA_SPEC }, \
283 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
284 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
285 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
286 SUBTARGET_EXTRA_SPECS
287
288 #ifndef SUBTARGET_EXTRA_SPECS
289 #define SUBTARGET_EXTRA_SPECS
290 #endif
291
292 #ifndef SUBTARGET_CPP_SPEC
293 #define SUBTARGET_CPP_SPEC ""
294 #endif
295 \f
296 /* Run-time Target Specification. */
297 #ifndef TARGET_VERSION
298 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
299 #endif
300
301 /* Nonzero if the function prologue (and epilogue) should obey
302 the ARM Procedure Call Standard. */
303 #define ARM_FLAG_APCS_FRAME (1 << 0)
304
305 /* Nonzero if the function prologue should output the function name to enable
306 the post mortem debugger to print a backtrace (very useful on RISCOS,
307 unused on RISCiX). Specifying this flag also enables
308 -fno-omit-frame-pointer.
309 XXX Must still be implemented in the prologue. */
310 #define ARM_FLAG_POKE (1 << 1)
311
312 /* Nonzero if floating point instructions are emulated by the FPE, in which
313 case instruction scheduling becomes very uninteresting. */
314 #define ARM_FLAG_FPE (1 << 2)
315
316 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
317 that assume restoration of the condition flags when returning from a
318 branch and link (ie a function). */
319 #define ARM_FLAG_APCS_32 (1 << 3)
320
321 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
322
323 /* Nonzero if stack checking should be performed on entry to each function
324 which allocates temporary variables on the stack. */
325 #define ARM_FLAG_APCS_STACK (1 << 4)
326
327 /* Nonzero if floating point parameters should be passed to functions in
328 floating point registers. */
329 #define ARM_FLAG_APCS_FLOAT (1 << 5)
330
331 /* Nonzero if re-entrant, position independent code should be generated.
332 This is equivalent to -fpic. */
333 #define ARM_FLAG_APCS_REENT (1 << 6)
334
335 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
336 be loaded using either LDRH or LDRB instructions. */
337 #define ARM_FLAG_MMU_TRAPS (1 << 7)
338
339 /* Nonzero if all floating point instructions are missing (and there is no
340 emulator either). Generate function calls for all ops in this case. */
341 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
342
343 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
344 #define ARM_FLAG_BIG_END (1 << 9)
345
346 /* Nonzero if we should compile for Thumb interworking. */
347 #define ARM_FLAG_INTERWORK (1 << 10)
348
349 /* Nonzero if we should have little-endian words even when compiling for
350 big-endian (for backwards compatibility with older versions of GCC). */
351 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
352
353 /* Nonzero if we need to protect the prolog from scheduling */
354 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
355
356 /* Nonzero if a call to abort should be generated if a noreturn
357 function tries to return. */
358 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
359
360 /* Nonzero if function prologues should not load the PIC register. */
361 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
362
363 /* Nonzero if all call instructions should be indirect. */
364 #define ARM_FLAG_LONG_CALLS (1 << 15)
365
366 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
367 #define ARM_FLAG_THUMB (1 << 16)
368
369 /* Set if a TPCS style stack frame should be generated, for non-leaf
370 functions, even if they do not need one. */
371 #define THUMB_FLAG_BACKTRACE (1 << 17)
372
373 /* Set if a TPCS style stack frame should be generated, for leaf
374 functions, even if they do not need one. */
375 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
376
377 /* Set if externally visible functions should assume that they
378 might be called in ARM mode, from a non-thumb aware code. */
379 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
380
381 /* Set if calls via function pointers should assume that their
382 destination is non-Thumb aware. */
383 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
384
385 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
386 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
387 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
388 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
389 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
390 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
391 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
392 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
393 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
394 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
395 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
396 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
397 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
398 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
399 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
400 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
401 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
402 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
403 #define TARGET_ARM (! TARGET_THUMB)
404 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
405 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
406 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
407 #define TARGET_BACKTRACE (leaf_function_p () \
408 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
409 : (target_flags & THUMB_FLAG_BACKTRACE))
410
411 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
412 Bit 31 is reserved. See riscix.h. */
413 #ifndef SUBTARGET_SWITCHES
414 #define SUBTARGET_SWITCHES
415 #endif
416
417 #define TARGET_SWITCHES \
418 { \
419 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
420 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
421 N_("Generate APCS conformant stack frames") }, \
422 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
423 {"poke-function-name", ARM_FLAG_POKE, \
424 N_("Store function names in object code") }, \
425 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
426 {"fpe", ARM_FLAG_FPE, "" }, \
427 {"apcs-32", ARM_FLAG_APCS_32, \
428 N_("Use the 32bit version of the APCS") }, \
429 {"apcs-26", -ARM_FLAG_APCS_32, \
430 N_("Use the 26bit version of the APCS") }, \
431 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
432 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
433 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
434 N_("Pass FP arguments in FP registers") }, \
435 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
436 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
437 N_("Generate re-entrant, PIC code") }, \
438 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
439 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
440 N_("The MMU will trap on unaligned accesses") }, \
441 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
442 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
443 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
444 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
446 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
447 N_("Use library calls to perform FP operations") }, \
448 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
449 N_("Use hardware floating point instructions") }, \
450 {"big-endian", ARM_FLAG_BIG_END, \
451 N_("Assume target CPU is configured as big endian") }, \
452 {"little-endian", -ARM_FLAG_BIG_END, \
453 N_("Assume target CPU is configured as little endian") }, \
454 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
455 N_("Assume big endian bytes, little endian words") }, \
456 {"thumb-interwork", ARM_FLAG_INTERWORK, \
457 N_("Support calls between THUMB and ARM instructions sets") }, \
458 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
459 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
460 N_("Generate a call to abort if a noreturn function returns")}, \
461 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
462 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
463 N_("Do not move instructions into a function's prologue") }, \
464 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
465 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
466 N_("Do not load the PIC register in function prologues") }, \
467 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
468 {"long-calls", ARM_FLAG_LONG_CALLS, \
469 N_("Generate call insns as indirect calls, if necessary") }, \
470 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
471 {"thumb", ARM_FLAG_THUMB, \
472 N_("Compile for the Thumb not the ARM") }, \
473 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
474 {"arm", -ARM_FLAG_THUMB, "" }, \
475 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
476 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
477 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
478 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
479 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
480 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
481 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
482 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
483 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
484 "" }, \
485 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
486 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
487 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
488 "" }, \
489 SUBTARGET_SWITCHES \
490 {"", TARGET_DEFAULT, "" } \
491 }
492
493 #define TARGET_OPTIONS \
494 { \
495 {"cpu=", & arm_select[0].string, \
496 N_("Specify the name of the target CPU") }, \
497 {"arch=", & arm_select[1].string, \
498 N_("Specify the name of the target architecture") }, \
499 {"tune=", & arm_select[2].string, "" }, \
500 {"fpe=", & target_fp_name, "" }, \
501 {"fp=", & target_fp_name, \
502 N_("Specify the version of the floating point emulator") }, \
503 {"structure-size-boundary=", & structure_size_string, \
504 N_("Specify the minimum bit alignment of structures") }, \
505 {"pic-register=", & arm_pic_register_string, \
506 N_("Specify the register to be used for PIC addressing") } \
507 }
508
509 struct arm_cpu_select
510 {
511 const char * string;
512 const char * name;
513 const struct processors * processors;
514 };
515
516 /* This is a magic array. If the user specifies a command line switch
517 which matches one of the entries in TARGET_OPTIONS then the corresponding
518 string pointer will be set to the value specified by the user. */
519 extern struct arm_cpu_select arm_select[];
520
521 enum prog_mode_type
522 {
523 prog_mode26,
524 prog_mode32
525 };
526
527 /* Recast the program mode class to be the prog_mode attribute */
528 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
529
530 extern enum prog_mode_type arm_prgmode;
531
532 /* What sort of floating point unit do we have? Hardware or software.
533 If software, is it issue 2 or issue 3? */
534 enum floating_point_type
535 {
536 FP_HARD,
537 FP_SOFT2,
538 FP_SOFT3
539 };
540
541 /* Recast the floating point class to be the floating point attribute. */
542 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
543
544 /* What type of floating point to tune for */
545 extern enum floating_point_type arm_fpu;
546
547 /* What type of floating point instructions are available */
548 extern enum floating_point_type arm_fpu_arch;
549
550 /* Default floating point architecture. Override in sub-target if
551 necessary. */
552 #define FP_DEFAULT FP_SOFT2
553
554 /* Nonzero if the processor has a fast multiply insn, and one that does
555 a 64-bit multiply of two 32-bit values. */
556 extern int arm_fast_multiply;
557
558 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
559 extern int arm_arch4;
560
561 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
562 extern int arm_arch5;
563
564 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
565 extern int arm_arch5e;
566
567 /* Nonzero if this chip can benefit from load scheduling. */
568 extern int arm_ld_sched;
569
570 /* Nonzero if generating thumb code. */
571 extern int thumb_code;
572
573 /* Nonzero if this chip is a StrongARM. */
574 extern int arm_is_strong;
575
576 /* Nonzero if this chip is an XScale. */
577 extern int arm_is_xscale;
578
579 /* Nonzero if this chip is a an ARM6 or an ARM7. */
580 extern int arm_is_6_or_7;
581
582 #ifndef TARGET_DEFAULT
583 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
584 #endif
585
586 /* The frame pointer register used in gcc has nothing to do with debugging;
587 that is controlled by the APCS-FRAME option. */
588 #define CAN_DEBUG_WITHOUT_FP
589
590 #define TARGET_MEM_FUNCTIONS 1
591
592 #define OVERRIDE_OPTIONS arm_override_options ()
593
594 /* Nonzero if PIC code requires explicit qualifiers to generate
595 PLT and GOT relocs rather than the assembler doing so implicitly.
596 Subtargets can override these if required. */
597 #ifndef NEED_GOT_RELOC
598 #define NEED_GOT_RELOC 0
599 #endif
600 #ifndef NEED_PLT_RELOC
601 #define NEED_PLT_RELOC 0
602 #endif
603
604 /* Nonzero if we need to refer to the GOT with a PC-relative
605 offset. In other words, generate
606
607 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
608
609 rather than
610
611 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
612
613 The default is true, which matches NetBSD. Subtargets can
614 override this if required. */
615 #ifndef GOT_PCREL
616 #define GOT_PCREL 1
617 #endif
618 \f
619 /* Target machine storage Layout. */
620
621
622 /* Define this macro if it is advisable to hold scalars in registers
623 in a wider mode than that declared by the program. In such cases,
624 the value is constrained to be within the bounds of the declared
625 type, but kept valid in the wider mode. The signedness of the
626 extension may differ from that of the type. */
627
628 /* It is far faster to zero extend chars than to sign extend them */
629
630 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
631 if (GET_MODE_CLASS (MODE) == MODE_INT \
632 && GET_MODE_SIZE (MODE) < 4) \
633 { \
634 if (MODE == QImode) \
635 UNSIGNEDP = 1; \
636 else if (MODE == HImode) \
637 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
638 (MODE) = SImode; \
639 }
640
641 /* Define this macro if the promotion described by `PROMOTE_MODE'
642 should also be done for outgoing function arguments. */
643 /* This is required to ensure that push insns always push a word. */
644 #define PROMOTE_FUNCTION_ARGS
645
646 /* Define for XFmode extended real floating point support.
647 This will automatically cause REAL_ARITHMETIC to be defined. */
648 /* For the ARM:
649 I think I have added all the code to make this work. Unfortunately,
650 early releases of the floating point emulation code on RISCiX used a
651 different format for extended precision numbers. On my RISCiX box there
652 is a bug somewhere which causes the machine to lock up when running enquire
653 with long doubles. There is the additional aspect that Norcroft C
654 treats long doubles as doubles and we ought to remain compatible.
655 Perhaps someone with an FPA coprocessor and not running RISCiX would like
656 to try this someday. */
657 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
658
659 /* Disable XFmode patterns in md file */
660 #define ENABLE_XF_PATTERNS 0
661
662 /* Define if you don't want extended real, but do want to use the
663 software floating point emulator for REAL_ARITHMETIC and
664 decimal <-> binary conversion. */
665 /* See comment above */
666 #define REAL_ARITHMETIC
667
668 /* Define this if most significant bit is lowest numbered
669 in instructions that operate on numbered bit-fields. */
670 #define BITS_BIG_ENDIAN 0
671
672 /* Define this if most significant byte of a word is the lowest numbered.
673 Most ARM processors are run in little endian mode, so that is the default.
674 If you want to have it run-time selectable, change the definition in a
675 cover file to be TARGET_BIG_ENDIAN. */
676 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
677
678 /* Define this if most significant word of a multiword number is the lowest
679 numbered.
680 This is always false, even when in big-endian mode. */
681 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
682
683 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
684 on processor pre-defineds when compiling libgcc2.c. */
685 #if defined(__ARMEB__) && !defined(__ARMWEL__)
686 #define LIBGCC2_WORDS_BIG_ENDIAN 1
687 #else
688 #define LIBGCC2_WORDS_BIG_ENDIAN 0
689 #endif
690
691 /* Define this if most significant word of doubles is the lowest numbered.
692 This is always true, even when in little-endian mode. */
693 #define FLOAT_WORDS_BIG_ENDIAN 1
694
695 /* Number of bits in an addressable storage unit */
696 #define BITS_PER_UNIT 8
697
698 #define BITS_PER_WORD 32
699
700 #define UNITS_PER_WORD 4
701
702 #define POINTER_SIZE 32
703
704 #define PARM_BOUNDARY 32
705
706 #define STACK_BOUNDARY 32
707
708 #define FUNCTION_BOUNDARY 32
709
710 #define EMPTY_FIELD_BOUNDARY 32
711
712 #define BIGGEST_ALIGNMENT 32
713
714 /* Make strings word-aligned so strcpy from constants will be faster. */
715 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
716
717 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
718 ((TREE_CODE (EXP) == STRING_CST \
719 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
720 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
721
722 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
723 value set in previous versions of this toolchain was 8, which produces more
724 compact structures. The command line option -mstructure_size_boundary=<n>
725 can be used to change this value. For compatability with the ARM SDK
726 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
727 0020D) page 2-20 says "Structures are aligned on word boundaries". */
728 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
729 extern int arm_structure_size_boundary;
730
731 /* This is the value used to initialise arm_structure_size_boundary. If a
732 particular arm target wants to change the default value it should change
733 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
734 for an example of this. */
735 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
736 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
737 #endif
738
739 /* Used when parsing command line option -mstructure_size_boundary. */
740 extern const char * structure_size_string;
741
742 /* Non-zero if move instructions will actually fail to work
743 when given unaligned data. */
744 #define STRICT_ALIGNMENT 1
745
746 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
747
748 \f
749 /* Standard register usage. */
750
751 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
752 (S - saved over call).
753
754 r0 * argument word/integer result
755 r1-r3 argument word
756
757 r4-r8 S register variable
758 r9 S (rfp) register variable (real frame pointer)
759
760 r10 F S (sl) stack limit (used by -mapcs-stack-check)
761 r11 F S (fp) argument pointer
762 r12 (ip) temp workspace
763 r13 F S (sp) lower end of current stack frame
764 r14 (lr) link address/workspace
765 r15 F (pc) program counter
766
767 f0 floating point result
768 f1-f3 floating point scratch
769
770 f4-f7 S floating point variable
771
772 cc This is NOT a real register, but is used internally
773 to represent things that use or set the condition
774 codes.
775 sfp This isn't either. It is used during rtl generation
776 since the offset between the frame pointer and the
777 auto's isn't known until after register allocation.
778 afp Nor this, we only need this because of non-local
779 goto. Without it fp appears to be used and the
780 elimination code won't get rid of sfp. It tracks
781 fp exactly at all times.
782
783 *: See CONDITIONAL_REGISTER_USAGE */
784
785 /* The stack backtrace structure is as follows:
786 fp points to here: | save code pointer | [fp]
787 | return link value | [fp, #-4]
788 | return sp value | [fp, #-8]
789 | return fp value | [fp, #-12]
790 [| saved r10 value |]
791 [| saved r9 value |]
792 [| saved r8 value |]
793 [| saved r7 value |]
794 [| saved r6 value |]
795 [| saved r5 value |]
796 [| saved r4 value |]
797 [| saved r3 value |]
798 [| saved r2 value |]
799 [| saved r1 value |]
800 [| saved r0 value |]
801 [| saved f7 value |] three words
802 [| saved f6 value |] three words
803 [| saved f5 value |] three words
804 [| saved f4 value |] three words
805 r0-r3 are not normally saved in a C function. */
806
807 /* 1 for registers that have pervasive standard uses
808 and are not available for the register allocator. */
809 #define FIXED_REGISTERS \
810 { \
811 0,0,0,0,0,0,0,0, \
812 0,0,0,0,0,1,0,1, \
813 0,0,0,0,0,0,0,0, \
814 1,1,1 \
815 }
816
817 /* 1 for registers not available across function calls.
818 These must include the FIXED_REGISTERS and also any
819 registers that can be used without being saved.
820 The latter must include the registers where values are returned
821 and the register where structure-value addresses are passed.
822 Aside from that, you can include as many other registers as you like.
823 The CC is not preserved over function calls on the ARM 6, so it is
824 easier to assume this for all. SFP is preserved, since FP is. */
825 #define CALL_USED_REGISTERS \
826 { \
827 1,1,1,1,0,0,0,0, \
828 0,0,0,0,1,1,1,1, \
829 1,1,1,1,0,0,0,0, \
830 1,1,1 \
831 }
832
833 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
834 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
835 #endif
836
837 #define CONDITIONAL_REGISTER_USAGE \
838 { \
839 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
840 { \
841 int regno; \
842 for (regno = FIRST_ARM_FP_REGNUM; \
843 regno <= LAST_ARM_FP_REGNUM; ++regno) \
844 fixed_regs[regno] = call_used_regs[regno] = 1; \
845 } \
846 if (flag_pic) \
847 { \
848 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
849 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
850 } \
851 else if (TARGET_APCS_STACK) \
852 { \
853 fixed_regs[10] = 1; \
854 call_used_regs[10] = 1; \
855 } \
856 if (TARGET_APCS_FRAME) \
857 { \
858 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
859 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
860 } \
861 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
862 }
863
864 /* These are a couple of extensions to the formats accecpted
865 by asm_fprintf:
866 %@ prints out ASM_COMMENT_START
867 %r prints out REGISTER_PREFIX reg_names[arg] */
868 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
869 case '@': \
870 fputs (ASM_COMMENT_START, FILE); \
871 break; \
872 \
873 case 'r': \
874 fputs (REGISTER_PREFIX, FILE); \
875 fputs (reg_names [va_arg (ARGS, int)], FILE); \
876 break;
877
878 /* Round X up to the nearest word. */
879 #define ROUND_UP(X) (((X) + 3) & ~3)
880
881 /* Convert fron bytes to ints. */
882 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
883
884 /* The number of (integer) registers required to hold a quantity of type MODE. */
885 #define NUM_REGS(MODE) \
886 NUM_INTS (GET_MODE_SIZE (MODE))
887
888 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
889 #define NUM_REGS2(MODE, TYPE) \
890 NUM_INTS ((MODE) == BLKmode ? \
891 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
892
893 /* The number of (integer) argument register available. */
894 #define NUM_ARG_REGS 4
895
896 /* Return the regiser number of the N'th (integer) argument. */
897 #define ARG_REGISTER(N) (N - 1)
898
899 /* RTX for structure returns. NULL means use a hidden first argument. */
900 #define STRUCT_VALUE 0
901
902 /* Specify the registers used for certain standard purposes.
903 The values of these macros are register numbers. */
904
905 /* The number of the last argument register. */
906 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
907
908 /* The number of the last "lo" register (thumb). */
909 #define LAST_LO_REGNUM 7
910
911 /* The register that holds the return address in exception handlers. */
912 #define EXCEPTION_LR_REGNUM 2
913
914 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
915 as an invisible last argument (possible since varargs don't exist in
916 Pascal), so the following is not true. */
917 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
918
919 /* Define this to be where the real frame pointer is if it is not possible to
920 work out the offset between the frame pointer and the automatic variables
921 until after register allocation has taken place. FRAME_POINTER_REGNUM
922 should point to a special register that we will make sure is eliminated.
923
924 For the Thumb we have another problem. The TPCS defines the frame pointer
925 as r11, and GCC belives that it is always possible to use the frame pointer
926 as base register for addressing purposes. (See comments in
927 find_reloads_address()). But - the Thumb does not allow high registers,
928 including r11, to be used as base address registers. Hence our problem.
929
930 The solution used here, and in the old thumb port is to use r7 instead of
931 r11 as the hard frame pointer and to have special code to generate
932 backtrace structures on the stack (if required to do so via a command line
933 option) using r11. This is the only 'user visable' use of r11 as a frame
934 pointer. */
935 #define ARM_HARD_FRAME_POINTER_REGNUM 11
936 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
937
938 #define HARD_FRAME_POINTER_REGNUM \
939 (TARGET_ARM \
940 ? ARM_HARD_FRAME_POINTER_REGNUM \
941 : THUMB_HARD_FRAME_POINTER_REGNUM)
942
943 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
944
945 /* Register to use for pushing function arguments. */
946 #define STACK_POINTER_REGNUM SP_REGNUM
947
948 /* ARM floating pointer registers. */
949 #define FIRST_ARM_FP_REGNUM 16
950 #define LAST_ARM_FP_REGNUM 23
951
952 /* Base register for access to local variables of the function. */
953 #define FRAME_POINTER_REGNUM 25
954
955 /* Base register for access to arguments of the function. */
956 #define ARG_POINTER_REGNUM 26
957
958 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
959 #define FIRST_PSEUDO_REGISTER 27
960
961 /* Value should be nonzero if functions must have frame pointers.
962 Zero means the frame pointer need not be set up (and parms may be accessed
963 via the stack pointer) in functions that seem suitable.
964 If we have to have a frame pointer we might as well make use of it.
965 APCS says that the frame pointer does not need to be pushed in leaf
966 functions, or simple tail call functions. */
967 #define FRAME_POINTER_REQUIRED \
968 (current_function_has_nonlocal_label \
969 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
970
971 /* Return number of consecutive hard regs needed starting at reg REGNO
972 to hold something of mode MODE.
973 This is ordinarily the length in words of a value of mode MODE
974 but can be less for certain modes in special long registers.
975
976 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
977 mode. */
978 #define HARD_REGNO_NREGS(REGNO, MODE) \
979 ((TARGET_ARM \
980 && REGNO >= FIRST_ARM_FP_REGNUM \
981 && REGNO != FRAME_POINTER_REGNUM \
982 && REGNO != ARG_POINTER_REGNUM) \
983 ? 1 : NUM_REGS (MODE))
984
985 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
986 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
987 regs holding FP.
988 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
989 so that there is always a second lo register available to hold the upper
990 part of the value. Probably we ought to ensure that the register is the
991 start of an even numbered register pair. */
992 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
993 (TARGET_ARM ? \
994 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
995 ( REGNO <= LAST_ARM_REGNUM \
996 || REGNO == FRAME_POINTER_REGNUM \
997 || REGNO == ARG_POINTER_REGNUM \
998 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
999 : \
1000 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1001 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
1002
1003 /* Value is 1 if it is a good idea to tie two pseudo registers
1004 when one has mode MODE1 and one has mode MODE2.
1005 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1006 for any hard reg, then this must be 0 for correct output. */
1007 #define MODES_TIEABLE_P(MODE1, MODE2) \
1008 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1009
1010 /* The order in which register should be allocated. It is good to use ip
1011 since no saving is required (though calls clobber it) and it never contains
1012 function parameters. It is quite good to use lr since other calls may
1013 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1014 least likely to contain a function parameter; in addition results are
1015 returned in r0. */
1016 #define REG_ALLOC_ORDER \
1017 { \
1018 3, 2, 1, 0, 12, 14, 4, 5, \
1019 6, 7, 8, 10, 9, 11, 13, 15, \
1020 16, 17, 18, 19, 20, 21, 22, 23, \
1021 24, 25, 26 \
1022 }
1023 \f
1024 /* Register and constant classes. */
1025
1026 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1027 Now that the Thumb is involved it has become more compilcated. */
1028 enum reg_class
1029 {
1030 NO_REGS,
1031 FPU_REGS,
1032 LO_REGS,
1033 STACK_REG,
1034 BASE_REGS,
1035 HI_REGS,
1036 CC_REG,
1037 GENERAL_REGS,
1038 ALL_REGS,
1039 LIM_REG_CLASSES
1040 };
1041
1042 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1043
1044 /* Give names of register classes as strings for dump file. */
1045 #define REG_CLASS_NAMES \
1046 { \
1047 "NO_REGS", \
1048 "FPU_REGS", \
1049 "LO_REGS", \
1050 "STACK_REG", \
1051 "BASE_REGS", \
1052 "HI_REGS", \
1053 "CC_REG", \
1054 "GENERAL_REGS", \
1055 "ALL_REGS", \
1056 }
1057
1058 /* Define which registers fit in which classes.
1059 This is an initializer for a vector of HARD_REG_SET
1060 of length N_REG_CLASSES. */
1061 #define REG_CLASS_CONTENTS \
1062 { \
1063 { 0x0000000 }, /* NO_REGS */ \
1064 { 0x0FF0000 }, /* FPU_REGS */ \
1065 { 0x00000FF }, /* LO_REGS */ \
1066 { 0x0002000 }, /* STACK_REG */ \
1067 { 0x00020FF }, /* BASE_REGS */ \
1068 { 0x000FF00 }, /* HI_REGS */ \
1069 { 0x1000000 }, /* CC_REG */ \
1070 { 0x200FFFF }, /* GENERAL_REGS */ \
1071 { 0x2FFFFFF } /* ALL_REGS */ \
1072 }
1073
1074 /* The same information, inverted:
1075 Return the class number of the smallest class containing
1076 reg number REGNO. This could be a conditional expression
1077 or could index an array. */
1078 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1079
1080 /* The class value for index registers, and the one for base regs. */
1081 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1082 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1083
1084 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1085 registers explicitly used in the rtl to be used as spill registers
1086 but prevents the compiler from extending the lifetime of these
1087 registers. */
1088 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1089
1090 /* Get reg_class from a letter such as appears in the machine description.
1091 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1092 ARM, but several more letters for the Thumb. */
1093 #define REG_CLASS_FROM_LETTER(C) \
1094 ( (C) == 'f' ? FPU_REGS \
1095 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1096 : TARGET_ARM ? NO_REGS \
1097 : (C) == 'h' ? HI_REGS \
1098 : (C) == 'b' ? BASE_REGS \
1099 : (C) == 'k' ? STACK_REG \
1100 : (C) == 'c' ? CC_REG \
1101 : NO_REGS)
1102
1103 /* The letters I, J, K, L and M in a register constraint string
1104 can be used to stand for particular ranges of immediate operands.
1105 This macro defines what the ranges are.
1106 C is the letter, and VALUE is a constant value.
1107 Return 1 if VALUE is in the range specified by C.
1108 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1109 J: valid indexing constants.
1110 K: ~value ok in rhs argument of data operand.
1111 L: -value ok in rhs argument of data operand.
1112 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1113 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1114 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1115 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1116 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1117 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1118 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1119 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1120 : 0)
1121
1122 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1123 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1124 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1125 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1126 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1127 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1128 && ((VAL) & 3) == 0) : \
1129 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1130 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1131 : 0)
1132
1133 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1134 (TARGET_ARM ? \
1135 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1136
1137 /* Constant letter 'G' for the FPU immediate constants.
1138 'H' means the same constant negated. */
1139 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1140 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1141 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1142
1143 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1144 (TARGET_ARM ? \
1145 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1146
1147 /* For the ARM, `Q' means that this is a memory operand that is just
1148 an offset from a register.
1149 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1150 address. This means that the symbol is in the text segment and can be
1151 accessed without using a load. */
1152
1153 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1154 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1155 (C) == 'R' ? (GET_CODE (OP) == MEM \
1156 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1157 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1158 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1159 : 0)
1160
1161 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1162 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1163 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1164
1165 #define EXTRA_CONSTRAINT(X, C) \
1166 (TARGET_ARM ? \
1167 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1168
1169 /* Given an rtx X being reloaded into a reg required to be
1170 in class CLASS, return the class of reg to actually use.
1171 In general this is just CLASS, but for the Thumb we prefer
1172 a LO_REGS class or a subset. */
1173 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1174 (TARGET_ARM ? (CLASS) : \
1175 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1176
1177 /* Must leave BASE_REGS reloads alone */
1178 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1179 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1180 ? ((true_regnum (X) == -1 ? LO_REGS \
1181 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1182 : NO_REGS)) \
1183 : NO_REGS)
1184
1185 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1186 ((CLASS) != LO_REGS \
1187 ? ((true_regnum (X) == -1 ? LO_REGS \
1188 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1189 : NO_REGS)) \
1190 : NO_REGS)
1191
1192 /* Return the register class of a scratch register needed to copy IN into
1193 or out of a register in CLASS in MODE. If it can be done directly,
1194 NO_REGS is returned. */
1195 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1196 (TARGET_ARM ? \
1197 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1198 ? GENERAL_REGS : NO_REGS) \
1199 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1200
1201 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1202 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1203 (TARGET_ARM ? \
1204 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1205 && (GET_CODE (X) == MEM \
1206 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1207 && true_regnum (X) == -1))) \
1208 ? GENERAL_REGS : NO_REGS) \
1209 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1210
1211 /* Try a machine-dependent way of reloading an illegitimate address
1212 operand. If we find one, push the reload and jump to WIN. This
1213 macro is used in only one place: `find_reloads_address' in reload.c.
1214
1215 For the ARM, we wish to handle large displacements off a base
1216 register by splitting the addend across a MOV and the mem insn.
1217 This can cut the number of reloads needed. */
1218 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1219 do \
1220 { \
1221 if (GET_CODE (X) == PLUS \
1222 && GET_CODE (XEXP (X, 0)) == REG \
1223 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1224 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1225 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1226 { \
1227 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1228 HOST_WIDE_INT low, high; \
1229 \
1230 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1231 low = ((val & 0xf) ^ 0x8) - 0x8; \
1232 else if (MODE == SImode \
1233 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1234 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1235 /* Need to be careful, -4096 is not a valid offset. */ \
1236 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1237 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1238 /* Need to be careful, -256 is not a valid offset. */ \
1239 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1240 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1241 && TARGET_HARD_FLOAT) \
1242 /* Need to be careful, -1024 is not a valid offset. */ \
1243 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1244 else \
1245 break; \
1246 \
1247 high = ((((val - low) & HOST_UINT (0xffffffff)) \
1248 ^ HOST_UINT (0x80000000)) \
1249 - HOST_UINT (0x80000000)); \
1250 /* Check for overflow or zero */ \
1251 if (low == 0 || high == 0 || (high + low != val)) \
1252 break; \
1253 \
1254 /* Reload the high part into a base reg; leave the low part \
1255 in the mem. */ \
1256 X = gen_rtx_PLUS (GET_MODE (X), \
1257 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1258 GEN_INT (high)), \
1259 GEN_INT (low)); \
1260 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1261 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1262 OPNUM, TYPE); \
1263 goto WIN; \
1264 } \
1265 } \
1266 while (0)
1267
1268 /* ??? If an HImode FP+large_offset address is converted to an HImode
1269 SP+large_offset address, then reload won't know how to fix it. It sees
1270 only that SP isn't valid for HImode, and so reloads the SP into an index
1271 register, but the resulting address is still invalid because the offset
1272 is too big. We fix it here instead by reloading the entire address. */
1273 /* We could probably achieve better results by defining PROMOTE_MODE to help
1274 cope with the variances between the Thumb's signed and unsigned byte and
1275 halfword load instructions. */
1276 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1277 { \
1278 if (GET_CODE (X) == PLUS \
1279 && GET_MODE_SIZE (MODE) < 4 \
1280 && GET_CODE (XEXP (X, 0)) == REG \
1281 && XEXP (X, 0) == stack_pointer_rtx \
1282 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1283 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1284 { \
1285 rtx orig_X = X; \
1286 X = copy_rtx (X); \
1287 push_reload (orig_X, NULL_RTX, &X, NULL, \
1288 BASE_REG_CLASS, \
1289 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1290 goto WIN; \
1291 } \
1292 }
1293
1294 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1295 if (TARGET_ARM) \
1296 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1297 else \
1298 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1299
1300 /* Return the maximum number of consecutive registers
1301 needed to represent mode MODE in a register of class CLASS.
1302 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1303 #define CLASS_MAX_NREGS(CLASS, MODE) \
1304 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1305
1306 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1307 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1308 (TARGET_ARM ? \
1309 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1310 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1311 : \
1312 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1313 \f
1314 /* Stack layout; function entry, exit and calling. */
1315
1316 /* Define this if pushing a word on the stack
1317 makes the stack pointer a smaller address. */
1318 #define STACK_GROWS_DOWNWARD 1
1319
1320 /* Define this if the nominal address of the stack frame
1321 is at the high-address end of the local variables;
1322 that is, each additional local variable allocated
1323 goes at a more negative offset in the frame. */
1324 #define FRAME_GROWS_DOWNWARD 1
1325
1326 /* Offset within stack frame to start allocating local variables at.
1327 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1328 first local allocated. Otherwise, it is the offset to the BEGINNING
1329 of the first local allocated. */
1330 #define STARTING_FRAME_OFFSET 0
1331
1332 /* If we generate an insn to push BYTES bytes,
1333 this says how many the stack pointer really advances by. */
1334 /* The push insns do not do this rounding implicitly.
1335 So don't define this. */
1336 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1337
1338 /* Define this if the maximum size of all the outgoing args is to be
1339 accumulated and pushed during the prologue. The amount can be
1340 found in the variable current_function_outgoing_args_size. */
1341 #define ACCUMULATE_OUTGOING_ARGS 1
1342
1343 /* Offset of first parameter from the argument pointer register value. */
1344 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1345
1346 /* Value is the number of byte of arguments automatically
1347 popped when returning from a subroutine call.
1348 FUNDECL is the declaration node of the function (as a tree),
1349 FUNTYPE is the data type of the function (as a tree),
1350 or for a library call it is an identifier node for the subroutine name.
1351 SIZE is the number of bytes of arguments passed on the stack.
1352
1353 On the ARM, the caller does not pop any of its arguments that were passed
1354 on the stack. */
1355 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1356
1357 /* Define how to find the value returned by a library function
1358 assuming the value has mode MODE. */
1359 #define LIBCALL_VALUE(MODE) \
1360 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1361 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1362 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1363
1364 /* Define how to find the value returned by a function.
1365 VALTYPE is the data type of the value (as a tree).
1366 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1367 otherwise, FUNC is 0. */
1368 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1369 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1370
1371 /* 1 if N is a possible register number for a function value.
1372 On the ARM, only r0 and f0 can return results. */
1373 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1374 ((REGNO) == ARG_REGISTER (1) \
1375 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1376
1377 /* How large values are returned */
1378 /* A C expression which can inhibit the returning of certain function values
1379 in registers, based on the type of value. */
1380 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1381
1382 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1383 values must be in memory. On the ARM, they need only do so if larger
1384 than a word, or if they contain elements offset from zero in the struct. */
1385 #define DEFAULT_PCC_STRUCT_RETURN 0
1386
1387 /* Flags for the call/call_value rtl operations set up by function_arg. */
1388 #define CALL_NORMAL 0x00000000 /* No special processing. */
1389 #define CALL_LONG 0x00000001 /* Always call indirect. */
1390 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1391
1392 /* These bits describe the different types of function supported
1393 by the ARM backend. They are exclusive. ie a function cannot be both a
1394 normal function and an interworked function, for example. Knowing the
1395 type of a function is important for determining its prologue and
1396 epilogue sequences.
1397 Note value 7 is currently unassigned. Also note that the interrupt
1398 function types all have bit 2 set, so that they can be tested for easily.
1399 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1400 machine_function structure is initialised (to zero) func_type will
1401 default to unknown. This will force the first use of arm_current_func_type
1402 to call arm_compute_func_type. */
1403 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1404 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1405 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1406 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1407 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1408 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1409 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1410
1411 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1412
1413 /* In addition functions can have several type modifiers,
1414 outlined by these bit masks: */
1415 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1416 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1417 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1418 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1419
1420 /* Some macros to test these flags. */
1421 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1422 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1423 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1424 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1425 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1426
1427 /* A C structure for machine-specific, per-function data.
1428 This is added to the cfun structure. */
1429 typedef struct machine_function
1430 {
1431 /* Records __builtin_return address. */
1432 struct rtx_def *ra_rtx;
1433 /* Additionsl stack adjustment in __builtin_eh_throw. */
1434 struct rtx_def *eh_epilogue_sp_ofs;
1435 /* Records if LR has to be saved for far jumps. */
1436 int far_jump_used;
1437 /* Records if ARG_POINTER was ever live. */
1438 int arg_pointer_live;
1439 /* Records if the save of LR has been eliminated. */
1440 int lr_save_eliminated;
1441 /* Records the type of the current function. */
1442 unsigned long func_type;
1443 }
1444 machine_function;
1445
1446 /* A C type for declaring a variable that is used as the first argument of
1447 `FUNCTION_ARG' and other related values. For some target machines, the
1448 type `int' suffices and can hold the number of bytes of argument so far. */
1449 typedef struct
1450 {
1451 /* This is the number of registers of arguments scanned so far. */
1452 int nregs;
1453 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1454 int call_cookie;
1455 } CUMULATIVE_ARGS;
1456
1457 /* Define where to put the arguments to a function.
1458 Value is zero to push the argument on the stack,
1459 or a hard register in which to store the argument.
1460
1461 MODE is the argument's machine mode.
1462 TYPE is the data type of the argument (as a tree).
1463 This is null for libcalls where that information may
1464 not be available.
1465 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1466 the preceding args and about the function being called.
1467 NAMED is nonzero if this argument is a named parameter
1468 (otherwise it is an extra parameter matching an ellipsis).
1469
1470 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1471 other arguments are passed on the stack. If (NAMED == 0) (which happens
1472 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1473 passed in the stack (function_prologue will indeed make it pass in the
1474 stack if necessary). */
1475 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1476 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1477
1478 /* For an arg passed partly in registers and partly in memory,
1479 this is the number of registers used.
1480 For args passed entirely in registers or entirely in memory, zero. */
1481 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1482 ( NUM_ARG_REGS > (CUM).nregs \
1483 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1484 ? NUM_ARG_REGS - (CUM).nregs : 0)
1485
1486 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1487 for a call to a function whose data type is FNTYPE.
1488 For a library call, FNTYPE is 0.
1489 On the ARM, the offset starts at 0. */
1490 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1491 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1492
1493 /* Update the data in CUM to advance over an argument
1494 of mode MODE and data type TYPE.
1495 (TYPE is null for libcalls where that information may not be available.) */
1496 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1497 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1498
1499 /* 1 if N is a possible register number for function argument passing.
1500 On the ARM, r0-r3 are used to pass args. */
1501 #define FUNCTION_ARG_REGNO_P(REGNO) \
1502 ((REGNO) >= 0 && (REGNO) <= 3)
1503
1504 \f
1505 /* Tail calling. */
1506
1507 /* A C expression that evaluates to true if it is ok to perform a sibling
1508 call to DECL. */
1509 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1510
1511 /* Perform any actions needed for a function that is receiving a variable
1512 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1513 of the current parameter. PRETEND_SIZE is a variable that should be set to
1514 the amount of stack that must be pushed by the prolog to pretend that our
1515 caller pushed it.
1516
1517 Normally, this macro will push all remaining incoming registers on the
1518 stack and set PRETEND_SIZE to the length of the registers pushed.
1519
1520 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1521 named arg and all anonymous args onto the stack.
1522 XXX I know the prologue shouldn't be pushing registers, but it is faster
1523 that way. */
1524 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1525 { \
1526 extern int current_function_anonymous_args; \
1527 current_function_anonymous_args = 1; \
1528 if ((CUM).nregs < NUM_ARG_REGS) \
1529 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1530 }
1531
1532 /* Generate assembly output for the start of a function. */
1533 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1534 do \
1535 { \
1536 if (TARGET_ARM) \
1537 output_arm_prologue (STREAM, SIZE); \
1538 else \
1539 output_thumb_prologue (STREAM); \
1540 } \
1541 while (0)
1542
1543 /* If your target environment doesn't prefix user functions with an
1544 underscore, you may wish to re-define this to prevent any conflicts.
1545 e.g. AOF may prefix mcount with an underscore. */
1546 #ifndef ARM_MCOUNT_NAME
1547 #define ARM_MCOUNT_NAME "*mcount"
1548 #endif
1549
1550 /* Call the function profiler with a given profile label. The Acorn
1551 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1552 On the ARM the full profile code will look like:
1553 .data
1554 LP1
1555 .word 0
1556 .text
1557 mov ip, lr
1558 bl mcount
1559 .word LP1
1560
1561 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1562 will output the .text section.
1563
1564 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1565 ``prof'' doesn't seem to mind about this! */
1566 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1567 { \
1568 char temp[20]; \
1569 rtx sym; \
1570 \
1571 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1572 IP_REGNUM, LR_REGNUM); \
1573 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1574 fputc ('\n', STREAM); \
1575 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1576 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1577 ASM_OUTPUT_INT (STREAM, sym); \
1578 }
1579
1580 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1581 { \
1582 fprintf (STREAM, "\tmov\\tip, lr\n"); \
1583 fprintf (STREAM, "\tbl\tmcount\n"); \
1584 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1585 }
1586
1587 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1588 if (TARGET_ARM) \
1589 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1590 else \
1591 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1592
1593 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1594 the stack pointer does not matter. The value is tested only in
1595 functions that have frame pointers.
1596 No definition is equivalent to always zero.
1597
1598 On the ARM, the function epilogue recovers the stack pointer from the
1599 frame. */
1600 #define EXIT_IGNORE_STACK 1
1601
1602 /* Generate the assembly code for function exit. */
1603 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1604 output_func_epilogue (SIZE)
1605
1606 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1607
1608 /* Determine if the epilogue should be output as RTL.
1609 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1610 #define USE_RETURN_INSN(ISCOND) \
1611 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1612
1613 /* Definitions for register eliminations.
1614
1615 This is an array of structures. Each structure initializes one pair
1616 of eliminable registers. The "from" register number is given first,
1617 followed by "to". Eliminations of the same "from" register are listed
1618 in order of preference.
1619
1620 We have two registers that can be eliminated on the ARM. First, the
1621 arg pointer register can often be eliminated in favor of the stack
1622 pointer register. Secondly, the pseudo frame pointer register can always
1623 be eliminated; it is replaced with either the stack or the real frame
1624 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1625 because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */
1626
1627 #define ELIMINABLE_REGS \
1628 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1629 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1630 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1631 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1632 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1633 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1634 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1635
1636 /* Given FROM and TO register numbers, say whether this elimination is
1637 allowed. Frame pointer elimination is automatically handled.
1638
1639 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1640 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1641 pointer, we must eliminate FRAME_POINTER_REGNUM into
1642 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1643 ARG_POINTER_REGNUM. */
1644 #define CAN_ELIMINATE(FROM, TO) \
1645 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1646 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1647 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1648 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1649 1)
1650
1651 /* Define the offset between two registers, one to be eliminated, and the
1652 other its replacement, at the start of a routine. */
1653 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1654 { \
1655 int volatile_func = IS_VOLATILE (arm_current_func_type ()); \
1656 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1657 { \
1658 if (! current_function_needs_context || ! frame_pointer_needed) \
1659 (OFFSET) = 0; \
1660 else \
1661 (OFFSET) = 4; \
1662 } \
1663 else if ((FROM) == FRAME_POINTER_REGNUM \
1664 && (TO) == STACK_POINTER_REGNUM) \
1665 (OFFSET) = current_function_outgoing_args_size \
1666 + ROUND_UP (get_frame_size ()); \
1667 else \
1668 { \
1669 int regno; \
1670 int offset = 12; \
1671 int saved_hard_reg = 0; \
1672 \
1673 if (! volatile_func) \
1674 { \
1675 for (regno = 0; regno <= 10; regno++) \
1676 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1677 saved_hard_reg = 1, offset += 4; \
1678 if (! TARGET_APCS_FRAME \
1679 && ! frame_pointer_needed \
1680 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \
1681 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \
1682 saved_hard_reg = 1, offset += 4; \
1683 /* PIC register is a fixed reg, so call_used_regs set. */ \
1684 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1685 saved_hard_reg = 1, offset += 4; \
1686 for (regno = FIRST_ARM_FP_REGNUM; \
1687 regno <= LAST_ARM_FP_REGNUM; regno++) \
1688 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1689 offset += 12; \
1690 } \
1691 if ((FROM) == FRAME_POINTER_REGNUM) \
1692 (OFFSET) = - offset; \
1693 else \
1694 { \
1695 if (! frame_pointer_needed) \
1696 offset -= 16; \
1697 if (! volatile_func \
1698 && (regs_ever_live[LR_REGNUM] /*|| saved_hard_reg */)) \
1699 offset += 4; \
1700 offset += current_function_outgoing_args_size; \
1701 (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \
1702 } \
1703 } \
1704 }
1705
1706 /* Note: This macro must match the code in thumb_function_prologue(). */
1707 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1708 { \
1709 (OFFSET) = 0; \
1710 if ((FROM) == ARG_POINTER_REGNUM) \
1711 { \
1712 int count_regs = 0; \
1713 int regno; \
1714 for (regno = 8; regno < 13; regno ++) \
1715 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1716 count_regs ++; \
1717 if (count_regs) \
1718 (OFFSET) += 4 * count_regs; \
1719 count_regs = 0; \
1720 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1721 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1722 count_regs ++; \
1723 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1724 (OFFSET) += 4 * (count_regs + 1); \
1725 if (TARGET_BACKTRACE) \
1726 { \
1727 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1728 (OFFSET) += 20; \
1729 else \
1730 (OFFSET) += 16; \
1731 } \
1732 } \
1733 if ((TO) == STACK_POINTER_REGNUM) \
1734 { \
1735 (OFFSET) += current_function_outgoing_args_size; \
1736 (OFFSET) += ROUND_UP (get_frame_size ()); \
1737 } \
1738 }
1739
1740 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1741 if (TARGET_ARM) \
1742 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \
1743 else \
1744 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1745
1746 /* Special case handling of the location of arguments passed on the stack. */
1747 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1748
1749 /* Initialize data used by insn expanders. This is called from insn_emit,
1750 once for every function before code is generated. */
1751 #define INIT_EXPANDERS arm_init_expanders ()
1752
1753 /* Output assembler code for a block containing the constant parts
1754 of a trampoline, leaving space for the variable parts.
1755
1756 On the ARM, (if r8 is the static chain regnum, and remembering that
1757 referencing pc adds an offset of 8) the trampoline looks like:
1758 ldr r8, [pc, #0]
1759 ldr pc, [pc]
1760 .word static chain value
1761 .word function's address
1762 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1763 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1764 { \
1765 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1766 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1767 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1768 PC_REGNUM, PC_REGNUM); \
1769 ASM_OUTPUT_INT (FILE, const0_rtx); \
1770 ASM_OUTPUT_INT (FILE, const0_rtx); \
1771 }
1772
1773 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1774 Why - because it is easier. This code will always be branched to via
1775 a BX instruction and since the compiler magically generates the address
1776 of the function the linker has no opportunity to ensure that the
1777 bottom bit is set. Thus the processor will be in ARM mode when it
1778 reaches this code. So we duplicate the ARM trampoline code and add
1779 a switch into Thumb mode as well. */
1780 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1781 { \
1782 fprintf (FILE, "\t.code 32\n"); \
1783 fprintf (FILE, ".Ltrampoline_start:\n"); \
1784 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1785 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1786 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1787 IP_REGNUM, PC_REGNUM); \
1788 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1789 IP_REGNUM, IP_REGNUM); \
1790 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1791 fprintf (FILE, "\t.word\t0\n"); \
1792 fprintf (FILE, "\t.word\t0\n"); \
1793 fprintf (FILE, "\t.code 16\n"); \
1794 }
1795
1796 #define TRAMPOLINE_TEMPLATE(FILE) \
1797 if (TARGET_ARM) \
1798 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1799 else \
1800 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1801
1802 /* Length in units of the trampoline for entering a nested function. */
1803 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1804
1805 /* Alignment required for a trampoline in units. */
1806 #define TRAMPOLINE_ALIGN 4
1807
1808 /* Emit RTL insns to initialize the variable parts of a trampoline.
1809 FNADDR is an RTX for the address of the function's pure code.
1810 CXT is an RTX for the static chain value for the function. */
1811 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1812 { \
1813 emit_move_insn \
1814 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1815 emit_move_insn \
1816 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1817 }
1818
1819 \f
1820 /* Addressing modes, and classification of registers for them. */
1821 #define HAVE_POST_INCREMENT 1
1822 #define HAVE_PRE_INCREMENT TARGET_ARM
1823 #define HAVE_POST_DECREMENT TARGET_ARM
1824 #define HAVE_PRE_DECREMENT TARGET_ARM
1825
1826 /* Macros to check register numbers against specific register classes. */
1827
1828 /* These assume that REGNO is a hard or pseudo reg number.
1829 They give nonzero only if REGNO is a hard reg of the suitable class
1830 or a pseudo reg currently allocated to a suitable hard reg.
1831 Since they use reg_renumber, they are safe only once reg_renumber
1832 has been allocated, which happens in local-alloc.c. */
1833 #define TEST_REGNO(R, TEST, VALUE) \
1834 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1835
1836 /* On the ARM, don't allow the pc to be used. */
1837 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1838 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1839 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1840 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1841
1842 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1843 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1844 || (GET_MODE_SIZE (MODE) >= 4 \
1845 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1846
1847 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1848 (TARGET_THUMB \
1849 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1850 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1851
1852 /* For ARM code, we don't care about the mode, but for Thumb, the index
1853 must be suitable for use in a QImode load. */
1854 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1855 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1856
1857 /* Maximum number of registers that can appear in a valid memory address.
1858 Shifts in addresses can't be by a register. */
1859 #define MAX_REGS_PER_ADDRESS 2
1860
1861 /* Recognize any constant value that is a valid address. */
1862 /* XXX We can address any constant, eventually... */
1863
1864 #ifdef AOF_ASSEMBLER
1865
1866 #define CONSTANT_ADDRESS_P(X) \
1867 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1868
1869 #else
1870
1871 #define CONSTANT_ADDRESS_P(X) \
1872 (GET_CODE (X) == SYMBOL_REF \
1873 && (CONSTANT_POOL_ADDRESS_P (X) \
1874 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1875
1876 #endif /* AOF_ASSEMBLER */
1877
1878 /* Nonzero if the constant value X is a legitimate general operand.
1879 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1880
1881 On the ARM, allow any integer (invalid ones are removed later by insn
1882 patterns), nice doubles and symbol_refs which refer to the function's
1883 constant pool XXX.
1884
1885 When generating pic allow anything. */
1886 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1887
1888 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1889 ( GET_CODE (X) == CONST_INT \
1890 || GET_CODE (X) == CONST_DOUBLE \
1891 || CONSTANT_ADDRESS_P (X))
1892
1893 #define LEGITIMATE_CONSTANT_P(X) \
1894 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1895
1896 /* Special characters prefixed to function names
1897 in order to encode attribute like information.
1898 Note, '@' and '*' have already been taken. */
1899 #define SHORT_CALL_FLAG_CHAR '^'
1900 #define LONG_CALL_FLAG_CHAR '#'
1901
1902 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1903 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1904
1905 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1906 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1907
1908 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1909 #define SUBTARGET_NAME_ENCODING_LENGTHS
1910 #endif
1911
1912 /* This is a C fragement for the inside of a switch statement.
1913 Each case label should return the number of characters to
1914 be stripped from the start of a function's name, if that
1915 name starts with the indicated character. */
1916 #define ARM_NAME_ENCODING_LENGTHS \
1917 case SHORT_CALL_FLAG_CHAR: return 1; \
1918 case LONG_CALL_FLAG_CHAR: return 1; \
1919 case '*': return 1; \
1920 SUBTARGET_NAME_ENCODING_LENGTHS
1921
1922 /* This has to be handled by a function because more than part of the
1923 ARM backend uses function name prefixes to encode attributes. */
1924 #undef STRIP_NAME_ENCODING
1925 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1926 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1927
1928 /* This is how to output a reference to a user-level label named NAME.
1929 `assemble_name' uses this. */
1930 #undef ASM_OUTPUT_LABELREF
1931 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1932 asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME))
1933
1934 /* If we are referencing a function that is weak then encode a long call
1935 flag in the function name, otherwise if the function is static or
1936 or known to be defined in this file then encode a short call flag.
1937 This macro is used inside the ENCODE_SECTION macro. */
1938 #define ARM_ENCODE_CALL_TYPE(decl) \
1939 if (TREE_CODE (decl) == FUNCTION_DECL) \
1940 { \
1941 if (DECL_WEAK (decl)) \
1942 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1943 else if (! TREE_PUBLIC (decl)) \
1944 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1945 } \
1946
1947 /* Symbols in the text segment can be accessed without indirecting via the
1948 constant pool; it may take an extra binary operation, but this is still
1949 faster than indirecting via memory. Don't do this when not optimizing,
1950 since we won't be calculating al of the offsets necessary to do this
1951 simplification. */
1952 /* This doesn't work with AOF syntax, since the string table may be in
1953 a different AREA. */
1954 #ifndef AOF_ASSEMBLER
1955 #define ENCODE_SECTION_INFO(decl) \
1956 { \
1957 if (optimize > 0 && TREE_CONSTANT (decl) \
1958 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1959 { \
1960 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1961 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1962 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1963 } \
1964 ARM_ENCODE_CALL_TYPE (decl) \
1965 }
1966 #else
1967 #define ENCODE_SECTION_INFO(decl) \
1968 { \
1969 ARM_ENCODE_CALL_TYPE (decl) \
1970 }
1971 #endif
1972
1973 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1974 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1975
1976 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1977 and check its validity for a certain class.
1978 We have two alternate definitions for each of them.
1979 The usual definition accepts all pseudo regs; the other rejects
1980 them unless they have been allocated suitable hard regs.
1981 The symbol REG_OK_STRICT causes the latter definition to be used. */
1982 #ifndef REG_OK_STRICT
1983
1984 #define ARM_REG_OK_FOR_BASE_P(X) \
1985 (REGNO (X) <= LAST_ARM_REGNUM \
1986 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1987 || REGNO (X) == FRAME_POINTER_REGNUM \
1988 || REGNO (X) == ARG_POINTER_REGNUM)
1989
1990 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1991 (REGNO (X) <= LAST_LO_REGNUM \
1992 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1993 || (GET_MODE_SIZE (MODE) >= 4 \
1994 && (REGNO (X) == STACK_POINTER_REGNUM \
1995 || (X) == hard_frame_pointer_rtx \
1996 || (X) == arg_pointer_rtx)))
1997
1998 #else /* REG_OK_STRICT */
1999
2000 #define ARM_REG_OK_FOR_BASE_P(X) \
2001 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2002
2003 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2004 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2005
2006 #endif /* REG_OK_STRICT */
2007
2008 /* Now define some helpers in terms of the above. */
2009
2010 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2011 (TARGET_THUMB \
2012 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2013 : ARM_REG_OK_FOR_BASE_P (X))
2014
2015 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2016
2017 /* For Thumb, a valid index register is anything that can be used in
2018 a byte load instruction. */
2019 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2020
2021 /* Nonzero if X is a hard reg that can be used as an index
2022 or if it is a pseudo reg. On the Thumb, the stack pointer
2023 is not suitable. */
2024 #define REG_OK_FOR_INDEX_P(X) \
2025 (TARGET_THUMB \
2026 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2027 : ARM_REG_OK_FOR_INDEX_P (X))
2028
2029 \f
2030 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2031 that is a valid memory address for an instruction.
2032 The MODE argument is the machine mode for the MEM expression
2033 that wants to use this address.
2034
2035 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
2036
2037 /* --------------------------------arm version----------------------------- */
2038 #define ARM_BASE_REGISTER_RTX_P(X) \
2039 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2040
2041 #define ARM_INDEX_REGISTER_RTX_P(X) \
2042 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2043
2044 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2045 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2046 only be small constants. */
2047 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2048 do \
2049 { \
2050 HOST_WIDE_INT range; \
2051 enum rtx_code code = GET_CODE (INDEX); \
2052 \
2053 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2054 { \
2055 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2056 && INTVAL (INDEX) > -1024 \
2057 && (INTVAL (INDEX) & 3) == 0) \
2058 goto LABEL; \
2059 } \
2060 else \
2061 { \
2062 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2063 && GET_MODE_SIZE (MODE) <= 4) \
2064 goto LABEL; \
2065 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2066 && (! arm_arch4 || (MODE) != HImode)) \
2067 { \
2068 rtx xiop0 = XEXP (INDEX, 0); \
2069 rtx xiop1 = XEXP (INDEX, 1); \
2070 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2071 && power_of_two_operand (xiop1, SImode)) \
2072 goto LABEL; \
2073 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2074 && power_of_two_operand (xiop0, SImode)) \
2075 goto LABEL; \
2076 } \
2077 if (GET_MODE_SIZE (MODE) <= 4 \
2078 && (code == LSHIFTRT || code == ASHIFTRT \
2079 || code == ASHIFT || code == ROTATERT) \
2080 && (! arm_arch4 || (MODE) != HImode)) \
2081 { \
2082 rtx op = XEXP (INDEX, 1); \
2083 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2084 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2085 && INTVAL (op) <= 31) \
2086 goto LABEL; \
2087 } \
2088 /* NASTY: Since this limits the addressing of unsigned \
2089 byte loads. */ \
2090 range = ((MODE) == HImode || (MODE) == QImode) \
2091 ? (arm_arch4 ? 256 : 4095) : 4096; \
2092 if (code == CONST_INT && INTVAL (INDEX) < range \
2093 && INTVAL (INDEX) > -range) \
2094 goto LABEL; \
2095 } \
2096 } \
2097 while (0)
2098
2099 /* Jump to LABEL if X is a valid address RTX. This must take
2100 REG_OK_STRICT into account when deciding about valid registers.
2101
2102 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2103 floating SYMBOL_REF to the constant pool. Allow REG-only and
2104 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2105 forced though a static cell to ensure addressability. */
2106 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2107 { \
2108 if (ARM_BASE_REGISTER_RTX_P (X)) \
2109 goto LABEL; \
2110 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2111 && GET_CODE (XEXP (X, 0)) == REG \
2112 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2113 goto LABEL; \
2114 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2115 && (GET_CODE (X) == LABEL_REF \
2116 || (GET_CODE (X) == CONST \
2117 && GET_CODE (XEXP ((X), 0)) == PLUS \
2118 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2119 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2120 goto LABEL; \
2121 else if ((MODE) == TImode) \
2122 ; \
2123 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2124 { \
2125 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2126 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2127 { \
2128 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2129 if (val == 4 || val == -4 || val == -8) \
2130 goto LABEL; \
2131 } \
2132 } \
2133 else if (GET_CODE (X) == PLUS) \
2134 { \
2135 rtx xop0 = XEXP (X, 0); \
2136 rtx xop1 = XEXP (X, 1); \
2137 \
2138 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2139 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2140 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2141 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2142 } \
2143 /* Reload currently can't handle MINUS, so disable this for now */ \
2144 /* else if (GET_CODE (X) == MINUS) \
2145 { \
2146 rtx xop0 = XEXP (X,0); \
2147 rtx xop1 = XEXP (X,1); \
2148 \
2149 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2150 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2151 } */ \
2152 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2153 && GET_CODE (X) == SYMBOL_REF \
2154 && CONSTANT_POOL_ADDRESS_P (X) \
2155 && ! (flag_pic \
2156 && symbol_mentioned_p (get_pool_constant (X)))) \
2157 goto LABEL; \
2158 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2159 && (GET_MODE_SIZE (MODE) <= 4) \
2160 && GET_CODE (XEXP (X, 0)) == REG \
2161 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2162 goto LABEL; \
2163 }
2164
2165 /* ---------------------thumb version----------------------------------*/
2166 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2167 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2168 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2169 && ((VAL) & 1) == 0) \
2170 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2171 && ((VAL) & 3) == 0))
2172
2173 /* The AP may be eliminated to either the SP or the FP, so we use the
2174 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2175
2176 /* ??? Verify whether the above is the right approach. */
2177
2178 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2179 needs special handling also. */
2180
2181 /* ??? Look at how the mips16 port solves this problem. It probably uses
2182 better ways to solve some of these problems. */
2183
2184 /* Although it is not incorrect, we don't accept QImode and HImode
2185 addresses based on the frame pointer or arg pointer until the
2186 reload pass starts. This is so that eliminating such addresses
2187 into stack based ones won't produce impossible code. */
2188 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2189 { \
2190 /* ??? Not clear if this is right. Experiment. */ \
2191 if (GET_MODE_SIZE (MODE) < 4 \
2192 && ! (reload_in_progress || reload_completed) \
2193 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2194 || reg_mentioned_p (arg_pointer_rtx, X) \
2195 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2196 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2197 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2198 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2199 ; \
2200 /* Accept any base register. SP only in SImode or larger. */ \
2201 else if (GET_CODE (X) == REG \
2202 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2203 goto WIN; \
2204 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2205 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2206 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2207 goto WIN; \
2208 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2209 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2210 && (GET_CODE (X) == LABEL_REF \
2211 || (GET_CODE (X) == CONST \
2212 && GET_CODE (XEXP (X, 0)) == PLUS \
2213 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2214 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2215 goto WIN; \
2216 /* Post-inc indexing only supported for SImode and larger. */ \
2217 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2218 && GET_CODE (XEXP (X, 0)) == REG \
2219 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2220 goto WIN; \
2221 else if (GET_CODE (X) == PLUS) \
2222 { \
2223 /* REG+REG address can be any two index registers. */ \
2224 /* We disallow FRAME+REG addressing since we know that FRAME \
2225 will be replaced with STACK, and SP relative addressing only \
2226 permits SP+OFFSET. */ \
2227 if (GET_MODE_SIZE (MODE) <= 4 \
2228 && GET_CODE (XEXP (X, 0)) == REG \
2229 && GET_CODE (XEXP (X, 1)) == REG \
2230 && XEXP (X, 0) != frame_pointer_rtx \
2231 && XEXP (X, 1) != frame_pointer_rtx \
2232 && XEXP (X, 0) != virtual_stack_vars_rtx \
2233 && XEXP (X, 1) != virtual_stack_vars_rtx \
2234 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2235 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2236 goto WIN; \
2237 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2238 else if (GET_CODE (XEXP (X, 0)) == REG \
2239 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2240 || XEXP (X, 0) == arg_pointer_rtx) \
2241 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2242 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2243 goto WIN; \
2244 /* REG+const has 10 bit offset for SP, but only SImode and \
2245 larger is supported. */ \
2246 /* ??? Should probably check for DI/DFmode overflow here \
2247 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2248 else if (GET_CODE (XEXP (X, 0)) == REG \
2249 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2250 && GET_MODE_SIZE (MODE) >= 4 \
2251 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2252 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2253 + GET_MODE_SIZE (MODE)) <= 1024 \
2254 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2255 goto WIN; \
2256 else if (GET_CODE (XEXP (X, 0)) == REG \
2257 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2258 && GET_MODE_SIZE (MODE) >= 4 \
2259 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2260 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2261 goto WIN; \
2262 } \
2263 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2264 && GET_CODE (X) == SYMBOL_REF \
2265 && CONSTANT_POOL_ADDRESS_P (X) \
2266 && ! (flag_pic \
2267 && symbol_mentioned_p (get_pool_constant (X)))) \
2268 goto WIN; \
2269 }
2270
2271 /* ------------------------------------------------------------------- */
2272 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2273 if (TARGET_ARM) \
2274 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2275 else /* if (TARGET_THUMB) */ \
2276 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2277 /* ------------------------------------------------------------------- */
2278 \f
2279 /* Try machine-dependent ways of modifying an illegitimate address
2280 to be legitimate. If we find one, return the new, valid address.
2281 This macro is used in only one place: `memory_address' in explow.c.
2282
2283 OLDX is the address as it was before break_out_memory_refs was called.
2284 In some cases it is useful to look at this to decide what needs to be done.
2285
2286 MODE and WIN are passed so that this macro can use
2287 GO_IF_LEGITIMATE_ADDRESS.
2288
2289 It is always safe for this macro to do nothing. It exists to recognize
2290 opportunities to optimize the output.
2291
2292 On the ARM, try to convert [REG, #BIGCONST]
2293 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2294 where VALIDCONST == 0 in case of TImode. */
2295 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2296 { \
2297 if (GET_CODE (X) == PLUS) \
2298 { \
2299 rtx xop0 = XEXP (X, 0); \
2300 rtx xop1 = XEXP (X, 1); \
2301 \
2302 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2303 xop0 = force_reg (SImode, xop0); \
2304 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2305 xop1 = force_reg (SImode, xop1); \
2306 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2307 && GET_CODE (xop1) == CONST_INT) \
2308 { \
2309 HOST_WIDE_INT n, low_n; \
2310 rtx base_reg, val; \
2311 n = INTVAL (xop1); \
2312 \
2313 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2314 { \
2315 low_n = n & 0x0f; \
2316 n &= ~0x0f; \
2317 if (low_n > 4) \
2318 { \
2319 n += 16; \
2320 low_n -= 16; \
2321 } \
2322 } \
2323 else \
2324 { \
2325 low_n = ((MODE) == TImode ? 0 \
2326 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2327 n -= low_n; \
2328 } \
2329 base_reg = gen_reg_rtx (SImode); \
2330 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2331 GEN_INT (n)), NULL_RTX); \
2332 emit_move_insn (base_reg, val); \
2333 (X) = (low_n == 0 ? base_reg \
2334 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2335 } \
2336 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2337 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2338 } \
2339 else if (GET_CODE (X) == MINUS) \
2340 { \
2341 rtx xop0 = XEXP (X, 0); \
2342 rtx xop1 = XEXP (X, 1); \
2343 \
2344 if (CONSTANT_P (xop0)) \
2345 xop0 = force_reg (SImode, xop0); \
2346 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2347 xop1 = force_reg (SImode, xop1); \
2348 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2349 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2350 } \
2351 if (flag_pic) \
2352 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2353 if (memory_address_p (MODE, X)) \
2354 goto WIN; \
2355 }
2356
2357 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2358 if (flag_pic) \
2359 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2360
2361 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2362 if (TARGET_ARM) \
2363 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2364 else \
2365 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2366
2367 /* Go to LABEL if ADDR (a legitimate address expression)
2368 has an effect that depends on the machine mode it is used for. */
2369 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2370 { \
2371 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2372 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2373 goto LABEL; \
2374 }
2375
2376 /* Nothing helpful to do for the Thumb */
2377 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2378 if (TARGET_ARM) \
2379 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2380 \f
2381
2382 /* Specify the machine mode that this machine uses
2383 for the index in the tablejump instruction. */
2384 #define CASE_VECTOR_MODE Pmode
2385
2386 /* Define as C expression which evaluates to nonzero if the tablejump
2387 instruction expects the table to contain offsets from the address of the
2388 table.
2389 Do not define this if the table should contain absolute addresses. */
2390 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2391
2392 /* Specify the tree operation to be used to convert reals to integers. */
2393 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2394
2395 /* This is the kind of divide that is easiest to do in the general case. */
2396 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2397
2398 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2399 unsigned is probably best, but may break some code. */
2400 #ifndef DEFAULT_SIGNED_CHAR
2401 #define DEFAULT_SIGNED_CHAR 0
2402 #endif
2403
2404 /* Don't cse the address of the function being compiled. */
2405 #define NO_RECURSIVE_FUNCTION_CSE 1
2406
2407 /* Max number of bytes we can move from memory to memory
2408 in one reasonably fast instruction. */
2409 #define MOVE_MAX 4
2410
2411 #undef MOVE_RATIO
2412 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2413
2414 /* Define if operations between registers always perform the operation
2415 on the full register even if a narrower mode is specified. */
2416 #define WORD_REGISTER_OPERATIONS
2417
2418 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2419 will either zero-extend or sign-extend. The value of this macro should
2420 be the code that says which one of the two operations is implicitly
2421 done, NIL if none. */
2422 #define LOAD_EXTEND_OP(MODE) \
2423 (TARGET_THUMB ? ZERO_EXTEND : \
2424 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2425 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2426
2427 /* Define this if zero-extension is slow (more than one real instruction).
2428 On the ARM, it is more than one instruction only if not fetching from
2429 memory. */
2430 /* #define SLOW_ZERO_EXTEND */
2431
2432 /* Nonzero if access to memory by bytes is slow and undesirable. */
2433 #define SLOW_BYTE_ACCESS 0
2434
2435 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2436
2437 /* Immediate shift counts are truncated by the output routines (or was it
2438 the assembler?). Shift counts in a register are truncated by ARM. Note
2439 that the native compiler puts too large (> 32) immediate shift counts
2440 into a register and shifts by the register, letting the ARM decide what
2441 to do instead of doing that itself. */
2442 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2443 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2444 On the arm, Y in a register is used modulo 256 for the shift. Only for
2445 rotates is modulo 32 used. */
2446 /* #define SHIFT_COUNT_TRUNCATED 1 */
2447
2448 /* All integers have the same format so truncation is easy. */
2449 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2450
2451 /* Calling from registers is a massive pain. */
2452 #define NO_FUNCTION_CSE 1
2453
2454 /* Chars and shorts should be passed as ints. */
2455 #define PROMOTE_PROTOTYPES 1
2456
2457 /* The machine modes of pointers and functions */
2458 #define Pmode SImode
2459 #define FUNCTION_MODE Pmode
2460
2461 #define ARM_FRAME_RTX(X) \
2462 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2463 || (X) == arg_pointer_rtx)
2464
2465 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2466 return arm_rtx_costs (X, CODE, OUTER_CODE);
2467
2468 /* Moves to and from memory are quite expensive */
2469 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2470 (TARGET_ARM ? 10 : \
2471 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2472 * (CLASS == LO_REGS ? 1 : 2)))
2473
2474 /* All address computations that can be done are free, but rtx cost returns
2475 the same for practically all of them. So we weight the different types
2476 of address here in the order (most pref first):
2477 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2478 #define ARM_ADDRESS_COST(X) \
2479 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2480 || GET_CODE (X) == SYMBOL_REF) \
2481 ? 0 \
2482 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2483 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2484 ? 10 \
2485 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2486 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2487 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2488 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2489 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2490 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2491 ? 1 : 0)) \
2492 : 4)))))
2493
2494 #define THUMB_ADDRESS_COST(X) \
2495 ((GET_CODE (X) == REG \
2496 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2497 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2498 ? 1 : 2)
2499
2500 #define ADDRESS_COST(X) \
2501 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2502
2503 /* Try to generate sequences that don't involve branches, we can then use
2504 conditional instructions */
2505 #define BRANCH_COST \
2506 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2507
2508 /* A C statement to update the variable COST based on the relationship
2509 between INSN that is dependent on DEP through dependence LINK. */
2510 #define ADJUST_COST(INSN, LINK, DEP, COST) \
2511 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
2512 \f
2513 /* Position Independent Code. */
2514 /* We decide which register to use based on the compilation options and
2515 the assembler in use; this is more general than the APCS restriction of
2516 using sb (r9) all the time. */
2517 extern int arm_pic_register;
2518
2519 /* Used when parsing command line option -mpic-register=. */
2520 extern const char * arm_pic_register_string;
2521
2522 /* The register number of the register used to address a table of static
2523 data addresses in memory. */
2524 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2525
2526 #define FINALIZE_PIC arm_finalize_pic (1)
2527
2528 /* We can't directly access anything that contains a symbol,
2529 nor can we indirect via the constant pool. */
2530 #define LEGITIMATE_PIC_OPERAND_P(X) \
2531 ( ! symbol_mentioned_p (X) \
2532 && ! label_mentioned_p (X) \
2533 && (! CONSTANT_POOL_ADDRESS_P (X) \
2534 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2535 && ! label_mentioned_p (get_pool_constant (X)))))
2536
2537 /* We need to know when we are making a constant pool; this determines
2538 whether data needs to be in the GOT or can be referenced via a GOT
2539 offset. */
2540 extern int making_const_table;
2541 \f
2542 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2543 with arguments ARGS is a valid machine specific attribute for TYPE.
2544 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2545 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2546 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2547
2548 /* If defined, a C expression whose value is zero if the attributes on
2549 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2550 two if they are nearly compatible (which causes a warning to be
2551 generated). */
2552 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2553 (arm_comp_type_attributes (TYPE1, TYPE2))
2554
2555 /* If defined, a C statement that assigns default attributes to newly
2556 defined TYPE. */
2557 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
2558 arm_set_default_type_attributes (TYPE)
2559
2560 /* Handle pragmas for compatibility with Intel's compilers. */
2561 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2562 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2563 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2564 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2565 } while (0)
2566
2567 /* Condition code information. */
2568 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2569 return the mode to be used for the comparison.
2570 CCFPEmode should be used with floating inequalities,
2571 CCFPmode should be used with floating equalities.
2572 CC_NOOVmode should be used with SImode integer equalities.
2573 CC_Zmode should be used if only the Z flag is set correctly
2574 CCmode should be used otherwise. */
2575
2576 #define EXTRA_CC_MODES \
2577 CC(CC_NOOVmode, "CC_NOOV") \
2578 CC(CC_Zmode, "CC_Z") \
2579 CC(CC_SWPmode, "CC_SWP") \
2580 CC(CCFPmode, "CCFP") \
2581 CC(CCFPEmode, "CCFPE") \
2582 CC(CC_DNEmode, "CC_DNE") \
2583 CC(CC_DEQmode, "CC_DEQ") \
2584 CC(CC_DLEmode, "CC_DLE") \
2585 CC(CC_DLTmode, "CC_DLT") \
2586 CC(CC_DGEmode, "CC_DGE") \
2587 CC(CC_DGTmode, "CC_DGT") \
2588 CC(CC_DLEUmode, "CC_DLEU") \
2589 CC(CC_DLTUmode, "CC_DLTU") \
2590 CC(CC_DGEUmode, "CC_DGEU") \
2591 CC(CC_DGTUmode, "CC_DGTU") \
2592 CC(CC_Cmode, "CC_C")
2593
2594 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2595
2596 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2597
2598 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2599 do \
2600 { \
2601 if (GET_CODE (OP1) == CONST_INT \
2602 && ! (const_ok_for_arm (INTVAL (OP1)) \
2603 || (const_ok_for_arm (- INTVAL (OP1))))) \
2604 { \
2605 rtx const_op = OP1; \
2606 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2607 OP1 = const_op; \
2608 } \
2609 } \
2610 while (0)
2611
2612 #define STORE_FLAG_VALUE 1
2613
2614 \f
2615
2616 /* Gcc puts the pool in the wrong place for ARM, since we can only
2617 load addresses a limited distance around the pc. We do some
2618 special munging to move the constant pool values to the correct
2619 point in the code. */
2620 #define MACHINE_DEPENDENT_REORG(INSN) \
2621 arm_reorg (INSN); \
2622
2623 #undef ASM_APP_OFF
2624 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2625
2626 /* Output an internal label definition. */
2627 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2628 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2629 do \
2630 { \
2631 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2632 \
2633 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2634 && !strcmp (PREFIX, "L")) \
2635 { \
2636 arm_ccfsm_state = 0; \
2637 arm_target_insn = NULL; \
2638 } \
2639 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2640 ASM_OUTPUT_LABEL (STREAM, s); \
2641 } \
2642 while (0)
2643 #endif
2644
2645 /* Output a push or a pop instruction (only used when profiling). */
2646 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2647 if (TARGET_ARM) \
2648 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2649 STACK_POINTER_REGNUM, REGNO); \
2650 else \
2651 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2652
2653
2654 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2655 if (TARGET_ARM) \
2656 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2657 STACK_POINTER_REGNUM, REGNO); \
2658 else \
2659 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2660
2661 /* This is how to output a label which precedes a jumptable. Since
2662 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2663 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2664 do \
2665 { \
2666 if (TARGET_THUMB) \
2667 ASM_OUTPUT_ALIGN (FILE, 2); \
2668 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2669 } \
2670 while (0)
2671
2672 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2673 do \
2674 { \
2675 if (TARGET_THUMB) \
2676 { \
2677 if (is_called_in_ARM_mode (DECL)) \
2678 fprintf (STREAM, "\t.code 32\n") ; \
2679 else \
2680 fprintf (STREAM, "\t.thumb_func\n") ; \
2681 } \
2682 if (TARGET_POKE_FUNCTION_NAME) \
2683 arm_poke_function_name (STREAM, (char *) NAME); \
2684 } \
2685 while (0)
2686
2687 /* For aliases of functions we use .thumb_set instead. */
2688 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2689 do \
2690 { \
2691 char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2692 char * LABEL2 = IDENTIFIER_POINTER (DECL2); \
2693 \
2694 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2695 { \
2696 fprintf (FILE, "\t.thumb_set "); \
2697 assemble_name (FILE, LABEL1); \
2698 fprintf (FILE, ","); \
2699 assemble_name (FILE, LABEL2); \
2700 fprintf (FILE, "\n"); \
2701 } \
2702 else \
2703 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2704 } \
2705 while (0)
2706
2707 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2708 /* To support -falign-* switches we need to use .p2align so
2709 that alignment directives in code sections will be padded
2710 with no-op instructions, rather than zeroes. */
2711 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2712 if ((LOG) != 0) \
2713 { \
2714 if ((MAX_SKIP) == 0) \
2715 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2716 else \
2717 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2718 (LOG), (MAX_SKIP)); \
2719 }
2720 #endif
2721
2722 /* Target characters. */
2723 #define TARGET_BELL 007
2724 #define TARGET_BS 010
2725 #define TARGET_TAB 011
2726 #define TARGET_NEWLINE 012
2727 #define TARGET_VT 013
2728 #define TARGET_FF 014
2729 #define TARGET_CR 015
2730 \f
2731 /* Only perform branch elimination (by making instructions conditional) if
2732 we're optimising. Otherwise it's of no use anyway. */
2733 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2734 if (TARGET_ARM && optimize) \
2735 arm_final_prescan_insn (INSN); \
2736 else if (TARGET_THUMB) \
2737 thumb_final_prescan_insn (INSN)
2738
2739 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2740 (CODE == '@' || CODE == '|' \
2741 || (TARGET_ARM && (CODE == '?')) \
2742 || (TARGET_THUMB && (CODE == '_')))
2743
2744 /* Output an operand of an instruction. */
2745 #define PRINT_OPERAND(STREAM, X, CODE) \
2746 arm_print_operand (STREAM, X, CODE)
2747
2748 /* Create an [unsigned] host sized integer declaration that
2749 avoids compiler warnings. */
2750 #ifdef __STDC__
2751 #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL)
2752 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL)
2753 #else
2754 #define HOST_INT(x) ((HOST_WIDE_INT) x)
2755 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x)
2756 #endif
2757
2758 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2759 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2760 : (((x) & HOST_UINT (0xffffffff)) | \
2761 (((x) & HOST_UINT (0x80000000)) \
2762 ? ((~ HOST_INT (0)) \
2763 & ~ HOST_UINT(0xffffffff)) \
2764 : 0))))
2765
2766 /* Output the address of an operand. */
2767 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2768 { \
2769 int is_minus = GET_CODE (X) == MINUS; \
2770 \
2771 if (GET_CODE (X) == REG) \
2772 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2773 else if (GET_CODE (X) == PLUS || is_minus) \
2774 { \
2775 rtx base = XEXP (X, 0); \
2776 rtx index = XEXP (X, 1); \
2777 HOST_WIDE_INT offset = 0; \
2778 if (GET_CODE (base) != REG) \
2779 { \
2780 /* Ensure that BASE is a register */ \
2781 /* (one of them must be). */ \
2782 rtx temp = base; \
2783 base = index; \
2784 index = temp; \
2785 } \
2786 switch (GET_CODE (index)) \
2787 { \
2788 case CONST_INT: \
2789 offset = INTVAL (index); \
2790 if (is_minus) \
2791 offset = -offset; \
2792 asm_fprintf (STREAM, "[%r, #%d]", \
2793 REGNO (base), offset); \
2794 break; \
2795 \
2796 case REG: \
2797 asm_fprintf (STREAM, "[%r, %s%r]", \
2798 REGNO (base), is_minus ? "-" : "", \
2799 REGNO (index)); \
2800 break; \
2801 \
2802 case MULT: \
2803 case ASHIFTRT: \
2804 case LSHIFTRT: \
2805 case ASHIFT: \
2806 case ROTATERT: \
2807 { \
2808 asm_fprintf (STREAM, "[%r, %s%r", \
2809 REGNO (base), is_minus ? "-" : "", \
2810 REGNO (XEXP (index, 0))); \
2811 arm_print_operand (STREAM, index, 'S'); \
2812 fputs ("]", STREAM); \
2813 break; \
2814 } \
2815 \
2816 default: \
2817 abort(); \
2818 } \
2819 } \
2820 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2821 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2822 { \
2823 extern int output_memory_reference_mode; \
2824 \
2825 if (GET_CODE (XEXP (X, 0)) != REG) \
2826 abort (); \
2827 \
2828 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2829 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2830 REGNO (XEXP (X, 0)), \
2831 GET_CODE (X) == PRE_DEC ? "-" : "", \
2832 GET_MODE_SIZE (output_memory_reference_mode));\
2833 else \
2834 asm_fprintf (STREAM, "[%r], #%s%d", \
2835 REGNO (XEXP (X, 0)), \
2836 GET_CODE (X) == POST_DEC ? "-" : "", \
2837 GET_MODE_SIZE (output_memory_reference_mode));\
2838 } \
2839 else output_addr_const (STREAM, X); \
2840 }
2841
2842 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2843 { \
2844 if (GET_CODE (X) == REG) \
2845 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2846 else if (GET_CODE (X) == POST_INC) \
2847 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2848 else if (GET_CODE (X) == PLUS) \
2849 { \
2850 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2851 asm_fprintf (STREAM, "[%r, #%d]", \
2852 REGNO (XEXP (X, 0)), \
2853 (int) INTVAL (XEXP (X, 1))); \
2854 else \
2855 asm_fprintf (STREAM, "[%r, %r]", \
2856 REGNO (XEXP (X, 0)), \
2857 REGNO (XEXP (X, 1))); \
2858 } \
2859 else \
2860 output_addr_const (STREAM, X); \
2861 }
2862
2863 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2864 if (TARGET_ARM) \
2865 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2866 else \
2867 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2868
2869 #define OUTPUT_INT_ADDR_CONST(STREAM, X) \
2870 { \
2871 output_addr_const (STREAM, X); \
2872 \
2873 /* Mark symbols as position independent. We only do this in the \
2874 .text segment, not in the .data segment. */ \
2875 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2876 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2877 { \
2878 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2879 fprintf (STREAM, "(GOTOFF)"); \
2880 else if (GET_CODE (X) == LABEL_REF) \
2881 fprintf (STREAM, "(GOTOFF)"); \
2882 else \
2883 fprintf (STREAM, "(GOT)"); \
2884 } \
2885 }
2886
2887 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2888 Used for C++ multiple inheritance. */
2889 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2890 do \
2891 { \
2892 int mi_delta = (DELTA); \
2893 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2894 int shift = 0; \
2895 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2896 ? 1 : 0); \
2897 if (mi_delta < 0) \
2898 mi_delta = - mi_delta; \
2899 while (mi_delta != 0) \
2900 { \
2901 if ((mi_delta & (3 << shift)) == 0) \
2902 shift += 2; \
2903 else \
2904 { \
2905 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2906 mi_op, this_regno, this_regno, \
2907 mi_delta & (0xff << shift)); \
2908 mi_delta &= ~(0xff << shift); \
2909 shift += 8; \
2910 } \
2911 } \
2912 fputs ("\tb\t", FILE); \
2913 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2914 if (NEED_PLT_RELOC) \
2915 fputs ("(PLT)", FILE); \
2916 fputc ('\n', FILE); \
2917 } \
2918 while (0)
2919
2920 /* A C expression whose value is RTL representing the value of the return
2921 address for the frame COUNT steps up from the current frame. */
2922
2923 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2924 arm_return_addr (COUNT, FRAME)
2925
2926 /* Mask of the bits in the PC that contain the real return address
2927 when running in 26-bit mode. */
2928 #define RETURN_ADDR_MASK26 (0x03fffffc)
2929
2930 /* Pick up the return address upon entry to a procedure. Used for
2931 dwarf2 unwind information. This also enables the table driven
2932 mechanism. */
2933 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2934 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2935
2936 /* Used to mask out junk bits from the return address, such as
2937 processor state, interrupt status, condition codes and the like. */
2938 #define MASK_RETURN_ADDR \
2939 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2940 in 26 bit mode, the condition codes must be masked out of the \
2941 return address. This does not apply to ARM6 and later processors \
2942 when running in 32 bit mode. */ \
2943 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2944 : (GEN_INT ((unsigned long)0xffffffff)))
2945
2946 \f
2947 /* Define the codes that are matched by predicates in arm.c */
2948 #define PREDICATE_CODES \
2949 {"s_register_operand", {SUBREG, REG}}, \
2950 {"arm_hard_register_operand", {REG}}, \
2951 {"f_register_operand", {SUBREG, REG}}, \
2952 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2953 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2954 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2955 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2956 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2957 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2958 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2959 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2960 {"offsettable_memory_operand", {MEM}}, \
2961 {"bad_signed_byte_operand", {MEM}}, \
2962 {"alignable_memory_operand", {MEM}}, \
2963 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2964 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2965 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2966 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2967 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2968 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2969 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2970 {"load_multiple_operation", {PARALLEL}}, \
2971 {"store_multiple_operation", {PARALLEL}}, \
2972 {"equality_operator", {EQ, NE}}, \
2973 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2974 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2975 UNGE, UNGT}}, \
2976 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2977 {"const_shift_operand", {CONST_INT}}, \
2978 {"multi_register_push", {PARALLEL}}, \
2979 {"cc_register", {REG}}, \
2980 {"logical_binary_operator", {AND, IOR, XOR}}, \
2981 {"dominant_cc_register", {REG}},
2982
2983 /* Define this if you have special predicates that know special things
2984 about modes. Genrecog will warn about certain forms of
2985 match_operand without a mode; if the operand predicate is listed in
2986 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2987 #define SPECIAL_MODE_PREDICATES \
2988 "cc_register", "dominant_cc_register",
2989
2990 enum arm_builtins
2991 {
2992 ARM_BUILTIN_CLZ,
2993 ARM_BUILTIN_PREFETCH,
2994 ARM_BUILTIN_MAX
2995 };
2996
2997 #define MD_INIT_BUILTINS \
2998 do \
2999 { \
3000 arm_init_builtins (); \
3001 } \
3002 while (0)
3003
3004 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
3005 arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
3006 #endif /* __ARM_H__ */
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