?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* config.gcc: Add support for arm926ejs, arm1026ejs, arm1136js,
[official-gcc.git] / gcc / config / arm / arm.c
blob42f4f172ffa68276740c6e9d21ce2f399fd7defe
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "rtl.h"
30 #include "tree.h"
31 #include "obstack.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "output.h"
38 #include "insn-attr.h"
39 #include "flags.h"
40 #include "reload.h"
41 #include "function.h"
42 #include "expr.h"
43 #include "optabs.h"
44 #include "toplev.h"
45 #include "recog.h"
46 #include "ggc.h"
47 #include "except.h"
48 #include "c-pragma.h"
49 #include "integrate.h"
50 #include "tm_p.h"
51 #include "target.h"
52 #include "target-def.h"
53
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode;
56 typedef struct minipool_fixup Mfix;
57
58 const struct attribute_spec arm_attribute_table[];
59
60 /* Forward function declarations. */
61 static void arm_add_gc_roots (void);
62 static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT,
63 rtx, rtx, int, int);
64 static unsigned bit_count (unsigned long);
65 static int arm_address_register_rtx_p (rtx, int);
66 static int arm_legitimate_index_p (enum machine_mode, rtx, int);
67 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
68 inline static int thumb_index_register_rtx_p (rtx, int);
69 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
70 static rtx emit_multi_reg_push (int);
71 static rtx emit_sfm (int, int);
72 #ifndef AOF_ASSEMBLER
73 static bool arm_assemble_integer (rtx, unsigned int, int);
74 #endif
75 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
76 static arm_cc get_arm_condition_code (rtx);
77 static void init_fpa_table (void);
78 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
79 static rtx is_jump_table (rtx);
80 static const char *output_multi_immediate (rtx *, const char *, const char *,
81 int, HOST_WIDE_INT);
82 static void print_multi_reg (FILE *, const char *, int, int);
83 static const char *shift_op (rtx, HOST_WIDE_INT *);
84 static struct machine_function *arm_init_machine_status (void);
85 static int number_of_first_bit_set (int);
86 static void replace_symbols_in_block (tree, rtx, rtx);
87 static void thumb_exit (FILE *, int, rtx);
88 static void thumb_pushpop (FILE *, int, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
102 rtx);
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
113 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
114 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static int arm_comp_type_attributes (tree, tree);
116 static void arm_set_default_type_attributes (tree);
117 static int arm_adjust_cost (rtx, rtx, rtx, int);
118 static int arm_use_dfa_pipeline_interface (void);
119 static int count_insns_for_constant (HOST_WIDE_INT, int);
120 static int arm_get_strip_length (int);
121 static bool arm_function_ok_for_sibcall (tree, tree);
122 static void arm_internal_label (FILE *, const char *, unsigned long);
123 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
124 tree);
125 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
126 static bool arm_rtx_costs (rtx, int, int, int *);
127 static int arm_address_cost (rtx);
128 static bool arm_memory_load_p (rtx);
129 static bool arm_cirrus_insn_p (rtx);
130 static void cirrus_reorg (rtx);
131 static void arm_init_builtins (void);
132 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
133 static void arm_init_iwmmxt_builtins (void);
134 static rtx safe_vector_operand (rtx, enum machine_mode);
135 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
136 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
138
139 #ifdef OBJECT_FORMAT_ELF
140 static void arm_elf_asm_named_section (const char *, unsigned int);
141 #endif
142 #ifndef ARM_PE
143 static void arm_encode_section_info (tree, rtx, int);
144 #endif
145 #ifdef AOF_ASSEMBLER
146 static void aof_globalize_label (FILE *, const char *);
147 static void aof_dump_imports (FILE *);
148 static void aof_dump_pic_table (FILE *);
149 static void aof_file_start (void);
150 static void aof_file_end (void);
151 #endif
152
153 \f
154 /* Initialize the GCC target structure. */
155 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
156 #undef TARGET_MERGE_DECL_ATTRIBUTES
157 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
158 #endif
159
160 #undef TARGET_ATTRIBUTE_TABLE
161 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
162
163 #ifdef AOF_ASSEMBLER
164 #undef TARGET_ASM_BYTE_OP
165 #define TARGET_ASM_BYTE_OP "\tDCB\t"
166 #undef TARGET_ASM_ALIGNED_HI_OP
167 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
170 #undef TARGET_ASM_GLOBALIZE_LABEL
171 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
172 #undef TARGET_ASM_FILE_START
173 #define TARGET_ASM_FILE_START aof_file_start
174 #undef TARGET_ASM_FILE_END
175 #define TARGET_ASM_FILE_END aof_file_end
176 #else
177 #undef TARGET_ASM_ALIGNED_SI_OP
178 #define TARGET_ASM_ALIGNED_SI_OP NULL
179 #undef TARGET_ASM_INTEGER
180 #define TARGET_ASM_INTEGER arm_assemble_integer
181 #endif
182
183 #undef TARGET_ASM_FUNCTION_PROLOGUE
184 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
185
186 #undef TARGET_ASM_FUNCTION_EPILOGUE
187 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
188
189 #undef TARGET_COMP_TYPE_ATTRIBUTES
190 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
191
192 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
193 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
194
195 #undef TARGET_SCHED_ADJUST_COST
196 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
197
198 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
199 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
200
201 #undef TARGET_ENCODE_SECTION_INFO
202 #ifdef ARM_PE
203 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
204 #else
205 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
206 #endif
207
208 #undef TARGET_STRIP_NAME_ENCODING
209 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
210
211 #undef TARGET_ASM_INTERNAL_LABEL
212 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
213
214 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
215 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
216
217 #undef TARGET_ASM_OUTPUT_MI_THUNK
218 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
219 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
220 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
221
222 #undef TARGET_RTX_COSTS
223 #define TARGET_RTX_COSTS arm_rtx_costs
224 #undef TARGET_ADDRESS_COST
225 #define TARGET_ADDRESS_COST arm_address_cost
226
227 #undef TARGET_MACHINE_DEPENDENT_REORG
228 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
229
230 #undef TARGET_INIT_BUILTINS
231 #define TARGET_INIT_BUILTINS arm_init_builtins
232 #undef TARGET_EXPAND_BUILTIN
233 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
234
235 struct gcc_target targetm = TARGET_INITIALIZER;
236 \f
237 /* Obstack for minipool constant handling. */
238 static struct obstack minipool_obstack;
239 static char * minipool_startobj;
240
241 /* The maximum number of insns skipped which
242 will be conditionalised if possible. */
243 static int max_insns_skipped = 5;
244
245 extern FILE * asm_out_file;
246
247 /* True if we are currently building a constant table. */
248 int making_const_table;
249
250 /* Define the information needed to generate branch insns. This is
251 stored from the compare operation. */
252 rtx arm_compare_op0, arm_compare_op1;
253
254 /* What type of floating point are we tuning for? */
255 enum fputype arm_fpu_tune;
256
257 /* What type of floating point instructions are available? */
258 enum fputype arm_fpu_arch;
259
260 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
261 enum prog_mode_type arm_prgmode;
262
263 /* Set by the -mfp=... option. */
264 const char * target_fp_name = NULL;
265
266 /* Used to parse -mstructure_size_boundary command line option. */
267 const char * structure_size_string = NULL;
268 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
269
270 /* Bit values used to identify processor capabilities. */
271 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
272 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
273 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
274 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
275 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
276 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
277 #define FL_THUMB (1 << 6) /* Thumb aware */
278 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
279 #define FL_STRONG (1 << 8) /* StrongARM */
280 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
281 #define FL_XSCALE (1 << 10) /* XScale */
282 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
283 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
284 #define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds
285 media instructions. */
286 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
287
288 /* The bits in this mask specify which
289 instructions we are allowed to generate. */
290 static unsigned long insn_flags = 0;
291
292 /* The bits in this mask specify which instruction scheduling options should
293 be used. Note - there is an overlap with the FL_FAST_MULT. For some
294 hardware we want to be able to generate the multiply instructions, but to
295 tune as if they were not present in the architecture. */
296 static unsigned long tune_flags = 0;
297
298 /* The following are used in the arm.md file as equivalents to bits
299 in the above two flag variables. */
300
301 /* Nonzero if this is an "M" variant of the processor. */
302 int arm_fast_multiply = 0;
303
304 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
305 int arm_arch4 = 0;
306
307 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
308 int arm_arch5 = 0;
309
310 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
311 int arm_arch5e = 0;
312
313 /* Nonzero if this chip can benefit from load scheduling. */
314 int arm_ld_sched = 0;
315
316 /* Nonzero if this chip is a StrongARM. */
317 int arm_is_strong = 0;
318
319 /* Nonzero if this chip supports Intel Wireless MMX technology. */
320 int arm_arch_iwmmxt = 0;
321
322 /* Nonzero if this chip is an XScale. */
323 int arm_arch_xscale = 0;
324
325 /* Nonzero if tuning for XScale */
326 int arm_tune_xscale = 0;
327
328 /* Nonzero if this chip is an ARM6 or an ARM7. */
329 int arm_is_6_or_7 = 0;
330
331 /* Nonzero if this chip is a Cirrus/DSP. */
332 int arm_is_cirrus = 0;
333
334 /* Nonzero if generating Thumb instructions. */
335 int thumb_code = 0;
336
337 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
338 must report the mode of the memory reference from PRINT_OPERAND to
339 PRINT_OPERAND_ADDRESS. */
340 enum machine_mode output_memory_reference_mode;
341
342 /* The register number to be used for the PIC offset register. */
343 const char * arm_pic_register_string = NULL;
344 int arm_pic_register = INVALID_REGNUM;
345
346 /* Set to 1 when a return insn is output, this means that the epilogue
347 is not needed. */
348 int return_used_this_function;
349
350 /* Set to 1 after arm_reorg has started. Reset to start at the start of
351 the next function. */
352 static int after_arm_reorg = 0;
353
354 /* The maximum number of insns to be used when loading a constant. */
355 static int arm_constant_limit = 3;
356
357 /* For an explanation of these variables, see final_prescan_insn below. */
358 int arm_ccfsm_state;
359 enum arm_cond_code arm_current_cc;
360 rtx arm_target_insn;
361 int arm_target_label;
362
363 /* The condition codes of the ARM, and the inverse function. */
364 static const char * const arm_condition_codes[] =
365 {
366 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
367 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
368 };
369
370 #define streq(string1, string2) (strcmp (string1, string2) == 0)
371 \f
372 /* Initialization code. */
373
374 struct processors
375 {
376 const char *const name;
377 const unsigned long flags;
378 };
379
380 /* Not all of these give usefully different compilation alternatives,
381 but there is no simple way of generalizing them. */
382 static const struct processors all_cores[] =
383 {
384 /* ARM Cores */
385
386 {"arm2", FL_CO_PROC | FL_MODE26 },
387 {"arm250", FL_CO_PROC | FL_MODE26 },
388 {"arm3", FL_CO_PROC | FL_MODE26 },
389 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
390 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
391 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
392 {"arm610", FL_MODE26 | FL_MODE32 },
393 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
394 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
395 /* arm7m doesn't exist on its own, but only with D, (and I), but
396 those don't alter the code, so arm7m is sometimes used. */
397 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
398 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
399 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
400 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
401 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
402 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
403 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
404 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
405 {"arm710", FL_MODE26 | FL_MODE32 },
406 {"arm720", FL_MODE26 | FL_MODE32 },
407 {"arm710c", FL_MODE26 | FL_MODE32 },
408 {"arm7100", FL_MODE26 | FL_MODE32 },
409 {"arm7500", FL_MODE26 | FL_MODE32 },
410 /* Doesn't have an external co-proc, but does have embedded fpa. */
411 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
412 /* V4 Architecture Processors */
413 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
414 {"arm710t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
415 {"arm720t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
416 {"arm740t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
417 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
418 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
419 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
420 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
421 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
422 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
423 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
424 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
425 {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
426 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
427 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
428 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
429 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
430 /* V5 Architecture Processors */
431 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
432 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
433 {"arm926ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
434 {"arm1026ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
435 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
436 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
437 /* V6 Architecture Processors */
438 {"arm1136js", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
439 {"arm1136jfs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2 },
440 {NULL, 0}
441 };
442
443 static const struct processors all_architectures[] =
444 {
445 /* ARM Architectures */
446
447 { "armv2", FL_CO_PROC | FL_MODE26 },
448 { "armv2a", FL_CO_PROC | FL_MODE26 },
449 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
450 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
451 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
452 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
453 implementations that support it, so we will leave it out for now. */
454 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
455 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
456 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
457 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
458 { "armv6j", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
459 { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
460 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
461 { NULL, 0 }
462 };
463
464 /* This is a magic structure. The 'string' field is magically filled in
465 with a pointer to the value specified by the user on the command line
466 assuming that the user has specified such a value. */
467
468 struct arm_cpu_select arm_select[] =
469 {
470 /* string name processors */
471 { NULL, "-mcpu=", all_cores },
472 { NULL, "-march=", all_architectures },
473 { NULL, "-mtune=", all_cores }
474 };
475
476 /* Return the number of bits set in VALUE. */
477 static unsigned
478 bit_count (unsigned long value)
479 {
480 unsigned long count = 0;
481
482 while (value)
483 {
484 count++;
485 value &= value - 1; /* Clear the least-significant set bit. */
486 }
487
488 return count;
489 }
490
491 /* Fix up any incompatible options that the user has specified.
492 This has now turned into a maze. */
493 void
494 arm_override_options (void)
495 {
496 unsigned i;
497
498 /* Set up the flags based on the cpu/architecture selected by the user. */
499 for (i = ARRAY_SIZE (arm_select); i--;)
500 {
501 struct arm_cpu_select * ptr = arm_select + i;
502
503 if (ptr->string != NULL && ptr->string[0] != '\0')
504 {
505 const struct processors * sel;
506
507 for (sel = ptr->processors; sel->name != NULL; sel++)
508 if (streq (ptr->string, sel->name))
509 {
510 if (i == 2)
511 tune_flags = sel->flags;
512 else
513 {
514 /* If we have been given an architecture and a processor
515 make sure that they are compatible. We only generate
516 a warning though, and we prefer the CPU over the
517 architecture. */
518 if (insn_flags != 0 && (insn_flags ^ sel->flags))
519 warning ("switch -mcpu=%s conflicts with -march= switch",
520 ptr->string);
521
522 insn_flags = sel->flags;
523 }
524
525 break;
526 }
527
528 if (sel->name == NULL)
529 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
530 }
531 }
532
533 /* If the user did not specify a processor, choose one for them. */
534 if (insn_flags == 0)
535 {
536 const struct processors * sel;
537 unsigned int sought;
538 static const struct cpu_default
539 {
540 const int cpu;
541 const char *const name;
542 }
543 cpu_defaults[] =
544 {
545 { TARGET_CPU_arm2, "arm2" },
546 { TARGET_CPU_arm6, "arm6" },
547 { TARGET_CPU_arm610, "arm610" },
548 { TARGET_CPU_arm710, "arm710" },
549 { TARGET_CPU_arm7m, "arm7m" },
550 { TARGET_CPU_arm7500fe, "arm7500fe" },
551 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
552 { TARGET_CPU_arm8, "arm8" },
553 { TARGET_CPU_arm810, "arm810" },
554 { TARGET_CPU_arm9, "arm9" },
555 { TARGET_CPU_strongarm, "strongarm" },
556 { TARGET_CPU_xscale, "xscale" },
557 { TARGET_CPU_ep9312, "ep9312" },
558 { TARGET_CPU_iwmmxt, "iwmmxt" },
559 { TARGET_CPU_arm926ej_s, "arm926ej-s" },
560 { TARGET_CPU_arm1026ej_s, "arm1026ej-s" },
561 { TARGET_CPU_arm1136j_s, "arm1136j_s" },
562 { TARGET_CPU_arm1136jf_s, "arm1136jf_s" },
563 { TARGET_CPU_generic, "arm" },
564 { 0, 0 }
565 };
566 const struct cpu_default * def;
567
568 /* Find the default. */
569 for (def = cpu_defaults; def->name; def++)
570 if (def->cpu == TARGET_CPU_DEFAULT)
571 break;
572
573 /* Make sure we found the default CPU. */
574 if (def->name == NULL)
575 abort ();
576
577 /* Find the default CPU's flags. */
578 for (sel = all_cores; sel->name != NULL; sel++)
579 if (streq (def->name, sel->name))
580 break;
581
582 if (sel->name == NULL)
583 abort ();
584
585 insn_flags = sel->flags;
586
587 /* Now check to see if the user has specified some command line
588 switch that require certain abilities from the cpu. */
589 sought = 0;
590
591 if (TARGET_INTERWORK || TARGET_THUMB)
592 {
593 sought |= (FL_THUMB | FL_MODE32);
594
595 /* Force apcs-32 to be used for interworking. */
596 target_flags |= ARM_FLAG_APCS_32;
597
598 /* There are no ARM processors that support both APCS-26 and
599 interworking. Therefore we force FL_MODE26 to be removed
600 from insn_flags here (if it was set), so that the search
601 below will always be able to find a compatible processor. */
602 insn_flags &= ~FL_MODE26;
603 }
604 else if (!TARGET_APCS_32)
605 sought |= FL_MODE26;
606
607 if (sought != 0 && ((sought & insn_flags) != sought))
608 {
609 /* Try to locate a CPU type that supports all of the abilities
610 of the default CPU, plus the extra abilities requested by
611 the user. */
612 for (sel = all_cores; sel->name != NULL; sel++)
613 if ((sel->flags & sought) == (sought | insn_flags))
614 break;
615
616 if (sel->name == NULL)
617 {
618 unsigned current_bit_count = 0;
619 const struct processors * best_fit = NULL;
620
621 /* Ideally we would like to issue an error message here
622 saying that it was not possible to find a CPU compatible
623 with the default CPU, but which also supports the command
624 line options specified by the programmer, and so they
625 ought to use the -mcpu=<name> command line option to
626 override the default CPU type.
627
628 Unfortunately this does not work with multilibing. We
629 need to be able to support multilibs for -mapcs-26 and for
630 -mthumb-interwork and there is no CPU that can support both
631 options. Instead if we cannot find a cpu that has both the
632 characteristics of the default cpu and the given command line
633 options we scan the array again looking for a best match. */
634 for (sel = all_cores; sel->name != NULL; sel++)
635 if ((sel->flags & sought) == sought)
636 {
637 unsigned count;
638
639 count = bit_count (sel->flags & insn_flags);
640
641 if (count >= current_bit_count)
642 {
643 best_fit = sel;
644 current_bit_count = count;
645 }
646 }
647
648 if (best_fit == NULL)
649 abort ();
650 else
651 sel = best_fit;
652 }
653
654 insn_flags = sel->flags;
655 }
656 }
657
658 /* If tuning has not been specified, tune for whichever processor or
659 architecture has been selected. */
660 if (tune_flags == 0)
661 tune_flags = insn_flags;
662
663 /* Make sure that the processor choice does not conflict with any of the
664 other command line choices. */
665 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
666 {
667 /* If APCS-32 was not the default then it must have been set by the
668 user, so issue a warning message. If the user has specified
669 "-mapcs-32 -mcpu=arm2" then we loose here. */
670 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
671 warning ("target CPU does not support APCS-32" );
672 target_flags &= ~ARM_FLAG_APCS_32;
673 }
674 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
675 {
676 warning ("target CPU does not support APCS-26" );
677 target_flags |= ARM_FLAG_APCS_32;
678 }
679
680 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
681 {
682 warning ("target CPU does not support interworking" );
683 target_flags &= ~ARM_FLAG_INTERWORK;
684 }
685
686 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
687 {
688 warning ("target CPU does not support THUMB instructions");
689 target_flags &= ~ARM_FLAG_THUMB;
690 }
691
692 if (TARGET_APCS_FRAME && TARGET_THUMB)
693 {
694 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
695 target_flags &= ~ARM_FLAG_APCS_FRAME;
696 }
697
698 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
699 from here where no function is being compiled currently. */
700 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
701 && TARGET_ARM)
702 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
703
704 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
705 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
706
707 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
708 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
709
710 /* If interworking is enabled then APCS-32 must be selected as well. */
711 if (TARGET_INTERWORK)
712 {
713 if (!TARGET_APCS_32)
714 warning ("interworking forces APCS-32 to be used" );
715 target_flags |= ARM_FLAG_APCS_32;
716 }
717
718 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
719 {
720 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
721 target_flags |= ARM_FLAG_APCS_FRAME;
722 }
723
724 if (TARGET_POKE_FUNCTION_NAME)
725 target_flags |= ARM_FLAG_APCS_FRAME;
726
727 if (TARGET_APCS_REENT && flag_pic)
728 error ("-fpic and -mapcs-reent are incompatible");
729
730 if (TARGET_APCS_REENT)
731 warning ("APCS reentrant code not supported. Ignored");
732
733 /* If this target is normally configured to use APCS frames, warn if they
734 are turned off and debugging is turned on. */
735 if (TARGET_ARM
736 && write_symbols != NO_DEBUG
737 && !TARGET_APCS_FRAME
738 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
739 warning ("-g with -mno-apcs-frame may not give sensible debugging");
740
741 /* If stack checking is disabled, we can use r10 as the PIC register,
742 which keeps r9 available. */
743 if (flag_pic)
744 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
745
746 if (TARGET_APCS_FLOAT)
747 warning ("passing floating point arguments in fp regs not yet supported");
748
749 /* Initialize boolean versions of the flags, for use in the arm.md file. */
750 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
751 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
752 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
753 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
754 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
755
756 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
757 arm_is_strong = (tune_flags & FL_STRONG) != 0;
758 thumb_code = (TARGET_ARM == 0);
759 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
760 && !(tune_flags & FL_ARCH4))) != 0;
761 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
762 arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0;
763 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
764
765 if (TARGET_IWMMXT && (! TARGET_ATPCS))
766 target_flags |= ARM_FLAG_ATPCS;
767
768 if (arm_is_cirrus)
769 {
770 arm_fpu_tune = FPUTYPE_MAVERICK;
771
772 /* Ignore -mhard-float if -mcpu=ep9312. */
773 if (TARGET_HARD_FLOAT)
774 target_flags ^= ARM_FLAG_SOFT_FLOAT;
775 }
776 else
777 /* Default value for floating point code... if no co-processor
778 bus, then schedule for emulated floating point. Otherwise,
779 assume the user has an FPA.
780 Note: this does not prevent use of floating point instructions,
781 -msoft-float does that. */
782 arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3;
783
784 if (target_fp_name)
785 {
786 if (streq (target_fp_name, "2"))
787 arm_fpu_arch = FPUTYPE_FPA_EMU2;
788 else if (streq (target_fp_name, "3"))
789 arm_fpu_arch = FPUTYPE_FPA_EMU3;
790 else
791 error ("invalid floating point emulation option: -mfpe-%s",
792 target_fp_name);
793 }
794 else
795 arm_fpu_arch = FPUTYPE_DEFAULT;
796
797 if (TARGET_FPE)
798 {
799 if (arm_fpu_tune == FPUTYPE_FPA_EMU3)
800 arm_fpu_tune = FPUTYPE_FPA_EMU2;
801 else if (arm_fpu_tune == FPUTYPE_MAVERICK)
802 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
803 else if (arm_fpu_tune != FPUTYPE_FPA)
804 arm_fpu_tune = FPUTYPE_FPA_EMU2;
805 }
806
807 /* For arm2/3 there is no need to do any scheduling if there is only
808 a floating point emulator, or we are doing software floating-point. */
809 if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA)
810 && (tune_flags & FL_MODE32) == 0)
811 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
812
813 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
814
815 if (structure_size_string != NULL)
816 {
817 int size = strtol (structure_size_string, NULL, 0);
818
819 if (size == 8 || size == 32)
820 arm_structure_size_boundary = size;
821 else
822 warning ("structure size boundary can only be set to 8 or 32");
823 }
824
825 if (arm_pic_register_string != NULL)
826 {
827 int pic_register = decode_reg_name (arm_pic_register_string);
828
829 if (!flag_pic)
830 warning ("-mpic-register= is useless without -fpic");
831
832 /* Prevent the user from choosing an obviously stupid PIC register. */
833 else if (pic_register < 0 || call_used_regs[pic_register]
834 || pic_register == HARD_FRAME_POINTER_REGNUM
835 || pic_register == STACK_POINTER_REGNUM
836 || pic_register >= PC_REGNUM)
837 error ("unable to use '%s' for PIC register", arm_pic_register_string);
838 else
839 arm_pic_register = pic_register;
840 }
841
842 if (TARGET_THUMB && flag_schedule_insns)
843 {
844 /* Don't warn since it's on by default in -O2. */
845 flag_schedule_insns = 0;
846 }
847
848 /* If optimizing for space, don't synthesize constants.
849 For processors with load scheduling, it never costs more than 2 cycles
850 to load a constant, and the load scheduler may well reduce that to 1. */
851 if (optimize_size || (tune_flags & FL_LDSCHED))
852 arm_constant_limit = 1;
853
854 if (arm_tune_xscale)
855 arm_constant_limit = 2;
856
857 /* If optimizing for size, bump the number of instructions that we
858 are prepared to conditionally execute (even on a StrongARM).
859 Otherwise for the StrongARM, which has early execution of branches,
860 a sequence that is worth skipping is shorter. */
861 if (optimize_size)
862 max_insns_skipped = 6;
863 else if (arm_is_strong)
864 max_insns_skipped = 3;
865
866 /* Register global variables with the garbage collector. */
867 arm_add_gc_roots ();
868 }
869
870 static void
871 arm_add_gc_roots (void)
872 {
873 gcc_obstack_init(&minipool_obstack);
874 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
875 }
876 \f
877 /* A table of known ARM exception types.
878 For use with the interrupt function attribute. */
879
880 typedef struct
881 {
882 const char *const arg;
883 const unsigned long return_value;
884 }
885 isr_attribute_arg;
886
887 static const isr_attribute_arg isr_attribute_args [] =
888 {
889 { "IRQ", ARM_FT_ISR },
890 { "irq", ARM_FT_ISR },
891 { "FIQ", ARM_FT_FIQ },
892 { "fiq", ARM_FT_FIQ },
893 { "ABORT", ARM_FT_ISR },
894 { "abort", ARM_FT_ISR },
895 { "ABORT", ARM_FT_ISR },
896 { "abort", ARM_FT_ISR },
897 { "UNDEF", ARM_FT_EXCEPTION },
898 { "undef", ARM_FT_EXCEPTION },
899 { "SWI", ARM_FT_EXCEPTION },
900 { "swi", ARM_FT_EXCEPTION },
901 { NULL, ARM_FT_NORMAL }
902 };
903
904 /* Returns the (interrupt) function type of the current
905 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
906
907 static unsigned long
908 arm_isr_value (tree argument)
909 {
910 const isr_attribute_arg * ptr;
911 const char * arg;
912
913 /* No argument - default to IRQ. */
914 if (argument == NULL_TREE)
915 return ARM_FT_ISR;
916
917 /* Get the value of the argument. */
918 if (TREE_VALUE (argument) == NULL_TREE
919 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
920 return ARM_FT_UNKNOWN;
921
922 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
923
924 /* Check it against the list of known arguments. */
925 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
926 if (streq (arg, ptr->arg))
927 return ptr->return_value;
928
929 /* An unrecognized interrupt type. */
930 return ARM_FT_UNKNOWN;
931 }
932
933 /* Computes the type of the current function. */
934
935 static unsigned long
936 arm_compute_func_type (void)
937 {
938 unsigned long type = ARM_FT_UNKNOWN;
939 tree a;
940 tree attr;
941
942 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
943 abort ();
944
945 /* Decide if the current function is volatile. Such functions
946 never return, and many memory cycles can be saved by not storing
947 register values that will never be needed again. This optimization
948 was added to speed up context switching in a kernel application. */
949 if (optimize > 0
950 && current_function_nothrow
951 && TREE_THIS_VOLATILE (current_function_decl))
952 type |= ARM_FT_VOLATILE;
953
954 if (current_function_needs_context)
955 type |= ARM_FT_NESTED;
956
957 attr = DECL_ATTRIBUTES (current_function_decl);
958
959 a = lookup_attribute ("naked", attr);
960 if (a != NULL_TREE)
961 type |= ARM_FT_NAKED;
962
963 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
964 type |= ARM_FT_EXCEPTION_HANDLER;
965 else
966 {
967 a = lookup_attribute ("isr", attr);
968 if (a == NULL_TREE)
969 a = lookup_attribute ("interrupt", attr);
970
971 if (a == NULL_TREE)
972 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
973 else
974 type |= arm_isr_value (TREE_VALUE (a));
975 }
976
977 return type;
978 }
979
980 /* Returns the type of the current function. */
981
982 unsigned long
983 arm_current_func_type (void)
984 {
985 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
986 cfun->machine->func_type = arm_compute_func_type ();
987
988 return cfun->machine->func_type;
989 }
990 \f
991 /* Return 1 if it is possible to return using a single instruction. */
992
993 int
994 use_return_insn (int iscond)
995 {
996 int regno;
997 unsigned int func_type;
998 unsigned long saved_int_regs;
999
1000 /* Never use a return instruction before reload has run. */
1001 if (!reload_completed)
1002 return 0;
1003
1004 /* We need two instructions when there's a frame pointer. */
1005 if (frame_pointer_needed)
1006 return 0;
1007
1008 func_type = arm_current_func_type ();
1009
1010 /* Naked functions and volatile functions need special
1011 consideration. */
1012 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1013 return 0;
1014
1015 /* So do interrupt functions that use the frame pointer. */
1016 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1017 return 0;
1018
1019 /* As do variadic functions. */
1020 if (current_function_pretend_args_size
1021 || cfun->machine->uses_anonymous_args
1022 /* Of if the function calls __builtin_eh_return () */
1023 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1024 /* Or if there is no frame pointer and there is a stack adjustment. */
1025 || ((arm_get_frame_size () + current_function_outgoing_args_size != 0)
1026 && !frame_pointer_needed))
1027 return 0;
1028
1029 saved_int_regs = arm_compute_save_reg_mask ();
1030
1031 /* Can't be done if interworking with Thumb, and any registers have been
1032 stacked. */
1033 if (TARGET_INTERWORK && saved_int_regs != 0)
1034 return 0;
1035
1036 /* On StrongARM, conditional returns are expensive if they aren't
1037 taken and multiple registers have been stacked. */
1038 if (iscond && arm_is_strong)
1039 {
1040 /* Conditional return when just the LR is stored is a simple
1041 conditional-load instruction, that's not expensive. */
1042 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1043 return 0;
1044
1045 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1046 return 0;
1047 }
1048
1049 /* If there are saved registers but the LR isn't saved, then we need
1050 two instructions for the return. */
1051 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1052 return 0;
1053
1054 /* Can't be done if any of the FPA regs are pushed,
1055 since this also requires an insn. */
1056 if (TARGET_HARD_FLOAT)
1057 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
1058 if (regs_ever_live[regno] && !call_used_regs[regno])
1059 return 0;
1060
1061 if (TARGET_REALLY_IWMMXT)
1062 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1063 if (regs_ever_live[regno] && ! call_used_regs [regno])
1064 return 0;
1065
1066 return 1;
1067 }
1068
1069 /* Return TRUE if int I is a valid immediate ARM constant. */
1070
1071 int
1072 const_ok_for_arm (HOST_WIDE_INT i)
1073 {
1074 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1075
1076 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1077 be all zero, or all one. */
1078 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1079 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1080 != ((~(unsigned HOST_WIDE_INT) 0)
1081 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1082 return FALSE;
1083
1084 /* Fast return for 0 and powers of 2 */
1085 if ((i & (i - 1)) == 0)
1086 return TRUE;
1087
1088 do
1089 {
1090 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1091 return TRUE;
1092 mask =
1093 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1094 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1095 }
1096 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1097
1098 return FALSE;
1099 }
1100
1101 /* Return true if I is a valid constant for the operation CODE. */
1102 static int
1103 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1104 {
1105 if (const_ok_for_arm (i))
1106 return 1;
1107
1108 switch (code)
1109 {
1110 case PLUS:
1111 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1112
1113 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1114 case XOR:
1115 case IOR:
1116 return 0;
1117
1118 case AND:
1119 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1120
1121 default:
1122 abort ();
1123 }
1124 }
1125
1126 /* Emit a sequence of insns to handle a large constant.
1127 CODE is the code of the operation required, it can be any of SET, PLUS,
1128 IOR, AND, XOR, MINUS;
1129 MODE is the mode in which the operation is being performed;
1130 VAL is the integer to operate on;
1131 SOURCE is the other operand (a register, or a null-pointer for SET);
1132 SUBTARGETS means it is safe to create scratch registers if that will
1133 either produce a simpler sequence, or we will want to cse the values.
1134 Return value is the number of insns emitted. */
1135
1136 int
1137 arm_split_constant (enum rtx_code code, enum machine_mode mode,
1138 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1139 {
1140 if (subtargets || code == SET
1141 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1142 && REGNO (target) != REGNO (source)))
1143 {
1144 /* After arm_reorg has been called, we can't fix up expensive
1145 constants by pushing them into memory so we must synthesize
1146 them in-line, regardless of the cost. This is only likely to
1147 be more costly on chips that have load delay slots and we are
1148 compiling without running the scheduler (so no splitting
1149 occurred before the final instruction emission).
1150
1151 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1152 */
1153 if (!after_arm_reorg
1154 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1155 > arm_constant_limit + (code != SET)))
1156 {
1157 if (code == SET)
1158 {
1159 /* Currently SET is the only monadic value for CODE, all
1160 the rest are diadic. */
1161 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1162 return 1;
1163 }
1164 else
1165 {
1166 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1167
1168 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1169 /* For MINUS, the value is subtracted from, since we never
1170 have subtraction of a constant. */
1171 if (code == MINUS)
1172 emit_insn (gen_rtx_SET (VOIDmode, target,
1173 gen_rtx_MINUS (mode, temp, source)));
1174 else
1175 emit_insn (gen_rtx_SET (VOIDmode, target,
1176 gen_rtx (code, mode, source, temp)));
1177 return 2;
1178 }
1179 }
1180 }
1181
1182 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1183 }
1184
1185 static int
1186 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1187 {
1188 HOST_WIDE_INT temp1;
1189 int num_insns = 0;
1190 do
1191 {
1192 int end;
1193
1194 if (i <= 0)
1195 i += 32;
1196 if (remainder & (3 << (i - 2)))
1197 {
1198 end = i - 8;
1199 if (end < 0)
1200 end += 32;
1201 temp1 = remainder & ((0x0ff << end)
1202 | ((i < end) ? (0xff >> (32 - end)) : 0));
1203 remainder &= ~temp1;
1204 num_insns++;
1205 i -= 6;
1206 }
1207 i -= 2;
1208 } while (remainder);
1209 return num_insns;
1210 }
1211
1212 /* As above, but extra parameter GENERATE which, if clear, suppresses
1213 RTL generation. */
1214
1215 static int
1216 arm_gen_constant (enum rtx_code code, enum machine_mode mode,
1217 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1218 int generate)
1219 {
1220 int can_invert = 0;
1221 int can_negate = 0;
1222 int can_negate_initial = 0;
1223 int can_shift = 0;
1224 int i;
1225 int num_bits_set = 0;
1226 int set_sign_bit_copies = 0;
1227 int clear_sign_bit_copies = 0;
1228 int clear_zero_bit_copies = 0;
1229 int set_zero_bit_copies = 0;
1230 int insns = 0;
1231 unsigned HOST_WIDE_INT temp1, temp2;
1232 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1233
1234 /* Find out which operations are safe for a given CODE. Also do a quick
1235 check for degenerate cases; these can occur when DImode operations
1236 are split. */
1237 switch (code)
1238 {
1239 case SET:
1240 can_invert = 1;
1241 can_shift = 1;
1242 can_negate = 1;
1243 break;
1244
1245 case PLUS:
1246 can_negate = 1;
1247 can_negate_initial = 1;
1248 break;
1249
1250 case IOR:
1251 if (remainder == 0xffffffff)
1252 {
1253 if (generate)
1254 emit_insn (gen_rtx_SET (VOIDmode, target,
1255 GEN_INT (ARM_SIGN_EXTEND (val))));
1256 return 1;
1257 }
1258 if (remainder == 0)
1259 {
1260 if (reload_completed && rtx_equal_p (target, source))
1261 return 0;
1262 if (generate)
1263 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1264 return 1;
1265 }
1266 break;
1267
1268 case AND:
1269 if (remainder == 0)
1270 {
1271 if (generate)
1272 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1273 return 1;
1274 }
1275 if (remainder == 0xffffffff)
1276 {
1277 if (reload_completed && rtx_equal_p (target, source))
1278 return 0;
1279 if (generate)
1280 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1281 return 1;
1282 }
1283 can_invert = 1;
1284 break;
1285
1286 case XOR:
1287 if (remainder == 0)
1288 {
1289 if (reload_completed && rtx_equal_p (target, source))
1290 return 0;
1291 if (generate)
1292 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1293 return 1;
1294 }
1295 if (remainder == 0xffffffff)
1296 {
1297 if (generate)
1298 emit_insn (gen_rtx_SET (VOIDmode, target,
1299 gen_rtx_NOT (mode, source)));
1300 return 1;
1301 }
1302
1303 /* We don't know how to handle this yet below. */
1304 abort ();
1305
1306 case MINUS:
1307 /* We treat MINUS as (val - source), since (source - val) is always
1308 passed as (source + (-val)). */
1309 if (remainder == 0)
1310 {
1311 if (generate)
1312 emit_insn (gen_rtx_SET (VOIDmode, target,
1313 gen_rtx_NEG (mode, source)));
1314 return 1;
1315 }
1316 if (const_ok_for_arm (val))
1317 {
1318 if (generate)
1319 emit_insn (gen_rtx_SET (VOIDmode, target,
1320 gen_rtx_MINUS (mode, GEN_INT (val),
1321 source)));
1322 return 1;
1323 }
1324 can_negate = 1;
1325
1326 break;
1327
1328 default:
1329 abort ();
1330 }
1331
1332 /* If we can do it in one insn get out quickly. */
1333 if (const_ok_for_arm (val)
1334 || (can_negate_initial && const_ok_for_arm (-val))
1335 || (can_invert && const_ok_for_arm (~val)))
1336 {
1337 if (generate)
1338 emit_insn (gen_rtx_SET (VOIDmode, target,
1339 (source ? gen_rtx (code, mode, source,
1340 GEN_INT (val))
1341 : GEN_INT (val))));
1342 return 1;
1343 }
1344
1345 /* Calculate a few attributes that may be useful for specific
1346 optimizations. */
1347 for (i = 31; i >= 0; i--)
1348 {
1349 if ((remainder & (1 << i)) == 0)
1350 clear_sign_bit_copies++;
1351 else
1352 break;
1353 }
1354
1355 for (i = 31; i >= 0; i--)
1356 {
1357 if ((remainder & (1 << i)) != 0)
1358 set_sign_bit_copies++;
1359 else
1360 break;
1361 }
1362
1363 for (i = 0; i <= 31; i++)
1364 {
1365 if ((remainder & (1 << i)) == 0)
1366 clear_zero_bit_copies++;
1367 else
1368 break;
1369 }
1370
1371 for (i = 0; i <= 31; i++)
1372 {
1373 if ((remainder & (1 << i)) != 0)
1374 set_zero_bit_copies++;
1375 else
1376 break;
1377 }
1378
1379 switch (code)
1380 {
1381 case SET:
1382 /* See if we can do this by sign_extending a constant that is known
1383 to be negative. This is a good, way of doing it, since the shift
1384 may well merge into a subsequent insn. */
1385 if (set_sign_bit_copies > 1)
1386 {
1387 if (const_ok_for_arm
1388 (temp1 = ARM_SIGN_EXTEND (remainder
1389 << (set_sign_bit_copies - 1))))
1390 {
1391 if (generate)
1392 {
1393 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1394 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1395 GEN_INT (temp1)));
1396 emit_insn (gen_ashrsi3 (target, new_src,
1397 GEN_INT (set_sign_bit_copies - 1)));
1398 }
1399 return 2;
1400 }
1401 /* For an inverted constant, we will need to set the low bits,
1402 these will be shifted out of harm's way. */
1403 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1404 if (const_ok_for_arm (~temp1))
1405 {
1406 if (generate)
1407 {
1408 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1409 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1410 GEN_INT (temp1)));
1411 emit_insn (gen_ashrsi3 (target, new_src,
1412 GEN_INT (set_sign_bit_copies - 1)));
1413 }
1414 return 2;
1415 }
1416 }
1417
1418 /* See if we can generate this by setting the bottom (or the top)
1419 16 bits, and then shifting these into the other half of the
1420 word. We only look for the simplest cases, to do more would cost
1421 too much. Be careful, however, not to generate this when the
1422 alternative would take fewer insns. */
1423 if (val & 0xffff0000)
1424 {
1425 temp1 = remainder & 0xffff0000;
1426 temp2 = remainder & 0x0000ffff;
1427
1428 /* Overlaps outside this range are best done using other methods. */
1429 for (i = 9; i < 24; i++)
1430 {
1431 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1432 && !const_ok_for_arm (temp2))
1433 {
1434 rtx new_src = (subtargets
1435 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1436 : target);
1437 insns = arm_gen_constant (code, mode, temp2, new_src,
1438 source, subtargets, generate);
1439 source = new_src;
1440 if (generate)
1441 emit_insn (gen_rtx_SET
1442 (VOIDmode, target,
1443 gen_rtx_IOR (mode,
1444 gen_rtx_ASHIFT (mode, source,
1445 GEN_INT (i)),
1446 source)));
1447 return insns + 1;
1448 }
1449 }
1450
1451 /* Don't duplicate cases already considered. */
1452 for (i = 17; i < 24; i++)
1453 {
1454 if (((temp1 | (temp1 >> i)) == remainder)
1455 && !const_ok_for_arm (temp1))
1456 {
1457 rtx new_src = (subtargets
1458 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1459 : target);
1460 insns = arm_gen_constant (code, mode, temp1, new_src,
1461 source, subtargets, generate);
1462 source = new_src;
1463 if (generate)
1464 emit_insn
1465 (gen_rtx_SET (VOIDmode, target,
1466 gen_rtx_IOR
1467 (mode,
1468 gen_rtx_LSHIFTRT (mode, source,
1469 GEN_INT (i)),
1470 source)));
1471 return insns + 1;
1472 }
1473 }
1474 }
1475 break;
1476
1477 case IOR:
1478 case XOR:
1479 /* If we have IOR or XOR, and the constant can be loaded in a
1480 single instruction, and we can find a temporary to put it in,
1481 then this can be done in two instructions instead of 3-4. */
1482 if (subtargets
1483 /* TARGET can't be NULL if SUBTARGETS is 0 */
1484 || (reload_completed && !reg_mentioned_p (target, source)))
1485 {
1486 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1487 {
1488 if (generate)
1489 {
1490 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1491
1492 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1493 emit_insn (gen_rtx_SET (VOIDmode, target,
1494 gen_rtx (code, mode, source, sub)));
1495 }
1496 return 2;
1497 }
1498 }
1499
1500 if (code == XOR)
1501 break;
1502
1503 if (set_sign_bit_copies > 8
1504 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1505 {
1506 if (generate)
1507 {
1508 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1509 rtx shift = GEN_INT (set_sign_bit_copies);
1510
1511 emit_insn (gen_rtx_SET (VOIDmode, sub,
1512 gen_rtx_NOT (mode,
1513 gen_rtx_ASHIFT (mode,
1514 source,
1515 shift))));
1516 emit_insn (gen_rtx_SET (VOIDmode, target,
1517 gen_rtx_NOT (mode,
1518 gen_rtx_LSHIFTRT (mode, sub,
1519 shift))));
1520 }
1521 return 2;
1522 }
1523
1524 if (set_zero_bit_copies > 8
1525 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1526 {
1527 if (generate)
1528 {
1529 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1530 rtx shift = GEN_INT (set_zero_bit_copies);
1531
1532 emit_insn (gen_rtx_SET (VOIDmode, sub,
1533 gen_rtx_NOT (mode,
1534 gen_rtx_LSHIFTRT (mode,
1535 source,
1536 shift))));
1537 emit_insn (gen_rtx_SET (VOIDmode, target,
1538 gen_rtx_NOT (mode,
1539 gen_rtx_ASHIFT (mode, sub,
1540 shift))));
1541 }
1542 return 2;
1543 }
1544
1545 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1546 {
1547 if (generate)
1548 {
1549 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1550 emit_insn (gen_rtx_SET (VOIDmode, sub,
1551 gen_rtx_NOT (mode, source)));
1552 source = sub;
1553 if (subtargets)
1554 sub = gen_reg_rtx (mode);
1555 emit_insn (gen_rtx_SET (VOIDmode, sub,
1556 gen_rtx_AND (mode, source,
1557 GEN_INT (temp1))));
1558 emit_insn (gen_rtx_SET (VOIDmode, target,
1559 gen_rtx_NOT (mode, sub)));
1560 }
1561 return 3;
1562 }
1563 break;
1564
1565 case AND:
1566 /* See if two shifts will do 2 or more insn's worth of work. */
1567 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1568 {
1569 HOST_WIDE_INT shift_mask = ((0xffffffff
1570 << (32 - clear_sign_bit_copies))
1571 & 0xffffffff);
1572
1573 if ((remainder | shift_mask) != 0xffffffff)
1574 {
1575 if (generate)
1576 {
1577 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1578 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1579 new_src, source, subtargets, 1);
1580 source = new_src;
1581 }
1582 else
1583 {
1584 rtx targ = subtargets ? NULL_RTX : target;
1585 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1586 targ, source, subtargets, 0);
1587 }
1588 }
1589
1590 if (generate)
1591 {
1592 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1593 rtx shift = GEN_INT (clear_sign_bit_copies);
1594
1595 emit_insn (gen_ashlsi3 (new_src, source, shift));
1596 emit_insn (gen_lshrsi3 (target, new_src, shift));
1597 }
1598
1599 return insns + 2;
1600 }
1601
1602 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1603 {
1604 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1605
1606 if ((remainder | shift_mask) != 0xffffffff)
1607 {
1608 if (generate)
1609 {
1610 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1611
1612 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1613 new_src, source, subtargets, 1);
1614 source = new_src;
1615 }
1616 else
1617 {
1618 rtx targ = subtargets ? NULL_RTX : target;
1619
1620 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1621 targ, source, subtargets, 0);
1622 }
1623 }
1624
1625 if (generate)
1626 {
1627 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1628 rtx shift = GEN_INT (clear_zero_bit_copies);
1629
1630 emit_insn (gen_lshrsi3 (new_src, source, shift));
1631 emit_insn (gen_ashlsi3 (target, new_src, shift));
1632 }
1633
1634 return insns + 2;
1635 }
1636
1637 break;
1638
1639 default:
1640 break;
1641 }
1642
1643 for (i = 0; i < 32; i++)
1644 if (remainder & (1 << i))
1645 num_bits_set++;
1646
1647 if (code == AND || (can_invert && num_bits_set > 16))
1648 remainder = (~remainder) & 0xffffffff;
1649 else if (code == PLUS && num_bits_set > 16)
1650 remainder = (-remainder) & 0xffffffff;
1651 else
1652 {
1653 can_invert = 0;
1654 can_negate = 0;
1655 }
1656
1657 /* Now try and find a way of doing the job in either two or three
1658 instructions.
1659 We start by looking for the largest block of zeros that are aligned on
1660 a 2-bit boundary, we then fill up the temps, wrapping around to the
1661 top of the word when we drop off the bottom.
1662 In the worst case this code should produce no more than four insns. */
1663 {
1664 int best_start = 0;
1665 int best_consecutive_zeros = 0;
1666
1667 for (i = 0; i < 32; i += 2)
1668 {
1669 int consecutive_zeros = 0;
1670
1671 if (!(remainder & (3 << i)))
1672 {
1673 while ((i < 32) && !(remainder & (3 << i)))
1674 {
1675 consecutive_zeros += 2;
1676 i += 2;
1677 }
1678 if (consecutive_zeros > best_consecutive_zeros)
1679 {
1680 best_consecutive_zeros = consecutive_zeros;
1681 best_start = i - consecutive_zeros;
1682 }
1683 i -= 2;
1684 }
1685 }
1686
1687 /* So long as it won't require any more insns to do so, it's
1688 desirable to emit a small constant (in bits 0...9) in the last
1689 insn. This way there is more chance that it can be combined with
1690 a later addressing insn to form a pre-indexed load or store
1691 operation. Consider:
1692
1693 *((volatile int *)0xe0000100) = 1;
1694 *((volatile int *)0xe0000110) = 2;
1695
1696 We want this to wind up as:
1697
1698 mov rA, #0xe0000000
1699 mov rB, #1
1700 str rB, [rA, #0x100]
1701 mov rB, #2
1702 str rB, [rA, #0x110]
1703
1704 rather than having to synthesize both large constants from scratch.
1705
1706 Therefore, we calculate how many insns would be required to emit
1707 the constant starting from `best_start', and also starting from
1708 zero (ie with bit 31 first to be output). If `best_start' doesn't
1709 yield a shorter sequence, we may as well use zero. */
1710 if (best_start != 0
1711 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1712 && (count_insns_for_constant (remainder, 0) <=
1713 count_insns_for_constant (remainder, best_start)))
1714 best_start = 0;
1715
1716 /* Now start emitting the insns. */
1717 i = best_start;
1718 do
1719 {
1720 int end;
1721
1722 if (i <= 0)
1723 i += 32;
1724 if (remainder & (3 << (i - 2)))
1725 {
1726 end = i - 8;
1727 if (end < 0)
1728 end += 32;
1729 temp1 = remainder & ((0x0ff << end)
1730 | ((i < end) ? (0xff >> (32 - end)) : 0));
1731 remainder &= ~temp1;
1732
1733 if (generate)
1734 {
1735 rtx new_src, temp1_rtx;
1736
1737 if (code == SET || code == MINUS)
1738 {
1739 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1740 if (can_invert && code != MINUS)
1741 temp1 = ~temp1;
1742 }
1743 else
1744 {
1745 if (remainder && subtargets)
1746 new_src = gen_reg_rtx (mode);
1747 else
1748 new_src = target;
1749 if (can_invert)
1750 temp1 = ~temp1;
1751 else if (can_negate)
1752 temp1 = -temp1;
1753 }
1754
1755 temp1 = trunc_int_for_mode (temp1, mode);
1756 temp1_rtx = GEN_INT (temp1);
1757
1758 if (code == SET)
1759 ;
1760 else if (code == MINUS)
1761 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1762 else
1763 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1764
1765 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1766 source = new_src;
1767 }
1768
1769 if (code == SET)
1770 {
1771 can_invert = 0;
1772 code = PLUS;
1773 }
1774 else if (code == MINUS)
1775 code = PLUS;
1776
1777 insns++;
1778 i -= 6;
1779 }
1780 i -= 2;
1781 }
1782 while (remainder);
1783 }
1784
1785 return insns;
1786 }
1787
1788 /* Canonicalize a comparison so that we are more likely to recognize it.
1789 This can be done for a few constant compares, where we can make the
1790 immediate value easier to load. */
1791
1792 enum rtx_code
1793 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
1794 {
1795 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1796
1797 switch (code)
1798 {
1799 case EQ:
1800 case NE:
1801 return code;
1802
1803 case GT:
1804 case LE:
1805 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1806 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1807 {
1808 *op1 = GEN_INT (i + 1);
1809 return code == GT ? GE : LT;
1810 }
1811 break;
1812
1813 case GE:
1814 case LT:
1815 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1816 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1817 {
1818 *op1 = GEN_INT (i - 1);
1819 return code == GE ? GT : LE;
1820 }
1821 break;
1822
1823 case GTU:
1824 case LEU:
1825 if (i != ~((unsigned HOST_WIDE_INT) 0)
1826 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1827 {
1828 *op1 = GEN_INT (i + 1);
1829 return code == GTU ? GEU : LTU;
1830 }
1831 break;
1832
1833 case GEU:
1834 case LTU:
1835 if (i != 0
1836 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1837 {
1838 *op1 = GEN_INT (i - 1);
1839 return code == GEU ? GTU : LEU;
1840 }
1841 break;
1842
1843 default:
1844 abort ();
1845 }
1846
1847 return code;
1848 }
1849
1850 /* Decide whether a type should be returned in memory (true)
1851 or in a register (false). This is called by the macro
1852 RETURN_IN_MEMORY. */
1853 int
1854 arm_return_in_memory (tree type)
1855 {
1856 HOST_WIDE_INT size;
1857
1858 if (!AGGREGATE_TYPE_P (type))
1859 /* All simple types are returned in registers. */
1860 return 0;
1861
1862 size = int_size_in_bytes (type);
1863
1864 if (TARGET_ATPCS)
1865 {
1866 /* ATPCS returns aggregate types in memory only if they are
1867 larger than a word (or are variable size). */
1868 return (size < 0 || size > UNITS_PER_WORD);
1869 }
1870
1871 /* For the arm-wince targets we choose to be compatible with Microsoft's
1872 ARM and Thumb compilers, which always return aggregates in memory. */
1873 #ifndef ARM_WINCE
1874 /* All structures/unions bigger than one word are returned in memory.
1875 Also catch the case where int_size_in_bytes returns -1. In this case
1876 the aggregate is either huge or of variable size, and in either case
1877 we will want to return it via memory and not in a register. */
1878 if (size < 0 || size > UNITS_PER_WORD)
1879 return 1;
1880
1881 if (TREE_CODE (type) == RECORD_TYPE)
1882 {
1883 tree field;
1884
1885 /* For a struct the APCS says that we only return in a register
1886 if the type is 'integer like' and every addressable element
1887 has an offset of zero. For practical purposes this means
1888 that the structure can have at most one non bit-field element
1889 and that this element must be the first one in the structure. */
1890
1891 /* Find the first field, ignoring non FIELD_DECL things which will
1892 have been created by C++. */
1893 for (field = TYPE_FIELDS (type);
1894 field && TREE_CODE (field) != FIELD_DECL;
1895 field = TREE_CHAIN (field))
1896 continue;
1897
1898 if (field == NULL)
1899 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1900
1901 /* Check that the first field is valid for returning in a register. */
1902
1903 /* ... Floats are not allowed */
1904 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1905 return 1;
1906
1907 /* ... Aggregates that are not themselves valid for returning in
1908 a register are not allowed. */
1909 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1910 return 1;
1911
1912 /* Now check the remaining fields, if any. Only bitfields are allowed,
1913 since they are not addressable. */
1914 for (field = TREE_CHAIN (field);
1915 field;
1916 field = TREE_CHAIN (field))
1917 {
1918 if (TREE_CODE (field) != FIELD_DECL)
1919 continue;
1920
1921 if (!DECL_BIT_FIELD_TYPE (field))
1922 return 1;
1923 }
1924
1925 return 0;
1926 }
1927
1928 if (TREE_CODE (type) == UNION_TYPE)
1929 {
1930 tree field;
1931
1932 /* Unions can be returned in registers if every element is
1933 integral, or can be returned in an integer register. */
1934 for (field = TYPE_FIELDS (type);
1935 field;
1936 field = TREE_CHAIN (field))
1937 {
1938 if (TREE_CODE (field) != FIELD_DECL)
1939 continue;
1940
1941 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1942 return 1;
1943
1944 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1945 return 1;
1946 }
1947
1948 return 0;
1949 }
1950 #endif /* not ARM_WINCE */
1951
1952 /* Return all other types in memory. */
1953 return 1;
1954 }
1955
1956 /* Indicate whether or not words of a double are in big-endian order. */
1957
1958 int
1959 arm_float_words_big_endian (void)
1960 {
1961 if (TARGET_CIRRUS)
1962 return 0;
1963
1964 /* For FPA, float words are always big-endian. For VFP, floats words
1965 follow the memory system mode. */
1966
1967 if (TARGET_HARD_FLOAT)
1968 {
1969 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1970 return 1;
1971 }
1972
1973 if (TARGET_VFP)
1974 return (TARGET_BIG_END ? 1 : 0);
1975
1976 return 1;
1977 }
1978
1979 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1980 for a call to a function whose data type is FNTYPE.
1981 For a library call, FNTYPE is NULL. */
1982 void
1983 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
1984 rtx libname ATTRIBUTE_UNUSED,
1985 tree fndecl ATTRIBUTE_UNUSED)
1986 {
1987 /* On the ARM, the offset starts at 0. */
1988 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
1989 pcum->iwmmxt_nregs = 0;
1990
1991 pcum->call_cookie = CALL_NORMAL;
1992
1993 if (TARGET_LONG_CALLS)
1994 pcum->call_cookie = CALL_LONG;
1995
1996 /* Check for long call/short call attributes. The attributes
1997 override any command line option. */
1998 if (fntype)
1999 {
2000 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2001 pcum->call_cookie = CALL_SHORT;
2002 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2003 pcum->call_cookie = CALL_LONG;
2004 }
2005
2006 /* Varargs vectors are treated the same as long long.
2007 named_count avoids having to change the way arm handles 'named' */
2008 pcum->named_count = 0;
2009 pcum->nargs = 0;
2010
2011 if (TARGET_REALLY_IWMMXT && fntype)
2012 {
2013 tree fn_arg;
2014
2015 for (fn_arg = TYPE_ARG_TYPES (fntype);
2016 fn_arg;
2017 fn_arg = TREE_CHAIN (fn_arg))
2018 pcum->named_count += 1;
2019
2020 if (! pcum->named_count)
2021 pcum->named_count = INT_MAX;
2022 }
2023 }
2024
2025 /* Determine where to put an argument to a function.
2026 Value is zero to push the argument on the stack,
2027 or a hard register in which to store the argument.
2028
2029 MODE is the argument's machine mode.
2030 TYPE is the data type of the argument (as a tree).
2031 This is null for libcalls where that information may
2032 not be available.
2033 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2034 the preceding args and about the function being called.
2035 NAMED is nonzero if this argument is a named parameter
2036 (otherwise it is an extra parameter matching an ellipsis). */
2037
2038 rtx
2039 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2040 tree type ATTRIBUTE_UNUSED, int named)
2041 {
2042 if (TARGET_REALLY_IWMMXT)
2043 {
2044 if (VECTOR_MODE_SUPPORTED_P (mode))
2045 {
2046 /* varargs vectors are treated the same as long long.
2047 named_count avoids having to change the way arm handles 'named' */
2048 if (pcum->named_count <= pcum->nargs + 1)
2049 {
2050 if (pcum->nregs == 1)
2051 pcum->nregs += 1;
2052 if (pcum->nregs <= 2)
2053 return gen_rtx_REG (mode, pcum->nregs);
2054 else
2055 return NULL_RTX;
2056 }
2057 else if (pcum->iwmmxt_nregs <= 9)
2058 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2059 else
2060 return NULL_RTX;
2061 }
2062 else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1)
2063 pcum->nregs += 1;
2064 }
2065
2066 if (mode == VOIDmode)
2067 /* Compute operand 2 of the call insn. */
2068 return GEN_INT (pcum->call_cookie);
2069
2070 if (!named || pcum->nregs >= NUM_ARG_REGS)
2071 return NULL_RTX;
2072
2073 return gen_rtx_REG (mode, pcum->nregs);
2074 }
2075
2076 /* Variable sized types are passed by reference. This is a GCC
2077 extension to the ARM ABI. */
2078
2079 int
2080 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2081 enum machine_mode mode ATTRIBUTE_UNUSED,
2082 tree type, int named ATTRIBUTE_UNUSED)
2083 {
2084 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2085 }
2086
2087 /* Implement va_arg. */
2088
2089 rtx
2090 arm_va_arg (tree valist, tree type)
2091 {
2092 /* Variable sized types are passed by reference. */
2093 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2094 {
2095 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2096 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2097 }
2098
2099 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT)
2100 {
2101 tree minus_eight;
2102 tree t;
2103
2104 /* Maintain 64-bit alignment of the valist pointer by
2105 constructing: valist = ((valist + (8 - 1)) & -8). */
2106 minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
2107 t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
2108 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2109 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight);
2110 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2111 TREE_SIDE_EFFECTS (t) = 1;
2112 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2113
2114 /* This is to stop the combine pass optimizing
2115 away the alignment adjustment. */
2116 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2117 }
2118
2119 return std_expand_builtin_va_arg (valist, type);
2120 }
2121 \f
2122 /* Encode the current state of the #pragma [no_]long_calls. */
2123 typedef enum
2124 {
2125 OFF, /* No #pramgma [no_]long_calls is in effect. */
2126 LONG, /* #pragma long_calls is in effect. */
2127 SHORT /* #pragma no_long_calls is in effect. */
2128 } arm_pragma_enum;
2129
2130 static arm_pragma_enum arm_pragma_long_calls = OFF;
2131
2132 void
2133 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2134 {
2135 arm_pragma_long_calls = LONG;
2136 }
2137
2138 void
2139 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2140 {
2141 arm_pragma_long_calls = SHORT;
2142 }
2143
2144 void
2145 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2146 {
2147 arm_pragma_long_calls = OFF;
2148 }
2149 \f
2150 /* Table of machine attributes. */
2151 const struct attribute_spec arm_attribute_table[] =
2152 {
2153 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2154 /* Function calls made to this symbol must be done indirectly, because
2155 it may lie outside of the 26 bit addressing range of a normal function
2156 call. */
2157 { "long_call", 0, 0, false, true, true, NULL },
2158 /* Whereas these functions are always known to reside within the 26 bit
2159 addressing range. */
2160 { "short_call", 0, 0, false, true, true, NULL },
2161 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2162 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2163 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2164 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2165 #ifdef ARM_PE
2166 /* ARM/PE has three new attributes:
2167 interfacearm - ?
2168 dllexport - for exporting a function/variable that will live in a dll
2169 dllimport - for importing a function/variable from a dll
2170
2171 Microsoft allows multiple declspecs in one __declspec, separating
2172 them with spaces. We do NOT support this. Instead, use __declspec
2173 multiple times.
2174 */
2175 { "dllimport", 0, 0, true, false, false, NULL },
2176 { "dllexport", 0, 0, true, false, false, NULL },
2177 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2178 #endif
2179 { NULL, 0, 0, false, false, false, NULL }
2180 };
2181
2182 /* Handle an attribute requiring a FUNCTION_DECL;
2183 arguments as in struct attribute_spec.handler. */
2184 static tree
2185 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2186 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2187 {
2188 if (TREE_CODE (*node) != FUNCTION_DECL)
2189 {
2190 warning ("`%s' attribute only applies to functions",
2191 IDENTIFIER_POINTER (name));
2192 *no_add_attrs = true;
2193 }
2194
2195 return NULL_TREE;
2196 }
2197
2198 /* Handle an "interrupt" or "isr" attribute;
2199 arguments as in struct attribute_spec.handler. */
2200 static tree
2201 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2202 bool *no_add_attrs)
2203 {
2204 if (DECL_P (*node))
2205 {
2206 if (TREE_CODE (*node) != FUNCTION_DECL)
2207 {
2208 warning ("`%s' attribute only applies to functions",
2209 IDENTIFIER_POINTER (name));
2210 *no_add_attrs = true;
2211 }
2212 /* FIXME: the argument if any is checked for type attributes;
2213 should it be checked for decl ones? */
2214 }
2215 else
2216 {
2217 if (TREE_CODE (*node) == FUNCTION_TYPE
2218 || TREE_CODE (*node) == METHOD_TYPE)
2219 {
2220 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2221 {
2222 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2223 *no_add_attrs = true;
2224 }
2225 }
2226 else if (TREE_CODE (*node) == POINTER_TYPE
2227 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2228 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2229 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2230 {
2231 *node = build_type_copy (*node);
2232 TREE_TYPE (*node) = build_type_attribute_variant
2233 (TREE_TYPE (*node),
2234 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2235 *no_add_attrs = true;
2236 }
2237 else
2238 {
2239 /* Possibly pass this attribute on from the type to a decl. */
2240 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2241 | (int) ATTR_FLAG_FUNCTION_NEXT
2242 | (int) ATTR_FLAG_ARRAY_NEXT))
2243 {
2244 *no_add_attrs = true;
2245 return tree_cons (name, args, NULL_TREE);
2246 }
2247 else
2248 {
2249 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2250 }
2251 }
2252 }
2253
2254 return NULL_TREE;
2255 }
2256
2257 /* Return 0 if the attributes for two types are incompatible, 1 if they
2258 are compatible, and 2 if they are nearly compatible (which causes a
2259 warning to be generated). */
2260 static int
2261 arm_comp_type_attributes (tree type1, tree type2)
2262 {
2263 int l1, l2, s1, s2;
2264
2265 /* Check for mismatch of non-default calling convention. */
2266 if (TREE_CODE (type1) != FUNCTION_TYPE)
2267 return 1;
2268
2269 /* Check for mismatched call attributes. */
2270 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2271 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2272 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2273 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2274
2275 /* Only bother to check if an attribute is defined. */
2276 if (l1 | l2 | s1 | s2)
2277 {
2278 /* If one type has an attribute, the other must have the same attribute. */
2279 if ((l1 != l2) || (s1 != s2))
2280 return 0;
2281
2282 /* Disallow mixed attributes. */
2283 if ((l1 & s2) || (l2 & s1))
2284 return 0;
2285 }
2286
2287 /* Check for mismatched ISR attribute. */
2288 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2289 if (! l1)
2290 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2291 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2292 if (! l2)
2293 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2294 if (l1 != l2)
2295 return 0;
2296
2297 return 1;
2298 }
2299
2300 /* Encode long_call or short_call attribute by prefixing
2301 symbol name in DECL with a special character FLAG. */
2302 void
2303 arm_encode_call_attribute (tree decl, int flag)
2304 {
2305 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2306 int len = strlen (str);
2307 char * newstr;
2308
2309 /* Do not allow weak functions to be treated as short call. */
2310 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2311 return;
2312
2313 newstr = alloca (len + 2);
2314 newstr[0] = flag;
2315 strcpy (newstr + 1, str);
2316
2317 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2318 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2319 }
2320
2321 /* Assigns default attributes to newly defined type. This is used to
2322 set short_call/long_call attributes for function types of
2323 functions defined inside corresponding #pragma scopes. */
2324 static void
2325 arm_set_default_type_attributes (tree type)
2326 {
2327 /* Add __attribute__ ((long_call)) to all functions, when
2328 inside #pragma long_calls or __attribute__ ((short_call)),
2329 when inside #pragma no_long_calls. */
2330 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2331 {
2332 tree type_attr_list, attr_name;
2333 type_attr_list = TYPE_ATTRIBUTES (type);
2334
2335 if (arm_pragma_long_calls == LONG)
2336 attr_name = get_identifier ("long_call");
2337 else if (arm_pragma_long_calls == SHORT)
2338 attr_name = get_identifier ("short_call");
2339 else
2340 return;
2341
2342 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2343 TYPE_ATTRIBUTES (type) = type_attr_list;
2344 }
2345 }
2346 \f
2347 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2348 defined within the current compilation unit. If this cannot be
2349 determined, then 0 is returned. */
2350 static int
2351 current_file_function_operand (rtx sym_ref)
2352 {
2353 /* This is a bit of a fib. A function will have a short call flag
2354 applied to its name if it has the short call attribute, or it has
2355 already been defined within the current compilation unit. */
2356 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2357 return 1;
2358
2359 /* The current function is always defined within the current compilation
2360 unit. if it s a weak definition however, then this may not be the real
2361 definition of the function, and so we have to say no. */
2362 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2363 && !DECL_WEAK (current_function_decl))
2364 return 1;
2365
2366 /* We cannot make the determination - default to returning 0. */
2367 return 0;
2368 }
2369
2370 /* Return nonzero if a 32 bit "long_call" should be generated for
2371 this call. We generate a long_call if the function:
2372
2373 a. has an __attribute__((long call))
2374 or b. is within the scope of a #pragma long_calls
2375 or c. the -mlong-calls command line switch has been specified
2376
2377 However we do not generate a long call if the function:
2378
2379 d. has an __attribute__ ((short_call))
2380 or e. is inside the scope of a #pragma no_long_calls
2381 or f. has an __attribute__ ((section))
2382 or g. is defined within the current compilation unit.
2383
2384 This function will be called by C fragments contained in the machine
2385 description file. CALL_REF and CALL_COOKIE correspond to the matched
2386 rtl operands. CALL_SYMBOL is used to distinguish between
2387 two different callers of the function. It is set to 1 in the
2388 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2389 and "call_value" patterns. This is because of the difference in the
2390 SYM_REFs passed by these patterns. */
2391 int
2392 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2393 {
2394 if (!call_symbol)
2395 {
2396 if (GET_CODE (sym_ref) != MEM)
2397 return 0;
2398
2399 sym_ref = XEXP (sym_ref, 0);
2400 }
2401
2402 if (GET_CODE (sym_ref) != SYMBOL_REF)
2403 return 0;
2404
2405 if (call_cookie & CALL_SHORT)
2406 return 0;
2407
2408 if (TARGET_LONG_CALLS && flag_function_sections)
2409 return 1;
2410
2411 if (current_file_function_operand (sym_ref))
2412 return 0;
2413
2414 return (call_cookie & CALL_LONG)
2415 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2416 || TARGET_LONG_CALLS;
2417 }
2418
2419 /* Return nonzero if it is ok to make a tail-call to DECL. */
2420 static bool
2421 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2422 {
2423 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2424
2425 if (cfun->machine->sibcall_blocked)
2426 return false;
2427
2428 /* Never tailcall something for which we have no decl, or if we
2429 are in Thumb mode. */
2430 if (decl == NULL || TARGET_THUMB)
2431 return false;
2432
2433 /* Get the calling method. */
2434 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2435 call_type = CALL_SHORT;
2436 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2437 call_type = CALL_LONG;
2438
2439 /* Cannot tail-call to long calls, since these are out of range of
2440 a branch instruction. However, if not compiling PIC, we know
2441 we can reach the symbol if it is in this compilation unit. */
2442 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2443 return false;
2444
2445 /* If we are interworking and the function is not declared static
2446 then we can't tail-call it unless we know that it exists in this
2447 compilation unit (since it might be a Thumb routine). */
2448 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2449 return false;
2450
2451 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2452 if (IS_INTERRUPT (arm_current_func_type ()))
2453 return false;
2454
2455 /* Everything else is ok. */
2456 return true;
2457 }
2458
2459 \f
2460 /* Addressing mode support functions. */
2461
2462 /* Return nonzero if X is a legitimate immediate operand when compiling
2463 for PIC. */
2464 int
2465 legitimate_pic_operand_p (rtx x)
2466 {
2467 if (CONSTANT_P (x)
2468 && flag_pic
2469 && (GET_CODE (x) == SYMBOL_REF
2470 || (GET_CODE (x) == CONST
2471 && GET_CODE (XEXP (x, 0)) == PLUS
2472 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2473 return 0;
2474
2475 return 1;
2476 }
2477
2478 rtx
2479 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2480 {
2481 if (GET_CODE (orig) == SYMBOL_REF
2482 || GET_CODE (orig) == LABEL_REF)
2483 {
2484 #ifndef AOF_ASSEMBLER
2485 rtx pic_ref, address;
2486 #endif
2487 rtx insn;
2488 int subregs = 0;
2489
2490 if (reg == 0)
2491 {
2492 if (no_new_pseudos)
2493 abort ();
2494 else
2495 reg = gen_reg_rtx (Pmode);
2496
2497 subregs = 1;
2498 }
2499
2500 #ifdef AOF_ASSEMBLER
2501 /* The AOF assembler can generate relocations for these directly, and
2502 understands that the PIC register has to be added into the offset. */
2503 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2504 #else
2505 if (subregs)
2506 address = gen_reg_rtx (Pmode);
2507 else
2508 address = reg;
2509
2510 if (TARGET_ARM)
2511 emit_insn (gen_pic_load_addr_arm (address, orig));
2512 else
2513 emit_insn (gen_pic_load_addr_thumb (address, orig));
2514
2515 if ((GET_CODE (orig) == LABEL_REF
2516 || (GET_CODE (orig) == SYMBOL_REF &&
2517 SYMBOL_REF_LOCAL_P (orig)))
2518 && NEED_GOT_RELOC)
2519 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2520 else
2521 {
2522 pic_ref = gen_rtx_MEM (Pmode,
2523 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2524 address));
2525 RTX_UNCHANGING_P (pic_ref) = 1;
2526 }
2527
2528 insn = emit_move_insn (reg, pic_ref);
2529 #endif
2530 current_function_uses_pic_offset_table = 1;
2531 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2532 by loop. */
2533 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2534 REG_NOTES (insn));
2535 return reg;
2536 }
2537 else if (GET_CODE (orig) == CONST)
2538 {
2539 rtx base, offset;
2540
2541 if (GET_CODE (XEXP (orig, 0)) == PLUS
2542 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2543 return orig;
2544
2545 if (reg == 0)
2546 {
2547 if (no_new_pseudos)
2548 abort ();
2549 else
2550 reg = gen_reg_rtx (Pmode);
2551 }
2552
2553 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2554 {
2555 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2556 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2557 base == reg ? 0 : reg);
2558 }
2559 else
2560 abort ();
2561
2562 if (GET_CODE (offset) == CONST_INT)
2563 {
2564 /* The base register doesn't really matter, we only want to
2565 test the index for the appropriate mode. */
2566 if (!arm_legitimate_index_p (mode, offset, 0))
2567 {
2568 if (!no_new_pseudos)
2569 offset = force_reg (Pmode, offset);
2570 else
2571 abort ();
2572 }
2573
2574 if (GET_CODE (offset) == CONST_INT)
2575 return plus_constant (base, INTVAL (offset));
2576 }
2577
2578 if (GET_MODE_SIZE (mode) > 4
2579 && (GET_MODE_CLASS (mode) == MODE_INT
2580 || TARGET_SOFT_FLOAT))
2581 {
2582 emit_insn (gen_addsi3 (reg, base, offset));
2583 return reg;
2584 }
2585
2586 return gen_rtx_PLUS (Pmode, base, offset);
2587 }
2588
2589 return orig;
2590 }
2591
2592 /* Generate code to load the PIC register. PROLOGUE is true if
2593 called from arm_expand_prologue (in which case we want the
2594 generated insns at the start of the function); false if called
2595 by an exception receiver that needs the PIC register reloaded
2596 (in which case the insns are just dumped at the current location). */
2597 void
2598 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2599 {
2600 #ifndef AOF_ASSEMBLER
2601 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2602 rtx global_offset_table;
2603
2604 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2605 return;
2606
2607 if (!flag_pic)
2608 abort ();
2609
2610 start_sequence ();
2611 l1 = gen_label_rtx ();
2612
2613 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2614 /* On the ARM the PC register contains 'dot + 8' at the time of the
2615 addition, on the Thumb it is 'dot + 4'. */
2616 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2617 if (GOT_PCREL)
2618 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2619 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2620 else
2621 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2622
2623 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2624
2625 if (TARGET_ARM)
2626 {
2627 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2628 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2629 }
2630 else
2631 {
2632 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2633 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2634 }
2635
2636 seq = get_insns ();
2637 end_sequence ();
2638 if (prologue)
2639 emit_insn_after (seq, get_insns ());
2640 else
2641 emit_insn (seq);
2642
2643 /* Need to emit this whether or not we obey regdecls,
2644 since setjmp/longjmp can cause life info to screw up. */
2645 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2646 #endif /* AOF_ASSEMBLER */
2647 }
2648
2649 /* Return nonzero if X is valid as an ARM state addressing register. */
2650 static int
2651 arm_address_register_rtx_p (rtx x, int strict_p)
2652 {
2653 int regno;
2654
2655 if (GET_CODE (x) != REG)
2656 return 0;
2657
2658 regno = REGNO (x);
2659
2660 if (strict_p)
2661 return ARM_REGNO_OK_FOR_BASE_P (regno);
2662
2663 return (regno <= LAST_ARM_REGNUM
2664 || regno >= FIRST_PSEUDO_REGISTER
2665 || regno == FRAME_POINTER_REGNUM
2666 || regno == ARG_POINTER_REGNUM);
2667 }
2668
2669 /* Return nonzero if X is a valid ARM state address operand. */
2670 int
2671 arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2672 {
2673 if (arm_address_register_rtx_p (x, strict_p))
2674 return 1;
2675
2676 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2677 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2678
2679 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2680 && GET_MODE_SIZE (mode) <= 4
2681 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2682 && GET_CODE (XEXP (x, 1)) == PLUS
2683 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2684 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p);
2685
2686 /* After reload constants split into minipools will have addresses
2687 from a LABEL_REF. */
2688 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2689 && (GET_CODE (x) == LABEL_REF
2690 || (GET_CODE (x) == CONST
2691 && GET_CODE (XEXP (x, 0)) == PLUS
2692 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2693 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2694 return 1;
2695
2696 else if (mode == TImode)
2697 return 0;
2698
2699 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2700 {
2701 if (GET_CODE (x) == PLUS
2702 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2703 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2704 {
2705 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2706
2707 if (val == 4 || val == -4 || val == -8)
2708 return 1;
2709 }
2710 }
2711
2712 else if (GET_CODE (x) == PLUS)
2713 {
2714 rtx xop0 = XEXP (x, 0);
2715 rtx xop1 = XEXP (x, 1);
2716
2717 return ((arm_address_register_rtx_p (xop0, strict_p)
2718 && arm_legitimate_index_p (mode, xop1, strict_p))
2719 || (arm_address_register_rtx_p (xop1, strict_p)
2720 && arm_legitimate_index_p (mode, xop0, strict_p)));
2721 }
2722
2723 #if 0
2724 /* Reload currently can't handle MINUS, so disable this for now */
2725 else if (GET_CODE (x) == MINUS)
2726 {
2727 rtx xop0 = XEXP (x, 0);
2728 rtx xop1 = XEXP (x, 1);
2729
2730 return (arm_address_register_rtx_p (xop0, strict_p)
2731 && arm_legitimate_index_p (mode, xop1, strict_p));
2732 }
2733 #endif
2734
2735 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2736 && GET_CODE (x) == SYMBOL_REF
2737 && CONSTANT_POOL_ADDRESS_P (x)
2738 && ! (flag_pic
2739 && symbol_mentioned_p (get_pool_constant (x))))
2740 return 1;
2741
2742 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2743 && (GET_MODE_SIZE (mode) <= 4)
2744 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
2745 return 1;
2746
2747 return 0;
2748 }
2749
2750 /* Return nonzero if INDEX is valid for an address index operand in
2751 ARM state. */
2752 static int
2753 arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
2754 {
2755 HOST_WIDE_INT range;
2756 enum rtx_code code = GET_CODE (index);
2757
2758 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
2759 return (code == CONST_INT && INTVAL (index) < 1024
2760 && INTVAL (index) > -1024
2761 && (INTVAL (index) & 3) == 0);
2762
2763 if (TARGET_CIRRUS
2764 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
2765 return (code == CONST_INT
2766 && INTVAL (index) < 255
2767 && INTVAL (index) > -255);
2768
2769 if (arm_address_register_rtx_p (index, strict_p)
2770 && GET_MODE_SIZE (mode) <= 4)
2771 return 1;
2772
2773 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
2774 return (code == CONST_INT
2775 && INTVAL (index) < 256
2776 && INTVAL (index) > -256);
2777
2778 /* XXX What about ldrsb? */
2779 if (GET_MODE_SIZE (mode) <= 4 && code == MULT
2780 && (!arm_arch4 || (mode) != HImode))
2781 {
2782 rtx xiop0 = XEXP (index, 0);
2783 rtx xiop1 = XEXP (index, 1);
2784
2785 return ((arm_address_register_rtx_p (xiop0, strict_p)
2786 && power_of_two_operand (xiop1, SImode))
2787 || (arm_address_register_rtx_p (xiop1, strict_p)
2788 && power_of_two_operand (xiop0, SImode)));
2789 }
2790
2791 if (GET_MODE_SIZE (mode) <= 4
2792 && (code == LSHIFTRT || code == ASHIFTRT
2793 || code == ASHIFT || code == ROTATERT)
2794 && (!arm_arch4 || (mode) != HImode))
2795 {
2796 rtx op = XEXP (index, 1);
2797
2798 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
2799 && GET_CODE (op) == CONST_INT
2800 && INTVAL (op) > 0
2801 && INTVAL (op) <= 31);
2802 }
2803
2804 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2805 load, but that has a restricted addressing range and we are unable
2806 to tell here whether that is the case. To be safe we restrict all
2807 loads to that range. */
2808 range = ((mode) == HImode || (mode) == QImode)
2809 ? (arm_arch4 ? 256 : 4095) : 4096;
2810
2811 return (code == CONST_INT
2812 && INTVAL (index) < range
2813 && INTVAL (index) > -range);
2814 }
2815
2816 /* Return nonzero if X is valid as an ARM state addressing register. */
2817 static int
2818 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
2819 {
2820 int regno;
2821
2822 if (GET_CODE (x) != REG)
2823 return 0;
2824
2825 regno = REGNO (x);
2826
2827 if (strict_p)
2828 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
2829
2830 return (regno <= LAST_LO_REGNUM
2831 || regno >= FIRST_PSEUDO_REGISTER
2832 || regno == FRAME_POINTER_REGNUM
2833 || (GET_MODE_SIZE (mode) >= 4
2834 && (regno == STACK_POINTER_REGNUM
2835 || x == hard_frame_pointer_rtx
2836 || x == arg_pointer_rtx)));
2837 }
2838
2839 /* Return nonzero if x is a legitimate index register. This is the case
2840 for any base register that can access a QImode object. */
2841 inline static int
2842 thumb_index_register_rtx_p (rtx x, int strict_p)
2843 {
2844 return thumb_base_register_rtx_p (x, QImode, strict_p);
2845 }
2846
2847 /* Return nonzero if x is a legitimate Thumb-state address.
2848
2849 The AP may be eliminated to either the SP or the FP, so we use the
2850 least common denominator, e.g. SImode, and offsets from 0 to 64.
2851
2852 ??? Verify whether the above is the right approach.
2853
2854 ??? Also, the FP may be eliminated to the SP, so perhaps that
2855 needs special handling also.
2856
2857 ??? Look at how the mips16 port solves this problem. It probably uses
2858 better ways to solve some of these problems.
2859
2860 Although it is not incorrect, we don't accept QImode and HImode
2861 addresses based on the frame pointer or arg pointer until the
2862 reload pass starts. This is so that eliminating such addresses
2863 into stack based ones won't produce impossible code. */
2864 int
2865 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2866 {
2867 /* ??? Not clear if this is right. Experiment. */
2868 if (GET_MODE_SIZE (mode) < 4
2869 && !(reload_in_progress || reload_completed)
2870 && (reg_mentioned_p (frame_pointer_rtx, x)
2871 || reg_mentioned_p (arg_pointer_rtx, x)
2872 || reg_mentioned_p (virtual_incoming_args_rtx, x)
2873 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
2874 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
2875 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
2876 return 0;
2877
2878 /* Accept any base register. SP only in SImode or larger. */
2879 else if (thumb_base_register_rtx_p (x, mode, strict_p))
2880 return 1;
2881
2882 /* This is PC relative data before arm_reorg runs. */
2883 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
2884 && GET_CODE (x) == SYMBOL_REF
2885 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
2886 return 1;
2887
2888 /* This is PC relative data after arm_reorg runs. */
2889 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2890 && (GET_CODE (x) == LABEL_REF
2891 || (GET_CODE (x) == CONST
2892 && GET_CODE (XEXP (x, 0)) == PLUS
2893 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2894 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2895 return 1;
2896
2897 /* Post-inc indexing only supported for SImode and larger. */
2898 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
2899 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
2900 return 1;
2901
2902 else if (GET_CODE (x) == PLUS)
2903 {
2904 /* REG+REG address can be any two index registers. */
2905 /* We disallow FRAME+REG addressing since we know that FRAME
2906 will be replaced with STACK, and SP relative addressing only
2907 permits SP+OFFSET. */
2908 if (GET_MODE_SIZE (mode) <= 4
2909 && XEXP (x, 0) != frame_pointer_rtx
2910 && XEXP (x, 1) != frame_pointer_rtx
2911 && XEXP (x, 0) != virtual_stack_vars_rtx
2912 && XEXP (x, 1) != virtual_stack_vars_rtx
2913 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2914 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
2915 return 1;
2916
2917 /* REG+const has 5-7 bit offset for non-SP registers. */
2918 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2919 || XEXP (x, 0) == arg_pointer_rtx)
2920 && GET_CODE (XEXP (x, 1)) == CONST_INT
2921 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
2922 return 1;
2923
2924 /* REG+const has 10 bit offset for SP, but only SImode and
2925 larger is supported. */
2926 /* ??? Should probably check for DI/DFmode overflow here
2927 just like GO_IF_LEGITIMATE_OFFSET does. */
2928 else if (GET_CODE (XEXP (x, 0)) == REG
2929 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
2930 && GET_MODE_SIZE (mode) >= 4
2931 && GET_CODE (XEXP (x, 1)) == CONST_INT
2932 && INTVAL (XEXP (x, 1)) >= 0
2933 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
2934 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2935 return 1;
2936
2937 else if (GET_CODE (XEXP (x, 0)) == REG
2938 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
2939 && GET_MODE_SIZE (mode) >= 4
2940 && GET_CODE (XEXP (x, 1)) == CONST_INT
2941 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2942 return 1;
2943 }
2944
2945 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2946 && GET_CODE (x) == SYMBOL_REF
2947 && CONSTANT_POOL_ADDRESS_P (x)
2948 && !(flag_pic
2949 && symbol_mentioned_p (get_pool_constant (x))))
2950 return 1;
2951
2952 return 0;
2953 }
2954
2955 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
2956 instruction of mode MODE. */
2957 int
2958 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
2959 {
2960 switch (GET_MODE_SIZE (mode))
2961 {
2962 case 1:
2963 return val >= 0 && val < 32;
2964
2965 case 2:
2966 return val >= 0 && val < 64 && (val & 1) == 0;
2967
2968 default:
2969 return (val >= 0
2970 && (val + GET_MODE_SIZE (mode)) <= 128
2971 && (val & 3) == 0);
2972 }
2973 }
2974
2975 /* Try machine-dependent ways of modifying an illegitimate address
2976 to be legitimate. If we find one, return the new, valid address. */
2977 rtx
2978 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
2979 {
2980 if (GET_CODE (x) == PLUS)
2981 {
2982 rtx xop0 = XEXP (x, 0);
2983 rtx xop1 = XEXP (x, 1);
2984
2985 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
2986 xop0 = force_reg (SImode, xop0);
2987
2988 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
2989 xop1 = force_reg (SImode, xop1);
2990
2991 if (ARM_BASE_REGISTER_RTX_P (xop0)
2992 && GET_CODE (xop1) == CONST_INT)
2993 {
2994 HOST_WIDE_INT n, low_n;
2995 rtx base_reg, val;
2996 n = INTVAL (xop1);
2997
2998 if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2999 {
3000 low_n = n & 0x0f;
3001 n &= ~0x0f;
3002 if (low_n > 4)
3003 {
3004 n += 16;
3005 low_n -= 16;
3006 }
3007 }
3008 else
3009 {
3010 low_n = ((mode) == TImode ? 0
3011 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3012 n -= low_n;
3013 }
3014
3015 base_reg = gen_reg_rtx (SImode);
3016 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3017 GEN_INT (n)), NULL_RTX);
3018 emit_move_insn (base_reg, val);
3019 x = (low_n == 0 ? base_reg
3020 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3021 }
3022 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3023 x = gen_rtx_PLUS (SImode, xop0, xop1);
3024 }
3025
3026 /* XXX We don't allow MINUS any more -- see comment in
3027 arm_legitimate_address_p (). */
3028 else if (GET_CODE (x) == MINUS)
3029 {
3030 rtx xop0 = XEXP (x, 0);
3031 rtx xop1 = XEXP (x, 1);
3032
3033 if (CONSTANT_P (xop0))
3034 xop0 = force_reg (SImode, xop0);
3035
3036 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3037 xop1 = force_reg (SImode, xop1);
3038
3039 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3040 x = gen_rtx_MINUS (SImode, xop0, xop1);
3041 }
3042
3043 if (flag_pic)
3044 {
3045 /* We need to find and carefully transform any SYMBOL and LABEL
3046 references; so go back to the original address expression. */
3047 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3048
3049 if (new_x != orig_x)
3050 x = new_x;
3051 }
3052
3053 return x;
3054 }
3055
3056 \f
3057
3058 #define REG_OR_SUBREG_REG(X) \
3059 (GET_CODE (X) == REG \
3060 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3061
3062 #define REG_OR_SUBREG_RTX(X) \
3063 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3064
3065 #ifndef COSTS_N_INSNS
3066 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3067 #endif
3068 /* Worker routine for arm_rtx_costs. */
3069 static inline int
3070 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3071 {
3072 enum machine_mode mode = GET_MODE (x);
3073 enum rtx_code subcode;
3074 int extra_cost;
3075
3076 if (TARGET_THUMB)
3077 {
3078 switch (code)
3079 {
3080 case ASHIFT:
3081 case ASHIFTRT:
3082 case LSHIFTRT:
3083 case ROTATERT:
3084 case PLUS:
3085 case MINUS:
3086 case COMPARE:
3087 case NEG:
3088 case NOT:
3089 return COSTS_N_INSNS (1);
3090
3091 case MULT:
3092 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3093 {
3094 int cycles = 0;
3095 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3096
3097 while (i)
3098 {
3099 i >>= 2;
3100 cycles++;
3101 }
3102 return COSTS_N_INSNS (2) + cycles;
3103 }
3104 return COSTS_N_INSNS (1) + 16;
3105
3106 case SET:
3107 return (COSTS_N_INSNS (1)
3108 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3109 + GET_CODE (SET_DEST (x)) == MEM));
3110
3111 case CONST_INT:
3112 if (outer == SET)
3113 {
3114 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3115 return 0;
3116 if (thumb_shiftable_const (INTVAL (x)))
3117 return COSTS_N_INSNS (2);
3118 return COSTS_N_INSNS (3);
3119 }
3120 else if (outer == PLUS
3121 && INTVAL (x) < 256 && INTVAL (x) > -256)
3122 return 0;
3123 else if (outer == COMPARE
3124 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3125 return 0;
3126 else if (outer == ASHIFT || outer == ASHIFTRT
3127 || outer == LSHIFTRT)
3128 return 0;
3129 return COSTS_N_INSNS (2);
3130
3131 case CONST:
3132 case CONST_DOUBLE:
3133 case LABEL_REF:
3134 case SYMBOL_REF:
3135 return COSTS_N_INSNS (3);
3136
3137 case UDIV:
3138 case UMOD:
3139 case DIV:
3140 case MOD:
3141 return 100;
3142
3143 case TRUNCATE:
3144 return 99;
3145
3146 case AND:
3147 case XOR:
3148 case IOR:
3149 /* XXX guess. */
3150 return 8;
3151
3152 case ADDRESSOF:
3153 case MEM:
3154 /* XXX another guess. */
3155 /* Memory costs quite a lot for the first word, but subsequent words
3156 load at the equivalent of a single insn each. */
3157 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3158 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3159 ? 4 : 0));
3160
3161 case IF_THEN_ELSE:
3162 /* XXX a guess. */
3163 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3164 return 14;
3165 return 2;
3166
3167 case ZERO_EXTEND:
3168 /* XXX still guessing. */
3169 switch (GET_MODE (XEXP (x, 0)))
3170 {
3171 case QImode:
3172 return (1 + (mode == DImode ? 4 : 0)
3173 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3174
3175 case HImode:
3176 return (4 + (mode == DImode ? 4 : 0)
3177 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3178
3179 case SImode:
3180 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3181
3182 default:
3183 return 99;
3184 }
3185
3186 default:
3187 return 99;
3188 }
3189 }
3190
3191 switch (code)
3192 {
3193 case MEM:
3194 /* Memory costs quite a lot for the first word, but subsequent words
3195 load at the equivalent of a single insn each. */
3196 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3197 + (GET_CODE (x) == SYMBOL_REF
3198 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3199
3200 case DIV:
3201 case MOD:
3202 return 100;
3203
3204 case ROTATE:
3205 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3206 return 4;
3207 /* Fall through */
3208 case ROTATERT:
3209 if (mode != SImode)
3210 return 8;
3211 /* Fall through */
3212 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3213 if (mode == DImode)
3214 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3215 + ((GET_CODE (XEXP (x, 0)) == REG
3216 || (GET_CODE (XEXP (x, 0)) == SUBREG
3217 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3218 ? 0 : 8));
3219 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3220 || (GET_CODE (XEXP (x, 0)) == SUBREG
3221 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3222 ? 0 : 4)
3223 + ((GET_CODE (XEXP (x, 1)) == REG
3224 || (GET_CODE (XEXP (x, 1)) == SUBREG
3225 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3226 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3227 ? 0 : 4));
3228
3229 case MINUS:
3230 if (mode == DImode)
3231 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3232 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3233 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3234 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3235 ? 0 : 8));
3236
3237 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3238 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3239 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3240 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3241 ? 0 : 8)
3242 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3243 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3244 && const_double_rtx_ok_for_fpa (XEXP (x, 0))))
3245 ? 0 : 8));
3246
3247 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3248 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3249 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3250 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3251 || subcode == ASHIFTRT || subcode == LSHIFTRT
3252 || subcode == ROTATE || subcode == ROTATERT
3253 || (subcode == MULT
3254 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3255 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3256 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3257 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3258 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3259 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3260 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3261 return 1;
3262 /* Fall through */
3263
3264 case PLUS:
3265 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3266 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3267 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3268 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3269 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3270 ? 0 : 8));
3271
3272 /* Fall through */
3273 case AND: case XOR: case IOR:
3274 extra_cost = 0;
3275
3276 /* Normally the frame registers will be spilt into reg+const during
3277 reload, so it is a bad idea to combine them with other instructions,
3278 since then they might not be moved outside of loops. As a compromise
3279 we allow integration with ops that have a constant as their second
3280 operand. */
3281 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3282 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3283 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3284 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3285 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3286 extra_cost = 4;
3287
3288 if (mode == DImode)
3289 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3290 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3291 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3292 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3293 ? 0 : 8));
3294
3295 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3296 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3297 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3298 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3299 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3300 ? 0 : 4));
3301
3302 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3303 return (1 + extra_cost
3304 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3305 || subcode == LSHIFTRT || subcode == ASHIFTRT
3306 || subcode == ROTATE || subcode == ROTATERT
3307 || (subcode == MULT
3308 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3309 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3310 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3311 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3312 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3313 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3314 ? 0 : 4));
3315
3316 return 8;
3317
3318 case MULT:
3319 /* There is no point basing this on the tuning, since it is always the
3320 fast variant if it exists at all. */
3321 if (arm_fast_multiply && mode == DImode
3322 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3323 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3324 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3325 return 8;
3326
3327 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3328 || mode == DImode)
3329 return 30;
3330
3331 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3332 {
3333 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3334 & (unsigned HOST_WIDE_INT) 0xffffffff);
3335 int add_cost = const_ok_for_arm (i) ? 4 : 8;
3336 int j;
3337
3338 /* Tune as appropriate. */
3339 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
3340
3341 for (j = 0; i && j < 32; j += booth_unit_size)
3342 {
3343 i >>= booth_unit_size;
3344 add_cost += 2;
3345 }
3346
3347 return add_cost;
3348 }
3349
3350 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
3351 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3352 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
3353
3354 case TRUNCATE:
3355 if (arm_fast_multiply && mode == SImode
3356 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3357 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3358 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3359 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3360 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3361 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3362 return 8;
3363 return 99;
3364
3365 case NEG:
3366 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3367 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3368 /* Fall through */
3369 case NOT:
3370 if (mode == DImode)
3371 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3372
3373 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3374
3375 case IF_THEN_ELSE:
3376 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3377 return 14;
3378 return 2;
3379
3380 case COMPARE:
3381 return 1;
3382
3383 case ABS:
3384 return 4 + (mode == DImode ? 4 : 0);
3385
3386 case SIGN_EXTEND:
3387 if (GET_MODE (XEXP (x, 0)) == QImode)
3388 return (4 + (mode == DImode ? 4 : 0)
3389 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3390 /* Fall through */
3391 case ZERO_EXTEND:
3392 switch (GET_MODE (XEXP (x, 0)))
3393 {
3394 case QImode:
3395 return (1 + (mode == DImode ? 4 : 0)
3396 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3397
3398 case HImode:
3399 return (4 + (mode == DImode ? 4 : 0)
3400 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3401
3402 case SImode:
3403 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3404
3405 case V8QImode:
3406 case V4HImode:
3407 case V2SImode:
3408 case V4QImode:
3409 case V2HImode:
3410 return 1;
3411
3412 default:
3413 break;
3414 }
3415 abort ();
3416
3417 case CONST_INT:
3418 if (const_ok_for_arm (INTVAL (x)))
3419 return outer == SET ? 2 : -1;
3420 else if (outer == AND
3421 && const_ok_for_arm (~INTVAL (x)))
3422 return -1;
3423 else if ((outer == COMPARE
3424 || outer == PLUS || outer == MINUS)
3425 && const_ok_for_arm (-INTVAL (x)))
3426 return -1;
3427 else
3428 return 5;
3429
3430 case CONST:
3431 case LABEL_REF:
3432 case SYMBOL_REF:
3433 return 6;
3434
3435 case CONST_DOUBLE:
3436 if (const_double_rtx_ok_for_fpa (x))
3437 return outer == SET ? 2 : -1;
3438 else if ((outer == COMPARE || outer == PLUS)
3439 && neg_const_double_rtx_ok_for_fpa (x))
3440 return -1;
3441 return 7;
3442
3443 default:
3444 return 99;
3445 }
3446 }
3447
3448 static bool
3449 arm_rtx_costs (rtx x, int code, int outer_code, int *total)
3450 {
3451 *total = arm_rtx_costs_1 (x, code, outer_code);
3452 return true;
3453 }
3454
3455 /* All address computations that can be done are free, but rtx cost returns
3456 the same for practically all of them. So we weight the different types
3457 of address here in the order (most pref first):
3458 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3459 static int
3460 arm_address_cost (rtx x)
3461 {
3462 #define ARM_ADDRESS_COST(X) \
3463 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
3464 || GET_CODE (X) == SYMBOL_REF) \
3465 ? 0 \
3466 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
3467 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
3468 ? 10 \
3469 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
3470 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
3471 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
3472 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
3473 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
3474 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
3475 ? 1 : 0)) \
3476 : 4)))))
3477
3478 #define THUMB_ADDRESS_COST(X) \
3479 ((GET_CODE (X) == REG \
3480 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
3481 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
3482 ? 1 : 2)
3483
3484 return (TARGET_ARM ? ARM_ADDRESS_COST (x) : THUMB_ADDRESS_COST (x));
3485 }
3486
3487 static int
3488 arm_use_dfa_pipeline_interface (void)
3489 {
3490 return true;
3491 }
3492
3493 static int
3494 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
3495 {
3496 rtx i_pat, d_pat;
3497
3498 /* Some true dependencies can have a higher cost depending
3499 on precisely how certain input operands are used. */
3500 if (arm_tune_xscale
3501 && REG_NOTE_KIND (link) == 0
3502 && recog_memoized (insn) >= 0
3503 && recog_memoized (dep) >= 0)
3504 {
3505 int shift_opnum = get_attr_shift (insn);
3506 enum attr_type attr_type = get_attr_type (dep);
3507
3508 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3509 operand for INSN. If we have a shifted input operand and the
3510 instruction we depend on is another ALU instruction, then we may
3511 have to account for an additional stall. */
3512 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
3513 {
3514 rtx shifted_operand;
3515 int opno;
3516
3517 /* Get the shifted operand. */
3518 extract_insn (insn);
3519 shifted_operand = recog_data.operand[shift_opnum];
3520
3521 /* Iterate over all the operands in DEP. If we write an operand
3522 that overlaps with SHIFTED_OPERAND, then we have increase the
3523 cost of this dependency. */
3524 extract_insn (dep);
3525 preprocess_constraints ();
3526 for (opno = 0; opno < recog_data.n_operands; opno++)
3527 {
3528 /* We can ignore strict inputs. */
3529 if (recog_data.operand_type[opno] == OP_IN)
3530 continue;
3531
3532 if (reg_overlap_mentioned_p (recog_data.operand[opno],
3533 shifted_operand))
3534 return 2;
3535 }
3536 }
3537 }
3538
3539 /* XXX This is not strictly true for the FPA. */
3540 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
3541 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3542 return 0;
3543
3544 /* Call insns don't incur a stall, even if they follow a load. */
3545 if (REG_NOTE_KIND (link) == 0
3546 && GET_CODE (insn) == CALL_INSN)
3547 return 1;
3548
3549 if ((i_pat = single_set (insn)) != NULL
3550 && GET_CODE (SET_SRC (i_pat)) == MEM
3551 && (d_pat = single_set (dep)) != NULL
3552 && GET_CODE (SET_DEST (d_pat)) == MEM)
3553 {
3554 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3555 /* This is a load after a store, there is no conflict if the load reads
3556 from a cached area. Assume that loads from the stack, and from the
3557 constant pool are cached, and that others will miss. This is a
3558 hack. */
3559
3560 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3561 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3562 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3563 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3564 return 1;
3565 }
3566
3567 return cost;
3568 }
3569
3570 static int fpa_consts_inited = 0;
3571
3572 static const char * const strings_fpa[8] =
3573 {
3574 "0", "1", "2", "3",
3575 "4", "5", "0.5", "10"
3576 };
3577
3578 static REAL_VALUE_TYPE values_fpa[8];
3579
3580 static void
3581 init_fpa_table (void)
3582 {
3583 int i;
3584 REAL_VALUE_TYPE r;
3585
3586 for (i = 0; i < 8; i++)
3587 {
3588 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
3589 values_fpa[i] = r;
3590 }
3591
3592 fpa_consts_inited = 1;
3593 }
3594
3595 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3596 int
3597 const_double_rtx_ok_for_fpa (rtx x)
3598 {
3599 REAL_VALUE_TYPE r;
3600 int i;
3601
3602 if (!fpa_consts_inited)
3603 init_fpa_table ();
3604
3605 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3606 if (REAL_VALUE_MINUS_ZERO (r))
3607 return 0;
3608
3609 for (i = 0; i < 8; i++)
3610 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3611 return 1;
3612
3613 return 0;
3614 }
3615
3616 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3617 int
3618 neg_const_double_rtx_ok_for_fpa (rtx x)
3619 {
3620 REAL_VALUE_TYPE r;
3621 int i;
3622
3623 if (!fpa_consts_inited)
3624 init_fpa_table ();
3625
3626 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3627 r = REAL_VALUE_NEGATE (r);
3628 if (REAL_VALUE_MINUS_ZERO (r))
3629 return 0;
3630
3631 for (i = 0; i < 8; i++)
3632 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3633 return 1;
3634
3635 return 0;
3636 }
3637 \f
3638 /* Predicates for `match_operand' and `match_operator'. */
3639
3640 /* s_register_operand is the same as register_operand, but it doesn't accept
3641 (SUBREG (MEM)...).
3642
3643 This function exists because at the time it was put in it led to better
3644 code. SUBREG(MEM) always needs a reload in the places where
3645 s_register_operand is used, and this seemed to lead to excessive
3646 reloading. */
3647 int
3648 s_register_operand (rtx op, enum machine_mode mode)
3649 {
3650 if (GET_MODE (op) != mode && mode != VOIDmode)
3651 return 0;
3652
3653 if (GET_CODE (op) == SUBREG)
3654 op = SUBREG_REG (op);
3655
3656 /* We don't consider registers whose class is NO_REGS
3657 to be a register operand. */
3658 /* XXX might have to check for lo regs only for thumb ??? */
3659 return (GET_CODE (op) == REG
3660 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3661 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3662 }
3663
3664 /* A hard register operand (even before reload. */
3665 int
3666 arm_hard_register_operand (rtx op, enum machine_mode mode)
3667 {
3668 if (GET_MODE (op) != mode && mode != VOIDmode)
3669 return 0;
3670
3671 return (GET_CODE (op) == REG
3672 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3673 }
3674
3675 /* Only accept reg, subreg(reg), const_int. */
3676 int
3677 reg_or_int_operand (rtx op, enum machine_mode mode)
3678 {
3679 if (GET_CODE (op) == CONST_INT)
3680 return 1;
3681
3682 if (GET_MODE (op) != mode && mode != VOIDmode)
3683 return 0;
3684
3685 if (GET_CODE (op) == SUBREG)
3686 op = SUBREG_REG (op);
3687
3688 /* We don't consider registers whose class is NO_REGS
3689 to be a register operand. */
3690 return (GET_CODE (op) == REG
3691 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3692 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3693 }
3694
3695 /* Return 1 if OP is an item in memory, given that we are in reload. */
3696 int
3697 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3698 {
3699 int regno = true_regnum (op);
3700
3701 return (!CONSTANT_P (op)
3702 && (regno == -1
3703 || (GET_CODE (op) == REG
3704 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3705 }
3706
3707 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3708 memory access (architecture V4).
3709 MODE is QImode if called when computing constraints, or VOIDmode when
3710 emitting patterns. In this latter case we cannot use memory_operand()
3711 because it will fail on badly formed MEMs, which is precisely what we are
3712 trying to catch. */
3713 int
3714 bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3715 {
3716 if (GET_CODE (op) != MEM)
3717 return 0;
3718
3719 op = XEXP (op, 0);
3720
3721 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3722 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3723 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3724 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3725 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3726 return 1;
3727
3728 /* Big constants are also bad. */
3729 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3730 && (INTVAL (XEXP (op, 1)) > 0xff
3731 || -INTVAL (XEXP (op, 1)) > 0xff))
3732 return 1;
3733
3734 /* Everything else is good, or can will automatically be made so. */
3735 return 0;
3736 }
3737
3738 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3739 int
3740 arm_rhs_operand (rtx op, enum machine_mode mode)
3741 {
3742 return (s_register_operand (op, mode)
3743 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3744 }
3745
3746 /* Return TRUE for valid operands for the
3747 rhs of an ARM instruction, or a load. */
3748 int
3749 arm_rhsm_operand (rtx op, enum machine_mode mode)
3750 {
3751 return (s_register_operand (op, mode)
3752 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3753 || memory_operand (op, mode));
3754 }
3755
3756 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3757 constant that is valid when negated. */
3758 int
3759 arm_add_operand (rtx op, enum machine_mode mode)
3760 {
3761 if (TARGET_THUMB)
3762 return thumb_cmp_operand (op, mode);
3763
3764 return (s_register_operand (op, mode)
3765 || (GET_CODE (op) == CONST_INT
3766 && (const_ok_for_arm (INTVAL (op))
3767 || const_ok_for_arm (-INTVAL (op)))));
3768 }
3769
3770 /* Return TRUE for valid ARM constants (or when valid if negated). */
3771 int
3772 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3773 {
3774 return (GET_CODE (op) == CONST_INT
3775 && (const_ok_for_arm (INTVAL (op))
3776 || const_ok_for_arm (-INTVAL (op))));
3777 }
3778
3779 int
3780 arm_not_operand (rtx op, enum machine_mode mode)
3781 {
3782 return (s_register_operand (op, mode)
3783 || (GET_CODE (op) == CONST_INT
3784 && (const_ok_for_arm (INTVAL (op))
3785 || const_ok_for_arm (~INTVAL (op)))));
3786 }
3787
3788 /* Return TRUE if the operand is a memory reference which contains an
3789 offsettable address. */
3790 int
3791 offsettable_memory_operand (rtx op, enum machine_mode mode)
3792 {
3793 if (mode == VOIDmode)
3794 mode = GET_MODE (op);
3795
3796 return (mode == GET_MODE (op)
3797 && GET_CODE (op) == MEM
3798 && offsettable_address_p (reload_completed | reload_in_progress,
3799 mode, XEXP (op, 0)));
3800 }
3801
3802 /* Return TRUE if the operand is a memory reference which is, or can be
3803 made word aligned by adjusting the offset. */
3804 int
3805 alignable_memory_operand (rtx op, enum machine_mode mode)
3806 {
3807 rtx reg;
3808
3809 if (mode == VOIDmode)
3810 mode = GET_MODE (op);
3811
3812 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3813 return 0;
3814
3815 op = XEXP (op, 0);
3816
3817 return ((GET_CODE (reg = op) == REG
3818 || (GET_CODE (op) == SUBREG
3819 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3820 || (GET_CODE (op) == PLUS
3821 && GET_CODE (XEXP (op, 1)) == CONST_INT
3822 && (GET_CODE (reg = XEXP (op, 0)) == REG
3823 || (GET_CODE (XEXP (op, 0)) == SUBREG
3824 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3825 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3826 }
3827
3828 /* Similar to s_register_operand, but does not allow hard integer
3829 registers. */
3830 int
3831 f_register_operand (rtx op, enum machine_mode mode)
3832 {
3833 if (GET_MODE (op) != mode && mode != VOIDmode)
3834 return 0;
3835
3836 if (GET_CODE (op) == SUBREG)
3837 op = SUBREG_REG (op);
3838
3839 /* We don't consider registers whose class is NO_REGS
3840 to be a register operand. */
3841 return (GET_CODE (op) == REG
3842 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3843 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
3844 }
3845
3846 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3847 int
3848 fpa_rhs_operand (rtx op, enum machine_mode mode)
3849 {
3850 if (s_register_operand (op, mode))
3851 return TRUE;
3852
3853 if (GET_MODE (op) != mode && mode != VOIDmode)
3854 return FALSE;
3855
3856 if (GET_CODE (op) == CONST_DOUBLE)
3857 return const_double_rtx_ok_for_fpa (op);
3858
3859 return FALSE;
3860 }
3861
3862 int
3863 fpa_add_operand (rtx op, enum machine_mode mode)
3864 {
3865 if (s_register_operand (op, mode))
3866 return TRUE;
3867
3868 if (GET_MODE (op) != mode && mode != VOIDmode)
3869 return FALSE;
3870
3871 if (GET_CODE (op) == CONST_DOUBLE)
3872 return (const_double_rtx_ok_for_fpa (op)
3873 || neg_const_double_rtx_ok_for_fpa (op));
3874
3875 return FALSE;
3876 }
3877
3878 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3879 int
3880 cirrus_memory_offset (rtx op)
3881 {
3882 /* Reject eliminable registers. */
3883 if (! (reload_in_progress || reload_completed)
3884 && ( reg_mentioned_p (frame_pointer_rtx, op)
3885 || reg_mentioned_p (arg_pointer_rtx, op)
3886 || reg_mentioned_p (virtual_incoming_args_rtx, op)
3887 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
3888 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
3889 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
3890 return 0;
3891
3892 if (GET_CODE (op) == MEM)
3893 {
3894 rtx ind;
3895
3896 ind = XEXP (op, 0);
3897
3898 /* Match: (mem (reg)). */
3899 if (GET_CODE (ind) == REG)
3900 return 1;
3901
3902 /* Match:
3903 (mem (plus (reg)
3904 (const))). */
3905 if (GET_CODE (ind) == PLUS
3906 && GET_CODE (XEXP (ind, 0)) == REG
3907 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
3908 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
3909 return 1;
3910 }
3911
3912 return 0;
3913 }
3914
3915 /* Return nonzero if OP is a Cirrus or general register. */
3916 int
3917 cirrus_register_operand (rtx op, enum machine_mode mode)
3918 {
3919 if (GET_MODE (op) != mode && mode != VOIDmode)
3920 return FALSE;
3921
3922 if (GET_CODE (op) == SUBREG)
3923 op = SUBREG_REG (op);
3924
3925 return (GET_CODE (op) == REG
3926 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
3927 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
3928 }
3929
3930 /* Return nonzero if OP is a cirrus FP register. */
3931 int
3932 cirrus_fp_register (rtx op, enum machine_mode mode)
3933 {
3934 if (GET_MODE (op) != mode && mode != VOIDmode)
3935 return FALSE;
3936
3937 if (GET_CODE (op) == SUBREG)
3938 op = SUBREG_REG (op);
3939
3940 return (GET_CODE (op) == REG
3941 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3942 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
3943 }
3944
3945 /* Return nonzero if OP is a 6bit constant (0..63). */
3946 int
3947 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3948 {
3949 return (GET_CODE (op) == CONST_INT
3950 && INTVAL (op) >= 0
3951 && INTVAL (op) < 64);
3952 }
3953
3954 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
3955 Use by the Cirrus Maverick code which has to workaround
3956 a hardware bug triggered by such instructions. */
3957 static bool
3958 arm_memory_load_p (rtx insn)
3959 {
3960 rtx body, lhs, rhs;;
3961
3962 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
3963 return false;
3964
3965 body = PATTERN (insn);
3966
3967 if (GET_CODE (body) != SET)
3968 return false;
3969
3970 lhs = XEXP (body, 0);
3971 rhs = XEXP (body, 1);
3972
3973 lhs = REG_OR_SUBREG_RTX (lhs);
3974
3975 /* If the destination is not a general purpose
3976 register we do not have to worry. */
3977 if (GET_CODE (lhs) != REG
3978 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
3979 return false;
3980
3981 /* As well as loads from memory we also have to react
3982 to loads of invalid constants which will be turned
3983 into loads from the minipool. */
3984 return (GET_CODE (rhs) == MEM
3985 || GET_CODE (rhs) == SYMBOL_REF
3986 || note_invalid_constants (insn, -1, false));
3987 }
3988
3989 /* Return TRUE if INSN is a Cirrus instruction. */
3990 static bool
3991 arm_cirrus_insn_p (rtx insn)
3992 {
3993 enum attr_cirrus attr;
3994
3995 /* get_attr aborts on USE and CLOBBER. */
3996 if (!insn
3997 || GET_CODE (insn) != INSN
3998 || GET_CODE (PATTERN (insn)) == USE
3999 || GET_CODE (PATTERN (insn)) == CLOBBER)
4000 return 0;
4001
4002 attr = get_attr_cirrus (insn);
4003
4004 return attr != CIRRUS_NOT;
4005 }
4006
4007 /* Cirrus reorg for invalid instruction combinations. */
4008 static void
4009 cirrus_reorg (rtx first)
4010 {
4011 enum attr_cirrus attr;
4012 rtx body = PATTERN (first);
4013 rtx t;
4014 int nops;
4015
4016 /* Any branch must be followed by 2 non Cirrus instructions. */
4017 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4018 {
4019 nops = 0;
4020 t = next_nonnote_insn (first);
4021
4022 if (arm_cirrus_insn_p (t))
4023 ++ nops;
4024
4025 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4026 ++ nops;
4027
4028 while (nops --)
4029 emit_insn_after (gen_nop (), first);
4030
4031 return;
4032 }
4033
4034 /* (float (blah)) is in parallel with a clobber. */
4035 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4036 body = XVECEXP (body, 0, 0);
4037
4038 if (GET_CODE (body) == SET)
4039 {
4040 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4041
4042 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4043 be followed by a non Cirrus insn. */
4044 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4045 {
4046 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4047 emit_insn_after (gen_nop (), first);
4048
4049 return;
4050 }
4051 else if (arm_memory_load_p (first))
4052 {
4053 unsigned int arm_regno;
4054
4055 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4056 ldr/cfmv64hr combination where the Rd field is the same
4057 in both instructions must be split with a non Cirrus
4058 insn. Example:
4059
4060 ldr r0, blah
4061 nop
4062 cfmvsr mvf0, r0. */
4063
4064 /* Get Arm register number for ldr insn. */
4065 if (GET_CODE (lhs) == REG)
4066 arm_regno = REGNO (lhs);
4067 else if (GET_CODE (rhs) == REG)
4068 arm_regno = REGNO (rhs);
4069 else
4070 abort ();
4071
4072 /* Next insn. */
4073 first = next_nonnote_insn (first);
4074
4075 if (! arm_cirrus_insn_p (first))
4076 return;
4077
4078 body = PATTERN (first);
4079
4080 /* (float (blah)) is in parallel with a clobber. */
4081 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4082 body = XVECEXP (body, 0, 0);
4083
4084 if (GET_CODE (body) == FLOAT)
4085 body = XEXP (body, 0);
4086
4087 if (get_attr_cirrus (first) == CIRRUS_MOVE
4088 && GET_CODE (XEXP (body, 1)) == REG
4089 && arm_regno == REGNO (XEXP (body, 1)))
4090 emit_insn_after (gen_nop (), first);
4091
4092 return;
4093 }
4094 }
4095
4096 /* get_attr aborts on USE and CLOBBER. */
4097 if (!first
4098 || GET_CODE (first) != INSN
4099 || GET_CODE (PATTERN (first)) == USE
4100 || GET_CODE (PATTERN (first)) == CLOBBER)
4101 return;
4102
4103 attr = get_attr_cirrus (first);
4104
4105 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4106 must be followed by a non-coprocessor instruction. */
4107 if (attr == CIRRUS_COMPARE)
4108 {
4109 nops = 0;
4110
4111 t = next_nonnote_insn (first);
4112
4113 if (arm_cirrus_insn_p (t))
4114 ++ nops;
4115
4116 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4117 ++ nops;
4118
4119 while (nops --)
4120 emit_insn_after (gen_nop (), first);
4121
4122 return;
4123 }
4124 }
4125
4126 /* Return nonzero if OP is a constant power of two. */
4127 int
4128 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4129 {
4130 if (GET_CODE (op) == CONST_INT)
4131 {
4132 HOST_WIDE_INT value = INTVAL (op);
4133
4134 return value != 0 && (value & (value - 1)) == 0;
4135 }
4136
4137 return FALSE;
4138 }
4139
4140 /* Return TRUE for a valid operand of a DImode operation.
4141 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4142 Note that this disallows MEM(REG+REG), but allows
4143 MEM(PRE/POST_INC/DEC(REG)). */
4144 int
4145 di_operand (rtx op, enum machine_mode mode)
4146 {
4147 if (s_register_operand (op, mode))
4148 return TRUE;
4149
4150 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4151 return FALSE;
4152
4153 if (GET_CODE (op) == SUBREG)
4154 op = SUBREG_REG (op);
4155
4156 switch (GET_CODE (op))
4157 {
4158 case CONST_DOUBLE:
4159 case CONST_INT:
4160 return TRUE;
4161
4162 case MEM:
4163 return memory_address_p (DImode, XEXP (op, 0));
4164
4165 default:
4166 return FALSE;
4167 }
4168 }
4169
4170 /* Like di_operand, but don't accept constants. */
4171 int
4172 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4173 {
4174 if (s_register_operand (op, mode))
4175 return TRUE;
4176
4177 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4178 return FALSE;
4179
4180 if (GET_CODE (op) == SUBREG)
4181 op = SUBREG_REG (op);
4182
4183 if (GET_CODE (op) == MEM)
4184 return memory_address_p (DImode, XEXP (op, 0));
4185
4186 return FALSE;
4187 }
4188
4189 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4190 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4191 Note that this disallows MEM(REG+REG), but allows
4192 MEM(PRE/POST_INC/DEC(REG)). */
4193 int
4194 soft_df_operand (rtx op, enum machine_mode mode)
4195 {
4196 if (s_register_operand (op, mode))
4197 return TRUE;
4198
4199 if (mode != VOIDmode && GET_MODE (op) != mode)
4200 return FALSE;
4201
4202 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4203 return FALSE;
4204
4205 if (GET_CODE (op) == SUBREG)
4206 op = SUBREG_REG (op);
4207
4208 switch (GET_CODE (op))
4209 {
4210 case CONST_DOUBLE:
4211 return TRUE;
4212
4213 case MEM:
4214 return memory_address_p (DFmode, XEXP (op, 0));
4215
4216 default:
4217 return FALSE;
4218 }
4219 }
4220
4221 /* Like soft_df_operand, but don't accept constants. */
4222 int
4223 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4224 {
4225 if (s_register_operand (op, mode))
4226 return TRUE;
4227
4228 if (mode != VOIDmode && GET_MODE (op) != mode)
4229 return FALSE;
4230
4231 if (GET_CODE (op) == SUBREG)
4232 op = SUBREG_REG (op);
4233
4234 if (GET_CODE (op) == MEM)
4235 return memory_address_p (DFmode, XEXP (op, 0));
4236 return FALSE;
4237 }
4238
4239 /* Return TRUE for valid index operands. */
4240 int
4241 index_operand (rtx op, enum machine_mode mode)
4242 {
4243 return (s_register_operand (op, mode)
4244 || (immediate_operand (op, mode)
4245 && (GET_CODE (op) != CONST_INT
4246 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4247 }
4248
4249 /* Return TRUE for valid shifts by a constant. This also accepts any
4250 power of two on the (somewhat overly relaxed) assumption that the
4251 shift operator in this case was a mult. */
4252 int
4253 const_shift_operand (rtx op, enum machine_mode mode)
4254 {
4255 return (power_of_two_operand (op, mode)
4256 || (immediate_operand (op, mode)
4257 && (GET_CODE (op) != CONST_INT
4258 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4259 }
4260
4261 /* Return TRUE for arithmetic operators which can be combined with a multiply
4262 (shift). */
4263 int
4264 shiftable_operator (rtx x, enum machine_mode mode)
4265 {
4266 enum rtx_code code;
4267
4268 if (GET_MODE (x) != mode)
4269 return FALSE;
4270
4271 code = GET_CODE (x);
4272
4273 return (code == PLUS || code == MINUS
4274 || code == IOR || code == XOR || code == AND);
4275 }
4276
4277 /* Return TRUE for binary logical operators. */
4278 int
4279 logical_binary_operator (rtx x, enum machine_mode mode)
4280 {
4281 enum rtx_code code;
4282
4283 if (GET_MODE (x) != mode)
4284 return FALSE;
4285
4286 code = GET_CODE (x);
4287
4288 return (code == IOR || code == XOR || code == AND);
4289 }
4290
4291 /* Return TRUE for shift operators. */
4292 int
4293 shift_operator (rtx x,enum machine_mode mode)
4294 {
4295 enum rtx_code code;
4296
4297 if (GET_MODE (x) != mode)
4298 return FALSE;
4299
4300 code = GET_CODE (x);
4301
4302 if (code == MULT)
4303 return power_of_two_operand (XEXP (x, 1), mode);
4304
4305 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4306 || code == ROTATERT);
4307 }
4308
4309 /* Return TRUE if x is EQ or NE. */
4310 int
4311 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
4312 {
4313 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4314 }
4315
4316 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4317 int
4318 arm_comparison_operator (rtx x, enum machine_mode mode)
4319 {
4320 return (comparison_operator (x, mode)
4321 && GET_CODE (x) != LTGT
4322 && GET_CODE (x) != UNEQ);
4323 }
4324
4325 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4326 int
4327 minmax_operator (rtx x, enum machine_mode mode)
4328 {
4329 enum rtx_code code = GET_CODE (x);
4330
4331 if (GET_MODE (x) != mode)
4332 return FALSE;
4333
4334 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4335 }
4336
4337 /* Return TRUE if this is the condition code register, if we aren't given
4338 a mode, accept any class CCmode register. */
4339 int
4340 cc_register (rtx x, enum machine_mode mode)
4341 {
4342 if (mode == VOIDmode)
4343 {
4344 mode = GET_MODE (x);
4345
4346 if (GET_MODE_CLASS (mode) != MODE_CC)
4347 return FALSE;
4348 }
4349
4350 if ( GET_MODE (x) == mode
4351 && GET_CODE (x) == REG
4352 && REGNO (x) == CC_REGNUM)
4353 return TRUE;
4354
4355 return FALSE;
4356 }
4357
4358 /* Return TRUE if this is the condition code register, if we aren't given
4359 a mode, accept any class CCmode register which indicates a dominance
4360 expression. */
4361 int
4362 dominant_cc_register (rtx x, enum machine_mode mode)
4363 {
4364 if (mode == VOIDmode)
4365 {
4366 mode = GET_MODE (x);
4367
4368 if (GET_MODE_CLASS (mode) != MODE_CC)
4369 return FALSE;
4370 }
4371
4372 if (mode != CC_DNEmode && mode != CC_DEQmode
4373 && mode != CC_DLEmode && mode != CC_DLTmode
4374 && mode != CC_DGEmode && mode != CC_DGTmode
4375 && mode != CC_DLEUmode && mode != CC_DLTUmode
4376 && mode != CC_DGEUmode && mode != CC_DGTUmode)
4377 return FALSE;
4378
4379 return cc_register (x, mode);
4380 }
4381
4382 /* Return TRUE if X references a SYMBOL_REF. */
4383 int
4384 symbol_mentioned_p (rtx x)
4385 {
4386 const char * fmt;
4387 int i;
4388
4389 if (GET_CODE (x) == SYMBOL_REF)
4390 return 1;
4391
4392 fmt = GET_RTX_FORMAT (GET_CODE (x));
4393
4394 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4395 {
4396 if (fmt[i] == 'E')
4397 {
4398 int j;
4399
4400 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4401 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4402 return 1;
4403 }
4404 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4405 return 1;
4406 }
4407
4408 return 0;
4409 }
4410
4411 /* Return TRUE if X references a LABEL_REF. */
4412 int
4413 label_mentioned_p (rtx x)
4414 {
4415 const char * fmt;
4416 int i;
4417
4418 if (GET_CODE (x) == LABEL_REF)
4419 return 1;
4420
4421 fmt = GET_RTX_FORMAT (GET_CODE (x));
4422 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4423 {
4424 if (fmt[i] == 'E')
4425 {
4426 int j;
4427
4428 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4429 if (label_mentioned_p (XVECEXP (x, i, j)))
4430 return 1;
4431 }
4432 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4433 return 1;
4434 }
4435
4436 return 0;
4437 }
4438
4439 enum rtx_code
4440 minmax_code (rtx x)
4441 {
4442 enum rtx_code code = GET_CODE (x);
4443
4444 if (code == SMAX)
4445 return GE;
4446 else if (code == SMIN)
4447 return LE;
4448 else if (code == UMIN)
4449 return LEU;
4450 else if (code == UMAX)
4451 return GEU;
4452
4453 abort ();
4454 }
4455
4456 /* Return 1 if memory locations are adjacent. */
4457 int
4458 adjacent_mem_locations (rtx a, rtx b)
4459 {
4460 if ((GET_CODE (XEXP (a, 0)) == REG
4461 || (GET_CODE (XEXP (a, 0)) == PLUS
4462 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4463 && (GET_CODE (XEXP (b, 0)) == REG
4464 || (GET_CODE (XEXP (b, 0)) == PLUS
4465 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
4466 {
4467 int val0 = 0, val1 = 0;
4468 int reg0, reg1;
4469
4470 if (GET_CODE (XEXP (a, 0)) == PLUS)
4471 {
4472 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
4473 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
4474 }
4475 else
4476 reg0 = REGNO (XEXP (a, 0));
4477
4478 if (GET_CODE (XEXP (b, 0)) == PLUS)
4479 {
4480 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
4481 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
4482 }
4483 else
4484 reg1 = REGNO (XEXP (b, 0));
4485
4486 /* Don't accept any offset that will require multiple
4487 instructions to handle, since this would cause the
4488 arith_adjacentmem pattern to output an overlong sequence. */
4489 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
4490 return 0;
4491
4492 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
4493 }
4494 return 0;
4495 }
4496
4497 /* Return 1 if OP is a load multiple operation. It is known to be
4498 parallel and the first section will be tested. */
4499 int
4500 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4501 {
4502 HOST_WIDE_INT count = XVECLEN (op, 0);
4503 int dest_regno;
4504 rtx src_addr;
4505 HOST_WIDE_INT i = 1, base = 0;
4506 rtx elt;
4507
4508 if (count <= 1
4509 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4510 return 0;
4511
4512 /* Check to see if this might be a write-back. */
4513 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4514 {
4515 i++;
4516 base = 1;
4517
4518 /* Now check it more carefully. */
4519 if (GET_CODE (SET_DEST (elt)) != REG
4520 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4521 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
4522 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4523 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4524 return 0;
4525 }
4526
4527 /* Perform a quick check so we don't blow up below. */
4528 if (count <= i
4529 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4530 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
4531 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
4532 return 0;
4533
4534 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
4535 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
4536
4537 for (; i < count; i++)
4538 {
4539 elt = XVECEXP (op, 0, i);
4540
4541 if (GET_CODE (elt) != SET
4542 || GET_CODE (SET_DEST (elt)) != REG
4543 || GET_MODE (SET_DEST (elt)) != SImode
4544 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
4545 || GET_CODE (SET_SRC (elt)) != MEM
4546 || GET_MODE (SET_SRC (elt)) != SImode
4547 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
4548 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
4549 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
4550 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
4551 return 0;
4552 }
4553
4554 return 1;
4555 }
4556
4557 /* Return 1 if OP is a store multiple operation. It is known to be
4558 parallel and the first section will be tested. */
4559 int
4560 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4561 {
4562 HOST_WIDE_INT count = XVECLEN (op, 0);
4563 int src_regno;
4564 rtx dest_addr;
4565 HOST_WIDE_INT i = 1, base = 0;
4566 rtx elt;
4567
4568 if (count <= 1
4569 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4570 return 0;
4571
4572 /* Check to see if this might be a write-back. */
4573 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4574 {
4575 i++;
4576 base = 1;
4577
4578 /* Now check it more carefully. */
4579 if (GET_CODE (SET_DEST (elt)) != REG
4580 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4581 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
4582 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4583 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4584 return 0;
4585 }
4586
4587 /* Perform a quick check so we don't blow up below. */
4588 if (count <= i
4589 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4590 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
4591 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
4592 return 0;
4593
4594 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
4595 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
4596
4597 for (; i < count; i++)
4598 {
4599 elt = XVECEXP (op, 0, i);
4600
4601 if (GET_CODE (elt) != SET
4602 || GET_CODE (SET_SRC (elt)) != REG
4603 || GET_MODE (SET_SRC (elt)) != SImode
4604 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
4605 || GET_CODE (SET_DEST (elt)) != MEM
4606 || GET_MODE (SET_DEST (elt)) != SImode
4607 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
4608 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
4609 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
4610 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
4611 return 0;
4612 }
4613
4614 return 1;
4615 }
4616
4617 int
4618 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4619 HOST_WIDE_INT *load_offset)
4620 {
4621 int unsorted_regs[4];
4622 HOST_WIDE_INT unsorted_offsets[4];
4623 int order[4];
4624 int base_reg = -1;
4625 int i;
4626
4627 /* Can only handle 2, 3, or 4 insns at present,
4628 though could be easily extended if required. */
4629 if (nops < 2 || nops > 4)
4630 abort ();
4631
4632 /* Loop over the operands and check that the memory references are
4633 suitable (ie immediate offsets from the same base register). At
4634 the same time, extract the target register, and the memory
4635 offsets. */
4636 for (i = 0; i < nops; i++)
4637 {
4638 rtx reg;
4639 rtx offset;
4640
4641 /* Convert a subreg of a mem into the mem itself. */
4642 if (GET_CODE (operands[nops + i]) == SUBREG)
4643 operands[nops + i] = alter_subreg (operands + (nops + i));
4644
4645 if (GET_CODE (operands[nops + i]) != MEM)
4646 abort ();
4647
4648 /* Don't reorder volatile memory references; it doesn't seem worth
4649 looking for the case where the order is ok anyway. */
4650 if (MEM_VOLATILE_P (operands[nops + i]))
4651 return 0;
4652
4653 offset = const0_rtx;
4654
4655 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4656 || (GET_CODE (reg) == SUBREG
4657 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4658 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4659 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4660 == REG)
4661 || (GET_CODE (reg) == SUBREG
4662 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4663 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4664 == CONST_INT)))
4665 {
4666 if (i == 0)
4667 {
4668 base_reg = REGNO (reg);
4669 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4670 ? REGNO (operands[i])
4671 : REGNO (SUBREG_REG (operands[i])));
4672 order[0] = 0;
4673 }
4674 else
4675 {
4676 if (base_reg != (int) REGNO (reg))
4677 /* Not addressed from the same base register. */
4678 return 0;
4679
4680 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4681 ? REGNO (operands[i])
4682 : REGNO (SUBREG_REG (operands[i])));
4683 if (unsorted_regs[i] < unsorted_regs[order[0]])
4684 order[0] = i;
4685 }
4686
4687 /* If it isn't an integer register, or if it overwrites the
4688 base register but isn't the last insn in the list, then
4689 we can't do this. */
4690 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
4691 || (i != nops - 1 && unsorted_regs[i] == base_reg))
4692 return 0;
4693
4694 unsorted_offsets[i] = INTVAL (offset);
4695 }
4696 else
4697 /* Not a suitable memory address. */
4698 return 0;
4699 }
4700
4701 /* All the useful information has now been extracted from the
4702 operands into unsorted_regs and unsorted_offsets; additionally,
4703 order[0] has been set to the lowest numbered register in the
4704 list. Sort the registers into order, and check that the memory
4705 offsets are ascending and adjacent. */
4706
4707 for (i = 1; i < nops; i++)
4708 {
4709 int j;
4710
4711 order[i] = order[i - 1];
4712 for (j = 0; j < nops; j++)
4713 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4714 && (order[i] == order[i - 1]
4715 || unsorted_regs[j] < unsorted_regs[order[i]]))
4716 order[i] = j;
4717
4718 /* Have we found a suitable register? if not, one must be used more
4719 than once. */
4720 if (order[i] == order[i - 1])
4721 return 0;
4722
4723 /* Is the memory address adjacent and ascending? */
4724 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4725 return 0;
4726 }
4727
4728 if (base)
4729 {
4730 *base = base_reg;
4731
4732 for (i = 0; i < nops; i++)
4733 regs[i] = unsorted_regs[order[i]];
4734
4735 *load_offset = unsorted_offsets[order[0]];
4736 }
4737
4738 if (unsorted_offsets[order[0]] == 0)
4739 return 1; /* ldmia */
4740
4741 if (unsorted_offsets[order[0]] == 4)
4742 return 2; /* ldmib */
4743
4744 if (unsorted_offsets[order[nops - 1]] == 0)
4745 return 3; /* ldmda */
4746
4747 if (unsorted_offsets[order[nops - 1]] == -4)
4748 return 4; /* ldmdb */
4749
4750 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4751 if the offset isn't small enough. The reason 2 ldrs are faster
4752 is because these ARMs are able to do more than one cache access
4753 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4754 whilst the ARM8 has a double bandwidth cache. This means that
4755 these cores can do both an instruction fetch and a data fetch in
4756 a single cycle, so the trick of calculating the address into a
4757 scratch register (one of the result regs) and then doing a load
4758 multiple actually becomes slower (and no smaller in code size).
4759 That is the transformation
4760
4761 ldr rd1, [rbase + offset]
4762 ldr rd2, [rbase + offset + 4]
4763
4764 to
4765
4766 add rd1, rbase, offset
4767 ldmia rd1, {rd1, rd2}
4768
4769 produces worse code -- '3 cycles + any stalls on rd2' instead of
4770 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4771 access per cycle, the first sequence could never complete in less
4772 than 6 cycles, whereas the ldm sequence would only take 5 and
4773 would make better use of sequential accesses if not hitting the
4774 cache.
4775
4776 We cheat here and test 'arm_ld_sched' which we currently know to
4777 only be true for the ARM8, ARM9 and StrongARM. If this ever
4778 changes, then the test below needs to be reworked. */
4779 if (nops == 2 && arm_ld_sched)
4780 return 0;
4781
4782 /* Can't do it without setting up the offset, only do this if it takes
4783 no more than one insn. */
4784 return (const_ok_for_arm (unsorted_offsets[order[0]])
4785 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
4786 }
4787
4788 const char *
4789 emit_ldm_seq (rtx *operands, int nops)
4790 {
4791 int regs[4];
4792 int base_reg;
4793 HOST_WIDE_INT offset;
4794 char buf[100];
4795 int i;
4796
4797 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4798 {
4799 case 1:
4800 strcpy (buf, "ldm%?ia\t");
4801 break;
4802
4803 case 2:
4804 strcpy (buf, "ldm%?ib\t");
4805 break;
4806
4807 case 3:
4808 strcpy (buf, "ldm%?da\t");
4809 break;
4810
4811 case 4:
4812 strcpy (buf, "ldm%?db\t");
4813 break;
4814
4815 case 5:
4816 if (offset >= 0)
4817 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4818 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4819 (long) offset);
4820 else
4821 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4822 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4823 (long) -offset);
4824 output_asm_insn (buf, operands);
4825 base_reg = regs[0];
4826 strcpy (buf, "ldm%?ia\t");
4827 break;
4828
4829 default:
4830 abort ();
4831 }
4832
4833 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4834 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4835
4836 for (i = 1; i < nops; i++)
4837 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4838 reg_names[regs[i]]);
4839
4840 strcat (buf, "}\t%@ phole ldm");
4841
4842 output_asm_insn (buf, operands);
4843 return "";
4844 }
4845
4846 int
4847 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4848 HOST_WIDE_INT * load_offset)
4849 {
4850 int unsorted_regs[4];
4851 HOST_WIDE_INT unsorted_offsets[4];
4852 int order[4];
4853 int base_reg = -1;
4854 int i;
4855
4856 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4857 extended if required. */
4858 if (nops < 2 || nops > 4)
4859 abort ();
4860
4861 /* Loop over the operands and check that the memory references are
4862 suitable (ie immediate offsets from the same base register). At
4863 the same time, extract the target register, and the memory
4864 offsets. */
4865 for (i = 0; i < nops; i++)
4866 {
4867 rtx reg;
4868 rtx offset;
4869
4870 /* Convert a subreg of a mem into the mem itself. */
4871 if (GET_CODE (operands[nops + i]) == SUBREG)
4872 operands[nops + i] = alter_subreg (operands + (nops + i));
4873
4874 if (GET_CODE (operands[nops + i]) != MEM)
4875 abort ();
4876
4877 /* Don't reorder volatile memory references; it doesn't seem worth
4878 looking for the case where the order is ok anyway. */
4879 if (MEM_VOLATILE_P (operands[nops + i]))
4880 return 0;
4881
4882 offset = const0_rtx;
4883
4884 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4885 || (GET_CODE (reg) == SUBREG
4886 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4887 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4888 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4889 == REG)
4890 || (GET_CODE (reg) == SUBREG
4891 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4892 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4893 == CONST_INT)))
4894 {
4895 if (i == 0)
4896 {
4897 base_reg = REGNO (reg);
4898 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4899 ? REGNO (operands[i])
4900 : REGNO (SUBREG_REG (operands[i])));
4901 order[0] = 0;
4902 }
4903 else
4904 {
4905 if (base_reg != (int) REGNO (reg))
4906 /* Not addressed from the same base register. */
4907 return 0;
4908
4909 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4910 ? REGNO (operands[i])
4911 : REGNO (SUBREG_REG (operands[i])));
4912 if (unsorted_regs[i] < unsorted_regs[order[0]])
4913 order[0] = i;
4914 }
4915
4916 /* If it isn't an integer register, then we can't do this. */
4917 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
4918 return 0;
4919
4920 unsorted_offsets[i] = INTVAL (offset);
4921 }
4922 else
4923 /* Not a suitable memory address. */
4924 return 0;
4925 }
4926
4927 /* All the useful information has now been extracted from the
4928 operands into unsorted_regs and unsorted_offsets; additionally,
4929 order[0] has been set to the lowest numbered register in the
4930 list. Sort the registers into order, and check that the memory
4931 offsets are ascending and adjacent. */
4932
4933 for (i = 1; i < nops; i++)
4934 {
4935 int j;
4936
4937 order[i] = order[i - 1];
4938 for (j = 0; j < nops; j++)
4939 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4940 && (order[i] == order[i - 1]
4941 || unsorted_regs[j] < unsorted_regs[order[i]]))
4942 order[i] = j;
4943
4944 /* Have we found a suitable register? if not, one must be used more
4945 than once. */
4946 if (order[i] == order[i - 1])
4947 return 0;
4948
4949 /* Is the memory address adjacent and ascending? */
4950 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4951 return 0;
4952 }
4953
4954 if (base)
4955 {
4956 *base = base_reg;
4957
4958 for (i = 0; i < nops; i++)
4959 regs[i] = unsorted_regs[order[i]];
4960
4961 *load_offset = unsorted_offsets[order[0]];
4962 }
4963
4964 if (unsorted_offsets[order[0]] == 0)
4965 return 1; /* stmia */
4966
4967 if (unsorted_offsets[order[0]] == 4)
4968 return 2; /* stmib */
4969
4970 if (unsorted_offsets[order[nops - 1]] == 0)
4971 return 3; /* stmda */
4972
4973 if (unsorted_offsets[order[nops - 1]] == -4)
4974 return 4; /* stmdb */
4975
4976 return 0;
4977 }
4978
4979 const char *
4980 emit_stm_seq (rtx *operands, int nops)
4981 {
4982 int regs[4];
4983 int base_reg;
4984 HOST_WIDE_INT offset;
4985 char buf[100];
4986 int i;
4987
4988 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4989 {
4990 case 1:
4991 strcpy (buf, "stm%?ia\t");
4992 break;
4993
4994 case 2:
4995 strcpy (buf, "stm%?ib\t");
4996 break;
4997
4998 case 3:
4999 strcpy (buf, "stm%?da\t");
5000 break;
5001
5002 case 4:
5003 strcpy (buf, "stm%?db\t");
5004 break;
5005
5006 default:
5007 abort ();
5008 }
5009
5010 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5011 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5012
5013 for (i = 1; i < nops; i++)
5014 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5015 reg_names[regs[i]]);
5016
5017 strcat (buf, "}\t%@ phole stm");
5018
5019 output_asm_insn (buf, operands);
5020 return "";
5021 }
5022
5023 int
5024 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5025 {
5026 if (GET_CODE (op) != PARALLEL
5027 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5028 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5029 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5030 return 0;
5031
5032 return 1;
5033 }
5034 \f
5035 /* Routines for use in generating RTL. */
5036
5037 rtx
5038 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5039 int write_back, int unchanging_p, int in_struct_p,
5040 int scalar_p)
5041 {
5042 int i = 0, j;
5043 rtx result;
5044 int sign = up ? 1 : -1;
5045 rtx mem;
5046
5047 /* XScale has load-store double instructions, but they have stricter
5048 alignment requirements than load-store multiple, so we can not
5049 use them.
5050
5051 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5052 the pipeline until completion.
5053
5054 NREGS CYCLES
5055 1 3
5056 2 4
5057 3 5
5058 4 6
5059
5060 An ldr instruction takes 1-3 cycles, but does not block the
5061 pipeline.
5062
5063 NREGS CYCLES
5064 1 1-3
5065 2 2-6
5066 3 3-9
5067 4 4-12
5068
5069 Best case ldr will always win. However, the more ldr instructions
5070 we issue, the less likely we are to be able to schedule them well.
5071 Using ldr instructions also increases code size.
5072
5073 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5074 for counts of 3 or 4 regs. */
5075 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5076 {
5077 rtx seq;
5078
5079 start_sequence ();
5080
5081 for (i = 0; i < count; i++)
5082 {
5083 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5084 RTX_UNCHANGING_P (mem) = unchanging_p;
5085 MEM_IN_STRUCT_P (mem) = in_struct_p;
5086 MEM_SCALAR_P (mem) = scalar_p;
5087 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5088 }
5089
5090 if (write_back)
5091 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5092
5093 seq = get_insns ();
5094 end_sequence ();
5095
5096 return seq;
5097 }
5098
5099 result = gen_rtx_PARALLEL (VOIDmode,
5100 rtvec_alloc (count + (write_back ? 1 : 0)));
5101 if (write_back)
5102 {
5103 XVECEXP (result, 0, 0)
5104 = gen_rtx_SET (GET_MODE (from), from,
5105 plus_constant (from, count * 4 * sign));
5106 i = 1;
5107 count++;
5108 }
5109
5110 for (j = 0; i < count; i++, j++)
5111 {
5112 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5113 RTX_UNCHANGING_P (mem) = unchanging_p;
5114 MEM_IN_STRUCT_P (mem) = in_struct_p;
5115 MEM_SCALAR_P (mem) = scalar_p;
5116 XVECEXP (result, 0, i)
5117 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5118 }
5119
5120 return result;
5121 }
5122
5123 rtx
5124 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5125 int write_back, int unchanging_p, int in_struct_p,
5126 int scalar_p)
5127 {
5128 int i = 0, j;
5129 rtx result;
5130 int sign = up ? 1 : -1;
5131 rtx mem;
5132
5133 /* See arm_gen_load_multiple for discussion of
5134 the pros/cons of ldm/stm usage for XScale. */
5135 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5136 {
5137 rtx seq;
5138
5139 start_sequence ();
5140
5141 for (i = 0; i < count; i++)
5142 {
5143 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5144 RTX_UNCHANGING_P (mem) = unchanging_p;
5145 MEM_IN_STRUCT_P (mem) = in_struct_p;
5146 MEM_SCALAR_P (mem) = scalar_p;
5147 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5148 }
5149
5150 if (write_back)
5151 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5152
5153 seq = get_insns ();
5154 end_sequence ();
5155
5156 return seq;
5157 }
5158
5159 result = gen_rtx_PARALLEL (VOIDmode,
5160 rtvec_alloc (count + (write_back ? 1 : 0)));
5161 if (write_back)
5162 {
5163 XVECEXP (result, 0, 0)
5164 = gen_rtx_SET (GET_MODE (to), to,
5165 plus_constant (to, count * 4 * sign));
5166 i = 1;
5167 count++;
5168 }
5169
5170 for (j = 0; i < count; i++, j++)
5171 {
5172 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5173 RTX_UNCHANGING_P (mem) = unchanging_p;
5174 MEM_IN_STRUCT_P (mem) = in_struct_p;
5175 MEM_SCALAR_P (mem) = scalar_p;
5176
5177 XVECEXP (result, 0, i)
5178 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5179 }
5180
5181 return result;
5182 }
5183
5184 int
5185 arm_gen_movstrqi (rtx *operands)
5186 {
5187 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5188 int i;
5189 rtx src, dst;
5190 rtx st_src, st_dst, fin_src, fin_dst;
5191 rtx part_bytes_reg = NULL;
5192 rtx mem;
5193 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5194 int dst_scalar_p, src_scalar_p;
5195
5196 if (GET_CODE (operands[2]) != CONST_INT
5197 || GET_CODE (operands[3]) != CONST_INT
5198 || INTVAL (operands[2]) > 64
5199 || INTVAL (operands[3]) & 3)
5200 return 0;
5201
5202 st_dst = XEXP (operands[0], 0);
5203 st_src = XEXP (operands[1], 0);
5204
5205 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5206 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5207 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5208 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5209 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5210 src_scalar_p = MEM_SCALAR_P (operands[1]);
5211
5212 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5213 fin_src = src = copy_to_mode_reg (SImode, st_src);
5214
5215 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5216 out_words_to_go = INTVAL (operands[2]) / 4;
5217 last_bytes = INTVAL (operands[2]) & 3;
5218
5219 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5220 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5221
5222 for (i = 0; in_words_to_go >= 2; i+=4)
5223 {
5224 if (in_words_to_go > 4)
5225 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5226 src_unchanging_p,
5227 src_in_struct_p,
5228 src_scalar_p));
5229 else
5230 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5231 FALSE, src_unchanging_p,
5232 src_in_struct_p, src_scalar_p));
5233
5234 if (out_words_to_go)
5235 {
5236 if (out_words_to_go > 4)
5237 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5238 dst_unchanging_p,
5239 dst_in_struct_p,
5240 dst_scalar_p));
5241 else if (out_words_to_go != 1)
5242 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5243 dst, TRUE,
5244 (last_bytes == 0
5245 ? FALSE : TRUE),
5246 dst_unchanging_p,
5247 dst_in_struct_p,
5248 dst_scalar_p));
5249 else
5250 {
5251 mem = gen_rtx_MEM (SImode, dst);
5252 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5253 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5254 MEM_SCALAR_P (mem) = dst_scalar_p;
5255 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5256 if (last_bytes != 0)
5257 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5258 }
5259 }
5260
5261 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5262 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5263 }
5264
5265 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5266 if (out_words_to_go)
5267 {
5268 rtx sreg;
5269
5270 mem = gen_rtx_MEM (SImode, src);
5271 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5272 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5273 MEM_SCALAR_P (mem) = src_scalar_p;
5274 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5275 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5276
5277 mem = gen_rtx_MEM (SImode, dst);
5278 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5279 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5280 MEM_SCALAR_P (mem) = dst_scalar_p;
5281 emit_move_insn (mem, sreg);
5282 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
5283 in_words_to_go--;
5284
5285 if (in_words_to_go) /* Sanity check */
5286 abort ();
5287 }
5288
5289 if (in_words_to_go)
5290 {
5291 if (in_words_to_go < 0)
5292 abort ();
5293
5294 mem = gen_rtx_MEM (SImode, src);
5295 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5296 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5297 MEM_SCALAR_P (mem) = src_scalar_p;
5298 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5299 }
5300
5301 if (last_bytes && part_bytes_reg == NULL)
5302 abort ();
5303
5304 if (BYTES_BIG_ENDIAN && last_bytes)
5305 {
5306 rtx tmp = gen_reg_rtx (SImode);
5307
5308 /* The bytes we want are in the top end of the word. */
5309 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5310 GEN_INT (8 * (4 - last_bytes))));
5311 part_bytes_reg = tmp;
5312
5313 while (last_bytes)
5314 {
5315 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
5316 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5317 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5318 MEM_SCALAR_P (mem) = dst_scalar_p;
5319 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5320
5321 if (--last_bytes)
5322 {
5323 tmp = gen_reg_rtx (SImode);
5324 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5325 part_bytes_reg = tmp;
5326 }
5327 }
5328
5329 }
5330 else
5331 {
5332 if (last_bytes > 1)
5333 {
5334 mem = gen_rtx_MEM (HImode, dst);
5335 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5336 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5337 MEM_SCALAR_P (mem) = dst_scalar_p;
5338 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5339 last_bytes -= 2;
5340 if (last_bytes)
5341 {
5342 rtx tmp = gen_reg_rtx (SImode);
5343
5344 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
5345 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5346 part_bytes_reg = tmp;
5347 }
5348 }
5349
5350 if (last_bytes)
5351 {
5352 mem = gen_rtx_MEM (QImode, dst);
5353 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5354 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5355 MEM_SCALAR_P (mem) = dst_scalar_p;
5356 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5357 }
5358 }
5359
5360 return 1;
5361 }
5362
5363 /* Generate a memory reference for a half word, such that it will be loaded
5364 into the top 16 bits of the word. We can assume that the address is
5365 known to be alignable and of the form reg, or plus (reg, const). */
5366
5367 rtx
5368 arm_gen_rotated_half_load (rtx memref)
5369 {
5370 HOST_WIDE_INT offset = 0;
5371 rtx base = XEXP (memref, 0);
5372
5373 if (GET_CODE (base) == PLUS)
5374 {
5375 offset = INTVAL (XEXP (base, 1));
5376 base = XEXP (base, 0);
5377 }
5378
5379 /* If we aren't allowed to generate unaligned addresses, then fail. */
5380 if (TARGET_MMU_TRAPS
5381 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
5382 return NULL;
5383
5384 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5385
5386 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5387 return base;
5388
5389 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5390 }
5391
5392 /* Select a dominance comparison mode if possible for a test of the general
5393 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5394 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5395 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5396 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5397 In all cases OP will be either EQ or NE, but we don't need to know which
5398 here. If we are unable to support a dominance comparison we return
5399 CC mode. This will then fail to match for the RTL expressions that
5400 generate this call. */
5401 enum machine_mode
5402 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5403 {
5404 enum rtx_code cond1, cond2;
5405 int swapped = 0;
5406
5407 /* Currently we will probably get the wrong result if the individual
5408 comparisons are not simple. This also ensures that it is safe to
5409 reverse a comparison if necessary. */
5410 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5411 != CCmode)
5412 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5413 != CCmode))
5414 return CCmode;
5415
5416 /* The if_then_else variant of this tests the second condition if the
5417 first passes, but is true if the first fails. Reverse the first
5418 condition to get a true "inclusive-or" expression. */
5419 if (cond_or == DOM_CC_NX_OR_Y)
5420 cond1 = reverse_condition (cond1);
5421
5422 /* If the comparisons are not equal, and one doesn't dominate the other,
5423 then we can't do this. */
5424 if (cond1 != cond2
5425 && !comparison_dominates_p (cond1, cond2)
5426 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5427 return CCmode;
5428
5429 if (swapped)
5430 {
5431 enum rtx_code temp = cond1;
5432 cond1 = cond2;
5433 cond2 = temp;
5434 }
5435
5436 switch (cond1)
5437 {
5438 case EQ:
5439 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5440 return CC_DEQmode;
5441
5442 switch (cond2)
5443 {
5444 case LE: return CC_DLEmode;
5445 case LEU: return CC_DLEUmode;
5446 case GE: return CC_DGEmode;
5447 case GEU: return CC_DGEUmode;
5448 default: break;
5449 }
5450
5451 break;
5452
5453 case LT:
5454 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5455 return CC_DLTmode;
5456 if (cond2 == LE)
5457 return CC_DLEmode;
5458 if (cond2 == NE)
5459 return CC_DNEmode;
5460 break;
5461
5462 case GT:
5463 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5464 return CC_DGTmode;
5465 if (cond2 == GE)
5466 return CC_DGEmode;
5467 if (cond2 == NE)
5468 return CC_DNEmode;
5469 break;
5470
5471 case LTU:
5472 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
5473 return CC_DLTUmode;
5474 if (cond2 == LEU)
5475 return CC_DLEUmode;
5476 if (cond2 == NE)
5477 return CC_DNEmode;
5478 break;
5479
5480 case GTU:
5481 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
5482 return CC_DGTUmode;
5483 if (cond2 == GEU)
5484 return CC_DGEUmode;
5485 if (cond2 == NE)
5486 return CC_DNEmode;
5487 break;
5488
5489 /* The remaining cases only occur when both comparisons are the
5490 same. */
5491 case NE:
5492 return CC_DNEmode;
5493
5494 case LE:
5495 return CC_DLEmode;
5496
5497 case GE:
5498 return CC_DGEmode;
5499
5500 case LEU:
5501 return CC_DLEUmode;
5502
5503 case GEU:
5504 return CC_DGEUmode;
5505
5506 default:
5507 break;
5508 }
5509
5510 abort ();
5511 }
5512
5513 enum machine_mode
5514 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
5515 {
5516 /* All floating point compares return CCFP if it is an equality
5517 comparison, and CCFPE otherwise. */
5518 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5519 {
5520 switch (op)
5521 {
5522 case EQ:
5523 case NE:
5524 case UNORDERED:
5525 case ORDERED:
5526 case UNLT:
5527 case UNLE:
5528 case UNGT:
5529 case UNGE:
5530 case UNEQ:
5531 case LTGT:
5532 return CCFPmode;
5533
5534 case LT:
5535 case LE:
5536 case GT:
5537 case GE:
5538 if (TARGET_CIRRUS)
5539 return CCFPmode;
5540 return CCFPEmode;
5541
5542 default:
5543 abort ();
5544 }
5545 }
5546
5547 /* A compare with a shifted operand. Because of canonicalization, the
5548 comparison will have to be swapped when we emit the assembler. */
5549 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5550 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5551 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5552 || GET_CODE (x) == ROTATERT))
5553 return CC_SWPmode;
5554
5555 /* This is a special case that is used by combine to allow a
5556 comparison of a shifted byte load to be split into a zero-extend
5557 followed by a comparison of the shifted integer (only valid for
5558 equalities and unsigned inequalities). */
5559 if (GET_MODE (x) == SImode
5560 && GET_CODE (x) == ASHIFT
5561 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5562 && GET_CODE (XEXP (x, 0)) == SUBREG
5563 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5564 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5565 && (op == EQ || op == NE
5566 || op == GEU || op == GTU || op == LTU || op == LEU)
5567 && GET_CODE (y) == CONST_INT)
5568 return CC_Zmode;
5569
5570 /* A construct for a conditional compare, if the false arm contains
5571 0, then both conditions must be true, otherwise either condition
5572 must be true. Not all conditions are possible, so CCmode is
5573 returned if it can't be done. */
5574 if (GET_CODE (x) == IF_THEN_ELSE
5575 && (XEXP (x, 2) == const0_rtx
5576 || XEXP (x, 2) == const1_rtx)
5577 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5578 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5579 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5580 INTVAL (XEXP (x, 2)));
5581
5582 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5583 if (GET_CODE (x) == AND
5584 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5585 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5586 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5587 DOM_CC_X_AND_Y);
5588
5589 if (GET_CODE (x) == IOR
5590 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5591 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5592 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5593 DOM_CC_X_OR_Y);
5594
5595 /* An operation (on Thumb) where we want to test for a single bit.
5596 This is done by shifting that bit up into the top bit of a
5597 scratch register; we can then branch on the sign bit. */
5598 if (TARGET_THUMB
5599 && GET_MODE (x) == SImode
5600 && (op == EQ || op == NE)
5601 && (GET_CODE (x) == ZERO_EXTRACT))
5602 return CC_Nmode;
5603
5604 /* An operation that sets the condition codes as a side-effect, the
5605 V flag is not set correctly, so we can only use comparisons where
5606 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5607 instead.) */
5608 if (GET_MODE (x) == SImode
5609 && y == const0_rtx
5610 && (op == EQ || op == NE || op == LT || op == GE)
5611 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
5612 || GET_CODE (x) == AND || GET_CODE (x) == IOR
5613 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
5614 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
5615 || GET_CODE (x) == LSHIFTRT
5616 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5617 || GET_CODE (x) == ROTATERT
5618 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
5619 return CC_NOOVmode;
5620
5621 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
5622 return CC_Zmode;
5623
5624 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
5625 && GET_CODE (x) == PLUS
5626 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
5627 return CC_Cmode;
5628
5629 return CCmode;
5630 }
5631
5632 /* X and Y are two things to compare using CODE. Emit the compare insn and
5633 return the rtx for register 0 in the proper mode. FP means this is a
5634 floating point compare: I don't think that it is needed on the arm. */
5635 rtx
5636 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
5637 {
5638 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
5639 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
5640
5641 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5642 gen_rtx_COMPARE (mode, x, y)));
5643
5644 return cc_reg;
5645 }
5646
5647 /* Generate a sequence of insns that will generate the correct return
5648 address mask depending on the physical architecture that the program
5649 is running on. */
5650 rtx
5651 arm_gen_return_addr_mask (void)
5652 {
5653 rtx reg = gen_reg_rtx (Pmode);
5654
5655 emit_insn (gen_return_addr_mask (reg));
5656 return reg;
5657 }
5658
5659 void
5660 arm_reload_in_hi (rtx *operands)
5661 {
5662 rtx ref = operands[1];
5663 rtx base, scratch;
5664 HOST_WIDE_INT offset = 0;
5665
5666 if (GET_CODE (ref) == SUBREG)
5667 {
5668 offset = SUBREG_BYTE (ref);
5669 ref = SUBREG_REG (ref);
5670 }
5671
5672 if (GET_CODE (ref) == REG)
5673 {
5674 /* We have a pseudo which has been spilt onto the stack; there
5675 are two cases here: the first where there is a simple
5676 stack-slot replacement and a second where the stack-slot is
5677 out of range, or is used as a subreg. */
5678 if (reg_equiv_mem[REGNO (ref)])
5679 {
5680 ref = reg_equiv_mem[REGNO (ref)];
5681 base = find_replacement (&XEXP (ref, 0));
5682 }
5683 else
5684 /* The slot is out of range, or was dressed up in a SUBREG. */
5685 base = reg_equiv_address[REGNO (ref)];
5686 }
5687 else
5688 base = find_replacement (&XEXP (ref, 0));
5689
5690 /* Handle the case where the address is too complex to be offset by 1. */
5691 if (GET_CODE (base) == MINUS
5692 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5693 {
5694 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5695
5696 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5697 base = base_plus;
5698 }
5699 else if (GET_CODE (base) == PLUS)
5700 {
5701 /* The addend must be CONST_INT, or we would have dealt with it above. */
5702 HOST_WIDE_INT hi, lo;
5703
5704 offset += INTVAL (XEXP (base, 1));
5705 base = XEXP (base, 0);
5706
5707 /* Rework the address into a legal sequence of insns. */
5708 /* Valid range for lo is -4095 -> 4095 */
5709 lo = (offset >= 0
5710 ? (offset & 0xfff)
5711 : -((-offset) & 0xfff));
5712
5713 /* Corner case, if lo is the max offset then we would be out of range
5714 once we have added the additional 1 below, so bump the msb into the
5715 pre-loading insn(s). */
5716 if (lo == 4095)
5717 lo &= 0x7ff;
5718
5719 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5720 ^ (HOST_WIDE_INT) 0x80000000)
5721 - (HOST_WIDE_INT) 0x80000000);
5722
5723 if (hi + lo != offset)
5724 abort ();
5725
5726 if (hi != 0)
5727 {
5728 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5729
5730 /* Get the base address; addsi3 knows how to handle constants
5731 that require more than one insn. */
5732 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5733 base = base_plus;
5734 offset = lo;
5735 }
5736 }
5737
5738 /* Operands[2] may overlap operands[0] (though it won't overlap
5739 operands[1]), that's why we asked for a DImode reg -- so we can
5740 use the bit that does not overlap. */
5741 if (REGNO (operands[2]) == REGNO (operands[0]))
5742 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5743 else
5744 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5745
5746 emit_insn (gen_zero_extendqisi2 (scratch,
5747 gen_rtx_MEM (QImode,
5748 plus_constant (base,
5749 offset))));
5750 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
5751 gen_rtx_MEM (QImode,
5752 plus_constant (base,
5753 offset + 1))));
5754 if (!BYTES_BIG_ENDIAN)
5755 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5756 gen_rtx_IOR (SImode,
5757 gen_rtx_ASHIFT
5758 (SImode,
5759 gen_rtx_SUBREG (SImode, operands[0], 0),
5760 GEN_INT (8)),
5761 scratch)));
5762 else
5763 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5764 gen_rtx_IOR (SImode,
5765 gen_rtx_ASHIFT (SImode, scratch,
5766 GEN_INT (8)),
5767 gen_rtx_SUBREG (SImode, operands[0],
5768 0))));
5769 }
5770
5771 /* Handle storing a half-word to memory during reload by synthesizing as two
5772 byte stores. Take care not to clobber the input values until after we
5773 have moved them somewhere safe. This code assumes that if the DImode
5774 scratch in operands[2] overlaps either the input value or output address
5775 in some way, then that value must die in this insn (we absolutely need
5776 two scratch registers for some corner cases). */
5777 void
5778 arm_reload_out_hi (rtx *operands)
5779 {
5780 rtx ref = operands[0];
5781 rtx outval = operands[1];
5782 rtx base, scratch;
5783 HOST_WIDE_INT offset = 0;
5784
5785 if (GET_CODE (ref) == SUBREG)
5786 {
5787 offset = SUBREG_BYTE (ref);
5788 ref = SUBREG_REG (ref);
5789 }
5790
5791 if (GET_CODE (ref) == REG)
5792 {
5793 /* We have a pseudo which has been spilt onto the stack; there
5794 are two cases here: the first where there is a simple
5795 stack-slot replacement and a second where the stack-slot is
5796 out of range, or is used as a subreg. */
5797 if (reg_equiv_mem[REGNO (ref)])
5798 {
5799 ref = reg_equiv_mem[REGNO (ref)];
5800 base = find_replacement (&XEXP (ref, 0));
5801 }
5802 else
5803 /* The slot is out of range, or was dressed up in a SUBREG. */
5804 base = reg_equiv_address[REGNO (ref)];
5805 }
5806 else
5807 base = find_replacement (&XEXP (ref, 0));
5808
5809 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5810
5811 /* Handle the case where the address is too complex to be offset by 1. */
5812 if (GET_CODE (base) == MINUS
5813 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5814 {
5815 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5816
5817 /* Be careful not to destroy OUTVAL. */
5818 if (reg_overlap_mentioned_p (base_plus, outval))
5819 {
5820 /* Updating base_plus might destroy outval, see if we can
5821 swap the scratch and base_plus. */
5822 if (!reg_overlap_mentioned_p (scratch, outval))
5823 {
5824 rtx tmp = scratch;
5825 scratch = base_plus;
5826 base_plus = tmp;
5827 }
5828 else
5829 {
5830 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5831
5832 /* Be conservative and copy OUTVAL into the scratch now,
5833 this should only be necessary if outval is a subreg
5834 of something larger than a word. */
5835 /* XXX Might this clobber base? I can't see how it can,
5836 since scratch is known to overlap with OUTVAL, and
5837 must be wider than a word. */
5838 emit_insn (gen_movhi (scratch_hi, outval));
5839 outval = scratch_hi;
5840 }
5841 }
5842
5843 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5844 base = base_plus;
5845 }
5846 else if (GET_CODE (base) == PLUS)
5847 {
5848 /* The addend must be CONST_INT, or we would have dealt with it above. */
5849 HOST_WIDE_INT hi, lo;
5850
5851 offset += INTVAL (XEXP (base, 1));
5852 base = XEXP (base, 0);
5853
5854 /* Rework the address into a legal sequence of insns. */
5855 /* Valid range for lo is -4095 -> 4095 */
5856 lo = (offset >= 0
5857 ? (offset & 0xfff)
5858 : -((-offset) & 0xfff));
5859
5860 /* Corner case, if lo is the max offset then we would be out of range
5861 once we have added the additional 1 below, so bump the msb into the
5862 pre-loading insn(s). */
5863 if (lo == 4095)
5864 lo &= 0x7ff;
5865
5866 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5867 ^ (HOST_WIDE_INT) 0x80000000)
5868 - (HOST_WIDE_INT) 0x80000000);
5869
5870 if (hi + lo != offset)
5871 abort ();
5872
5873 if (hi != 0)
5874 {
5875 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5876
5877 /* Be careful not to destroy OUTVAL. */
5878 if (reg_overlap_mentioned_p (base_plus, outval))
5879 {
5880 /* Updating base_plus might destroy outval, see if we
5881 can swap the scratch and base_plus. */
5882 if (!reg_overlap_mentioned_p (scratch, outval))
5883 {
5884 rtx tmp = scratch;
5885 scratch = base_plus;
5886 base_plus = tmp;
5887 }
5888 else
5889 {
5890 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5891
5892 /* Be conservative and copy outval into scratch now,
5893 this should only be necessary if outval is a
5894 subreg of something larger than a word. */
5895 /* XXX Might this clobber base? I can't see how it
5896 can, since scratch is known to overlap with
5897 outval. */
5898 emit_insn (gen_movhi (scratch_hi, outval));
5899 outval = scratch_hi;
5900 }
5901 }
5902
5903 /* Get the base address; addsi3 knows how to handle constants
5904 that require more than one insn. */
5905 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5906 base = base_plus;
5907 offset = lo;
5908 }
5909 }
5910
5911 if (BYTES_BIG_ENDIAN)
5912 {
5913 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5914 plus_constant (base, offset + 1)),
5915 gen_lowpart (QImode, outval)));
5916 emit_insn (gen_lshrsi3 (scratch,
5917 gen_rtx_SUBREG (SImode, outval, 0),
5918 GEN_INT (8)));
5919 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5920 gen_lowpart (QImode, scratch)));
5921 }
5922 else
5923 {
5924 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5925 gen_lowpart (QImode, outval)));
5926 emit_insn (gen_lshrsi3 (scratch,
5927 gen_rtx_SUBREG (SImode, outval, 0),
5928 GEN_INT (8)));
5929 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5930 plus_constant (base, offset + 1)),
5931 gen_lowpart (QImode, scratch)));
5932 }
5933 }
5934 \f
5935 /* Print a symbolic form of X to the debug file, F. */
5936 static void
5937 arm_print_value (FILE *f, rtx x)
5938 {
5939 switch (GET_CODE (x))
5940 {
5941 case CONST_INT:
5942 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5943 return;
5944
5945 case CONST_DOUBLE:
5946 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5947 return;
5948
5949 case CONST_VECTOR:
5950 {
5951 int i;
5952
5953 fprintf (f, "<");
5954 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
5955 {
5956 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
5957 if (i < (CONST_VECTOR_NUNITS (x) - 1))
5958 fputc (',', f);
5959 }
5960 fprintf (f, ">");
5961 }
5962 return;
5963
5964 case CONST_STRING:
5965 fprintf (f, "\"%s\"", XSTR (x, 0));
5966 return;
5967
5968 case SYMBOL_REF:
5969 fprintf (f, "`%s'", XSTR (x, 0));
5970 return;
5971
5972 case LABEL_REF:
5973 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5974 return;
5975
5976 case CONST:
5977 arm_print_value (f, XEXP (x, 0));
5978 return;
5979
5980 case PLUS:
5981 arm_print_value (f, XEXP (x, 0));
5982 fprintf (f, "+");
5983 arm_print_value (f, XEXP (x, 1));
5984 return;
5985
5986 case PC:
5987 fprintf (f, "pc");
5988 return;
5989
5990 default:
5991 fprintf (f, "????");
5992 return;
5993 }
5994 }
5995 \f
5996 /* Routines for manipulation of the constant pool. */
5997
5998 /* Arm instructions cannot load a large constant directly into a
5999 register; they have to come from a pc relative load. The constant
6000 must therefore be placed in the addressable range of the pc
6001 relative load. Depending on the precise pc relative load
6002 instruction the range is somewhere between 256 bytes and 4k. This
6003 means that we often have to dump a constant inside a function, and
6004 generate code to branch around it.
6005
6006 It is important to minimize this, since the branches will slow
6007 things down and make the code larger.
6008
6009 Normally we can hide the table after an existing unconditional
6010 branch so that there is no interruption of the flow, but in the
6011 worst case the code looks like this:
6012
6013 ldr rn, L1
6014 ...
6015 b L2
6016 align
6017 L1: .long value
6018 L2:
6019 ...
6020
6021 ldr rn, L3
6022 ...
6023 b L4
6024 align
6025 L3: .long value
6026 L4:
6027 ...
6028
6029 We fix this by performing a scan after scheduling, which notices
6030 which instructions need to have their operands fetched from the
6031 constant table and builds the table.
6032
6033 The algorithm starts by building a table of all the constants that
6034 need fixing up and all the natural barriers in the function (places
6035 where a constant table can be dropped without breaking the flow).
6036 For each fixup we note how far the pc-relative replacement will be
6037 able to reach and the offset of the instruction into the function.
6038
6039 Having built the table we then group the fixes together to form
6040 tables that are as large as possible (subject to addressing
6041 constraints) and emit each table of constants after the last
6042 barrier that is within range of all the instructions in the group.
6043 If a group does not contain a barrier, then we forcibly create one
6044 by inserting a jump instruction into the flow. Once the table has
6045 been inserted, the insns are then modified to reference the
6046 relevant entry in the pool.
6047
6048 Possible enhancements to the algorithm (not implemented) are:
6049
6050 1) For some processors and object formats, there may be benefit in
6051 aligning the pools to the start of cache lines; this alignment
6052 would need to be taken into account when calculating addressability
6053 of a pool. */
6054
6055 /* These typedefs are located at the start of this file, so that
6056 they can be used in the prototypes there. This comment is to
6057 remind readers of that fact so that the following structures
6058 can be understood more easily.
6059
6060 typedef struct minipool_node Mnode;
6061 typedef struct minipool_fixup Mfix; */
6062
6063 struct minipool_node
6064 {
6065 /* Doubly linked chain of entries. */
6066 Mnode * next;
6067 Mnode * prev;
6068 /* The maximum offset into the code that this entry can be placed. While
6069 pushing fixes for forward references, all entries are sorted in order
6070 of increasing max_address. */
6071 HOST_WIDE_INT max_address;
6072 /* Similarly for an entry inserted for a backwards ref. */
6073 HOST_WIDE_INT min_address;
6074 /* The number of fixes referencing this entry. This can become zero
6075 if we "unpush" an entry. In this case we ignore the entry when we
6076 come to emit the code. */
6077 int refcount;
6078 /* The offset from the start of the minipool. */
6079 HOST_WIDE_INT offset;
6080 /* The value in table. */
6081 rtx value;
6082 /* The mode of value. */
6083 enum machine_mode mode;
6084 /* The size of the value. With iWMMXt enabled
6085 sizes > 4 also imply an alignment of 8-bytes. */
6086 int fix_size;
6087 };
6088
6089 struct minipool_fixup
6090 {
6091 Mfix * next;
6092 rtx insn;
6093 HOST_WIDE_INT address;
6094 rtx * loc;
6095 enum machine_mode mode;
6096 int fix_size;
6097 rtx value;
6098 Mnode * minipool;
6099 HOST_WIDE_INT forwards;
6100 HOST_WIDE_INT backwards;
6101 };
6102
6103 /* Fixes less than a word need padding out to a word boundary. */
6104 #define MINIPOOL_FIX_SIZE(mode) \
6105 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6106
6107 static Mnode * minipool_vector_head;
6108 static Mnode * minipool_vector_tail;
6109 static rtx minipool_vector_label;
6110
6111 /* The linked list of all minipool fixes required for this function. */
6112 Mfix * minipool_fix_head;
6113 Mfix * minipool_fix_tail;
6114 /* The fix entry for the current minipool, once it has been placed. */
6115 Mfix * minipool_barrier;
6116
6117 /* Determines if INSN is the start of a jump table. Returns the end
6118 of the TABLE or NULL_RTX. */
6119 static rtx
6120 is_jump_table (rtx insn)
6121 {
6122 rtx table;
6123
6124 if (GET_CODE (insn) == JUMP_INSN
6125 && JUMP_LABEL (insn) != NULL
6126 && ((table = next_real_insn (JUMP_LABEL (insn)))
6127 == next_real_insn (insn))
6128 && table != NULL
6129 && GET_CODE (table) == JUMP_INSN
6130 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6131 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6132 return table;
6133
6134 return NULL_RTX;
6135 }
6136
6137 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6138 #define JUMP_TABLES_IN_TEXT_SECTION 0
6139 #endif
6140
6141 static HOST_WIDE_INT
6142 get_jump_table_size (rtx insn)
6143 {
6144 /* ADDR_VECs only take room if read-only data does into the text
6145 section. */
6146 if (JUMP_TABLES_IN_TEXT_SECTION
6147 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6148 || 1
6149 #endif
6150 )
6151 {
6152 rtx body = PATTERN (insn);
6153 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6154
6155 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6156 }
6157
6158 return 0;
6159 }
6160
6161 /* Move a minipool fix MP from its current location to before MAX_MP.
6162 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6163 constraints may need updating. */
6164 static Mnode *
6165 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6166 HOST_WIDE_INT max_address)
6167 {
6168 /* This should never be true and the code below assumes these are
6169 different. */
6170 if (mp == max_mp)
6171 abort ();
6172
6173 if (max_mp == NULL)
6174 {
6175 if (max_address < mp->max_address)
6176 mp->max_address = max_address;
6177 }
6178 else
6179 {
6180 if (max_address > max_mp->max_address - mp->fix_size)
6181 mp->max_address = max_mp->max_address - mp->fix_size;
6182 else
6183 mp->max_address = max_address;
6184
6185 /* Unlink MP from its current position. Since max_mp is non-null,
6186 mp->prev must be non-null. */
6187 mp->prev->next = mp->next;
6188 if (mp->next != NULL)
6189 mp->next->prev = mp->prev;
6190 else
6191 minipool_vector_tail = mp->prev;
6192
6193 /* Re-insert it before MAX_MP. */
6194 mp->next = max_mp;
6195 mp->prev = max_mp->prev;
6196 max_mp->prev = mp;
6197
6198 if (mp->prev != NULL)
6199 mp->prev->next = mp;
6200 else
6201 minipool_vector_head = mp;
6202 }
6203
6204 /* Save the new entry. */
6205 max_mp = mp;
6206
6207 /* Scan over the preceding entries and adjust their addresses as
6208 required. */
6209 while (mp->prev != NULL
6210 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6211 {
6212 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6213 mp = mp->prev;
6214 }
6215
6216 return max_mp;
6217 }
6218
6219 /* Add a constant to the minipool for a forward reference. Returns the
6220 node added or NULL if the constant will not fit in this pool. */
6221 static Mnode *
6222 add_minipool_forward_ref (Mfix *fix)
6223 {
6224 /* If set, max_mp is the first pool_entry that has a lower
6225 constraint than the one we are trying to add. */
6226 Mnode * max_mp = NULL;
6227 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6228 Mnode * mp;
6229
6230 /* If this fix's address is greater than the address of the first
6231 entry, then we can't put the fix in this pool. We subtract the
6232 size of the current fix to ensure that if the table is fully
6233 packed we still have enough room to insert this value by suffling
6234 the other fixes forwards. */
6235 if (minipool_vector_head &&
6236 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6237 return NULL;
6238
6239 /* Scan the pool to see if a constant with the same value has
6240 already been added. While we are doing this, also note the
6241 location where we must insert the constant if it doesn't already
6242 exist. */
6243 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6244 {
6245 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6246 && fix->mode == mp->mode
6247 && (GET_CODE (fix->value) != CODE_LABEL
6248 || (CODE_LABEL_NUMBER (fix->value)
6249 == CODE_LABEL_NUMBER (mp->value)))
6250 && rtx_equal_p (fix->value, mp->value))
6251 {
6252 /* More than one fix references this entry. */
6253 mp->refcount++;
6254 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6255 }
6256
6257 /* Note the insertion point if necessary. */
6258 if (max_mp == NULL
6259 && mp->max_address > max_address)
6260 max_mp = mp;
6261
6262 /* If we are inserting an 8-bytes aligned quantity and
6263 we have not already found an insertion point, then
6264 make sure that all such 8-byte aligned quantities are
6265 placed at the start of the pool. */
6266 if (TARGET_REALLY_IWMMXT
6267 && max_mp == NULL
6268 && fix->fix_size == 8
6269 && mp->fix_size != 8)
6270 {
6271 max_mp = mp;
6272 max_address = mp->max_address;
6273 }
6274 }
6275
6276 /* The value is not currently in the minipool, so we need to create
6277 a new entry for it. If MAX_MP is NULL, the entry will be put on
6278 the end of the list since the placement is less constrained than
6279 any existing entry. Otherwise, we insert the new fix before
6280 MAX_MP and, if necessary, adjust the constraints on the other
6281 entries. */
6282 mp = xmalloc (sizeof (* mp));
6283 mp->fix_size = fix->fix_size;
6284 mp->mode = fix->mode;
6285 mp->value = fix->value;
6286 mp->refcount = 1;
6287 /* Not yet required for a backwards ref. */
6288 mp->min_address = -65536;
6289
6290 if (max_mp == NULL)
6291 {
6292 mp->max_address = max_address;
6293 mp->next = NULL;
6294 mp->prev = minipool_vector_tail;
6295
6296 if (mp->prev == NULL)
6297 {
6298 minipool_vector_head = mp;
6299 minipool_vector_label = gen_label_rtx ();
6300 }
6301 else
6302 mp->prev->next = mp;
6303
6304 minipool_vector_tail = mp;
6305 }
6306 else
6307 {
6308 if (max_address > max_mp->max_address - mp->fix_size)
6309 mp->max_address = max_mp->max_address - mp->fix_size;
6310 else
6311 mp->max_address = max_address;
6312
6313 mp->next = max_mp;
6314 mp->prev = max_mp->prev;
6315 max_mp->prev = mp;
6316 if (mp->prev != NULL)
6317 mp->prev->next = mp;
6318 else
6319 minipool_vector_head = mp;
6320 }
6321
6322 /* Save the new entry. */
6323 max_mp = mp;
6324
6325 /* Scan over the preceding entries and adjust their addresses as
6326 required. */
6327 while (mp->prev != NULL
6328 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6329 {
6330 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6331 mp = mp->prev;
6332 }
6333
6334 return max_mp;
6335 }
6336
6337 static Mnode *
6338 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6339 HOST_WIDE_INT min_address)
6340 {
6341 HOST_WIDE_INT offset;
6342
6343 /* This should never be true, and the code below assumes these are
6344 different. */
6345 if (mp == min_mp)
6346 abort ();
6347
6348 if (min_mp == NULL)
6349 {
6350 if (min_address > mp->min_address)
6351 mp->min_address = min_address;
6352 }
6353 else
6354 {
6355 /* We will adjust this below if it is too loose. */
6356 mp->min_address = min_address;
6357
6358 /* Unlink MP from its current position. Since min_mp is non-null,
6359 mp->next must be non-null. */
6360 mp->next->prev = mp->prev;
6361 if (mp->prev != NULL)
6362 mp->prev->next = mp->next;
6363 else
6364 minipool_vector_head = mp->next;
6365
6366 /* Reinsert it after MIN_MP. */
6367 mp->prev = min_mp;
6368 mp->next = min_mp->next;
6369 min_mp->next = mp;
6370 if (mp->next != NULL)
6371 mp->next->prev = mp;
6372 else
6373 minipool_vector_tail = mp;
6374 }
6375
6376 min_mp = mp;
6377
6378 offset = 0;
6379 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6380 {
6381 mp->offset = offset;
6382 if (mp->refcount > 0)
6383 offset += mp->fix_size;
6384
6385 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6386 mp->next->min_address = mp->min_address + mp->fix_size;
6387 }
6388
6389 return min_mp;
6390 }
6391
6392 /* Add a constant to the minipool for a backward reference. Returns the
6393 node added or NULL if the constant will not fit in this pool.
6394
6395 Note that the code for insertion for a backwards reference can be
6396 somewhat confusing because the calculated offsets for each fix do
6397 not take into account the size of the pool (which is still under
6398 construction. */
6399 static Mnode *
6400 add_minipool_backward_ref (Mfix *fix)
6401 {
6402 /* If set, min_mp is the last pool_entry that has a lower constraint
6403 than the one we are trying to add. */
6404 Mnode *min_mp = NULL;
6405 /* This can be negative, since it is only a constraint. */
6406 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6407 Mnode *mp;
6408
6409 /* If we can't reach the current pool from this insn, or if we can't
6410 insert this entry at the end of the pool without pushing other
6411 fixes out of range, then we don't try. This ensures that we
6412 can't fail later on. */
6413 if (min_address >= minipool_barrier->address
6414 || (minipool_vector_tail->min_address + fix->fix_size
6415 >= minipool_barrier->address))
6416 return NULL;
6417
6418 /* Scan the pool to see if a constant with the same value has
6419 already been added. While we are doing this, also note the
6420 location where we must insert the constant if it doesn't already
6421 exist. */
6422 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6423 {
6424 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6425 && fix->mode == mp->mode
6426 && (GET_CODE (fix->value) != CODE_LABEL
6427 || (CODE_LABEL_NUMBER (fix->value)
6428 == CODE_LABEL_NUMBER (mp->value)))
6429 && rtx_equal_p (fix->value, mp->value)
6430 /* Check that there is enough slack to move this entry to the
6431 end of the table (this is conservative). */
6432 && (mp->max_address
6433 > (minipool_barrier->address
6434 + minipool_vector_tail->offset
6435 + minipool_vector_tail->fix_size)))
6436 {
6437 mp->refcount++;
6438 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6439 }
6440
6441 if (min_mp != NULL)
6442 mp->min_address += fix->fix_size;
6443 else
6444 {
6445 /* Note the insertion point if necessary. */
6446 if (mp->min_address < min_address)
6447 {
6448 /* For now, we do not allow the insertion of 8-byte alignment
6449 requiring nodes anywhere but at the start of the pool. */
6450 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8)
6451 return NULL;
6452 else
6453 min_mp = mp;
6454 }
6455 else if (mp->max_address
6456 < minipool_barrier->address + mp->offset + fix->fix_size)
6457 {
6458 /* Inserting before this entry would push the fix beyond
6459 its maximum address (which can happen if we have
6460 re-located a forwards fix); force the new fix to come
6461 after it. */
6462 min_mp = mp;
6463 min_address = mp->min_address + fix->fix_size;
6464 }
6465 /* If we are inserting an 8-bytes aligned quantity and
6466 we have not already found an insertion point, then
6467 make sure that all such 8-byte aligned quantities are
6468 placed at the start of the pool. */
6469 else if (TARGET_REALLY_IWMMXT
6470 && min_mp == NULL
6471 && fix->fix_size == 8
6472 && mp->fix_size < 8)
6473 {
6474 min_mp = mp;
6475 min_address = mp->min_address + fix->fix_size;
6476 }
6477 }
6478 }
6479
6480 /* We need to create a new entry. */
6481 mp = xmalloc (sizeof (* mp));
6482 mp->fix_size = fix->fix_size;
6483 mp->mode = fix->mode;
6484 mp->value = fix->value;
6485 mp->refcount = 1;
6486 mp->max_address = minipool_barrier->address + 65536;
6487
6488 mp->min_address = min_address;
6489
6490 if (min_mp == NULL)
6491 {
6492 mp->prev = NULL;
6493 mp->next = minipool_vector_head;
6494
6495 if (mp->next == NULL)
6496 {
6497 minipool_vector_tail = mp;
6498 minipool_vector_label = gen_label_rtx ();
6499 }
6500 else
6501 mp->next->prev = mp;
6502
6503 minipool_vector_head = mp;
6504 }
6505 else
6506 {
6507 mp->next = min_mp->next;
6508 mp->prev = min_mp;
6509 min_mp->next = mp;
6510
6511 if (mp->next != NULL)
6512 mp->next->prev = mp;
6513 else
6514 minipool_vector_tail = mp;
6515 }
6516
6517 /* Save the new entry. */
6518 min_mp = mp;
6519
6520 if (mp->prev)
6521 mp = mp->prev;
6522 else
6523 mp->offset = 0;
6524
6525 /* Scan over the following entries and adjust their offsets. */
6526 while (mp->next != NULL)
6527 {
6528 if (mp->next->min_address < mp->min_address + mp->fix_size)
6529 mp->next->min_address = mp->min_address + mp->fix_size;
6530
6531 if (mp->refcount)
6532 mp->next->offset = mp->offset + mp->fix_size;
6533 else
6534 mp->next->offset = mp->offset;
6535
6536 mp = mp->next;
6537 }
6538
6539 return min_mp;
6540 }
6541
6542 static void
6543 assign_minipool_offsets (Mfix *barrier)
6544 {
6545 HOST_WIDE_INT offset = 0;
6546 Mnode *mp;
6547
6548 minipool_barrier = barrier;
6549
6550 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6551 {
6552 mp->offset = offset;
6553
6554 if (mp->refcount > 0)
6555 offset += mp->fix_size;
6556 }
6557 }
6558
6559 /* Output the literal table */
6560 static void
6561 dump_minipool (rtx scan)
6562 {
6563 Mnode * mp;
6564 Mnode * nmp;
6565 int align64 = 0;
6566
6567 if (TARGET_REALLY_IWMMXT)
6568 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6569 if (mp->refcount > 0 && mp->fix_size == 8)
6570 {
6571 align64 = 1;
6572 break;
6573 }
6574
6575 if (rtl_dump_file)
6576 fprintf (rtl_dump_file,
6577 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6578 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
6579
6580 scan = emit_label_after (gen_label_rtx (), scan);
6581 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
6582 scan = emit_label_after (minipool_vector_label, scan);
6583
6584 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6585 {
6586 if (mp->refcount > 0)
6587 {
6588 if (rtl_dump_file)
6589 {
6590 fprintf (rtl_dump_file,
6591 ";; Offset %u, min %ld, max %ld ",
6592 (unsigned) mp->offset, (unsigned long) mp->min_address,
6593 (unsigned long) mp->max_address);
6594 arm_print_value (rtl_dump_file, mp->value);
6595 fputc ('\n', rtl_dump_file);
6596 }
6597
6598 switch (mp->fix_size)
6599 {
6600 #ifdef HAVE_consttable_1
6601 case 1:
6602 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
6603 break;
6604
6605 #endif
6606 #ifdef HAVE_consttable_2
6607 case 2:
6608 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
6609 break;
6610
6611 #endif
6612 #ifdef HAVE_consttable_4
6613 case 4:
6614 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6615 break;
6616
6617 #endif
6618 #ifdef HAVE_consttable_8
6619 case 8:
6620 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
6621 break;
6622
6623 #endif
6624 default:
6625 abort ();
6626 break;
6627 }
6628 }
6629
6630 nmp = mp->next;
6631 free (mp);
6632 }
6633
6634 minipool_vector_head = minipool_vector_tail = NULL;
6635 scan = emit_insn_after (gen_consttable_end (), scan);
6636 scan = emit_barrier_after (scan);
6637 }
6638
6639 /* Return the cost of forcibly inserting a barrier after INSN. */
6640 static int
6641 arm_barrier_cost (rtx insn)
6642 {
6643 /* Basing the location of the pool on the loop depth is preferable,
6644 but at the moment, the basic block information seems to be
6645 corrupt by this stage of the compilation. */
6646 int base_cost = 50;
6647 rtx next = next_nonnote_insn (insn);
6648
6649 if (next != NULL && GET_CODE (next) == CODE_LABEL)
6650 base_cost -= 20;
6651
6652 switch (GET_CODE (insn))
6653 {
6654 case CODE_LABEL:
6655 /* It will always be better to place the table before the label, rather
6656 than after it. */
6657 return 50;
6658
6659 case INSN:
6660 case CALL_INSN:
6661 return base_cost;
6662
6663 case JUMP_INSN:
6664 return base_cost - 10;
6665
6666 default:
6667 return base_cost + 10;
6668 }
6669 }
6670
6671 /* Find the best place in the insn stream in the range
6672 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6673 Create the barrier by inserting a jump and add a new fix entry for
6674 it. */
6675 static Mfix *
6676 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
6677 {
6678 HOST_WIDE_INT count = 0;
6679 rtx barrier;
6680 rtx from = fix->insn;
6681 rtx selected = from;
6682 int selected_cost;
6683 HOST_WIDE_INT selected_address;
6684 Mfix * new_fix;
6685 HOST_WIDE_INT max_count = max_address - fix->address;
6686 rtx label = gen_label_rtx ();
6687
6688 selected_cost = arm_barrier_cost (from);
6689 selected_address = fix->address;
6690
6691 while (from && count < max_count)
6692 {
6693 rtx tmp;
6694 int new_cost;
6695
6696 /* This code shouldn't have been called if there was a natural barrier
6697 within range. */
6698 if (GET_CODE (from) == BARRIER)
6699 abort ();
6700
6701 /* Count the length of this insn. */
6702 count += get_attr_length (from);
6703
6704 /* If there is a jump table, add its length. */
6705 tmp = is_jump_table (from);
6706 if (tmp != NULL)
6707 {
6708 count += get_jump_table_size (tmp);
6709
6710 /* Jump tables aren't in a basic block, so base the cost on
6711 the dispatch insn. If we select this location, we will
6712 still put the pool after the table. */
6713 new_cost = arm_barrier_cost (from);
6714
6715 if (count < max_count && new_cost <= selected_cost)
6716 {
6717 selected = tmp;
6718 selected_cost = new_cost;
6719 selected_address = fix->address + count;
6720 }
6721
6722 /* Continue after the dispatch table. */
6723 from = NEXT_INSN (tmp);
6724 continue;
6725 }
6726
6727 new_cost = arm_barrier_cost (from);
6728
6729 if (count < max_count && new_cost <= selected_cost)
6730 {
6731 selected = from;
6732 selected_cost = new_cost;
6733 selected_address = fix->address + count;
6734 }
6735
6736 from = NEXT_INSN (from);
6737 }
6738
6739 /* Create a new JUMP_INSN that branches around a barrier. */
6740 from = emit_jump_insn_after (gen_jump (label), selected);
6741 JUMP_LABEL (from) = label;
6742 barrier = emit_barrier_after (from);
6743 emit_label_after (label, barrier);
6744
6745 /* Create a minipool barrier entry for the new barrier. */
6746 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
6747 new_fix->insn = barrier;
6748 new_fix->address = selected_address;
6749 new_fix->next = fix->next;
6750 fix->next = new_fix;
6751
6752 return new_fix;
6753 }
6754
6755 /* Record that there is a natural barrier in the insn stream at
6756 ADDRESS. */
6757 static void
6758 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
6759 {
6760 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6761
6762 fix->insn = insn;
6763 fix->address = address;
6764
6765 fix->next = NULL;
6766 if (minipool_fix_head != NULL)
6767 minipool_fix_tail->next = fix;
6768 else
6769 minipool_fix_head = fix;
6770
6771 minipool_fix_tail = fix;
6772 }
6773
6774 /* Record INSN, which will need fixing up to load a value from the
6775 minipool. ADDRESS is the offset of the insn since the start of the
6776 function; LOC is a pointer to the part of the insn which requires
6777 fixing; VALUE is the constant that must be loaded, which is of type
6778 MODE. */
6779 static void
6780 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
6781 enum machine_mode mode, rtx value)
6782 {
6783 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6784
6785 #ifdef AOF_ASSEMBLER
6786 /* PIC symbol references need to be converted into offsets into the
6787 based area. */
6788 /* XXX This shouldn't be done here. */
6789 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
6790 value = aof_pic_entry (value);
6791 #endif /* AOF_ASSEMBLER */
6792
6793 fix->insn = insn;
6794 fix->address = address;
6795 fix->loc = loc;
6796 fix->mode = mode;
6797 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
6798 fix->value = value;
6799 fix->forwards = get_attr_pool_range (insn);
6800 fix->backwards = get_attr_neg_pool_range (insn);
6801 fix->minipool = NULL;
6802
6803 /* If an insn doesn't have a range defined for it, then it isn't
6804 expecting to be reworked by this code. Better to abort now than
6805 to generate duff assembly code. */
6806 if (fix->forwards == 0 && fix->backwards == 0)
6807 abort ();
6808
6809 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6810 So there might be an empty word before the start of the pool.
6811 Hence we reduce the forward range by 4 to allow for this
6812 possibility. */
6813 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8)
6814 fix->forwards -= 4;
6815
6816 if (rtl_dump_file)
6817 {
6818 fprintf (rtl_dump_file,
6819 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6820 GET_MODE_NAME (mode),
6821 INSN_UID (insn), (unsigned long) address,
6822 -1 * (long)fix->backwards, (long)fix->forwards);
6823 arm_print_value (rtl_dump_file, fix->value);
6824 fprintf (rtl_dump_file, "\n");
6825 }
6826
6827 /* Add it to the chain of fixes. */
6828 fix->next = NULL;
6829
6830 if (minipool_fix_head != NULL)
6831 minipool_fix_tail->next = fix;
6832 else
6833 minipool_fix_head = fix;
6834
6835 minipool_fix_tail = fix;
6836 }
6837
6838 /* Scan INSN and note any of its operands that need fixing.
6839 If DO_PUSHES is false we do not actually push any of the fixups
6840 needed. The function returns TRUE is any fixups were needed/pushed.
6841 This is used by arm_memory_load_p() which needs to know about loads
6842 of constants that will be converted into minipool loads. */
6843 static bool
6844 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
6845 {
6846 bool result = false;
6847 int opno;
6848
6849 extract_insn (insn);
6850
6851 if (!constrain_operands (1))
6852 fatal_insn_not_found (insn);
6853
6854 /* Fill in recog_op_alt with information about the constraints of this insn. */
6855 preprocess_constraints ();
6856
6857 for (opno = 0; opno < recog_data.n_operands; opno++)
6858 {
6859 /* Things we need to fix can only occur in inputs. */
6860 if (recog_data.operand_type[opno] != OP_IN)
6861 continue;
6862
6863 /* If this alternative is a memory reference, then any mention
6864 of constants in this alternative is really to fool reload
6865 into allowing us to accept one there. We need to fix them up
6866 now so that we output the right code. */
6867 if (recog_op_alt[opno][which_alternative].memory_ok)
6868 {
6869 rtx op = recog_data.operand[opno];
6870
6871 if (CONSTANT_P (op))
6872 {
6873 if (do_pushes)
6874 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6875 recog_data.operand_mode[opno], op);
6876 result = true;
6877 }
6878 else if (GET_CODE (op) == MEM
6879 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
6880 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
6881 {
6882 if (do_pushes)
6883 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6884 recog_data.operand_mode[opno],
6885 get_pool_constant (XEXP (op, 0)));
6886
6887 result = true;
6888 }
6889 }
6890 }
6891
6892 return result;
6893 }
6894
6895 /* Gcc puts the pool in the wrong place for ARM, since we can only
6896 load addresses a limited distance around the pc. We do some
6897 special munging to move the constant pool values to the correct
6898 point in the code. */
6899 static void
6900 arm_reorg (void)
6901 {
6902 rtx insn;
6903 HOST_WIDE_INT address = 0;
6904 Mfix * fix;
6905
6906 minipool_fix_head = minipool_fix_tail = NULL;
6907
6908 /* The first insn must always be a note, or the code below won't
6909 scan it properly. */
6910 insn = get_insns ();
6911 if (GET_CODE (insn) != NOTE)
6912 abort ();
6913
6914 /* Scan all the insns and record the operands that will need fixing. */
6915 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
6916 {
6917 if (TARGET_CIRRUS_FIX_INVALID_INSNS
6918 && (arm_cirrus_insn_p (insn)
6919 || GET_CODE (insn) == JUMP_INSN
6920 || arm_memory_load_p (insn)))
6921 cirrus_reorg (insn);
6922
6923 if (GET_CODE (insn) == BARRIER)
6924 push_minipool_barrier (insn, address);
6925 else if (INSN_P (insn))
6926 {
6927 rtx table;
6928
6929 note_invalid_constants (insn, address, true);
6930 address += get_attr_length (insn);
6931
6932 /* If the insn is a vector jump, add the size of the table
6933 and skip the table. */
6934 if ((table = is_jump_table (insn)) != NULL)
6935 {
6936 address += get_jump_table_size (table);
6937 insn = table;
6938 }
6939 }
6940 }
6941
6942 fix = minipool_fix_head;
6943
6944 /* Now scan the fixups and perform the required changes. */
6945 while (fix)
6946 {
6947 Mfix * ftmp;
6948 Mfix * fdel;
6949 Mfix * last_added_fix;
6950 Mfix * last_barrier = NULL;
6951 Mfix * this_fix;
6952
6953 /* Skip any further barriers before the next fix. */
6954 while (fix && GET_CODE (fix->insn) == BARRIER)
6955 fix = fix->next;
6956
6957 /* No more fixes. */
6958 if (fix == NULL)
6959 break;
6960
6961 last_added_fix = NULL;
6962
6963 for (ftmp = fix; ftmp; ftmp = ftmp->next)
6964 {
6965 if (GET_CODE (ftmp->insn) == BARRIER)
6966 {
6967 if (ftmp->address >= minipool_vector_head->max_address)
6968 break;
6969
6970 last_barrier = ftmp;
6971 }
6972 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
6973 break;
6974
6975 last_added_fix = ftmp; /* Keep track of the last fix added. */
6976 }
6977
6978 /* If we found a barrier, drop back to that; any fixes that we
6979 could have reached but come after the barrier will now go in
6980 the next mini-pool. */
6981 if (last_barrier != NULL)
6982 {
6983 /* Reduce the refcount for those fixes that won't go into this
6984 pool after all. */
6985 for (fdel = last_barrier->next;
6986 fdel && fdel != ftmp;
6987 fdel = fdel->next)
6988 {
6989 fdel->minipool->refcount--;
6990 fdel->minipool = NULL;
6991 }
6992
6993 ftmp = last_barrier;
6994 }
6995 else
6996 {
6997 /* ftmp is first fix that we can't fit into this pool and
6998 there no natural barriers that we could use. Insert a
6999 new barrier in the code somewhere between the previous
7000 fix and this one, and arrange to jump around it. */
7001 HOST_WIDE_INT max_address;
7002
7003 /* The last item on the list of fixes must be a barrier, so
7004 we can never run off the end of the list of fixes without
7005 last_barrier being set. */
7006 if (ftmp == NULL)
7007 abort ();
7008
7009 max_address = minipool_vector_head->max_address;
7010 /* Check that there isn't another fix that is in range that
7011 we couldn't fit into this pool because the pool was
7012 already too large: we need to put the pool before such an
7013 instruction. */
7014 if (ftmp->address < max_address)
7015 max_address = ftmp->address;
7016
7017 last_barrier = create_fix_barrier (last_added_fix, max_address);
7018 }
7019
7020 assign_minipool_offsets (last_barrier);
7021
7022 while (ftmp)
7023 {
7024 if (GET_CODE (ftmp->insn) != BARRIER
7025 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7026 == NULL))
7027 break;
7028
7029 ftmp = ftmp->next;
7030 }
7031
7032 /* Scan over the fixes we have identified for this pool, fixing them
7033 up and adding the constants to the pool itself. */
7034 for (this_fix = fix; this_fix && ftmp != this_fix;
7035 this_fix = this_fix->next)
7036 if (GET_CODE (this_fix->insn) != BARRIER)
7037 {
7038 rtx addr
7039 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7040 minipool_vector_label),
7041 this_fix->minipool->offset);
7042 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7043 }
7044
7045 dump_minipool (last_barrier->insn);
7046 fix = ftmp;
7047 }
7048
7049 /* From now on we must synthesize any constants that we can't handle
7050 directly. This can happen if the RTL gets split during final
7051 instruction generation. */
7052 after_arm_reorg = 1;
7053
7054 /* Free the minipool memory. */
7055 obstack_free (&minipool_obstack, minipool_startobj);
7056 }
7057 \f
7058 /* Routines to output assembly language. */
7059
7060 /* If the rtx is the correct value then return the string of the number.
7061 In this way we can ensure that valid double constants are generated even
7062 when cross compiling. */
7063 const char *
7064 fp_immediate_constant (rtx x)
7065 {
7066 REAL_VALUE_TYPE r;
7067 int i;
7068
7069 if (!fpa_consts_inited)
7070 init_fpa_table ();
7071
7072 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7073 for (i = 0; i < 8; i++)
7074 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
7075 return strings_fpa[i];
7076
7077 abort ();
7078 }
7079
7080 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7081 static const char *
7082 fp_const_from_val (REAL_VALUE_TYPE *r)
7083 {
7084 int i;
7085
7086 if (!fpa_consts_inited)
7087 init_fpa_table ();
7088
7089 for (i = 0; i < 8; i++)
7090 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
7091 return strings_fpa[i];
7092
7093 abort ();
7094 }
7095
7096 /* Output the operands of a LDM/STM instruction to STREAM.
7097 MASK is the ARM register set mask of which only bits 0-15 are important.
7098 REG is the base register, either the frame pointer or the stack pointer,
7099 INSTR is the possibly suffixed load or store instruction. */
7100 static void
7101 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7102 {
7103 int i;
7104 int not_first = FALSE;
7105
7106 fputc ('\t', stream);
7107 asm_fprintf (stream, instr, reg);
7108 fputs (", {", stream);
7109
7110 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7111 if (mask & (1 << i))
7112 {
7113 if (not_first)
7114 fprintf (stream, ", ");
7115
7116 asm_fprintf (stream, "%r", i);
7117 not_first = TRUE;
7118 }
7119
7120 fprintf (stream, "}");
7121
7122 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7123 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7124 Strictly speaking the instruction would be unpredicatble only if
7125 we were writing back the base register as well, but since we never
7126 want to generate an LDM type 2 instruction (register bank switching)
7127 which is what you get if the PC is not being loaded, we do not need
7128 to check for writeback. */
7129 if (! TARGET_APCS_32
7130 && ((mask & (1 << PC_REGNUM)) != 0))
7131 fprintf (stream, "^");
7132
7133 fprintf (stream, "\n");
7134 }
7135
7136 /* Output a 'call' insn. */
7137 const char *
7138 output_call (rtx *operands)
7139 {
7140 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7141
7142 if (REGNO (operands[0]) == LR_REGNUM)
7143 {
7144 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7145 output_asm_insn ("mov%?\t%0, %|lr", operands);
7146 }
7147
7148 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7149
7150 if (TARGET_INTERWORK)
7151 output_asm_insn ("bx%?\t%0", operands);
7152 else
7153 output_asm_insn ("mov%?\t%|pc, %0", operands);
7154
7155 return "";
7156 }
7157
7158 /* Output a 'call' insn that is a reference in memory. */
7159 const char *
7160 output_call_mem (rtx *operands)
7161 {
7162 if (TARGET_INTERWORK)
7163 {
7164 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7165 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7166 output_asm_insn ("bx%?\t%|ip", operands);
7167 }
7168 else if (regno_use_in (LR_REGNUM, operands[0]))
7169 {
7170 /* LR is used in the memory address. We load the address in the
7171 first instruction. It's safe to use IP as the target of the
7172 load since the call will kill it anyway. */
7173 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7174 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7175 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7176 }
7177 else
7178 {
7179 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7180 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7181 }
7182
7183 return "";
7184 }
7185
7186
7187 /* Output a move from arm registers to an fpa registers.
7188 OPERANDS[0] is an fpa register.
7189 OPERANDS[1] is the first registers of an arm register pair. */
7190 const char *
7191 output_mov_long_double_fpa_from_arm (rtx *operands)
7192 {
7193 int arm_reg0 = REGNO (operands[1]);
7194 rtx ops[3];
7195
7196 if (arm_reg0 == IP_REGNUM)
7197 abort ();
7198
7199 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7200 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7201 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7202
7203 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7204 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7205
7206 return "";
7207 }
7208
7209 /* Output a move from an fpa register to arm registers.
7210 OPERANDS[0] is the first registers of an arm register pair.
7211 OPERANDS[1] is an fpa register. */
7212 const char *
7213 output_mov_long_double_arm_from_fpa (rtx *operands)
7214 {
7215 int arm_reg0 = REGNO (operands[0]);
7216 rtx ops[3];
7217
7218 if (arm_reg0 == IP_REGNUM)
7219 abort ();
7220
7221 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7222 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7223 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7224
7225 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7226 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7227 return "";
7228 }
7229
7230 /* Output a move from arm registers to arm registers of a long double
7231 OPERANDS[0] is the destination.
7232 OPERANDS[1] is the source. */
7233 const char *
7234 output_mov_long_double_arm_from_arm (rtx *operands)
7235 {
7236 /* We have to be careful here because the two might overlap. */
7237 int dest_start = REGNO (operands[0]);
7238 int src_start = REGNO (operands[1]);
7239 rtx ops[2];
7240 int i;
7241
7242 if (dest_start < src_start)
7243 {
7244 for (i = 0; i < 3; i++)
7245 {
7246 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7247 ops[1] = gen_rtx_REG (SImode, src_start + i);
7248 output_asm_insn ("mov%?\t%0, %1", ops);
7249 }
7250 }
7251 else
7252 {
7253 for (i = 2; i >= 0; i--)
7254 {
7255 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7256 ops[1] = gen_rtx_REG (SImode, src_start + i);
7257 output_asm_insn ("mov%?\t%0, %1", ops);
7258 }
7259 }
7260
7261 return "";
7262 }
7263
7264
7265 /* Output a move from arm registers to an fpa registers.
7266 OPERANDS[0] is an fpa register.
7267 OPERANDS[1] is the first registers of an arm register pair. */
7268 const char *
7269 output_mov_double_fpa_from_arm (rtx *operands)
7270 {
7271 int arm_reg0 = REGNO (operands[1]);
7272 rtx ops[2];
7273
7274 if (arm_reg0 == IP_REGNUM)
7275 abort ();
7276
7277 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7278 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7279 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7280 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7281 return "";
7282 }
7283
7284 /* Output a move from an fpa register to arm registers.
7285 OPERANDS[0] is the first registers of an arm register pair.
7286 OPERANDS[1] is an fpa register. */
7287 const char *
7288 output_mov_double_arm_from_fpa (rtx *operands)
7289 {
7290 int arm_reg0 = REGNO (operands[0]);
7291 rtx ops[2];
7292
7293 if (arm_reg0 == IP_REGNUM)
7294 abort ();
7295
7296 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7297 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7298 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7299 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7300 return "";
7301 }
7302
7303 /* Output a move between double words.
7304 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7305 or MEM<-REG and all MEMs must be offsettable addresses. */
7306 const char *
7307 output_move_double (rtx *operands)
7308 {
7309 enum rtx_code code0 = GET_CODE (operands[0]);
7310 enum rtx_code code1 = GET_CODE (operands[1]);
7311 rtx otherops[3];
7312
7313 if (code0 == REG)
7314 {
7315 int reg0 = REGNO (operands[0]);
7316
7317 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7318
7319 if (code1 == REG)
7320 {
7321 int reg1 = REGNO (operands[1]);
7322 if (reg1 == IP_REGNUM)
7323 abort ();
7324
7325 /* Ensure the second source is not overwritten. */
7326 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7327 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7328 else
7329 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7330 }
7331 else if (code1 == CONST_VECTOR)
7332 {
7333 HOST_WIDE_INT hint = 0;
7334
7335 switch (GET_MODE (operands[1]))
7336 {
7337 case V2SImode:
7338 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
7339 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
7340 break;
7341
7342 case V4HImode:
7343 if (BYTES_BIG_ENDIAN)
7344 {
7345 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7346 hint <<= 16;
7347 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7348 }
7349 else
7350 {
7351 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7352 hint <<= 16;
7353 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7354 }
7355
7356 otherops[1] = GEN_INT (hint);
7357 hint = 0;
7358
7359 if (BYTES_BIG_ENDIAN)
7360 {
7361 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7362 hint <<= 16;
7363 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7364 }
7365 else
7366 {
7367 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7368 hint <<= 16;
7369 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7370 }
7371
7372 operands[1] = GEN_INT (hint);
7373 break;
7374
7375 case V8QImode:
7376 if (BYTES_BIG_ENDIAN)
7377 {
7378 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7379 hint <<= 8;
7380 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7381 hint <<= 8;
7382 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7383 hint <<= 8;
7384 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7385 }
7386 else
7387 {
7388 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7389 hint <<= 8;
7390 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7391 hint <<= 8;
7392 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7393 hint <<= 8;
7394 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7395 }
7396
7397 otherops[1] = GEN_INT (hint);
7398 hint = 0;
7399
7400 if (BYTES_BIG_ENDIAN)
7401 {
7402 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7403 hint <<= 8;
7404 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7405 hint <<= 8;
7406 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7407 hint <<= 8;
7408 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7409 }
7410 else
7411 {
7412 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7413 hint <<= 8;
7414 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7415 hint <<= 8;
7416 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7417 hint <<= 8;
7418 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7419 }
7420
7421 operands[1] = GEN_INT (hint);
7422 break;
7423
7424 default:
7425 abort ();
7426 }
7427 output_mov_immediate (operands);
7428 output_mov_immediate (otherops);
7429 }
7430 else if (code1 == CONST_DOUBLE)
7431 {
7432 if (GET_MODE (operands[1]) == DFmode)
7433 {
7434 REAL_VALUE_TYPE r;
7435 long l[2];
7436
7437 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
7438 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
7439 otherops[1] = GEN_INT (l[1]);
7440 operands[1] = GEN_INT (l[0]);
7441 }
7442 else if (GET_MODE (operands[1]) != VOIDmode)
7443 abort ();
7444 else if (WORDS_BIG_ENDIAN)
7445 {
7446 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7447 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7448 }
7449 else
7450 {
7451 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7452 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7453 }
7454
7455 output_mov_immediate (operands);
7456 output_mov_immediate (otherops);
7457 }
7458 else if (code1 == CONST_INT)
7459 {
7460 #if HOST_BITS_PER_WIDE_INT > 32
7461 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7462 what the upper word is. */
7463 if (WORDS_BIG_ENDIAN)
7464 {
7465 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7466 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7467 }
7468 else
7469 {
7470 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7471 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7472 }
7473 #else
7474 /* Sign extend the intval into the high-order word. */
7475 if (WORDS_BIG_ENDIAN)
7476 {
7477 otherops[1] = operands[1];
7478 operands[1] = (INTVAL (operands[1]) < 0
7479 ? constm1_rtx : const0_rtx);
7480 }
7481 else
7482 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
7483 #endif
7484 output_mov_immediate (otherops);
7485 output_mov_immediate (operands);
7486 }
7487 else if (code1 == MEM)
7488 {
7489 switch (GET_CODE (XEXP (operands[1], 0)))
7490 {
7491 case REG:
7492 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
7493 break;
7494
7495 case PRE_INC:
7496 abort (); /* Should never happen now. */
7497 break;
7498
7499 case PRE_DEC:
7500 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
7501 break;
7502
7503 case POST_INC:
7504 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
7505 break;
7506
7507 case POST_DEC:
7508 abort (); /* Should never happen now. */
7509 break;
7510
7511 case LABEL_REF:
7512 case CONST:
7513 output_asm_insn ("adr%?\t%0, %1", operands);
7514 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
7515 break;
7516
7517 default:
7518 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
7519 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
7520 {
7521 otherops[0] = operands[0];
7522 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
7523 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
7524
7525 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
7526 {
7527 if (GET_CODE (otherops[2]) == CONST_INT)
7528 {
7529 switch ((int) INTVAL (otherops[2]))
7530 {
7531 case -8:
7532 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
7533 return "";
7534 case -4:
7535 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
7536 return "";
7537 case 4:
7538 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
7539 return "";
7540 }
7541
7542 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
7543 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
7544 else
7545 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7546 }
7547 else
7548 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7549 }
7550 else
7551 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
7552
7553 return "ldm%?ia\t%0, %M0";
7554 }
7555 else
7556 {
7557 otherops[1] = adjust_address (operands[1], SImode, 4);
7558 /* Take care of overlapping base/data reg. */
7559 if (reg_mentioned_p (operands[0], operands[1]))
7560 {
7561 output_asm_insn ("ldr%?\t%0, %1", otherops);
7562 output_asm_insn ("ldr%?\t%0, %1", operands);
7563 }
7564 else
7565 {
7566 output_asm_insn ("ldr%?\t%0, %1", operands);
7567 output_asm_insn ("ldr%?\t%0, %1", otherops);
7568 }
7569 }
7570 }
7571 }
7572 else
7573 abort (); /* Constraints should prevent this. */
7574 }
7575 else if (code0 == MEM && code1 == REG)
7576 {
7577 if (REGNO (operands[1]) == IP_REGNUM)
7578 abort ();
7579
7580 switch (GET_CODE (XEXP (operands[0], 0)))
7581 {
7582 case REG:
7583 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
7584 break;
7585
7586 case PRE_INC:
7587 abort (); /* Should never happen now. */
7588 break;
7589
7590 case PRE_DEC:
7591 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
7592 break;
7593
7594 case POST_INC:
7595 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
7596 break;
7597
7598 case POST_DEC:
7599 abort (); /* Should never happen now. */
7600 break;
7601
7602 case PLUS:
7603 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
7604 {
7605 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
7606 {
7607 case -8:
7608 output_asm_insn ("stm%?db\t%m0, %M1", operands);
7609 return "";
7610
7611 case -4:
7612 output_asm_insn ("stm%?da\t%m0, %M1", operands);
7613 return "";
7614
7615 case 4:
7616 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
7617 return "";
7618 }
7619 }
7620 /* Fall through */
7621
7622 default:
7623 otherops[0] = adjust_address (operands[0], SImode, 4);
7624 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
7625 output_asm_insn ("str%?\t%1, %0", operands);
7626 output_asm_insn ("str%?\t%1, %0", otherops);
7627 }
7628 }
7629 else
7630 /* Constraints should prevent this. */
7631 abort ();
7632
7633 return "";
7634 }
7635
7636
7637 /* Output an arbitrary MOV reg, #n.
7638 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7639 const char *
7640 output_mov_immediate (rtx *operands)
7641 {
7642 HOST_WIDE_INT n = INTVAL (operands[1]);
7643
7644 /* Try to use one MOV. */
7645 if (const_ok_for_arm (n))
7646 output_asm_insn ("mov%?\t%0, %1", operands);
7647
7648 /* Try to use one MVN. */
7649 else if (const_ok_for_arm (~n))
7650 {
7651 operands[1] = GEN_INT (~n);
7652 output_asm_insn ("mvn%?\t%0, %1", operands);
7653 }
7654 else
7655 {
7656 int n_ones = 0;
7657 int i;
7658
7659 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7660 for (i = 0; i < 32; i++)
7661 if (n & 1 << i)
7662 n_ones++;
7663
7664 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
7665 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
7666 else
7667 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
7668 }
7669
7670 return "";
7671 }
7672
7673 /* Output an ADD r, s, #n where n may be too big for one instruction.
7674 If adding zero to one register, output nothing. */
7675 const char *
7676 output_add_immediate (rtx *operands)
7677 {
7678 HOST_WIDE_INT n = INTVAL (operands[2]);
7679
7680 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
7681 {
7682 if (n < 0)
7683 output_multi_immediate (operands,
7684 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7685 -n);
7686 else
7687 output_multi_immediate (operands,
7688 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7689 n);
7690 }
7691
7692 return "";
7693 }
7694
7695 /* Output a multiple immediate operation.
7696 OPERANDS is the vector of operands referred to in the output patterns.
7697 INSTR1 is the output pattern to use for the first constant.
7698 INSTR2 is the output pattern to use for subsequent constants.
7699 IMMED_OP is the index of the constant slot in OPERANDS.
7700 N is the constant value. */
7701 static const char *
7702 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
7703 int immed_op, HOST_WIDE_INT n)
7704 {
7705 #if HOST_BITS_PER_WIDE_INT > 32
7706 n &= 0xffffffff;
7707 #endif
7708
7709 if (n == 0)
7710 {
7711 /* Quick and easy output. */
7712 operands[immed_op] = const0_rtx;
7713 output_asm_insn (instr1, operands);
7714 }
7715 else
7716 {
7717 int i;
7718 const char * instr = instr1;
7719
7720 /* Note that n is never zero here (which would give no output). */
7721 for (i = 0; i < 32; i += 2)
7722 {
7723 if (n & (3 << i))
7724 {
7725 operands[immed_op] = GEN_INT (n & (255 << i));
7726 output_asm_insn (instr, operands);
7727 instr = instr2;
7728 i += 6;
7729 }
7730 }
7731 }
7732
7733 return "";
7734 }
7735
7736 /* Return the appropriate ARM instruction for the operation code.
7737 The returned result should not be overwritten. OP is the rtx of the
7738 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7739 was shifted. */
7740 const char *
7741 arithmetic_instr (rtx op, int shift_first_arg)
7742 {
7743 switch (GET_CODE (op))
7744 {
7745 case PLUS:
7746 return "add";
7747
7748 case MINUS:
7749 return shift_first_arg ? "rsb" : "sub";
7750
7751 case IOR:
7752 return "orr";
7753
7754 case XOR:
7755 return "eor";
7756
7757 case AND:
7758 return "and";
7759
7760 default:
7761 abort ();
7762 }
7763 }
7764
7765 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7766 for the operation code. The returned result should not be overwritten.
7767 OP is the rtx code of the shift.
7768 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7769 shift. */
7770 static const char *
7771 shift_op (rtx op, HOST_WIDE_INT *amountp)
7772 {
7773 const char * mnem;
7774 enum rtx_code code = GET_CODE (op);
7775
7776 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
7777 *amountp = -1;
7778 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
7779 *amountp = INTVAL (XEXP (op, 1));
7780 else
7781 abort ();
7782
7783 switch (code)
7784 {
7785 case ASHIFT:
7786 mnem = "asl";
7787 break;
7788
7789 case ASHIFTRT:
7790 mnem = "asr";
7791 break;
7792
7793 case LSHIFTRT:
7794 mnem = "lsr";
7795 break;
7796
7797 case ROTATERT:
7798 mnem = "ror";
7799 break;
7800
7801 case MULT:
7802 /* We never have to worry about the amount being other than a
7803 power of 2, since this case can never be reloaded from a reg. */
7804 if (*amountp != -1)
7805 *amountp = int_log2 (*amountp);
7806 else
7807 abort ();
7808 return "asl";
7809
7810 default:
7811 abort ();
7812 }
7813
7814 if (*amountp != -1)
7815 {
7816 /* This is not 100% correct, but follows from the desire to merge
7817 multiplication by a power of 2 with the recognizer for a
7818 shift. >=32 is not a valid shift for "asl", so we must try and
7819 output a shift that produces the correct arithmetical result.
7820 Using lsr #32 is identical except for the fact that the carry bit
7821 is not set correctly if we set the flags; but we never use the
7822 carry bit from such an operation, so we can ignore that. */
7823 if (code == ROTATERT)
7824 /* Rotate is just modulo 32. */
7825 *amountp &= 31;
7826 else if (*amountp != (*amountp & 31))
7827 {
7828 if (code == ASHIFT)
7829 mnem = "lsr";
7830 *amountp = 32;
7831 }
7832
7833 /* Shifts of 0 are no-ops. */
7834 if (*amountp == 0)
7835 return NULL;
7836 }
7837
7838 return mnem;
7839 }
7840
7841 /* Obtain the shift from the POWER of two. */
7842
7843 static HOST_WIDE_INT
7844 int_log2 (HOST_WIDE_INT power)
7845 {
7846 HOST_WIDE_INT shift = 0;
7847
7848 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
7849 {
7850 if (shift > 31)
7851 abort ();
7852 shift++;
7853 }
7854
7855 return shift;
7856 }
7857
7858 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7859 /bin/as is horribly restrictive. */
7860 #define MAX_ASCII_LEN 51
7861
7862 void
7863 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
7864 {
7865 int i;
7866 int len_so_far = 0;
7867
7868 fputs ("\t.ascii\t\"", stream);
7869
7870 for (i = 0; i < len; i++)
7871 {
7872 int c = p[i];
7873
7874 if (len_so_far >= MAX_ASCII_LEN)
7875 {
7876 fputs ("\"\n\t.ascii\t\"", stream);
7877 len_so_far = 0;
7878 }
7879
7880 switch (c)
7881 {
7882 case TARGET_TAB:
7883 fputs ("\\t", stream);
7884 len_so_far += 2;
7885 break;
7886
7887 case TARGET_FF:
7888 fputs ("\\f", stream);
7889 len_so_far += 2;
7890 break;
7891
7892 case TARGET_BS:
7893 fputs ("\\b", stream);
7894 len_so_far += 2;
7895 break;
7896
7897 case TARGET_CR:
7898 fputs ("\\r", stream);
7899 len_so_far += 2;
7900 break;
7901
7902 case TARGET_NEWLINE:
7903 fputs ("\\n", stream);
7904 c = p [i + 1];
7905 if ((c >= ' ' && c <= '~')
7906 || c == TARGET_TAB)
7907 /* This is a good place for a line break. */
7908 len_so_far = MAX_ASCII_LEN;
7909 else
7910 len_so_far += 2;
7911 break;
7912
7913 case '\"':
7914 case '\\':
7915 putc ('\\', stream);
7916 len_so_far++;
7917 /* drop through. */
7918
7919 default:
7920 if (c >= ' ' && c <= '~')
7921 {
7922 putc (c, stream);
7923 len_so_far++;
7924 }
7925 else
7926 {
7927 fprintf (stream, "\\%03o", c);
7928 len_so_far += 4;
7929 }
7930 break;
7931 }
7932 }
7933
7934 fputs ("\"\n", stream);
7935 }
7936 \f
7937 /* Compute the register sabe mask for registers 0 through 12
7938 inclusive. This code is used by both arm_compute_save_reg_mask
7939 and arm_compute_initial_elimination_offset. */
7940 static unsigned long
7941 arm_compute_save_reg0_reg12_mask (void)
7942 {
7943 unsigned long func_type = arm_current_func_type ();
7944 unsigned int save_reg_mask = 0;
7945 unsigned int reg;
7946
7947 if (IS_INTERRUPT (func_type))
7948 {
7949 unsigned int max_reg;
7950 /* Interrupt functions must not corrupt any registers,
7951 even call clobbered ones. If this is a leaf function
7952 we can just examine the registers used by the RTL, but
7953 otherwise we have to assume that whatever function is
7954 called might clobber anything, and so we have to save
7955 all the call-clobbered registers as well. */
7956 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7957 /* FIQ handlers have registers r8 - r12 banked, so
7958 we only need to check r0 - r7, Normal ISRs only
7959 bank r14 and r15, so we must check up to r12.
7960 r13 is the stack pointer which is always preserved,
7961 so we do not need to consider it here. */
7962 max_reg = 7;
7963 else
7964 max_reg = 12;
7965
7966 for (reg = 0; reg <= max_reg; reg++)
7967 if (regs_ever_live[reg]
7968 || (! current_function_is_leaf && call_used_regs [reg]))
7969 save_reg_mask |= (1 << reg);
7970 }
7971 else
7972 {
7973 /* In the normal case we only need to save those registers
7974 which are call saved and which are used by this function. */
7975 for (reg = 0; reg <= 10; reg++)
7976 if (regs_ever_live[reg] && ! call_used_regs [reg])
7977 save_reg_mask |= (1 << reg);
7978
7979 /* Handle the frame pointer as a special case. */
7980 if (! TARGET_APCS_FRAME
7981 && ! frame_pointer_needed
7982 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7983 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
7984 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
7985
7986 /* If we aren't loading the PIC register,
7987 don't stack it even though it may be live. */
7988 if (flag_pic
7989 && ! TARGET_SINGLE_PIC_BASE
7990 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7991 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
7992 }
7993
7994 return save_reg_mask;
7995 }
7996
7997 /* Compute a bit mask of which registers need to be
7998 saved on the stack for the current function. */
7999
8000 static unsigned long
8001 arm_compute_save_reg_mask (void)
8002 {
8003 unsigned int save_reg_mask = 0;
8004 unsigned long func_type = arm_current_func_type ();
8005
8006 if (IS_NAKED (func_type))
8007 /* This should never really happen. */
8008 return 0;
8009
8010 /* If we are creating a stack frame, then we must save the frame pointer,
8011 IP (which will hold the old stack pointer), LR and the PC. */
8012 if (frame_pointer_needed)
8013 save_reg_mask |=
8014 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8015 | (1 << IP_REGNUM)
8016 | (1 << LR_REGNUM)
8017 | (1 << PC_REGNUM);
8018
8019 /* Volatile functions do not return, so there
8020 is no need to save any other registers. */
8021 if (IS_VOLATILE (func_type))
8022 return save_reg_mask;
8023
8024 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8025
8026 /* Decide if we need to save the link register.
8027 Interrupt routines have their own banked link register,
8028 so they never need to save it.
8029 Otherwise if we do not use the link register we do not need to save
8030 it. If we are pushing other registers onto the stack however, we
8031 can save an instruction in the epilogue by pushing the link register
8032 now and then popping it back into the PC. This incurs extra memory
8033 accesses though, so we only do it when optimizing for size, and only
8034 if we know that we will not need a fancy return sequence. */
8035 if (regs_ever_live [LR_REGNUM]
8036 || (save_reg_mask
8037 && optimize_size
8038 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8039 save_reg_mask |= 1 << LR_REGNUM;
8040
8041 if (cfun->machine->lr_save_eliminated)
8042 save_reg_mask &= ~ (1 << LR_REGNUM);
8043
8044 if (TARGET_REALLY_IWMMXT
8045 && ((bit_count (save_reg_mask)
8046 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8047 {
8048 unsigned int reg;
8049
8050 /* The total number of registers that are going to be pushed
8051 onto the stack is odd. We need to ensure that the stack
8052 is 64-bit aligned before we start to save iWMMXt registers,
8053 and also before we start to create locals. (A local variable
8054 might be a double or long long which we will load/store using
8055 an iWMMXt instruction). Therefore we need to push another
8056 ARM register, so that the stack will be 64-bit aligned. We
8057 try to avoid using the arg registers (r0 -r3) as they might be
8058 used to pass values in a tail call. */
8059 for (reg = 4; reg <= 12; reg++)
8060 if ((save_reg_mask & (1 << reg)) == 0)
8061 break;
8062
8063 if (reg <= 12)
8064 save_reg_mask |= (1 << reg);
8065 else
8066 {
8067 cfun->machine->sibcall_blocked = 1;
8068 save_reg_mask |= (1 << 3);
8069 }
8070 }
8071
8072 return save_reg_mask;
8073 }
8074
8075 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
8076 everything bar the final return instruction. */
8077 const char *
8078 output_return_instruction (rtx operand, int really_return, int reverse)
8079 {
8080 char conditional[10];
8081 char instr[100];
8082 int reg;
8083 unsigned long live_regs_mask;
8084 unsigned long func_type;
8085
8086 func_type = arm_current_func_type ();
8087
8088 if (IS_NAKED (func_type))
8089 return "";
8090
8091 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8092 {
8093 /* If this function was declared non-returning, and we have found a tail
8094 call, then we have to trust that the called function won't return. */
8095 if (really_return)
8096 {
8097 rtx ops[2];
8098
8099 /* Otherwise, trap an attempted return by aborting. */
8100 ops[0] = operand;
8101 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8102 : "abort");
8103 assemble_external_libcall (ops[1]);
8104 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8105 }
8106
8107 return "";
8108 }
8109
8110 if (current_function_calls_alloca && !really_return)
8111 abort ();
8112
8113 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8114
8115 return_used_this_function = 1;
8116
8117 live_regs_mask = arm_compute_save_reg_mask ();
8118
8119 if (live_regs_mask)
8120 {
8121 const char * return_reg;
8122
8123 /* If we do not have any special requirements for function exit
8124 (eg interworking, or ISR) then we can load the return address
8125 directly into the PC. Otherwise we must load it into LR. */
8126 if (really_return
8127 && ! TARGET_INTERWORK)
8128 return_reg = reg_names[PC_REGNUM];
8129 else
8130 return_reg = reg_names[LR_REGNUM];
8131
8132 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8133 /* There are two possible reasons for the IP register being saved.
8134 Either a stack frame was created, in which case IP contains the
8135 old stack pointer, or an ISR routine corrupted it. If this in an
8136 ISR routine then just restore IP, otherwise restore IP into SP. */
8137 if (! IS_INTERRUPT (func_type))
8138 {
8139 live_regs_mask &= ~ (1 << IP_REGNUM);
8140 live_regs_mask |= (1 << SP_REGNUM);
8141 }
8142
8143 /* On some ARM architectures it is faster to use LDR rather than
8144 LDM to load a single register. On other architectures, the
8145 cost is the same. In 26 bit mode, or for exception handlers,
8146 we have to use LDM to load the PC so that the CPSR is also
8147 restored. */
8148 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8149 {
8150 if (live_regs_mask == (unsigned int)(1 << reg))
8151 break;
8152 }
8153 if (reg <= LAST_ARM_REGNUM
8154 && (reg != LR_REGNUM
8155 || ! really_return
8156 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
8157 {
8158 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8159 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8160 }
8161 else
8162 {
8163 char *p;
8164 int first = 1;
8165
8166 /* Generate the load multiple instruction to restore the registers. */
8167 if (frame_pointer_needed)
8168 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
8169 else if (live_regs_mask & (1 << SP_REGNUM))
8170 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8171 else
8172 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8173
8174 p = instr + strlen (instr);
8175
8176 for (reg = 0; reg <= SP_REGNUM; reg++)
8177 if (live_regs_mask & (1 << reg))
8178 {
8179 int l = strlen (reg_names[reg]);
8180
8181 if (first)
8182 first = 0;
8183 else
8184 {
8185 memcpy (p, ", ", 2);
8186 p += 2;
8187 }
8188
8189 memcpy (p, "%|", 2);
8190 memcpy (p + 2, reg_names[reg], l);
8191 p += l + 2;
8192 }
8193
8194 if (live_regs_mask & (1 << LR_REGNUM))
8195 {
8196 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
8197 /* Decide if we need to add the ^ symbol to the end of the
8198 register list. This causes the saved condition codes
8199 register to be copied into the current condition codes
8200 register. We do the copy if we are conforming to the 32-bit
8201 ABI and this is an interrupt function, or if we are
8202 conforming to the 26-bit ABI. There is a special case for
8203 the 26-bit ABI however, which is if we are writing back the
8204 stack pointer but not loading the PC. In this case adding
8205 the ^ symbol would create a type 2 LDM instruction, where
8206 writeback is UNPREDICTABLE. We are safe in leaving the ^
8207 character off in this case however, since the actual return
8208 instruction will be a MOVS which will restore the CPSR. */
8209 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
8210 || (! TARGET_APCS_32 && really_return))
8211 strcat (p, "^");
8212 }
8213 else
8214 strcpy (p, "}");
8215 }
8216
8217 output_asm_insn (instr, & operand);
8218
8219 /* See if we need to generate an extra instruction to
8220 perform the actual function return. */
8221 if (really_return
8222 && func_type != ARM_FT_INTERWORKED
8223 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8224 {
8225 /* The return has already been handled
8226 by loading the LR into the PC. */
8227 really_return = 0;
8228 }
8229 }
8230
8231 if (really_return)
8232 {
8233 switch ((int) ARM_FUNC_TYPE (func_type))
8234 {
8235 case ARM_FT_ISR:
8236 case ARM_FT_FIQ:
8237 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8238 break;
8239
8240 case ARM_FT_INTERWORKED:
8241 sprintf (instr, "bx%s\t%%|lr", conditional);
8242 break;
8243
8244 case ARM_FT_EXCEPTION:
8245 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8246 break;
8247
8248 default:
8249 /* ARMv5 implementations always provide BX, so interworking
8250 is the default unless APCS-26 is in use. */
8251 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
8252 sprintf (instr, "bx%s\t%%|lr", conditional);
8253 else
8254 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
8255 conditional, TARGET_APCS_32 ? "" : "s");
8256 break;
8257 }
8258
8259 output_asm_insn (instr, & operand);
8260 }
8261
8262 return "";
8263 }
8264
8265 /* Write the function name into the code section, directly preceding
8266 the function prologue.
8267
8268 Code will be output similar to this:
8269 t0
8270 .ascii "arm_poke_function_name", 0
8271 .align
8272 t1
8273 .word 0xff000000 + (t1 - t0)
8274 arm_poke_function_name
8275 mov ip, sp
8276 stmfd sp!, {fp, ip, lr, pc}
8277 sub fp, ip, #4
8278
8279 When performing a stack backtrace, code can inspect the value
8280 of 'pc' stored at 'fp' + 0. If the trace function then looks
8281 at location pc - 12 and the top 8 bits are set, then we know
8282 that there is a function name embedded immediately preceding this
8283 location and has length ((pc[-3]) & 0xff000000).
8284
8285 We assume that pc is declared as a pointer to an unsigned long.
8286
8287 It is of no benefit to output the function name if we are assembling
8288 a leaf function. These function types will not contain a stack
8289 backtrace structure, therefore it is not possible to determine the
8290 function name. */
8291 void
8292 arm_poke_function_name (FILE *stream, const char *name)
8293 {
8294 unsigned long alignlength;
8295 unsigned long length;
8296 rtx x;
8297
8298 length = strlen (name) + 1;
8299 alignlength = ROUND_UP_WORD (length);
8300
8301 ASM_OUTPUT_ASCII (stream, name, length);
8302 ASM_OUTPUT_ALIGN (stream, 2);
8303 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
8304 assemble_aligned_integer (UNITS_PER_WORD, x);
8305 }
8306
8307 /* Place some comments into the assembler stream
8308 describing the current function. */
8309 static void
8310 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
8311 {
8312 unsigned long func_type;
8313
8314 if (!TARGET_ARM)
8315 {
8316 thumb_output_function_prologue (f, frame_size);
8317 return;
8318 }
8319
8320 /* Sanity check. */
8321 if (arm_ccfsm_state || arm_target_insn)
8322 abort ();
8323
8324 func_type = arm_current_func_type ();
8325
8326 switch ((int) ARM_FUNC_TYPE (func_type))
8327 {
8328 default:
8329 case ARM_FT_NORMAL:
8330 break;
8331 case ARM_FT_INTERWORKED:
8332 asm_fprintf (f, "\t%@ Function supports interworking.\n");
8333 break;
8334 case ARM_FT_EXCEPTION_HANDLER:
8335 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
8336 break;
8337 case ARM_FT_ISR:
8338 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
8339 break;
8340 case ARM_FT_FIQ:
8341 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
8342 break;
8343 case ARM_FT_EXCEPTION:
8344 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
8345 break;
8346 }
8347
8348 if (IS_NAKED (func_type))
8349 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8350
8351 if (IS_VOLATILE (func_type))
8352 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
8353
8354 if (IS_NESTED (func_type))
8355 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
8356
8357 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8358 current_function_args_size,
8359 current_function_pretend_args_size, frame_size);
8360
8361 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8362 frame_pointer_needed,
8363 cfun->machine->uses_anonymous_args);
8364
8365 if (cfun->machine->lr_save_eliminated)
8366 asm_fprintf (f, "\t%@ link register save eliminated.\n");
8367
8368 #ifdef AOF_ASSEMBLER
8369 if (flag_pic)
8370 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
8371 #endif
8372
8373 return_used_this_function = 0;
8374 }
8375
8376 const char *
8377 arm_output_epilogue (int really_return)
8378 {
8379 int reg;
8380 unsigned long saved_regs_mask;
8381 unsigned long func_type;
8382 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8383 frame that is $fp + 4 for a non-variadic function. */
8384 int floats_offset = 0;
8385 rtx operands[3];
8386 int frame_size = arm_get_frame_size ();
8387 FILE * f = asm_out_file;
8388 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
8389 unsigned int lrm_count = 0;
8390
8391 /* If we have already generated the return instruction
8392 then it is futile to generate anything else. */
8393 if (use_return_insn (FALSE) && return_used_this_function)
8394 return "";
8395
8396 func_type = arm_current_func_type ();
8397
8398 if (IS_NAKED (func_type))
8399 /* Naked functions don't have epilogues. */
8400 return "";
8401
8402 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8403 {
8404 rtx op;
8405
8406 /* A volatile function should never return. Call abort. */
8407 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
8408 assemble_external_libcall (op);
8409 output_asm_insn ("bl\t%a0", &op);
8410
8411 return "";
8412 }
8413
8414 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
8415 && ! really_return)
8416 /* If we are throwing an exception, then we really must
8417 be doing a return, so we can't tail-call. */
8418 abort ();
8419
8420 saved_regs_mask = arm_compute_save_reg_mask ();
8421
8422 if (TARGET_IWMMXT)
8423 lrm_count = bit_count (saved_regs_mask);
8424
8425 /* XXX We should adjust floats_offset for any anonymous args, and then
8426 re-adjust vfp_offset below to compensate. */
8427
8428 /* Compute how far away the floats will be. */
8429 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8430 if (saved_regs_mask & (1 << reg))
8431 floats_offset += 4;
8432
8433 if (frame_pointer_needed)
8434 {
8435 int vfp_offset = 4;
8436
8437 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8438 {
8439 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8440 if (regs_ever_live[reg] && !call_used_regs[reg])
8441 {
8442 floats_offset += 12;
8443 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
8444 reg, FP_REGNUM, floats_offset - vfp_offset);
8445 }
8446 }
8447 else
8448 {
8449 int start_reg = LAST_ARM_FP_REGNUM;
8450
8451 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8452 {
8453 if (regs_ever_live[reg] && !call_used_regs[reg])
8454 {
8455 floats_offset += 12;
8456
8457 /* We can't unstack more than four registers at once. */
8458 if (start_reg - reg == 3)
8459 {
8460 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
8461 reg, FP_REGNUM, floats_offset - vfp_offset);
8462 start_reg = reg - 1;
8463 }
8464 }
8465 else
8466 {
8467 if (reg != start_reg)
8468 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8469 reg + 1, start_reg - reg,
8470 FP_REGNUM, floats_offset - vfp_offset);
8471 start_reg = reg - 1;
8472 }
8473 }
8474
8475 /* Just in case the last register checked also needs unstacking. */
8476 if (reg != start_reg)
8477 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8478 reg + 1, start_reg - reg,
8479 FP_REGNUM, floats_offset - vfp_offset);
8480 }
8481
8482 if (TARGET_IWMMXT)
8483 {
8484 /* The frame pointer is guaranteed to be non-double-word aligned.
8485 This is because it is set to (old_stack_pointer - 4) and the
8486 old_stack_pointer was double word aligned. Thus the offset to
8487 the iWMMXt registers to be loaded must also be non-double-word
8488 sized, so that the resultant address *is* double-word aligned.
8489 We can ignore floats_offset since that was already included in
8490 the live_regs_mask. */
8491 lrm_count += (lrm_count % 2 ? 2 : 1);
8492
8493 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8494 if (regs_ever_live[reg] && !call_used_regs[reg])
8495 {
8496 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
8497 reg, FP_REGNUM, lrm_count * 4);
8498 lrm_count += 2;
8499 }
8500 }
8501
8502 /* saved_regs_mask should contain the IP, which at the time of stack
8503 frame generation actually contains the old stack pointer. So a
8504 quick way to unwind the stack is just pop the IP register directly
8505 into the stack pointer. */
8506 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
8507 abort ();
8508 saved_regs_mask &= ~ (1 << IP_REGNUM);
8509 saved_regs_mask |= (1 << SP_REGNUM);
8510
8511 /* There are two registers left in saved_regs_mask - LR and PC. We
8512 only need to restore the LR register (the return address), but to
8513 save time we can load it directly into the PC, unless we need a
8514 special function exit sequence, or we are not really returning. */
8515 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
8516 /* Delete the LR from the register mask, so that the LR on
8517 the stack is loaded into the PC in the register mask. */
8518 saved_regs_mask &= ~ (1 << LR_REGNUM);
8519 else
8520 saved_regs_mask &= ~ (1 << PC_REGNUM);
8521
8522 /* We must use SP as the base register, because SP is one of the
8523 registers being restored. If an interrupt or page fault
8524 happens in the ldm instruction, the SP might or might not
8525 have been restored. That would be bad, as then SP will no
8526 longer indicate the safe area of stack, and we can get stack
8527 corruption. Using SP as the base register means that it will
8528 be reset correctly to the original value, should an interrupt
8529 occur. */
8530 asm_fprintf (f, "\tsub\t%r,%r,#%d\n", SP_REGNUM, FP_REGNUM,
8531 4 * bit_count (saved_regs_mask));
8532 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8533
8534 if (IS_INTERRUPT (func_type))
8535 /* Interrupt handlers will have pushed the
8536 IP onto the stack, so restore it now. */
8537 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
8538 }
8539 else
8540 {
8541 /* Restore stack pointer if necessary. */
8542 if (frame_size + current_function_outgoing_args_size != 0)
8543 {
8544 operands[0] = operands[1] = stack_pointer_rtx;
8545 operands[2] = GEN_INT (frame_size
8546 + current_function_outgoing_args_size);
8547 output_add_immediate (operands);
8548 }
8549
8550 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8551 {
8552 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8553 if (regs_ever_live[reg] && !call_used_regs[reg])
8554 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
8555 reg, SP_REGNUM);
8556 }
8557 else
8558 {
8559 int start_reg = FIRST_ARM_FP_REGNUM;
8560
8561 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8562 {
8563 if (regs_ever_live[reg] && !call_used_regs[reg])
8564 {
8565 if (reg - start_reg == 3)
8566 {
8567 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
8568 start_reg, SP_REGNUM);
8569 start_reg = reg + 1;
8570 }
8571 }
8572 else
8573 {
8574 if (reg != start_reg)
8575 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8576 start_reg, reg - start_reg,
8577 SP_REGNUM);
8578
8579 start_reg = reg + 1;
8580 }
8581 }
8582
8583 /* Just in case the last register checked also needs unstacking. */
8584 if (reg != start_reg)
8585 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8586 start_reg, reg - start_reg, SP_REGNUM);
8587 }
8588
8589 if (TARGET_IWMMXT)
8590 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8591 if (regs_ever_live[reg] && !call_used_regs[reg])
8592 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
8593
8594 /* If we can, restore the LR into the PC. */
8595 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8596 && really_return
8597 && current_function_pretend_args_size == 0
8598 && saved_regs_mask & (1 << LR_REGNUM))
8599 {
8600 saved_regs_mask &= ~ (1 << LR_REGNUM);
8601 saved_regs_mask |= (1 << PC_REGNUM);
8602 }
8603
8604 /* Load the registers off the stack. If we only have one register
8605 to load use the LDR instruction - it is faster. */
8606 if (saved_regs_mask == (1 << LR_REGNUM))
8607 {
8608 /* The exception handler ignores the LR, so we do
8609 not really need to load it off the stack. */
8610 if (eh_ofs)
8611 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
8612 else
8613 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
8614 }
8615 else if (saved_regs_mask)
8616 {
8617 if (saved_regs_mask & (1 << SP_REGNUM))
8618 /* Note - write back to the stack register is not enabled
8619 (ie "ldmfd sp!..."). We know that the stack pointer is
8620 in the list of registers and if we add writeback the
8621 instruction becomes UNPREDICTABLE. */
8622 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8623 else
8624 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
8625 }
8626
8627 if (current_function_pretend_args_size)
8628 {
8629 /* Unwind the pre-pushed regs. */
8630 operands[0] = operands[1] = stack_pointer_rtx;
8631 operands[2] = GEN_INT (current_function_pretend_args_size);
8632 output_add_immediate (operands);
8633 }
8634 }
8635
8636 if (! really_return
8637 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8638 && current_function_pretend_args_size == 0
8639 && saved_regs_mask & (1 << PC_REGNUM)))
8640 return "";
8641
8642 /* Generate the return instruction. */
8643 switch ((int) ARM_FUNC_TYPE (func_type))
8644 {
8645 case ARM_FT_EXCEPTION_HANDLER:
8646 /* Even in 26-bit mode we do a mov (rather than a movs)
8647 because we don't have the PSR bits set in the address. */
8648 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
8649 break;
8650
8651 case ARM_FT_ISR:
8652 case ARM_FT_FIQ:
8653 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
8654 break;
8655
8656 case ARM_FT_EXCEPTION:
8657 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8658 break;
8659
8660 case ARM_FT_INTERWORKED:
8661 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
8662 break;
8663
8664 default:
8665 if (frame_pointer_needed)
8666 /* If we used the frame pointer then the return address
8667 will have been loaded off the stack directly into the
8668 PC, so there is no need to issue a MOV instruction
8669 here. */
8670 ;
8671 else if (current_function_pretend_args_size == 0
8672 && (saved_regs_mask & (1 << LR_REGNUM)))
8673 /* Similarly we may have been able to load LR into the PC
8674 even if we did not create a stack frame. */
8675 ;
8676 else if (TARGET_APCS_32)
8677 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8678 else
8679 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8680 break;
8681 }
8682
8683 return "";
8684 }
8685
8686 static void
8687 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8688 HOST_WIDE_INT frame_size)
8689 {
8690 if (TARGET_THUMB)
8691 {
8692 /* ??? Probably not safe to set this here, since it assumes that a
8693 function will be emitted as assembly immediately after we generate
8694 RTL for it. This does not happen for inline functions. */
8695 return_used_this_function = 0;
8696 }
8697 else
8698 {
8699 /* We need to take into account any stack-frame rounding. */
8700 frame_size = arm_get_frame_size ();
8701
8702 if (use_return_insn (FALSE)
8703 && return_used_this_function
8704 && (frame_size + current_function_outgoing_args_size) != 0
8705 && !frame_pointer_needed)
8706 abort ();
8707
8708 /* Reset the ARM-specific per-function variables. */
8709 after_arm_reorg = 0;
8710 }
8711 }
8712
8713 /* Generate and emit an insn that we will recognize as a push_multi.
8714 Unfortunately, since this insn does not reflect very well the actual
8715 semantics of the operation, we need to annotate the insn for the benefit
8716 of DWARF2 frame unwind information. */
8717 static rtx
8718 emit_multi_reg_push (int mask)
8719 {
8720 int num_regs = 0;
8721 int num_dwarf_regs;
8722 int i, j;
8723 rtx par;
8724 rtx dwarf;
8725 int dwarf_par_index;
8726 rtx tmp, reg;
8727
8728 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8729 if (mask & (1 << i))
8730 num_regs++;
8731
8732 if (num_regs == 0 || num_regs > 16)
8733 abort ();
8734
8735 /* We don't record the PC in the dwarf frame information. */
8736 num_dwarf_regs = num_regs;
8737 if (mask & (1 << PC_REGNUM))
8738 num_dwarf_regs--;
8739
8740 /* For the body of the insn we are going to generate an UNSPEC in
8741 parallel with several USEs. This allows the insn to be recognized
8742 by the push_multi pattern in the arm.md file. The insn looks
8743 something like this:
8744
8745 (parallel [
8746 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8747 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8748 (use (reg:SI 11 fp))
8749 (use (reg:SI 12 ip))
8750 (use (reg:SI 14 lr))
8751 (use (reg:SI 15 pc))
8752 ])
8753
8754 For the frame note however, we try to be more explicit and actually
8755 show each register being stored into the stack frame, plus a (single)
8756 decrement of the stack pointer. We do it this way in order to be
8757 friendly to the stack unwinding code, which only wants to see a single
8758 stack decrement per instruction. The RTL we generate for the note looks
8759 something like this:
8760
8761 (sequence [
8762 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8763 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8764 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8765 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8766 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8767 ])
8768
8769 This sequence is used both by the code to support stack unwinding for
8770 exceptions handlers and the code to generate dwarf2 frame debugging. */
8771
8772 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
8773 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
8774 dwarf_par_index = 1;
8775
8776 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8777 {
8778 if (mask & (1 << i))
8779 {
8780 reg = gen_rtx_REG (SImode, i);
8781
8782 XVECEXP (par, 0, 0)
8783 = gen_rtx_SET (VOIDmode,
8784 gen_rtx_MEM (BLKmode,
8785 gen_rtx_PRE_DEC (BLKmode,
8786 stack_pointer_rtx)),
8787 gen_rtx_UNSPEC (BLKmode,
8788 gen_rtvec (1, reg),
8789 UNSPEC_PUSH_MULT));
8790
8791 if (i != PC_REGNUM)
8792 {
8793 tmp = gen_rtx_SET (VOIDmode,
8794 gen_rtx_MEM (SImode, stack_pointer_rtx),
8795 reg);
8796 RTX_FRAME_RELATED_P (tmp) = 1;
8797 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
8798 dwarf_par_index++;
8799 }
8800
8801 break;
8802 }
8803 }
8804
8805 for (j = 1, i++; j < num_regs; i++)
8806 {
8807 if (mask & (1 << i))
8808 {
8809 reg = gen_rtx_REG (SImode, i);
8810
8811 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
8812
8813 if (i != PC_REGNUM)
8814 {
8815 tmp = gen_rtx_SET (VOIDmode,
8816 gen_rtx_MEM (SImode,
8817 plus_constant (stack_pointer_rtx,
8818 4 * j)),
8819 reg);
8820 RTX_FRAME_RELATED_P (tmp) = 1;
8821 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
8822 }
8823
8824 j++;
8825 }
8826 }
8827
8828 par = emit_insn (par);
8829
8830 tmp = gen_rtx_SET (SImode,
8831 stack_pointer_rtx,
8832 gen_rtx_PLUS (SImode,
8833 stack_pointer_rtx,
8834 GEN_INT (-4 * num_regs)));
8835 RTX_FRAME_RELATED_P (tmp) = 1;
8836 XVECEXP (dwarf, 0, 0) = tmp;
8837
8838 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8839 REG_NOTES (par));
8840 return par;
8841 }
8842
8843 static rtx
8844 emit_sfm (int base_reg, int count)
8845 {
8846 rtx par;
8847 rtx dwarf;
8848 rtx tmp, reg;
8849 int i;
8850
8851 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8852 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8853
8854 reg = gen_rtx_REG (XFmode, base_reg++);
8855
8856 XVECEXP (par, 0, 0)
8857 = gen_rtx_SET (VOIDmode,
8858 gen_rtx_MEM (BLKmode,
8859 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8860 gen_rtx_UNSPEC (BLKmode,
8861 gen_rtvec (1, reg),
8862 UNSPEC_PUSH_MULT));
8863 tmp
8864 = gen_rtx_SET (VOIDmode,
8865 gen_rtx_MEM (XFmode,
8866 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8867 reg);
8868 RTX_FRAME_RELATED_P (tmp) = 1;
8869 XVECEXP (dwarf, 0, count - 1) = tmp;
8870
8871 for (i = 1; i < count; i++)
8872 {
8873 reg = gen_rtx_REG (XFmode, base_reg++);
8874 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8875
8876 tmp = gen_rtx_SET (VOIDmode,
8877 gen_rtx_MEM (XFmode,
8878 gen_rtx_PRE_DEC (BLKmode,
8879 stack_pointer_rtx)),
8880 reg);
8881 RTX_FRAME_RELATED_P (tmp) = 1;
8882 XVECEXP (dwarf, 0, count - i - 1) = tmp;
8883 }
8884
8885 par = emit_insn (par);
8886 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8887 REG_NOTES (par));
8888 return par;
8889 }
8890
8891 /* Compute the distance from register FROM to register TO.
8892 These can be the arg pointer (26), the soft frame pointer (25),
8893 the stack pointer (13) or the hard frame pointer (11).
8894 Typical stack layout looks like this:
8895
8896 old stack pointer -> | |
8897 ----
8898 | | \
8899 | | saved arguments for
8900 | | vararg functions
8901 | | /
8902 --
8903 hard FP & arg pointer -> | | \
8904 | | stack
8905 | | frame
8906 | | /
8907 --
8908 | | \
8909 | | call saved
8910 | | registers
8911 soft frame pointer -> | | /
8912 --
8913 | | \
8914 | | local
8915 | | variables
8916 | | /
8917 --
8918 | | \
8919 | | outgoing
8920 | | arguments
8921 current stack pointer -> | | /
8922 --
8923
8924 For a given function some or all of these stack components
8925 may not be needed, giving rise to the possibility of
8926 eliminating some of the registers.
8927
8928 The values returned by this function must reflect the behavior
8929 of arm_expand_prologue() and arm_compute_save_reg_mask().
8930
8931 The sign of the number returned reflects the direction of stack
8932 growth, so the values are positive for all eliminations except
8933 from the soft frame pointer to the hard frame pointer. */
8934 unsigned int
8935 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
8936 {
8937 unsigned int local_vars = arm_get_frame_size ();
8938 unsigned int outgoing_args = current_function_outgoing_args_size;
8939 unsigned int stack_frame;
8940 unsigned int call_saved_registers;
8941 unsigned long func_type;
8942
8943 func_type = arm_current_func_type ();
8944
8945 /* Volatile functions never return, so there is
8946 no need to save call saved registers. */
8947 call_saved_registers = 0;
8948 if (! IS_VOLATILE (func_type))
8949 {
8950 unsigned int reg_mask;
8951 unsigned int reg;
8952
8953 /* Make sure that we compute which registers will be saved
8954 on the stack using the same algorithm that is used by
8955 the prologue creation code. */
8956 reg_mask = arm_compute_save_reg_mask ();
8957
8958 /* Now count the number of bits set in save_reg_mask.
8959 If we have already counted the registers in the stack
8960 frame, do not count them again. Non call-saved registers
8961 might be saved in the call-save area of the stack, if
8962 doing so will preserve the stack's alignment. Hence we
8963 must count them here. For each set bit we need 4 bytes
8964 of stack space. */
8965 if (frame_pointer_needed)
8966 reg_mask &= 0x07ff;
8967 call_saved_registers += 4 * bit_count (reg_mask);
8968
8969 /* If the hard floating point registers are going to be
8970 used then they must be saved on the stack as well.
8971 Each register occupies 12 bytes of stack space. */
8972 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8973 if (regs_ever_live[reg] && ! call_used_regs[reg])
8974 call_saved_registers += 12;
8975
8976 if (TARGET_REALLY_IWMMXT)
8977 /* Check for the call-saved iWMMXt registers. */
8978 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8979 if (regs_ever_live[reg] && ! call_used_regs [reg])
8980 call_saved_registers += 8;
8981 }
8982
8983 /* The stack frame contains 4 registers - the old frame pointer,
8984 the old stack pointer, the return address and PC of the start
8985 of the function. */
8986 stack_frame = frame_pointer_needed ? 16 : 0;
8987
8988 /* OK, now we have enough information to compute the distances.
8989 There must be an entry in these switch tables for each pair
8990 of registers in ELIMINABLE_REGS, even if some of the entries
8991 seem to be redundant or useless. */
8992 switch (from)
8993 {
8994 case ARG_POINTER_REGNUM:
8995 switch (to)
8996 {
8997 case THUMB_HARD_FRAME_POINTER_REGNUM:
8998 return 0;
8999
9000 case FRAME_POINTER_REGNUM:
9001 /* This is the reverse of the soft frame pointer
9002 to hard frame pointer elimination below. */
9003 if (call_saved_registers == 0 && stack_frame == 0)
9004 return 0;
9005 return (call_saved_registers + stack_frame - 4);
9006
9007 case ARM_HARD_FRAME_POINTER_REGNUM:
9008 /* If there is no stack frame then the hard
9009 frame pointer and the arg pointer coincide. */
9010 if (stack_frame == 0 && call_saved_registers != 0)
9011 return 0;
9012 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9013 return (frame_pointer_needed
9014 && current_function_needs_context
9015 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9016
9017 case STACK_POINTER_REGNUM:
9018 /* If nothing has been pushed on the stack at all
9019 then this will return -4. This *is* correct! */
9020 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
9021
9022 default:
9023 abort ();
9024 }
9025 break;
9026
9027 case FRAME_POINTER_REGNUM:
9028 switch (to)
9029 {
9030 case THUMB_HARD_FRAME_POINTER_REGNUM:
9031 return 0;
9032
9033 case ARM_HARD_FRAME_POINTER_REGNUM:
9034 /* The hard frame pointer points to the top entry in the
9035 stack frame. The soft frame pointer to the bottom entry
9036 in the stack frame. If there is no stack frame at all,
9037 then they are identical. */
9038 if (call_saved_registers == 0 && stack_frame == 0)
9039 return 0;
9040 return - (call_saved_registers + stack_frame - 4);
9041
9042 case STACK_POINTER_REGNUM:
9043 return local_vars + outgoing_args;
9044
9045 default:
9046 abort ();
9047 }
9048 break;
9049
9050 default:
9051 /* You cannot eliminate from the stack pointer.
9052 In theory you could eliminate from the hard frame
9053 pointer to the stack pointer, but this will never
9054 happen, since if a stack frame is not needed the
9055 hard frame pointer will never be used. */
9056 abort ();
9057 }
9058 }
9059
9060 /* Calculate the size of the stack frame, taking into account any
9061 padding that is required to ensure stack-alignment. */
9062 HOST_WIDE_INT
9063 arm_get_frame_size (void)
9064 {
9065 int regno;
9066
9067 int base_size = ROUND_UP_WORD (get_frame_size ());
9068 int entry_size = 0;
9069 unsigned long func_type = arm_current_func_type ();
9070 int leaf;
9071
9072 if (! TARGET_ARM)
9073 abort();
9074
9075 if (! TARGET_ATPCS)
9076 return base_size;
9077
9078 /* We need to know if we are a leaf function. Unfortunately, it
9079 is possible to be called after start_sequence has been called,
9080 which causes get_insns to return the insns for the sequence,
9081 not the function, which will cause leaf_function_p to return
9082 the incorrect result.
9083
9084 To work around this, we cache the computed frame size. This
9085 works because we will only be calling RTL expanders that need
9086 to know about leaf functions once reload has completed, and the
9087 frame size cannot be changed after that time, so we can safely
9088 use the cached value. */
9089
9090 if (reload_completed)
9091 return cfun->machine->frame_size;
9092
9093 leaf = leaf_function_p ();
9094
9095 /* A leaf function does not need any stack alignment if it has nothing
9096 on the stack. */
9097 if (leaf && base_size == 0)
9098 {
9099 cfun->machine->frame_size = 0;
9100 return 0;
9101 }
9102
9103 /* We know that SP will be word aligned on entry, and we must
9104 preserve that condition at any subroutine call. But those are
9105 the only constraints. */
9106
9107 /* Space for variadic functions. */
9108 if (current_function_pretend_args_size)
9109 entry_size += current_function_pretend_args_size;
9110
9111 /* Space for saved registers. */
9112 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
9113
9114 /* Space for saved FPA registers. */
9115 if (! IS_VOLATILE (func_type))
9116 {
9117 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
9118 if (regs_ever_live[regno] && ! call_used_regs[regno])
9119 entry_size += 12;
9120 }
9121
9122 if (TARGET_REALLY_IWMMXT)
9123 {
9124 /* Check for the call-saved iWMMXt registers. */
9125 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
9126 if (regs_ever_live [regno] && ! call_used_regs [regno])
9127 entry_size += 8;
9128 }
9129
9130 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9131 base_size += 4;
9132 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9133 abort ();
9134
9135 cfun->machine->frame_size = base_size;
9136
9137 return base_size;
9138 }
9139
9140 /* Generate the prologue instructions for entry into an ARM function. */
9141 void
9142 arm_expand_prologue (void)
9143 {
9144 int reg;
9145 rtx amount;
9146 rtx insn;
9147 rtx ip_rtx;
9148 unsigned long live_regs_mask;
9149 unsigned long func_type;
9150 int fp_offset = 0;
9151 int saved_pretend_args = 0;
9152 unsigned int args_to_push;
9153
9154 func_type = arm_current_func_type ();
9155
9156 /* Naked functions don't have prologues. */
9157 if (IS_NAKED (func_type))
9158 return;
9159
9160 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9161 args_to_push = current_function_pretend_args_size;
9162
9163 /* Compute which register we will have to save onto the stack. */
9164 live_regs_mask = arm_compute_save_reg_mask ();
9165
9166 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9167
9168 if (frame_pointer_needed)
9169 {
9170 if (IS_INTERRUPT (func_type))
9171 {
9172 /* Interrupt functions must not corrupt any registers.
9173 Creating a frame pointer however, corrupts the IP
9174 register, so we must push it first. */
9175 insn = emit_multi_reg_push (1 << IP_REGNUM);
9176
9177 /* Do not set RTX_FRAME_RELATED_P on this insn.
9178 The dwarf stack unwinding code only wants to see one
9179 stack decrement per function, and this is not it. If
9180 this instruction is labeled as being part of the frame
9181 creation sequence then dwarf2out_frame_debug_expr will
9182 abort when it encounters the assignment of IP to FP
9183 later on, since the use of SP here establishes SP as
9184 the CFA register and not IP.
9185
9186 Anyway this instruction is not really part of the stack
9187 frame creation although it is part of the prologue. */
9188 }
9189 else if (IS_NESTED (func_type))
9190 {
9191 /* The Static chain register is the same as the IP register
9192 used as a scratch register during stack frame creation.
9193 To get around this need to find somewhere to store IP
9194 whilst the frame is being created. We try the following
9195 places in order:
9196
9197 1. The last argument register.
9198 2. A slot on the stack above the frame. (This only
9199 works if the function is not a varargs function).
9200 3. Register r3, after pushing the argument registers
9201 onto the stack.
9202
9203 Note - we only need to tell the dwarf2 backend about the SP
9204 adjustment in the second variant; the static chain register
9205 doesn't need to be unwound, as it doesn't contain a value
9206 inherited from the caller. */
9207
9208 if (regs_ever_live[3] == 0)
9209 {
9210 insn = gen_rtx_REG (SImode, 3);
9211 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9212 insn = emit_insn (insn);
9213 }
9214 else if (args_to_push == 0)
9215 {
9216 rtx dwarf;
9217 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
9218 insn = gen_rtx_MEM (SImode, insn);
9219 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
9220 insn = emit_insn (insn);
9221
9222 fp_offset = 4;
9223
9224 /* Just tell the dwarf backend that we adjusted SP. */
9225 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9226 gen_rtx_PLUS (SImode, stack_pointer_rtx,
9227 GEN_INT (-fp_offset)));
9228 RTX_FRAME_RELATED_P (insn) = 1;
9229 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9230 dwarf, REG_NOTES (insn));
9231 }
9232 else
9233 {
9234 /* Store the args on the stack. */
9235 if (cfun->machine->uses_anonymous_args)
9236 insn = emit_multi_reg_push
9237 ((0xf0 >> (args_to_push / 4)) & 0xf);
9238 else
9239 insn = emit_insn
9240 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9241 GEN_INT (- args_to_push)));
9242
9243 RTX_FRAME_RELATED_P (insn) = 1;
9244
9245 saved_pretend_args = 1;
9246 fp_offset = args_to_push;
9247 args_to_push = 0;
9248
9249 /* Now reuse r3 to preserve IP. */
9250 insn = gen_rtx_REG (SImode, 3);
9251 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9252 (void) emit_insn (insn);
9253 }
9254 }
9255
9256 if (fp_offset)
9257 {
9258 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
9259 insn = gen_rtx_SET (SImode, ip_rtx, insn);
9260 }
9261 else
9262 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
9263
9264 insn = emit_insn (insn);
9265 RTX_FRAME_RELATED_P (insn) = 1;
9266 }
9267
9268 if (args_to_push)
9269 {
9270 /* Push the argument registers, or reserve space for them. */
9271 if (cfun->machine->uses_anonymous_args)
9272 insn = emit_multi_reg_push
9273 ((0xf0 >> (args_to_push / 4)) & 0xf);
9274 else
9275 insn = emit_insn
9276 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9277 GEN_INT (- args_to_push)));
9278 RTX_FRAME_RELATED_P (insn) = 1;
9279 }
9280
9281 /* If this is an interrupt service routine, and the link register
9282 is going to be pushed, and we are not creating a stack frame,
9283 (which would involve an extra push of IP and a pop in the epilogue)
9284 subtracting four from LR now will mean that the function return
9285 can be done with a single instruction. */
9286 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
9287 && (live_regs_mask & (1 << LR_REGNUM)) != 0
9288 && ! frame_pointer_needed)
9289 emit_insn (gen_rtx_SET (SImode,
9290 gen_rtx_REG (SImode, LR_REGNUM),
9291 gen_rtx_PLUS (SImode,
9292 gen_rtx_REG (SImode, LR_REGNUM),
9293 GEN_INT (-4))));
9294
9295 if (live_regs_mask)
9296 {
9297 insn = emit_multi_reg_push (live_regs_mask);
9298 RTX_FRAME_RELATED_P (insn) = 1;
9299 }
9300
9301 if (TARGET_IWMMXT)
9302 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9303 if (regs_ever_live[reg] && ! call_used_regs [reg])
9304 {
9305 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
9306 insn = gen_rtx_MEM (V2SImode, insn);
9307 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9308 gen_rtx_REG (V2SImode, reg)));
9309 RTX_FRAME_RELATED_P (insn) = 1;
9310 }
9311
9312 if (! IS_VOLATILE (func_type))
9313 {
9314 /* Save any floating point call-saved registers used by this
9315 function. */
9316 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9317 {
9318 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9319 if (regs_ever_live[reg] && !call_used_regs[reg])
9320 {
9321 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
9322 insn = gen_rtx_MEM (XFmode, insn);
9323 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9324 gen_rtx_REG (XFmode, reg)));
9325 RTX_FRAME_RELATED_P (insn) = 1;
9326 }
9327 }
9328 else
9329 {
9330 int start_reg = LAST_ARM_FP_REGNUM;
9331
9332 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9333 {
9334 if (regs_ever_live[reg] && !call_used_regs[reg])
9335 {
9336 if (start_reg - reg == 3)
9337 {
9338 insn = emit_sfm (reg, 4);
9339 RTX_FRAME_RELATED_P (insn) = 1;
9340 start_reg = reg - 1;
9341 }
9342 }
9343 else
9344 {
9345 if (start_reg != reg)
9346 {
9347 insn = emit_sfm (reg + 1, start_reg - reg);
9348 RTX_FRAME_RELATED_P (insn) = 1;
9349 }
9350 start_reg = reg - 1;
9351 }
9352 }
9353
9354 if (start_reg != reg)
9355 {
9356 insn = emit_sfm (reg + 1, start_reg - reg);
9357 RTX_FRAME_RELATED_P (insn) = 1;
9358 }
9359 }
9360 }
9361
9362 if (frame_pointer_needed)
9363 {
9364 /* Create the new frame pointer. */
9365 insn = GEN_INT (-(4 + args_to_push + fp_offset));
9366 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
9367 RTX_FRAME_RELATED_P (insn) = 1;
9368
9369 if (IS_NESTED (func_type))
9370 {
9371 /* Recover the static chain register. */
9372 if (regs_ever_live [3] == 0
9373 || saved_pretend_args)
9374 insn = gen_rtx_REG (SImode, 3);
9375 else /* if (current_function_pretend_args_size == 0) */
9376 {
9377 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
9378 GEN_INT (4));
9379 insn = gen_rtx_MEM (SImode, insn);
9380 }
9381
9382 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
9383 /* Add a USE to stop propagate_one_insn() from barfing. */
9384 emit_insn (gen_prologue_use (ip_rtx));
9385 }
9386 }
9387
9388 amount = GEN_INT (-(arm_get_frame_size ()
9389 + current_function_outgoing_args_size));
9390
9391 if (amount != const0_rtx)
9392 {
9393 /* This add can produce multiple insns for a large constant, so we
9394 need to get tricky. */
9395 rtx last = get_last_insn ();
9396 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9397 amount));
9398 do
9399 {
9400 last = last ? NEXT_INSN (last) : get_insns ();
9401 RTX_FRAME_RELATED_P (last) = 1;
9402 }
9403 while (last != insn);
9404
9405 /* If the frame pointer is needed, emit a special barrier that
9406 will prevent the scheduler from moving stores to the frame
9407 before the stack adjustment. */
9408 if (frame_pointer_needed)
9409 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
9410 hard_frame_pointer_rtx));
9411 }
9412
9413 /* If we are profiling, make sure no instructions are scheduled before
9414 the call to mcount. Similarly if the user has requested no
9415 scheduling in the prolog. */
9416 if (current_function_profile || TARGET_NO_SCHED_PRO)
9417 emit_insn (gen_blockage ());
9418
9419 /* If the link register is being kept alive, with the return address in it,
9420 then make sure that it does not get reused by the ce2 pass. */
9421 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
9422 {
9423 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
9424 cfun->machine->lr_save_eliminated = 1;
9425 }
9426 }
9427 \f
9428 /* If CODE is 'd', then the X is a condition operand and the instruction
9429 should only be executed if the condition is true.
9430 if CODE is 'D', then the X is a condition operand and the instruction
9431 should only be executed if the condition is false: however, if the mode
9432 of the comparison is CCFPEmode, then always execute the instruction -- we
9433 do this because in these circumstances !GE does not necessarily imply LT;
9434 in these cases the instruction pattern will take care to make sure that
9435 an instruction containing %d will follow, thereby undoing the effects of
9436 doing this instruction unconditionally.
9437 If CODE is 'N' then X is a floating point operand that must be negated
9438 before output.
9439 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9440 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9441 void
9442 arm_print_operand (FILE *stream, rtx x, int code)
9443 {
9444 switch (code)
9445 {
9446 case '@':
9447 fputs (ASM_COMMENT_START, stream);
9448 return;
9449
9450 case '_':
9451 fputs (user_label_prefix, stream);
9452 return;
9453
9454 case '|':
9455 fputs (REGISTER_PREFIX, stream);
9456 return;
9457
9458 case '?':
9459 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
9460 {
9461 if (TARGET_THUMB || current_insn_predicate != NULL)
9462 abort ();
9463
9464 fputs (arm_condition_codes[arm_current_cc], stream);
9465 }
9466 else if (current_insn_predicate)
9467 {
9468 enum arm_cond_code code;
9469
9470 if (TARGET_THUMB)
9471 abort ();
9472
9473 code = get_arm_condition_code (current_insn_predicate);
9474 fputs (arm_condition_codes[code], stream);
9475 }
9476 return;
9477
9478 case 'N':
9479 {
9480 REAL_VALUE_TYPE r;
9481 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9482 r = REAL_VALUE_NEGATE (r);
9483 fprintf (stream, "%s", fp_const_from_val (&r));
9484 }
9485 return;
9486
9487 case 'B':
9488 if (GET_CODE (x) == CONST_INT)
9489 {
9490 HOST_WIDE_INT val;
9491 val = ARM_SIGN_EXTEND (~INTVAL (x));
9492 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
9493 }
9494 else
9495 {
9496 putc ('~', stream);
9497 output_addr_const (stream, x);
9498 }
9499 return;
9500
9501 case 'i':
9502 fprintf (stream, "%s", arithmetic_instr (x, 1));
9503 return;
9504
9505 /* Truncate Cirrus shift counts. */
9506 case 's':
9507 if (GET_CODE (x) == CONST_INT)
9508 {
9509 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
9510 return;
9511 }
9512 arm_print_operand (stream, x, 0);
9513 return;
9514
9515 case 'I':
9516 fprintf (stream, "%s", arithmetic_instr (x, 0));
9517 return;
9518
9519 case 'S':
9520 {
9521 HOST_WIDE_INT val;
9522 const char * shift = shift_op (x, &val);
9523
9524 if (shift)
9525 {
9526 fprintf (stream, ", %s ", shift_op (x, &val));
9527 if (val == -1)
9528 arm_print_operand (stream, XEXP (x, 1), 0);
9529 else
9530 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
9531 }
9532 }
9533 return;
9534
9535 /* An explanation of the 'Q', 'R' and 'H' register operands:
9536
9537 In a pair of registers containing a DI or DF value the 'Q'
9538 operand returns the register number of the register containing
9539 the least significant part of the value. The 'R' operand returns
9540 the register number of the register containing the most
9541 significant part of the value.
9542
9543 The 'H' operand returns the higher of the two register numbers.
9544 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9545 same as the 'Q' operand, since the most significant part of the
9546 value is held in the lower number register. The reverse is true
9547 on systems where WORDS_BIG_ENDIAN is false.
9548
9549 The purpose of these operands is to distinguish between cases
9550 where the endian-ness of the values is important (for example
9551 when they are added together), and cases where the endian-ness
9552 is irrelevant, but the order of register operations is important.
9553 For example when loading a value from memory into a register
9554 pair, the endian-ness does not matter. Provided that the value
9555 from the lower memory address is put into the lower numbered
9556 register, and the value from the higher address is put into the
9557 higher numbered register, the load will work regardless of whether
9558 the value being loaded is big-wordian or little-wordian. The
9559 order of the two register loads can matter however, if the address
9560 of the memory location is actually held in one of the registers
9561 being overwritten by the load. */
9562 case 'Q':
9563 if (REGNO (x) > LAST_ARM_REGNUM)
9564 abort ();
9565 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
9566 return;
9567
9568 case 'R':
9569 if (REGNO (x) > LAST_ARM_REGNUM)
9570 abort ();
9571 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
9572 return;
9573
9574 case 'H':
9575 if (REGNO (x) > LAST_ARM_REGNUM)
9576 abort ();
9577 asm_fprintf (stream, "%r", REGNO (x) + 1);
9578 return;
9579
9580 case 'm':
9581 asm_fprintf (stream, "%r",
9582 GET_CODE (XEXP (x, 0)) == REG
9583 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
9584 return;
9585
9586 case 'M':
9587 asm_fprintf (stream, "{%r-%r}",
9588 REGNO (x),
9589 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
9590 return;
9591
9592 case 'd':
9593 /* CONST_TRUE_RTX means always -- that's the default. */
9594 if (x == const_true_rtx)
9595 return;
9596
9597 fputs (arm_condition_codes[get_arm_condition_code (x)],
9598 stream);
9599 return;
9600
9601 case 'D':
9602 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9603 want to do that. */
9604 if (x == const_true_rtx)
9605 abort ();
9606
9607 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
9608 (get_arm_condition_code (x))],
9609 stream);
9610 return;
9611
9612 /* Cirrus registers can be accessed in a variety of ways:
9613 single floating point (f)
9614 double floating point (d)
9615 32bit integer (fx)
9616 64bit integer (dx). */
9617 case 'W': /* Cirrus register in F mode. */
9618 case 'X': /* Cirrus register in D mode. */
9619 case 'Y': /* Cirrus register in FX mode. */
9620 case 'Z': /* Cirrus register in DX mode. */
9621 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9622 abort ();
9623
9624 fprintf (stream, "mv%s%s",
9625 code == 'W' ? "f"
9626 : code == 'X' ? "d"
9627 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
9628
9629 return;
9630
9631 /* Print cirrus register in the mode specified by the register's mode. */
9632 case 'V':
9633 {
9634 int mode = GET_MODE (x);
9635
9636 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9637 abort ();
9638
9639 fprintf (stream, "mv%s%s",
9640 mode == DFmode ? "d"
9641 : mode == SImode ? "fx"
9642 : mode == DImode ? "dx"
9643 : "f", reg_names[REGNO (x)] + 2);
9644
9645 return;
9646 }
9647
9648 case 'U':
9649 if (GET_CODE (x) != REG
9650 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
9651 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
9652 /* Bad value for wCG register number. */
9653 abort ();
9654 else
9655 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
9656 return;
9657
9658 /* Print an iWMMXt control register name. */
9659 case 'w':
9660 if (GET_CODE (x) != CONST_INT
9661 || INTVAL (x) < 0
9662 || INTVAL (x) >= 16)
9663 /* Bad value for wC register number. */
9664 abort ();
9665 else
9666 {
9667 static const char * wc_reg_names [16] =
9668 {
9669 "wCID", "wCon", "wCSSF", "wCASF",
9670 "wC4", "wC5", "wC6", "wC7",
9671 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9672 "wC12", "wC13", "wC14", "wC15"
9673 };
9674
9675 fprintf (stream, wc_reg_names [INTVAL (x)]);
9676 }
9677 return;
9678
9679 default:
9680 if (x == 0)
9681 abort ();
9682
9683 if (GET_CODE (x) == REG)
9684 asm_fprintf (stream, "%r", REGNO (x));
9685 else if (GET_CODE (x) == MEM)
9686 {
9687 output_memory_reference_mode = GET_MODE (x);
9688 output_address (XEXP (x, 0));
9689 }
9690 else if (GET_CODE (x) == CONST_DOUBLE)
9691 fprintf (stream, "#%s", fp_immediate_constant (x));
9692 else if (GET_CODE (x) == NEG)
9693 abort (); /* This should never happen now. */
9694 else
9695 {
9696 fputc ('#', stream);
9697 output_addr_const (stream, x);
9698 }
9699 }
9700 }
9701 \f
9702 #ifndef AOF_ASSEMBLER
9703 /* Target hook for assembling integer objects. The ARM version needs to
9704 handle word-sized values specially. */
9705 static bool
9706 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
9707 {
9708 if (size == UNITS_PER_WORD && aligned_p)
9709 {
9710 fputs ("\t.word\t", asm_out_file);
9711 output_addr_const (asm_out_file, x);
9712
9713 /* Mark symbols as position independent. We only do this in the
9714 .text segment, not in the .data segment. */
9715 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
9716 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
9717 {
9718 if (GET_CODE (x) == SYMBOL_REF
9719 && (CONSTANT_POOL_ADDRESS_P (x)
9720 || SYMBOL_REF_LOCAL_P (x)))
9721 fputs ("(GOTOFF)", asm_out_file);
9722 else if (GET_CODE (x) == LABEL_REF)
9723 fputs ("(GOTOFF)", asm_out_file);
9724 else
9725 fputs ("(GOT)", asm_out_file);
9726 }
9727 fputc ('\n', asm_out_file);
9728 return true;
9729 }
9730
9731 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
9732 {
9733 int i, units;
9734
9735 if (GET_CODE (x) != CONST_VECTOR)
9736 abort ();
9737
9738 units = CONST_VECTOR_NUNITS (x);
9739
9740 switch (GET_MODE (x))
9741 {
9742 case V2SImode: size = 4; break;
9743 case V4HImode: size = 2; break;
9744 case V8QImode: size = 1; break;
9745 default:
9746 abort ();
9747 }
9748
9749 for (i = 0; i < units; i++)
9750 {
9751 rtx elt;
9752
9753 elt = CONST_VECTOR_ELT (x, i);
9754 assemble_integer
9755 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
9756 }
9757
9758 return true;
9759 }
9760
9761 return default_assemble_integer (x, size, aligned_p);
9762 }
9763 #endif
9764 \f
9765 /* A finite state machine takes care of noticing whether or not instructions
9766 can be conditionally executed, and thus decrease execution time and code
9767 size by deleting branch instructions. The fsm is controlled by
9768 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9769
9770 /* The state of the fsm controlling condition codes are:
9771 0: normal, do nothing special
9772 1: make ASM_OUTPUT_OPCODE not output this instruction
9773 2: make ASM_OUTPUT_OPCODE not output this instruction
9774 3: make instructions conditional
9775 4: make instructions conditional
9776
9777 State transitions (state->state by whom under condition):
9778 0 -> 1 final_prescan_insn if the `target' is a label
9779 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9780 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9781 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9782 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9783 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9784 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9785 (the target insn is arm_target_insn).
9786
9787 If the jump clobbers the conditions then we use states 2 and 4.
9788
9789 A similar thing can be done with conditional return insns.
9790
9791 XXX In case the `target' is an unconditional branch, this conditionalising
9792 of the instructions always reduces code size, but not always execution
9793 time. But then, I want to reduce the code size to somewhere near what
9794 /bin/cc produces. */
9795
9796 /* Returns the index of the ARM condition code string in
9797 `arm_condition_codes'. COMPARISON should be an rtx like
9798 `(eq (...) (...))'. */
9799 static enum arm_cond_code
9800 get_arm_condition_code (rtx comparison)
9801 {
9802 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
9803 int code;
9804 enum rtx_code comp_code = GET_CODE (comparison);
9805
9806 if (GET_MODE_CLASS (mode) != MODE_CC)
9807 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
9808 XEXP (comparison, 1));
9809
9810 switch (mode)
9811 {
9812 case CC_DNEmode: code = ARM_NE; goto dominance;
9813 case CC_DEQmode: code = ARM_EQ; goto dominance;
9814 case CC_DGEmode: code = ARM_GE; goto dominance;
9815 case CC_DGTmode: code = ARM_GT; goto dominance;
9816 case CC_DLEmode: code = ARM_LE; goto dominance;
9817 case CC_DLTmode: code = ARM_LT; goto dominance;
9818 case CC_DGEUmode: code = ARM_CS; goto dominance;
9819 case CC_DGTUmode: code = ARM_HI; goto dominance;
9820 case CC_DLEUmode: code = ARM_LS; goto dominance;
9821 case CC_DLTUmode: code = ARM_CC;
9822
9823 dominance:
9824 if (comp_code != EQ && comp_code != NE)
9825 abort ();
9826
9827 if (comp_code == EQ)
9828 return ARM_INVERSE_CONDITION_CODE (code);
9829 return code;
9830
9831 case CC_NOOVmode:
9832 switch (comp_code)
9833 {
9834 case NE: return ARM_NE;
9835 case EQ: return ARM_EQ;
9836 case GE: return ARM_PL;
9837 case LT: return ARM_MI;
9838 default: abort ();
9839 }
9840
9841 case CC_Zmode:
9842 switch (comp_code)
9843 {
9844 case NE: return ARM_NE;
9845 case EQ: return ARM_EQ;
9846 default: abort ();
9847 }
9848
9849 case CC_Nmode:
9850 switch (comp_code)
9851 {
9852 case NE: return ARM_MI;
9853 case EQ: return ARM_PL;
9854 default: abort ();
9855 }
9856
9857 case CCFPEmode:
9858 case CCFPmode:
9859 /* These encodings assume that AC=1 in the FPA system control
9860 byte. This allows us to handle all cases except UNEQ and
9861 LTGT. */
9862 switch (comp_code)
9863 {
9864 case GE: return ARM_GE;
9865 case GT: return ARM_GT;
9866 case LE: return ARM_LS;
9867 case LT: return ARM_MI;
9868 case NE: return ARM_NE;
9869 case EQ: return ARM_EQ;
9870 case ORDERED: return ARM_VC;
9871 case UNORDERED: return ARM_VS;
9872 case UNLT: return ARM_LT;
9873 case UNLE: return ARM_LE;
9874 case UNGT: return ARM_HI;
9875 case UNGE: return ARM_PL;
9876 /* UNEQ and LTGT do not have a representation. */
9877 case UNEQ: /* Fall through. */
9878 case LTGT: /* Fall through. */
9879 default: abort ();
9880 }
9881
9882 case CC_SWPmode:
9883 switch (comp_code)
9884 {
9885 case NE: return ARM_NE;
9886 case EQ: return ARM_EQ;
9887 case GE: return ARM_LE;
9888 case GT: return ARM_LT;
9889 case LE: return ARM_GE;
9890 case LT: return ARM_GT;
9891 case GEU: return ARM_LS;
9892 case GTU: return ARM_CC;
9893 case LEU: return ARM_CS;
9894 case LTU: return ARM_HI;
9895 default: abort ();
9896 }
9897
9898 case CC_Cmode:
9899 switch (comp_code)
9900 {
9901 case LTU: return ARM_CS;
9902 case GEU: return ARM_CC;
9903 default: abort ();
9904 }
9905
9906 case CCmode:
9907 switch (comp_code)
9908 {
9909 case NE: return ARM_NE;
9910 case EQ: return ARM_EQ;
9911 case GE: return ARM_GE;
9912 case GT: return ARM_GT;
9913 case LE: return ARM_LE;
9914 case LT: return ARM_LT;
9915 case GEU: return ARM_CS;
9916 case GTU: return ARM_HI;
9917 case LEU: return ARM_LS;
9918 case LTU: return ARM_CC;
9919 default: abort ();
9920 }
9921
9922 default: abort ();
9923 }
9924
9925 abort ();
9926 }
9927
9928 void
9929 arm_final_prescan_insn (rtx insn)
9930 {
9931 /* BODY will hold the body of INSN. */
9932 rtx body = PATTERN (insn);
9933
9934 /* This will be 1 if trying to repeat the trick, and things need to be
9935 reversed if it appears to fail. */
9936 int reverse = 0;
9937
9938 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9939 taken are clobbered, even if the rtl suggests otherwise. It also
9940 means that we have to grub around within the jump expression to find
9941 out what the conditions are when the jump isn't taken. */
9942 int jump_clobbers = 0;
9943
9944 /* If we start with a return insn, we only succeed if we find another one. */
9945 int seeking_return = 0;
9946
9947 /* START_INSN will hold the insn from where we start looking. This is the
9948 first insn after the following code_label if REVERSE is true. */
9949 rtx start_insn = insn;
9950
9951 /* If in state 4, check if the target branch is reached, in order to
9952 change back to state 0. */
9953 if (arm_ccfsm_state == 4)
9954 {
9955 if (insn == arm_target_insn)
9956 {
9957 arm_target_insn = NULL;
9958 arm_ccfsm_state = 0;
9959 }
9960 return;
9961 }
9962
9963 /* If in state 3, it is possible to repeat the trick, if this insn is an
9964 unconditional branch to a label, and immediately following this branch
9965 is the previous target label which is only used once, and the label this
9966 branch jumps to is not too far off. */
9967 if (arm_ccfsm_state == 3)
9968 {
9969 if (simplejump_p (insn))
9970 {
9971 start_insn = next_nonnote_insn (start_insn);
9972 if (GET_CODE (start_insn) == BARRIER)
9973 {
9974 /* XXX Isn't this always a barrier? */
9975 start_insn = next_nonnote_insn (start_insn);
9976 }
9977 if (GET_CODE (start_insn) == CODE_LABEL
9978 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
9979 && LABEL_NUSES (start_insn) == 1)
9980 reverse = TRUE;
9981 else
9982 return;
9983 }
9984 else if (GET_CODE (body) == RETURN)
9985 {
9986 start_insn = next_nonnote_insn (start_insn);
9987 if (GET_CODE (start_insn) == BARRIER)
9988 start_insn = next_nonnote_insn (start_insn);
9989 if (GET_CODE (start_insn) == CODE_LABEL
9990 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
9991 && LABEL_NUSES (start_insn) == 1)
9992 {
9993 reverse = TRUE;
9994 seeking_return = 1;
9995 }
9996 else
9997 return;
9998 }
9999 else
10000 return;
10001 }
10002
10003 if (arm_ccfsm_state != 0 && !reverse)
10004 abort ();
10005 if (GET_CODE (insn) != JUMP_INSN)
10006 return;
10007
10008 /* This jump might be paralleled with a clobber of the condition codes
10009 the jump should always come first */
10010 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
10011 body = XVECEXP (body, 0, 0);
10012
10013 if (reverse
10014 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
10015 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
10016 {
10017 int insns_skipped;
10018 int fail = FALSE, succeed = FALSE;
10019 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10020 int then_not_else = TRUE;
10021 rtx this_insn = start_insn, label = 0;
10022
10023 /* If the jump cannot be done with one instruction, we cannot
10024 conditionally execute the instruction in the inverse case. */
10025 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
10026 {
10027 jump_clobbers = 1;
10028 return;
10029 }
10030
10031 /* Register the insn jumped to. */
10032 if (reverse)
10033 {
10034 if (!seeking_return)
10035 label = XEXP (SET_SRC (body), 0);
10036 }
10037 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
10038 label = XEXP (XEXP (SET_SRC (body), 1), 0);
10039 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
10040 {
10041 label = XEXP (XEXP (SET_SRC (body), 2), 0);
10042 then_not_else = FALSE;
10043 }
10044 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
10045 seeking_return = 1;
10046 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
10047 {
10048 seeking_return = 1;
10049 then_not_else = FALSE;
10050 }
10051 else
10052 abort ();
10053
10054 /* See how many insns this branch skips, and what kind of insns. If all
10055 insns are okay, and the label or unconditional branch to the same
10056 label is not too far away, succeed. */
10057 for (insns_skipped = 0;
10058 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
10059 {
10060 rtx scanbody;
10061
10062 this_insn = next_nonnote_insn (this_insn);
10063 if (!this_insn)
10064 break;
10065
10066 switch (GET_CODE (this_insn))
10067 {
10068 case CODE_LABEL:
10069 /* Succeed if it is the target label, otherwise fail since
10070 control falls in from somewhere else. */
10071 if (this_insn == label)
10072 {
10073 if (jump_clobbers)
10074 {
10075 arm_ccfsm_state = 2;
10076 this_insn = next_nonnote_insn (this_insn);
10077 }
10078 else
10079 arm_ccfsm_state = 1;
10080 succeed = TRUE;
10081 }
10082 else
10083 fail = TRUE;
10084 break;
10085
10086 case BARRIER:
10087 /* Succeed if the following insn is the target label.
10088 Otherwise fail.
10089 If return insns are used then the last insn in a function
10090 will be a barrier. */
10091 this_insn = next_nonnote_insn (this_insn);
10092 if (this_insn && this_insn == label)
10093 {
10094 if (jump_clobbers)
10095 {
10096 arm_ccfsm_state = 2;
10097 this_insn = next_nonnote_insn (this_insn);
10098 }
10099 else
10100 arm_ccfsm_state = 1;
10101 succeed = TRUE;
10102 }
10103 else
10104 fail = TRUE;
10105 break;
10106
10107 case CALL_INSN:
10108 /* If using 32-bit addresses the cc is not preserved over
10109 calls. */
10110 if (TARGET_APCS_32)
10111 {
10112 /* Succeed if the following insn is the target label,
10113 or if the following two insns are a barrier and
10114 the target label. */
10115 this_insn = next_nonnote_insn (this_insn);
10116 if (this_insn && GET_CODE (this_insn) == BARRIER)
10117 this_insn = next_nonnote_insn (this_insn);
10118
10119 if (this_insn && this_insn == label
10120 && insns_skipped < max_insns_skipped)
10121 {
10122 if (jump_clobbers)
10123 {
10124 arm_ccfsm_state = 2;
10125 this_insn = next_nonnote_insn (this_insn);
10126 }
10127 else
10128 arm_ccfsm_state = 1;
10129 succeed = TRUE;
10130 }
10131 else
10132 fail = TRUE;
10133 }
10134 break;
10135
10136 case JUMP_INSN:
10137 /* If this is an unconditional branch to the same label, succeed.
10138 If it is to another label, do nothing. If it is conditional,
10139 fail. */
10140 /* XXX Probably, the tests for SET and the PC are
10141 unnecessary. */
10142
10143 scanbody = PATTERN (this_insn);
10144 if (GET_CODE (scanbody) == SET
10145 && GET_CODE (SET_DEST (scanbody)) == PC)
10146 {
10147 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
10148 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
10149 {
10150 arm_ccfsm_state = 2;
10151 succeed = TRUE;
10152 }
10153 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
10154 fail = TRUE;
10155 }
10156 /* Fail if a conditional return is undesirable (eg on a
10157 StrongARM), but still allow this if optimizing for size. */
10158 else if (GET_CODE (scanbody) == RETURN
10159 && !use_return_insn (TRUE)
10160 && !optimize_size)
10161 fail = TRUE;
10162 else if (GET_CODE (scanbody) == RETURN
10163 && seeking_return)
10164 {
10165 arm_ccfsm_state = 2;
10166 succeed = TRUE;
10167 }
10168 else if (GET_CODE (scanbody) == PARALLEL)
10169 {
10170 switch (get_attr_conds (this_insn))
10171 {
10172 case CONDS_NOCOND:
10173 break;
10174 default:
10175 fail = TRUE;
10176 break;
10177 }
10178 }
10179 else
10180 fail = TRUE; /* Unrecognized jump (eg epilogue). */
10181
10182 break;
10183
10184 case INSN:
10185 /* Instructions using or affecting the condition codes make it
10186 fail. */
10187 scanbody = PATTERN (this_insn);
10188 if (!(GET_CODE (scanbody) == SET
10189 || GET_CODE (scanbody) == PARALLEL)
10190 || get_attr_conds (this_insn) != CONDS_NOCOND)
10191 fail = TRUE;
10192
10193 /* A conditional cirrus instruction must be followed by
10194 a non Cirrus instruction. However, since we
10195 conditionalize instructions in this function and by
10196 the time we get here we can't add instructions
10197 (nops), because shorten_branches() has already been
10198 called, we will disable conditionalizing Cirrus
10199 instructions to be safe. */
10200 if (GET_CODE (scanbody) != USE
10201 && GET_CODE (scanbody) != CLOBBER
10202 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
10203 fail = TRUE;
10204 break;
10205
10206 default:
10207 break;
10208 }
10209 }
10210 if (succeed)
10211 {
10212 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
10213 arm_target_label = CODE_LABEL_NUMBER (label);
10214 else if (seeking_return || arm_ccfsm_state == 2)
10215 {
10216 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
10217 {
10218 this_insn = next_nonnote_insn (this_insn);
10219 if (this_insn && (GET_CODE (this_insn) == BARRIER
10220 || GET_CODE (this_insn) == CODE_LABEL))
10221 abort ();
10222 }
10223 if (!this_insn)
10224 {
10225 /* Oh, dear! we ran off the end.. give up */
10226 recog (PATTERN (insn), insn, NULL);
10227 arm_ccfsm_state = 0;
10228 arm_target_insn = NULL;
10229 return;
10230 }
10231 arm_target_insn = this_insn;
10232 }
10233 else
10234 abort ();
10235 if (jump_clobbers)
10236 {
10237 if (reverse)
10238 abort ();
10239 arm_current_cc =
10240 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
10241 0), 0), 1));
10242 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
10243 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10244 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
10245 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10246 }
10247 else
10248 {
10249 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10250 what it was. */
10251 if (!reverse)
10252 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
10253 0));
10254 }
10255
10256 if (reverse || then_not_else)
10257 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10258 }
10259
10260 /* Restore recog_data (getting the attributes of other insns can
10261 destroy this array, but final.c assumes that it remains intact
10262 across this call; since the insn has been recognized already we
10263 call recog direct). */
10264 recog (PATTERN (insn), insn, NULL);
10265 }
10266 }
10267
10268 /* Returns true if REGNO is a valid register
10269 for holding a quantity of tyoe MODE. */
10270 int
10271 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10272 {
10273 if (GET_MODE_CLASS (mode) == MODE_CC)
10274 return regno == CC_REGNUM;
10275
10276 if (TARGET_THUMB)
10277 /* For the Thumb we only allow values bigger than SImode in
10278 registers 0 - 6, so that there is always a second low
10279 register available to hold the upper part of the value.
10280 We probably we ought to ensure that the register is the
10281 start of an even numbered register pair. */
10282 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
10283
10284 if (IS_CIRRUS_REGNUM (regno))
10285 /* We have outlawed SI values in Cirrus registers because they
10286 reside in the lower 32 bits, but SF values reside in the
10287 upper 32 bits. This causes gcc all sorts of grief. We can't
10288 even split the registers into pairs because Cirrus SI values
10289 get sign extended to 64bits-- aldyh. */
10290 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
10291
10292 if (IS_IWMMXT_GR_REGNUM (regno))
10293 return mode == SImode;
10294
10295 if (IS_IWMMXT_REGNUM (regno))
10296 return VALID_IWMMXT_REG_MODE (mode);
10297
10298 if (regno <= LAST_ARM_REGNUM)
10299 /* We allow any value to be stored in the general registers. */
10300 return 1;
10301
10302 if ( regno == FRAME_POINTER_REGNUM
10303 || regno == ARG_POINTER_REGNUM)
10304 /* We only allow integers in the fake hard registers. */
10305 return GET_MODE_CLASS (mode) == MODE_INT;
10306
10307 /* The only registers left are the FPA registers
10308 which we only allow to hold FP values. */
10309 return GET_MODE_CLASS (mode) == MODE_FLOAT
10310 && regno >= FIRST_ARM_FP_REGNUM
10311 && regno <= LAST_ARM_FP_REGNUM;
10312 }
10313
10314 int
10315 arm_regno_class (int regno)
10316 {
10317 if (TARGET_THUMB)
10318 {
10319 if (regno == STACK_POINTER_REGNUM)
10320 return STACK_REG;
10321 if (regno == CC_REGNUM)
10322 return CC_REG;
10323 if (regno < 8)
10324 return LO_REGS;
10325 return HI_REGS;
10326 }
10327
10328 if ( regno <= LAST_ARM_REGNUM
10329 || regno == FRAME_POINTER_REGNUM
10330 || regno == ARG_POINTER_REGNUM)
10331 return GENERAL_REGS;
10332
10333 if (regno == CC_REGNUM)
10334 return NO_REGS;
10335
10336 if (IS_CIRRUS_REGNUM (regno))
10337 return CIRRUS_REGS;
10338
10339 if (IS_IWMMXT_REGNUM (regno))
10340 return IWMMXT_REGS;
10341
10342 if (IS_IWMMXT_GR_REGNUM (regno))
10343 return IWMMXT_GR_REGS;
10344
10345 return FPA_REGS;
10346 }
10347
10348 /* Handle a special case when computing the offset
10349 of an argument from the frame pointer. */
10350 int
10351 arm_debugger_arg_offset (int value, rtx addr)
10352 {
10353 rtx insn;
10354
10355 /* We are only interested if dbxout_parms() failed to compute the offset. */
10356 if (value != 0)
10357 return 0;
10358
10359 /* We can only cope with the case where the address is held in a register. */
10360 if (GET_CODE (addr) != REG)
10361 return 0;
10362
10363 /* If we are using the frame pointer to point at the argument, then
10364 an offset of 0 is correct. */
10365 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
10366 return 0;
10367
10368 /* If we are using the stack pointer to point at the
10369 argument, then an offset of 0 is correct. */
10370 if ((TARGET_THUMB || !frame_pointer_needed)
10371 && REGNO (addr) == SP_REGNUM)
10372 return 0;
10373
10374 /* Oh dear. The argument is pointed to by a register rather
10375 than being held in a register, or being stored at a known
10376 offset from the frame pointer. Since GDB only understands
10377 those two kinds of argument we must translate the address
10378 held in the register into an offset from the frame pointer.
10379 We do this by searching through the insns for the function
10380 looking to see where this register gets its value. If the
10381 register is initialized from the frame pointer plus an offset
10382 then we are in luck and we can continue, otherwise we give up.
10383
10384 This code is exercised by producing debugging information
10385 for a function with arguments like this:
10386
10387 double func (double a, double b, int c, double d) {return d;}
10388
10389 Without this code the stab for parameter 'd' will be set to
10390 an offset of 0 from the frame pointer, rather than 8. */
10391
10392 /* The if() statement says:
10393
10394 If the insn is a normal instruction
10395 and if the insn is setting the value in a register
10396 and if the register being set is the register holding the address of the argument
10397 and if the address is computing by an addition
10398 that involves adding to a register
10399 which is the frame pointer
10400 a constant integer
10401
10402 then... */
10403
10404 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10405 {
10406 if ( GET_CODE (insn) == INSN
10407 && GET_CODE (PATTERN (insn)) == SET
10408 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
10409 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
10410 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
10411 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10412 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
10413 )
10414 {
10415 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
10416
10417 break;
10418 }
10419 }
10420
10421 if (value == 0)
10422 {
10423 debug_rtx (addr);
10424 warning ("unable to compute real location of stacked parameter");
10425 value = 8; /* XXX magic hack */
10426 }
10427
10428 return value;
10429 }
10430 \f
10431 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10432 do \
10433 { \
10434 if ((MASK) & insn_flags) \
10435 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10436 } \
10437 while (0)
10438
10439 struct builtin_description
10440 {
10441 const unsigned int mask;
10442 const enum insn_code icode;
10443 const char * const name;
10444 const enum arm_builtins code;
10445 const enum rtx_code comparison;
10446 const unsigned int flag;
10447 };
10448
10449 static const struct builtin_description bdesc_2arg[] =
10450 {
10451 #define IWMMXT_BUILTIN(code, string, builtin) \
10452 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10453 ARM_BUILTIN_##builtin, 0, 0 },
10454
10455 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
10456 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
10457 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
10458 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
10459 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
10460 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
10461 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
10462 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
10463 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
10464 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
10465 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
10466 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
10467 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
10468 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
10469 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
10470 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
10471 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
10472 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
10473 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
10474 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH)
10475 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH)
10476 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
10477 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
10478 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
10479 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
10480 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
10481 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
10482 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
10483 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
10484 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
10485 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
10486 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
10487 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
10488 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
10489 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
10490 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
10491 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
10492 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
10493 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
10494 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
10495 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
10496 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
10497 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
10498 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
10499 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
10500 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
10501 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
10502 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
10503 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
10504 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
10505 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
10506 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
10507 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
10508 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
10509 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
10510 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
10511 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
10512 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
10513
10514 #define IWMMXT_BUILTIN2(code, builtin) \
10515 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10516
10517 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
10518 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
10519 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
10520 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
10521 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
10522 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
10523 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
10524 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
10525 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
10526 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
10527 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
10528 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
10529 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
10530 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
10531 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
10532 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
10533 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
10534 IWMMXT_BUILTIN2 (lshrdi3, WSRLDI)
10535 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
10536 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
10537 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
10538 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
10539 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
10540 IWMMXT_BUILTIN2 (ashrdi3, WSRADI)
10541 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
10542 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
10543 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
10544 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
10545 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
10546 IWMMXT_BUILTIN2 (rordi3, WRORDI)
10547 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
10548 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
10549 };
10550
10551 static const struct builtin_description bdesc_1arg[] =
10552 {
10553 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
10554 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
10555 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
10556 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
10557 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
10558 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
10559 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
10560 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
10561 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
10562 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
10563 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
10564 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
10565 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
10566 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
10567 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
10568 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
10569 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
10570 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
10571 };
10572
10573 /* Set up all the iWMMXt builtins. This is
10574 not called if TARGET_IWMMXT is zero. */
10575
10576 static void
10577 arm_init_iwmmxt_builtins (void)
10578 {
10579 const struct builtin_description * d;
10580 size_t i;
10581 tree endlink = void_list_node;
10582
10583 tree int_ftype_int
10584 = build_function_type (integer_type_node,
10585 tree_cons (NULL_TREE, integer_type_node, endlink));
10586 tree v8qi_ftype_v8qi_v8qi_int
10587 = build_function_type (V8QI_type_node,
10588 tree_cons (NULL_TREE, V8QI_type_node,
10589 tree_cons (NULL_TREE, V8QI_type_node,
10590 tree_cons (NULL_TREE,
10591 integer_type_node,
10592 endlink))));
10593 tree v4hi_ftype_v4hi_int
10594 = build_function_type (V4HI_type_node,
10595 tree_cons (NULL_TREE, V4HI_type_node,
10596 tree_cons (NULL_TREE, integer_type_node,
10597 endlink)));
10598 tree v2si_ftype_v2si_int
10599 = build_function_type (V2SI_type_node,
10600 tree_cons (NULL_TREE, V2SI_type_node,
10601 tree_cons (NULL_TREE, integer_type_node,
10602 endlink)));
10603 tree v2si_ftype_di_di
10604 = build_function_type (V2SI_type_node,
10605 tree_cons (NULL_TREE, long_long_integer_type_node,
10606 tree_cons (NULL_TREE, long_long_integer_type_node,
10607 endlink)));
10608 tree di_ftype_di_int
10609 = build_function_type (long_long_integer_type_node,
10610 tree_cons (NULL_TREE, long_long_integer_type_node,
10611 tree_cons (NULL_TREE, integer_type_node,
10612 endlink)));
10613 tree di_ftype_di_int_int
10614 = build_function_type (long_long_integer_type_node,
10615 tree_cons (NULL_TREE, long_long_integer_type_node,
10616 tree_cons (NULL_TREE, integer_type_node,
10617 tree_cons (NULL_TREE,
10618 integer_type_node,
10619 endlink))));
10620 tree int_ftype_v8qi
10621 = build_function_type (integer_type_node,
10622 tree_cons (NULL_TREE, V8QI_type_node,
10623 endlink));
10624 tree int_ftype_v4hi
10625 = build_function_type (integer_type_node,
10626 tree_cons (NULL_TREE, V4HI_type_node,
10627 endlink));
10628 tree int_ftype_v2si
10629 = build_function_type (integer_type_node,
10630 tree_cons (NULL_TREE, V2SI_type_node,
10631 endlink));
10632 tree int_ftype_v8qi_int
10633 = build_function_type (integer_type_node,
10634 tree_cons (NULL_TREE, V8QI_type_node,
10635 tree_cons (NULL_TREE, integer_type_node,
10636 endlink)));
10637 tree int_ftype_v4hi_int
10638 = build_function_type (integer_type_node,
10639 tree_cons (NULL_TREE, V4HI_type_node,
10640 tree_cons (NULL_TREE, integer_type_node,
10641 endlink)));
10642 tree int_ftype_v2si_int
10643 = build_function_type (integer_type_node,
10644 tree_cons (NULL_TREE, V2SI_type_node,
10645 tree_cons (NULL_TREE, integer_type_node,
10646 endlink)));
10647 tree v8qi_ftype_v8qi_int_int
10648 = build_function_type (V8QI_type_node,
10649 tree_cons (NULL_TREE, V8QI_type_node,
10650 tree_cons (NULL_TREE, integer_type_node,
10651 tree_cons (NULL_TREE,
10652 integer_type_node,
10653 endlink))));
10654 tree v4hi_ftype_v4hi_int_int
10655 = build_function_type (V4HI_type_node,
10656 tree_cons (NULL_TREE, V4HI_type_node,
10657 tree_cons (NULL_TREE, integer_type_node,
10658 tree_cons (NULL_TREE,
10659 integer_type_node,
10660 endlink))));
10661 tree v2si_ftype_v2si_int_int
10662 = build_function_type (V2SI_type_node,
10663 tree_cons (NULL_TREE, V2SI_type_node,
10664 tree_cons (NULL_TREE, integer_type_node,
10665 tree_cons (NULL_TREE,
10666 integer_type_node,
10667 endlink))));
10668 /* Miscellaneous. */
10669 tree v8qi_ftype_v4hi_v4hi
10670 = build_function_type (V8QI_type_node,
10671 tree_cons (NULL_TREE, V4HI_type_node,
10672 tree_cons (NULL_TREE, V4HI_type_node,
10673 endlink)));
10674 tree v4hi_ftype_v2si_v2si
10675 = build_function_type (V4HI_type_node,
10676 tree_cons (NULL_TREE, V2SI_type_node,
10677 tree_cons (NULL_TREE, V2SI_type_node,
10678 endlink)));
10679 tree v2si_ftype_v4hi_v4hi
10680 = build_function_type (V2SI_type_node,
10681 tree_cons (NULL_TREE, V4HI_type_node,
10682 tree_cons (NULL_TREE, V4HI_type_node,
10683 endlink)));
10684 tree v2si_ftype_v8qi_v8qi
10685 = build_function_type (V2SI_type_node,
10686 tree_cons (NULL_TREE, V8QI_type_node,
10687 tree_cons (NULL_TREE, V8QI_type_node,
10688 endlink)));
10689 tree v4hi_ftype_v4hi_di
10690 = build_function_type (V4HI_type_node,
10691 tree_cons (NULL_TREE, V4HI_type_node,
10692 tree_cons (NULL_TREE,
10693 long_long_integer_type_node,
10694 endlink)));
10695 tree v2si_ftype_v2si_di
10696 = build_function_type (V2SI_type_node,
10697 tree_cons (NULL_TREE, V2SI_type_node,
10698 tree_cons (NULL_TREE,
10699 long_long_integer_type_node,
10700 endlink)));
10701 tree void_ftype_int_int
10702 = build_function_type (void_type_node,
10703 tree_cons (NULL_TREE, integer_type_node,
10704 tree_cons (NULL_TREE, integer_type_node,
10705 endlink)));
10706 tree di_ftype_void
10707 = build_function_type (long_long_unsigned_type_node, endlink);
10708 tree di_ftype_v8qi
10709 = build_function_type (long_long_integer_type_node,
10710 tree_cons (NULL_TREE, V8QI_type_node,
10711 endlink));
10712 tree di_ftype_v4hi
10713 = build_function_type (long_long_integer_type_node,
10714 tree_cons (NULL_TREE, V4HI_type_node,
10715 endlink));
10716 tree di_ftype_v2si
10717 = build_function_type (long_long_integer_type_node,
10718 tree_cons (NULL_TREE, V2SI_type_node,
10719 endlink));
10720 tree v2si_ftype_v4hi
10721 = build_function_type (V2SI_type_node,
10722 tree_cons (NULL_TREE, V4HI_type_node,
10723 endlink));
10724 tree v4hi_ftype_v8qi
10725 = build_function_type (V4HI_type_node,
10726 tree_cons (NULL_TREE, V8QI_type_node,
10727 endlink));
10728
10729 tree di_ftype_di_v4hi_v4hi
10730 = build_function_type (long_long_unsigned_type_node,
10731 tree_cons (NULL_TREE,
10732 long_long_unsigned_type_node,
10733 tree_cons (NULL_TREE, V4HI_type_node,
10734 tree_cons (NULL_TREE,
10735 V4HI_type_node,
10736 endlink))));
10737
10738 tree di_ftype_v4hi_v4hi
10739 = build_function_type (long_long_unsigned_type_node,
10740 tree_cons (NULL_TREE, V4HI_type_node,
10741 tree_cons (NULL_TREE, V4HI_type_node,
10742 endlink)));
10743
10744 /* Normal vector binops. */
10745 tree v8qi_ftype_v8qi_v8qi
10746 = build_function_type (V8QI_type_node,
10747 tree_cons (NULL_TREE, V8QI_type_node,
10748 tree_cons (NULL_TREE, V8QI_type_node,
10749 endlink)));
10750 tree v4hi_ftype_v4hi_v4hi
10751 = build_function_type (V4HI_type_node,
10752 tree_cons (NULL_TREE, V4HI_type_node,
10753 tree_cons (NULL_TREE, V4HI_type_node,
10754 endlink)));
10755 tree v2si_ftype_v2si_v2si
10756 = build_function_type (V2SI_type_node,
10757 tree_cons (NULL_TREE, V2SI_type_node,
10758 tree_cons (NULL_TREE, V2SI_type_node,
10759 endlink)));
10760 tree di_ftype_di_di
10761 = build_function_type (long_long_unsigned_type_node,
10762 tree_cons (NULL_TREE, long_long_unsigned_type_node,
10763 tree_cons (NULL_TREE,
10764 long_long_unsigned_type_node,
10765 endlink)));
10766
10767 /* Add all builtins that are more or less simple operations on two
10768 operands. */
10769 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10770 {
10771 /* Use one of the operands; the target can have a different mode for
10772 mask-generating compares. */
10773 enum machine_mode mode;
10774 tree type;
10775
10776 if (d->name == 0)
10777 continue;
10778
10779 mode = insn_data[d->icode].operand[1].mode;
10780
10781 switch (mode)
10782 {
10783 case V8QImode:
10784 type = v8qi_ftype_v8qi_v8qi;
10785 break;
10786 case V4HImode:
10787 type = v4hi_ftype_v4hi_v4hi;
10788 break;
10789 case V2SImode:
10790 type = v2si_ftype_v2si_v2si;
10791 break;
10792 case DImode:
10793 type = di_ftype_di_di;
10794 break;
10795
10796 default:
10797 abort ();
10798 }
10799
10800 def_mbuiltin (d->mask, d->name, type, d->code);
10801 }
10802
10803 /* Add the remaining MMX insns with somewhat more complicated types. */
10804 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
10805 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
10806 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
10807
10808 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
10809 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
10810 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
10811 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
10812 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
10813 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
10814
10815 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
10816 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
10817 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
10818 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
10819 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
10820 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
10821
10822 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
10823 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
10824 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
10825 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
10826 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
10827 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
10828
10829 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
10830 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
10831 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
10832 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
10833 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
10834 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
10835
10836 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
10837
10838 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
10839 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
10840 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
10841 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
10842
10843 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
10844 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
10845 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
10846 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
10847 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
10848 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
10849 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
10850 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
10851 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
10852
10853 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
10854 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
10855 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
10856
10857 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
10858 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
10859 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
10860
10861 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
10862 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
10863 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
10864 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
10865 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
10866 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
10867
10868 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
10869 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
10870 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
10871 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
10872 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
10873 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
10874 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
10875 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
10876 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
10877 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
10878 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
10879 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
10880
10881 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
10882 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
10883 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
10884 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
10885
10886 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
10887 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
10888 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
10889 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
10890 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
10891 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
10892 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
10893 }
10894
10895 static void
10896 arm_init_builtins (void)
10897 {
10898 if (TARGET_REALLY_IWMMXT)
10899 arm_init_iwmmxt_builtins ();
10900 }
10901
10902 /* Errors in the source file can cause expand_expr to return const0_rtx
10903 where we expect a vector. To avoid crashing, use one of the vector
10904 clear instructions. */
10905
10906 static rtx
10907 safe_vector_operand (rtx x, enum machine_mode mode)
10908 {
10909 if (x != const0_rtx)
10910 return x;
10911 x = gen_reg_rtx (mode);
10912
10913 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
10914 : gen_rtx_SUBREG (DImode, x, 0)));
10915 return x;
10916 }
10917
10918 /* Subroutine of arm_expand_builtin to take care of binop insns. */
10919
10920 static rtx
10921 arm_expand_binop_builtin (enum insn_code icode,
10922 tree arglist, rtx target)
10923 {
10924 rtx pat;
10925 tree arg0 = TREE_VALUE (arglist);
10926 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
10927 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
10928 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
10929 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10930 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10931 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10932
10933 if (VECTOR_MODE_P (mode0))
10934 op0 = safe_vector_operand (op0, mode0);
10935 if (VECTOR_MODE_P (mode1))
10936 op1 = safe_vector_operand (op1, mode1);
10937
10938 if (! target
10939 || GET_MODE (target) != tmode
10940 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10941 target = gen_reg_rtx (tmode);
10942
10943 /* In case the insn wants input operands in modes different from
10944 the result, abort. */
10945 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
10946 abort ();
10947
10948 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10949 op0 = copy_to_mode_reg (mode0, op0);
10950 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10951 op1 = copy_to_mode_reg (mode1, op1);
10952
10953 pat = GEN_FCN (icode) (target, op0, op1);
10954 if (! pat)
10955 return 0;
10956 emit_insn (pat);
10957 return target;
10958 }
10959
10960 /* Subroutine of arm_expand_builtin to take care of unop insns. */
10961
10962 static rtx
10963 arm_expand_unop_builtin (enum insn_code icode,
10964 tree arglist, rtx target, int do_load)
10965 {
10966 rtx pat;
10967 tree arg0 = TREE_VALUE (arglist);
10968 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
10969 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10970 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10971
10972 if (! target
10973 || GET_MODE (target) != tmode
10974 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10975 target = gen_reg_rtx (tmode);
10976 if (do_load)
10977 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10978 else
10979 {
10980 if (VECTOR_MODE_P (mode0))
10981 op0 = safe_vector_operand (op0, mode0);
10982
10983 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10984 op0 = copy_to_mode_reg (mode0, op0);
10985 }
10986
10987 pat = GEN_FCN (icode) (target, op0);
10988 if (! pat)
10989 return 0;
10990 emit_insn (pat);
10991 return target;
10992 }
10993
10994 /* Expand an expression EXP that calls a built-in function,
10995 with result going to TARGET if that's convenient
10996 (and in mode MODE if that's convenient).
10997 SUBTARGET may be used as the target for computing one of EXP's operands.
10998 IGNORE is nonzero if the value is to be ignored. */
10999
11000 static rtx
11001 arm_expand_builtin (tree exp,
11002 rtx target,
11003 rtx subtarget ATTRIBUTE_UNUSED,
11004 enum machine_mode mode ATTRIBUTE_UNUSED,
11005 int ignore ATTRIBUTE_UNUSED)
11006 {
11007 const struct builtin_description * d;
11008 enum insn_code icode;
11009 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
11010 tree arglist = TREE_OPERAND (exp, 1);
11011 tree arg0;
11012 tree arg1;
11013 tree arg2;
11014 rtx op0;
11015 rtx op1;
11016 rtx op2;
11017 rtx pat;
11018 int fcode = DECL_FUNCTION_CODE (fndecl);
11019 size_t i;
11020 enum machine_mode tmode;
11021 enum machine_mode mode0;
11022 enum machine_mode mode1;
11023 enum machine_mode mode2;
11024
11025 switch (fcode)
11026 {
11027 case ARM_BUILTIN_TEXTRMSB:
11028 case ARM_BUILTIN_TEXTRMUB:
11029 case ARM_BUILTIN_TEXTRMSH:
11030 case ARM_BUILTIN_TEXTRMUH:
11031 case ARM_BUILTIN_TEXTRMSW:
11032 case ARM_BUILTIN_TEXTRMUW:
11033 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
11034 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
11035 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
11036 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
11037 : CODE_FOR_iwmmxt_textrmw);
11038
11039 arg0 = TREE_VALUE (arglist);
11040 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11041 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11042 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11043 tmode = insn_data[icode].operand[0].mode;
11044 mode0 = insn_data[icode].operand[1].mode;
11045 mode1 = insn_data[icode].operand[2].mode;
11046
11047 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11048 op0 = copy_to_mode_reg (mode0, op0);
11049 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11050 {
11051 /* @@@ better error message */
11052 error ("selector must be an immediate");
11053 return gen_reg_rtx (tmode);
11054 }
11055 if (target == 0
11056 || GET_MODE (target) != tmode
11057 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11058 target = gen_reg_rtx (tmode);
11059 pat = GEN_FCN (icode) (target, op0, op1);
11060 if (! pat)
11061 return 0;
11062 emit_insn (pat);
11063 return target;
11064
11065 case ARM_BUILTIN_TINSRB:
11066 case ARM_BUILTIN_TINSRH:
11067 case ARM_BUILTIN_TINSRW:
11068 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
11069 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
11070 : CODE_FOR_iwmmxt_tinsrw);
11071 arg0 = TREE_VALUE (arglist);
11072 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11073 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11074 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11075 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11076 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11077 tmode = insn_data[icode].operand[0].mode;
11078 mode0 = insn_data[icode].operand[1].mode;
11079 mode1 = insn_data[icode].operand[2].mode;
11080 mode2 = insn_data[icode].operand[3].mode;
11081
11082 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11083 op0 = copy_to_mode_reg (mode0, op0);
11084 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11085 op1 = copy_to_mode_reg (mode1, op1);
11086 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11087 {
11088 /* @@@ better error message */
11089 error ("selector must be an immediate");
11090 return const0_rtx;
11091 }
11092 if (target == 0
11093 || GET_MODE (target) != tmode
11094 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11095 target = gen_reg_rtx (tmode);
11096 pat = GEN_FCN (icode) (target, op0, op1, op2);
11097 if (! pat)
11098 return 0;
11099 emit_insn (pat);
11100 return target;
11101
11102 case ARM_BUILTIN_SETWCX:
11103 arg0 = TREE_VALUE (arglist);
11104 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11105 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11106 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11107 emit_insn (gen_iwmmxt_tmcr (op0, op1));
11108 return 0;
11109
11110 case ARM_BUILTIN_GETWCX:
11111 arg0 = TREE_VALUE (arglist);
11112 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11113 target = gen_reg_rtx (SImode);
11114 emit_insn (gen_iwmmxt_tmrc (target, op0));
11115 return target;
11116
11117 case ARM_BUILTIN_WSHUFH:
11118 icode = CODE_FOR_iwmmxt_wshufh;
11119 arg0 = TREE_VALUE (arglist);
11120 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11121 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11122 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11123 tmode = insn_data[icode].operand[0].mode;
11124 mode1 = insn_data[icode].operand[1].mode;
11125 mode2 = insn_data[icode].operand[2].mode;
11126
11127 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
11128 op0 = copy_to_mode_reg (mode1, op0);
11129 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
11130 {
11131 /* @@@ better error message */
11132 error ("mask must be an immediate");
11133 return const0_rtx;
11134 }
11135 if (target == 0
11136 || GET_MODE (target) != tmode
11137 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11138 target = gen_reg_rtx (tmode);
11139 pat = GEN_FCN (icode) (target, op0, op1);
11140 if (! pat)
11141 return 0;
11142 emit_insn (pat);
11143 return target;
11144
11145 case ARM_BUILTIN_WSADB:
11146 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
11147 case ARM_BUILTIN_WSADH:
11148 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
11149 case ARM_BUILTIN_WSADBZ:
11150 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
11151 case ARM_BUILTIN_WSADHZ:
11152 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
11153
11154 /* Several three-argument builtins. */
11155 case ARM_BUILTIN_WMACS:
11156 case ARM_BUILTIN_WMACU:
11157 case ARM_BUILTIN_WALIGN:
11158 case ARM_BUILTIN_TMIA:
11159 case ARM_BUILTIN_TMIAPH:
11160 case ARM_BUILTIN_TMIATT:
11161 case ARM_BUILTIN_TMIATB:
11162 case ARM_BUILTIN_TMIABT:
11163 case ARM_BUILTIN_TMIABB:
11164 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
11165 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
11166 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
11167 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
11168 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
11169 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
11170 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
11171 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
11172 : CODE_FOR_iwmmxt_walign);
11173 arg0 = TREE_VALUE (arglist);
11174 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11175 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11176 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11177 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11178 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11179 tmode = insn_data[icode].operand[0].mode;
11180 mode0 = insn_data[icode].operand[1].mode;
11181 mode1 = insn_data[icode].operand[2].mode;
11182 mode2 = insn_data[icode].operand[3].mode;
11183
11184 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11185 op0 = copy_to_mode_reg (mode0, op0);
11186 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11187 op1 = copy_to_mode_reg (mode1, op1);
11188 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11189 op2 = copy_to_mode_reg (mode2, op2);
11190 if (target == 0
11191 || GET_MODE (target) != tmode
11192 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11193 target = gen_reg_rtx (tmode);
11194 pat = GEN_FCN (icode) (target, op0, op1, op2);
11195 if (! pat)
11196 return 0;
11197 emit_insn (pat);
11198 return target;
11199
11200 case ARM_BUILTIN_WZERO:
11201 target = gen_reg_rtx (DImode);
11202 emit_insn (gen_iwmmxt_clrdi (target));
11203 return target;
11204
11205 default:
11206 break;
11207 }
11208
11209 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11210 if (d->code == (const enum arm_builtins) fcode)
11211 return arm_expand_binop_builtin (d->icode, arglist, target);
11212
11213 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11214 if (d->code == (const enum arm_builtins) fcode)
11215 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
11216
11217 /* @@@ Should really do something sensible here. */
11218 return NULL_RTX;
11219 }
11220 \f
11221 /* Recursively search through all of the blocks in a function
11222 checking to see if any of the variables created in that
11223 function match the RTX called 'orig'. If they do then
11224 replace them with the RTX called 'new'. */
11225 static void
11226 replace_symbols_in_block (tree block, rtx orig, rtx new)
11227 {
11228 for (; block; block = BLOCK_CHAIN (block))
11229 {
11230 tree sym;
11231
11232 if (!TREE_USED (block))
11233 continue;
11234
11235 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
11236 {
11237 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
11238 || DECL_IGNORED_P (sym)
11239 || TREE_CODE (sym) != VAR_DECL
11240 || DECL_EXTERNAL (sym)
11241 || !rtx_equal_p (DECL_RTL (sym), orig)
11242 )
11243 continue;
11244
11245 SET_DECL_RTL (sym, new);
11246 }
11247
11248 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
11249 }
11250 }
11251
11252 /* Return the number (counting from 0) of
11253 the least significant set bit in MASK. */
11254
11255 inline static int
11256 number_of_first_bit_set (int mask)
11257 {
11258 int bit;
11259
11260 for (bit = 0;
11261 (mask & (1 << bit)) == 0;
11262 ++bit)
11263 continue;
11264
11265 return bit;
11266 }
11267
11268 /* Generate code to return from a thumb function.
11269 If 'reg_containing_return_addr' is -1, then the return address is
11270 actually on the stack, at the stack pointer. */
11271 static void
11272 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
11273 {
11274 unsigned regs_available_for_popping;
11275 unsigned regs_to_pop;
11276 int pops_needed;
11277 unsigned available;
11278 unsigned required;
11279 int mode;
11280 int size;
11281 int restore_a4 = FALSE;
11282
11283 /* Compute the registers we need to pop. */
11284 regs_to_pop = 0;
11285 pops_needed = 0;
11286
11287 /* There is an assumption here, that if eh_ofs is not NULL, the
11288 normal return address will have been pushed. */
11289 if (reg_containing_return_addr == -1 || eh_ofs)
11290 {
11291 /* When we are generating a return for __builtin_eh_return,
11292 reg_containing_return_addr must specify the return regno. */
11293 if (eh_ofs && reg_containing_return_addr == -1)
11294 abort ();
11295
11296 regs_to_pop |= 1 << LR_REGNUM;
11297 ++pops_needed;
11298 }
11299
11300 if (TARGET_BACKTRACE)
11301 {
11302 /* Restore the (ARM) frame pointer and stack pointer. */
11303 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
11304 pops_needed += 2;
11305 }
11306
11307 /* If there is nothing to pop then just emit the BX instruction and
11308 return. */
11309 if (pops_needed == 0)
11310 {
11311 if (eh_ofs)
11312 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11313
11314 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11315 return;
11316 }
11317 /* Otherwise if we are not supporting interworking and we have not created
11318 a backtrace structure and the function was not entered in ARM mode then
11319 just pop the return address straight into the PC. */
11320 else if (!TARGET_INTERWORK
11321 && !TARGET_BACKTRACE
11322 && !is_called_in_ARM_mode (current_function_decl))
11323 {
11324 if (eh_ofs)
11325 {
11326 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
11327 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11328 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11329 }
11330 else
11331 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
11332
11333 return;
11334 }
11335
11336 /* Find out how many of the (return) argument registers we can corrupt. */
11337 regs_available_for_popping = 0;
11338
11339 /* If returning via __builtin_eh_return, the bottom three registers
11340 all contain information needed for the return. */
11341 if (eh_ofs)
11342 size = 12;
11343 else
11344 {
11345 #ifdef RTX_CODE
11346 /* If we can deduce the registers used from the function's
11347 return value. This is more reliable that examining
11348 regs_ever_live[] because that will be set if the register is
11349 ever used in the function, not just if the register is used
11350 to hold a return value. */
11351
11352 if (current_function_return_rtx != 0)
11353 mode = GET_MODE (current_function_return_rtx);
11354 else
11355 #endif
11356 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11357
11358 size = GET_MODE_SIZE (mode);
11359
11360 if (size == 0)
11361 {
11362 /* In a void function we can use any argument register.
11363 In a function that returns a structure on the stack
11364 we can use the second and third argument registers. */
11365 if (mode == VOIDmode)
11366 regs_available_for_popping =
11367 (1 << ARG_REGISTER (1))
11368 | (1 << ARG_REGISTER (2))
11369 | (1 << ARG_REGISTER (3));
11370 else
11371 regs_available_for_popping =
11372 (1 << ARG_REGISTER (2))
11373 | (1 << ARG_REGISTER (3));
11374 }
11375 else if (size <= 4)
11376 regs_available_for_popping =
11377 (1 << ARG_REGISTER (2))
11378 | (1 << ARG_REGISTER (3));
11379 else if (size <= 8)
11380 regs_available_for_popping =
11381 (1 << ARG_REGISTER (3));
11382 }
11383
11384 /* Match registers to be popped with registers into which we pop them. */
11385 for (available = regs_available_for_popping,
11386 required = regs_to_pop;
11387 required != 0 && available != 0;
11388 available &= ~(available & - available),
11389 required &= ~(required & - required))
11390 -- pops_needed;
11391
11392 /* If we have any popping registers left over, remove them. */
11393 if (available > 0)
11394 regs_available_for_popping &= ~available;
11395
11396 /* Otherwise if we need another popping register we can use
11397 the fourth argument register. */
11398 else if (pops_needed)
11399 {
11400 /* If we have not found any free argument registers and
11401 reg a4 contains the return address, we must move it. */
11402 if (regs_available_for_popping == 0
11403 && reg_containing_return_addr == LAST_ARG_REGNUM)
11404 {
11405 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11406 reg_containing_return_addr = LR_REGNUM;
11407 }
11408 else if (size > 12)
11409 {
11410 /* Register a4 is being used to hold part of the return value,
11411 but we have dire need of a free, low register. */
11412 restore_a4 = TRUE;
11413
11414 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
11415 }
11416
11417 if (reg_containing_return_addr != LAST_ARG_REGNUM)
11418 {
11419 /* The fourth argument register is available. */
11420 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
11421
11422 --pops_needed;
11423 }
11424 }
11425
11426 /* Pop as many registers as we can. */
11427 thumb_pushpop (f, regs_available_for_popping, FALSE);
11428
11429 /* Process the registers we popped. */
11430 if (reg_containing_return_addr == -1)
11431 {
11432 /* The return address was popped into the lowest numbered register. */
11433 regs_to_pop &= ~(1 << LR_REGNUM);
11434
11435 reg_containing_return_addr =
11436 number_of_first_bit_set (regs_available_for_popping);
11437
11438 /* Remove this register for the mask of available registers, so that
11439 the return address will not be corrupted by further pops. */
11440 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
11441 }
11442
11443 /* If we popped other registers then handle them here. */
11444 if (regs_available_for_popping)
11445 {
11446 int frame_pointer;
11447
11448 /* Work out which register currently contains the frame pointer. */
11449 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
11450
11451 /* Move it into the correct place. */
11452 asm_fprintf (f, "\tmov\t%r, %r\n",
11453 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
11454
11455 /* (Temporarily) remove it from the mask of popped registers. */
11456 regs_available_for_popping &= ~(1 << frame_pointer);
11457 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
11458
11459 if (regs_available_for_popping)
11460 {
11461 int stack_pointer;
11462
11463 /* We popped the stack pointer as well,
11464 find the register that contains it. */
11465 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
11466
11467 /* Move it into the stack register. */
11468 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
11469
11470 /* At this point we have popped all necessary registers, so
11471 do not worry about restoring regs_available_for_popping
11472 to its correct value:
11473
11474 assert (pops_needed == 0)
11475 assert (regs_available_for_popping == (1 << frame_pointer))
11476 assert (regs_to_pop == (1 << STACK_POINTER)) */
11477 }
11478 else
11479 {
11480 /* Since we have just move the popped value into the frame
11481 pointer, the popping register is available for reuse, and
11482 we know that we still have the stack pointer left to pop. */
11483 regs_available_for_popping |= (1 << frame_pointer);
11484 }
11485 }
11486
11487 /* If we still have registers left on the stack, but we no longer have
11488 any registers into which we can pop them, then we must move the return
11489 address into the link register and make available the register that
11490 contained it. */
11491 if (regs_available_for_popping == 0 && pops_needed > 0)
11492 {
11493 regs_available_for_popping |= 1 << reg_containing_return_addr;
11494
11495 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
11496 reg_containing_return_addr);
11497
11498 reg_containing_return_addr = LR_REGNUM;
11499 }
11500
11501 /* If we have registers left on the stack then pop some more.
11502 We know that at most we will want to pop FP and SP. */
11503 if (pops_needed > 0)
11504 {
11505 int popped_into;
11506 int move_to;
11507
11508 thumb_pushpop (f, regs_available_for_popping, FALSE);
11509
11510 /* We have popped either FP or SP.
11511 Move whichever one it is into the correct register. */
11512 popped_into = number_of_first_bit_set (regs_available_for_popping);
11513 move_to = number_of_first_bit_set (regs_to_pop);
11514
11515 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
11516
11517 regs_to_pop &= ~(1 << move_to);
11518
11519 --pops_needed;
11520 }
11521
11522 /* If we still have not popped everything then we must have only
11523 had one register available to us and we are now popping the SP. */
11524 if (pops_needed > 0)
11525 {
11526 int popped_into;
11527
11528 thumb_pushpop (f, regs_available_for_popping, FALSE);
11529
11530 popped_into = number_of_first_bit_set (regs_available_for_popping);
11531
11532 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
11533 /*
11534 assert (regs_to_pop == (1 << STACK_POINTER))
11535 assert (pops_needed == 1)
11536 */
11537 }
11538
11539 /* If necessary restore the a4 register. */
11540 if (restore_a4)
11541 {
11542 if (reg_containing_return_addr != LR_REGNUM)
11543 {
11544 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11545 reg_containing_return_addr = LR_REGNUM;
11546 }
11547
11548 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
11549 }
11550
11551 if (eh_ofs)
11552 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11553
11554 /* Return to caller. */
11555 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11556 }
11557
11558 /* Emit code to push or pop registers to or from the stack. */
11559 static void
11560 thumb_pushpop (FILE *f, int mask, int push)
11561 {
11562 int regno;
11563 int lo_mask = mask & 0xFF;
11564
11565 if (lo_mask == 0 && !push && (mask & (1 << 15)))
11566 {
11567 /* Special case. Do not generate a POP PC statement here, do it in
11568 thumb_exit() */
11569 thumb_exit (f, -1, NULL_RTX);
11570 return;
11571 }
11572
11573 fprintf (f, "\t%s\t{", push ? "push" : "pop");
11574
11575 /* Look at the low registers first. */
11576 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
11577 {
11578 if (lo_mask & 1)
11579 {
11580 asm_fprintf (f, "%r", regno);
11581
11582 if ((lo_mask & ~1) != 0)
11583 fprintf (f, ", ");
11584 }
11585 }
11586
11587 if (push && (mask & (1 << LR_REGNUM)))
11588 {
11589 /* Catch pushing the LR. */
11590 if (mask & 0xFF)
11591 fprintf (f, ", ");
11592
11593 asm_fprintf (f, "%r", LR_REGNUM);
11594 }
11595 else if (!push && (mask & (1 << PC_REGNUM)))
11596 {
11597 /* Catch popping the PC. */
11598 if (TARGET_INTERWORK || TARGET_BACKTRACE)
11599 {
11600 /* The PC is never poped directly, instead
11601 it is popped into r3 and then BX is used. */
11602 fprintf (f, "}\n");
11603
11604 thumb_exit (f, -1, NULL_RTX);
11605
11606 return;
11607 }
11608 else
11609 {
11610 if (mask & 0xFF)
11611 fprintf (f, ", ");
11612
11613 asm_fprintf (f, "%r", PC_REGNUM);
11614 }
11615 }
11616
11617 fprintf (f, "}\n");
11618 }
11619 \f
11620 void
11621 thumb_final_prescan_insn (rtx insn)
11622 {
11623 if (flag_print_asm_name)
11624 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
11625 INSN_ADDRESSES (INSN_UID (insn)));
11626 }
11627
11628 int
11629 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
11630 {
11631 unsigned HOST_WIDE_INT mask = 0xff;
11632 int i;
11633
11634 if (val == 0) /* XXX */
11635 return 0;
11636
11637 for (i = 0; i < 25; i++)
11638 if ((val & (mask << i)) == val)
11639 return 1;
11640
11641 return 0;
11642 }
11643
11644 /* Returns nonzero if the current function contains,
11645 or might contain a far jump. */
11646 int
11647 thumb_far_jump_used_p (int in_prologue)
11648 {
11649 rtx insn;
11650
11651 /* This test is only important for leaf functions. */
11652 /* assert (!leaf_function_p ()); */
11653
11654 /* If we have already decided that far jumps may be used,
11655 do not bother checking again, and always return true even if
11656 it turns out that they are not being used. Once we have made
11657 the decision that far jumps are present (and that hence the link
11658 register will be pushed onto the stack) we cannot go back on it. */
11659 if (cfun->machine->far_jump_used)
11660 return 1;
11661
11662 /* If this function is not being called from the prologue/epilogue
11663 generation code then it must be being called from the
11664 INITIAL_ELIMINATION_OFFSET macro. */
11665 if (!in_prologue)
11666 {
11667 /* In this case we know that we are being asked about the elimination
11668 of the arg pointer register. If that register is not being used,
11669 then there are no arguments on the stack, and we do not have to
11670 worry that a far jump might force the prologue to push the link
11671 register, changing the stack offsets. In this case we can just
11672 return false, since the presence of far jumps in the function will
11673 not affect stack offsets.
11674
11675 If the arg pointer is live (or if it was live, but has now been
11676 eliminated and so set to dead) then we do have to test to see if
11677 the function might contain a far jump. This test can lead to some
11678 false negatives, since before reload is completed, then length of
11679 branch instructions is not known, so gcc defaults to returning their
11680 longest length, which in turn sets the far jump attribute to true.
11681
11682 A false negative will not result in bad code being generated, but it
11683 will result in a needless push and pop of the link register. We
11684 hope that this does not occur too often. */
11685 if (regs_ever_live [ARG_POINTER_REGNUM])
11686 cfun->machine->arg_pointer_live = 1;
11687 else if (!cfun->machine->arg_pointer_live)
11688 return 0;
11689 }
11690
11691 /* Check to see if the function contains a branch
11692 insn with the far jump attribute set. */
11693 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11694 {
11695 if (GET_CODE (insn) == JUMP_INSN
11696 /* Ignore tablejump patterns. */
11697 && GET_CODE (PATTERN (insn)) != ADDR_VEC
11698 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
11699 && get_attr_far_jump (insn) == FAR_JUMP_YES
11700 )
11701 {
11702 /* Record the fact that we have decided that
11703 the function does use far jumps. */
11704 cfun->machine->far_jump_used = 1;
11705 return 1;
11706 }
11707 }
11708
11709 return 0;
11710 }
11711
11712 /* Return nonzero if FUNC must be entered in ARM mode. */
11713 int
11714 is_called_in_ARM_mode (tree func)
11715 {
11716 if (TREE_CODE (func) != FUNCTION_DECL)
11717 abort ();
11718
11719 /* Ignore the problem about functions whoes address is taken. */
11720 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
11721 return TRUE;
11722
11723 #ifdef ARM_PE
11724 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
11725 #else
11726 return FALSE;
11727 #endif
11728 }
11729
11730 /* The bits which aren't usefully expanded as rtl. */
11731 const char *
11732 thumb_unexpanded_epilogue (void)
11733 {
11734 int regno;
11735 int live_regs_mask = 0;
11736 int high_regs_pushed = 0;
11737 int leaf_function = leaf_function_p ();
11738 int had_to_push_lr;
11739 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
11740
11741 if (return_used_this_function)
11742 return "";
11743
11744 if (IS_NAKED (arm_current_func_type ()))
11745 return "";
11746
11747 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11748 if (THUMB_REG_PUSHED_P (regno))
11749 live_regs_mask |= 1 << regno;
11750
11751 for (regno = 8; regno < 13; regno++)
11752 if (THUMB_REG_PUSHED_P (regno))
11753 high_regs_pushed++;
11754
11755 /* The prolog may have pushed some high registers to use as
11756 work registers. eg the testsuite file:
11757 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11758 compiles to produce:
11759 push {r4, r5, r6, r7, lr}
11760 mov r7, r9
11761 mov r6, r8
11762 push {r6, r7}
11763 as part of the prolog. We have to undo that pushing here. */
11764
11765 if (high_regs_pushed)
11766 {
11767 int mask = live_regs_mask;
11768 int next_hi_reg;
11769 int size;
11770 int mode;
11771
11772 #ifdef RTX_CODE
11773 /* If we can deduce the registers used from the function's return value.
11774 This is more reliable that examining regs_ever_live[] because that
11775 will be set if the register is ever used in the function, not just if
11776 the register is used to hold a return value. */
11777
11778 if (current_function_return_rtx != 0)
11779 mode = GET_MODE (current_function_return_rtx);
11780 else
11781 #endif
11782 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11783
11784 size = GET_MODE_SIZE (mode);
11785
11786 /* Unless we are returning a type of size > 12 register r3 is
11787 available. */
11788 if (size < 13)
11789 mask |= 1 << 3;
11790
11791 if (mask == 0)
11792 /* Oh dear! We have no low registers into which we can pop
11793 high registers! */
11794 internal_error
11795 ("no low registers available for popping high registers");
11796
11797 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
11798 if (THUMB_REG_PUSHED_P (next_hi_reg))
11799 break;
11800
11801 while (high_regs_pushed)
11802 {
11803 /* Find lo register(s) into which the high register(s) can
11804 be popped. */
11805 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11806 {
11807 if (mask & (1 << regno))
11808 high_regs_pushed--;
11809 if (high_regs_pushed == 0)
11810 break;
11811 }
11812
11813 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
11814
11815 /* Pop the values into the low register(s). */
11816 thumb_pushpop (asm_out_file, mask, 0);
11817
11818 /* Move the value(s) into the high registers. */
11819 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11820 {
11821 if (mask & (1 << regno))
11822 {
11823 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
11824 regno);
11825
11826 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
11827 if (THUMB_REG_PUSHED_P (next_hi_reg))
11828 break;
11829 }
11830 }
11831 }
11832 }
11833
11834 had_to_push_lr = (live_regs_mask || !leaf_function
11835 || thumb_far_jump_used_p (1));
11836
11837 if (TARGET_BACKTRACE
11838 && ((live_regs_mask & 0xFF) == 0)
11839 && regs_ever_live [LAST_ARG_REGNUM] != 0)
11840 {
11841 /* The stack backtrace structure creation code had to
11842 push R7 in order to get a work register, so we pop
11843 it now. */
11844 live_regs_mask |= (1 << LAST_LO_REGNUM);
11845 }
11846
11847 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
11848 {
11849 if (had_to_push_lr
11850 && !is_called_in_ARM_mode (current_function_decl)
11851 && !eh_ofs)
11852 live_regs_mask |= 1 << PC_REGNUM;
11853
11854 /* Either no argument registers were pushed or a backtrace
11855 structure was created which includes an adjusted stack
11856 pointer, so just pop everything. */
11857 if (live_regs_mask)
11858 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
11859
11860 if (eh_ofs)
11861 thumb_exit (asm_out_file, 2, eh_ofs);
11862 /* We have either just popped the return address into the
11863 PC or it is was kept in LR for the entire function or
11864 it is still on the stack because we do not want to
11865 return by doing a pop {pc}. */
11866 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
11867 thumb_exit (asm_out_file,
11868 (had_to_push_lr
11869 && is_called_in_ARM_mode (current_function_decl)) ?
11870 -1 : LR_REGNUM, NULL_RTX);
11871 }
11872 else
11873 {
11874 /* Pop everything but the return address. */
11875 live_regs_mask &= ~(1 << PC_REGNUM);
11876
11877 if (live_regs_mask)
11878 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
11879
11880 if (had_to_push_lr)
11881 /* Get the return address into a temporary register. */
11882 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
11883
11884 /* Remove the argument registers that were pushed onto the stack. */
11885 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
11886 SP_REGNUM, SP_REGNUM,
11887 current_function_pretend_args_size);
11888
11889 if (eh_ofs)
11890 thumb_exit (asm_out_file, 2, eh_ofs);
11891 else
11892 thumb_exit (asm_out_file,
11893 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
11894 }
11895
11896 return "";
11897 }
11898
11899 /* Functions to save and restore machine-specific function data. */
11900 static struct machine_function *
11901 arm_init_machine_status (void)
11902 {
11903 struct machine_function *machine;
11904 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
11905
11906 #if ARM_FT_UNKNOWN != 0
11907 machine->func_type = ARM_FT_UNKNOWN;
11908 #endif
11909 return machine;
11910 }
11911
11912 /* Return an RTX indicating where the return address to the
11913 calling function can be found. */
11914 rtx
11915 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
11916 {
11917 if (count != 0)
11918 return NULL_RTX;
11919
11920 if (TARGET_APCS_32)
11921 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
11922 else
11923 {
11924 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
11925 GEN_INT (RETURN_ADDR_MASK26));
11926 return get_func_hard_reg_initial_val (cfun, lr);
11927 }
11928 }
11929
11930 /* Do anything needed before RTL is emitted for each function. */
11931 void
11932 arm_init_expanders (void)
11933 {
11934 /* Arrange to initialize and mark the machine per-function status. */
11935 init_machine_status = arm_init_machine_status;
11936 }
11937
11938 HOST_WIDE_INT
11939 thumb_get_frame_size (void)
11940 {
11941 int regno;
11942
11943 int base_size = ROUND_UP_WORD (get_frame_size ());
11944 int count_regs = 0;
11945 int entry_size = 0;
11946 int leaf;
11947
11948 if (! TARGET_THUMB)
11949 abort ();
11950
11951 if (! TARGET_ATPCS)
11952 return base_size;
11953
11954 /* We need to know if we are a leaf function. Unfortunately, it
11955 is possible to be called after start_sequence has been called,
11956 which causes get_insns to return the insns for the sequence,
11957 not the function, which will cause leaf_function_p to return
11958 the incorrect result.
11959
11960 To work around this, we cache the computed frame size. This
11961 works because we will only be calling RTL expanders that need
11962 to know about leaf functions once reload has completed, and the
11963 frame size cannot be changed after that time, so we can safely
11964 use the cached value. */
11965
11966 if (reload_completed)
11967 return cfun->machine->frame_size;
11968
11969 leaf = leaf_function_p ();
11970
11971 /* A leaf function does not need any stack alignment if it has nothing
11972 on the stack. */
11973 if (leaf && base_size == 0)
11974 {
11975 cfun->machine->frame_size = 0;
11976 return 0;
11977 }
11978
11979 /* We know that SP will be word aligned on entry, and we must
11980 preserve that condition at any subroutine call. But those are
11981 the only constraints. */
11982
11983 /* Space for variadic functions. */
11984 if (current_function_pretend_args_size)
11985 entry_size += current_function_pretend_args_size;
11986
11987 /* Space for pushed lo registers. */
11988 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11989 if (THUMB_REG_PUSHED_P (regno))
11990 count_regs++;
11991
11992 /* Space for backtrace structure. */
11993 if (TARGET_BACKTRACE)
11994 {
11995 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
11996 entry_size += 20;
11997 else
11998 entry_size += 16;
11999 }
12000
12001 if (count_regs || !leaf || thumb_far_jump_used_p (1))
12002 count_regs++; /* LR */
12003
12004 entry_size += count_regs * 4;
12005 count_regs = 0;
12006
12007 /* Space for pushed hi regs. */
12008 for (regno = 8; regno < 13; regno++)
12009 if (THUMB_REG_PUSHED_P (regno))
12010 count_regs++;
12011
12012 entry_size += count_regs * 4;
12013
12014 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12015 base_size += 4;
12016 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12017 abort ();
12018
12019 cfun->machine->frame_size = base_size;
12020
12021 return base_size;
12022 }
12023
12024 /* Generate the rest of a function's prologue. */
12025 void
12026 thumb_expand_prologue (void)
12027 {
12028 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12029 + current_function_outgoing_args_size);
12030 unsigned long func_type;
12031
12032 func_type = arm_current_func_type ();
12033
12034 /* Naked functions don't have prologues. */
12035 if (IS_NAKED (func_type))
12036 return;
12037
12038 if (IS_INTERRUPT (func_type))
12039 {
12040 error ("interrupt Service Routines cannot be coded in Thumb mode");
12041 return;
12042 }
12043
12044 if (frame_pointer_needed)
12045 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
12046
12047 if (amount)
12048 {
12049 amount = ROUND_UP_WORD (amount);
12050
12051 if (amount < 512)
12052 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12053 GEN_INT (- amount)));
12054 else
12055 {
12056 int regno;
12057 rtx reg;
12058
12059 /* The stack decrement is too big for an immediate value in a single
12060 insn. In theory we could issue multiple subtracts, but after
12061 three of them it becomes more space efficient to place the full
12062 value in the constant pool and load into a register. (Also the
12063 ARM debugger really likes to see only one stack decrement per
12064 function). So instead we look for a scratch register into which
12065 we can load the decrement, and then we subtract this from the
12066 stack pointer. Unfortunately on the thumb the only available
12067 scratch registers are the argument registers, and we cannot use
12068 these as they may hold arguments to the function. Instead we
12069 attempt to locate a call preserved register which is used by this
12070 function. If we can find one, then we know that it will have
12071 been pushed at the start of the prologue and so we can corrupt
12072 it now. */
12073 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
12074 if (THUMB_REG_PUSHED_P (regno)
12075 && !(frame_pointer_needed
12076 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
12077 break;
12078
12079 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
12080 {
12081 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
12082
12083 /* Choose an arbitrary, non-argument low register. */
12084 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
12085
12086 /* Save it by copying it into a high, scratch register. */
12087 emit_insn (gen_movsi (spare, reg));
12088 /* Add a USE to stop propagate_one_insn() from barfing. */
12089 emit_insn (gen_prologue_use (spare));
12090
12091 /* Decrement the stack. */
12092 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12093 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12094 reg));
12095
12096 /* Restore the low register's original value. */
12097 emit_insn (gen_movsi (reg, spare));
12098
12099 /* Emit a USE of the restored scratch register, so that flow
12100 analysis will not consider the restore redundant. The
12101 register won't be used again in this function and isn't
12102 restored by the epilogue. */
12103 emit_insn (gen_prologue_use (reg));
12104 }
12105 else
12106 {
12107 reg = gen_rtx (REG, SImode, regno);
12108
12109 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12110 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12111 reg));
12112 }
12113 }
12114 }
12115
12116 if (current_function_profile || TARGET_NO_SCHED_PRO)
12117 emit_insn (gen_blockage ());
12118 }
12119
12120 void
12121 thumb_expand_epilogue (void)
12122 {
12123 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12124 + current_function_outgoing_args_size);
12125 int regno;
12126
12127 /* Naked functions don't have prologues. */
12128 if (IS_NAKED (arm_current_func_type ()))
12129 return;
12130
12131 if (frame_pointer_needed)
12132 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
12133 else if (amount)
12134 {
12135 amount = ROUND_UP_WORD (amount);
12136
12137 if (amount < 512)
12138 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12139 GEN_INT (amount)));
12140 else
12141 {
12142 /* r3 is always free in the epilogue. */
12143 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
12144
12145 emit_insn (gen_movsi (reg, GEN_INT (amount)));
12146 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
12147 }
12148 }
12149
12150 /* Emit a USE (stack_pointer_rtx), so that
12151 the stack adjustment will not be deleted. */
12152 emit_insn (gen_prologue_use (stack_pointer_rtx));
12153
12154 if (current_function_profile || TARGET_NO_SCHED_PRO)
12155 emit_insn (gen_blockage ());
12156
12157 /* Emit a clobber for each insn that will be restored in the epilogue,
12158 so that flow2 will get register lifetimes correct. */
12159 for (regno = 0; regno < 13; regno++)
12160 if (regs_ever_live[regno] && !call_used_regs[regno])
12161 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
12162
12163 if (! regs_ever_live[LR_REGNUM])
12164 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
12165 }
12166
12167 static void
12168 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12169 {
12170 int live_regs_mask = 0;
12171 int high_regs_pushed = 0;
12172 int regno;
12173
12174 if (IS_NAKED (arm_current_func_type ()))
12175 return;
12176
12177 if (is_called_in_ARM_mode (current_function_decl))
12178 {
12179 const char * name;
12180
12181 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
12182 abort ();
12183 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
12184 abort ();
12185 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12186
12187 /* Generate code sequence to switch us into Thumb mode. */
12188 /* The .code 32 directive has already been emitted by
12189 ASM_DECLARE_FUNCTION_NAME. */
12190 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
12191 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
12192
12193 /* Generate a label, so that the debugger will notice the
12194 change in instruction sets. This label is also used by
12195 the assembler to bypass the ARM code when this function
12196 is called from a Thumb encoded function elsewhere in the
12197 same file. Hence the definition of STUB_NAME here must
12198 agree with the definition in gas/config/tc-arm.c */
12199
12200 #define STUB_NAME ".real_start_of"
12201
12202 fprintf (f, "\t.code\t16\n");
12203 #ifdef ARM_PE
12204 if (arm_dllexport_name_p (name))
12205 name = arm_strip_name_encoding (name);
12206 #endif
12207 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
12208 fprintf (f, "\t.thumb_func\n");
12209 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
12210 }
12211
12212 if (current_function_pretend_args_size)
12213 {
12214 if (cfun->machine->uses_anonymous_args)
12215 {
12216 int num_pushes;
12217
12218 fprintf (f, "\tpush\t{");
12219
12220 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
12221
12222 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
12223 regno <= LAST_ARG_REGNUM;
12224 regno++)
12225 asm_fprintf (f, "%r%s", regno,
12226 regno == LAST_ARG_REGNUM ? "" : ", ");
12227
12228 fprintf (f, "}\n");
12229 }
12230 else
12231 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
12232 SP_REGNUM, SP_REGNUM,
12233 current_function_pretend_args_size);
12234 }
12235
12236 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12237 if (THUMB_REG_PUSHED_P (regno))
12238 live_regs_mask |= 1 << regno;
12239
12240 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
12241 live_regs_mask |= 1 << LR_REGNUM;
12242
12243 if (TARGET_BACKTRACE)
12244 {
12245 int offset;
12246 int work_register = 0;
12247 int wr;
12248
12249 /* We have been asked to create a stack backtrace structure.
12250 The code looks like this:
12251
12252 0 .align 2
12253 0 func:
12254 0 sub SP, #16 Reserve space for 4 registers.
12255 2 push {R7} Get a work register.
12256 4 add R7, SP, #20 Get the stack pointer before the push.
12257 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12258 8 mov R7, PC Get hold of the start of this code plus 12.
12259 10 str R7, [SP, #16] Store it.
12260 12 mov R7, FP Get hold of the current frame pointer.
12261 14 str R7, [SP, #4] Store it.
12262 16 mov R7, LR Get hold of the current return address.
12263 18 str R7, [SP, #12] Store it.
12264 20 add R7, SP, #16 Point at the start of the backtrace structure.
12265 22 mov FP, R7 Put this value into the frame pointer. */
12266
12267 if ((live_regs_mask & 0xFF) == 0)
12268 {
12269 /* See if the a4 register is free. */
12270
12271 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
12272 work_register = LAST_ARG_REGNUM;
12273 else /* We must push a register of our own */
12274 live_regs_mask |= (1 << LAST_LO_REGNUM);
12275 }
12276
12277 if (work_register == 0)
12278 {
12279 /* Select a register from the list that will be pushed to
12280 use as our work register. */
12281 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
12282 if ((1 << work_register) & live_regs_mask)
12283 break;
12284 }
12285
12286 asm_fprintf
12287 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12288 SP_REGNUM, SP_REGNUM);
12289
12290 if (live_regs_mask)
12291 thumb_pushpop (f, live_regs_mask, 1);
12292
12293 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
12294 if (wr & live_regs_mask)
12295 offset += 4;
12296
12297 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12298 offset + 16 + current_function_pretend_args_size);
12299
12300 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12301 offset + 4);
12302
12303 /* Make sure that the instruction fetching the PC is in the right place
12304 to calculate "start of backtrace creation code + 12". */
12305 if (live_regs_mask)
12306 {
12307 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12308 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12309 offset + 12);
12310 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12311 ARM_HARD_FRAME_POINTER_REGNUM);
12312 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12313 offset);
12314 }
12315 else
12316 {
12317 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12318 ARM_HARD_FRAME_POINTER_REGNUM);
12319 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12320 offset);
12321 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12322 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12323 offset + 12);
12324 }
12325
12326 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
12327 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12328 offset + 8);
12329 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12330 offset + 12);
12331 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12332 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
12333 }
12334 else if (live_regs_mask)
12335 thumb_pushpop (f, live_regs_mask, 1);
12336
12337 for (regno = 8; regno < 13; regno++)
12338 if (THUMB_REG_PUSHED_P (regno))
12339 high_regs_pushed++;
12340
12341 if (high_regs_pushed)
12342 {
12343 int pushable_regs = 0;
12344 int mask = live_regs_mask & 0xff;
12345 int next_hi_reg;
12346
12347 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
12348 if (THUMB_REG_PUSHED_P (next_hi_reg))
12349 break;
12350
12351 pushable_regs = mask;
12352
12353 if (pushable_regs == 0)
12354 {
12355 /* Desperation time -- this probably will never happen. */
12356 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
12357 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
12358 mask = 1 << LAST_ARG_REGNUM;
12359 }
12360
12361 while (high_regs_pushed > 0)
12362 {
12363 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
12364 {
12365 if (mask & (1 << regno))
12366 {
12367 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
12368
12369 high_regs_pushed--;
12370
12371 if (high_regs_pushed)
12372 {
12373 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
12374 next_hi_reg--)
12375 if (THUMB_REG_PUSHED_P (next_hi_reg))
12376 break;
12377 }
12378 else
12379 {
12380 mask &= ~((1 << regno) - 1);
12381 break;
12382 }
12383 }
12384 }
12385
12386 thumb_pushpop (f, mask, 1);
12387 }
12388
12389 if (pushable_regs == 0
12390 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
12391 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12392 }
12393 }
12394
12395 /* Handle the case of a double word load into a low register from
12396 a computed memory address. The computed address may involve a
12397 register which is overwritten by the load. */
12398 const char *
12399 thumb_load_double_from_address (rtx *operands)
12400 {
12401 rtx addr;
12402 rtx base;
12403 rtx offset;
12404 rtx arg1;
12405 rtx arg2;
12406
12407 if (GET_CODE (operands[0]) != REG)
12408 abort ();
12409
12410 if (GET_CODE (operands[1]) != MEM)
12411 abort ();
12412
12413 /* Get the memory address. */
12414 addr = XEXP (operands[1], 0);
12415
12416 /* Work out how the memory address is computed. */
12417 switch (GET_CODE (addr))
12418 {
12419 case REG:
12420 operands[2] = gen_rtx (MEM, SImode,
12421 plus_constant (XEXP (operands[1], 0), 4));
12422
12423 if (REGNO (operands[0]) == REGNO (addr))
12424 {
12425 output_asm_insn ("ldr\t%H0, %2", operands);
12426 output_asm_insn ("ldr\t%0, %1", operands);
12427 }
12428 else
12429 {
12430 output_asm_insn ("ldr\t%0, %1", operands);
12431 output_asm_insn ("ldr\t%H0, %2", operands);
12432 }
12433 break;
12434
12435 case CONST:
12436 /* Compute <address> + 4 for the high order load. */
12437 operands[2] = gen_rtx (MEM, SImode,
12438 plus_constant (XEXP (operands[1], 0), 4));
12439
12440 output_asm_insn ("ldr\t%0, %1", operands);
12441 output_asm_insn ("ldr\t%H0, %2", operands);
12442 break;
12443
12444 case PLUS:
12445 arg1 = XEXP (addr, 0);
12446 arg2 = XEXP (addr, 1);
12447
12448 if (CONSTANT_P (arg1))
12449 base = arg2, offset = arg1;
12450 else
12451 base = arg1, offset = arg2;
12452
12453 if (GET_CODE (base) != REG)
12454 abort ();
12455
12456 /* Catch the case of <address> = <reg> + <reg> */
12457 if (GET_CODE (offset) == REG)
12458 {
12459 int reg_offset = REGNO (offset);
12460 int reg_base = REGNO (base);
12461 int reg_dest = REGNO (operands[0]);
12462
12463 /* Add the base and offset registers together into the
12464 higher destination register. */
12465 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
12466 reg_dest + 1, reg_base, reg_offset);
12467
12468 /* Load the lower destination register from the address in
12469 the higher destination register. */
12470 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
12471 reg_dest, reg_dest + 1);
12472
12473 /* Load the higher destination register from its own address
12474 plus 4. */
12475 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
12476 reg_dest + 1, reg_dest + 1);
12477 }
12478 else
12479 {
12480 /* Compute <address> + 4 for the high order load. */
12481 operands[2] = gen_rtx (MEM, SImode,
12482 plus_constant (XEXP (operands[1], 0), 4));
12483
12484 /* If the computed address is held in the low order register
12485 then load the high order register first, otherwise always
12486 load the low order register first. */
12487 if (REGNO (operands[0]) == REGNO (base))
12488 {
12489 output_asm_insn ("ldr\t%H0, %2", operands);
12490 output_asm_insn ("ldr\t%0, %1", operands);
12491 }
12492 else
12493 {
12494 output_asm_insn ("ldr\t%0, %1", operands);
12495 output_asm_insn ("ldr\t%H0, %2", operands);
12496 }
12497 }
12498 break;
12499
12500 case LABEL_REF:
12501 /* With no registers to worry about we can just load the value
12502 directly. */
12503 operands[2] = gen_rtx (MEM, SImode,
12504 plus_constant (XEXP (operands[1], 0), 4));
12505
12506 output_asm_insn ("ldr\t%H0, %2", operands);
12507 output_asm_insn ("ldr\t%0, %1", operands);
12508 break;
12509
12510 default:
12511 abort ();
12512 break;
12513 }
12514
12515 return "";
12516 }
12517
12518 const char *
12519 thumb_output_move_mem_multiple (int n, rtx *operands)
12520 {
12521 rtx tmp;
12522
12523 switch (n)
12524 {
12525 case 2:
12526 if (REGNO (operands[4]) > REGNO (operands[5]))
12527 {
12528 tmp = operands[4];
12529 operands[4] = operands[5];
12530 operands[5] = tmp;
12531 }
12532 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
12533 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
12534 break;
12535
12536 case 3:
12537 if (REGNO (operands[4]) > REGNO (operands[5]))
12538 {
12539 tmp = operands[4];
12540 operands[4] = operands[5];
12541 operands[5] = tmp;
12542 }
12543 if (REGNO (operands[5]) > REGNO (operands[6]))
12544 {
12545 tmp = operands[5];
12546 operands[5] = operands[6];
12547 operands[6] = tmp;
12548 }
12549 if (REGNO (operands[4]) > REGNO (operands[5]))
12550 {
12551 tmp = operands[4];
12552 operands[4] = operands[5];
12553 operands[5] = tmp;
12554 }
12555
12556 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
12557 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
12558 break;
12559
12560 default:
12561 abort ();
12562 }
12563
12564 return "";
12565 }
12566
12567 /* Routines for generating rtl. */
12568 void
12569 thumb_expand_movstrqi (rtx *operands)
12570 {
12571 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
12572 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
12573 HOST_WIDE_INT len = INTVAL (operands[2]);
12574 HOST_WIDE_INT offset = 0;
12575
12576 while (len >= 12)
12577 {
12578 emit_insn (gen_movmem12b (out, in, out, in));
12579 len -= 12;
12580 }
12581
12582 if (len >= 8)
12583 {
12584 emit_insn (gen_movmem8b (out, in, out, in));
12585 len -= 8;
12586 }
12587
12588 if (len >= 4)
12589 {
12590 rtx reg = gen_reg_rtx (SImode);
12591 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
12592 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
12593 len -= 4;
12594 offset += 4;
12595 }
12596
12597 if (len >= 2)
12598 {
12599 rtx reg = gen_reg_rtx (HImode);
12600 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
12601 plus_constant (in, offset))));
12602 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
12603 reg));
12604 len -= 2;
12605 offset += 2;
12606 }
12607
12608 if (len)
12609 {
12610 rtx reg = gen_reg_rtx (QImode);
12611 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
12612 plus_constant (in, offset))));
12613 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
12614 reg));
12615 }
12616 }
12617
12618 int
12619 thumb_cmp_operand (rtx op, enum machine_mode mode)
12620 {
12621 return ((GET_CODE (op) == CONST_INT
12622 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
12623 || s_register_operand (op, mode));
12624 }
12625
12626 /* Return TRUE if a result can be stored in OP without clobbering the
12627 condition code register. Prior to reload we only accept a
12628 register. After reload we have to be able to handle memory as
12629 well, since a pseudo may not get a hard reg and reload cannot
12630 handle output-reloads on jump insns.
12631
12632 We could possibly handle mem before reload as well, but that might
12633 complicate things with the need to handle increment
12634 side-effects. */
12635
12636 int
12637 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
12638 {
12639 return (s_register_operand (op, mode)
12640 || ((reload_in_progress || reload_completed)
12641 && memory_operand (op, mode)));
12642 }
12643
12644 /* Handle storing a half-word to memory during reload. */
12645 void
12646 thumb_reload_out_hi (rtx *operands)
12647 {
12648 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
12649 }
12650
12651 /* Handle reading a half-word from memory during reload. */
12652 void
12653 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
12654 {
12655 abort ();
12656 }
12657
12658 /* Return the length of a function name prefix
12659 that starts with the character 'c'. */
12660 static int
12661 arm_get_strip_length (int c)
12662 {
12663 switch (c)
12664 {
12665 ARM_NAME_ENCODING_LENGTHS
12666 default: return 0;
12667 }
12668 }
12669
12670 /* Return a pointer to a function's name with any
12671 and all prefix encodings stripped from it. */
12672 const char *
12673 arm_strip_name_encoding (const char *name)
12674 {
12675 int skip;
12676
12677 while ((skip = arm_get_strip_length (* name)))
12678 name += skip;
12679
12680 return name;
12681 }
12682
12683 /* If there is a '*' anywhere in the name's prefix, then
12684 emit the stripped name verbatim, otherwise prepend an
12685 underscore if leading underscores are being used. */
12686 void
12687 arm_asm_output_labelref (FILE *stream, const char *name)
12688 {
12689 int skip;
12690 int verbatim = 0;
12691
12692 while ((skip = arm_get_strip_length (* name)))
12693 {
12694 verbatim |= (*name == '*');
12695 name += skip;
12696 }
12697
12698 if (verbatim)
12699 fputs (name, stream);
12700 else
12701 asm_fprintf (stream, "%U%s", name);
12702 }
12703
12704 rtx aof_pic_label;
12705
12706 #ifdef AOF_ASSEMBLER
12707 /* Special functions only needed when producing AOF syntax assembler. */
12708
12709 struct pic_chain
12710 {
12711 struct pic_chain * next;
12712 const char * symname;
12713 };
12714
12715 static struct pic_chain * aof_pic_chain = NULL;
12716
12717 rtx
12718 aof_pic_entry (rtx x)
12719 {
12720 struct pic_chain ** chainp;
12721 int offset;
12722
12723 if (aof_pic_label == NULL_RTX)
12724 {
12725 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
12726 }
12727
12728 for (offset = 0, chainp = &aof_pic_chain; *chainp;
12729 offset += 4, chainp = &(*chainp)->next)
12730 if ((*chainp)->symname == XSTR (x, 0))
12731 return plus_constant (aof_pic_label, offset);
12732
12733 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
12734 (*chainp)->next = NULL;
12735 (*chainp)->symname = XSTR (x, 0);
12736 return plus_constant (aof_pic_label, offset);
12737 }
12738
12739 void
12740 aof_dump_pic_table (FILE *f)
12741 {
12742 struct pic_chain * chain;
12743
12744 if (aof_pic_chain == NULL)
12745 return;
12746
12747 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
12748 PIC_OFFSET_TABLE_REGNUM,
12749 PIC_OFFSET_TABLE_REGNUM);
12750 fputs ("|x$adcons|\n", f);
12751
12752 for (chain = aof_pic_chain; chain; chain = chain->next)
12753 {
12754 fputs ("\tDCD\t", f);
12755 assemble_name (f, chain->symname);
12756 fputs ("\n", f);
12757 }
12758 }
12759
12760 int arm_text_section_count = 1;
12761
12762 char *
12763 aof_text_section (void )
12764 {
12765 static char buf[100];
12766 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
12767 arm_text_section_count++);
12768 if (flag_pic)
12769 strcat (buf, ", PIC, REENTRANT");
12770 return buf;
12771 }
12772
12773 static int arm_data_section_count = 1;
12774
12775 char *
12776 aof_data_section (void)
12777 {
12778 static char buf[100];
12779 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
12780 return buf;
12781 }
12782
12783 /* The AOF assembler is religiously strict about declarations of
12784 imported and exported symbols, so that it is impossible to declare
12785 a function as imported near the beginning of the file, and then to
12786 export it later on. It is, however, possible to delay the decision
12787 until all the functions in the file have been compiled. To get
12788 around this, we maintain a list of the imports and exports, and
12789 delete from it any that are subsequently defined. At the end of
12790 compilation we spit the remainder of the list out before the END
12791 directive. */
12792
12793 struct import
12794 {
12795 struct import * next;
12796 const char * name;
12797 };
12798
12799 static struct import * imports_list = NULL;
12800
12801 void
12802 aof_add_import (const char *name)
12803 {
12804 struct import * new;
12805
12806 for (new = imports_list; new; new = new->next)
12807 if (new->name == name)
12808 return;
12809
12810 new = (struct import *) xmalloc (sizeof (struct import));
12811 new->next = imports_list;
12812 imports_list = new;
12813 new->name = name;
12814 }
12815
12816 void
12817 aof_delete_import (const char *name)
12818 {
12819 struct import ** old;
12820
12821 for (old = &imports_list; *old; old = & (*old)->next)
12822 {
12823 if ((*old)->name == name)
12824 {
12825 *old = (*old)->next;
12826 return;
12827 }
12828 }
12829 }
12830
12831 int arm_main_function = 0;
12832
12833 static void
12834 aof_dump_imports (FILE *f)
12835 {
12836 /* The AOF assembler needs this to cause the startup code to be extracted
12837 from the library. Brining in __main causes the whole thing to work
12838 automagically. */
12839 if (arm_main_function)
12840 {
12841 text_section ();
12842 fputs ("\tIMPORT __main\n", f);
12843 fputs ("\tDCD __main\n", f);
12844 }
12845
12846 /* Now dump the remaining imports. */
12847 while (imports_list)
12848 {
12849 fprintf (f, "\tIMPORT\t");
12850 assemble_name (f, imports_list->name);
12851 fputc ('\n', f);
12852 imports_list = imports_list->next;
12853 }
12854 }
12855
12856 static void
12857 aof_globalize_label (FILE *stream, const char *name)
12858 {
12859 default_globalize_label (stream, name);
12860 if (! strcmp (name, "main"))
12861 arm_main_function = 1;
12862 }
12863
12864 static void
12865 aof_file_start ()
12866 {
12867 fputs ("__r0\tRN\t0\n", asm_out_file);
12868 fputs ("__a1\tRN\t0\n", asm_out_file);
12869 fputs ("__a2\tRN\t1\n", asm_out_file);
12870 fputs ("__a3\tRN\t2\n", asm_out_file);
12871 fputs ("__a4\tRN\t3\n", asm_out_file);
12872 fputs ("__v1\tRN\t4\n", asm_out_file);
12873 fputs ("__v2\tRN\t5\n", asm_out_file);
12874 fputs ("__v3\tRN\t6\n", asm_out_file);
12875 fputs ("__v4\tRN\t7\n", asm_out_file);
12876 fputs ("__v5\tRN\t8\n", asm_out_file);
12877 fputs ("__v6\tRN\t9\n", asm_out_file);
12878 fputs ("__sl\tRN\t10\n", asm_out_file);
12879 fputs ("__fp\tRN\t11\n", asm_out_file);
12880 fputs ("__ip\tRN\t12\n", asm_out_file);
12881 fputs ("__sp\tRN\t13\n", asm_out_file);
12882 fputs ("__lr\tRN\t14\n", asm_out_file);
12883 fputs ("__pc\tRN\t15\n", asm_out_file);
12884 fputs ("__f0\tFN\t0\n", asm_out_file);
12885 fputs ("__f1\tFN\t1\n", asm_out_file);
12886 fputs ("__f2\tFN\t2\n", asm_out_file);
12887 fputs ("__f3\tFN\t3\n", asm_out_file);
12888 fputs ("__f4\tFN\t4\n", asm_out_file);
12889 fputs ("__f5\tFN\t5\n", asm_out_file);
12890 fputs ("__f6\tFN\t6\n", asm_out_file);
12891 fputs ("__f7\tFN\t7\n", asm_out_file);
12892 text_section ();
12893 }
12894
12895 static void
12896 aof_file_end (void)
12897 {
12898 if (flag_pic)
12899 aof_dump_pic_table (asm_out_file);
12900 aof_dump_imports (asm_out_file);
12901 fputs ("\tEND\n", asm_out_file);
12902 }
12903 #endif /* AOF_ASSEMBLER */
12904
12905 #ifdef OBJECT_FORMAT_ELF
12906 /* Switch to an arbitrary section NAME with attributes as specified
12907 by FLAGS. ALIGN specifies any known alignment requirements for
12908 the section; 0 if the default should be used.
12909
12910 Differs from the default elf version only in the prefix character
12911 used before the section type. */
12912
12913 static void
12914 arm_elf_asm_named_section (const char *name, unsigned int flags)
12915 {
12916 char flagchars[10], *f = flagchars;
12917
12918 if (! named_section_first_declaration (name))
12919 {
12920 fprintf (asm_out_file, "\t.section\t%s\n", name);
12921 return;
12922 }
12923
12924 if (!(flags & SECTION_DEBUG))
12925 *f++ = 'a';
12926 if (flags & SECTION_WRITE)
12927 *f++ = 'w';
12928 if (flags & SECTION_CODE)
12929 *f++ = 'x';
12930 if (flags & SECTION_SMALL)
12931 *f++ = 's';
12932 if (flags & SECTION_MERGE)
12933 *f++ = 'M';
12934 if (flags & SECTION_STRINGS)
12935 *f++ = 'S';
12936 if (flags & SECTION_TLS)
12937 *f++ = 'T';
12938 *f = '\0';
12939
12940 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
12941
12942 if (!(flags & SECTION_NOTYPE))
12943 {
12944 const char *type;
12945
12946 if (flags & SECTION_BSS)
12947 type = "nobits";
12948 else
12949 type = "progbits";
12950
12951 fprintf (asm_out_file, ",%%%s", type);
12952
12953 if (flags & SECTION_ENTSIZE)
12954 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
12955 }
12956
12957 putc ('\n', asm_out_file);
12958 }
12959 #endif
12960
12961 #ifndef ARM_PE
12962 /* Symbols in the text segment can be accessed without indirecting via the
12963 constant pool; it may take an extra binary operation, but this is still
12964 faster than indirecting via memory. Don't do this when not optimizing,
12965 since we won't be calculating al of the offsets necessary to do this
12966 simplification. */
12967
12968 static void
12969 arm_encode_section_info (tree decl, rtx rtl, int first)
12970 {
12971 /* This doesn't work with AOF syntax, since the string table may be in
12972 a different AREA. */
12973 #ifndef AOF_ASSEMBLER
12974 if (optimize > 0 && TREE_CONSTANT (decl)
12975 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
12976 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
12977 #endif
12978
12979 /* If we are referencing a function that is weak then encode a long call
12980 flag in the function name, otherwise if the function is static or
12981 or known to be defined in this file then encode a short call flag. */
12982 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
12983 {
12984 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
12985 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
12986 else if (! TREE_PUBLIC (decl))
12987 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
12988 }
12989 }
12990 #endif /* !ARM_PE */
12991
12992 static void
12993 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
12994 {
12995 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
12996 && !strcmp (prefix, "L"))
12997 {
12998 arm_ccfsm_state = 0;
12999 arm_target_insn = NULL;
13000 }
13001 default_internal_label (stream, prefix, labelno);
13002 }
13003
13004 /* Output code to add DELTA to the first argument, and then jump
13005 to FUNCTION. Used for C++ multiple inheritance. */
13006 static void
13007 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13008 HOST_WIDE_INT delta,
13009 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13010 tree function)
13011 {
13012 int mi_delta = delta;
13013 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13014 int shift = 0;
13015 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13016 ? 1 : 0);
13017 if (mi_delta < 0)
13018 mi_delta = - mi_delta;
13019 while (mi_delta != 0)
13020 {
13021 if ((mi_delta & (3 << shift)) == 0)
13022 shift += 2;
13023 else
13024 {
13025 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
13026 mi_op, this_regno, this_regno,
13027 mi_delta & (0xff << shift));
13028 mi_delta &= ~(0xff << shift);
13029 shift += 8;
13030 }
13031 }
13032 fputs ("\tb\t", file);
13033 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
13034 if (NEED_PLT_RELOC)
13035 fputs ("(PLT)", file);
13036 fputc ('\n', file);
13037 }
13038
13039 int
13040 arm_emit_vector_const (file, x)
13041 FILE * file;
13042 rtx x;
13043 {
13044 int i;
13045 const char * pattern;
13046
13047 if (GET_CODE (x) != CONST_VECTOR)
13048 abort ();
13049
13050 switch (GET_MODE (x))
13051 {
13052 case V2SImode: pattern = "%08x"; break;
13053 case V4HImode: pattern = "%04x"; break;
13054 case V8QImode: pattern = "%02x"; break;
13055 default: abort ();
13056 }
13057
13058 fprintf (file, "0x");
13059 for (i = CONST_VECTOR_NUNITS (x); i--;)
13060 {
13061 rtx element;
13062
13063 element = CONST_VECTOR_ELT (x, i);
13064 fprintf (file, pattern, INTVAL (element));
13065 }
13066
13067 return 1;
13068 }
13069
13070 const char *
13071 arm_output_load_gr (operands)
13072 rtx * operands;
13073 {
13074 rtx reg;
13075 rtx offset;
13076 rtx wcgr;
13077 rtx sum;
13078
13079 if (GET_CODE (operands [1]) != MEM
13080 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
13081 || GET_CODE (reg = XEXP (sum, 0)) != REG
13082 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
13083 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
13084 return "wldrw%?\t%0, %1";
13085
13086 /* Fix up an out-of-range load of a GR register. */
13087 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
13088 wcgr = operands[0];
13089 operands[0] = reg;
13090 output_asm_insn ("ldr%?\t%0, %1", operands);
13091
13092 operands[0] = wcgr;
13093 operands[1] = reg;
13094 output_asm_insn ("tmcr%?\t%0, %1", operands);
13095 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
13096
13097 return "";
13098 }
Mirror of the offical gcc git repository hosted at gcc.gnu.org