1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
36 (UNSPEC_UMK_LOAD_CIW 9)
44 (UNSPEC_TLSGD_CALL 15)
45 (UNSPEC_TLSLDM_CALL 16)
72 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
73 (UNSPECV_LONGJMP 3) ; builtin_longjmp
75 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
77 (UNSPECV_EHR 7) ; exception_receiver
81 (UNSPECV_PLDGP2 11) ; prologue ldgp
84 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
85 (UNSPECV_LL 15) ; load-locked
86 (UNSPECV_SC 16) ; store-conditional
89 ;; Where necessary, the suffixes _le and _be are used to distinguish between
90 ;; little-endian and big-endian patterns.
92 ;; Note that the Unicos/Mk assembler does not support the following
93 ;; opcodes: mov, fmov, nop, fnop, unop.
95 ;; Processor type -- this attribute must exactly match the processor_type
96 ;; enumeration in alpha.h.
98 (define_attr "tune" "ev4,ev5,ev6"
99 (const (symbol_ref "alpha_tune")))
101 ;; Define an insn type attribute. This is used in function unit delay
102 ;; computations, among other purposes. For the most part, we use the names
103 ;; defined in the EV4 documentation, but add a few that we have to know about
107 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
108 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
110 (const_string "iadd"))
112 ;; Describe a user's asm statement.
113 (define_asm_attributes
114 [(set_attr "type" "multi")])
116 ;; Define the operand size an insn operates on. Used primarily by mul
117 ;; and div operations that have size dependent timings.
119 (define_attr "opsize" "si,di,udi"
122 ;; The TRAP attribute marks instructions that may generate traps
123 ;; (which are imprecise and may need a trapb if software completion
126 (define_attr "trap" "no,yes"
129 ;; The ROUND_SUFFIX attribute marks which instructions require a
130 ;; rounding-mode suffix. The value NONE indicates no suffix,
131 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
133 (define_attr "round_suffix" "none,normal,c"
134 (const_string "none"))
136 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
138 ;; SU accepts only /su (cmpt et al)
139 ;; SUI accepts only /sui (cvtqt and cvtqs)
140 ;; V_SV accepts /v and /sv (cvtql only)
141 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
142 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
144 ;; The actual suffix emitted is controlled by alpha_fptm.
146 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
147 (const_string "none"))
149 ;; The length of an instruction sequence in bytes.
151 (define_attr "length" ""
154 ;; The USEGP attribute marks instructions that have relocations that use
157 (define_attr "usegp" "no,yes"
158 (cond [(eq_attr "type" "ldsym,jsr")
160 (eq_attr "type" "ild,fld,ist,fst")
161 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
163 (const_string "no")))
165 ;; The CANNOT_COPY attribute marks instructions with relocations that
166 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
167 ;; since they have to stay in 1-1 correspondence with one another. This
168 ;; also includes jsr insns, since they must stay in correspondence with
169 ;; the immediately following gpdisp instructions.
171 (define_attr "cannot_copy" "false,true"
172 (const_string "false"))
174 ;; Include scheduling descriptions.
181 ;; Include predicate definitions
183 (include "predicates.md")
186 ;; First define the arithmetic insns. Note that the 32-bit forms also
189 ;; Handle 32-64 bit extension from memory to a floating point register
190 ;; specially, since this occurs frequently in int->double conversions.
192 ;; Note that while we must retain the =f case in the insn for reload's
193 ;; benefit, it should be eliminated after reload, so we should never emit
194 ;; code for that case. But we don't reject the possibility.
196 (define_expand "extendsidi2"
197 [(set (match_operand:DI 0 "register_operand" "")
198 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
202 (define_insn "*cvtlq"
203 [(set (match_operand:DI 0 "register_operand" "=f")
204 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
208 [(set_attr "type" "fadd")])
210 (define_insn "*extendsidi2_1"
211 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
213 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
218 lds %0,%1\;cvtlq %0,%0"
219 [(set_attr "type" "iadd,ild,fld")
220 (set_attr "length" "*,*,8")])
223 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
224 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
226 [(set (match_dup 2) (match_dup 1))
227 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
229 operands[1] = adjust_address (operands[1], SFmode, 0);
230 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
233 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
234 ;; reload when converting fp->int.
237 [(set (match_operand:SI 0 "hard_int_register_operand" "")
238 (match_operand:SI 1 "memory_operand" ""))
239 (set (match_operand:DI 2 "hard_int_register_operand" "")
240 (sign_extend:DI (match_dup 0)))]
241 "true_regnum (operands[0]) == true_regnum (operands[2])
242 || peep2_reg_dead_p (2, operands[0])"
244 (sign_extend:DI (match_dup 1)))]
247 ;; Don't say we have addsi3 if optimizing. This generates better code. We
248 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
249 (define_expand "addsi3"
250 [(set (match_operand:SI 0 "register_operand" "")
251 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
252 (match_operand:SI 2 "add_operand" "")))]
256 (define_insn "*addsi_internal"
257 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
258 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
259 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
268 [(set (match_operand:SI 0 "register_operand" "")
269 (plus:SI (match_operand:SI 1 "register_operand" "")
270 (match_operand:SI 2 "const_int_operand" "")))]
271 "! add_operand (operands[2], SImode)"
272 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
273 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
275 HOST_WIDE_INT val = INTVAL (operands[2]);
276 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
277 HOST_WIDE_INT rest = val - low;
279 operands[3] = GEN_INT (rest);
280 operands[4] = GEN_INT (low);
283 (define_insn "*addsi_se"
284 [(set (match_operand:DI 0 "register_operand" "=r,r")
286 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
287 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
293 (define_insn "*addsi_se2"
294 [(set (match_operand:DI 0 "register_operand" "=r,r")
296 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
297 (match_operand:DI 2 "sext_add_operand" "rI,O"))
305 [(set (match_operand:DI 0 "register_operand" "")
307 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
308 (match_operand:SI 2 "const_int_operand" ""))))
309 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
310 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
311 && INTVAL (operands[2]) % 4 == 0"
312 [(set (match_dup 3) (match_dup 4))
313 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
317 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
323 operands[4] = GEN_INT (val);
324 operands[5] = GEN_INT (mult);
328 [(set (match_operand:DI 0 "register_operand" "")
330 (plus:SI (match_operator:SI 1 "comparison_operator"
331 [(match_operand 2 "" "")
332 (match_operand 3 "" "")])
333 (match_operand:SI 4 "add_operand" ""))))
334 (clobber (match_operand:DI 5 "register_operand" ""))]
336 [(set (match_dup 5) (match_dup 6))
337 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
339 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
340 operands[2], operands[3]);
341 operands[7] = gen_lowpart (SImode, operands[5]);
344 (define_insn "addvsi3"
345 [(set (match_operand:SI 0 "register_operand" "=r,r")
346 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
347 (match_operand:SI 2 "sext_add_operand" "rI,O")))
348 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
349 (sign_extend:DI (match_dup 2)))
350 (sign_extend:DI (plus:SI (match_dup 1)
358 (define_expand "adddi3"
359 [(set (match_operand:DI 0 "register_operand" "")
360 (plus:DI (match_operand:DI 1 "register_operand" "")
361 (match_operand:DI 2 "add_operand" "")))]
365 (define_insn "*adddi_er_lo16_dtp"
366 [(set (match_operand:DI 0 "register_operand" "=r")
367 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
368 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
370 "lda %0,%2(%1)\t\t!dtprel")
372 (define_insn "*adddi_er_hi32_dtp"
373 [(set (match_operand:DI 0 "register_operand" "=r")
374 (plus:DI (match_operand:DI 1 "register_operand" "r")
375 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
377 "ldah %0,%2(%1)\t\t!dtprelhi")
379 (define_insn "*adddi_er_lo32_dtp"
380 [(set (match_operand:DI 0 "register_operand" "=r")
381 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
382 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
384 "lda %0,%2(%1)\t\t!dtprello")
386 (define_insn "*adddi_er_lo16_tp"
387 [(set (match_operand:DI 0 "register_operand" "=r")
388 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
389 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
391 "lda %0,%2(%1)\t\t!tprel")
393 (define_insn "*adddi_er_hi32_tp"
394 [(set (match_operand:DI 0 "register_operand" "=r")
395 (plus:DI (match_operand:DI 1 "register_operand" "r")
396 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
398 "ldah %0,%2(%1)\t\t!tprelhi")
400 (define_insn "*adddi_er_lo32_tp"
401 [(set (match_operand:DI 0 "register_operand" "=r")
402 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
403 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
405 "lda %0,%2(%1)\t\t!tprello")
407 (define_insn "*adddi_er_high_l"
408 [(set (match_operand:DI 0 "register_operand" "=r")
409 (plus:DI (match_operand:DI 1 "register_operand" "r")
410 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
411 "TARGET_EXPLICIT_RELOCS && reload_completed"
412 "ldah %0,%2(%1)\t\t!gprelhigh"
413 [(set_attr "usegp" "yes")])
416 [(set (match_operand:DI 0 "register_operand" "")
417 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
418 "TARGET_EXPLICIT_RELOCS && reload_completed"
420 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
421 "operands[2] = pic_offset_table_rtx;")
423 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
424 ;; With complications like
426 ;; The NT stack unwind code can't handle a subq to adjust the stack
427 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
428 ;; the exception handling code will loop if a subq is used and an
431 ;; The 19980616 change to emit prologues as RTL also confused some
432 ;; versions of GDB, which also interprets prologues. This has been
433 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
436 ;; and the fact that the three insns schedule exactly the same, it's
437 ;; just not worth the effort.
439 (define_insn "*adddi_internal"
440 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
441 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
442 (match_operand:DI 2 "add_operand" "r,K,L")))]
449 ;; ??? Allow large constants when basing off the frame pointer or some
450 ;; virtual register that may eliminate to the frame pointer. This is
451 ;; done because register elimination offsets will change the hi/lo split,
452 ;; and if we split before reload, we will require additional instructions.
454 (define_insn "*adddi_fp_hack"
455 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
456 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
457 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
458 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
459 && INTVAL (operands[2]) >= 0
460 /* This is the largest constant an lda+ldah pair can add, minus
461 an upper bound on the displacement between SP and AP during
462 register elimination. See INITIAL_ELIMINATION_OFFSET. */
463 && INTVAL (operands[2])
465 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
466 - ALPHA_ROUND(current_function_outgoing_args_size)
467 - (ALPHA_ROUND (get_frame_size ()
468 + max_reg_num () * UNITS_PER_WORD
469 + current_function_pretend_args_size)
470 - current_function_pretend_args_size))"
476 ;; Don't do this if we are adjusting SP since we don't want to do it
477 ;; in two steps. Don't split FP sources for the reason listed above.
479 [(set (match_operand:DI 0 "register_operand" "")
480 (plus:DI (match_operand:DI 1 "register_operand" "")
481 (match_operand:DI 2 "const_int_operand" "")))]
482 "! add_operand (operands[2], DImode)
483 && operands[0] != stack_pointer_rtx
484 && operands[1] != frame_pointer_rtx
485 && operands[1] != arg_pointer_rtx"
486 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
487 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
489 HOST_WIDE_INT val = INTVAL (operands[2]);
490 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
491 HOST_WIDE_INT rest = val - low;
493 operands[4] = GEN_INT (low);
494 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
495 operands[3] = GEN_INT (rest);
496 else if (! no_new_pseudos)
498 operands[3] = gen_reg_rtx (DImode);
499 emit_move_insn (operands[3], operands[2]);
500 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
507 (define_insn "*saddl"
508 [(set (match_operand:SI 0 "register_operand" "=r,r")
509 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
510 (match_operand:SI 2 "const48_operand" "I,I"))
511 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
517 (define_insn "*saddl_se"
518 [(set (match_operand:DI 0 "register_operand" "=r,r")
520 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
521 (match_operand:SI 2 "const48_operand" "I,I"))
522 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
529 [(set (match_operand:DI 0 "register_operand" "")
531 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
532 [(match_operand 2 "" "")
533 (match_operand 3 "" "")])
534 (match_operand:SI 4 "const48_operand" ""))
535 (match_operand:SI 5 "sext_add_operand" ""))))
536 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
538 [(set (match_dup 6) (match_dup 7))
540 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
543 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
544 operands[2], operands[3]);
545 operands[8] = gen_lowpart (SImode, operands[6]);
548 (define_insn "*saddq"
549 [(set (match_operand:DI 0 "register_operand" "=r,r")
550 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
551 (match_operand:DI 2 "const48_operand" "I,I"))
552 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
558 (define_insn "addvdi3"
559 [(set (match_operand:DI 0 "register_operand" "=r,r")
560 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
561 (match_operand:DI 2 "sext_add_operand" "rI,O")))
562 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
563 (sign_extend:TI (match_dup 2)))
564 (sign_extend:TI (plus:DI (match_dup 1)
572 (define_insn "negsi2"
573 [(set (match_operand:SI 0 "register_operand" "=r")
574 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
578 (define_insn "*negsi_se"
579 [(set (match_operand:DI 0 "register_operand" "=r")
580 (sign_extend:DI (neg:SI
581 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
585 (define_insn "negvsi2"
586 [(set (match_operand:SI 0 "register_operand" "=r")
587 (neg:SI (match_operand:SI 1 "register_operand" "r")))
588 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
589 (sign_extend:DI (neg:SI (match_dup 1))))
594 (define_insn "negdi2"
595 [(set (match_operand:DI 0 "register_operand" "=r")
596 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
600 (define_insn "negvdi2"
601 [(set (match_operand:DI 0 "register_operand" "=r")
602 (neg:DI (match_operand:DI 1 "register_operand" "r")))
603 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
604 (sign_extend:TI (neg:DI (match_dup 1))))
609 (define_expand "subsi3"
610 [(set (match_operand:SI 0 "register_operand" "")
611 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
612 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
616 (define_insn "*subsi_internal"
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
619 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
623 (define_insn "*subsi_se"
624 [(set (match_operand:DI 0 "register_operand" "=r")
625 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
626 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
630 (define_insn "*subsi_se2"
631 [(set (match_operand:DI 0 "register_operand" "=r")
633 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
634 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
639 (define_insn "subvsi3"
640 [(set (match_operand:SI 0 "register_operand" "=r")
641 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
642 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
643 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
644 (sign_extend:DI (match_dup 2)))
645 (sign_extend:DI (minus:SI (match_dup 1)
651 (define_insn "subdi3"
652 [(set (match_operand:DI 0 "register_operand" "=r")
653 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
654 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
658 (define_insn "*ssubl"
659 [(set (match_operand:SI 0 "register_operand" "=r")
660 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
661 (match_operand:SI 2 "const48_operand" "I"))
662 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
666 (define_insn "*ssubl_se"
667 [(set (match_operand:DI 0 "register_operand" "=r")
669 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
670 (match_operand:SI 2 "const48_operand" "I"))
671 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
675 (define_insn "*ssubq"
676 [(set (match_operand:DI 0 "register_operand" "=r")
677 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
678 (match_operand:DI 2 "const48_operand" "I"))
679 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
683 (define_insn "subvdi3"
684 [(set (match_operand:DI 0 "register_operand" "=r")
685 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
686 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
687 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
688 (sign_extend:TI (match_dup 2)))
689 (sign_extend:TI (minus:DI (match_dup 1)
695 ;; The Unicos/Mk assembler doesn't support mull.
697 (define_insn "mulsi3"
698 [(set (match_operand:SI 0 "register_operand" "=r")
699 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
700 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
701 "!TARGET_ABI_UNICOSMK"
703 [(set_attr "type" "imul")
704 (set_attr "opsize" "si")])
706 (define_insn "*mulsi_se"
707 [(set (match_operand:DI 0 "register_operand" "=r")
709 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
710 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
711 "!TARGET_ABI_UNICOSMK"
713 [(set_attr "type" "imul")
714 (set_attr "opsize" "si")])
716 (define_insn "mulvsi3"
717 [(set (match_operand:SI 0 "register_operand" "=r")
718 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
719 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
720 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
721 (sign_extend:DI (match_dup 2)))
722 (sign_extend:DI (mult:SI (match_dup 1)
725 "!TARGET_ABI_UNICOSMK"
727 [(set_attr "type" "imul")
728 (set_attr "opsize" "si")])
730 (define_insn "muldi3"
731 [(set (match_operand:DI 0 "register_operand" "=r")
732 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
733 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
736 [(set_attr "type" "imul")])
738 (define_insn "mulvdi3"
739 [(set (match_operand:DI 0 "register_operand" "=r")
740 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
741 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
742 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
743 (sign_extend:TI (match_dup 2)))
744 (sign_extend:TI (mult:DI (match_dup 1)
749 [(set_attr "type" "imul")])
751 (define_expand "umuldi3_highpart"
752 [(set (match_operand:DI 0 "register_operand" "")
755 (mult:TI (zero_extend:TI
756 (match_operand:DI 1 "register_operand" ""))
757 (match_operand:DI 2 "reg_or_8bit_operand" ""))
761 if (REG_P (operands[2]))
762 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
765 (define_insn "*umuldi3_highpart_reg"
766 [(set (match_operand:DI 0 "register_operand" "=r")
769 (mult:TI (zero_extend:TI
770 (match_operand:DI 1 "register_operand" "r"))
772 (match_operand:DI 2 "register_operand" "r")))
776 [(set_attr "type" "imul")
777 (set_attr "opsize" "udi")])
779 (define_insn "*umuldi3_highpart_const"
780 [(set (match_operand:DI 0 "register_operand" "=r")
783 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
784 (match_operand:TI 2 "cint8_operand" "I"))
788 [(set_attr "type" "imul")
789 (set_attr "opsize" "udi")])
791 ;; The divide and remainder operations take their inputs from r24 and
792 ;; r25, put their output in r27, and clobber r23 and r28 on all
793 ;; systems except Unicos/Mk. On Unicos, the standard library provides
794 ;; subroutines which use the standard calling convention and work on
797 ;; ??? Force sign-extension here because some versions of OSF/1 and
798 ;; Interix/NT don't do the right thing if the inputs are not properly
799 ;; sign-extended. But Linux, for instance, does not have this
800 ;; problem. Is it worth the complication here to eliminate the sign
803 (define_expand "divsi3"
805 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
807 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
808 (parallel [(set (match_dup 5)
809 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
810 (clobber (reg:DI 23))
811 (clobber (reg:DI 28))])
812 (set (match_operand:SI 0 "nonimmediate_operand" "")
813 (subreg:SI (match_dup 5) 0))]
814 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
816 operands[3] = gen_reg_rtx (DImode);
817 operands[4] = gen_reg_rtx (DImode);
818 operands[5] = gen_reg_rtx (DImode);
821 (define_expand "udivsi3"
823 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
825 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
826 (parallel [(set (match_dup 5)
827 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
828 (clobber (reg:DI 23))
829 (clobber (reg:DI 28))])
830 (set (match_operand:SI 0 "nonimmediate_operand" "")
831 (subreg:SI (match_dup 5) 0))]
832 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
834 operands[3] = gen_reg_rtx (DImode);
835 operands[4] = gen_reg_rtx (DImode);
836 operands[5] = gen_reg_rtx (DImode);
839 (define_expand "modsi3"
841 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
843 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
844 (parallel [(set (match_dup 5)
845 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
846 (clobber (reg:DI 23))
847 (clobber (reg:DI 28))])
848 (set (match_operand:SI 0 "nonimmediate_operand" "")
849 (subreg:SI (match_dup 5) 0))]
850 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
852 operands[3] = gen_reg_rtx (DImode);
853 operands[4] = gen_reg_rtx (DImode);
854 operands[5] = gen_reg_rtx (DImode);
857 (define_expand "umodsi3"
859 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
861 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
862 (parallel [(set (match_dup 5)
863 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
864 (clobber (reg:DI 23))
865 (clobber (reg:DI 28))])
866 (set (match_operand:SI 0 "nonimmediate_operand" "")
867 (subreg:SI (match_dup 5) 0))]
868 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
870 operands[3] = gen_reg_rtx (DImode);
871 operands[4] = gen_reg_rtx (DImode);
872 operands[5] = gen_reg_rtx (DImode);
875 (define_expand "divdi3"
876 [(parallel [(set (match_operand:DI 0 "register_operand" "")
877 (div:DI (match_operand:DI 1 "register_operand" "")
878 (match_operand:DI 2 "register_operand" "")))
879 (clobber (reg:DI 23))
880 (clobber (reg:DI 28))])]
881 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
884 (define_expand "udivdi3"
885 [(parallel [(set (match_operand:DI 0 "register_operand" "")
886 (udiv:DI (match_operand:DI 1 "register_operand" "")
887 (match_operand:DI 2 "register_operand" "")))
888 (clobber (reg:DI 23))
889 (clobber (reg:DI 28))])]
890 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
893 (define_expand "moddi3"
894 [(use (match_operand:DI 0 "register_operand" ""))
895 (use (match_operand:DI 1 "register_operand" ""))
896 (use (match_operand:DI 2 "register_operand" ""))]
897 "!TARGET_ABI_OPEN_VMS"
899 if (TARGET_ABI_UNICOSMK)
900 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
902 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
906 (define_expand "moddi3_dft"
907 [(parallel [(set (match_operand:DI 0 "register_operand" "")
908 (mod:DI (match_operand:DI 1 "register_operand" "")
909 (match_operand:DI 2 "register_operand" "")))
910 (clobber (reg:DI 23))
911 (clobber (reg:DI 28))])]
912 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
915 ;; On Unicos/Mk, we do as the system's C compiler does:
916 ;; compute the quotient, multiply and subtract.
918 (define_expand "moddi3_umk"
919 [(use (match_operand:DI 0 "register_operand" ""))
920 (use (match_operand:DI 1 "register_operand" ""))
921 (use (match_operand:DI 2 "register_operand" ""))]
922 "TARGET_ABI_UNICOSMK"
924 rtx div, mul = gen_reg_rtx (DImode);
926 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
927 NULL_RTX, 0, OPTAB_LIB);
928 div = force_reg (DImode, div);
929 emit_insn (gen_muldi3 (mul, operands[2], div));
930 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
934 (define_expand "umoddi3"
935 [(use (match_operand:DI 0 "register_operand" ""))
936 (use (match_operand:DI 1 "register_operand" ""))
937 (use (match_operand:DI 2 "register_operand" ""))]
938 "! TARGET_ABI_OPEN_VMS"
940 if (TARGET_ABI_UNICOSMK)
941 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
943 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
947 (define_expand "umoddi3_dft"
948 [(parallel [(set (match_operand:DI 0 "register_operand" "")
949 (umod:DI (match_operand:DI 1 "register_operand" "")
950 (match_operand:DI 2 "register_operand" "")))
951 (clobber (reg:DI 23))
952 (clobber (reg:DI 28))])]
953 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
956 (define_expand "umoddi3_umk"
957 [(use (match_operand:DI 0 "register_operand" ""))
958 (use (match_operand:DI 1 "register_operand" ""))
959 (use (match_operand:DI 2 "register_operand" ""))]
960 "TARGET_ABI_UNICOSMK"
962 rtx div, mul = gen_reg_rtx (DImode);
964 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
965 NULL_RTX, 1, OPTAB_LIB);
966 div = force_reg (DImode, div);
967 emit_insn (gen_muldi3 (mul, operands[2], div));
968 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
972 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
973 ;; expanded by the assembler.
975 (define_insn_and_split "*divmodsi_internal_er"
976 [(set (match_operand:DI 0 "register_operand" "=c")
977 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
978 [(match_operand:DI 1 "register_operand" "a")
979 (match_operand:DI 2 "register_operand" "b")])))
980 (clobber (reg:DI 23))
981 (clobber (reg:DI 28))]
982 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
984 "&& reload_completed"
985 [(parallel [(set (match_dup 0)
986 (sign_extend:DI (match_dup 3)))
989 (clobber (reg:DI 23))
990 (clobber (reg:DI 28))])]
993 switch (GET_CODE (operands[3]))
1010 operands[4] = GEN_INT (alpha_next_sequence_number++);
1011 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1012 gen_rtx_SYMBOL_REF (DImode, str),
1015 [(set_attr "type" "jsr")
1016 (set_attr "length" "8")])
1018 (define_insn "*divmodsi_internal_er_1"
1019 [(set (match_operand:DI 0 "register_operand" "=c")
1020 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1021 [(match_operand:DI 1 "register_operand" "a")
1022 (match_operand:DI 2 "register_operand" "b")])))
1023 (use (match_operand:DI 4 "register_operand" "c"))
1024 (use (match_operand 5 "const_int_operand" ""))
1025 (clobber (reg:DI 23))
1026 (clobber (reg:DI 28))]
1027 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1028 "jsr $23,($27),__%E3%j5"
1029 [(set_attr "type" "jsr")
1030 (set_attr "length" "4")])
1032 (define_insn "*divmodsi_internal"
1033 [(set (match_operand:DI 0 "register_operand" "=c")
1034 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1035 [(match_operand:DI 1 "register_operand" "a")
1036 (match_operand:DI 2 "register_operand" "b")])))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))]
1039 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1041 [(set_attr "type" "jsr")
1042 (set_attr "length" "8")])
1044 (define_insn_and_split "*divmoddi_internal_er"
1045 [(set (match_operand:DI 0 "register_operand" "=c")
1046 (match_operator:DI 3 "divmod_operator"
1047 [(match_operand:DI 1 "register_operand" "a")
1048 (match_operand:DI 2 "register_operand" "b")]))
1049 (clobber (reg:DI 23))
1050 (clobber (reg:DI 28))]
1051 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1053 "&& reload_completed"
1054 [(parallel [(set (match_dup 0) (match_dup 3))
1057 (clobber (reg:DI 23))
1058 (clobber (reg:DI 28))])]
1061 switch (GET_CODE (operands[3]))
1078 operands[4] = GEN_INT (alpha_next_sequence_number++);
1079 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1080 gen_rtx_SYMBOL_REF (DImode, str),
1083 [(set_attr "type" "jsr")
1084 (set_attr "length" "8")])
1086 (define_insn "*divmoddi_internal_er_1"
1087 [(set (match_operand:DI 0 "register_operand" "=c")
1088 (match_operator:DI 3 "divmod_operator"
1089 [(match_operand:DI 1 "register_operand" "a")
1090 (match_operand:DI 2 "register_operand" "b")]))
1091 (use (match_operand:DI 4 "register_operand" "c"))
1092 (use (match_operand 5 "const_int_operand" ""))
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))]
1095 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1096 "jsr $23,($27),__%E3%j5"
1097 [(set_attr "type" "jsr")
1098 (set_attr "length" "4")])
1100 (define_insn "*divmoddi_internal"
1101 [(set (match_operand:DI 0 "register_operand" "=c")
1102 (match_operator:DI 3 "divmod_operator"
1103 [(match_operand:DI 1 "register_operand" "a")
1104 (match_operand:DI 2 "register_operand" "b")]))
1105 (clobber (reg:DI 23))
1106 (clobber (reg:DI 28))]
1107 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1109 [(set_attr "type" "jsr")
1110 (set_attr "length" "8")])
1112 ;; Next are the basic logical operations. We only expose the DImode operations
1113 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1114 ;; the atomic operation splitters.
1116 (define_insn "*andsi_internal"
1117 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1118 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1119 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1125 [(set_attr "type" "ilog,ilog,shift")])
1127 (define_insn "anddi3"
1128 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1129 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1130 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1136 [(set_attr "type" "ilog,ilog,shift")])
1138 ;; There are times when we can split an AND into two AND insns. This occurs
1139 ;; when we can first clear any bytes and then clear anything else. For
1140 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1141 ;; Only do this when running on 64-bit host since the computations are
1142 ;; too messy otherwise.
1145 [(set (match_operand:DI 0 "register_operand" "")
1146 (and:DI (match_operand:DI 1 "register_operand" "")
1147 (match_operand:DI 2 "const_int_operand" "")))]
1148 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1149 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1150 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1152 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1153 unsigned HOST_WIDE_INT mask2 = mask1;
1156 /* For each byte that isn't all zeros, make it all ones. */
1157 for (i = 0; i < 64; i += 8)
1158 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1159 mask1 |= (HOST_WIDE_INT) 0xff << i;
1161 /* Now turn on any bits we've just turned off. */
1164 operands[3] = GEN_INT (mask1);
1165 operands[4] = GEN_INT (mask2);
1168 (define_expand "zero_extendqihi2"
1169 [(set (match_operand:HI 0 "register_operand" "")
1170 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1174 operands[1] = force_reg (QImode, operands[1]);
1177 (define_insn "*zero_extendqihi2_bwx"
1178 [(set (match_operand:HI 0 "register_operand" "=r,r")
1179 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1184 [(set_attr "type" "ilog,ild")])
1186 (define_insn "*zero_extendqihi2_nobwx"
1187 [(set (match_operand:HI 0 "register_operand" "=r")
1188 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1191 [(set_attr "type" "ilog")])
1193 (define_expand "zero_extendqisi2"
1194 [(set (match_operand:SI 0 "register_operand" "")
1195 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1199 operands[1] = force_reg (QImode, operands[1]);
1202 (define_insn "*zero_extendqisi2_bwx"
1203 [(set (match_operand:SI 0 "register_operand" "=r,r")
1204 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1209 [(set_attr "type" "ilog,ild")])
1211 (define_insn "*zero_extendqisi2_nobwx"
1212 [(set (match_operand:SI 0 "register_operand" "=r")
1213 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1216 [(set_attr "type" "ilog")])
1218 (define_expand "zero_extendqidi2"
1219 [(set (match_operand:DI 0 "register_operand" "")
1220 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1224 operands[1] = force_reg (QImode, operands[1]);
1227 (define_insn "*zero_extendqidi2_bwx"
1228 [(set (match_operand:DI 0 "register_operand" "=r,r")
1229 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1234 [(set_attr "type" "ilog,ild")])
1236 (define_insn "*zero_extendqidi2_nobwx"
1237 [(set (match_operand:DI 0 "register_operand" "=r")
1238 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1241 [(set_attr "type" "ilog")])
1243 (define_expand "zero_extendhisi2"
1244 [(set (match_operand:SI 0 "register_operand" "")
1245 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1249 operands[1] = force_reg (HImode, operands[1]);
1252 (define_insn "*zero_extendhisi2_bwx"
1253 [(set (match_operand:SI 0 "register_operand" "=r,r")
1254 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1259 [(set_attr "type" "shift,ild")])
1261 (define_insn "*zero_extendhisi2_nobwx"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1266 [(set_attr "type" "shift")])
1268 (define_expand "zero_extendhidi2"
1269 [(set (match_operand:DI 0 "register_operand" "")
1270 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1274 operands[1] = force_reg (HImode, operands[1]);
1277 (define_insn "*zero_extendhidi2_bwx"
1278 [(set (match_operand:DI 0 "register_operand" "=r,r")
1279 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1284 [(set_attr "type" "shift,ild")])
1286 (define_insn "*zero_extendhidi2_nobwx"
1287 [(set (match_operand:DI 0 "register_operand" "=r")
1288 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1291 [(set_attr "type" "shift")])
1293 (define_insn "zero_extendsidi2"
1294 [(set (match_operand:DI 0 "register_operand" "=r")
1295 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1298 [(set_attr "type" "shift")])
1300 (define_insn "*andnotsi3"
1301 [(set (match_operand:SI 0 "register_operand" "=r")
1302 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1303 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1306 [(set_attr "type" "ilog")])
1308 (define_insn "andnotdi3"
1309 [(set (match_operand:DI 0 "register_operand" "=r")
1310 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1311 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1314 [(set_attr "type" "ilog")])
1316 (define_insn "*iorsi_internal"
1317 [(set (match_operand:SI 0 "register_operand" "=r,r")
1318 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1319 (match_operand:SI 2 "or_operand" "rI,N")))]
1324 [(set_attr "type" "ilog")])
1326 (define_insn "iordi3"
1327 [(set (match_operand:DI 0 "register_operand" "=r,r")
1328 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1329 (match_operand:DI 2 "or_operand" "rI,N")))]
1334 [(set_attr "type" "ilog")])
1336 (define_insn "*one_cmplsi_internal"
1337 [(set (match_operand:SI 0 "register_operand" "=r")
1338 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1341 [(set_attr "type" "ilog")])
1343 (define_insn "one_cmpldi2"
1344 [(set (match_operand:DI 0 "register_operand" "=r")
1345 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1348 [(set_attr "type" "ilog")])
1350 (define_insn "*iornotsi3"
1351 [(set (match_operand:SI 0 "register_operand" "=r")
1352 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1353 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1356 [(set_attr "type" "ilog")])
1358 (define_insn "*iornotdi3"
1359 [(set (match_operand:DI 0 "register_operand" "=r")
1360 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1361 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1364 [(set_attr "type" "ilog")])
1366 (define_insn "*xorsi_internal"
1367 [(set (match_operand:SI 0 "register_operand" "=r,r")
1368 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1369 (match_operand:SI 2 "or_operand" "rI,N")))]
1374 [(set_attr "type" "ilog")])
1376 (define_insn "xordi3"
1377 [(set (match_operand:DI 0 "register_operand" "=r,r")
1378 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1379 (match_operand:DI 2 "or_operand" "rI,N")))]
1384 [(set_attr "type" "ilog")])
1386 (define_insn "*xornotsi3"
1387 [(set (match_operand:SI 0 "register_operand" "=r")
1388 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1389 (match_operand:SI 2 "register_operand" "rI"))))]
1392 [(set_attr "type" "ilog")])
1394 (define_insn "*xornotdi3"
1395 [(set (match_operand:DI 0 "register_operand" "=r")
1396 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1397 (match_operand:DI 2 "register_operand" "rI"))))]
1400 [(set_attr "type" "ilog")])
1402 ;; Handle FFS and related insns iff we support CIX.
1404 (define_expand "ffsdi2"
1406 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1408 (plus:DI (match_dup 2) (const_int 1)))
1409 (set (match_operand:DI 0 "register_operand" "")
1410 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1411 (const_int 0) (match_dup 3)))]
1414 operands[2] = gen_reg_rtx (DImode);
1415 operands[3] = gen_reg_rtx (DImode);
1418 (define_insn "clzdi2"
1419 [(set (match_operand:DI 0 "register_operand" "=r")
1420 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1423 [(set_attr "type" "mvi")])
1425 (define_insn "ctzdi2"
1426 [(set (match_operand:DI 0 "register_operand" "=r")
1427 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1430 [(set_attr "type" "mvi")])
1432 (define_insn "popcountdi2"
1433 [(set (match_operand:DI 0 "register_operand" "=r")
1434 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1437 [(set_attr "type" "mvi")])
1439 ;; Next come the shifts and the various extract and insert operations.
1441 (define_insn "ashldi3"
1442 [(set (match_operand:DI 0 "register_operand" "=r,r")
1443 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1444 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1447 switch (which_alternative)
1450 if (operands[2] == const1_rtx)
1451 return "addq %r1,%r1,%0";
1453 return "s%P2addq %r1,0,%0";
1455 return "sll %r1,%2,%0";
1460 [(set_attr "type" "iadd,shift")])
1462 (define_insn "*ashldi_se"
1463 [(set (match_operand:DI 0 "register_operand" "=r")
1465 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1466 (match_operand:DI 2 "const_int_operand" "P"))
1468 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1470 if (operands[2] == const1_rtx)
1471 return "addl %r1,%r1,%0";
1473 return "s%P2addl %r1,0,%0";
1475 [(set_attr "type" "iadd")])
1477 (define_insn "lshrdi3"
1478 [(set (match_operand:DI 0 "register_operand" "=r")
1479 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1480 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1483 [(set_attr "type" "shift")])
1485 (define_insn "ashrdi3"
1486 [(set (match_operand:DI 0 "register_operand" "=r")
1487 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1488 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1491 [(set_attr "type" "shift")])
1493 (define_expand "extendqihi2"
1495 (ashift:DI (match_operand:QI 1 "some_operand" "")
1497 (set (match_operand:HI 0 "register_operand" "")
1498 (ashiftrt:DI (match_dup 2)
1504 emit_insn (gen_extendqihi2x (operands[0],
1505 force_reg (QImode, operands[1])));
1509 /* If we have an unaligned MEM, extend to DImode (which we do
1510 specially) and then copy to the result. */
1511 if (unaligned_memory_operand (operands[1], HImode))
1513 rtx temp = gen_reg_rtx (DImode);
1515 emit_insn (gen_extendqidi2 (temp, operands[1]));
1516 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1520 operands[0] = gen_lowpart (DImode, operands[0]);
1521 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1522 operands[2] = gen_reg_rtx (DImode);
1525 (define_insn "extendqidi2x"
1526 [(set (match_operand:DI 0 "register_operand" "=r")
1527 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1530 [(set_attr "type" "shift")])
1532 (define_insn "extendhidi2x"
1533 [(set (match_operand:DI 0 "register_operand" "=r")
1534 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1537 [(set_attr "type" "shift")])
1539 (define_insn "extendqisi2x"
1540 [(set (match_operand:SI 0 "register_operand" "=r")
1541 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1544 [(set_attr "type" "shift")])
1546 (define_insn "extendhisi2x"
1547 [(set (match_operand:SI 0 "register_operand" "=r")
1548 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1551 [(set_attr "type" "shift")])
1553 (define_insn "extendqihi2x"
1554 [(set (match_operand:HI 0 "register_operand" "=r")
1555 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1558 [(set_attr "type" "shift")])
1560 (define_expand "extendqisi2"
1562 (ashift:DI (match_operand:QI 1 "some_operand" "")
1564 (set (match_operand:SI 0 "register_operand" "")
1565 (ashiftrt:DI (match_dup 2)
1571 emit_insn (gen_extendqisi2x (operands[0],
1572 force_reg (QImode, operands[1])));
1576 /* If we have an unaligned MEM, extend to a DImode form of
1577 the result (which we do specially). */
1578 if (unaligned_memory_operand (operands[1], QImode))
1580 rtx temp = gen_reg_rtx (DImode);
1582 emit_insn (gen_extendqidi2 (temp, operands[1]));
1583 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1587 operands[0] = gen_lowpart (DImode, operands[0]);
1588 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1589 operands[2] = gen_reg_rtx (DImode);
1592 (define_expand "extendqidi2"
1594 (ashift:DI (match_operand:QI 1 "some_operand" "")
1596 (set (match_operand:DI 0 "register_operand" "")
1597 (ashiftrt:DI (match_dup 2)
1603 emit_insn (gen_extendqidi2x (operands[0],
1604 force_reg (QImode, operands[1])));
1608 if (unaligned_memory_operand (operands[1], QImode))
1611 = gen_unaligned_extendqidi (operands[0],
1612 get_unaligned_address (operands[1], 1));
1614 alpha_set_memflags (seq, operands[1]);
1619 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1620 operands[2] = gen_reg_rtx (DImode);
1623 (define_expand "extendhisi2"
1625 (ashift:DI (match_operand:HI 1 "some_operand" "")
1627 (set (match_operand:SI 0 "register_operand" "")
1628 (ashiftrt:DI (match_dup 2)
1634 emit_insn (gen_extendhisi2x (operands[0],
1635 force_reg (HImode, operands[1])));
1639 /* If we have an unaligned MEM, extend to a DImode form of
1640 the result (which we do specially). */
1641 if (unaligned_memory_operand (operands[1], HImode))
1643 rtx temp = gen_reg_rtx (DImode);
1645 emit_insn (gen_extendhidi2 (temp, operands[1]));
1646 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1650 operands[0] = gen_lowpart (DImode, operands[0]);
1651 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1652 operands[2] = gen_reg_rtx (DImode);
1655 (define_expand "extendhidi2"
1657 (ashift:DI (match_operand:HI 1 "some_operand" "")
1659 (set (match_operand:DI 0 "register_operand" "")
1660 (ashiftrt:DI (match_dup 2)
1666 emit_insn (gen_extendhidi2x (operands[0],
1667 force_reg (HImode, operands[1])));
1671 if (unaligned_memory_operand (operands[1], HImode))
1674 = gen_unaligned_extendhidi (operands[0],
1675 get_unaligned_address (operands[1], 2));
1677 alpha_set_memflags (seq, operands[1]);
1682 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1683 operands[2] = gen_reg_rtx (DImode);
1686 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1687 ;; as a pattern saves one instruction. The code is similar to that for
1688 ;; the unaligned loads (see below).
1690 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1691 (define_expand "unaligned_extendqidi"
1692 [(use (match_operand:QI 0 "register_operand" ""))
1693 (use (match_operand:DI 1 "address_operand" ""))]
1696 if (WORDS_BIG_ENDIAN)
1697 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1699 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1703 (define_expand "unaligned_extendqidi_le"
1704 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1706 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1709 (ashift:DI (match_dup 3)
1710 (minus:DI (const_int 64)
1712 (and:DI (match_dup 2) (const_int 7))
1714 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1715 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1716 "! WORDS_BIG_ENDIAN"
1718 operands[2] = gen_reg_rtx (DImode);
1719 operands[3] = gen_reg_rtx (DImode);
1720 operands[4] = gen_reg_rtx (DImode);
1723 (define_expand "unaligned_extendqidi_be"
1724 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1725 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1727 (mem:DI (and:DI (match_dup 3)
1729 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1731 (ashift:DI (match_dup 4)
1734 (plus:DI (match_dup 5) (const_int 1))
1737 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1738 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1741 operands[2] = gen_reg_rtx (DImode);
1742 operands[3] = gen_reg_rtx (DImode);
1743 operands[4] = gen_reg_rtx (DImode);
1744 operands[5] = gen_reg_rtx (DImode);
1745 operands[6] = gen_reg_rtx (DImode);
1748 (define_expand "unaligned_extendhidi"
1749 [(use (match_operand:QI 0 "register_operand" ""))
1750 (use (match_operand:DI 1 "address_operand" ""))]
1753 operands[0] = gen_lowpart (DImode, operands[0]);
1754 emit_insn ((WORDS_BIG_ENDIAN
1755 ? gen_unaligned_extendhidi_be
1756 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1760 (define_expand "unaligned_extendhidi_le"
1761 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1763 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1766 (ashift:DI (match_dup 3)
1767 (minus:DI (const_int 64)
1769 (and:DI (match_dup 2) (const_int 7))
1771 (set (match_operand:DI 0 "register_operand" "")
1772 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1773 "! WORDS_BIG_ENDIAN"
1775 operands[2] = gen_reg_rtx (DImode);
1776 operands[3] = gen_reg_rtx (DImode);
1777 operands[4] = gen_reg_rtx (DImode);
1780 (define_expand "unaligned_extendhidi_be"
1781 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1782 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1784 (mem:DI (and:DI (match_dup 3)
1786 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1788 (ashift:DI (match_dup 4)
1791 (plus:DI (match_dup 5) (const_int 1))
1794 (set (match_operand:DI 0 "register_operand" "")
1795 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1798 operands[2] = gen_reg_rtx (DImode);
1799 operands[3] = gen_reg_rtx (DImode);
1800 operands[4] = gen_reg_rtx (DImode);
1801 operands[5] = gen_reg_rtx (DImode);
1802 operands[6] = gen_reg_rtx (DImode);
1805 (define_insn "*extxl_const"
1806 [(set (match_operand:DI 0 "register_operand" "=r")
1807 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1808 (match_operand:DI 2 "mode_width_operand" "n")
1809 (match_operand:DI 3 "mul8_operand" "I")))]
1811 "ext%M2l %r1,%s3,%0"
1812 [(set_attr "type" "shift")])
1814 (define_insn "extxl_le"
1815 [(set (match_operand:DI 0 "register_operand" "=r")
1816 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1817 (match_operand:DI 2 "mode_width_operand" "n")
1818 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1820 "! WORDS_BIG_ENDIAN"
1822 [(set_attr "type" "shift")])
1824 (define_insn "extxl_be"
1825 [(set (match_operand:DI 0 "register_operand" "=r")
1826 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1827 (match_operand:DI 2 "mode_width_operand" "n")
1831 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1835 [(set_attr "type" "shift")])
1837 ;; Combine has some strange notion of preserving existing undefined behavior
1838 ;; in shifts larger than a word size. So capture these patterns that it
1839 ;; should have turned into zero_extracts.
1841 (define_insn "*extxl_1_le"
1842 [(set (match_operand:DI 0 "register_operand" "=r")
1843 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1844 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1846 (match_operand:DI 3 "mode_mask_operand" "n")))]
1847 "! WORDS_BIG_ENDIAN"
1849 [(set_attr "type" "shift")])
1851 (define_insn "*extxl_1_be"
1852 [(set (match_operand:DI 0 "register_operand" "=r")
1853 (and:DI (lshiftrt:DI
1854 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1855 (minus:DI (const_int 56)
1856 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1858 (match_operand:DI 3 "mode_mask_operand" "n")))]
1861 [(set_attr "type" "shift")])
1863 (define_insn "*extql_2_le"
1864 [(set (match_operand:DI 0 "register_operand" "=r")
1865 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1866 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1868 "! WORDS_BIG_ENDIAN"
1870 [(set_attr "type" "shift")])
1872 (define_insn "*extql_2_be"
1873 [(set (match_operand:DI 0 "register_operand" "=r")
1875 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1876 (minus:DI (const_int 56)
1878 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1882 [(set_attr "type" "shift")])
1884 (define_insn "extqh_le"
1885 [(set (match_operand:DI 0 "register_operand" "=r")
1887 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1888 (minus:DI (const_int 64)
1891 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1894 "! WORDS_BIG_ENDIAN"
1896 [(set_attr "type" "shift")])
1898 (define_insn "extqh_be"
1899 [(set (match_operand:DI 0 "register_operand" "=r")
1901 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1904 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1910 [(set_attr "type" "shift")])
1912 (define_insn "extlh_le"
1913 [(set (match_operand:DI 0 "register_operand" "=r")
1915 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1916 (const_int 2147483647))
1917 (minus:DI (const_int 64)
1920 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1923 "! WORDS_BIG_ENDIAN"
1925 [(set_attr "type" "shift")])
1927 (define_insn "extlh_be"
1928 [(set (match_operand:DI 0 "register_operand" "=r")
1931 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1935 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1939 (const_int 2147483647)))]
1942 [(set_attr "type" "shift")])
1944 (define_insn "extwh_le"
1945 [(set (match_operand:DI 0 "register_operand" "=r")
1947 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1949 (minus:DI (const_int 64)
1952 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1955 "! WORDS_BIG_ENDIAN"
1957 [(set_attr "type" "shift")])
1959 (define_insn "extwh_be"
1960 [(set (match_operand:DI 0 "register_operand" "=r")
1962 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1966 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1970 (const_int 65535)))]
1973 [(set_attr "type" "shift")])
1975 ;; This converts an extXl into an extXh with an appropriate adjustment
1976 ;; to the address calculation.
1979 ;; [(set (match_operand:DI 0 "register_operand" "")
1980 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1981 ;; (match_operand:DI 2 "mode_width_operand" "")
1982 ;; (ashift:DI (match_operand:DI 3 "" "")
1984 ;; (match_operand:DI 4 "const_int_operand" "")))
1985 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1986 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1987 ;; [(set (match_dup 5) (match_dup 6))
1988 ;; (set (match_dup 0)
1989 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1990 ;; (ashift:DI (plus:DI (match_dup 5)
1996 ;; operands[6] = plus_constant (operands[3],
1997 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1998 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2001 (define_insn "*insbl_const"
2002 [(set (match_operand:DI 0 "register_operand" "=r")
2003 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2004 (match_operand:DI 2 "mul8_operand" "I")))]
2007 [(set_attr "type" "shift")])
2009 (define_insn "*inswl_const"
2010 [(set (match_operand:DI 0 "register_operand" "=r")
2011 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2012 (match_operand:DI 2 "mul8_operand" "I")))]
2015 [(set_attr "type" "shift")])
2017 (define_insn "*insll_const"
2018 [(set (match_operand:DI 0 "register_operand" "=r")
2019 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2020 (match_operand:DI 2 "mul8_operand" "I")))]
2023 [(set_attr "type" "shift")])
2025 (define_insn "insbl_le"
2026 [(set (match_operand:DI 0 "register_operand" "=r")
2027 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2028 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2030 "! WORDS_BIG_ENDIAN"
2032 [(set_attr "type" "shift")])
2034 (define_insn "insbl_be"
2035 [(set (match_operand:DI 0 "register_operand" "=r")
2036 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2037 (minus:DI (const_int 56)
2038 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2042 [(set_attr "type" "shift")])
2044 (define_insn "inswl_le"
2045 [(set (match_operand:DI 0 "register_operand" "=r")
2046 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2047 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2049 "! WORDS_BIG_ENDIAN"
2051 [(set_attr "type" "shift")])
2053 (define_insn "inswl_be"
2054 [(set (match_operand:DI 0 "register_operand" "=r")
2055 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2056 (minus:DI (const_int 56)
2057 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2061 [(set_attr "type" "shift")])
2063 (define_insn "insll_le"
2064 [(set (match_operand:DI 0 "register_operand" "=r")
2065 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2066 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2068 "! WORDS_BIG_ENDIAN"
2070 [(set_attr "type" "shift")])
2072 (define_insn "insll_be"
2073 [(set (match_operand:DI 0 "register_operand" "=r")
2074 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2075 (minus:DI (const_int 56)
2076 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2080 [(set_attr "type" "shift")])
2082 (define_insn "insql_le"
2083 [(set (match_operand:DI 0 "register_operand" "=r")
2084 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2085 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2087 "! WORDS_BIG_ENDIAN"
2089 [(set_attr "type" "shift")])
2091 (define_insn "insql_be"
2092 [(set (match_operand:DI 0 "register_operand" "=r")
2093 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2094 (minus:DI (const_int 56)
2095 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2099 [(set_attr "type" "shift")])
2101 ;; Combine has this sometimes habit of moving the and outside of the
2102 ;; shift, making life more interesting.
2104 (define_insn "*insxl"
2105 [(set (match_operand:DI 0 "register_operand" "=r")
2106 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2107 (match_operand:DI 2 "mul8_operand" "I"))
2108 (match_operand:DI 3 "immediate_operand" "i")))]
2109 "HOST_BITS_PER_WIDE_INT == 64
2110 && GET_CODE (operands[3]) == CONST_INT
2111 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2112 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2113 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2114 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2115 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2116 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2118 #if HOST_BITS_PER_WIDE_INT == 64
2119 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2120 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2121 return "insbl %1,%s2,%0";
2122 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2123 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2124 return "inswl %1,%s2,%0";
2125 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2126 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2127 return "insll %1,%s2,%0";
2131 [(set_attr "type" "shift")])
2133 ;; We do not include the insXh insns because they are complex to express
2134 ;; and it does not appear that we would ever want to generate them.
2136 ;; Since we need them for block moves, though, cop out and use unspec.
2138 (define_insn "insxh"
2139 [(set (match_operand:DI 0 "register_operand" "=r")
2140 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2141 (match_operand:DI 2 "mode_width_operand" "n")
2142 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2146 [(set_attr "type" "shift")])
2148 (define_insn "mskxl_le"
2149 [(set (match_operand:DI 0 "register_operand" "=r")
2150 (and:DI (not:DI (ashift:DI
2151 (match_operand:DI 2 "mode_mask_operand" "n")
2153 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2155 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2156 "! WORDS_BIG_ENDIAN"
2158 [(set_attr "type" "shift")])
2160 (define_insn "mskxl_be"
2161 [(set (match_operand:DI 0 "register_operand" "=r")
2162 (and:DI (not:DI (ashift:DI
2163 (match_operand:DI 2 "mode_mask_operand" "n")
2164 (minus:DI (const_int 56)
2166 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2168 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2171 [(set_attr "type" "shift")])
2173 ;; We do not include the mskXh insns because it does not appear we would
2174 ;; ever generate one.
2176 ;; Again, we do for block moves and we use unspec again.
2178 (define_insn "mskxh"
2179 [(set (match_operand:DI 0 "register_operand" "=r")
2180 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2181 (match_operand:DI 2 "mode_width_operand" "n")
2182 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2186 [(set_attr "type" "shift")])
2188 ;; Prefer AND + NE over LSHIFTRT + AND.
2190 (define_insn_and_split "*ze_and_ne"
2191 [(set (match_operand:DI 0 "register_operand" "=r")
2192 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2194 (match_operand 2 "const_int_operand" "I")))]
2195 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2197 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2199 (and:DI (match_dup 1) (match_dup 3)))
2201 (ne:DI (match_dup 0) (const_int 0)))]
2202 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2204 ;; Floating-point operations. All the double-precision insns can extend
2205 ;; from single, so indicate that. The exception are the ones that simply
2206 ;; play with the sign bits; it's not clear what to do there.
2208 (define_insn "abssf2"
2209 [(set (match_operand:SF 0 "register_operand" "=f")
2210 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2213 [(set_attr "type" "fcpys")])
2215 (define_insn "*nabssf2"
2216 [(set (match_operand:SF 0 "register_operand" "=f")
2217 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2220 [(set_attr "type" "fadd")])
2222 (define_insn "absdf2"
2223 [(set (match_operand:DF 0 "register_operand" "=f")
2224 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2227 [(set_attr "type" "fcpys")])
2229 (define_insn "*nabsdf2"
2230 [(set (match_operand:DF 0 "register_operand" "=f")
2231 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2234 [(set_attr "type" "fadd")])
2236 (define_expand "abstf2"
2237 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2238 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2239 (use (match_dup 2))])]
2240 "TARGET_HAS_XFLOATING_LIBS"
2242 #if HOST_BITS_PER_WIDE_INT >= 64
2243 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2245 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2249 (define_insn_and_split "*abstf_internal"
2250 [(set (match_operand:TF 0 "register_operand" "=r")
2251 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2252 (use (match_operand:DI 2 "register_operand" "r"))]
2253 "TARGET_HAS_XFLOATING_LIBS"
2255 "&& reload_completed"
2257 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2259 (define_insn "negsf2"
2260 [(set (match_operand:SF 0 "register_operand" "=f")
2261 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2264 [(set_attr "type" "fadd")])
2266 (define_insn "negdf2"
2267 [(set (match_operand:DF 0 "register_operand" "=f")
2268 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2271 [(set_attr "type" "fadd")])
2273 (define_expand "negtf2"
2274 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2275 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2276 (use (match_dup 2))])]
2277 "TARGET_HAS_XFLOATING_LIBS"
2279 #if HOST_BITS_PER_WIDE_INT >= 64
2280 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2282 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2286 (define_insn_and_split "*negtf_internal"
2287 [(set (match_operand:TF 0 "register_operand" "=r")
2288 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2289 (use (match_operand:DI 2 "register_operand" "r"))]
2290 "TARGET_HAS_XFLOATING_LIBS"
2292 "&& reload_completed"
2294 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2296 (define_insn "copysignsf3"
2297 [(set (match_operand:SF 0 "register_operand" "=f")
2298 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2299 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2303 [(set_attr "type" "fadd")])
2305 (define_insn "*ncopysignsf3"
2306 [(set (match_operand:SF 0 "register_operand" "=f")
2307 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2308 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2312 [(set_attr "type" "fadd")])
2314 (define_insn "copysigndf3"
2315 [(set (match_operand:DF 0 "register_operand" "=f")
2316 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2317 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2321 [(set_attr "type" "fadd")])
2323 (define_insn "*ncopysigndf3"
2324 [(set (match_operand:DF 0 "register_operand" "=f")
2325 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2326 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2330 [(set_attr "type" "fadd")])
2332 (define_insn "*addsf_ieee"
2333 [(set (match_operand:SF 0 "register_operand" "=&f")
2334 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2335 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2336 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2337 "add%,%/ %R1,%R2,%0"
2338 [(set_attr "type" "fadd")
2339 (set_attr "trap" "yes")
2340 (set_attr "round_suffix" "normal")
2341 (set_attr "trap_suffix" "u_su_sui")])
2343 (define_insn "addsf3"
2344 [(set (match_operand:SF 0 "register_operand" "=f")
2345 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2346 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2348 "add%,%/ %R1,%R2,%0"
2349 [(set_attr "type" "fadd")
2350 (set_attr "trap" "yes")
2351 (set_attr "round_suffix" "normal")
2352 (set_attr "trap_suffix" "u_su_sui")])
2354 (define_insn "*adddf_ieee"
2355 [(set (match_operand:DF 0 "register_operand" "=&f")
2356 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2357 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2358 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2359 "add%-%/ %R1,%R2,%0"
2360 [(set_attr "type" "fadd")
2361 (set_attr "trap" "yes")
2362 (set_attr "round_suffix" "normal")
2363 (set_attr "trap_suffix" "u_su_sui")])
2365 (define_insn "adddf3"
2366 [(set (match_operand:DF 0 "register_operand" "=f")
2367 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2368 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2370 "add%-%/ %R1,%R2,%0"
2371 [(set_attr "type" "fadd")
2372 (set_attr "trap" "yes")
2373 (set_attr "round_suffix" "normal")
2374 (set_attr "trap_suffix" "u_su_sui")])
2376 (define_insn "*adddf_ext1"
2377 [(set (match_operand:DF 0 "register_operand" "=f")
2378 (plus:DF (float_extend:DF
2379 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2380 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2381 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2382 "add%-%/ %R1,%R2,%0"
2383 [(set_attr "type" "fadd")
2384 (set_attr "trap" "yes")
2385 (set_attr "round_suffix" "normal")
2386 (set_attr "trap_suffix" "u_su_sui")])
2388 (define_insn "*adddf_ext2"
2389 [(set (match_operand:DF 0 "register_operand" "=f")
2390 (plus:DF (float_extend:DF
2391 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2393 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2394 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2395 "add%-%/ %R1,%R2,%0"
2396 [(set_attr "type" "fadd")
2397 (set_attr "trap" "yes")
2398 (set_attr "round_suffix" "normal")
2399 (set_attr "trap_suffix" "u_su_sui")])
2401 (define_expand "addtf3"
2402 [(use (match_operand 0 "register_operand" ""))
2403 (use (match_operand 1 "general_operand" ""))
2404 (use (match_operand 2 "general_operand" ""))]
2405 "TARGET_HAS_XFLOATING_LIBS"
2406 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2408 ;; Define conversion operators between DFmode and SImode, using the cvtql
2409 ;; instruction. To allow combine et al to do useful things, we keep the
2410 ;; operation as a unit until after reload, at which point we split the
2413 ;; Note that we (attempt to) only consider this optimization when the
2414 ;; ultimate destination is memory. If we will be doing further integer
2415 ;; processing, it is cheaper to do the truncation in the int regs.
2417 (define_insn "*cvtql"
2418 [(set (match_operand:SF 0 "register_operand" "=f")
2419 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2423 [(set_attr "type" "fadd")
2424 (set_attr "trap" "yes")
2425 (set_attr "trap_suffix" "v_sv")])
2427 (define_insn_and_split "*fix_truncdfsi_ieee"
2428 [(set (match_operand:SI 0 "memory_operand" "=m")
2430 (match_operator:DI 4 "fix_operator"
2431 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2432 (clobber (match_scratch:DI 2 "=&f"))
2433 (clobber (match_scratch:SF 3 "=&f"))]
2434 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2436 "&& reload_completed"
2437 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2438 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2439 (set (match_dup 5) (match_dup 3))]
2441 operands[5] = adjust_address (operands[0], SFmode, 0);
2443 [(set_attr "type" "fadd")
2444 (set_attr "trap" "yes")])
2446 (define_insn_and_split "*fix_truncdfsi_internal"
2447 [(set (match_operand:SI 0 "memory_operand" "=m")
2449 (match_operator:DI 3 "fix_operator"
2450 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2451 (clobber (match_scratch:DI 2 "=f"))]
2452 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2454 "&& reload_completed"
2455 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2456 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2457 (set (match_dup 5) (match_dup 4))]
2459 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2460 operands[5] = adjust_address (operands[0], SFmode, 0);
2462 [(set_attr "type" "fadd")
2463 (set_attr "trap" "yes")])
2465 (define_insn "*fix_truncdfdi_ieee"
2466 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2467 (match_operator:DI 2 "fix_operator"
2468 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2469 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2471 [(set_attr "type" "fadd")
2472 (set_attr "trap" "yes")
2473 (set_attr "round_suffix" "c")
2474 (set_attr "trap_suffix" "v_sv_svi")])
2476 (define_insn "*fix_truncdfdi2"
2477 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2478 (match_operator:DI 2 "fix_operator"
2479 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2482 [(set_attr "type" "fadd")
2483 (set_attr "trap" "yes")
2484 (set_attr "round_suffix" "c")
2485 (set_attr "trap_suffix" "v_sv_svi")])
2487 (define_expand "fix_truncdfdi2"
2488 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2489 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2493 (define_expand "fixuns_truncdfdi2"
2494 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2495 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2499 ;; Likewise between SFmode and SImode.
2501 (define_insn_and_split "*fix_truncsfsi_ieee"
2502 [(set (match_operand:SI 0 "memory_operand" "=m")
2504 (match_operator:DI 4 "fix_operator"
2506 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2507 (clobber (match_scratch:DI 2 "=&f"))
2508 (clobber (match_scratch:SF 3 "=&f"))]
2509 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2511 "&& reload_completed"
2512 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2513 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2514 (set (match_dup 5) (match_dup 3))]
2516 operands[5] = adjust_address (operands[0], SFmode, 0);
2518 [(set_attr "type" "fadd")
2519 (set_attr "trap" "yes")])
2521 (define_insn_and_split "*fix_truncsfsi_internal"
2522 [(set (match_operand:SI 0 "memory_operand" "=m")
2524 (match_operator:DI 3 "fix_operator"
2526 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2527 (clobber (match_scratch:DI 2 "=f"))]
2528 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2530 "&& reload_completed"
2531 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2532 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2533 (set (match_dup 5) (match_dup 4))]
2535 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2536 operands[5] = adjust_address (operands[0], SFmode, 0);
2538 [(set_attr "type" "fadd")
2539 (set_attr "trap" "yes")])
2541 (define_insn "*fix_truncsfdi_ieee"
2542 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2543 (match_operator:DI 2 "fix_operator"
2544 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2545 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2547 [(set_attr "type" "fadd")
2548 (set_attr "trap" "yes")
2549 (set_attr "round_suffix" "c")
2550 (set_attr "trap_suffix" "v_sv_svi")])
2552 (define_insn "*fix_truncsfdi2"
2553 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2554 (match_operator:DI 2 "fix_operator"
2555 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2558 [(set_attr "type" "fadd")
2559 (set_attr "trap" "yes")
2560 (set_attr "round_suffix" "c")
2561 (set_attr "trap_suffix" "v_sv_svi")])
2563 (define_expand "fix_truncsfdi2"
2564 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2565 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2569 (define_expand "fixuns_truncsfdi2"
2570 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2572 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2576 (define_expand "fix_trunctfdi2"
2577 [(use (match_operand:DI 0 "register_operand" ""))
2578 (use (match_operand:TF 1 "general_operand" ""))]
2579 "TARGET_HAS_XFLOATING_LIBS"
2580 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2582 (define_expand "fixuns_trunctfdi2"
2583 [(use (match_operand:DI 0 "register_operand" ""))
2584 (use (match_operand:TF 1 "general_operand" ""))]
2585 "TARGET_HAS_XFLOATING_LIBS"
2586 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2588 (define_insn "*floatdisf_ieee"
2589 [(set (match_operand:SF 0 "register_operand" "=&f")
2590 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2591 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2593 [(set_attr "type" "fadd")
2594 (set_attr "trap" "yes")
2595 (set_attr "round_suffix" "normal")
2596 (set_attr "trap_suffix" "sui")])
2598 (define_insn "floatdisf2"
2599 [(set (match_operand:SF 0 "register_operand" "=f")
2600 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2603 [(set_attr "type" "fadd")
2604 (set_attr "trap" "yes")
2605 (set_attr "round_suffix" "normal")
2606 (set_attr "trap_suffix" "sui")])
2608 (define_insn_and_split "*floatsisf2_ieee"
2609 [(set (match_operand:SF 0 "register_operand" "=&f")
2610 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2611 (clobber (match_scratch:DI 2 "=&f"))
2612 (clobber (match_scratch:SF 3 "=&f"))]
2613 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2615 "&& reload_completed"
2616 [(set (match_dup 3) (match_dup 1))
2617 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2618 (set (match_dup 0) (float:SF (match_dup 2)))]
2620 operands[1] = adjust_address (operands[1], SFmode, 0);
2623 (define_insn_and_split "*floatsisf2"
2624 [(set (match_operand:SF 0 "register_operand" "=f")
2625 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2628 "&& reload_completed"
2629 [(set (match_dup 0) (match_dup 1))
2630 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2631 (set (match_dup 0) (float:SF (match_dup 2)))]
2633 operands[1] = adjust_address (operands[1], SFmode, 0);
2634 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2637 (define_insn "*floatdidf_ieee"
2638 [(set (match_operand:DF 0 "register_operand" "=&f")
2639 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2640 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2642 [(set_attr "type" "fadd")
2643 (set_attr "trap" "yes")
2644 (set_attr "round_suffix" "normal")
2645 (set_attr "trap_suffix" "sui")])
2647 (define_insn "floatdidf2"
2648 [(set (match_operand:DF 0 "register_operand" "=f")
2649 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2652 [(set_attr "type" "fadd")
2653 (set_attr "trap" "yes")
2654 (set_attr "round_suffix" "normal")
2655 (set_attr "trap_suffix" "sui")])
2657 (define_insn_and_split "*floatsidf2_ieee"
2658 [(set (match_operand:DF 0 "register_operand" "=&f")
2659 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2660 (clobber (match_scratch:DI 2 "=&f"))
2661 (clobber (match_scratch:SF 3 "=&f"))]
2662 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2664 "&& reload_completed"
2665 [(set (match_dup 3) (match_dup 1))
2666 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2667 (set (match_dup 0) (float:DF (match_dup 2)))]
2669 operands[1] = adjust_address (operands[1], SFmode, 0);
2672 (define_insn_and_split "*floatsidf2"
2673 [(set (match_operand:DF 0 "register_operand" "=f")
2674 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2677 "&& reload_completed"
2678 [(set (match_dup 3) (match_dup 1))
2679 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2680 (set (match_dup 0) (float:DF (match_dup 2)))]
2682 operands[1] = adjust_address (operands[1], SFmode, 0);
2683 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2684 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2687 (define_expand "floatditf2"
2688 [(use (match_operand:TF 0 "register_operand" ""))
2689 (use (match_operand:DI 1 "general_operand" ""))]
2690 "TARGET_HAS_XFLOATING_LIBS"
2691 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2693 (define_expand "floatunsdisf2"
2694 [(use (match_operand:SF 0 "register_operand" ""))
2695 (use (match_operand:DI 1 "register_operand" ""))]
2697 "alpha_emit_floatuns (operands); DONE;")
2699 (define_expand "floatunsdidf2"
2700 [(use (match_operand:DF 0 "register_operand" ""))
2701 (use (match_operand:DI 1 "register_operand" ""))]
2703 "alpha_emit_floatuns (operands); DONE;")
2705 (define_expand "floatunsditf2"
2706 [(use (match_operand:TF 0 "register_operand" ""))
2707 (use (match_operand:DI 1 "general_operand" ""))]
2708 "TARGET_HAS_XFLOATING_LIBS"
2709 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2711 (define_expand "extendsfdf2"
2712 [(set (match_operand:DF 0 "register_operand" "")
2713 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2716 if (alpha_fptm >= ALPHA_FPTM_SU)
2717 operands[1] = force_reg (SFmode, operands[1]);
2720 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2721 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2723 (define_insn "*extendsfdf2_ieee"
2724 [(set (match_operand:DF 0 "register_operand" "=&f")
2725 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2726 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2728 [(set_attr "type" "fadd")
2729 (set_attr "trap" "yes")])
2731 (define_insn "*extendsfdf2_internal"
2732 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2733 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2734 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2739 [(set_attr "type" "fcpys,fld,fst")])
2741 ;; Use register_operand for operand 1 to prevent compress_float_constant
2742 ;; from doing something silly. When optimizing we'll put things back
2744 (define_expand "extendsftf2"
2745 [(use (match_operand:TF 0 "register_operand" ""))
2746 (use (match_operand:SF 1 "register_operand" ""))]
2747 "TARGET_HAS_XFLOATING_LIBS"
2749 rtx tmp = gen_reg_rtx (DFmode);
2750 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2751 emit_insn (gen_extenddftf2 (operands[0], tmp));
2755 (define_expand "extenddftf2"
2756 [(use (match_operand:TF 0 "register_operand" ""))
2757 (use (match_operand:DF 1 "register_operand" ""))]
2758 "TARGET_HAS_XFLOATING_LIBS"
2759 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2761 (define_insn "*truncdfsf2_ieee"
2762 [(set (match_operand:SF 0 "register_operand" "=&f")
2763 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2764 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2766 [(set_attr "type" "fadd")
2767 (set_attr "trap" "yes")
2768 (set_attr "round_suffix" "normal")
2769 (set_attr "trap_suffix" "u_su_sui")])
2771 (define_insn "truncdfsf2"
2772 [(set (match_operand:SF 0 "register_operand" "=f")
2773 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2776 [(set_attr "type" "fadd")
2777 (set_attr "trap" "yes")
2778 (set_attr "round_suffix" "normal")
2779 (set_attr "trap_suffix" "u_su_sui")])
2781 (define_expand "trunctfdf2"
2782 [(use (match_operand:DF 0 "register_operand" ""))
2783 (use (match_operand:TF 1 "general_operand" ""))]
2784 "TARGET_HAS_XFLOATING_LIBS"
2785 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2787 (define_expand "trunctfsf2"
2788 [(use (match_operand:SF 0 "register_operand" ""))
2789 (use (match_operand:TF 1 "general_operand" ""))]
2790 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2792 rtx tmpf, sticky, arg, lo, hi;
2794 tmpf = gen_reg_rtx (DFmode);
2795 sticky = gen_reg_rtx (DImode);
2796 arg = copy_to_mode_reg (TFmode, operands[1]);
2797 lo = gen_lowpart (DImode, arg);
2798 hi = gen_highpart (DImode, arg);
2800 /* Convert the low word of the TFmode value into a sticky rounding bit,
2801 then or it into the low bit of the high word. This leaves the sticky
2802 bit at bit 48 of the fraction, which is representable in DFmode,
2803 which prevents rounding error in the final conversion to SFmode. */
2805 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2806 gen_rtx_NE (DImode, lo, const0_rtx)));
2807 emit_insn (gen_iordi3 (hi, hi, sticky));
2808 emit_insn (gen_trunctfdf2 (tmpf, arg));
2809 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2813 (define_insn "*divsf3_ieee"
2814 [(set (match_operand:SF 0 "register_operand" "=&f")
2815 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2816 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2817 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2818 "div%,%/ %R1,%R2,%0"
2819 [(set_attr "type" "fdiv")
2820 (set_attr "opsize" "si")
2821 (set_attr "trap" "yes")
2822 (set_attr "round_suffix" "normal")
2823 (set_attr "trap_suffix" "u_su_sui")])
2825 (define_insn "divsf3"
2826 [(set (match_operand:SF 0 "register_operand" "=f")
2827 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2828 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2830 "div%,%/ %R1,%R2,%0"
2831 [(set_attr "type" "fdiv")
2832 (set_attr "opsize" "si")
2833 (set_attr "trap" "yes")
2834 (set_attr "round_suffix" "normal")
2835 (set_attr "trap_suffix" "u_su_sui")])
2837 (define_insn "*divdf3_ieee"
2838 [(set (match_operand:DF 0 "register_operand" "=&f")
2839 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2840 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2841 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2842 "div%-%/ %R1,%R2,%0"
2843 [(set_attr "type" "fdiv")
2844 (set_attr "trap" "yes")
2845 (set_attr "round_suffix" "normal")
2846 (set_attr "trap_suffix" "u_su_sui")])
2848 (define_insn "divdf3"
2849 [(set (match_operand:DF 0 "register_operand" "=f")
2850 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2851 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2853 "div%-%/ %R1,%R2,%0"
2854 [(set_attr "type" "fdiv")
2855 (set_attr "trap" "yes")
2856 (set_attr "round_suffix" "normal")
2857 (set_attr "trap_suffix" "u_su_sui")])
2859 (define_insn "*divdf_ext1"
2860 [(set (match_operand:DF 0 "register_operand" "=f")
2861 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2862 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2863 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2864 "div%-%/ %R1,%R2,%0"
2865 [(set_attr "type" "fdiv")
2866 (set_attr "trap" "yes")
2867 (set_attr "round_suffix" "normal")
2868 (set_attr "trap_suffix" "u_su_sui")])
2870 (define_insn "*divdf_ext2"
2871 [(set (match_operand:DF 0 "register_operand" "=f")
2872 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2874 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2875 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2876 "div%-%/ %R1,%R2,%0"
2877 [(set_attr "type" "fdiv")
2878 (set_attr "trap" "yes")
2879 (set_attr "round_suffix" "normal")
2880 (set_attr "trap_suffix" "u_su_sui")])
2882 (define_insn "*divdf_ext3"
2883 [(set (match_operand:DF 0 "register_operand" "=f")
2884 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2885 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2886 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2887 "div%-%/ %R1,%R2,%0"
2888 [(set_attr "type" "fdiv")
2889 (set_attr "trap" "yes")
2890 (set_attr "round_suffix" "normal")
2891 (set_attr "trap_suffix" "u_su_sui")])
2893 (define_expand "divtf3"
2894 [(use (match_operand 0 "register_operand" ""))
2895 (use (match_operand 1 "general_operand" ""))
2896 (use (match_operand 2 "general_operand" ""))]
2897 "TARGET_HAS_XFLOATING_LIBS"
2898 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2900 (define_insn "*mulsf3_ieee"
2901 [(set (match_operand:SF 0 "register_operand" "=&f")
2902 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2903 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2904 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2905 "mul%,%/ %R1,%R2,%0"
2906 [(set_attr "type" "fmul")
2907 (set_attr "trap" "yes")
2908 (set_attr "round_suffix" "normal")
2909 (set_attr "trap_suffix" "u_su_sui")])
2911 (define_insn "mulsf3"
2912 [(set (match_operand:SF 0 "register_operand" "=f")
2913 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2914 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2916 "mul%,%/ %R1,%R2,%0"
2917 [(set_attr "type" "fmul")
2918 (set_attr "trap" "yes")
2919 (set_attr "round_suffix" "normal")
2920 (set_attr "trap_suffix" "u_su_sui")])
2922 (define_insn "*muldf3_ieee"
2923 [(set (match_operand:DF 0 "register_operand" "=&f")
2924 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2925 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2926 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2927 "mul%-%/ %R1,%R2,%0"
2928 [(set_attr "type" "fmul")
2929 (set_attr "trap" "yes")
2930 (set_attr "round_suffix" "normal")
2931 (set_attr "trap_suffix" "u_su_sui")])
2933 (define_insn "muldf3"
2934 [(set (match_operand:DF 0 "register_operand" "=f")
2935 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2936 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2938 "mul%-%/ %R1,%R2,%0"
2939 [(set_attr "type" "fmul")
2940 (set_attr "trap" "yes")
2941 (set_attr "round_suffix" "normal")
2942 (set_attr "trap_suffix" "u_su_sui")])
2944 (define_insn "*muldf_ext1"
2945 [(set (match_operand:DF 0 "register_operand" "=f")
2946 (mult:DF (float_extend:DF
2947 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2948 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2949 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2950 "mul%-%/ %R1,%R2,%0"
2951 [(set_attr "type" "fmul")
2952 (set_attr "trap" "yes")
2953 (set_attr "round_suffix" "normal")
2954 (set_attr "trap_suffix" "u_su_sui")])
2956 (define_insn "*muldf_ext2"
2957 [(set (match_operand:DF 0 "register_operand" "=f")
2958 (mult:DF (float_extend:DF
2959 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2961 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2962 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2963 "mul%-%/ %R1,%R2,%0"
2964 [(set_attr "type" "fmul")
2965 (set_attr "trap" "yes")
2966 (set_attr "round_suffix" "normal")
2967 (set_attr "trap_suffix" "u_su_sui")])
2969 (define_expand "multf3"
2970 [(use (match_operand 0 "register_operand" ""))
2971 (use (match_operand 1 "general_operand" ""))
2972 (use (match_operand 2 "general_operand" ""))]
2973 "TARGET_HAS_XFLOATING_LIBS"
2974 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2976 (define_insn "*subsf3_ieee"
2977 [(set (match_operand:SF 0 "register_operand" "=&f")
2978 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2979 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2980 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2981 "sub%,%/ %R1,%R2,%0"
2982 [(set_attr "type" "fadd")
2983 (set_attr "trap" "yes")
2984 (set_attr "round_suffix" "normal")
2985 (set_attr "trap_suffix" "u_su_sui")])
2987 (define_insn "subsf3"
2988 [(set (match_operand:SF 0 "register_operand" "=f")
2989 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2990 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2992 "sub%,%/ %R1,%R2,%0"
2993 [(set_attr "type" "fadd")
2994 (set_attr "trap" "yes")
2995 (set_attr "round_suffix" "normal")
2996 (set_attr "trap_suffix" "u_su_sui")])
2998 (define_insn "*subdf3_ieee"
2999 [(set (match_operand:DF 0 "register_operand" "=&f")
3000 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3001 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3002 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3003 "sub%-%/ %R1,%R2,%0"
3004 [(set_attr "type" "fadd")
3005 (set_attr "trap" "yes")
3006 (set_attr "round_suffix" "normal")
3007 (set_attr "trap_suffix" "u_su_sui")])
3009 (define_insn "subdf3"
3010 [(set (match_operand:DF 0 "register_operand" "=f")
3011 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3012 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3014 "sub%-%/ %R1,%R2,%0"
3015 [(set_attr "type" "fadd")
3016 (set_attr "trap" "yes")
3017 (set_attr "round_suffix" "normal")
3018 (set_attr "trap_suffix" "u_su_sui")])
3020 (define_insn "*subdf_ext1"
3021 [(set (match_operand:DF 0 "register_operand" "=f")
3022 (minus:DF (float_extend:DF
3023 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3024 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3025 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3026 "sub%-%/ %R1,%R2,%0"
3027 [(set_attr "type" "fadd")
3028 (set_attr "trap" "yes")
3029 (set_attr "round_suffix" "normal")
3030 (set_attr "trap_suffix" "u_su_sui")])
3032 (define_insn "*subdf_ext2"
3033 [(set (match_operand:DF 0 "register_operand" "=f")
3034 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3036 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3037 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3038 "sub%-%/ %R1,%R2,%0"
3039 [(set_attr "type" "fadd")
3040 (set_attr "trap" "yes")
3041 (set_attr "round_suffix" "normal")
3042 (set_attr "trap_suffix" "u_su_sui")])
3044 (define_insn "*subdf_ext3"
3045 [(set (match_operand:DF 0 "register_operand" "=f")
3046 (minus:DF (float_extend:DF
3047 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3049 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3050 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3051 "sub%-%/ %R1,%R2,%0"
3052 [(set_attr "type" "fadd")
3053 (set_attr "trap" "yes")
3054 (set_attr "round_suffix" "normal")
3055 (set_attr "trap_suffix" "u_su_sui")])
3057 (define_expand "subtf3"
3058 [(use (match_operand 0 "register_operand" ""))
3059 (use (match_operand 1 "general_operand" ""))
3060 (use (match_operand 2 "general_operand" ""))]
3061 "TARGET_HAS_XFLOATING_LIBS"
3062 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3064 (define_insn "*sqrtsf2_ieee"
3065 [(set (match_operand:SF 0 "register_operand" "=&f")
3066 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3067 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3069 [(set_attr "type" "fsqrt")
3070 (set_attr "opsize" "si")
3071 (set_attr "trap" "yes")
3072 (set_attr "round_suffix" "normal")
3073 (set_attr "trap_suffix" "u_su_sui")])
3075 (define_insn "sqrtsf2"
3076 [(set (match_operand:SF 0 "register_operand" "=f")
3077 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3078 "TARGET_FP && TARGET_FIX"
3080 [(set_attr "type" "fsqrt")
3081 (set_attr "opsize" "si")
3082 (set_attr "trap" "yes")
3083 (set_attr "round_suffix" "normal")
3084 (set_attr "trap_suffix" "u_su_sui")])
3086 (define_insn "*sqrtdf2_ieee"
3087 [(set (match_operand:DF 0 "register_operand" "=&f")
3088 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3089 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3091 [(set_attr "type" "fsqrt")
3092 (set_attr "trap" "yes")
3093 (set_attr "round_suffix" "normal")
3094 (set_attr "trap_suffix" "u_su_sui")])
3096 (define_insn "sqrtdf2"
3097 [(set (match_operand:DF 0 "register_operand" "=f")
3098 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3099 "TARGET_FP && TARGET_FIX"
3101 [(set_attr "type" "fsqrt")
3102 (set_attr "trap" "yes")
3103 (set_attr "round_suffix" "normal")
3104 (set_attr "trap_suffix" "u_su_sui")])
3106 ;; Next are all the integer comparisons, and conditional moves and branches
3107 ;; and some of the related define_expand's and define_split's.
3109 (define_insn "*setcc_internal"
3110 [(set (match_operand 0 "register_operand" "=r")
3111 (match_operator 1 "alpha_comparison_operator"
3112 [(match_operand:DI 2 "register_operand" "r")
3113 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3114 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3115 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3116 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3118 [(set_attr "type" "icmp")])
3120 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3121 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3123 (define_insn "*setcc_swapped_internal"
3124 [(set (match_operand 0 "register_operand" "=r")
3125 (match_operator 1 "alpha_swapped_comparison_operator"
3126 [(match_operand:DI 2 "register_operand" "r")
3127 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3128 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3129 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3130 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3132 [(set_attr "type" "icmp")])
3134 ;; Use match_operator rather than ne directly so that we can match
3135 ;; multiple integer modes.
3136 (define_insn "*setne_internal"
3137 [(set (match_operand 0 "register_operand" "=r")
3138 (match_operator 1 "signed_comparison_operator"
3139 [(match_operand:DI 2 "register_operand" "r")
3141 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3142 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3143 && GET_CODE (operands[1]) == NE
3144 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3146 [(set_attr "type" "icmp")])
3148 ;; The mode folding trick can't be used with const_int operands, since
3149 ;; reload needs to know the proper mode.
3151 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3152 ;; in order to create more pairs of constants. As long as we're allowing
3153 ;; two constants at the same time, and will have to reload one of them...
3155 (define_insn "*movqicc_internal"
3156 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3158 (match_operator 2 "signed_comparison_operator"
3159 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3160 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3161 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3162 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3163 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3169 [(set_attr "type" "icmov")])
3171 (define_insn "*movhicc_internal"
3172 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3174 (match_operator 2 "signed_comparison_operator"
3175 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3176 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3177 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3178 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3179 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3185 [(set_attr "type" "icmov")])
3187 (define_insn "*movsicc_internal"
3188 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3190 (match_operator 2 "signed_comparison_operator"
3191 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3192 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3193 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3194 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3195 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3201 [(set_attr "type" "icmov")])
3203 (define_insn "*movdicc_internal"
3204 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3206 (match_operator 2 "signed_comparison_operator"
3207 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3208 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3209 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3210 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3211 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3217 [(set_attr "type" "icmov")])
3219 (define_insn "*movqicc_lbc"
3220 [(set (match_operand:QI 0 "register_operand" "=r,r")
3222 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3226 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3227 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3232 [(set_attr "type" "icmov")])
3234 (define_insn "*movhicc_lbc"
3235 [(set (match_operand:HI 0 "register_operand" "=r,r")
3237 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3241 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3242 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3247 [(set_attr "type" "icmov")])
3249 (define_insn "*movsicc_lbc"
3250 [(set (match_operand:SI 0 "register_operand" "=r,r")
3252 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3256 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3257 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3262 [(set_attr "type" "icmov")])
3264 (define_insn "*movdicc_lbc"
3265 [(set (match_operand:DI 0 "register_operand" "=r,r")
3267 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3271 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3272 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3277 [(set_attr "type" "icmov")])
3279 (define_insn "*movqicc_lbs"
3280 [(set (match_operand:QI 0 "register_operand" "=r,r")
3282 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3286 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3287 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3292 [(set_attr "type" "icmov")])
3294 (define_insn "*movhicc_lbs"
3295 [(set (match_operand:HI 0 "register_operand" "=r,r")
3297 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3301 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3302 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3307 [(set_attr "type" "icmov")])
3309 (define_insn "*movsicc_lbs"
3310 [(set (match_operand:SI 0 "register_operand" "=r,r")
3312 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3316 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3317 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3322 [(set_attr "type" "icmov")])
3324 (define_insn "*movdicc_lbs"
3325 [(set (match_operand:DI 0 "register_operand" "=r,r")
3327 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3331 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3332 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3337 [(set_attr "type" "icmov")])
3339 ;; For ABS, we have two choices, depending on whether the input and output
3340 ;; registers are the same or not.
3341 (define_expand "absdi2"
3342 [(set (match_operand:DI 0 "register_operand" "")
3343 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3346 if (rtx_equal_p (operands[0], operands[1]))
3347 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3349 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3353 (define_expand "absdi2_same"
3354 [(set (match_operand:DI 1 "register_operand" "")
3355 (neg:DI (match_operand:DI 0 "register_operand" "")))
3357 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3363 (define_expand "absdi2_diff"
3364 [(set (match_operand:DI 0 "register_operand" "")
3365 (neg:DI (match_operand:DI 1 "register_operand" "")))
3367 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3374 [(set (match_operand:DI 0 "register_operand" "")
3375 (abs:DI (match_dup 0)))
3376 (clobber (match_operand:DI 1 "register_operand" ""))]
3378 [(set (match_dup 1) (neg:DI (match_dup 0)))
3379 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3380 (match_dup 0) (match_dup 1)))]
3384 [(set (match_operand:DI 0 "register_operand" "")
3385 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3386 "! rtx_equal_p (operands[0], operands[1])"
3387 [(set (match_dup 0) (neg:DI (match_dup 1)))
3388 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3389 (match_dup 0) (match_dup 1)))]
3393 [(set (match_operand:DI 0 "register_operand" "")
3394 (neg:DI (abs:DI (match_dup 0))))
3395 (clobber (match_operand:DI 1 "register_operand" ""))]
3397 [(set (match_dup 1) (neg:DI (match_dup 0)))
3398 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3399 (match_dup 0) (match_dup 1)))]
3403 [(set (match_operand:DI 0 "register_operand" "")
3404 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3405 "! rtx_equal_p (operands[0], operands[1])"
3406 [(set (match_dup 0) (neg:DI (match_dup 1)))
3407 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3408 (match_dup 0) (match_dup 1)))]
3411 (define_insn "sminqi3"
3412 [(set (match_operand:QI 0 "register_operand" "=r")
3413 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3414 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3417 [(set_attr "type" "mvi")])
3419 (define_insn "uminqi3"
3420 [(set (match_operand:QI 0 "register_operand" "=r")
3421 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3422 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3425 [(set_attr "type" "mvi")])
3427 (define_insn "smaxqi3"
3428 [(set (match_operand:QI 0 "register_operand" "=r")
3429 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3430 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3433 [(set_attr "type" "mvi")])
3435 (define_insn "umaxqi3"
3436 [(set (match_operand:QI 0 "register_operand" "=r")
3437 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3438 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3441 [(set_attr "type" "mvi")])
3443 (define_insn "sminhi3"
3444 [(set (match_operand:HI 0 "register_operand" "=r")
3445 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3446 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3449 [(set_attr "type" "mvi")])
3451 (define_insn "uminhi3"
3452 [(set (match_operand:HI 0 "register_operand" "=r")
3453 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3454 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3457 [(set_attr "type" "mvi")])
3459 (define_insn "smaxhi3"
3460 [(set (match_operand:HI 0 "register_operand" "=r")
3461 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3462 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3465 [(set_attr "type" "mvi")])
3467 (define_insn "umaxhi3"
3468 [(set (match_operand:HI 0 "register_operand" "=r")
3469 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3470 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3473 [(set_attr "type" "mvi")])
3475 (define_expand "smaxdi3"
3477 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3478 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3479 (set (match_operand:DI 0 "register_operand" "")
3480 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3481 (match_dup 1) (match_dup 2)))]
3483 { operands[3] = gen_reg_rtx (DImode); })
3486 [(set (match_operand:DI 0 "register_operand" "")
3487 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3488 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3489 (clobber (match_operand:DI 3 "register_operand" ""))]
3490 "operands[2] != const0_rtx"
3491 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3492 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3493 (match_dup 1) (match_dup 2)))]
3496 (define_insn "*smax_const0"
3497 [(set (match_operand:DI 0 "register_operand" "=r")
3498 (smax:DI (match_operand:DI 1 "register_operand" "0")
3502 [(set_attr "type" "icmov")])
3504 (define_expand "smindi3"
3506 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3507 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3508 (set (match_operand:DI 0 "register_operand" "")
3509 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3510 (match_dup 1) (match_dup 2)))]
3512 { operands[3] = gen_reg_rtx (DImode); })
3515 [(set (match_operand:DI 0 "register_operand" "")
3516 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3517 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3518 (clobber (match_operand:DI 3 "register_operand" ""))]
3519 "operands[2] != const0_rtx"
3520 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3521 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3522 (match_dup 1) (match_dup 2)))]
3525 (define_insn "*smin_const0"
3526 [(set (match_operand:DI 0 "register_operand" "=r")
3527 (smin:DI (match_operand:DI 1 "register_operand" "0")
3531 [(set_attr "type" "icmov")])
3533 (define_expand "umaxdi3"
3535 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3536 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3537 (set (match_operand:DI 0 "register_operand" "")
3538 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3539 (match_dup 1) (match_dup 2)))]
3541 "operands[3] = gen_reg_rtx (DImode);")
3544 [(set (match_operand:DI 0 "register_operand" "")
3545 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3546 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3547 (clobber (match_operand:DI 3 "register_operand" ""))]
3548 "operands[2] != const0_rtx"
3549 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3550 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3551 (match_dup 1) (match_dup 2)))]
3554 (define_expand "umindi3"
3556 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3557 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3558 (set (match_operand:DI 0 "register_operand" "")
3559 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3560 (match_dup 1) (match_dup 2)))]
3562 "operands[3] = gen_reg_rtx (DImode);")
3565 [(set (match_operand:DI 0 "register_operand" "")
3566 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3567 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3568 (clobber (match_operand:DI 3 "register_operand" ""))]
3569 "operands[2] != const0_rtx"
3570 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3571 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3572 (match_dup 1) (match_dup 2)))]
3575 (define_insn "*bcc_normal"
3578 (match_operator 1 "signed_comparison_operator"
3579 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3581 (label_ref (match_operand 0 "" ""))
3585 [(set_attr "type" "ibr")])
3587 (define_insn "*bcc_reverse"
3590 (match_operator 1 "signed_comparison_operator"
3591 [(match_operand:DI 2 "register_operand" "r")
3595 (label_ref (match_operand 0 "" ""))))]
3598 [(set_attr "type" "ibr")])
3600 (define_insn "*blbs_normal"
3603 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3607 (label_ref (match_operand 0 "" ""))
3611 [(set_attr "type" "ibr")])
3613 (define_insn "*blbc_normal"
3616 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3620 (label_ref (match_operand 0 "" ""))
3624 [(set_attr "type" "ibr")])
3630 (match_operator 1 "comparison_operator"
3631 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3633 (match_operand:DI 3 "const_int_operand" ""))
3635 (label_ref (match_operand 0 "" ""))
3637 (clobber (match_operand:DI 4 "register_operand" ""))])]
3638 "INTVAL (operands[3]) != 0"
3640 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3642 (if_then_else (match_op_dup 1
3643 [(zero_extract:DI (match_dup 4)
3647 (label_ref (match_dup 0))
3651 ;; The following are the corresponding floating-point insns. Recall
3652 ;; we need to have variants that expand the arguments from SFmode
3655 (define_insn "*cmpdf_ieee"
3656 [(set (match_operand:DF 0 "register_operand" "=&f")
3657 (match_operator:DF 1 "alpha_fp_comparison_operator"
3658 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3659 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3660 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3661 "cmp%-%C1%/ %R2,%R3,%0"
3662 [(set_attr "type" "fadd")
3663 (set_attr "trap" "yes")
3664 (set_attr "trap_suffix" "su")])
3666 (define_insn "*cmpdf_internal"
3667 [(set (match_operand:DF 0 "register_operand" "=f")
3668 (match_operator:DF 1 "alpha_fp_comparison_operator"
3669 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3670 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3671 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3672 "cmp%-%C1%/ %R2,%R3,%0"
3673 [(set_attr "type" "fadd")
3674 (set_attr "trap" "yes")
3675 (set_attr "trap_suffix" "su")])
3677 (define_insn "*cmpdf_ieee_ext1"
3678 [(set (match_operand:DF 0 "register_operand" "=&f")
3679 (match_operator:DF 1 "alpha_fp_comparison_operator"
3681 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3682 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3683 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3684 "cmp%-%C1%/ %R2,%R3,%0"
3685 [(set_attr "type" "fadd")
3686 (set_attr "trap" "yes")
3687 (set_attr "trap_suffix" "su")])
3689 (define_insn "*cmpdf_ext1"
3690 [(set (match_operand:DF 0 "register_operand" "=f")
3691 (match_operator:DF 1 "alpha_fp_comparison_operator"
3693 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3694 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3695 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3696 "cmp%-%C1%/ %R2,%R3,%0"
3697 [(set_attr "type" "fadd")
3698 (set_attr "trap" "yes")
3699 (set_attr "trap_suffix" "su")])
3701 (define_insn "*cmpdf_ieee_ext2"
3702 [(set (match_operand:DF 0 "register_operand" "=&f")
3703 (match_operator:DF 1 "alpha_fp_comparison_operator"
3704 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3706 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3707 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3708 "cmp%-%C1%/ %R2,%R3,%0"
3709 [(set_attr "type" "fadd")
3710 (set_attr "trap" "yes")
3711 (set_attr "trap_suffix" "su")])
3713 (define_insn "*cmpdf_ext2"
3714 [(set (match_operand:DF 0 "register_operand" "=f")
3715 (match_operator:DF 1 "alpha_fp_comparison_operator"
3716 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3718 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3719 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3720 "cmp%-%C1%/ %R2,%R3,%0"
3721 [(set_attr "type" "fadd")
3722 (set_attr "trap" "yes")
3723 (set_attr "trap_suffix" "su")])
3725 (define_insn "*cmpdf_ieee_ext3"
3726 [(set (match_operand:DF 0 "register_operand" "=&f")
3727 (match_operator:DF 1 "alpha_fp_comparison_operator"
3729 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3731 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3732 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3733 "cmp%-%C1%/ %R2,%R3,%0"
3734 [(set_attr "type" "fadd")
3735 (set_attr "trap" "yes")
3736 (set_attr "trap_suffix" "su")])
3738 (define_insn "*cmpdf_ext3"
3739 [(set (match_operand:DF 0 "register_operand" "=f")
3740 (match_operator:DF 1 "alpha_fp_comparison_operator"
3742 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3744 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3745 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3746 "cmp%-%C1%/ %R2,%R3,%0"
3747 [(set_attr "type" "fadd")
3748 (set_attr "trap" "yes")
3749 (set_attr "trap_suffix" "su")])
3751 (define_insn "*movdfcc_internal"
3752 [(set (match_operand:DF 0 "register_operand" "=f,f")
3754 (match_operator 3 "signed_comparison_operator"
3755 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3756 (match_operand:DF 2 "const0_operand" "G,G")])
3757 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3758 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3762 fcmov%D3 %R4,%R5,%0"
3763 [(set_attr "type" "fcmov")])
3765 (define_insn "*movsfcc_internal"
3766 [(set (match_operand:SF 0 "register_operand" "=f,f")
3768 (match_operator 3 "signed_comparison_operator"
3769 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3770 (match_operand:DF 2 "const0_operand" "G,G")])
3771 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3772 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3776 fcmov%D3 %R4,%R5,%0"
3777 [(set_attr "type" "fcmov")])
3779 (define_insn "*movdfcc_ext1"
3780 [(set (match_operand:DF 0 "register_operand" "=f,f")
3782 (match_operator 3 "signed_comparison_operator"
3783 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3784 (match_operand:DF 2 "const0_operand" "G,G")])
3785 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3786 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3790 fcmov%D3 %R4,%R5,%0"
3791 [(set_attr "type" "fcmov")])
3793 (define_insn "*movdfcc_ext2"
3794 [(set (match_operand:DF 0 "register_operand" "=f,f")
3796 (match_operator 3 "signed_comparison_operator"
3798 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3799 (match_operand:DF 2 "const0_operand" "G,G")])
3800 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3801 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3805 fcmov%D3 %R4,%R5,%0"
3806 [(set_attr "type" "fcmov")])
3808 (define_insn "*movdfcc_ext3"
3809 [(set (match_operand:SF 0 "register_operand" "=f,f")
3811 (match_operator 3 "signed_comparison_operator"
3813 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3814 (match_operand:DF 2 "const0_operand" "G,G")])
3815 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3816 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3820 fcmov%D3 %R4,%R5,%0"
3821 [(set_attr "type" "fcmov")])
3823 (define_insn "*movdfcc_ext4"
3824 [(set (match_operand:DF 0 "register_operand" "=f,f")
3826 (match_operator 3 "signed_comparison_operator"
3828 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3829 (match_operand:DF 2 "const0_operand" "G,G")])
3830 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3831 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3835 fcmov%D3 %R4,%R5,%0"
3836 [(set_attr "type" "fcmov")])
3838 (define_expand "smaxdf3"
3840 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3841 (match_operand:DF 2 "reg_or_0_operand" "")))
3842 (set (match_operand:DF 0 "register_operand" "")
3843 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3844 (match_dup 1) (match_dup 2)))]
3847 operands[3] = gen_reg_rtx (DFmode);
3848 operands[4] = CONST0_RTX (DFmode);
3851 (define_expand "smindf3"
3853 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3854 (match_operand:DF 2 "reg_or_0_operand" "")))
3855 (set (match_operand:DF 0 "register_operand" "")
3856 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3857 (match_dup 1) (match_dup 2)))]
3860 operands[3] = gen_reg_rtx (DFmode);
3861 operands[4] = CONST0_RTX (DFmode);
3864 (define_expand "smaxsf3"
3866 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3867 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3868 (set (match_operand:SF 0 "register_operand" "")
3869 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3870 (match_dup 1) (match_dup 2)))]
3873 operands[3] = gen_reg_rtx (DFmode);
3874 operands[4] = CONST0_RTX (DFmode);
3877 (define_expand "sminsf3"
3879 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3880 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3881 (set (match_operand:SF 0 "register_operand" "")
3882 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3883 (match_dup 1) (match_dup 2)))]
3886 operands[3] = gen_reg_rtx (DFmode);
3887 operands[4] = CONST0_RTX (DFmode);
3890 (define_insn "*fbcc_normal"
3893 (match_operator 1 "signed_comparison_operator"
3894 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3895 (match_operand:DF 3 "const0_operand" "G")])
3896 (label_ref (match_operand 0 "" ""))
3900 [(set_attr "type" "fbr")])
3902 (define_insn "*fbcc_ext_normal"
3905 (match_operator 1 "signed_comparison_operator"
3907 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3908 (match_operand:DF 3 "const0_operand" "G")])
3909 (label_ref (match_operand 0 "" ""))
3913 [(set_attr "type" "fbr")])
3915 ;; These are the main define_expand's used to make conditional branches
3918 (define_expand "cmpdf"
3919 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3920 (match_operand:DF 1 "reg_or_0_operand" "")))]
3923 alpha_compare.op0 = operands[0];
3924 alpha_compare.op1 = operands[1];
3925 alpha_compare.fp_p = 1;
3929 (define_expand "cmptf"
3930 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3931 (match_operand:TF 1 "general_operand" "")))]
3932 "TARGET_HAS_XFLOATING_LIBS"
3934 alpha_compare.op0 = operands[0];
3935 alpha_compare.op1 = operands[1];
3936 alpha_compare.fp_p = 1;
3940 (define_expand "cmpdi"
3941 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3942 (match_operand:DI 1 "some_operand" "")))]
3945 alpha_compare.op0 = operands[0];
3946 alpha_compare.op1 = operands[1];
3947 alpha_compare.fp_p = 0;
3951 (define_expand "beq"
3953 (if_then_else (match_dup 1)
3954 (label_ref (match_operand 0 "" ""))
3957 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3959 (define_expand "bne"
3961 (if_then_else (match_dup 1)
3962 (label_ref (match_operand 0 "" ""))
3965 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3967 (define_expand "blt"
3969 (if_then_else (match_dup 1)
3970 (label_ref (match_operand 0 "" ""))
3973 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3975 (define_expand "ble"
3977 (if_then_else (match_dup 1)
3978 (label_ref (match_operand 0 "" ""))
3981 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3983 (define_expand "bgt"
3985 (if_then_else (match_dup 1)
3986 (label_ref (match_operand 0 "" ""))
3989 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3991 (define_expand "bge"
3993 (if_then_else (match_dup 1)
3994 (label_ref (match_operand 0 "" ""))
3997 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3999 (define_expand "bltu"
4001 (if_then_else (match_dup 1)
4002 (label_ref (match_operand 0 "" ""))
4005 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4007 (define_expand "bleu"
4009 (if_then_else (match_dup 1)
4010 (label_ref (match_operand 0 "" ""))
4013 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4015 (define_expand "bgtu"
4017 (if_then_else (match_dup 1)
4018 (label_ref (match_operand 0 "" ""))
4021 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4023 (define_expand "bgeu"
4025 (if_then_else (match_dup 1)
4026 (label_ref (match_operand 0 "" ""))
4029 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4031 (define_expand "bunordered"
4033 (if_then_else (match_dup 1)
4034 (label_ref (match_operand 0 "" ""))
4037 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4039 (define_expand "bordered"
4041 (if_then_else (match_dup 1)
4042 (label_ref (match_operand 0 "" ""))
4045 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4047 (define_expand "seq"
4048 [(set (match_operand:DI 0 "register_operand" "")
4051 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4053 (define_expand "sne"
4054 [(set (match_operand:DI 0 "register_operand" "")
4057 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4059 (define_expand "slt"
4060 [(set (match_operand:DI 0 "register_operand" "")
4063 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4065 (define_expand "sle"
4066 [(set (match_operand:DI 0 "register_operand" "")
4069 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4071 (define_expand "sgt"
4072 [(set (match_operand:DI 0 "register_operand" "")
4075 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4077 (define_expand "sge"
4078 [(set (match_operand:DI 0 "register_operand" "")
4081 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4083 (define_expand "sltu"
4084 [(set (match_operand:DI 0 "register_operand" "")
4087 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4089 (define_expand "sleu"
4090 [(set (match_operand:DI 0 "register_operand" "")
4093 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4095 (define_expand "sgtu"
4096 [(set (match_operand:DI 0 "register_operand" "")
4099 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4101 (define_expand "sgeu"
4102 [(set (match_operand:DI 0 "register_operand" "")
4105 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4107 (define_expand "sunordered"
4108 [(set (match_operand:DI 0 "register_operand" "")
4111 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4113 (define_expand "sordered"
4114 [(set (match_operand:DI 0 "register_operand" "")
4117 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4119 ;; These are the main define_expand's used to make conditional moves.
4121 (define_expand "movsicc"
4122 [(set (match_operand:SI 0 "register_operand" "")
4123 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4124 (match_operand:SI 2 "reg_or_8bit_operand" "")
4125 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4128 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4132 (define_expand "movdicc"
4133 [(set (match_operand:DI 0 "register_operand" "")
4134 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4135 (match_operand:DI 2 "reg_or_8bit_operand" "")
4136 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4139 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4143 (define_expand "movsfcc"
4144 [(set (match_operand:SF 0 "register_operand" "")
4145 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4146 (match_operand:SF 2 "reg_or_8bit_operand" "")
4147 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4150 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4154 (define_expand "movdfcc"
4155 [(set (match_operand:DF 0 "register_operand" "")
4156 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4157 (match_operand:DF 2 "reg_or_8bit_operand" "")
4158 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4161 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4165 ;; These define_split definitions are used in cases when comparisons have
4166 ;; not be stated in the correct way and we need to reverse the second
4167 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4168 ;; comparison that tests the result being reversed. We have one define_split
4169 ;; for each use of a comparison. They do not match valid insns and need
4170 ;; not generate valid insns.
4172 ;; We can also handle equality comparisons (and inequality comparisons in
4173 ;; cases where the resulting add cannot overflow) by doing an add followed by
4174 ;; a comparison with zero. This is faster since the addition takes one
4175 ;; less cycle than a compare when feeding into a conditional move.
4176 ;; For this case, we also have an SImode pattern since we can merge the add
4177 ;; and sign extend and the order doesn't matter.
4179 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4180 ;; operation could have been generated.
4183 [(set (match_operand:DI 0 "register_operand" "")
4185 (match_operator 1 "comparison_operator"
4186 [(match_operand:DI 2 "reg_or_0_operand" "")
4187 (match_operand:DI 3 "reg_or_cint_operand" "")])
4188 (match_operand:DI 4 "reg_or_cint_operand" "")
4189 (match_operand:DI 5 "reg_or_cint_operand" "")))
4190 (clobber (match_operand:DI 6 "register_operand" ""))]
4191 "operands[3] != const0_rtx"
4192 [(set (match_dup 6) (match_dup 7))
4194 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4196 enum rtx_code code = GET_CODE (operands[1]);
4197 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4199 /* If we are comparing for equality with a constant and that constant
4200 appears in the arm when the register equals the constant, use the
4201 register since that is more likely to match (and to produce better code
4204 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4205 && rtx_equal_p (operands[4], operands[3]))
4206 operands[4] = operands[2];
4208 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4209 && rtx_equal_p (operands[5], operands[3]))
4210 operands[5] = operands[2];
4212 if (code == NE || code == EQ
4213 || (extended_count (operands[2], DImode, unsignedp) >= 1
4214 && extended_count (operands[3], DImode, unsignedp) >= 1))
4216 if (GET_CODE (operands[3]) == CONST_INT)
4217 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4218 GEN_INT (- INTVAL (operands[3])));
4220 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4222 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4225 else if (code == EQ || code == LE || code == LT
4226 || code == LEU || code == LTU)
4228 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4229 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4233 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4234 operands[2], operands[3]);
4235 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4240 [(set (match_operand:DI 0 "register_operand" "")
4242 (match_operator 1 "comparison_operator"
4243 [(match_operand:SI 2 "reg_or_0_operand" "")
4244 (match_operand:SI 3 "reg_or_cint_operand" "")])
4245 (match_operand:DI 4 "reg_or_8bit_operand" "")
4246 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4247 (clobber (match_operand:DI 6 "register_operand" ""))]
4248 "operands[3] != const0_rtx
4249 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4250 [(set (match_dup 6) (match_dup 7))
4252 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4254 enum rtx_code code = GET_CODE (operands[1]);
4255 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4258 if ((code != NE && code != EQ
4259 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4260 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4263 if (GET_CODE (operands[3]) == CONST_INT)
4264 tem = gen_rtx_PLUS (SImode, operands[2],
4265 GEN_INT (- INTVAL (operands[3])));
4267 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4269 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4270 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4271 operands[6], const0_rtx);
4274 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4277 [(set (match_operand 0 "register_operand" "")
4278 (if_then_else (match_operator 1 "signed_comparison_operator"
4279 [(match_operand:DI 2 "reg_or_0_operand" "")
4281 (match_operand 3 "const_int_operand" "")
4282 (match_operand 4 "const_int_operand" "")))]
4286 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4287 operands[2], operands[3], operands[4]))
4293 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4294 ;; Oh well, we match it in movcc, so it must be partially our fault.
4296 [(set (match_operand 0 "register_operand" "")
4297 (if_then_else (match_operator 1 "signed_comparison_operator"
4299 (match_operand:DI 2 "reg_or_0_operand" "")])
4300 (match_operand 3 "const_int_operand" "")
4301 (match_operand 4 "const_int_operand" "")))]
4305 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4306 operands[0], operands[2], operands[3],
4313 (define_insn_and_split "*cmp_sadd_di"
4314 [(set (match_operand:DI 0 "register_operand" "=r")
4315 (plus:DI (if_then_else:DI
4316 (match_operator 1 "alpha_zero_comparison_operator"
4317 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4319 (match_operand:DI 3 "const48_operand" "I")
4321 (match_operand:DI 4 "sext_add_operand" "rIO")))
4322 (clobber (match_scratch:DI 5 "=r"))]
4325 "! no_new_pseudos || reload_completed"
4327 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4329 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4332 if (! no_new_pseudos)
4333 operands[5] = gen_reg_rtx (DImode);
4334 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4335 operands[5] = operands[0];
4338 (define_insn_and_split "*cmp_sadd_si"
4339 [(set (match_operand:SI 0 "register_operand" "=r")
4340 (plus:SI (if_then_else:SI
4341 (match_operator 1 "alpha_zero_comparison_operator"
4342 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4344 (match_operand:SI 3 "const48_operand" "I")
4346 (match_operand:SI 4 "sext_add_operand" "rIO")))
4347 (clobber (match_scratch:SI 5 "=r"))]
4350 "! no_new_pseudos || reload_completed"
4352 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4354 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4357 if (! no_new_pseudos)
4358 operands[5] = gen_reg_rtx (DImode);
4359 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4360 operands[5] = operands[0];
4363 (define_insn_and_split "*cmp_sadd_sidi"
4364 [(set (match_operand:DI 0 "register_operand" "=r")
4366 (plus:SI (if_then_else:SI
4367 (match_operator 1 "alpha_zero_comparison_operator"
4368 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4370 (match_operand:SI 3 "const48_operand" "I")
4372 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4373 (clobber (match_scratch:SI 5 "=r"))]
4376 "! no_new_pseudos || reload_completed"
4378 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4380 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4383 if (! no_new_pseudos)
4384 operands[5] = gen_reg_rtx (DImode);
4385 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4386 operands[5] = operands[0];
4389 (define_insn_and_split "*cmp_ssub_di"
4390 [(set (match_operand:DI 0 "register_operand" "=r")
4391 (minus:DI (if_then_else:DI
4392 (match_operator 1 "alpha_zero_comparison_operator"
4393 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4395 (match_operand:DI 3 "const48_operand" "I")
4397 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4398 (clobber (match_scratch:DI 5 "=r"))]
4401 "! no_new_pseudos || reload_completed"
4403 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4405 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4408 if (! no_new_pseudos)
4409 operands[5] = gen_reg_rtx (DImode);
4410 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4411 operands[5] = operands[0];
4414 (define_insn_and_split "*cmp_ssub_si"
4415 [(set (match_operand:SI 0 "register_operand" "=r")
4416 (minus:SI (if_then_else:SI
4417 (match_operator 1 "alpha_zero_comparison_operator"
4418 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4420 (match_operand:SI 3 "const48_operand" "I")
4422 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4423 (clobber (match_scratch:SI 5 "=r"))]
4426 "! no_new_pseudos || reload_completed"
4428 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4430 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4433 if (! no_new_pseudos)
4434 operands[5] = gen_reg_rtx (DImode);
4435 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4436 operands[5] = operands[0];
4439 (define_insn_and_split "*cmp_ssub_sidi"
4440 [(set (match_operand:DI 0 "register_operand" "=r")
4442 (minus:SI (if_then_else:SI
4443 (match_operator 1 "alpha_zero_comparison_operator"
4444 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4446 (match_operand:SI 3 "const48_operand" "I")
4448 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4449 (clobber (match_scratch:SI 5 "=r"))]
4452 "! no_new_pseudos || reload_completed"
4454 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4456 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4459 if (! no_new_pseudos)
4460 operands[5] = gen_reg_rtx (DImode);
4461 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4462 operands[5] = operands[0];
4465 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4466 ;; work differently, so we have different patterns for each.
4468 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4469 ;; call. The CIW contains information about arguments passed in registers
4470 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4471 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4472 ;; in the presence of inlining since the CIWs for calls performed by the
4473 ;; inlined function must be stored in the SSIB of the function it is inlined
4474 ;; into as well. We encode the CIW in an unspec and append it to the list
4475 ;; of the CIWs for the current function only when the instruction for loading
4476 ;; $25 is generated.
4478 (define_expand "call"
4479 [(use (match_operand:DI 0 "" ""))
4480 (use (match_operand 1 "" ""))
4481 (use (match_operand 2 "" ""))
4482 (use (match_operand 3 "" ""))]
4485 if (TARGET_ABI_WINDOWS_NT)
4486 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4487 else if (TARGET_ABI_OPEN_VMS)
4488 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4489 else if (TARGET_ABI_UNICOSMK)
4490 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4492 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4496 (define_expand "sibcall"
4497 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4498 (match_operand 1 "" ""))
4499 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4502 gcc_assert (GET_CODE (operands[0]) == MEM);
4503 operands[0] = XEXP (operands[0], 0);
4506 (define_expand "call_osf"
4507 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4508 (match_operand 1 "" ""))
4510 (clobber (reg:DI 26))])]
4513 gcc_assert (GET_CODE (operands[0]) == MEM);
4515 operands[0] = XEXP (operands[0], 0);
4516 if (! call_operand (operands[0], Pmode))
4517 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4520 (define_expand "call_nt"
4521 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4522 (match_operand 1 "" ""))
4523 (clobber (reg:DI 26))])]
4526 gcc_assert (GET_CODE (operands[0]) == MEM);
4528 operands[0] = XEXP (operands[0], 0);
4529 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4530 operands[0] = force_reg (DImode, operands[0]);
4533 ;; Calls on Unicos/Mk are always indirect.
4534 ;; op 0: symbol ref for called function
4535 ;; op 1: CIW for $25 represented by an unspec
4537 (define_expand "call_umk"
4538 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4539 (match_operand 1 "" ""))
4541 (clobber (reg:DI 26))])]
4544 gcc_assert (GET_CODE (operands[0]) == MEM);
4546 /* Always load the address of the called function into a register;
4547 load the CIW in $25. */
4549 operands[0] = XEXP (operands[0], 0);
4550 if (GET_CODE (operands[0]) != REG)
4551 operands[0] = force_reg (DImode, operands[0]);
4553 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4557 ;; call openvms/alpha
4558 ;; op 0: symbol ref for called function
4559 ;; op 1: next_arg_reg (argument information value for R25)
4561 (define_expand "call_vms"
4562 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4563 (match_operand 1 "" ""))
4567 (clobber (reg:DI 27))])]
4570 gcc_assert (GET_CODE (operands[0]) == MEM);
4572 operands[0] = XEXP (operands[0], 0);
4574 /* Always load AI with argument information, then handle symbolic and
4575 indirect call differently. Load RA and set operands[2] to PV in
4578 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4579 if (GET_CODE (operands[0]) == SYMBOL_REF)
4581 alpha_need_linkage (XSTR (operands[0], 0), 0);
4583 operands[2] = const0_rtx;
4587 emit_move_insn (gen_rtx_REG (Pmode, 26),
4588 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4589 operands[2] = operands[0];
4594 (define_expand "call_value"
4595 [(use (match_operand 0 "" ""))
4596 (use (match_operand:DI 1 "" ""))
4597 (use (match_operand 2 "" ""))
4598 (use (match_operand 3 "" ""))
4599 (use (match_operand 4 "" ""))]
4602 if (TARGET_ABI_WINDOWS_NT)
4603 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4604 else if (TARGET_ABI_OPEN_VMS)
4605 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4607 else if (TARGET_ABI_UNICOSMK)
4608 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4611 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4616 (define_expand "sibcall_value"
4617 [(parallel [(set (match_operand 0 "" "")
4618 (call (mem:DI (match_operand 1 "" ""))
4619 (match_operand 2 "" "")))
4620 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4623 gcc_assert (GET_CODE (operands[1]) == MEM);
4624 operands[1] = XEXP (operands[1], 0);
4627 (define_expand "call_value_osf"
4628 [(parallel [(set (match_operand 0 "" "")
4629 (call (mem:DI (match_operand 1 "" ""))
4630 (match_operand 2 "" "")))
4632 (clobber (reg:DI 26))])]
4635 gcc_assert (GET_CODE (operands[1]) == MEM);
4637 operands[1] = XEXP (operands[1], 0);
4638 if (! call_operand (operands[1], Pmode))
4639 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4642 (define_expand "call_value_nt"
4643 [(parallel [(set (match_operand 0 "" "")
4644 (call (mem:DI (match_operand 1 "" ""))
4645 (match_operand 2 "" "")))
4646 (clobber (reg:DI 26))])]
4649 gcc_assert (GET_CODE (operands[1]) == MEM);
4651 operands[1] = XEXP (operands[1], 0);
4652 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4653 operands[1] = force_reg (DImode, operands[1]);
4656 (define_expand "call_value_vms"
4657 [(parallel [(set (match_operand 0 "" "")
4658 (call (mem:DI (match_operand:DI 1 "" ""))
4659 (match_operand 2 "" "")))
4663 (clobber (reg:DI 27))])]
4666 gcc_assert (GET_CODE (operands[1]) == MEM);
4668 operands[1] = XEXP (operands[1], 0);
4670 /* Always load AI with argument information, then handle symbolic and
4671 indirect call differently. Load RA and set operands[3] to PV in
4674 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4675 if (GET_CODE (operands[1]) == SYMBOL_REF)
4677 alpha_need_linkage (XSTR (operands[1], 0), 0);
4679 operands[3] = const0_rtx;
4683 emit_move_insn (gen_rtx_REG (Pmode, 26),
4684 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4685 operands[3] = operands[1];
4689 (define_expand "call_value_umk"
4690 [(parallel [(set (match_operand 0 "" "")
4691 (call (mem:DI (match_operand 1 "" ""))
4692 (match_operand 2 "" "")))
4694 (clobber (reg:DI 26))])]
4697 gcc_assert (GET_CODE (operands[1]) == MEM);
4699 operands[1] = XEXP (operands[1], 0);
4700 if (GET_CODE (operands[1]) != REG)
4701 operands[1] = force_reg (DImode, operands[1]);
4703 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4706 (define_insn "*call_osf_1_er"
4707 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4708 (match_operand 1 "" ""))
4710 (clobber (reg:DI 26))]
4711 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4713 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4714 bsr $26,%0\t\t!samegp
4715 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4716 [(set_attr "type" "jsr")
4717 (set_attr "length" "12,*,16")])
4719 ;; We must use peep2 instead of a split because we need accurate life
4720 ;; information for $gp. Consider the case of { bar(); while (1); }.
4722 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4723 (match_operand 1 "" ""))
4725 (clobber (reg:DI 26))])]
4726 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4727 && ! samegp_function_operand (operands[0], Pmode)
4728 && (peep2_regno_dead_p (1, 29)
4729 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4730 [(parallel [(call (mem:DI (match_dup 2))
4732 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4733 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4735 (use (match_dup 3))])]
4737 if (CONSTANT_P (operands[0]))
4739 operands[2] = gen_rtx_REG (Pmode, 27);
4740 operands[3] = GEN_INT (alpha_next_sequence_number++);
4741 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4742 operands[0], operands[3]));
4746 operands[2] = operands[0];
4747 operands[0] = const0_rtx;
4748 operands[3] = const0_rtx;
4753 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4754 (match_operand 1 "" ""))
4756 (clobber (reg:DI 26))])]
4757 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4758 && ! samegp_function_operand (operands[0], Pmode)
4759 && ! (peep2_regno_dead_p (1, 29)
4760 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4761 [(parallel [(call (mem:DI (match_dup 2))
4763 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4764 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4766 (use (match_dup 4))])
4768 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4770 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4772 if (CONSTANT_P (operands[0]))
4774 operands[2] = gen_rtx_REG (Pmode, 27);
4775 operands[4] = GEN_INT (alpha_next_sequence_number++);
4776 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4777 operands[0], operands[4]));
4781 operands[2] = operands[0];
4782 operands[0] = const0_rtx;
4783 operands[4] = const0_rtx;
4785 operands[3] = GEN_INT (alpha_next_sequence_number++);
4788 ;; We add a blockage unspec_volatile to prevent insns from moving down
4789 ;; from above the call to in between the call and the ldah gpdisp.
4791 (define_insn "*call_osf_2_er"
4792 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4793 (match_operand 1 "" ""))
4794 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4795 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4796 (use (match_operand 2 "" ""))
4797 (use (match_operand 3 "const_int_operand" ""))]
4798 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4799 "jsr $26,(%0),%2%J3"
4800 [(set_attr "type" "jsr")
4801 (set_attr "cannot_copy" "true")])
4803 ;; We output a nop after noreturn calls at the very end of the function to
4804 ;; ensure that the return address always remains in the caller's code range,
4805 ;; as not doing so might confuse unwinding engines.
4807 ;; The potential change in insn length is not reflected in the length
4808 ;; attributes at this stage. Since the extra space is only actually added at
4809 ;; the very end of the compilation process (via final/print_operand), it
4810 ;; really seems harmless and not worth the trouble of some extra computation
4811 ;; cost and complexity.
4813 (define_insn "*call_osf_1_noreturn"
4814 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4815 (match_operand 1 "" ""))
4817 (clobber (reg:DI 26))]
4818 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4819 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4824 [(set_attr "type" "jsr")
4825 (set_attr "length" "*,*,8")])
4827 (define_insn "*call_osf_1"
4828 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4829 (match_operand 1 "" ""))
4831 (clobber (reg:DI 26))]
4832 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4834 jsr $26,($27),0\;ldgp $29,0($26)
4836 jsr $26,%0\;ldgp $29,0($26)"
4837 [(set_attr "type" "jsr")
4838 (set_attr "length" "12,*,16")])
4840 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4841 ;; doesn't do what we want.
4842 (define_insn "*sibcall_osf_1_er"
4843 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4844 (match_operand 1 "" ""))
4845 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4846 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4848 br $31,%0\t\t!samegp
4849 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4850 [(set_attr "type" "jsr")
4851 (set_attr "length" "*,8")])
4853 (define_insn "*sibcall_osf_1"
4854 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4855 (match_operand 1 "" ""))
4856 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4857 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4860 lda $27,%0\;jmp $31,($27),%0"
4861 [(set_attr "type" "jsr")
4862 (set_attr "length" "*,8")])
4864 (define_insn "*call_nt_1"
4865 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4866 (match_operand 1 "" ""))
4867 (clobber (reg:DI 26))]
4868 "TARGET_ABI_WINDOWS_NT"
4873 [(set_attr "type" "jsr")
4874 (set_attr "length" "*,*,12")])
4876 ; GAS relies on the order and position of instructions output below in order
4877 ; to generate relocs for VMS link to potentially optimize the call.
4878 ; Please do not molest.
4879 (define_insn "*call_vms_1"
4880 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4881 (match_operand 1 "" ""))
4882 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4885 (clobber (reg:DI 27))]
4886 "TARGET_ABI_OPEN_VMS"
4888 switch (which_alternative)
4891 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4893 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4894 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4895 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4900 [(set_attr "type" "jsr")
4901 (set_attr "length" "12,16")])
4903 (define_insn "*call_umk_1"
4904 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4905 (match_operand 1 "" ""))
4907 (clobber (reg:DI 26))]
4908 "TARGET_ABI_UNICOSMK"
4910 [(set_attr "type" "jsr")])
4912 ;; Call subroutine returning any type.
4914 (define_expand "untyped_call"
4915 [(parallel [(call (match_operand 0 "" "")
4917 (match_operand 1 "" "")
4918 (match_operand 2 "" "")])]
4923 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4925 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4927 rtx set = XVECEXP (operands[2], 0, i);
4928 emit_move_insn (SET_DEST (set), SET_SRC (set));
4931 /* The optimizer does not know that the call sets the function value
4932 registers we stored in the result block. We avoid problems by
4933 claiming that all hard registers are used and clobbered at this
4935 emit_insn (gen_blockage ());
4940 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4941 ;; all of memory. This blocks insns from being moved across this point.
4943 (define_insn "blockage"
4944 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4947 [(set_attr "length" "0")
4948 (set_attr "type" "none")])
4952 (label_ref (match_operand 0 "" "")))]
4955 [(set_attr "type" "ibr")])
4957 (define_expand "return"
4962 (define_insn "*return_internal"
4966 [(set_attr "type" "ibr")])
4968 (define_insn "indirect_jump"
4969 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4972 [(set_attr "type" "ibr")])
4974 (define_expand "tablejump"
4975 [(parallel [(set (pc)
4976 (match_operand 0 "register_operand" ""))
4977 (use (label_ref:DI (match_operand 1 "" "")))])]
4980 if (TARGET_ABI_WINDOWS_NT)
4982 rtx dest = gen_reg_rtx (DImode);
4983 emit_insn (gen_extendsidi2 (dest, operands[0]));
4986 else if (TARGET_ABI_OSF)
4988 rtx dest = gen_reg_rtx (DImode);
4989 emit_insn (gen_extendsidi2 (dest, operands[0]));
4990 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4995 (define_insn "*tablejump_osf_nt_internal"
4997 (match_operand:DI 0 "register_operand" "r"))
4998 (use (label_ref:DI (match_operand 1 "" "")))]
4999 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5000 && alpha_tablejump_addr_vec (insn)"
5002 operands[2] = alpha_tablejump_best_label (insn);
5003 return "jmp $31,(%0),%2";
5005 [(set_attr "type" "ibr")])
5007 (define_insn "*tablejump_internal"
5009 (match_operand:DI 0 "register_operand" "r"))
5010 (use (label_ref (match_operand 1 "" "")))]
5013 [(set_attr "type" "ibr")])
5015 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5016 ;; want to have to include pal.h in our .s file.
5018 ;; Technically the type for call_pal is jsr, but we use that for determining
5019 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5022 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5025 [(set_attr "type" "callpal")])
5027 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5028 ;; NT does not document anything at 0x81 -- presumably it would generate
5029 ;; the equivalent of SIGILL, but this isn't that important.
5030 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5032 [(trap_if (const_int 1) (const_int 0))]
5033 "!TARGET_ABI_WINDOWS_NT"
5035 [(set_attr "type" "callpal")])
5037 ;; For userland, we load the thread pointer from the TCB.
5038 ;; For the kernel, we load the per-cpu private value.
5040 (define_insn "load_tp"
5041 [(set (match_operand:DI 0 "register_operand" "=v")
5042 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5045 if (TARGET_TLS_KERNEL)
5046 return "call_pal 0x32";
5048 return "call_pal 0x9e";
5050 [(set_attr "type" "callpal")])
5052 ;; For completeness, and possibly a __builtin function, here's how to
5053 ;; set the thread pointer. Since we don't describe enough of this
5054 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5055 ;; not much point in creating an R16_REG register class.
5057 (define_expand "set_tp"
5058 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5059 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5063 (define_insn "*set_tp"
5064 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5067 if (TARGET_TLS_KERNEL)
5068 return "call_pal 0x31";
5070 return "call_pal 0x9f";
5072 [(set_attr "type" "callpal")])
5074 ;; Finally, we have the basic data motion insns. The byte and word insns
5075 ;; are done via define_expand. Start with the floating-point insns, since
5076 ;; they are simpler.
5078 (define_insn "*movsf_nofix"
5079 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5080 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5081 "TARGET_FPREGS && ! TARGET_FIX
5082 && (register_operand (operands[0], SFmode)
5083 || reg_or_0_operand (operands[1], SFmode))"
5091 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5093 (define_insn "*movsf_fix"
5094 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5095 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5096 "TARGET_FPREGS && TARGET_FIX
5097 && (register_operand (operands[0], SFmode)
5098 || reg_or_0_operand (operands[1], SFmode))"
5108 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5110 (define_insn "*movsf_nofp"
5111 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5112 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5114 && (register_operand (operands[0], SFmode)
5115 || reg_or_0_operand (operands[1], SFmode))"
5120 [(set_attr "type" "ilog,ild,ist")])
5122 (define_insn "*movdf_nofix"
5123 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5124 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5125 "TARGET_FPREGS && ! TARGET_FIX
5126 && (register_operand (operands[0], DFmode)
5127 || reg_or_0_operand (operands[1], DFmode))"
5135 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5137 (define_insn "*movdf_fix"
5138 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5139 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5140 "TARGET_FPREGS && TARGET_FIX
5141 && (register_operand (operands[0], DFmode)
5142 || reg_or_0_operand (operands[1], DFmode))"
5152 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5154 (define_insn "*movdf_nofp"
5155 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5156 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5158 && (register_operand (operands[0], DFmode)
5159 || reg_or_0_operand (operands[1], DFmode))"
5164 [(set_attr "type" "ilog,ild,ist")])
5166 ;; Subregs suck for register allocation. Pretend we can move TFmode
5167 ;; data between general registers until after reload.
5169 (define_insn_and_split "*movtf_internal"
5170 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5171 (match_operand:TF 1 "input_operand" "roG,rG"))]
5172 "register_operand (operands[0], TFmode)
5173 || reg_or_0_operand (operands[1], TFmode)"
5176 [(set (match_dup 0) (match_dup 2))
5177 (set (match_dup 1) (match_dup 3))]
5179 alpha_split_tmode_pair (operands, TFmode, true);
5182 (define_expand "movsf"
5183 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5184 (match_operand:SF 1 "general_operand" ""))]
5187 if (GET_CODE (operands[0]) == MEM
5188 && ! reg_or_0_operand (operands[1], SFmode))
5189 operands[1] = force_reg (SFmode, operands[1]);
5192 (define_expand "movdf"
5193 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5194 (match_operand:DF 1 "general_operand" ""))]
5197 if (GET_CODE (operands[0]) == MEM
5198 && ! reg_or_0_operand (operands[1], DFmode))
5199 operands[1] = force_reg (DFmode, operands[1]);
5202 (define_expand "movtf"
5203 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5204 (match_operand:TF 1 "general_operand" ""))]
5207 if (GET_CODE (operands[0]) == MEM
5208 && ! reg_or_0_operand (operands[1], TFmode))
5209 operands[1] = force_reg (TFmode, operands[1]);
5212 (define_insn "*movsi"
5213 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5214 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5215 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5216 && (register_operand (operands[0], SImode)
5217 || reg_or_0_operand (operands[1], SImode))"
5225 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5227 (define_insn "*movsi_nt_vms"
5228 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5229 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5230 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5231 && (register_operand (operands[0], SImode)
5232 || reg_or_0_operand (operands[1], SImode))"
5241 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5243 (define_insn "*movhi_nobwx"
5244 [(set (match_operand:HI 0 "register_operand" "=r,r")
5245 (match_operand:HI 1 "input_operand" "rJ,n"))]
5247 && (register_operand (operands[0], HImode)
5248 || register_operand (operands[1], HImode))"
5252 [(set_attr "type" "ilog,iadd")])
5254 (define_insn "*movhi_bwx"
5255 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5256 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5258 && (register_operand (operands[0], HImode)
5259 || reg_or_0_operand (operands[1], HImode))"
5265 [(set_attr "type" "ilog,iadd,ild,ist")])
5267 (define_insn "*movqi_nobwx"
5268 [(set (match_operand:QI 0 "register_operand" "=r,r")
5269 (match_operand:QI 1 "input_operand" "rJ,n"))]
5271 && (register_operand (operands[0], QImode)
5272 || register_operand (operands[1], QImode))"
5276 [(set_attr "type" "ilog,iadd")])
5278 (define_insn "*movqi_bwx"
5279 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5280 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5282 && (register_operand (operands[0], QImode)
5283 || reg_or_0_operand (operands[1], QImode))"
5289 [(set_attr "type" "ilog,iadd,ild,ist")])
5291 ;; We do two major things here: handle mem->mem and construct long
5294 (define_expand "movsi"
5295 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5296 (match_operand:SI 1 "general_operand" ""))]
5299 if (alpha_expand_mov (SImode, operands))
5303 ;; Split a load of a large constant into the appropriate two-insn
5307 [(set (match_operand:SI 0 "register_operand" "")
5308 (match_operand:SI 1 "non_add_const_operand" ""))]
5312 if (alpha_split_const_mov (SImode, operands))
5318 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5319 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5320 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5321 ;; notes and update LABEL_NUSES because this is not done automatically.
5322 ;; Labels may be incorrectly deleted if we don't do this.
5324 ;; Describing what the individual instructions do correctly is too complicated
5325 ;; so use UNSPECs for each of the three parts of an address.
5328 [(set (match_operand:DI 0 "register_operand" "")
5329 (match_operand:DI 1 "symbolic_operand" ""))]
5330 "TARGET_ABI_UNICOSMK && reload_completed"
5333 rtx insn1, insn2, insn3;
5335 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5336 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5337 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5338 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5339 set_unique_reg_note (insn3, REG_EQUAL, operands[1]);
5341 if (GET_CODE (operands[1]) == LABEL_REF)
5345 label = XEXP (operands[1], 0);
5346 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5348 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5350 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5352 LABEL_NUSES (label) += 3;
5357 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5359 (define_insn "umk_laum"
5360 [(set (match_operand:DI 0 "register_operand" "=r")
5361 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5363 "TARGET_ABI_UNICOSMK"
5365 [(set_attr "type" "iadd")])
5367 (define_insn "umk_lalm"
5368 [(set (match_operand:DI 0 "register_operand" "=r")
5369 (plus:DI (match_operand:DI 1 "register_operand" "r")
5370 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5372 "TARGET_ABI_UNICOSMK"
5374 [(set_attr "type" "iadd")])
5376 (define_insn "umk_lal"
5377 [(set (match_operand:DI 0 "register_operand" "=r")
5378 (plus:DI (match_operand:DI 1 "register_operand" "r")
5379 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5381 "TARGET_ABI_UNICOSMK"
5383 [(set_attr "type" "iadd")])
5385 ;; Add a new call information word to the current function's list of CIWs
5386 ;; and load its index into $25. Doing it here ensures that the CIW will be
5387 ;; associated with the correct function even in the presence of inlining.
5389 (define_insn "*umk_load_ciw"
5391 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5392 "TARGET_ABI_UNICOSMK"
5394 operands[0] = unicosmk_add_call_info_word (operands[0]);
5395 return "lda $25,%0";
5397 [(set_attr "type" "iadd")])
5399 (define_insn "*movdi_er_low_l"
5400 [(set (match_operand:DI 0 "register_operand" "=r")
5401 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5402 (match_operand:DI 2 "local_symbolic_operand" "")))]
5403 "TARGET_EXPLICIT_RELOCS"
5405 if (true_regnum (operands[1]) == 29)
5406 return "lda %0,%2(%1)\t\t!gprel";
5408 return "lda %0,%2(%1)\t\t!gprellow";
5410 [(set_attr "usegp" "yes")])
5413 [(set (match_operand:DI 0 "register_operand" "")
5414 (match_operand:DI 1 "small_symbolic_operand" ""))]
5415 "TARGET_EXPLICIT_RELOCS && reload_completed"
5417 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5418 "operands[2] = pic_offset_table_rtx;")
5421 [(set (match_operand:DI 0 "register_operand" "")
5422 (match_operand:DI 1 "local_symbolic_operand" ""))]
5423 "TARGET_EXPLICIT_RELOCS && reload_completed"
5425 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5427 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5428 "operands[2] = pic_offset_table_rtx;")
5431 [(match_operand 0 "some_small_symbolic_operand" "")]
5434 "operands[0] = split_small_symbolic_operand (operands[0]);")
5436 ;; Accepts any symbolic, not just global, since function calls that
5437 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5438 (define_insn "movdi_er_high_g"
5439 [(set (match_operand:DI 0 "register_operand" "=r")
5440 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5441 (match_operand:DI 2 "symbolic_operand" "")
5442 (match_operand 3 "const_int_operand" "")]
5444 "TARGET_EXPLICIT_RELOCS"
5446 if (INTVAL (operands[3]) == 0)
5447 return "ldq %0,%2(%1)\t\t!literal";
5449 return "ldq %0,%2(%1)\t\t!literal!%3";
5451 [(set_attr "type" "ldsym")])
5454 [(set (match_operand:DI 0 "register_operand" "")
5455 (match_operand:DI 1 "global_symbolic_operand" ""))]
5456 "TARGET_EXPLICIT_RELOCS && reload_completed"
5458 (unspec:DI [(match_dup 2)
5460 (const_int 0)] UNSPEC_LITERAL))]
5461 "operands[2] = pic_offset_table_rtx;")
5463 (define_insn "movdi_er_tlsgd"
5464 [(set (match_operand:DI 0 "register_operand" "=r")
5465 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5466 (match_operand:DI 2 "symbolic_operand" "")
5467 (match_operand 3 "const_int_operand" "")]
5471 if (INTVAL (operands[3]) == 0)
5472 return "lda %0,%2(%1)\t\t!tlsgd";
5474 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5477 (define_insn "movdi_er_tlsldm"
5478 [(set (match_operand:DI 0 "register_operand" "=r")
5479 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5480 (match_operand 2 "const_int_operand" "")]
5484 if (INTVAL (operands[2]) == 0)
5485 return "lda %0,%&(%1)\t\t!tlsldm";
5487 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5490 (define_insn "*movdi_er_gotdtp"
5491 [(set (match_operand:DI 0 "register_operand" "=r")
5492 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5493 (match_operand:DI 2 "symbolic_operand" "")]
5496 "ldq %0,%2(%1)\t\t!gotdtprel"
5497 [(set_attr "type" "ild")
5498 (set_attr "usegp" "yes")])
5501 [(set (match_operand:DI 0 "register_operand" "")
5502 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5503 "HAVE_AS_TLS && reload_completed"
5505 (unspec:DI [(match_dup 2)
5506 (match_dup 1)] UNSPEC_DTPREL))]
5508 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5509 operands[2] = pic_offset_table_rtx;
5512 (define_insn "*movdi_er_gottp"
5513 [(set (match_operand:DI 0 "register_operand" "=r")
5514 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5515 (match_operand:DI 2 "symbolic_operand" "")]
5518 "ldq %0,%2(%1)\t\t!gottprel"
5519 [(set_attr "type" "ild")
5520 (set_attr "usegp" "yes")])
5523 [(set (match_operand:DI 0 "register_operand" "")
5524 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5525 "HAVE_AS_TLS && reload_completed"
5527 (unspec:DI [(match_dup 2)
5528 (match_dup 1)] UNSPEC_TPREL))]
5530 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5531 operands[2] = pic_offset_table_rtx;
5534 (define_insn "*movdi_er_nofix"
5535 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5536 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5537 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5538 && (register_operand (operands[0], DImode)
5539 || reg_or_0_operand (operands[1], DImode))"
5552 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5553 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5555 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5556 ;; have been split up by the rules above but we shouldn't reject the
5557 ;; possibility of them getting through.
5559 (define_insn "*movdi_nofix"
5560 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5561 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5563 && (register_operand (operands[0], DImode)
5564 || reg_or_0_operand (operands[1], DImode))"
5569 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5577 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5578 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5580 (define_insn "*movdi_er_fix"
5581 [(set (match_operand:DI 0 "nonimmediate_operand"
5582 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5583 (match_operand:DI 1 "input_operand"
5584 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5585 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5586 && (register_operand (operands[0], DImode)
5587 || reg_or_0_operand (operands[1], DImode))"
5602 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5603 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5605 (define_insn "*movdi_fix"
5606 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5607 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5608 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5609 && (register_operand (operands[0], DImode)
5610 || reg_or_0_operand (operands[1], DImode))"
5624 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5626 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5627 ;; often appears dead to the life analysis code, at which point we
5628 ;; die for emitting dead prologue instructions. Force this live.
5630 (define_insn "force_movdi"
5631 [(set (match_operand:DI 0 "register_operand" "=r")
5632 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5633 UNSPECV_FORCE_MOV))]
5636 [(set_attr "type" "ilog")])
5638 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5639 ;; memory, and construct long 32-bit constants.
5641 (define_expand "movdi"
5642 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5643 (match_operand:DI 1 "general_operand" ""))]
5646 if (alpha_expand_mov (DImode, operands))
5650 ;; Split a load of a large constant into the appropriate two-insn
5654 [(set (match_operand:DI 0 "register_operand" "")
5655 (match_operand:DI 1 "non_add_const_operand" ""))]
5659 if (alpha_split_const_mov (DImode, operands))
5665 ;; We need to prevent reload from splitting TImode moves, because it
5666 ;; might decide to overwrite a pointer with the value it points to.
5667 ;; In that case we have to do the loads in the appropriate order so
5668 ;; that the pointer is not destroyed too early.
5670 (define_insn_and_split "*movti_internal"
5671 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
5672 (match_operand:TI 1 "input_operand" "roJ,rJ"))]
5673 "(register_operand (operands[0], TImode)
5674 /* Prevent rematerialization of constants. */
5675 && ! CONSTANT_P (operands[1]))
5676 || reg_or_0_operand (operands[1], TImode)"
5679 [(set (match_dup 0) (match_dup 2))
5680 (set (match_dup 1) (match_dup 3))]
5682 alpha_split_tmode_pair (operands, TImode, true);
5685 (define_expand "movti"
5686 [(set (match_operand:TI 0 "nonimmediate_operand" "")
5687 (match_operand:TI 1 "general_operand" ""))]
5690 if (GET_CODE (operands[0]) == MEM
5691 && ! reg_or_0_operand (operands[1], TImode))
5692 operands[1] = force_reg (TImode, operands[1]);
5694 if (operands[1] == const0_rtx)
5696 /* We must put 64-bit constants in memory. We could keep the
5697 32-bit constants in TImode and rely on the splitter, but
5698 this doesn't seem to be worth the pain. */
5699 else if (GET_CODE (operands[1]) == CONST_INT
5700 || GET_CODE (operands[1]) == CONST_DOUBLE)
5702 rtx in[2], out[2], target;
5704 gcc_assert (!no_new_pseudos);
5706 split_double (operands[1], &in[0], &in[1]);
5708 if (in[0] == const0_rtx)
5709 out[0] = const0_rtx;
5712 out[0] = gen_reg_rtx (DImode);
5713 emit_insn (gen_movdi (out[0], in[0]));
5716 if (in[1] == const0_rtx)
5717 out[1] = const0_rtx;
5720 out[1] = gen_reg_rtx (DImode);
5721 emit_insn (gen_movdi (out[1], in[1]));
5724 if (GET_CODE (operands[0]) != REG)
5725 target = gen_reg_rtx (TImode);
5727 target = operands[0];
5729 emit_insn (gen_movdi (gen_rtx_SUBREG (DImode, target, 0), out[0]));
5730 emit_insn (gen_movdi (gen_rtx_SUBREG (DImode, target, 8), out[1]));
5732 if (target != operands[0])
5733 emit_insn (gen_rtx_SET (VOIDmode, operands[0], target));
5739 ;; These are the partial-word cases.
5741 ;; First we have the code to load an aligned word. Operand 0 is the register
5742 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5743 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5744 ;; number of bits within the word that the value is. Operand 3 is an SImode
5745 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5746 ;; same register. It is allowed to conflict with operand 1 as well.
5748 (define_expand "aligned_loadqi"
5749 [(set (match_operand:SI 3 "register_operand" "")
5750 (match_operand:SI 1 "memory_operand" ""))
5751 (set (match_operand:DI 0 "register_operand" "")
5752 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5754 (match_operand:DI 2 "const_int_operand" "")))]
5759 (define_expand "aligned_loadhi"
5760 [(set (match_operand:SI 3 "register_operand" "")
5761 (match_operand:SI 1 "memory_operand" ""))
5762 (set (match_operand:DI 0 "register_operand" "")
5763 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5765 (match_operand:DI 2 "const_int_operand" "")))]
5770 ;; Similar for unaligned loads, where we use the sequence from the
5771 ;; Alpha Architecture manual. We have to distinguish between little-endian
5772 ;; and big-endian systems as the sequences are different.
5774 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5775 ;; operand 3 can overlap the input and output registers.
5777 (define_expand "unaligned_loadqi"
5778 [(use (match_operand:DI 0 "register_operand" ""))
5779 (use (match_operand:DI 1 "address_operand" ""))
5780 (use (match_operand:DI 2 "register_operand" ""))
5781 (use (match_operand:DI 3 "register_operand" ""))]
5784 if (WORDS_BIG_ENDIAN)
5785 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5786 operands[2], operands[3]));
5788 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5789 operands[2], operands[3]));
5793 (define_expand "unaligned_loadqi_le"
5794 [(set (match_operand:DI 2 "register_operand" "")
5795 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5797 (set (match_operand:DI 3 "register_operand" "")
5799 (set (match_operand:DI 0 "register_operand" "")
5800 (zero_extract:DI (match_dup 2)
5802 (ashift:DI (match_dup 3) (const_int 3))))]
5803 "! WORDS_BIG_ENDIAN"
5806 (define_expand "unaligned_loadqi_be"
5807 [(set (match_operand:DI 2 "register_operand" "")
5808 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5810 (set (match_operand:DI 3 "register_operand" "")
5812 (set (match_operand:DI 0 "register_operand" "")
5813 (zero_extract:DI (match_dup 2)
5817 (ashift:DI (match_dup 3) (const_int 3)))))]
5821 (define_expand "unaligned_loadhi"
5822 [(use (match_operand:DI 0 "register_operand" ""))
5823 (use (match_operand:DI 1 "address_operand" ""))
5824 (use (match_operand:DI 2 "register_operand" ""))
5825 (use (match_operand:DI 3 "register_operand" ""))]
5828 if (WORDS_BIG_ENDIAN)
5829 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5830 operands[2], operands[3]));
5832 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5833 operands[2], operands[3]));
5837 (define_expand "unaligned_loadhi_le"
5838 [(set (match_operand:DI 2 "register_operand" "")
5839 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5841 (set (match_operand:DI 3 "register_operand" "")
5843 (set (match_operand:DI 0 "register_operand" "")
5844 (zero_extract:DI (match_dup 2)
5846 (ashift:DI (match_dup 3) (const_int 3))))]
5847 "! WORDS_BIG_ENDIAN"
5850 (define_expand "unaligned_loadhi_be"
5851 [(set (match_operand:DI 2 "register_operand" "")
5852 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5854 (set (match_operand:DI 3 "register_operand" "")
5855 (plus:DI (match_dup 1) (const_int 1)))
5856 (set (match_operand:DI 0 "register_operand" "")
5857 (zero_extract:DI (match_dup 2)
5861 (ashift:DI (match_dup 3) (const_int 3)))))]
5865 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5866 ;; aligned SImode MEM. Operand 1 is the register containing the
5867 ;; byte or word to store. Operand 2 is the number of bits within the word that
5868 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5870 (define_expand "aligned_store"
5871 [(set (match_operand:SI 3 "register_operand" "")
5872 (match_operand:SI 0 "memory_operand" ""))
5873 (set (subreg:DI (match_dup 3) 0)
5874 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5875 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5876 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5877 (match_operand:DI 2 "const_int_operand" "")))
5878 (set (subreg:DI (match_dup 4) 0)
5879 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5880 (set (match_dup 0) (match_dup 4))]
5883 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5884 << INTVAL (operands[2])));
5887 ;; For the unaligned byte and halfword cases, we use code similar to that
5888 ;; in the ;; Architecture book, but reordered to lower the number of registers
5889 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5890 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5891 ;; be the same temporary, if desired. If the address is in a register,
5892 ;; operand 2 can be that register.
5894 (define_expand "unaligned_storeqi"
5895 [(use (match_operand:DI 0 "address_operand" ""))
5896 (use (match_operand:QI 1 "register_operand" ""))
5897 (use (match_operand:DI 2 "register_operand" ""))
5898 (use (match_operand:DI 3 "register_operand" ""))
5899 (use (match_operand:DI 4 "register_operand" ""))]
5902 if (WORDS_BIG_ENDIAN)
5903 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5904 operands[2], operands[3],
5907 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5908 operands[2], operands[3],
5913 (define_expand "unaligned_storeqi_le"
5914 [(set (match_operand:DI 3 "register_operand" "")
5915 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5917 (set (match_operand:DI 2 "register_operand" "")
5920 (and:DI (not:DI (ashift:DI (const_int 255)
5921 (ashift:DI (match_dup 2) (const_int 3))))
5923 (set (match_operand:DI 4 "register_operand" "")
5924 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5925 (ashift:DI (match_dup 2) (const_int 3))))
5926 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5927 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5929 "! WORDS_BIG_ENDIAN"
5932 (define_expand "unaligned_storeqi_be"
5933 [(set (match_operand:DI 3 "register_operand" "")
5934 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5936 (set (match_operand:DI 2 "register_operand" "")
5939 (and:DI (not:DI (ashift:DI (const_int 255)
5940 (minus:DI (const_int 56)
5941 (ashift:DI (match_dup 2) (const_int 3)))))
5943 (set (match_operand:DI 4 "register_operand" "")
5944 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5945 (minus:DI (const_int 56)
5946 (ashift:DI (match_dup 2) (const_int 3)))))
5947 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5948 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5953 (define_expand "unaligned_storehi"
5954 [(use (match_operand:DI 0 "address_operand" ""))
5955 (use (match_operand:HI 1 "register_operand" ""))
5956 (use (match_operand:DI 2 "register_operand" ""))
5957 (use (match_operand:DI 3 "register_operand" ""))
5958 (use (match_operand:DI 4 "register_operand" ""))]
5961 if (WORDS_BIG_ENDIAN)
5962 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5963 operands[2], operands[3],
5966 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5967 operands[2], operands[3],
5972 (define_expand "unaligned_storehi_le"
5973 [(set (match_operand:DI 3 "register_operand" "")
5974 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5976 (set (match_operand:DI 2 "register_operand" "")
5979 (and:DI (not:DI (ashift:DI (const_int 65535)
5980 (ashift:DI (match_dup 2) (const_int 3))))
5982 (set (match_operand:DI 4 "register_operand" "")
5983 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5984 (ashift:DI (match_dup 2) (const_int 3))))
5985 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5986 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5988 "! WORDS_BIG_ENDIAN"
5991 (define_expand "unaligned_storehi_be"
5992 [(set (match_operand:DI 3 "register_operand" "")
5993 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5995 (set (match_operand:DI 2 "register_operand" "")
5996 (plus:DI (match_dup 0) (const_int 1)))
5998 (and:DI (not:DI (ashift:DI
6000 (minus:DI (const_int 56)
6001 (ashift:DI (match_dup 2) (const_int 3)))))
6003 (set (match_operand:DI 4 "register_operand" "")
6004 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6005 (minus:DI (const_int 56)
6006 (ashift:DI (match_dup 2) (const_int 3)))))
6007 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6008 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6013 ;; Here are the define_expand's for QI and HI moves that use the above
6014 ;; patterns. We have the normal sets, plus the ones that need scratch
6015 ;; registers for reload.
6017 (define_expand "movqi"
6018 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6019 (match_operand:QI 1 "general_operand" ""))]
6023 ? alpha_expand_mov (QImode, operands)
6024 : alpha_expand_mov_nobwx (QImode, operands))
6028 (define_expand "movhi"
6029 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6030 (match_operand:HI 1 "general_operand" ""))]
6034 ? alpha_expand_mov (HImode, operands)
6035 : alpha_expand_mov_nobwx (HImode, operands))
6039 ;; Here are the versions for reload. Note that in the unaligned cases
6040 ;; we know that the operand must not be a pseudo-register because stack
6041 ;; slots are always aligned references.
6043 (define_expand "reload_inqi"
6044 [(parallel [(match_operand:QI 0 "register_operand" "=r")
6045 (match_operand:QI 1 "any_memory_operand" "m")
6046 (match_operand:TI 2 "register_operand" "=&r")])]
6051 if (aligned_memory_operand (operands[1], QImode))
6053 seq = gen_reload_inqi_help (operands[0], operands[1],
6054 gen_rtx_REG (SImode, REGNO (operands[2])));
6060 /* It is possible that one of the registers we got for operands[2]
6061 might coincide with that of operands[0] (which is why we made
6062 it TImode). Pick the other one to use as our scratch. */
6063 if (REGNO (operands[0]) == REGNO (operands[2]))
6064 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6066 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6068 addr = get_unaligned_address (operands[1], 0);
6069 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6070 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
6071 alpha_set_memflags (seq, operands[1]);
6077 (define_expand "reload_inhi"
6078 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6079 (match_operand:HI 1 "any_memory_operand" "m")
6080 (match_operand:TI 2 "register_operand" "=&r")])]
6085 if (aligned_memory_operand (operands[1], HImode))
6087 seq = gen_reload_inhi_help (operands[0], operands[1],
6088 gen_rtx_REG (SImode, REGNO (operands[2])));
6094 /* It is possible that one of the registers we got for operands[2]
6095 might coincide with that of operands[0] (which is why we made
6096 it TImode). Pick the other one to use as our scratch. */
6097 if (REGNO (operands[0]) == REGNO (operands[2]))
6098 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6100 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6102 addr = get_unaligned_address (operands[1], 0);
6103 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6104 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
6105 alpha_set_memflags (seq, operands[1]);
6111 (define_expand "reload_outqi"
6112 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6113 (match_operand:QI 1 "register_operand" "r")
6114 (match_operand:TI 2 "register_operand" "=&r")])]
6117 if (aligned_memory_operand (operands[0], QImode))
6119 emit_insn (gen_reload_outqi_help
6120 (operands[0], operands[1],
6121 gen_rtx_REG (SImode, REGNO (operands[2])),
6122 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6126 rtx addr = get_unaligned_address (operands[0], 0);
6127 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6128 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6129 rtx scratch3 = scratch1;
6132 if (GET_CODE (addr) == REG)
6135 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6136 scratch2, scratch3);
6137 alpha_set_memflags (seq, operands[0]);
6143 (define_expand "reload_outhi"
6144 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6145 (match_operand:HI 1 "register_operand" "r")
6146 (match_operand:TI 2 "register_operand" "=&r")])]
6149 if (aligned_memory_operand (operands[0], HImode))
6151 emit_insn (gen_reload_outhi_help
6152 (operands[0], operands[1],
6153 gen_rtx_REG (SImode, REGNO (operands[2])),
6154 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6158 rtx addr = get_unaligned_address (operands[0], 0);
6159 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6160 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6161 rtx scratch3 = scratch1;
6164 if (GET_CODE (addr) == REG)
6167 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6168 scratch2, scratch3);
6169 alpha_set_memflags (seq, operands[0]);
6175 ;; Helpers for the above. The way reload is structured, we can't
6176 ;; always get a proper address for a stack slot during reload_foo
6177 ;; expansion, so we must delay our address manipulations until after.
6179 (define_insn_and_split "reload_inqi_help"
6180 [(set (match_operand:QI 0 "register_operand" "=r")
6181 (match_operand:QI 1 "memory_operand" "m"))
6182 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6183 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6185 "! TARGET_BWX && reload_completed"
6188 rtx aligned_mem, bitnum;
6189 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6190 operands[0] = gen_lowpart (DImode, operands[0]);
6191 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6196 (define_insn_and_split "reload_inhi_help"
6197 [(set (match_operand:HI 0 "register_operand" "=r")
6198 (match_operand:HI 1 "memory_operand" "m"))
6199 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6200 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6202 "! TARGET_BWX && reload_completed"
6205 rtx aligned_mem, bitnum;
6206 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6207 operands[0] = gen_lowpart (DImode, operands[0]);
6208 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6213 (define_insn_and_split "reload_outqi_help"
6214 [(set (match_operand:QI 0 "memory_operand" "=m")
6215 (match_operand:QI 1 "register_operand" "r"))
6216 (clobber (match_operand:SI 2 "register_operand" "=r"))
6217 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6218 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6220 "! TARGET_BWX && reload_completed"
6223 rtx aligned_mem, bitnum;
6224 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6225 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6226 operands[2], operands[3]));
6230 (define_insn_and_split "reload_outhi_help"
6231 [(set (match_operand:HI 0 "memory_operand" "=m")
6232 (match_operand:HI 1 "register_operand" "r"))
6233 (clobber (match_operand:SI 2 "register_operand" "=r"))
6234 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6235 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6237 "! TARGET_BWX && reload_completed"
6240 rtx aligned_mem, bitnum;
6241 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6242 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6243 operands[2], operands[3]));
6247 ;; Vector operations
6249 (define_mode_macro VEC [V8QI V4HI V2SI])
6251 (define_expand "mov<mode>"
6252 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6253 (match_operand:VEC 1 "general_operand" ""))]
6256 if (alpha_expand_mov (<MODE>mode, operands))
6261 [(set (match_operand:VEC 0 "register_operand" "")
6262 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6266 if (alpha_split_const_mov (<MODE>mode, operands))
6273 (define_expand "movmisalign<mode>"
6274 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6275 (match_operand:VEC 1 "general_operand" ""))]
6278 alpha_expand_movmisalign (<MODE>mode, operands);
6282 (define_insn "*mov<mode>_fix"
6283 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6284 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6286 && (register_operand (operands[0], <MODE>mode)
6287 || reg_or_0_operand (operands[1], <MODE>mode))"
6298 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6300 (define_insn "*mov<mode>_nofix"
6301 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6302 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6304 && (register_operand (operands[0], <MODE>mode)
6305 || reg_or_0_operand (operands[1], <MODE>mode))"
6314 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6316 (define_insn "uminv8qi3"
6317 [(set (match_operand:V8QI 0 "register_operand" "=r")
6318 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6319 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6322 [(set_attr "type" "mvi")])
6324 (define_insn "sminv8qi3"
6325 [(set (match_operand:V8QI 0 "register_operand" "=r")
6326 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6327 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6330 [(set_attr "type" "mvi")])
6332 (define_insn "uminv4hi3"
6333 [(set (match_operand:V4HI 0 "register_operand" "=r")
6334 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6335 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6338 [(set_attr "type" "mvi")])
6340 (define_insn "sminv4hi3"
6341 [(set (match_operand:V4HI 0 "register_operand" "=r")
6342 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6343 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6346 [(set_attr "type" "mvi")])
6348 (define_insn "umaxv8qi3"
6349 [(set (match_operand:V8QI 0 "register_operand" "=r")
6350 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6351 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6354 [(set_attr "type" "mvi")])
6356 (define_insn "smaxv8qi3"
6357 [(set (match_operand:V8QI 0 "register_operand" "=r")
6358 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6359 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6362 [(set_attr "type" "mvi")])
6364 (define_insn "umaxv4hi3"
6365 [(set (match_operand:V4HI 0 "register_operand" "=r")
6366 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6367 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6370 [(set_attr "type" "mvi")])
6372 (define_insn "smaxv4hi3"
6373 [(set (match_operand:V4HI 0 "register_operand" "=r")
6374 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6375 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6378 [(set_attr "type" "mvi")])
6380 (define_insn "one_cmpl<mode>2"
6381 [(set (match_operand:VEC 0 "register_operand" "=r")
6382 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6385 [(set_attr "type" "ilog")])
6387 (define_insn "and<mode>3"
6388 [(set (match_operand:VEC 0 "register_operand" "=r")
6389 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6390 (match_operand:VEC 2 "register_operand" "r")))]
6393 [(set_attr "type" "ilog")])
6395 (define_insn "*andnot<mode>3"
6396 [(set (match_operand:VEC 0 "register_operand" "=r")
6397 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6398 (match_operand:VEC 2 "register_operand" "r")))]
6401 [(set_attr "type" "ilog")])
6403 (define_insn "ior<mode>3"
6404 [(set (match_operand:VEC 0 "register_operand" "=r")
6405 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6406 (match_operand:VEC 2 "register_operand" "r")))]
6409 [(set_attr "type" "ilog")])
6411 (define_insn "*iornot<mode>3"
6412 [(set (match_operand:VEC 0 "register_operand" "=r")
6413 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6414 (match_operand:VEC 2 "register_operand" "r")))]
6417 [(set_attr "type" "ilog")])
6419 (define_insn "xor<mode>3"
6420 [(set (match_operand:VEC 0 "register_operand" "=r")
6421 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6422 (match_operand:VEC 2 "register_operand" "r")))]
6425 [(set_attr "type" "ilog")])
6427 (define_insn "*xornot<mode>3"
6428 [(set (match_operand:VEC 0 "register_operand" "=r")
6429 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6430 (match_operand:VEC 2 "register_operand" "r"))))]
6433 [(set_attr "type" "ilog")])
6435 (define_expand "vec_shl_<mode>"
6436 [(set (match_operand:VEC 0 "register_operand" "")
6437 (ashift:DI (match_operand:VEC 1 "register_operand" "")
6438 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6441 operands[0] = gen_lowpart (DImode, operands[0]);
6442 operands[1] = gen_lowpart (DImode, operands[1]);
6445 (define_expand "vec_shr_<mode>"
6446 [(set (match_operand:VEC 0 "register_operand" "")
6447 (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
6448 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6451 operands[0] = gen_lowpart (DImode, operands[0]);
6452 operands[1] = gen_lowpart (DImode, operands[1]);
6455 ;; Bit field extract patterns which use ext[wlq][lh]
6457 (define_expand "extv"
6458 [(set (match_operand:DI 0 "register_operand" "")
6459 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6460 (match_operand:DI 2 "immediate_operand" "")
6461 (match_operand:DI 3 "immediate_operand" "")))]
6466 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6467 if (INTVAL (operands[3]) % 8 != 0
6468 || (INTVAL (operands[2]) != 16
6469 && INTVAL (operands[2]) != 32
6470 && INTVAL (operands[2]) != 64))
6473 /* From mips.md: extract_bit_field doesn't verify that our source
6474 matches the predicate, so we force it to be a MEM here. */
6475 if (GET_CODE (operands[1]) != MEM)
6478 /* The bit number is relative to the mode of operand 1 which is
6479 usually QImode (this might actually be a bug in expmed.c). Note
6480 that the bit number is negative in big-endian mode in this case.
6481 We have to convert that to the offset. */
6482 if (WORDS_BIG_ENDIAN)
6483 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6484 - INTVAL (operands[2]) - INTVAL (operands[3]);
6486 ofs = INTVAL (operands[3]);
6490 alpha_expand_unaligned_load (operands[0], operands[1],
6491 INTVAL (operands[2]) / 8,
6496 (define_expand "extzv"
6497 [(set (match_operand:DI 0 "register_operand" "")
6498 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6499 (match_operand:DI 2 "immediate_operand" "")
6500 (match_operand:DI 3 "immediate_operand" "")))]
6503 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6504 if (INTVAL (operands[3]) % 8 != 0
6505 || (INTVAL (operands[2]) != 8
6506 && INTVAL (operands[2]) != 16
6507 && INTVAL (operands[2]) != 32
6508 && INTVAL (operands[2]) != 64))
6511 if (GET_CODE (operands[1]) == MEM)
6515 /* Fail 8 bit fields, falling back on a simple byte load. */
6516 if (INTVAL (operands[2]) == 8)
6519 /* The bit number is relative to the mode of operand 1 which is
6520 usually QImode (this might actually be a bug in expmed.c). Note
6521 that the bit number is negative in big-endian mode in this case.
6522 We have to convert that to the offset. */
6523 if (WORDS_BIG_ENDIAN)
6524 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6525 - INTVAL (operands[2]) - INTVAL (operands[3]);
6527 ofs = INTVAL (operands[3]);
6531 alpha_expand_unaligned_load (operands[0], operands[1],
6532 INTVAL (operands[2]) / 8,
6538 (define_expand "insv"
6539 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6540 (match_operand:DI 1 "immediate_operand" "")
6541 (match_operand:DI 2 "immediate_operand" ""))
6542 (match_operand:DI 3 "register_operand" ""))]
6547 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6548 if (INTVAL (operands[2]) % 8 != 0
6549 || (INTVAL (operands[1]) != 16
6550 && INTVAL (operands[1]) != 32
6551 && INTVAL (operands[1]) != 64))
6554 /* From mips.md: store_bit_field doesn't verify that our source
6555 matches the predicate, so we force it to be a MEM here. */
6556 if (GET_CODE (operands[0]) != MEM)
6559 /* The bit number is relative to the mode of operand 1 which is
6560 usually QImode (this might actually be a bug in expmed.c). Note
6561 that the bit number is negative in big-endian mode in this case.
6562 We have to convert that to the offset. */
6563 if (WORDS_BIG_ENDIAN)
6564 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6565 - INTVAL (operands[1]) - INTVAL (operands[2]);
6567 ofs = INTVAL (operands[2]);
6571 alpha_expand_unaligned_store (operands[0], operands[3],
6572 INTVAL (operands[1]) / 8, ofs);
6576 ;; Block move/clear, see alpha.c for more details.
6577 ;; Argument 0 is the destination
6578 ;; Argument 1 is the source
6579 ;; Argument 2 is the length
6580 ;; Argument 3 is the alignment
6582 (define_expand "movmemqi"
6583 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6584 (match_operand:BLK 1 "memory_operand" ""))
6585 (use (match_operand:DI 2 "immediate_operand" ""))
6586 (use (match_operand:DI 3 "immediate_operand" ""))])]
6589 if (alpha_expand_block_move (operands))
6595 (define_expand "movmemdi"
6596 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6597 (match_operand:BLK 1 "memory_operand" ""))
6598 (use (match_operand:DI 2 "immediate_operand" ""))
6599 (use (match_operand:DI 3 "immediate_operand" ""))
6601 (clobber (reg:DI 25))
6602 (clobber (reg:DI 16))
6603 (clobber (reg:DI 17))
6604 (clobber (reg:DI 18))
6605 (clobber (reg:DI 19))
6606 (clobber (reg:DI 20))
6607 (clobber (reg:DI 26))
6608 (clobber (reg:DI 27))])]
6609 "TARGET_ABI_OPEN_VMS"
6611 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6612 alpha_need_linkage (XSTR (operands[4], 0), 0);
6615 (define_insn "*movmemdi_1"
6616 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6617 (match_operand:BLK 1 "memory_operand" "m,m"))
6618 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6619 (use (match_operand:DI 3 "immediate_operand" ""))
6620 (use (match_operand:DI 4 "call_operand" "i,i"))
6621 (clobber (reg:DI 25))
6622 (clobber (reg:DI 16))
6623 (clobber (reg:DI 17))
6624 (clobber (reg:DI 18))
6625 (clobber (reg:DI 19))
6626 (clobber (reg:DI 20))
6627 (clobber (reg:DI 26))
6628 (clobber (reg:DI 27))]
6629 "TARGET_ABI_OPEN_VMS"
6631 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6632 switch (which_alternative)
6635 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6637 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6642 [(set_attr "type" "multi")
6643 (set_attr "length" "28")])
6645 (define_expand "setmemqi"
6646 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6647 (match_operand 2 "const_int_operand" ""))
6648 (use (match_operand:DI 1 "immediate_operand" ""))
6649 (use (match_operand:DI 3 "immediate_operand" ""))])]
6652 /* If value to set is not zero, use the library routine. */
6653 if (operands[2] != const0_rtx)
6656 if (alpha_expand_block_clear (operands))
6662 (define_expand "setmemdi"
6663 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6664 (match_operand 2 "const_int_operand" ""))
6665 (use (match_operand:DI 1 "immediate_operand" ""))
6666 (use (match_operand:DI 3 "immediate_operand" ""))
6668 (clobber (reg:DI 25))
6669 (clobber (reg:DI 16))
6670 (clobber (reg:DI 17))
6671 (clobber (reg:DI 26))
6672 (clobber (reg:DI 27))])]
6673 "TARGET_ABI_OPEN_VMS"
6675 /* If value to set is not zero, use the library routine. */
6676 if (operands[2] != const0_rtx)
6679 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6680 alpha_need_linkage (XSTR (operands[4], 0), 0);
6683 (define_insn "*clrmemdi_1"
6684 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6686 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6687 (use (match_operand:DI 2 "immediate_operand" ""))
6688 (use (match_operand:DI 3 "call_operand" "i,i"))
6689 (clobber (reg:DI 25))
6690 (clobber (reg:DI 16))
6691 (clobber (reg:DI 17))
6692 (clobber (reg:DI 26))
6693 (clobber (reg:DI 27))]
6694 "TARGET_ABI_OPEN_VMS"
6696 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6697 switch (which_alternative)
6700 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6702 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6707 [(set_attr "type" "multi")
6708 (set_attr "length" "24")])
6711 ;; Subroutine of stack space allocation. Perform a stack probe.
6712 (define_expand "probe_stack"
6713 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6716 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6717 INTVAL (operands[0])));
6718 MEM_VOLATILE_P (operands[1]) = 1;
6720 operands[0] = const0_rtx;
6723 ;; This is how we allocate stack space. If we are allocating a
6724 ;; constant amount of space and we know it is less than 4096
6725 ;; bytes, we need do nothing.
6727 ;; If it is more than 4096 bytes, we need to probe the stack
6729 (define_expand "allocate_stack"
6731 (plus:DI (reg:DI 30)
6732 (match_operand:DI 1 "reg_or_cint_operand" "")))
6733 (set (match_operand:DI 0 "register_operand" "=r")
6737 if (GET_CODE (operands[1]) == CONST_INT
6738 && INTVAL (operands[1]) < 32768)
6740 if (INTVAL (operands[1]) >= 4096)
6742 /* We do this the same way as in the prologue and generate explicit
6743 probes. Then we update the stack by the constant. */
6747 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6748 while (probed + 8192 < INTVAL (operands[1]))
6749 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6751 if (probed + 4096 < INTVAL (operands[1]))
6752 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6755 operands[1] = GEN_INT (- INTVAL (operands[1]));
6756 operands[2] = virtual_stack_dynamic_rtx;
6761 rtx loop_label = gen_label_rtx ();
6762 rtx want = gen_reg_rtx (Pmode);
6763 rtx tmp = gen_reg_rtx (Pmode);
6766 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6767 force_reg (Pmode, operands[1])));
6768 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6770 if (GET_CODE (operands[1]) != CONST_INT)
6772 out_label = gen_label_rtx ();
6773 emit_insn (gen_cmpdi (want, tmp));
6774 emit_jump_insn (gen_bgeu (out_label));
6777 emit_label (loop_label);
6778 memref = gen_rtx_MEM (DImode, tmp);
6779 MEM_VOLATILE_P (memref) = 1;
6780 emit_move_insn (memref, const0_rtx);
6781 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6782 emit_insn (gen_cmpdi (tmp, want));
6783 emit_jump_insn (gen_bgtu (loop_label));
6785 memref = gen_rtx_MEM (DImode, want);
6786 MEM_VOLATILE_P (memref) = 1;
6787 emit_move_insn (memref, const0_rtx);
6790 emit_label (out_label);
6792 emit_move_insn (stack_pointer_rtx, want);
6793 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6798 ;; This is used by alpha_expand_prolog to do the same thing as above,
6799 ;; except we cannot at that time generate new basic blocks, so we hide
6800 ;; the loop in this one insn.
6802 (define_insn "prologue_stack_probe_loop"
6803 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6804 (match_operand:DI 1 "register_operand" "r")]
6808 operands[2] = gen_label_rtx ();
6809 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6810 CODE_LABEL_NUMBER (operands[2]));
6812 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6814 [(set_attr "length" "16")
6815 (set_attr "type" "multi")])
6817 (define_expand "prologue"
6818 [(clobber (const_int 0))]
6821 alpha_expand_prologue ();
6825 ;; These take care of emitting the ldgp insn in the prologue. This will be
6826 ;; an lda/ldah pair and we want to align them properly. So we have two
6827 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6828 ;; and the second of which emits nothing. However, both are marked as type
6829 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6832 (define_expand "prologue_ldgp"
6834 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6836 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6839 operands[0] = pic_offset_table_rtx;
6840 operands[1] = gen_rtx_REG (Pmode, 27);
6841 operands[2] = (TARGET_EXPLICIT_RELOCS
6842 ? GEN_INT (alpha_next_sequence_number++)
6846 (define_insn "*ldgp_er_1"
6847 [(set (match_operand:DI 0 "register_operand" "=r")
6848 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6849 (match_operand 2 "const_int_operand" "")]
6851 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6852 "ldah %0,0(%1)\t\t!gpdisp!%2"
6853 [(set_attr "cannot_copy" "true")])
6855 (define_insn "*ldgp_er_2"
6856 [(set (match_operand:DI 0 "register_operand" "=r")
6857 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6858 (match_operand 2 "const_int_operand" "")]
6860 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6861 "lda %0,0(%1)\t\t!gpdisp!%2"
6862 [(set_attr "cannot_copy" "true")])
6864 (define_insn "*prologue_ldgp_er_2"
6865 [(set (match_operand:DI 0 "register_operand" "=r")
6866 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6867 (match_operand 2 "const_int_operand" "")]
6869 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6870 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6871 [(set_attr "cannot_copy" "true")])
6873 (define_insn "*prologue_ldgp_1"
6874 [(set (match_operand:DI 0 "register_operand" "=r")
6875 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6876 (match_operand 2 "const_int_operand" "")]
6879 "ldgp %0,0(%1)\n$%~..ng:"
6880 [(set_attr "cannot_copy" "true")])
6882 (define_insn "*prologue_ldgp_2"
6883 [(set (match_operand:DI 0 "register_operand" "=r")
6884 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6885 (match_operand 2 "const_int_operand" "")]
6890 ;; The _mcount profiling hook has special calling conventions, and
6891 ;; does not clobber all the registers that a normal call would. So
6892 ;; hide the fact this is a call at all.
6894 (define_insn "prologue_mcount"
6895 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6898 if (TARGET_EXPLICIT_RELOCS)
6899 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6900 cannot be called via the PLT. */
6901 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6903 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6905 [(set_attr "type" "multi")
6906 (set_attr "length" "8")])
6908 (define_insn "init_fp"
6909 [(set (match_operand:DI 0 "register_operand" "=r")
6910 (match_operand:DI 1 "register_operand" "r"))
6911 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6915 (define_expand "epilogue"
6919 alpha_expand_epilogue ();
6922 (define_expand "sibcall_epilogue"
6926 alpha_expand_epilogue ();
6930 (define_expand "builtin_longjmp"
6931 [(use (match_operand:DI 0 "register_operand" "r"))]
6934 /* The elements of the buffer are, in order: */
6935 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6936 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6937 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6938 rtx pv = gen_rtx_REG (Pmode, 27);
6940 /* This bit is the same as expand_builtin_longjmp. */
6941 emit_move_insn (hard_frame_pointer_rtx, fp);
6942 emit_move_insn (pv, lab);
6943 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6944 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6945 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6947 /* Load the label we are jumping through into $27 so that we know
6948 where to look for it when we get back to setjmp's function for
6949 restoring the gp. */
6950 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6955 ;; This is effectively a copy of indirect_jump, but constrained such
6956 ;; that register renaming cannot foil our cunning plan with $27.
6957 (define_insn "builtin_longjmp_internal"
6959 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6963 [(set_attr "type" "ibr")])
6965 (define_expand "builtin_setjmp_receiver"
6966 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6970 (define_insn_and_split "*builtin_setjmp_receiver_1"
6971 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6974 if (TARGET_EXPLICIT_RELOCS)
6977 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6979 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6981 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6983 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6985 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6986 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6987 UNSPECV_SETJMPR_ER));
6988 operands[1] = pic_offset_table_rtx;
6989 operands[2] = gen_rtx_REG (Pmode, 27);
6990 operands[3] = GEN_INT (alpha_next_sequence_number++);
6992 [(set_attr "length" "12")
6993 (set_attr "type" "multi")])
6995 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6996 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6997 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6998 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
7000 (define_insn "*builtin_setjmp_receiver_er_1"
7001 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7002 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
7003 "br $27,$LSJ%=\n$LSJ%=:"
7004 [(set_attr "type" "ibr")])
7006 (define_expand "exception_receiver"
7007 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
7010 if (TARGET_LD_BUGGY_LDGP)
7011 operands[0] = alpha_gp_save_rtx ();
7013 operands[0] = const0_rtx;
7016 (define_insn "*exception_receiver_2"
7017 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
7018 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
7020 [(set_attr "type" "ild")])
7022 (define_insn_and_split "*exception_receiver_1"
7023 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
7026 if (TARGET_EXPLICIT_RELOCS)
7027 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
7029 return "ldgp $29,0($26)";
7031 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
7033 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
7035 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
7037 operands[0] = pic_offset_table_rtx;
7038 operands[1] = gen_rtx_REG (Pmode, 26);
7039 operands[2] = GEN_INT (alpha_next_sequence_number++);
7041 [(set_attr "length" "8")
7042 (set_attr "type" "multi")])
7044 (define_expand "nonlocal_goto_receiver"
7045 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7046 (set (reg:DI 27) (mem:DI (reg:DI 29)))
7047 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7049 "TARGET_ABI_OPEN_VMS"
7052 (define_insn "arg_home"
7053 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7068 (clobber (mem:BLK (const_int 0)))
7069 (clobber (reg:DI 24))
7070 (clobber (reg:DI 25))
7071 (clobber (reg:DI 0))]
7072 "TARGET_ABI_OPEN_VMS"
7073 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7074 [(set_attr "length" "16")
7075 (set_attr "type" "multi")])
7077 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7079 (define_expand "umk_mismatch_args"
7080 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7081 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7082 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7083 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7086 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7087 "TARGET_ABI_UNICOSMK"
7089 operands[1] = gen_reg_rtx (DImode);
7090 operands[2] = gen_reg_rtx (DImode);
7091 operands[3] = gen_reg_rtx (DImode);
7094 (define_insn "arg_home_umk"
7095 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7110 (clobber (mem:BLK (const_int 0)))
7112 (clobber (reg:DI 22))
7113 (clobber (reg:DI 23))
7114 (clobber (reg:DI 24))
7115 (clobber (reg:DI 0))
7116 (clobber (reg:DI 1))
7117 (clobber (reg:DI 2))
7118 (clobber (reg:DI 3))
7119 (clobber (reg:DI 4))
7120 (clobber (reg:DI 5))
7121 (clobber (reg:DI 6))
7122 (clobber (reg:DI 7))
7123 (clobber (reg:DI 8))])]
7124 "TARGET_ABI_UNICOSMK"
7125 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7126 [(set_attr "length" "16")
7127 (set_attr "type" "multi")])
7131 ;; On EV4, these instructions are nops -- no load occurs.
7133 ;; On EV5, these instructions act as a normal load, and thus can trap
7134 ;; if the address is invalid. The OS may (or may not) handle this in
7135 ;; the entMM fault handler and suppress the fault. If so, then this
7136 ;; has the effect of a read prefetch instruction.
7138 ;; On EV6, these become official prefetch instructions.
7140 (define_insn "prefetch"
7141 [(prefetch (match_operand:DI 0 "address_operand" "p")
7142 (match_operand:DI 1 "const_int_operand" "n")
7143 (match_operand:DI 2 "const_int_operand" "n"))]
7144 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7146 /* Interpret "no temporal locality" as this data should be evicted once
7147 it is used. The "evict next" alternatives load the data into the cache
7148 and leave the LRU eviction counter pointing to that block. */
7149 static const char * const alt[2][2] = {
7151 "ldq $31,%a0", /* read, evict next */
7152 "ldl $31,%a0", /* read, evict last */
7155 "ldt $f31,%a0", /* write, evict next */
7156 "lds $f31,%a0", /* write, evict last */
7160 bool write = INTVAL (operands[1]) != 0;
7161 bool lru = INTVAL (operands[2]) != 0;
7163 return alt[write][lru];
7165 [(set_attr "type" "ild")])
7167 ;; Close the trap shadow of preceding instructions. This is generated
7170 (define_insn "trapb"
7171 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7174 [(set_attr "type" "misc")])
7176 ;; No-op instructions used by machine-dependent reorg to preserve
7177 ;; alignment for instruction issue.
7178 ;; The Unicos/Mk assembler does not support these opcodes.
7184 [(set_attr "type" "ilog")])
7189 "cpys $f31,$f31,$f31"
7190 [(set_attr "type" "fcpys")])
7197 ;; On Unicos/Mk we use a macro for aligning code.
7199 (define_insn "realign"
7200 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7204 if (TARGET_ABI_UNICOSMK)
7205 return "gcc@code@align %0";
7207 return ".align %0 #realign";
7210 ;; Instructions to be emitted from __builtins.
7212 (define_insn "builtin_cmpbge"
7213 [(set (match_operand:DI 0 "register_operand" "=r")
7214 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7215 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7219 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7220 ;; actually differentiate between ILOG and ICMP in the schedule.
7221 [(set_attr "type" "icmp")])
7223 (define_expand "builtin_extbl"
7224 [(match_operand:DI 0 "register_operand" "")
7225 (match_operand:DI 1 "reg_or_0_operand" "")
7226 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7229 rtx (*gen) (rtx, rtx, rtx, rtx);
7230 if (WORDS_BIG_ENDIAN)
7234 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7238 (define_expand "builtin_extwl"
7239 [(match_operand:DI 0 "register_operand" "")
7240 (match_operand:DI 1 "reg_or_0_operand" "")
7241 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7244 rtx (*gen) (rtx, rtx, rtx, rtx);
7245 if (WORDS_BIG_ENDIAN)
7249 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7253 (define_expand "builtin_extll"
7254 [(match_operand:DI 0 "register_operand" "")
7255 (match_operand:DI 1 "reg_or_0_operand" "")
7256 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7259 rtx (*gen) (rtx, rtx, rtx, rtx);
7260 if (WORDS_BIG_ENDIAN)
7264 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7268 (define_expand "builtin_extql"
7269 [(match_operand:DI 0 "register_operand" "")
7270 (match_operand:DI 1 "reg_or_0_operand" "")
7271 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7274 rtx (*gen) (rtx, rtx, rtx, rtx);
7275 if (WORDS_BIG_ENDIAN)
7279 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7283 (define_expand "builtin_extwh"
7284 [(match_operand:DI 0 "register_operand" "")
7285 (match_operand:DI 1 "reg_or_0_operand" "")
7286 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7289 rtx (*gen) (rtx, rtx, rtx);
7290 if (WORDS_BIG_ENDIAN)
7294 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7298 (define_expand "builtin_extlh"
7299 [(match_operand:DI 0 "register_operand" "")
7300 (match_operand:DI 1 "reg_or_0_operand" "")
7301 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7304 rtx (*gen) (rtx, rtx, rtx);
7305 if (WORDS_BIG_ENDIAN)
7309 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7313 (define_expand "builtin_extqh"
7314 [(match_operand:DI 0 "register_operand" "")
7315 (match_operand:DI 1 "reg_or_0_operand" "")
7316 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7319 rtx (*gen) (rtx, rtx, rtx);
7320 if (WORDS_BIG_ENDIAN)
7324 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7328 (define_expand "builtin_insbl"
7329 [(match_operand:DI 0 "register_operand" "")
7330 (match_operand:DI 1 "register_operand" "")
7331 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7334 rtx (*gen) (rtx, rtx, rtx);
7335 if (WORDS_BIG_ENDIAN)
7339 operands[1] = gen_lowpart (QImode, operands[1]);
7340 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7344 (define_expand "builtin_inswl"
7345 [(match_operand:DI 0 "register_operand" "")
7346 (match_operand:DI 1 "register_operand" "")
7347 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7350 rtx (*gen) (rtx, rtx, rtx);
7351 if (WORDS_BIG_ENDIAN)
7355 operands[1] = gen_lowpart (HImode, operands[1]);
7356 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7360 (define_expand "builtin_insll"
7361 [(match_operand:DI 0 "register_operand" "")
7362 (match_operand:DI 1 "register_operand" "")
7363 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7366 rtx (*gen) (rtx, rtx, rtx);
7367 if (WORDS_BIG_ENDIAN)
7371 operands[1] = gen_lowpart (SImode, operands[1]);
7372 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7373 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7377 (define_expand "builtin_insql"
7378 [(match_operand:DI 0 "register_operand" "")
7379 (match_operand:DI 1 "reg_or_0_operand" "")
7380 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7383 rtx (*gen) (rtx, rtx, rtx);
7384 if (WORDS_BIG_ENDIAN)
7388 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7392 (define_expand "builtin_inswh"
7393 [(match_operand:DI 0 "register_operand" "")
7394 (match_operand:DI 1 "register_operand" "")
7395 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7398 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7402 (define_expand "builtin_inslh"
7403 [(match_operand:DI 0 "register_operand" "")
7404 (match_operand:DI 1 "register_operand" "")
7405 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7408 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7412 (define_expand "builtin_insqh"
7413 [(match_operand:DI 0 "register_operand" "")
7414 (match_operand:DI 1 "register_operand" "")
7415 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7418 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7422 (define_expand "builtin_mskbl"
7423 [(match_operand:DI 0 "register_operand" "")
7424 (match_operand:DI 1 "reg_or_0_operand" "")
7425 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7428 rtx (*gen) (rtx, rtx, rtx, rtx);
7430 if (WORDS_BIG_ENDIAN)
7434 mask = GEN_INT (0xff);
7435 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7439 (define_expand "builtin_mskwl"
7440 [(match_operand:DI 0 "register_operand" "")
7441 (match_operand:DI 1 "reg_or_0_operand" "")
7442 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7445 rtx (*gen) (rtx, rtx, rtx, rtx);
7447 if (WORDS_BIG_ENDIAN)
7451 mask = GEN_INT (0xffff);
7452 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7456 (define_expand "builtin_mskll"
7457 [(match_operand:DI 0 "register_operand" "")
7458 (match_operand:DI 1 "reg_or_0_operand" "")
7459 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7462 rtx (*gen) (rtx, rtx, rtx, rtx);
7464 if (WORDS_BIG_ENDIAN)
7468 mask = immed_double_const (0xffffffff, 0, DImode);
7469 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7473 (define_expand "builtin_mskql"
7474 [(match_operand:DI 0 "register_operand" "")
7475 (match_operand:DI 1 "reg_or_0_operand" "")
7476 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7479 rtx (*gen) (rtx, rtx, rtx, rtx);
7481 if (WORDS_BIG_ENDIAN)
7486 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7490 (define_expand "builtin_mskwh"
7491 [(match_operand:DI 0 "register_operand" "")
7492 (match_operand:DI 1 "register_operand" "")
7493 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7496 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7500 (define_expand "builtin_msklh"
7501 [(match_operand:DI 0 "register_operand" "")
7502 (match_operand:DI 1 "register_operand" "")
7503 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7506 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7510 (define_expand "builtin_mskqh"
7511 [(match_operand:DI 0 "register_operand" "")
7512 (match_operand:DI 1 "register_operand" "")
7513 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7516 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7520 (define_expand "builtin_zap"
7521 [(set (match_operand:DI 0 "register_operand" "")
7523 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7525 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7528 if (GET_CODE (operands[2]) == CONST_INT)
7530 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7532 if (mask == const0_rtx)
7534 emit_move_insn (operands[0], const0_rtx);
7537 if (mask == constm1_rtx)
7539 emit_move_insn (operands[0], operands[1]);
7543 operands[1] = force_reg (DImode, operands[1]);
7544 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7548 operands[1] = force_reg (DImode, operands[1]);
7549 operands[2] = gen_lowpart (QImode, operands[2]);
7552 (define_insn "*builtin_zap_1"
7553 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7555 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7557 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7564 [(set_attr "type" "shift,shift,ilog,shift")])
7567 [(set (match_operand:DI 0 "register_operand" "")
7569 [(match_operand:QI 2 "const_int_operand" "")]
7571 (match_operand:DI 1 "const_int_operand" "")))]
7575 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7576 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7577 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7580 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7581 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7582 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7583 c_hi & CONST_DOUBLE_HIGH (mask),
7586 emit_move_insn (operands[0], operands[1]);
7591 [(set (match_operand:DI 0 "register_operand" "")
7593 [(match_operand:QI 2 "const_int_operand" "")]
7595 (match_operand:DI 1 "register_operand" "")))]
7598 (and:DI (match_dup 1) (match_dup 2)))]
7600 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7601 if (operands[2] == const0_rtx)
7603 emit_move_insn (operands[0], const0_rtx);
7606 if (operands[2] == constm1_rtx)
7608 emit_move_insn (operands[0], operands[1]);
7613 (define_expand "builtin_zapnot"
7614 [(set (match_operand:DI 0 "register_operand" "")
7616 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7618 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7621 if (GET_CODE (operands[2]) == CONST_INT)
7623 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7625 if (mask == const0_rtx)
7627 emit_move_insn (operands[0], const0_rtx);
7630 if (mask == constm1_rtx)
7632 emit_move_insn (operands[0], operands[1]);
7636 operands[1] = force_reg (DImode, operands[1]);
7637 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7641 operands[1] = force_reg (DImode, operands[1]);
7642 operands[2] = gen_lowpart (QImode, operands[2]);
7645 (define_insn "*builtin_zapnot_1"
7646 [(set (match_operand:DI 0 "register_operand" "=r")
7648 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7650 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7653 [(set_attr "type" "shift")])
7655 (define_insn "builtin_amask"
7656 [(set (match_operand:DI 0 "register_operand" "=r")
7657 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7661 [(set_attr "type" "ilog")])
7663 (define_insn "builtin_implver"
7664 [(set (match_operand:DI 0 "register_operand" "=r")
7665 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7668 [(set_attr "type" "ilog")])
7670 (define_insn "builtin_rpcc"
7671 [(set (match_operand:DI 0 "register_operand" "=r")
7672 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7675 [(set_attr "type" "ilog")])
7677 (define_expand "builtin_minub8"
7678 [(match_operand:DI 0 "register_operand" "")
7679 (match_operand:DI 1 "reg_or_0_operand" "")
7680 (match_operand:DI 2 "reg_or_0_operand" "")]
7683 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7684 operands[1], operands[2]);
7688 (define_expand "builtin_minsb8"
7689 [(match_operand:DI 0 "register_operand" "")
7690 (match_operand:DI 1 "reg_or_0_operand" "")
7691 (match_operand:DI 2 "reg_or_0_operand" "")]
7694 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7695 operands[1], operands[2]);
7699 (define_expand "builtin_minuw4"
7700 [(match_operand:DI 0 "register_operand" "")
7701 (match_operand:DI 1 "reg_or_0_operand" "")
7702 (match_operand:DI 2 "reg_or_0_operand" "")]
7705 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7706 operands[1], operands[2]);
7710 (define_expand "builtin_minsw4"
7711 [(match_operand:DI 0 "register_operand" "")
7712 (match_operand:DI 1 "reg_or_0_operand" "")
7713 (match_operand:DI 2 "reg_or_0_operand" "")]
7716 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7717 operands[1], operands[2]);
7721 (define_expand "builtin_maxub8"
7722 [(match_operand:DI 0 "register_operand" "")
7723 (match_operand:DI 1 "reg_or_0_operand" "")
7724 (match_operand:DI 2 "reg_or_0_operand" "")]
7727 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7728 operands[1], operands[2]);
7732 (define_expand "builtin_maxsb8"
7733 [(match_operand:DI 0 "register_operand" "")
7734 (match_operand:DI 1 "reg_or_0_operand" "")
7735 (match_operand:DI 2 "reg_or_0_operand" "")]
7738 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7739 operands[1], operands[2]);
7743 (define_expand "builtin_maxuw4"
7744 [(match_operand:DI 0 "register_operand" "")
7745 (match_operand:DI 1 "reg_or_0_operand" "")
7746 (match_operand:DI 2 "reg_or_0_operand" "")]
7749 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7750 operands[1], operands[2]);
7754 (define_expand "builtin_maxsw4"
7755 [(match_operand:DI 0 "register_operand" "")
7756 (match_operand:DI 1 "reg_or_0_operand" "")
7757 (match_operand:DI 2 "reg_or_0_operand" "")]
7760 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7761 operands[1], operands[2]);
7765 (define_insn "builtin_perr"
7766 [(set (match_operand:DI 0 "register_operand" "=r")
7767 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7768 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7772 [(set_attr "type" "mvi")])
7774 (define_expand "builtin_pklb"
7775 [(set (match_operand:DI 0 "register_operand" "")
7778 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7783 operands[0] = gen_lowpart (V8QImode, operands[0]);
7784 operands[1] = gen_lowpart (V2SImode, operands[1]);
7785 operands[2] = CONST0_RTX (V2QImode);
7786 operands[3] = CONST0_RTX (V4QImode);
7789 (define_insn "*pklb"
7790 [(set (match_operand:V8QI 0 "register_operand" "=r")
7793 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7794 (match_operand:V2QI 2 "const0_operand" ""))
7795 (match_operand:V4QI 3 "const0_operand" "")))]
7798 [(set_attr "type" "mvi")])
7800 (define_expand "builtin_pkwb"
7801 [(set (match_operand:DI 0 "register_operand" "")
7803 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7807 operands[0] = gen_lowpart (V8QImode, operands[0]);
7808 operands[1] = gen_lowpart (V4HImode, operands[1]);
7809 operands[2] = CONST0_RTX (V4QImode);
7812 (define_insn "*pkwb"
7813 [(set (match_operand:V8QI 0 "register_operand" "=r")
7815 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7816 (match_operand:V4QI 2 "const0_operand" "")))]
7819 [(set_attr "type" "mvi")])
7821 (define_expand "builtin_unpkbl"
7822 [(set (match_operand:DI 0 "register_operand" "")
7824 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7825 (parallel [(const_int 0) (const_int 1)]))))]
7828 operands[0] = gen_lowpart (V2SImode, operands[0]);
7829 operands[1] = gen_lowpart (V8QImode, operands[1]);
7832 (define_insn "*unpkbl"
7833 [(set (match_operand:V2SI 0 "register_operand" "=r")
7835 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7836 (parallel [(const_int 0) (const_int 1)]))))]
7839 [(set_attr "type" "mvi")])
7841 (define_expand "builtin_unpkbw"
7842 [(set (match_operand:DI 0 "register_operand" "")
7844 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7845 (parallel [(const_int 0)
7851 operands[0] = gen_lowpart (V4HImode, operands[0]);
7852 operands[1] = gen_lowpart (V8QImode, operands[1]);
7855 (define_insn "*unpkbw"
7856 [(set (match_operand:V4HI 0 "register_operand" "=r")
7858 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7859 (parallel [(const_int 0)
7865 [(set_attr "type" "mvi")])
7869 ;; The call patterns are at the end of the file because their
7870 ;; wildcard operand0 interferes with nice recognition.
7872 (define_insn "*call_value_osf_1_er"
7873 [(set (match_operand 0 "" "")
7874 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7875 (match_operand 2 "" "")))
7877 (clobber (reg:DI 26))]
7878 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7880 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7881 bsr $26,%1\t\t!samegp
7882 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7883 [(set_attr "type" "jsr")
7884 (set_attr "length" "12,*,16")])
7886 ;; We must use peep2 instead of a split because we need accurate life
7887 ;; information for $gp. Consider the case of { bar(); while (1); }.
7889 [(parallel [(set (match_operand 0 "" "")
7890 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7891 (match_operand 2 "" "")))
7893 (clobber (reg:DI 26))])]
7894 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7895 && ! samegp_function_operand (operands[1], Pmode)
7896 && (peep2_regno_dead_p (1, 29)
7897 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7898 [(parallel [(set (match_dup 0)
7899 (call (mem:DI (match_dup 3))
7901 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7902 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7904 (use (match_dup 4))])]
7906 if (CONSTANT_P (operands[1]))
7908 operands[3] = gen_rtx_REG (Pmode, 27);
7909 operands[4] = GEN_INT (alpha_next_sequence_number++);
7910 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7911 operands[1], operands[4]));
7915 operands[3] = operands[1];
7916 operands[1] = const0_rtx;
7917 operands[4] = const0_rtx;
7922 [(parallel [(set (match_operand 0 "" "")
7923 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7924 (match_operand 2 "" "")))
7926 (clobber (reg:DI 26))])]
7927 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7928 && ! samegp_function_operand (operands[1], Pmode)
7929 && ! (peep2_regno_dead_p (1, 29)
7930 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7931 [(parallel [(set (match_dup 0)
7932 (call (mem:DI (match_dup 3))
7934 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7935 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7937 (use (match_dup 5))])
7939 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7941 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7943 if (CONSTANT_P (operands[1]))
7945 operands[3] = gen_rtx_REG (Pmode, 27);
7946 operands[5] = GEN_INT (alpha_next_sequence_number++);
7947 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7948 operands[1], operands[5]));
7952 operands[3] = operands[1];
7953 operands[1] = const0_rtx;
7954 operands[5] = const0_rtx;
7956 operands[4] = GEN_INT (alpha_next_sequence_number++);
7959 ;; We add a blockage unspec_volatile to prevent insns from moving down
7960 ;; from above the call to in between the call and the ldah gpdisp.
7961 (define_insn "*call_value_osf_2_er"
7962 [(set (match_operand 0 "" "")
7963 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7964 (match_operand 2 "" "")))
7966 (plus:DI (pc) (const_int 4)))
7967 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7968 (use (match_operand 3 "" ""))
7969 (use (match_operand 4 "" ""))]
7970 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7971 "jsr $26,(%1),%3%J4"
7972 [(set_attr "type" "jsr")
7973 (set_attr "cannot_copy" "true")])
7975 (define_insn "*call_value_osf_1_noreturn"
7976 [(set (match_operand 0 "" "")
7977 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7978 (match_operand 2 "" "")))
7980 (clobber (reg:DI 26))]
7981 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7982 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7987 [(set_attr "type" "jsr")
7988 (set_attr "length" "*,*,8")])
7990 (define_insn_and_split "call_value_osf_tlsgd"
7991 [(set (match_operand 0 "" "")
7992 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7994 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7996 (clobber (reg:DI 26))]
7999 "&& reload_completed"
8001 (unspec:DI [(match_dup 5)
8003 (match_dup 2)] UNSPEC_LITERAL))
8004 (parallel [(set (match_dup 0)
8005 (call (mem:DI (match_dup 3))
8007 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
8008 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
8010 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
8012 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
8014 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8016 operands[3] = gen_rtx_REG (Pmode, 27);
8017 operands[4] = GEN_INT (alpha_next_sequence_number++);
8018 operands[5] = pic_offset_table_rtx;
8020 [(set_attr "type" "multi")])
8022 (define_insn_and_split "call_value_osf_tlsldm"
8023 [(set (match_operand 0 "" "")
8024 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8026 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
8028 (clobber (reg:DI 26))]
8031 "&& reload_completed"
8033 (unspec:DI [(match_dup 5)
8035 (match_dup 2)] UNSPEC_LITERAL))
8036 (parallel [(set (match_dup 0)
8037 (call (mem:DI (match_dup 3))
8039 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
8040 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
8042 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
8044 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
8046 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
8048 operands[3] = gen_rtx_REG (Pmode, 27);
8049 operands[4] = GEN_INT (alpha_next_sequence_number++);
8050 operands[5] = pic_offset_table_rtx;
8052 [(set_attr "type" "multi")])
8054 (define_insn "*call_value_osf_1"
8055 [(set (match_operand 0 "" "")
8056 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8057 (match_operand 2 "" "")))
8059 (clobber (reg:DI 26))]
8060 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8062 jsr $26,($27),0\;ldgp $29,0($26)
8064 jsr $26,%1\;ldgp $29,0($26)"
8065 [(set_attr "type" "jsr")
8066 (set_attr "length" "12,*,16")])
8068 (define_insn "*sibcall_value_osf_1_er"
8069 [(set (match_operand 0 "" "")
8070 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8071 (match_operand 2 "" "")))
8072 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8073 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8075 br $31,%1\t\t!samegp
8076 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8077 [(set_attr "type" "jsr")
8078 (set_attr "length" "*,8")])
8080 (define_insn "*sibcall_value_osf_1"
8081 [(set (match_operand 0 "" "")
8082 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8083 (match_operand 2 "" "")))
8084 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8085 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8088 lda $27,%1\;jmp $31,($27),%1"
8089 [(set_attr "type" "jsr")
8090 (set_attr "length" "*,8")])
8092 (define_insn "*call_value_nt_1"
8093 [(set (match_operand 0 "" "")
8094 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8095 (match_operand 2 "" "")))
8096 (clobber (reg:DI 26))]
8097 "TARGET_ABI_WINDOWS_NT"
8102 [(set_attr "type" "jsr")
8103 (set_attr "length" "*,*,12")])
8105 ; GAS relies on the order and position of instructions output below in order
8106 ; to generate relocs for VMS link to potentially optimize the call.
8107 ; Please do not molest.
8108 (define_insn "*call_value_vms_1"
8109 [(set (match_operand 0 "" "")
8110 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8111 (match_operand 2 "" "")))
8112 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8115 (clobber (reg:DI 27))]
8116 "TARGET_ABI_OPEN_VMS"
8118 switch (which_alternative)
8121 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8123 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8124 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8125 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8130 [(set_attr "type" "jsr")
8131 (set_attr "length" "12,16")])
8133 (define_insn "*call_value_umk"
8134 [(set (match_operand 0 "" "")
8135 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8136 (match_operand 2 "" "")))
8138 (clobber (reg:DI 26))]
8139 "TARGET_ABI_UNICOSMK"
8141 [(set_attr "type" "jsr")])