| blob | c95b493886bced6f12026306ee41f711b21e7675 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
125 /* Number of attempts to combine instructions in this function. */
129 /* Number of attempts that got as far as substitution in this function. */
133 /* Number of instructions combined with added SETs in this function. */
137 /* Number of instructions combined in this function. */
141 /* Totals over entire compilation. */
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
161 \f
163 /* Record last point of death of (hard or pseudo) register n. */
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
176 following ways:
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
191 register's value
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
196 table.
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
214 rtx last_set_value;
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
221 /* Record the value of label_tick when the value for register n is placed in
222 last_set_value. */
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
249 zero.
251 If an entry is zero, it means that we don't know anything special. */
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
266 value. */
274 /* Record the luid of the last insn that invalidated memory
275 (anything that writes memory, and subroutine calls, but not pushes). */
279 /* Record the luid of the last CALL_INSN
280 so we can tell whether a potential combination crosses any calls. */
284 /* When `subst' is called, this is the insn that is being modified
285 (by combining in a previous insn). The PATTERN of this insn
286 is still the old pattern partially modified and it should not be
287 looked at, but this may be used to examine the successors of the insn
288 to judge whether a simplification is valid. */
292 /* This is the lowest LUID that `subst' is currently dealing with.
293 get_last_value will not return a value if the register was set at or
294 after this LUID. If not for this mechanism, we could get confused if
295 I2 or I1 in try_combine were an insn that used the old value of a register
296 to obtain a new value. In that case, we might erroneously get the
297 new value of the register when we wanted the old one. */
301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
302 must consider all these registers to be always live. */
306 /* This is an insn to which a LOG_LINKS entry has been added. If this
307 insn is the earlier than I2 or I3, combine should rescan starting at
308 that location. */
312 /* Basic block in which we are performing combines. */
316 \f
317 /* Length of the currently allocated uid_insn_cost array. */
321 /* The following array records the insn_rtx_cost for every insn
322 in the instruction stream. */
326 /* The following array records the LOG_LINKS for every insn in the
327 instruction stream as struct insn_link pointers. */
333 };
337 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
338 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
340 #define FOR_EACH_LOG_LINK(L, INSN) \
341 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
343 /* Links for LOG_LINKS are allocated from this obstack. */
347 /* Allocate a link. */
351 {
359 }
361 /* Incremented for each basic block. */
365 /* Reset to label_tick for each extended basic block in scanning order. */
369 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
370 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
374 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
375 be safely used. It is zero while computing them and after combine has
376 completed. This former test prevents propagating values based on
377 previously set values, which can be incorrect if a variable is modified
378 in a loop. */
382 \f
383 /* Record one modification to rtl structure
384 to be undone by storing old_contents into *where. */
388 struct undo
389 {
394 };
396 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
397 num_undo says how many are currently recorded.
399 other_insn is nonzero if we have modified some other insn in the process
400 of working on subst_insn. It must be verified too. */
402 struct undobuf
403 {
407 };
411 /* Number of times the pseudo being substituted for
412 was found and replaced. */
417 machine_mode,
421 machine_mode,
493 \f
495 /* It is not safe to use ordinary gen_lowpart in combine.
496 See comments in gen_lowpart_for_combine. */
497 #undef RTL_HOOKS_GEN_LOWPART
498 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
500 /* Our implementation of gen_lowpart never emits a new pseudo. */
501 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
502 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
504 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
505 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
507 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
508 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
510 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
511 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
515 \f
516 /* Convenience wrapper for the canonicalize_comparison target hook.
517 Target hooks cannot use enum rtx_code. */
521 {
525 }
527 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
528 PATTERN can not be split. Otherwise, it returns an insn sequence.
529 This is a wrapper around split_insns which ensures that the
530 reg_stat vector is made larger if the splitter creates a new
531 register. */
535 {
544 }
546 /* This is used by find_single_use to locate an rtx in LOC that
547 contains exactly one use of DEST, which is typically either a REG
548 or CC0. It returns a pointer to the innermost rtx expression
549 containing DEST. Appearances of DEST that are being used to
550 totally replace it are not counted. */
554 {
563 {
567 CASE_CONST_ANY:
572 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
573 of a REG that occupies all of the REG, the insn uses DEST if
574 it is mentioned in the destination or the source. Otherwise, we
575 need just check the source. */
595 }
597 /* If it wasn't one of the common cases above, check each expression and
598 vector of this code. Look for a unique usage of DEST. */
602 {
604 {
609 else
615 /* Duplicate usage. */
617 }
619 {
623 {
629 else
636 }
637 }
638 }
641 }
644 /* See if DEST, produced in INSN, is used only a single time in the
645 sequel. If so, return a pointer to the innermost rtx expression in which
646 it is used.
648 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
650 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
651 care about REG_DEAD notes or LOG_LINKS.
653 Otherwise, we find the single use by finding an insn that has a
654 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
655 only referenced once in that insn, we know that it must be the first
656 and last insn referencing DEST. */
660 {
661 basic_block bb;
666 #ifdef HAVE_cc0
668 {
678 }
679 #endif
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 #ifndef HAVE_cc0
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 static void
823 {
832 else
841 }
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 #endif
845 \f
846 /* Subroutine of try_combine. Determine whether the replacement patterns
847 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
848 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
849 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
850 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
851 of all the instructions can be estimated and the replacements are more
852 expensive than the original sequence. */
854 static bool
857 {
862 /* Lookup the original insn_rtx_costs. */
867 {
870 {
874 }
875 else
876 {
880 }
881 }
882 else
883 {
886 }
888 /* Calculate the replacement insn_rtx_costs. */
891 {
895 }
896 else
897 {
900 }
903 {
909 {
912 }
913 else
915 }
917 /* Disallow this combination if both new_cost and old_cost are greater than
918 zero, and new_cost is greater than old cost. */
922 {
941 else
943 }
948 /* Update the uid_insn_cost array with the replacement costs. */
952 {
956 }
959 }
962 /* Delete any insns that copy a register to itself. */
964 static void
966 {
968 basic_block bb;
971 {
973 {
976 {
981 }
982 }
983 }
984 }
986 \f
987 /* Return false if we do not want to (or cannot) combine DEF. */
988 static bool
990 {
991 /* Do not consider if it is pre/post modification in MEM. */
997 /* Do not combine frame pointer adjustments. */
1000 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1003 #endif
1004 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1006 #endif
1007 )
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1117 #ifdef HAVE_cc0
1120 #endif
1122 }
1123 \f
1124 /* Main entry point for combiner. F is the first insn of the function.
1125 NREGS is the first unused pseudo-reg number.
1127 Return nonzero if the combiner has turned an indirect jump
1128 instruction into a direct jump. */
1129 static int
1131 {
1133 #ifdef HAVE_cc0
1135 #endif
1138 basic_block last_bb;
1158 /* Allocate array for insn info. */
1166 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1167 problems when, for example, we have j <<= 1 in a loop. */
1172 /* Scan all SETs and see if we can deduce anything about what
1173 bits are known to be zero for some registers and how many copies
1174 of the sign bit are known to exist for those registers.
1176 Also set any known values so that we can use it while searching
1177 for what bits are known to be set. */
1180 /* Allow the entry block and the first block to fall into the same EBB.
1181 Conceptually the incoming promotions are assigned to the entry block. */
1186 {
1191 label_tick++;
1199 {
1200 #ifdef AUTO_INC_DEC
1201 rtx links;
1202 #endif
1208 insn);
1211 #ifdef AUTO_INC_DEC
1215 insn);
1216 #endif
1218 /* Record the current insn_rtx_cost of this instruction. */
1221 optimize_this_for_speed_p);
1225 }
1226 }
1230 /* Now scan all the insns in forward order. */
1238 {
1244 label_tick++;
1254 {
1268 /* See if we know about function return values before this
1269 insn based upon SUBREG flags. */
1272 /* See if we can find hardregs and subreg of pseudos in
1273 narrower modes. This could help turning TRUNCATEs
1274 into SUBREGs. */
1277 /* Try this insn with each insn it links back to. */
1283 {
1286 }
1288 /* Try each sequence of three linked insns ending with this one. */
1292 {
1295 /* If the linked insn has been replaced by a note, then there
1296 is no point in pursuing this chain any further. */
1304 {
1307 }
1308 }
1310 #ifdef HAVE_cc0
1311 /* Try to combine a jump insn that uses CC0
1312 with a preceding insn that sets CC0, and maybe with its
1313 logical predecessor as well.
1314 This is how we make decrement-and-branch insns.
1315 We need this special code because data flow connections
1316 via CC0 do not get entered in LOG_LINKS. */
1322 {
1333 }
1335 /* Do the same for an insn that explicitly references CC0. */
1342 {
1353 }
1355 /* Finally, see if any of the insns that this insn links to
1356 explicitly references CC0. If so, try this insn, that insn,
1357 and its predecessor if it sets CC0. */
1369 #endif
1371 /* Try combining an insn with two different insns whose results it
1372 uses. */
1382 {
1385 }
1387 /* Try four-instruction combinations. */
1390 {
1394 /* If the linked insn has been replaced by a note, then there
1395 is no point in pursuing this chain any further. */
1400 {
1404 /* I0 -> I1 -> I2 -> I3. */
1410 {
1413 }
1414 /* I0, I1 -> I2, I2 -> I3. */
1421 {
1424 }
1425 }
1428 {
1432 /* I0 -> I2; I1, I2 -> I3. */
1438 {
1441 }
1442 /* I0 -> I1; I1, I2 -> I3. */
1448 {
1451 }
1452 }
1453 }
1455 /* Try this insn with each REG_EQUAL note it links back to. */
1457 {
1463 /* Avoid using a register that may already been marked
1464 dead by an earlier instruction. */
1469 {
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1480 last_combined_insn);
1483 {
1486 }
1488 }
1489 }
1494 retry:
1495 ;
1496 }
1497 }
1504 /* Clean up. */
1510 {
1513 {
1516 }
1518 }
1528 /* Make recognizer allow volatile MEMs again. */
1532 }
1534 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1536 static void
1538 {
1544 }
1545 \f
1546 /* Set up any promoted values for incoming argument registers. */
1548 static void
1550 {
1551 tree arg;
1556 {
1561 /* Only continue if the incoming argument is in a register. */
1565 /* Determine, if possible, whether all call sites of the current
1566 function lie within the current compilation unit. (This does
1567 take into account the exporting of a function via taking its
1568 address, and so forth.) */
1571 /* The mode and signedness of the argument before any promotions happen
1572 (equal to the mode of the pseudo holding it at that stage). */
1576 /* The mode and signedness of the argument after any source language and
1577 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1581 /* The mode and signedness of the argument as it is actually passed,
1582 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1586 /* The mode of the register in which the argument is being passed. */
1589 /* Eliminate sign extensions in the callee when:
1590 (a) A mode promotion has occurred; */
1593 /* (b) The mode of the register is the same as the mode of
1594 the argument as it is passed; */
1597 /* (c) There's no language level extension; */
1599 ;
1600 /* (c.1) All callers are from the current compilation unit. If that's
1601 the case we don't have to rely on an ABI, we only have to know
1602 what we're generating right now, and we know that we will do the
1603 mode1 to mode2 promotion with the given sign. */
1606 /* (c.2) The combination of the two promotions is useful. This is
1607 true when the signs match, or if the first promotion is unsigned.
1608 In the later case, (sign_extend (zero_extend x)) is the same as
1609 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1615 /* Record that the value was promoted from mode1 to mode3,
1616 so that any sign extension at the head of the current
1617 function may be eliminated. */
1621 }
1622 }
1624 /* Called via note_stores. If X is a pseudo that is narrower than
1625 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1627 If we are setting only a portion of X and we can't figure out what
1628 portion, assume all bits will be used since we don't know what will
1629 be happening.
1631 Similarly, set how many bits of X are known to be copies of the sign bit
1632 at all locations in the function. This is the smallest number implied
1633 by any set of X. */
1635 static void
1637 {
1643 /* If this register is undefined at the start of the file, we can't
1644 say what its contents were. */
1645 && ! REGNO_REG_SET_P
1648 {
1652 {
1656 }
1658 /* If this register is being initialized using itself, and the
1659 register is uninitialized in this basic block, and there are
1660 no LOG_LINKS which set the register, then part of the
1661 register is uninitialized. In that case we can't assume
1662 anything about the number of nonzero bits.
1664 ??? We could do better if we checked this in
1665 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1666 could avoid making assumptions about the insn which initially
1667 sets the register, while still using the information in other
1668 insns. We would have to be careful to check every insn
1669 involved in the combination. */
1675 {
1682 {
1686 }
1687 }
1689 /* If this is a complex assignment, see if we can convert it into a
1690 simple assignment. */
1693 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1694 set what we know about X. */
1699 {
1702 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1703 /* If X is narrower than a word and SRC is a non-negative
1704 constant that would appear negative in the mode of X,
1705 sign-extend it for use in reg_stat[].nonzero_bits because some
1706 machines (maybe most) will actually do the sign-extension
1707 and this is the conservative approach.
1709 ??? For 2.5, try to tighten up the MD files in this regard
1710 instead of this kludge. */
1717 #endif
1719 /* Don't call nonzero_bits if it cannot change anything. */
1726 }
1727 else
1728 {
1731 }
1732 }
1733 }
1734 \f
1735 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1736 optionally insns that were previously combined into I3 or that will be
1737 combined into the merger of INSN and I3. The order is PRED, PRED2,
1738 INSN, SUCC, SUCC2, I3.
1740 Return 0 if the combination is not allowed for any reason.
1742 If the combination is allowed, *PDEST will be set to the single
1743 destination of INSN and *PSRC to the single source, and this function
1744 will return 1. */
1746 static int
1750 {
1755 #ifdef AUTO_INC_DEC
1756 rtx link;
1757 #endif
1762 {
1764 {
1769 }
1774 }
1778 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1779 or a PARALLEL consisting of such a SET and CLOBBERs.
1781 If INSN has CLOBBER parallel parts, ignore them for our processing.
1782 By definition, these happen during the execution of the insn. When it
1783 is merged with another insn, all bets are off. If they are, in fact,
1784 needed and aren't also supplied in I3, they may be added by
1785 recog_for_combine. Otherwise, it won't match.
1787 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1788 note.
1790 Get the source and destination of INSN. If more than one, can't
1791 combine. */
1797 {
1799 {
1803 {
1804 /* This is important to combine floating point insns
1805 for the SH4 port. */
1807 /* Combining an isolated USE doesn't make sense.
1808 We depend here on combinable_i3pat to reject them. */
1809 /* The code below this loop only verifies that the inputs of
1810 the SET in INSN do not change. We call reg_set_between_p
1811 to verify that the REG in the USE does not change between
1812 I3 and INSN.
1813 If the USE in INSN was for a pseudo register, the matching
1814 insn pattern will likely match any register; combining this
1815 with any other USE would only be safe if we knew that the
1816 used registers have identical values, or if there was
1817 something to tell them apart, e.g. different modes. For
1818 now, we forgo such complicated tests and simply disallow
1819 combining of USES of pseudo registers with any other USE. */
1822 {
1827 do
1828 {
1838 }
1840 }
1843 /* We can ignore CLOBBERs. */
1848 /* Ignore SETs whose result isn't used but not those that
1849 have side-effects. */
1855 /* If we have already found a SET, this is a second one and
1856 so we cannot combine with this insn. */
1864 /* Anything else means we can't combine. */
1866 }
1867 }
1870 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1871 so don't do anything with it. */
1874 }
1875 else
1881 /* The simplification in expand_field_assignment may call back to
1882 get_last_value, so set safe guard here. */
1888 /* Don't eliminate a store in the stack pointer. */
1890 /* Don't combine with an insn that sets a register to itself if it has
1891 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1893 /* Can't merge an ASM_OPERANDS. */
1895 /* Can't merge a function call. */
1897 /* Don't eliminate a function call argument. */
1903 /* Don't substitute into an incremented register. */
1907 /* Don't substitute into a non-local goto, this confuses CFG. */
1909 /* Make sure that DEST is not used after SUCC but before I3. */
1910 || (!all_adjacent
1911 && ((succ2
1915 /* Make sure that the value that is to be substituted for the register
1916 does not use any registers whose values alter in between. However,
1917 If the insns are adjacent, a use can't cross a set even though we
1918 think it might (this can happen for a sequence of insns each setting
1919 the same destination; last_set of that register might point to
1920 a NOTE). If INSN has a REG_EQUIV note, the register is always
1921 equivalent to the memory so the substitution is valid even if there
1922 are intervening stores. Also, don't move a volatile asm or
1923 UNSPEC_VOLATILE across any other insns. */
1924 || (! all_adjacent
1930 /* Don't combine across a CALL_INSN, because that would possibly
1931 change whether the life span of some REGs crosses calls or not,
1932 and it is a pain to update that information.
1933 Exception: if source is a constant, moving it later can't hurt.
1934 Accept that as a special case. */
1938 /* DEST must either be a REG or CC0. */
1940 {
1941 /* If register alignment is being enforced for multi-word items in all
1942 cases except for parameters, it is possible to have a register copy
1943 insn referencing a hard register that is not allowed to contain the
1944 mode being copied and which would not be valid as an operand of most
1945 insns. Eliminate this problem by not combining with such an insn.
1947 Also, on some machines we don't want to extend the life of a hard
1948 register. */
1953 /* Don't extend the life of a hard register unless it is
1954 user variable (if we have few registers) or it can't
1955 fit into the desired register (meaning something special
1956 is going on).
1957 Also avoid substituting a return register into I3, because
1958 reload can't handle a conflict with constraints of other
1959 inputs. */
1963 }
1971 {
1974 /* If the clobber represents an earlyclobber operand, we must not
1975 substitute an expression containing the clobbered register.
1976 As we do not analyze the constraint strings here, we have to
1977 make the conservative assumption. However, if the register is
1978 a fixed hard reg, the clobber cannot represent any operand;
1979 we leave it up to the machine description to either accept or
1980 reject use-and-clobber patterns. */
1986 }
1988 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 or not), reject, unless nothing volatile comes between it and I3 */
1992 {
1993 /* Make sure neither succ nor succ2 contains a volatile reference. */
1998 /* We'll check insns between INSN and I3 below. */
1999 }
2001 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 to be an explicit register variable, and was chosen for a reason. */
2008 /* If INSN contains volatile references (specifically volatile MEMs),
2009 we cannot combine across any other volatile references.
2010 Even if INSN doesn't contain volatile references, any intervening
2011 volatile insn might affect machine state. */
2014 ? volatile_refs_p
2021 /* If INSN contains an autoincrement or autodecrement, make sure that
2022 register is not used between there and I3, and not already used in
2023 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 Also insist that I3 not be a jump; if it were one
2025 and the incremented register were spilled, we would lose. */
2027 #ifdef AUTO_INC_DEC
2042 #endif
2044 #ifdef HAVE_cc0
2045 /* Don't combine an insn that follows a CC0-setting insn.
2046 An insn that uses CC0 must not be separated from the one that sets it.
2047 We do, however, allow I2 to follow a CC0-setting insn if that insn
2048 is passed as I1; in that case it will be deleted also.
2049 We also allow combining in this case if all the insns are adjacent
2050 because that would leave the two CC0 insns adjacent as well.
2051 It would be more logical to test whether CC0 occurs inside I1 or I2,
2052 but that would be much slower, and this ought to be equivalent. */
2058 #endif
2060 /* If we get here, we have passed all the tests and the combination is
2061 to be allowed. */
2067 }
2068 \f
2069 /* LOC is the location within I3 that contains its pattern or the component
2070 of a PARALLEL of the pattern. We validate that it is valid for combining.
2072 One problem is if I3 modifies its output, as opposed to replacing it
2073 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2074 doing so would produce an insn that is not equivalent to the original insns.
2076 Consider:
2078 (set (reg:DI 101) (reg:DI 100))
2079 (set (subreg:SI (reg:DI 101) 0) <foo>)
2081 This is NOT equivalent to:
2083 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2084 (set (reg:DI 101) (reg:DI 100))])
2086 Not only does this modify 100 (in which case it might still be valid
2087 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2089 We can also run into a problem if I2 sets a register that I1
2090 uses and I1 gets directly substituted into I3 (not via I2). In that
2091 case, we would be getting the wrong value of I2DEST into I3, so we
2092 must reject the combination. This case occurs when I2 and I1 both
2093 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2094 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2095 of a SET must prevent combination from occurring. The same situation
2096 can occur for I0, in which case I0_NOT_IN_SRC is set.
2098 Before doing the above check, we first try to expand a field assignment
2099 into a set of logical operations.
2101 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2102 we place a register that is both set and used within I3. If more than one
2103 such register is detected, we fail.
2105 Return 1 if the combination is valid, zero otherwise. */
2107 static int
2110 {
2114 {
2119 rtx subdest;
2126 /* Check for the case where I3 modifies its output, as discussed
2127 above. We don't want to prevent pseudos from being combined
2128 into the address of a MEM, so only prevent the combination if
2129 i1 or i2 set the same MEM. */
2139 /* This is the same test done in can_combine_p except we can't test
2140 all_adjacent; we don't have to, since this instruction will stay
2141 in place, thus we are not considering increasing the lifetime of
2142 INNER_DEST.
2144 Also, if this insn sets a function argument, combining it with
2145 something that might need a spill could clobber a previous
2146 function argument; the all_adjacent test in can_combine_p also
2147 checks this; here, we do a more specific test for this case. */
2157 /* If DEST is used in I3, it is being killed in this insn, so
2158 record that for later. We have to consider paradoxical
2159 subregs here, since they kill the whole register, but we
2160 ignore partial subregs, STRICT_LOW_PART, etc.
2161 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2162 STACK_POINTER_REGNUM, since these are always considered to be
2163 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2173 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2175 #endif
2176 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2179 #endif
2181 {
2186 }
2187 }
2190 {
2197 }
2200 }
2201 \f
2202 /* Return 1 if X is an arithmetic expression that contains a multiplication
2203 and division. We don't count multiplications by powers of two here. */
2205 static int
2207 {
2209 {
2225 }
2226 }
2227 \f
2228 /* Determine whether INSN can be used in a combination. Return nonzero if
2229 not. This is used in try_combine to detect early some cases where we
2230 can't perform combinations. */
2232 static int
2234 {
2235 rtx set;
2238 /* If this isn't really an insn, we can't do anything.
2239 This can occur when flow deletes an insn that it has merged into an
2240 auto-increment address. */
2244 /* Never combine loads and stores involving hard regs that are likely
2245 to be spilled. The register allocator can usually handle such
2246 reg-reg moves by tying. If we allow the combiner to make
2247 substitutions of likely-spilled regs, reload might die.
2248 As an exception, we allow combinations involving fixed regs; these are
2249 not available to the register allocator so there's no risk involved. */
2270 }
2272 struct likely_spilled_retval_info
2273 {
2276 };
2278 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2279 hard registers that are known to be written to / clobbered in full. */
2280 static void
2282 {
2299 else
2302 }
2304 /* Return nonzero iff part of the return value is live during INSN, and
2305 it is likely spilled. This can happen when more than one insn is needed
2306 to copy the return value, e.g. when we consider to combine into the
2307 second copy insn for a complex value. */
2309 static int
2311 {
2313 rtx reg;
2316 /* We assume here that no machine mode needs more than
2317 32 hard registers when the value overlaps with a register
2318 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2333 /* Disregard parts of the return value that are set later. */
2342 /* Check if any of the (probably) live return value registers is
2343 likely spilled. */
2344 nregs --;
2345 do
2346 {
2352 }
2354 /* Adjust INSN after we made a change to its destination.
2356 Changing the destination can invalidate notes that say something about
2357 the results of the insn and a LOG_LINK pointing to the insn. */
2359 static void
2361 {
2362 /* For notes, be conservative and simply remove them. */
2365 /* The new insn will have a destination that was previously the destination
2366 of an insn just above it. Call distribute_links to make a LOG_LINK from
2367 the next use of that destination. */
2383 }
2385 /* Return TRUE if combine can reuse reg X in mode MODE.
2386 ADDED_SETS is nonzero if the original set is still required. */
2387 static bool
2389 {
2396 /* Allow hard registers if the new mode is legal, and occupies no more
2397 registers than the old mode. */
2403 /* Or a pseudo that is only used once. */
2406 }
2409 /* Check whether X, the destination of a set, refers to part of
2410 the register specified by REG. */
2412 static bool
2414 {
2415 /* Check that reg is an integer mode register. */
2426 }
2428 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2429 Note that the INSN should be deleted *after* removing dead edges, so
2430 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2431 but not for a (set (pc) (label_ref FOO)). */
2433 static void
2435 {
2443 {
2448 /* Remove barriers from the footer if there are any. */
2451 {
2454 else
2458 }
2461 }
2462 }
2464 #ifndef HAVE_cc0
2465 /* Return whether INSN is a PARALLEL of exactly N register SETs followed
2466 by an arbitrary number of CLOBBERs. */
2467 static bool
2469 {
2489 }
2491 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2492 CLOBBERs), can be split into individual SETs in that order, without
2493 changing semantics. */
2494 static bool
2496 {
2504 {
2513 }
2516 }
2517 #endif
2519 /* Try to combine the insns I0, I1 and I2 into I3.
2520 Here I0, I1 and I2 appear earlier than I3.
2521 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2522 I3.
2524 If we are combining more than two insns and the resulting insn is not
2525 recognized, try splitting it into two insns. If that happens, I2 and I3
2526 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2527 Otherwise, I0, I1 and I2 are pseudo-deleted.
2529 Return 0 if the combination does not work. Then nothing is changed.
2530 If we did the combination, return the insn at which combine should
2531 resume scanning.
2533 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2534 new direct jump instruction.
2536 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2537 been I3 passed to an earlier try_combine within the same basic
2538 block. */
2543 {
2544 /* New patterns for I3 and I2, respectively. */
2548 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2549 dead. */
2551 /* Total number of SETs to put into I3. */
2553 /* Nonzero if I2's or I1's body now appears in I3. */
2555 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2557 /* Contains I3 if the destination of I3 is used in its source, which means
2558 that the old life of I3 is being killed. If that usage is placed into
2559 I2 and not in I3, a REG_DEAD note must be made. */
2561 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2563 /* Copy of SET_SRC of I1 and I0, if needed. */
2565 /* Set if I2DEST was reused as a scratch register. */
2567 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2569 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2574 /* Notes that must be added to REG_NOTES in I3 and I2. */
2576 /* Notes that we substituted I3 into I2 instead of the normal case. */
2578 /* Notes that I1, I2 or I3 is a MULT operation. */
2585 rtx temp_expr;
2588 rtx new_other_notes;
2591 /* Only try four-insn combinations when there's high likelihood of
2592 success. Look for simple insns, such as loads of constants or
2593 binary operations involving a constant. */
2595 {
2604 {
2607 rtx src;
2612 {
2615 }
2617 ngood++;
2620 nshift++;
2621 }
2624 }
2626 /* Exit early if one of the insns involved can't be used for
2627 combinations. */
2638 combine_attempts++;
2641 /* Reset the hard register usage information. */
2645 {
2652 else
2655 }
2657 /* If multiple insns feed into one of I2 or I3, they can be in any
2658 order. To simplify the code below, reorder them in sequence. */
2668 /* First check for one important special case that the code below will
2669 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2670 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2671 we may be able to replace that destination with the destination of I3.
2672 This occurs in the common code where we compute both a quotient and
2673 remainder into a structure, in which case we want to do the computation
2674 directly into the structure to avoid register-register copies.
2676 Note that this case handles both multiple sets in I2 and also cases
2677 where I2 has a number of CLOBBERs inside the PARALLEL.
2679 We make very conservative checks below and only try to handle the
2680 most common cases of this. For example, we only handle the case
2681 where I2 and I3 are adjacent to avoid making difficult register
2682 usage tests. */
2690 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2691 below would need to check what is inside (and reg_overlap_mentioned_p
2692 doesn't support those codes anyway). Don't allow those destinations;
2693 the resulting insn isn't likely to be recognized anyway. */
2699 {
2702 /* Make sure that the destination of I3,
2703 which we are going to substitute into one output of I2,
2704 is not used within another output of I2. We must avoid making this:
2705 (parallel [(set (mem (reg 69)) ...)
2706 (set (reg 69) ...)])
2707 which is not well-defined as to order of actions.
2708 (Besides, reload can't handle output reloads for this.)
2710 The problem can also happen if the dest of I3 is a memory ref,
2711 if another dest in I2 is an indirect memory ref. */
2719 /* Make sure this PARALLEL is not an asm. We do not allow combining
2720 that usually (see can_combine_p), so do not here either. */
2730 {
2731 combine_merges++;
2741 /* Replace the dest in I2 with our dest and make the resulting
2742 insn the new pattern for I3. Then skip to where we validate
2743 the pattern. Everything was set up above. */
2748 }
2749 }
2751 /* If I2 is setting a pseudo to a constant and I3 is setting some
2752 sub-part of it to another constant, merge them by making a new
2753 constant. */
2760 {
2766 {
2769 {
2775 }
2776 }
2777 else
2778 {
2783 }
2786 {
2787 /* If this is the low part, we're done. */
2789 ;
2790 /* Handle the case where inner is twice the size of outer. */
2794 /* Otherwise give up for now. */
2795 else
2797 }
2800 {
2804 wide_int o
2809 combine_merges++;
2816 /* Replace the source in I2 with the new constant and make the
2817 resulting insn the new pattern for I3. Then skip to where we
2818 validate the pattern. Everything was set up above. */
2824 /* The dest of I3 has been replaced with the dest of I2. */
2827 }
2828 }
2830 #ifndef HAVE_cc0
2831 /* If we have no I1 and I2 looks like:
2832 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2833 (set Y OP)])
2834 make up a dummy I1 that is
2835 (set Y OP)
2836 and change I2 to be
2837 (set (reg:CC X) (compare:CC Y (const_int 0)))
2839 (We can ignore any trailing CLOBBERs.)
2841 This undoes a previous combination and allows us to match a branch-and-
2842 decrement insn. */
2854 {
2855 /* We make I1 with the same INSN_UID as I2. This gives it
2856 the same DF_INSN_LUID for value tracking. Our fake I1 will
2857 never appear in the insn stream so giving it the same INSN_UID
2858 as I2 will not cause a problem. */
2871 }
2873 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2874 make those two SETs separate I1 and I2 insns, and make an I0 that is
2875 the original I1. */
2881 {
2882 /* If there is no I1, there is no I0 either. */
2885 /* We make I1 with the same INSN_UID as I2. This gives it
2886 the same DF_INSN_LUID for value tracking. Our fake I1 will
2887 never appear in the insn stream so giving it the same INSN_UID
2888 as I2 will not cause a problem. */
2896 }
2897 #endif
2899 /* Verify that I2 and I1 are valid for combining. */
2905 {
2908 }
2910 /* Record whether I2DEST is used in I2SRC and similarly for the other
2911 cases. Knowing this will help in register status updating below. */
2922 /* For the earlier insns, determine which of the subsequent ones they
2923 feed. */
2930 /* Ensure that I3's pattern can be the destination of combines. */
2936 {
2939 }
2941 /* See if any of the insns is a MULT operation. Unless one is, we will
2942 reject a combination that is, since it must be slower. Be conservative
2943 here. */
2951 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2952 We used to do this EXCEPT in one case: I3 has a post-inc in an
2953 output operand. However, that exception can give rise to insns like
2954 mov r3,(r3)+
2955 which is a famous insn on the PDP-11 where the value of r3 used as the
2956 source was model-dependent. Avoid this sort of thing. */
2958 #if 0
2964 /* It's not the exception. */
2965 #endif
2966 #ifdef AUTO_INC_DEC
2967 {
2968 rtx link;
2974 {
2977 }
2978 }
2979 #endif
2981 /* See if the SETs in I1 or I2 need to be kept around in the merged
2982 instruction: whenever the value set there is still needed past I3.
2983 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2985 For the SET in I1, we have two cases: if I1 and I2 independently feed
2986 into I3, the set in I1 needs to be kept around unless I1DEST dies
2987 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2988 in I1 needs to be kept around unless I1DEST dies or is set in either
2989 I2 or I3. The same considerations apply to I0. */
2996 else
3004 else
3007 /* We are about to copy insns for the case where they need to be kept
3008 around. Check that they can be copied in the merged instruction. */
3014 {
3017 }
3019 /* If the set in I2 needs to be kept around, we must make a copy of
3020 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3021 PATTERN (I2), we are only substituting for the original I1DEST, not into
3022 an already-substituted copy. This also prevents making self-referential
3023 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3024 I2DEST. */
3027 {
3030 else
3032 }
3035 {
3038 else
3040 }
3043 {
3046 else
3048 }
3050 combine_merges++;
3052 /* Substitute in the latest insn for the regs set by the earlier ones. */
3058 #ifndef HAVE_cc0
3059 /* Many machines that don't use CC0 have insns that can both perform an
3060 arithmetic operation and set the condition code. These operations will
3061 be represented as a PARALLEL with the first element of the vector
3062 being a COMPARE of an arithmetic operation with the constant zero.
3063 The second element of the vector will set some pseudo to the result
3064 of the same arithmetic operation. If we simplify the COMPARE, we won't
3065 match such a pattern and so will generate an extra insn. Here we test
3066 for this case, where both the comparison and the operation result are
3067 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3068 I2SRC. Later we will make the PARALLEL that contains I2. */
3074 {
3075 rtx newpat_dest;
3089 {
3094 }
3096 /* Do the rest only if op1 is const0_rtx, which may be the
3097 result of simplification. */
3099 {
3100 /* If a single use of the CC is found, prepare to modify it
3101 when SELECT_CC_MODE returns a new CC-class mode, or when
3102 the above simplify_compare_const() returned a new comparison
3103 operator. undobuf.other_insn is assigned the CC use insn
3104 when modifying it. */
3106 {
3107 #ifdef SELECT_CC_MODE
3108 machine_mode new_mode
3113 {
3118 else
3119 {
3122 }
3123 }
3124 #endif
3125 /* Cases for modifying the CC-using comparison. */
3127 /* ??? Do we need to verify the zero rtx? */
3129 {
3130 /* Replace cc_use_loc with entire new RTX. */
3135 }
3137 {
3138 /* Just replace the CC reg with a new mode. */
3141 }
3142 }
3144 /* Now we modify the current newpat:
3145 First, SET_DEST(newpat) is updated if the CC mode has been
3146 altered. For targets without SELECT_CC_MODE, this should be
3147 optimized away. */
3150 /* This is always done to propagate i2src into newpat. */
3153 /* Create new version of i2pat if needed; the below PARALLEL
3154 creation needs this to work correctly. */
3158 }
3159 }
3160 #endif
3163 {
3164 /* It is possible that the source of I2 or I1 may be performing
3165 an unneeded operation, such as a ZERO_EXTEND of something
3166 that is known to have the high part zero. Handle that case
3167 by letting subst look at the inner insns.
3169 Another way to do this would be to have a function that tries
3170 to simplify a single insn instead of merging two or more
3171 insns. We don't do this because of the potential of infinite
3172 loops and because of the potential extra memory required.
3173 However, doing it the way we are is a bit of a kludge and
3174 doesn't catch all cases.
3176 But only do this if -fexpensive-optimizations since it slows
3177 things down and doesn't usually win.
3179 This is not done in the COMPARE case above because the
3180 unmodified I2PAT is used in the PARALLEL and so a pattern
3181 with a modified I2SRC would not match. */
3184 {
3185 /* Pass pc_rtx so no substitutions are done, just
3186 simplifications. */
3188 {
3191 }
3195 }
3200 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3201 copy of I2SRC each time we substitute it, in order to avoid creating
3202 self-referential RTL when we will be substituting I1SRC for I1DEST
3203 later. Likewise if I0 feeds into I2, either directly or indirectly
3204 through I1, and I0DEST is in I0SRC. */
3211 /* Record whether I2's body now appears within I3's body. */
3213 }
3215 /* If we already got a failure, don't try to do more. Otherwise, try to
3216 substitute I1 if we have it. */
3219 {
3220 /* Check that an autoincrement side-effect on I1 has not been lost.
3221 This happens if I1DEST is mentioned in I2 and dies there, and
3222 has disappeared from the new pattern. */
3224 && i1_feeds_i2_n
3227 /* Before we can do this substitution, we must redo the test done
3228 above (see detailed comments there) that ensures I1DEST isn't
3229 mentioned in any SETs in NEWPAT that are field assignments. */
3232 {
3235 }
3240 /* If the following substitution will modify I1SRC, make a copy of it
3241 for the case where it is substituted for I1DEST in I2PAT later. */
3245 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3246 copy of I1SRC each time we substitute it, in order to avoid creating
3247 self-referential RTL when we will be substituting I0SRC for I0DEST
3248 later. */
3253 /* Record whether I1's body now appears within I3's body. */
3255 }
3257 /* Likewise for I0 if we have it. */
3260 {
3267 {
3270 }
3272 /* If the following substitution will modify I0SRC, make a copy of it
3273 for the case where it is substituted for I0DEST in I1PAT later. */
3276 /* And a copy for I0DEST in I2PAT substitution. */
3285 }
3287 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3288 to count all the ways that I2SRC and I1SRC can be used. */
3299 /* Fail if we tried to make a new register. */
3301 /* Fail if we couldn't do something and have a CLOBBER. */
3303 /* Fail if this new pattern is a MULT and we didn't have one before
3304 at the outer level. */
3307 {
3310 }
3312 /* If the actions of the earlier insns must be kept
3313 in addition to substituting them into the latest one,
3314 we must make a new PARALLEL for the latest insn
3315 to hold additional the SETs. */
3318 {
3320 combine_extras++;
3323 {
3329 }
3330 else
3331 {
3336 }
3342 {
3348 }
3350 {
3359 }
3360 }
3362 validate_replacement:
3364 /* Note which hard regs this insn has as inputs. */
3367 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3368 consider splitting this pattern, we might need these clobbers. */
3371 {
3377 }
3379 /* We have recognized nothing yet. */
3382 /* See if this is a PARALLEL of two SETs where one SET's destination is
3383 a register that is unused and this isn't marked as an instruction that
3384 might trap in an EH region. In that case, we just need the other SET.
3385 We prefer this over the PARALLEL.
3387 This can occur when simplifying a divmod insn. We *must* test for this
3388 case here because the code below that splits two independent SETs doesn't
3389 handle this case correctly when it updates the register status.
3391 It's pointless doing this if we originally had two sets, one from
3392 i3, and one from i2. Combining then splitting the parallel results
3393 in the original i2 again plus an invalid insn (which we delete).
3394 The net effect is only to move instructions around, which makes
3395 debug info less accurate. */
3403 {
3414 {
3417 }
3426 {
3432 }
3436 }
3438 /* Is the result of combination a valid instruction? */
3442 /* If we were combining three insns and the result is a simple SET
3443 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3444 insns. There are two ways to do this. It can be split using a
3445 machine-specific method (like when you have an addition of a large
3446 constant) or by combine in the function find_split_point. */
3450 {
3454 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3455 use I2DEST as a scratch register will help. In the latter case,
3456 convert I2DEST to the mode of the source of NEWPAT if we can. */
3460 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3461 inputs of NEWPAT. */
3463 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3464 possible to try that as a scratch reg. This would require adding
3465 more code to make it work though. */
3468 {
3471 /* First try to split using the original register as a
3472 scratch register. */
3476 i2dest)));
3479 /* If that didn't work, try changing the mode of I2DEST if
3480 we can. */
3485 {
3487 rtx ni2dest;
3491 else
3492 {
3495 }
3497 parallel = (gen_rtx_PARALLEL
3501 ni2dest))));
3506 {
3514 }
3515 }
3518 }
3520 /* If recog_for_combine has discarded clobbers, try to use them
3521 again for the split. */
3523 {
3526 }
3529 {
3534 }
3538 {
3548 /* If I2 or I3 has multiple SETs, we won't know how to track
3549 register status, so don't use these insns. If I2's destination
3550 is used between I2 and I3, we also can't use these insns. */
3560 /* It is possible that both insns now set the destination of I3.
3561 If so, we must show an extra use of it. */
3564 {
3582 }
3583 }
3585 /* If we can split it and use I2DEST, go ahead and see if that
3586 helps things be recognized. Verify that none of the registers
3587 are set between I2 and I3. */
3590 #ifdef HAVE_cc0
3592 #endif
3593 /* We need I2DEST in the proper mode. If it is a hard register
3594 or the only use of a pseudo, we can change its mode.
3595 Make sure we don't change a hard register to have a mode that
3596 isn't valid for it, or change the number of registers. */
3603 /* We can't overwrite I2DEST if its value is still used by
3604 NEWPAT. */
3606 {
3615 /* *SPLIT may be part of I2SRC, so make sure we have the
3616 original expression around for later debug processing.
3617 We should not need I2SRC any more in other cases. */
3620 else
3623 /* Get NEWDEST as a register in the proper mode. We have already
3624 validated that we can do this. */
3626 {
3629 else
3630 {
3633 }
3634 }
3636 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3637 an ASHIFT. This can occur if it was inside a PLUS and hence
3638 appeared to be a memory address. This is a kludge. */
3643 {
3646 /* Update split_code because we may not have a multiply
3647 anymore. */
3649 }
3651 #ifdef INSN_SCHEDULING
3652 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3653 be written as a ZERO_EXTEND. */
3655 {
3656 #ifdef LOAD_EXTEND_OP
3657 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3658 what it really is. */
3663 else
3664 #endif
3667 }
3668 #endif
3670 /* Attempt to split binary operators using arithmetic identities. */
3674 {
3681 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3683 {
3688 }
3689 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3696 {
3702 /* Split both "((X op Y) op X) op Y" and
3703 "((X op Y) op Y) op X" as "T op T" where T is
3704 "X op Y". */
3707 {
3713 }
3714 /* Split "((X op X) op Y) op Y)" as "T op T" where
3715 T is "X op Y". */
3717 {
3723 }
3724 }
3725 }
3728 {
3731 }
3735 /* recog_for_combine might have added CLOBBERs to newi2pat.
3736 Make sure NEWPAT does not depend on the clobbered regs. */
3740 {
3743 {
3746 }
3747 }
3749 /* If the split point was a MULT and we didn't have one before,
3750 don't use one now. */
3753 }
3754 }
3756 /* Check for a case where we loaded from memory in a narrow mode and
3757 then sign extended it, but we need both registers. In that case,
3758 we have a PARALLEL with both loads from the same memory location.
3759 We can split this into a load from memory followed by a register-register
3760 copy. This saves at least one insn, more if register allocation can
3761 eliminate the copy.
3763 We cannot do this if the destination of the first assignment is a
3764 condition code register or cc0. We eliminate this case by making sure
3765 the SET_DEST and SET_SRC have the same mode.
3767 We cannot do this if the destination of the second assignment is
3768 a register that we have already assumed is zero-extended. Similarly
3769 for a SUBREG of such a register. */
3804 {
3805 rtx ni2dest;
3819 }
3821 /* Similarly, check for a case where we have a PARALLEL of two independent
3822 SETs but we started with three insns. In this case, we can do the sets
3823 as two separate insns. This case occurs when some SET allows two
3824 other insns to combine, but the destination of that SET is still live.
3826 Also do this if we started with two insns and (at least) one of the
3827 resulting sets is a noop; this noop will be deleted later. */
3846 {
3850 /* Normally, it doesn't matter which of the two is done first,
3851 but the one that references cc0 can't be the second, and
3852 one which uses any regs/memory set in between i2 and i3 can't
3853 be first. The PARALLEL might also have been pre-existing in i3,
3854 so we need to make sure that we won't wrongly hoist a SET to i2
3855 that would conflict with a death note present in there. */
3862 #ifdef HAVE_cc0
3864 #endif
3865 /* If I3 is a jump, ensure that set0 is a jump so that
3866 we do not create invalid RTL. */
3868 )
3869 {
3872 }
3879 #ifdef HAVE_cc0
3881 #endif
3882 /* If I3 is a jump, ensure that set1 is a jump so that
3883 we do not create invalid RTL. */
3885 )
3886 {
3889 }
3890 else
3891 {
3894 }
3899 {
3900 /* recog_for_combine might have added CLOBBERs to newi2pat.
3901 Make sure NEWPAT does not depend on the clobbered regs. */
3903 {
3906 {
3909 {
3912 }
3913 }
3914 }
3917 }
3918 }
3920 /* If it still isn't recognized, fail and change things back the way they
3921 were. */
3923 /* Is the result a reasonable ASM_OPERANDS? */
3925 {
3928 }
3930 /* If we had to change another insn, make sure it is valid also. */
3932 {
3940 {
3943 }
3944 }
3946 #ifdef HAVE_cc0
3947 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3948 they are adjacent to each other or not. */
3949 {
3953 {
3956 }
3957 }
3958 #endif
3960 /* Only allow this combination if insn_rtx_costs reports that the
3961 replacement instructions are cheaper than the originals. */
3963 {
3966 }
3969 {
3974 {
3979 /* Temporarily revert mode back. */
3983 {
3984 /* If we used i2dest as a scratch register with a
3985 different mode, substitute it for the original
3986 i2src while its original mode is temporarily
3987 restored, and then clear i2scratch so that we don't
3988 do it again later. */
3990 this_basic_block);
3992 /* Put back the new mode. */
3994 }
3995 else
3996 {
4001 {
4004 }
4005 else
4006 {
4013 }
4015 /* We're dealing with a reg that changed mode but not
4016 meaning, so we want to turn it into a subreg for
4017 the new mode. However, because of REG sharing and
4018 because its mode had already changed, we have to do
4019 it in two steps. First, replace any debug uses of
4020 reg, with its original mode temporarily restored,
4021 with this copy we have created; then, replace the
4022 copy with the SUBREG of the original shared reg,
4023 once again changed to the new mode. */
4025 this_basic_block);
4029 this_basic_block);
4030 }
4031 }
4032 }
4034 /* If we will be able to accept this, we have made a
4035 change to the destination of I3. This requires us to
4036 do a few adjustments. */
4039 {
4042 }
4044 /* We now know that we can do this combination. Merge the insns and
4045 update the status of registers and LOG_LINKS. */
4048 {
4053 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4054 ensure that they are still valid. Then add any non-duplicate
4055 notes added by recog_for_combine. */
4057 {
4067 }
4071 NULL_RTX);
4072 }
4075 {
4078 rtx ni2dest;
4080 /* I3 now uses what used to be its destination and which is now
4081 I2's destination. This requires us to do a few adjustments. */
4085 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4086 so we still will.
4088 However, some later insn might be using I2's dest and have
4089 a LOG_LINK pointing at I3. We must remove this link.
4090 The simplest way to remove the link is to point it at I1,
4091 which we know will be a NOTE. */
4093 /* newi2pat is usually a SET here; however, recog_for_combine might
4094 have added some clobbers. */
4097 else
4104 {
4106 {
4112 }
4113 }
4114 }
4116 {
4121 /* Compute which registers we expect to eliminate. newi2pat may be setting
4122 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4123 same as i3dest, in which case newi2pat may be setting i1dest. */
4126 || !i2dest_killed
4130 || !i1dest_killed
4134 || !i0dest_killed
4137 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4138 clear them. */
4146 /* Ensure that we do not have something that should not be shared but
4147 occurs multiple times in the new insns. Check this by first
4148 resetting all the `used' flags and then copying anything is shared. */
4172 {
4179 {
4180 /* I2SRC must still be meaningful at this point. Some splitting
4181 operations can invalidate I2SRC, but those operations do not
4182 apply to calls. */
4185 }
4193 }
4198 /* We had one special case above where I2 had more than one set and
4199 we replaced a destination of one of those sets with the destination
4200 of I3. In that case, we have to update LOG_LINKS of insns later
4201 in this basic block. Note that this (expensive) case is rare.
4203 Also, in this case, we must pretend that all REG_NOTEs for I2
4204 actually came from I3, so that REG_UNUSED notes from I2 will be
4205 properly handled. */
4208 {
4217 temp_insn
4227 {
4232 }
4233 else
4236 }
4244 {
4247 this_basic_block);
4250 }
4251 else
4252 {
4255 this_basic_block);
4257 }
4260 {
4265 this_basic_block);
4267 }
4270 {
4275 this_basic_block);
4277 }
4279 /* Get death notes for everything that is now used in either I3 or
4280 I2 and used to die in a previous insn. If we built two new
4281 patterns, move from I1 to I2 then I2 to I3 so that we get the
4282 proper movement on registers that I2 modifies. */
4288 else
4294 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4311 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4312 know these are REG_UNUSED and want them to go to the desired insn,
4313 so we always pass it as i3. */
4317 NULL_RTX);
4321 NULL_RTX);
4323 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4324 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4325 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4326 in that case, it might delete I2. Similarly for I2 and I1.
4327 Show an additional death due to the REG_DEAD note we make here. If
4328 we discard it in distribute_notes, we will decrement it again. */
4331 {
4336 else
4339 }
4342 {
4347 else
4350 }
4353 {
4358 else
4361 }
4364 {
4369 else
4372 }
4380 {
4385 /* The insn that used to set this register doesn't exist, and
4386 this life of the register may not exist either. See if one of
4387 I3's links points to an insn that sets I2DEST. If it does,
4388 that is now the last known value for I2DEST. If we don't update
4389 this and I2 set the register to a value that depended on its old
4390 contents, we will get confused. If this insn is used, thing
4391 will be set correctly in combine_instructions. */
4399 /* If the reg formerly set in I2 died only once and that was in I3,
4400 zero its use count so it won't make `reload' do any work. */
4405 }
4408 {
4422 }
4425 {
4439 }
4441 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4442 been made to this insn. The order is important, because newi2pat
4443 can affect nonzero_bits of newpat. */
4447 }
4450 {
4452 {
4455 }
4457 }
4460 {
4462 {
4465 }
4467 }
4470 {
4472 {
4475 }
4477 }
4480 {
4482 {
4485 }
4487 }
4490 {
4492 {
4495 }
4497 }
4499 /* Set new_direct_jump_p if a new return or simple jump instruction
4500 has been created. Adjust the CFG accordingly. */
4502 {
4506 }
4511 {
4514 }
4516 /* A noop might also need cleaning up of CFG, if it comes from the
4517 simplification of a jump. */
4522 {
4525 }
4532 {
4535 }
4537 combine_successes++;
4544 else
4546 }
4547 \f
4548 /* Undo all the modifications recorded in undobuf. */
4550 static void
4552 {
4556 {
4559 {
4574 }
4578 }
4581 }
4583 /* We've committed to accepting the changes we made. Move all
4584 of the undos to the free list. */
4586 static void
4588 {
4592 {
4596 }
4598 }
4599 \f
4600 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4601 where we have an arithmetic expression and return that point. LOC will
4602 be inside INSN.
4604 try_combine will call this function to see if an insn can be split into
4605 two insns. */
4609 {
4618 /* First special-case some codes. */
4620 {
4622 #ifdef INSN_SCHEDULING
4623 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4624 point. */
4627 #endif
4631 #ifdef HAVE_lo_sum
4632 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4633 using LO_SUM and HIGH. */
4636 {
4644 }
4645 #endif
4647 /* If we have a PLUS whose second operand is a constant and the
4648 address is not valid, perhaps will can split it up using
4649 the machine-specific way to split large constants. We use
4650 the first pseudo-reg (one of the virtual regs) as a placeholder;
4651 it will not remain in the result. */
4656 {
4660 subst_insn);
4662 /* This should have produced two insns, each of which sets our
4663 placeholder. If the source of the second is a valid address,
4664 we can make put both sources together and make a split point
4665 in the middle. */
4678 && memory_address_addr_space_p
4681 {
4685 /* Replace the placeholder in SRC2 with SRC1. If we can
4686 find where in SRC2 it was placed, that can become our
4687 split point and we can replace this address with SRC2.
4688 Just try two obvious places. */
4699 {
4702 }
4703 }
4705 /* If that didn't work, perhaps the first operand is complex and
4706 needs to be computed separately, so make a split point there.
4707 This will occur on machines that just support REG + CONST
4708 and have a constant moved through some previous computation. */
4714 }
4716 /* If we have a PLUS whose first operand is complex, try computing it
4717 separately by making a split there. */
4728 #ifdef HAVE_cc0
4729 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4730 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4731 we need to put the operand into a register. So split at that
4732 point. */
4741 #endif
4743 /* See if we can split SET_SRC as it stands. */
4748 /* See if we can split SET_DEST as it stands. */
4753 /* See if this is a bitfield assignment with everything constant. If
4754 so, this is an IOR of an AND, so split it into that. */
4764 {
4770 unsigned HOST_WIDE_INT mask
4772 rtx or_mask;
4781 else
4782 {
4788 or_mask));
4789 }
4796 }
4798 /* Otherwise, see if this is an operation that we can split into two.
4799 If so, try to split that. */
4803 {
4805 /* If we are AND'ing with a large constant that is only a single
4806 bit and the result is only being used in a context where we
4807 need to know if it is zero or nonzero, replace it with a bit
4808 extraction. This will avoid the large constant, which might
4809 have taken more than one insn to make. If the constant were
4810 not a valid argument to the AND but took only one insn to make,
4811 this is no worse, but if it took more than one insn, it will
4812 be better. */
4822 {
4827 {
4830 }
4831 }
4835 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4836 is known to be on, this can be converted into a NEG of a shift. */
4842 {
4854 }
4860 /* We can't optimize if either mode is a partial integer
4861 mode as we don't know how many bits are significant
4862 in those modes. */
4876 {
4884 }
4889 }
4893 {
4896 /* For unsigned, we have a choice of a shift followed by an
4897 AND or two shifts. Use two shifts for field sizes where the
4898 constant might be too large. We assume here that we can
4899 always at least get 8-bit constants in an AND insn, which is
4900 true for every current RISC. */
4903 {
4904 unsigned HOST_WIDE_INT mask
4908 gen_rtx_LSHIFTRT
4916 }
4917 else
4918 {
4920 gen_rtx_fmt_ee
4931 }
4932 }
4934 /* See if this is a simple operation with a constant as the second
4935 operand. It might be that this constant is out of range and hence
4936 could be used as a split point. */
4944 /* Finally, see if this is a simple operation with its first operand
4945 not in a register. The operation might require this operand in a
4946 register, so return it as a split point. We can always do this
4947 because if the first operand were another operation, we would have
4948 already found it as a split point. */
4957 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4958 it is better to write this as (not (ior A B)) so we can split it.
4959 Similarly for IOR. */
4961 {
4969 }
4971 /* Many RISC machines have a large set of logical insns. If the
4972 second operand is a NOT, put it first so we will try to split the
4973 other operand first. */
4975 {
4979 }
4984 /* Canonicalization can produce (minus A (mult B C)), where C is a
4985 constant. It may be better to try splitting (plus (mult B -C) A)
4986 instead if this isn't a multiply by a power of two. */
4990 {
4998 mode)),
5001 }
5003 /* Split at a multiply-accumulate instruction. However if this is
5004 the SET_SRC, we likely do not have such an instruction and it's
5005 worthless to try this split. */
5011 }
5013 /* Otherwise, select our actions depending on our rtx class. */
5015 {
5021 /* ... fall through ... */
5029 /* ... fall through ... */
5031 /* Some machines have (and (shift ...) ...) insns. If X is not
5032 an AND, but XEXP (X, 0) is, use it as our split point. */
5042 /* Otherwise, we don't have a split point. */
5044 }
5045 }
5046 \f
5047 /* Throughout X, replace FROM with TO, and return the result.
5048 The result is TO if X is FROM;
5049 otherwise the result is X, but its contents may have been modified.
5050 If they were modified, a record was made in undobuf so that
5051 undo_all will (among other things) return X to its original state.
5053 If the number of changes necessary is too much to record to undo,
5054 the excess changes are not made, so the result is invalid.
5055 The changes already made can still be undone.
5056 undobuf.num_undo is incremented for such changes, so by testing that
5057 the caller can tell whether the result is valid.
5059 `n_occurrences' is incremented each time FROM is replaced.
5061 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5063 IN_COND is nonzero if we are at the top level of a condition.
5065 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5066 by copying if `n_occurrences' is nonzero. */
5068 static rtx
5070 {
5075 rtx new_rtx;
5077 /* Two expressions are equal if they are identical copies of a shared
5078 RTX or if they are both registers with the same register number
5079 and mode. */
5081 #define COMBINE_RTX_EQUAL_P(X,Y) \
5082 ((X) == (Y) \
5083 || (REG_P (X) && REG_P (Y) \
5084 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5086 /* Do not substitute into clobbers of regs -- this will never result in
5087 valid RTL. */
5092 {
5093 n_occurrences++;
5095 }
5097 /* If X and FROM are the same register but different modes, they
5098 will not have been seen as equal above. However, the log links code
5099 will make a LOG_LINKS entry for that case. If we do nothing, we
5100 will try to rerecognize our original insn and, when it succeeds,
5101 we will delete the feeding insn, which is incorrect.
5103 So force this insn not to match in this (rare) case. */
5108 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5109 of which may contain things that can be combined. */
5113 /* It is possible to have a subexpression appear twice in the insn.
5114 Suppose that FROM is a register that appears within TO.
5115 Then, after that subexpression has been scanned once by `subst',
5116 the second time it is scanned, TO may be found. If we were
5117 to scan TO here, we would find FROM within it and create a
5118 self-referent rtl structure which is completely wrong. */
5122 /* Parallel asm_operands need special attention because all of the
5123 inputs are shared across the arms. Furthermore, unsharing the
5124 rtl results in recognition failures. Failure to handle this case
5125 specially can result in circular rtl.
5127 Solve this by doing a normal pass across the first entry of the
5128 parallel, and only processing the SET_DESTs of the subsequent
5129 entries. Ug. */
5134 {
5137 /* If this substitution failed, this whole thing fails. */
5145 {
5151 {
5154 /* If this substitution failed, this whole thing fails. */
5160 }
5161 }
5162 }
5163 else
5164 {
5168 /* We don't need to process a SET_DEST that is a register, CC0,
5169 or PC, so set up to skip this common case. All other cases
5170 where we want to suppress replacing something inside a
5171 SET_SRC are handled via the IN_DEST operand. */
5178 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5179 constant. */
5184 {
5186 {
5189 {
5191 {
5194 n_occurrences++;
5195 }
5196 else
5197 {
5199 unique_copy);
5201 /* If this substitution failed, this whole thing
5202 fails. */
5206 }
5209 }
5210 }
5212 {
5213 /* If this is a register being set, ignore it. */
5220 ;
5223 {
5224 /* In general, don't install a subreg involving two
5225 modes not tieable. It can worsen register
5226 allocation, and can even make invalid reload
5227 insns, since the reg inside may need to be copied
5228 from in the outside mode, and that may be invalid
5229 if it is an fp reg copied in integer mode.
5231 We allow two exceptions to this: It is valid if
5232 it is inside another SUBREG and the mode of that
5233 SUBREG and the mode of the inside of TO is
5234 tieable and it is valid if X is a SET that copies
5235 FROM to CC0. */
5243 #ifdef HAVE_cc0
5245 #endif
5246 )
5258 n_occurrences++;
5259 }
5260 else
5261 /* If we are in a SET_DEST, suppress most cases unless we
5262 have gone inside a MEM, in which case we want to
5263 simplify the address. We assume here that things that
5264 are actually part of the destination have their inner
5265 parts in the first expression. This is true for SUBREG,
5266 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5267 things aside from REG and MEM that should appear in a
5268 SET_DEST. */
5270 (((in_dest
5276 unique_copy);
5278 /* If we found that we will have to reject this combination,
5279 indicate that by returning the CLOBBER ourselves, rather than
5280 an expression containing it. This will speed things up as
5281 well as prevent accidents where two CLOBBERs are considered
5282 to be equal, thus producing an incorrect simplification. */
5288 {
5296 }
5299 {
5303 }
5304 else
5306 }
5307 }
5308 }
5310 /* Check if we are loading something from the constant pool via float
5311 extension; in this case we would undo compress_float_constant
5312 optimization and degenerate constant load to an immediate value. */
5316 {
5320 }
5322 /* Try to simplify X. If the simplification changed the code, it is likely
5323 that further simplification will help, so loop, but limit the number
5324 of repetitions that will be performed. */
5327 {
5328 /* If X is sufficiently simple, don't bother trying to do anything
5329 with it. */
5338 /* We no longer know the original mode of operand 0 since we
5339 have changed the form of X) */
5341 }
5344 }
5345 \f
5346 /* Simplify X, a piece of RTL. We just operate on the expression at the
5347 outer level; call `subst' to simplify recursively. Return the new
5348 expression.
5350 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5351 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5352 of a condition. */
5354 static rtx
5357 {
5360 rtx temp;
5363 /* If this is a commutative operation, put a constant last and a complex
5364 expression first. We don't need to do this for comparisons here. */
5367 {
5371 }
5373 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5374 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5375 things. Check for cases where both arms are testing the same
5376 condition.
5378 Don't do anything if all operands are very simple. */
5391 {
5396 /* If everything is a comparison, what we have is highly unlikely
5397 to be simpler, so don't use it. */
5400 {
5407 /* Simplify the alternative arms; this may collapse the true and
5408 false arms to store-flag values. Be careful to use copy_rtx
5409 here since true_rtx or false_rtx might share RTL with x as a
5410 result of the if_then_else_cond call above. */
5414 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5415 is unlikely to be simpler. */
5418 {
5421 /* Restarting if we generate a store-flag expression will cause
5422 us to loop. Just drop through in this case. */
5424 /* If the result values are STORE_FLAG_VALUE and zero, we can
5425 just make the comparison operation. */
5436 /* Likewise, we can make the negate of a comparison operation
5437 if the result values are - STORE_FLAG_VALUE and zero. */
5445 mode);
5456 mode);
5457 else
5460 mode,
5461 VOIDmode,
5462 cond,
5463 cop1),
5468 }
5469 }
5470 }
5472 /* Try to fold this expression in case we have constants that weren't
5473 present before. */
5476 {
5484 {
5487 {
5491 }
5494 }
5507 }
5510 {
5515 }
5517 /* First see if we can apply the inverse distributive law. */
5520 {
5524 }
5526 /* If CODE is an associative operation not otherwise handled, see if we
5527 can associate some operands. This can win if they are constants or
5528 if they are logically related (i.e. (a & b) & a). */
5534 {
5536 {
5540 rtx inner;
5542 /* Make sure we pass the constant operand if any as the second
5543 one if this is a commutative operation. */
5545 {
5549 }
5555 /* For commutative operations, try the other pair if that one
5556 didn't simplify. */
5558 {
5563 }
5567 }
5568 }
5570 /* A little bit of algebraic simplification here. */
5572 {
5574 /* Ensure that our address has any ASHIFTs converted to MULT in case
5575 address-recognizing predicates are called later. */
5584 /* See if this can be moved to simplify_subreg. */
5587 /* Don't call gen_lowpart if the inner mode
5588 is VOIDmode and we cannot simplify it, as SUBREG without
5589 inner mode is invalid. */
5596 {
5597 rtx temp;
5603 /* If op is known to have all lower bits zero, the result is zero. */
5613 }
5615 /* Don't change the mode of the MEM if that would change the meaning
5616 of the address. */
5623 /* Note that we cannot do any narrowing for non-constants since
5624 we might have been counting on using the fact that some bits were
5625 zero. We now do this in the SET. */
5632 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5633 replaced by (lshiftrt X C). This will convert
5634 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5642 /* If X has only a single bit that might be nonzero, say, bit I, convert
5643 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5644 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5645 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5646 or a SUBREG of one since we'd be making the expression more
5647 complex if it was just a register. */
5653 {
5654 rtx temp1 = simplify_shift_const
5660 /* If all we did was surround TEMP with the two shifts, we
5661 haven't improved anything, so don't use it. Otherwise,
5662 we are better off with TEMP1. */
5667 }
5671 /* We can't handle truncation to a partial integer mode here
5672 because we don't know the real bitsize of the partial
5673 integer mode. */
5682 /* We can truncate a constant value and return it. */
5686 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5687 whose value is a comparison can be replaced with a subreg if
5688 STORE_FLAG_VALUE permits. */
5697 /* (const (const X)) can become (const X). Do it this way rather than
5698 returning the inner CONST since CONST can be shared with a
5699 REG_EQUAL note. */
5704 #ifdef HAVE_lo_sum
5706 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5707 can add in an offset. find_split_point will split this address up
5708 again if it doesn't match. */
5713 #endif
5716 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5717 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5718 bit-field and can be replaced by either a sign_extend or a
5719 sign_extract. The `and' may be a zero_extend and the two
5720 <c>, -<c> constants may be reversed. */
5735 return simplify_shift_const
5742 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5743 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5744 the bitsize of the mode - 1. This allows simplification of
5745 "a = (b & 8) == 0;" */
5757 /* If we are adding two things that have no bits in common, convert
5758 the addition into an IOR. This will often be further simplified,
5759 for example in cases like ((a & 1) + (a & 2)), which can
5760 become a & 3. */
5765 {
5766 /* Try to simplify the expression further. */
5770 /* If we could, great. If not, do not go ahead with the IOR
5771 replacement, since PLUS appears in many special purpose
5772 address arithmetic instructions. */
5780 }
5784 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5785 (and <foo> (const_int pow2-1)) */
5795 /* If we have (mult (plus A B) C), apply the distributive law and then
5796 the inverse distributive law to see if things simplify. This
5797 occurs mostly in addresses, often when unrolling loops. */
5800 {
5804 }
5806 /* Try simplify a*(b/c) as (a*b)/c. */
5809 {
5815 }
5819 /* If this is a divide by a power of two, treat it as a shift if
5820 its first operand is a shift. */
5838 /* If the first operand is a condition code, we can't do anything
5839 with it. */
5843 {
5851 /* Simplify our comparison, if possible. */
5854 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5855 if only the low-order bit is possibly nonzero in X (such as when
5856 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5857 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5858 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5859 (plus X 1).
5861 Remove any ZERO_EXTRACT we made when thinking this was a
5862 comparison. It may now be simpler to use, e.g., an AND. If a
5863 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5864 the call to make_compound_operation in the SET case.
5866 Don't apply these optimizations if the caller would
5867 prefer a comparison rather than a value.
5868 E.g., for the condition in an IF_THEN_ELSE most targets need
5869 an explicit comparison. */
5872 ;
5888 {
5892 mode);
5893 }
5900 {
5904 const1_rtx);
5905 }
5913 {
5916 }
5918 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5919 those above. */
5921 ;
5937 {
5941 mode);
5942 }
5950 {
5954 mode);
5955 }
5957 /* If X is 0/1, (eq X 0) is X-1. */
5963 {
5966 }
5968 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5969 one bit that might be nonzero, we can convert (ne x 0) to
5970 (ashift x c) where C puts the bit in the sign bit. Remove any
5971 AND with STORE_FLAG_VALUE when we are done, since we are only
5972 going to test the sign bit. */
5979 {
5985 else
5987 }
5989 /* If the code changed, return a whole new comparison.
5990 We also need to avoid using SUBST in cases where
5991 simplify_comparison has widened a comparison with a CONST_INT,
5992 since in that case the wider CONST_INT may fail the sanity
5993 checks in do_SUBST. */
6000 /* Otherwise, keep this operation, but maybe change its operands.
6001 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6004 }
6014 /* If we are processing SET_DEST, we are done. */
6032 /* If this is a shift by a constant amount, simplify it. */
6048 }
6051 }
6052 \f
6053 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6055 static rtx
6057 {
6064 rtx temp;
6067 rtx reversed;
6069 /* Simplify storing of the truth value. */
6074 /* Also when the truth value has to be reversed. */
6080 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6081 in it is being compared against certain values. Get the true and false
6082 comparisons and see if that says anything about the value of each arm. */
6088 {
6089 HOST_WIDE_INT nzb;
6095 /* If FALSE_CODE is EQ, swap the codes and arms. */
6098 {
6101 }
6103 /* If we are comparing against zero and the expression being tested has
6104 only a single bit that might be nonzero, that is its value when it is
6105 not equal to zero. Similarly if it is known to be -1 or 0. */
6109 {
6112 }
6116 {
6119 }
6121 /* Now simplify an arm if we know the value of the register in the
6122 branch and it is used in the arm. Be careful due to the potential
6123 of locally-shared RTL. */
6140 }
6142 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6143 reversed, do so to avoid needing two sets of patterns for
6144 subtract-and-branch insns. Similarly if we have a constant in the true
6145 arm, the false arm is the same as the first operand of the comparison, or
6146 the false arm is more complicated than the true arm. */
6159 {
6168 /* It is possible that the conditional has been simplified out. */
6171 }
6173 /* If the two arms are identical, we don't need the comparison. */
6178 /* Convert a == b ? b : a to "a". */
6190 /* Look for cases where we have (abs x) or (neg (abs X)). */
6193 && comparison_p
6200 {
6206 return
6209 mode);
6212 }
6214 /* Look for MIN or MAX. */
6217 && comparison_p
6222 {
6237 }
6239 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6240 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6241 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6242 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6243 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6244 neither 1 or -1, but it isn't worth checking for. */
6247 && comparison_p
6250 {
6266 /* If an identity-zero op is commutative, check whether there
6267 would be a match if we swapped the operands. */
6287 {
6291 }
6303 {
6307 }
6323 {
6327 }
6339 {
6343 }
6346 {
6352 const_true_rtx));
6360 }
6361 }
6363 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6364 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6365 negation of a single bit, we can convert this operation to a shift. We
6366 can actually do this more generally, but it doesn't seem worth it. */
6375 return
6379 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6389 }
6390 \f
6391 /* Simplify X, a SET expression. Return the new expression. */
6393 static rtx
6395 {
6398 machine_mode mode
6403 /* (set (pc) (return)) gets written as (return). */
6407 /* Now that we know for sure which bits of SRC we are using, see if we can
6408 simplify the expression for the object knowing that we only need the
6409 low-order bits. */
6412 {
6415 }
6417 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6418 the comparison result and try to simplify it unless we already have used
6419 undobuf.other_insn. */
6427 {
6436 {
6439 {
6442 }
6443 }
6444 else
6452 {
6456 }
6457 else
6458 {
6463 /* Attempt to simplify CC user. */
6465 {
6469 }
6471 /* Convert X into a no-op move. */
6475 }
6477 /* Simplify our comparison, if possible. */
6480 #ifdef SELECT_CC_MODE
6481 /* If this machine has CC modes other than CCmode, check to see if we
6482 need to use a different CC mode here. */
6491 else
6494 #ifndef HAVE_cc0
6495 /* If the mode changed, we have to change SET_DEST, the mode in the
6496 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6497 a hard register, just build new versions with the proper mode. If it
6498 is a pseudo, we lose unless it is only time we set the pseudo, in
6499 which case we can safely change its mode. */
6501 {
6503 {
6505 rtx new_dest;
6509 else
6510 {
6513 }
6520 }
6521 }
6525 /* If the code changed, we have to build a new comparison in
6526 undobuf.other_insn. */
6528 {
6537 /* If the only change we made was to change an EQ into an NE or
6538 vice versa, OP0 has only one bit that might be nonzero, and OP1
6539 is zero, check if changing the user of the condition code will
6540 produce a valid insn. If it won't, we can keep the original code
6541 in that insn by surrounding our operation with an XOR. */
6548 {
6553 {
6560 }
6561 }
6562 }
6567 /* Otherwise, if we didn't previously have a COMPARE in the
6568 correct mode, we need one. */
6570 {
6573 }
6575 {
6578 }
6579 /* Otherwise, update the COMPARE if needed. */
6581 {
6584 }
6585 }
6586 else
6587 {
6588 /* Get SET_SRC in a form where we have placed back any
6589 compound expressions. Then do the checks below. */
6592 }
6594 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6595 and X being a REG or (subreg (reg)), we may be able to convert this to
6596 (set (subreg:m2 x) (op)).
6598 We can always do this if M1 is narrower than M2 because that means that
6599 we only care about the low bits of the result.
6601 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6602 perform a narrower operation than requested since the high-order bits will
6603 be undefined. On machine where it is defined, this transformation is safe
6604 as long as M1 and M2 have the same number of words. */
6612 #ifndef WORD_REGISTER_OPERATIONS
6615 #endif
6616 #ifdef CANNOT_CHANGE_MODE_CLASS
6621 #endif
6625 {
6628 dest));
6632 }
6634 #ifdef HAVE_cc0
6635 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6636 in SRC. */
6642 {
6646 /* Here we make sure that we don't have a sign bit on. */
6649 {
6652 }
6653 }
6654 #endif
6656 #ifdef LOAD_EXTEND_OP
6657 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6658 would require a paradoxical subreg. Replace the subreg with a
6659 zero_extend to avoid the reload that would otherwise be required. */
6667 {
6673 }
6674 #endif
6676 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6677 are comparing an item known to be 0 or -1 against 0, use a logical
6678 operation instead. Check for one of the arms being an IOR of the other
6679 arm with some value. We compute three terms to be IOR'ed together. In
6680 practice, at most two will be nonzero. Then we do the IOR's. */
6688 #ifdef HAVE_conditional_move
6690 #endif
6695 {
6721 false_rtx);
6727 term3));
6730 }
6732 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6733 whole thing fail. */
6738 else
6739 /* Convert this into a field assignment operation, if possible. */
6741 }
6742 \f
6743 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6744 result. */
6746 static rtx
6748 {
6754 {
6756 /* We can call simplify_and_const_int only if we don't lose
6757 any (sign) bits when converting INTVAL (op1) to
6758 "unsigned HOST_WIDE_INT". */
6762 {
6769 }
6771 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6772 apply the distributive law and then the inverse distributive
6773 law to see if things simplify. */
6775 {
6779 }
6781 {
6785 }
6789 /* If we have (ior (and A B) C), apply the distributive law and then
6790 the inverse distributive law to see if things simplify. */
6793 {
6797 }
6800 {
6804 }
6809 }
6812 }
6813 \f
6814 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6815 operations" because they can be replaced with two more basic operations.
6816 ZERO_EXTEND is also considered "compound" because it can be replaced with
6817 an AND operation, which is simpler, though only one operation.
6819 The function expand_compound_operation is called with an rtx expression
6820 and will convert it to the appropriate shifts and AND operations,
6821 simplifying at each stage.
6823 The function make_compound_operation is called to convert an expression
6824 consisting of shifts and ANDs into the equivalent compound expression.
6825 It is the inverse of this function, loosely speaking. */
6827 static rtx
6829 {
6833 rtx tem;
6836 {
6840 /* We can't necessarily use a const_int for a multiword mode;
6841 it depends on implicitly extending the value.
6842 Since we don't know the right way to extend it,
6843 we can't tell whether the implicit way is right.
6845 Even for a mode that is no wider than a const_int,
6846 we can't win, because we need to sign extend one of its bits through
6847 the rest of it, and we don't know which bit. */
6851 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6852 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6853 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6854 reloaded. If not for that, MEM's would very rarely be safe.
6856 Reject MODEs bigger than a word, because we might not be able
6857 to reference a two-register group starting with an arbitrary register
6858 (and currently gen_lowpart might crash for a SUBREG). */
6863 /* Reject MODEs that aren't scalar integers because turning vector
6864 or complex modes into shifts causes problems. */
6870 /* If the inner object has VOIDmode (the only way this can happen
6871 is if it is an ASM_OPERANDS), we can't do anything since we don't
6872 know how much masking to do. */
6881 /* ... fall through ... */
6884 /* If the operand is a CLOBBER, just return it. */
6893 /* Reject MODEs that aren't scalar integers because turning vector
6894 or complex modes into shifts causes problems. */
6902 /* This should stay within the object being extracted, fail otherwise. */
6913 }
6914 /* Convert sign extension to zero extension, if we know that the high
6915 bit is not set, as this is easier to optimize. It will be converted
6916 back to cheaper alternative in make_extraction. */
6924 {
6928 /* Make sure this is a profitable operation. */
6935 else
6937 }
6939 /* We can optimize some special cases of ZERO_EXTEND. */
6941 {
6942 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6943 know that the last value didn't have any inappropriate bits
6944 set. */
6952 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6961 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6962 is a comparison and STORE_FLAG_VALUE permits. This is like
6963 the first case, but it works even when GET_MODE (x) is larger
6964 than HOST_WIDE_INT. */
6973 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6983 }
6985 /* If we reach here, we want to return a pair of shifts. The inner
6986 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6987 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6988 logical depending on the value of UNSIGNEDP.
6990 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6991 converted into an AND of a shift.
6993 We must check for the case where the left shift would have a negative
6994 count. This can happen in a case like (x >> 31) & 255 on machines
6995 that can't shift by a constant. On those machines, we would first
6996 combine the shift with the AND to produce a variable-position
6997 extraction. Then the constant of 31 would be substituted in
6998 to produce such a position. */
7002 {
7011 }
7018 else
7019 /* Any other cases we can't handle. */
7022 /* If we couldn't do this for some reason, return the original
7023 expression. */
7028 }
7029 \f
7030 /* X is a SET which contains an assignment of one object into
7031 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7032 or certain SUBREGS). If possible, convert it into a series of
7033 logical operations.
7035 We half-heartedly support variable positions, but do not at all
7036 support variable lengths. */
7038 static const_rtx
7040 {
7041 rtx inner;
7045 machine_mode compute_mode;
7047 /* Loop until we find something we can't simplify. */
7049 {
7052 {
7056 }
7059 {
7064 /* A constant position should stay within the width of INNER. */
7070 {
7078 /* If position is ADJUST - X, new position is X. */
7080 else
7081 {
7086 pos);
7087 }
7088 }
7089 }
7091 /* A SUBREG between two modes that occupy the same numbers of words
7092 can be done by moving the SUBREG to the source. */
7094 /* We need SUBREGs to compute nonzero_bits properly. */
7095 && nonzero_sign_valid
7100 {
7102 gen_lowpart
7106 }
7107 else
7115 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7117 {
7118 machine_mode imode;
7120 /* Don't do anything for vector or complex integral types. */
7124 /* Try to find an integral mode to pun with. */
7131 }
7133 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7137 /* Now compute the equivalent expression. Make a copy of INNER
7138 for the SET_DEST in case it is a MEM into which we will substitute;
7139 we don't want shared RTL in that case. */
7141 compute_mode);
7145 compute_mode,
7147 compute_mode),
7148 inner);
7153 mask),
7154 pos);
7159 }
7162 }
7163 \f
7164 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7165 it is an RTX that represents the (variable) starting position; otherwise,
7166 POS is the (constant) starting bit position. Both are counted from the LSB.
7168 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7170 IN_DEST is nonzero if this is a reference in the destination of a SET.
7171 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7172 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7173 be used.
7175 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7176 ZERO_EXTRACT should be built even for bits starting at bit 0.
7178 MODE is the desired mode of the result (if IN_DEST == 0).
7180 The result is an RTX for the extraction or NULL_RTX if the target
7181 can't handle it. */
7183 static rtx
7187 {
7188 /* This mode describes the size of the storage area
7189 to fetch the overall value from. Within that, we
7190 ignore the POS lowest bits, etc. */
7192 machine_mode inner_mode;
7193 machine_mode wanted_inner_mode;
7200 HOST_WIDE_INT orig_pos;
7206 {
7207 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7208 consider just the QI as the memory to extract from.
7209 The subreg adds or removes high bits; its mode is
7210 irrelevant to the meaning of this extraction,
7211 since POS and LEN count from the lsb. */
7215 }
7220 {
7221 /* We're extracting the least significant bits of an rtx
7222 (ashift X (const_int C)), where LEN > C. Extract the
7223 least significant (LEN - C) bits of X, giving an rtx
7224 whose mode is MODE, then shift it left C times. */
7230 }
7236 /* See if this can be done without an extraction. We never can if the
7237 width of the field is not the same as that of some integer mode. For
7238 registers, we can only avoid the extraction if the position is at the
7239 low-order bit and this is either not in the destination or we have the
7240 appropriate STRICT_LOW_PART operation available.
7242 For MEM, we can avoid an extract if the field starts on an appropriate
7243 boundary and we can change the mode of the memory reference. */
7252 && (! in_dest
7256 && (pos
7259 /* We can't do this if we are widening INNER_MODE (it
7260 may not be aligned, for one thing). */
7266 {
7267 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7268 field. If the original and current mode are the same, we need not
7269 adjust the offset. Otherwise, we do if bytes big endian.
7271 If INNER is not a MEM, get a piece consisting of just the field
7272 of interest (in this case POS % BITS_PER_WORD must be 0). */
7275 {
7276 HOST_WIDE_INT offset;
7278 /* POS counts from lsb, but make OFFSET count in memory order. */
7281 else
7285 }
7287 {
7289 {
7290 /* We can't call gen_lowpart in a DEST since we
7291 always want a SUBREG (see below) and it would sometimes
7292 return a new hard register. */
7294 {
7309 /* Avoid creating invalid subregs, for example when
7310 simplifying (x>>32)&255. */
7315 }
7316 else
7318 }
7319 else
7321 }
7322 else
7324 len >= HOST_BITS_PER_WIDE_INT
7329 /* If this extraction is going into the destination of a SET,
7330 make a STRICT_LOW_PART unless we made a MEM. */
7345 /* If we know that no extraneous bits are set, and that the high
7346 bit is not set, convert the extraction to the cheaper of
7347 sign and zero extension, that are equivalent in these cases. */
7353 {
7357 /* Prefer ZERO_EXTENSION, since it gives more information to
7358 backends. */
7363 }
7365 /* Otherwise, sign- or zero-extend unless we already are in the
7366 proper mode. */
7370 }
7372 /* Unless this is a COMPARE or we have a funny memory reference,
7373 don't do anything with zero-extending field extracts starting at
7374 the low-order bit since they are simple AND operations. */
7379 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7380 if the position is not a constant and the length is not 1. In all
7381 other cases, we would only be going outside our object in cases when
7382 an original shift would have been undefined. */
7391 /* If INNER is not from memory, we want it to have the mode of a register
7392 extraction pattern's structure operand, or word_mode if there is no
7393 such pattern. The same applies to extraction_mode and pos_mode
7394 and their respective operands.
7396 For memory, assume that the desired extraction_mode and pos_mode
7397 are the same as for a register operation, since at present we don't
7398 have named patterns for aligned memory structures. */
7402 {
7406 }
7408 /* Never narrow an object, since that might not be safe. */
7416 else
7417 {
7418 /* Be careful not to go beyond the extracted object and maintain the
7419 natural alignment of the memory. */
7423 {
7426 }
7427 }
7432 {
7433 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7434 BITS_BIG_ENDIAN style. If position is constant, compute new
7435 position. Otherwise, build subtraction.
7436 Note that POS is relative to the mode of the original argument.
7437 If it's a MEM we need to recompute POS relative to that.
7438 However, if we're extracting from (or inserting into) a register,
7439 we want to recompute POS relative to wanted_inner_mode. */
7446 else
7447 pos_rtx
7450 pos_rtx);
7451 /* POS may be less than 0 now, but we check for that below.
7452 Note that it can only be less than 0 if !MEM_P (inner). */
7453 }
7455 /* If INNER has a wider mode, and this is a constant extraction, try to
7456 make it smaller and adjust the byte to point to the byte containing
7457 the value. */
7460 && ! pos_rtx
7465 {
7468 /* The computations below will be correct if the machine is big
7469 endian in both bits and bytes or little endian in bits and bytes.
7470 If it is mixed, we must adjust. */
7472 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7473 adjust OFFSET to compensate. */
7478 /* We can now move to the desired byte. */
7489 }
7491 /* If INNER is not memory, get it into the proper mode. If we are changing
7492 its mode, POS must be a constant and smaller than the size of the new
7493 mode. */
7495 {
7496 /* On the LHS, don't create paradoxical subregs implicitely truncating
7497 the register unless TRULY_NOOP_TRUNCATION. */
7500 wanted_inner_mode))
7512 pos_rtx
7518 }
7520 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7521 have to zero extend. Otherwise, we can just use a SUBREG. */
7524 {
7528 /* If we know that no extraneous bits are set, and that the high
7529 bit is not set, convert extraction to cheaper one - either
7530 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7531 cases. */
7539 {
7543 /* Prefer ZERO_EXTENSION, since it gives more information to
7544 backends. */
7548 }
7550 }
7552 /* Make POS_RTX unless we already have it and it is correct. If we don't
7553 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7554 be a CONST_INT. */
7561 /* Make the required operation. See if we can use existing rtx. */
7568 }
7569 \f
7570 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7571 with any other operations in X. Return X without that shift if so. */
7573 static rtx
7575 {
7578 rtx tem;
7581 {
7583 /* This is the shift itself. If it is wide enough, we will return
7584 either the value being shifted if the shift count is equal to
7585 COUNT or a shift for the difference. */
7599 /* If we can safely shift this constant and we find the inner shift,
7600 make a new operation. */
7605 {
7609 }
7614 }
7617 }
7618 \f
7619 /* Look at the expression rooted at X. Look for expressions
7620 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7621 Form these expressions.
7623 Return the new rtx, usually just X.
7625 Also, for machines like the VAX that don't have logical shift insns,
7626 try to convert logical to arithmetic shift operations in cases where
7627 they are equivalent. This undoes the canonicalizations to logical
7628 shifts done elsewhere.
7630 We try, as much as possible, to re-use rtl expressions to save memory.
7632 IN_CODE says what kind of expression we are processing. Normally, it is
7633 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7634 being kludges), it is MEM. When processing the arguments of a comparison
7635 or a COMPARE against zero, it is COMPARE. */
7637 rtx
7639 {
7647 rtx tem;
7650 /* Select the code to be used in recursive calls. Once we are inside an
7651 address, we stay there. If we have a comparison, set to COMPARE,
7652 but once inside, go back to our default of SET. */
7661 /* Process depending on the code of this operation. If NEW is set
7662 nonzero, it will be returned. */
7665 {
7667 /* Convert shifts by constants into multiplications if inside
7668 an address. */
7673 {
7679 {
7682 }
7685 }
7695 {
7699 }
7702 {
7706 mode));
7708 }
7709 else
7710 {
7714 }
7725 {
7729 }
7732 {
7736 mode));
7738 }
7739 else
7740 {
7744 }
7748 /* If the second operand is not a constant, we can't do anything
7749 with it. */
7753 /* If the constant is a power of two minus one and the first operand
7754 is a logical right shift, make an extraction. */
7757 {
7761 }
7763 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7768 {
7770 next_code);
7774 }
7775 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7781 {
7782 /* Apply the distributive law, and then try to make extractions. */
7789 }
7791 /* If we are have (and (rotate X C) M) and C is larger than the number
7792 of bits in M, this is an extraction. */
7798 {
7804 }
7806 /* On machines without logical shifts, if the operand of the AND is
7807 a logical shift and our mask turns off all the propagated sign
7808 bits, we can replace the logical shift with an arithmetic shift. */
7816 {
7823 make_compound_operation
7826 }
7828 /* If the constant is one less than a power of two, this might be
7829 representable by an extraction even if no shift is present.
7830 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7831 we are in a COMPARE. */
7835 next_code),
7838 /* If we are in a comparison and this is an AND with a power of two,
7839 convert this into the appropriate bit extract. */
7844 next_code),
7850 /* If the sign bit is known to be zero, replace this with an
7851 arithmetic shift. */
7856 {
7859 next_code),
7862 }
7864 /* ... fall through ... */
7870 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7871 this is a SIGN_EXTRACT. */
7878 {
7885 }
7887 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7888 If so, try to merge the shifts into a SIGN_EXTEND. We could
7889 also do this for some cases of SIGN_EXTRACT, but it doesn't
7890 seem worth the effort; the case checked for occurs on Alpha. */
7906 /* Call ourselves recursively on the inner expression. If we are
7907 narrowing the object and it has a different RTL code from
7908 what it originally did, do this SUBREG as a force_to_mode. */
7909 {
7913 /* If in_code is COMPARE, it isn't always safe to pass it through
7914 to the recursive make_compound_operation call. */
7918 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7919 is (const_int 0), rather than
7920 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7930 simplified
7938 {
7939 rtx newer
7942 /* If we have something other than a SUBREG, we might have
7943 done an expansion, so rerun ourselves. */
7947 /* force_to_mode can expand compounds. If it just re-expanded the
7948 compound, use gen_lowpart to convert to the desired mode. */
7950 /* Likewise if it re-expanded the compound only partially.
7951 This happens for SUBREG of ZERO_EXTRACT if they extract
7952 the same number of bits. */
7961 }
7965 }
7970 }
7973 {
7976 }
7978 /* Now recursively process each operand of this operation. We need to
7979 handle ZERO_EXTEND specially so that we don't lose track of the
7980 inner mode. */
7982 {
7990 }
7995 {
7998 }
8001 {
8004 }
8006 maybe_swap:
8007 /* If this is a commutative operation, the changes to the operands
8008 may have made it noncanonical. */
8011 {
8015 }
8018 }
8019 \f
8020 /* Given M see if it is a value that would select a field of bits
8021 within an item, but not the entire word. Return -1 if not.
8022 Otherwise, return the starting position of the field, where 0 is the
8023 low-order bit.
8025 *PLEN is set to the length of the field. */
8027 static int
8029 {
8030 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8035 /* Now shift off the low-order zero bits and see if we have a
8036 power of two minus 1. */
8044 }
8045 \f
8046 /* If X refers to a register that equals REG in value, replace these
8047 references with REG. */
8048 static rtx
8050 {
8058 {
8094 {
8098 else
8100 }
8102 /* fall through */
8109 {
8112 {
8114 {
8117 }
8119 }
8120 }
8122 {
8125 {
8128 {
8130 {
8133 }
8135 }
8136 }
8137 }
8140 }
8143 }
8145 /* Return X converted to MODE. If the value is already truncated to
8146 MODE we can just return a subreg even though in the general case we
8147 would need an explicit truncation. */
8149 static rtx
8151 {
8156 {
8157 /* Bit-cast X into an integer mode. */
8162 }
8165 }
8167 /* See if X can be simplified knowing that we will only refer to it in
8168 MODE and will only refer to those bits that are nonzero in MASK.
8169 If other bits are being computed or if masking operations are done
8170 that select a superset of the bits in MASK, they can sometimes be
8171 ignored.
8173 Return a possibly simplified expression, but always convert X to
8174 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8176 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8177 are all off in X. This is used when X will be complemented, by either
8178 NOT, NEG, or XOR. */
8180 static rtx
8183 {
8186 machine_mode op_mode;
8190 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8191 code below will do the wrong thing since the mode of such an
8192 expression is VOIDmode.
8194 Also do nothing if X is a CLOBBER; this can happen if X was
8195 the return value from a call to gen_lowpart. */
8199 /* We want to perform the operation in its present mode unless we know
8200 that the operation is valid in MODE, in which case we do the operation
8201 in MODE. */
8206 /* It is not valid to do a right-shift in a narrower mode
8207 than the one it came in with. */
8212 /* Truncate MASK to fit OP_MODE. */
8216 /* When we have an arithmetic operation, or a shift whose count we
8217 do not know, we need to assume that all bits up to the highest-order
8218 bit in MASK will be needed. This is how we form such a mask. */
8221 else
8225 /* Determine what bits of X are guaranteed to be (non)zero. */
8228 /* If none of the bits in X are needed, return a zero. */
8232 /* If X is a CONST_INT, return a new one. Do this here since the
8233 test below will fail. */
8235 {
8238 else
8239 {
8242 }
8243 }
8245 /* If X is narrower than MODE and we want all the bits in X's mode, just
8246 get X in the proper mode. */
8251 /* We can ignore the effect of a SUBREG if it narrows the mode or
8252 if the constant masks to zero all the bits the mode doesn't have. */
8262 /* The arithmetic simplifications here only work for scalar integer modes. */
8267 {
8269 /* If X is a (clobber (const_int)), return it since we know we are
8270 generating something that won't match. */
8283 /* Similarly for a truncate. */
8287 /* If this is an AND with a constant, convert it into an AND
8288 whose constant is the AND of that constant with MASK. If it
8289 remains an AND of MASK, delete it since it is redundant. */
8292 {
8296 /* If X is still an AND, see if it is an AND with a mask that
8297 is just some low-order bits. If so, and it is MASK, we don't
8298 need it. */
8305 /* If it remains an AND, try making another AND with the bits
8306 in the mode mask that aren't in MASK turned on. If the
8307 constant in the AND is wide enough, this might make a
8308 cheaper constant. */
8313 {
8314 unsigned HOST_WIDE_INT cval
8317 rtx y;
8324 }
8327 }
8332 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8333 low-order bits (as in an alignment operation) and FOO is already
8334 aligned to that boundary, mask C1 to that boundary as well.
8335 This may eliminate that PLUS and, later, the AND. */
8337 {
8341 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8342 number, sign extend it. */
8355 }
8357 /* ... fall through ... */
8360 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8361 most significant bit in MASK since carries from those bits will
8362 affect the bits we are interested in. */
8367 /* If X is (minus C Y) where C's least set bit is larger than any bit
8368 in the mask, then we may replace with (neg Y). */
8371 {
8375 }
8377 /* Similarly, if C contains every bit in the fuller_mask, then we may
8378 replace with (not Y). */
8381 {
8385 }
8392 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8393 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8394 operation which may be a bitfield extraction. Ensure that the
8395 constant we form is not wider than the mode of X. */
8407 {
8416 }
8418 binop:
8419 /* For most binary operations, just propagate into the operation and
8420 change the mode if we have an operation of that mode. */
8425 /* If we ended up truncating both operands, truncate the result of the
8426 operation instead. */
8429 {
8432 }
8442 /* For left shifts, do the same, but just for the first operand.
8443 However, we cannot do anything with shifts where we cannot
8444 guarantee that the counts are smaller than the size of the mode
8445 because such a count will have a different meaning in a
8446 wider mode. */
8456 /* If the shift count is a constant and we can do arithmetic in
8457 the mode of the shift, refine which bits we need. Otherwise, use the
8458 conservative form of the mask. */
8464 else
8476 /* Here we can only do something if the shift count is a constant,
8477 this shift constant is valid for the host, and we can do arithmetic
8478 in OP_MODE. */
8484 {
8488 /* Select the mask of the bits we need for the shift operand. */
8491 /* We can only change the mode of the shift if we can do arithmetic
8492 in the mode of the shift and INNER_MASK is no wider than the
8493 width of X's mode. */
8501 }
8503 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8504 shift and AND produces only copies of the sign bit (C2 is one less
8505 than a power of two), we can do this with just a shift. */
8509 /* The shift puts one of the sign bit copies in the least significant
8510 bit. */
8515 /* Number of bits left after the shift must be more than the mask
8516 needs. */
8519 /* Must be more sign bit copies than the mask needs. */
8529 /* If we are just looking for the sign bit, we don't need this shift at
8530 all, even if it has a variable count. */
8534 /* If this is a shift by a constant, get a mask that contains those bits
8535 that are not copies of the sign bit. We then have two cases: If
8536 MASK only includes those bits, this can be a logical shift, which may
8537 allow simplifications. If MASK is a single-bit field not within
8538 those bits, we are requesting a copy of the sign bit and hence can
8539 shift the sign bit to the appropriate location. */
8543 {
8546 /* If the considered data is wider than HOST_WIDE_INT, we can't
8547 represent a mask for all its bits in a single scalar.
8548 But we only care about the lower bits, so calculate these. */
8551 {
8554 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8555 is the number of bits a full-width mask would have set.
8556 We need only shift if these are fewer than nonzero can
8557 hold. If not, we must keep all bits set in nonzero. */
8562 + HOST_BITS_PER_WIDE_INT
8564 }
8565 else
8566 {
8569 }
8572 {
8577 }
8580 {
8581 x = simplify_shift_const
8587 }
8588 }
8590 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8591 even if the shift count isn't a constant. */
8596 shiftrt:
8598 /* If this is a zero- or sign-extension operation that just affects bits
8599 we don't care about, remove it. Be sure the call above returned
8600 something that is still a shift. */
8610 next_select);
8616 /* If the shift count is constant and we can do computations
8617 in the mode of X, compute where the bits we care about are.
8618 Otherwise, we can't do anything. Don't change the mode of
8619 the shift or propagate MODE into the shift, though. */
8622 {
8632 }
8636 /* If we just want the low-order bit, the NEG isn't needed since it
8637 won't change the low-order bit. */
8641 /* We need any bits less significant than the most significant bit in
8642 MASK since carries from those bits will affect the bits we are
8643 interested in. */
8648 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8649 same as the XOR case above. Ensure that the constant we form is not
8650 wider than the mode of X. */
8658 {
8667 }
8669 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8670 use the full mask inside the NOT. */
8673 unop:
8676 next_select));
8682 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8683 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8684 which is equal to STORE_FLAG_VALUE. */
8696 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8697 written in a narrower mode. We play it safe and do not do so. */
8713 }
8715 /* Ensure we return a value of the proper mode. */
8717 }
8718 \f
8719 /* Return nonzero if X is an expression that has one of two values depending on
8720 whether some other value is zero or nonzero. In that case, we return the
8721 value that is being tested, *PTRUE is set to the value if the rtx being
8722 returned has a nonzero value, and *PFALSE is set to the other alternative.
8724 If we return zero, we set *PTRUE and *PFALSE to X. */
8726 static rtx
8728 {
8734 /* If we are comparing a value against zero, we are done. */
8737 {
8741 }
8743 /* If this is a unary operation whose operand has one of two values, apply
8744 our opcode to compute those values. */
8747 {
8752 }
8754 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8755 make can't possibly match and would suppress other optimizations. */
8757 ;
8759 /* If this is a binary operation, see if either side has only one of two
8760 values. If either one does or if both do and they are conditional on
8761 the same value, compute the new true and false values. */
8763 {
8769 {
8770 /* If if_then_else_cond returned zero, then true/false are the
8771 same rtl. We must copy one of them to prevent invalid rtl
8772 sharing. */
8779 {
8784 }
8785 else
8786 {
8789 }
8792 }
8794 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8795 operands is zero when the other is nonzero, and vice-versa,
8796 and STORE_FLAG_VALUE is 1 or -1. */
8802 {
8819 {
8826 const_true_rtx);
8828 }
8829 }
8831 /* Similarly for MULT, AND and UMIN, except that for these the result
8832 is always zero. */
8836 {
8850 {
8853 }
8854 }
8855 }
8858 {
8859 /* If we have IF_THEN_ELSE already, extract the condition and
8860 canonicalize it if it is NE or EQ. */
8866 {
8869 }
8870 else
8872 }
8874 /* If X is a SUBREG, we can narrow both the true and false values
8875 if the inner expression, if there is a condition. */
8879 {
8885 {
8889 }
8890 }
8892 /* If X is a constant, this isn't special and will cause confusions
8893 if we treat it as such. Likewise if it is equivalent to a constant. */
8896 ;
8898 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8899 will be least confusing to the rest of the compiler. */
8901 {
8904 }
8906 /* If X is known to be either 0 or -1, those are the true and
8907 false values when testing X. */
8911 {
8914 }
8916 /* Likewise for 0 or a single bit. */
8919 {
8922 }
8924 /* Otherwise fail; show no condition with true and false values the same. */
8927 }
8928 \f
8929 /* Return the value of expression X given the fact that condition COND
8930 is known to be true when applied to REG as its first operand and VAL
8931 as its second. X is known to not be shared and so can be modified in
8932 place.
8934 We only handle the simplest cases, and specifically those cases that
8935 arise with IF_THEN_ELSE expressions. */
8937 static rtx
8939 {
8941 rtx temp;
8948 /* If either operand of the condition is a floating point value,
8949 then we have to avoid collapsing an EQ comparison. */
8959 /* If X is (abs REG) and we know something about REG's relationship
8960 with zero, we may be able to simplify this. */
8964 {
8973 }
8975 /* The only other cases we handle are MIN, MAX, and comparisons if the
8976 operands are the same as REG and VAL. */
8979 {
8984 {
8986 {
8994 else
8996 }
8999 {
9002 /* Do not reverse the condition when it is NE or EQ.
9003 This is because we cannot conclude anything about
9004 the value of 'SMAX (x, y)' when x is not equal to y,
9005 but we can when x equals y. */
9011 {
9022 }
9023 }
9024 }
9025 }
9027 {
9032 {
9033 /* We must simplify subreg here, before we lose track of the
9034 original inner_mode. */
9039 else
9041 }
9044 }
9045 /* We don't have to handle SIGN_EXTEND here, because even in the
9046 case of replacing something with a modeless CONST_INT, a
9047 CONST_INT is already (supposed to be) a valid sign extension for
9048 its narrower mode, which implies it's already properly
9049 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9050 story is different. */
9052 {
9057 {
9058 /* We must simplify the zero_extend here, before we lose
9059 track of the original inner_mode. */
9064 else
9066 }
9069 }
9073 {
9080 }
9083 }
9084 \f
9085 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9086 assignment as a field assignment. */
9088 static int
9090 {
9097 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9098 Note that all SUBREGs of MEM are paradoxical; otherwise they
9099 would have been rewritten. */
9112 /* We used to see if get_last_value of X and Y were the same but that's
9113 not correct. In one direction, we'll cause the assignment to have
9114 the wrong destination and in the case, we'll import a register into this
9115 insn that might have already have been dead. So fail if none of the
9116 above cases are true. */
9118 }
9119 \f
9120 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9121 Return that assignment if so.
9123 We only handle the most common cases. */
9125 static rtx
9127 {
9130 rtx assign;
9132 HOST_WIDE_INT c1;
9133 HOST_WIDE_INT pos;
9135 rtx other;
9136 machine_mode mode;
9138 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9139 a clear of a one-bit field. We will have changed it to
9140 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9141 for a SUBREG. */
9147 {
9153 }
9163 {
9170 }
9172 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9173 one-bit field. */
9177 {
9183 }
9185 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9186 SRC is an AND with all bits of that field set, then we can discard
9187 the AND. */
9192 {
9199 else
9202 /* Complete overlap. We can remove the source AND. */
9206 /* Partial overlap. We can reduce the source AND. */
9208 {
9213 }
9214 }
9216 /* The other case we handle is assignments into a constant-position
9217 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9218 a mask that has all one bits except for a group of zero bits and
9219 OTHER is known to have zeros where C1 has ones, this is such an
9220 assignment. Compute the position and length from C1. Shift OTHER
9221 to the appropriate position, force it to the required mode, and
9222 make the extraction. Check for the AND in both operands. */
9238 else
9251 /* The mode to use for the source is the mode of the assignment, or of
9252 what is inside a possible STRICT_LOW_PART. */
9256 /* Shift OTHER right POS places and make it the source, restricting it
9257 to the proper length and mode. */
9262 dest);
9269 /* If SRC is masked by an AND that does not make a difference in
9270 the value being stored, strip it. */
9281 }
9282 \f
9283 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9284 if so. */
9286 static rtx
9288 {
9292 rtx tem;
9294 /* Distributivity is not true for floating point as it can change the
9295 value. So we don't do it unless -funsafe-math-optimizations. */
9300 /* The outer operation can only be one of the following: */
9308 /* If either operand is a primitive we can't do anything, so get out
9309 fast. */
9319 /* See if the inner and outer operations distribute. */
9321 {
9326 /* These all distribute except over PLUS. */
9337 /* This is also a multiply, so it distributes over everything. */
9340 /* This used to handle SUBREG, but this turned out to be counter-
9341 productive, since (subreg (op ...)) usually is not handled by
9342 insn patterns, and this "optimization" therefore transformed
9343 recognizable patterns into unrecognizable ones. Therefore the
9344 SUBREG case was removed from here.
9346 It is possible that distributing SUBREG over arithmetic operations
9347 leads to an intermediate result than can then be optimized further,
9348 e.g. by moving the outer SUBREG to the other side of a SET as done
9349 in simplify_set. This seems to have been the original intent of
9350 handling SUBREGs here.
9352 However, with current GCC this does not appear to actually happen,
9353 at least on major platforms. If some case is found where removing
9354 the SUBREG case here prevents follow-on optimizations, distributing
9355 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9359 }
9361 /* Set LHS and RHS to the inner operands (A and B in the example
9362 above) and set OTHER to the common operand (C in the example).
9363 There is only one way to do this unless the inner operation is
9364 commutative. */
9376 else
9379 /* Form the new inner operation, seeing if it simplifies first. */
9382 /* There is one exception to the general way of distributing:
9383 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9385 {
9388 }
9390 /* We may be able to continuing distributing the result, so call
9391 ourselves recursively on the inner operation before forming the
9392 outer operation, which we return. */
9395 }
9397 /* See if X is of the form (* (+ A B) C), and if so convert to
9398 (+ (* A C) (* B C)) and try to simplify.
9400 Most of the time, this results in no change. However, if some of
9401 the operands are the same or inverses of each other, simplifications
9402 will result.
9404 For example, (and (ior A B) (not B)) can occur as the result of
9405 expanding a bit field assignment. When we apply the distributive
9406 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9407 which then simplifies to (and (A (not B))).
9409 Note that no checks happen on the validity of applying the inverse
9410 distributive law. This is pointless since we can do it in the
9411 few places where this routine is called.
9413 N is the index of the term that is decomposed (the arithmetic operation,
9414 i.e. (+ A B) in the first example above). !N is the index of the term that
9415 is distributed, i.e. of C in the first example above. */
9416 static rtx
9418 {
9419 machine_mode mode;
9423 /* Distributivity is not true for floating point as it can change the
9424 value. So we don't do it unless -funsafe-math-optimizations. */
9441 /* Special case (and (xor B C) (not A)), which is equivalent to
9442 (xor (ior A B) (ior A C)) */
9444 {
9447 }
9450 {
9451 /* Distribute the second term. */
9454 }
9455 else
9456 {
9457 /* Distribute the first term. */
9460 }
9470 }
9471 \f
9472 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9473 in MODE. Return an equivalent form, if different from (and VAROP
9474 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9476 static rtx
9479 {
9482 rtx orig_varop;
9490 /* Simplify VAROP knowing that we will be only looking at some of the
9491 bits in it.
9493 Note by passing in CONSTOP, we guarantee that the bits not set in
9494 CONSTOP are not significant and will never be examined. We must
9495 ensure that is the case by explicitly masking out those bits
9496 before returning. */
9499 /* If VAROP is a CLOBBER, we will fail so return it. */
9503 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9504 to VAROP and return the new constant. */
9508 /* See what bits may be nonzero in VAROP. Unlike the general case of
9509 a call to nonzero_bits, here we don't care about bits outside
9510 MODE. */
9514 /* Turn off all bits in the constant that are known to already be zero.
9515 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9516 which is tested below. */
9520 /* If we don't have any bits left, return zero. */
9524 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9525 a power of two, we can replace this with an ASHIFT. */
9530 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9531 or XOR, then try to apply the distributive law. This may eliminate
9532 operations if either branch can be simplified because of the AND.
9533 It may also make some cases more complex, but those cases probably
9534 won't match a pattern either with or without this. */
9537 return
9538 gen_lowpart
9540 apply_distributive_law
9545 constop),
9549 constop))));
9551 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9552 the AND and see if one of the operands simplifies to zero. If so, we
9553 may eliminate it. */
9557 {
9566 }
9568 /* Make a SUBREG if necessary. If we can't make it, fail. */
9573 /* If we are only masking insignificant bits, return VAROP. */
9580 /* Otherwise, return an AND. */
9582 }
9585 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9586 in MODE.
9588 Return an equivalent form, if different from X. Otherwise, return X. If
9589 X is zero, we are to always construct the equivalent form. */
9591 static rtx
9594 {
9605 }
9606 \f
9607 /* Given a REG, X, compute which bits in X can be nonzero.
9608 We don't care about bits outside of those defined in MODE.
9610 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9611 a shift, AND, or zero_extract, we can do better. */
9613 static rtx
9615 const_rtx known_x ATTRIBUTE_UNUSED,
9616 machine_mode known_mode ATTRIBUTE_UNUSED,
9619 {
9620 rtx tem;
9623 /* If X is a register whose nonzero bits value is current, use it.
9624 Otherwise, if X is a register whose value we can find, use that
9625 value. Otherwise, use the previously-computed global nonzero bits
9626 for this register. */
9639 && !REGNO_REG_SET_P
9642 {
9646 /* We don't know anything about the upper bits. */
9651 }
9656 {
9657 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9658 /* If X is narrower than MODE and TEM is a non-negative
9659 constant that would appear negative in the mode of X,
9660 sign-extend it for use in reg_nonzero_bits because some
9661 machines (maybe most) will actually do the sign-extension
9662 and this is the conservative approach.
9664 ??? For 2.5, try to tighten up the MD files in this regard
9665 instead of this kludge. */
9672 #endif
9674 }
9676 {
9680 /* We don't know anything about the upper bits. */
9684 }
9687 }
9689 /* Return the number of bits at the high-order end of X that are known to
9690 be equal to the sign bit. X will be used in mode MODE; if MODE is
9691 VOIDmode, X will be used in its own mode. The returned value will always
9692 be between 1 and the number of bits in MODE. */
9694 static rtx
9696 const_rtx known_x ATTRIBUTE_UNUSED,
9697 machine_mode known_mode
9698 ATTRIBUTE_UNUSED,
9701 {
9702 rtx tem;
9714 && !REGNO_REG_SET_P
9717 {
9720 }
9731 }
9732 \f
9733 /* Return the number of "extended" bits there are in X, when interpreted
9734 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9735 unsigned quantities, this is the number of high-order zero bits.
9736 For signed quantities, this is the number of copies of the sign bit
9737 minus 1. In both case, this function returns the number of "spare"
9738 bits. For example, if two quantities for which this function returns
9739 at least 1 are added, the addition is known not to overflow.
9741 This function will always return 0 unless called during combine, which
9742 implies that it must be called from a define_split. */
9744 unsigned int
9746 {
9756 }
9758 /* This function is called from `simplify_shift_const' to merge two
9759 outer operations. Specifically, we have already found that we need
9760 to perform operation *POP0 with constant *PCONST0 at the outermost
9761 position. We would now like to also perform OP1 with constant CONST1
9762 (with *POP0 being done last).
9764 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9765 the resulting operation. *PCOMP_P is set to 1 if we would need to
9766 complement the innermost operand, otherwise it is unchanged.
9768 MODE is the mode in which the operation will be done. No bits outside
9769 the width of this mode matter. It is assumed that the width of this mode
9770 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9772 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9773 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9774 result is simply *PCONST0.
9776 If the resulting operation cannot be expressed as one operation, we
9777 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9779 static int
9780 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9781 {
9788 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9792 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9793 if OP0 is SET. */
9802 {
9804 {
9822 }
9823 }
9825 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9829 /* If the two constants aren't the same, we can't do anything. The
9830 remaining six cases can all be done. */
9834 else
9836 {
9839 /* (a & b) | b == b */
9842 /* (a ^ b) | b == a | b */
9843 {;}
9848 /* (a & b) ^ b == (~a) & b */
9851 /* (a | b) ^ b == a & ~b */
9857 /* (a | b) & b == b */
9860 /* (a ^ b) & b) == (~a) & b */
9865 }
9867 /* Check for NO-OP cases. */
9880 /* ??? Slightly redundant with the above mask, but not entirely.
9881 Moving this above means we'd have to sign-extend the mode mask
9882 for the final test. */
9887 }
9888 \f
9889 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9890 the shift in. The original shift operation CODE is performed on OP in
9891 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9892 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9893 result of the shift is subject to operation OUTER_CODE with operand
9894 OUTER_CONST. */
9896 static machine_mode
9900 {
9905 /* In general we can't perform in wider mode for right shift and rotate. */
9907 {
9909 /* We can still widen if the bits brought in from the left are identical
9910 to the sign bit of ORIG_MODE. */
9918 /* Similarly here but with zero bits. */
9923 /* We can also widen if the bits brought in will be masked off. This
9924 operation is performed in ORIG_MODE. */
9926 {
9932 }
9933 /* fall through */
9943 }
9944 }
9946 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9947 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9948 if we cannot simplify it. Otherwise, return a simplified value.
9950 The shift is normally computed in the widest mode we find in VAROP, as
9951 long as it isn't a different number of words than RESULT_MODE. Exceptions
9952 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9954 static rtx
9957 {
9963 unsigned int mode_words
9965 /* We form (outer_op (code varop count) (outer_const)). */
9971 /* Make sure and truncate the "natural" shift on the way in. We don't
9972 want to do this inside the loop as it makes it more difficult to
9973 combine shifts. */
9977 /* If we were given an invalid count, don't do anything except exactly
9978 what was requested. */
9985 /* Unless one of the branches of the `if' in this loop does a `continue',
9986 we will `break' the loop after the `if'. */
9989 {
9990 /* If we have an operand of (clobber (const_int 0)), fail. */
9994 /* Convert ROTATERT to ROTATE. */
9996 {
10001 else
10003 }
10008 /* Handle cases where the count is greater than the size of the mode
10009 minus 1. For ASHIFT, use the size minus one as the count (this can
10010 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10011 take the count modulo the size. For other shifts, the result is
10012 zero.
10014 Since these shifts are being produced by the compiler by combining
10015 multiple operations, each of which are defined, we know what the
10016 result is supposed to be. */
10019 {
10024 else
10025 {
10026 /* We can't simply return zero because there may be an
10027 outer op. */
10031 }
10032 }
10034 /* If we discovered we had to complement VAROP, leave. Making a NOT
10035 here would cause an infinite loop. */
10039 /* An arithmetic right shift of a quantity known to be -1 or 0
10040 is a no-op. */
10044 {
10047 }
10049 /* If we are doing an arithmetic right shift and discarding all but
10050 the sign bit copies, this is equivalent to doing a shift by the
10051 bitsize minus one. Convert it into that shift because it will often
10052 allow other simplifications. */
10059 /* We simplify the tests below and elsewhere by converting
10060 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10061 `make_compound_operation' will convert it to an ASHIFTRT for
10062 those machines (such as VAX) that don't have an LSHIFTRT. */
10079 {
10086 {
10089 }
10093 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10094 minus the width of a smaller mode, we can do this with a
10095 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10102 {
10111 }
10115 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10116 the same number of words as what we've seen so far. Then store
10117 the widest mode in MODE. */
10123 == mode_words
10126 {
10131 }
10135 /* Some machines use MULT instead of ASHIFT because MULT
10136 is cheaper. But it is still better on those machines to
10137 merge two shifts into one. */
10140 {
10141 varop
10147 }
10151 /* Similar, for when divides are cheaper. */
10154 {
10155 varop
10161 }
10165 /* If we are extracting just the sign bit of an arithmetic
10166 right shift, that shift is not needed. However, the sign
10167 bit of a wider mode may be different from what would be
10168 interpreted as the sign bit in a narrower mode, so, if
10169 the result is narrower, don't discard the shift. */
10174 {
10177 }
10179 /* ... fall through ... */
10184 /* Here we have two nested shifts. The result is usually the
10185 AND of a new shift with a mask. We compute the result below. */
10192 {
10196 rtx mask_rtx;
10198 /* We have one common special case. We can't do any merging if
10199 the inner code is an ASHIFTRT of a smaller mode. However, if
10200 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10201 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10202 we can convert it to
10203 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10204 This simplifies certain SIGN_EXTEND operations. */
10208 {
10209 /* C3 has the low-order C1 bits zero. */
10221 }
10223 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10224 than C1 high-order bits equal to the sign bit, we can convert
10225 this to either an ASHIFT or an ASHIFTRT depending on the
10226 two counts.
10228 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10234 {
10238 {
10241 }
10244 }
10246 /* There are some cases we can't do. If CODE is ASHIFTRT,
10247 we can only do this if FIRST_CODE is also ASHIFTRT.
10249 We can't do the case when CODE is ROTATE and FIRST_CODE is
10250 ASHIFTRT.
10252 If the mode of this shift is not the mode of the outer shift,
10253 we can't do this if either shift is a right shift or ROTATE.
10255 Finally, we can't do any of these if the mode is too wide
10256 unless the codes are the same.
10258 Handle the case where the shift codes are the same
10259 first. */
10262 {
10271 }
10282 /* To compute the mask to apply after the shift, shift the
10283 nonzero bits of the inner shift the same way the
10284 outer shift will. */
10287 result_mode);
10289 mask_rtx
10293 /* Give up if we can't compute an outer operation to use. */
10301 /* If the shifts are in the same direction, we add the
10302 counts. Otherwise, we subtract them. */
10306 else
10309 /* If COUNT is positive, the new shift is usually CODE,
10310 except for the two exceptions below, in which case it is
10311 FIRST_CODE. If the count is negative, FIRST_CODE should
10312 always be used */
10322 }
10324 /* If we have (A << B << C) for any shift, we can convert this to
10325 (A << C << B). This wins if A is a constant. Only try this if
10326 B is not a constant. */
10331 {
10338 }
10345 /* Make this fit the case below. */
10352 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10353 with C the size of VAROP - 1 and the shift is logical if
10354 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10355 we have an (le X 0) operation. If we have an arithmetic shift
10356 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10357 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10365 {
10368 const0_rtx);
10374 }
10376 /* If we have (shift (logical)), move the logical to the outside
10377 to allow it to possibly combine with another logical and the
10378 shift to combine with another shift. This also canonicalizes to
10379 what a ZERO_EXTRACT looks like. Also, some machines have
10380 (and (shift)) insns. */
10383 /* We can't do this if we have (ashiftrt (xor)) and the
10384 constant has its sign bit set in shift_mode with shift_mode
10385 wider than result_mode. */
10389 shift_mode))
10397 {
10400 }
10402 /* If we can't do that, try to simplify the shift in each arm of the
10403 logical expression, make a new logical expression, and apply
10404 the inverse distributive law. This also can't be done for
10405 (ashiftrt (xor)) where we've widened the shift and the constant
10406 changes the sign bit. */
10411 shift_mode)))
10412 {
10424 }
10428 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10429 says that the sign bit can be tested, FOO has mode MODE, C is
10430 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10431 that may be nonzero. */
10441 {
10445 }
10449 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10450 than the number of bits in the mode is equivalent to A. */
10454 {
10458 }
10460 /* NEG commutes with ASHIFT since it is multiplication. Move the
10461 NEG outside to allow shifts to combine. */
10465 {
10468 }
10472 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10473 is one less than the number of bits in the mode is
10474 equivalent to (xor A 1). */
10481 {
10485 }
10487 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10488 that might be nonzero in BAR are those being shifted out and those
10489 bits are known zero in FOO, we can replace the PLUS with FOO.
10490 Similarly in the other operand order. This code occurs when
10491 we are computing the size of a variable-size array. */
10498 {
10501 }
10509 result_mode)))
10510 {
10513 }
10515 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10525 {
10528 }
10530 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10531 signbit', and attempt to change the PLUS to an XOR and move it to
10532 the outer operation as is done above in the AND/IOR/XOR case
10533 leg for shift(logical). See details in logical handling above
10534 for reasoning in doing so. */
10545 {
10548 }
10553 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10554 with C the size of VAROP - 1 and the shift is logical if
10555 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10556 we have a (gt X 0) operation. If the shift is arithmetic with
10557 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10558 we have a (neg (gt X 0)) operation. */
10567 {
10570 const0_rtx);
10576 }
10580 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10581 if the truncate does not affect the value. */
10588 {
10591 varop_inner
10594 GEN_INT
10599 }
10604 }
10607 }
10612 /* We have now finished analyzing the shift. The result should be
10613 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10614 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10615 to the result of the shift. OUTER_CONST is the relevant constant,
10616 but we must turn off all bits turned off in the shift. */
10624 /* Make a SUBREG if necessary. If we can't make it, fail. */
10629 /* If we have an outer operation and we just made a shift, it is
10630 possible that we could have simplified the shift were it not
10631 for the outer operation. So try to do the simplification
10632 recursively. */
10636 else
10642 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10643 turn off all the bits that the shift would have turned off. */
10648 /* Do the remainder of the processing in RESULT_MODE. */
10651 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10652 operation. */
10657 {
10665 {
10666 /* This means that we have determined that the result is
10667 equivalent to a constant. This should be rare. */
10670 }
10673 else
10676 }
10679 }
10681 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10682 The result of the shift is RESULT_MODE. If we cannot simplify it,
10683 return X or, if it is NULL, synthesize the expression with
10684 simplify_gen_binary. Otherwise, return a simplified value.
10686 The shift is normally computed in the widest mode we find in VAROP, as
10687 long as it isn't a different number of words than RESULT_MODE. Exceptions
10688 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10690 static rtx
10693 {
10703 }
10705 \f
10706 /* Like recog, but we receive the address of a pointer to a new pattern.
10707 We try to match the rtx that the pointer points to.
10708 If that fails, we may try to modify or replace the pattern,
10709 storing the replacement into the same pointer object.
10711 Modifications include deletion or addition of CLOBBERs.
10713 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10714 the CLOBBERs are placed.
10716 The value is the final insn code from the pattern ultimately matched,
10717 or -1. */
10719 static int
10721 {
10723 rtx pat_without_clobbers;
10731 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10732 we use to indicate that something didn't match. If we find such a
10733 thing, force rejection. */
10747 {
10750 else
10753 }
10755 /* If it isn't, there is the possibility that we previously had an insn
10756 that clobbered some register as a side effect, but the combined
10757 insn doesn't need to do that. So try once more without the clobbers
10758 unless this represents an ASM insn. */
10762 {
10767 {
10770 pos++;
10771 }
10781 {
10784 else
10787 }
10788 }
10795 /* Recognize all noop sets, these will be killed by followup pass. */
10799 /* If we had any clobbers to add, make a new pattern than contains
10800 them. Then check to make sure that all of them are dead. */
10802 {
10812 else
10819 {
10824 {
10828 }
10829 }
10831 }
10835 {
10842 /* Allow targets to reject combined insn. */
10844 {
10847 dump_file);
10849 /* Callers expect recog_for_combine to strip
10850 clobbers from the pattern on failure. */
10855 }
10860 }
10866 }
10867 \f
10868 /* Like gen_lowpart_general but for use by combine. In combine it
10869 is not possible to create any new pseudoregs. However, it is
10870 safe to create invalid memory addresses, because combine will
10871 try to recognize them and all they will do is make the combine
10872 attempt fail.
10874 If for some reason this cannot do its job, an rtx
10875 (clobber (const_int 0)) is returned.
10876 An insn containing that will not be recognized. */
10878 static rtx
10880 {
10884 rtx result;
10889 /* We can only support MODE being wider than a word if X is a
10890 constant integer or has a mode the same size. */
10895 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10896 won't know what to do. So we will strip off the SUBREG here and
10897 process normally. */
10899 {
10902 /* For use in case we fall down into the address adjustments
10903 further below, we need to adjust the known mode and size of
10904 x; imode and isize, since we just adjusted x. */
10911 }
10919 {
10922 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10923 address. */
10928 /* If we want to refer to something bigger than the original memref,
10929 generate a paradoxical subreg instead. That will force a reload
10930 of the original memref X. */
10937 /* Adjust the address so that the address-after-the-data is
10938 unchanged. */
10943 }
10945 /* If X is a comparison operator, rewrite it in a new mode. This
10946 probably won't match, but may allow further simplifications. */
10950 /* If we couldn't simplify X any other way, just enclose it in a
10951 SUBREG. Normally, this SUBREG won't match, but some patterns may
10952 include an explicit SUBREG or we may simplify it further in combine. */
10953 else
10954 {
10956 rtx res;
10960 {
10965 }
10969 }
10971 fail:
10973 }
10974 \f
10975 /* Try to simplify a comparison between OP0 and a constant OP1,
10976 where CODE is the comparison code that will be tested, into a
10977 (CODE OP0 const0_rtx) form.
10979 The result is a possibly different comparison code to use.
10980 *POP1 may be updated. */
10982 static enum rtx_code
10985 {
10989 /* Get the constant we are comparing against and turn off all bits
10990 not on in our mode. */
10994 /* If we are comparing against a constant power of two and the value
10995 being compared can only have that single bit nonzero (e.g., it was
10996 `and'ed with that bit), we can replace this with a comparison
10997 with zero. */
11005 {
11008 }
11010 /* Similarly, if we are comparing a value known to be either -1 or
11011 0 with -1, change it to the opposite comparison against zero. */
11016 {
11019 }
11021 /* Do some canonicalizations based on the comparison code. We prefer
11022 comparisons against zero and then prefer equality comparisons.
11023 If we can reduce the size of a constant, we will do that too. */
11025 {
11027 /* < C is equivalent to <= (C - 1) */
11029 {
11032 /* ... fall through to LE case below. */
11033 }
11034 else
11038 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11040 {
11043 }
11045 /* If we are doing a <= 0 comparison on a value known to have
11046 a zero sign bit, we can replace this with == 0. */
11056 /* >= C is equivalent to > (C - 1). */
11058 {
11061 /* ... fall through to GT below. */
11062 }
11063 else
11067 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11069 {
11072 }
11074 /* If we are doing a > 0 comparison on a value known to have
11075 a zero sign bit, we can replace this with != 0. */
11085 /* < C is equivalent to <= (C - 1). */
11087 {
11090 /* ... fall through ... */
11091 }
11092 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11096 {
11100 }
11101 else
11105 /* unsigned <= 0 is equivalent to == 0 */
11108 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11112 {
11115 }
11119 /* >= C is equivalent to > (C - 1). */
11121 {
11124 /* ... fall through ... */
11125 }
11127 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11131 {
11135 }
11136 else
11140 /* unsigned > 0 is equivalent to != 0 */
11143 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11147 {
11150 }
11155 }
11159 }
11160 \f
11161 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11162 comparison code that will be tested.
11164 The result is a possibly different comparison code to use. *POP0 and
11165 *POP1 may be updated.
11167 It is possible that we might detect that a comparison is either always
11168 true or always false. However, we do not perform general constant
11169 folding in combine, so this knowledge isn't useful. Such tautologies
11170 should have been detected earlier. Hence we ignore all such cases. */
11172 static enum rtx_code
11174 {
11181 /* Try a few ways of applying the same transformation to both operands. */
11183 {
11184 #ifndef WORD_REGISTER_OPERATIONS
11185 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11186 so check specially. */
11201 - (GET_MODE_PRECISION
11203 {
11206 }
11207 #endif
11209 /* If both operands are the same constant shift, see if we can ignore the
11210 shift. We can if the shift is a rotate or if the bits shifted out of
11211 this shift are known to be zero for both inputs and if the type of
11212 comparison is compatible with the shift. */
11225 {
11238 else
11240 }
11242 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11243 SUBREGs are of the same mode, and, in both cases, the AND would
11244 be redundant if the comparison was done in the narrower mode,
11245 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11246 and the operand's possibly nonzero bits are 0xffffff01; in that case
11247 if we only care about QImode, we don't need the AND). This case
11248 occurs if the output mode of an scc insn is not SImode and
11249 STORE_FLAG_VALUE == 1 (e.g., the 386).
11251 Similarly, check for a case where the AND's are ZERO_EXTEND
11252 operations from some narrower mode even though a SUBREG is not
11253 present. */
11258 {
11275 {
11279 /* The resulting comparison is always unsigned since we masked
11280 off the original sign bit. */
11284 }
11291 {
11297 }
11301 }
11303 /* If both operands are NOT, we can strip off the outer operation
11304 and adjust the comparison code for swapped operands; similarly for
11305 NEG, except that this must be an equality comparison. */
11311 else
11313 }
11315 /* If the first operand is a constant, swap the operands and adjust the
11316 comparison code appropriately, but don't do this if the second operand
11317 is already a constant integer. */
11319 {
11322 }
11324 /* We now enter a loop during which we will try to simplify the comparison.
11325 For the most part, we only are concerned with comparisons with zero,
11326 but some things may really be comparisons with zero but not start
11327 out looking that way. */
11330 {
11337 HOST_WIDE_INT const_op;
11339 /* We only want to handle integral modes. This catches VOIDmode,
11340 CCmode, and the floating-point modes. An exception is that we
11341 can handle VOIDmode if OP0 is a COMPARE or a comparison
11342 operation. */
11349 /* Try to simplify the compare to constant, possibly changing the
11350 comparison op, and/or changing op1 to zero. */
11354 /* Compute some predicates to simplify code below. */
11361 /* If this is a sign bit comparison and we can do arithmetic in
11362 MODE, say that we will only be needing the sign bit of OP0. */
11369 /* Now try cases based on the opcode of OP0. If none of the cases
11370 does a "continue", we exit this loop immediately after the
11371 switch. */
11374 {
11376 /* If we are extracting a single bit from a variable position in
11377 a constant that has only a single bit set and are comparing it
11378 with zero, we can convert this into an equality comparison
11379 between the position and the location of the single bit. */
11380 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11381 have already reduced the shift count modulo the word size. */
11387 {
11395 /* Result is nonzero iff shift count is equal to I. */
11398 }
11400 /* ... fall through ... */
11405 {
11408 }
11412 /* If testing for equality, we can take the NOT of the constant. */
11415 {
11419 }
11421 /* If just looking at the sign bit, reverse the sense of the
11422 comparison. */
11424 {
11428 }
11432 /* If testing for equality, we can take the NEG of the constant. */
11435 {
11439 }
11441 /* The remaining cases only apply to comparisons with zero. */
11445 /* When X is ABS or is known positive,
11446 (neg X) is < 0 if and only if X != 0. */
11454 {
11458 }
11460 /* If we have NEG of something whose two high-order bits are the
11461 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11463 {
11467 }
11471 /* If we are testing equality and our count is a constant, we
11472 can perform the inverse operation on our RHS. */
11476 {
11480 }
11482 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11483 a particular bit. Convert it to an AND of a constant of that
11484 bit. This will be converted into a ZERO_EXTRACT. */
11488 {
11495 }
11497 /* Fall through. */
11500 /* ABS is ignorable inside an equality comparison with zero. */
11502 {
11505 }
11509 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11510 (compare FOO CONST) if CONST fits in FOO's mode and we
11511 are either testing inequality or have an unsigned
11512 comparison with ZERO_EXTEND or a signed comparison with
11513 SIGN_EXTEND. But don't do it if we don't have a compare
11514 insn of the given mode, since we'd have to revert it
11515 later on, and then we wouldn't know whether to sign- or
11516 zero-extend. */
11519 && ! unsigned_comparison_p
11523 {
11526 }
11530 /* Check for the case where we are comparing A - C1 with C2, that is
11532 (subreg:MODE (plus (A) (-C1))) op (C2)
11534 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11535 comparison in the wider mode. One of the following two conditions
11536 must be true in order for this to be valid:
11538 1. The mode extension results in the same bit pattern being added
11539 on both sides and the comparison is equality or unsigned. As
11540 C2 has been truncated to fit in MODE, the pattern can only be
11541 all 0s or all 1s.
11543 2. The mode extension results in the sign bit being copied on
11544 each side.
11546 The difficulty here is that we have predicates for A but not for
11547 (A - C1) so we need to check that C1 is within proper bounds so
11548 as to perturbate A as little as possible. */
11555 {
11564 /* (A - C1) zero-extends if it is positive and sign-extends
11565 if it is negative, C2 both zero- and sign-extends. */
11569 /* (A - C1) sign-extends if it is positive and 1-extends
11570 if it is negative, C2 both sign- and 1-extends. */
11577 /* (A - C1) always sign-extends, like C2. */
11581 {
11584 }
11585 }
11587 /* If the inner mode is narrower and we are extracting the low part,
11588 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11592 else
11595 /* ... fall through ... */
11605 {
11608 }
11612 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11613 this for equality comparisons due to pathological cases involving
11614 overflows. */
11618 {
11622 }
11624 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11627 {
11631 }
11635 /* We used to optimize signed comparisons against zero, but that
11636 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11637 arrive here as equality comparisons, or (GEU, LTU) are
11638 optimized away. No need to special-case them. */
11640 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11641 (eq B (minus A C)), whichever simplifies. We can only do
11642 this for equality comparisons due to pathological cases involving
11643 overflows. */
11647 {
11651 }
11656 {
11660 }
11662 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11663 of bits in X minus 1, is one iff X > 0. */
11668 {
11672 }
11676 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11677 if C is zero or B is a constant. */
11681 {
11685 }
11693 /* We can't do anything if OP0 is a condition code value, rather
11694 than an actual data value. */
11700 /* Get the two operands being compared. */
11703 else
11706 /* Check for the cases where we simply want the result of the
11707 earlier test or the opposite of that result. */
11711 {
11715 else
11719 {
11724 }
11725 }
11729 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11730 iff X <= 0. */
11734 {
11738 }
11742 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11743 will be converted to a ZERO_EXTRACT later. */
11747 {
11752 }
11754 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11755 zero and X is a comparison and C1 and C2 describe only bits set
11756 in STORE_FLAG_VALUE, we can compare with X. */
11764 {
11771 {
11774 }
11775 }
11777 /* If we are doing an equality comparison of an AND of a bit equal
11778 to the sign bit, replace this with a LT or GE comparison of
11779 the underlying value. */
11786 {
11790 }
11792 /* If this AND operation is really a ZERO_EXTEND from a narrower
11793 mode, the constant fits within that mode, and this is either an
11794 equality or unsigned comparison, try to do this comparison in
11795 the narrower mode.
11797 Note that in:
11799 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11800 -> (ne:DI (reg:SI 4) (const_int 0))
11802 unless TRULY_NOOP_TRUNCATION allows it or the register is
11803 known to hold a value of the required mode the
11804 transformation is invalid. */
11815 {
11818 }
11820 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11821 fits in both M1 and M2 and the SUBREG is either paradoxical
11822 or represents the low part, permute the SUBREG and the AND
11823 and try again. */
11825 {
11828 /* Require an integral mode, to avoid creating something like
11829 (AND:SF ...). */
11831 /* It is unsafe to commute the AND into the SUBREG if the
11832 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11833 not defined. As originally written the upper bits
11834 have a defined value due to the AND operation.
11835 However, if we commute the AND inside the SUBREG then
11836 they no longer have defined values and the meaning of
11837 the code has been changed. */
11839 #ifdef WORD_REGISTER_OPERATIONS
11842 #endif
11852 {
11858 }
11859 }
11861 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11865 {
11870 }
11872 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11873 (eq (and (lshiftrt X) 1) 0).
11874 Also handle the case where (not X) is expressed using xor. */
11878 {
11890 {
11891 op0
11896 }
11897 }
11901 /* If we have (compare (ashift FOO N) (const_int C)) and
11902 the high order N bits of FOO (N+1 if an inequality comparison)
11903 are known to be zero, we can do this by comparing FOO with C
11904 shifted right N bits so long as the low-order N bits of C are
11905 zero. */
11917 {
11918 /* We must perform a logical shift, not an arithmetic one,
11919 as we want the top N bits of C to be zero. */
11926 }
11928 /* If we are doing a sign bit comparison, it means we are testing
11929 a particular bit. Convert it to the appropriate AND. */
11932 {
11939 }
11941 /* If this an equality comparison with zero and we are shifting
11942 the low bit to the sign bit, we can convert this to an AND of the
11943 low-order bit. */
11947 {
11950 }
11954 /* If this is an equality comparison with zero, we can do this
11955 as a logical shift, which might be much simpler. */
11958 {
11963 }
11965 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11966 do the comparison in a narrower mode. */
11976 {
11979 }
11981 /* Likewise if OP0 is a PLUS of a sign extension with a
11982 constant, which is usually represented with the PLUS
11983 between the shifts. */
11995 {
12003 new_const);
12005 }
12007 /* ... fall through ... */
12009 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12010 the low order N bits of FOO are known to be zero, we can do this
12011 by comparing FOO with C shifted left N bits so long as no
12012 overflow occurs. Even if the low order N bits of FOO aren't known
12013 to be zero, if the comparison is >= or < we can use the same
12014 optimization and for > or <= by setting all the low
12015 order N bits in the comparison constant. */
12026 {
12027 unsigned HOST_WIDE_INT low_bits
12032 {
12033 /* If the shift was logical, then we must make the condition
12034 unsigned. */
12042 const_op
12047 }
12048 }
12050 /* If we are using this shift to extract just the sign bit, we
12051 can replace this with an LT or GE comparison. */
12056 {
12060 }
12065 }
12068 }
12070 /* Now make any compound operations involved in this comparison. Then,
12071 check for an outmost SUBREG on OP0 that is not doing anything or is
12072 paradoxical. The latter transformation must only be performed when
12073 it is known that the "extra" bits will be the same in op0 and op1 or
12074 that they don't matter. There are three cases to consider:
12076 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12077 care bits and we can assume they have any convenient value. So
12078 making the transformation is safe.
12080 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12081 In this case the upper bits of op0 are undefined. We should not make
12082 the simplification in that case as we do not know the contents of
12083 those bits.
12085 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12086 UNKNOWN. In that case we know those bits are zeros or ones. We must
12087 also be sure that they are the same as the upper bits of op1.
12089 We can never remove a SUBREG for a non-equality comparison because
12090 the sign bit is in a different place in the underlying object. */
12099 {
12101 {
12102 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12103 implemented. */
12105 {
12108 }
12109 }
12115 {
12121 }
12122 }
12124 /* We now do the opposite procedure: Some machines don't have compare
12125 insns in all modes. If OP0's mode is an integer mode smaller than a
12126 word and we can't do a compare in that mode, see if there is a larger
12127 mode for which we can do the compare. There are a number of cases in
12128 which we can use the wider mode. */
12138 {
12141 /* If this is a test for negative, we can make an explicit
12142 test of the sign bit. Test this first so we can use
12143 a paradoxical subreg to extend OP0. */
12147 {
12148 unsigned HOST_WIDE_INT sign
12155 }
12157 /* If the only nonzero bits in OP0 and OP1 are those in the
12158 narrower mode and this is an equality or unsigned comparison,
12159 we can use the wider mode. Similarly for sign-extended
12160 values, in which case it is true for all comparisons. */
12177 {
12178 /* If OP0 is an AND and we don't have an AND in MODE either,
12179 make a new AND in the proper mode. */
12187 else
12188 {
12190 {
12193 }
12194 else
12195 {
12198 }
12200 }
12201 }
12202 }
12204 /* We may have changed the comparison operands. Re-canonicalize. */
12206 {
12209 }
12211 /* If this machine only supports a subset of valid comparisons, see if we
12212 can convert an unsupported one into a supported one. */
12219 }
12220 \f
12221 /* Utility function for record_value_for_reg. Count number of
12222 rtxs in X. */
12223 static int
12225 {
12232 {
12252 }
12263 }
12264 \f
12265 /* Utility function for following routine. Called when X is part of a value
12266 being stored into last_set_value. Sets last_set_table_tick
12267 for each register mentioned. Similar to mention_regs in cse.c */
12269 static void
12271 {
12277 {
12283 {
12286 }
12289 }
12293 {
12294 /* Check for identical subexpressions. If x contains
12295 identical subexpression we only have to traverse one of
12296 them. */
12298 {
12299 /* Note that at this point x1 has already been
12300 processed. */
12304 /* If x0 and x1 are identical then there is no need to
12305 process x0. */
12309 /* If x0 is identical to a subexpression of x1 then while
12310 processing x1, x0 has already been processed. Thus we
12311 are done with x. */
12316 /* If x1 is identical to a subexpression of x0 then we
12317 still have to process the rest of x0. */
12320 {
12323 }
12324 }
12327 }
12331 }
12333 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12334 are saying that the register is clobbered and we no longer know its
12335 value. If INSN is zero, don't update reg_stat[].last_set; this is
12336 only permitted with VALUE also zero and is used to invalidate the
12337 register. */
12339 static void
12341 {
12347 /* If VALUE contains REG and we have a previous value for REG, substitute
12348 the previous value. */
12350 {
12351 rtx tem;
12353 /* Set things up so get_last_value is allowed to see anything set up to
12354 our insn. */
12358 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12359 it isn't going to be useful and will take a lot of time to process,
12360 so just use the CLOBBER. */
12363 {
12369 {
12370 /* If there are two or more occurrences of REG in VALUE,
12371 prevent the value from growing too much. */
12374 }
12377 }
12378 }
12380 /* For each register modified, show we don't know its value, that
12381 we don't know about its bitwise content, that its value has been
12382 updated, and that we don't know the location of the death of the
12383 register. */
12385 {
12397 }
12399 /* Mark registers that are being referenced in this value. */
12403 /* Now update the status of each register being set.
12404 If someone is using this register in this block, set this register
12405 to invalid since we will get confused between the two lives in this
12406 basic block. This makes using this register always invalid. In cse, we
12407 scan the table to invalidate all entries using this register, but this
12408 is too much work for us. */
12411 {
12417 else
12419 }
12421 /* The value being assigned might refer to X (like in "x++;"). In that
12422 case, we must replace it with (clobber (const_int 0)) to prevent
12423 infinite loops. */
12426 {
12430 }
12432 /* For the main register being modified, update the value, the mode, the
12433 nonzero bits, and the number of sign bit copies. */
12438 {
12446 rsp->last_set_sign_bit_copies
12448 }
12449 }
12451 /* Called via note_stores from record_dead_and_set_regs to handle one
12452 SET or CLOBBER in an insn. DATA is the instruction in which the
12453 set is occurring. */
12455 static void
12457 {
12464 {
12468 }
12471 {
12472 /* If we are setting the whole register, we know its value. Otherwise
12473 show that we don't know the value. We can handle SUBREG in
12474 some cases. */
12485 else
12487 }
12489 /* Ignore pushes, they clobber nothing. */
12492 }
12494 /* Update the records of when each REG was most recently set or killed
12495 for the things done by INSN. This is the last thing done in processing
12496 INSN in the combiner loop.
12498 We update reg_stat[], in particular fields last_set, last_set_value,
12499 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12500 last_death, and also the similar information mem_last_set (which insn
12501 most recently modified memory) and last_call_luid (which insn was the
12502 most recent subroutine call). */
12504 static void
12506 {
12507 rtx link;
12511 {
12514 {
12519 {
12524 }
12525 }
12528 }
12531 {
12532 hard_reg_set_iterator hrsi;
12534 {
12546 }
12550 /* We can't combine into a call pattern. Remember, though, that
12551 the return value register is set at this LUID. We could
12552 still replace a register with the return value from the
12553 wrong subroutine call! */
12555 }
12556 else
12558 }
12560 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12561 register present in the SUBREG, so for each such SUBREG go back and
12562 adjust nonzero and sign bit information of the registers that are
12563 known to have some zero/sign bits set.
12565 This is needed because when combine blows the SUBREGs away, the
12566 information on zero/sign bits is lost and further combines can be
12567 missed because of that. */
12569 static void
12571 {
12573 rtx set;
12581 {
12590 {
12593 }
12597 {
12600 }
12603 {
12606 }
12607 else
12609 }
12610 }
12612 /* Check if X, a register, is known to contain a value already
12613 truncated to MODE. In this case we can use a subreg to refer to
12614 the truncated value even though in the generic case we would need
12615 an explicit truncation. */
12617 static bool
12619 {
12631 }
12633 /* If X is a hard reg or a subreg record the mode that the register is
12634 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12635 to turn a truncate into a subreg using this information. Return true
12636 if traversing X is complete. */
12638 static bool
12640 {
12641 machine_mode truncated_mode;
12645 {
12656 }
12657 /* ??? For hard-regs we now record everything. We might be able to
12658 optimize this using last_set_mode. */
12661 else
12669 {
12672 }
12675 }
12677 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12678 the modes they are used in. This can help truning TRUNCATEs into
12679 SUBREGs. */
12681 static void
12683 {
12688 }
12690 /* Scan X for promoted SUBREGs. For each one found,
12691 note what it implies to the registers used in it. */
12693 static void
12695 {
12700 else
12701 {
12707 {
12717 }
12718 }
12719 }
12720 \f
12721 /* Verify that all the registers and memory references mentioned in *LOC are
12722 still valid. *LOC was part of a value set in INSN when label_tick was
12723 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12724 the invalid references with (clobber (const_int 0)) and return 1. This
12725 replacement is useful because we often can get useful information about
12726 the form of a value (e.g., if it was produced by a shift that always
12727 produces -1 or 0) even though we don't know exactly what registers it
12728 was produced from. */
12730 static int
12732 {
12739 {
12745 {
12748 /* If this is a pseudo-register that was only set once and not
12749 live at the beginning of the function, it is always valid. */
12752 && (!REGNO_REG_SET_P
12754 regno)))
12756 {
12760 }
12761 }
12764 }
12765 /* If this is a memory reference, make sure that there were no stores after
12766 it that might have clobbered the value. We don't have alias info, so we
12767 assume any store invalidates it. Moreover, we only have local UIDs, so
12768 we also assume that there were stores in the intervening basic blocks. */
12771 {
12775 }
12778 {
12780 {
12781 /* Check for identical subexpressions. If x contains
12782 identical subexpression we only have to traverse one of
12783 them. */
12785 {
12786 /* Note that at this point x0 has already been checked
12787 and found valid. */
12791 /* If x0 and x1 are identical then x is also valid. */
12795 /* If x1 is identical to a subexpression of x0 then
12796 while checking x0, x1 has already been checked. Thus
12797 it is valid and so as x. */
12802 /* If x0 is identical to a subexpression of x1 then x is
12803 valid iff the rest of x1 is valid. */
12806 return
12810 }
12815 }
12821 }
12823 /* If we haven't found a reason for it to be invalid, it is valid. */
12825 }
12827 /* Get the last value assigned to X, if known. Some registers
12828 in the value may be replaced with (clobber (const_int 0)) if their value
12829 is known longer known reliably. */
12831 static rtx
12833 {
12835 rtx value;
12838 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12839 then convert it to the desired mode. If this is a paradoxical SUBREG,
12840 we cannot predict what values the "extra" bits might have. */
12854 /* If we don't have a value, or if it isn't for this basic block and
12855 it's either a hard register, set more than once, or it's a live
12856 at the beginning of the function, return 0.
12858 Because if it's not live at the beginning of the function then the reg
12859 is always set before being used (is never used without being set).
12860 And, if it's set only once, and it's always set before use, then all
12861 uses must have the same last value, even if it's not from this basic
12862 block. */
12868 || REGNO_REG_SET_P
12872 /* If the value was set in a later insn than the ones we are processing,
12873 we can't use it even if the register was only set once. */
12878 /* If the value has all its registers valid, return it. */
12882 /* Otherwise, make a copy and replace any invalid register with
12883 (clobber (const_int 0)). If that fails for some reason, return 0. */
12890 }
12891 \f
12892 /* Return nonzero if expression X refers to a REG or to memory
12893 that is set in an instruction more recent than FROM_LUID. */
12895 static int
12897 {
12903 {
12907 #ifdef PUSH_ROUNDING
12908 /* Don't allow uses of the stack pointer to be moved,
12909 because we don't know whether the move crosses a push insn. */
12912 #endif
12914 {
12920 }
12922 }
12930 {
12932 {
12937 }
12941 }
12943 }
12944 \f
12945 /* Define three variables used for communication between the following
12946 routines. */
12951 /* Function called via note_stores from reg_dead_at_p.
12953 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12954 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12956 static void
12958 {
12968 }
12970 /* Return nonzero if REG is known to be dead at INSN.
12972 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12973 referencing REG, it is dead. If we hit a SET referencing REG, it is
12974 live. Otherwise, see if it is live or dead at the start of the basic
12975 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12976 must be assumed to be always live. */
12978 static int
12980 {
12981 basic_block block;
12984 /* Set variables for reg_dead_at_p_1. */
12990 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12991 we allow the machine description to decide whether use-and-clobber
12992 patterns are OK. */
12994 {
12998 }
13000 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13001 beginning of basic block. */
13004 {
13006 {
13016 }
13022 }
13024 /* Look at live-in sets for the basic block that we were in. */
13030 }
13031 \f
13032 /* Note hard registers in X that are used. */
13034 static void
13036 {
13042 {
13046 CASE_CONST_ANY:
13051 #ifdef HAVE_cc0
13052 /* CC0 must die in the insn after it is set, so we don't need to take
13053 special note of it here. */
13055 #endif
13059 /* If we are clobbering a MEM, mark any hard registers inside the
13060 address as used. */
13067 /* A hard reg in a wide mode may really be multiple registers.
13068 If so, mark all of them just like the first. */
13070 {
13071 /* None of this applies to the stack, frame or arg pointers. */
13073 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13075 #endif
13076 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13078 #endif
13083 }
13087 {
13088 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13089 the address. */
13101 }
13106 }
13108 /* Recursively scan the operands of this expression. */
13110 {
13114 {
13118 {
13123 }
13124 }
13125 }
13126 }
13127 \f
13128 /* Remove register number REGNO from the dead registers list of INSN.
13130 Return the note used to record the death, if there was one. */
13132 rtx
13134 {
13141 }
13143 /* For each register (hardware or pseudo) used within expression X, if its
13144 death is in an instruction with luid between FROM_LUID (inclusive) and
13145 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13146 list headed by PNOTES.
13148 That said, don't move registers killed by maybe_kill_insn.
13150 This is done when X is being merged by combination into TO_INSN. These
13151 notes will then be distributed as needed. */
13153 static void
13156 {
13162 {
13166 /* Don't move the register if it gets killed in between from and to. */
13175 {
13178 /* It is possible for the call above to return 0. This can occur
13179 when last_death points to I2 or I1 that we combined with.
13180 In that case make a new note.
13182 We must also check for the case where X is a hard register
13183 and NOTE is a death note for a range of hard registers
13184 including X. In that case, we must put REG_DEAD notes for
13185 the remaining registers in place of NOTE. */
13190 {
13199 }
13201 /* If we didn't find any note, or if we found a REG_DEAD note that
13202 covers only part of the given reg, and we have a multi-reg hard
13203 register, then to be safe we must check for REG_DEAD notes
13204 for each register other than the first. They could have
13205 their own REG_DEAD notes lying around. */
13212 {
13219 else
13225 }
13228 {
13231 }
13232 else
13234 }
13237 }
13240 {
13245 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13246 that accesses one word of a multi-word item, some
13247 piece of everything register in the expression is used by
13248 this insn, so remove any old death. */
13249 /* ??? So why do we test for equality of the sizes? */
13258 {
13261 }
13263 /* If this is some other SUBREG, we know it replaces the entire
13264 value, so use that as the destination. */
13268 /* If this is a MEM, adjust deaths of anything used in the address.
13269 For a REG (the only other possibility), the entire value is
13270 being replaced so the old value is not used in this insn. */
13276 }
13285 {
13287 {
13292 }
13295 }
13296 }
13297 \f
13298 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13299 pattern of an insn. X must be a REG. */
13301 static int
13303 {
13307 {
13309 rtx target;
13316 else
13333 }
13341 }
13342 \f
13343 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13344 as appropriate. I3 and I2 are the insns resulting from the combination
13345 insns including FROM (I2 may be zero).
13347 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13348 not need REG_DEAD notes because they are being substituted for. This
13349 saves searching in the most common cases.
13351 Each note in the list is either ignored or placed on some insns, depending
13352 on the type of note. */
13354 static void
13357 {
13359 rtx tem_note;
13363 {
13368 {
13371 /* Doesn't matter much where we put this, as long as it's somewhere.
13372 It is preferable to keep these notes on branches, which is most
13373 likely to be i3. */
13380 else
13381 {
13384 }
13388 /* These notes must remain with the call or trapping instruction. */
13393 else
13394 {
13400 /* ??? Otherwise assume we've combined things such that we
13401 can now prove that the instructions can't trap. Drop the
13402 note in this case. */
13403 }
13407 /* ??? How to distribute between i3-i1. Assume i3 contains the
13408 entire adjustment. Assert i3 contains at least some adjust. */
13410 {
13412 /* fixup_args_size_notes looks at REG_NORETURN note,
13413 so ensure the note is placed there first. */
13415 {
13419 {
13425 }
13426 }
13428 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13429 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13432 && !ACCUMULATE_OUTGOING_ARGS
13434 }
13441 /* These notes must remain with the call. It should not be
13442 possible for both I2 and I3 to be a call. */
13445 else
13446 {
13449 }
13453 /* Any clobbers for i3 may still exist, and so we must process
13454 REG_UNUSED notes from that insn.
13456 Any clobbers from i2 or i1 can only exist if they were added by
13457 recog_for_combine. In that case, recog_for_combine created the
13458 necessary REG_UNUSED notes. Trying to keep any original
13459 REG_UNUSED notes from these insns can cause incorrect output
13460 if it is for the same register as the original i3 dest.
13461 In that case, we will notice that the register is set in i3,
13462 and then add a REG_UNUSED note for the destination of i3, which
13463 is wrong. However, it is possible to have REG_UNUSED notes from
13464 i2 or i1 for register which were both used and clobbered, so
13465 we keep notes from i2 or i1 if they will turn into REG_DEAD
13466 notes. */
13468 /* If this register is set or clobbered in I3, put the note there
13469 unless there is one already. */
13471 {
13479 }
13480 /* Otherwise, if this register is used by I3, then this register
13481 now dies here, so we must put a REG_DEAD note here unless there
13482 is one already. */
13488 {
13491 }
13497 /* These notes say something about results of an insn. We can
13498 only support them if they used to be on I3 in which case they
13499 remain on I3. Otherwise they are ignored.
13501 If the note refers to an expression that is not a constant, we
13502 must also ignore the note since we cannot tell whether the
13503 equivalence is still true. It might be possible to do
13504 slightly better than this (we only have a problem if I2DEST
13505 or I1DEST is present in the expression), but it doesn't
13506 seem worth the trouble. */
13514 /* These notes say something about how a register is used. They must
13515 be present on any use of the register in I2 or I3. */
13520 {
13523 else
13525 }
13530 /* This can show up in several ways -- either directly in the
13531 pattern, or hidden off in the constant pool with (or without?)
13532 a REG_EQUAL note. */
13533 /* ??? Ignore the without-reg_equal-note problem for now. */
13545 {
13548 else
13550 }
13552 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13553 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13554 there. */
13559 {
13566 }
13572 {
13580 }
13584 /* This note says something about the value of a register prior
13585 to the execution of an insn. It is too much trouble to see
13586 if the note is still correct in all situations. It is better
13587 to simply delete it. */
13591 /* If we replaced the right hand side of FROM_INSN with a
13592 REG_EQUAL note, the original use of the dying register
13593 will not have been combined into I3 and I2. In such cases,
13594 FROM_INSN is guaranteed to be the first of the combined
13595 instructions, so we simply need to search back before
13596 FROM_INSN for the previous use or set of this register,
13597 then alter the notes there appropriately.
13599 If the register is used as an input in I3, it dies there.
13600 Similarly for I2, if it is nonzero and adjacent to I3.
13602 If the register is not used as an input in either I3 or I2
13603 and it is not one of the registers we were supposed to eliminate,
13604 there are two possibilities. We might have a non-adjacent I2
13605 or we might have somehow eliminated an additional register
13606 from a computation. For example, we might have had A & B where
13607 we discover that B will always be zero. In this case we will
13608 eliminate the reference to A.
13610 In both cases, we must search to see if we can find a previous
13611 use of A and put the death note there. */
13617 else
13618 {
13629 && !(i2mod
13631 i2mod_old_rhs)))
13636 }
13639 {
13643 {
13645 {
13649 }
13651 /* If the register is being set at TEM_INSN, see if that is all
13652 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13653 into a REG_UNUSED note instead. Don't delete sets to
13654 global register vars. */
13658 {
13661 #ifdef HAVE_cc0
13663 #endif
13671 ;
13673 /* Verify that it was the set, and not a clobber that
13674 modified the register.
13676 CC0 targets must be careful to maintain setter/user
13677 pairs. If we cannot delete the setter due to side
13678 effects, mark the user with an UNUSED note instead
13679 of deleting it. */
13683 #ifdef HAVE_cc0
13687 #endif
13688 )
13689 {
13690 /* Move the notes and links of TEM_INSN elsewhere.
13691 This might delete other dead insns recursively.
13692 First set the pattern to something that won't use
13693 any register. */
13707 #ifdef HAVE_cc0
13708 /* Delete the setter too. */
13710 {
13723 }
13724 #endif
13725 }
13726 else
13727 {
13730 /* If there isn't already a REG_UNUSED note, put one
13731 here. Do not place a REG_DEAD note, even if
13732 the register is also used here; that would not
13733 match the algorithm used in lifetime analysis
13734 and can cause the consistency check in the
13735 scheduler to fail. */
13740 }
13741 }
13745 {
13748 /* If we are doing a 3->2 combination, and we have a
13749 register which formerly died in i3 and was not used
13750 by i2, which now no longer dies in i3 and is used in
13751 i2 but does not die in i2, and place is between i2
13752 and i3, then we may need to move a link from place to
13753 i2. */
13755 && from_insn
13758 {
13762 }
13764 }
13768 }
13770 }
13772 /* If the register is set or already dead at PLACE, we needn't do
13773 anything with this note if it is still a REG_DEAD note.
13774 We check here if it is set at all, not if is it totally replaced,
13775 which is what `dead_or_set_p' checks, so also check for it being
13776 set partially. */
13779 {
13785 {
13786 /* Unless the register previously died in PLACE, clear
13787 last_death. [I no longer understand why this is
13788 being done.] */
13792 }
13793 else
13796 /* If this is a death note for a hard reg that is occupying
13797 multiple registers, ensure that we are still using all
13798 parts of the object. If we find a piece of the object
13799 that is unused, we must arrange for an appropriate REG_DEAD
13800 note to be added for it. However, we can't just emit a USE
13801 and tag the note to it, since the register might actually
13802 be dead; so we recourse, and the recursive call then finds
13803 the previous insn that used this register. */
13807 {
13816 {
13819 }
13822 {
13823 /* Put only REG_DEAD notes for pieces that are
13824 not already dead or set. */
13828 {
13835 {
13837 NULL_RTX);
13841 NULL_RTX);
13842 }
13848 {
13850 {
13854 }
13858 {
13861 }
13862 }
13863 }
13866 }
13867 }
13868 }
13872 /* Any other notes should not be present at this point in the
13873 compilation. */
13875 }
13878 {
13881 }
13885 }
13886 }
13887 \f
13888 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13889 I3, I2, and I1 to new locations. This is also called to add a link
13890 pointing at I3 when I3's destination is changed. */
13892 static void
13894 {
13898 {
13905 /* If the insn that this link points to is a NOTE, ignore it. */
13914 {
13917 {
13933 }
13936 }
13937 else
13947 /* A LOG_LINK is defined as being placed on the first insn that uses
13948 a register and points to the insn that sets the register. Start
13949 searching at the next insn after the target of the link and stop
13950 when we reach a set of the register or the end of the basic block.
13952 Note that this correctly handles the link that used to point from
13953 I3 to I2. Also note that not much searching is typically done here
13954 since most links don't point very far away. */
13963 {
13967 }
13970 {
13973 }
13977 /* If we found a place to put the link, place it there unless there
13978 is already a link to the same insn as LINK at that point. */
13981 {
13989 {
13993 /* Set added_links_insn to the earliest insn we added a
13994 link to. */
13998 }
13999 }
14000 }
14001 }
14002 \f
14003 /* Check for any register or memory mentioned in EQUIV that is not
14004 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14005 of EXPR where some registers may have been replaced by constants. */
14007 static bool
14009 {
14012 {
14017 }
14019 }
14020 \f
14021 DEBUG_FUNCTION void
14023 {
14024 fprintf
14026 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14028 }
14030 void
14032 {
14033 fprintf
14035 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14037 }
14038 \f
14039 /* Try combining insns through substitution. */
14040 static unsigned int
14042 {
14051 rebuild_jump_labels_after_combine
14054 /* Combining insns may have turned an indirect jump into a
14055 direct jump. Rebuild the JUMP_LABEL fields of jumping
14056 instructions. */
14058 {
14063 }
14067 }
14072 {
14082 };
14085 {
14089 {}
14091 /* opt_pass methods: */
14094 {
14096 }
14102 rtl_opt_pass *
14104 {
14106 }