libgfortran/config/fpu-387.h

   1 /* FPU-related code for x86 and x86_64 processors.
   2    Copyright 2005, 2007, 2009, 2010 Free Software Foundation, Inc.
   3    Contributed by Francois-Xavier Coudert <coudert@clipper.ens.fr>
   4
   5 This file is part of the GNU Fortran 95 runtime library (libgfortran).
   6
   7 Libgfortran is free software; you can redistribute it and/or
   8 modify it under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either
  10 version 3 of the License, or (at your option) any later version.
  11
  12 Libgfortran is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 Under Section 7 of GPL version 3, you are granted additional
  18 permissions described in the GCC Runtime Library Exception, version
  19 3.1, as published by the Free Software Foundation.
  20
  21 You should have received a copy of the GNU General Public License and
  22 a copy of the GCC Runtime Library Exception along with this program;
  23 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  24 <http://www.gnu.org/licenses/>.  */
  25
  26 #ifndef __x86_64__
  27 #include "cpuid.h"
  28 #endif
  29
  30 #if defined(__sun__) && defined(__svr4__)
  31 #include <signal.h>
  32 #include <ucontext.h>
  33
  34 static volatile sig_atomic_t sigill_caught;
  35
  36 static void
  37 sigill_hdlr (int sig __attribute((unused)),
  38              siginfo_t *sip __attribute__((unused)),
  39              ucontext_t *ucp)
  40 {
  41   sigill_caught = 1;
  42   /* Set PC to the instruction after the faulting one to skip over it,
  43      otherwise we enter an infinite loop.  4 is the size of the stmxcsr
  44      instruction.  */
  45   ucp->uc_mcontext.gregs[EIP] += 4;
  46   setcontext (ucp);
  47 }
  48 #endif
  49
  50 static int
  51 has_sse (void)
  52 {
  53 #ifndef __x86_64__
  54   unsigned int eax, ebx, ecx, edx;
  55
  56   if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
  57     return 0;
  58
  59 #if defined(__sun__) && defined(__svr4__)
  60   /* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions even
  61      if the CPU supports them.  Programs receive SIGILL instead, so check
  62      for that at runtime.  */
  63
  64   if (edx & bit_SSE)
  65     {
  66       struct sigaction act, oact;
  67       unsigned int cw_sse;
  68
  69       act.sa_handler = sigill_hdlr;
  70       sigemptyset (&act.sa_mask);
  71       /* Need to set SA_SIGINFO so a ucontext_t * is passed to the handler.  */
  72       act.sa_flags = SA_SIGINFO;
  73       sigaction (SIGILL, &act, &oact);
  74
  75       asm volatile ("stmxcsr %0" : "=m" (cw_sse));
  76
  77       sigaction (SIGILL, &oact, NULL);
  78
  79       if (sigill_caught)
  80         return 0;
  81     }
  82 #endif /* __sun__ && __svr4__ */
  83
  84   return edx & bit_SSE;
  85 #else
  86   return 1;
  87 #endif
  88 }
  89
  90 /* i387 -- see linux <fpu_control.h> header file for details.  */
  91 #define _FPU_MASK_IM  0x01
  92 #define _FPU_MASK_DM  0x02
  93 #define _FPU_MASK_ZM  0x04
  94 #define _FPU_MASK_OM  0x08
  95 #define _FPU_MASK_UM  0x10
  96 #define _FPU_MASK_PM  0x20
  97
  98 void set_fpu (void)
  99 {
 100   unsigned short cw;
 101
 102   asm volatile ("fnstcw %0" : "=m" (cw));
 103
 104   cw |= (_FPU_MASK_IM | _FPU_MASK_DM | _FPU_MASK_ZM | _FPU_MASK_OM
 105          | _FPU_MASK_UM | _FPU_MASK_PM);
 106
 107   if (options.fpe & GFC_FPE_INVALID) cw &= ~_FPU_MASK_IM;
 108   if (options.fpe & GFC_FPE_DENORMAL) cw &= ~_FPU_MASK_DM;
 109   if (options.fpe & GFC_FPE_ZERO) cw &= ~_FPU_MASK_ZM;
 110   if (options.fpe & GFC_FPE_OVERFLOW) cw &= ~_FPU_MASK_OM;
 111   if (options.fpe & GFC_FPE_UNDERFLOW) cw &= ~_FPU_MASK_UM;
 112   if (options.fpe & GFC_FPE_PRECISION) cw &= ~_FPU_MASK_PM;
 113
 114   asm volatile ("fldcw %0" : : "m" (cw));
 115
 116   if (has_sse())
 117     {
 118       unsigned int cw_sse;
 119
 120       asm volatile ("stmxcsr %0" : "=m" (cw_sse));
 121
 122       cw_sse &= 0xffff0000;
 123       cw_sse |= (_FPU_MASK_IM | _FPU_MASK_DM | _FPU_MASK_ZM | _FPU_MASK_OM
 124                  | _FPU_MASK_UM | _FPU_MASK_PM ) << 7;
 125
 126       if (options.fpe & GFC_FPE_INVALID) cw_sse &= ~(_FPU_MASK_IM << 7);
 127       if (options.fpe & GFC_FPE_DENORMAL) cw_sse &= ~(_FPU_MASK_DM << 7);
 128       if (options.fpe & GFC_FPE_ZERO) cw_sse &= ~(_FPU_MASK_ZM << 7);
 129       if (options.fpe & GFC_FPE_OVERFLOW) cw_sse &= ~(_FPU_MASK_OM << 7);
 130       if (options.fpe & GFC_FPE_UNDERFLOW) cw_sse &= ~(_FPU_MASK_UM << 7);
 131       if (options.fpe & GFC_FPE_PRECISION) cw_sse &= ~(_FPU_MASK_PM << 7);
 132
 133       asm volatile ("ldmxcsr %0" : : "m" (cw_sse));
 134     }
 135 }