1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "stringpool.h"
40 #include "diagnostic-core.h"
41 #include "insn-attr.h"
44 #include "fold-const.h"
46 #include "stor-layout.h"
48 #include "print-tree.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
57 #include "sched-int.h"
59 #include "gimple-fold.h"
60 #include "gimple-iterator.h"
61 #include "gimple-ssa.h"
62 #include "gimple-walk.h"
65 #include "tm-constrs.h"
66 #include "tree-vectorizer.h"
67 #include "target-globals.h"
70 #include "tree-pass.h"
73 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
76 #include "gstab.h" /* for N_SLINE */
78 #include "case-cfn-macros.h"
80 #include "tree-ssa-propagate.h"
82 /* This file should be included last. */
83 #include "target-def.h"
85 #ifndef TARGET_NO_PROTOTYPE
86 #define TARGET_NO_PROTOTYPE 0
89 #define min(A,B) ((A) < (B) ? (A) : (B))
90 #define max(A,B) ((A) > (B) ? (A) : (B))
92 /* Structure used to define the rs6000 stack */
93 typedef struct rs6000_stack
{
94 int reload_completed
; /* stack info won't change from here on */
95 int first_gp_reg_save
; /* first callee saved GP register used */
96 int first_fp_reg_save
; /* first callee saved FP register used */
97 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
98 int lr_save_p
; /* true if the link reg needs to be saved */
99 int cr_save_p
; /* true if the CR reg needs to be saved */
100 unsigned int vrsave_mask
; /* mask of vec registers to save */
101 int push_p
; /* true if we need to allocate stack space */
102 int calls_p
; /* true if the function makes any calls */
103 int world_save_p
; /* true if we're saving *everything*:
104 r13-r31, cr, f14-f31, vrsave, v20-v31 */
105 enum rs6000_abi abi
; /* which ABI to use */
106 int gp_save_offset
; /* offset to save GP regs from initial SP */
107 int fp_save_offset
; /* offset to save FP regs from initial SP */
108 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
109 int lr_save_offset
; /* offset to save LR from initial SP */
110 int cr_save_offset
; /* offset to save CR from initial SP */
111 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
112 int varargs_save_offset
; /* offset to save the varargs registers */
113 int ehrd_offset
; /* offset to EH return data */
114 int ehcr_offset
; /* offset to EH CR field data */
115 int reg_size
; /* register size (4 or 8) */
116 HOST_WIDE_INT vars_size
; /* variable save area size */
117 int parm_size
; /* outgoing parameter size */
118 int save_size
; /* save area size */
119 int fixed_size
; /* fixed size of stack frame */
120 int gp_size
; /* size of saved GP registers */
121 int fp_size
; /* size of saved FP registers */
122 int altivec_size
; /* size of saved AltiVec registers */
123 int cr_size
; /* size to hold CR if not in fixed area */
124 int vrsave_size
; /* size to hold VRSAVE */
125 int altivec_padding_size
; /* size of altivec alignment padding */
126 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
130 /* A C structure for machine-specific, per-function data.
131 This is added to the cfun structure. */
132 typedef struct GTY(()) machine_function
134 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
135 int ra_needs_full_frame
;
136 /* Flags if __builtin_return_address (0) was used. */
138 /* Cache lr_save_p after expansion of builtin_eh_return. */
140 /* Whether we need to save the TOC to the reserved stack location in the
141 function prologue. */
142 bool save_toc_in_prologue
;
143 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
144 varargs save area. */
145 HOST_WIDE_INT varargs_save_offset
;
146 /* Alternative internal arg pointer for -fsplit-stack. */
147 rtx split_stack_arg_pointer
;
148 bool split_stack_argp_used
;
149 /* Flag if r2 setup is needed with ELFv2 ABI. */
150 bool r2_setup_needed
;
151 /* The number of components we use for separate shrink-wrapping. */
153 /* The components already handled by separate shrink-wrapping, which should
154 not be considered by the prologue and epilogue. */
155 bool gpr_is_wrapped_separately
[32];
156 bool fpr_is_wrapped_separately
[32];
157 bool lr_is_wrapped_separately
;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load
;
163 /* Set to nonzero once AIX common-mode calls have been defined. */
164 static GTY(()) int common_mode_defined
;
166 /* Label number of label created for -mrelocatable, to call to so we can
167 get the address of the GOT section */
168 static int rs6000_pic_labelno
;
171 /* Counter for labels which are to be placed in .fixup. */
172 int fixuplabelno
= 0;
175 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
178 /* Specify the machine mode that pointers have. After generation of rtl, the
179 compiler makes no further distinction between pointers and any other objects
180 of this machine mode. The type is unsigned since not all things that
181 include rs6000.h also include machmode.h. */
182 unsigned rs6000_pmode
;
184 /* Width in bits of a pointer. */
185 unsigned rs6000_pointer_size
;
187 #ifdef HAVE_AS_GNU_ATTRIBUTE
188 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
189 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
191 /* Flag whether floating point values have been passed/returned.
192 Note that this doesn't say whether fprs are used, since the
193 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
194 should be set for soft-float values passed in gprs and ieee128
195 values passed in vsx registers. */
196 static bool rs6000_passes_float
;
197 static bool rs6000_passes_long_double
;
198 /* Flag whether vector values have been passed/returned. */
199 static bool rs6000_passes_vector
;
200 /* Flag whether small (<= 8 byte) structures have been returned. */
201 static bool rs6000_returns_struct
;
204 /* Value is TRUE if register/mode pair is acceptable. */
205 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
207 /* Maximum number of registers needed for a given register class and mode. */
208 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
210 /* How many registers are needed for a given register and mode. */
211 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
213 /* Map register number to register class. */
214 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
216 static int dbg_cost_ctrl
;
218 /* Built in types. */
219 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
220 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
222 /* Flag to say the TOC is initialized */
223 int toc_initialized
, need_toc_init
;
224 char toc_label_name
[10];
226 /* Cached value of rs6000_variable_issue. This is cached in
227 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
228 static short cached_can_issue_more
;
230 static GTY(()) section
*read_only_data_section
;
231 static GTY(()) section
*private_data_section
;
232 static GTY(()) section
*tls_data_section
;
233 static GTY(()) section
*tls_private_data_section
;
234 static GTY(()) section
*read_only_private_data_section
;
235 static GTY(()) section
*sdata2_section
;
236 static GTY(()) section
*toc_section
;
238 struct builtin_description
240 const HOST_WIDE_INT mask
;
241 const enum insn_code icode
;
242 const char *const name
;
243 const enum rs6000_builtins code
;
246 /* Describe the vector unit used for modes. */
247 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
248 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
250 /* Register classes for various constraints that are based on the target
252 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
254 /* Describe the alignment of a vector. */
255 int rs6000_vector_align
[NUM_MACHINE_MODES
];
257 /* Map selected modes to types for builtins. */
258 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
260 /* What modes to automatically generate reciprocal divide estimate (fre) and
261 reciprocal sqrt (frsqrte) for. */
262 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
264 /* Masks to determine which reciprocal esitmate instructions to generate
266 enum rs6000_recip_mask
{
267 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
268 RECIP_DF_DIV
= 0x002,
269 RECIP_V4SF_DIV
= 0x004,
270 RECIP_V2DF_DIV
= 0x008,
272 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
273 RECIP_DF_RSQRT
= 0x020,
274 RECIP_V4SF_RSQRT
= 0x040,
275 RECIP_V2DF_RSQRT
= 0x080,
277 /* Various combination of flags for -mrecip=xxx. */
279 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
280 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
281 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
283 RECIP_HIGH_PRECISION
= RECIP_ALL
,
285 /* On low precision machines like the power5, don't enable double precision
286 reciprocal square root estimate, since it isn't accurate enough. */
287 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
290 /* -mrecip options. */
293 const char *string
; /* option name */
294 unsigned int mask
; /* mask bits to set */
295 } recip_options
[] = {
296 { "all", RECIP_ALL
},
297 { "none", RECIP_NONE
},
298 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
300 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
301 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
302 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
303 | RECIP_V2DF_RSQRT
) },
304 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
305 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
308 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
314 { "power9", PPC_PLATFORM_POWER9
},
315 { "power8", PPC_PLATFORM_POWER8
},
316 { "power7", PPC_PLATFORM_POWER7
},
317 { "power6x", PPC_PLATFORM_POWER6X
},
318 { "power6", PPC_PLATFORM_POWER6
},
319 { "power5+", PPC_PLATFORM_POWER5_PLUS
},
320 { "power5", PPC_PLATFORM_POWER5
},
321 { "ppc970", PPC_PLATFORM_PPC970
},
322 { "power4", PPC_PLATFORM_POWER4
},
323 { "ppca2", PPC_PLATFORM_PPCA2
},
324 { "ppc476", PPC_PLATFORM_PPC476
},
325 { "ppc464", PPC_PLATFORM_PPC464
},
326 { "ppc440", PPC_PLATFORM_PPC440
},
327 { "ppc405", PPC_PLATFORM_PPC405
},
328 { "ppc-cell-be", PPC_PLATFORM_CELL_BE
}
331 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
337 } cpu_supports_info
[] = {
338 /* AT_HWCAP masks. */
339 { "4xxmac", PPC_FEATURE_HAS_4xxMAC
, 0 },
340 { "altivec", PPC_FEATURE_HAS_ALTIVEC
, 0 },
341 { "arch_2_05", PPC_FEATURE_ARCH_2_05
, 0 },
342 { "arch_2_06", PPC_FEATURE_ARCH_2_06
, 0 },
343 { "archpmu", PPC_FEATURE_PERFMON_COMPAT
, 0 },
344 { "booke", PPC_FEATURE_BOOKE
, 0 },
345 { "cellbe", PPC_FEATURE_CELL_BE
, 0 },
346 { "dfp", PPC_FEATURE_HAS_DFP
, 0 },
347 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE
, 0 },
348 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE
, 0 },
349 { "fpu", PPC_FEATURE_HAS_FPU
, 0 },
350 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP
, 0 },
351 { "mmu", PPC_FEATURE_HAS_MMU
, 0 },
352 { "notb", PPC_FEATURE_NO_TB
, 0 },
353 { "pa6t", PPC_FEATURE_PA6T
, 0 },
354 { "power4", PPC_FEATURE_POWER4
, 0 },
355 { "power5", PPC_FEATURE_POWER5
, 0 },
356 { "power5+", PPC_FEATURE_POWER5_PLUS
, 0 },
357 { "power6x", PPC_FEATURE_POWER6_EXT
, 0 },
358 { "ppc32", PPC_FEATURE_32
, 0 },
359 { "ppc601", PPC_FEATURE_601_INSTR
, 0 },
360 { "ppc64", PPC_FEATURE_64
, 0 },
361 { "ppcle", PPC_FEATURE_PPC_LE
, 0 },
362 { "smt", PPC_FEATURE_SMT
, 0 },
363 { "spe", PPC_FEATURE_HAS_SPE
, 0 },
364 { "true_le", PPC_FEATURE_TRUE_LE
, 0 },
365 { "ucache", PPC_FEATURE_UNIFIED_CACHE
, 0 },
366 { "vsx", PPC_FEATURE_HAS_VSX
, 0 },
368 /* AT_HWCAP2 masks. */
369 { "arch_2_07", PPC_FEATURE2_ARCH_2_07
, 1 },
370 { "dscr", PPC_FEATURE2_HAS_DSCR
, 1 },
371 { "ebb", PPC_FEATURE2_HAS_EBB
, 1 },
372 { "htm", PPC_FEATURE2_HAS_HTM
, 1 },
373 { "htm-nosc", PPC_FEATURE2_HTM_NOSC
, 1 },
374 { "isel", PPC_FEATURE2_HAS_ISEL
, 1 },
375 { "tar", PPC_FEATURE2_HAS_TAR
, 1 },
376 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO
, 1 },
377 { "arch_3_00", PPC_FEATURE2_ARCH_3_00
, 1 },
378 { "ieee128", PPC_FEATURE2_HAS_IEEE128
, 1 },
379 { "darn", PPC_FEATURE2_DARN
, 1 },
380 { "scv", PPC_FEATURE2_SCV
, 1 }
383 /* On PowerPC, we have a limited number of target clones that we care about
384 which means we can use an array to hold the options, rather than having more
385 elaborate data structures to identify each possible variation. Order the
386 clones from the default to the highest ISA. */
388 CLONE_DEFAULT
= 0, /* default clone. */
389 CLONE_ISA_2_05
, /* ISA 2.05 (power6). */
390 CLONE_ISA_2_06
, /* ISA 2.06 (power7). */
391 CLONE_ISA_2_07
, /* ISA 2.07 (power8). */
392 CLONE_ISA_3_00
, /* ISA 3.00 (power9). */
396 /* Map compiler ISA bits into HWCAP names. */
398 HOST_WIDE_INT isa_mask
; /* rs6000_isa mask */
399 const char *name
; /* name to use in __builtin_cpu_supports. */
402 static const struct clone_map rs6000_clone_map
[CLONE_MAX
] = {
403 { 0, "" }, /* Default options. */
404 { OPTION_MASK_CMPB
, "arch_2_05" }, /* ISA 2.05 (power6). */
405 { OPTION_MASK_POPCNTD
, "arch_2_06" }, /* ISA 2.06 (power7). */
406 { OPTION_MASK_P8_VECTOR
, "arch_2_07" }, /* ISA 2.07 (power8). */
407 { OPTION_MASK_P9_VECTOR
, "arch_3_00" }, /* ISA 3.00 (power9). */
411 /* Newer LIBCs explicitly export this symbol to declare that they provide
412 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
413 reference to this symbol whenever we expand a CPU builtin, so that
414 we never link against an old LIBC. */
415 const char *tcb_verification_symbol
= "__parse_hwcap_and_convert_at_platform";
417 /* True if we have expanded a CPU builtin. */
420 /* Pointer to function (in rs6000-c.c) that can define or undefine target
421 macros that have changed. Languages that don't support the preprocessor
422 don't link in rs6000-c.c, so we can't call it directly. */
423 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
425 /* Simplfy register classes into simpler classifications. We assume
426 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
427 check for standard register classes (gpr/floating/altivec/vsx) and
428 floating/vector classes (float/altivec/vsx). */
430 enum rs6000_reg_type
{
441 /* Map register class to register type. */
442 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
444 /* First/last register type for the 'normal' register types (i.e. general
445 purpose, floating point, altivec, and VSX registers). */
446 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
448 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
451 /* Register classes we care about in secondary reload or go if legitimate
452 address. We only need to worry about GPR, FPR, and Altivec registers here,
453 along an ANY field that is the OR of the 3 register classes. */
455 enum rs6000_reload_reg_type
{
456 RELOAD_REG_GPR
, /* General purpose registers. */
457 RELOAD_REG_FPR
, /* Traditional floating point regs. */
458 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
459 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
463 /* For setting up register classes, loop through the 3 register classes mapping
464 into real registers, and skip the ANY class, which is just an OR of the
466 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
467 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
469 /* Map reload register type to a register in the register class. */
470 struct reload_reg_map_type
{
471 const char *name
; /* Register class name. */
472 int reg
; /* Register in the register class. */
475 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
476 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
477 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
478 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
479 { "Any", -1 }, /* RELOAD_REG_ANY. */
482 /* Mask bits for each register class, indexed per mode. Historically the
483 compiler has been more restrictive which types can do PRE_MODIFY instead of
484 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
485 typedef unsigned char addr_mask_type
;
487 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
488 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
489 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
490 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
491 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
492 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
493 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
494 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
496 /* Register type masks based on the type, of valid addressing modes. */
497 struct rs6000_reg_addr
{
498 enum insn_code reload_load
; /* INSN to reload for loading. */
499 enum insn_code reload_store
; /* INSN to reload for storing. */
500 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
501 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
502 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
503 enum insn_code fusion_gpr_ld
; /* INSN for fusing gpr ADDIS/loads. */
504 /* INSNs for fusing addi with loads
505 or stores for each reg. class. */
506 enum insn_code fusion_addi_ld
[(int)N_RELOAD_REG
];
507 enum insn_code fusion_addi_st
[(int)N_RELOAD_REG
];
508 /* INSNs for fusing addis with loads
509 or stores for each reg. class. */
510 enum insn_code fusion_addis_ld
[(int)N_RELOAD_REG
];
511 enum insn_code fusion_addis_st
[(int)N_RELOAD_REG
];
512 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
513 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
514 bool fused_toc
; /* Mode supports TOC fusion. */
517 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
519 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
521 mode_supports_pre_incdec_p (machine_mode mode
)
523 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
527 /* Helper function to say whether a mode supports PRE_MODIFY. */
529 mode_supports_pre_modify_p (machine_mode mode
)
531 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
535 /* Given that there exists at least one variable that is set (produced)
536 by OUT_INSN and read (consumed) by IN_INSN, return true iff
537 IN_INSN represents one or more memory store operations and none of
538 the variables set by OUT_INSN is used by IN_INSN as the address of a
539 store operation. If either IN_INSN or OUT_INSN does not represent
540 a "single" RTL SET expression (as loosely defined by the
541 implementation of the single_set function) or a PARALLEL with only
542 SETs, CLOBBERs, and USEs inside, this function returns false.
544 This rs6000-specific version of store_data_bypass_p checks for
545 certain conditions that result in assertion failures (and internal
546 compiler errors) in the generic store_data_bypass_p function and
547 returns false rather than calling store_data_bypass_p if one of the
548 problematic conditions is detected. */
551 rs6000_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
558 in_set
= single_set (in_insn
);
561 if (MEM_P (SET_DEST (in_set
)))
563 out_set
= single_set (out_insn
);
566 out_pat
= PATTERN (out_insn
);
567 if (GET_CODE (out_pat
) == PARALLEL
)
569 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
571 out_exp
= XVECEXP (out_pat
, 0, i
);
572 if ((GET_CODE (out_exp
) == CLOBBER
)
573 || (GET_CODE (out_exp
) == USE
))
575 else if (GET_CODE (out_exp
) != SET
)
584 in_pat
= PATTERN (in_insn
);
585 if (GET_CODE (in_pat
) != PARALLEL
)
588 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
590 in_exp
= XVECEXP (in_pat
, 0, i
);
591 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
593 else if (GET_CODE (in_exp
) != SET
)
596 if (MEM_P (SET_DEST (in_exp
)))
598 out_set
= single_set (out_insn
);
601 out_pat
= PATTERN (out_insn
);
602 if (GET_CODE (out_pat
) != PARALLEL
)
604 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
606 out_exp
= XVECEXP (out_pat
, 0, j
);
607 if ((GET_CODE (out_exp
) == CLOBBER
)
608 || (GET_CODE (out_exp
) == USE
))
610 else if (GET_CODE (out_exp
) != SET
)
617 return store_data_bypass_p (out_insn
, in_insn
);
620 /* Return true if we have D-form addressing in altivec registers. */
622 mode_supports_vmx_dform (machine_mode mode
)
624 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_OFFSET
) != 0);
627 /* Return true if we have D-form addressing in VSX registers. This addressing
628 is more limited than normal d-form addressing in that the offset must be
629 aligned on a 16-byte boundary. */
631 mode_supports_vsx_dform_quad (machine_mode mode
)
633 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_QUAD_OFFSET
)
638 /* Target cpu costs. */
640 struct processor_costs
{
641 const int mulsi
; /* cost of SImode multiplication. */
642 const int mulsi_const
; /* cost of SImode multiplication by constant. */
643 const int mulsi_const9
; /* cost of SImode mult by short constant. */
644 const int muldi
; /* cost of DImode multiplication. */
645 const int divsi
; /* cost of SImode division. */
646 const int divdi
; /* cost of DImode division. */
647 const int fp
; /* cost of simple SFmode and DFmode insns. */
648 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
649 const int sdiv
; /* cost of SFmode division (fdivs). */
650 const int ddiv
; /* cost of DFmode division (fdiv). */
651 const int cache_line_size
; /* cache line size in bytes. */
652 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
653 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
654 const int simultaneous_prefetches
; /* number of parallel prefetch
656 const int sfdf_convert
; /* cost of SF->DF conversion. */
659 const struct processor_costs
*rs6000_cost
;
661 /* Processor costs (relative to an add) */
663 /* Instruction size costs on 32bit processors. */
665 struct processor_costs size32_cost
= {
666 COSTS_N_INSNS (1), /* mulsi */
667 COSTS_N_INSNS (1), /* mulsi_const */
668 COSTS_N_INSNS (1), /* mulsi_const9 */
669 COSTS_N_INSNS (1), /* muldi */
670 COSTS_N_INSNS (1), /* divsi */
671 COSTS_N_INSNS (1), /* divdi */
672 COSTS_N_INSNS (1), /* fp */
673 COSTS_N_INSNS (1), /* dmul */
674 COSTS_N_INSNS (1), /* sdiv */
675 COSTS_N_INSNS (1), /* ddiv */
676 32, /* cache line size */
680 0, /* SF->DF convert */
683 /* Instruction size costs on 64bit processors. */
685 struct processor_costs size64_cost
= {
686 COSTS_N_INSNS (1), /* mulsi */
687 COSTS_N_INSNS (1), /* mulsi_const */
688 COSTS_N_INSNS (1), /* mulsi_const9 */
689 COSTS_N_INSNS (1), /* muldi */
690 COSTS_N_INSNS (1), /* divsi */
691 COSTS_N_INSNS (1), /* divdi */
692 COSTS_N_INSNS (1), /* fp */
693 COSTS_N_INSNS (1), /* dmul */
694 COSTS_N_INSNS (1), /* sdiv */
695 COSTS_N_INSNS (1), /* ddiv */
696 128, /* cache line size */
700 0, /* SF->DF convert */
703 /* Instruction costs on RS64A processors. */
705 struct processor_costs rs64a_cost
= {
706 COSTS_N_INSNS (20), /* mulsi */
707 COSTS_N_INSNS (12), /* mulsi_const */
708 COSTS_N_INSNS (8), /* mulsi_const9 */
709 COSTS_N_INSNS (34), /* muldi */
710 COSTS_N_INSNS (65), /* divsi */
711 COSTS_N_INSNS (67), /* divdi */
712 COSTS_N_INSNS (4), /* fp */
713 COSTS_N_INSNS (4), /* dmul */
714 COSTS_N_INSNS (31), /* sdiv */
715 COSTS_N_INSNS (31), /* ddiv */
716 128, /* cache line size */
720 0, /* SF->DF convert */
723 /* Instruction costs on MPCCORE processors. */
725 struct processor_costs mpccore_cost
= {
726 COSTS_N_INSNS (2), /* mulsi */
727 COSTS_N_INSNS (2), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (2), /* muldi */
730 COSTS_N_INSNS (6), /* divsi */
731 COSTS_N_INSNS (6), /* divdi */
732 COSTS_N_INSNS (4), /* fp */
733 COSTS_N_INSNS (5), /* dmul */
734 COSTS_N_INSNS (10), /* sdiv */
735 COSTS_N_INSNS (17), /* ddiv */
736 32, /* cache line size */
740 0, /* SF->DF convert */
743 /* Instruction costs on PPC403 processors. */
745 struct processor_costs ppc403_cost
= {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (4), /* mulsi_const */
748 COSTS_N_INSNS (4), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (33), /* divsi */
751 COSTS_N_INSNS (33), /* divdi */
752 COSTS_N_INSNS (11), /* fp */
753 COSTS_N_INSNS (11), /* dmul */
754 COSTS_N_INSNS (11), /* sdiv */
755 COSTS_N_INSNS (11), /* ddiv */
756 32, /* cache line size */
760 0, /* SF->DF convert */
763 /* Instruction costs on PPC405 processors. */
765 struct processor_costs ppc405_cost
= {
766 COSTS_N_INSNS (5), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (3), /* mulsi_const9 */
769 COSTS_N_INSNS (5), /* muldi */
770 COSTS_N_INSNS (35), /* divsi */
771 COSTS_N_INSNS (35), /* divdi */
772 COSTS_N_INSNS (11), /* fp */
773 COSTS_N_INSNS (11), /* dmul */
774 COSTS_N_INSNS (11), /* sdiv */
775 COSTS_N_INSNS (11), /* ddiv */
776 32, /* cache line size */
780 0, /* SF->DF convert */
783 /* Instruction costs on PPC440 processors. */
785 struct processor_costs ppc440_cost
= {
786 COSTS_N_INSNS (3), /* mulsi */
787 COSTS_N_INSNS (2), /* mulsi_const */
788 COSTS_N_INSNS (2), /* mulsi_const9 */
789 COSTS_N_INSNS (3), /* muldi */
790 COSTS_N_INSNS (34), /* divsi */
791 COSTS_N_INSNS (34), /* divdi */
792 COSTS_N_INSNS (5), /* fp */
793 COSTS_N_INSNS (5), /* dmul */
794 COSTS_N_INSNS (19), /* sdiv */
795 COSTS_N_INSNS (33), /* ddiv */
796 32, /* cache line size */
800 0, /* SF->DF convert */
803 /* Instruction costs on PPC476 processors. */
805 struct processor_costs ppc476_cost
= {
806 COSTS_N_INSNS (4), /* mulsi */
807 COSTS_N_INSNS (4), /* mulsi_const */
808 COSTS_N_INSNS (4), /* mulsi_const9 */
809 COSTS_N_INSNS (4), /* muldi */
810 COSTS_N_INSNS (11), /* divsi */
811 COSTS_N_INSNS (11), /* divdi */
812 COSTS_N_INSNS (6), /* fp */
813 COSTS_N_INSNS (6), /* dmul */
814 COSTS_N_INSNS (19), /* sdiv */
815 COSTS_N_INSNS (33), /* ddiv */
816 32, /* l1 cache line size */
820 0, /* SF->DF convert */
823 /* Instruction costs on PPC601 processors. */
825 struct processor_costs ppc601_cost
= {
826 COSTS_N_INSNS (5), /* mulsi */
827 COSTS_N_INSNS (5), /* mulsi_const */
828 COSTS_N_INSNS (5), /* mulsi_const9 */
829 COSTS_N_INSNS (5), /* muldi */
830 COSTS_N_INSNS (36), /* divsi */
831 COSTS_N_INSNS (36), /* divdi */
832 COSTS_N_INSNS (4), /* fp */
833 COSTS_N_INSNS (5), /* dmul */
834 COSTS_N_INSNS (17), /* sdiv */
835 COSTS_N_INSNS (31), /* ddiv */
836 32, /* cache line size */
840 0, /* SF->DF convert */
843 /* Instruction costs on PPC603 processors. */
845 struct processor_costs ppc603_cost
= {
846 COSTS_N_INSNS (5), /* mulsi */
847 COSTS_N_INSNS (3), /* mulsi_const */
848 COSTS_N_INSNS (2), /* mulsi_const9 */
849 COSTS_N_INSNS (5), /* muldi */
850 COSTS_N_INSNS (37), /* divsi */
851 COSTS_N_INSNS (37), /* divdi */
852 COSTS_N_INSNS (3), /* fp */
853 COSTS_N_INSNS (4), /* dmul */
854 COSTS_N_INSNS (18), /* sdiv */
855 COSTS_N_INSNS (33), /* ddiv */
856 32, /* cache line size */
860 0, /* SF->DF convert */
863 /* Instruction costs on PPC604 processors. */
865 struct processor_costs ppc604_cost
= {
866 COSTS_N_INSNS (4), /* mulsi */
867 COSTS_N_INSNS (4), /* mulsi_const */
868 COSTS_N_INSNS (4), /* mulsi_const9 */
869 COSTS_N_INSNS (4), /* muldi */
870 COSTS_N_INSNS (20), /* divsi */
871 COSTS_N_INSNS (20), /* divdi */
872 COSTS_N_INSNS (3), /* fp */
873 COSTS_N_INSNS (3), /* dmul */
874 COSTS_N_INSNS (18), /* sdiv */
875 COSTS_N_INSNS (32), /* ddiv */
876 32, /* cache line size */
880 0, /* SF->DF convert */
883 /* Instruction costs on PPC604e processors. */
885 struct processor_costs ppc604e_cost
= {
886 COSTS_N_INSNS (2), /* mulsi */
887 COSTS_N_INSNS (2), /* mulsi_const */
888 COSTS_N_INSNS (2), /* mulsi_const9 */
889 COSTS_N_INSNS (2), /* muldi */
890 COSTS_N_INSNS (20), /* divsi */
891 COSTS_N_INSNS (20), /* divdi */
892 COSTS_N_INSNS (3), /* fp */
893 COSTS_N_INSNS (3), /* dmul */
894 COSTS_N_INSNS (18), /* sdiv */
895 COSTS_N_INSNS (32), /* ddiv */
896 32, /* cache line size */
900 0, /* SF->DF convert */
903 /* Instruction costs on PPC620 processors. */
905 struct processor_costs ppc620_cost
= {
906 COSTS_N_INSNS (5), /* mulsi */
907 COSTS_N_INSNS (4), /* mulsi_const */
908 COSTS_N_INSNS (3), /* mulsi_const9 */
909 COSTS_N_INSNS (7), /* muldi */
910 COSTS_N_INSNS (21), /* divsi */
911 COSTS_N_INSNS (37), /* divdi */
912 COSTS_N_INSNS (3), /* fp */
913 COSTS_N_INSNS (3), /* dmul */
914 COSTS_N_INSNS (18), /* sdiv */
915 COSTS_N_INSNS (32), /* ddiv */
916 128, /* cache line size */
920 0, /* SF->DF convert */
923 /* Instruction costs on PPC630 processors. */
925 struct processor_costs ppc630_cost
= {
926 COSTS_N_INSNS (5), /* mulsi */
927 COSTS_N_INSNS (4), /* mulsi_const */
928 COSTS_N_INSNS (3), /* mulsi_const9 */
929 COSTS_N_INSNS (7), /* muldi */
930 COSTS_N_INSNS (21), /* divsi */
931 COSTS_N_INSNS (37), /* divdi */
932 COSTS_N_INSNS (3), /* fp */
933 COSTS_N_INSNS (3), /* dmul */
934 COSTS_N_INSNS (17), /* sdiv */
935 COSTS_N_INSNS (21), /* ddiv */
936 128, /* cache line size */
940 0, /* SF->DF convert */
943 /* Instruction costs on Cell processor. */
944 /* COSTS_N_INSNS (1) ~ one add. */
946 struct processor_costs ppccell_cost
= {
947 COSTS_N_INSNS (9/2)+2, /* mulsi */
948 COSTS_N_INSNS (6/2), /* mulsi_const */
949 COSTS_N_INSNS (6/2), /* mulsi_const9 */
950 COSTS_N_INSNS (15/2)+2, /* muldi */
951 COSTS_N_INSNS (38/2), /* divsi */
952 COSTS_N_INSNS (70/2), /* divdi */
953 COSTS_N_INSNS (10/2), /* fp */
954 COSTS_N_INSNS (10/2), /* dmul */
955 COSTS_N_INSNS (74/2), /* sdiv */
956 COSTS_N_INSNS (74/2), /* ddiv */
957 128, /* cache line size */
961 0, /* SF->DF convert */
964 /* Instruction costs on PPC750 and PPC7400 processors. */
966 struct processor_costs ppc750_cost
= {
967 COSTS_N_INSNS (5), /* mulsi */
968 COSTS_N_INSNS (3), /* mulsi_const */
969 COSTS_N_INSNS (2), /* mulsi_const9 */
970 COSTS_N_INSNS (5), /* muldi */
971 COSTS_N_INSNS (17), /* divsi */
972 COSTS_N_INSNS (17), /* divdi */
973 COSTS_N_INSNS (3), /* fp */
974 COSTS_N_INSNS (3), /* dmul */
975 COSTS_N_INSNS (17), /* sdiv */
976 COSTS_N_INSNS (31), /* ddiv */
977 32, /* cache line size */
981 0, /* SF->DF convert */
984 /* Instruction costs on PPC7450 processors. */
986 struct processor_costs ppc7450_cost
= {
987 COSTS_N_INSNS (4), /* mulsi */
988 COSTS_N_INSNS (3), /* mulsi_const */
989 COSTS_N_INSNS (3), /* mulsi_const9 */
990 COSTS_N_INSNS (4), /* muldi */
991 COSTS_N_INSNS (23), /* divsi */
992 COSTS_N_INSNS (23), /* divdi */
993 COSTS_N_INSNS (5), /* fp */
994 COSTS_N_INSNS (5), /* dmul */
995 COSTS_N_INSNS (21), /* sdiv */
996 COSTS_N_INSNS (35), /* ddiv */
997 32, /* cache line size */
1001 0, /* SF->DF convert */
1004 /* Instruction costs on PPC8540 processors. */
1006 struct processor_costs ppc8540_cost
= {
1007 COSTS_N_INSNS (4), /* mulsi */
1008 COSTS_N_INSNS (4), /* mulsi_const */
1009 COSTS_N_INSNS (4), /* mulsi_const9 */
1010 COSTS_N_INSNS (4), /* muldi */
1011 COSTS_N_INSNS (19), /* divsi */
1012 COSTS_N_INSNS (19), /* divdi */
1013 COSTS_N_INSNS (4), /* fp */
1014 COSTS_N_INSNS (4), /* dmul */
1015 COSTS_N_INSNS (29), /* sdiv */
1016 COSTS_N_INSNS (29), /* ddiv */
1017 32, /* cache line size */
1020 1, /* prefetch streams /*/
1021 0, /* SF->DF convert */
1024 /* Instruction costs on E300C2 and E300C3 cores. */
1026 struct processor_costs ppce300c2c3_cost
= {
1027 COSTS_N_INSNS (4), /* mulsi */
1028 COSTS_N_INSNS (4), /* mulsi_const */
1029 COSTS_N_INSNS (4), /* mulsi_const9 */
1030 COSTS_N_INSNS (4), /* muldi */
1031 COSTS_N_INSNS (19), /* divsi */
1032 COSTS_N_INSNS (19), /* divdi */
1033 COSTS_N_INSNS (3), /* fp */
1034 COSTS_N_INSNS (4), /* dmul */
1035 COSTS_N_INSNS (18), /* sdiv */
1036 COSTS_N_INSNS (33), /* ddiv */
1040 1, /* prefetch streams /*/
1041 0, /* SF->DF convert */
1044 /* Instruction costs on PPCE500MC processors. */
1046 struct processor_costs ppce500mc_cost
= {
1047 COSTS_N_INSNS (4), /* mulsi */
1048 COSTS_N_INSNS (4), /* mulsi_const */
1049 COSTS_N_INSNS (4), /* mulsi_const9 */
1050 COSTS_N_INSNS (4), /* muldi */
1051 COSTS_N_INSNS (14), /* divsi */
1052 COSTS_N_INSNS (14), /* divdi */
1053 COSTS_N_INSNS (8), /* fp */
1054 COSTS_N_INSNS (10), /* dmul */
1055 COSTS_N_INSNS (36), /* sdiv */
1056 COSTS_N_INSNS (66), /* ddiv */
1057 64, /* cache line size */
1060 1, /* prefetch streams /*/
1061 0, /* SF->DF convert */
1064 /* Instruction costs on PPCE500MC64 processors. */
1066 struct processor_costs ppce500mc64_cost
= {
1067 COSTS_N_INSNS (4), /* mulsi */
1068 COSTS_N_INSNS (4), /* mulsi_const */
1069 COSTS_N_INSNS (4), /* mulsi_const9 */
1070 COSTS_N_INSNS (4), /* muldi */
1071 COSTS_N_INSNS (14), /* divsi */
1072 COSTS_N_INSNS (14), /* divdi */
1073 COSTS_N_INSNS (4), /* fp */
1074 COSTS_N_INSNS (10), /* dmul */
1075 COSTS_N_INSNS (36), /* sdiv */
1076 COSTS_N_INSNS (66), /* ddiv */
1077 64, /* cache line size */
1080 1, /* prefetch streams /*/
1081 0, /* SF->DF convert */
1084 /* Instruction costs on PPCE5500 processors. */
1086 struct processor_costs ppce5500_cost
= {
1087 COSTS_N_INSNS (5), /* mulsi */
1088 COSTS_N_INSNS (5), /* mulsi_const */
1089 COSTS_N_INSNS (4), /* mulsi_const9 */
1090 COSTS_N_INSNS (5), /* muldi */
1091 COSTS_N_INSNS (14), /* divsi */
1092 COSTS_N_INSNS (14), /* divdi */
1093 COSTS_N_INSNS (7), /* fp */
1094 COSTS_N_INSNS (10), /* dmul */
1095 COSTS_N_INSNS (36), /* sdiv */
1096 COSTS_N_INSNS (66), /* ddiv */
1097 64, /* cache line size */
1100 1, /* prefetch streams /*/
1101 0, /* SF->DF convert */
1104 /* Instruction costs on PPCE6500 processors. */
1106 struct processor_costs ppce6500_cost
= {
1107 COSTS_N_INSNS (5), /* mulsi */
1108 COSTS_N_INSNS (5), /* mulsi_const */
1109 COSTS_N_INSNS (4), /* mulsi_const9 */
1110 COSTS_N_INSNS (5), /* muldi */
1111 COSTS_N_INSNS (14), /* divsi */
1112 COSTS_N_INSNS (14), /* divdi */
1113 COSTS_N_INSNS (7), /* fp */
1114 COSTS_N_INSNS (10), /* dmul */
1115 COSTS_N_INSNS (36), /* sdiv */
1116 COSTS_N_INSNS (66), /* ddiv */
1117 64, /* cache line size */
1120 1, /* prefetch streams /*/
1121 0, /* SF->DF convert */
1124 /* Instruction costs on AppliedMicro Titan processors. */
1126 struct processor_costs titan_cost
= {
1127 COSTS_N_INSNS (5), /* mulsi */
1128 COSTS_N_INSNS (5), /* mulsi_const */
1129 COSTS_N_INSNS (5), /* mulsi_const9 */
1130 COSTS_N_INSNS (5), /* muldi */
1131 COSTS_N_INSNS (18), /* divsi */
1132 COSTS_N_INSNS (18), /* divdi */
1133 COSTS_N_INSNS (10), /* fp */
1134 COSTS_N_INSNS (10), /* dmul */
1135 COSTS_N_INSNS (46), /* sdiv */
1136 COSTS_N_INSNS (72), /* ddiv */
1137 32, /* cache line size */
1140 1, /* prefetch streams /*/
1141 0, /* SF->DF convert */
1144 /* Instruction costs on POWER4 and POWER5 processors. */
1146 struct processor_costs power4_cost
= {
1147 COSTS_N_INSNS (3), /* mulsi */
1148 COSTS_N_INSNS (2), /* mulsi_const */
1149 COSTS_N_INSNS (2), /* mulsi_const9 */
1150 COSTS_N_INSNS (4), /* muldi */
1151 COSTS_N_INSNS (18), /* divsi */
1152 COSTS_N_INSNS (34), /* divdi */
1153 COSTS_N_INSNS (3), /* fp */
1154 COSTS_N_INSNS (3), /* dmul */
1155 COSTS_N_INSNS (17), /* sdiv */
1156 COSTS_N_INSNS (17), /* ddiv */
1157 128, /* cache line size */
1159 1024, /* l2 cache */
1160 8, /* prefetch streams /*/
1161 0, /* SF->DF convert */
1164 /* Instruction costs on POWER6 processors. */
1166 struct processor_costs power6_cost
= {
1167 COSTS_N_INSNS (8), /* mulsi */
1168 COSTS_N_INSNS (8), /* mulsi_const */
1169 COSTS_N_INSNS (8), /* mulsi_const9 */
1170 COSTS_N_INSNS (8), /* muldi */
1171 COSTS_N_INSNS (22), /* divsi */
1172 COSTS_N_INSNS (28), /* divdi */
1173 COSTS_N_INSNS (3), /* fp */
1174 COSTS_N_INSNS (3), /* dmul */
1175 COSTS_N_INSNS (13), /* sdiv */
1176 COSTS_N_INSNS (16), /* ddiv */
1177 128, /* cache line size */
1179 2048, /* l2 cache */
1180 16, /* prefetch streams */
1181 0, /* SF->DF convert */
1184 /* Instruction costs on POWER7 processors. */
1186 struct processor_costs power7_cost
= {
1187 COSTS_N_INSNS (2), /* mulsi */
1188 COSTS_N_INSNS (2), /* mulsi_const */
1189 COSTS_N_INSNS (2), /* mulsi_const9 */
1190 COSTS_N_INSNS (2), /* muldi */
1191 COSTS_N_INSNS (18), /* divsi */
1192 COSTS_N_INSNS (34), /* divdi */
1193 COSTS_N_INSNS (3), /* fp */
1194 COSTS_N_INSNS (3), /* dmul */
1195 COSTS_N_INSNS (13), /* sdiv */
1196 COSTS_N_INSNS (16), /* ddiv */
1197 128, /* cache line size */
1200 12, /* prefetch streams */
1201 COSTS_N_INSNS (3), /* SF->DF convert */
1204 /* Instruction costs on POWER8 processors. */
1206 struct processor_costs power8_cost
= {
1207 COSTS_N_INSNS (3), /* mulsi */
1208 COSTS_N_INSNS (3), /* mulsi_const */
1209 COSTS_N_INSNS (3), /* mulsi_const9 */
1210 COSTS_N_INSNS (3), /* muldi */
1211 COSTS_N_INSNS (19), /* divsi */
1212 COSTS_N_INSNS (35), /* divdi */
1213 COSTS_N_INSNS (3), /* fp */
1214 COSTS_N_INSNS (3), /* dmul */
1215 COSTS_N_INSNS (14), /* sdiv */
1216 COSTS_N_INSNS (17), /* ddiv */
1217 128, /* cache line size */
1220 12, /* prefetch streams */
1221 COSTS_N_INSNS (3), /* SF->DF convert */
1224 /* Instruction costs on POWER9 processors. */
1226 struct processor_costs power9_cost
= {
1227 COSTS_N_INSNS (3), /* mulsi */
1228 COSTS_N_INSNS (3), /* mulsi_const */
1229 COSTS_N_INSNS (3), /* mulsi_const9 */
1230 COSTS_N_INSNS (3), /* muldi */
1231 COSTS_N_INSNS (8), /* divsi */
1232 COSTS_N_INSNS (12), /* divdi */
1233 COSTS_N_INSNS (3), /* fp */
1234 COSTS_N_INSNS (3), /* dmul */
1235 COSTS_N_INSNS (13), /* sdiv */
1236 COSTS_N_INSNS (18), /* ddiv */
1237 128, /* cache line size */
1240 8, /* prefetch streams */
1241 COSTS_N_INSNS (3), /* SF->DF convert */
1244 /* Instruction costs on POWER A2 processors. */
1246 struct processor_costs ppca2_cost
= {
1247 COSTS_N_INSNS (16), /* mulsi */
1248 COSTS_N_INSNS (16), /* mulsi_const */
1249 COSTS_N_INSNS (16), /* mulsi_const9 */
1250 COSTS_N_INSNS (16), /* muldi */
1251 COSTS_N_INSNS (22), /* divsi */
1252 COSTS_N_INSNS (28), /* divdi */
1253 COSTS_N_INSNS (3), /* fp */
1254 COSTS_N_INSNS (3), /* dmul */
1255 COSTS_N_INSNS (59), /* sdiv */
1256 COSTS_N_INSNS (72), /* ddiv */
1259 2048, /* l2 cache */
1260 16, /* prefetch streams */
1261 0, /* SF->DF convert */
1265 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1266 #undef RS6000_BUILTIN_0
1267 #undef RS6000_BUILTIN_1
1268 #undef RS6000_BUILTIN_2
1269 #undef RS6000_BUILTIN_3
1270 #undef RS6000_BUILTIN_A
1271 #undef RS6000_BUILTIN_D
1272 #undef RS6000_BUILTIN_H
1273 #undef RS6000_BUILTIN_P
1274 #undef RS6000_BUILTIN_Q
1275 #undef RS6000_BUILTIN_X
1277 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1278 { NAME, ICODE, MASK, ATTR },
1280 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1281 { NAME, ICODE, MASK, ATTR },
1283 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1284 { NAME, ICODE, MASK, ATTR },
1286 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1287 { NAME, ICODE, MASK, ATTR },
1289 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1290 { NAME, ICODE, MASK, ATTR },
1292 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1293 { NAME, ICODE, MASK, ATTR },
1295 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1296 { NAME, ICODE, MASK, ATTR },
1298 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1299 { NAME, ICODE, MASK, ATTR },
1301 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1302 { NAME, ICODE, MASK, ATTR },
1304 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1305 { NAME, ICODE, MASK, ATTR },
1307 struct rs6000_builtin_info_type
{
1309 const enum insn_code icode
;
1310 const HOST_WIDE_INT mask
;
1311 const unsigned attr
;
1314 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1316 #include "rs6000-builtin.def"
1319 #undef RS6000_BUILTIN_0
1320 #undef RS6000_BUILTIN_1
1321 #undef RS6000_BUILTIN_2
1322 #undef RS6000_BUILTIN_3
1323 #undef RS6000_BUILTIN_A
1324 #undef RS6000_BUILTIN_D
1325 #undef RS6000_BUILTIN_H
1326 #undef RS6000_BUILTIN_P
1327 #undef RS6000_BUILTIN_Q
1328 #undef RS6000_BUILTIN_X
1330 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1331 static tree (*rs6000_veclib_handler
) (combined_fn
, tree
, tree
);
1334 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1335 static struct machine_function
* rs6000_init_machine_status (void);
1336 static int rs6000_ra_ever_killed (void);
1337 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1338 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1339 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1340 static tree
rs6000_builtin_vectorized_libmass (combined_fn
, tree
, tree
);
1341 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1342 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1343 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1344 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1346 static int rs6000_debug_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
1348 static bool is_microcoded_insn (rtx_insn
*);
1349 static bool is_nonpipeline_insn (rtx_insn
*);
1350 static bool is_cracked_insn (rtx_insn
*);
1351 static bool is_load_insn (rtx
, rtx
*);
1352 static bool is_store_insn (rtx
, rtx
*);
1353 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1354 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1355 static bool insn_must_be_first_in_group (rtx_insn
*);
1356 static bool insn_must_be_last_in_group (rtx_insn
*);
1357 static void altivec_init_builtins (void);
1358 static tree
builtin_function_type (machine_mode
, machine_mode
,
1359 machine_mode
, machine_mode
,
1360 enum rs6000_builtins
, const char *name
);
1361 static void rs6000_common_init_builtins (void);
1362 static void paired_init_builtins (void);
1363 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1364 static void htm_init_builtins (void);
1365 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1366 static rs6000_stack_t
*rs6000_stack_info (void);
1367 static void is_altivec_return_reg (rtx
, void *);
1368 int easy_vector_constant (rtx
, machine_mode
);
1369 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1370 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1371 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1374 static void macho_branch_islands (void);
1376 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1378 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1380 static bool rs6000_mode_dependent_address (const_rtx
);
1381 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1382 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1384 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1387 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1388 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1390 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1392 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1395 static bool rs6000_cannot_change_mode_class (machine_mode
,
1398 static bool rs6000_debug_cannot_change_mode_class (machine_mode
,
1401 static bool rs6000_save_toc_in_prologue_p (void);
1402 static rtx
rs6000_internal_arg_pointer (void);
1404 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1406 = rs6000_legitimize_reload_address
;
1408 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1409 = rs6000_mode_dependent_address
;
1411 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1413 = rs6000_secondary_reload_class
;
1415 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1416 = rs6000_preferred_reload_class
;
1418 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1420 = rs6000_secondary_memory_needed
;
1422 bool (*rs6000_cannot_change_mode_class_ptr
) (machine_mode
,
1425 = rs6000_cannot_change_mode_class
;
1427 const int INSN_NOT_AVAILABLE
= -1;
1429 static void rs6000_print_isa_options (FILE *, int, const char *,
1431 static void rs6000_print_builtin_options (FILE *, int, const char *,
1433 static HOST_WIDE_INT
rs6000_disable_incompatible_switches (void);
1435 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1436 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1437 enum rs6000_reg_type
,
1439 secondary_reload_info
*,
1441 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1442 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused
));
1443 static tree
rs6000_fold_builtin (tree
, int, tree
*, bool);
1445 /* Hash table stuff for keeping track of TOC entries. */
1447 struct GTY((for_user
)) toc_hash_struct
1449 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1450 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1452 machine_mode key_mode
;
1456 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1458 static hashval_t
hash (toc_hash_struct
*);
1459 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1462 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1464 /* Hash table to keep track of the argument types for builtin functions. */
1466 struct GTY((for_user
)) builtin_hash_struct
1469 machine_mode mode
[4]; /* return value + 3 arguments. */
1470 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1473 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1475 static hashval_t
hash (builtin_hash_struct
*);
1476 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1479 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1482 /* Default register names. */
1483 char rs6000_reg_names
[][8] =
1485 "0", "1", "2", "3", "4", "5", "6", "7",
1486 "8", "9", "10", "11", "12", "13", "14", "15",
1487 "16", "17", "18", "19", "20", "21", "22", "23",
1488 "24", "25", "26", "27", "28", "29", "30", "31",
1489 "0", "1", "2", "3", "4", "5", "6", "7",
1490 "8", "9", "10", "11", "12", "13", "14", "15",
1491 "16", "17", "18", "19", "20", "21", "22", "23",
1492 "24", "25", "26", "27", "28", "29", "30", "31",
1493 "mq", "lr", "ctr","ap",
1494 "0", "1", "2", "3", "4", "5", "6", "7",
1496 /* AltiVec registers. */
1497 "0", "1", "2", "3", "4", "5", "6", "7",
1498 "8", "9", "10", "11", "12", "13", "14", "15",
1499 "16", "17", "18", "19", "20", "21", "22", "23",
1500 "24", "25", "26", "27", "28", "29", "30", "31",
1502 /* Soft frame pointer. */
1504 /* HTM SPR registers. */
1505 "tfhar", "tfiar", "texasr"
1508 #ifdef TARGET_REGNAMES
1509 static const char alt_reg_names
[][8] =
1511 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1512 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1513 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1514 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1515 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1516 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1517 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1518 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1519 "mq", "lr", "ctr", "ap",
1520 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1522 /* AltiVec registers. */
1523 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1524 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1525 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1526 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1528 /* Soft frame pointer. */
1530 /* HTM SPR registers. */
1531 "tfhar", "tfiar", "texasr"
1535 /* Table of valid machine attributes. */
1537 static const struct attribute_spec rs6000_attribute_table
[] =
1539 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1540 affects_type_identity } */
1541 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1543 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1545 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1547 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1549 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1551 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1552 SUBTARGET_ATTRIBUTE_TABLE
,
1554 { NULL
, 0, 0, false, false, false, NULL
, false }
1557 #ifndef TARGET_PROFILE_KERNEL
1558 #define TARGET_PROFILE_KERNEL 0
1561 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1562 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1564 /* Initialize the GCC target structure. */
1565 #undef TARGET_ATTRIBUTE_TABLE
1566 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1567 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1568 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1569 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1570 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1572 #undef TARGET_ASM_ALIGNED_DI_OP
1573 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1575 /* Default unaligned ops are only provided for ELF. Find the ops needed
1576 for non-ELF systems. */
1577 #ifndef OBJECT_FORMAT_ELF
1579 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1581 #undef TARGET_ASM_UNALIGNED_HI_OP
1582 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1583 #undef TARGET_ASM_UNALIGNED_SI_OP
1584 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1585 #undef TARGET_ASM_UNALIGNED_DI_OP
1586 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1589 #undef TARGET_ASM_UNALIGNED_HI_OP
1590 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1591 #undef TARGET_ASM_UNALIGNED_SI_OP
1592 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1593 #undef TARGET_ASM_UNALIGNED_DI_OP
1594 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1595 #undef TARGET_ASM_ALIGNED_DI_OP
1596 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1600 /* This hook deals with fixups for relocatable code and DI-mode objects
1602 #undef TARGET_ASM_INTEGER
1603 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1605 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1606 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1607 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1610 #undef TARGET_SET_UP_BY_PROLOGUE
1611 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1613 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1614 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1615 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1616 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1617 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1618 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1619 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1620 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1621 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1622 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1623 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1624 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1626 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1627 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1629 #undef TARGET_INTERNAL_ARG_POINTER
1630 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1632 #undef TARGET_HAVE_TLS
1633 #define TARGET_HAVE_TLS HAVE_AS_TLS
1635 #undef TARGET_CANNOT_FORCE_CONST_MEM
1636 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1638 #undef TARGET_DELEGITIMIZE_ADDRESS
1639 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1641 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1642 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1644 #undef TARGET_LEGITIMATE_COMBINED_INSN
1645 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1647 #undef TARGET_ASM_FUNCTION_PROLOGUE
1648 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1649 #undef TARGET_ASM_FUNCTION_EPILOGUE
1650 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1652 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1653 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1655 #undef TARGET_LEGITIMIZE_ADDRESS
1656 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1658 #undef TARGET_SCHED_VARIABLE_ISSUE
1659 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1661 #undef TARGET_SCHED_ISSUE_RATE
1662 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1663 #undef TARGET_SCHED_ADJUST_COST
1664 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1665 #undef TARGET_SCHED_ADJUST_PRIORITY
1666 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1667 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1668 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1669 #undef TARGET_SCHED_INIT
1670 #define TARGET_SCHED_INIT rs6000_sched_init
1671 #undef TARGET_SCHED_FINISH
1672 #define TARGET_SCHED_FINISH rs6000_sched_finish
1673 #undef TARGET_SCHED_REORDER
1674 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1675 #undef TARGET_SCHED_REORDER2
1676 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1678 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1679 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1681 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1682 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1684 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1685 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1686 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1687 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1688 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1689 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1690 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1691 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1693 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1694 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1696 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1697 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1698 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1699 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1700 rs6000_builtin_support_vector_misalignment
1701 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1702 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1703 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1704 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1705 rs6000_builtin_vectorization_cost
1706 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1707 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1708 rs6000_preferred_simd_mode
1709 #undef TARGET_VECTORIZE_INIT_COST
1710 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1711 #undef TARGET_VECTORIZE_ADD_STMT_COST
1712 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1713 #undef TARGET_VECTORIZE_FINISH_COST
1714 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1715 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1716 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1718 #undef TARGET_INIT_BUILTINS
1719 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1720 #undef TARGET_BUILTIN_DECL
1721 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1723 #undef TARGET_FOLD_BUILTIN
1724 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1725 #undef TARGET_GIMPLE_FOLD_BUILTIN
1726 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1728 #undef TARGET_EXPAND_BUILTIN
1729 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1731 #undef TARGET_MANGLE_TYPE
1732 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1734 #undef TARGET_INIT_LIBFUNCS
1735 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1738 #undef TARGET_BINDS_LOCAL_P
1739 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1742 #undef TARGET_MS_BITFIELD_LAYOUT_P
1743 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1745 #undef TARGET_ASM_OUTPUT_MI_THUNK
1746 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1748 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1749 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1751 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1752 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1754 #undef TARGET_REGISTER_MOVE_COST
1755 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1756 #undef TARGET_MEMORY_MOVE_COST
1757 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1758 #undef TARGET_CANNOT_COPY_INSN_P
1759 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1760 #undef TARGET_RTX_COSTS
1761 #define TARGET_RTX_COSTS rs6000_rtx_costs
1762 #undef TARGET_ADDRESS_COST
1763 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1765 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1766 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1768 #undef TARGET_PROMOTE_FUNCTION_MODE
1769 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1771 #undef TARGET_RETURN_IN_MEMORY
1772 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1774 #undef TARGET_RETURN_IN_MSB
1775 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1777 #undef TARGET_SETUP_INCOMING_VARARGS
1778 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1780 /* Always strict argument naming on rs6000. */
1781 #undef TARGET_STRICT_ARGUMENT_NAMING
1782 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1783 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1784 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1785 #undef TARGET_SPLIT_COMPLEX_ARG
1786 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1787 #undef TARGET_MUST_PASS_IN_STACK
1788 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1789 #undef TARGET_PASS_BY_REFERENCE
1790 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1791 #undef TARGET_ARG_PARTIAL_BYTES
1792 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1793 #undef TARGET_FUNCTION_ARG_ADVANCE
1794 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1795 #undef TARGET_FUNCTION_ARG
1796 #define TARGET_FUNCTION_ARG rs6000_function_arg
1797 #undef TARGET_FUNCTION_ARG_BOUNDARY
1798 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1800 #undef TARGET_BUILD_BUILTIN_VA_LIST
1801 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1803 #undef TARGET_EXPAND_BUILTIN_VA_START
1804 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1806 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1807 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1809 #undef TARGET_EH_RETURN_FILTER_MODE
1810 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1812 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1813 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1815 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1816 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1818 #undef TARGET_FLOATN_MODE
1819 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1821 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1822 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1824 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1825 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1827 #undef TARGET_MD_ASM_ADJUST
1828 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1830 #undef TARGET_OPTION_OVERRIDE
1831 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1833 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1834 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1835 rs6000_builtin_vectorized_function
1837 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1838 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1839 rs6000_builtin_md_vectorized_function
1841 #undef TARGET_STACK_PROTECT_GUARD
1842 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1845 #undef TARGET_STACK_PROTECT_FAIL
1846 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1850 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1851 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1854 /* Use a 32-bit anchor range. This leads to sequences like:
1856 addis tmp,anchor,high
1859 where tmp itself acts as an anchor, and can be shared between
1860 accesses to the same 64k page. */
1861 #undef TARGET_MIN_ANCHOR_OFFSET
1862 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1863 #undef TARGET_MAX_ANCHOR_OFFSET
1864 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1865 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1866 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1867 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1868 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1870 #undef TARGET_BUILTIN_RECIPROCAL
1871 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1873 #undef TARGET_SECONDARY_RELOAD
1874 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1876 #undef TARGET_LEGITIMATE_ADDRESS_P
1877 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1879 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1880 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1882 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1883 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1885 #undef TARGET_CAN_ELIMINATE
1886 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1888 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1889 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1891 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1892 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1894 #undef TARGET_TRAMPOLINE_INIT
1895 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1897 #undef TARGET_FUNCTION_VALUE
1898 #define TARGET_FUNCTION_VALUE rs6000_function_value
1900 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1901 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1903 #undef TARGET_OPTION_SAVE
1904 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1906 #undef TARGET_OPTION_RESTORE
1907 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1909 #undef TARGET_OPTION_PRINT
1910 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1912 #undef TARGET_CAN_INLINE_P
1913 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1915 #undef TARGET_SET_CURRENT_FUNCTION
1916 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1918 #undef TARGET_LEGITIMATE_CONSTANT_P
1919 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1921 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1922 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1924 #undef TARGET_CAN_USE_DOLOOP_P
1925 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1927 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1928 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1930 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1931 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1932 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1933 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1934 #undef TARGET_UNWIND_WORD_MODE
1935 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1937 #undef TARGET_OFFLOAD_OPTIONS
1938 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1940 #undef TARGET_C_MODE_FOR_SUFFIX
1941 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1943 #undef TARGET_INVALID_BINARY_OP
1944 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1946 #undef TARGET_OPTAB_SUPPORTED_P
1947 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1949 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1950 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1952 #undef TARGET_COMPARE_VERSION_PRIORITY
1953 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1955 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1956 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1957 rs6000_generate_version_dispatcher_body
1959 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1960 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1961 rs6000_get_function_versions_dispatcher
1963 #undef TARGET_OPTION_FUNCTION_VERSIONS
1964 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1968 /* Processor table. */
1971 const char *const name
; /* Canonical processor name. */
1972 const enum processor_type processor
; /* Processor type enum value. */
1973 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1976 static struct rs6000_ptt
const processor_target_table
[] =
1978 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1979 #include "rs6000-cpus.def"
1983 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1987 rs6000_cpu_name_lookup (const char *name
)
1993 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1994 if (! strcmp (name
, processor_target_table
[i
].name
))
2002 /* Return number of consecutive hard regs needed starting at reg REGNO
2003 to hold something of mode MODE.
2004 This is ordinarily the length in words of a value of mode MODE
2005 but can be less for certain modes in special long registers.
2007 POWER and PowerPC GPRs hold 32 bits worth;
2008 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2011 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
2013 unsigned HOST_WIDE_INT reg_size
;
2015 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2016 128-bit floating point that can go in vector registers, which has VSX
2017 memory addressing. */
2018 if (FP_REGNO_P (regno
))
2019 reg_size
= (VECTOR_MEM_VSX_P (mode
) || FLOAT128_VECTOR_P (mode
)
2020 ? UNITS_PER_VSX_WORD
2021 : UNITS_PER_FP_WORD
);
2023 else if (ALTIVEC_REGNO_P (regno
))
2024 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2027 reg_size
= UNITS_PER_WORD
;
2029 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
2032 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2035 rs6000_hard_regno_mode_ok (int regno
, machine_mode mode
)
2037 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
2039 if (COMPLEX_MODE_P (mode
))
2040 mode
= GET_MODE_INNER (mode
);
2042 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2043 register combinations, and use PTImode where we need to deal with quad
2044 word memory operations. Don't allow quad words in the argument or frame
2045 pointer registers, just registers 0..31. */
2046 if (mode
== PTImode
)
2047 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2048 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2049 && ((regno
& 1) == 0));
2051 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2052 implementations. Don't allow an item to be split between a FP register
2053 and an Altivec register. Allow TImode in all VSX registers if the user
2055 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
2056 && (VECTOR_MEM_VSX_P (mode
)
2057 || FLOAT128_VECTOR_P (mode
)
2058 || reg_addr
[mode
].scalar_in_vmx_p
2060 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
2062 if (FP_REGNO_P (regno
))
2063 return FP_REGNO_P (last_regno
);
2065 if (ALTIVEC_REGNO_P (regno
))
2067 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
2070 return ALTIVEC_REGNO_P (last_regno
);
2074 /* The GPRs can hold any mode, but values bigger than one register
2075 cannot go past R31. */
2076 if (INT_REGNO_P (regno
))
2077 return INT_REGNO_P (last_regno
);
2079 /* The float registers (except for VSX vector modes) can only hold floating
2080 modes and DImode. */
2081 if (FP_REGNO_P (regno
))
2083 if (FLOAT128_VECTOR_P (mode
))
2086 if (SCALAR_FLOAT_MODE_P (mode
)
2087 && (mode
!= TDmode
|| (regno
% 2) == 0)
2088 && FP_REGNO_P (last_regno
))
2091 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2093 if(GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
2096 if (TARGET_P8_VECTOR
&& (mode
== SImode
))
2099 if (TARGET_P9_VECTOR
&& (mode
== QImode
|| mode
== HImode
))
2103 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
2104 && PAIRED_VECTOR_MODE (mode
))
2110 /* The CR register can only hold CC modes. */
2111 if (CR_REGNO_P (regno
))
2112 return GET_MODE_CLASS (mode
) == MODE_CC
;
2114 if (CA_REGNO_P (regno
))
2115 return mode
== Pmode
|| mode
== SImode
;
2117 /* AltiVec only in AldyVec registers. */
2118 if (ALTIVEC_REGNO_P (regno
))
2119 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
2120 || mode
== V1TImode
);
2122 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2123 and it must be able to fit within the register set. */
2125 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
2128 /* Print interesting facts about registers. */
2130 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
2134 for (r
= first_regno
; r
<= last_regno
; ++r
)
2136 const char *comma
= "";
2139 if (first_regno
== last_regno
)
2140 fprintf (stderr
, "%s:\t", reg_name
);
2142 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
2145 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2146 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
2150 fprintf (stderr
, ",\n\t");
2155 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
2156 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
2157 rs6000_hard_regno_nregs
[m
][r
]);
2159 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
2164 if (call_used_regs
[r
])
2168 fprintf (stderr
, ",\n\t");
2173 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
2181 fprintf (stderr
, ",\n\t");
2186 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
2192 fprintf (stderr
, ",\n\t");
2196 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
2197 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
2202 fprintf (stderr
, ",\n\t");
2206 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
2211 rs6000_debug_vector_unit (enum rs6000_vector v
)
2217 case VECTOR_NONE
: ret
= "none"; break;
2218 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
2219 case VECTOR_VSX
: ret
= "vsx"; break;
2220 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
2221 case VECTOR_PAIRED
: ret
= "paired"; break;
2222 case VECTOR_OTHER
: ret
= "other"; break;
2223 default: ret
= "unknown"; break;
2229 /* Inner function printing just the address mask for a particular reload
2231 DEBUG_FUNCTION
char *
2232 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
2237 if ((mask
& RELOAD_REG_VALID
) != 0)
2239 else if (keep_spaces
)
2242 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
2244 else if (keep_spaces
)
2247 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2249 else if (keep_spaces
)
2252 if ((mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
2254 else if ((mask
& RELOAD_REG_OFFSET
) != 0)
2256 else if (keep_spaces
)
2259 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2261 else if (keep_spaces
)
2264 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2266 else if (keep_spaces
)
2269 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2271 else if (keep_spaces
)
2279 /* Print the address masks in a human readble fashion. */
2281 rs6000_debug_print_mode (ssize_t m
)
2287 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2288 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2289 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2290 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2292 if ((reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2293 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
2294 fprintf (stderr
, " Reload=%c%c",
2295 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2296 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
2298 spaces
+= sizeof (" Reload=sl") - 1;
2300 if (reg_addr
[m
].scalar_in_vmx_p
)
2302 fprintf (stderr
, "%*s Upper=y", spaces
, "");
2306 spaces
+= sizeof (" Upper=y") - 1;
2308 fuse_extra_p
= ((reg_addr
[m
].fusion_gpr_ld
!= CODE_FOR_nothing
)
2309 || reg_addr
[m
].fused_toc
);
2312 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2314 if (rc
!= RELOAD_REG_ANY
)
2316 if (reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
2317 || reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
2318 || reg_addr
[m
].fusion_addi_st
[rc
] != CODE_FOR_nothing
2319 || reg_addr
[m
].fusion_addis_ld
[rc
] != CODE_FOR_nothing
2320 || reg_addr
[m
].fusion_addis_st
[rc
] != CODE_FOR_nothing
)
2322 fuse_extra_p
= true;
2331 fprintf (stderr
, "%*s Fuse:", spaces
, "");
2334 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2336 if (rc
!= RELOAD_REG_ANY
)
2340 if (reg_addr
[m
].fusion_addis_ld
[rc
] != CODE_FOR_nothing
)
2342 else if (reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
)
2347 if (reg_addr
[m
].fusion_addis_st
[rc
] != CODE_FOR_nothing
)
2349 else if (reg_addr
[m
].fusion_addi_st
[rc
] != CODE_FOR_nothing
)
2354 if (load
== '-' && store
== '-')
2358 fprintf (stderr
, "%*s%c=%c%c", (spaces
+ 1), "",
2359 reload_reg_map
[rc
].name
[0], load
, store
);
2365 if (reg_addr
[m
].fusion_gpr_ld
!= CODE_FOR_nothing
)
2367 fprintf (stderr
, "%*sP8gpr", (spaces
+ 1), "");
2371 spaces
+= sizeof (" P8gpr") - 1;
2373 if (reg_addr
[m
].fused_toc
)
2375 fprintf (stderr
, "%*sToc", (spaces
+ 1), "");
2379 spaces
+= sizeof (" Toc") - 1;
2382 spaces
+= sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2384 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2385 || rs6000_vector_mem
[m
] != VECTOR_NONE
)
2387 fprintf (stderr
, "%*s vector: arith=%-10s mem=%s",
2389 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2390 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]));
2393 fputs ("\n", stderr
);
2396 #define DEBUG_FMT_ID "%-32s= "
2397 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2398 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2399 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2401 /* Print various interesting information with -mdebug=reg. */
2403 rs6000_debug_reg_global (void)
2405 static const char *const tf
[2] = { "false", "true" };
2406 const char *nl
= (const char *)0;
2409 char costly_num
[20];
2411 char flags_buffer
[40];
2412 const char *costly_str
;
2413 const char *nop_str
;
2414 const char *trace_str
;
2415 const char *abi_str
;
2416 const char *cmodel_str
;
2417 struct cl_target_option cl_opts
;
2419 /* Modes we want tieable information on. */
2420 static const machine_mode print_tieable_modes
[] = {
2456 /* Virtual regs we are interested in. */
2457 const static struct {
2458 int regno
; /* register number. */
2459 const char *name
; /* register name. */
2460 } virtual_regs
[] = {
2461 { STACK_POINTER_REGNUM
, "stack pointer:" },
2462 { TOC_REGNUM
, "toc: " },
2463 { STATIC_CHAIN_REGNUM
, "static chain: " },
2464 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2465 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2466 { ARG_POINTER_REGNUM
, "arg pointer: " },
2467 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2468 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2469 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2470 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2471 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2472 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2473 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2474 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2475 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2476 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2479 fputs ("\nHard register information:\n", stderr
);
2480 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2481 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2482 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2485 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2486 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2487 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2488 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2489 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2490 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2492 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2493 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2494 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2498 "d reg_class = %s\n"
2499 "f reg_class = %s\n"
2500 "v reg_class = %s\n"
2501 "wa reg_class = %s\n"
2502 "wb reg_class = %s\n"
2503 "wd reg_class = %s\n"
2504 "we reg_class = %s\n"
2505 "wf reg_class = %s\n"
2506 "wg reg_class = %s\n"
2507 "wh reg_class = %s\n"
2508 "wi reg_class = %s\n"
2509 "wj reg_class = %s\n"
2510 "wk reg_class = %s\n"
2511 "wl reg_class = %s\n"
2512 "wm reg_class = %s\n"
2513 "wo reg_class = %s\n"
2514 "wp reg_class = %s\n"
2515 "wq reg_class = %s\n"
2516 "wr reg_class = %s\n"
2517 "ws reg_class = %s\n"
2518 "wt reg_class = %s\n"
2519 "wu reg_class = %s\n"
2520 "wv reg_class = %s\n"
2521 "ww reg_class = %s\n"
2522 "wx reg_class = %s\n"
2523 "wy reg_class = %s\n"
2524 "wz reg_class = %s\n"
2525 "wA reg_class = %s\n"
2526 "wH reg_class = %s\n"
2527 "wI reg_class = %s\n"
2528 "wJ reg_class = %s\n"
2529 "wK reg_class = %s\n"
2531 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2532 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2533 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2534 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2535 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wb
]],
2536 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2537 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_we
]],
2538 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2539 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2540 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2541 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2542 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2543 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2544 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2545 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2546 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wo
]],
2547 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2548 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2549 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2550 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2551 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2552 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2553 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2554 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2555 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2556 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2557 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]],
2558 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wA
]],
2559 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wH
]],
2560 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wI
]],
2561 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wJ
]],
2562 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wK
]]);
2565 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2566 rs6000_debug_print_mode (m
);
2568 fputs ("\n", stderr
);
2570 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2572 machine_mode mode1
= print_tieable_modes
[m1
];
2573 bool first_time
= true;
2575 nl
= (const char *)0;
2576 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2578 machine_mode mode2
= print_tieable_modes
[m2
];
2579 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2583 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2588 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2593 fputs ("\n", stderr
);
2599 if (rs6000_recip_control
)
2601 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2603 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2604 if (rs6000_recip_bits
[m
])
2607 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2609 (RS6000_RECIP_AUTO_RE_P (m
)
2611 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2612 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2614 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2617 fputs ("\n", stderr
);
2620 if (rs6000_cpu_index
>= 0)
2622 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2624 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2626 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2627 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2630 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2632 if (rs6000_tune_index
>= 0)
2634 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2636 = processor_target_table
[rs6000_tune_index
].target_enable
;
2638 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2639 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2642 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2644 cl_target_option_save (&cl_opts
, &global_options
);
2645 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2648 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2649 rs6000_isa_flags_explicit
);
2651 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2652 rs6000_builtin_mask
);
2654 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2656 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2657 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2659 switch (rs6000_sched_costly_dep
)
2661 case max_dep_latency
:
2662 costly_str
= "max_dep_latency";
2666 costly_str
= "no_dep_costly";
2669 case all_deps_costly
:
2670 costly_str
= "all_deps_costly";
2673 case true_store_to_load_dep_costly
:
2674 costly_str
= "true_store_to_load_dep_costly";
2677 case store_to_load_dep_costly
:
2678 costly_str
= "store_to_load_dep_costly";
2682 costly_str
= costly_num
;
2683 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2687 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2689 switch (rs6000_sched_insert_nops
)
2691 case sched_finish_regroup_exact
:
2692 nop_str
= "sched_finish_regroup_exact";
2695 case sched_finish_pad_groups
:
2696 nop_str
= "sched_finish_pad_groups";
2699 case sched_finish_none
:
2700 nop_str
= "sched_finish_none";
2705 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2709 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2711 switch (rs6000_sdata
)
2718 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2722 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2726 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2731 switch (rs6000_traceback
)
2733 case traceback_default
: trace_str
= "default"; break;
2734 case traceback_none
: trace_str
= "none"; break;
2735 case traceback_part
: trace_str
= "part"; break;
2736 case traceback_full
: trace_str
= "full"; break;
2737 default: trace_str
= "unknown"; break;
2740 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2742 switch (rs6000_current_cmodel
)
2744 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2745 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2746 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2747 default: cmodel_str
= "unknown"; break;
2750 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2752 switch (rs6000_current_abi
)
2754 case ABI_NONE
: abi_str
= "none"; break;
2755 case ABI_AIX
: abi_str
= "aix"; break;
2756 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2757 case ABI_V4
: abi_str
= "V4"; break;
2758 case ABI_DARWIN
: abi_str
= "darwin"; break;
2759 default: abi_str
= "unknown"; break;
2762 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2764 if (rs6000_altivec_abi
)
2765 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2767 if (rs6000_darwin64_abi
)
2768 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2770 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2771 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2773 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2774 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2776 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2777 (TARGET_SOFT_FLOAT
? "true" : "false"));
2779 if (TARGET_LINK_STACK
)
2780 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2782 if (TARGET_P8_FUSION
)
2786 strcpy (options
, (TARGET_P9_FUSION
) ? "power9" : "power8");
2787 if (TARGET_TOC_FUSION
)
2788 strcat (options
, ", toc");
2790 if (TARGET_P8_FUSION_SIGN
)
2791 strcat (options
, ", sign");
2793 fprintf (stderr
, DEBUG_FMT_S
, "fusion", options
);
2796 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2797 TARGET_SECURE_PLT
? "secure" : "bss");
2798 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2799 aix_struct_return
? "aix" : "sysv");
2800 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2801 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2802 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2803 tf
[!!rs6000_align_branch_targets
]);
2804 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2805 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2806 rs6000_long_double_type_size
);
2807 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2808 (int)rs6000_sched_restricted_insns_priority
);
2809 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2811 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2812 (int)RS6000_BUILTIN_COUNT
);
2814 fprintf (stderr
, DEBUG_FMT_D
, "Enable float128 on VSX",
2815 (int)TARGET_FLOAT128_ENABLE_TYPE
);
2818 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2819 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2821 if (TARGET_DIRECT_MOVE_128
)
2822 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit mfvsrld element",
2823 (int)VECTOR_ELEMENT_MFVSRLD_64BIT
);
2827 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2828 legitimate address support to figure out the appropriate addressing to
2832 rs6000_setup_reg_addr_masks (void)
2834 ssize_t rc
, reg
, m
, nregs
;
2835 addr_mask_type any_addr_mask
, addr_mask
;
2837 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2839 machine_mode m2
= (machine_mode
) m
;
2840 bool complex_p
= false;
2841 bool small_int_p
= (m2
== QImode
|| m2
== HImode
|| m2
== SImode
);
2844 if (COMPLEX_MODE_P (m2
))
2847 m2
= GET_MODE_INNER (m2
);
2850 msize
= GET_MODE_SIZE (m2
);
2852 /* SDmode is special in that we want to access it only via REG+REG
2853 addressing on power7 and above, since we want to use the LFIWZX and
2854 STFIWZX instructions to load it. */
2855 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2858 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2861 reg
= reload_reg_map
[rc
].reg
;
2863 /* Can mode values go in the GPR/FPR/Altivec registers? */
2864 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2866 bool small_int_vsx_p
= (small_int_p
2867 && (rc
== RELOAD_REG_FPR
2868 || rc
== RELOAD_REG_VMX
));
2870 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2871 addr_mask
|= RELOAD_REG_VALID
;
2873 /* Indicate if the mode takes more than 1 physical register. If
2874 it takes a single register, indicate it can do REG+REG
2875 addressing. Small integers in VSX registers can only do
2876 REG+REG addressing. */
2877 if (small_int_vsx_p
)
2878 addr_mask
|= RELOAD_REG_INDEXED
;
2879 else if (nregs
> 1 || m
== BLKmode
|| complex_p
)
2880 addr_mask
|= RELOAD_REG_MULTIPLE
;
2882 addr_mask
|= RELOAD_REG_INDEXED
;
2884 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2885 addressing. If we allow scalars into Altivec registers,
2886 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
2889 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2891 && !VECTOR_MODE_P (m2
)
2892 && !FLOAT128_VECTOR_P (m2
)
2894 && !small_int_vsx_p
)
2896 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2898 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2899 we don't allow PRE_MODIFY for some multi-register
2904 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2908 if (TARGET_POWERPC64
)
2909 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2915 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2921 /* GPR and FPR registers can do REG+OFFSET addressing, except
2922 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2923 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2924 if ((addr_mask
!= 0) && !indexed_only_p
2926 && (rc
== RELOAD_REG_GPR
2927 || ((msize
== 8 || m2
== SFmode
)
2928 && (rc
== RELOAD_REG_FPR
2929 || (rc
== RELOAD_REG_VMX
2930 && TARGET_P9_DFORM_SCALAR
)))))
2931 addr_mask
|= RELOAD_REG_OFFSET
;
2933 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2934 instructions are enabled. The offset for 128-bit VSX registers is
2935 only 12-bits. While GPRs can handle the full offset range, VSX
2936 registers can only handle the restricted range. */
2937 else if ((addr_mask
!= 0) && !indexed_only_p
2938 && msize
== 16 && TARGET_P9_DFORM_VECTOR
2939 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2
)
2940 || (m2
== TImode
&& TARGET_VSX
)))
2942 addr_mask
|= RELOAD_REG_OFFSET
;
2943 if (rc
== RELOAD_REG_FPR
|| rc
== RELOAD_REG_VMX
)
2944 addr_mask
|= RELOAD_REG_QUAD_OFFSET
;
2947 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2948 addressing on 128-bit types. */
2949 if (rc
== RELOAD_REG_VMX
&& msize
== 16
2950 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2951 addr_mask
|= RELOAD_REG_AND_M16
;
2953 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2954 any_addr_mask
|= addr_mask
;
2957 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2962 /* Initialize the various global tables that are based on register size. */
2964 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2970 /* Precalculate REGNO_REG_CLASS. */
2971 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2972 for (r
= 1; r
< 32; ++r
)
2973 rs6000_regno_regclass
[r
] = BASE_REGS
;
2975 for (r
= 32; r
< 64; ++r
)
2976 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2978 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2979 rs6000_regno_regclass
[r
] = NO_REGS
;
2981 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2982 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2984 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2985 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2986 rs6000_regno_regclass
[r
] = CR_REGS
;
2988 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2989 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2990 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
2991 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2992 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2993 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2994 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2995 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2996 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2997 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2999 /* Precalculate register class to simpler reload register class. We don't
3000 need all of the register classes that are combinations of different
3001 classes, just the simple ones that have constraint letters. */
3002 for (c
= 0; c
< N_REG_CLASSES
; c
++)
3003 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
3005 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
3006 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
3007 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
3008 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
3009 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
3010 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
3011 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
3012 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
3013 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
3014 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
3018 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
3019 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
3023 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
3024 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
3027 /* Precalculate the valid memory formats as well as the vector information,
3028 this must be set up before the rs6000_hard_regno_nregs_internal calls
3030 gcc_assert ((int)VECTOR_NONE
== 0);
3031 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
3032 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
3034 gcc_assert ((int)CODE_FOR_nothing
== 0);
3035 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
3037 gcc_assert ((int)NO_REGS
== 0);
3038 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
3040 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3041 believes it can use native alignment or still uses 128-bit alignment. */
3042 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
3053 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3054 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3055 if (TARGET_FLOAT128_TYPE
)
3057 rs6000_vector_mem
[KFmode
] = VECTOR_VSX
;
3058 rs6000_vector_align
[KFmode
] = 128;
3060 if (FLOAT128_IEEE_P (TFmode
))
3062 rs6000_vector_mem
[TFmode
] = VECTOR_VSX
;
3063 rs6000_vector_align
[TFmode
] = 128;
3067 /* V2DF mode, VSX only. */
3070 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
3071 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
3072 rs6000_vector_align
[V2DFmode
] = align64
;
3075 /* V4SF mode, either VSX or Altivec. */
3078 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
3079 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
3080 rs6000_vector_align
[V4SFmode
] = align32
;
3082 else if (TARGET_ALTIVEC
)
3084 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
3085 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
3086 rs6000_vector_align
[V4SFmode
] = align32
;
3089 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3093 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
3094 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
3095 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
3096 rs6000_vector_align
[V4SImode
] = align32
;
3097 rs6000_vector_align
[V8HImode
] = align32
;
3098 rs6000_vector_align
[V16QImode
] = align32
;
3102 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
3103 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
3104 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
3108 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
3109 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
3110 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
3114 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3115 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3118 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
3119 rs6000_vector_unit
[V2DImode
]
3120 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3121 rs6000_vector_align
[V2DImode
] = align64
;
3123 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
3124 rs6000_vector_unit
[V1TImode
]
3125 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3126 rs6000_vector_align
[V1TImode
] = 128;
3129 /* DFmode, see if we want to use the VSX unit. Memory is handled
3130 differently, so don't set rs6000_vector_mem. */
3131 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
3133 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
3134 rs6000_vector_align
[DFmode
] = 64;
3137 /* SFmode, see if we want to use the VSX unit. */
3138 if (TARGET_P8_VECTOR
&& TARGET_VSX_SCALAR_FLOAT
)
3140 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
3141 rs6000_vector_align
[SFmode
] = 32;
3144 /* Allow TImode in VSX register and set the VSX memory macros. */
3147 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
3148 rs6000_vector_align
[TImode
] = align64
;
3151 /* TODO add paired floating point vector support. */
3153 /* Register class constraints for the constraints that depend on compile
3154 switches. When the VSX code was added, different constraints were added
3155 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3156 of the VSX registers are used. The register classes for scalar floating
3157 point types is set, based on whether we allow that type into the upper
3158 (Altivec) registers. GCC has register classes to target the Altivec
3159 registers for load/store operations, to select using a VSX memory
3160 operation instead of the traditional floating point operation. The
3163 d - Register class to use with traditional DFmode instructions.
3164 f - Register class to use with traditional SFmode instructions.
3165 v - Altivec register.
3166 wa - Any VSX register.
3167 wc - Reserved to represent individual CR bits (used in LLVM).
3168 wd - Preferred register class for V2DFmode.
3169 wf - Preferred register class for V4SFmode.
3170 wg - Float register for power6x move insns.
3171 wh - FP register for direct move instructions.
3172 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3173 wj - FP or VSX register to hold 64-bit integers for direct moves.
3174 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3175 wl - Float register if we can do 32-bit signed int loads.
3176 wm - VSX register for ISA 2.07 direct move operations.
3177 wn - always NO_REGS.
3178 wr - GPR if 64-bit mode is permitted.
3179 ws - Register class to do ISA 2.06 DF operations.
3180 wt - VSX register for TImode in VSX registers.
3181 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3182 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3183 ww - Register class to do SF conversions in with VSX operations.
3184 wx - Float register if we can do 32-bit int stores.
3185 wy - Register class to do ISA 2.07 SF operations.
3186 wz - Float register if we can do 32-bit unsigned int loads.
3187 wH - Altivec register if SImode is allowed in VSX registers.
3188 wI - VSX register if SImode is allowed in VSX registers.
3189 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3190 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3192 if (TARGET_HARD_FLOAT
)
3193 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
3195 if (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
3196 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
3200 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
3201 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
3202 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
3203 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
; /* DFmode */
3204 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
; /* DFmode */
3205 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = VSX_REGS
; /* DImode */
3206 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
3209 /* Add conditional constraints based on various options, to allow us to
3210 collapse multiple insn patterns. */
3212 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
3214 if (TARGET_MFPGPR
) /* DFmode */
3215 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
3218 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
3220 if (TARGET_DIRECT_MOVE
)
3222 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
3223 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
3224 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
3225 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
3226 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
3227 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
3230 if (TARGET_POWERPC64
)
3232 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
3233 rs6000_constraints
[RS6000_CONSTRAINT_wA
] = BASE_REGS
;
3236 if (TARGET_P8_VECTOR
) /* SFmode */
3238 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
3239 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
3240 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
3242 else if (TARGET_VSX
)
3243 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3246 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
3249 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
3251 if (TARGET_FLOAT128_TYPE
)
3253 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
3254 if (FLOAT128_IEEE_P (TFmode
))
3255 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
3258 /* Support for new D-form instructions. */
3259 if (TARGET_P9_DFORM_SCALAR
)
3260 rs6000_constraints
[RS6000_CONSTRAINT_wb
] = ALTIVEC_REGS
;
3262 /* Support for ISA 3.0 (power9) vectors. */
3263 if (TARGET_P9_VECTOR
)
3264 rs6000_constraints
[RS6000_CONSTRAINT_wo
] = VSX_REGS
;
3266 /* Support for new direct moves (ISA 3.0 + 64bit). */
3267 if (TARGET_DIRECT_MOVE_128
)
3268 rs6000_constraints
[RS6000_CONSTRAINT_we
] = VSX_REGS
;
3270 /* Support small integers in VSX registers. */
3271 if (TARGET_P8_VECTOR
)
3273 rs6000_constraints
[RS6000_CONSTRAINT_wH
] = ALTIVEC_REGS
;
3274 rs6000_constraints
[RS6000_CONSTRAINT_wI
] = FLOAT_REGS
;
3275 if (TARGET_P9_VECTOR
)
3277 rs6000_constraints
[RS6000_CONSTRAINT_wJ
] = FLOAT_REGS
;
3278 rs6000_constraints
[RS6000_CONSTRAINT_wK
] = ALTIVEC_REGS
;
3282 /* Set up the reload helper and direct move functions. */
3283 if (TARGET_VSX
|| TARGET_ALTIVEC
)
3287 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
3288 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
3289 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
3290 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
3291 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
3292 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
3293 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
3294 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
3295 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
3296 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
3297 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
3298 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
3299 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
3300 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
3301 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
3302 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
3303 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
3304 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
3305 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
3306 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
3308 if (FLOAT128_VECTOR_P (KFmode
))
3310 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_di_store
;
3311 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_di_load
;
3314 if (FLOAT128_VECTOR_P (TFmode
))
3316 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_di_store
;
3317 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_di_load
;
3320 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3322 if (TARGET_NO_SDMODE_STACK
)
3324 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
3325 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
3330 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
3331 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
3334 if (TARGET_DIRECT_MOVE
&& !TARGET_DIRECT_MOVE_128
)
3336 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
3337 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
3338 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
3339 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
3340 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
3341 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
3342 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
3343 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
3344 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
3346 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
3347 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
3348 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
3349 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
3350 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
3351 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
3352 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
3353 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
3354 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
3356 if (FLOAT128_VECTOR_P (KFmode
))
3358 reg_addr
[KFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxkf
;
3359 reg_addr
[KFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprkf
;
3362 if (FLOAT128_VECTOR_P (TFmode
))
3364 reg_addr
[TFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxtf
;
3365 reg_addr
[TFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprtf
;
3371 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
3372 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
3373 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
3374 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
3375 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
3376 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
3377 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
3378 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
3379 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
3380 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
3381 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
3382 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
3383 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
3384 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
3385 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
3386 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
3387 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
3388 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
3389 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
3390 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
3392 if (FLOAT128_VECTOR_P (KFmode
))
3394 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_si_store
;
3395 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_si_load
;
3398 if (FLOAT128_IEEE_P (TFmode
))
3400 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_si_store
;
3401 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_si_load
;
3404 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3406 if (TARGET_NO_SDMODE_STACK
)
3408 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
3409 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
3414 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
3415 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
3418 if (TARGET_DIRECT_MOVE
)
3420 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
3421 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
3422 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
3426 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
3427 reg_addr
[DImode
].scalar_in_vmx_p
= true;
3429 if (TARGET_P8_VECTOR
)
3431 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
3432 reg_addr
[SImode
].scalar_in_vmx_p
= true;
3434 if (TARGET_P9_VECTOR
)
3436 reg_addr
[HImode
].scalar_in_vmx_p
= true;
3437 reg_addr
[QImode
].scalar_in_vmx_p
= true;
3442 /* Setup the fusion operations. */
3443 if (TARGET_P8_FUSION
)
3445 reg_addr
[QImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_qi
;
3446 reg_addr
[HImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_hi
;
3447 reg_addr
[SImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_si
;
3449 reg_addr
[DImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_di
;
3452 if (TARGET_P9_FUSION
)
3455 enum machine_mode mode
; /* mode of the fused type. */
3456 enum machine_mode pmode
; /* pointer mode. */
3457 enum rs6000_reload_reg_type rtype
; /* register type. */
3458 enum insn_code load
; /* load insn. */
3459 enum insn_code store
; /* store insn. */
3462 static const struct fuse_insns addis_insns
[] = {
3463 { SFmode
, DImode
, RELOAD_REG_FPR
,
3464 CODE_FOR_fusion_vsx_di_sf_load
,
3465 CODE_FOR_fusion_vsx_di_sf_store
},
3467 { SFmode
, SImode
, RELOAD_REG_FPR
,
3468 CODE_FOR_fusion_vsx_si_sf_load
,
3469 CODE_FOR_fusion_vsx_si_sf_store
},
3471 { DFmode
, DImode
, RELOAD_REG_FPR
,
3472 CODE_FOR_fusion_vsx_di_df_load
,
3473 CODE_FOR_fusion_vsx_di_df_store
},
3475 { DFmode
, SImode
, RELOAD_REG_FPR
,
3476 CODE_FOR_fusion_vsx_si_df_load
,
3477 CODE_FOR_fusion_vsx_si_df_store
},
3479 { DImode
, DImode
, RELOAD_REG_FPR
,
3480 CODE_FOR_fusion_vsx_di_di_load
,
3481 CODE_FOR_fusion_vsx_di_di_store
},
3483 { DImode
, SImode
, RELOAD_REG_FPR
,
3484 CODE_FOR_fusion_vsx_si_di_load
,
3485 CODE_FOR_fusion_vsx_si_di_store
},
3487 { QImode
, DImode
, RELOAD_REG_GPR
,
3488 CODE_FOR_fusion_gpr_di_qi_load
,
3489 CODE_FOR_fusion_gpr_di_qi_store
},
3491 { QImode
, SImode
, RELOAD_REG_GPR
,
3492 CODE_FOR_fusion_gpr_si_qi_load
,
3493 CODE_FOR_fusion_gpr_si_qi_store
},
3495 { HImode
, DImode
, RELOAD_REG_GPR
,
3496 CODE_FOR_fusion_gpr_di_hi_load
,
3497 CODE_FOR_fusion_gpr_di_hi_store
},
3499 { HImode
, SImode
, RELOAD_REG_GPR
,
3500 CODE_FOR_fusion_gpr_si_hi_load
,
3501 CODE_FOR_fusion_gpr_si_hi_store
},
3503 { SImode
, DImode
, RELOAD_REG_GPR
,
3504 CODE_FOR_fusion_gpr_di_si_load
,
3505 CODE_FOR_fusion_gpr_di_si_store
},
3507 { SImode
, SImode
, RELOAD_REG_GPR
,
3508 CODE_FOR_fusion_gpr_si_si_load
,
3509 CODE_FOR_fusion_gpr_si_si_store
},
3511 { SFmode
, DImode
, RELOAD_REG_GPR
,
3512 CODE_FOR_fusion_gpr_di_sf_load
,
3513 CODE_FOR_fusion_gpr_di_sf_store
},
3515 { SFmode
, SImode
, RELOAD_REG_GPR
,
3516 CODE_FOR_fusion_gpr_si_sf_load
,
3517 CODE_FOR_fusion_gpr_si_sf_store
},
3519 { DImode
, DImode
, RELOAD_REG_GPR
,
3520 CODE_FOR_fusion_gpr_di_di_load
,
3521 CODE_FOR_fusion_gpr_di_di_store
},
3523 { DFmode
, DImode
, RELOAD_REG_GPR
,
3524 CODE_FOR_fusion_gpr_di_df_load
,
3525 CODE_FOR_fusion_gpr_di_df_store
},
3528 machine_mode cur_pmode
= Pmode
;
3531 for (i
= 0; i
< ARRAY_SIZE (addis_insns
); i
++)
3533 machine_mode xmode
= addis_insns
[i
].mode
;
3534 enum rs6000_reload_reg_type rtype
= addis_insns
[i
].rtype
;
3536 if (addis_insns
[i
].pmode
!= cur_pmode
)
3539 if (rtype
== RELOAD_REG_FPR
&& !TARGET_HARD_FLOAT
)
3542 reg_addr
[xmode
].fusion_addis_ld
[rtype
] = addis_insns
[i
].load
;
3543 reg_addr
[xmode
].fusion_addis_st
[rtype
] = addis_insns
[i
].store
;
3545 if (rtype
== RELOAD_REG_FPR
&& TARGET_P9_DFORM_SCALAR
)
3547 reg_addr
[xmode
].fusion_addis_ld
[RELOAD_REG_VMX
]
3548 = addis_insns
[i
].load
;
3549 reg_addr
[xmode
].fusion_addis_st
[RELOAD_REG_VMX
]
3550 = addis_insns
[i
].store
;
3555 /* Note which types we support fusing TOC setup plus memory insn. We only do
3556 fused TOCs for medium/large code models. */
3557 if (TARGET_P8_FUSION
&& TARGET_TOC_FUSION
&& TARGET_POWERPC64
3558 && (TARGET_CMODEL
!= CMODEL_SMALL
))
3560 reg_addr
[QImode
].fused_toc
= true;
3561 reg_addr
[HImode
].fused_toc
= true;
3562 reg_addr
[SImode
].fused_toc
= true;
3563 reg_addr
[DImode
].fused_toc
= true;
3564 if (TARGET_HARD_FLOAT
)
3566 if (TARGET_SINGLE_FLOAT
)
3567 reg_addr
[SFmode
].fused_toc
= true;
3568 if (TARGET_DOUBLE_FLOAT
)
3569 reg_addr
[DFmode
].fused_toc
= true;
3573 /* Precalculate HARD_REGNO_NREGS. */
3574 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3575 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3576 rs6000_hard_regno_nregs
[m
][r
]
3577 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
3579 /* Precalculate HARD_REGNO_MODE_OK. */
3580 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3581 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3582 if (rs6000_hard_regno_mode_ok (r
, (machine_mode
)m
))
3583 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
3585 /* Precalculate CLASS_MAX_NREGS sizes. */
3586 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3590 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3591 reg_size
= UNITS_PER_VSX_WORD
;
3593 else if (c
== ALTIVEC_REGS
)
3594 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3596 else if (c
== FLOAT_REGS
)
3597 reg_size
= UNITS_PER_FP_WORD
;
3600 reg_size
= UNITS_PER_WORD
;
3602 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3604 machine_mode m2
= (machine_mode
)m
;
3605 int reg_size2
= reg_size
;
3607 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3609 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3610 reg_size2
= UNITS_PER_FP_WORD
;
3612 rs6000_class_max_nregs
[m
][c
]
3613 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3617 /* Calculate which modes to automatically generate code to use a the
3618 reciprocal divide and square root instructions. In the future, possibly
3619 automatically generate the instructions even if the user did not specify
3620 -mrecip. The older machines double precision reciprocal sqrt estimate is
3621 not accurate enough. */
3622 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3624 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3626 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3627 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3628 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3629 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3630 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3632 if (TARGET_FRSQRTES
)
3633 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3635 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3636 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3637 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3638 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3639 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3641 if (rs6000_recip_control
)
3643 if (!flag_finite_math_only
)
3644 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3646 if (flag_trapping_math
)
3647 warning (0, "%qs requires %qs or %qs", "-mrecip",
3648 "-fno-trapping-math", "-ffast-math");
3649 if (!flag_reciprocal_math
)
3650 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3652 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3654 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3655 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3656 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3658 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3659 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3660 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3662 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3663 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3664 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3666 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3667 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3668 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3670 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3671 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3672 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3674 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3675 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3676 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3678 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3679 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3680 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3682 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3683 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3684 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3688 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3689 legitimate address support to figure out the appropriate addressing to
3691 rs6000_setup_reg_addr_masks ();
3693 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3695 if (TARGET_DEBUG_REG
)
3696 rs6000_debug_reg_global ();
3698 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3700 "SImode variable mult cost = %d\n"
3701 "SImode constant mult cost = %d\n"
3702 "SImode short constant mult cost = %d\n"
3703 "DImode multipliciation cost = %d\n"
3704 "SImode division cost = %d\n"
3705 "DImode division cost = %d\n"
3706 "Simple fp operation cost = %d\n"
3707 "DFmode multiplication cost = %d\n"
3708 "SFmode division cost = %d\n"
3709 "DFmode division cost = %d\n"
3710 "cache line size = %d\n"
3711 "l1 cache size = %d\n"
3712 "l2 cache size = %d\n"
3713 "simultaneous prefetches = %d\n"
3716 rs6000_cost
->mulsi_const
,
3717 rs6000_cost
->mulsi_const9
,
3725 rs6000_cost
->cache_line_size
,
3726 rs6000_cost
->l1_cache_size
,
3727 rs6000_cost
->l2_cache_size
,
3728 rs6000_cost
->simultaneous_prefetches
);
3733 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3736 darwin_rs6000_override_options (void)
3738 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3740 rs6000_altivec_abi
= 1;
3741 TARGET_ALTIVEC_VRSAVE
= 1;
3742 rs6000_current_abi
= ABI_DARWIN
;
3744 if (DEFAULT_ABI
== ABI_DARWIN
3746 darwin_one_byte_bool
= 1;
3748 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3750 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3751 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3755 rs6000_default_long_calls
= 1;
3756 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3759 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3761 if (!flag_mkernel
&& !flag_apple_kext
3763 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3764 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3766 /* Unless the user (not the configurer) has explicitly overridden
3767 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3768 G4 unless targeting the kernel. */
3771 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3772 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3773 && ! global_options_set
.x_rs6000_cpu_index
)
3775 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3780 /* If not otherwise specified by a target, make 'long double' equivalent to
3783 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3784 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3787 /* Return the builtin mask of the various options used that could affect which
3788 builtins were used. In the past we used target_flags, but we've run out of
3789 bits, and some options like PAIRED are no longer in target_flags. */
3792 rs6000_builtin_mask_calculate (void)
3794 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3795 | ((TARGET_CMPB
) ? RS6000_BTM_CMPB
: 0)
3796 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3797 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3798 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3799 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3800 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3801 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3802 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3803 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3804 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3805 | ((TARGET_P9_VECTOR
) ? RS6000_BTM_P9_VECTOR
: 0)
3806 | ((TARGET_P9_MISC
) ? RS6000_BTM_P9_MISC
: 0)
3807 | ((TARGET_MODULO
) ? RS6000_BTM_MODULO
: 0)
3808 | ((TARGET_64BIT
) ? RS6000_BTM_64BIT
: 0)
3809 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3810 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3811 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3812 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3813 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0)
3814 | ((TARGET_FLOAT128_TYPE
) ? RS6000_BTM_FLOAT128
: 0));
3817 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3818 to clobber the XER[CA] bit because clobbering that bit without telling
3819 the compiler worked just fine with versions of GCC before GCC 5, and
3820 breaking a lot of older code in ways that are hard to track down is
3821 not such a great idea. */
3824 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3825 vec
<const char *> &/*constraints*/,
3826 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3828 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3829 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3833 /* Override command line options.
3835 Combine build-specific configuration information with options
3836 specified on the command line to set various state variables which
3837 influence code generation, optimization, and expansion of built-in
3838 functions. Assure that command-line configuration preferences are
3839 compatible with each other and with the build configuration; issue
3840 warnings while adjusting configuration or error messages while
3841 rejecting configuration.
3843 Upon entry to this function:
3845 This function is called once at the beginning of
3846 compilation, and then again at the start and end of compiling
3847 each section of code that has a different configuration, as
3848 indicated, for example, by adding the
3850 __attribute__((__target__("cpu=power9")))
3852 qualifier to a function definition or, for example, by bracketing
3855 #pragma GCC target("altivec")
3859 #pragma GCC reset_options
3861 directives. Parameter global_init_p is true for the initial
3862 invocation, which initializes global variables, and false for all
3863 subsequent invocations.
3866 Various global state information is assumed to be valid. This
3867 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3868 default CPU specified at build configure time, TARGET_DEFAULT,
3869 representing the default set of option flags for the default
3870 target, and global_options_set.x_rs6000_isa_flags, representing
3871 which options were requested on the command line.
3873 Upon return from this function:
3875 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3876 was set by name on the command line. Additionally, if certain
3877 attributes are automatically enabled or disabled by this function
3878 in order to assure compatibility between options and
3879 configuration, the flags associated with those attributes are
3880 also set. By setting these "explicit bits", we avoid the risk
3881 that other code might accidentally overwrite these particular
3882 attributes with "default values".
3884 The various bits of rs6000_isa_flags are set to indicate the
3885 target options that have been selected for the most current
3886 compilation efforts. This has the effect of also turning on the
3887 associated TARGET_XXX values since these are macros which are
3888 generally defined to test the corresponding bit of the
3889 rs6000_isa_flags variable.
3891 The variable rs6000_builtin_mask is set to represent the target
3892 options for the most current compilation efforts, consistent with
3893 the current contents of rs6000_isa_flags. This variable controls
3894 expansion of built-in functions.
3896 Various other global variables and fields of global structures
3897 (over 50 in all) are initialized to reflect the desired options
3898 for the most current compilation efforts. */
3901 rs6000_option_override_internal (bool global_init_p
)
3904 bool have_cpu
= false;
3906 /* The default cpu requested at configure time, if any. */
3907 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3909 HOST_WIDE_INT set_masks
;
3910 HOST_WIDE_INT ignore_masks
;
3913 struct cl_target_option
*main_target_opt
3914 = ((global_init_p
|| target_option_default_node
== NULL
)
3915 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3917 /* Print defaults. */
3918 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3919 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3921 /* Remember the explicit arguments. */
3923 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3925 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3926 library functions, so warn about it. The flag may be useful for
3927 performance studies from time to time though, so don't disable it
3929 if (global_options_set
.x_rs6000_alignment_flags
3930 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3931 && DEFAULT_ABI
== ABI_DARWIN
3933 warning (0, "%qs is not supported for 64-bit Darwin;"
3934 " it is incompatible with the installed C and C++ libraries",
3937 /* Numerous experiment shows that IRA based loop pressure
3938 calculation works better for RTL loop invariant motion on targets
3939 with enough (>= 32) registers. It is an expensive optimization.
3940 So it is on only for peak performance. */
3941 if (optimize
>= 3 && global_init_p
3942 && !global_options_set
.x_flag_ira_loop_pressure
)
3943 flag_ira_loop_pressure
= 1;
3945 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3946 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3947 options were already specified. */
3948 if (flag_sanitize
& SANITIZE_USER_ADDRESS
3949 && !global_options_set
.x_flag_asynchronous_unwind_tables
)
3950 flag_asynchronous_unwind_tables
= 1;
3952 /* Set the pointer size. */
3955 rs6000_pmode
= (int)DImode
;
3956 rs6000_pointer_size
= 64;
3960 rs6000_pmode
= (int)SImode
;
3961 rs6000_pointer_size
= 32;
3964 /* Some OSs don't support saving the high part of 64-bit registers on context
3965 switch. Other OSs don't support saving Altivec registers. On those OSs,
3966 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3967 if the user wants either, the user must explicitly specify them and we
3968 won't interfere with the user's specification. */
3970 set_masks
= POWERPC_MASKS
;
3971 #ifdef OS_MISSING_POWERPC64
3972 if (OS_MISSING_POWERPC64
)
3973 set_masks
&= ~OPTION_MASK_POWERPC64
;
3975 #ifdef OS_MISSING_ALTIVEC
3976 if (OS_MISSING_ALTIVEC
)
3977 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
3978 | OTHER_VSX_VECTOR_MASKS
);
3981 /* Don't override by the processor default if given explicitly. */
3982 set_masks
&= ~rs6000_isa_flags_explicit
;
3984 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3985 the cpu in a target attribute or pragma, but did not specify a tuning
3986 option, use the cpu for the tuning option rather than the option specified
3987 with -mtune on the command line. Process a '--with-cpu' configuration
3988 request as an implicit --cpu. */
3989 if (rs6000_cpu_index
>= 0)
3991 cpu_index
= rs6000_cpu_index
;
3994 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3996 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3999 else if (implicit_cpu
)
4001 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
4006 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4007 const char *default_cpu
= ((!TARGET_POWERPC64
)
4009 : ((BYTES_BIG_ENDIAN
)
4013 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
4017 gcc_assert (cpu_index
>= 0);
4021 #ifndef HAVE_AS_POWER9
4022 if (processor_target_table
[rs6000_cpu_index
].processor
4023 == PROCESSOR_POWER9
)
4026 warning (0, "will not generate power9 instructions because "
4027 "assembler lacks power9 support");
4030 #ifndef HAVE_AS_POWER8
4031 if (processor_target_table
[rs6000_cpu_index
].processor
4032 == PROCESSOR_POWER8
)
4035 warning (0, "will not generate power8 instructions because "
4036 "assembler lacks power8 support");
4039 #ifndef HAVE_AS_POPCNTD
4040 if (processor_target_table
[rs6000_cpu_index
].processor
4041 == PROCESSOR_POWER7
)
4044 warning (0, "will not generate power7 instructions because "
4045 "assembler lacks power7 support");
4049 if (processor_target_table
[rs6000_cpu_index
].processor
4050 == PROCESSOR_POWER6
)
4053 warning (0, "will not generate power6 instructions because "
4054 "assembler lacks power6 support");
4057 #ifndef HAVE_AS_POPCNTB
4058 if (processor_target_table
[rs6000_cpu_index
].processor
4059 == PROCESSOR_POWER5
)
4062 warning (0, "will not generate power5 instructions because "
4063 "assembler lacks power5 support");
4069 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4070 const char *default_cpu
= (!TARGET_POWERPC64
4076 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
4080 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4081 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4082 with those from the cpu, except for options that were explicitly set. If
4083 we don't have a cpu, do not override the target bits set in
4087 rs6000_isa_flags
&= ~set_masks
;
4088 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
4093 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4094 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4095 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4096 to using rs6000_isa_flags, we need to do the initialization here.
4098 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4099 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4100 HOST_WIDE_INT flags
= ((TARGET_DEFAULT
) ? TARGET_DEFAULT
4101 : processor_target_table
[cpu_index
].target_enable
);
4102 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
4105 if (rs6000_tune_index
>= 0)
4106 tune_index
= rs6000_tune_index
;
4108 rs6000_tune_index
= tune_index
= cpu_index
;
4112 enum processor_type tune_proc
4113 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
4116 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
4117 if (processor_target_table
[i
].processor
== tune_proc
)
4119 rs6000_tune_index
= tune_index
= i
;
4124 gcc_assert (tune_index
>= 0);
4125 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
4127 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
4128 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
4129 || rs6000_cpu
== PROCESSOR_PPCE5500
)
4132 error ("AltiVec not supported in this target");
4135 /* If we are optimizing big endian systems for space, use the load/store
4136 multiple and string instructions. */
4137 if (BYTES_BIG_ENDIAN
&& optimize_size
)
4138 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
4139 | OPTION_MASK_STRING
);
4141 /* Don't allow -mmultiple or -mstring on little endian systems
4142 unless the cpu is a 750, because the hardware doesn't support the
4143 instructions used in little endian mode, and causes an alignment
4144 trap. The 750 does not cause an alignment trap (except when the
4145 target is unaligned). */
4147 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
4149 if (TARGET_MULTIPLE
)
4151 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
4152 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
4153 warning (0, "%qs is not supported on little endian systems",
4159 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
4160 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
4161 warning (0, "%qs is not supported on little endian systems",
4166 /* If little-endian, default to -mstrict-align on older processors.
4167 Testing for htm matches power8 and later. */
4168 if (!BYTES_BIG_ENDIAN
4169 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
4170 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
4172 /* -maltivec={le,be} implies -maltivec. */
4173 if (rs6000_altivec_element_order
!= 0)
4174 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
4176 /* Disallow -maltivec=le in big endian mode for now. This is not
4177 known to be useful for anyone. */
4178 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
4180 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4181 rs6000_altivec_element_order
= 0;
4184 if (!rs6000_fold_gimple
)
4186 "gimple folding of rs6000 builtins has been disabled.\n");
4188 /* Add some warnings for VSX. */
4191 const char *msg
= NULL
;
4192 if (!TARGET_HARD_FLOAT
|| !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
4194 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4195 msg
= N_("-mvsx requires hardware floating point");
4198 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4199 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4202 else if (TARGET_PAIRED_FLOAT
)
4203 msg
= N_("-mvsx and -mpaired are incompatible");
4204 else if (TARGET_AVOID_XFORM
> 0)
4205 msg
= N_("-mvsx needs indexed addressing");
4206 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
4207 & OPTION_MASK_ALTIVEC
))
4209 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4210 msg
= N_("-mvsx and -mno-altivec are incompatible");
4212 msg
= N_("-mno-altivec disables vsx");
4218 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4219 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4223 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4224 the -mcpu setting to enable options that conflict. */
4225 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
4226 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
4227 | OPTION_MASK_ALTIVEC
4228 | OPTION_MASK_VSX
)) != 0)
4229 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
4230 | OPTION_MASK_DIRECT_MOVE
)
4231 & ~rs6000_isa_flags_explicit
);
4233 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4234 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
4236 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4237 off all of the options that depend on those flags. */
4238 ignore_masks
= rs6000_disable_incompatible_switches ();
4240 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4241 unless the user explicitly used the -mno-<option> to disable the code. */
4242 if (TARGET_P9_VECTOR
|| TARGET_MODULO
|| TARGET_P9_DFORM_SCALAR
4243 || TARGET_P9_DFORM_VECTOR
|| TARGET_P9_DFORM_BOTH
> 0)
4244 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4245 else if (TARGET_P9_MINMAX
)
4249 if (cpu_index
== PROCESSOR_POWER9
)
4251 /* legacy behavior: allow -mcpu=power9 with certain
4252 capabilities explicitly disabled. */
4253 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4256 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4257 "for <xxx> less than power9", "-mcpu");
4259 else if ((ISA_3_0_MASKS_SERVER
& rs6000_isa_flags_explicit
)
4260 != (ISA_3_0_MASKS_SERVER
& rs6000_isa_flags
4261 & rs6000_isa_flags_explicit
))
4262 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4263 were explicitly cleared. */
4264 error ("%qs incompatible with explicitly disabled options",
4267 rs6000_isa_flags
|= ISA_3_0_MASKS_SERVER
;
4269 else if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
4270 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~ignore_masks
);
4271 else if (TARGET_VSX
)
4272 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~ignore_masks
);
4273 else if (TARGET_POPCNTD
)
4274 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~ignore_masks
);
4275 else if (TARGET_DFP
)
4276 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~ignore_masks
);
4277 else if (TARGET_CMPB
)
4278 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~ignore_masks
);
4279 else if (TARGET_FPRND
)
4280 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~ignore_masks
);
4281 else if (TARGET_POPCNTB
)
4282 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~ignore_masks
);
4283 else if (TARGET_ALTIVEC
)
4284 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~ignore_masks
);
4286 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
4288 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
4289 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4290 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
4293 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
4295 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
4296 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4297 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
4300 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
4302 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4303 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4304 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4307 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
4309 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4310 && (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
))
4311 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4312 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
) == 0)
4314 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4315 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4316 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4320 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4322 rs6000_isa_flags
|= OPTION_MASK_VSX
;
4323 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4327 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
4329 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
4330 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4331 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
4334 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4335 silently turn off quad memory mode. */
4336 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
4338 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4339 warning (0, N_("-mquad-memory requires 64-bit mode"));
4341 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
4342 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4344 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
4345 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
4348 /* Non-atomic quad memory load/store are disabled for little endian, since
4349 the words are reversed, but atomic operations can still be done by
4350 swapping the words. */
4351 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
4353 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4354 warning (0, N_("-mquad-memory is not available in little endian "
4357 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
4360 /* Assume if the user asked for normal quad memory instructions, they want
4361 the atomic versions as well, unless they explicity told us not to use quad
4362 word atomic instructions. */
4363 if (TARGET_QUAD_MEMORY
4364 && !TARGET_QUAD_MEMORY_ATOMIC
4365 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
4366 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
4368 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4369 generating power8 instructions. */
4370 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
4371 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4372 & OPTION_MASK_P8_FUSION
);
4374 /* Setting additional fusion flags turns on base fusion. */
4375 if (!TARGET_P8_FUSION
&& (TARGET_P8_FUSION_SIGN
|| TARGET_TOC_FUSION
))
4377 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4379 if (TARGET_P8_FUSION_SIGN
)
4380 error ("%qs requires %qs", "-mpower8-fusion-sign",
4383 if (TARGET_TOC_FUSION
)
4384 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4386 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4389 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4392 /* Power9 fusion is a superset over power8 fusion. */
4393 if (TARGET_P9_FUSION
&& !TARGET_P8_FUSION
)
4395 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4397 /* We prefer to not mention undocumented options in
4398 error messages. However, if users have managed to select
4399 power9-fusion without selecting power8-fusion, they
4400 already know about undocumented flags. */
4401 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4402 rs6000_isa_flags
&= ~OPTION_MASK_P9_FUSION
;
4405 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4408 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4409 generating power9 instructions. */
4410 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_FUSION
))
4411 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4412 & OPTION_MASK_P9_FUSION
);
4414 /* Power8 does not fuse sign extended loads with the addis. If we are
4415 optimizing at high levels for speed, convert a sign extended load into a
4416 zero extending load, and an explicit sign extension. */
4417 if (TARGET_P8_FUSION
4418 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
4419 && optimize_function_for_speed_p (cfun
)
4421 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
4423 /* TOC fusion requires 64-bit and medium/large code model. */
4424 if (TARGET_TOC_FUSION
&& !TARGET_POWERPC64
)
4426 rs6000_isa_flags
&= ~OPTION_MASK_TOC_FUSION
;
4427 if ((rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
) != 0)
4428 warning (0, N_("-mtoc-fusion requires 64-bit"));
4431 if (TARGET_TOC_FUSION
&& (TARGET_CMODEL
== CMODEL_SMALL
))
4433 rs6000_isa_flags
&= ~OPTION_MASK_TOC_FUSION
;
4434 if ((rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
) != 0)
4435 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4438 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4440 if (TARGET_P8_FUSION
&& !TARGET_TOC_FUSION
&& TARGET_POWERPC64
4441 && (TARGET_CMODEL
!= CMODEL_SMALL
)
4442 && !(rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
))
4443 rs6000_isa_flags
|= OPTION_MASK_TOC_FUSION
;
4445 /* ISA 3.0 vector instructions include ISA 2.07. */
4446 if (TARGET_P9_VECTOR
&& !TARGET_P8_VECTOR
)
4448 /* We prefer to not mention undocumented options in
4449 error messages. However, if users have managed to select
4450 power9-vector without selecting power8-vector, they
4451 already know about undocumented flags. */
4452 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) &&
4453 (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
))
4454 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4455 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) == 0)
4457 rs6000_isa_flags
&= ~OPTION_MASK_P9_VECTOR
;
4458 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4459 rs6000_isa_flags_explicit
|= OPTION_MASK_P9_VECTOR
;
4463 /* OPTION_MASK_P9_VECTOR is explicit and
4464 OPTION_MASK_P8_VECTOR is not explicit. */
4465 rs6000_isa_flags
|= OPTION_MASK_P8_VECTOR
;
4466 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4470 /* -mpower9-dform turns on both -mpower9-dform-scalar and
4471 -mpower9-dform-vector. */
4472 if (TARGET_P9_DFORM_BOTH
> 0)
4474 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_VECTOR
))
4475 rs6000_isa_flags
|= OPTION_MASK_P9_DFORM_VECTOR
;
4477 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_SCALAR
))
4478 rs6000_isa_flags
|= OPTION_MASK_P9_DFORM_SCALAR
;
4480 else if (TARGET_P9_DFORM_BOTH
== 0)
4482 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_VECTOR
))
4483 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM_VECTOR
;
4485 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_SCALAR
))
4486 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM_SCALAR
;
4489 /* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
4490 if ((TARGET_P9_DFORM_SCALAR
|| TARGET_P9_DFORM_VECTOR
) && !TARGET_P9_VECTOR
)
4492 /* We prefer to not mention undocumented options in
4493 error messages. However, if users have managed to select
4494 power9-dform without selecting power9-vector, they
4495 already know about undocumented flags. */
4496 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
)
4497 && (rs6000_isa_flags_explicit
& (OPTION_MASK_P9_DFORM_SCALAR
4498 | OPTION_MASK_P9_DFORM_VECTOR
)))
4499 error ("%qs requires %qs", "-mpower9-dform", "-mpower9-vector");
4500 else if (rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
)
4503 ~(OPTION_MASK_P9_DFORM_SCALAR
| OPTION_MASK_P9_DFORM_VECTOR
);
4504 rs6000_isa_flags_explicit
|=
4505 (OPTION_MASK_P9_DFORM_SCALAR
| OPTION_MASK_P9_DFORM_VECTOR
);
4509 /* We know that OPTION_MASK_P9_VECTOR is not explicit and
4510 OPTION_MASK_P9_DFORM_SCALAR or OPTION_MASK_P9_DORM_VECTOR
4512 rs6000_isa_flags
|= OPTION_MASK_P9_VECTOR
;
4513 rs6000_isa_flags_explicit
|= OPTION_MASK_P9_VECTOR
;
4517 if ((TARGET_P9_DFORM_SCALAR
|| TARGET_P9_DFORM_VECTOR
)
4518 && !TARGET_DIRECT_MOVE
)
4520 /* We prefer to not mention undocumented options in
4521 error messages. However, if users have managed to select
4522 power9-dform without selecting direct-move, they
4523 already know about undocumented flags. */
4524 if ((rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
4525 && ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_VECTOR
) ||
4526 (rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_SCALAR
) ||
4527 (TARGET_P9_DFORM_BOTH
== 1)))
4528 error ("%qs, %qs, %qs require %qs", "-mpower9-dform",
4529 "-mpower9-dform-vector", "-mpower9-dform-scalar",
4531 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
) == 0)
4533 rs6000_isa_flags
|= OPTION_MASK_DIRECT_MOVE
;
4534 rs6000_isa_flags_explicit
|= OPTION_MASK_DIRECT_MOVE
;
4539 ~(OPTION_MASK_P9_DFORM_SCALAR
| OPTION_MASK_P9_DFORM_VECTOR
);
4540 rs6000_isa_flags_explicit
|=
4541 (OPTION_MASK_P9_DFORM_SCALAR
| OPTION_MASK_P9_DFORM_VECTOR
);
4545 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4546 support. If we only have ISA 2.06 support, and the user did not specify
4547 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4548 but we don't enable the full vectorization support */
4549 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
4550 TARGET_ALLOW_MOVMISALIGN
= 1;
4552 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
4554 if (TARGET_ALLOW_MOVMISALIGN
> 0
4555 && global_options_set
.x_TARGET_ALLOW_MOVMISALIGN
)
4556 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4558 TARGET_ALLOW_MOVMISALIGN
= 0;
4561 /* Determine when unaligned vector accesses are permitted, and when
4562 they are preferred over masked Altivec loads. Note that if
4563 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4564 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4566 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4570 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4571 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4573 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4576 else if (!TARGET_ALLOW_MOVMISALIGN
)
4578 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4579 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4580 "-mallow-movmisalign");
4582 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4586 /* Set long double size before the IEEE 128-bit tests. */
4587 if (!global_options_set
.x_rs6000_long_double_type_size
)
4589 if (main_target_opt
!= NULL
4590 && (main_target_opt
->x_rs6000_long_double_type_size
4591 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
4592 error ("target attribute or pragma changes long double size");
4594 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
4597 /* Set -mabi=ieeelongdouble on some old targets. Note, AIX and Darwin
4598 explicitly redefine TARGET_IEEEQUAD to 0, so those systems will not
4599 pick up this default. */
4600 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
4601 if (!global_options_set
.x_rs6000_ieeequad
)
4602 rs6000_ieeequad
= 1;
4605 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4606 sytems, but don't enable the __float128 keyword. */
4607 if (TARGET_VSX
&& TARGET_LONG_DOUBLE_128
4608 && (TARGET_FLOAT128_ENABLE_TYPE
|| TARGET_IEEEQUAD
)
4609 && ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_TYPE
) == 0))
4610 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_TYPE
;
4612 /* IEEE 128-bit floating point requires VSX support. */
4615 if (TARGET_FLOAT128_KEYWORD
)
4617 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4618 error ("%qs requires VSX support", "-mfloat128");
4620 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4621 | OPTION_MASK_FLOAT128_KEYWORD
4622 | OPTION_MASK_FLOAT128_HW
);
4625 else if (TARGET_FLOAT128_TYPE
)
4627 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_TYPE
) != 0)
4628 error ("%qs requires VSX support", "-mfloat128-type");
4630 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4631 | OPTION_MASK_FLOAT128_KEYWORD
4632 | OPTION_MASK_FLOAT128_HW
);
4636 /* -mfloat128 and -mfloat128-hardware internally require the underlying IEEE
4637 128-bit floating point support to be enabled. */
4638 if (!TARGET_FLOAT128_TYPE
)
4640 if (TARGET_FLOAT128_KEYWORD
)
4642 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4644 error ("%qs requires %qs", "-mfloat128", "-mfloat128-type");
4645 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4646 | OPTION_MASK_FLOAT128_KEYWORD
4647 | OPTION_MASK_FLOAT128_HW
);
4650 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_TYPE
;
4653 if (TARGET_FLOAT128_HW
)
4655 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4657 error ("%qs requires %qs", "-mfloat128-hardware",
4659 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4662 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4663 | OPTION_MASK_FLOAT128_KEYWORD
4664 | OPTION_MASK_FLOAT128_HW
);
4668 /* If we have -mfloat128-type and full ISA 3.0 support, enable
4669 -mfloat128-hardware by default. However, don't enable the __float128
4670 keyword. If the user explicitly turned on -mfloat128-hardware, enable the
4671 -mfloat128 option as well if it was not already set. */
4672 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_HW
4673 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) == ISA_3_0_MASKS_IEEE
4674 && !(rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
))
4675 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_HW
;
4677 if (TARGET_FLOAT128_HW
4678 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) != ISA_3_0_MASKS_IEEE
)
4680 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4681 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4683 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4686 if (TARGET_FLOAT128_HW
&& !TARGET_64BIT
)
4688 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4689 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4691 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4694 if (TARGET_FLOAT128_HW
&& !TARGET_FLOAT128_KEYWORD
4695 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0
4696 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) == 0)
4697 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_KEYWORD
;
4699 /* Print the options after updating the defaults. */
4700 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4701 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
4703 /* E500mc does "better" if we inline more aggressively. Respect the
4704 user's opinion, though. */
4705 if (rs6000_block_move_inline_limit
== 0
4706 && (rs6000_cpu
== PROCESSOR_PPCE500MC
4707 || rs6000_cpu
== PROCESSOR_PPCE500MC64
4708 || rs6000_cpu
== PROCESSOR_PPCE5500
4709 || rs6000_cpu
== PROCESSOR_PPCE6500
))
4710 rs6000_block_move_inline_limit
= 128;
4712 /* store_one_arg depends on expand_block_move to handle at least the
4713 size of reg_parm_stack_space. */
4714 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
4715 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
4719 /* If the appropriate debug option is enabled, replace the target hooks
4720 with debug versions that call the real version and then prints
4721 debugging information. */
4722 if (TARGET_DEBUG_COST
)
4724 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
4725 targetm
.address_cost
= rs6000_debug_address_cost
;
4726 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
4729 if (TARGET_DEBUG_ADDR
)
4731 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
4732 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
4733 rs6000_secondary_reload_class_ptr
4734 = rs6000_debug_secondary_reload_class
;
4735 rs6000_secondary_memory_needed_ptr
4736 = rs6000_debug_secondary_memory_needed
;
4737 rs6000_cannot_change_mode_class_ptr
4738 = rs6000_debug_cannot_change_mode_class
;
4739 rs6000_preferred_reload_class_ptr
4740 = rs6000_debug_preferred_reload_class
;
4741 rs6000_legitimize_reload_address_ptr
4742 = rs6000_debug_legitimize_reload_address
;
4743 rs6000_mode_dependent_address_ptr
4744 = rs6000_debug_mode_dependent_address
;
4747 if (rs6000_veclibabi_name
)
4749 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
4750 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
4753 error ("unknown vectorization library ABI type (%qs) for "
4754 "%qs switch", rs6000_veclibabi_name
, "-mveclibabi=");
4760 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4761 target attribute or pragma which automatically enables both options,
4762 unless the altivec ABI was set. This is set by default for 64-bit, but
4764 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4765 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
4766 | OPTION_MASK_FLOAT128_TYPE
4767 | OPTION_MASK_FLOAT128_KEYWORD
)
4768 & ~rs6000_isa_flags_explicit
);
4770 /* Enable Altivec ABI for AIX -maltivec. */
4771 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
4773 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4774 error ("target attribute or pragma changes AltiVec ABI");
4776 rs6000_altivec_abi
= 1;
4779 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4780 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4781 be explicitly overridden in either case. */
4784 if (!global_options_set
.x_rs6000_altivec_abi
4785 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
4787 if (main_target_opt
!= NULL
&&
4788 !main_target_opt
->x_rs6000_altivec_abi
)
4789 error ("target attribute or pragma changes AltiVec ABI");
4791 rs6000_altivec_abi
= 1;
4795 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4796 So far, the only darwin64 targets are also MACH-O. */
4798 && DEFAULT_ABI
== ABI_DARWIN
4801 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
4802 error ("target attribute or pragma changes darwin64 ABI");
4805 rs6000_darwin64_abi
= 1;
4806 /* Default to natural alignment, for better performance. */
4807 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
4811 /* Place FP constants in the constant pool instead of TOC
4812 if section anchors enabled. */
4813 if (flag_section_anchors
4814 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
4815 TARGET_NO_FP_IN_TOC
= 1;
4817 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4818 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
4820 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4821 SUBTARGET_OVERRIDE_OPTIONS
;
4823 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4824 SUBSUBTARGET_OVERRIDE_OPTIONS
;
4826 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4827 SUB3TARGET_OVERRIDE_OPTIONS
;
4830 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4831 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
4833 /* For the E500 family of cores, reset the single/double FP flags to let us
4834 check that they remain constant across attributes or pragmas. Also,
4835 clear a possible request for string instructions, not supported and which
4836 we might have silently queried above for -Os.
4838 For other families, clear ISEL in case it was set implicitly.
4843 case PROCESSOR_PPC8540
:
4844 case PROCESSOR_PPC8548
:
4845 case PROCESSOR_PPCE500MC
:
4846 case PROCESSOR_PPCE500MC64
:
4847 case PROCESSOR_PPCE5500
:
4848 case PROCESSOR_PPCE6500
:
4850 rs6000_single_float
= 0;
4851 rs6000_double_float
= 0;
4853 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
4859 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
4860 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
4865 if (main_target_opt
)
4867 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
4868 error ("target attribute or pragma changes single precision floating "
4870 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
4871 error ("target attribute or pragma changes double precision floating "
4875 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
4876 && rs6000_cpu
!= PROCESSOR_POWER5
4877 && rs6000_cpu
!= PROCESSOR_POWER6
4878 && rs6000_cpu
!= PROCESSOR_POWER7
4879 && rs6000_cpu
!= PROCESSOR_POWER8
4880 && rs6000_cpu
!= PROCESSOR_POWER9
4881 && rs6000_cpu
!= PROCESSOR_PPCA2
4882 && rs6000_cpu
!= PROCESSOR_CELL
4883 && rs6000_cpu
!= PROCESSOR_PPC476
);
4884 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
4885 || rs6000_cpu
== PROCESSOR_POWER5
4886 || rs6000_cpu
== PROCESSOR_POWER7
4887 || rs6000_cpu
== PROCESSOR_POWER8
);
4888 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
4889 || rs6000_cpu
== PROCESSOR_POWER5
4890 || rs6000_cpu
== PROCESSOR_POWER6
4891 || rs6000_cpu
== PROCESSOR_POWER7
4892 || rs6000_cpu
== PROCESSOR_POWER8
4893 || rs6000_cpu
== PROCESSOR_POWER9
4894 || rs6000_cpu
== PROCESSOR_PPCE500MC
4895 || rs6000_cpu
== PROCESSOR_PPCE500MC64
4896 || rs6000_cpu
== PROCESSOR_PPCE5500
4897 || rs6000_cpu
== PROCESSOR_PPCE6500
);
4899 /* Allow debug switches to override the above settings. These are set to -1
4900 in rs6000.opt to indicate the user hasn't directly set the switch. */
4901 if (TARGET_ALWAYS_HINT
>= 0)
4902 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
4904 if (TARGET_SCHED_GROUPS
>= 0)
4905 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
4907 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
4908 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
4910 rs6000_sched_restricted_insns_priority
4911 = (rs6000_sched_groups
? 1 : 0);
4913 /* Handle -msched-costly-dep option. */
4914 rs6000_sched_costly_dep
4915 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
4917 if (rs6000_sched_costly_dep_str
)
4919 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
4920 rs6000_sched_costly_dep
= no_dep_costly
;
4921 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
4922 rs6000_sched_costly_dep
= all_deps_costly
;
4923 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
4924 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
4925 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
4926 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4928 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4929 atoi (rs6000_sched_costly_dep_str
));
4932 /* Handle -minsert-sched-nops option. */
4933 rs6000_sched_insert_nops
4934 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4936 if (rs6000_sched_insert_nops_str
)
4938 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4939 rs6000_sched_insert_nops
= sched_finish_none
;
4940 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4941 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4942 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4943 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4945 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4946 atoi (rs6000_sched_insert_nops_str
));
4949 /* Handle stack protector */
4950 if (!global_options_set
.x_rs6000_stack_protector_guard
)
4951 #ifdef TARGET_THREAD_SSP_OFFSET
4952 rs6000_stack_protector_guard
= SSP_TLS
;
4954 rs6000_stack_protector_guard
= SSP_GLOBAL
;
4957 #ifdef TARGET_THREAD_SSP_OFFSET
4958 rs6000_stack_protector_guard_offset
= TARGET_THREAD_SSP_OFFSET
;
4959 rs6000_stack_protector_guard_reg
= TARGET_64BIT
? 13 : 2;
4962 if (global_options_set
.x_rs6000_stack_protector_guard_offset_str
)
4965 const char *str
= rs6000_stack_protector_guard_offset_str
;
4968 long offset
= strtol (str
, &endp
, 0);
4969 if (!*str
|| *endp
|| errno
)
4970 error ("%qs is not a valid number in %qs", str
,
4971 "-mstack-protector-guard-offset=");
4973 if (!IN_RANGE (offset
, -0x8000, 0x7fff)
4974 || (TARGET_64BIT
&& (offset
& 3)))
4975 error ("%qs is not a valid offset in %qs", str
,
4976 "-mstack-protector-guard-offset=");
4978 rs6000_stack_protector_guard_offset
= offset
;
4981 if (global_options_set
.x_rs6000_stack_protector_guard_reg_str
)
4983 const char *str
= rs6000_stack_protector_guard_reg_str
;
4984 int reg
= decode_reg_name (str
);
4986 if (!IN_RANGE (reg
, 1, 31))
4987 error ("%qs is not a valid base register in %qs", str
,
4988 "-mstack-protector-guard-reg=");
4990 rs6000_stack_protector_guard_reg
= reg
;
4993 if (rs6000_stack_protector_guard
== SSP_TLS
4994 && !IN_RANGE (rs6000_stack_protector_guard_reg
, 1, 31))
4995 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4999 #ifdef TARGET_REGNAMES
5000 /* If the user desires alternate register names, copy in the
5001 alternate names now. */
5002 if (TARGET_REGNAMES
)
5003 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
5006 /* Set aix_struct_return last, after the ABI is determined.
5007 If -maix-struct-return or -msvr4-struct-return was explicitly
5008 used, don't override with the ABI default. */
5009 if (!global_options_set
.x_aix_struct_return
)
5010 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
5013 /* IBM XL compiler defaults to unsigned bitfields. */
5014 if (TARGET_XL_COMPAT
)
5015 flag_signed_bitfields
= 0;
5018 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
5019 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
5021 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
5023 /* We can only guarantee the availability of DI pseudo-ops when
5024 assembling for 64-bit targets. */
5027 targetm
.asm_out
.aligned_op
.di
= NULL
;
5028 targetm
.asm_out
.unaligned_op
.di
= NULL
;
5032 /* Set branch target alignment, if not optimizing for size. */
5035 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
5036 aligned 8byte to avoid misprediction by the branch predictor. */
5037 if (rs6000_cpu
== PROCESSOR_TITAN
5038 || rs6000_cpu
== PROCESSOR_CELL
)
5040 if (align_functions
<= 0)
5041 align_functions
= 8;
5042 if (align_jumps
<= 0)
5044 if (align_loops
<= 0)
5047 if (rs6000_align_branch_targets
)
5049 if (align_functions
<= 0)
5050 align_functions
= 16;
5051 if (align_jumps
<= 0)
5053 if (align_loops
<= 0)
5055 can_override_loop_align
= 1;
5059 if (align_jumps_max_skip
<= 0)
5060 align_jumps_max_skip
= 15;
5061 if (align_loops_max_skip
<= 0)
5062 align_loops_max_skip
= 15;
5065 /* Arrange to save and restore machine status around nested functions. */
5066 init_machine_status
= rs6000_init_machine_status
;
5068 /* We should always be splitting complex arguments, but we can't break
5069 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
5070 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
5071 targetm
.calls
.split_complex_arg
= NULL
;
5073 /* The AIX and ELFv1 ABIs define standard function descriptors. */
5074 if (DEFAULT_ABI
== ABI_AIX
)
5075 targetm
.calls
.custom_function_descriptors
= 0;
5078 /* Initialize rs6000_cost with the appropriate target costs. */
5080 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
5084 case PROCESSOR_RS64A
:
5085 rs6000_cost
= &rs64a_cost
;
5088 case PROCESSOR_MPCCORE
:
5089 rs6000_cost
= &mpccore_cost
;
5092 case PROCESSOR_PPC403
:
5093 rs6000_cost
= &ppc403_cost
;
5096 case PROCESSOR_PPC405
:
5097 rs6000_cost
= &ppc405_cost
;
5100 case PROCESSOR_PPC440
:
5101 rs6000_cost
= &ppc440_cost
;
5104 case PROCESSOR_PPC476
:
5105 rs6000_cost
= &ppc476_cost
;
5108 case PROCESSOR_PPC601
:
5109 rs6000_cost
= &ppc601_cost
;
5112 case PROCESSOR_PPC603
:
5113 rs6000_cost
= &ppc603_cost
;
5116 case PROCESSOR_PPC604
:
5117 rs6000_cost
= &ppc604_cost
;
5120 case PROCESSOR_PPC604e
:
5121 rs6000_cost
= &ppc604e_cost
;
5124 case PROCESSOR_PPC620
:
5125 rs6000_cost
= &ppc620_cost
;
5128 case PROCESSOR_PPC630
:
5129 rs6000_cost
= &ppc630_cost
;
5132 case PROCESSOR_CELL
:
5133 rs6000_cost
= &ppccell_cost
;
5136 case PROCESSOR_PPC750
:
5137 case PROCESSOR_PPC7400
:
5138 rs6000_cost
= &ppc750_cost
;
5141 case PROCESSOR_PPC7450
:
5142 rs6000_cost
= &ppc7450_cost
;
5145 case PROCESSOR_PPC8540
:
5146 case PROCESSOR_PPC8548
:
5147 rs6000_cost
= &ppc8540_cost
;
5150 case PROCESSOR_PPCE300C2
:
5151 case PROCESSOR_PPCE300C3
:
5152 rs6000_cost
= &ppce300c2c3_cost
;
5155 case PROCESSOR_PPCE500MC
:
5156 rs6000_cost
= &ppce500mc_cost
;
5159 case PROCESSOR_PPCE500MC64
:
5160 rs6000_cost
= &ppce500mc64_cost
;
5163 case PROCESSOR_PPCE5500
:
5164 rs6000_cost
= &ppce5500_cost
;
5167 case PROCESSOR_PPCE6500
:
5168 rs6000_cost
= &ppce6500_cost
;
5171 case PROCESSOR_TITAN
:
5172 rs6000_cost
= &titan_cost
;
5175 case PROCESSOR_POWER4
:
5176 case PROCESSOR_POWER5
:
5177 rs6000_cost
= &power4_cost
;
5180 case PROCESSOR_POWER6
:
5181 rs6000_cost
= &power6_cost
;
5184 case PROCESSOR_POWER7
:
5185 rs6000_cost
= &power7_cost
;
5188 case PROCESSOR_POWER8
:
5189 rs6000_cost
= &power8_cost
;
5192 case PROCESSOR_POWER9
:
5193 rs6000_cost
= &power9_cost
;
5196 case PROCESSOR_PPCA2
:
5197 rs6000_cost
= &ppca2_cost
;
5206 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
5207 rs6000_cost
->simultaneous_prefetches
,
5208 global_options
.x_param_values
,
5209 global_options_set
.x_param_values
);
5210 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
5211 global_options
.x_param_values
,
5212 global_options_set
.x_param_values
);
5213 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
5214 rs6000_cost
->cache_line_size
,
5215 global_options
.x_param_values
,
5216 global_options_set
.x_param_values
);
5217 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
5218 global_options
.x_param_values
,
5219 global_options_set
.x_param_values
);
5221 /* Increase loop peeling limits based on performance analysis. */
5222 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
5223 global_options
.x_param_values
,
5224 global_options_set
.x_param_values
);
5225 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
5226 global_options
.x_param_values
,
5227 global_options_set
.x_param_values
);
5229 /* Use the 'model' -fsched-pressure algorithm by default. */
5230 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
,
5231 SCHED_PRESSURE_MODEL
,
5232 global_options
.x_param_values
,
5233 global_options_set
.x_param_values
);
5235 /* If using typedef char *va_list, signal that
5236 __builtin_va_start (&ap, 0) can be optimized to
5237 ap = __builtin_next_arg (0). */
5238 if (DEFAULT_ABI
!= ABI_V4
)
5239 targetm
.expand_builtin_va_start
= NULL
;
5242 /* Set up single/double float flags.
5243 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5244 then set both flags. */
5245 if (TARGET_HARD_FLOAT
&& rs6000_single_float
== 0 && rs6000_double_float
== 0)
5246 rs6000_single_float
= rs6000_double_float
= 1;
5248 /* If not explicitly specified via option, decide whether to generate indexed
5249 load/store instructions. A value of -1 indicates that the
5250 initial value of this variable has not been overwritten. During
5251 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5252 if (TARGET_AVOID_XFORM
== -1)
5253 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5254 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5255 need indexed accesses and the type used is the scalar type of the element
5256 being loaded or stored. */
5257 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
5258 && !TARGET_ALTIVEC
);
5260 /* Set the -mrecip options. */
5261 if (rs6000_recip_name
)
5263 char *p
= ASTRDUP (rs6000_recip_name
);
5265 unsigned int mask
, i
;
5268 while ((q
= strtok (p
, ",")) != NULL
)
5279 if (!strcmp (q
, "default"))
5280 mask
= ((TARGET_RECIP_PRECISION
)
5281 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
5284 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
5285 if (!strcmp (q
, recip_options
[i
].string
))
5287 mask
= recip_options
[i
].mask
;
5291 if (i
== ARRAY_SIZE (recip_options
))
5293 error ("unknown option for %<%s=%s%>", "-mrecip", q
);
5301 rs6000_recip_control
&= ~mask
;
5303 rs6000_recip_control
|= mask
;
5307 /* Set the builtin mask of the various options used that could affect which
5308 builtins were used. In the past we used target_flags, but we've run out
5309 of bits, and some options like PAIRED are no longer in target_flags. */
5310 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
5311 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
5312 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
5313 rs6000_builtin_mask
);
5315 /* Initialize all of the registers. */
5316 rs6000_init_hard_regno_mode_ok (global_init_p
);
5318 /* Save the initial options in case the user does function specific options */
5320 target_option_default_node
= target_option_current_node
5321 = build_target_option_node (&global_options
);
5323 /* If not explicitly specified via option, decide whether to generate the
5324 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5325 if (TARGET_LINK_STACK
== -1)
5326 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
5331 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5332 define the target cpu type. */
5335 rs6000_option_override (void)
5337 (void) rs6000_option_override_internal (true);
5341 /* Implement targetm.vectorize.builtin_mask_for_load. */
5343 rs6000_builtin_mask_for_load (void)
5345 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5346 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
5347 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
5348 return altivec_builtin_mask_for_load
;
5353 /* Implement LOOP_ALIGN. */
5355 rs6000_loop_align (rtx label
)
5360 /* Don't override loop alignment if -falign-loops was specified. */
5361 if (!can_override_loop_align
)
5362 return align_loops_log
;
5364 bb
= BLOCK_FOR_INSN (label
);
5365 ninsns
= num_loop_insns(bb
->loop_father
);
5367 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5368 if (ninsns
> 4 && ninsns
<= 8
5369 && (rs6000_cpu
== PROCESSOR_POWER4
5370 || rs6000_cpu
== PROCESSOR_POWER5
5371 || rs6000_cpu
== PROCESSOR_POWER6
5372 || rs6000_cpu
== PROCESSOR_POWER7
5373 || rs6000_cpu
== PROCESSOR_POWER8
5374 || rs6000_cpu
== PROCESSOR_POWER9
))
5377 return align_loops_log
;
5380 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5382 rs6000_loop_align_max_skip (rtx_insn
*label
)
5384 return (1 << rs6000_loop_align (label
)) - 1;
5387 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5388 after applying N number of iterations. This routine does not determine
5389 how may iterations are required to reach desired alignment. */
5392 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
5399 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
5402 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
5412 /* Assuming that all other types are naturally aligned. CHECKME! */
5417 /* Return true if the vector misalignment factor is supported by the
5420 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
5427 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5430 /* Return if movmisalign pattern is not supported for this mode. */
5431 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
5434 if (misalignment
== -1)
5436 /* Misalignment factor is unknown at compile time but we know
5437 it's word aligned. */
5438 if (rs6000_vector_alignment_reachable (type
, is_packed
))
5440 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
5442 if (element_size
== 64 || element_size
== 32)
5449 /* VSX supports word-aligned vector. */
5450 if (misalignment
% 4 == 0)
5456 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5458 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
5459 tree vectype
, int misalign
)
5464 switch (type_of_cost
)
5474 case cond_branch_not_taken
:
5483 case vec_promote_demote
:
5489 case cond_branch_taken
:
5492 case unaligned_load
:
5493 if (TARGET_P9_VECTOR
)
5496 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5499 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5501 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5503 /* Double word aligned. */
5511 /* Double word aligned. */
5515 /* Unknown misalignment. */
5528 /* Misaligned loads are not supported. */
5533 case unaligned_store
:
5534 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5537 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5539 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5541 /* Double word aligned. */
5549 /* Double word aligned. */
5553 /* Unknown misalignment. */
5566 /* Misaligned stores are not supported. */
5572 /* This is a rough approximation assuming non-constant elements
5573 constructed into a vector via element insertion. FIXME:
5574 vec_construct is not granular enough for uniformly good
5575 decisions. If the initialization is a splat, this is
5576 cheaper than we estimate. Improve this someday. */
5577 elem_type
= TREE_TYPE (vectype
);
5578 /* 32-bit vectors loaded into registers are stored as double
5579 precision, so we need 2 permutes, 2 converts, and 1 merge
5580 to construct a vector of short floats from them. */
5581 if (SCALAR_FLOAT_TYPE_P (elem_type
)
5582 && TYPE_PRECISION (elem_type
) == 32)
5584 /* On POWER9, integer vector types are built up in GPRs and then
5585 use a direct move (2 cycles). For POWER8 this is even worse,
5586 as we need two direct moves and a merge, and the direct moves
5588 else if (INTEGRAL_TYPE_P (elem_type
))
5590 if (TARGET_P9_VECTOR
)
5591 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 2;
5593 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 5;
5596 /* V2DFmode doesn't need a direct move. */
5604 /* Implement targetm.vectorize.preferred_simd_mode. */
5607 rs6000_preferred_simd_mode (machine_mode mode
)
5616 if (TARGET_ALTIVEC
|| TARGET_VSX
)
5633 if (TARGET_PAIRED_FLOAT
5639 typedef struct _rs6000_cost_data
5641 struct loop
*loop_info
;
5645 /* Test for likely overcommitment of vector hardware resources. If a
5646 loop iteration is relatively large, and too large a percentage of
5647 instructions in the loop are vectorized, the cost model may not
5648 adequately reflect delays from unavailable vector resources.
5649 Penalize the loop body cost for this case. */
5652 rs6000_density_test (rs6000_cost_data
*data
)
5654 const int DENSITY_PCT_THRESHOLD
= 85;
5655 const int DENSITY_SIZE_THRESHOLD
= 70;
5656 const int DENSITY_PENALTY
= 10;
5657 struct loop
*loop
= data
->loop_info
;
5658 basic_block
*bbs
= get_loop_body (loop
);
5659 int nbbs
= loop
->num_nodes
;
5660 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
5663 for (i
= 0; i
< nbbs
; i
++)
5665 basic_block bb
= bbs
[i
];
5666 gimple_stmt_iterator gsi
;
5668 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
5670 gimple
*stmt
= gsi_stmt (gsi
);
5671 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
5673 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
5674 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
5680 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
5682 if (density_pct
> DENSITY_PCT_THRESHOLD
5683 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
5685 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
5686 if (dump_enabled_p ())
5687 dump_printf_loc (MSG_NOTE
, vect_location
,
5688 "density %d%%, cost %d exceeds threshold, penalizing "
5689 "loop body cost by %d%%", density_pct
,
5690 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
5694 /* Implement targetm.vectorize.init_cost. */
5696 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5697 instruction is needed by the vectorization. */
5698 static bool rs6000_vect_nonmem
;
5701 rs6000_init_cost (struct loop
*loop_info
)
5703 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
5704 data
->loop_info
= loop_info
;
5705 data
->cost
[vect_prologue
] = 0;
5706 data
->cost
[vect_body
] = 0;
5707 data
->cost
[vect_epilogue
] = 0;
5708 rs6000_vect_nonmem
= false;
5712 /* Implement targetm.vectorize.add_stmt_cost. */
5715 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
5716 struct _stmt_vec_info
*stmt_info
, int misalign
,
5717 enum vect_cost_model_location where
)
5719 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5720 unsigned retval
= 0;
5722 if (flag_vect_cost_model
)
5724 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
5725 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
5727 /* Statements in an inner loop relative to the loop being
5728 vectorized are weighted more heavily. The value here is
5729 arbitrary and could potentially be improved with analysis. */
5730 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
5731 count
*= 50; /* FIXME. */
5733 retval
= (unsigned) (count
* stmt_cost
);
5734 cost_data
->cost
[where
] += retval
;
5736 /* Check whether we're doing something other than just a copy loop.
5737 Not all such loops may be profitably vectorized; see
5738 rs6000_finish_cost. */
5739 if ((kind
== vec_to_scalar
|| kind
== vec_perm
5740 || kind
== vec_promote_demote
|| kind
== vec_construct
5741 || kind
== scalar_to_vec
)
5742 || (where
== vect_body
&& kind
== vector_stmt
))
5743 rs6000_vect_nonmem
= true;
5749 /* Implement targetm.vectorize.finish_cost. */
5752 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
5753 unsigned *body_cost
, unsigned *epilogue_cost
)
5755 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5757 if (cost_data
->loop_info
)
5758 rs6000_density_test (cost_data
);
5760 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5761 that require versioning for any reason. The vectorization is at
5762 best a wash inside the loop, and the versioning checks make
5763 profitability highly unlikely and potentially quite harmful. */
5764 if (cost_data
->loop_info
)
5766 loop_vec_info vec_info
= loop_vec_info_for_loop (cost_data
->loop_info
);
5767 if (!rs6000_vect_nonmem
5768 && LOOP_VINFO_VECT_FACTOR (vec_info
) == 2
5769 && LOOP_REQUIRES_VERSIONING (vec_info
))
5770 cost_data
->cost
[vect_body
] += 10000;
5773 *prologue_cost
= cost_data
->cost
[vect_prologue
];
5774 *body_cost
= cost_data
->cost
[vect_body
];
5775 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
5778 /* Implement targetm.vectorize.destroy_cost_data. */
5781 rs6000_destroy_cost_data (void *data
)
5786 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5787 library with vectorized intrinsics. */
5790 rs6000_builtin_vectorized_libmass (combined_fn fn
, tree type_out
,
5794 const char *suffix
= NULL
;
5795 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
5798 machine_mode el_mode
, in_mode
;
5801 /* Libmass is suitable for unsafe math only as it does not correctly support
5802 parts of IEEE with the required precision such as denormals. Only support
5803 it if we have VSX to use the simd d2 or f4 functions.
5804 XXX: Add variable length support. */
5805 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
5808 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5809 n
= TYPE_VECTOR_SUBPARTS (type_out
);
5810 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5811 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5812 if (el_mode
!= in_mode
5848 if (el_mode
== DFmode
&& n
== 2)
5850 bdecl
= mathfn_built_in (double_type_node
, fn
);
5851 suffix
= "d2"; /* pow -> powd2 */
5853 else if (el_mode
== SFmode
&& n
== 4)
5855 bdecl
= mathfn_built_in (float_type_node
, fn
);
5856 suffix
= "4"; /* powf -> powf4 */
5868 gcc_assert (suffix
!= NULL
);
5869 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
5873 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
5874 strcat (name
, suffix
);
5877 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
5878 else if (n_args
== 2)
5879 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
5883 /* Build a function declaration for the vectorized function. */
5884 new_fndecl
= build_decl (BUILTINS_LOCATION
,
5885 FUNCTION_DECL
, get_identifier (name
), fntype
);
5886 TREE_PUBLIC (new_fndecl
) = 1;
5887 DECL_EXTERNAL (new_fndecl
) = 1;
5888 DECL_IS_NOVOPS (new_fndecl
) = 1;
5889 TREE_READONLY (new_fndecl
) = 1;
5894 /* Returns a function decl for a vectorized version of the builtin function
5895 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5896 if it is not available. */
5899 rs6000_builtin_vectorized_function (unsigned int fn
, tree type_out
,
5902 machine_mode in_mode
, out_mode
;
5905 if (TARGET_DEBUG_BUILTIN
)
5906 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5907 combined_fn_name (combined_fn (fn
)),
5908 GET_MODE_NAME (TYPE_MODE (type_out
)),
5909 GET_MODE_NAME (TYPE_MODE (type_in
)));
5911 if (TREE_CODE (type_out
) != VECTOR_TYPE
5912 || TREE_CODE (type_in
) != VECTOR_TYPE
5913 || !TARGET_VECTORIZE_BUILTINS
)
5916 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5917 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5918 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5919 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5924 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5925 && out_mode
== DFmode
&& out_n
== 2
5926 && in_mode
== DFmode
&& in_n
== 2)
5927 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
5928 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5929 && out_mode
== SFmode
&& out_n
== 4
5930 && in_mode
== SFmode
&& in_n
== 4)
5931 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
5932 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5933 && out_mode
== SFmode
&& out_n
== 4
5934 && in_mode
== SFmode
&& in_n
== 4)
5935 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
5938 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5939 && out_mode
== DFmode
&& out_n
== 2
5940 && in_mode
== DFmode
&& in_n
== 2)
5941 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5942 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5943 && out_mode
== SFmode
&& out_n
== 4
5944 && in_mode
== SFmode
&& in_n
== 4)
5945 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5946 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5947 && out_mode
== SFmode
&& out_n
== 4
5948 && in_mode
== SFmode
&& in_n
== 4)
5949 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5952 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5953 && out_mode
== DFmode
&& out_n
== 2
5954 && in_mode
== DFmode
&& in_n
== 2)
5955 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5956 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5957 && out_mode
== SFmode
&& out_n
== 4
5958 && in_mode
== SFmode
&& in_n
== 4)
5959 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5960 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5961 && out_mode
== SFmode
&& out_n
== 4
5962 && in_mode
== SFmode
&& in_n
== 4)
5963 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5966 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5967 && out_mode
== DFmode
&& out_n
== 2
5968 && in_mode
== DFmode
&& in_n
== 2)
5969 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5970 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5971 && out_mode
== SFmode
&& out_n
== 4
5972 && in_mode
== SFmode
&& in_n
== 4)
5973 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5974 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5975 && out_mode
== SFmode
&& out_n
== 4
5976 && in_mode
== SFmode
&& in_n
== 4)
5977 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5980 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5981 && out_mode
== DFmode
&& out_n
== 2
5982 && in_mode
== DFmode
&& in_n
== 2)
5983 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5984 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5985 && out_mode
== SFmode
&& out_n
== 4
5986 && in_mode
== SFmode
&& in_n
== 4)
5987 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5988 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5989 && out_mode
== SFmode
&& out_n
== 4
5990 && in_mode
== SFmode
&& in_n
== 4)
5991 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5994 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5995 && flag_unsafe_math_optimizations
5996 && out_mode
== DFmode
&& out_n
== 2
5997 && in_mode
== DFmode
&& in_n
== 2)
5998 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5999 if (VECTOR_UNIT_VSX_P (V4SFmode
)
6000 && flag_unsafe_math_optimizations
6001 && out_mode
== SFmode
&& out_n
== 4
6002 && in_mode
== SFmode
&& in_n
== 4)
6003 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
6006 if (VECTOR_UNIT_VSX_P (V2DFmode
)
6007 && !flag_trapping_math
6008 && out_mode
== DFmode
&& out_n
== 2
6009 && in_mode
== DFmode
&& in_n
== 2)
6010 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
6011 if (VECTOR_UNIT_VSX_P (V4SFmode
)
6012 && !flag_trapping_math
6013 && out_mode
== SFmode
&& out_n
== 4
6014 && in_mode
== SFmode
&& in_n
== 4)
6015 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
6021 /* Generate calls to libmass if appropriate. */
6022 if (rs6000_veclib_handler
)
6023 return rs6000_veclib_handler (combined_fn (fn
), type_out
, type_in
);
6028 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
6031 rs6000_builtin_md_vectorized_function (tree fndecl
, tree type_out
,
6034 machine_mode in_mode
, out_mode
;
6037 if (TARGET_DEBUG_BUILTIN
)
6038 fprintf (stderr
, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
6039 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
6040 GET_MODE_NAME (TYPE_MODE (type_out
)),
6041 GET_MODE_NAME (TYPE_MODE (type_in
)));
6043 if (TREE_CODE (type_out
) != VECTOR_TYPE
6044 || TREE_CODE (type_in
) != VECTOR_TYPE
6045 || !TARGET_VECTORIZE_BUILTINS
)
6048 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
6049 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
6050 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
6051 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
6053 enum rs6000_builtins fn
6054 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
6057 case RS6000_BUILTIN_RSQRTF
:
6058 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
6059 && out_mode
== SFmode
&& out_n
== 4
6060 && in_mode
== SFmode
&& in_n
== 4)
6061 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
6063 case RS6000_BUILTIN_RSQRT
:
6064 if (VECTOR_UNIT_VSX_P (V2DFmode
)
6065 && out_mode
== DFmode
&& out_n
== 2
6066 && in_mode
== DFmode
&& in_n
== 2)
6067 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
6069 case RS6000_BUILTIN_RECIPF
:
6070 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
6071 && out_mode
== SFmode
&& out_n
== 4
6072 && in_mode
== SFmode
&& in_n
== 4)
6073 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
6075 case RS6000_BUILTIN_RECIP
:
6076 if (VECTOR_UNIT_VSX_P (V2DFmode
)
6077 && out_mode
== DFmode
&& out_n
== 2
6078 && in_mode
== DFmode
&& in_n
== 2)
6079 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
6087 /* Default CPU string for rs6000*_file_start functions. */
6088 static const char *rs6000_default_cpu
;
6090 /* Do anything needed at the start of the asm file. */
6093 rs6000_file_start (void)
6096 const char *start
= buffer
;
6097 FILE *file
= asm_out_file
;
6099 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
6101 default_file_start ();
6103 if (flag_verbose_asm
)
6105 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
6107 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
6109 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
6113 if (global_options_set
.x_rs6000_cpu_index
)
6115 fprintf (file
, "%s -mcpu=%s", start
,
6116 processor_target_table
[rs6000_cpu_index
].name
);
6120 if (global_options_set
.x_rs6000_tune_index
)
6122 fprintf (file
, "%s -mtune=%s", start
,
6123 processor_target_table
[rs6000_tune_index
].name
);
6127 if (PPC405_ERRATUM77
)
6129 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
6133 #ifdef USING_ELFOS_H
6134 switch (rs6000_sdata
)
6136 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
6137 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
6138 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
6139 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
6142 if (rs6000_sdata
&& g_switch_value
)
6144 fprintf (file
, "%s -G %d", start
,
6154 #ifdef USING_ELFOS_H
6155 if (!(rs6000_default_cpu
&& rs6000_default_cpu
[0])
6156 && !global_options_set
.x_rs6000_cpu_index
)
6158 fputs ("\t.machine ", asm_out_file
);
6159 if ((rs6000_isa_flags
& OPTION_MASK_MODULO
) != 0)
6160 fputs ("power9\n", asm_out_file
);
6161 else if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
6162 fputs ("power8\n", asm_out_file
);
6163 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
6164 fputs ("power7\n", asm_out_file
);
6165 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
6166 fputs ("power6\n", asm_out_file
);
6167 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
6168 fputs ("power5\n", asm_out_file
);
6169 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
6170 fputs ("power4\n", asm_out_file
);
6171 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
6172 fputs ("ppc64\n", asm_out_file
);
6174 fputs ("ppc\n", asm_out_file
);
6178 if (DEFAULT_ABI
== ABI_ELFv2
)
6179 fprintf (file
, "\t.abiversion 2\n");
6183 /* Return nonzero if this function is known to have a null epilogue. */
6186 direct_return (void)
6188 if (reload_completed
)
6190 rs6000_stack_t
*info
= rs6000_stack_info ();
6192 if (info
->first_gp_reg_save
== 32
6193 && info
->first_fp_reg_save
== 64
6194 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
6195 && ! info
->lr_save_p
6196 && ! info
->cr_save_p
6197 && info
->vrsave_size
== 0
6205 /* Return the number of instructions it takes to form a constant in an
6206 integer register. */
6209 num_insns_constant_wide (HOST_WIDE_INT value
)
6211 /* signed constant loadable with addi */
6212 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
6215 /* constant loadable with addis */
6216 else if ((value
& 0xffff) == 0
6217 && (value
>> 31 == -1 || value
>> 31 == 0))
6220 else if (TARGET_POWERPC64
)
6222 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
6223 HOST_WIDE_INT high
= value
>> 31;
6225 if (high
== 0 || high
== -1)
6231 return num_insns_constant_wide (high
) + 1;
6233 return num_insns_constant_wide (low
) + 1;
6235 return (num_insns_constant_wide (high
)
6236 + num_insns_constant_wide (low
) + 1);
6244 num_insns_constant (rtx op
, machine_mode mode
)
6246 HOST_WIDE_INT low
, high
;
6248 switch (GET_CODE (op
))
6251 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
6252 && rs6000_is_valid_and_mask (op
, mode
))
6255 return num_insns_constant_wide (INTVAL (op
));
6257 case CONST_WIDE_INT
:
6260 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
6261 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
6262 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
6267 if (mode
== SFmode
|| mode
== SDmode
)
6271 if (DECIMAL_FLOAT_MODE_P (mode
))
6272 REAL_VALUE_TO_TARGET_DECIMAL32
6273 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6275 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6276 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
6280 if (DECIMAL_FLOAT_MODE_P (mode
))
6281 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6283 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6284 high
= l
[WORDS_BIG_ENDIAN
== 0];
6285 low
= l
[WORDS_BIG_ENDIAN
!= 0];
6288 return (num_insns_constant_wide (low
)
6289 + num_insns_constant_wide (high
));
6292 if ((high
== 0 && low
>= 0)
6293 || (high
== -1 && low
< 0))
6294 return num_insns_constant_wide (low
);
6296 else if (rs6000_is_valid_and_mask (op
, mode
))
6300 return num_insns_constant_wide (high
) + 1;
6303 return (num_insns_constant_wide (high
)
6304 + num_insns_constant_wide (low
) + 1);
6312 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6313 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6314 corresponding element of the vector, but for V4SFmode and V2SFmode,
6315 the corresponding "float" is interpreted as an SImode integer. */
6318 const_vector_elt_as_int (rtx op
, unsigned int elt
)
6322 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6323 gcc_assert (GET_MODE (op
) != V2DImode
6324 && GET_MODE (op
) != V2DFmode
);
6326 tmp
= CONST_VECTOR_ELT (op
, elt
);
6327 if (GET_MODE (op
) == V4SFmode
6328 || GET_MODE (op
) == V2SFmode
)
6329 tmp
= gen_lowpart (SImode
, tmp
);
6330 return INTVAL (tmp
);
6333 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6334 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6335 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6336 all items are set to the same value and contain COPIES replicas of the
6337 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6338 operand and the others are set to the value of the operand's msb. */
6341 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
6343 machine_mode mode
= GET_MODE (op
);
6344 machine_mode inner
= GET_MODE_INNER (mode
);
6352 HOST_WIDE_INT splat_val
;
6353 HOST_WIDE_INT msb_val
;
6355 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
6358 nunits
= GET_MODE_NUNITS (mode
);
6359 bitsize
= GET_MODE_BITSIZE (inner
);
6360 mask
= GET_MODE_MASK (inner
);
6362 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6364 msb_val
= val
>= 0 ? 0 : -1;
6366 /* Construct the value to be splatted, if possible. If not, return 0. */
6367 for (i
= 2; i
<= copies
; i
*= 2)
6369 HOST_WIDE_INT small_val
;
6371 small_val
= splat_val
>> bitsize
;
6373 if (splat_val
!= ((HOST_WIDE_INT
)
6374 ((unsigned HOST_WIDE_INT
) small_val
<< bitsize
)
6375 | (small_val
& mask
)))
6377 splat_val
= small_val
;
6380 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6381 if (EASY_VECTOR_15 (splat_val
))
6384 /* Also check if we can splat, and then add the result to itself. Do so if
6385 the value is positive, of if the splat instruction is using OP's mode;
6386 for splat_val < 0, the splat and the add should use the same mode. */
6387 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
6388 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
6391 /* Also check if are loading up the most significant bit which can be done by
6392 loading up -1 and shifting the value left by -1. */
6393 else if (EASY_VECTOR_MSB (splat_val
, inner
))
6399 /* Check if VAL is present in every STEP-th element, and the
6400 other elements are filled with its most significant bit. */
6401 for (i
= 1; i
< nunits
; ++i
)
6403 HOST_WIDE_INT desired_val
;
6404 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
6405 if ((i
& (step
- 1)) == 0)
6408 desired_val
= msb_val
;
6410 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
6417 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6418 instruction, filling in the bottom elements with 0 or -1.
6420 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6421 for the number of zeroes to shift in, or negative for the number of 0xff
6424 OP is a CONST_VECTOR. */
6427 vspltis_shifted (rtx op
)
6429 machine_mode mode
= GET_MODE (op
);
6430 machine_mode inner
= GET_MODE_INNER (mode
);
6438 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
6441 /* We need to create pseudo registers to do the shift, so don't recognize
6442 shift vector constants after reload. */
6443 if (!can_create_pseudo_p ())
6446 nunits
= GET_MODE_NUNITS (mode
);
6447 mask
= GET_MODE_MASK (inner
);
6449 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
6451 /* Check if the value can really be the operand of a vspltis[bhw]. */
6452 if (EASY_VECTOR_15 (val
))
6455 /* Also check if we are loading up the most significant bit which can be done
6456 by loading up -1 and shifting the value left by -1. */
6457 else if (EASY_VECTOR_MSB (val
, inner
))
6463 /* Check if VAL is present in every STEP-th element until we find elements
6464 that are 0 or all 1 bits. */
6465 for (i
= 1; i
< nunits
; ++i
)
6467 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
6468 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
6470 /* If the value isn't the splat value, check for the remaining elements
6476 for (j
= i
+1; j
< nunits
; ++j
)
6478 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6479 if (const_vector_elt_as_int (op
, elt2
) != 0)
6483 return (nunits
- i
) * GET_MODE_SIZE (inner
);
6486 else if ((elt_val
& mask
) == mask
)
6488 for (j
= i
+1; j
< nunits
; ++j
)
6490 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6491 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
6495 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
6503 /* If all elements are equal, we don't need to do VLSDOI. */
6508 /* Return true if OP is of the given MODE and can be synthesized
6509 with a vspltisb, vspltish or vspltisw. */
6512 easy_altivec_constant (rtx op
, machine_mode mode
)
6514 unsigned step
, copies
;
6516 if (mode
== VOIDmode
)
6517 mode
= GET_MODE (op
);
6518 else if (mode
!= GET_MODE (op
))
6521 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6523 if (mode
== V2DFmode
)
6524 return zero_constant (op
, mode
);
6526 else if (mode
== V2DImode
)
6528 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
6529 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
6532 if (zero_constant (op
, mode
))
6535 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
6536 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
6542 /* V1TImode is a special container for TImode. Ignore for now. */
6543 else if (mode
== V1TImode
)
6546 /* Start with a vspltisw. */
6547 step
= GET_MODE_NUNITS (mode
) / 4;
6550 if (vspltis_constant (op
, step
, copies
))
6553 /* Then try with a vspltish. */
6559 if (vspltis_constant (op
, step
, copies
))
6562 /* And finally a vspltisb. */
6568 if (vspltis_constant (op
, step
, copies
))
6571 if (vspltis_shifted (op
) != 0)
6577 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6578 result is OP. Abort if it is not possible. */
6581 gen_easy_altivec_constant (rtx op
)
6583 machine_mode mode
= GET_MODE (op
);
6584 int nunits
= GET_MODE_NUNITS (mode
);
6585 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6586 unsigned step
= nunits
/ 4;
6587 unsigned copies
= 1;
6589 /* Start with a vspltisw. */
6590 if (vspltis_constant (op
, step
, copies
))
6591 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
6593 /* Then try with a vspltish. */
6599 if (vspltis_constant (op
, step
, copies
))
6600 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
6602 /* And finally a vspltisb. */
6608 if (vspltis_constant (op
, step
, copies
))
6609 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
6614 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6615 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6617 Return the number of instructions needed (1 or 2) into the address pointed
6620 Return the constant that is being split via CONSTANT_PTR. */
6623 xxspltib_constant_p (rtx op
,
6628 size_t nunits
= GET_MODE_NUNITS (mode
);
6630 HOST_WIDE_INT value
;
6633 /* Set the returned values to out of bound values. */
6634 *num_insns_ptr
= -1;
6635 *constant_ptr
= 256;
6637 if (!TARGET_P9_VECTOR
)
6640 if (mode
== VOIDmode
)
6641 mode
= GET_MODE (op
);
6643 else if (mode
!= GET_MODE (op
) && GET_MODE (op
) != VOIDmode
)
6646 /* Handle (vec_duplicate <constant>). */
6647 if (GET_CODE (op
) == VEC_DUPLICATE
)
6649 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6650 && mode
!= V2DImode
)
6653 element
= XEXP (op
, 0);
6654 if (!CONST_INT_P (element
))
6657 value
= INTVAL (element
);
6658 if (!IN_RANGE (value
, -128, 127))
6662 /* Handle (const_vector [...]). */
6663 else if (GET_CODE (op
) == CONST_VECTOR
)
6665 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6666 && mode
!= V2DImode
)
6669 element
= CONST_VECTOR_ELT (op
, 0);
6670 if (!CONST_INT_P (element
))
6673 value
= INTVAL (element
);
6674 if (!IN_RANGE (value
, -128, 127))
6677 for (i
= 1; i
< nunits
; i
++)
6679 element
= CONST_VECTOR_ELT (op
, i
);
6680 if (!CONST_INT_P (element
))
6683 if (value
!= INTVAL (element
))
6688 /* Handle integer constants being loaded into the upper part of the VSX
6689 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6690 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6691 else if (CONST_INT_P (op
))
6693 if (!SCALAR_INT_MODE_P (mode
))
6696 value
= INTVAL (op
);
6697 if (!IN_RANGE (value
, -128, 127))
6700 if (!IN_RANGE (value
, -1, 0))
6702 if (!(reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
))
6705 if (EASY_VECTOR_15 (value
))
6713 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6714 sign extend. Special case 0/-1 to allow getting any VSX register instead
6715 of an Altivec register. */
6716 if ((mode
== V4SImode
|| mode
== V8HImode
) && !IN_RANGE (value
, -1, 0)
6717 && EASY_VECTOR_15 (value
))
6720 /* Return # of instructions and the constant byte for XXSPLTIB. */
6721 if (mode
== V16QImode
)
6724 else if (IN_RANGE (value
, -1, 0))
6730 *constant_ptr
= (int) value
;
6735 output_vec_const_move (rtx
*operands
)
6743 mode
= GET_MODE (dest
);
6747 bool dest_vmx_p
= ALTIVEC_REGNO_P (REGNO (dest
));
6748 int xxspltib_value
= 256;
6751 if (zero_constant (vec
, mode
))
6753 if (TARGET_P9_VECTOR
)
6754 return "xxspltib %x0,0";
6756 else if (dest_vmx_p
)
6757 return "vspltisw %0,0";
6760 return "xxlxor %x0,%x0,%x0";
6763 if (all_ones_constant (vec
, mode
))
6765 if (TARGET_P9_VECTOR
)
6766 return "xxspltib %x0,255";
6768 else if (dest_vmx_p
)
6769 return "vspltisw %0,-1";
6771 else if (TARGET_P8_VECTOR
)
6772 return "xxlorc %x0,%x0,%x0";
6778 if (TARGET_P9_VECTOR
6779 && xxspltib_constant_p (vec
, mode
, &num_insns
, &xxspltib_value
))
6783 operands
[2] = GEN_INT (xxspltib_value
& 0xff);
6784 return "xxspltib %x0,%2";
6795 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest
)));
6796 if (zero_constant (vec
, mode
))
6797 return "vspltisw %0,0";
6799 if (all_ones_constant (vec
, mode
))
6800 return "vspltisw %0,-1";
6802 /* Do we need to construct a value using VSLDOI? */
6803 shift
= vspltis_shifted (vec
);
6807 splat_vec
= gen_easy_altivec_constant (vec
);
6808 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
6809 operands
[1] = XEXP (splat_vec
, 0);
6810 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
6813 switch (GET_MODE (splat_vec
))
6816 return "vspltisw %0,%1";
6819 return "vspltish %0,%1";
6822 return "vspltisb %0,%1";
6832 /* Initialize TARGET of vector PAIRED to VALS. */
6835 paired_expand_vector_init (rtx target
, rtx vals
)
6837 machine_mode mode
= GET_MODE (target
);
6838 int n_elts
= GET_MODE_NUNITS (mode
);
6840 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
6843 for (i
= 0; i
< n_elts
; ++i
)
6845 x
= XVECEXP (vals
, 0, i
);
6846 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6851 /* Load from constant pool. */
6852 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
6858 /* The vector is initialized only with non-constants. */
6859 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
6860 XVECEXP (vals
, 0, 1));
6862 emit_move_insn (target
, new_rtx
);
6866 /* One field is non-constant and the other one is a constant. Load the
6867 constant from the constant pool and use ps_merge instruction to
6868 construct the whole vector. */
6869 op1
= XVECEXP (vals
, 0, 0);
6870 op2
= XVECEXP (vals
, 0, 1);
6872 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
6874 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
6875 emit_move_insn (tmp
, constant_op
);
6877 if (CONSTANT_P (op1
))
6878 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
6880 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
6882 emit_move_insn (target
, new_rtx
);
6886 paired_expand_vector_move (rtx operands
[])
6888 rtx op0
= operands
[0], op1
= operands
[1];
6890 emit_move_insn (op0
, op1
);
6893 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6894 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6895 operands for the relation operation COND. This is a recursive
6899 paired_emit_vector_compare (enum rtx_code rcode
,
6900 rtx dest
, rtx op0
, rtx op1
,
6901 rtx cc_op0
, rtx cc_op1
)
6903 rtx tmp
= gen_reg_rtx (V2SFmode
);
6906 gcc_assert (TARGET_PAIRED_FLOAT
);
6907 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
6913 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6917 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
6918 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
6922 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
6925 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6928 tmp1
= gen_reg_rtx (V2SFmode
);
6929 max
= gen_reg_rtx (V2SFmode
);
6930 min
= gen_reg_rtx (V2SFmode
);
6931 gen_reg_rtx (V2SFmode
);
6933 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
6934 emit_insn (gen_selv2sf4
6935 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
6936 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
6937 emit_insn (gen_selv2sf4
6938 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
6939 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
6940 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
6943 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6946 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6949 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6952 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6955 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6964 /* Emit vector conditional expression.
6965 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6966 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6969 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
6970 rtx cond
, rtx cc_op0
, rtx cc_op1
)
6972 enum rtx_code rcode
= GET_CODE (cond
);
6974 if (!TARGET_PAIRED_FLOAT
)
6977 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
6982 /* Initialize vector TARGET to VALS. */
6985 rs6000_expand_vector_init (rtx target
, rtx vals
)
6987 machine_mode mode
= GET_MODE (target
);
6988 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6989 int n_elts
= GET_MODE_NUNITS (mode
);
6990 int n_var
= 0, one_var
= -1;
6991 bool all_same
= true, all_const_zero
= true;
6995 for (i
= 0; i
< n_elts
; ++i
)
6997 x
= XVECEXP (vals
, 0, i
);
6998 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6999 ++n_var
, one_var
= i
;
7000 else if (x
!= CONST0_RTX (inner_mode
))
7001 all_const_zero
= false;
7003 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
7009 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
7010 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
7011 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
7013 /* Zero register. */
7014 emit_move_insn (target
, CONST0_RTX (mode
));
7017 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
7019 /* Splat immediate. */
7020 emit_insn (gen_rtx_SET (target
, const_vec
));
7025 /* Load from constant pool. */
7026 emit_move_insn (target
, const_vec
);
7031 /* Double word values on VSX can use xxpermdi or lxvdsx. */
7032 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
7036 size_t num_elements
= all_same
? 1 : 2;
7037 for (i
= 0; i
< num_elements
; i
++)
7039 op
[i
] = XVECEXP (vals
, 0, i
);
7040 /* Just in case there is a SUBREG with a smaller mode, do a
7042 if (GET_MODE (op
[i
]) != inner_mode
)
7044 rtx tmp
= gen_reg_rtx (inner_mode
);
7045 convert_move (tmp
, op
[i
], 0);
7048 /* Allow load with splat double word. */
7049 else if (MEM_P (op
[i
]))
7052 op
[i
] = force_reg (inner_mode
, op
[i
]);
7054 else if (!REG_P (op
[i
]))
7055 op
[i
] = force_reg (inner_mode
, op
[i
]);
7060 if (mode
== V2DFmode
)
7061 emit_insn (gen_vsx_splat_v2df (target
, op
[0]));
7063 emit_insn (gen_vsx_splat_v2di (target
, op
[0]));
7067 if (mode
== V2DFmode
)
7068 emit_insn (gen_vsx_concat_v2df (target
, op
[0], op
[1]));
7070 emit_insn (gen_vsx_concat_v2di (target
, op
[0], op
[1]));
7075 /* Special case initializing vector int if we are on 64-bit systems with
7076 direct move or we have the ISA 3.0 instructions. */
7077 if (mode
== V4SImode
&& VECTOR_MEM_VSX_P (V4SImode
)
7078 && TARGET_DIRECT_MOVE_64BIT
)
7082 rtx element0
= XVECEXP (vals
, 0, 0);
7083 if (MEM_P (element0
))
7084 element0
= rs6000_address_for_fpconvert (element0
);
7086 element0
= force_reg (SImode
, element0
);
7088 if (TARGET_P9_VECTOR
)
7089 emit_insn (gen_vsx_splat_v4si (target
, element0
));
7092 rtx tmp
= gen_reg_rtx (DImode
);
7093 emit_insn (gen_zero_extendsidi2 (tmp
, element0
));
7094 emit_insn (gen_vsx_splat_v4si_di (target
, tmp
));
7103 for (i
= 0; i
< 4; i
++)
7105 elements
[i
] = XVECEXP (vals
, 0, i
);
7106 if (!CONST_INT_P (elements
[i
]) && !REG_P (elements
[i
]))
7107 elements
[i
] = copy_to_mode_reg (SImode
, elements
[i
]);
7110 emit_insn (gen_vsx_init_v4si (target
, elements
[0], elements
[1],
7111 elements
[2], elements
[3]));
7116 /* With single precision floating point on VSX, know that internally single
7117 precision is actually represented as a double, and either make 2 V2DF
7118 vectors, and convert these vectors to single precision, or do one
7119 conversion, and splat the result to the other elements. */
7120 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (V4SFmode
))
7124 rtx element0
= XVECEXP (vals
, 0, 0);
7126 if (TARGET_P9_VECTOR
)
7128 if (MEM_P (element0
))
7129 element0
= rs6000_address_for_fpconvert (element0
);
7131 emit_insn (gen_vsx_splat_v4sf (target
, element0
));
7136 rtx freg
= gen_reg_rtx (V4SFmode
);
7137 rtx sreg
= force_reg (SFmode
, element0
);
7138 rtx cvt
= (TARGET_XSCVDPSPN
7139 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
7140 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
7143 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
,
7149 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
7150 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
7151 rtx flt_even
= gen_reg_rtx (V4SFmode
);
7152 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
7153 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
7154 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
7155 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
7156 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
7158 /* Use VMRGEW if we can instead of doing a permute. */
7159 if (TARGET_P8_VECTOR
)
7161 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op2
));
7162 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op1
, op3
));
7163 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
7164 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
7165 if (BYTES_BIG_ENDIAN
)
7166 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_even
, flt_odd
));
7168 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_odd
, flt_even
));
7172 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
7173 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
7174 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
7175 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
7176 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
7182 /* Special case initializing vector short/char that are splats if we are on
7183 64-bit systems with direct move. */
7184 if (all_same
&& TARGET_DIRECT_MOVE_64BIT
7185 && (mode
== V16QImode
|| mode
== V8HImode
))
7187 rtx op0
= XVECEXP (vals
, 0, 0);
7188 rtx di_tmp
= gen_reg_rtx (DImode
);
7191 op0
= force_reg (GET_MODE_INNER (mode
), op0
);
7193 if (mode
== V16QImode
)
7195 emit_insn (gen_zero_extendqidi2 (di_tmp
, op0
));
7196 emit_insn (gen_vsx_vspltb_di (target
, di_tmp
));
7200 if (mode
== V8HImode
)
7202 emit_insn (gen_zero_extendhidi2 (di_tmp
, op0
));
7203 emit_insn (gen_vsx_vsplth_di (target
, di_tmp
));
7208 /* Store value to stack temp. Load vector element. Splat. However, splat
7209 of 64-bit items is not supported on Altivec. */
7210 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
7212 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
7213 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
7214 XVECEXP (vals
, 0, 0));
7215 x
= gen_rtx_UNSPEC (VOIDmode
,
7216 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
7217 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
7219 gen_rtx_SET (target
, mem
),
7221 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
7222 gen_rtx_PARALLEL (VOIDmode
,
7223 gen_rtvec (1, const0_rtx
)));
7224 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
7228 /* One field is non-constant. Load constant then overwrite
7232 rtx copy
= copy_rtx (vals
);
7234 /* Load constant part of vector, substitute neighboring value for
7236 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
7237 rs6000_expand_vector_init (target
, copy
);
7239 /* Insert variable. */
7240 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
7244 /* Construct the vector in memory one field at a time
7245 and load the whole vector. */
7246 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
7247 for (i
= 0; i
< n_elts
; i
++)
7248 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
7249 i
* GET_MODE_SIZE (inner_mode
)),
7250 XVECEXP (vals
, 0, i
));
7251 emit_move_insn (target
, mem
);
7254 /* Set field ELT of TARGET to VAL. */
7257 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
7259 machine_mode mode
= GET_MODE (target
);
7260 machine_mode inner_mode
= GET_MODE_INNER (mode
);
7261 rtx reg
= gen_reg_rtx (mode
);
7263 int width
= GET_MODE_SIZE (inner_mode
);
7266 val
= force_reg (GET_MODE (val
), val
);
7268 if (VECTOR_MEM_VSX_P (mode
))
7270 rtx insn
= NULL_RTX
;
7271 rtx elt_rtx
= GEN_INT (elt
);
7273 if (mode
== V2DFmode
)
7274 insn
= gen_vsx_set_v2df (target
, target
, val
, elt_rtx
);
7276 else if (mode
== V2DImode
)
7277 insn
= gen_vsx_set_v2di (target
, target
, val
, elt_rtx
);
7279 else if (TARGET_P9_VECTOR
&& TARGET_POWERPC64
)
7281 if (mode
== V4SImode
)
7282 insn
= gen_vsx_set_v4si_p9 (target
, target
, val
, elt_rtx
);
7283 else if (mode
== V8HImode
)
7284 insn
= gen_vsx_set_v8hi_p9 (target
, target
, val
, elt_rtx
);
7285 else if (mode
== V16QImode
)
7286 insn
= gen_vsx_set_v16qi_p9 (target
, target
, val
, elt_rtx
);
7287 else if (mode
== V4SFmode
)
7288 insn
= gen_vsx_set_v4sf_p9 (target
, target
, val
, elt_rtx
);
7298 /* Simplify setting single element vectors like V1TImode. */
7299 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
7301 emit_move_insn (target
, gen_lowpart (mode
, val
));
7305 /* Load single variable value. */
7306 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
7307 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
7308 x
= gen_rtx_UNSPEC (VOIDmode
,
7309 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
7310 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
7312 gen_rtx_SET (reg
, mem
),
7315 /* Linear sequence. */
7316 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
7317 for (i
= 0; i
< 16; ++i
)
7318 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
7320 /* Set permute mask to insert element into target. */
7321 for (i
= 0; i
< width
; ++i
)
7322 XVECEXP (mask
, 0, elt
*width
+ i
)
7323 = GEN_INT (i
+ 0x10);
7324 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
7326 if (BYTES_BIG_ENDIAN
)
7327 x
= gen_rtx_UNSPEC (mode
,
7328 gen_rtvec (3, target
, reg
,
7329 force_reg (V16QImode
, x
)),
7333 if (TARGET_P9_VECTOR
)
7334 x
= gen_rtx_UNSPEC (mode
,
7335 gen_rtvec (3, target
, reg
,
7336 force_reg (V16QImode
, x
)),
7340 /* Invert selector. We prefer to generate VNAND on P8 so
7341 that future fusion opportunities can kick in, but must
7342 generate VNOR elsewhere. */
7343 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
7344 rtx iorx
= (TARGET_P8_VECTOR
7345 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
7346 : gen_rtx_AND (V16QImode
, notx
, notx
));
7347 rtx tmp
= gen_reg_rtx (V16QImode
);
7348 emit_insn (gen_rtx_SET (tmp
, iorx
));
7350 /* Permute with operands reversed and adjusted selector. */
7351 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
7356 emit_insn (gen_rtx_SET (target
, x
));
7359 /* Extract field ELT from VEC into TARGET. */
7362 rs6000_expand_vector_extract (rtx target
, rtx vec
, rtx elt
)
7364 machine_mode mode
= GET_MODE (vec
);
7365 machine_mode inner_mode
= GET_MODE_INNER (mode
);
7368 if (VECTOR_MEM_VSX_P (mode
) && CONST_INT_P (elt
))
7375 gcc_assert (INTVAL (elt
) == 0 && inner_mode
== TImode
);
7376 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
7379 emit_insn (gen_vsx_extract_v2df (target
, vec
, elt
));
7382 emit_insn (gen_vsx_extract_v2di (target
, vec
, elt
));
7385 emit_insn (gen_vsx_extract_v4sf (target
, vec
, elt
));
7388 if (TARGET_DIRECT_MOVE_64BIT
)
7390 emit_insn (gen_vsx_extract_v16qi (target
, vec
, elt
));
7396 if (TARGET_DIRECT_MOVE_64BIT
)
7398 emit_insn (gen_vsx_extract_v8hi (target
, vec
, elt
));
7404 if (TARGET_DIRECT_MOVE_64BIT
)
7406 emit_insn (gen_vsx_extract_v4si (target
, vec
, elt
));
7412 else if (VECTOR_MEM_VSX_P (mode
) && !CONST_INT_P (elt
)
7413 && TARGET_DIRECT_MOVE_64BIT
)
7415 if (GET_MODE (elt
) != DImode
)
7417 rtx tmp
= gen_reg_rtx (DImode
);
7418 convert_move (tmp
, elt
, 0);
7421 else if (!REG_P (elt
))
7422 elt
= force_reg (DImode
, elt
);
7427 emit_insn (gen_vsx_extract_v2df_var (target
, vec
, elt
));
7431 emit_insn (gen_vsx_extract_v2di_var (target
, vec
, elt
));
7435 emit_insn (gen_vsx_extract_v4sf_var (target
, vec
, elt
));
7439 emit_insn (gen_vsx_extract_v4si_var (target
, vec
, elt
));
7443 emit_insn (gen_vsx_extract_v8hi_var (target
, vec
, elt
));
7447 emit_insn (gen_vsx_extract_v16qi_var (target
, vec
, elt
));
7455 gcc_assert (CONST_INT_P (elt
));
7457 /* Allocate mode-sized buffer. */
7458 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
7460 emit_move_insn (mem
, vec
);
7462 /* Add offset to field within buffer matching vector element. */
7463 mem
= adjust_address_nv (mem
, inner_mode
,
7464 INTVAL (elt
) * GET_MODE_SIZE (inner_mode
));
7466 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
7469 /* Helper function to return the register number of a RTX. */
7471 regno_or_subregno (rtx op
)
7475 else if (SUBREG_P (op
))
7476 return subreg_regno (op
);
7481 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7482 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7483 temporary (BASE_TMP) to fixup the address. Return the new memory address
7484 that is valid for reads or writes to a given register (SCALAR_REG). */
7487 rs6000_adjust_vec_address (rtx scalar_reg
,
7491 machine_mode scalar_mode
)
7493 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7494 rtx addr
= XEXP (mem
, 0);
7499 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7500 gcc_assert (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
);
7502 /* Calculate what we need to add to the address to get the element
7504 if (CONST_INT_P (element
))
7505 element_offset
= GEN_INT (INTVAL (element
) * scalar_size
);
7508 int byte_shift
= exact_log2 (scalar_size
);
7509 gcc_assert (byte_shift
>= 0);
7511 if (byte_shift
== 0)
7512 element_offset
= element
;
7516 if (TARGET_POWERPC64
)
7517 emit_insn (gen_ashldi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
7519 emit_insn (gen_ashlsi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
7521 element_offset
= base_tmp
;
7525 /* Create the new address pointing to the element within the vector. If we
7526 are adding 0, we don't have to change the address. */
7527 if (element_offset
== const0_rtx
)
7530 /* A simple indirect address can be converted into a reg + offset
7532 else if (REG_P (addr
) || SUBREG_P (addr
))
7533 new_addr
= gen_rtx_PLUS (Pmode
, addr
, element_offset
);
7535 /* Optimize D-FORM addresses with constant offset with a constant element, to
7536 include the element offset in the address directly. */
7537 else if (GET_CODE (addr
) == PLUS
)
7539 rtx op0
= XEXP (addr
, 0);
7540 rtx op1
= XEXP (addr
, 1);
7543 gcc_assert (REG_P (op0
) || SUBREG_P (op0
));
7544 if (CONST_INT_P (op1
) && CONST_INT_P (element_offset
))
7546 HOST_WIDE_INT offset
= INTVAL (op1
) + INTVAL (element_offset
);
7547 rtx offset_rtx
= GEN_INT (offset
);
7549 if (IN_RANGE (offset
, -32768, 32767)
7550 && (scalar_size
< 8 || (offset
& 0x3) == 0))
7551 new_addr
= gen_rtx_PLUS (Pmode
, op0
, offset_rtx
);
7554 emit_move_insn (base_tmp
, offset_rtx
);
7555 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7560 bool op1_reg_p
= (REG_P (op1
) || SUBREG_P (op1
));
7561 bool ele_reg_p
= (REG_P (element_offset
) || SUBREG_P (element_offset
));
7563 /* Note, ADDI requires the register being added to be a base
7564 register. If the register was R0, load it up into the temporary
7567 && (ele_reg_p
|| reg_or_subregno (op1
) != FIRST_GPR_REGNO
))
7569 insn
= gen_add3_insn (base_tmp
, op1
, element_offset
);
7570 gcc_assert (insn
!= NULL_RTX
);
7575 && reg_or_subregno (element_offset
) != FIRST_GPR_REGNO
)
7577 insn
= gen_add3_insn (base_tmp
, element_offset
, op1
);
7578 gcc_assert (insn
!= NULL_RTX
);
7584 emit_move_insn (base_tmp
, op1
);
7585 emit_insn (gen_add2_insn (base_tmp
, element_offset
));
7588 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7594 emit_move_insn (base_tmp
, addr
);
7595 new_addr
= gen_rtx_PLUS (Pmode
, base_tmp
, element_offset
);
7598 /* If we have a PLUS, we need to see whether the particular register class
7599 allows for D-FORM or X-FORM addressing. */
7600 if (GET_CODE (new_addr
) == PLUS
)
7602 rtx op1
= XEXP (new_addr
, 1);
7603 addr_mask_type addr_mask
;
7604 int scalar_regno
= regno_or_subregno (scalar_reg
);
7606 gcc_assert (scalar_regno
< FIRST_PSEUDO_REGISTER
);
7607 if (INT_REGNO_P (scalar_regno
))
7608 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_GPR
];
7610 else if (FP_REGNO_P (scalar_regno
))
7611 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_FPR
];
7613 else if (ALTIVEC_REGNO_P (scalar_regno
))
7614 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_VMX
];
7619 if (REG_P (op1
) || SUBREG_P (op1
))
7620 valid_addr_p
= (addr_mask
& RELOAD_REG_INDEXED
) != 0;
7622 valid_addr_p
= (addr_mask
& RELOAD_REG_OFFSET
) != 0;
7625 else if (REG_P (new_addr
) || SUBREG_P (new_addr
))
7626 valid_addr_p
= true;
7629 valid_addr_p
= false;
7633 emit_move_insn (base_tmp
, new_addr
);
7634 new_addr
= base_tmp
;
7637 return change_address (mem
, scalar_mode
, new_addr
);
7640 /* Split a variable vec_extract operation into the component instructions. */
7643 rs6000_split_vec_extract_var (rtx dest
, rtx src
, rtx element
, rtx tmp_gpr
,
7646 machine_mode mode
= GET_MODE (src
);
7647 machine_mode scalar_mode
= GET_MODE (dest
);
7648 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7649 int byte_shift
= exact_log2 (scalar_size
);
7651 gcc_assert (byte_shift
>= 0);
7653 /* If we are given a memory address, optimize to load just the element. We
7654 don't have to adjust the vector element number on little endian
7658 gcc_assert (REG_P (tmp_gpr
));
7659 emit_move_insn (dest
, rs6000_adjust_vec_address (dest
, src
, element
,
7660 tmp_gpr
, scalar_mode
));
7664 else if (REG_P (src
) || SUBREG_P (src
))
7666 int bit_shift
= byte_shift
+ 3;
7668 int dest_regno
= regno_or_subregno (dest
);
7669 int src_regno
= regno_or_subregno (src
);
7670 int element_regno
= regno_or_subregno (element
);
7672 gcc_assert (REG_P (tmp_gpr
));
7674 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7675 a general purpose register. */
7676 if (TARGET_P9_VECTOR
7677 && (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
7678 && INT_REGNO_P (dest_regno
)
7679 && ALTIVEC_REGNO_P (src_regno
)
7680 && INT_REGNO_P (element_regno
))
7682 rtx dest_si
= gen_rtx_REG (SImode
, dest_regno
);
7683 rtx element_si
= gen_rtx_REG (SImode
, element_regno
);
7685 if (mode
== V16QImode
)
7686 emit_insn (VECTOR_ELT_ORDER_BIG
7687 ? gen_vextublx (dest_si
, element_si
, src
)
7688 : gen_vextubrx (dest_si
, element_si
, src
));
7690 else if (mode
== V8HImode
)
7692 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7693 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const1_rtx
));
7694 emit_insn (VECTOR_ELT_ORDER_BIG
7695 ? gen_vextuhlx (dest_si
, tmp_gpr_si
, src
)
7696 : gen_vextuhrx (dest_si
, tmp_gpr_si
, src
));
7702 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7703 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const2_rtx
));
7704 emit_insn (VECTOR_ELT_ORDER_BIG
7705 ? gen_vextuwlx (dest_si
, tmp_gpr_si
, src
)
7706 : gen_vextuwrx (dest_si
, tmp_gpr_si
, src
));
7713 gcc_assert (REG_P (tmp_altivec
));
7715 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7716 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7717 will shift the element into the upper position (adding 3 to convert a
7718 byte shift into a bit shift). */
7719 if (scalar_size
== 8)
7721 if (!VECTOR_ELT_ORDER_BIG
)
7723 emit_insn (gen_xordi3 (tmp_gpr
, element
, const1_rtx
));
7729 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7731 emit_insn (gen_rtx_SET (tmp_gpr
,
7732 gen_rtx_AND (DImode
,
7733 gen_rtx_ASHIFT (DImode
,
7740 if (!VECTOR_ELT_ORDER_BIG
)
7742 rtx num_ele_m1
= GEN_INT (GET_MODE_NUNITS (mode
) - 1);
7744 emit_insn (gen_anddi3 (tmp_gpr
, element
, num_ele_m1
));
7745 emit_insn (gen_subdi3 (tmp_gpr
, num_ele_m1
, tmp_gpr
));
7751 emit_insn (gen_ashldi3 (tmp_gpr
, element2
, GEN_INT (bit_shift
)));
7754 /* Get the value into the lower byte of the Altivec register where VSLO
7756 if (TARGET_P9_VECTOR
)
7757 emit_insn (gen_vsx_splat_v2di (tmp_altivec
, tmp_gpr
));
7758 else if (can_create_pseudo_p ())
7759 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_gpr
, tmp_gpr
));
7762 rtx tmp_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7763 emit_move_insn (tmp_di
, tmp_gpr
);
7764 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_di
, tmp_di
));
7767 /* Do the VSLO to get the value into the final location. */
7771 emit_insn (gen_vsx_vslo_v2df (dest
, src
, tmp_altivec
));
7775 emit_insn (gen_vsx_vslo_v2di (dest
, src
, tmp_altivec
));
7780 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7781 rtx tmp_altivec_v4sf
= gen_rtx_REG (V4SFmode
, REGNO (tmp_altivec
));
7782 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7783 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7786 emit_insn (gen_vsx_xscvspdp_scalar2 (dest
, tmp_altivec_v4sf
));
7794 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7795 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7796 rtx tmp_gpr_di
= gen_rtx_REG (DImode
, REGNO (dest
));
7797 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7799 emit_move_insn (tmp_gpr_di
, tmp_altivec_di
);
7800 emit_insn (gen_ashrdi3 (tmp_gpr_di
, tmp_gpr_di
,
7801 GEN_INT (64 - (8 * scalar_size
))));
7815 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7816 two SImode values. */
7819 rs6000_split_v4si_init_di_reg (rtx dest
, rtx si1
, rtx si2
, rtx tmp
)
7821 const unsigned HOST_WIDE_INT mask_32bit
= HOST_WIDE_INT_C (0xffffffff);
7823 if (CONST_INT_P (si1
) && CONST_INT_P (si2
))
7825 unsigned HOST_WIDE_INT const1
= (UINTVAL (si1
) & mask_32bit
) << 32;
7826 unsigned HOST_WIDE_INT const2
= UINTVAL (si2
) & mask_32bit
;
7828 emit_move_insn (dest
, GEN_INT (const1
| const2
));
7832 /* Put si1 into upper 32-bits of dest. */
7833 if (CONST_INT_P (si1
))
7834 emit_move_insn (dest
, GEN_INT ((UINTVAL (si1
) & mask_32bit
) << 32));
7837 /* Generate RLDIC. */
7838 rtx si1_di
= gen_rtx_REG (DImode
, regno_or_subregno (si1
));
7839 rtx shift_rtx
= gen_rtx_ASHIFT (DImode
, si1_di
, GEN_INT (32));
7840 rtx mask_rtx
= GEN_INT (mask_32bit
<< 32);
7841 rtx and_rtx
= gen_rtx_AND (DImode
, shift_rtx
, mask_rtx
);
7842 gcc_assert (!reg_overlap_mentioned_p (dest
, si1
));
7843 emit_insn (gen_rtx_SET (dest
, and_rtx
));
7846 /* Put si2 into the temporary. */
7847 gcc_assert (!reg_overlap_mentioned_p (dest
, tmp
));
7848 if (CONST_INT_P (si2
))
7849 emit_move_insn (tmp
, GEN_INT (UINTVAL (si2
) & mask_32bit
));
7851 emit_insn (gen_zero_extendsidi2 (tmp
, si2
));
7853 /* Combine the two parts. */
7854 emit_insn (gen_iordi3 (dest
, dest
, tmp
));
7858 /* Split a V4SI initialization. */
7861 rs6000_split_v4si_init (rtx operands
[])
7863 rtx dest
= operands
[0];
7865 /* Destination is a GPR, build up the two DImode parts in place. */
7866 if (REG_P (dest
) || SUBREG_P (dest
))
7868 int d_regno
= regno_or_subregno (dest
);
7869 rtx scalar1
= operands
[1];
7870 rtx scalar2
= operands
[2];
7871 rtx scalar3
= operands
[3];
7872 rtx scalar4
= operands
[4];
7873 rtx tmp1
= operands
[5];
7874 rtx tmp2
= operands
[6];
7876 /* Even though we only need one temporary (plus the destination, which
7877 has an early clobber constraint, try to use two temporaries, one for
7878 each double word created. That way the 2nd insn scheduling pass can
7879 rearrange things so the two parts are done in parallel. */
7880 if (BYTES_BIG_ENDIAN
)
7882 rtx di_lo
= gen_rtx_REG (DImode
, d_regno
);
7883 rtx di_hi
= gen_rtx_REG (DImode
, d_regno
+ 1);
7884 rs6000_split_v4si_init_di_reg (di_lo
, scalar1
, scalar2
, tmp1
);
7885 rs6000_split_v4si_init_di_reg (di_hi
, scalar3
, scalar4
, tmp2
);
7889 rtx di_lo
= gen_rtx_REG (DImode
, d_regno
+ 1);
7890 rtx di_hi
= gen_rtx_REG (DImode
, d_regno
);
7891 gcc_assert (!VECTOR_ELT_ORDER_BIG
);
7892 rs6000_split_v4si_init_di_reg (di_lo
, scalar4
, scalar3
, tmp1
);
7893 rs6000_split_v4si_init_di_reg (di_hi
, scalar2
, scalar1
, tmp2
);
7902 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7903 selects whether the alignment is abi mandated, optional, or
7904 both abi and optional alignment. */
7907 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
7909 if (how
!= align_opt
)
7911 if (TREE_CODE (type
) == VECTOR_TYPE
)
7913 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
)))
7918 else if (align
< 128)
7923 if (how
!= align_abi
)
7925 if (TREE_CODE (type
) == ARRAY_TYPE
7926 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
7928 if (align
< BITS_PER_WORD
)
7929 align
= BITS_PER_WORD
;
7936 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7939 rs6000_special_adjust_field_align_p (tree type
, unsigned int computed
)
7941 if (TARGET_ALTIVEC
&& TREE_CODE (type
) == VECTOR_TYPE
)
7943 if (computed
!= 128)
7946 if (!warned
&& warn_psabi
)
7949 inform (input_location
,
7950 "the layout of aggregates containing vectors with"
7951 " %d-byte alignment has changed in GCC 5",
7952 computed
/ BITS_PER_UNIT
);
7955 /* In current GCC there is no special case. */
7962 /* AIX increases natural record alignment to doubleword if the first
7963 field is an FP double while the FP fields remain word aligned. */
7966 rs6000_special_round_type_align (tree type
, unsigned int computed
,
7967 unsigned int specified
)
7969 unsigned int align
= MAX (computed
, specified
);
7970 tree field
= TYPE_FIELDS (type
);
7972 /* Skip all non field decls */
7973 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7974 field
= DECL_CHAIN (field
);
7976 if (field
!= NULL
&& field
!= type
)
7978 type
= TREE_TYPE (field
);
7979 while (TREE_CODE (type
) == ARRAY_TYPE
)
7980 type
= TREE_TYPE (type
);
7982 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
7983 align
= MAX (align
, 64);
7989 /* Darwin increases record alignment to the natural alignment of
7993 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
7994 unsigned int specified
)
7996 unsigned int align
= MAX (computed
, specified
);
7998 if (TYPE_PACKED (type
))
8001 /* Find the first field, looking down into aggregates. */
8003 tree field
= TYPE_FIELDS (type
);
8004 /* Skip all non field decls */
8005 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
8006 field
= DECL_CHAIN (field
);
8009 /* A packed field does not contribute any extra alignment. */
8010 if (DECL_PACKED (field
))
8012 type
= TREE_TYPE (field
);
8013 while (TREE_CODE (type
) == ARRAY_TYPE
)
8014 type
= TREE_TYPE (type
);
8015 } while (AGGREGATE_TYPE_P (type
));
8017 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
8018 align
= MAX (align
, TYPE_ALIGN (type
));
8023 /* Return 1 for an operand in small memory on V.4/eabi. */
8026 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
8027 machine_mode mode ATTRIBUTE_UNUSED
)
8032 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
8035 if (DEFAULT_ABI
!= ABI_V4
)
8038 if (GET_CODE (op
) == SYMBOL_REF
)
8041 else if (GET_CODE (op
) != CONST
8042 || GET_CODE (XEXP (op
, 0)) != PLUS
8043 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
8044 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
8049 rtx sum
= XEXP (op
, 0);
8050 HOST_WIDE_INT summand
;
8052 /* We have to be careful here, because it is the referenced address
8053 that must be 32k from _SDA_BASE_, not just the symbol. */
8054 summand
= INTVAL (XEXP (sum
, 1));
8055 if (summand
< 0 || summand
> g_switch_value
)
8058 sym_ref
= XEXP (sum
, 0);
8061 return SYMBOL_REF_SMALL_P (sym_ref
);
8067 /* Return true if either operand is a general purpose register. */
8070 gpr_or_gpr_p (rtx op0
, rtx op1
)
8072 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
8073 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
8076 /* Return true if this is a move direct operation between GPR registers and
8077 floating point/VSX registers. */
8080 direct_move_p (rtx op0
, rtx op1
)
8084 if (!REG_P (op0
) || !REG_P (op1
))
8087 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
8090 regno0
= REGNO (op0
);
8091 regno1
= REGNO (op1
);
8092 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
8095 if (INT_REGNO_P (regno0
))
8096 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
8098 else if (INT_REGNO_P (regno1
))
8100 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
8103 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
8110 /* Return true if the OFFSET is valid for the quad address instructions that
8111 use d-form (register + offset) addressing. */
8114 quad_address_offset_p (HOST_WIDE_INT offset
)
8116 return (IN_RANGE (offset
, -32768, 32767) && ((offset
) & 0xf) == 0);
8119 /* Return true if the ADDR is an acceptable address for a quad memory
8120 operation of mode MODE (either LQ/STQ for general purpose registers, or
8121 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
8122 is intended for LQ/STQ. If it is false, the address is intended for the ISA
8123 3.0 LXV/STXV instruction. */
8126 quad_address_p (rtx addr
, machine_mode mode
, bool strict
)
8130 if (GET_MODE_SIZE (mode
) != 16)
8133 if (legitimate_indirect_address_p (addr
, strict
))
8136 if (VECTOR_MODE_P (mode
) && !mode_supports_vsx_dform_quad (mode
))
8139 if (GET_CODE (addr
) != PLUS
)
8142 op0
= XEXP (addr
, 0);
8143 if (!REG_P (op0
) || !INT_REG_OK_FOR_BASE_P (op0
, strict
))
8146 op1
= XEXP (addr
, 1);
8147 if (!CONST_INT_P (op1
))
8150 return quad_address_offset_p (INTVAL (op1
));
8153 /* Return true if this is a load or store quad operation. This function does
8154 not handle the atomic quad memory instructions. */
8157 quad_load_store_p (rtx op0
, rtx op1
)
8161 if (!TARGET_QUAD_MEMORY
)
8164 else if (REG_P (op0
) && MEM_P (op1
))
8165 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
8166 && quad_memory_operand (op1
, GET_MODE (op1
))
8167 && !reg_overlap_mentioned_p (op0
, op1
));
8169 else if (MEM_P (op0
) && REG_P (op1
))
8170 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
8171 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
8176 if (TARGET_DEBUG_ADDR
)
8178 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
8179 ret
? "true" : "false");
8180 debug_rtx (gen_rtx_SET (op0
, op1
));
8186 /* Given an address, return a constant offset term if one exists. */
8189 address_offset (rtx op
)
8191 if (GET_CODE (op
) == PRE_INC
8192 || GET_CODE (op
) == PRE_DEC
)
8194 else if (GET_CODE (op
) == PRE_MODIFY
8195 || GET_CODE (op
) == LO_SUM
)
8198 if (GET_CODE (op
) == CONST
)
8201 if (GET_CODE (op
) == PLUS
)
8204 if (CONST_INT_P (op
))
8210 /* Return true if the MEM operand is a memory operand suitable for use
8211 with a (full width, possibly multiple) gpr load/store. On
8212 powerpc64 this means the offset must be divisible by 4.
8213 Implements 'Y' constraint.
8215 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8216 a constraint function we know the operand has satisfied a suitable
8217 memory predicate. Also accept some odd rtl generated by reload
8218 (see rs6000_legitimize_reload_address for various forms). It is
8219 important that reload rtl be accepted by appropriate constraints
8220 but not by the operand predicate.
8222 Offsetting a lo_sum should not be allowed, except where we know by
8223 alignment that a 32k boundary is not crossed, but see the ???
8224 comment in rs6000_legitimize_reload_address. Note that by
8225 "offsetting" here we mean a further offset to access parts of the
8226 MEM. It's fine to have a lo_sum where the inner address is offset
8227 from a sym, since the same sym+offset will appear in the high part
8228 of the address calculation. */
8231 mem_operand_gpr (rtx op
, machine_mode mode
)
8233 unsigned HOST_WIDE_INT offset
;
8235 rtx addr
= XEXP (op
, 0);
8237 op
= address_offset (addr
);
8241 offset
= INTVAL (op
);
8242 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
8245 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
8249 if (GET_CODE (addr
) == LO_SUM
)
8250 /* For lo_sum addresses, we must allow any offset except one that
8251 causes a wrap, so test only the low 16 bits. */
8252 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
8254 return offset
+ 0x8000 < 0x10000u
- extra
;
8257 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8258 enforce an offset divisible by 4 even for 32-bit. */
8261 mem_operand_ds_form (rtx op
, machine_mode mode
)
8263 unsigned HOST_WIDE_INT offset
;
8265 rtx addr
= XEXP (op
, 0);
8267 if (!offsettable_address_p (false, mode
, addr
))
8270 op
= address_offset (addr
);
8274 offset
= INTVAL (op
);
8275 if ((offset
& 3) != 0)
8278 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
8282 if (GET_CODE (addr
) == LO_SUM
)
8283 /* For lo_sum addresses, we must allow any offset except one that
8284 causes a wrap, so test only the low 16 bits. */
8285 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
8287 return offset
+ 0x8000 < 0x10000u
- extra
;
8290 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8293 reg_offset_addressing_ok_p (machine_mode mode
)
8307 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8308 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8309 a vector mode, if we want to use the VSX registers to move it around,
8310 we need to restrict ourselves to reg+reg addressing. Similarly for
8311 IEEE 128-bit floating point that is passed in a single vector
8313 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
8314 return mode_supports_vsx_dform_quad (mode
);
8319 /* Paired vector modes. Only reg+reg addressing is valid. */
8320 if (TARGET_PAIRED_FLOAT
)
8325 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8326 addressing for the LFIWZX and STFIWX instructions. */
8327 if (TARGET_NO_SDMODE_STACK
)
8339 virtual_stack_registers_memory_p (rtx op
)
8343 if (GET_CODE (op
) == REG
)
8344 regnum
= REGNO (op
);
8346 else if (GET_CODE (op
) == PLUS
8347 && GET_CODE (XEXP (op
, 0)) == REG
8348 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8349 regnum
= REGNO (XEXP (op
, 0));
8354 return (regnum
>= FIRST_VIRTUAL_REGISTER
8355 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
8358 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8359 is known to not straddle a 32k boundary. This function is used
8360 to determine whether -mcmodel=medium code can use TOC pointer
8361 relative addressing for OP. This means the alignment of the TOC
8362 pointer must also be taken into account, and unfortunately that is
8365 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8366 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8370 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
8374 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
8376 if (GET_CODE (op
) != SYMBOL_REF
)
8379 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8381 if (mode_supports_vsx_dform_quad (mode
))
8384 dsize
= GET_MODE_SIZE (mode
);
8385 decl
= SYMBOL_REF_DECL (op
);
8391 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8392 replacing memory addresses with an anchor plus offset. We
8393 could find the decl by rummaging around in the block->objects
8394 VEC for the given offset but that seems like too much work. */
8395 dalign
= BITS_PER_UNIT
;
8396 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
8397 && SYMBOL_REF_ANCHOR_P (op
)
8398 && SYMBOL_REF_BLOCK (op
) != NULL
)
8400 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
8402 dalign
= block
->alignment
;
8403 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
8405 else if (CONSTANT_POOL_ADDRESS_P (op
))
8407 /* It would be nice to have get_pool_align().. */
8408 machine_mode cmode
= get_pool_mode (op
);
8410 dalign
= GET_MODE_ALIGNMENT (cmode
);
8413 else if (DECL_P (decl
))
8415 dalign
= DECL_ALIGN (decl
);
8419 /* Allow BLKmode when the entire object is known to not
8420 cross a 32k boundary. */
8421 if (!DECL_SIZE_UNIT (decl
))
8424 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
8427 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
8431 dalign
/= BITS_PER_UNIT
;
8432 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
8433 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
8434 return dalign
>= dsize
;
8440 /* Find how many bits of the alignment we know for this access. */
8441 dalign
/= BITS_PER_UNIT
;
8442 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
8443 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
8445 lsb
= offset
& -offset
;
8449 return dalign
>= dsize
;
8453 constant_pool_expr_p (rtx op
)
8457 split_const (op
, &base
, &offset
);
8458 return (GET_CODE (base
) == SYMBOL_REF
8459 && CONSTANT_POOL_ADDRESS_P (base
)
8460 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
8463 /* These are only used to pass through from print_operand/print_operand_address
8464 to rs6000_output_addr_const_extra over the intervening function
8465 output_addr_const which is not target code. */
8466 static const_rtx tocrel_base_oac
, tocrel_offset_oac
;
8468 /* Return true if OP is a toc pointer relative address (the output
8469 of create_TOC_reference). If STRICT, do not match non-split
8470 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8471 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8472 TOCREL_OFFSET_RET respectively. */
8475 toc_relative_expr_p (const_rtx op
, bool strict
, const_rtx
*tocrel_base_ret
,
8476 const_rtx
*tocrel_offset_ret
)
8481 if (TARGET_CMODEL
!= CMODEL_SMALL
)
8483 /* When strict ensure we have everything tidy. */
8485 && !(GET_CODE (op
) == LO_SUM
8486 && REG_P (XEXP (op
, 0))
8487 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
)))
8490 /* When not strict, allow non-split TOC addresses and also allow
8491 (lo_sum (high ..)) TOC addresses created during reload. */
8492 if (GET_CODE (op
) == LO_SUM
)
8496 const_rtx tocrel_base
= op
;
8497 const_rtx tocrel_offset
= const0_rtx
;
8499 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
8501 tocrel_base
= XEXP (op
, 0);
8502 tocrel_offset
= XEXP (op
, 1);
8505 if (tocrel_base_ret
)
8506 *tocrel_base_ret
= tocrel_base
;
8507 if (tocrel_offset_ret
)
8508 *tocrel_offset_ret
= tocrel_offset
;
8510 return (GET_CODE (tocrel_base
) == UNSPEC
8511 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
8514 /* Return true if X is a constant pool address, and also for cmodel=medium
8515 if X is a toc-relative address known to be offsettable within MODE. */
8518 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
8521 const_rtx tocrel_base
, tocrel_offset
;
8522 return (toc_relative_expr_p (x
, strict
, &tocrel_base
, &tocrel_offset
)
8523 && (TARGET_CMODEL
!= CMODEL_MEDIUM
8524 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
8526 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
8527 INTVAL (tocrel_offset
), mode
)));
8531 legitimate_small_data_p (machine_mode mode
, rtx x
)
8533 return (DEFAULT_ABI
== ABI_V4
8534 && !flag_pic
&& !TARGET_TOC
8535 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
8536 && small_data_operand (x
, mode
));
8540 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
8541 bool strict
, bool worst_case
)
8543 unsigned HOST_WIDE_INT offset
;
8546 if (GET_CODE (x
) != PLUS
)
8548 if (!REG_P (XEXP (x
, 0)))
8550 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8552 if (mode_supports_vsx_dform_quad (mode
))
8553 return quad_address_p (x
, mode
, strict
);
8554 if (!reg_offset_addressing_ok_p (mode
))
8555 return virtual_stack_registers_memory_p (x
);
8556 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
8558 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8561 offset
= INTVAL (XEXP (x
, 1));
8567 /* Paired single modes: offset addressing isn't valid. */
8573 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8575 if (VECTOR_MEM_VSX_P (mode
))
8580 if (!TARGET_POWERPC64
)
8582 else if (offset
& 3)
8595 if (!TARGET_POWERPC64
)
8597 else if (offset
& 3)
8606 return offset
< 0x10000 - extra
;
8610 legitimate_indexed_address_p (rtx x
, int strict
)
8614 if (GET_CODE (x
) != PLUS
)
8620 return (REG_P (op0
) && REG_P (op1
)
8621 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
8622 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
8623 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
8624 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
8628 avoiding_indexed_address_p (machine_mode mode
)
8630 /* Avoid indexed addressing for modes that have non-indexed
8631 load/store instruction forms. */
8632 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
8636 legitimate_indirect_address_p (rtx x
, int strict
)
8638 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
8642 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
8644 if (!TARGET_MACHO
|| !flag_pic
8645 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
8649 if (GET_CODE (x
) != LO_SUM
)
8651 if (GET_CODE (XEXP (x
, 0)) != REG
)
8653 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
8657 return CONSTANT_P (x
);
8661 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
8663 if (GET_CODE (x
) != LO_SUM
)
8665 if (GET_CODE (XEXP (x
, 0)) != REG
)
8667 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8669 /* quad word addresses are restricted, and we can't use LO_SUM. */
8670 if (mode_supports_vsx_dform_quad (mode
))
8674 if (TARGET_ELF
|| TARGET_MACHO
)
8678 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
8680 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8681 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8682 recognizes some LO_SUM addresses as valid although this
8683 function says opposite. In most cases, LRA through different
8684 transformations can generate correct code for address reloads.
8685 It can not manage only some LO_SUM cases. So we need to add
8686 code analogous to one in rs6000_legitimize_reload_address for
8687 LOW_SUM here saying that some addresses are still valid. */
8688 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
8689 && small_toc_ref (x
, VOIDmode
));
8690 if (TARGET_TOC
&& ! large_toc_ok
)
8692 if (GET_MODE_NUNITS (mode
) != 1)
8694 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8695 && !(/* ??? Assume floating point reg based on mode? */
8696 TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
8697 && (mode
== DFmode
|| mode
== DDmode
)))
8700 return CONSTANT_P (x
) || large_toc_ok
;
8707 /* Try machine-dependent ways of modifying an illegitimate address
8708 to be legitimate. If we find one, return the new, valid address.
8709 This is used from only one place: `memory_address' in explow.c.
8711 OLDX is the address as it was before break_out_memory_refs was
8712 called. In some cases it is useful to look at this to decide what
8715 It is always safe for this function to do nothing. It exists to
8716 recognize opportunities to optimize the output.
8718 On RS/6000, first check for the sum of a register with a constant
8719 integer that is out of range. If so, generate code to add the
8720 constant with the low-order 16 bits masked to the register and force
8721 this result into another register (this can be done with `cau').
8722 Then generate an address of REG+(CONST&0xffff), allowing for the
8723 possibility of bit 16 being a one.
8725 Then check for the sum of a register and something not constant, try to
8726 load the other things into a register and return the sum. */
8729 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
8734 if (!reg_offset_addressing_ok_p (mode
)
8735 || mode_supports_vsx_dform_quad (mode
))
8737 if (virtual_stack_registers_memory_p (x
))
8740 /* In theory we should not be seeing addresses of the form reg+0,
8741 but just in case it is generated, optimize it away. */
8742 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
8743 return force_reg (Pmode
, XEXP (x
, 0));
8745 /* For TImode with load/store quad, restrict addresses to just a single
8746 pointer, so it works with both GPRs and VSX registers. */
8747 /* Make sure both operands are registers. */
8748 else if (GET_CODE (x
) == PLUS
8749 && (mode
!= TImode
|| !TARGET_VSX
))
8750 return gen_rtx_PLUS (Pmode
,
8751 force_reg (Pmode
, XEXP (x
, 0)),
8752 force_reg (Pmode
, XEXP (x
, 1)));
8754 return force_reg (Pmode
, x
);
8756 if (GET_CODE (x
) == SYMBOL_REF
)
8758 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
8760 return rs6000_legitimize_tls_address (x
, model
);
8772 /* As in legitimate_offset_address_p we do not assume
8773 worst-case. The mode here is just a hint as to the registers
8774 used. A TImode is usually in gprs, but may actually be in
8775 fprs. Leave worst-case scenario for reload to handle via
8776 insn constraints. PTImode is only GPRs. */
8783 if (GET_CODE (x
) == PLUS
8784 && GET_CODE (XEXP (x
, 0)) == REG
8785 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8786 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
8788 && !PAIRED_VECTOR_MODE (mode
))
8790 HOST_WIDE_INT high_int
, low_int
;
8792 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8793 if (low_int
>= 0x8000 - extra
)
8795 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
8796 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8797 GEN_INT (high_int
)), 0);
8798 return plus_constant (Pmode
, sum
, low_int
);
8800 else if (GET_CODE (x
) == PLUS
8801 && GET_CODE (XEXP (x
, 0)) == REG
8802 && GET_CODE (XEXP (x
, 1)) != CONST_INT
8803 && GET_MODE_NUNITS (mode
) == 1
8804 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8805 || (/* ??? Assume floating point reg based on mode? */
8806 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
8807 && (mode
== DFmode
|| mode
== DDmode
)))
8808 && !avoiding_indexed_address_p (mode
))
8810 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8811 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
8813 else if (PAIRED_VECTOR_MODE (mode
))
8817 /* We accept [reg + reg]. */
8819 if (GET_CODE (x
) == PLUS
)
8821 rtx op1
= XEXP (x
, 0);
8822 rtx op2
= XEXP (x
, 1);
8825 op1
= force_reg (Pmode
, op1
);
8826 op2
= force_reg (Pmode
, op2
);
8828 /* We can't always do [reg + reg] for these, because [reg +
8829 reg + offset] is not a legitimate addressing mode. */
8830 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
8832 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
8833 return force_reg (Pmode
, y
);
8838 return force_reg (Pmode
, x
);
8840 else if ((TARGET_ELF
8842 || !MACHO_DYNAMIC_NO_PIC_P
8848 && GET_CODE (x
) != CONST_INT
8849 && GET_CODE (x
) != CONST_WIDE_INT
8850 && GET_CODE (x
) != CONST_DOUBLE
8852 && GET_MODE_NUNITS (mode
) == 1
8853 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8854 || (/* ??? Assume floating point reg based on mode? */
8855 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
8856 && (mode
== DFmode
|| mode
== DDmode
))))
8858 rtx reg
= gen_reg_rtx (Pmode
);
8860 emit_insn (gen_elf_high (reg
, x
));
8862 emit_insn (gen_macho_high (reg
, x
));
8863 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
8866 && GET_CODE (x
) == SYMBOL_REF
8867 && constant_pool_expr_p (x
)
8868 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
8869 return create_TOC_reference (x
, NULL_RTX
);
8874 /* Debug version of rs6000_legitimize_address. */
8876 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
8882 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
8883 insns
= get_insns ();
8889 "\nrs6000_legitimize_address: mode %s, old code %s, "
8890 "new code %s, modified\n",
8891 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
8892 GET_RTX_NAME (GET_CODE (ret
)));
8894 fprintf (stderr
, "Original address:\n");
8897 fprintf (stderr
, "oldx:\n");
8900 fprintf (stderr
, "New address:\n");
8905 fprintf (stderr
, "Insns added:\n");
8906 debug_rtx_list (insns
, 20);
8912 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8913 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
8924 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8925 We need to emit DTP-relative relocations. */
8927 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
8929 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8934 fputs ("\t.long\t", file
);
8937 fputs (DOUBLE_INT_ASM_OP
, file
);
8942 output_addr_const (file
, x
);
8944 fputs ("@dtprel+0x8000", file
);
8945 else if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
)
8947 switch (SYMBOL_REF_TLS_MODEL (x
))
8951 case TLS_MODEL_LOCAL_EXEC
:
8952 fputs ("@le", file
);
8954 case TLS_MODEL_INITIAL_EXEC
:
8955 fputs ("@ie", file
);
8957 case TLS_MODEL_GLOBAL_DYNAMIC
:
8958 case TLS_MODEL_LOCAL_DYNAMIC
:
8967 /* Return true if X is a symbol that refers to real (rather than emulated)
8971 rs6000_real_tls_symbol_ref_p (rtx x
)
8973 return (GET_CODE (x
) == SYMBOL_REF
8974 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
8977 /* In the name of slightly smaller debug output, and to cater to
8978 general assembler lossage, recognize various UNSPEC sequences
8979 and turn them back into a direct symbol reference. */
8982 rs6000_delegitimize_address (rtx orig_x
)
8986 orig_x
= delegitimize_mem_from_attrs (orig_x
);
8992 if (TARGET_CMODEL
!= CMODEL_SMALL
8993 && GET_CODE (y
) == LO_SUM
)
8997 if (GET_CODE (y
) == PLUS
8998 && GET_MODE (y
) == Pmode
8999 && CONST_INT_P (XEXP (y
, 1)))
9001 offset
= XEXP (y
, 1);
9005 if (GET_CODE (y
) == UNSPEC
9006 && XINT (y
, 1) == UNSPEC_TOCREL
)
9008 y
= XVECEXP (y
, 0, 0);
9011 /* Do not associate thread-local symbols with the original
9012 constant pool symbol. */
9014 && GET_CODE (y
) == SYMBOL_REF
9015 && CONSTANT_POOL_ADDRESS_P (y
)
9016 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
9020 if (offset
!= NULL_RTX
)
9021 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
9022 if (!MEM_P (orig_x
))
9025 return replace_equiv_address_nv (orig_x
, y
);
9029 && GET_CODE (orig_x
) == LO_SUM
9030 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
9032 y
= XEXP (XEXP (orig_x
, 1), 0);
9033 if (GET_CODE (y
) == UNSPEC
9034 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
9035 return XVECEXP (y
, 0, 0);
9041 /* Return true if X shouldn't be emitted into the debug info.
9042 The linker doesn't like .toc section references from
9043 .debug_* sections, so reject .toc section symbols. */
9046 rs6000_const_not_ok_for_debug_p (rtx x
)
9048 if (GET_CODE (x
) == SYMBOL_REF
9049 && CONSTANT_POOL_ADDRESS_P (x
))
9051 rtx c
= get_pool_constant (x
);
9052 machine_mode cmode
= get_pool_mode (x
);
9053 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
9061 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
9064 rs6000_legitimate_combined_insn (rtx_insn
*insn
)
9066 int icode
= INSN_CODE (insn
);
9068 /* Reject creating doloop insns. Combine should not be allowed
9069 to create these for a number of reasons:
9070 1) In a nested loop, if combine creates one of these in an
9071 outer loop and the register allocator happens to allocate ctr
9072 to the outer loop insn, then the inner loop can't use ctr.
9073 Inner loops ought to be more highly optimized.
9074 2) Combine often wants to create one of these from what was
9075 originally a three insn sequence, first combining the three
9076 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
9077 allocated ctr, the splitter takes use back to the three insn
9078 sequence. It's better to stop combine at the two insn
9080 3) Faced with not being able to allocate ctr for ctrsi/crtdi
9081 insns, the register allocator sometimes uses floating point
9082 or vector registers for the pseudo. Since ctrsi/ctrdi is a
9083 jump insn and output reloads are not implemented for jumps,
9084 the ctrsi/ctrdi splitters need to handle all possible cases.
9085 That's a pain, and it gets to be seriously difficult when a
9086 splitter that runs after reload needs memory to transfer from
9087 a gpr to fpr. See PR70098 and PR71763 which are not fixed
9088 for the difficult case. It's better to not create problems
9089 in the first place. */
9090 if (icode
!= CODE_FOR_nothing
9091 && (icode
== CODE_FOR_ctrsi_internal1
9092 || icode
== CODE_FOR_ctrdi_internal1
9093 || icode
== CODE_FOR_ctrsi_internal2
9094 || icode
== CODE_FOR_ctrdi_internal2
9095 || icode
== CODE_FOR_ctrsi_internal3
9096 || icode
== CODE_FOR_ctrdi_internal3
9097 || icode
== CODE_FOR_ctrsi_internal4
9098 || icode
== CODE_FOR_ctrdi_internal4
))
9104 /* Construct the SYMBOL_REF for the tls_get_addr function. */
9106 static GTY(()) rtx rs6000_tls_symbol
;
9108 rs6000_tls_get_addr (void)
9110 if (!rs6000_tls_symbol
)
9111 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
9113 return rs6000_tls_symbol
;
9116 /* Construct the SYMBOL_REF for TLS GOT references. */
9118 static GTY(()) rtx rs6000_got_symbol
;
9120 rs6000_got_sym (void)
9122 if (!rs6000_got_symbol
)
9124 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9125 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
9126 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
9129 return rs6000_got_symbol
;
9132 /* AIX Thread-Local Address support. */
9135 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
9137 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
9141 name
= XSTR (addr
, 0);
9142 /* Append TLS CSECT qualifier, unless the symbol already is qualified
9143 or the symbol will be in TLS private data section. */
9144 if (name
[strlen (name
) - 1] != ']'
9145 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
9146 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
9148 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
9149 strcpy (tlsname
, name
);
9151 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
9152 tlsaddr
= copy_rtx (addr
);
9153 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
9158 /* Place addr into TOC constant pool. */
9159 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
9161 /* Output the TOC entry and create the MEM referencing the value. */
9162 if (constant_pool_expr_p (XEXP (sym
, 0))
9163 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
9165 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
9166 mem
= gen_const_mem (Pmode
, tocref
);
9167 set_mem_alias_set (mem
, get_TOC_alias_set ());
9172 /* Use global-dynamic for local-dynamic. */
9173 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
9174 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
9176 /* Create new TOC reference for @m symbol. */
9177 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
9178 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
9179 strcpy (tlsname
, "*LCM");
9180 strcat (tlsname
, name
+ 3);
9181 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
9182 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
9183 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
9184 rtx modmem
= gen_const_mem (Pmode
, tocref
);
9185 set_mem_alias_set (modmem
, get_TOC_alias_set ());
9187 rtx modreg
= gen_reg_rtx (Pmode
);
9188 emit_insn (gen_rtx_SET (modreg
, modmem
));
9190 tmpreg
= gen_reg_rtx (Pmode
);
9191 emit_insn (gen_rtx_SET (tmpreg
, mem
));
9193 dest
= gen_reg_rtx (Pmode
);
9195 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
9197 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
9200 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
9201 else if (TARGET_32BIT
)
9203 tlsreg
= gen_reg_rtx (SImode
);
9204 emit_insn (gen_tls_get_tpointer (tlsreg
));
9207 tlsreg
= gen_rtx_REG (DImode
, 13);
9209 /* Load the TOC value into temporary register. */
9210 tmpreg
= gen_reg_rtx (Pmode
);
9211 emit_insn (gen_rtx_SET (tmpreg
, mem
));
9212 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
9213 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
9215 /* Add TOC symbol value to TLS pointer. */
9216 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
9221 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9222 this (thread-local) address. */
9225 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
9230 return rs6000_legitimize_tls_address_aix (addr
, model
);
9232 dest
= gen_reg_rtx (Pmode
);
9233 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
9239 tlsreg
= gen_rtx_REG (Pmode
, 13);
9240 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
9244 tlsreg
= gen_rtx_REG (Pmode
, 2);
9245 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
9249 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
9253 tmp
= gen_reg_rtx (Pmode
);
9256 tlsreg
= gen_rtx_REG (Pmode
, 13);
9257 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
9261 tlsreg
= gen_rtx_REG (Pmode
, 2);
9262 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
9266 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
9268 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
9273 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
9275 /* We currently use relocations like @got@tlsgd for tls, which
9276 means the linker will handle allocation of tls entries, placing
9277 them in the .got section. So use a pointer to the .got section,
9278 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9279 or to secondary GOT sections used by 32-bit -fPIC. */
9281 got
= gen_rtx_REG (Pmode
, 2);
9285 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
9288 rtx gsym
= rs6000_got_sym ();
9289 got
= gen_reg_rtx (Pmode
);
9291 rs6000_emit_move (got
, gsym
, Pmode
);
9296 tmp1
= gen_reg_rtx (Pmode
);
9297 tmp2
= gen_reg_rtx (Pmode
);
9298 mem
= gen_const_mem (Pmode
, tmp1
);
9299 lab
= gen_label_rtx ();
9300 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
9301 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
9302 if (TARGET_LINK_STACK
)
9303 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
9304 emit_move_insn (tmp2
, mem
);
9305 rtx_insn
*last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
9306 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
9311 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
9313 tga
= rs6000_tls_get_addr ();
9314 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
9315 1, const0_rtx
, Pmode
);
9317 r3
= gen_rtx_REG (Pmode
, 3);
9318 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9321 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
9323 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
9325 else if (DEFAULT_ABI
== ABI_V4
)
9326 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
9329 call_insn
= last_call_insn ();
9330 PATTERN (call_insn
) = insn
;
9331 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
9332 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
9333 pic_offset_table_rtx
);
9335 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
9337 tga
= rs6000_tls_get_addr ();
9338 tmp1
= gen_reg_rtx (Pmode
);
9339 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
9340 1, const0_rtx
, Pmode
);
9342 r3
= gen_rtx_REG (Pmode
, 3);
9343 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9346 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
9348 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
9350 else if (DEFAULT_ABI
== ABI_V4
)
9351 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
9354 call_insn
= last_call_insn ();
9355 PATTERN (call_insn
) = insn
;
9356 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
9357 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
9358 pic_offset_table_rtx
);
9360 if (rs6000_tls_size
== 16)
9363 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
9365 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
9367 else if (rs6000_tls_size
== 32)
9369 tmp2
= gen_reg_rtx (Pmode
);
9371 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
9373 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
9376 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
9378 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
9382 tmp2
= gen_reg_rtx (Pmode
);
9384 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
9386 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
9388 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
9394 /* IE, or 64-bit offset LE. */
9395 tmp2
= gen_reg_rtx (Pmode
);
9397 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
9399 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
9402 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
9404 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
9412 /* Only create the global variable for the stack protect guard if we are using
9413 the global flavor of that guard. */
9415 rs6000_init_stack_protect_guard (void)
9417 if (rs6000_stack_protector_guard
== SSP_GLOBAL
)
9418 return default_stack_protect_guard ();
9423 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9426 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
9428 if (GET_CODE (x
) == HIGH
9429 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
9432 /* A TLS symbol in the TOC cannot contain a sum. */
9433 if (GET_CODE (x
) == CONST
9434 && GET_CODE (XEXP (x
, 0)) == PLUS
9435 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
9436 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
9439 /* Do not place an ELF TLS symbol in the constant pool. */
9440 return TARGET_ELF
&& tls_referenced_p (x
);
9443 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9444 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9445 can be addressed relative to the toc pointer. */
9448 use_toc_relative_ref (rtx sym
, machine_mode mode
)
9450 return ((constant_pool_expr_p (sym
)
9451 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
9452 get_pool_mode (sym
)))
9453 || (TARGET_CMODEL
== CMODEL_MEDIUM
9454 && SYMBOL_REF_LOCAL_P (sym
)
9455 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
9458 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9459 replace the input X, or the original X if no replacement is called for.
9460 The output parameter *WIN is 1 if the calling macro should goto WIN,
9463 For RS/6000, we wish to handle large displacements off a base
9464 register by splitting the addend across an addiu/addis and the mem insn.
9465 This cuts number of extra insns needed from 3 to 1.
9467 On Darwin, we use this to generate code for floating point constants.
9468 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9469 The Darwin code is inside #if TARGET_MACHO because only then are the
9470 machopic_* functions defined. */
9472 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
9473 int opnum
, int type
,
9474 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
9476 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9477 bool quad_offset_p
= mode_supports_vsx_dform_quad (mode
);
9479 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9480 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9483 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
9484 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)
9485 || (mode
== SFmode
&& recog_data
.operand_mode
[0] == V4SFmode
9486 && TARGET_P9_VECTOR
)
9487 || (mode
== SImode
&& recog_data
.operand_mode
[0] == V4SImode
9488 && TARGET_P9_VECTOR
)))
9489 reg_offset_p
= false;
9491 /* We must recognize output that we have already generated ourselves. */
9492 if (GET_CODE (x
) == PLUS
9493 && GET_CODE (XEXP (x
, 0)) == PLUS
9494 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
9495 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
9496 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9498 if (TARGET_DEBUG_ADDR
)
9500 fprintf (stderr
, "\nlegitimize_reload_address push_reload #1:\n");
9503 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9504 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
9505 opnum
, (enum reload_type
) type
);
9510 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9511 if (GET_CODE (x
) == LO_SUM
9512 && GET_CODE (XEXP (x
, 0)) == HIGH
)
9514 if (TARGET_DEBUG_ADDR
)
9516 fprintf (stderr
, "\nlegitimize_reload_address push_reload #2:\n");
9519 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9520 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9521 opnum
, (enum reload_type
) type
);
9527 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
9528 && GET_CODE (x
) == LO_SUM
9529 && GET_CODE (XEXP (x
, 0)) == PLUS
9530 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
9531 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
9532 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
9533 && machopic_operand_p (XEXP (x
, 1)))
9535 /* Result of previous invocation of this function on Darwin
9536 floating point constant. */
9537 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9538 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9539 opnum
, (enum reload_type
) type
);
9545 if (TARGET_CMODEL
!= CMODEL_SMALL
9548 && small_toc_ref (x
, VOIDmode
))
9550 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
9551 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
9552 if (TARGET_DEBUG_ADDR
)
9554 fprintf (stderr
, "\nlegitimize_reload_address push_reload #3:\n");
9557 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9558 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9559 opnum
, (enum reload_type
) type
);
9564 if (GET_CODE (x
) == PLUS
9565 && REG_P (XEXP (x
, 0))
9566 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
9567 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
9568 && CONST_INT_P (XEXP (x
, 1))
9570 && !PAIRED_VECTOR_MODE (mode
)
9571 && (quad_offset_p
|| !VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
9573 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
9574 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
9576 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9578 /* Check for 32-bit overflow or quad addresses with one of the
9579 four least significant bits set. */
9580 if (high
+ low
!= val
9581 || (quad_offset_p
&& (low
& 0xf)))
9587 /* Reload the high part into a base reg; leave the low part
9588 in the mem directly. */
9590 x
= gen_rtx_PLUS (GET_MODE (x
),
9591 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
9595 if (TARGET_DEBUG_ADDR
)
9597 fprintf (stderr
, "\nlegitimize_reload_address push_reload #4:\n");
9600 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9601 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
9602 opnum
, (enum reload_type
) type
);
9607 if (GET_CODE (x
) == SYMBOL_REF
9610 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
9611 && !PAIRED_VECTOR_MODE (mode
)
9613 && DEFAULT_ABI
== ABI_DARWIN
9614 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
9615 && machopic_symbol_defined_p (x
)
9617 && DEFAULT_ABI
== ABI_V4
9620 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9621 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9623 ??? Assume floating point reg based on mode? This assumption is
9624 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9625 where reload ends up doing a DFmode load of a constant from
9626 mem using two gprs. Unfortunately, at this point reload
9627 hasn't yet selected regs so poking around in reload data
9628 won't help and even if we could figure out the regs reliably,
9629 we'd still want to allow this transformation when the mem is
9630 naturally aligned. Since we say the address is good here, we
9631 can't disable offsets from LO_SUMs in mem_operand_gpr.
9632 FIXME: Allow offset from lo_sum for other modes too, when
9633 mem is sufficiently aligned.
9635 Also disallow this if the type can go in VMX/Altivec registers, since
9636 those registers do not have d-form (reg+offset) address modes. */
9637 && !reg_addr
[mode
].scalar_in_vmx_p
9642 && (mode
!= TImode
|| !TARGET_VSX
)
9644 && (mode
!= DImode
|| TARGET_POWERPC64
)
9645 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
9646 || (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)))
9651 rtx offset
= machopic_gen_offset (x
);
9652 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9653 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
9654 gen_rtx_HIGH (Pmode
, offset
)), offset
);
9658 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9659 gen_rtx_HIGH (Pmode
, x
), x
);
9661 if (TARGET_DEBUG_ADDR
)
9663 fprintf (stderr
, "\nlegitimize_reload_address push_reload #5:\n");
9666 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9667 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9668 opnum
, (enum reload_type
) type
);
9673 /* Reload an offset address wrapped by an AND that represents the
9674 masking of the lower bits. Strip the outer AND and let reload
9675 convert the offset address into an indirect address. For VSX,
9676 force reload to create the address with an AND in a separate
9677 register, because we can't guarantee an altivec register will
9679 if (VECTOR_MEM_ALTIVEC_P (mode
)
9680 && GET_CODE (x
) == AND
9681 && GET_CODE (XEXP (x
, 0)) == PLUS
9682 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
9683 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
9684 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9685 && INTVAL (XEXP (x
, 1)) == -16)
9695 && GET_CODE (x
) == SYMBOL_REF
9696 && use_toc_relative_ref (x
, mode
))
9698 x
= create_TOC_reference (x
, NULL_RTX
);
9699 if (TARGET_CMODEL
!= CMODEL_SMALL
)
9701 if (TARGET_DEBUG_ADDR
)
9703 fprintf (stderr
, "\nlegitimize_reload_address push_reload #6:\n");
9706 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9707 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9708 opnum
, (enum reload_type
) type
);
9717 /* Debug version of rs6000_legitimize_reload_address. */
9719 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
9720 int opnum
, int type
,
9721 int ind_levels
, int *win
)
9723 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
9726 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9727 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9728 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
9732 fprintf (stderr
, "Same address returned\n");
9734 fprintf (stderr
, "NULL returned\n");
9737 fprintf (stderr
, "New address:\n");
9744 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9745 that is a valid memory address for an instruction.
9746 The MODE argument is the machine mode for the MEM expression
9747 that wants to use this address.
9749 On the RS/6000, there are four valid address: a SYMBOL_REF that
9750 refers to a constant pool entry of an address (or the sum of it
9751 plus a constant), a short (16-bit signed) constant plus a register,
9752 the sum of two registers, or a register indirect, possibly with an
9753 auto-increment. For DFmode, DDmode and DImode with a constant plus
9754 register, we must ensure that both words are addressable or PowerPC64
9755 with offset word aligned.
9757 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9758 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9759 because adjacent memory cells are accessed by adding word-sized offsets
9760 during assembly output. */
9762 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
9764 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9765 bool quad_offset_p
= mode_supports_vsx_dform_quad (mode
);
9767 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9768 if (VECTOR_MEM_ALTIVEC_P (mode
)
9769 && GET_CODE (x
) == AND
9770 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9771 && INTVAL (XEXP (x
, 1)) == -16)
9774 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
9776 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
9779 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
9780 && mode_supports_pre_incdec_p (mode
)
9781 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
9783 /* Handle restricted vector d-form offsets in ISA 3.0. */
9786 if (quad_address_p (x
, mode
, reg_ok_strict
))
9789 else if (virtual_stack_registers_memory_p (x
))
9792 else if (reg_offset_p
)
9794 if (legitimate_small_data_p (mode
, x
))
9796 if (legitimate_constant_pool_address_p (x
, mode
,
9797 reg_ok_strict
|| lra_in_progress
))
9799 if (reg_addr
[mode
].fused_toc
&& GET_CODE (x
) == UNSPEC
9800 && XINT (x
, 1) == UNSPEC_FUSION_ADDIS
)
9804 /* For TImode, if we have TImode in VSX registers, only allow register
9805 indirect addresses. This will allow the values to go in either GPRs
9806 or VSX registers without reloading. The vector types would tend to
9807 go into VSX registers, so we allow REG+REG, while TImode seems
9808 somewhat split, in that some uses are GPR based, and some VSX based. */
9809 /* FIXME: We could loosen this by changing the following to
9810 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9811 but currently we cannot allow REG+REG addressing for TImode. See
9812 PR72827 for complete details on how this ends up hoodwinking DSE. */
9813 if (mode
== TImode
&& TARGET_VSX
)
9815 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9818 && GET_CODE (x
) == PLUS
9819 && GET_CODE (XEXP (x
, 0)) == REG
9820 && (XEXP (x
, 0) == virtual_stack_vars_rtx
9821 || XEXP (x
, 0) == arg_pointer_rtx
)
9822 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9824 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
9826 if (!FLOAT128_2REG_P (mode
)
9827 && ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9829 || (mode
!= DFmode
&& mode
!= DDmode
))
9830 && (TARGET_POWERPC64
|| mode
!= DImode
)
9831 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
9833 && !avoiding_indexed_address_p (mode
)
9834 && legitimate_indexed_address_p (x
, reg_ok_strict
))
9836 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
9837 && mode_supports_pre_modify_p (mode
)
9838 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
9839 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
9840 reg_ok_strict
, false)
9841 || (!avoiding_indexed_address_p (mode
)
9842 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
9843 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
9845 if (reg_offset_p
&& !quad_offset_p
9846 && legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
9851 /* Debug version of rs6000_legitimate_address_p. */
9853 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
9856 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
9858 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9859 "strict = %d, reload = %s, code = %s\n",
9860 ret
? "true" : "false",
9861 GET_MODE_NAME (mode
),
9863 (reload_completed
? "after" : "before"),
9864 GET_RTX_NAME (GET_CODE (x
)));
9870 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9873 rs6000_mode_dependent_address_p (const_rtx addr
,
9874 addr_space_t as ATTRIBUTE_UNUSED
)
9876 return rs6000_mode_dependent_address_ptr (addr
);
9879 /* Go to LABEL if ADDR (a legitimate address expression)
9880 has an effect that depends on the machine mode it is used for.
9882 On the RS/6000 this is true of all integral offsets (since AltiVec
9883 and VSX modes don't allow them) or is a pre-increment or decrement.
9885 ??? Except that due to conceptual problems in offsettable_address_p
9886 we can't really report the problems of integral offsets. So leave
9887 this assuming that the adjustable offset must be valid for the
9888 sub-words of a TFmode operand, which is what we had before. */
9891 rs6000_mode_dependent_address (const_rtx addr
)
9893 switch (GET_CODE (addr
))
9896 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9897 is considered a legitimate address before reload, so there
9898 are no offset restrictions in that case. Note that this
9899 condition is safe in strict mode because any address involving
9900 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9901 been rejected as illegitimate. */
9902 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
9903 && XEXP (addr
, 0) != arg_pointer_rtx
9904 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
9906 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
9907 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
9912 /* Anything in the constant pool is sufficiently aligned that
9913 all bytes have the same high part address. */
9914 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
9916 /* Auto-increment cases are now treated generically in recog.c. */
9918 return TARGET_UPDATE
;
9920 /* AND is only allowed in Altivec loads. */
9931 /* Debug version of rs6000_mode_dependent_address. */
9933 rs6000_debug_mode_dependent_address (const_rtx addr
)
9935 bool ret
= rs6000_mode_dependent_address (addr
);
9937 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
9938 ret
? "true" : "false");
9944 /* Implement FIND_BASE_TERM. */
9947 rs6000_find_base_term (rtx op
)
9952 if (GET_CODE (base
) == CONST
)
9953 base
= XEXP (base
, 0);
9954 if (GET_CODE (base
) == PLUS
)
9955 base
= XEXP (base
, 0);
9956 if (GET_CODE (base
) == UNSPEC
)
9957 switch (XINT (base
, 1))
9960 case UNSPEC_MACHOPIC_OFFSET
:
9961 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9962 for aliasing purposes. */
9963 return XVECEXP (base
, 0, 0);
9969 /* More elaborate version of recog's offsettable_memref_p predicate
9970 that works around the ??? note of rs6000_mode_dependent_address.
9971 In particular it accepts
9973 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9975 in 32-bit mode, that the recog predicate rejects. */
9978 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
)
9985 /* First mimic offsettable_memref_p. */
9986 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
9989 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9990 the latter predicate knows nothing about the mode of the memory
9991 reference and, therefore, assumes that it is the largest supported
9992 mode (TFmode). As a consequence, legitimate offsettable memory
9993 references are rejected. rs6000_legitimate_offset_address_p contains
9994 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9995 at least with a little bit of help here given that we know the
9996 actual registers used. */
9997 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
9998 || GET_MODE_SIZE (reg_mode
) == 4);
9999 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
10003 /* Determine the reassociation width to be used in reassociate_bb.
10004 This takes into account how many parallel operations we
10005 can actually do of a given type, and also the latency.
10007 int add/sub 6/cycle
10009 vect add/sub/mul 2/cycle
10010 fp add/sub/mul 2/cycle
10015 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
10018 switch (rs6000_cpu
)
10020 case PROCESSOR_POWER8
:
10021 case PROCESSOR_POWER9
:
10022 if (DECIMAL_FLOAT_MODE_P (mode
))
10024 if (VECTOR_MODE_P (mode
))
10026 if (INTEGRAL_MODE_P (mode
))
10027 return opc
== MULT_EXPR
? 4 : 6;
10028 if (FLOAT_MODE_P (mode
))
10037 /* Change register usage conditional on target flags. */
10039 rs6000_conditional_register_usage (void)
10043 if (TARGET_DEBUG_TARGET
)
10044 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
10046 /* Set MQ register fixed (already call_used) so that it will not be
10048 fixed_regs
[64] = 1;
10050 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
10052 fixed_regs
[13] = call_used_regs
[13]
10053 = call_really_used_regs
[13] = 1;
10055 /* Conditionally disable FPRs. */
10056 if (TARGET_SOFT_FLOAT
)
10057 for (i
= 32; i
< 64; i
++)
10058 fixed_regs
[i
] = call_used_regs
[i
]
10059 = call_really_used_regs
[i
] = 1;
10061 /* The TOC register is not killed across calls in a way that is
10062 visible to the compiler. */
10063 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10064 call_really_used_regs
[2] = 0;
10066 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
10067 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
10069 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
10070 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
10071 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
10072 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
10074 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
10075 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
10076 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
10077 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
10079 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
10080 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
10081 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
10083 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
10085 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
10086 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
10087 call_really_used_regs
[VRSAVE_REGNO
] = 1;
10090 if (TARGET_ALTIVEC
|| TARGET_VSX
)
10091 global_regs
[VSCR_REGNO
] = 1;
10093 if (TARGET_ALTIVEC_ABI
)
10095 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
10096 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
10098 /* AIX reserves VR20:31 in non-extended ABI mode. */
10100 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
10101 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
10106 /* Output insns to set DEST equal to the constant SOURCE as a series of
10107 lis, ori and shl instructions and return TRUE. */
10110 rs6000_emit_set_const (rtx dest
, rtx source
)
10112 machine_mode mode
= GET_MODE (dest
);
10117 gcc_checking_assert (CONST_INT_P (source
));
10118 c
= INTVAL (source
);
10123 emit_insn (gen_rtx_SET (dest
, source
));
10127 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
10129 emit_insn (gen_rtx_SET (copy_rtx (temp
),
10130 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
10131 emit_insn (gen_rtx_SET (dest
,
10132 gen_rtx_IOR (SImode
, copy_rtx (temp
),
10133 GEN_INT (c
& 0xffff))));
10137 if (!TARGET_POWERPC64
)
10141 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
10143 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
10145 emit_move_insn (hi
, GEN_INT (c
>> 32));
10146 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
10147 emit_move_insn (lo
, GEN_INT (c
));
10150 rs6000_emit_set_long_const (dest
, c
);
10154 gcc_unreachable ();
10157 insn
= get_last_insn ();
10158 set
= single_set (insn
);
10159 if (! CONSTANT_P (SET_SRC (set
)))
10160 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
10165 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
10166 Output insns to set DEST equal to the constant C as a series of
10167 lis, ori and shl instructions. */
10170 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
10173 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
10183 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
10184 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
10185 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
10187 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
10188 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
10190 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10192 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
10193 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
10195 emit_move_insn (dest
,
10196 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10199 else if (ud3
== 0 && ud4
== 0)
10201 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10203 gcc_assert (ud2
& 0x8000);
10204 emit_move_insn (copy_rtx (temp
),
10205 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
10207 emit_move_insn (copy_rtx (temp
),
10208 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10210 emit_move_insn (dest
,
10211 gen_rtx_ZERO_EXTEND (DImode
,
10212 gen_lowpart (SImode
,
10213 copy_rtx (temp
))));
10215 else if ((ud4
== 0xffff && (ud3
& 0x8000))
10216 || (ud4
== 0 && ! (ud3
& 0x8000)))
10218 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10220 emit_move_insn (copy_rtx (temp
),
10221 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
10223 emit_move_insn (copy_rtx (temp
),
10224 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10226 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
10227 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
10230 emit_move_insn (dest
,
10231 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10236 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10238 emit_move_insn (copy_rtx (temp
),
10239 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
10241 emit_move_insn (copy_rtx (temp
),
10242 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10245 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
10246 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
10249 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
10250 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10251 GEN_INT (ud2
<< 16)));
10253 emit_move_insn (dest
,
10254 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10259 /* Helper for the following. Get rid of [r+r] memory refs
10260 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10263 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
10265 if (GET_CODE (operands
[0]) == MEM
10266 && GET_CODE (XEXP (operands
[0], 0)) != REG
10267 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
10268 GET_MODE (operands
[0]), false))
10270 = replace_equiv_address (operands
[0],
10271 copy_addr_to_reg (XEXP (operands
[0], 0)));
10273 if (GET_CODE (operands
[1]) == MEM
10274 && GET_CODE (XEXP (operands
[1], 0)) != REG
10275 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
10276 GET_MODE (operands
[1]), false))
10278 = replace_equiv_address (operands
[1],
10279 copy_addr_to_reg (XEXP (operands
[1], 0)));
10282 /* Generate a vector of constants to permute MODE for a little-endian
10283 storage operation by swapping the two halves of a vector. */
10285 rs6000_const_vec (machine_mode mode
)
10313 v
= rtvec_alloc (subparts
);
10315 for (i
= 0; i
< subparts
/ 2; ++i
)
10316 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
10317 for (i
= subparts
/ 2; i
< subparts
; ++i
)
10318 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
10323 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10324 store operation. */
10326 rs6000_emit_le_vsx_permute (rtx dest
, rtx source
, machine_mode mode
)
10328 /* Scalar permutations are easier to express in integer modes rather than
10329 floating-point modes, so cast them here. We use V1TImode instead
10330 of TImode to ensure that the values don't go through GPRs. */
10331 if (FLOAT128_VECTOR_P (mode
))
10333 dest
= gen_lowpart (V1TImode
, dest
);
10334 source
= gen_lowpart (V1TImode
, source
);
10338 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10340 if (mode
== TImode
|| mode
== V1TImode
)
10341 emit_insn (gen_rtx_SET (dest
, gen_rtx_ROTATE (mode
, source
,
10345 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
10346 emit_insn (gen_rtx_SET (dest
, gen_rtx_VEC_SELECT (mode
, source
, par
)));
10350 /* Emit a little-endian load from vector memory location SOURCE to VSX
10351 register DEST in mode MODE. The load is done with two permuting
10352 insn's that represent an lxvd2x and xxpermdi. */
10354 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
10356 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10358 if (mode
== TImode
|| mode
== V1TImode
)
10361 dest
= gen_lowpart (V2DImode
, dest
);
10362 source
= adjust_address (source
, V2DImode
, 0);
10365 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
10366 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
10367 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
10370 /* Emit a little-endian store to vector memory location DEST from VSX
10371 register SOURCE in mode MODE. The store is done with two permuting
10372 insn's that represent an xxpermdi and an stxvd2x. */
10374 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
10376 /* This should never be called during or after LRA, because it does
10377 not re-permute the source register. It is intended only for use
10379 gcc_assert (!lra_in_progress
&& !reload_completed
);
10381 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10383 if (mode
== TImode
|| mode
== V1TImode
)
10386 dest
= adjust_address (dest
, V2DImode
, 0);
10387 source
= gen_lowpart (V2DImode
, source
);
10390 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
10391 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
10392 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
10395 /* Emit a sequence representing a little-endian VSX load or store,
10396 moving data from SOURCE to DEST in mode MODE. This is done
10397 separately from rs6000_emit_move to ensure it is called only
10398 during expand. LE VSX loads and stores introduced later are
10399 handled with a split. The expand-time RTL generation allows
10400 us to optimize away redundant pairs of register-permutes. */
10402 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
10404 gcc_assert (!BYTES_BIG_ENDIAN
10405 && VECTOR_MEM_VSX_P (mode
)
10406 && !TARGET_P9_VECTOR
10407 && !gpr_or_gpr_p (dest
, source
)
10408 && (MEM_P (source
) ^ MEM_P (dest
)));
10410 if (MEM_P (source
))
10412 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
10413 rs6000_emit_le_vsx_load (dest
, source
, mode
);
10417 if (!REG_P (source
))
10418 source
= force_reg (mode
, source
);
10419 rs6000_emit_le_vsx_store (dest
, source
, mode
);
10423 /* Return whether a SFmode or SImode move can be done without converting one
10424 mode to another. This arrises when we have:
10426 (SUBREG:SF (REG:SI ...))
10427 (SUBREG:SI (REG:SF ...))
10429 and one of the values is in a floating point/vector register, where SFmode
10430 scalars are stored in DFmode format. */
10433 valid_sf_si_move (rtx dest
, rtx src
, machine_mode mode
)
10435 if (TARGET_ALLOW_SF_SUBREG
)
10438 if (mode
!= SFmode
&& GET_MODE_CLASS (mode
) != MODE_INT
)
10441 if (!SUBREG_P (src
) || !sf_subreg_operand (src
, mode
))
10444 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10445 if (SUBREG_P (dest
))
10447 rtx dest_subreg
= SUBREG_REG (dest
);
10448 rtx src_subreg
= SUBREG_REG (src
);
10449 return GET_MODE (dest_subreg
) == GET_MODE (src_subreg
);
10456 /* Helper function to change moves with:
10458 (SUBREG:SF (REG:SI)) and
10459 (SUBREG:SI (REG:SF))
10461 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10462 values are stored as DFmode values in the VSX registers. We need to convert
10463 the bits before we can use a direct move or operate on the bits in the
10464 vector register as an integer type.
10466 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10469 rs6000_emit_move_si_sf_subreg (rtx dest
, rtx source
, machine_mode mode
)
10471 if (TARGET_DIRECT_MOVE_64BIT
&& !lra_in_progress
&& !reload_completed
10472 && (!SUBREG_P (dest
) || !sf_subreg_operand (dest
, mode
))
10473 && SUBREG_P (source
) && sf_subreg_operand (source
, mode
))
10475 rtx inner_source
= SUBREG_REG (source
);
10476 machine_mode inner_mode
= GET_MODE (inner_source
);
10478 if (mode
== SImode
&& inner_mode
== SFmode
)
10480 emit_insn (gen_movsi_from_sf (dest
, inner_source
));
10484 if (mode
== SFmode
&& inner_mode
== SImode
)
10486 emit_insn (gen_movsf_from_si (dest
, inner_source
));
10494 /* Emit a move from SOURCE to DEST in mode MODE. */
10496 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
10499 operands
[0] = dest
;
10500 operands
[1] = source
;
10502 if (TARGET_DEBUG_ADDR
)
10505 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10506 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10507 GET_MODE_NAME (mode
),
10510 can_create_pseudo_p ());
10512 fprintf (stderr
, "source:\n");
10513 debug_rtx (source
);
10516 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10517 if (CONST_WIDE_INT_P (operands
[1])
10518 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10520 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10521 gcc_unreachable ();
10524 /* See if we need to special case SImode/SFmode SUBREG moves. */
10525 if ((mode
== SImode
|| mode
== SFmode
) && SUBREG_P (source
)
10526 && rs6000_emit_move_si_sf_subreg (dest
, source
, mode
))
10529 /* Check if GCC is setting up a block move that will end up using FP
10530 registers as temporaries. We must make sure this is acceptable. */
10531 if (GET_CODE (operands
[0]) == MEM
10532 && GET_CODE (operands
[1]) == MEM
10534 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
10535 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
10536 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
10537 ? 32 : MEM_ALIGN (operands
[0])))
10538 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
10540 : MEM_ALIGN (operands
[1]))))
10541 && ! MEM_VOLATILE_P (operands
[0])
10542 && ! MEM_VOLATILE_P (operands
[1]))
10544 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
10545 adjust_address (operands
[1], SImode
, 0));
10546 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
10547 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
10551 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
10552 && !gpc_reg_operand (operands
[1], mode
))
10553 operands
[1] = force_reg (mode
, operands
[1]);
10555 /* Recognize the case where operand[1] is a reference to thread-local
10556 data and load its address to a register. */
10557 if (tls_referenced_p (operands
[1]))
10559 enum tls_model model
;
10560 rtx tmp
= operands
[1];
10563 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
10565 addend
= XEXP (XEXP (tmp
, 0), 1);
10566 tmp
= XEXP (XEXP (tmp
, 0), 0);
10569 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
10570 model
= SYMBOL_REF_TLS_MODEL (tmp
);
10571 gcc_assert (model
!= 0);
10573 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
10576 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
10577 tmp
= force_operand (tmp
, operands
[0]);
10582 /* 128-bit constant floating-point values on Darwin should really be loaded
10583 as two parts. However, this premature splitting is a problem when DFmode
10584 values can go into Altivec registers. */
10585 if (FLOAT128_IBM_P (mode
) && !reg_addr
[DFmode
].scalar_in_vmx_p
10586 && GET_CODE (operands
[1]) == CONST_DOUBLE
)
10588 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
10589 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
10591 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
10592 GET_MODE_SIZE (DFmode
)),
10593 simplify_gen_subreg (DFmode
, operands
[1], mode
,
10594 GET_MODE_SIZE (DFmode
)),
10599 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10600 p1:SD) if p1 is not of floating point class and p0 is spilled as
10601 we can have no analogous movsd_store for this. */
10602 if (lra_in_progress
&& mode
== DDmode
10603 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
10604 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10605 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
10606 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
10609 int regno
= REGNO (SUBREG_REG (operands
[1]));
10611 if (regno
>= FIRST_PSEUDO_REGISTER
)
10613 cl
= reg_preferred_class (regno
);
10614 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
10616 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10619 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
10620 operands
[1] = SUBREG_REG (operands
[1]);
10623 if (lra_in_progress
10625 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
10626 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10627 && (REG_P (operands
[1])
10628 || (GET_CODE (operands
[1]) == SUBREG
10629 && REG_P (SUBREG_REG (operands
[1])))))
10631 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
10632 ? SUBREG_REG (operands
[1]) : operands
[1]);
10635 if (regno
>= FIRST_PSEUDO_REGISTER
)
10637 cl
= reg_preferred_class (regno
);
10638 gcc_assert (cl
!= NO_REGS
);
10639 regno
= ira_class_hard_regs
[cl
][0];
10641 if (FP_REGNO_P (regno
))
10643 if (GET_MODE (operands
[0]) != DDmode
)
10644 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
10645 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
10647 else if (INT_REGNO_P (regno
))
10648 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10653 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10654 p:DD)) if p0 is not of floating point class and p1 is spilled as
10655 we can have no analogous movsd_load for this. */
10656 if (lra_in_progress
&& mode
== DDmode
10657 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
10658 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
10659 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10660 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10663 int regno
= REGNO (SUBREG_REG (operands
[0]));
10665 if (regno
>= FIRST_PSEUDO_REGISTER
)
10667 cl
= reg_preferred_class (regno
);
10668 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
10670 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10673 operands
[0] = SUBREG_REG (operands
[0]);
10674 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
10677 if (lra_in_progress
10679 && (REG_P (operands
[0])
10680 || (GET_CODE (operands
[0]) == SUBREG
10681 && REG_P (SUBREG_REG (operands
[0]))))
10682 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10683 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10685 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
10686 ? SUBREG_REG (operands
[0]) : operands
[0]);
10689 if (regno
>= FIRST_PSEUDO_REGISTER
)
10691 cl
= reg_preferred_class (regno
);
10692 gcc_assert (cl
!= NO_REGS
);
10693 regno
= ira_class_hard_regs
[cl
][0];
10695 if (FP_REGNO_P (regno
))
10697 if (GET_MODE (operands
[1]) != DDmode
)
10698 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
10699 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
10701 else if (INT_REGNO_P (regno
))
10702 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10708 /* FIXME: In the long term, this switch statement should go away
10709 and be replaced by a sequence of tests based on things like
10715 if (CONSTANT_P (operands
[1])
10716 && GET_CODE (operands
[1]) != CONST_INT
)
10717 operands
[1] = force_const_mem (mode
, operands
[1]);
10724 if (FLOAT128_2REG_P (mode
))
10725 rs6000_eliminate_indexed_memrefs (operands
);
10732 if (CONSTANT_P (operands
[1])
10733 && ! easy_fp_constant (operands
[1], mode
))
10734 operands
[1] = force_const_mem (mode
, operands
[1]);
10746 if (CONSTANT_P (operands
[1])
10747 && !easy_vector_constant (operands
[1], mode
))
10748 operands
[1] = force_const_mem (mode
, operands
[1]);
10753 /* Use default pattern for address of ELF small data */
10756 && DEFAULT_ABI
== ABI_V4
10757 && (GET_CODE (operands
[1]) == SYMBOL_REF
10758 || GET_CODE (operands
[1]) == CONST
)
10759 && small_data_operand (operands
[1], mode
))
10761 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10765 if (DEFAULT_ABI
== ABI_V4
10766 && mode
== Pmode
&& mode
== SImode
10767 && flag_pic
== 1 && got_operand (operands
[1], mode
))
10769 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
10773 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
10777 && CONSTANT_P (operands
[1])
10778 && GET_CODE (operands
[1]) != HIGH
10779 && GET_CODE (operands
[1]) != CONST_INT
)
10781 rtx target
= (!can_create_pseudo_p ()
10783 : gen_reg_rtx (mode
));
10785 /* If this is a function address on -mcall-aixdesc,
10786 convert it to the address of the descriptor. */
10787 if (DEFAULT_ABI
== ABI_AIX
10788 && GET_CODE (operands
[1]) == SYMBOL_REF
10789 && XSTR (operands
[1], 0)[0] == '.')
10791 const char *name
= XSTR (operands
[1], 0);
10793 while (*name
== '.')
10795 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
10796 CONSTANT_POOL_ADDRESS_P (new_ref
)
10797 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
10798 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
10799 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
10800 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
10801 operands
[1] = new_ref
;
10804 if (DEFAULT_ABI
== ABI_DARWIN
)
10807 if (MACHO_DYNAMIC_NO_PIC_P
)
10809 /* Take care of any required data indirection. */
10810 operands
[1] = rs6000_machopic_legitimize_pic_address (
10811 operands
[1], mode
, operands
[0]);
10812 if (operands
[0] != operands
[1])
10813 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10817 emit_insn (gen_macho_high (target
, operands
[1]));
10818 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
10822 emit_insn (gen_elf_high (target
, operands
[1]));
10823 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
10827 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10828 and we have put it in the TOC, we just need to make a TOC-relative
10829 reference to it. */
10831 && GET_CODE (operands
[1]) == SYMBOL_REF
10832 && use_toc_relative_ref (operands
[1], mode
))
10833 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
10834 else if (mode
== Pmode
10835 && CONSTANT_P (operands
[1])
10836 && GET_CODE (operands
[1]) != HIGH
10837 && ((GET_CODE (operands
[1]) != CONST_INT
10838 && ! easy_fp_constant (operands
[1], mode
))
10839 || (GET_CODE (operands
[1]) == CONST_INT
10840 && (num_insns_constant (operands
[1], mode
)
10841 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
10842 || (GET_CODE (operands
[0]) == REG
10843 && FP_REGNO_P (REGNO (operands
[0]))))
10844 && !toc_relative_expr_p (operands
[1], false, NULL
, NULL
)
10845 && (TARGET_CMODEL
== CMODEL_SMALL
10846 || can_create_pseudo_p ()
10847 || (REG_P (operands
[0])
10848 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
10852 /* Darwin uses a special PIC legitimizer. */
10853 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
10856 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
10858 if (operands
[0] != operands
[1])
10859 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10864 /* If we are to limit the number of things we put in the TOC and
10865 this is a symbol plus a constant we can add in one insn,
10866 just put the symbol in the TOC and add the constant. */
10867 if (GET_CODE (operands
[1]) == CONST
10868 && TARGET_NO_SUM_IN_TOC
10869 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
10870 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
10871 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
10872 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
10873 && ! side_effects_p (operands
[0]))
10876 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
10877 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
10879 sym
= force_reg (mode
, sym
);
10880 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
10884 operands
[1] = force_const_mem (mode
, operands
[1]);
10887 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
10888 && use_toc_relative_ref (XEXP (operands
[1], 0), mode
))
10890 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
10892 operands
[1] = gen_const_mem (mode
, tocref
);
10893 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
10899 if (!VECTOR_MEM_VSX_P (TImode
))
10900 rs6000_eliminate_indexed_memrefs (operands
);
10904 rs6000_eliminate_indexed_memrefs (operands
);
10908 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
10911 /* Above, we may have called force_const_mem which may have returned
10912 an invalid address. If we can, fix this up; otherwise, reload will
10913 have to deal with it. */
10914 if (GET_CODE (operands
[1]) == MEM
)
10915 operands
[1] = validize_mem (operands
[1]);
10917 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10920 /* Nonzero if we can use a floating-point register to pass this arg. */
10921 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10922 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10923 && (CUM)->fregno <= FP_ARG_MAX_REG \
10924 && TARGET_HARD_FLOAT)
10926 /* Nonzero if we can use an AltiVec register to pass this arg. */
10927 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10928 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10929 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10930 && TARGET_ALTIVEC_ABI \
10933 /* Walk down the type tree of TYPE counting consecutive base elements.
10934 If *MODEP is VOIDmode, then set it to the first valid floating point
10935 or vector type. If a non-floating point or vector type is found, or
10936 if a floating point or vector type that doesn't match a non-VOIDmode
10937 *MODEP is found, then return -1, otherwise return the count in the
10941 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
10944 HOST_WIDE_INT size
;
10946 switch (TREE_CODE (type
))
10949 mode
= TYPE_MODE (type
);
10950 if (!SCALAR_FLOAT_MODE_P (mode
))
10953 if (*modep
== VOIDmode
)
10956 if (*modep
== mode
)
10962 mode
= TYPE_MODE (TREE_TYPE (type
));
10963 if (!SCALAR_FLOAT_MODE_P (mode
))
10966 if (*modep
== VOIDmode
)
10969 if (*modep
== mode
)
10975 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
10978 /* Use V4SImode as representative of all 128-bit vector types. */
10979 size
= int_size_in_bytes (type
);
10989 if (*modep
== VOIDmode
)
10992 /* Vector modes are considered to be opaque: two vectors are
10993 equivalent for the purposes of being homogeneous aggregates
10994 if they are the same size. */
10995 if (*modep
== mode
)
11003 tree index
= TYPE_DOMAIN (type
);
11005 /* Can't handle incomplete types nor sizes that are not
11007 if (!COMPLETE_TYPE_P (type
)
11008 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
11011 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
11014 || !TYPE_MAX_VALUE (index
)
11015 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
11016 || !TYPE_MIN_VALUE (index
)
11017 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
11021 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
11022 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
11024 /* There must be no padding. */
11025 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
11037 /* Can't handle incomplete types nor sizes that are not
11039 if (!COMPLETE_TYPE_P (type
)
11040 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
11043 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
11045 if (TREE_CODE (field
) != FIELD_DECL
)
11048 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
11051 count
+= sub_count
;
11054 /* There must be no padding. */
11055 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
11062 case QUAL_UNION_TYPE
:
11064 /* These aren't very interesting except in a degenerate case. */
11069 /* Can't handle incomplete types nor sizes that are not
11071 if (!COMPLETE_TYPE_P (type
)
11072 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
11075 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
11077 if (TREE_CODE (field
) != FIELD_DECL
)
11080 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
11083 count
= count
> sub_count
? count
: sub_count
;
11086 /* There must be no padding. */
11087 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
11100 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
11101 float or vector aggregate that shall be passed in FP/vector registers
11102 according to the ELFv2 ABI, return the homogeneous element mode in
11103 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
11105 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
11108 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
11109 machine_mode
*elt_mode
,
11112 /* Note that we do not accept complex types at the top level as
11113 homogeneous aggregates; these types are handled via the
11114 targetm.calls.split_complex_arg mechanism. Complex types
11115 can be elements of homogeneous aggregates, however. */
11116 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
11118 machine_mode field_mode
= VOIDmode
;
11119 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
11121 if (field_count
> 0)
11123 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
) ?
11124 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
11126 /* The ELFv2 ABI allows homogeneous aggregates to occupy
11127 up to AGGR_ARG_NUM_REG registers. */
11128 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
11131 *elt_mode
= field_mode
;
11133 *n_elts
= field_count
;
11146 /* Return a nonzero value to say to return the function value in
11147 memory, just as large structures are always returned. TYPE will be
11148 the data type of the value, and FNTYPE will be the type of the
11149 function doing the returning, or @code{NULL} for libcalls.
11151 The AIX ABI for the RS/6000 specifies that all structures are
11152 returned in memory. The Darwin ABI does the same.
11154 For the Darwin 64 Bit ABI, a function result can be returned in
11155 registers or in memory, depending on the size of the return data
11156 type. If it is returned in registers, the value occupies the same
11157 registers as it would if it were the first and only function
11158 argument. Otherwise, the function places its result in memory at
11159 the location pointed to by GPR3.
11161 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
11162 but a draft put them in memory, and GCC used to implement the draft
11163 instead of the final standard. Therefore, aix_struct_return
11164 controls this instead of DEFAULT_ABI; V.4 targets needing backward
11165 compatibility can change DRAFT_V4_STRUCT_RET to override the
11166 default, and -m switches get the final word. See
11167 rs6000_option_override_internal for more details.
11169 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
11170 long double support is enabled. These values are returned in memory.
11172 int_size_in_bytes returns -1 for variable size objects, which go in
11173 memory always. The cast to unsigned makes -1 > 8. */
11176 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
11178 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
11180 && rs6000_darwin64_abi
11181 && TREE_CODE (type
) == RECORD_TYPE
11182 && int_size_in_bytes (type
) > 0)
11184 CUMULATIVE_ARGS valcum
;
11188 valcum
.fregno
= FP_ARG_MIN_REG
;
11189 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
11190 /* Do a trial code generation as if this were going to be passed
11191 as an argument; if any part goes in memory, we return NULL. */
11192 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
11195 /* Otherwise fall through to more conventional ABI rules. */
11198 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11199 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
11203 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11204 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
11205 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
11208 if (AGGREGATE_TYPE_P (type
)
11209 && (aix_struct_return
11210 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
11213 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11214 modes only exist for GCC vector types if -maltivec. */
11215 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
11216 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11219 /* Return synthetic vectors in memory. */
11220 if (TREE_CODE (type
) == VECTOR_TYPE
11221 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
11223 static bool warned_for_return_big_vectors
= false;
11224 if (!warned_for_return_big_vectors
)
11226 warning (OPT_Wpsabi
, "GCC vector returned by reference: "
11227 "non-standard ABI extension with no compatibility "
11229 warned_for_return_big_vectors
= true;
11234 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
11235 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
11241 /* Specify whether values returned in registers should be at the most
11242 significant end of a register. We want aggregates returned by
11243 value to match the way aggregates are passed to functions. */
11246 rs6000_return_in_msb (const_tree valtype
)
11248 return (DEFAULT_ABI
== ABI_ELFv2
11249 && BYTES_BIG_ENDIAN
11250 && AGGREGATE_TYPE_P (valtype
)
11251 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
11254 #ifdef HAVE_AS_GNU_ATTRIBUTE
11255 /* Return TRUE if a call to function FNDECL may be one that
11256 potentially affects the function calling ABI of the object file. */
11259 call_ABI_of_interest (tree fndecl
)
11261 if (rs6000_gnu_attr
&& symtab
->state
== EXPANSION
)
11263 struct cgraph_node
*c_node
;
11265 /* Libcalls are always interesting. */
11266 if (fndecl
== NULL_TREE
)
11269 /* Any call to an external function is interesting. */
11270 if (DECL_EXTERNAL (fndecl
))
11273 /* Interesting functions that we are emitting in this object file. */
11274 c_node
= cgraph_node::get (fndecl
);
11275 c_node
= c_node
->ultimate_alias_target ();
11276 return !c_node
->only_called_directly_p ();
11282 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11283 for a call to a function whose data type is FNTYPE.
11284 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11286 For incoming args we set the number of arguments in the prototype large
11287 so we never return a PARALLEL. */
11290 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
11291 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
11292 int libcall
, int n_named_args
,
11293 tree fndecl ATTRIBUTE_UNUSED
,
11294 machine_mode return_mode ATTRIBUTE_UNUSED
)
11296 static CUMULATIVE_ARGS zero_cumulative
;
11298 *cum
= zero_cumulative
;
11300 cum
->fregno
= FP_ARG_MIN_REG
;
11301 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
11302 cum
->prototype
= (fntype
&& prototype_p (fntype
));
11303 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
11304 ? CALL_LIBCALL
: CALL_NORMAL
);
11305 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
11306 cum
->stdarg
= stdarg_p (fntype
);
11307 cum
->libcall
= libcall
;
11309 cum
->nargs_prototype
= 0;
11310 if (incoming
|| cum
->prototype
)
11311 cum
->nargs_prototype
= n_named_args
;
11313 /* Check for a longcall attribute. */
11314 if ((!fntype
&& rs6000_default_long_calls
)
11316 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
11317 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
11318 cum
->call_cookie
|= CALL_LONG
;
11320 if (TARGET_DEBUG_ARG
)
11322 fprintf (stderr
, "\ninit_cumulative_args:");
11325 tree ret_type
= TREE_TYPE (fntype
);
11326 fprintf (stderr
, " ret code = %s,",
11327 get_tree_code_name (TREE_CODE (ret_type
)));
11330 if (cum
->call_cookie
& CALL_LONG
)
11331 fprintf (stderr
, " longcall,");
11333 fprintf (stderr
, " proto = %d, nargs = %d\n",
11334 cum
->prototype
, cum
->nargs_prototype
);
11337 #ifdef HAVE_AS_GNU_ATTRIBUTE
11338 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
))
11340 cum
->escapes
= call_ABI_of_interest (fndecl
);
11347 return_type
= TREE_TYPE (fntype
);
11348 return_mode
= TYPE_MODE (return_type
);
11351 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
11353 if (return_type
!= NULL
)
11355 if (TREE_CODE (return_type
) == RECORD_TYPE
11356 && TYPE_TRANSPARENT_AGGR (return_type
))
11358 return_type
= TREE_TYPE (first_field (return_type
));
11359 return_mode
= TYPE_MODE (return_type
);
11361 if (AGGREGATE_TYPE_P (return_type
)
11362 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
11364 rs6000_returns_struct
= true;
11366 if (SCALAR_FLOAT_MODE_P (return_mode
))
11368 rs6000_passes_float
= true;
11369 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11370 && (FLOAT128_IBM_P (return_mode
)
11371 || FLOAT128_IEEE_P (return_mode
)
11372 || (return_type
!= NULL
11373 && (TYPE_MAIN_VARIANT (return_type
)
11374 == long_double_type_node
))))
11375 rs6000_passes_long_double
= true;
11377 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
11378 || PAIRED_VECTOR_MODE (return_mode
))
11379 rs6000_passes_vector
= true;
11386 && TARGET_ALTIVEC_ABI
11387 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
11389 error ("cannot return value in vector register because"
11390 " altivec instructions are disabled, use %qs"
11391 " to enable them", "-maltivec");
11395 /* The mode the ABI uses for a word. This is not the same as word_mode
11396 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11398 static machine_mode
11399 rs6000_abi_word_mode (void)
11401 return TARGET_32BIT
? SImode
: DImode
;
11404 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11406 rs6000_offload_options (void)
11409 return xstrdup ("-foffload-abi=lp64");
11411 return xstrdup ("-foffload-abi=ilp32");
11414 /* On rs6000, function arguments are promoted, as are function return
11417 static machine_mode
11418 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
11420 int *punsignedp ATTRIBUTE_UNUSED
,
11423 PROMOTE_MODE (mode
, *punsignedp
, type
);
11428 /* Return true if TYPE must be passed on the stack and not in registers. */
11431 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
11433 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
11434 return must_pass_in_stack_var_size (mode
, type
);
11436 return must_pass_in_stack_var_size_or_pad (mode
, type
);
11440 is_complex_IBM_long_double (machine_mode mode
)
11442 return mode
== ICmode
|| (!TARGET_IEEEQUAD
&& mode
== TCmode
);
11445 /* Whether ABI_V4 passes MODE args to a function in floating point
11449 abi_v4_pass_in_fpr (machine_mode mode
)
11451 if (!TARGET_HARD_FLOAT
)
11453 if (TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
11455 if (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
11457 /* ABI_V4 passes complex IBM long double in 8 gprs.
11458 Stupid, but we can't change the ABI now. */
11459 if (is_complex_IBM_long_double (mode
))
11461 if (FLOAT128_2REG_P (mode
))
11463 if (DECIMAL_FLOAT_MODE_P (mode
))
11468 /* If defined, a C expression which determines whether, and in which
11469 direction, to pad out an argument with extra space. The value
11470 should be of type `enum direction': either `upward' to pad above
11471 the argument, `downward' to pad below, or `none' to inhibit
11474 For the AIX ABI structs are always stored left shifted in their
11478 function_arg_padding (machine_mode mode
, const_tree type
)
11480 #ifndef AGGREGATE_PADDING_FIXED
11481 #define AGGREGATE_PADDING_FIXED 0
11483 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11484 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11487 if (!AGGREGATE_PADDING_FIXED
)
11489 /* GCC used to pass structures of the same size as integer types as
11490 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
11491 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11492 passed padded downward, except that -mstrict-align further
11493 muddied the water in that multi-component structures of 2 and 4
11494 bytes in size were passed padded upward.
11496 The following arranges for best compatibility with previous
11497 versions of gcc, but removes the -mstrict-align dependency. */
11498 if (BYTES_BIG_ENDIAN
)
11500 HOST_WIDE_INT size
= 0;
11502 if (mode
== BLKmode
)
11504 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
11505 size
= int_size_in_bytes (type
);
11508 size
= GET_MODE_SIZE (mode
);
11510 if (size
== 1 || size
== 2 || size
== 4)
11516 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
11518 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
11522 /* Fall back to the default. */
11523 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
11526 /* If defined, a C expression that gives the alignment boundary, in bits,
11527 of an argument with the specified mode and type. If it is not defined,
11528 PARM_BOUNDARY is used for all arguments.
11530 V.4 wants long longs and doubles to be double word aligned. Just
11531 testing the mode size is a boneheaded way to do this as it means
11532 that other types such as complex int are also double word aligned.
11533 However, we're stuck with this because changing the ABI might break
11534 existing library interfaces.
11536 Quadword align Altivec/VSX vectors.
11537 Quadword align large synthetic vector types. */
11539 static unsigned int
11540 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
11542 machine_mode elt_mode
;
11545 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11547 if (DEFAULT_ABI
== ABI_V4
11548 && (GET_MODE_SIZE (mode
) == 8
11549 || (TARGET_HARD_FLOAT
11550 && !is_complex_IBM_long_double (mode
)
11551 && FLOAT128_2REG_P (mode
))))
11553 else if (FLOAT128_VECTOR_P (mode
))
11555 else if (PAIRED_VECTOR_MODE (mode
)
11556 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11557 && int_size_in_bytes (type
) >= 8
11558 && int_size_in_bytes (type
) < 16))
11560 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11561 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11562 && int_size_in_bytes (type
) >= 16))
11565 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11566 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11567 -mcompat-align-parm is used. */
11568 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
11569 || DEFAULT_ABI
== ABI_ELFv2
)
11570 && type
&& TYPE_ALIGN (type
) > 64)
11572 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11573 or homogeneous float/vector aggregates here. We already handled
11574 vector aggregates above, but still need to check for float here. */
11575 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
11576 && !SCALAR_FLOAT_MODE_P (elt_mode
));
11578 /* We used to check for BLKmode instead of the above aggregate type
11579 check. Warn when this results in any difference to the ABI. */
11580 if (aggregate_p
!= (mode
== BLKmode
))
11582 static bool warned
;
11583 if (!warned
&& warn_psabi
)
11586 inform (input_location
,
11587 "the ABI of passing aggregates with %d-byte alignment"
11588 " has changed in GCC 5",
11589 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
11597 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11598 implement the "aggregate type" check as a BLKmode check here; this
11599 means certain aggregate types are in fact not aligned. */
11600 if (TARGET_MACHO
&& rs6000_darwin64_abi
11602 && type
&& TYPE_ALIGN (type
) > 64)
11605 return PARM_BOUNDARY
;
11608 /* The offset in words to the start of the parameter save area. */
11610 static unsigned int
11611 rs6000_parm_offset (void)
11613 return (DEFAULT_ABI
== ABI_V4
? 2
11614 : DEFAULT_ABI
== ABI_ELFv2
? 4
11618 /* For a function parm of MODE and TYPE, return the starting word in
11619 the parameter area. NWORDS of the parameter area are already used. */
11621 static unsigned int
11622 rs6000_parm_start (machine_mode mode
, const_tree type
,
11623 unsigned int nwords
)
11625 unsigned int align
;
11627 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
11628 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
11631 /* Compute the size (in words) of a function argument. */
11633 static unsigned long
11634 rs6000_arg_size (machine_mode mode
, const_tree type
)
11636 unsigned long size
;
11638 if (mode
!= BLKmode
)
11639 size
= GET_MODE_SIZE (mode
);
11641 size
= int_size_in_bytes (type
);
11644 return (size
+ 3) >> 2;
11646 return (size
+ 7) >> 3;
11649 /* Use this to flush pending int fields. */
11652 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
11653 HOST_WIDE_INT bitpos
, int final
)
11655 unsigned int startbit
, endbit
;
11656 int intregs
, intoffset
;
11659 /* Handle the situations where a float is taking up the first half
11660 of the GPR, and the other half is empty (typically due to
11661 alignment restrictions). We can detect this by a 8-byte-aligned
11662 int field, or by seeing that this is the final flush for this
11663 argument. Count the word and continue on. */
11664 if (cum
->floats_in_gpr
== 1
11665 && (cum
->intoffset
% 64 == 0
11666 || (cum
->intoffset
== -1 && final
)))
11669 cum
->floats_in_gpr
= 0;
11672 if (cum
->intoffset
== -1)
11675 intoffset
= cum
->intoffset
;
11676 cum
->intoffset
= -1;
11677 cum
->floats_in_gpr
= 0;
11679 if (intoffset
% BITS_PER_WORD
!= 0)
11681 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
11683 if (mode
== BLKmode
)
11685 /* We couldn't find an appropriate mode, which happens,
11686 e.g., in packed structs when there are 3 bytes to load.
11687 Back intoffset back to the beginning of the word in this
11689 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11693 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11694 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11695 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11696 cum
->words
+= intregs
;
11697 /* words should be unsigned. */
11698 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
11700 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
11705 /* The darwin64 ABI calls for us to recurse down through structs,
11706 looking for elements passed in registers. Unfortunately, we have
11707 to track int register count here also because of misalignments
11708 in powerpc alignment mode. */
11711 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
11713 HOST_WIDE_INT startbitpos
)
11717 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11718 if (TREE_CODE (f
) == FIELD_DECL
)
11720 HOST_WIDE_INT bitpos
= startbitpos
;
11721 tree ftype
= TREE_TYPE (f
);
11723 if (ftype
== error_mark_node
)
11725 mode
= TYPE_MODE (ftype
);
11727 if (DECL_SIZE (f
) != 0
11728 && tree_fits_uhwi_p (bit_position (f
)))
11729 bitpos
+= int_bit_position (f
);
11731 /* ??? FIXME: else assume zero offset. */
11733 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11734 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
11735 else if (USE_FP_FOR_ARG_P (cum
, mode
))
11737 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11738 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11739 cum
->fregno
+= n_fpregs
;
11740 /* Single-precision floats present a special problem for
11741 us, because they are smaller than an 8-byte GPR, and so
11742 the structure-packing rules combined with the standard
11743 varargs behavior mean that we want to pack float/float
11744 and float/int combinations into a single register's
11745 space. This is complicated by the arg advance flushing,
11746 which works on arbitrarily large groups of int-type
11748 if (mode
== SFmode
)
11750 if (cum
->floats_in_gpr
== 1)
11752 /* Two floats in a word; count the word and reset
11753 the float count. */
11755 cum
->floats_in_gpr
= 0;
11757 else if (bitpos
% 64 == 0)
11759 /* A float at the beginning of an 8-byte word;
11760 count it and put off adjusting cum->words until
11761 we see if a arg advance flush is going to do it
11763 cum
->floats_in_gpr
++;
11767 /* The float is at the end of a word, preceded
11768 by integer fields, so the arg advance flush
11769 just above has already set cum->words and
11770 everything is taken care of. */
11774 cum
->words
+= n_fpregs
;
11776 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11778 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11782 else if (cum
->intoffset
== -1)
11783 cum
->intoffset
= bitpos
;
11787 /* Check for an item that needs to be considered specially under the darwin 64
11788 bit ABI. These are record types where the mode is BLK or the structure is
11789 8 bytes in size. */
11791 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
11793 return rs6000_darwin64_abi
11794 && ((mode
== BLKmode
11795 && TREE_CODE (type
) == RECORD_TYPE
11796 && int_size_in_bytes (type
) > 0)
11797 || (type
&& TREE_CODE (type
) == RECORD_TYPE
11798 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
11801 /* Update the data in CUM to advance over an argument
11802 of mode MODE and data type TYPE.
11803 (TYPE is null for libcalls where that information may not be available.)
11805 Note that for args passed by reference, function_arg will be called
11806 with MODE and TYPE set to that of the pointer to the arg, not the arg
11810 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
11811 const_tree type
, bool named
, int depth
)
11813 machine_mode elt_mode
;
11816 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11818 /* Only tick off an argument if we're not recursing. */
11820 cum
->nargs_prototype
--;
11822 #ifdef HAVE_AS_GNU_ATTRIBUTE
11823 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
11826 if (SCALAR_FLOAT_MODE_P (mode
))
11828 rs6000_passes_float
= true;
11829 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11830 && (FLOAT128_IBM_P (mode
)
11831 || FLOAT128_IEEE_P (mode
)
11833 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
)))
11834 rs6000_passes_long_double
= true;
11836 if ((named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
11837 || (PAIRED_VECTOR_MODE (mode
)
11839 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
))
11840 rs6000_passes_vector
= true;
11844 if (TARGET_ALTIVEC_ABI
11845 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11846 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11847 && int_size_in_bytes (type
) == 16)))
11849 bool stack
= false;
11851 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11853 cum
->vregno
+= n_elts
;
11855 if (!TARGET_ALTIVEC
)
11856 error ("cannot pass argument in vector register because"
11857 " altivec instructions are disabled, use %qs"
11858 " to enable them", "-maltivec");
11860 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11861 even if it is going to be passed in a vector register.
11862 Darwin does the same for variable-argument functions. */
11863 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11865 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
11875 /* Vector parameters must be 16-byte aligned. In 32-bit
11876 mode this means we need to take into account the offset
11877 to the parameter save area. In 64-bit mode, they just
11878 have to start on an even word, since the parameter save
11879 area is 16-byte aligned. */
11881 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11883 align
= cum
->words
& 1;
11884 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
11886 if (TARGET_DEBUG_ARG
)
11888 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
11889 cum
->words
, align
);
11890 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
11891 cum
->nargs_prototype
, cum
->prototype
,
11892 GET_MODE_NAME (mode
));
11896 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11898 int size
= int_size_in_bytes (type
);
11899 /* Variable sized types have size == -1 and are
11900 treated as if consisting entirely of ints.
11901 Pad to 16 byte boundary if needed. */
11902 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11903 && (cum
->words
% 2) != 0)
11905 /* For varargs, we can just go up by the size of the struct. */
11907 cum
->words
+= (size
+ 7) / 8;
11910 /* It is tempting to say int register count just goes up by
11911 sizeof(type)/8, but this is wrong in a case such as
11912 { int; double; int; } [powerpc alignment]. We have to
11913 grovel through the fields for these too. */
11914 cum
->intoffset
= 0;
11915 cum
->floats_in_gpr
= 0;
11916 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
11917 rs6000_darwin64_record_arg_advance_flush (cum
,
11918 size
* BITS_PER_UNIT
, 1);
11920 if (TARGET_DEBUG_ARG
)
11922 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
11923 cum
->words
, TYPE_ALIGN (type
), size
);
11925 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11926 cum
->nargs_prototype
, cum
->prototype
,
11927 GET_MODE_NAME (mode
));
11930 else if (DEFAULT_ABI
== ABI_V4
)
11932 if (abi_v4_pass_in_fpr (mode
))
11934 /* _Decimal128 must use an even/odd register pair. This assumes
11935 that the register number is odd when fregno is odd. */
11936 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11939 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11940 <= FP_ARG_V4_MAX_REG
)
11941 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
11944 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
11945 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
11946 || mode
== DDmode
|| mode
== TDmode
)
11947 cum
->words
+= cum
->words
& 1;
11948 cum
->words
+= rs6000_arg_size (mode
, type
);
11953 int n_words
= rs6000_arg_size (mode
, type
);
11954 int gregno
= cum
->sysv_gregno
;
11956 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11957 As does any other 2 word item such as complex int due to a
11958 historical mistake. */
11960 gregno
+= (1 - gregno
) & 1;
11962 /* Multi-reg args are not split between registers and stack. */
11963 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11965 /* Long long is aligned on the stack. So are other 2 word
11966 items such as complex int due to a historical mistake. */
11968 cum
->words
+= cum
->words
& 1;
11969 cum
->words
+= n_words
;
11972 /* Note: continuing to accumulate gregno past when we've started
11973 spilling to the stack indicates the fact that we've started
11974 spilling to the stack to expand_builtin_saveregs. */
11975 cum
->sysv_gregno
= gregno
+ n_words
;
11978 if (TARGET_DEBUG_ARG
)
11980 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11981 cum
->words
, cum
->fregno
);
11982 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
11983 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
11984 fprintf (stderr
, "mode = %4s, named = %d\n",
11985 GET_MODE_NAME (mode
), named
);
11990 int n_words
= rs6000_arg_size (mode
, type
);
11991 int start_words
= cum
->words
;
11992 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
11994 cum
->words
= align_words
+ n_words
;
11996 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
)
11998 /* _Decimal128 must be passed in an even/odd float register pair.
11999 This assumes that the register number is odd when fregno is
12001 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
12003 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
12006 if (TARGET_DEBUG_ARG
)
12008 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
12009 cum
->words
, cum
->fregno
);
12010 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
12011 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
12012 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
12013 named
, align_words
- start_words
, depth
);
12019 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
12020 const_tree type
, bool named
)
12022 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
12026 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
12027 structure between cum->intoffset and bitpos to integer registers. */
12030 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
12031 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
12034 unsigned int regno
;
12035 unsigned int startbit
, endbit
;
12036 int this_regno
, intregs
, intoffset
;
12039 if (cum
->intoffset
== -1)
12042 intoffset
= cum
->intoffset
;
12043 cum
->intoffset
= -1;
12045 /* If this is the trailing part of a word, try to only load that
12046 much into the register. Otherwise load the whole register. Note
12047 that in the latter case we may pick up unwanted bits. It's not a
12048 problem at the moment but may wish to revisit. */
12050 if (intoffset
% BITS_PER_WORD
!= 0)
12052 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
12054 if (mode
== BLKmode
)
12056 /* We couldn't find an appropriate mode, which happens,
12057 e.g., in packed structs when there are 3 bytes to load.
12058 Back intoffset back to the beginning of the word in this
12060 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
12067 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
12068 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
12069 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
12070 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
12072 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
12073 cum
->use_stack
= 1;
12075 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
12079 intoffset
/= BITS_PER_UNIT
;
12082 regno
= GP_ARG_MIN_REG
+ this_regno
;
12083 reg
= gen_rtx_REG (mode
, regno
);
12085 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
12088 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
12092 while (intregs
> 0);
12095 /* Recursive workhorse for the following. */
12098 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
12099 HOST_WIDE_INT startbitpos
, rtx rvec
[],
12104 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
12105 if (TREE_CODE (f
) == FIELD_DECL
)
12107 HOST_WIDE_INT bitpos
= startbitpos
;
12108 tree ftype
= TREE_TYPE (f
);
12110 if (ftype
== error_mark_node
)
12112 mode
= TYPE_MODE (ftype
);
12114 if (DECL_SIZE (f
) != 0
12115 && tree_fits_uhwi_p (bit_position (f
)))
12116 bitpos
+= int_bit_position (f
);
12118 /* ??? FIXME: else assume zero offset. */
12120 if (TREE_CODE (ftype
) == RECORD_TYPE
)
12121 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
12122 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
12124 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
12128 case SCmode
: mode
= SFmode
; break;
12129 case DCmode
: mode
= DFmode
; break;
12130 case TCmode
: mode
= TFmode
; break;
12134 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
12135 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
12137 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
12138 && (mode
== TFmode
|| mode
== TDmode
));
12139 /* Long double or _Decimal128 split over regs and memory. */
12140 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
12144 = gen_rtx_EXPR_LIST (VOIDmode
,
12145 gen_rtx_REG (mode
, cum
->fregno
++),
12146 GEN_INT (bitpos
/ BITS_PER_UNIT
));
12147 if (FLOAT128_2REG_P (mode
))
12150 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
12152 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
12154 = gen_rtx_EXPR_LIST (VOIDmode
,
12155 gen_rtx_REG (mode
, cum
->vregno
++),
12156 GEN_INT (bitpos
/ BITS_PER_UNIT
));
12158 else if (cum
->intoffset
== -1)
12159 cum
->intoffset
= bitpos
;
12163 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12164 the register(s) to be used for each field and subfield of a struct
12165 being passed by value, along with the offset of where the
12166 register's value may be found in the block. FP fields go in FP
12167 register, vector fields go in vector registers, and everything
12168 else goes in int registers, packed as in memory.
12170 This code is also used for function return values. RETVAL indicates
12171 whether this is the case.
12173 Much of this is taken from the SPARC V9 port, which has a similar
12174 calling convention. */
12177 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
12178 bool named
, bool retval
)
12180 rtx rvec
[FIRST_PSEUDO_REGISTER
];
12181 int k
= 1, kbase
= 1;
12182 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
12183 /* This is a copy; modifications are not visible to our caller. */
12184 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
12185 CUMULATIVE_ARGS
*cum
= ©_cum
;
12187 /* Pad to 16 byte boundary if needed. */
12188 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
12189 && (cum
->words
% 2) != 0)
12192 cum
->intoffset
= 0;
12193 cum
->use_stack
= 0;
12194 cum
->named
= named
;
12196 /* Put entries into rvec[] for individual FP and vector fields, and
12197 for the chunks of memory that go in int regs. Note we start at
12198 element 1; 0 is reserved for an indication of using memory, and
12199 may or may not be filled in below. */
12200 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
12201 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
12203 /* If any part of the struct went on the stack put all of it there.
12204 This hack is because the generic code for
12205 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12206 parts of the struct are not at the beginning. */
12207 if (cum
->use_stack
)
12210 return NULL_RTX
; /* doesn't go in registers at all */
12212 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12214 if (k
> 1 || cum
->use_stack
)
12215 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
12220 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12223 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
12228 rtx rvec
[GP_ARG_NUM_REG
+ 1];
12230 if (align_words
>= GP_ARG_NUM_REG
)
12233 n_units
= rs6000_arg_size (mode
, type
);
12235 /* Optimize the simple case where the arg fits in one gpr, except in
12236 the case of BLKmode due to assign_parms assuming that registers are
12237 BITS_PER_WORD wide. */
12239 || (n_units
== 1 && mode
!= BLKmode
))
12240 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12243 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
12244 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12245 using a magic NULL_RTX component.
12246 This is not strictly correct. Only some of the arg belongs in
12247 memory, not all of it. However, the normal scheme using
12248 function_arg_partial_nregs can result in unusual subregs, eg.
12249 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12250 store the whole arg to memory is often more efficient than code
12251 to store pieces, and we know that space is available in the right
12252 place for the whole arg. */
12253 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12258 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
12259 rtx off
= GEN_INT (i
++ * 4);
12260 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12262 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
12264 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
12267 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12268 but must also be copied into the parameter save area starting at
12269 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12270 to the GPRs and/or memory. Return the number of elements used. */
12273 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
12274 int align_words
, rtx
*rvec
)
12278 if (align_words
< GP_ARG_NUM_REG
)
12280 int n_words
= rs6000_arg_size (mode
, type
);
12282 if (align_words
+ n_words
> GP_ARG_NUM_REG
12284 || (TARGET_32BIT
&& TARGET_POWERPC64
))
12286 /* If this is partially on the stack, then we only
12287 include the portion actually in registers here. */
12288 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
12291 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
12293 /* Not all of the arg fits in gprs. Say that it goes in memory
12294 too, using a magic NULL_RTX component. Also see comment in
12295 rs6000_mixed_function_arg for why the normal
12296 function_arg_partial_nregs scheme doesn't work in this case. */
12297 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12302 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
12303 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
12304 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12306 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
12310 /* The whole arg fits in gprs. */
12311 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12312 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
12317 /* It's entirely in memory. */
12318 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12324 /* RVEC is a vector of K components of an argument of mode MODE.
12325 Construct the final function_arg return value from it. */
12328 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
12330 gcc_assert (k
>= 1);
12332 /* Avoid returning a PARALLEL in the trivial cases. */
12335 if (XEXP (rvec
[0], 0) == NULL_RTX
)
12338 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
12339 return XEXP (rvec
[0], 0);
12342 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
12345 /* Determine where to put an argument to a function.
12346 Value is zero to push the argument on the stack,
12347 or a hard register in which to store the argument.
12349 MODE is the argument's machine mode.
12350 TYPE is the data type of the argument (as a tree).
12351 This is null for libcalls where that information may
12353 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12354 the preceding args and about the function being called. It is
12355 not modified in this routine.
12356 NAMED is nonzero if this argument is a named parameter
12357 (otherwise it is an extra parameter matching an ellipsis).
12359 On RS/6000 the first eight words of non-FP are normally in registers
12360 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12361 Under V.4, the first 8 FP args are in registers.
12363 If this is floating-point and no prototype is specified, we use
12364 both an FP and integer register (or possibly FP reg and stack). Library
12365 functions (when CALL_LIBCALL is set) always have the proper types for args,
12366 so we can pass the FP value just in one register. emit_library_function
12367 doesn't support PARALLEL anyway.
12369 Note that for args passed by reference, function_arg will be called
12370 with MODE and TYPE set to that of the pointer to the arg, not the arg
12374 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
12375 const_tree type
, bool named
)
12377 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12378 enum rs6000_abi abi
= DEFAULT_ABI
;
12379 machine_mode elt_mode
;
12382 /* Return a marker to indicate whether CR1 needs to set or clear the
12383 bit that V.4 uses to say fp args were passed in registers.
12384 Assume that we don't need the marker for software floating point,
12385 or compiler generated library calls. */
12386 if (mode
== VOIDmode
)
12389 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
12391 || (cum
->nargs_prototype
< 0
12392 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
)))
12393 && TARGET_HARD_FLOAT
)
12394 return GEN_INT (cum
->call_cookie
12395 | ((cum
->fregno
== FP_ARG_MIN_REG
)
12396 ? CALL_V4_SET_FP_ARGS
12397 : CALL_V4_CLEAR_FP_ARGS
));
12399 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
12402 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12404 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12406 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
12407 if (rslt
!= NULL_RTX
)
12409 /* Else fall through to usual handling. */
12412 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12414 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
12418 /* Do we also need to pass this argument in the parameter save area?
12419 Library support functions for IEEE 128-bit are assumed to not need the
12420 value passed both in GPRs and in vector registers. */
12421 if (TARGET_64BIT
&& !cum
->prototype
12422 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12424 int align_words
= ROUND_UP (cum
->words
, 2);
12425 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
12428 /* Describe where this argument goes in the vector registers. */
12429 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
12431 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
12432 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
12433 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12436 return rs6000_finish_function_arg (mode
, rvec
, k
);
12438 else if (TARGET_ALTIVEC_ABI
12439 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
12440 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
12441 && int_size_in_bytes (type
) == 16)))
12443 if (named
|| abi
== ABI_V4
)
12447 /* Vector parameters to varargs functions under AIX or Darwin
12448 get passed in memory and possibly also in GPRs. */
12449 int align
, align_words
, n_words
;
12450 machine_mode part_mode
;
12452 /* Vector parameters must be 16-byte aligned. In 32-bit
12453 mode this means we need to take into account the offset
12454 to the parameter save area. In 64-bit mode, they just
12455 have to start on an even word, since the parameter save
12456 area is 16-byte aligned. */
12458 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
12460 align
= cum
->words
& 1;
12461 align_words
= cum
->words
+ align
;
12463 /* Out of registers? Memory, then. */
12464 if (align_words
>= GP_ARG_NUM_REG
)
12467 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12468 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12470 /* The vector value goes in GPRs. Only the part of the
12471 value in GPRs is reported here. */
12473 n_words
= rs6000_arg_size (mode
, type
);
12474 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
12475 /* Fortunately, there are only two possibilities, the value
12476 is either wholly in GPRs or half in GPRs and half not. */
12477 part_mode
= DImode
;
12479 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
12483 else if (abi
== ABI_V4
)
12485 if (abi_v4_pass_in_fpr (mode
))
12487 /* _Decimal128 must use an even/odd register pair. This assumes
12488 that the register number is odd when fregno is odd. */
12489 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
12492 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
12493 <= FP_ARG_V4_MAX_REG
)
12494 return gen_rtx_REG (mode
, cum
->fregno
);
12500 int n_words
= rs6000_arg_size (mode
, type
);
12501 int gregno
= cum
->sysv_gregno
;
12503 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12504 As does any other 2 word item such as complex int due to a
12505 historical mistake. */
12507 gregno
+= (1 - gregno
) & 1;
12509 /* Multi-reg args are not split between registers and stack. */
12510 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
12513 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12514 return rs6000_mixed_function_arg (mode
, type
,
12515 gregno
- GP_ARG_MIN_REG
);
12516 return gen_rtx_REG (mode
, gregno
);
12521 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12523 /* _Decimal128 must be passed in an even/odd float register pair.
12524 This assumes that the register number is odd when fregno is odd. */
12525 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
12528 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
12530 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
12533 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12536 /* Do we also need to pass this argument in the parameter
12538 if (type
&& (cum
->nargs_prototype
<= 0
12539 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12540 && TARGET_XL_COMPAT
12541 && align_words
>= GP_ARG_NUM_REG
)))
12542 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
12544 /* Describe where this argument goes in the fprs. */
12545 for (i
= 0; i
< n_elts
12546 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
12548 /* Check if the argument is split over registers and memory.
12549 This can only ever happen for long double or _Decimal128;
12550 complex types are handled via split_complex_arg. */
12551 machine_mode fmode
= elt_mode
;
12552 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
12554 gcc_assert (FLOAT128_2REG_P (fmode
));
12555 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
12558 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
12559 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
12560 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12563 /* If there were not enough FPRs to hold the argument, the rest
12564 usually goes into memory. However, if the current position
12565 is still within the register parameter area, a portion may
12566 actually have to go into GPRs.
12568 Note that it may happen that the portion of the argument
12569 passed in the first "half" of the first GPR was already
12570 passed in the last FPR as well.
12572 For unnamed arguments, we already set up GPRs to cover the
12573 whole argument in rs6000_psave_function_arg, so there is
12574 nothing further to do at this point. */
12575 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
12576 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
12577 && cum
->nargs_prototype
> 0)
12579 static bool warned
;
12581 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
12582 int n_words
= rs6000_arg_size (mode
, type
);
12584 align_words
+= fpr_words
;
12585 n_words
-= fpr_words
;
12589 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
12590 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
12591 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12593 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
12595 if (!warned
&& warn_psabi
)
12598 inform (input_location
,
12599 "the ABI of passing homogeneous float aggregates"
12600 " has changed in GCC 5");
12604 return rs6000_finish_function_arg (mode
, rvec
, k
);
12606 else if (align_words
< GP_ARG_NUM_REG
)
12608 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12609 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12611 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12618 /* For an arg passed partly in registers and partly in memory, this is
12619 the number of bytes passed in registers. For args passed entirely in
12620 registers or entirely in memory, zero. When an arg is described by a
12621 PARALLEL, perhaps using more than one register type, this function
12622 returns the number of bytes used by the first element of the PARALLEL. */
12625 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
12626 tree type
, bool named
)
12628 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12629 bool passed_in_gprs
= true;
12632 machine_mode elt_mode
;
12635 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12637 if (DEFAULT_ABI
== ABI_V4
)
12640 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12642 /* If we are passing this arg in the fixed parameter save area (gprs or
12643 memory) as well as VRs, we do not use the partial bytes mechanism;
12644 instead, rs6000_function_arg will return a PARALLEL including a memory
12645 element as necessary. Library support functions for IEEE 128-bit are
12646 assumed to not need the value passed both in GPRs and in vector
12648 if (TARGET_64BIT
&& !cum
->prototype
12649 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12652 /* Otherwise, we pass in VRs only. Check for partial copies. */
12653 passed_in_gprs
= false;
12654 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
12655 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
12658 /* In this complicated case we just disable the partial_nregs code. */
12659 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12662 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12664 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
12666 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12668 /* If we are passing this arg in the fixed parameter save area
12669 (gprs or memory) as well as FPRs, we do not use the partial
12670 bytes mechanism; instead, rs6000_function_arg will return a
12671 PARALLEL including a memory element as necessary. */
12673 && (cum
->nargs_prototype
<= 0
12674 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12675 && TARGET_XL_COMPAT
12676 && align_words
>= GP_ARG_NUM_REG
)))
12679 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12680 passed_in_gprs
= false;
12681 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
12683 /* Compute number of bytes / words passed in FPRs. If there
12684 is still space available in the register parameter area
12685 *after* that amount, a part of the argument will be passed
12686 in GPRs. In that case, the total amount passed in any
12687 registers is equal to the amount that would have been passed
12688 in GPRs if everything were passed there, so we fall back to
12689 the GPR code below to compute the appropriate value. */
12690 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
12691 * MIN (8, GET_MODE_SIZE (elt_mode
)));
12692 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
12694 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
12695 passed_in_gprs
= true;
12702 && align_words
< GP_ARG_NUM_REG
12703 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
12704 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
12706 if (ret
!= 0 && TARGET_DEBUG_ARG
)
12707 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
12712 /* A C expression that indicates when an argument must be passed by
12713 reference. If nonzero for an argument, a copy of that argument is
12714 made in memory and a pointer to the argument is passed instead of
12715 the argument itself. The pointer is passed in whatever way is
12716 appropriate for passing a pointer to that type.
12718 Under V.4, aggregates and long double are passed by reference.
12720 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12721 reference unless the AltiVec vector extension ABI is in force.
12723 As an extension to all ABIs, variable sized types are passed by
12727 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
12728 machine_mode mode
, const_tree type
,
12729 bool named ATTRIBUTE_UNUSED
)
12734 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
12735 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
12737 if (TARGET_DEBUG_ARG
)
12738 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12742 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
12744 if (TARGET_DEBUG_ARG
)
12745 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
12749 if (int_size_in_bytes (type
) < 0)
12751 if (TARGET_DEBUG_ARG
)
12752 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
12756 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12757 modes only exist for GCC vector types if -maltivec. */
12758 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12760 if (TARGET_DEBUG_ARG
)
12761 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
12765 /* Pass synthetic vectors in memory. */
12766 if (TREE_CODE (type
) == VECTOR_TYPE
12767 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
12769 static bool warned_for_pass_big_vectors
= false;
12770 if (TARGET_DEBUG_ARG
)
12771 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
12772 if (!warned_for_pass_big_vectors
)
12774 warning (OPT_Wpsabi
, "GCC vector passed by reference: "
12775 "non-standard ABI extension with no compatibility "
12777 warned_for_pass_big_vectors
= true;
12785 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12786 already processes. Return true if the parameter must be passed
12787 (fully or partially) on the stack. */
12790 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
12796 /* Catch errors. */
12797 if (type
== NULL
|| type
== error_mark_node
)
12800 /* Handle types with no storage requirement. */
12801 if (TYPE_MODE (type
) == VOIDmode
)
12804 /* Handle complex types. */
12805 if (TREE_CODE (type
) == COMPLEX_TYPE
)
12806 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
12807 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
12809 /* Handle transparent aggregates. */
12810 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
12811 && TYPE_TRANSPARENT_AGGR (type
))
12812 type
= TREE_TYPE (first_field (type
));
12814 /* See if this arg was passed by invisible reference. */
12815 if (pass_by_reference (get_cumulative_args (args_so_far
),
12816 TYPE_MODE (type
), type
, true))
12817 type
= build_pointer_type (type
);
12819 /* Find mode as it is passed by the ABI. */
12820 unsignedp
= TYPE_UNSIGNED (type
);
12821 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
12823 /* If we must pass in stack, we need a stack. */
12824 if (rs6000_must_pass_in_stack (mode
, type
))
12827 /* If there is no incoming register, we need a stack. */
12828 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
12829 if (entry_parm
== NULL
)
12832 /* Likewise if we need to pass both in registers and on the stack. */
12833 if (GET_CODE (entry_parm
) == PARALLEL
12834 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
12837 /* Also true if we're partially in registers and partially not. */
12838 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
12841 /* Update info on where next arg arrives in registers. */
12842 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
12846 /* Return true if FUN has no prototype, has a variable argument
12847 list, or passes any parameter in memory. */
12850 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
12852 tree fntype
, result
;
12853 CUMULATIVE_ARGS args_so_far_v
;
12854 cumulative_args_t args_so_far
;
12857 /* Must be a libcall, all of which only use reg parms. */
12862 fntype
= TREE_TYPE (fun
);
12864 /* Varargs functions need the parameter save area. */
12865 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
12868 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
12869 args_so_far
= pack_cumulative_args (&args_so_far_v
);
12871 /* When incoming, we will have been passed the function decl.
12872 It is necessary to use the decl to handle K&R style functions,
12873 where TYPE_ARG_TYPES may not be available. */
12876 gcc_assert (DECL_P (fun
));
12877 result
= DECL_RESULT (fun
);
12880 result
= TREE_TYPE (fntype
);
12882 if (result
&& aggregate_value_p (result
, fntype
))
12884 if (!TYPE_P (result
))
12885 result
= TREE_TYPE (result
);
12886 result
= build_pointer_type (result
);
12887 rs6000_parm_needs_stack (args_so_far
, result
);
12894 for (parm
= DECL_ARGUMENTS (fun
);
12895 parm
&& parm
!= void_list_node
;
12896 parm
= TREE_CHAIN (parm
))
12897 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
12902 function_args_iterator args_iter
;
12905 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
12906 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
12913 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12914 usually a constant depending on the ABI. However, in the ELFv2 ABI
12915 the register parameter area is optional when calling a function that
12916 has a prototype is scope, has no variable argument list, and passes
12917 all parameters in registers. */
12920 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
12922 int reg_parm_stack_space
;
12924 switch (DEFAULT_ABI
)
12927 reg_parm_stack_space
= 0;
12932 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12936 /* ??? Recomputing this every time is a bit expensive. Is there
12937 a place to cache this information? */
12938 if (rs6000_function_parms_need_stack (fun
, incoming
))
12939 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12941 reg_parm_stack_space
= 0;
12945 return reg_parm_stack_space
;
12949 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
12952 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
12957 for (i
= 0; i
< nregs
; i
++)
12959 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
12960 if (reload_completed
)
12962 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
12965 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
12966 i
* GET_MODE_SIZE (reg_mode
));
12969 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
12973 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
12977 /* Perform any needed actions needed for a function that is receiving a
12978 variable number of arguments.
12982 MODE and TYPE are the mode and type of the current parameter.
12984 PRETEND_SIZE is a variable that should be set to the amount of stack
12985 that must be pushed by the prolog to pretend that our caller pushed
12988 Normally, this macro will push all remaining incoming registers on the
12989 stack and set PRETEND_SIZE to the length of the registers pushed. */
12992 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
12993 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
12996 CUMULATIVE_ARGS next_cum
;
12997 int reg_size
= TARGET_32BIT
? 4 : 8;
12998 rtx save_area
= NULL_RTX
, mem
;
12999 int first_reg_offset
;
13000 alias_set_type set
;
13002 /* Skip the last named argument. */
13003 next_cum
= *get_cumulative_args (cum
);
13004 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
13006 if (DEFAULT_ABI
== ABI_V4
)
13008 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
13012 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
13013 HOST_WIDE_INT offset
= 0;
13015 /* Try to optimize the size of the varargs save area.
13016 The ABI requires that ap.reg_save_area is doubleword
13017 aligned, but we don't need to allocate space for all
13018 the bytes, only those to which we actually will save
13020 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
13021 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
13022 if (TARGET_HARD_FLOAT
13023 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
13024 && cfun
->va_list_fpr_size
)
13027 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
13028 * UNITS_PER_FP_WORD
;
13029 if (cfun
->va_list_fpr_size
13030 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
13031 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
13033 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
13034 * UNITS_PER_FP_WORD
;
13038 offset
= -((first_reg_offset
* reg_size
) & ~7);
13039 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
13041 gpr_reg_num
= cfun
->va_list_gpr_size
;
13042 if (reg_size
== 4 && (first_reg_offset
& 1))
13045 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
13048 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
13049 * UNITS_PER_FP_WORD
13050 - (int) (GP_ARG_NUM_REG
* reg_size
);
13052 if (gpr_size
+ fpr_size
)
13055 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
13056 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
13057 reg_save_area
= XEXP (reg_save_area
, 0);
13058 if (GET_CODE (reg_save_area
) == PLUS
)
13060 gcc_assert (XEXP (reg_save_area
, 0)
13061 == virtual_stack_vars_rtx
);
13062 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
13063 offset
+= INTVAL (XEXP (reg_save_area
, 1));
13066 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
13069 cfun
->machine
->varargs_save_offset
= offset
;
13070 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
13075 first_reg_offset
= next_cum
.words
;
13076 save_area
= crtl
->args
.internal_arg_pointer
;
13078 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
13079 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
13082 set
= get_varargs_alias_set ();
13083 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
13084 && cfun
->va_list_gpr_size
)
13086 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
13088 if (va_list_gpr_counter_field
)
13089 /* V4 va_list_gpr_size counts number of registers needed. */
13090 n_gpr
= cfun
->va_list_gpr_size
;
13092 /* char * va_list instead counts number of bytes needed. */
13093 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
13098 mem
= gen_rtx_MEM (BLKmode
,
13099 plus_constant (Pmode
, save_area
,
13100 first_reg_offset
* reg_size
));
13101 MEM_NOTRAP_P (mem
) = 1;
13102 set_mem_alias_set (mem
, set
);
13103 set_mem_align (mem
, BITS_PER_WORD
);
13105 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
13109 /* Save FP registers if needed. */
13110 if (DEFAULT_ABI
== ABI_V4
13111 && TARGET_HARD_FLOAT
13113 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
13114 && cfun
->va_list_fpr_size
)
13116 int fregno
= next_cum
.fregno
, nregs
;
13117 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
13118 rtx lab
= gen_label_rtx ();
13119 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
13120 * UNITS_PER_FP_WORD
);
13123 (gen_rtx_SET (pc_rtx
,
13124 gen_rtx_IF_THEN_ELSE (VOIDmode
,
13125 gen_rtx_NE (VOIDmode
, cr1
,
13127 gen_rtx_LABEL_REF (VOIDmode
, lab
),
13131 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
13132 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
13134 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
13136 plus_constant (Pmode
, save_area
, off
));
13137 MEM_NOTRAP_P (mem
) = 1;
13138 set_mem_alias_set (mem
, set
);
13139 set_mem_align (mem
, GET_MODE_ALIGNMENT (
13140 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
13141 ? DFmode
: SFmode
));
13142 emit_move_insn (mem
, gen_rtx_REG (
13143 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
13144 ? DFmode
: SFmode
, fregno
));
13151 /* Create the va_list data type. */
13154 rs6000_build_builtin_va_list (void)
13156 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
13158 /* For AIX, prefer 'char *' because that's what the system
13159 header files like. */
13160 if (DEFAULT_ABI
!= ABI_V4
)
13161 return build_pointer_type (char_type_node
);
13163 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
13164 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
13165 get_identifier ("__va_list_tag"), record
);
13167 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
13168 unsigned_char_type_node
);
13169 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
13170 unsigned_char_type_node
);
13171 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13172 every user file. */
13173 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
13174 get_identifier ("reserved"), short_unsigned_type_node
);
13175 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
13176 get_identifier ("overflow_arg_area"),
13178 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
13179 get_identifier ("reg_save_area"),
13182 va_list_gpr_counter_field
= f_gpr
;
13183 va_list_fpr_counter_field
= f_fpr
;
13185 DECL_FIELD_CONTEXT (f_gpr
) = record
;
13186 DECL_FIELD_CONTEXT (f_fpr
) = record
;
13187 DECL_FIELD_CONTEXT (f_res
) = record
;
13188 DECL_FIELD_CONTEXT (f_ovf
) = record
;
13189 DECL_FIELD_CONTEXT (f_sav
) = record
;
13191 TYPE_STUB_DECL (record
) = type_decl
;
13192 TYPE_NAME (record
) = type_decl
;
13193 TYPE_FIELDS (record
) = f_gpr
;
13194 DECL_CHAIN (f_gpr
) = f_fpr
;
13195 DECL_CHAIN (f_fpr
) = f_res
;
13196 DECL_CHAIN (f_res
) = f_ovf
;
13197 DECL_CHAIN (f_ovf
) = f_sav
;
13199 layout_type (record
);
13201 /* The correct type is an array type of one element. */
13202 return build_array_type (record
, build_index_type (size_zero_node
));
13205 /* Implement va_start. */
13208 rs6000_va_start (tree valist
, rtx nextarg
)
13210 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
13211 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
13212 tree gpr
, fpr
, ovf
, sav
, t
;
13214 /* Only SVR4 needs something special. */
13215 if (DEFAULT_ABI
!= ABI_V4
)
13217 std_expand_builtin_va_start (valist
, nextarg
);
13221 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
13222 f_fpr
= DECL_CHAIN (f_gpr
);
13223 f_res
= DECL_CHAIN (f_fpr
);
13224 f_ovf
= DECL_CHAIN (f_res
);
13225 f_sav
= DECL_CHAIN (f_ovf
);
13227 valist
= build_simple_mem_ref (valist
);
13228 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
13229 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
13231 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
13233 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
13236 /* Count number of gp and fp argument registers used. */
13237 words
= crtl
->args
.info
.words
;
13238 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
13240 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
13243 if (TARGET_DEBUG_ARG
)
13244 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
13245 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
13246 words
, n_gpr
, n_fpr
);
13248 if (cfun
->va_list_gpr_size
)
13250 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
13251 build_int_cst (NULL_TREE
, n_gpr
));
13252 TREE_SIDE_EFFECTS (t
) = 1;
13253 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13256 if (cfun
->va_list_fpr_size
)
13258 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
13259 build_int_cst (NULL_TREE
, n_fpr
));
13260 TREE_SIDE_EFFECTS (t
) = 1;
13261 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13263 #ifdef HAVE_AS_GNU_ATTRIBUTE
13264 if (call_ABI_of_interest (cfun
->decl
))
13265 rs6000_passes_float
= true;
13269 /* Find the overflow area. */
13270 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
13272 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
13273 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
13274 TREE_SIDE_EFFECTS (t
) = 1;
13275 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13277 /* If there were no va_arg invocations, don't set up the register
13279 if (!cfun
->va_list_gpr_size
13280 && !cfun
->va_list_fpr_size
13281 && n_gpr
< GP_ARG_NUM_REG
13282 && n_fpr
< FP_ARG_V4_MAX_REG
)
13285 /* Find the register save area. */
13286 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
13287 if (cfun
->machine
->varargs_save_offset
)
13288 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
13289 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
13290 TREE_SIDE_EFFECTS (t
) = 1;
13291 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13294 /* Implement va_arg. */
13297 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
13298 gimple_seq
*post_p
)
13300 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
13301 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
13302 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
13303 tree lab_false
, lab_over
, addr
;
13305 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
13309 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
13311 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
13312 return build_va_arg_indirect_ref (t
);
13315 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13316 earlier version of gcc, with the property that it always applied alignment
13317 adjustments to the va-args (even for zero-sized types). The cheapest way
13318 to deal with this is to replicate the effect of the part of
13319 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13321 We don't need to check for pass-by-reference because of the test above.
13322 We can return a simplifed answer, since we know there's no offset to add. */
13325 && rs6000_darwin64_abi
)
13326 || DEFAULT_ABI
== ABI_ELFv2
13327 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
13328 && integer_zerop (TYPE_SIZE (type
)))
13330 unsigned HOST_WIDE_INT align
, boundary
;
13331 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
13332 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
13333 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
13334 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
13335 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
13336 boundary
/= BITS_PER_UNIT
;
13337 if (boundary
> align
)
13340 /* This updates arg ptr by the amount that would be necessary
13341 to align the zero-sized (but not zero-alignment) item. */
13342 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
13343 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
13344 gimplify_and_add (t
, pre_p
);
13346 t
= fold_convert (sizetype
, valist_tmp
);
13347 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
13348 fold_convert (TREE_TYPE (valist
),
13349 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
13350 size_int (-boundary
))));
13351 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
13352 gimplify_and_add (t
, pre_p
);
13354 /* Since it is zero-sized there's no increment for the item itself. */
13355 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
13356 return build_va_arg_indirect_ref (valist_tmp
);
13359 if (DEFAULT_ABI
!= ABI_V4
)
13361 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
13363 tree elem_type
= TREE_TYPE (type
);
13364 machine_mode elem_mode
= TYPE_MODE (elem_type
);
13365 int elem_size
= GET_MODE_SIZE (elem_mode
);
13367 if (elem_size
< UNITS_PER_WORD
)
13369 tree real_part
, imag_part
;
13370 gimple_seq post
= NULL
;
13372 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
13374 /* Copy the value into a temporary, lest the formal temporary
13375 be reused out from under us. */
13376 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
13377 gimple_seq_add_seq (pre_p
, post
);
13379 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
13382 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
13386 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
13389 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
13390 f_fpr
= DECL_CHAIN (f_gpr
);
13391 f_res
= DECL_CHAIN (f_fpr
);
13392 f_ovf
= DECL_CHAIN (f_res
);
13393 f_sav
= DECL_CHAIN (f_ovf
);
13395 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
13396 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
13398 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
13400 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
13403 size
= int_size_in_bytes (type
);
13404 rsize
= (size
+ 3) / 4;
13405 int pad
= 4 * rsize
- size
;
13408 machine_mode mode
= TYPE_MODE (type
);
13409 if (abi_v4_pass_in_fpr (mode
))
13411 /* FP args go in FP registers, if present. */
13413 n_reg
= (size
+ 7) / 8;
13414 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
13415 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
13416 if (mode
!= SFmode
&& mode
!= SDmode
)
13421 /* Otherwise into GP registers. */
13430 /* Pull the value out of the saved registers.... */
13433 addr
= create_tmp_var (ptr_type_node
, "addr");
13435 /* AltiVec vectors never go in registers when -mabi=altivec. */
13436 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
13440 lab_false
= create_artificial_label (input_location
);
13441 lab_over
= create_artificial_label (input_location
);
13443 /* Long long is aligned in the registers. As are any other 2 gpr
13444 item such as complex int due to a historical mistake. */
13446 if (n_reg
== 2 && reg
== gpr
)
13449 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
13450 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
13451 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
13452 unshare_expr (reg
), u
);
13454 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13455 reg number is 0 for f1, so we want to make it odd. */
13456 else if (reg
== fpr
&& mode
== TDmode
)
13458 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
13459 build_int_cst (TREE_TYPE (reg
), 1));
13460 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
13463 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
13464 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
13465 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
13466 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
13467 gimplify_and_add (t
, pre_p
);
13471 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
13473 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
13474 build_int_cst (TREE_TYPE (reg
), n_reg
));
13475 u
= fold_convert (sizetype
, u
);
13476 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
13477 t
= fold_build_pointer_plus (t
, u
);
13479 /* _Decimal32 varargs are located in the second word of the 64-bit
13480 FP register for 32-bit binaries. */
13481 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
&& mode
== SDmode
)
13482 t
= fold_build_pointer_plus_hwi (t
, size
);
13484 /* Args are passed right-aligned. */
13485 if (BYTES_BIG_ENDIAN
)
13486 t
= fold_build_pointer_plus_hwi (t
, pad
);
13488 gimplify_assign (addr
, t
, pre_p
);
13490 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
13492 stmt
= gimple_build_label (lab_false
);
13493 gimple_seq_add_stmt (pre_p
, stmt
);
13495 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
13497 /* Ensure that we don't find any more args in regs.
13498 Alignment has taken care of for special cases. */
13499 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
13503 /* ... otherwise out of the overflow area. */
13505 /* Care for on-stack alignment if needed. */
13509 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
13510 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
13511 build_int_cst (TREE_TYPE (t
), -align
));
13514 /* Args are passed right-aligned. */
13515 if (BYTES_BIG_ENDIAN
)
13516 t
= fold_build_pointer_plus_hwi (t
, pad
);
13518 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
13520 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
13522 t
= fold_build_pointer_plus_hwi (t
, size
);
13523 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
13527 stmt
= gimple_build_label (lab_over
);
13528 gimple_seq_add_stmt (pre_p
, stmt
);
13531 if (STRICT_ALIGNMENT
13532 && (TYPE_ALIGN (type
)
13533 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
13535 /* The value (of type complex double, for example) may not be
13536 aligned in memory in the saved registers, so copy via a
13537 temporary. (This is the same code as used for SPARC.) */
13538 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
13539 tree dest_addr
= build_fold_addr_expr (tmp
);
13541 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
13542 3, dest_addr
, addr
, size_int (rsize
* 4));
13544 gimplify_and_add (copy
, pre_p
);
13548 addr
= fold_convert (ptrtype
, addr
);
13549 return build_va_arg_indirect_ref (addr
);
13555 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
13558 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
13559 const char *attr_string
= "";
13561 gcc_assert (name
!= NULL
);
13562 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
13564 if (rs6000_builtin_decls
[(int)code
])
13565 fatal_error (input_location
,
13566 "internal error: builtin function %qs already processed",
13569 rs6000_builtin_decls
[(int)code
] = t
=
13570 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
13572 /* Set any special attributes. */
13573 if ((classify
& RS6000_BTC_CONST
) != 0)
13575 /* const function, function only depends on the inputs. */
13576 TREE_READONLY (t
) = 1;
13577 TREE_NOTHROW (t
) = 1;
13578 attr_string
= ", const";
13580 else if ((classify
& RS6000_BTC_PURE
) != 0)
13582 /* pure function, function can read global memory, but does not set any
13584 DECL_PURE_P (t
) = 1;
13585 TREE_NOTHROW (t
) = 1;
13586 attr_string
= ", pure";
13588 else if ((classify
& RS6000_BTC_FP
) != 0)
13590 /* Function is a math function. If rounding mode is on, then treat the
13591 function as not reading global memory, but it can have arbitrary side
13592 effects. If it is off, then assume the function is a const function.
13593 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13594 builtin-attribute.def that is used for the math functions. */
13595 TREE_NOTHROW (t
) = 1;
13596 if (flag_rounding_math
)
13598 DECL_PURE_P (t
) = 1;
13599 DECL_IS_NOVOPS (t
) = 1;
13600 attr_string
= ", fp, pure";
13604 TREE_READONLY (t
) = 1;
13605 attr_string
= ", fp, const";
13608 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
13609 gcc_unreachable ();
13611 if (TARGET_DEBUG_BUILTIN
)
13612 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
13613 (int)code
, name
, attr_string
);
13616 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13618 #undef RS6000_BUILTIN_0
13619 #undef RS6000_BUILTIN_1
13620 #undef RS6000_BUILTIN_2
13621 #undef RS6000_BUILTIN_3
13622 #undef RS6000_BUILTIN_A
13623 #undef RS6000_BUILTIN_D
13624 #undef RS6000_BUILTIN_H
13625 #undef RS6000_BUILTIN_P
13626 #undef RS6000_BUILTIN_Q
13627 #undef RS6000_BUILTIN_X
13629 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13630 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13631 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13632 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13633 { MASK, ICODE, NAME, ENUM },
13635 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13636 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13637 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13638 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13639 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13640 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13642 static const struct builtin_description bdesc_3arg
[] =
13644 #include "rs6000-builtin.def"
13647 /* DST operations: void foo (void *, const int, const char). */
13649 #undef RS6000_BUILTIN_0
13650 #undef RS6000_BUILTIN_1
13651 #undef RS6000_BUILTIN_2
13652 #undef RS6000_BUILTIN_3
13653 #undef RS6000_BUILTIN_A
13654 #undef RS6000_BUILTIN_D
13655 #undef RS6000_BUILTIN_H
13656 #undef RS6000_BUILTIN_P
13657 #undef RS6000_BUILTIN_Q
13658 #undef RS6000_BUILTIN_X
13660 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13661 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13662 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13663 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13664 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13665 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13666 { MASK, ICODE, NAME, ENUM },
13668 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13669 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13670 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13671 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13673 static const struct builtin_description bdesc_dst
[] =
13675 #include "rs6000-builtin.def"
13678 /* Simple binary operations: VECc = foo (VECa, VECb). */
13680 #undef RS6000_BUILTIN_0
13681 #undef RS6000_BUILTIN_1
13682 #undef RS6000_BUILTIN_2
13683 #undef RS6000_BUILTIN_3
13684 #undef RS6000_BUILTIN_A
13685 #undef RS6000_BUILTIN_D
13686 #undef RS6000_BUILTIN_H
13687 #undef RS6000_BUILTIN_P
13688 #undef RS6000_BUILTIN_Q
13689 #undef RS6000_BUILTIN_X
13691 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13692 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13693 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13694 { MASK, ICODE, NAME, ENUM },
13696 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13697 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13698 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13699 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13700 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13701 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13702 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13704 static const struct builtin_description bdesc_2arg
[] =
13706 #include "rs6000-builtin.def"
13709 #undef RS6000_BUILTIN_0
13710 #undef RS6000_BUILTIN_1
13711 #undef RS6000_BUILTIN_2
13712 #undef RS6000_BUILTIN_3
13713 #undef RS6000_BUILTIN_A
13714 #undef RS6000_BUILTIN_D
13715 #undef RS6000_BUILTIN_H
13716 #undef RS6000_BUILTIN_P
13717 #undef RS6000_BUILTIN_Q
13718 #undef RS6000_BUILTIN_X
13720 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13721 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13722 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13723 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13724 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13725 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13726 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13727 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13728 { MASK, ICODE, NAME, ENUM },
13730 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13731 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13733 /* AltiVec predicates. */
13735 static const struct builtin_description bdesc_altivec_preds
[] =
13737 #include "rs6000-builtin.def"
13740 /* PAIRED predicates. */
13741 #undef RS6000_BUILTIN_0
13742 #undef RS6000_BUILTIN_1
13743 #undef RS6000_BUILTIN_2
13744 #undef RS6000_BUILTIN_3
13745 #undef RS6000_BUILTIN_A
13746 #undef RS6000_BUILTIN_D
13747 #undef RS6000_BUILTIN_H
13748 #undef RS6000_BUILTIN_P
13749 #undef RS6000_BUILTIN_Q
13750 #undef RS6000_BUILTIN_X
13752 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13753 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13754 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13755 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13756 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13757 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13758 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13759 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13760 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13761 { MASK, ICODE, NAME, ENUM },
13763 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13765 static const struct builtin_description bdesc_paired_preds
[] =
13767 #include "rs6000-builtin.def"
13770 /* ABS* operations. */
13772 #undef RS6000_BUILTIN_0
13773 #undef RS6000_BUILTIN_1
13774 #undef RS6000_BUILTIN_2
13775 #undef RS6000_BUILTIN_3
13776 #undef RS6000_BUILTIN_A
13777 #undef RS6000_BUILTIN_D
13778 #undef RS6000_BUILTIN_H
13779 #undef RS6000_BUILTIN_P
13780 #undef RS6000_BUILTIN_Q
13781 #undef RS6000_BUILTIN_X
13783 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13784 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13785 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13786 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13787 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13788 { MASK, ICODE, NAME, ENUM },
13790 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13791 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13792 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13793 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13794 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13796 static const struct builtin_description bdesc_abs
[] =
13798 #include "rs6000-builtin.def"
13801 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13804 #undef RS6000_BUILTIN_0
13805 #undef RS6000_BUILTIN_1
13806 #undef RS6000_BUILTIN_2
13807 #undef RS6000_BUILTIN_3
13808 #undef RS6000_BUILTIN_A
13809 #undef RS6000_BUILTIN_D
13810 #undef RS6000_BUILTIN_H
13811 #undef RS6000_BUILTIN_P
13812 #undef RS6000_BUILTIN_Q
13813 #undef RS6000_BUILTIN_X
13815 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13816 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13817 { MASK, ICODE, NAME, ENUM },
13819 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13820 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13821 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13822 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13823 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13824 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13825 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13826 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13828 static const struct builtin_description bdesc_1arg
[] =
13830 #include "rs6000-builtin.def"
13833 /* Simple no-argument operations: result = __builtin_darn_32 () */
13835 #undef RS6000_BUILTIN_0
13836 #undef RS6000_BUILTIN_1
13837 #undef RS6000_BUILTIN_2
13838 #undef RS6000_BUILTIN_3
13839 #undef RS6000_BUILTIN_A
13840 #undef RS6000_BUILTIN_D
13841 #undef RS6000_BUILTIN_H
13842 #undef RS6000_BUILTIN_P
13843 #undef RS6000_BUILTIN_Q
13844 #undef RS6000_BUILTIN_X
13846 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13847 { MASK, ICODE, NAME, ENUM },
13849 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13850 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13851 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13852 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13853 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13854 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13855 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13856 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13857 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13859 static const struct builtin_description bdesc_0arg
[] =
13861 #include "rs6000-builtin.def"
13864 /* HTM builtins. */
13865 #undef RS6000_BUILTIN_0
13866 #undef RS6000_BUILTIN_1
13867 #undef RS6000_BUILTIN_2
13868 #undef RS6000_BUILTIN_3
13869 #undef RS6000_BUILTIN_A
13870 #undef RS6000_BUILTIN_D
13871 #undef RS6000_BUILTIN_H
13872 #undef RS6000_BUILTIN_P
13873 #undef RS6000_BUILTIN_Q
13874 #undef RS6000_BUILTIN_X
13876 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13877 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13878 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13879 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13880 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13881 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13882 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13883 { MASK, ICODE, NAME, ENUM },
13885 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13886 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13887 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13889 static const struct builtin_description bdesc_htm
[] =
13891 #include "rs6000-builtin.def"
13894 #undef RS6000_BUILTIN_0
13895 #undef RS6000_BUILTIN_1
13896 #undef RS6000_BUILTIN_2
13897 #undef RS6000_BUILTIN_3
13898 #undef RS6000_BUILTIN_A
13899 #undef RS6000_BUILTIN_D
13900 #undef RS6000_BUILTIN_H
13901 #undef RS6000_BUILTIN_P
13902 #undef RS6000_BUILTIN_Q
13904 /* Return true if a builtin function is overloaded. */
13906 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
13908 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
13912 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode
)
13914 return rs6000_builtin_info
[(int)fncode
].name
;
13917 /* Expand an expression EXP that calls a builtin without arguments. */
13919 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
13922 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13924 if (icode
== CODE_FOR_nothing
)
13925 /* Builtin not supported on this processor. */
13929 || GET_MODE (target
) != tmode
13930 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13931 target
= gen_reg_rtx (tmode
);
13933 pat
= GEN_FCN (icode
) (target
);
13943 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
13946 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13947 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13948 rtx op0
= expand_normal (arg0
);
13949 rtx op1
= expand_normal (arg1
);
13950 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13951 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13953 if (icode
== CODE_FOR_nothing
)
13954 /* Builtin not supported on this processor. */
13957 /* If we got invalid arguments bail out before generating bad rtl. */
13958 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13961 if (GET_CODE (op0
) != CONST_INT
13962 || INTVAL (op0
) > 255
13963 || INTVAL (op0
) < 0)
13965 error ("argument 1 must be an 8-bit field value");
13969 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13970 op0
= copy_to_mode_reg (mode0
, op0
);
13972 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13973 op1
= copy_to_mode_reg (mode1
, op1
);
13975 pat
= GEN_FCN (icode
) (op0
, op1
);
13984 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13987 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13988 rtx op0
= expand_normal (arg0
);
13989 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13990 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13992 if (icode
== CODE_FOR_nothing
)
13993 /* Builtin not supported on this processor. */
13996 /* If we got invalid arguments bail out before generating bad rtl. */
13997 if (arg0
== error_mark_node
)
14000 if (icode
== CODE_FOR_altivec_vspltisb
14001 || icode
== CODE_FOR_altivec_vspltish
14002 || icode
== CODE_FOR_altivec_vspltisw
)
14004 /* Only allow 5-bit *signed* literals. */
14005 if (GET_CODE (op0
) != CONST_INT
14006 || INTVAL (op0
) > 15
14007 || INTVAL (op0
) < -16)
14009 error ("argument 1 must be a 5-bit signed literal");
14010 return CONST0_RTX (tmode
);
14015 || GET_MODE (target
) != tmode
14016 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14017 target
= gen_reg_rtx (tmode
);
14019 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14020 op0
= copy_to_mode_reg (mode0
, op0
);
14022 pat
= GEN_FCN (icode
) (target
, op0
);
14031 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
14033 rtx pat
, scratch1
, scratch2
;
14034 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14035 rtx op0
= expand_normal (arg0
);
14036 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14037 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14039 /* If we have invalid arguments, bail out before generating bad rtl. */
14040 if (arg0
== error_mark_node
)
14044 || GET_MODE (target
) != tmode
14045 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14046 target
= gen_reg_rtx (tmode
);
14048 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14049 op0
= copy_to_mode_reg (mode0
, op0
);
14051 scratch1
= gen_reg_rtx (mode0
);
14052 scratch2
= gen_reg_rtx (mode0
);
14054 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
14063 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
14066 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14067 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14068 rtx op0
= expand_normal (arg0
);
14069 rtx op1
= expand_normal (arg1
);
14070 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14071 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14072 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14074 if (icode
== CODE_FOR_nothing
)
14075 /* Builtin not supported on this processor. */
14078 /* If we got invalid arguments bail out before generating bad rtl. */
14079 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14082 if (icode
== CODE_FOR_altivec_vcfux
14083 || icode
== CODE_FOR_altivec_vcfsx
14084 || icode
== CODE_FOR_altivec_vctsxs
14085 || icode
== CODE_FOR_altivec_vctuxs
14086 || icode
== CODE_FOR_altivec_vspltb
14087 || icode
== CODE_FOR_altivec_vsplth
14088 || icode
== CODE_FOR_altivec_vspltw
)
14090 /* Only allow 5-bit unsigned literals. */
14092 if (TREE_CODE (arg1
) != INTEGER_CST
14093 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
14095 error ("argument 2 must be a 5-bit unsigned literal");
14096 return CONST0_RTX (tmode
);
14099 else if (icode
== CODE_FOR_dfptstsfi_eq_dd
14100 || icode
== CODE_FOR_dfptstsfi_lt_dd
14101 || icode
== CODE_FOR_dfptstsfi_gt_dd
14102 || icode
== CODE_FOR_dfptstsfi_unordered_dd
14103 || icode
== CODE_FOR_dfptstsfi_eq_td
14104 || icode
== CODE_FOR_dfptstsfi_lt_td
14105 || icode
== CODE_FOR_dfptstsfi_gt_td
14106 || icode
== CODE_FOR_dfptstsfi_unordered_td
)
14108 /* Only allow 6-bit unsigned literals. */
14110 if (TREE_CODE (arg0
) != INTEGER_CST
14111 || !IN_RANGE (TREE_INT_CST_LOW (arg0
), 0, 63))
14113 error ("argument 1 must be a 6-bit unsigned literal");
14114 return CONST0_RTX (tmode
);
14117 else if (icode
== CODE_FOR_xststdcqp
14118 || icode
== CODE_FOR_xststdcdp
14119 || icode
== CODE_FOR_xststdcsp
14120 || icode
== CODE_FOR_xvtstdcdp
14121 || icode
== CODE_FOR_xvtstdcsp
)
14123 /* Only allow 7-bit unsigned literals. */
14125 if (TREE_CODE (arg1
) != INTEGER_CST
14126 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 127))
14128 error ("argument 2 must be a 7-bit unsigned literal");
14129 return CONST0_RTX (tmode
);
14134 || GET_MODE (target
) != tmode
14135 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14136 target
= gen_reg_rtx (tmode
);
14138 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14139 op0
= copy_to_mode_reg (mode0
, op0
);
14140 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14141 op1
= copy_to_mode_reg (mode1
, op1
);
14143 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
14152 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
14155 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
14156 tree arg0
= CALL_EXPR_ARG (exp
, 1);
14157 tree arg1
= CALL_EXPR_ARG (exp
, 2);
14158 rtx op0
= expand_normal (arg0
);
14159 rtx op1
= expand_normal (arg1
);
14160 machine_mode tmode
= SImode
;
14161 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14162 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14165 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
14167 error ("argument 1 of %qs must be a constant",
14168 "__builtin_altivec_predicate");
14172 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
14174 gcc_assert (mode0
== mode1
);
14176 /* If we have invalid arguments, bail out before generating bad rtl. */
14177 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14181 || GET_MODE (target
) != tmode
14182 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14183 target
= gen_reg_rtx (tmode
);
14185 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14186 op0
= copy_to_mode_reg (mode0
, op0
);
14187 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14188 op1
= copy_to_mode_reg (mode1
, op1
);
14190 /* Note that for many of the relevant operations (e.g. cmpne or
14191 cmpeq) with float or double operands, it makes more sense for the
14192 mode of the allocated scratch register to select a vector of
14193 integer. But the choice to copy the mode of operand 0 was made
14194 long ago and there are no plans to change it. */
14195 scratch
= gen_reg_rtx (mode0
);
14197 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14202 /* The vec_any* and vec_all* predicates use the same opcodes for two
14203 different operations, but the bits in CR6 will be different
14204 depending on what information we want. So we have to play tricks
14205 with CR6 to get the right bits out.
14207 If you think this is disgusting, look at the specs for the
14208 AltiVec predicates. */
14210 switch (cr6_form_int
)
14213 emit_insn (gen_cr6_test_for_zero (target
));
14216 emit_insn (gen_cr6_test_for_zero_reverse (target
));
14219 emit_insn (gen_cr6_test_for_lt (target
));
14222 emit_insn (gen_cr6_test_for_lt_reverse (target
));
14225 error ("argument 1 of %qs is out of range",
14226 "__builtin_altivec_predicate");
14234 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
14237 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14238 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14239 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14240 machine_mode mode0
= Pmode
;
14241 machine_mode mode1
= Pmode
;
14242 rtx op0
= expand_normal (arg0
);
14243 rtx op1
= expand_normal (arg1
);
14245 if (icode
== CODE_FOR_nothing
)
14246 /* Builtin not supported on this processor. */
14249 /* If we got invalid arguments bail out before generating bad rtl. */
14250 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14254 || GET_MODE (target
) != tmode
14255 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14256 target
= gen_reg_rtx (tmode
);
14258 op1
= copy_to_mode_reg (mode1
, op1
);
14260 if (op0
== const0_rtx
)
14262 addr
= gen_rtx_MEM (tmode
, op1
);
14266 op0
= copy_to_mode_reg (mode0
, op0
);
14267 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
14270 pat
= GEN_FCN (icode
) (target
, addr
);
14279 /* Return a constant vector for use as a little-endian permute control vector
14280 to reverse the order of elements of the given vector mode. */
14282 swap_selector_for_mode (machine_mode mode
)
14284 /* These are little endian vectors, so their elements are reversed
14285 from what you would normally expect for a permute control vector. */
14286 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14287 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14288 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14289 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14290 unsigned int *swaparray
, i
;
14307 swaparray
= swap16
;
14310 gcc_unreachable ();
14313 for (i
= 0; i
< 16; ++i
)
14314 perm
[i
] = GEN_INT (swaparray
[i
]);
14316 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
14319 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14320 with -maltivec=be specified. Issue the load followed by an element-
14321 reversing permute. */
14323 altivec_expand_lvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
14325 rtx tmp
= gen_reg_rtx (mode
);
14326 rtx load
= gen_rtx_SET (tmp
, op1
);
14327 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
14328 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
14329 rtx sel
= swap_selector_for_mode (mode
);
14330 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
14332 gcc_assert (REG_P (op0
));
14334 emit_insn (gen_rtx_SET (op0
, vperm
));
14337 /* Generate code for a "stvxl" built-in for a little endian target with
14338 -maltivec=be specified. Issue the store preceded by an element-reversing
14341 altivec_expand_stvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
14343 rtx tmp
= gen_reg_rtx (mode
);
14344 rtx store
= gen_rtx_SET (op0
, tmp
);
14345 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
14346 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
14347 rtx sel
= swap_selector_for_mode (mode
);
14350 gcc_assert (REG_P (op1
));
14351 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
14352 emit_insn (gen_rtx_SET (tmp
, vperm
));
14356 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14357 specified. Issue the store preceded by an element-reversing permute. */
14359 altivec_expand_stvex_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
14361 machine_mode inner_mode
= GET_MODE_INNER (mode
);
14362 rtx tmp
= gen_reg_rtx (mode
);
14363 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
14364 rtx sel
= swap_selector_for_mode (mode
);
14367 gcc_assert (REG_P (op1
));
14368 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
14369 emit_insn (gen_rtx_SET (tmp
, vperm
));
14370 emit_insn (gen_rtx_SET (op0
, stvx
));
14374 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
14377 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14378 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14379 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14380 machine_mode mode0
= Pmode
;
14381 machine_mode mode1
= Pmode
;
14382 rtx op0
= expand_normal (arg0
);
14383 rtx op1
= expand_normal (arg1
);
14385 if (icode
== CODE_FOR_nothing
)
14386 /* Builtin not supported on this processor. */
14389 /* If we got invalid arguments bail out before generating bad rtl. */
14390 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14394 || GET_MODE (target
) != tmode
14395 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14396 target
= gen_reg_rtx (tmode
);
14398 op1
= copy_to_mode_reg (mode1
, op1
);
14400 /* For LVX, express the RTL accurately by ANDing the address with -16.
14401 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14402 so the raw address is fine. */
14403 if (icode
== CODE_FOR_altivec_lvx_v2df_2op
14404 || icode
== CODE_FOR_altivec_lvx_v2di_2op
14405 || icode
== CODE_FOR_altivec_lvx_v4sf_2op
14406 || icode
== CODE_FOR_altivec_lvx_v4si_2op
14407 || icode
== CODE_FOR_altivec_lvx_v8hi_2op
14408 || icode
== CODE_FOR_altivec_lvx_v16qi_2op
)
14411 if (op0
== const0_rtx
)
14415 op0
= copy_to_mode_reg (mode0
, op0
);
14416 rawaddr
= gen_rtx_PLUS (Pmode
, op1
, op0
);
14418 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
14419 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, addr
);
14421 /* For -maltivec=be, emit the load and follow it up with a
14422 permute to swap the elements. */
14423 if (!BYTES_BIG_ENDIAN
&& VECTOR_ELT_ORDER_BIG
)
14425 rtx temp
= gen_reg_rtx (tmode
);
14426 emit_insn (gen_rtx_SET (temp
, addr
));
14428 rtx sel
= swap_selector_for_mode (tmode
);
14429 rtx vperm
= gen_rtx_UNSPEC (tmode
, gen_rtvec (3, temp
, temp
, sel
),
14431 emit_insn (gen_rtx_SET (target
, vperm
));
14434 emit_insn (gen_rtx_SET (target
, addr
));
14438 if (op0
== const0_rtx
)
14439 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
14442 op0
= copy_to_mode_reg (mode0
, op0
);
14443 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
,
14444 gen_rtx_PLUS (Pmode
, op1
, op0
));
14447 pat
= GEN_FCN (icode
) (target
, addr
);
14457 altivec_expand_xl_be_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
14460 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14461 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14462 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14463 machine_mode mode0
= Pmode
;
14464 machine_mode mode1
= Pmode
;
14465 rtx op0
= expand_normal (arg0
);
14466 rtx op1
= expand_normal (arg1
);
14468 if (icode
== CODE_FOR_nothing
)
14469 /* Builtin not supported on this processor. */
14472 /* If we got invalid arguments bail out before generating bad rtl. */
14473 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14477 || GET_MODE (target
) != tmode
14478 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14479 target
= gen_reg_rtx (tmode
);
14481 op1
= copy_to_mode_reg (mode1
, op1
);
14483 if (op0
== const0_rtx
)
14484 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
14487 op0
= copy_to_mode_reg (mode0
, op0
);
14488 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
,
14489 gen_rtx_PLUS (Pmode
, op1
, op0
));
14492 pat
= GEN_FCN (icode
) (target
, addr
);
14497 /* Reverse element order of elements if in LE mode */
14498 if (!VECTOR_ELT_ORDER_BIG
)
14500 rtx sel
= swap_selector_for_mode (tmode
);
14501 rtx vperm
= gen_rtx_UNSPEC (tmode
, gen_rtvec (3, target
, target
, sel
),
14503 emit_insn (gen_rtx_SET (target
, vperm
));
14509 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
14511 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14512 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14513 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14514 rtx op0
= expand_normal (arg0
);
14515 rtx op1
= expand_normal (arg1
);
14516 rtx op2
= expand_normal (arg2
);
14518 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14519 machine_mode mode1
= Pmode
;
14520 machine_mode mode2
= Pmode
;
14522 /* Invalid arguments. Bail before doing anything stoopid! */
14523 if (arg0
== error_mark_node
14524 || arg1
== error_mark_node
14525 || arg2
== error_mark_node
)
14528 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
14529 op0
= copy_to_mode_reg (tmode
, op0
);
14531 op2
= copy_to_mode_reg (mode2
, op2
);
14533 if (op1
== const0_rtx
)
14535 addr
= gen_rtx_MEM (tmode
, op2
);
14539 op1
= copy_to_mode_reg (mode1
, op1
);
14540 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
14543 pat
= GEN_FCN (icode
) (addr
, op0
);
14550 altivec_expand_stxvl_builtin (enum insn_code icode
, tree exp
)
14553 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14554 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14555 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14556 rtx op0
= expand_normal (arg0
);
14557 rtx op1
= expand_normal (arg1
);
14558 rtx op2
= expand_normal (arg2
);
14559 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
14560 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
14561 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
14563 if (icode
== CODE_FOR_nothing
)
14564 /* Builtin not supported on this processor. */
14567 /* If we got invalid arguments bail out before generating bad rtl. */
14568 if (arg0
== error_mark_node
14569 || arg1
== error_mark_node
14570 || arg2
== error_mark_node
)
14573 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14574 op0
= copy_to_mode_reg (mode0
, op0
);
14575 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14576 op1
= copy_to_mode_reg (mode1
, op1
);
14577 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
14578 op2
= copy_to_mode_reg (mode2
, op2
);
14580 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
14588 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
14590 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14591 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14592 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14593 rtx op0
= expand_normal (arg0
);
14594 rtx op1
= expand_normal (arg1
);
14595 rtx op2
= expand_normal (arg2
);
14596 rtx pat
, addr
, rawaddr
;
14597 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14598 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
14599 machine_mode mode1
= Pmode
;
14600 machine_mode mode2
= Pmode
;
14602 /* Invalid arguments. Bail before doing anything stoopid! */
14603 if (arg0
== error_mark_node
14604 || arg1
== error_mark_node
14605 || arg2
== error_mark_node
)
14608 op2
= copy_to_mode_reg (mode2
, op2
);
14610 /* For STVX, express the RTL accurately by ANDing the address with -16.
14611 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14612 so the raw address is fine. */
14613 if (icode
== CODE_FOR_altivec_stvx_v2df_2op
14614 || icode
== CODE_FOR_altivec_stvx_v2di_2op
14615 || icode
== CODE_FOR_altivec_stvx_v4sf_2op
14616 || icode
== CODE_FOR_altivec_stvx_v4si_2op
14617 || icode
== CODE_FOR_altivec_stvx_v8hi_2op
14618 || icode
== CODE_FOR_altivec_stvx_v16qi_2op
)
14620 if (op1
== const0_rtx
)
14624 op1
= copy_to_mode_reg (mode1
, op1
);
14625 rawaddr
= gen_rtx_PLUS (Pmode
, op2
, op1
);
14628 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
14629 addr
= gen_rtx_MEM (tmode
, addr
);
14631 op0
= copy_to_mode_reg (tmode
, op0
);
14633 /* For -maltivec=be, emit a permute to swap the elements, followed
14635 if (!BYTES_BIG_ENDIAN
&& VECTOR_ELT_ORDER_BIG
)
14637 rtx temp
= gen_reg_rtx (tmode
);
14638 rtx sel
= swap_selector_for_mode (tmode
);
14639 rtx vperm
= gen_rtx_UNSPEC (tmode
, gen_rtvec (3, op0
, op0
, sel
),
14641 emit_insn (gen_rtx_SET (temp
, vperm
));
14642 emit_insn (gen_rtx_SET (addr
, temp
));
14645 emit_insn (gen_rtx_SET (addr
, op0
));
14649 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
14650 op0
= copy_to_mode_reg (smode
, op0
);
14652 if (op1
== const0_rtx
)
14653 addr
= gen_rtx_MEM (tmode
, op2
);
14656 op1
= copy_to_mode_reg (mode1
, op1
);
14657 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op2
, op1
));
14660 pat
= GEN_FCN (icode
) (addr
, op0
);
14668 /* Return the appropriate SPR number associated with the given builtin. */
14669 static inline HOST_WIDE_INT
14670 htm_spr_num (enum rs6000_builtins code
)
14672 if (code
== HTM_BUILTIN_GET_TFHAR
14673 || code
== HTM_BUILTIN_SET_TFHAR
)
14675 else if (code
== HTM_BUILTIN_GET_TFIAR
14676 || code
== HTM_BUILTIN_SET_TFIAR
)
14678 else if (code
== HTM_BUILTIN_GET_TEXASR
14679 || code
== HTM_BUILTIN_SET_TEXASR
)
14681 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
14682 || code
== HTM_BUILTIN_SET_TEXASRU
);
14683 return TEXASRU_SPR
;
14686 /* Return the appropriate SPR regno associated with the given builtin. */
14687 static inline HOST_WIDE_INT
14688 htm_spr_regno (enum rs6000_builtins code
)
14690 if (code
== HTM_BUILTIN_GET_TFHAR
14691 || code
== HTM_BUILTIN_SET_TFHAR
)
14692 return TFHAR_REGNO
;
14693 else if (code
== HTM_BUILTIN_GET_TFIAR
14694 || code
== HTM_BUILTIN_SET_TFIAR
)
14695 return TFIAR_REGNO
;
14696 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
14697 || code
== HTM_BUILTIN_SET_TEXASR
14698 || code
== HTM_BUILTIN_GET_TEXASRU
14699 || code
== HTM_BUILTIN_SET_TEXASRU
);
14700 return TEXASR_REGNO
;
14703 /* Return the correct ICODE value depending on whether we are
14704 setting or reading the HTM SPRs. */
14705 static inline enum insn_code
14706 rs6000_htm_spr_icode (bool nonvoid
)
14709 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
14711 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
14714 /* Expand the HTM builtin in EXP and store the result in TARGET.
14715 Store true in *EXPANDEDP if we found a builtin to expand. */
14717 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
14719 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14720 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
14721 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14722 const struct builtin_description
*d
;
14727 if (!TARGET_POWERPC64
14728 && (fcode
== HTM_BUILTIN_TABORTDC
14729 || fcode
== HTM_BUILTIN_TABORTDCI
))
14731 size_t uns_fcode
= (size_t)fcode
;
14732 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
14733 error ("builtin %qs is only valid in 64-bit mode", name
);
14737 /* Expand the HTM builtins. */
14739 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14740 if (d
->code
== fcode
)
14742 rtx op
[MAX_HTM_OPERANDS
], pat
;
14745 call_expr_arg_iterator iter
;
14746 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
14747 enum insn_code icode
= d
->icode
;
14748 const struct insn_operand_data
*insn_op
;
14749 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
14753 icode
= rs6000_htm_spr_icode (nonvoid
);
14754 insn_op
= &insn_data
[icode
].operand
[0];
14758 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: SImode
;
14760 || GET_MODE (target
) != tmode
14761 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
14762 target
= gen_reg_rtx (tmode
);
14764 op
[nopnds
++] = target
;
14767 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
14769 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
14772 insn_op
= &insn_data
[icode
].operand
[nopnds
];
14774 op
[nopnds
] = expand_normal (arg
);
14776 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
14778 if (!strcmp (insn_op
->constraint
, "n"))
14780 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
14781 if (!CONST_INT_P (op
[nopnds
]))
14782 error ("argument %d must be an unsigned literal", arg_num
);
14784 error ("argument %d is an unsigned literal that is "
14785 "out of range", arg_num
);
14788 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
14794 /* Handle the builtins for extended mnemonics. These accept
14795 no arguments, but map to builtins that take arguments. */
14798 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
14799 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
14800 op
[nopnds
++] = GEN_INT (1);
14802 attr
|= RS6000_BTC_UNARY
;
14804 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
14805 op
[nopnds
++] = GEN_INT (0);
14807 attr
|= RS6000_BTC_UNARY
;
14813 /* If this builtin accesses SPRs, then pass in the appropriate
14814 SPR number and SPR regno as the last two operands. */
14817 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
14818 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
14819 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
14821 /* If this builtin accesses a CR, then pass in a scratch
14822 CR as the last operand. */
14823 else if (attr
& RS6000_BTC_CR
)
14824 { cr
= gen_reg_rtx (CCmode
);
14830 int expected_nopnds
= 0;
14831 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
14832 expected_nopnds
= 1;
14833 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
14834 expected_nopnds
= 2;
14835 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
14836 expected_nopnds
= 3;
14837 if (!(attr
& RS6000_BTC_VOID
))
14838 expected_nopnds
+= 1;
14840 expected_nopnds
+= 2;
14842 gcc_assert (nopnds
== expected_nopnds
14843 && nopnds
<= MAX_HTM_OPERANDS
);
14849 pat
= GEN_FCN (icode
) (op
[0]);
14852 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
14855 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
14858 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
14861 gcc_unreachable ();
14867 if (attr
& RS6000_BTC_CR
)
14869 if (fcode
== HTM_BUILTIN_TBEGIN
)
14871 /* Emit code to set TARGET to true or false depending on
14872 whether the tbegin. instruction successfully or failed
14873 to start a transaction. We do this by placing the 1's
14874 complement of CR's EQ bit into TARGET. */
14875 rtx scratch
= gen_reg_rtx (SImode
);
14876 emit_insn (gen_rtx_SET (scratch
,
14877 gen_rtx_EQ (SImode
, cr
,
14879 emit_insn (gen_rtx_SET (target
,
14880 gen_rtx_XOR (SImode
, scratch
,
14885 /* Emit code to copy the 4-bit condition register field
14886 CR into the least significant end of register TARGET. */
14887 rtx scratch1
= gen_reg_rtx (SImode
);
14888 rtx scratch2
= gen_reg_rtx (SImode
);
14889 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
14890 emit_insn (gen_movcc (subreg
, cr
));
14891 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
14892 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
14901 *expandedp
= false;
14905 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14908 cpu_expand_builtin (enum rs6000_builtins fcode
, tree exp ATTRIBUTE_UNUSED
,
14911 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14912 if (fcode
== RS6000_BUILTIN_CPU_INIT
)
14915 if (target
== 0 || GET_MODE (target
) != SImode
)
14916 target
= gen_reg_rtx (SImode
);
14918 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14919 tree arg
= TREE_OPERAND (CALL_EXPR_ARG (exp
, 0), 0);
14920 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14921 to a STRING_CST. */
14922 if (TREE_CODE (arg
) == ARRAY_REF
14923 && TREE_CODE (TREE_OPERAND (arg
, 0)) == STRING_CST
14924 && TREE_CODE (TREE_OPERAND (arg
, 1)) == INTEGER_CST
14925 && compare_tree_int (TREE_OPERAND (arg
, 1), 0) == 0)
14926 arg
= TREE_OPERAND (arg
, 0);
14928 if (TREE_CODE (arg
) != STRING_CST
)
14930 error ("builtin %qs only accepts a string argument",
14931 rs6000_builtin_info
[(size_t) fcode
].name
);
14935 if (fcode
== RS6000_BUILTIN_CPU_IS
)
14937 const char *cpu
= TREE_STRING_POINTER (arg
);
14938 rtx cpuid
= NULL_RTX
;
14939 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_is_info
); i
++)
14940 if (strcmp (cpu
, cpu_is_info
[i
].cpu
) == 0)
14942 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14943 cpuid
= GEN_INT (cpu_is_info
[i
].cpuid
+ _DL_FIRST_PLATFORM
);
14946 if (cpuid
== NULL_RTX
)
14948 /* Invalid CPU argument. */
14949 error ("cpu %qs is an invalid argument to builtin %qs",
14950 cpu
, rs6000_builtin_info
[(size_t) fcode
].name
);
14954 rtx platform
= gen_reg_rtx (SImode
);
14955 rtx tcbmem
= gen_const_mem (SImode
,
14956 gen_rtx_PLUS (Pmode
,
14957 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14958 GEN_INT (TCB_PLATFORM_OFFSET
)));
14959 emit_move_insn (platform
, tcbmem
);
14960 emit_insn (gen_eqsi3 (target
, platform
, cpuid
));
14962 else if (fcode
== RS6000_BUILTIN_CPU_SUPPORTS
)
14964 const char *hwcap
= TREE_STRING_POINTER (arg
);
14965 rtx mask
= NULL_RTX
;
14967 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_supports_info
); i
++)
14968 if (strcmp (hwcap
, cpu_supports_info
[i
].hwcap
) == 0)
14970 mask
= GEN_INT (cpu_supports_info
[i
].mask
);
14971 hwcap_offset
= TCB_HWCAP_OFFSET (cpu_supports_info
[i
].id
);
14974 if (mask
== NULL_RTX
)
14976 /* Invalid HWCAP argument. */
14977 error ("%s %qs is an invalid argument to builtin %qs",
14978 "hwcap", hwcap
, rs6000_builtin_info
[(size_t) fcode
].name
);
14982 rtx tcb_hwcap
= gen_reg_rtx (SImode
);
14983 rtx tcbmem
= gen_const_mem (SImode
,
14984 gen_rtx_PLUS (Pmode
,
14985 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14986 GEN_INT (hwcap_offset
)));
14987 emit_move_insn (tcb_hwcap
, tcbmem
);
14988 rtx scratch1
= gen_reg_rtx (SImode
);
14989 emit_insn (gen_rtx_SET (scratch1
, gen_rtx_AND (SImode
, tcb_hwcap
, mask
)));
14990 rtx scratch2
= gen_reg_rtx (SImode
);
14991 emit_insn (gen_eqsi3 (scratch2
, scratch1
, const0_rtx
));
14992 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (SImode
, scratch2
, const1_rtx
)));
14995 gcc_unreachable ();
14997 /* Record that we have expanded a CPU builtin, so that we can later
14998 emit a reference to the special symbol exported by LIBC to ensure we
14999 do not link against an old LIBC that doesn't support this feature. */
15000 cpu_builtin_p
= true;
15003 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
15004 "capability bits", rs6000_builtin_info
[(size_t) fcode
].name
);
15006 /* For old LIBCs, always return FALSE. */
15007 emit_move_insn (target
, GEN_INT (0));
15008 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
15014 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
15017 tree arg0
= CALL_EXPR_ARG (exp
, 0);
15018 tree arg1
= CALL_EXPR_ARG (exp
, 1);
15019 tree arg2
= CALL_EXPR_ARG (exp
, 2);
15020 rtx op0
= expand_normal (arg0
);
15021 rtx op1
= expand_normal (arg1
);
15022 rtx op2
= expand_normal (arg2
);
15023 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
15024 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
15025 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
15026 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
15028 if (icode
== CODE_FOR_nothing
)
15029 /* Builtin not supported on this processor. */
15032 /* If we got invalid arguments bail out before generating bad rtl. */
15033 if (arg0
== error_mark_node
15034 || arg1
== error_mark_node
15035 || arg2
== error_mark_node
)
15038 /* Check and prepare argument depending on the instruction code.
15040 Note that a switch statement instead of the sequence of tests
15041 would be incorrect as many of the CODE_FOR values could be
15042 CODE_FOR_nothing and that would yield multiple alternatives
15043 with identical values. We'd never reach here at runtime in
15045 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
15046 || icode
== CODE_FOR_altivec_vsldoi_v2df
15047 || icode
== CODE_FOR_altivec_vsldoi_v4si
15048 || icode
== CODE_FOR_altivec_vsldoi_v8hi
15049 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
15051 /* Only allow 4-bit unsigned literals. */
15053 if (TREE_CODE (arg2
) != INTEGER_CST
15054 || TREE_INT_CST_LOW (arg2
) & ~0xf)
15056 error ("argument 3 must be a 4-bit unsigned literal");
15057 return CONST0_RTX (tmode
);
15060 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
15061 || icode
== CODE_FOR_vsx_xxpermdi_v2di
15062 || icode
== CODE_FOR_vsx_xxpermdi_v2df_be
15063 || icode
== CODE_FOR_vsx_xxpermdi_v2di_be
15064 || icode
== CODE_FOR_vsx_xxpermdi_v1ti
15065 || icode
== CODE_FOR_vsx_xxpermdi_v4sf
15066 || icode
== CODE_FOR_vsx_xxpermdi_v4si
15067 || icode
== CODE_FOR_vsx_xxpermdi_v8hi
15068 || icode
== CODE_FOR_vsx_xxpermdi_v16qi
15069 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
15070 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
15071 || icode
== CODE_FOR_vsx_xxsldwi_v4si
15072 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
15073 || icode
== CODE_FOR_vsx_xxsldwi_v2di
15074 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
15076 /* Only allow 2-bit unsigned literals. */
15078 if (TREE_CODE (arg2
) != INTEGER_CST
15079 || TREE_INT_CST_LOW (arg2
) & ~0x3)
15081 error ("argument 3 must be a 2-bit unsigned literal");
15082 return CONST0_RTX (tmode
);
15085 else if (icode
== CODE_FOR_vsx_set_v2df
15086 || icode
== CODE_FOR_vsx_set_v2di
15087 || icode
== CODE_FOR_bcdadd
15088 || icode
== CODE_FOR_bcdadd_lt
15089 || icode
== CODE_FOR_bcdadd_eq
15090 || icode
== CODE_FOR_bcdadd_gt
15091 || icode
== CODE_FOR_bcdsub
15092 || icode
== CODE_FOR_bcdsub_lt
15093 || icode
== CODE_FOR_bcdsub_eq
15094 || icode
== CODE_FOR_bcdsub_gt
)
15096 /* Only allow 1-bit unsigned literals. */
15098 if (TREE_CODE (arg2
) != INTEGER_CST
15099 || TREE_INT_CST_LOW (arg2
) & ~0x1)
15101 error ("argument 3 must be a 1-bit unsigned literal");
15102 return CONST0_RTX (tmode
);
15105 else if (icode
== CODE_FOR_dfp_ddedpd_dd
15106 || icode
== CODE_FOR_dfp_ddedpd_td
)
15108 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15110 if (TREE_CODE (arg0
) != INTEGER_CST
15111 || TREE_INT_CST_LOW (arg2
) & ~0x3)
15113 error ("argument 1 must be 0 or 2");
15114 return CONST0_RTX (tmode
);
15117 else if (icode
== CODE_FOR_dfp_denbcd_dd
15118 || icode
== CODE_FOR_dfp_denbcd_td
)
15120 /* Only allow 1-bit unsigned literals. */
15122 if (TREE_CODE (arg0
) != INTEGER_CST
15123 || TREE_INT_CST_LOW (arg0
) & ~0x1)
15125 error ("argument 1 must be a 1-bit unsigned literal");
15126 return CONST0_RTX (tmode
);
15129 else if (icode
== CODE_FOR_dfp_dscli_dd
15130 || icode
== CODE_FOR_dfp_dscli_td
15131 || icode
== CODE_FOR_dfp_dscri_dd
15132 || icode
== CODE_FOR_dfp_dscri_td
)
15134 /* Only allow 6-bit unsigned literals. */
15136 if (TREE_CODE (arg1
) != INTEGER_CST
15137 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
15139 error ("argument 2 must be a 6-bit unsigned literal");
15140 return CONST0_RTX (tmode
);
15143 else if (icode
== CODE_FOR_crypto_vshasigmaw
15144 || icode
== CODE_FOR_crypto_vshasigmad
)
15146 /* Check whether the 2nd and 3rd arguments are integer constants and in
15147 range and prepare arguments. */
15149 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
15151 error ("argument 2 must be 0 or 1");
15152 return CONST0_RTX (tmode
);
15156 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg2
, 16))
15158 error ("argument 3 must be in the range 0..15");
15159 return CONST0_RTX (tmode
);
15164 || GET_MODE (target
) != tmode
15165 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
15166 target
= gen_reg_rtx (tmode
);
15168 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
15169 op0
= copy_to_mode_reg (mode0
, op0
);
15170 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
15171 op1
= copy_to_mode_reg (mode1
, op1
);
15172 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
15173 op2
= copy_to_mode_reg (mode2
, op2
);
15175 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
15176 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
15178 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
15186 /* Expand the lvx builtins. */
15188 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
15190 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15191 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
15193 machine_mode tmode
, mode0
;
15195 enum insn_code icode
;
15199 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
15200 icode
= CODE_FOR_vector_altivec_load_v16qi
;
15202 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
15203 icode
= CODE_FOR_vector_altivec_load_v8hi
;
15205 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
15206 icode
= CODE_FOR_vector_altivec_load_v4si
;
15208 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
15209 icode
= CODE_FOR_vector_altivec_load_v4sf
;
15211 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
15212 icode
= CODE_FOR_vector_altivec_load_v2df
;
15214 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
15215 icode
= CODE_FOR_vector_altivec_load_v2di
;
15217 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
15218 icode
= CODE_FOR_vector_altivec_load_v1ti
;
15221 *expandedp
= false;
15227 arg0
= CALL_EXPR_ARG (exp
, 0);
15228 op0
= expand_normal (arg0
);
15229 tmode
= insn_data
[icode
].operand
[0].mode
;
15230 mode0
= insn_data
[icode
].operand
[1].mode
;
15233 || GET_MODE (target
) != tmode
15234 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
15235 target
= gen_reg_rtx (tmode
);
15237 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
15238 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
15240 pat
= GEN_FCN (icode
) (target
, op0
);
15247 /* Expand the stvx builtins. */
15249 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
15252 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15253 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
15255 machine_mode mode0
, mode1
;
15257 enum insn_code icode
;
15261 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
15262 icode
= CODE_FOR_vector_altivec_store_v16qi
;
15264 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
15265 icode
= CODE_FOR_vector_altivec_store_v8hi
;
15267 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
15268 icode
= CODE_FOR_vector_altivec_store_v4si
;
15270 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
15271 icode
= CODE_FOR_vector_altivec_store_v4sf
;
15273 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
15274 icode
= CODE_FOR_vector_altivec_store_v2df
;
15276 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
15277 icode
= CODE_FOR_vector_altivec_store_v2di
;
15279 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
15280 icode
= CODE_FOR_vector_altivec_store_v1ti
;
15283 *expandedp
= false;
15287 arg0
= CALL_EXPR_ARG (exp
, 0);
15288 arg1
= CALL_EXPR_ARG (exp
, 1);
15289 op0
= expand_normal (arg0
);
15290 op1
= expand_normal (arg1
);
15291 mode0
= insn_data
[icode
].operand
[0].mode
;
15292 mode1
= insn_data
[icode
].operand
[1].mode
;
15294 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
15295 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
15296 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
15297 op1
= copy_to_mode_reg (mode1
, op1
);
15299 pat
= GEN_FCN (icode
) (op0
, op1
);
15307 /* Expand the dst builtins. */
15309 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
15312 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15313 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15314 tree arg0
, arg1
, arg2
;
15315 machine_mode mode0
, mode1
;
15316 rtx pat
, op0
, op1
, op2
;
15317 const struct builtin_description
*d
;
15320 *expandedp
= false;
15322 /* Handle DST variants. */
15324 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
15325 if (d
->code
== fcode
)
15327 arg0
= CALL_EXPR_ARG (exp
, 0);
15328 arg1
= CALL_EXPR_ARG (exp
, 1);
15329 arg2
= CALL_EXPR_ARG (exp
, 2);
15330 op0
= expand_normal (arg0
);
15331 op1
= expand_normal (arg1
);
15332 op2
= expand_normal (arg2
);
15333 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
15334 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
15336 /* Invalid arguments, bail out before generating bad rtl. */
15337 if (arg0
== error_mark_node
15338 || arg1
== error_mark_node
15339 || arg2
== error_mark_node
)
15344 if (TREE_CODE (arg2
) != INTEGER_CST
15345 || TREE_INT_CST_LOW (arg2
) & ~0x3)
15347 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
15351 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
15352 op0
= copy_to_mode_reg (Pmode
, op0
);
15353 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
15354 op1
= copy_to_mode_reg (mode1
, op1
);
15356 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
15366 /* Expand vec_init builtin. */
15368 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
15370 machine_mode tmode
= TYPE_MODE (type
);
15371 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
15372 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
15374 gcc_assert (VECTOR_MODE_P (tmode
));
15375 gcc_assert (n_elt
== call_expr_nargs (exp
));
15377 if (!target
|| !register_operand (target
, tmode
))
15378 target
= gen_reg_rtx (tmode
);
15380 /* If we have a vector compromised of a single element, such as V1TImode, do
15381 the initialization directly. */
15382 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
15384 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
15385 emit_move_insn (target
, gen_lowpart (tmode
, x
));
15389 rtvec v
= rtvec_alloc (n_elt
);
15391 for (i
= 0; i
< n_elt
; ++i
)
15393 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
15394 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
15397 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
15403 /* Return the integer constant in ARG. Constrain it to be in the range
15404 of the subparts of VEC_TYPE; issue an error if not. */
15407 get_element_number (tree vec_type
, tree arg
)
15409 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
15411 if (!tree_fits_uhwi_p (arg
)
15412 || (elt
= tree_to_uhwi (arg
), elt
> max
))
15414 error ("selector must be an integer constant in the range 0..%wi", max
);
15421 /* Expand vec_set builtin. */
15423 altivec_expand_vec_set_builtin (tree exp
)
15425 machine_mode tmode
, mode1
;
15426 tree arg0
, arg1
, arg2
;
15430 arg0
= CALL_EXPR_ARG (exp
, 0);
15431 arg1
= CALL_EXPR_ARG (exp
, 1);
15432 arg2
= CALL_EXPR_ARG (exp
, 2);
15434 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
15435 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
15436 gcc_assert (VECTOR_MODE_P (tmode
));
15438 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
15439 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
15440 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
15442 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
15443 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
15445 op0
= force_reg (tmode
, op0
);
15446 op1
= force_reg (mode1
, op1
);
15448 rs6000_expand_vector_set (op0
, op1
, elt
);
15453 /* Expand vec_ext builtin. */
15455 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
15457 machine_mode tmode
, mode0
;
15462 arg0
= CALL_EXPR_ARG (exp
, 0);
15463 arg1
= CALL_EXPR_ARG (exp
, 1);
15465 op0
= expand_normal (arg0
);
15466 op1
= expand_normal (arg1
);
15468 /* Call get_element_number to validate arg1 if it is a constant. */
15469 if (TREE_CODE (arg1
) == INTEGER_CST
)
15470 (void) get_element_number (TREE_TYPE (arg0
), arg1
);
15472 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
15473 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
15474 gcc_assert (VECTOR_MODE_P (mode0
));
15476 op0
= force_reg (mode0
, op0
);
15478 if (optimize
|| !target
|| !register_operand (target
, tmode
))
15479 target
= gen_reg_rtx (tmode
);
15481 rs6000_expand_vector_extract (target
, op0
, op1
);
15486 /* Expand the builtin in EXP and store the result in TARGET. Store
15487 true in *EXPANDEDP if we found a builtin to expand. */
15489 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
15491 const struct builtin_description
*d
;
15493 enum insn_code icode
;
15494 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15495 tree arg0
, arg1
, arg2
;
15497 machine_mode tmode
, mode0
;
15498 enum rs6000_builtins fcode
15499 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15501 if (rs6000_overloaded_builtin_p (fcode
))
15504 error ("unresolved overload for Altivec builtin %qF", fndecl
);
15506 /* Given it is invalid, just generate a normal call. */
15507 return expand_call (exp
, target
, false);
15510 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
15514 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
15518 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
15526 case ALTIVEC_BUILTIN_STVX_V2DF
:
15527 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op
, exp
);
15528 case ALTIVEC_BUILTIN_STVX_V2DI
:
15529 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op
, exp
);
15530 case ALTIVEC_BUILTIN_STVX_V4SF
:
15531 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op
, exp
);
15532 case ALTIVEC_BUILTIN_STVX
:
15533 case ALTIVEC_BUILTIN_STVX_V4SI
:
15534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op
, exp
);
15535 case ALTIVEC_BUILTIN_STVX_V8HI
:
15536 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op
, exp
);
15537 case ALTIVEC_BUILTIN_STVX_V16QI
:
15538 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op
, exp
);
15539 case ALTIVEC_BUILTIN_STVEBX
:
15540 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
15541 case ALTIVEC_BUILTIN_STVEHX
:
15542 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
15543 case ALTIVEC_BUILTIN_STVEWX
:
15544 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
15545 case ALTIVEC_BUILTIN_STVXL_V2DF
:
15546 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
15547 case ALTIVEC_BUILTIN_STVXL_V2DI
:
15548 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
15549 case ALTIVEC_BUILTIN_STVXL_V4SF
:
15550 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
15551 case ALTIVEC_BUILTIN_STVXL
:
15552 case ALTIVEC_BUILTIN_STVXL_V4SI
:
15553 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
15554 case ALTIVEC_BUILTIN_STVXL_V8HI
:
15555 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
15556 case ALTIVEC_BUILTIN_STVXL_V16QI
:
15557 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
15559 case ALTIVEC_BUILTIN_STVLX
:
15560 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
15561 case ALTIVEC_BUILTIN_STVLXL
:
15562 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
15563 case ALTIVEC_BUILTIN_STVRX
:
15564 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
15565 case ALTIVEC_BUILTIN_STVRXL
:
15566 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
15568 case P9V_BUILTIN_STXVL
:
15569 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl
, exp
);
15571 case VSX_BUILTIN_STXVD2X_V1TI
:
15572 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
15573 case VSX_BUILTIN_STXVD2X_V2DF
:
15574 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
15575 case VSX_BUILTIN_STXVD2X_V2DI
:
15576 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
15577 case VSX_BUILTIN_STXVW4X_V4SF
:
15578 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
15579 case VSX_BUILTIN_STXVW4X_V4SI
:
15580 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
15581 case VSX_BUILTIN_STXVW4X_V8HI
:
15582 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
15583 case VSX_BUILTIN_STXVW4X_V16QI
:
15584 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
15586 /* For the following on big endian, it's ok to use any appropriate
15587 unaligned-supporting store, so use a generic expander. For
15588 little-endian, the exact element-reversing instruction must
15590 case VSX_BUILTIN_ST_ELEMREV_V2DF
:
15592 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2df
15593 : CODE_FOR_vsx_st_elemrev_v2df
);
15594 return altivec_expand_stv_builtin (code
, exp
);
15596 case VSX_BUILTIN_ST_ELEMREV_V2DI
:
15598 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2di
15599 : CODE_FOR_vsx_st_elemrev_v2di
);
15600 return altivec_expand_stv_builtin (code
, exp
);
15602 case VSX_BUILTIN_ST_ELEMREV_V4SF
:
15604 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4sf
15605 : CODE_FOR_vsx_st_elemrev_v4sf
);
15606 return altivec_expand_stv_builtin (code
, exp
);
15608 case VSX_BUILTIN_ST_ELEMREV_V4SI
:
15610 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4si
15611 : CODE_FOR_vsx_st_elemrev_v4si
);
15612 return altivec_expand_stv_builtin (code
, exp
);
15614 case VSX_BUILTIN_ST_ELEMREV_V8HI
:
15616 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v8hi
15617 : CODE_FOR_vsx_st_elemrev_v8hi
);
15618 return altivec_expand_stv_builtin (code
, exp
);
15620 case VSX_BUILTIN_ST_ELEMREV_V16QI
:
15622 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v16qi
15623 : CODE_FOR_vsx_st_elemrev_v16qi
);
15624 return altivec_expand_stv_builtin (code
, exp
);
15627 case ALTIVEC_BUILTIN_MFVSCR
:
15628 icode
= CODE_FOR_altivec_mfvscr
;
15629 tmode
= insn_data
[icode
].operand
[0].mode
;
15632 || GET_MODE (target
) != tmode
15633 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
15634 target
= gen_reg_rtx (tmode
);
15636 pat
= GEN_FCN (icode
) (target
);
15642 case ALTIVEC_BUILTIN_MTVSCR
:
15643 icode
= CODE_FOR_altivec_mtvscr
;
15644 arg0
= CALL_EXPR_ARG (exp
, 0);
15645 op0
= expand_normal (arg0
);
15646 mode0
= insn_data
[icode
].operand
[0].mode
;
15648 /* If we got invalid arguments bail out before generating bad rtl. */
15649 if (arg0
== error_mark_node
)
15652 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
15653 op0
= copy_to_mode_reg (mode0
, op0
);
15655 pat
= GEN_FCN (icode
) (op0
);
15660 case ALTIVEC_BUILTIN_DSSALL
:
15661 emit_insn (gen_altivec_dssall ());
15664 case ALTIVEC_BUILTIN_DSS
:
15665 icode
= CODE_FOR_altivec_dss
;
15666 arg0
= CALL_EXPR_ARG (exp
, 0);
15668 op0
= expand_normal (arg0
);
15669 mode0
= insn_data
[icode
].operand
[0].mode
;
15671 /* If we got invalid arguments bail out before generating bad rtl. */
15672 if (arg0
== error_mark_node
)
15675 if (TREE_CODE (arg0
) != INTEGER_CST
15676 || TREE_INT_CST_LOW (arg0
) & ~0x3)
15678 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15682 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
15683 op0
= copy_to_mode_reg (mode0
, op0
);
15685 emit_insn (gen_altivec_dss (op0
));
15688 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
15689 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
15690 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
15691 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
15692 case VSX_BUILTIN_VEC_INIT_V2DF
:
15693 case VSX_BUILTIN_VEC_INIT_V2DI
:
15694 case VSX_BUILTIN_VEC_INIT_V1TI
:
15695 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
15697 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
15698 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
15699 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
15700 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
15701 case VSX_BUILTIN_VEC_SET_V2DF
:
15702 case VSX_BUILTIN_VEC_SET_V2DI
:
15703 case VSX_BUILTIN_VEC_SET_V1TI
:
15704 return altivec_expand_vec_set_builtin (exp
);
15706 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
15707 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
15708 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
15709 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
15710 case VSX_BUILTIN_VEC_EXT_V2DF
:
15711 case VSX_BUILTIN_VEC_EXT_V2DI
:
15712 case VSX_BUILTIN_VEC_EXT_V1TI
:
15713 return altivec_expand_vec_ext_builtin (exp
, target
);
15715 case P9V_BUILTIN_VEXTRACT4B
:
15716 case P9V_BUILTIN_VEC_VEXTRACT4B
:
15717 arg1
= CALL_EXPR_ARG (exp
, 1);
15720 /* Generate a normal call if it is invalid. */
15721 if (arg1
== error_mark_node
)
15722 return expand_call (exp
, target
, false);
15724 if (TREE_CODE (arg1
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg1
) > 12)
15726 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15727 return expand_call (exp
, target
, false);
15731 case P9V_BUILTIN_VINSERT4B
:
15732 case P9V_BUILTIN_VINSERT4B_DI
:
15733 case P9V_BUILTIN_VEC_VINSERT4B
:
15734 arg2
= CALL_EXPR_ARG (exp
, 2);
15737 /* Generate a normal call if it is invalid. */
15738 if (arg2
== error_mark_node
)
15739 return expand_call (exp
, target
, false);
15741 if (TREE_CODE (arg2
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg2
) > 12)
15743 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15744 return expand_call (exp
, target
, false);
15750 /* Fall through. */
15753 /* Expand abs* operations. */
15755 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
15756 if (d
->code
== fcode
)
15757 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
15759 /* Expand the AltiVec predicates. */
15760 d
= bdesc_altivec_preds
;
15761 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
15762 if (d
->code
== fcode
)
15763 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
15765 /* LV* are funky. We initialized them differently. */
15768 case ALTIVEC_BUILTIN_LVSL
:
15769 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
15770 exp
, target
, false);
15771 case ALTIVEC_BUILTIN_LVSR
:
15772 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
15773 exp
, target
, false);
15774 case ALTIVEC_BUILTIN_LVEBX
:
15775 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
15776 exp
, target
, false);
15777 case ALTIVEC_BUILTIN_LVEHX
:
15778 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
15779 exp
, target
, false);
15780 case ALTIVEC_BUILTIN_LVEWX
:
15781 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
15782 exp
, target
, false);
15783 case ALTIVEC_BUILTIN_LVXL_V2DF
:
15784 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
15785 exp
, target
, false);
15786 case ALTIVEC_BUILTIN_LVXL_V2DI
:
15787 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
15788 exp
, target
, false);
15789 case ALTIVEC_BUILTIN_LVXL_V4SF
:
15790 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
15791 exp
, target
, false);
15792 case ALTIVEC_BUILTIN_LVXL
:
15793 case ALTIVEC_BUILTIN_LVXL_V4SI
:
15794 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
15795 exp
, target
, false);
15796 case ALTIVEC_BUILTIN_LVXL_V8HI
:
15797 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
15798 exp
, target
, false);
15799 case ALTIVEC_BUILTIN_LVXL_V16QI
:
15800 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
15801 exp
, target
, false);
15802 case ALTIVEC_BUILTIN_LVX_V2DF
:
15803 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op
,
15804 exp
, target
, false);
15805 case ALTIVEC_BUILTIN_LVX_V2DI
:
15806 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op
,
15807 exp
, target
, false);
15808 case ALTIVEC_BUILTIN_LVX_V4SF
:
15809 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op
,
15810 exp
, target
, false);
15811 case ALTIVEC_BUILTIN_LVX
:
15812 case ALTIVEC_BUILTIN_LVX_V4SI
:
15813 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op
,
15814 exp
, target
, false);
15815 case ALTIVEC_BUILTIN_LVX_V8HI
:
15816 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op
,
15817 exp
, target
, false);
15818 case ALTIVEC_BUILTIN_LVX_V16QI
:
15819 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op
,
15820 exp
, target
, false);
15821 case ALTIVEC_BUILTIN_LVLX
:
15822 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
15823 exp
, target
, true);
15824 case ALTIVEC_BUILTIN_LVLXL
:
15825 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
15826 exp
, target
, true);
15827 case ALTIVEC_BUILTIN_LVRX
:
15828 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
15829 exp
, target
, true);
15830 case ALTIVEC_BUILTIN_LVRXL
:
15831 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
15832 exp
, target
, true);
15833 case VSX_BUILTIN_LXVD2X_V1TI
:
15834 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
15835 exp
, target
, false);
15836 case VSX_BUILTIN_LXVD2X_V2DF
:
15837 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
15838 exp
, target
, false);
15839 case VSX_BUILTIN_LXVD2X_V2DI
:
15840 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
15841 exp
, target
, false);
15842 case VSX_BUILTIN_LXVW4X_V4SF
:
15843 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
15844 exp
, target
, false);
15845 case VSX_BUILTIN_LXVW4X_V4SI
:
15846 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
15847 exp
, target
, false);
15848 case VSX_BUILTIN_LXVW4X_V8HI
:
15849 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
15850 exp
, target
, false);
15851 case VSX_BUILTIN_LXVW4X_V16QI
:
15852 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
15853 exp
, target
, false);
15854 /* For the following on big endian, it's ok to use any appropriate
15855 unaligned-supporting load, so use a generic expander. For
15856 little-endian, the exact element-reversing instruction must
15858 case VSX_BUILTIN_LD_ELEMREV_V2DF
:
15860 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2df
15861 : CODE_FOR_vsx_ld_elemrev_v2df
);
15862 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15864 case VSX_BUILTIN_LD_ELEMREV_V2DI
:
15866 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2di
15867 : CODE_FOR_vsx_ld_elemrev_v2di
);
15868 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15870 case VSX_BUILTIN_LD_ELEMREV_V4SF
:
15872 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4sf
15873 : CODE_FOR_vsx_ld_elemrev_v4sf
);
15874 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15876 case VSX_BUILTIN_LD_ELEMREV_V4SI
:
15878 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4si
15879 : CODE_FOR_vsx_ld_elemrev_v4si
);
15880 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15882 case VSX_BUILTIN_LD_ELEMREV_V8HI
:
15884 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v8hi
15885 : CODE_FOR_vsx_ld_elemrev_v8hi
);
15886 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15888 case VSX_BUILTIN_LD_ELEMREV_V16QI
:
15890 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v16qi
15891 : CODE_FOR_vsx_ld_elemrev_v16qi
);
15892 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15897 /* Fall through. */
15900 /* XL_BE We initialized them to always load in big endian order. */
15903 case VSX_BUILTIN_XL_BE_V2DI
:
15905 enum insn_code code
= CODE_FOR_vsx_load_v2di
;
15906 return altivec_expand_xl_be_builtin (code
, exp
, target
, false);
15909 case VSX_BUILTIN_XL_BE_V4SI
:
15911 enum insn_code code
= CODE_FOR_vsx_load_v4si
;
15912 return altivec_expand_xl_be_builtin (code
, exp
, target
, false);
15915 case VSX_BUILTIN_XL_BE_V8HI
:
15917 enum insn_code code
= CODE_FOR_vsx_load_v8hi
;
15918 return altivec_expand_xl_be_builtin (code
, exp
, target
, false);
15921 case VSX_BUILTIN_XL_BE_V16QI
:
15923 enum insn_code code
= CODE_FOR_vsx_load_v16qi
;
15924 return altivec_expand_xl_be_builtin (code
, exp
, target
, false);
15927 case VSX_BUILTIN_XL_BE_V2DF
:
15929 enum insn_code code
= CODE_FOR_vsx_load_v2df
;
15930 return altivec_expand_xl_be_builtin (code
, exp
, target
, false);
15933 case VSX_BUILTIN_XL_BE_V4SF
:
15935 enum insn_code code
= CODE_FOR_vsx_load_v4sf
;
15936 return altivec_expand_xl_be_builtin (code
, exp
, target
, false);
15941 /* Fall through. */
15944 *expandedp
= false;
15948 /* Expand the builtin in EXP and store the result in TARGET. Store
15949 true in *EXPANDEDP if we found a builtin to expand. */
15951 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
15953 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15954 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15955 const struct builtin_description
*d
;
15962 case PAIRED_BUILTIN_STX
:
15963 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
15964 case PAIRED_BUILTIN_LX
:
15965 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
15968 /* Fall through. */
15971 /* Expand the paired predicates. */
15972 d
= bdesc_paired_preds
;
15973 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
15974 if (d
->code
== fcode
)
15975 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
15977 *expandedp
= false;
15982 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
15984 rtx pat
, scratch
, tmp
;
15985 tree form
= CALL_EXPR_ARG (exp
, 0);
15986 tree arg0
= CALL_EXPR_ARG (exp
, 1);
15987 tree arg1
= CALL_EXPR_ARG (exp
, 2);
15988 rtx op0
= expand_normal (arg0
);
15989 rtx op1
= expand_normal (arg1
);
15990 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
15991 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
15993 enum rtx_code code
;
15995 if (TREE_CODE (form
) != INTEGER_CST
)
15997 error ("argument 1 of %s must be a constant",
15998 "__builtin_paired_predicate");
16002 form_int
= TREE_INT_CST_LOW (form
);
16004 gcc_assert (mode0
== mode1
);
16006 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
16010 || GET_MODE (target
) != SImode
16011 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
16012 target
= gen_reg_rtx (SImode
);
16013 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
16014 op0
= copy_to_mode_reg (mode0
, op0
);
16015 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
16016 op1
= copy_to_mode_reg (mode1
, op1
);
16018 scratch
= gen_reg_rtx (CCFPmode
);
16020 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
16042 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
16045 error ("argument 1 of %qs is out of range",
16046 "__builtin_paired_predicate");
16050 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
16051 emit_move_insn (target
, tmp
);
16055 /* Raise an error message for a builtin function that is called without the
16056 appropriate target options being set. */
16059 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
16061 size_t uns_fncode
= (size_t) fncode
;
16062 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
16063 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
16065 gcc_assert (name
!= NULL
);
16066 if ((fnmask
& RS6000_BTM_CELL
) != 0)
16067 error ("builtin function %qs is only valid for the cell processor", name
);
16068 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
16069 error ("builtin function %qs requires the %qs option", name
, "-mvsx");
16070 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
16071 error ("builtin function %qs requires the %qs option", name
, "-mhtm");
16072 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
16073 error ("builtin function %qs requires the %qs option", name
, "-maltivec");
16074 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
16075 error ("builtin function %qs requires the %qs option", name
, "-mpaired");
16076 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
16077 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
16078 error ("builtin function %qs requires the %qs and %qs options",
16079 name
, "-mhard-dfp", "-mpower8-vector");
16080 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
16081 error ("builtin function %qs requires the %qs option", name
, "-mhard-dfp");
16082 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
16083 error ("builtin function %qs requires the %qs option", name
,
16084 "-mpower8-vector");
16085 else if ((fnmask
& (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
16086 == (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
16087 error ("builtin function %qs requires the %qs and %qs options",
16088 name
, "-mcpu=power9", "-m64");
16089 else if ((fnmask
& RS6000_BTM_P9_VECTOR
) != 0)
16090 error ("builtin function %qs requires the %qs option", name
,
16092 else if ((fnmask
& (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
16093 == (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
16094 error ("builtin function %qs requires the %qs and %qs options",
16095 name
, "-mcpu=power9", "-m64");
16096 else if ((fnmask
& RS6000_BTM_P9_MISC
) == RS6000_BTM_P9_MISC
)
16097 error ("builtin function %qs requires the %qs option", name
,
16099 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
16100 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
16101 error ("builtin function %qs requires the %qs and %qs options",
16102 name
, "-mhard-float", "-mlong-double-128");
16103 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
16104 error ("builtin function %qs requires the %qs option", name
,
16106 else if ((fnmask
& RS6000_BTM_FLOAT128
) != 0)
16107 error ("builtin function %qs requires the %qs option", name
, "-mfloat128");
16109 error ("builtin function %qs is not supported with the current options",
16113 /* Target hook for early folding of built-ins, shamelessly stolen
16117 rs6000_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
16118 tree
*args
, bool ignore ATTRIBUTE_UNUSED
)
16120 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
16122 enum rs6000_builtins fn_code
16123 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
16126 case RS6000_BUILTIN_NANQ
:
16127 case RS6000_BUILTIN_NANSQ
:
16129 tree type
= TREE_TYPE (TREE_TYPE (fndecl
));
16130 const char *str
= c_getstr (*args
);
16131 int quiet
= fn_code
== RS6000_BUILTIN_NANQ
;
16132 REAL_VALUE_TYPE real
;
16134 if (str
&& real_nan (&real
, str
, quiet
, TYPE_MODE (type
)))
16135 return build_real (type
, real
);
16138 case RS6000_BUILTIN_INFQ
:
16139 case RS6000_BUILTIN_HUGE_VALQ
:
16141 tree type
= TREE_TYPE (TREE_TYPE (fndecl
));
16142 REAL_VALUE_TYPE inf
;
16144 return build_real (type
, inf
);
16150 #ifdef SUBTARGET_FOLD_BUILTIN
16151 return SUBTARGET_FOLD_BUILTIN (fndecl
, n_args
, args
, ignore
);
16157 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16158 a constant, use rs6000_fold_builtin.) */
16161 rs6000_gimple_fold_builtin (gimple_stmt_iterator
*gsi
)
16163 gimple
*stmt
= gsi_stmt (*gsi
);
16164 tree fndecl
= gimple_call_fndecl (stmt
);
16165 gcc_checking_assert (fndecl
&& DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
);
16166 enum rs6000_builtins fn_code
16167 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
16168 tree arg0
, arg1
, lhs
;
16170 size_t uns_fncode
= (size_t) fn_code
;
16171 enum insn_code icode
= rs6000_builtin_info
[uns_fncode
].icode
;
16172 const char *fn_name1
= rs6000_builtin_info
[uns_fncode
].name
;
16173 const char *fn_name2
= (icode
!= CODE_FOR_nothing
)
16174 ? get_insn_name ((int) icode
)
16177 if (TARGET_DEBUG_BUILTIN
)
16178 fprintf (stderr
, "rs6000_gimple_fold_builtin %d %s %s\n",
16179 fn_code
, fn_name1
, fn_name2
);
16181 if (!rs6000_fold_gimple
)
16184 /* Generic solution to prevent gimple folding of code without a LHS. */
16185 if (!gimple_call_lhs (stmt
))
16190 /* Flavors of vec_add. We deliberately don't expand
16191 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16192 TImode, resulting in much poorer code generation. */
16193 case ALTIVEC_BUILTIN_VADDUBM
:
16194 case ALTIVEC_BUILTIN_VADDUHM
:
16195 case ALTIVEC_BUILTIN_VADDUWM
:
16196 case P8V_BUILTIN_VADDUDM
:
16197 case ALTIVEC_BUILTIN_VADDFP
:
16198 case VSX_BUILTIN_XVADDDP
:
16200 arg0
= gimple_call_arg (stmt
, 0);
16201 arg1
= gimple_call_arg (stmt
, 1);
16202 lhs
= gimple_call_lhs (stmt
);
16203 gimple
*g
= gimple_build_assign (lhs
, PLUS_EXPR
, arg0
, arg1
);
16204 gimple_set_location (g
, gimple_location (stmt
));
16205 gsi_replace (gsi
, g
, true);
16208 /* Flavors of vec_sub. We deliberately don't expand
16209 P8V_BUILTIN_VSUBUQM. */
16210 case ALTIVEC_BUILTIN_VSUBUBM
:
16211 case ALTIVEC_BUILTIN_VSUBUHM
:
16212 case ALTIVEC_BUILTIN_VSUBUWM
:
16213 case P8V_BUILTIN_VSUBUDM
:
16214 case ALTIVEC_BUILTIN_VSUBFP
:
16215 case VSX_BUILTIN_XVSUBDP
:
16217 arg0
= gimple_call_arg (stmt
, 0);
16218 arg1
= gimple_call_arg (stmt
, 1);
16219 lhs
= gimple_call_lhs (stmt
);
16220 gimple
*g
= gimple_build_assign (lhs
, MINUS_EXPR
, arg0
, arg1
);
16221 gimple_set_location (g
, gimple_location (stmt
));
16222 gsi_replace (gsi
, g
, true);
16225 case VSX_BUILTIN_XVMULSP
:
16226 case VSX_BUILTIN_XVMULDP
:
16228 arg0
= gimple_call_arg (stmt
, 0);
16229 arg1
= gimple_call_arg (stmt
, 1);
16230 lhs
= gimple_call_lhs (stmt
);
16231 gimple
*g
= gimple_build_assign (lhs
, MULT_EXPR
, arg0
, arg1
);
16232 gimple_set_location (g
, gimple_location (stmt
));
16233 gsi_replace (gsi
, g
, true);
16236 /* Even element flavors of vec_mul (signed). */
16237 case ALTIVEC_BUILTIN_VMULESB
:
16238 case ALTIVEC_BUILTIN_VMULESH
:
16239 /* Even element flavors of vec_mul (unsigned). */
16240 case ALTIVEC_BUILTIN_VMULEUB
:
16241 case ALTIVEC_BUILTIN_VMULEUH
:
16243 arg0
= gimple_call_arg (stmt
, 0);
16244 arg1
= gimple_call_arg (stmt
, 1);
16245 lhs
= gimple_call_lhs (stmt
);
16246 gimple
*g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_EVEN_EXPR
, arg0
, arg1
);
16247 gimple_set_location (g
, gimple_location (stmt
));
16248 gsi_replace (gsi
, g
, true);
16251 /* Odd element flavors of vec_mul (signed). */
16252 case ALTIVEC_BUILTIN_VMULOSB
:
16253 case ALTIVEC_BUILTIN_VMULOSH
:
16254 /* Odd element flavors of vec_mul (unsigned). */
16255 case ALTIVEC_BUILTIN_VMULOUB
:
16256 case ALTIVEC_BUILTIN_VMULOUH
:
16258 arg0
= gimple_call_arg (stmt
, 0);
16259 arg1
= gimple_call_arg (stmt
, 1);
16260 lhs
= gimple_call_lhs (stmt
);
16261 gimple
*g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_ODD_EXPR
, arg0
, arg1
);
16262 gimple_set_location (g
, gimple_location (stmt
));
16263 gsi_replace (gsi
, g
, true);
16266 /* Flavors of vec_div (Integer). */
16267 case VSX_BUILTIN_DIV_V2DI
:
16268 case VSX_BUILTIN_UDIV_V2DI
:
16270 arg0
= gimple_call_arg (stmt
, 0);
16271 arg1
= gimple_call_arg (stmt
, 1);
16272 lhs
= gimple_call_lhs (stmt
);
16273 gimple
*g
= gimple_build_assign (lhs
, TRUNC_DIV_EXPR
, arg0
, arg1
);
16274 gimple_set_location (g
, gimple_location (stmt
));
16275 gsi_replace (gsi
, g
, true);
16278 /* Flavors of vec_div (Float). */
16279 case VSX_BUILTIN_XVDIVSP
:
16280 case VSX_BUILTIN_XVDIVDP
:
16282 arg0
= gimple_call_arg (stmt
, 0);
16283 arg1
= gimple_call_arg (stmt
, 1);
16284 lhs
= gimple_call_lhs (stmt
);
16285 gimple
*g
= gimple_build_assign (lhs
, RDIV_EXPR
, arg0
, arg1
);
16286 gimple_set_location (g
, gimple_location (stmt
));
16287 gsi_replace (gsi
, g
, true);
16290 /* Flavors of vec_and. */
16291 case ALTIVEC_BUILTIN_VAND
:
16293 arg0
= gimple_call_arg (stmt
, 0);
16294 arg1
= gimple_call_arg (stmt
, 1);
16295 lhs
= gimple_call_lhs (stmt
);
16296 gimple
*g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, arg1
);
16297 gimple_set_location (g
, gimple_location (stmt
));
16298 gsi_replace (gsi
, g
, true);
16301 /* Flavors of vec_andc. */
16302 case ALTIVEC_BUILTIN_VANDC
:
16304 arg0
= gimple_call_arg (stmt
, 0);
16305 arg1
= gimple_call_arg (stmt
, 1);
16306 lhs
= gimple_call_lhs (stmt
);
16307 tree temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
16308 gimple
*g
= gimple_build_assign(temp
, BIT_NOT_EXPR
, arg1
);
16309 gimple_set_location (g
, gimple_location (stmt
));
16310 gsi_insert_before(gsi
, g
, GSI_SAME_STMT
);
16311 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, temp
);
16312 gimple_set_location (g
, gimple_location (stmt
));
16313 gsi_replace (gsi
, g
, true);
16316 /* Flavors of vec_nand. */
16317 case P8V_BUILTIN_VEC_NAND
:
16318 case P8V_BUILTIN_NAND_V16QI
:
16319 case P8V_BUILTIN_NAND_V8HI
:
16320 case P8V_BUILTIN_NAND_V4SI
:
16321 case P8V_BUILTIN_NAND_V4SF
:
16322 case P8V_BUILTIN_NAND_V2DF
:
16323 case P8V_BUILTIN_NAND_V2DI
:
16325 arg0
= gimple_call_arg (stmt
, 0);
16326 arg1
= gimple_call_arg (stmt
, 1);
16327 lhs
= gimple_call_lhs (stmt
);
16328 tree temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
16329 gimple
*g
= gimple_build_assign(temp
, BIT_AND_EXPR
, arg0
, arg1
);
16330 gimple_set_location (g
, gimple_location (stmt
));
16331 gsi_insert_before(gsi
, g
, GSI_SAME_STMT
);
16332 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
16333 gimple_set_location (g
, gimple_location (stmt
));
16334 gsi_replace (gsi
, g
, true);
16337 /* Flavors of vec_or. */
16338 case ALTIVEC_BUILTIN_VOR
:
16340 arg0
= gimple_call_arg (stmt
, 0);
16341 arg1
= gimple_call_arg (stmt
, 1);
16342 lhs
= gimple_call_lhs (stmt
);
16343 gimple
*g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, arg1
);
16344 gimple_set_location (g
, gimple_location (stmt
));
16345 gsi_replace (gsi
, g
, true);
16348 /* flavors of vec_orc. */
16349 case P8V_BUILTIN_ORC_V16QI
:
16350 case P8V_BUILTIN_ORC_V8HI
:
16351 case P8V_BUILTIN_ORC_V4SI
:
16352 case P8V_BUILTIN_ORC_V4SF
:
16353 case P8V_BUILTIN_ORC_V2DF
:
16354 case P8V_BUILTIN_ORC_V2DI
:
16356 arg0
= gimple_call_arg (stmt
, 0);
16357 arg1
= gimple_call_arg (stmt
, 1);
16358 lhs
= gimple_call_lhs (stmt
);
16359 tree temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
16360 gimple
*g
= gimple_build_assign(temp
, BIT_NOT_EXPR
, arg1
);
16361 gimple_set_location (g
, gimple_location (stmt
));
16362 gsi_insert_before(gsi
, g
, GSI_SAME_STMT
);
16363 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, temp
);
16364 gimple_set_location (g
, gimple_location (stmt
));
16365 gsi_replace (gsi
, g
, true);
16368 /* Flavors of vec_xor. */
16369 case ALTIVEC_BUILTIN_VXOR
:
16371 arg0
= gimple_call_arg (stmt
, 0);
16372 arg1
= gimple_call_arg (stmt
, 1);
16373 lhs
= gimple_call_lhs (stmt
);
16374 gimple
*g
= gimple_build_assign (lhs
, BIT_XOR_EXPR
, arg0
, arg1
);
16375 gimple_set_location (g
, gimple_location (stmt
));
16376 gsi_replace (gsi
, g
, true);
16379 /* Flavors of vec_nor. */
16380 case ALTIVEC_BUILTIN_VNOR
:
16382 arg0
= gimple_call_arg (stmt
, 0);
16383 arg1
= gimple_call_arg (stmt
, 1);
16384 lhs
= gimple_call_lhs (stmt
);
16385 tree temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
16386 gimple
*g
= gimple_build_assign (temp
, BIT_IOR_EXPR
, arg0
, arg1
);
16387 gimple_set_location (g
, gimple_location (stmt
));
16388 gsi_insert_before(gsi
, g
, GSI_SAME_STMT
);
16389 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
16390 gimple_set_location (g
, gimple_location (stmt
));
16391 gsi_replace (gsi
, g
, true);
16394 /* flavors of vec_abs. */
16395 case ALTIVEC_BUILTIN_ABS_V16QI
:
16396 case ALTIVEC_BUILTIN_ABS_V8HI
:
16397 case ALTIVEC_BUILTIN_ABS_V4SI
:
16398 case ALTIVEC_BUILTIN_ABS_V4SF
:
16399 case P8V_BUILTIN_ABS_V2DI
:
16400 case VSX_BUILTIN_XVABSDP
:
16402 arg0
= gimple_call_arg (stmt
, 0);
16403 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0
)))
16404 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0
))))
16406 lhs
= gimple_call_lhs (stmt
);
16407 gimple
*g
= gimple_build_assign (lhs
, ABS_EXPR
, arg0
);
16408 gimple_set_location (g
, gimple_location (stmt
));
16409 gsi_replace (gsi
, g
, true);
16412 /* flavors of vec_min. */
16413 case VSX_BUILTIN_XVMINDP
:
16414 case P8V_BUILTIN_VMINSD
:
16415 case P8V_BUILTIN_VMINUD
:
16416 case ALTIVEC_BUILTIN_VMINSB
:
16417 case ALTIVEC_BUILTIN_VMINSH
:
16418 case ALTIVEC_BUILTIN_VMINSW
:
16419 case ALTIVEC_BUILTIN_VMINUB
:
16420 case ALTIVEC_BUILTIN_VMINUH
:
16421 case ALTIVEC_BUILTIN_VMINUW
:
16422 case ALTIVEC_BUILTIN_VMINFP
:
16424 arg0
= gimple_call_arg (stmt
, 0);
16425 arg1
= gimple_call_arg (stmt
, 1);
16426 lhs
= gimple_call_lhs (stmt
);
16427 gimple
*g
= gimple_build_assign (lhs
, MIN_EXPR
, arg0
, arg1
);
16428 gimple_set_location (g
, gimple_location (stmt
));
16429 gsi_replace (gsi
, g
, true);
16432 /* flavors of vec_max. */
16433 case VSX_BUILTIN_XVMAXDP
:
16434 case P8V_BUILTIN_VMAXSD
:
16435 case P8V_BUILTIN_VMAXUD
:
16436 case ALTIVEC_BUILTIN_VMAXSB
:
16437 case ALTIVEC_BUILTIN_VMAXSH
:
16438 case ALTIVEC_BUILTIN_VMAXSW
:
16439 case ALTIVEC_BUILTIN_VMAXUB
:
16440 case ALTIVEC_BUILTIN_VMAXUH
:
16441 case ALTIVEC_BUILTIN_VMAXUW
:
16442 case ALTIVEC_BUILTIN_VMAXFP
:
16444 arg0
= gimple_call_arg (stmt
, 0);
16445 arg1
= gimple_call_arg (stmt
, 1);
16446 lhs
= gimple_call_lhs (stmt
);
16447 gimple
*g
= gimple_build_assign (lhs
, MAX_EXPR
, arg0
, arg1
);
16448 gimple_set_location (g
, gimple_location (stmt
));
16449 gsi_replace (gsi
, g
, true);
16452 /* Flavors of vec_eqv. */
16453 case P8V_BUILTIN_EQV_V16QI
:
16454 case P8V_BUILTIN_EQV_V8HI
:
16455 case P8V_BUILTIN_EQV_V4SI
:
16456 case P8V_BUILTIN_EQV_V4SF
:
16457 case P8V_BUILTIN_EQV_V2DF
:
16458 case P8V_BUILTIN_EQV_V2DI
:
16460 arg0
= gimple_call_arg (stmt
, 0);
16461 arg1
= gimple_call_arg (stmt
, 1);
16462 lhs
= gimple_call_lhs (stmt
);
16463 tree temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
16464 gimple
*g
= gimple_build_assign (temp
, BIT_XOR_EXPR
, arg0
, arg1
);
16465 gimple_set_location (g
, gimple_location (stmt
));
16466 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
16467 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
16468 gimple_set_location (g
, gimple_location (stmt
));
16469 gsi_replace (gsi
, g
, true);
16472 /* Flavors of vec_rotate_left. */
16473 case ALTIVEC_BUILTIN_VRLB
:
16474 case ALTIVEC_BUILTIN_VRLH
:
16475 case ALTIVEC_BUILTIN_VRLW
:
16476 case P8V_BUILTIN_VRLD
:
16478 arg0
= gimple_call_arg (stmt
, 0);
16479 arg1
= gimple_call_arg (stmt
, 1);
16480 lhs
= gimple_call_lhs (stmt
);
16481 gimple
*g
= gimple_build_assign (lhs
, LROTATE_EXPR
, arg0
, arg1
);
16482 gimple_set_location (g
, gimple_location (stmt
));
16483 gsi_replace (gsi
, g
, true);
16486 /* Flavors of vector shift right algebraic.
16487 vec_sra{b,h,w} -> vsra{b,h,w}. */
16488 case ALTIVEC_BUILTIN_VSRAB
:
16489 case ALTIVEC_BUILTIN_VSRAH
:
16490 case ALTIVEC_BUILTIN_VSRAW
:
16491 case P8V_BUILTIN_VSRAD
:
16493 arg0
= gimple_call_arg (stmt
, 0);
16494 arg1
= gimple_call_arg (stmt
, 1);
16495 lhs
= gimple_call_lhs (stmt
);
16496 gimple
*g
= gimple_build_assign (lhs
, RSHIFT_EXPR
, arg0
, arg1
);
16497 gimple_set_location (g
, gimple_location (stmt
));
16498 gsi_replace (gsi
, g
, true);
16501 /* Flavors of vector shift left.
16502 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
16503 case ALTIVEC_BUILTIN_VSLB
:
16504 case ALTIVEC_BUILTIN_VSLH
:
16505 case ALTIVEC_BUILTIN_VSLW
:
16506 case P8V_BUILTIN_VSLD
:
16508 arg0
= gimple_call_arg (stmt
, 0);
16509 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0
)))
16510 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0
))))
16512 arg1
= gimple_call_arg (stmt
, 1);
16513 lhs
= gimple_call_lhs (stmt
);
16514 gimple
*g
= gimple_build_assign (lhs
, LSHIFT_EXPR
, arg0
, arg1
);
16515 gimple_set_location (g
, gimple_location (stmt
));
16516 gsi_replace (gsi
, g
, true);
16519 /* Flavors of vector shift right. */
16520 case ALTIVEC_BUILTIN_VSRB
:
16521 case ALTIVEC_BUILTIN_VSRH
:
16522 case ALTIVEC_BUILTIN_VSRW
:
16523 case P8V_BUILTIN_VSRD
:
16525 arg0
= gimple_call_arg (stmt
, 0);
16526 arg1
= gimple_call_arg (stmt
, 1);
16527 lhs
= gimple_call_lhs (stmt
);
16528 gimple_seq stmts
= NULL
;
16529 /* Convert arg0 to unsigned. */
16531 = gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
16532 unsigned_type_for (TREE_TYPE (arg0
)), arg0
);
16534 = gimple_build (&stmts
, RSHIFT_EXPR
,
16535 TREE_TYPE (arg0_unsigned
), arg0_unsigned
, arg1
);
16536 /* Convert result back to the lhs type. */
16537 res
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
, TREE_TYPE (lhs
), res
);
16538 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16539 update_call_from_tree (gsi
, res
);
16543 if (TARGET_DEBUG_BUILTIN
)
16544 fprintf (stderr
, "gimple builtin intrinsic not matched:%d %s %s\n",
16545 fn_code
, fn_name1
, fn_name2
);
16552 /* Expand an expression EXP that calls a built-in function,
16553 with result going to TARGET if that's convenient
16554 (and in mode MODE if that's convenient).
16555 SUBTARGET may be used as the target for computing one of EXP's operands.
16556 IGNORE is nonzero if the value is to be ignored. */
16559 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
16560 machine_mode mode ATTRIBUTE_UNUSED
,
16561 int ignore ATTRIBUTE_UNUSED
)
16563 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
16564 enum rs6000_builtins fcode
16565 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
16566 size_t uns_fcode
= (size_t)fcode
;
16567 const struct builtin_description
*d
;
16571 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
16572 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
16574 if (TARGET_DEBUG_BUILTIN
)
16576 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
16577 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
16578 const char *name2
= (icode
!= CODE_FOR_nothing
)
16579 ? get_insn_name ((int) icode
)
16583 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
16585 default: name3
= "unknown"; break;
16586 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
16587 case RS6000_BTC_UNARY
: name3
= "unary"; break;
16588 case RS6000_BTC_BINARY
: name3
= "binary"; break;
16589 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
16590 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
16591 case RS6000_BTC_ABS
: name3
= "abs"; break;
16592 case RS6000_BTC_DST
: name3
= "dst"; break;
16597 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16598 (name1
) ? name1
: "---", fcode
,
16599 (name2
) ? name2
: "---", (int) icode
,
16601 func_valid_p
? "" : ", not valid");
16606 rs6000_invalid_builtin (fcode
);
16608 /* Given it is invalid, just generate a normal call. */
16609 return expand_call (exp
, target
, ignore
);
16614 case RS6000_BUILTIN_RECIP
:
16615 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
16617 case RS6000_BUILTIN_RECIPF
:
16618 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
16620 case RS6000_BUILTIN_RSQRTF
:
16621 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
16623 case RS6000_BUILTIN_RSQRT
:
16624 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
16626 case POWER7_BUILTIN_BPERMD
:
16627 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
16628 ? CODE_FOR_bpermd_di
16629 : CODE_FOR_bpermd_si
), exp
, target
);
16631 case RS6000_BUILTIN_GET_TB
:
16632 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
16635 case RS6000_BUILTIN_MFTB
:
16636 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
16637 ? CODE_FOR_rs6000_mftb_di
16638 : CODE_FOR_rs6000_mftb_si
),
16641 case RS6000_BUILTIN_MFFS
:
16642 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
16644 case RS6000_BUILTIN_MTFSF
:
16645 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
16647 case RS6000_BUILTIN_CPU_INIT
:
16648 case RS6000_BUILTIN_CPU_IS
:
16649 case RS6000_BUILTIN_CPU_SUPPORTS
:
16650 return cpu_expand_builtin (fcode
, exp
, target
);
16652 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
16653 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
16655 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
16656 : (int) CODE_FOR_altivec_lvsl_direct
);
16657 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
16658 machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
16662 gcc_assert (TARGET_ALTIVEC
);
16664 arg
= CALL_EXPR_ARG (exp
, 0);
16665 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
16666 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
16667 addr
= memory_address (mode
, op
);
16668 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
16672 /* For the load case need to negate the address. */
16673 op
= gen_reg_rtx (GET_MODE (addr
));
16674 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
16676 op
= gen_rtx_MEM (mode
, op
);
16679 || GET_MODE (target
) != tmode
16680 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
16681 target
= gen_reg_rtx (tmode
);
16683 pat
= GEN_FCN (icode
) (target
, op
);
16691 case ALTIVEC_BUILTIN_VCFUX
:
16692 case ALTIVEC_BUILTIN_VCFSX
:
16693 case ALTIVEC_BUILTIN_VCTUXS
:
16694 case ALTIVEC_BUILTIN_VCTSXS
:
16695 /* FIXME: There's got to be a nicer way to handle this case than
16696 constructing a new CALL_EXPR. */
16697 if (call_expr_nargs (exp
) == 1)
16699 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
16700 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
16708 if (TARGET_ALTIVEC
)
16710 ret
= altivec_expand_builtin (exp
, target
, &success
);
16715 if (TARGET_PAIRED_FLOAT
)
16717 ret
= paired_expand_builtin (exp
, target
, &success
);
16724 ret
= htm_expand_builtin (exp
, target
, &success
);
16730 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
16731 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16732 gcc_assert (attr
== RS6000_BTC_UNARY
16733 || attr
== RS6000_BTC_BINARY
16734 || attr
== RS6000_BTC_TERNARY
16735 || attr
== RS6000_BTC_SPECIAL
);
16737 /* Handle simple unary operations. */
16739 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
16740 if (d
->code
== fcode
)
16741 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
16743 /* Handle simple binary operations. */
16745 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16746 if (d
->code
== fcode
)
16747 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
16749 /* Handle simple ternary operations. */
16751 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
16752 if (d
->code
== fcode
)
16753 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
16755 /* Handle simple no-argument operations. */
16757 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
16758 if (d
->code
== fcode
)
16759 return rs6000_expand_zeroop_builtin (d
->icode
, target
);
16761 gcc_unreachable ();
16764 /* Create a builtin vector type with a name. Taking care not to give
16765 the canonical type a name. */
16768 rs6000_vector_type (const char *name
, tree elt_type
, unsigned num_elts
)
16770 tree result
= build_vector_type (elt_type
, num_elts
);
16772 /* Copy so we don't give the canonical type a name. */
16773 result
= build_variant_type_copy (result
);
16775 add_builtin_type (name
, result
);
16781 rs6000_init_builtins (void)
16787 if (TARGET_DEBUG_BUILTIN
)
16788 fprintf (stderr
, "rs6000_init_builtins%s%s%s\n",
16789 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
16790 (TARGET_ALTIVEC
) ? ", altivec" : "",
16791 (TARGET_VSX
) ? ", vsx" : "");
16793 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
16794 V2SF_type_node
= build_vector_type (float_type_node
, 2);
16795 V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
? "__vector long"
16796 : "__vector long long",
16797 intDI_type_node
, 2);
16798 V2DF_type_node
= rs6000_vector_type ("__vector double", double_type_node
, 2);
16799 V4SI_type_node
= rs6000_vector_type ("__vector signed int",
16800 intSI_type_node
, 4);
16801 V4SF_type_node
= rs6000_vector_type ("__vector float", float_type_node
, 4);
16802 V8HI_type_node
= rs6000_vector_type ("__vector signed short",
16803 intHI_type_node
, 8);
16804 V16QI_type_node
= rs6000_vector_type ("__vector signed char",
16805 intQI_type_node
, 16);
16807 unsigned_V16QI_type_node
= rs6000_vector_type ("__vector unsigned char",
16808 unsigned_intQI_type_node
, 16);
16809 unsigned_V8HI_type_node
= rs6000_vector_type ("__vector unsigned short",
16810 unsigned_intHI_type_node
, 8);
16811 unsigned_V4SI_type_node
= rs6000_vector_type ("__vector unsigned int",
16812 unsigned_intSI_type_node
, 4);
16813 unsigned_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16814 ? "__vector unsigned long"
16815 : "__vector unsigned long long",
16816 unsigned_intDI_type_node
, 2);
16818 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
16819 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
16820 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
16821 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
16823 const_str_type_node
16824 = build_pointer_type (build_qualified_type (char_type_node
,
16827 /* We use V1TI mode as a special container to hold __int128_t items that
16828 must live in VSX registers. */
16829 if (intTI_type_node
)
16831 V1TI_type_node
= rs6000_vector_type ("__vector __int128",
16832 intTI_type_node
, 1);
16833 unsigned_V1TI_type_node
16834 = rs6000_vector_type ("__vector unsigned __int128",
16835 unsigned_intTI_type_node
, 1);
16838 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16839 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16840 'vector unsigned short'. */
16842 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
16843 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16844 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
16845 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
16846 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16848 long_integer_type_internal_node
= long_integer_type_node
;
16849 long_unsigned_type_internal_node
= long_unsigned_type_node
;
16850 long_long_integer_type_internal_node
= long_long_integer_type_node
;
16851 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
16852 intQI_type_internal_node
= intQI_type_node
;
16853 uintQI_type_internal_node
= unsigned_intQI_type_node
;
16854 intHI_type_internal_node
= intHI_type_node
;
16855 uintHI_type_internal_node
= unsigned_intHI_type_node
;
16856 intSI_type_internal_node
= intSI_type_node
;
16857 uintSI_type_internal_node
= unsigned_intSI_type_node
;
16858 intDI_type_internal_node
= intDI_type_node
;
16859 uintDI_type_internal_node
= unsigned_intDI_type_node
;
16860 intTI_type_internal_node
= intTI_type_node
;
16861 uintTI_type_internal_node
= unsigned_intTI_type_node
;
16862 float_type_internal_node
= float_type_node
;
16863 double_type_internal_node
= double_type_node
;
16864 long_double_type_internal_node
= long_double_type_node
;
16865 dfloat64_type_internal_node
= dfloat64_type_node
;
16866 dfloat128_type_internal_node
= dfloat128_type_node
;
16867 void_type_internal_node
= void_type_node
;
16869 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16870 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16871 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16872 format that uses a pair of doubles, depending on the switches and
16875 We do not enable the actual __float128 keyword unless the user explicitly
16876 asks for it, because the library support is not yet complete.
16878 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16879 floating point, we need make sure the type is non-zero or else self-test
16880 fails during bootstrap.
16882 We don't register a built-in type for __ibm128 if the type is the same as
16883 long double. Instead we add a #define for __ibm128 in
16884 rs6000_cpu_cpp_builtins to long double. */
16885 if (TARGET_LONG_DOUBLE_128
&& FLOAT128_IEEE_P (TFmode
))
16887 ibm128_float_type_node
= make_node (REAL_TYPE
);
16888 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16889 SET_TYPE_MODE (ibm128_float_type_node
, IFmode
);
16890 layout_type (ibm128_float_type_node
);
16892 lang_hooks
.types
.register_builtin_type (ibm128_float_type_node
,
16896 ibm128_float_type_node
= long_double_type_node
;
16898 if (TARGET_FLOAT128_KEYWORD
)
16900 ieee128_float_type_node
= float128_type_node
;
16901 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16905 else if (TARGET_FLOAT128_TYPE
)
16907 ieee128_float_type_node
= make_node (REAL_TYPE
);
16908 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16909 SET_TYPE_MODE (ieee128_float_type_node
, KFmode
);
16910 layout_type (ieee128_float_type_node
);
16912 /* If we are not exporting the __float128/_Float128 keywords, we need a
16913 keyword to get the types created. Use __ieee128 as the dummy
16915 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16920 ieee128_float_type_node
= long_double_type_node
;
16922 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16924 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
16925 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
16926 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
16927 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
16928 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
16929 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
16930 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
16931 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
16932 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
16933 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
16934 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
16935 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
16936 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
16937 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
16938 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
16939 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
16940 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
16941 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
16942 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
16943 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
16944 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
16945 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
16946 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
16947 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
16948 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
16949 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
16950 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
16951 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
16952 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
16954 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
16955 TYPE_NAME (bool_char_type_node
) = tdecl
;
16957 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
16958 TYPE_NAME (bool_short_type_node
) = tdecl
;
16960 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
16961 TYPE_NAME (bool_int_type_node
) = tdecl
;
16963 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
16964 TYPE_NAME (pixel_type_node
) = tdecl
;
16966 bool_V16QI_type_node
= rs6000_vector_type ("__vector __bool char",
16967 bool_char_type_node
, 16);
16968 bool_V8HI_type_node
= rs6000_vector_type ("__vector __bool short",
16969 bool_short_type_node
, 8);
16970 bool_V4SI_type_node
= rs6000_vector_type ("__vector __bool int",
16971 bool_int_type_node
, 4);
16972 bool_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16973 ? "__vector __bool long"
16974 : "__vector __bool long long",
16975 bool_long_type_node
, 2);
16976 pixel_V8HI_type_node
= rs6000_vector_type ("__vector __pixel",
16977 pixel_type_node
, 8);
16979 /* Paired builtins are only available if you build a compiler with the
16980 appropriate options, so only create those builtins with the appropriate
16981 compiler option. Create Altivec and VSX builtins on machines with at
16982 least the general purpose extensions (970 and newer) to allow the use of
16983 the target attribute. */
16984 if (TARGET_PAIRED_FLOAT
)
16985 paired_init_builtins ();
16986 if (TARGET_EXTRA_BUILTINS
)
16987 altivec_init_builtins ();
16989 htm_init_builtins ();
16991 if (TARGET_EXTRA_BUILTINS
|| TARGET_PAIRED_FLOAT
)
16992 rs6000_common_init_builtins ();
16994 ftype
= build_function_type_list (ieee128_float_type_node
,
16995 const_str_type_node
, NULL_TREE
);
16996 def_builtin ("__builtin_nanq", ftype
, RS6000_BUILTIN_NANQ
);
16997 def_builtin ("__builtin_nansq", ftype
, RS6000_BUILTIN_NANSQ
);
16999 ftype
= build_function_type_list (ieee128_float_type_node
, NULL_TREE
);
17000 def_builtin ("__builtin_infq", ftype
, RS6000_BUILTIN_INFQ
);
17001 def_builtin ("__builtin_huge_valq", ftype
, RS6000_BUILTIN_HUGE_VALQ
);
17003 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
17004 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
17005 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
17007 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
17008 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
17009 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
17011 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
17012 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
17013 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
17015 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
17016 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
17017 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
17019 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
17020 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
17021 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
17022 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
17024 ftype
= build_function_type_list (unsigned_intDI_type_node
,
17026 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
17029 ftype
= build_function_type_list (unsigned_intDI_type_node
,
17032 ftype
= build_function_type_list (unsigned_intSI_type_node
,
17034 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
17036 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
17037 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
17039 ftype
= build_function_type_list (void_type_node
,
17040 intSI_type_node
, double_type_node
,
17042 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
17044 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
17045 def_builtin ("__builtin_cpu_init", ftype
, RS6000_BUILTIN_CPU_INIT
);
17047 ftype
= build_function_type_list (bool_int_type_node
, const_ptr_type_node
,
17049 def_builtin ("__builtin_cpu_is", ftype
, RS6000_BUILTIN_CPU_IS
);
17050 def_builtin ("__builtin_cpu_supports", ftype
, RS6000_BUILTIN_CPU_SUPPORTS
);
17052 /* AIX libm provides clog as __clog. */
17053 if (TARGET_XCOFF
&&
17054 (tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
17055 set_user_assembler_name (tdecl
, "__clog");
17057 #ifdef SUBTARGET_INIT_BUILTINS
17058 SUBTARGET_INIT_BUILTINS
;
17062 /* Returns the rs6000 builtin decl for CODE. */
17065 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
17067 HOST_WIDE_INT fnmask
;
17069 if (code
>= RS6000_BUILTIN_COUNT
)
17070 return error_mark_node
;
17072 fnmask
= rs6000_builtin_info
[code
].mask
;
17073 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
17075 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
17076 return error_mark_node
;
17079 return rs6000_builtin_decls
[code
];
17083 paired_init_builtins (void)
17085 const struct builtin_description
*d
;
17087 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17089 tree int_ftype_int_v2sf_v2sf
17090 = build_function_type_list (integer_type_node
,
17095 tree pcfloat_type_node
=
17096 build_pointer_type (build_qualified_type
17097 (float_type_node
, TYPE_QUAL_CONST
));
17099 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
17100 long_integer_type_node
,
17103 tree void_ftype_v2sf_long_pcfloat
=
17104 build_function_type_list (void_type_node
,
17106 long_integer_type_node
,
17111 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
17112 PAIRED_BUILTIN_LX
);
17115 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
17116 PAIRED_BUILTIN_STX
);
17119 d
= bdesc_paired_preds
;
17120 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
17123 HOST_WIDE_INT mask
= d
->mask
;
17125 if ((mask
& builtin_mask
) != mask
)
17127 if (TARGET_DEBUG_BUILTIN
)
17128 fprintf (stderr
, "paired_init_builtins, skip predicate %s\n",
17133 /* Cannot define builtin if the instruction is disabled. */
17134 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17136 if (TARGET_DEBUG_BUILTIN
)
17137 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
17138 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
17139 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
17141 switch (insn_data
[d
->icode
].operand
[1].mode
)
17144 type
= int_ftype_int_v2sf_v2sf
;
17147 gcc_unreachable ();
17150 def_builtin (d
->name
, type
, d
->code
);
17155 altivec_init_builtins (void)
17157 const struct builtin_description
*d
;
17161 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17163 tree pvoid_type_node
= build_pointer_type (void_type_node
);
17165 tree pcvoid_type_node
17166 = build_pointer_type (build_qualified_type (void_type_node
,
17169 tree int_ftype_opaque
17170 = build_function_type_list (integer_type_node
,
17171 opaque_V4SI_type_node
, NULL_TREE
);
17172 tree opaque_ftype_opaque
17173 = build_function_type_list (integer_type_node
, NULL_TREE
);
17174 tree opaque_ftype_opaque_int
17175 = build_function_type_list (opaque_V4SI_type_node
,
17176 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
17177 tree opaque_ftype_opaque_opaque_int
17178 = build_function_type_list (opaque_V4SI_type_node
,
17179 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
17180 integer_type_node
, NULL_TREE
);
17181 tree opaque_ftype_opaque_opaque_opaque
17182 = build_function_type_list (opaque_V4SI_type_node
,
17183 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
17184 opaque_V4SI_type_node
, NULL_TREE
);
17185 tree opaque_ftype_opaque_opaque
17186 = build_function_type_list (opaque_V4SI_type_node
,
17187 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
17189 tree int_ftype_int_opaque_opaque
17190 = build_function_type_list (integer_type_node
,
17191 integer_type_node
, opaque_V4SI_type_node
,
17192 opaque_V4SI_type_node
, NULL_TREE
);
17193 tree int_ftype_int_v4si_v4si
17194 = build_function_type_list (integer_type_node
,
17195 integer_type_node
, V4SI_type_node
,
17196 V4SI_type_node
, NULL_TREE
);
17197 tree int_ftype_int_v2di_v2di
17198 = build_function_type_list (integer_type_node
,
17199 integer_type_node
, V2DI_type_node
,
17200 V2DI_type_node
, NULL_TREE
);
17201 tree void_ftype_v4si
17202 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
17203 tree v8hi_ftype_void
17204 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
17205 tree void_ftype_void
17206 = build_function_type_list (void_type_node
, NULL_TREE
);
17207 tree void_ftype_int
17208 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
17210 tree opaque_ftype_long_pcvoid
17211 = build_function_type_list (opaque_V4SI_type_node
,
17212 long_integer_type_node
, pcvoid_type_node
,
17214 tree v16qi_ftype_long_pcvoid
17215 = build_function_type_list (V16QI_type_node
,
17216 long_integer_type_node
, pcvoid_type_node
,
17218 tree v8hi_ftype_long_pcvoid
17219 = build_function_type_list (V8HI_type_node
,
17220 long_integer_type_node
, pcvoid_type_node
,
17222 tree v4si_ftype_long_pcvoid
17223 = build_function_type_list (V4SI_type_node
,
17224 long_integer_type_node
, pcvoid_type_node
,
17226 tree v4sf_ftype_long_pcvoid
17227 = build_function_type_list (V4SF_type_node
,
17228 long_integer_type_node
, pcvoid_type_node
,
17230 tree v2df_ftype_long_pcvoid
17231 = build_function_type_list (V2DF_type_node
,
17232 long_integer_type_node
, pcvoid_type_node
,
17234 tree v2di_ftype_long_pcvoid
17235 = build_function_type_list (V2DI_type_node
,
17236 long_integer_type_node
, pcvoid_type_node
,
17239 tree void_ftype_opaque_long_pvoid
17240 = build_function_type_list (void_type_node
,
17241 opaque_V4SI_type_node
, long_integer_type_node
,
17242 pvoid_type_node
, NULL_TREE
);
17243 tree void_ftype_v4si_long_pvoid
17244 = build_function_type_list (void_type_node
,
17245 V4SI_type_node
, long_integer_type_node
,
17246 pvoid_type_node
, NULL_TREE
);
17247 tree void_ftype_v16qi_long_pvoid
17248 = build_function_type_list (void_type_node
,
17249 V16QI_type_node
, long_integer_type_node
,
17250 pvoid_type_node
, NULL_TREE
);
17252 tree void_ftype_v16qi_pvoid_long
17253 = build_function_type_list (void_type_node
,
17254 V16QI_type_node
, pvoid_type_node
,
17255 long_integer_type_node
, NULL_TREE
);
17257 tree void_ftype_v8hi_long_pvoid
17258 = build_function_type_list (void_type_node
,
17259 V8HI_type_node
, long_integer_type_node
,
17260 pvoid_type_node
, NULL_TREE
);
17261 tree void_ftype_v4sf_long_pvoid
17262 = build_function_type_list (void_type_node
,
17263 V4SF_type_node
, long_integer_type_node
,
17264 pvoid_type_node
, NULL_TREE
);
17265 tree void_ftype_v2df_long_pvoid
17266 = build_function_type_list (void_type_node
,
17267 V2DF_type_node
, long_integer_type_node
,
17268 pvoid_type_node
, NULL_TREE
);
17269 tree void_ftype_v2di_long_pvoid
17270 = build_function_type_list (void_type_node
,
17271 V2DI_type_node
, long_integer_type_node
,
17272 pvoid_type_node
, NULL_TREE
);
17273 tree int_ftype_int_v8hi_v8hi
17274 = build_function_type_list (integer_type_node
,
17275 integer_type_node
, V8HI_type_node
,
17276 V8HI_type_node
, NULL_TREE
);
17277 tree int_ftype_int_v16qi_v16qi
17278 = build_function_type_list (integer_type_node
,
17279 integer_type_node
, V16QI_type_node
,
17280 V16QI_type_node
, NULL_TREE
);
17281 tree int_ftype_int_v4sf_v4sf
17282 = build_function_type_list (integer_type_node
,
17283 integer_type_node
, V4SF_type_node
,
17284 V4SF_type_node
, NULL_TREE
);
17285 tree int_ftype_int_v2df_v2df
17286 = build_function_type_list (integer_type_node
,
17287 integer_type_node
, V2DF_type_node
,
17288 V2DF_type_node
, NULL_TREE
);
17289 tree v2di_ftype_v2di
17290 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
17291 tree v4si_ftype_v4si
17292 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
17293 tree v8hi_ftype_v8hi
17294 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
17295 tree v16qi_ftype_v16qi
17296 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
17297 tree v4sf_ftype_v4sf
17298 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
17299 tree v2df_ftype_v2df
17300 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
17301 tree void_ftype_pcvoid_int_int
17302 = build_function_type_list (void_type_node
,
17303 pcvoid_type_node
, integer_type_node
,
17304 integer_type_node
, NULL_TREE
);
17306 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
17307 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
17308 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
17309 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
17310 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
17311 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
17312 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
17313 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
17314 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
17315 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
17316 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
17317 ALTIVEC_BUILTIN_LVXL_V2DF
);
17318 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
17319 ALTIVEC_BUILTIN_LVXL_V2DI
);
17320 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
17321 ALTIVEC_BUILTIN_LVXL_V4SF
);
17322 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
17323 ALTIVEC_BUILTIN_LVXL_V4SI
);
17324 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
17325 ALTIVEC_BUILTIN_LVXL_V8HI
);
17326 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
17327 ALTIVEC_BUILTIN_LVXL_V16QI
);
17328 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
17329 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
17330 ALTIVEC_BUILTIN_LVX_V2DF
);
17331 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
17332 ALTIVEC_BUILTIN_LVX_V2DI
);
17333 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
17334 ALTIVEC_BUILTIN_LVX_V4SF
);
17335 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
17336 ALTIVEC_BUILTIN_LVX_V4SI
);
17337 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
17338 ALTIVEC_BUILTIN_LVX_V8HI
);
17339 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
17340 ALTIVEC_BUILTIN_LVX_V16QI
);
17341 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
17342 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
17343 ALTIVEC_BUILTIN_STVX_V2DF
);
17344 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
17345 ALTIVEC_BUILTIN_STVX_V2DI
);
17346 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
17347 ALTIVEC_BUILTIN_STVX_V4SF
);
17348 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
17349 ALTIVEC_BUILTIN_STVX_V4SI
);
17350 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
17351 ALTIVEC_BUILTIN_STVX_V8HI
);
17352 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
17353 ALTIVEC_BUILTIN_STVX_V16QI
);
17354 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
17355 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
17356 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
17357 ALTIVEC_BUILTIN_STVXL_V2DF
);
17358 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
17359 ALTIVEC_BUILTIN_STVXL_V2DI
);
17360 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
17361 ALTIVEC_BUILTIN_STVXL_V4SF
);
17362 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
17363 ALTIVEC_BUILTIN_STVXL_V4SI
);
17364 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
17365 ALTIVEC_BUILTIN_STVXL_V8HI
);
17366 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
17367 ALTIVEC_BUILTIN_STVXL_V16QI
);
17368 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
17369 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
17370 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
17371 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
17372 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
17373 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
17374 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
17375 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
17376 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
17377 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
17378 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
17379 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
17380 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
17381 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
17382 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
17383 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
17385 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
17386 VSX_BUILTIN_LXVD2X_V2DF
);
17387 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
17388 VSX_BUILTIN_LXVD2X_V2DI
);
17389 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
17390 VSX_BUILTIN_LXVW4X_V4SF
);
17391 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
17392 VSX_BUILTIN_LXVW4X_V4SI
);
17393 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
17394 VSX_BUILTIN_LXVW4X_V8HI
);
17395 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
17396 VSX_BUILTIN_LXVW4X_V16QI
);
17397 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
17398 VSX_BUILTIN_STXVD2X_V2DF
);
17399 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
17400 VSX_BUILTIN_STXVD2X_V2DI
);
17401 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
17402 VSX_BUILTIN_STXVW4X_V4SF
);
17403 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
17404 VSX_BUILTIN_STXVW4X_V4SI
);
17405 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
17406 VSX_BUILTIN_STXVW4X_V8HI
);
17407 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
17408 VSX_BUILTIN_STXVW4X_V16QI
);
17410 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid
,
17411 VSX_BUILTIN_LD_ELEMREV_V2DF
);
17412 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid
,
17413 VSX_BUILTIN_LD_ELEMREV_V2DI
);
17414 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid
,
17415 VSX_BUILTIN_LD_ELEMREV_V4SF
);
17416 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid
,
17417 VSX_BUILTIN_LD_ELEMREV_V4SI
);
17418 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid
,
17419 VSX_BUILTIN_ST_ELEMREV_V2DF
);
17420 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid
,
17421 VSX_BUILTIN_ST_ELEMREV_V2DI
);
17422 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid
,
17423 VSX_BUILTIN_ST_ELEMREV_V4SF
);
17424 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid
,
17425 VSX_BUILTIN_ST_ELEMREV_V4SI
);
17427 def_builtin ("__builtin_vsx_le_be_v8hi", v8hi_ftype_long_pcvoid
,
17428 VSX_BUILTIN_XL_BE_V8HI
);
17429 def_builtin ("__builtin_vsx_le_be_v4si", v4si_ftype_long_pcvoid
,
17430 VSX_BUILTIN_XL_BE_V4SI
);
17431 def_builtin ("__builtin_vsx_le_be_v2di", v2di_ftype_long_pcvoid
,
17432 VSX_BUILTIN_XL_BE_V2DI
);
17433 def_builtin ("__builtin_vsx_le_be_v4sf", v4sf_ftype_long_pcvoid
,
17434 VSX_BUILTIN_XL_BE_V4SF
);
17435 def_builtin ("__builtin_vsx_le_be_v2df", v2df_ftype_long_pcvoid
,
17436 VSX_BUILTIN_XL_BE_V2DF
);
17437 def_builtin ("__builtin_vsx_le_be_v16qi", v16qi_ftype_long_pcvoid
,
17438 VSX_BUILTIN_XL_BE_V16QI
);
17440 if (TARGET_P9_VECTOR
)
17442 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid
,
17443 VSX_BUILTIN_LD_ELEMREV_V8HI
);
17444 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid
,
17445 VSX_BUILTIN_LD_ELEMREV_V16QI
);
17446 def_builtin ("__builtin_vsx_st_elemrev_v8hi",
17447 void_ftype_v8hi_long_pvoid
, VSX_BUILTIN_ST_ELEMREV_V8HI
);
17448 def_builtin ("__builtin_vsx_st_elemrev_v16qi",
17449 void_ftype_v16qi_long_pvoid
, VSX_BUILTIN_ST_ELEMREV_V16QI
);
17453 rs6000_builtin_decls
[(int) VSX_BUILTIN_LD_ELEMREV_V8HI
]
17454 = rs6000_builtin_decls
[(int) VSX_BUILTIN_LXVW4X_V8HI
];
17455 rs6000_builtin_decls
[(int) VSX_BUILTIN_LD_ELEMREV_V16QI
]
17456 = rs6000_builtin_decls
[(int) VSX_BUILTIN_LXVW4X_V16QI
];
17457 rs6000_builtin_decls
[(int) VSX_BUILTIN_ST_ELEMREV_V8HI
]
17458 = rs6000_builtin_decls
[(int) VSX_BUILTIN_STXVW4X_V8HI
];
17459 rs6000_builtin_decls
[(int) VSX_BUILTIN_ST_ELEMREV_V16QI
]
17460 = rs6000_builtin_decls
[(int) VSX_BUILTIN_STXVW4X_V16QI
];
17463 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
17464 VSX_BUILTIN_VEC_LD
);
17465 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
17466 VSX_BUILTIN_VEC_ST
);
17467 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid
,
17468 VSX_BUILTIN_VEC_XL
);
17469 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid
,
17470 VSX_BUILTIN_VEC_XL_BE
);
17471 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid
,
17472 VSX_BUILTIN_VEC_XST
);
17474 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
17475 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
17476 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
17478 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
17479 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
17480 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
17481 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
17482 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
17483 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
17484 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
17485 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
17486 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
17487 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
17488 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
17489 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
17491 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque
,
17492 ALTIVEC_BUILTIN_VEC_ADDE
);
17493 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque
,
17494 ALTIVEC_BUILTIN_VEC_ADDEC
);
17495 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque
,
17496 ALTIVEC_BUILTIN_VEC_CMPNE
);
17497 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque
,
17498 ALTIVEC_BUILTIN_VEC_MUL
);
17499 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque
,
17500 ALTIVEC_BUILTIN_VEC_SUBE
);
17501 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque
,
17502 ALTIVEC_BUILTIN_VEC_SUBEC
);
17504 /* Cell builtins. */
17505 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
17506 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
17507 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
17508 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
17510 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
17511 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
17512 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
17513 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
17515 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
17516 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
17517 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
17518 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
17520 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
17521 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
17522 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
17523 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
17525 if (TARGET_P9_VECTOR
)
17526 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long
,
17527 P9V_BUILTIN_STXVL
);
17529 /* Add the DST variants. */
17531 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
17533 HOST_WIDE_INT mask
= d
->mask
;
17535 /* It is expected that these dst built-in functions may have
17536 d->icode equal to CODE_FOR_nothing. */
17537 if ((mask
& builtin_mask
) != mask
)
17539 if (TARGET_DEBUG_BUILTIN
)
17540 fprintf (stderr
, "altivec_init_builtins, skip dst %s\n",
17544 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
17547 /* Initialize the predicates. */
17548 d
= bdesc_altivec_preds
;
17549 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
17551 machine_mode mode1
;
17553 HOST_WIDE_INT mask
= d
->mask
;
17555 if ((mask
& builtin_mask
) != mask
)
17557 if (TARGET_DEBUG_BUILTIN
)
17558 fprintf (stderr
, "altivec_init_builtins, skip predicate %s\n",
17563 if (rs6000_overloaded_builtin_p (d
->code
))
17567 /* Cannot define builtin if the instruction is disabled. */
17568 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17569 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
17575 type
= int_ftype_int_opaque_opaque
;
17578 type
= int_ftype_int_v2di_v2di
;
17581 type
= int_ftype_int_v4si_v4si
;
17584 type
= int_ftype_int_v8hi_v8hi
;
17587 type
= int_ftype_int_v16qi_v16qi
;
17590 type
= int_ftype_int_v4sf_v4sf
;
17593 type
= int_ftype_int_v2df_v2df
;
17596 gcc_unreachable ();
17599 def_builtin (d
->name
, type
, d
->code
);
17602 /* Initialize the abs* operators. */
17604 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
17606 machine_mode mode0
;
17608 HOST_WIDE_INT mask
= d
->mask
;
17610 if ((mask
& builtin_mask
) != mask
)
17612 if (TARGET_DEBUG_BUILTIN
)
17613 fprintf (stderr
, "altivec_init_builtins, skip abs %s\n",
17618 /* Cannot define builtin if the instruction is disabled. */
17619 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17620 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
17625 type
= v2di_ftype_v2di
;
17628 type
= v4si_ftype_v4si
;
17631 type
= v8hi_ftype_v8hi
;
17634 type
= v16qi_ftype_v16qi
;
17637 type
= v4sf_ftype_v4sf
;
17640 type
= v2df_ftype_v2df
;
17643 gcc_unreachable ();
17646 def_builtin (d
->name
, type
, d
->code
);
17649 /* Initialize target builtin that implements
17650 targetm.vectorize.builtin_mask_for_load. */
17652 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
17653 v16qi_ftype_long_pcvoid
,
17654 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
17655 BUILT_IN_MD
, NULL
, NULL_TREE
);
17656 TREE_READONLY (decl
) = 1;
17657 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17658 altivec_builtin_mask_for_load
= decl
;
17660 /* Access to the vec_init patterns. */
17661 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
17662 integer_type_node
, integer_type_node
,
17663 integer_type_node
, NULL_TREE
);
17664 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
17666 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
17667 short_integer_type_node
,
17668 short_integer_type_node
,
17669 short_integer_type_node
,
17670 short_integer_type_node
,
17671 short_integer_type_node
,
17672 short_integer_type_node
,
17673 short_integer_type_node
, NULL_TREE
);
17674 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
17676 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
17677 char_type_node
, char_type_node
,
17678 char_type_node
, char_type_node
,
17679 char_type_node
, char_type_node
,
17680 char_type_node
, char_type_node
,
17681 char_type_node
, char_type_node
,
17682 char_type_node
, char_type_node
,
17683 char_type_node
, char_type_node
,
17684 char_type_node
, NULL_TREE
);
17685 def_builtin ("__builtin_vec_init_v16qi", ftype
,
17686 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
17688 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
17689 float_type_node
, float_type_node
,
17690 float_type_node
, NULL_TREE
);
17691 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
17693 /* VSX builtins. */
17694 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
17695 double_type_node
, NULL_TREE
);
17696 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
17698 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
17699 intDI_type_node
, NULL_TREE
);
17700 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
17702 /* Access to the vec_set patterns. */
17703 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
17705 integer_type_node
, NULL_TREE
);
17706 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
17708 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
17710 integer_type_node
, NULL_TREE
);
17711 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
17713 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
17715 integer_type_node
, NULL_TREE
);
17716 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
17718 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
17720 integer_type_node
, NULL_TREE
);
17721 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
17723 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
17725 integer_type_node
, NULL_TREE
);
17726 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
17728 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
17730 integer_type_node
, NULL_TREE
);
17731 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
17733 /* Access to the vec_extract patterns. */
17734 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
17735 integer_type_node
, NULL_TREE
);
17736 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
17738 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
17739 integer_type_node
, NULL_TREE
);
17740 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
17742 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
17743 integer_type_node
, NULL_TREE
);
17744 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
17746 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
17747 integer_type_node
, NULL_TREE
);
17748 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
17750 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
17751 integer_type_node
, NULL_TREE
);
17752 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
17754 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
17755 integer_type_node
, NULL_TREE
);
17756 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
17759 if (V1TI_type_node
)
17761 tree v1ti_ftype_long_pcvoid
17762 = build_function_type_list (V1TI_type_node
,
17763 long_integer_type_node
, pcvoid_type_node
,
17765 tree void_ftype_v1ti_long_pvoid
17766 = build_function_type_list (void_type_node
,
17767 V1TI_type_node
, long_integer_type_node
,
17768 pvoid_type_node
, NULL_TREE
);
17769 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
17770 VSX_BUILTIN_LXVD2X_V1TI
);
17771 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
17772 VSX_BUILTIN_STXVD2X_V1TI
);
17773 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
17774 NULL_TREE
, NULL_TREE
);
17775 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
17776 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
17778 integer_type_node
, NULL_TREE
);
17779 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
17780 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
17781 integer_type_node
, NULL_TREE
);
17782 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
17788 htm_init_builtins (void)
17790 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17791 const struct builtin_description
*d
;
17795 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
17797 tree op
[MAX_HTM_OPERANDS
], type
;
17798 HOST_WIDE_INT mask
= d
->mask
;
17799 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
17800 bool void_func
= (attr
& RS6000_BTC_VOID
);
17801 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
17803 tree gpr_type_node
;
17807 /* It is expected that these htm built-in functions may have
17808 d->icode equal to CODE_FOR_nothing. */
17810 if (TARGET_32BIT
&& TARGET_POWERPC64
)
17811 gpr_type_node
= long_long_unsigned_type_node
;
17813 gpr_type_node
= long_unsigned_type_node
;
17815 if (attr
& RS6000_BTC_SPR
)
17817 rettype
= gpr_type_node
;
17818 argtype
= gpr_type_node
;
17820 else if (d
->code
== HTM_BUILTIN_TABORTDC
17821 || d
->code
== HTM_BUILTIN_TABORTDCI
)
17823 rettype
= unsigned_type_node
;
17824 argtype
= gpr_type_node
;
17828 rettype
= unsigned_type_node
;
17829 argtype
= unsigned_type_node
;
17832 if ((mask
& builtin_mask
) != mask
)
17834 if (TARGET_DEBUG_BUILTIN
)
17835 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
17841 if (TARGET_DEBUG_BUILTIN
)
17842 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
17843 (long unsigned) i
);
17847 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
17849 if (attr_args
== RS6000_BTC_UNARY
)
17850 op
[nopnds
++] = argtype
;
17851 else if (attr_args
== RS6000_BTC_BINARY
)
17853 op
[nopnds
++] = argtype
;
17854 op
[nopnds
++] = argtype
;
17856 else if (attr_args
== RS6000_BTC_TERNARY
)
17858 op
[nopnds
++] = argtype
;
17859 op
[nopnds
++] = argtype
;
17860 op
[nopnds
++] = argtype
;
17866 type
= build_function_type_list (op
[0], NULL_TREE
);
17869 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
17872 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
17875 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
17879 gcc_unreachable ();
17882 def_builtin (d
->name
, type
, d
->code
);
17886 /* Hash function for builtin functions with up to 3 arguments and a return
17889 builtin_hasher::hash (builtin_hash_struct
*bh
)
17894 for (i
= 0; i
< 4; i
++)
17896 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
17897 ret
= (ret
* 2) + bh
->uns_p
[i
];
17903 /* Compare builtin hash entries H1 and H2 for equivalence. */
17905 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
17907 return ((p1
->mode
[0] == p2
->mode
[0])
17908 && (p1
->mode
[1] == p2
->mode
[1])
17909 && (p1
->mode
[2] == p2
->mode
[2])
17910 && (p1
->mode
[3] == p2
->mode
[3])
17911 && (p1
->uns_p
[0] == p2
->uns_p
[0])
17912 && (p1
->uns_p
[1] == p2
->uns_p
[1])
17913 && (p1
->uns_p
[2] == p2
->uns_p
[2])
17914 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
17917 /* Map types for builtin functions with an explicit return type and up to 3
17918 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17919 of the argument. */
17921 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
17922 machine_mode mode_arg1
, machine_mode mode_arg2
,
17923 enum rs6000_builtins builtin
, const char *name
)
17925 struct builtin_hash_struct h
;
17926 struct builtin_hash_struct
*h2
;
17929 tree ret_type
= NULL_TREE
;
17930 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
17932 /* Create builtin_hash_table. */
17933 if (builtin_hash_table
== NULL
)
17934 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
17936 h
.type
= NULL_TREE
;
17937 h
.mode
[0] = mode_ret
;
17938 h
.mode
[1] = mode_arg0
;
17939 h
.mode
[2] = mode_arg1
;
17940 h
.mode
[3] = mode_arg2
;
17946 /* If the builtin is a type that produces unsigned results or takes unsigned
17947 arguments, and it is returned as a decl for the vectorizer (such as
17948 widening multiplies, permute), make sure the arguments and return value
17949 are type correct. */
17952 /* unsigned 1 argument functions. */
17953 case CRYPTO_BUILTIN_VSBOX
:
17954 case P8V_BUILTIN_VGBBD
:
17955 case MISC_BUILTIN_CDTBCD
:
17956 case MISC_BUILTIN_CBCDTD
:
17961 /* unsigned 2 argument functions. */
17962 case ALTIVEC_BUILTIN_VMULEUB
:
17963 case ALTIVEC_BUILTIN_VMULEUH
:
17964 case ALTIVEC_BUILTIN_VMULEUW
:
17965 case ALTIVEC_BUILTIN_VMULOUB
:
17966 case ALTIVEC_BUILTIN_VMULOUH
:
17967 case ALTIVEC_BUILTIN_VMULOUW
:
17968 case CRYPTO_BUILTIN_VCIPHER
:
17969 case CRYPTO_BUILTIN_VCIPHERLAST
:
17970 case CRYPTO_BUILTIN_VNCIPHER
:
17971 case CRYPTO_BUILTIN_VNCIPHERLAST
:
17972 case CRYPTO_BUILTIN_VPMSUMB
:
17973 case CRYPTO_BUILTIN_VPMSUMH
:
17974 case CRYPTO_BUILTIN_VPMSUMW
:
17975 case CRYPTO_BUILTIN_VPMSUMD
:
17976 case CRYPTO_BUILTIN_VPMSUM
:
17977 case MISC_BUILTIN_ADDG6S
:
17978 case MISC_BUILTIN_DIVWEU
:
17979 case MISC_BUILTIN_DIVWEUO
:
17980 case MISC_BUILTIN_DIVDEU
:
17981 case MISC_BUILTIN_DIVDEUO
:
17982 case VSX_BUILTIN_UDIV_V2DI
:
17983 case ALTIVEC_BUILTIN_VMAXUB
:
17984 case ALTIVEC_BUILTIN_VMINUB
:
17985 case ALTIVEC_BUILTIN_VMAXUH
:
17986 case ALTIVEC_BUILTIN_VMINUH
:
17987 case ALTIVEC_BUILTIN_VMAXUW
:
17988 case ALTIVEC_BUILTIN_VMINUW
:
17989 case P8V_BUILTIN_VMAXUD
:
17990 case P8V_BUILTIN_VMINUD
:
17996 /* unsigned 3 argument functions. */
17997 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
17998 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
17999 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
18000 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
18001 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
18002 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
18003 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
18004 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
18005 case VSX_BUILTIN_VPERM_16QI_UNS
:
18006 case VSX_BUILTIN_VPERM_8HI_UNS
:
18007 case VSX_BUILTIN_VPERM_4SI_UNS
:
18008 case VSX_BUILTIN_VPERM_2DI_UNS
:
18009 case VSX_BUILTIN_XXSEL_16QI_UNS
:
18010 case VSX_BUILTIN_XXSEL_8HI_UNS
:
18011 case VSX_BUILTIN_XXSEL_4SI_UNS
:
18012 case VSX_BUILTIN_XXSEL_2DI_UNS
:
18013 case CRYPTO_BUILTIN_VPERMXOR
:
18014 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
18015 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
18016 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
18017 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
18018 case CRYPTO_BUILTIN_VSHASIGMAW
:
18019 case CRYPTO_BUILTIN_VSHASIGMAD
:
18020 case CRYPTO_BUILTIN_VSHASIGMA
:
18027 /* signed permute functions with unsigned char mask. */
18028 case ALTIVEC_BUILTIN_VPERM_16QI
:
18029 case ALTIVEC_BUILTIN_VPERM_8HI
:
18030 case ALTIVEC_BUILTIN_VPERM_4SI
:
18031 case ALTIVEC_BUILTIN_VPERM_4SF
:
18032 case ALTIVEC_BUILTIN_VPERM_2DI
:
18033 case ALTIVEC_BUILTIN_VPERM_2DF
:
18034 case VSX_BUILTIN_VPERM_16QI
:
18035 case VSX_BUILTIN_VPERM_8HI
:
18036 case VSX_BUILTIN_VPERM_4SI
:
18037 case VSX_BUILTIN_VPERM_4SF
:
18038 case VSX_BUILTIN_VPERM_2DI
:
18039 case VSX_BUILTIN_VPERM_2DF
:
18043 /* unsigned args, signed return. */
18044 case VSX_BUILTIN_XVCVUXDSP
:
18045 case VSX_BUILTIN_XVCVUXDDP_UNS
:
18046 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
18050 /* signed args, unsigned return. */
18051 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
18052 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
18053 case MISC_BUILTIN_UNPACK_TD
:
18054 case MISC_BUILTIN_UNPACK_V1TI
:
18058 /* unsigned arguments for 128-bit pack instructions. */
18059 case MISC_BUILTIN_PACK_TD
:
18060 case MISC_BUILTIN_PACK_V1TI
:
18065 /* unsigned second arguments (vector shift right). */
18066 case ALTIVEC_BUILTIN_VSRB
:
18067 case ALTIVEC_BUILTIN_VSRH
:
18068 case ALTIVEC_BUILTIN_VSRW
:
18069 case P8V_BUILTIN_VSRD
:
18077 /* Figure out how many args are present. */
18078 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
18081 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
18082 if (!ret_type
&& h
.uns_p
[0])
18083 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
18086 fatal_error (input_location
,
18087 "internal error: builtin function %qs had an unexpected "
18088 "return type %qs", name
, GET_MODE_NAME (h
.mode
[0]));
18090 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
18091 arg_type
[i
] = NULL_TREE
;
18093 for (i
= 0; i
< num_args
; i
++)
18095 int m
= (int) h
.mode
[i
+1];
18096 int uns_p
= h
.uns_p
[i
+1];
18098 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
18099 if (!arg_type
[i
] && uns_p
)
18100 arg_type
[i
] = builtin_mode_to_type
[m
][0];
18103 fatal_error (input_location
,
18104 "internal error: builtin function %qs, argument %d "
18105 "had unexpected argument type %qs", name
, i
,
18106 GET_MODE_NAME (m
));
18109 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
18110 if (*found
== NULL
)
18112 h2
= ggc_alloc
<builtin_hash_struct
> ();
18116 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
18117 arg_type
[2], NULL_TREE
);
18120 return (*found
)->type
;
18124 rs6000_common_init_builtins (void)
18126 const struct builtin_description
*d
;
18129 tree opaque_ftype_opaque
= NULL_TREE
;
18130 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
18131 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
18132 tree v2si_ftype
= NULL_TREE
;
18133 tree v2si_ftype_qi
= NULL_TREE
;
18134 tree v2si_ftype_v2si_qi
= NULL_TREE
;
18135 tree v2si_ftype_int_qi
= NULL_TREE
;
18136 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
18138 if (!TARGET_PAIRED_FLOAT
)
18140 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
18141 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
18144 /* Paired builtins are only available if you build a compiler with the
18145 appropriate options, so only create those builtins with the appropriate
18146 compiler option. Create Altivec and VSX builtins on machines with at
18147 least the general purpose extensions (970 and newer) to allow the use of
18148 the target attribute.. */
18150 if (TARGET_EXTRA_BUILTINS
)
18151 builtin_mask
|= RS6000_BTM_COMMON
;
18153 /* Add the ternary operators. */
18155 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
18158 HOST_WIDE_INT mask
= d
->mask
;
18160 if ((mask
& builtin_mask
) != mask
)
18162 if (TARGET_DEBUG_BUILTIN
)
18163 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
18167 if (rs6000_overloaded_builtin_p (d
->code
))
18169 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
18170 type
= opaque_ftype_opaque_opaque_opaque
18171 = build_function_type_list (opaque_V4SI_type_node
,
18172 opaque_V4SI_type_node
,
18173 opaque_V4SI_type_node
,
18174 opaque_V4SI_type_node
,
18179 enum insn_code icode
= d
->icode
;
18182 if (TARGET_DEBUG_BUILTIN
)
18183 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18189 if (icode
== CODE_FOR_nothing
)
18191 if (TARGET_DEBUG_BUILTIN
)
18192 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
18198 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
18199 insn_data
[icode
].operand
[1].mode
,
18200 insn_data
[icode
].operand
[2].mode
,
18201 insn_data
[icode
].operand
[3].mode
,
18205 def_builtin (d
->name
, type
, d
->code
);
18208 /* Add the binary operators. */
18210 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
18212 machine_mode mode0
, mode1
, mode2
;
18214 HOST_WIDE_INT mask
= d
->mask
;
18216 if ((mask
& builtin_mask
) != mask
)
18218 if (TARGET_DEBUG_BUILTIN
)
18219 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
18223 if (rs6000_overloaded_builtin_p (d
->code
))
18225 if (! (type
= opaque_ftype_opaque_opaque
))
18226 type
= opaque_ftype_opaque_opaque
18227 = build_function_type_list (opaque_V4SI_type_node
,
18228 opaque_V4SI_type_node
,
18229 opaque_V4SI_type_node
,
18234 enum insn_code icode
= d
->icode
;
18237 if (TARGET_DEBUG_BUILTIN
)
18238 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18244 if (icode
== CODE_FOR_nothing
)
18246 if (TARGET_DEBUG_BUILTIN
)
18247 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
18253 mode0
= insn_data
[icode
].operand
[0].mode
;
18254 mode1
= insn_data
[icode
].operand
[1].mode
;
18255 mode2
= insn_data
[icode
].operand
[2].mode
;
18257 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
18259 if (! (type
= v2si_ftype_v2si_qi
))
18260 type
= v2si_ftype_v2si_qi
18261 = build_function_type_list (opaque_V2SI_type_node
,
18262 opaque_V2SI_type_node
,
18267 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
18268 && mode2
== QImode
)
18270 if (! (type
= v2si_ftype_int_qi
))
18271 type
= v2si_ftype_int_qi
18272 = build_function_type_list (opaque_V2SI_type_node
,
18279 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
18283 def_builtin (d
->name
, type
, d
->code
);
18286 /* Add the simple unary operators. */
18288 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
18290 machine_mode mode0
, mode1
;
18292 HOST_WIDE_INT mask
= d
->mask
;
18294 if ((mask
& builtin_mask
) != mask
)
18296 if (TARGET_DEBUG_BUILTIN
)
18297 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
18301 if (rs6000_overloaded_builtin_p (d
->code
))
18303 if (! (type
= opaque_ftype_opaque
))
18304 type
= opaque_ftype_opaque
18305 = build_function_type_list (opaque_V4SI_type_node
,
18306 opaque_V4SI_type_node
,
18311 enum insn_code icode
= d
->icode
;
18314 if (TARGET_DEBUG_BUILTIN
)
18315 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18321 if (icode
== CODE_FOR_nothing
)
18323 if (TARGET_DEBUG_BUILTIN
)
18324 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
18330 mode0
= insn_data
[icode
].operand
[0].mode
;
18331 mode1
= insn_data
[icode
].operand
[1].mode
;
18333 if (mode0
== V2SImode
&& mode1
== QImode
)
18335 if (! (type
= v2si_ftype_qi
))
18336 type
= v2si_ftype_qi
18337 = build_function_type_list (opaque_V2SI_type_node
,
18343 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
18347 def_builtin (d
->name
, type
, d
->code
);
18350 /* Add the simple no-argument operators. */
18352 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
18354 machine_mode mode0
;
18356 HOST_WIDE_INT mask
= d
->mask
;
18358 if ((mask
& builtin_mask
) != mask
)
18360 if (TARGET_DEBUG_BUILTIN
)
18361 fprintf (stderr
, "rs6000_builtin, skip no-argument %s\n", d
->name
);
18364 if (rs6000_overloaded_builtin_p (d
->code
))
18366 if (!opaque_ftype_opaque
)
18367 opaque_ftype_opaque
18368 = build_function_type_list (opaque_V4SI_type_node
, NULL_TREE
);
18369 type
= opaque_ftype_opaque
;
18373 enum insn_code icode
= d
->icode
;
18376 if (TARGET_DEBUG_BUILTIN
)
18377 fprintf (stderr
, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18378 (long unsigned) i
);
18381 if (icode
== CODE_FOR_nothing
)
18383 if (TARGET_DEBUG_BUILTIN
)
18385 "rs6000_builtin, skip no-argument %s (no code)\n",
18389 mode0
= insn_data
[icode
].operand
[0].mode
;
18390 if (mode0
== V2SImode
)
18392 /* code for paired single */
18393 if (! (type
= v2si_ftype
))
18396 = build_function_type_list (opaque_V2SI_type_node
,
18402 type
= builtin_function_type (mode0
, VOIDmode
, VOIDmode
, VOIDmode
,
18405 def_builtin (d
->name
, type
, d
->code
);
18409 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18411 init_float128_ibm (machine_mode mode
)
18413 if (!TARGET_XL_COMPAT
)
18415 set_optab_libfunc (add_optab
, mode
, "__gcc_qadd");
18416 set_optab_libfunc (sub_optab
, mode
, "__gcc_qsub");
18417 set_optab_libfunc (smul_optab
, mode
, "__gcc_qmul");
18418 set_optab_libfunc (sdiv_optab
, mode
, "__gcc_qdiv");
18420 if (!TARGET_HARD_FLOAT
)
18422 set_optab_libfunc (neg_optab
, mode
, "__gcc_qneg");
18423 set_optab_libfunc (eq_optab
, mode
, "__gcc_qeq");
18424 set_optab_libfunc (ne_optab
, mode
, "__gcc_qne");
18425 set_optab_libfunc (gt_optab
, mode
, "__gcc_qgt");
18426 set_optab_libfunc (ge_optab
, mode
, "__gcc_qge");
18427 set_optab_libfunc (lt_optab
, mode
, "__gcc_qlt");
18428 set_optab_libfunc (le_optab
, mode
, "__gcc_qle");
18429 set_optab_libfunc (unord_optab
, mode
, "__gcc_qunord");
18431 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__gcc_stoq");
18432 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__gcc_dtoq");
18433 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__gcc_qtos");
18434 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__gcc_qtod");
18435 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__gcc_qtoi");
18436 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__gcc_qtou");
18437 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__gcc_itoq");
18438 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__gcc_utoq");
18443 set_optab_libfunc (add_optab
, mode
, "_xlqadd");
18444 set_optab_libfunc (sub_optab
, mode
, "_xlqsub");
18445 set_optab_libfunc (smul_optab
, mode
, "_xlqmul");
18446 set_optab_libfunc (sdiv_optab
, mode
, "_xlqdiv");
18449 /* Add various conversions for IFmode to use the traditional TFmode
18451 if (mode
== IFmode
)
18453 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdtf2");
18454 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddtf2");
18455 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctftd2");
18456 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunctfsd2");
18457 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunctfdd2");
18458 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtdtf2");
18460 if (TARGET_POWERPC64
)
18462 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixtfti");
18463 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunstfti");
18464 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattitf");
18465 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntitf");
18470 /* Set up IEEE 128-bit floating point routines. Use different names if the
18471 arguments can be passed in a vector register. The historical PowerPC
18472 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18473 continue to use that if we aren't using vector registers to pass IEEE
18474 128-bit floating point. */
18477 init_float128_ieee (machine_mode mode
)
18479 if (FLOAT128_VECTOR_P (mode
))
18481 set_optab_libfunc (add_optab
, mode
, "__addkf3");
18482 set_optab_libfunc (sub_optab
, mode
, "__subkf3");
18483 set_optab_libfunc (neg_optab
, mode
, "__negkf2");
18484 set_optab_libfunc (smul_optab
, mode
, "__mulkf3");
18485 set_optab_libfunc (sdiv_optab
, mode
, "__divkf3");
18486 set_optab_libfunc (sqrt_optab
, mode
, "__sqrtkf2");
18487 set_optab_libfunc (abs_optab
, mode
, "__abstkf2");
18489 set_optab_libfunc (eq_optab
, mode
, "__eqkf2");
18490 set_optab_libfunc (ne_optab
, mode
, "__nekf2");
18491 set_optab_libfunc (gt_optab
, mode
, "__gtkf2");
18492 set_optab_libfunc (ge_optab
, mode
, "__gekf2");
18493 set_optab_libfunc (lt_optab
, mode
, "__ltkf2");
18494 set_optab_libfunc (le_optab
, mode
, "__lekf2");
18495 set_optab_libfunc (unord_optab
, mode
, "__unordkf2");
18497 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__extendsfkf2");
18498 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__extenddfkf2");
18499 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__trunckfsf2");
18500 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__trunckfdf2");
18502 set_conv_libfunc (sext_optab
, mode
, IFmode
, "__extendtfkf2");
18503 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18504 set_conv_libfunc (sext_optab
, mode
, TFmode
, "__extendtfkf2");
18506 set_conv_libfunc (trunc_optab
, IFmode
, mode
, "__trunckftf2");
18507 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18508 set_conv_libfunc (trunc_optab
, TFmode
, mode
, "__trunckftf2");
18510 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdkf2");
18511 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddkf2");
18512 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunckftd2");
18513 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunckfsd2");
18514 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunckfdd2");
18515 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtdkf2");
18517 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__fixkfsi");
18518 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__fixunskfsi");
18519 set_conv_libfunc (sfix_optab
, DImode
, mode
, "__fixkfdi");
18520 set_conv_libfunc (ufix_optab
, DImode
, mode
, "__fixunskfdi");
18522 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__floatsikf");
18523 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__floatunsikf");
18524 set_conv_libfunc (sfloat_optab
, mode
, DImode
, "__floatdikf");
18525 set_conv_libfunc (ufloat_optab
, mode
, DImode
, "__floatundikf");
18527 if (TARGET_POWERPC64
)
18529 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixkfti");
18530 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunskfti");
18531 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattikf");
18532 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntikf");
18538 set_optab_libfunc (add_optab
, mode
, "_q_add");
18539 set_optab_libfunc (sub_optab
, mode
, "_q_sub");
18540 set_optab_libfunc (neg_optab
, mode
, "_q_neg");
18541 set_optab_libfunc (smul_optab
, mode
, "_q_mul");
18542 set_optab_libfunc (sdiv_optab
, mode
, "_q_div");
18543 if (TARGET_PPC_GPOPT
)
18544 set_optab_libfunc (sqrt_optab
, mode
, "_q_sqrt");
18546 set_optab_libfunc (eq_optab
, mode
, "_q_feq");
18547 set_optab_libfunc (ne_optab
, mode
, "_q_fne");
18548 set_optab_libfunc (gt_optab
, mode
, "_q_fgt");
18549 set_optab_libfunc (ge_optab
, mode
, "_q_fge");
18550 set_optab_libfunc (lt_optab
, mode
, "_q_flt");
18551 set_optab_libfunc (le_optab
, mode
, "_q_fle");
18553 set_conv_libfunc (sext_optab
, mode
, SFmode
, "_q_stoq");
18554 set_conv_libfunc (sext_optab
, mode
, DFmode
, "_q_dtoq");
18555 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "_q_qtos");
18556 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "_q_qtod");
18557 set_conv_libfunc (sfix_optab
, SImode
, mode
, "_q_qtoi");
18558 set_conv_libfunc (ufix_optab
, SImode
, mode
, "_q_qtou");
18559 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "_q_itoq");
18560 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "_q_utoq");
18565 rs6000_init_libfuncs (void)
18567 /* __float128 support. */
18568 if (TARGET_FLOAT128_TYPE
)
18570 init_float128_ibm (IFmode
);
18571 init_float128_ieee (KFmode
);
18574 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18575 if (TARGET_LONG_DOUBLE_128
)
18577 if (!TARGET_IEEEQUAD
)
18578 init_float128_ibm (TFmode
);
18580 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18582 init_float128_ieee (TFmode
);
18586 /* Emit a potentially record-form instruction, setting DST from SRC.
18587 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18588 signed comparison of DST with zero. If DOT is 1, the generated RTL
18589 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18590 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18591 a separate COMPARE. */
18594 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
18598 emit_move_insn (dst
, src
);
18602 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
18604 emit_move_insn (dst
, src
);
18605 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
18609 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
18612 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
18613 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
18617 rtx set
= gen_rtx_SET (dst
, src
);
18618 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
18623 /* A validation routine: say whether CODE, a condition code, and MODE
18624 match. The other alternatives either don't make sense or should
18625 never be generated. */
18628 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
18630 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
18631 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
18632 && GET_MODE_CLASS (mode
) == MODE_CC
);
18634 /* These don't make sense. */
18635 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
18636 || mode
!= CCUNSmode
);
18638 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
18639 || mode
== CCUNSmode
);
18641 gcc_assert (mode
== CCFPmode
18642 || (code
!= ORDERED
&& code
!= UNORDERED
18643 && code
!= UNEQ
&& code
!= LTGT
18644 && code
!= UNGT
&& code
!= UNLT
18645 && code
!= UNGE
&& code
!= UNLE
));
18647 /* These should never be generated except for
18648 flag_finite_math_only. */
18649 gcc_assert (mode
!= CCFPmode
18650 || flag_finite_math_only
18651 || (code
!= LE
&& code
!= GE
18652 && code
!= UNEQ
&& code
!= LTGT
18653 && code
!= UNGT
&& code
!= UNLT
));
18655 /* These are invalid; the information is not there. */
18656 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
18660 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18661 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18662 not zero, store there the bit offset (counted from the right) where
18663 the single stretch of 1 bits begins; and similarly for B, the bit
18664 offset where it ends. */
18667 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
18669 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
18670 unsigned HOST_WIDE_INT bit
;
18672 int n
= GET_MODE_PRECISION (mode
);
18674 if (mode
!= DImode
&& mode
!= SImode
)
18677 if (INTVAL (mask
) >= 0)
18680 ne
= exact_log2 (bit
);
18681 nb
= exact_log2 (val
+ bit
);
18683 else if (val
+ 1 == 0)
18692 nb
= exact_log2 (bit
);
18693 ne
= exact_log2 (val
+ bit
);
18698 ne
= exact_log2 (bit
);
18699 if (val
+ bit
== 0)
18707 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
18718 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18719 or rldicr instruction, to implement an AND with it in mode MODE. */
18722 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
18726 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18729 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18731 if (mode
== DImode
)
18732 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
18734 /* For SImode, rlwinm can do everything. */
18735 if (mode
== SImode
)
18736 return (nb
< 32 && ne
< 32);
18741 /* Return the instruction template for an AND with mask in mode MODE, with
18742 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18745 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18749 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
18750 gcc_unreachable ();
18752 if (mode
== DImode
&& ne
== 0)
18754 operands
[3] = GEN_INT (63 - nb
);
18756 return "rldicl. %0,%1,0,%3";
18757 return "rldicl %0,%1,0,%3";
18760 if (mode
== DImode
&& nb
== 63)
18762 operands
[3] = GEN_INT (63 - ne
);
18764 return "rldicr. %0,%1,0,%3";
18765 return "rldicr %0,%1,0,%3";
18768 if (nb
< 32 && ne
< 32)
18770 operands
[3] = GEN_INT (31 - nb
);
18771 operands
[4] = GEN_INT (31 - ne
);
18773 return "rlwinm. %0,%1,0,%3,%4";
18774 return "rlwinm %0,%1,0,%3,%4";
18777 gcc_unreachable ();
18780 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18781 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18782 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18785 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
18789 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18792 int n
= GET_MODE_PRECISION (mode
);
18795 if (CONST_INT_P (XEXP (shift
, 1)))
18797 sh
= INTVAL (XEXP (shift
, 1));
18798 if (sh
< 0 || sh
>= n
)
18802 rtx_code code
= GET_CODE (shift
);
18804 /* Convert any shift by 0 to a rotate, to simplify below code. */
18808 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18809 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18811 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18817 /* DImode rotates need rld*. */
18818 if (mode
== DImode
&& code
== ROTATE
)
18819 return (nb
== 63 || ne
== 0 || ne
== sh
);
18821 /* SImode rotates need rlw*. */
18822 if (mode
== SImode
&& code
== ROTATE
)
18823 return (nb
< 32 && ne
< 32 && sh
< 32);
18825 /* Wrap-around masks are only okay for rotates. */
18829 /* Variable shifts are only okay for rotates. */
18833 /* Don't allow ASHIFT if the mask is wrong for that. */
18834 if (code
== ASHIFT
&& ne
< sh
)
18837 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18838 if the mask is wrong for that. */
18839 if (nb
< 32 && ne
< 32 && sh
< 32
18840 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18843 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18844 if the mask is wrong for that. */
18845 if (code
== LSHIFTRT
)
18847 if (nb
== 63 || ne
== 0 || ne
== sh
)
18848 return !(code
== LSHIFTRT
&& nb
>= sh
);
18853 /* Return the instruction template for a shift with mask in mode MODE, with
18854 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18857 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18861 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18862 gcc_unreachable ();
18864 if (mode
== DImode
&& ne
== 0)
18866 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18867 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
18868 operands
[3] = GEN_INT (63 - nb
);
18870 return "rld%I2cl. %0,%1,%2,%3";
18871 return "rld%I2cl %0,%1,%2,%3";
18874 if (mode
== DImode
&& nb
== 63)
18876 operands
[3] = GEN_INT (63 - ne
);
18878 return "rld%I2cr. %0,%1,%2,%3";
18879 return "rld%I2cr %0,%1,%2,%3";
18883 && GET_CODE (operands
[4]) != LSHIFTRT
18884 && CONST_INT_P (operands
[2])
18885 && ne
== INTVAL (operands
[2]))
18887 operands
[3] = GEN_INT (63 - nb
);
18889 return "rld%I2c. %0,%1,%2,%3";
18890 return "rld%I2c %0,%1,%2,%3";
18893 if (nb
< 32 && ne
< 32)
18895 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18896 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18897 operands
[3] = GEN_INT (31 - nb
);
18898 operands
[4] = GEN_INT (31 - ne
);
18899 /* This insn can also be a 64-bit rotate with mask that really makes
18900 it just a shift right (with mask); the %h below are to adjust for
18901 that situation (shift count is >= 32 in that case). */
18903 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18904 return "rlw%I2nm %0,%1,%h2,%3,%4";
18907 gcc_unreachable ();
18910 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18911 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18912 ASHIFT, or LSHIFTRT) in mode MODE. */
18915 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
18919 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18922 int n
= GET_MODE_PRECISION (mode
);
18924 int sh
= INTVAL (XEXP (shift
, 1));
18925 if (sh
< 0 || sh
>= n
)
18928 rtx_code code
= GET_CODE (shift
);
18930 /* Convert any shift by 0 to a rotate, to simplify below code. */
18934 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18935 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18937 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18943 /* DImode rotates need rldimi. */
18944 if (mode
== DImode
&& code
== ROTATE
)
18947 /* SImode rotates need rlwimi. */
18948 if (mode
== SImode
&& code
== ROTATE
)
18949 return (nb
< 32 && ne
< 32 && sh
< 32);
18951 /* Wrap-around masks are only okay for rotates. */
18955 /* Don't allow ASHIFT if the mask is wrong for that. */
18956 if (code
== ASHIFT
&& ne
< sh
)
18959 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18960 if the mask is wrong for that. */
18961 if (nb
< 32 && ne
< 32 && sh
< 32
18962 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18965 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18966 if the mask is wrong for that. */
18967 if (code
== LSHIFTRT
)
18970 return !(code
== LSHIFTRT
&& nb
>= sh
);
18975 /* Return the instruction template for an insert with mask in mode MODE, with
18976 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18979 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18983 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18984 gcc_unreachable ();
18986 /* Prefer rldimi because rlwimi is cracked. */
18987 if (TARGET_POWERPC64
18988 && (!dot
|| mode
== DImode
)
18989 && GET_CODE (operands
[4]) != LSHIFTRT
18990 && ne
== INTVAL (operands
[2]))
18992 operands
[3] = GEN_INT (63 - nb
);
18994 return "rldimi. %0,%1,%2,%3";
18995 return "rldimi %0,%1,%2,%3";
18998 if (nb
< 32 && ne
< 32)
19000 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
19001 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
19002 operands
[3] = GEN_INT (31 - nb
);
19003 operands
[4] = GEN_INT (31 - ne
);
19005 return "rlwimi. %0,%1,%2,%3,%4";
19006 return "rlwimi %0,%1,%2,%3,%4";
19009 gcc_unreachable ();
19012 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19013 using two machine instructions. */
19016 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
19018 /* There are two kinds of AND we can handle with two insns:
19019 1) those we can do with two rl* insn;
19022 We do not handle that last case yet. */
19024 /* If there is just one stretch of ones, we can do it. */
19025 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
19028 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19029 one insn, we can do the whole thing with two. */
19030 unsigned HOST_WIDE_INT val
= INTVAL (c
);
19031 unsigned HOST_WIDE_INT bit1
= val
& -val
;
19032 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
19033 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
19034 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
19035 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
19038 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19039 If EXPAND is true, split rotate-and-mask instructions we generate to
19040 their constituent parts as well (this is used during expand); if DOT
19041 is 1, make the last insn a record-form instruction clobbering the
19042 destination GPR and setting the CC reg (from operands[3]); if 2, set
19043 that GPR as well as the CC reg. */
19046 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
19048 gcc_assert (!(expand
&& dot
));
19050 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
19052 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19053 shift right. This generates better code than doing the masks without
19054 shifts, or shifting first right and then left. */
19056 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
19058 gcc_assert (mode
== DImode
);
19060 int shift
= 63 - nb
;
19063 rtx tmp1
= gen_reg_rtx (DImode
);
19064 rtx tmp2
= gen_reg_rtx (DImode
);
19065 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
19066 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
19067 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
19071 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
19072 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
19073 emit_move_insn (operands
[0], tmp
);
19074 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
19075 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
19080 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19081 that does the rest. */
19082 unsigned HOST_WIDE_INT bit1
= val
& -val
;
19083 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
19084 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
19085 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
19087 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
19088 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
19090 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
19092 /* Two "no-rotate"-and-mask instructions, for SImode. */
19093 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
19095 gcc_assert (mode
== SImode
);
19097 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
19098 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
19099 emit_move_insn (reg
, tmp
);
19100 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
19101 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
19105 gcc_assert (mode
== DImode
);
19107 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
19108 insns; we have to do the first in SImode, because it wraps. */
19109 if (mask2
<= 0xffffffff
19110 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
19112 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
19113 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
19115 rtx reg_low
= gen_lowpart (SImode
, reg
);
19116 emit_move_insn (reg_low
, tmp
);
19117 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
19118 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
19122 /* Two rld* insns: rotate, clear the hole in the middle (which now is
19123 at the top end), rotate back and clear the other hole. */
19124 int right
= exact_log2 (bit3
);
19125 int left
= 64 - right
;
19127 /* Rotate the mask too. */
19128 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
19132 rtx tmp1
= gen_reg_rtx (DImode
);
19133 rtx tmp2
= gen_reg_rtx (DImode
);
19134 rtx tmp3
= gen_reg_rtx (DImode
);
19135 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
19136 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
19137 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
19138 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
19142 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
19143 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
19144 emit_move_insn (operands
[0], tmp
);
19145 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
19146 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
19147 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
19151 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
19152 for lfq and stfq insns iff the registers are hard registers. */
19155 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
19157 /* We might have been passed a SUBREG. */
19158 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
19161 /* We might have been passed non floating point registers. */
19162 if (!FP_REGNO_P (REGNO (reg1
))
19163 || !FP_REGNO_P (REGNO (reg2
)))
19166 return (REGNO (reg1
) == REGNO (reg2
) - 1);
19169 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
19170 addr1 and addr2 must be in consecutive memory locations
19171 (addr2 == addr1 + 8). */
19174 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
19177 unsigned int reg1
, reg2
;
19178 int offset1
, offset2
;
19180 /* The mems cannot be volatile. */
19181 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
19184 addr1
= XEXP (mem1
, 0);
19185 addr2
= XEXP (mem2
, 0);
19187 /* Extract an offset (if used) from the first addr. */
19188 if (GET_CODE (addr1
) == PLUS
)
19190 /* If not a REG, return zero. */
19191 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
19195 reg1
= REGNO (XEXP (addr1
, 0));
19196 /* The offset must be constant! */
19197 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
19199 offset1
= INTVAL (XEXP (addr1
, 1));
19202 else if (GET_CODE (addr1
) != REG
)
19206 reg1
= REGNO (addr1
);
19207 /* This was a simple (mem (reg)) expression. Offset is 0. */
19211 /* And now for the second addr. */
19212 if (GET_CODE (addr2
) == PLUS
)
19214 /* If not a REG, return zero. */
19215 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
19219 reg2
= REGNO (XEXP (addr2
, 0));
19220 /* The offset must be constant. */
19221 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
19223 offset2
= INTVAL (XEXP (addr2
, 1));
19226 else if (GET_CODE (addr2
) != REG
)
19230 reg2
= REGNO (addr2
);
19231 /* This was a simple (mem (reg)) expression. Offset is 0. */
19235 /* Both of these must have the same base register. */
19239 /* The offset for the second addr must be 8 more than the first addr. */
19240 if (offset2
!= offset1
+ 8)
19243 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19248 /* Return the mode to be used for memory when a secondary memory
19249 location is needed. For SDmode values we need to use DDmode, in
19250 all other cases we can use the same mode. */
19252 rs6000_secondary_memory_needed_mode (machine_mode mode
)
19254 if (lra_in_progress
&& mode
== SDmode
)
19259 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19260 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19261 only work on the traditional altivec registers, note if an altivec register
19264 static enum rs6000_reg_type
19265 register_to_reg_type (rtx reg
, bool *is_altivec
)
19267 HOST_WIDE_INT regno
;
19268 enum reg_class rclass
;
19270 if (GET_CODE (reg
) == SUBREG
)
19271 reg
= SUBREG_REG (reg
);
19274 return NO_REG_TYPE
;
19276 regno
= REGNO (reg
);
19277 if (regno
>= FIRST_PSEUDO_REGISTER
)
19279 if (!lra_in_progress
&& !reload_completed
)
19280 return PSEUDO_REG_TYPE
;
19282 regno
= true_regnum (reg
);
19283 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
19284 return PSEUDO_REG_TYPE
;
19287 gcc_assert (regno
>= 0);
19289 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
19290 *is_altivec
= true;
19292 rclass
= rs6000_regno_regclass
[regno
];
19293 return reg_class_to_reg_type
[(int)rclass
];
19296 /* Helper function to return the cost of adding a TOC entry address. */
19299 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
19303 if (TARGET_CMODEL
!= CMODEL_SMALL
)
19304 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
19307 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
19312 /* Helper function for rs6000_secondary_reload to determine whether the memory
19313 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19314 needs reloading. Return negative if the memory is not handled by the memory
19315 helper functions and to try a different reload method, 0 if no additional
19316 instructions are need, and positive to give the extra cost for the
19320 rs6000_secondary_reload_memory (rtx addr
,
19321 enum reg_class rclass
,
19324 int extra_cost
= 0;
19325 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
19326 addr_mask_type addr_mask
;
19327 const char *type
= NULL
;
19328 const char *fail_msg
= NULL
;
19330 if (GPR_REG_CLASS_P (rclass
))
19331 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
19333 else if (rclass
== FLOAT_REGS
)
19334 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
19336 else if (rclass
== ALTIVEC_REGS
)
19337 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
19339 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19340 else if (rclass
== VSX_REGS
)
19341 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
19342 & ~RELOAD_REG_AND_M16
);
19344 /* If the register allocator hasn't made up its mind yet on the register
19345 class to use, settle on defaults to use. */
19346 else if (rclass
== NO_REGS
)
19348 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
]
19349 & ~RELOAD_REG_AND_M16
);
19351 if ((addr_mask
& RELOAD_REG_MULTIPLE
) != 0)
19352 addr_mask
&= ~(RELOAD_REG_INDEXED
19353 | RELOAD_REG_PRE_INCDEC
19354 | RELOAD_REG_PRE_MODIFY
);
19360 /* If the register isn't valid in this register class, just return now. */
19361 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
19363 if (TARGET_DEBUG_ADDR
)
19366 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19367 "not valid in class\n",
19368 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
19375 switch (GET_CODE (addr
))
19377 /* Does the register class supports auto update forms for this mode? We
19378 don't need a scratch register, since the powerpc only supports
19379 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19382 reg
= XEXP (addr
, 0);
19383 if (!base_reg_operand (addr
, GET_MODE (reg
)))
19385 fail_msg
= "no base register #1";
19389 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
19397 reg
= XEXP (addr
, 0);
19398 plus_arg1
= XEXP (addr
, 1);
19399 if (!base_reg_operand (reg
, GET_MODE (reg
))
19400 || GET_CODE (plus_arg1
) != PLUS
19401 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
19403 fail_msg
= "bad PRE_MODIFY";
19407 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
19414 /* Do we need to simulate AND -16 to clear the bottom address bits used
19415 in VMX load/stores? Only allow the AND for vector sizes. */
19417 and_arg
= XEXP (addr
, 0);
19418 if (GET_MODE_SIZE (mode
) != 16
19419 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
19420 || INTVAL (XEXP (addr
, 1)) != -16)
19422 fail_msg
= "bad Altivec AND #1";
19426 if (rclass
!= ALTIVEC_REGS
)
19428 if (legitimate_indirect_address_p (and_arg
, false))
19431 else if (legitimate_indexed_address_p (and_arg
, false))
19436 fail_msg
= "bad Altivec AND #2";
19444 /* If this is an indirect address, make sure it is a base register. */
19447 if (!legitimate_indirect_address_p (addr
, false))
19454 /* If this is an indexed address, make sure the register class can handle
19455 indexed addresses for this mode. */
19457 plus_arg0
= XEXP (addr
, 0);
19458 plus_arg1
= XEXP (addr
, 1);
19460 /* (plus (plus (reg) (constant)) (constant)) is generated during
19461 push_reload processing, so handle it now. */
19462 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
19464 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19471 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19472 push_reload processing, so handle it now. */
19473 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
19475 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19478 type
= "indexed #2";
19482 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
19484 fail_msg
= "no base register #2";
19488 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
19490 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
19491 || !legitimate_indexed_address_p (addr
, false))
19498 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0
19499 && CONST_INT_P (plus_arg1
))
19501 if (!quad_address_offset_p (INTVAL (plus_arg1
)))
19504 type
= "vector d-form offset";
19508 /* Make sure the register class can handle offset addresses. */
19509 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
19511 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19514 type
= "offset #2";
19520 fail_msg
= "bad PLUS";
19527 /* Quad offsets are restricted and can't handle normal addresses. */
19528 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19531 type
= "vector d-form lo_sum";
19534 else if (!legitimate_lo_sum_address_p (mode
, addr
, false))
19536 fail_msg
= "bad LO_SUM";
19540 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19547 /* Static addresses need to create a TOC entry. */
19551 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19554 type
= "vector d-form lo_sum #2";
19560 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
19564 /* TOC references look like offsetable memory. */
19566 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
19568 fail_msg
= "bad UNSPEC";
19572 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19575 type
= "vector d-form lo_sum #3";
19578 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19581 type
= "toc reference";
19587 fail_msg
= "bad address";
19592 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
19594 if (extra_cost
< 0)
19596 "rs6000_secondary_reload_memory error: mode = %s, "
19597 "class = %s, addr_mask = '%s', %s\n",
19598 GET_MODE_NAME (mode
),
19599 reg_class_names
[rclass
],
19600 rs6000_debug_addr_mask (addr_mask
, false),
19601 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
19605 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19606 "addr_mask = '%s', extra cost = %d, %s\n",
19607 GET_MODE_NAME (mode
),
19608 reg_class_names
[rclass
],
19609 rs6000_debug_addr_mask (addr_mask
, false),
19611 (type
) ? type
: "<none>");
19619 /* Helper function for rs6000_secondary_reload to return true if a move to a
19620 different register classe is really a simple move. */
19623 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
19624 enum rs6000_reg_type from_type
,
19627 int size
= GET_MODE_SIZE (mode
);
19629 /* Add support for various direct moves available. In this function, we only
19630 look at cases where we don't need any extra registers, and one or more
19631 simple move insns are issued. Originally small integers are not allowed
19632 in FPR/VSX registers. Single precision binary floating is not a simple
19633 move because we need to convert to the single precision memory layout.
19634 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19635 need special direct move handling, which we do not support yet. */
19636 if (TARGET_DIRECT_MOVE
19637 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19638 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19640 if (TARGET_POWERPC64
)
19642 /* ISA 2.07: MTVSRD or MVFVSRD. */
19646 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19647 if (size
== 16 && TARGET_P9_VECTOR
&& mode
!= TDmode
)
19651 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19652 if (TARGET_P8_VECTOR
)
19654 if (mode
== SImode
)
19657 if (TARGET_P9_VECTOR
&& (mode
== HImode
|| mode
== QImode
))
19661 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19662 if (mode
== SDmode
)
19666 /* Power6+: MFTGPR or MFFGPR. */
19667 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
19668 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
19669 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19672 /* Move to/from SPR. */
19673 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
19674 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
19675 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19681 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19682 special direct moves that involve allocating an extra register, return the
19683 insn code of the helper function if there is such a function or
19684 CODE_FOR_nothing if not. */
19687 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
19688 enum rs6000_reg_type from_type
,
19690 secondary_reload_info
*sri
,
19694 enum insn_code icode
= CODE_FOR_nothing
;
19696 int size
= GET_MODE_SIZE (mode
);
19698 if (TARGET_POWERPC64
&& size
== 16)
19700 /* Handle moving 128-bit values from GPRs to VSX point registers on
19701 ISA 2.07 (power8, power9) when running in 64-bit mode using
19702 XXPERMDI to glue the two 64-bit values back together. */
19703 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19705 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
19706 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19709 /* Handle moving 128-bit values from VSX point registers to GPRs on
19710 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19711 bottom 64-bit value. */
19712 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19714 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
19715 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19719 else if (TARGET_POWERPC64
&& mode
== SFmode
)
19721 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19723 cost
= 3; /* xscvdpspn, mfvsrd, and. */
19724 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19727 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19729 cost
= 2; /* mtvsrz, xscvspdpn. */
19730 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19734 else if (!TARGET_POWERPC64
&& size
== 8)
19736 /* Handle moving 64-bit values from GPRs to floating point registers on
19737 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19738 32-bit values back together. Altivec register classes must be handled
19739 specially since a different instruction is used, and the secondary
19740 reload support requires a single instruction class in the scratch
19741 register constraint. However, right now TFmode is not allowed in
19742 Altivec registers, so the pattern will never match. */
19743 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
19745 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
19746 icode
= reg_addr
[mode
].reload_fpr_gpr
;
19750 if (icode
!= CODE_FOR_nothing
)
19755 sri
->icode
= icode
;
19756 sri
->extra_cost
= cost
;
19763 /* Return whether a move between two register classes can be done either
19764 directly (simple move) or via a pattern that uses a single extra temporary
19765 (using ISA 2.07's direct move in this case. */
19768 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
19769 enum rs6000_reg_type from_type
,
19771 secondary_reload_info
*sri
,
19774 /* Fall back to load/store reloads if either type is not a register. */
19775 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
19778 /* If we haven't allocated registers yet, assume the move can be done for the
19779 standard register types. */
19780 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
19781 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
19782 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
19785 /* Moves to the same set of registers is a simple move for non-specialized
19787 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
19790 /* Check whether a simple move can be done directly. */
19791 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
19795 sri
->icode
= CODE_FOR_nothing
;
19796 sri
->extra_cost
= 0;
19801 /* Now check if we can do it in a few steps. */
19802 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
19806 /* Inform reload about cases where moving X with a mode MODE to a register in
19807 RCLASS requires an extra scratch or immediate register. Return the class
19808 needed for the immediate register.
19810 For VSX and Altivec, we may need a register to convert sp+offset into
19813 For misaligned 64-bit gpr loads and stores we need a register to
19814 convert an offset address to indirect. */
19817 rs6000_secondary_reload (bool in_p
,
19819 reg_class_t rclass_i
,
19821 secondary_reload_info
*sri
)
19823 enum reg_class rclass
= (enum reg_class
) rclass_i
;
19824 reg_class_t ret
= ALL_REGS
;
19825 enum insn_code icode
;
19826 bool default_p
= false;
19827 bool done_p
= false;
19829 /* Allow subreg of memory before/during reload. */
19830 bool memory_p
= (MEM_P (x
)
19831 || (!reload_completed
&& GET_CODE (x
) == SUBREG
19832 && MEM_P (SUBREG_REG (x
))));
19834 sri
->icode
= CODE_FOR_nothing
;
19835 sri
->t_icode
= CODE_FOR_nothing
;
19836 sri
->extra_cost
= 0;
19838 ? reg_addr
[mode
].reload_load
19839 : reg_addr
[mode
].reload_store
);
19841 if (REG_P (x
) || register_operand (x
, mode
))
19843 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
19844 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
19845 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
19848 std::swap (to_type
, from_type
);
19850 /* Can we do a direct move of some sort? */
19851 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
19854 icode
= (enum insn_code
)sri
->icode
;
19861 /* Make sure 0.0 is not reloaded or forced into memory. */
19862 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
19869 /* If this is a scalar floating point value and we want to load it into the
19870 traditional Altivec registers, do it via a move via a traditional floating
19871 point register, unless we have D-form addressing. Also make sure that
19872 non-zero constants use a FPR. */
19873 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
19874 && !mode_supports_vmx_dform (mode
)
19875 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
19876 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
19883 /* Handle reload of load/stores if we have reload helper functions. */
19884 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
19886 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
19889 if (extra_cost
>= 0)
19893 if (extra_cost
> 0)
19895 sri
->extra_cost
= extra_cost
;
19896 sri
->icode
= icode
;
19901 /* Handle unaligned loads and stores of integer registers. */
19902 if (!done_p
&& TARGET_POWERPC64
19903 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19905 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
19907 rtx addr
= XEXP (x
, 0);
19908 rtx off
= address_offset (addr
);
19910 if (off
!= NULL_RTX
)
19912 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19913 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19915 /* We need a secondary reload when our legitimate_address_p
19916 says the address is good (as otherwise the entire address
19917 will be reloaded), and the offset is not a multiple of
19918 four or we have an address wrap. Address wrap will only
19919 occur for LO_SUMs since legitimate_offset_address_p
19920 rejects addresses for 16-byte mems that will wrap. */
19921 if (GET_CODE (addr
) == LO_SUM
19922 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19923 && ((offset
& 3) != 0
19924 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
19925 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
19926 && (offset
& 3) != 0))
19928 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19930 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
19931 : CODE_FOR_reload_di_load
);
19933 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
19934 : CODE_FOR_reload_di_store
);
19935 sri
->extra_cost
= 2;
19946 if (!done_p
&& !TARGET_POWERPC64
19947 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19949 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
19951 rtx addr
= XEXP (x
, 0);
19952 rtx off
= address_offset (addr
);
19954 if (off
!= NULL_RTX
)
19956 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19957 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19959 /* We need a secondary reload when our legitimate_address_p
19960 says the address is good (as otherwise the entire address
19961 will be reloaded), and we have a wrap.
19963 legitimate_lo_sum_address_p allows LO_SUM addresses to
19964 have any offset so test for wrap in the low 16 bits.
19966 legitimate_offset_address_p checks for the range
19967 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19968 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19969 [0x7ff4,0x7fff] respectively, so test for the
19970 intersection of these ranges, [0x7ffc,0x7fff] and
19971 [0x7ff4,0x7ff7] respectively.
19973 Note that the address we see here may have been
19974 manipulated by legitimize_reload_address. */
19975 if (GET_CODE (addr
) == LO_SUM
19976 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
19977 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
19980 sri
->icode
= CODE_FOR_reload_si_load
;
19982 sri
->icode
= CODE_FOR_reload_si_store
;
19983 sri
->extra_cost
= 2;
19998 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
20000 gcc_assert (ret
!= ALL_REGS
);
20002 if (TARGET_DEBUG_ADDR
)
20005 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20007 reg_class_names
[ret
],
20008 in_p
? "true" : "false",
20009 reg_class_names
[rclass
],
20010 GET_MODE_NAME (mode
));
20012 if (reload_completed
)
20013 fputs (", after reload", stderr
);
20016 fputs (", done_p not set", stderr
);
20019 fputs (", default secondary reload", stderr
);
20021 if (sri
->icode
!= CODE_FOR_nothing
)
20022 fprintf (stderr
, ", reload func = %s, extra cost = %d",
20023 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
20025 else if (sri
->extra_cost
> 0)
20026 fprintf (stderr
, ", extra cost = %d", sri
->extra_cost
);
20028 fputs ("\n", stderr
);
20035 /* Better tracing for rs6000_secondary_reload_inner. */
20038 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
20043 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
20045 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
20046 store_p
? "store" : "load");
20049 set
= gen_rtx_SET (mem
, reg
);
20051 set
= gen_rtx_SET (reg
, mem
);
20053 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
20054 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
20057 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
20058 ATTRIBUTE_NORETURN
;
20061 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
20064 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
20065 gcc_unreachable ();
20068 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
20069 reload helper functions. These were identified in
20070 rs6000_secondary_reload_memory, and if reload decided to use the secondary
20071 reload, it calls the insns:
20072 reload_<RELOAD:mode>_<P:mptrsize>_store
20073 reload_<RELOAD:mode>_<P:mptrsize>_load
20075 which in turn calls this function, to do whatever is necessary to create
20076 valid addresses. */
20079 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
20081 int regno
= true_regnum (reg
);
20082 machine_mode mode
= GET_MODE (reg
);
20083 addr_mask_type addr_mask
;
20086 rtx op_reg
, op0
, op1
;
20091 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
20092 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
20093 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20095 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
20096 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
20098 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
20099 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
20101 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
20102 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
20105 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20107 /* Make sure the mode is valid in this register class. */
20108 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
20109 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20111 if (TARGET_DEBUG_ADDR
)
20112 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
20114 new_addr
= addr
= XEXP (mem
, 0);
20115 switch (GET_CODE (addr
))
20117 /* Does the register class support auto update forms for this mode? If
20118 not, do the update now. We don't need a scratch register, since the
20119 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
20122 op_reg
= XEXP (addr
, 0);
20123 if (!base_reg_operand (op_reg
, Pmode
))
20124 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20126 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
20128 emit_insn (gen_add2_insn (op_reg
, GEN_INT (GET_MODE_SIZE (mode
))));
20134 op0
= XEXP (addr
, 0);
20135 op1
= XEXP (addr
, 1);
20136 if (!base_reg_operand (op0
, Pmode
)
20137 || GET_CODE (op1
) != PLUS
20138 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
20139 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20141 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
20143 emit_insn (gen_rtx_SET (op0
, op1
));
20148 /* Do we need to simulate AND -16 to clear the bottom address bits used
20149 in VMX load/stores? */
20151 op0
= XEXP (addr
, 0);
20152 op1
= XEXP (addr
, 1);
20153 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
20155 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
20158 else if (GET_CODE (op1
) == PLUS
)
20160 emit_insn (gen_rtx_SET (scratch
, op1
));
20165 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20167 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
20168 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
20169 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
20170 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
20171 new_addr
= scratch
;
20175 /* If this is an indirect address, make sure it is a base register. */
20178 if (!base_reg_operand (addr
, GET_MODE (addr
)))
20180 emit_insn (gen_rtx_SET (scratch
, addr
));
20181 new_addr
= scratch
;
20185 /* If this is an indexed address, make sure the register class can handle
20186 indexed addresses for this mode. */
20188 op0
= XEXP (addr
, 0);
20189 op1
= XEXP (addr
, 1);
20190 if (!base_reg_operand (op0
, Pmode
))
20191 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20193 else if (int_reg_operand (op1
, Pmode
))
20195 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
20197 emit_insn (gen_rtx_SET (scratch
, addr
));
20198 new_addr
= scratch
;
20202 else if (mode_supports_vsx_dform_quad (mode
) && CONST_INT_P (op1
))
20204 if (((addr_mask
& RELOAD_REG_QUAD_OFFSET
) == 0)
20205 || !quad_address_p (addr
, mode
, false))
20207 emit_insn (gen_rtx_SET (scratch
, addr
));
20208 new_addr
= scratch
;
20212 /* Make sure the register class can handle offset addresses. */
20213 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
20215 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20217 emit_insn (gen_rtx_SET (scratch
, addr
));
20218 new_addr
= scratch
;
20223 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20228 op0
= XEXP (addr
, 0);
20229 op1
= XEXP (addr
, 1);
20230 if (!base_reg_operand (op0
, Pmode
))
20231 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20233 else if (int_reg_operand (op1
, Pmode
))
20235 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
20237 emit_insn (gen_rtx_SET (scratch
, addr
));
20238 new_addr
= scratch
;
20242 /* Quad offsets are restricted and can't handle normal addresses. */
20243 else if (mode_supports_vsx_dform_quad (mode
))
20245 emit_insn (gen_rtx_SET (scratch
, addr
));
20246 new_addr
= scratch
;
20249 /* Make sure the register class can handle offset addresses. */
20250 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
20252 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20254 emit_insn (gen_rtx_SET (scratch
, addr
));
20255 new_addr
= scratch
;
20260 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20267 rs6000_emit_move (scratch
, addr
, Pmode
);
20268 new_addr
= scratch
;
20272 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20275 /* Adjust the address if it changed. */
20276 if (addr
!= new_addr
)
20278 mem
= replace_equiv_address_nv (mem
, new_addr
);
20279 if (TARGET_DEBUG_ADDR
)
20280 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20283 /* Now create the move. */
20285 emit_insn (gen_rtx_SET (mem
, reg
));
20287 emit_insn (gen_rtx_SET (reg
, mem
));
20292 /* Convert reloads involving 64-bit gprs and misaligned offset
20293 addressing, or multiple 32-bit gprs and offsets that are too large,
20294 to use indirect addressing. */
20297 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
20299 int regno
= true_regnum (reg
);
20300 enum reg_class rclass
;
20302 rtx scratch_or_premodify
= scratch
;
20304 if (TARGET_DEBUG_ADDR
)
20306 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
20307 store_p
? "store" : "load");
20308 fprintf (stderr
, "reg:\n");
20310 fprintf (stderr
, "mem:\n");
20312 fprintf (stderr
, "scratch:\n");
20313 debug_rtx (scratch
);
20316 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
20317 gcc_assert (GET_CODE (mem
) == MEM
);
20318 rclass
= REGNO_REG_CLASS (regno
);
20319 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
20320 addr
= XEXP (mem
, 0);
20322 if (GET_CODE (addr
) == PRE_MODIFY
)
20324 gcc_assert (REG_P (XEXP (addr
, 0))
20325 && GET_CODE (XEXP (addr
, 1)) == PLUS
20326 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
20327 scratch_or_premodify
= XEXP (addr
, 0);
20328 if (!HARD_REGISTER_P (scratch_or_premodify
))
20329 /* If we have a pseudo here then reload will have arranged
20330 to have it replaced, but only in the original insn.
20331 Use the replacement here too. */
20332 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
20334 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
20335 expressions from the original insn, without unsharing them.
20336 Any RTL that points into the original insn will of course
20337 have register replacements applied. That is why we don't
20338 need to look for replacements under the PLUS. */
20339 addr
= XEXP (addr
, 1);
20341 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
20343 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
20345 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
20347 /* Now create the move. */
20349 emit_insn (gen_rtx_SET (mem
, reg
));
20351 emit_insn (gen_rtx_SET (reg
, mem
));
20356 /* Given an rtx X being reloaded into a reg required to be
20357 in class CLASS, return the class of reg to actually use.
20358 In general this is just CLASS; but on some machines
20359 in some cases it is preferable to use a more restrictive class.
20361 On the RS/6000, we have to return NO_REGS when we want to reload a
20362 floating-point CONST_DOUBLE to force it to be copied to memory.
20364 We also don't want to reload integer values into floating-point
20365 registers if we can at all help it. In fact, this can
20366 cause reload to die, if it tries to generate a reload of CTR
20367 into a FP register and discovers it doesn't have the memory location
20370 ??? Would it be a good idea to have reload do the converse, that is
20371 try to reload floating modes into FP registers if possible?
20374 static enum reg_class
20375 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
20377 machine_mode mode
= GET_MODE (x
);
20378 bool is_constant
= CONSTANT_P (x
);
20380 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20381 reload class for it. */
20382 if ((rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
20383 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
) == 0)
20386 if ((rclass
== FLOAT_REGS
|| rclass
== VSX_REGS
)
20387 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
] & RELOAD_REG_VALID
) == 0)
20390 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20391 the reloading of address expressions using PLUS into floating point
20393 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
20397 /* Zero is always allowed in all VSX registers. */
20398 if (x
== CONST0_RTX (mode
))
20401 /* If this is a vector constant that can be formed with a few Altivec
20402 instructions, we want altivec registers. */
20403 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
20404 return ALTIVEC_REGS
;
20406 /* If this is an integer constant that can easily be loaded into
20407 vector registers, allow it. */
20408 if (CONST_INT_P (x
))
20410 HOST_WIDE_INT value
= INTVAL (x
);
20412 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20413 2.06 can generate it in the Altivec registers with
20417 if (TARGET_P8_VECTOR
)
20419 else if (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
20420 return ALTIVEC_REGS
;
20425 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20426 a sign extend in the Altivec registers. */
20427 if (IN_RANGE (value
, -128, 127) && TARGET_P9_VECTOR
20428 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
))
20429 return ALTIVEC_REGS
;
20432 /* Force constant to memory. */
20436 /* D-form addressing can easily reload the value. */
20437 if (mode_supports_vmx_dform (mode
)
20438 || mode_supports_vsx_dform_quad (mode
))
20441 /* If this is a scalar floating point value and we don't have D-form
20442 addressing, prefer the traditional floating point registers so that we
20443 can use D-form (register+offset) addressing. */
20444 if (rclass
== VSX_REGS
20445 && (mode
== SFmode
|| GET_MODE_SIZE (mode
) == 8))
20448 /* Prefer the Altivec registers if Altivec is handling the vector
20449 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20451 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
20452 || mode
== V1TImode
)
20453 return ALTIVEC_REGS
;
20458 if (is_constant
|| GET_CODE (x
) == PLUS
)
20460 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
20461 return GENERAL_REGS
;
20462 if (reg_class_subset_p (BASE_REGS
, rclass
))
20467 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
20468 return GENERAL_REGS
;
20473 /* Debug version of rs6000_preferred_reload_class. */
20474 static enum reg_class
20475 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
20477 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
20480 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20482 reg_class_names
[ret
], reg_class_names
[rclass
],
20483 GET_MODE_NAME (GET_MODE (x
)));
20489 /* If we are copying between FP or AltiVec registers and anything else, we need
20490 a memory location. The exception is when we are targeting ppc64 and the
20491 move to/from fpr to gpr instructions are available. Also, under VSX, you
20492 can copy vector registers from the FP register set to the Altivec register
20493 set and vice versa. */
20496 rs6000_secondary_memory_needed (enum reg_class from_class
,
20497 enum reg_class to_class
,
20500 enum rs6000_reg_type from_type
, to_type
;
20501 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
20502 || (to_class
== ALTIVEC_REGS
));
20504 /* If a simple/direct move is available, we don't need secondary memory */
20505 from_type
= reg_class_to_reg_type
[(int)from_class
];
20506 to_type
= reg_class_to_reg_type
[(int)to_class
];
20508 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
20509 (secondary_reload_info
*)0, altivec_p
))
20512 /* If we have a floating point or vector register class, we need to use
20513 memory to transfer the data. */
20514 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
20520 /* Debug version of rs6000_secondary_memory_needed. */
20522 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
20523 enum reg_class to_class
,
20526 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
20529 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20530 "to_class = %s, mode = %s\n",
20531 ret
? "true" : "false",
20532 reg_class_names
[from_class
],
20533 reg_class_names
[to_class
],
20534 GET_MODE_NAME (mode
));
20539 /* Return the register class of a scratch register needed to copy IN into
20540 or out of a register in RCLASS in MODE. If it can be done directly,
20541 NO_REGS is returned. */
20543 static enum reg_class
20544 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
20549 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
20551 && MACHOPIC_INDIRECT
20555 /* We cannot copy a symbolic operand directly into anything
20556 other than BASE_REGS for TARGET_ELF. So indicate that a
20557 register from BASE_REGS is needed as an intermediate
20560 On Darwin, pic addresses require a load from memory, which
20561 needs a base register. */
20562 if (rclass
!= BASE_REGS
20563 && (GET_CODE (in
) == SYMBOL_REF
20564 || GET_CODE (in
) == HIGH
20565 || GET_CODE (in
) == LABEL_REF
20566 || GET_CODE (in
) == CONST
))
20570 if (GET_CODE (in
) == REG
)
20572 regno
= REGNO (in
);
20573 if (regno
>= FIRST_PSEUDO_REGISTER
)
20575 regno
= true_regnum (in
);
20576 if (regno
>= FIRST_PSEUDO_REGISTER
)
20580 else if (GET_CODE (in
) == SUBREG
)
20582 regno
= true_regnum (in
);
20583 if (regno
>= FIRST_PSEUDO_REGISTER
)
20589 /* If we have VSX register moves, prefer moving scalar values between
20590 Altivec registers and GPR by going via an FPR (and then via memory)
20591 instead of reloading the secondary memory address for Altivec moves. */
20593 && GET_MODE_SIZE (mode
) < 16
20594 && !mode_supports_vmx_dform (mode
)
20595 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
20596 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
20597 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
20598 && (regno
>= 0 && INT_REGNO_P (regno
)))))
20601 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20603 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
20604 || (regno
>= 0 && INT_REGNO_P (regno
)))
20607 /* Constants, memory, and VSX registers can go into VSX registers (both the
20608 traditional floating point and the altivec registers). */
20609 if (rclass
== VSX_REGS
20610 && (regno
== -1 || VSX_REGNO_P (regno
)))
20613 /* Constants, memory, and FP registers can go into FP registers. */
20614 if ((regno
== -1 || FP_REGNO_P (regno
))
20615 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
20616 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
20618 /* Memory, and AltiVec registers can go into AltiVec registers. */
20619 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
20620 && rclass
== ALTIVEC_REGS
)
20623 /* We can copy among the CR registers. */
20624 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
20625 && regno
>= 0 && CR_REGNO_P (regno
))
20628 /* Otherwise, we need GENERAL_REGS. */
20629 return GENERAL_REGS
;
20632 /* Debug version of rs6000_secondary_reload_class. */
20633 static enum reg_class
20634 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
20635 machine_mode mode
, rtx in
)
20637 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
20639 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20640 "mode = %s, input rtx:\n",
20641 reg_class_names
[ret
], reg_class_names
[rclass
],
20642 GET_MODE_NAME (mode
));
20648 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
20651 rs6000_cannot_change_mode_class (machine_mode from
,
20653 enum reg_class rclass
)
20655 unsigned from_size
= GET_MODE_SIZE (from
);
20656 unsigned to_size
= GET_MODE_SIZE (to
);
20658 if (from_size
!= to_size
)
20660 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
20662 if (reg_classes_intersect_p (xclass
, rclass
))
20664 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
20665 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
20666 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
20667 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
20669 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20670 single register under VSX because the scalar part of the register
20671 is in the upper 64-bits, and not the lower 64-bits. Types like
20672 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20673 IEEE floating point can't overlap, and neither can small
20676 if (to_float128_vector_p
&& from_float128_vector_p
)
20679 else if (to_float128_vector_p
|| from_float128_vector_p
)
20682 /* TDmode in floating-mode registers must always go into a register
20683 pair with the most significant word in the even-numbered register
20684 to match ISA requirements. In little-endian mode, this does not
20685 match subreg numbering, so we cannot allow subregs. */
20686 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
20689 if (from_size
< 8 || to_size
< 8)
20692 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
20695 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
20704 /* Since the VSX register set includes traditional floating point registers
20705 and altivec registers, just check for the size being different instead of
20706 trying to check whether the modes are vector modes. Otherwise it won't
20707 allow say DF and DI to change classes. For types like TFmode and TDmode
20708 that take 2 64-bit registers, rather than a single 128-bit register, don't
20709 allow subregs of those types to other 128 bit types. */
20710 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
20712 unsigned num_regs
= (from_size
+ 15) / 16;
20713 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
20714 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
20717 return (from_size
!= 8 && from_size
!= 16);
20720 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
20721 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
20727 /* Debug version of rs6000_cannot_change_mode_class. */
20729 rs6000_debug_cannot_change_mode_class (machine_mode from
,
20731 enum reg_class rclass
)
20733 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
20736 "rs6000_cannot_change_mode_class, return %s, from = %s, "
20737 "to = %s, rclass = %s\n",
20738 ret
? "true" : "false",
20739 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
20740 reg_class_names
[rclass
]);
20745 /* Return a string to do a move operation of 128 bits of data. */
20748 rs6000_output_move_128bit (rtx operands
[])
20750 rtx dest
= operands
[0];
20751 rtx src
= operands
[1];
20752 machine_mode mode
= GET_MODE (dest
);
20755 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
20756 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
20760 dest_regno
= REGNO (dest
);
20761 dest_gpr_p
= INT_REGNO_P (dest_regno
);
20762 dest_fp_p
= FP_REGNO_P (dest_regno
);
20763 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
20764 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
20769 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
20774 src_regno
= REGNO (src
);
20775 src_gpr_p
= INT_REGNO_P (src_regno
);
20776 src_fp_p
= FP_REGNO_P (src_regno
);
20777 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
20778 src_vsx_p
= src_fp_p
| src_vmx_p
;
20783 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
20786 /* Register moves. */
20787 if (dest_regno
>= 0 && src_regno
>= 0)
20794 if (TARGET_DIRECT_MOVE_128
&& src_vsx_p
)
20795 return (WORDS_BIG_ENDIAN
20796 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20797 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20799 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
20803 else if (TARGET_VSX
&& dest_vsx_p
)
20806 return "xxlor %x0,%x1,%x1";
20808 else if (TARGET_DIRECT_MOVE_128
&& src_gpr_p
)
20809 return (WORDS_BIG_ENDIAN
20810 ? "mtvsrdd %x0,%1,%L1"
20811 : "mtvsrdd %x0,%L1,%1");
20813 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
20817 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
20818 return "vor %0,%1,%1";
20820 else if (dest_fp_p
&& src_fp_p
)
20825 else if (dest_regno
>= 0 && MEM_P (src
))
20829 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20835 else if (TARGET_ALTIVEC
&& dest_vmx_p
20836 && altivec_indexed_or_indirect_operand (src
, mode
))
20837 return "lvx %0,%y1";
20839 else if (TARGET_VSX
&& dest_vsx_p
)
20841 if (mode_supports_vsx_dform_quad (mode
)
20842 && quad_address_p (XEXP (src
, 0), mode
, true))
20843 return "lxv %x0,%1";
20845 else if (TARGET_P9_VECTOR
)
20846 return "lxvx %x0,%y1";
20848 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20849 return "lxvw4x %x0,%y1";
20852 return "lxvd2x %x0,%y1";
20855 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
20856 return "lvx %0,%y1";
20858 else if (dest_fp_p
)
20863 else if (src_regno
>= 0 && MEM_P (dest
))
20867 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20868 return "stq %1,%0";
20873 else if (TARGET_ALTIVEC
&& src_vmx_p
20874 && altivec_indexed_or_indirect_operand (src
, mode
))
20875 return "stvx %1,%y0";
20877 else if (TARGET_VSX
&& src_vsx_p
)
20879 if (mode_supports_vsx_dform_quad (mode
)
20880 && quad_address_p (XEXP (dest
, 0), mode
, true))
20881 return "stxv %x1,%0";
20883 else if (TARGET_P9_VECTOR
)
20884 return "stxvx %x1,%y0";
20886 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20887 return "stxvw4x %x1,%y0";
20890 return "stxvd2x %x1,%y0";
20893 else if (TARGET_ALTIVEC
&& src_vmx_p
)
20894 return "stvx %1,%y0";
20901 else if (dest_regno
>= 0
20902 && (GET_CODE (src
) == CONST_INT
20903 || GET_CODE (src
) == CONST_WIDE_INT
20904 || GET_CODE (src
) == CONST_DOUBLE
20905 || GET_CODE (src
) == CONST_VECTOR
))
20910 else if ((dest_vmx_p
&& TARGET_ALTIVEC
)
20911 || (dest_vsx_p
&& TARGET_VSX
))
20912 return output_vec_const_move (operands
);
20915 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
20918 /* Validate a 128-bit move. */
20920 rs6000_move_128bit_ok_p (rtx operands
[])
20922 machine_mode mode
= GET_MODE (operands
[0]);
20923 return (gpc_reg_operand (operands
[0], mode
)
20924 || gpc_reg_operand (operands
[1], mode
));
20927 /* Return true if a 128-bit move needs to be split. */
20929 rs6000_split_128bit_ok_p (rtx operands
[])
20931 if (!reload_completed
)
20934 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
20937 if (quad_load_store_p (operands
[0], operands
[1]))
20944 /* Given a comparison operation, return the bit number in CCR to test. We
20945 know this is a valid comparison.
20947 SCC_P is 1 if this is for an scc. That means that %D will have been
20948 used instead of %C, so the bits will be in different places.
20950 Return -1 if OP isn't a valid comparison for some reason. */
20953 ccr_bit (rtx op
, int scc_p
)
20955 enum rtx_code code
= GET_CODE (op
);
20956 machine_mode cc_mode
;
20961 if (!COMPARISON_P (op
))
20964 reg
= XEXP (op
, 0);
20966 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
20968 cc_mode
= GET_MODE (reg
);
20969 cc_regnum
= REGNO (reg
);
20970 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
20972 validate_condition_mode (code
, cc_mode
);
20974 /* When generating a sCOND operation, only positive conditions are
20977 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
20978 || code
== GTU
|| code
== LTU
);
20983 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
20985 return base_bit
+ 2;
20986 case GT
: case GTU
: case UNLE
:
20987 return base_bit
+ 1;
20988 case LT
: case LTU
: case UNGE
:
20990 case ORDERED
: case UNORDERED
:
20991 return base_bit
+ 3;
20994 /* If scc, we will have done a cror to put the bit in the
20995 unordered position. So test that bit. For integer, this is ! LT
20996 unless this is an scc insn. */
20997 return scc_p
? base_bit
+ 3 : base_bit
;
21000 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
21003 gcc_unreachable ();
21007 /* Return the GOT register. */
21010 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
21012 /* The second flow pass currently (June 1999) can't update
21013 regs_ever_live without disturbing other parts of the compiler, so
21014 update it here to make the prolog/epilogue code happy. */
21015 if (!can_create_pseudo_p ()
21016 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
21017 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
21019 crtl
->uses_pic_offset_table
= 1;
21021 return pic_offset_table_rtx
;
21024 static rs6000_stack_t stack_info
;
21026 /* Function to init struct machine_function.
21027 This will be called, via a pointer variable,
21028 from push_function_context. */
21030 static struct machine_function
*
21031 rs6000_init_machine_status (void)
21033 stack_info
.reload_completed
= 0;
21034 return ggc_cleared_alloc
<machine_function
> ();
21037 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
21039 /* Write out a function code label. */
21042 rs6000_output_function_entry (FILE *file
, const char *fname
)
21044 if (fname
[0] != '.')
21046 switch (DEFAULT_ABI
)
21049 gcc_unreachable ();
21055 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
21065 RS6000_OUTPUT_BASENAME (file
, fname
);
21068 /* Print an operand. Recognize special options, documented below. */
21071 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
21072 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
21074 #define SMALL_DATA_RELOC "sda21"
21075 #define SMALL_DATA_REG 0
21079 print_operand (FILE *file
, rtx x
, int code
)
21082 unsigned HOST_WIDE_INT uval
;
21086 /* %a is output_address. */
21088 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
21092 /* Like 'J' but get to the GT bit only. */
21093 gcc_assert (REG_P (x
));
21095 /* Bit 1 is GT bit. */
21096 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
21098 /* Add one for shift count in rlinm for scc. */
21099 fprintf (file
, "%d", i
+ 1);
21103 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
21106 output_operand_lossage ("invalid %%e value");
21111 if ((uval
& 0xffff) == 0 && uval
!= 0)
21116 /* X is a CR register. Print the number of the EQ bit of the CR */
21117 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
21118 output_operand_lossage ("invalid %%E value");
21120 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
21124 /* X is a CR register. Print the shift count needed to move it
21125 to the high-order four bits. */
21126 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
21127 output_operand_lossage ("invalid %%f value");
21129 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
21133 /* Similar, but print the count for the rotate in the opposite
21135 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
21136 output_operand_lossage ("invalid %%F value");
21138 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
21142 /* X is a constant integer. If it is negative, print "m",
21143 otherwise print "z". This is to make an aze or ame insn. */
21144 if (GET_CODE (x
) != CONST_INT
)
21145 output_operand_lossage ("invalid %%G value");
21146 else if (INTVAL (x
) >= 0)
21153 /* If constant, output low-order five bits. Otherwise, write
21156 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
21158 print_operand (file
, x
, 0);
21162 /* If constant, output low-order six bits. Otherwise, write
21165 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
21167 print_operand (file
, x
, 0);
21171 /* Print `i' if this is a constant, else nothing. */
21177 /* Write the bit number in CCR for jump. */
21178 i
= ccr_bit (x
, 0);
21180 output_operand_lossage ("invalid %%j code");
21182 fprintf (file
, "%d", i
);
21186 /* Similar, but add one for shift count in rlinm for scc and pass
21187 scc flag to `ccr_bit'. */
21188 i
= ccr_bit (x
, 1);
21190 output_operand_lossage ("invalid %%J code");
21192 /* If we want bit 31, write a shift count of zero, not 32. */
21193 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
21197 /* X must be a constant. Write the 1's complement of the
21200 output_operand_lossage ("invalid %%k value");
21202 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
21206 /* X must be a symbolic constant on ELF. Write an
21207 expression suitable for an 'addi' that adds in the low 16
21208 bits of the MEM. */
21209 if (GET_CODE (x
) == CONST
)
21211 if (GET_CODE (XEXP (x
, 0)) != PLUS
21212 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
21213 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
21214 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
21215 output_operand_lossage ("invalid %%K value");
21217 print_operand_address (file
, x
);
21218 fputs ("@l", file
);
21221 /* %l is output_asm_label. */
21224 /* Write second word of DImode or DFmode reference. Works on register
21225 or non-indexed memory only. */
21227 fputs (reg_names
[REGNO (x
) + 1], file
);
21228 else if (MEM_P (x
))
21230 machine_mode mode
= GET_MODE (x
);
21231 /* Handle possible auto-increment. Since it is pre-increment and
21232 we have already done it, we can just use an offset of word. */
21233 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21234 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21235 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
21237 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21238 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
21241 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
,
21245 if (small_data_operand (x
, GET_MODE (x
)))
21246 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21247 reg_names
[SMALL_DATA_REG
]);
21252 /* Write the number of elements in the vector times 4. */
21253 if (GET_CODE (x
) != PARALLEL
)
21254 output_operand_lossage ("invalid %%N value");
21256 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
21260 /* Similar, but subtract 1 first. */
21261 if (GET_CODE (x
) != PARALLEL
)
21262 output_operand_lossage ("invalid %%O value");
21264 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
21268 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21271 || (i
= exact_log2 (INTVAL (x
))) < 0)
21272 output_operand_lossage ("invalid %%p value");
21274 fprintf (file
, "%d", i
);
21278 /* The operand must be an indirect memory reference. The result
21279 is the register name. */
21280 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
21281 || REGNO (XEXP (x
, 0)) >= 32)
21282 output_operand_lossage ("invalid %%P value");
21284 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
21288 /* This outputs the logical code corresponding to a boolean
21289 expression. The expression may have one or both operands
21290 negated (if one, only the first one). For condition register
21291 logical operations, it will also treat the negated
21292 CR codes as NOTs, but not handle NOTs of them. */
21294 const char *const *t
= 0;
21296 enum rtx_code code
= GET_CODE (x
);
21297 static const char * const tbl
[3][3] = {
21298 { "and", "andc", "nor" },
21299 { "or", "orc", "nand" },
21300 { "xor", "eqv", "xor" } };
21304 else if (code
== IOR
)
21306 else if (code
== XOR
)
21309 output_operand_lossage ("invalid %%q value");
21311 if (GET_CODE (XEXP (x
, 0)) != NOT
)
21315 if (GET_CODE (XEXP (x
, 1)) == NOT
)
21326 if (! TARGET_MFCRF
)
21332 /* X is a CR register. Print the mask for `mtcrf'. */
21333 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
21334 output_operand_lossage ("invalid %%R value");
21336 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
21340 /* Low 5 bits of 32 - value */
21342 output_operand_lossage ("invalid %%s value");
21344 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
21348 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21349 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
21351 /* Bit 3 is OV bit. */
21352 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
21354 /* If we want bit 31, write a shift count of zero, not 32. */
21355 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
21359 /* Print the symbolic name of a branch target register. */
21360 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
21361 && REGNO (x
) != CTR_REGNO
))
21362 output_operand_lossage ("invalid %%T value");
21363 else if (REGNO (x
) == LR_REGNO
)
21364 fputs ("lr", file
);
21366 fputs ("ctr", file
);
21370 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21371 for use in unsigned operand. */
21374 output_operand_lossage ("invalid %%u value");
21379 if ((uval
& 0xffff) == 0)
21382 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
21386 /* High-order 16 bits of constant for use in signed operand. */
21388 output_operand_lossage ("invalid %%v value");
21390 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
21391 (INTVAL (x
) >> 16) & 0xffff);
21395 /* Print `u' if this has an auto-increment or auto-decrement. */
21397 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
21398 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
21399 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
21404 /* Print the trap code for this operand. */
21405 switch (GET_CODE (x
))
21408 fputs ("eq", file
); /* 4 */
21411 fputs ("ne", file
); /* 24 */
21414 fputs ("lt", file
); /* 16 */
21417 fputs ("le", file
); /* 20 */
21420 fputs ("gt", file
); /* 8 */
21423 fputs ("ge", file
); /* 12 */
21426 fputs ("llt", file
); /* 2 */
21429 fputs ("lle", file
); /* 6 */
21432 fputs ("lgt", file
); /* 1 */
21435 fputs ("lge", file
); /* 5 */
21438 gcc_unreachable ();
21443 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21446 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
21447 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
21449 print_operand (file
, x
, 0);
21453 /* X is a FPR or Altivec register used in a VSX context. */
21454 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
21455 output_operand_lossage ("invalid %%x value");
21458 int reg
= REGNO (x
);
21459 int vsx_reg
= (FP_REGNO_P (reg
)
21461 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
21463 #ifdef TARGET_REGNAMES
21464 if (TARGET_REGNAMES
)
21465 fprintf (file
, "%%vs%d", vsx_reg
);
21468 fprintf (file
, "%d", vsx_reg
);
21474 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
21475 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
21476 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
21481 /* Like 'L', for third word of TImode/PTImode */
21483 fputs (reg_names
[REGNO (x
) + 2], file
);
21484 else if (MEM_P (x
))
21486 machine_mode mode
= GET_MODE (x
);
21487 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21488 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21489 output_address (mode
, plus_constant (Pmode
,
21490 XEXP (XEXP (x
, 0), 0), 8));
21491 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21492 output_address (mode
, plus_constant (Pmode
,
21493 XEXP (XEXP (x
, 0), 0), 8));
21495 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 8), 0));
21496 if (small_data_operand (x
, GET_MODE (x
)))
21497 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21498 reg_names
[SMALL_DATA_REG
]);
21503 /* X is a SYMBOL_REF. Write out the name preceded by a
21504 period and without any trailing data in brackets. Used for function
21505 names. If we are configured for System V (or the embedded ABI) on
21506 the PowerPC, do not emit the period, since those systems do not use
21507 TOCs and the like. */
21508 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
21510 /* For macho, check to see if we need a stub. */
21513 const char *name
= XSTR (x
, 0);
21515 if (darwin_emit_branch_islands
21516 && MACHOPIC_INDIRECT
21517 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
21518 name
= machopic_indirection_name (x
, /*stub_p=*/true);
21520 assemble_name (file
, name
);
21522 else if (!DOT_SYMBOLS
)
21523 assemble_name (file
, XSTR (x
, 0));
21525 rs6000_output_function_entry (file
, XSTR (x
, 0));
21529 /* Like 'L', for last word of TImode/PTImode. */
21531 fputs (reg_names
[REGNO (x
) + 3], file
);
21532 else if (MEM_P (x
))
21534 machine_mode mode
= GET_MODE (x
);
21535 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21536 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21537 output_address (mode
, plus_constant (Pmode
,
21538 XEXP (XEXP (x
, 0), 0), 12));
21539 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21540 output_address (mode
, plus_constant (Pmode
,
21541 XEXP (XEXP (x
, 0), 0), 12));
21543 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 12), 0));
21544 if (small_data_operand (x
, GET_MODE (x
)))
21545 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21546 reg_names
[SMALL_DATA_REG
]);
21550 /* Print AltiVec memory operand. */
21555 gcc_assert (MEM_P (x
));
21559 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
21560 && GET_CODE (tmp
) == AND
21561 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
21562 && INTVAL (XEXP (tmp
, 1)) == -16)
21563 tmp
= XEXP (tmp
, 0);
21564 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
21565 && GET_CODE (tmp
) == PRE_MODIFY
)
21566 tmp
= XEXP (tmp
, 1);
21568 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
21571 if (GET_CODE (tmp
) != PLUS
21572 || !REG_P (XEXP (tmp
, 0))
21573 || !REG_P (XEXP (tmp
, 1)))
21575 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21579 if (REGNO (XEXP (tmp
, 0)) == 0)
21580 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
21581 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
21583 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
21584 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
21591 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
21592 else if (MEM_P (x
))
21594 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21595 know the width from the mode. */
21596 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
21597 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
21598 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21599 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21600 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
21601 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21602 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21603 output_address (GET_MODE (x
), XEXP (XEXP (x
, 0), 1));
21605 output_address (GET_MODE (x
), XEXP (x
, 0));
21609 if (toc_relative_expr_p (x
, false, &tocrel_base_oac
, &tocrel_offset_oac
))
21610 /* This hack along with a corresponding hack in
21611 rs6000_output_addr_const_extra arranges to output addends
21612 where the assembler expects to find them. eg.
21613 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21614 without this hack would be output as "x@toc+4". We
21616 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21618 output_addr_const (file
, x
);
21623 if (const char *name
= get_some_local_dynamic_name ())
21624 assemble_name (file
, name
);
21626 output_operand_lossage ("'%%&' used without any "
21627 "local dynamic TLS references");
21631 output_operand_lossage ("invalid %%xn code");
21635 /* Print the address of an operand. */
21638 print_operand_address (FILE *file
, rtx x
)
21641 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
21642 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
21643 || GET_CODE (x
) == LABEL_REF
)
21645 output_addr_const (file
, x
);
21646 if (small_data_operand (x
, GET_MODE (x
)))
21647 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21648 reg_names
[SMALL_DATA_REG
]);
21650 gcc_assert (!TARGET_TOC
);
21652 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21653 && REG_P (XEXP (x
, 1)))
21655 if (REGNO (XEXP (x
, 0)) == 0)
21656 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
21657 reg_names
[ REGNO (XEXP (x
, 0)) ]);
21659 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
21660 reg_names
[ REGNO (XEXP (x
, 1)) ]);
21662 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21663 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
21664 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
21665 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
21667 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21668 && CONSTANT_P (XEXP (x
, 1)))
21670 fprintf (file
, "lo16(");
21671 output_addr_const (file
, XEXP (x
, 1));
21672 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21676 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21677 && CONSTANT_P (XEXP (x
, 1)))
21679 output_addr_const (file
, XEXP (x
, 1));
21680 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21683 else if (toc_relative_expr_p (x
, false, &tocrel_base_oac
, &tocrel_offset_oac
))
21685 /* This hack along with a corresponding hack in
21686 rs6000_output_addr_const_extra arranges to output addends
21687 where the assembler expects to find them. eg.
21689 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21690 without this hack would be output as "x@toc+8@l(9)". We
21691 want "x+8@toc@l(9)". */
21692 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21693 if (GET_CODE (x
) == LO_SUM
)
21694 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
21696 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base_oac
, 0, 1))]);
21699 gcc_unreachable ();
21702 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21705 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
21707 if (GET_CODE (x
) == UNSPEC
)
21708 switch (XINT (x
, 1))
21710 case UNSPEC_TOCREL
:
21711 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
21712 && REG_P (XVECEXP (x
, 0, 1))
21713 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
21714 output_addr_const (file
, XVECEXP (x
, 0, 0));
21715 if (x
== tocrel_base_oac
&& tocrel_offset_oac
!= const0_rtx
)
21717 if (INTVAL (tocrel_offset_oac
) >= 0)
21718 fprintf (file
, "+");
21719 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset_oac
));
21721 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
21724 assemble_name (file
, toc_label_name
);
21727 else if (TARGET_ELF
)
21728 fputs ("@toc", file
);
21732 case UNSPEC_MACHOPIC_OFFSET
:
21733 output_addr_const (file
, XVECEXP (x
, 0, 0));
21735 machopic_output_function_base_name (file
);
21742 /* Target hook for assembling integer objects. The PowerPC version has
21743 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21744 is defined. It also needs to handle DI-mode objects on 64-bit
21748 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
21750 #ifdef RELOCATABLE_NEEDS_FIXUP
21751 /* Special handling for SI values. */
21752 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
21754 static int recurse
= 0;
21756 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21757 the .fixup section. Since the TOC section is already relocated, we
21758 don't need to mark it here. We used to skip the text section, but it
21759 should never be valid for relocated addresses to be placed in the text
21761 if (DEFAULT_ABI
== ABI_V4
21762 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
21763 && in_section
!= toc_section
21765 && !CONST_SCALAR_INT_P (x
)
21771 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
21773 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
21774 fprintf (asm_out_file
, "\t.long\t(");
21775 output_addr_const (asm_out_file
, x
);
21776 fprintf (asm_out_file
, ")@fixup\n");
21777 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
21778 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
21779 fprintf (asm_out_file
, "\t.long\t");
21780 assemble_name (asm_out_file
, buf
);
21781 fprintf (asm_out_file
, "\n\t.previous\n");
21785 /* Remove initial .'s to turn a -mcall-aixdesc function
21786 address into the address of the descriptor, not the function
21788 else if (GET_CODE (x
) == SYMBOL_REF
21789 && XSTR (x
, 0)[0] == '.'
21790 && DEFAULT_ABI
== ABI_AIX
)
21792 const char *name
= XSTR (x
, 0);
21793 while (*name
== '.')
21796 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
21800 #endif /* RELOCATABLE_NEEDS_FIXUP */
21801 return default_assemble_integer (x
, size
, aligned_p
);
21804 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21805 /* Emit an assembler directive to set symbol visibility for DECL to
21806 VISIBILITY_TYPE. */
21809 rs6000_assemble_visibility (tree decl
, int vis
)
21814 /* Functions need to have their entry point symbol visibility set as
21815 well as their descriptor symbol visibility. */
21816 if (DEFAULT_ABI
== ABI_AIX
21818 && TREE_CODE (decl
) == FUNCTION_DECL
)
21820 static const char * const visibility_types
[] = {
21821 NULL
, "protected", "hidden", "internal"
21824 const char *name
, *type
;
21826 name
= ((* targetm
.strip_name_encoding
)
21827 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
21828 type
= visibility_types
[vis
];
21830 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
21831 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
21834 default_assemble_visibility (decl
, vis
);
21839 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
21841 /* Reversal of FP compares takes care -- an ordered compare
21842 becomes an unordered compare and vice versa. */
21843 if (mode
== CCFPmode
21844 && (!flag_finite_math_only
21845 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
21846 || code
== UNEQ
|| code
== LTGT
))
21847 return reverse_condition_maybe_unordered (code
);
21849 return reverse_condition (code
);
21852 /* Generate a compare for CODE. Return a brand-new rtx that
21853 represents the result of the compare. */
21856 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
21858 machine_mode comp_mode
;
21859 rtx compare_result
;
21860 enum rtx_code code
= GET_CODE (cmp
);
21861 rtx op0
= XEXP (cmp
, 0);
21862 rtx op1
= XEXP (cmp
, 1);
21864 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21865 comp_mode
= CCmode
;
21866 else if (FLOAT_MODE_P (mode
))
21867 comp_mode
= CCFPmode
;
21868 else if (code
== GTU
|| code
== LTU
21869 || code
== GEU
|| code
== LEU
)
21870 comp_mode
= CCUNSmode
;
21871 else if ((code
== EQ
|| code
== NE
)
21872 && unsigned_reg_p (op0
)
21873 && (unsigned_reg_p (op1
)
21874 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
21875 /* These are unsigned values, perhaps there will be a later
21876 ordering compare that can be shared with this one. */
21877 comp_mode
= CCUNSmode
;
21879 comp_mode
= CCmode
;
21881 /* If we have an unsigned compare, make sure we don't have a signed value as
21883 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
21884 && INTVAL (op1
) < 0)
21886 op0
= copy_rtx_if_shared (op0
);
21887 op1
= force_reg (GET_MODE (op0
), op1
);
21888 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
21891 /* First, the compare. */
21892 compare_result
= gen_reg_rtx (comp_mode
);
21894 /* IEEE 128-bit support in VSX registers when we do not have hardware
21896 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21898 rtx libfunc
= NULL_RTX
;
21899 bool check_nan
= false;
21906 libfunc
= optab_libfunc (eq_optab
, mode
);
21911 libfunc
= optab_libfunc (ge_optab
, mode
);
21916 libfunc
= optab_libfunc (le_optab
, mode
);
21921 libfunc
= optab_libfunc (unord_optab
, mode
);
21922 code
= (code
== UNORDERED
) ? NE
: EQ
;
21928 libfunc
= optab_libfunc (ge_optab
, mode
);
21929 code
= (code
== UNGE
) ? GE
: GT
;
21935 libfunc
= optab_libfunc (le_optab
, mode
);
21936 code
= (code
== UNLE
) ? LE
: LT
;
21942 libfunc
= optab_libfunc (eq_optab
, mode
);
21943 code
= (code
= UNEQ
) ? EQ
: NE
;
21947 gcc_unreachable ();
21950 gcc_assert (libfunc
);
21953 dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
21954 SImode
, 2, op0
, mode
, op1
, mode
);
21956 /* The library signals an exception for signalling NaNs, so we need to
21957 handle isgreater, etc. by first checking isordered. */
21960 rtx ne_rtx
, normal_dest
, unord_dest
;
21961 rtx unord_func
= optab_libfunc (unord_optab
, mode
);
21962 rtx join_label
= gen_label_rtx ();
21963 rtx join_ref
= gen_rtx_LABEL_REF (VOIDmode
, join_label
);
21964 rtx unord_cmp
= gen_reg_rtx (comp_mode
);
21967 /* Test for either value being a NaN. */
21968 gcc_assert (unord_func
);
21969 unord_dest
= emit_library_call_value (unord_func
, NULL_RTX
, LCT_CONST
,
21970 SImode
, 2, op0
, mode
, op1
,
21973 /* Set value (0) if either value is a NaN, and jump to the join
21975 dest
= gen_reg_rtx (SImode
);
21976 emit_move_insn (dest
, const1_rtx
);
21977 emit_insn (gen_rtx_SET (unord_cmp
,
21978 gen_rtx_COMPARE (comp_mode
, unord_dest
,
21981 ne_rtx
= gen_rtx_NE (comp_mode
, unord_cmp
, const0_rtx
);
21982 emit_jump_insn (gen_rtx_SET (pc_rtx
,
21983 gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
21987 /* Do the normal comparison, knowing that the values are not
21989 normal_dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
21990 SImode
, 2, op0
, mode
, op1
,
21993 emit_insn (gen_cstoresi4 (dest
,
21994 gen_rtx_fmt_ee (code
, SImode
, normal_dest
,
21996 normal_dest
, const0_rtx
));
21998 /* Join NaN and non-Nan paths. Compare dest against 0. */
21999 emit_label (join_label
);
22003 emit_insn (gen_rtx_SET (compare_result
,
22004 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
22009 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22010 CLOBBERs to match cmptf_internal2 pattern. */
22011 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
22012 && FLOAT128_IBM_P (GET_MODE (op0
))
22013 && TARGET_HARD_FLOAT
)
22014 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22016 gen_rtx_SET (compare_result
,
22017 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
22018 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22019 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22020 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22021 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22022 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22023 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22024 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22025 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22026 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
22027 else if (GET_CODE (op1
) == UNSPEC
22028 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
22030 rtx op1b
= XVECEXP (op1
, 0, 0);
22031 comp_mode
= CCEQmode
;
22032 compare_result
= gen_reg_rtx (CCEQmode
);
22034 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
22036 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
22039 emit_insn (gen_rtx_SET (compare_result
,
22040 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
22043 /* Some kinds of FP comparisons need an OR operation;
22044 under flag_finite_math_only we don't bother. */
22045 if (FLOAT_MODE_P (mode
)
22046 && (!FLOAT128_IEEE_P (mode
) || TARGET_FLOAT128_HW
)
22047 && !flag_finite_math_only
22048 && (code
== LE
|| code
== GE
22049 || code
== UNEQ
|| code
== LTGT
22050 || code
== UNGT
|| code
== UNLT
))
22052 enum rtx_code or1
, or2
;
22053 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
22054 rtx or_result
= gen_reg_rtx (CCEQmode
);
22058 case LE
: or1
= LT
; or2
= EQ
; break;
22059 case GE
: or1
= GT
; or2
= EQ
; break;
22060 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
22061 case LTGT
: or1
= LT
; or2
= GT
; break;
22062 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
22063 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
22064 default: gcc_unreachable ();
22066 validate_condition_mode (or1
, comp_mode
);
22067 validate_condition_mode (or2
, comp_mode
);
22068 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
22069 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
22070 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
22071 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
22073 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
22075 compare_result
= or_result
;
22079 validate_condition_mode (code
, GET_MODE (compare_result
));
22081 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
22085 /* Return the diagnostic message string if the binary operation OP is
22086 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22089 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED
,
22093 machine_mode mode1
= TYPE_MODE (type1
);
22094 machine_mode mode2
= TYPE_MODE (type2
);
22096 /* For complex modes, use the inner type. */
22097 if (COMPLEX_MODE_P (mode1
))
22098 mode1
= GET_MODE_INNER (mode1
);
22100 if (COMPLEX_MODE_P (mode2
))
22101 mode2
= GET_MODE_INNER (mode2
);
22103 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22104 double to intermix unless -mfloat128-convert. */
22105 if (mode1
== mode2
)
22108 if (!TARGET_FLOAT128_CVT
)
22110 if ((mode1
== KFmode
&& mode2
== IFmode
)
22111 || (mode1
== IFmode
&& mode2
== KFmode
))
22112 return N_("__float128 and __ibm128 cannot be used in the same "
22115 if (TARGET_IEEEQUAD
22116 && ((mode1
== IFmode
&& mode2
== TFmode
)
22117 || (mode1
== TFmode
&& mode2
== IFmode
)))
22118 return N_("__ibm128 and long double cannot be used in the same "
22121 if (!TARGET_IEEEQUAD
22122 && ((mode1
== KFmode
&& mode2
== TFmode
)
22123 || (mode1
== TFmode
&& mode2
== KFmode
)))
22124 return N_("__float128 and long double cannot be used in the same "
22132 /* Expand floating point conversion to/from __float128 and __ibm128. */
22135 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
22137 machine_mode dest_mode
= GET_MODE (dest
);
22138 machine_mode src_mode
= GET_MODE (src
);
22139 convert_optab cvt
= unknown_optab
;
22140 bool do_move
= false;
22141 rtx libfunc
= NULL_RTX
;
22143 typedef rtx (*rtx_2func_t
) (rtx
, rtx
);
22144 rtx_2func_t hw_convert
= (rtx_2func_t
)0;
22148 rtx_2func_t from_df
;
22149 rtx_2func_t from_sf
;
22150 rtx_2func_t from_si_sign
;
22151 rtx_2func_t from_si_uns
;
22152 rtx_2func_t from_di_sign
;
22153 rtx_2func_t from_di_uns
;
22156 rtx_2func_t to_si_sign
;
22157 rtx_2func_t to_si_uns
;
22158 rtx_2func_t to_di_sign
;
22159 rtx_2func_t to_di_uns
;
22160 } hw_conversions
[2] = {
22161 /* convertions to/from KFmode */
22163 gen_extenddfkf2_hw
, /* KFmode <- DFmode. */
22164 gen_extendsfkf2_hw
, /* KFmode <- SFmode. */
22165 gen_float_kfsi2_hw
, /* KFmode <- SImode (signed). */
22166 gen_floatuns_kfsi2_hw
, /* KFmode <- SImode (unsigned). */
22167 gen_float_kfdi2_hw
, /* KFmode <- DImode (signed). */
22168 gen_floatuns_kfdi2_hw
, /* KFmode <- DImode (unsigned). */
22169 gen_trunckfdf2_hw
, /* DFmode <- KFmode. */
22170 gen_trunckfsf2_hw
, /* SFmode <- KFmode. */
22171 gen_fix_kfsi2_hw
, /* SImode <- KFmode (signed). */
22172 gen_fixuns_kfsi2_hw
, /* SImode <- KFmode (unsigned). */
22173 gen_fix_kfdi2_hw
, /* DImode <- KFmode (signed). */
22174 gen_fixuns_kfdi2_hw
, /* DImode <- KFmode (unsigned). */
22177 /* convertions to/from TFmode */
22179 gen_extenddftf2_hw
, /* TFmode <- DFmode. */
22180 gen_extendsftf2_hw
, /* TFmode <- SFmode. */
22181 gen_float_tfsi2_hw
, /* TFmode <- SImode (signed). */
22182 gen_floatuns_tfsi2_hw
, /* TFmode <- SImode (unsigned). */
22183 gen_float_tfdi2_hw
, /* TFmode <- DImode (signed). */
22184 gen_floatuns_tfdi2_hw
, /* TFmode <- DImode (unsigned). */
22185 gen_trunctfdf2_hw
, /* DFmode <- TFmode. */
22186 gen_trunctfsf2_hw
, /* SFmode <- TFmode. */
22187 gen_fix_tfsi2_hw
, /* SImode <- TFmode (signed). */
22188 gen_fixuns_tfsi2_hw
, /* SImode <- TFmode (unsigned). */
22189 gen_fix_tfdi2_hw
, /* DImode <- TFmode (signed). */
22190 gen_fixuns_tfdi2_hw
, /* DImode <- TFmode (unsigned). */
22194 if (dest_mode
== src_mode
)
22195 gcc_unreachable ();
22197 /* Eliminate memory operations. */
22199 src
= force_reg (src_mode
, src
);
22203 rtx tmp
= gen_reg_rtx (dest_mode
);
22204 rs6000_expand_float128_convert (tmp
, src
, unsigned_p
);
22205 rs6000_emit_move (dest
, tmp
, dest_mode
);
22209 /* Convert to IEEE 128-bit floating point. */
22210 if (FLOAT128_IEEE_P (dest_mode
))
22212 if (dest_mode
== KFmode
)
22214 else if (dest_mode
== TFmode
)
22217 gcc_unreachable ();
22223 hw_convert
= hw_conversions
[kf_or_tf
].from_df
;
22228 hw_convert
= hw_conversions
[kf_or_tf
].from_sf
;
22234 if (FLOAT128_IBM_P (src_mode
))
22243 cvt
= ufloat_optab
;
22244 hw_convert
= hw_conversions
[kf_or_tf
].from_si_uns
;
22248 cvt
= sfloat_optab
;
22249 hw_convert
= hw_conversions
[kf_or_tf
].from_si_sign
;
22256 cvt
= ufloat_optab
;
22257 hw_convert
= hw_conversions
[kf_or_tf
].from_di_uns
;
22261 cvt
= sfloat_optab
;
22262 hw_convert
= hw_conversions
[kf_or_tf
].from_di_sign
;
22267 gcc_unreachable ();
22271 /* Convert from IEEE 128-bit floating point. */
22272 else if (FLOAT128_IEEE_P (src_mode
))
22274 if (src_mode
== KFmode
)
22276 else if (src_mode
== TFmode
)
22279 gcc_unreachable ();
22285 hw_convert
= hw_conversions
[kf_or_tf
].to_df
;
22290 hw_convert
= hw_conversions
[kf_or_tf
].to_sf
;
22296 if (FLOAT128_IBM_P (dest_mode
))
22306 hw_convert
= hw_conversions
[kf_or_tf
].to_si_uns
;
22311 hw_convert
= hw_conversions
[kf_or_tf
].to_si_sign
;
22319 hw_convert
= hw_conversions
[kf_or_tf
].to_di_uns
;
22324 hw_convert
= hw_conversions
[kf_or_tf
].to_di_sign
;
22329 gcc_unreachable ();
22333 /* Both IBM format. */
22334 else if (FLOAT128_IBM_P (dest_mode
) && FLOAT128_IBM_P (src_mode
))
22338 gcc_unreachable ();
22340 /* Handle conversion between TFmode/KFmode. */
22342 emit_move_insn (dest
, gen_lowpart (dest_mode
, src
));
22344 /* Handle conversion if we have hardware support. */
22345 else if (TARGET_FLOAT128_HW
&& hw_convert
)
22346 emit_insn ((hw_convert
) (dest
, src
));
22348 /* Call an external function to do the conversion. */
22349 else if (cvt
!= unknown_optab
)
22351 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
22352 gcc_assert (libfunc
!= NULL_RTX
);
22354 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
, 1, src
,
22357 gcc_assert (dest2
!= NULL_RTX
);
22358 if (!rtx_equal_p (dest
, dest2
))
22359 emit_move_insn (dest
, dest2
);
22363 gcc_unreachable ();
22369 /* Emit the RTL for an sISEL pattern. */
22372 rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
22374 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
22377 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22378 can be used as that dest register. Return the dest register. */
22381 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
22383 if (op2
== const0_rtx
)
22386 if (GET_CODE (scratch
) == SCRATCH
)
22387 scratch
= gen_reg_rtx (mode
);
22389 if (logical_operand (op2
, mode
))
22390 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
22392 emit_insn (gen_rtx_SET (scratch
,
22393 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
22399 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
22402 machine_mode op_mode
;
22403 enum rtx_code cond_code
;
22404 rtx result
= operands
[0];
22406 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
22407 cond_code
= GET_CODE (condition_rtx
);
22409 if (cond_code
== NE
22410 || cond_code
== GE
|| cond_code
== LE
22411 || cond_code
== GEU
|| cond_code
== LEU
22412 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
22414 rtx not_result
= gen_reg_rtx (CCEQmode
);
22415 rtx not_op
, rev_cond_rtx
;
22416 machine_mode cc_mode
;
22418 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
22420 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
22421 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
22422 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
22423 emit_insn (gen_rtx_SET (not_result
, not_op
));
22424 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
22427 op_mode
= GET_MODE (XEXP (operands
[1], 0));
22428 if (op_mode
== VOIDmode
)
22429 op_mode
= GET_MODE (XEXP (operands
[1], 1));
22431 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
22433 PUT_MODE (condition_rtx
, DImode
);
22434 convert_move (result
, condition_rtx
, 0);
22438 PUT_MODE (condition_rtx
, SImode
);
22439 emit_insn (gen_rtx_SET (result
, condition_rtx
));
22443 /* Emit a branch of kind CODE to location LOC. */
22446 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
22448 rtx condition_rtx
, loc_ref
;
22450 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
22451 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
22452 emit_jump_insn (gen_rtx_SET (pc_rtx
,
22453 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
22454 loc_ref
, pc_rtx
)));
22457 /* Return the string to output a conditional branch to LABEL, which is
22458 the operand template of the label, or NULL if the branch is really a
22459 conditional return.
22461 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22462 condition code register and its mode specifies what kind of
22463 comparison we made.
22465 REVERSED is nonzero if we should reverse the sense of the comparison.
22467 INSN is the insn. */
22470 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
22472 static char string
[64];
22473 enum rtx_code code
= GET_CODE (op
);
22474 rtx cc_reg
= XEXP (op
, 0);
22475 machine_mode mode
= GET_MODE (cc_reg
);
22476 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
22477 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
22478 int really_reversed
= reversed
^ need_longbranch
;
22484 validate_condition_mode (code
, mode
);
22486 /* Work out which way this really branches. We could use
22487 reverse_condition_maybe_unordered here always but this
22488 makes the resulting assembler clearer. */
22489 if (really_reversed
)
22491 /* Reversal of FP compares takes care -- an ordered compare
22492 becomes an unordered compare and vice versa. */
22493 if (mode
== CCFPmode
)
22494 code
= reverse_condition_maybe_unordered (code
);
22496 code
= reverse_condition (code
);
22501 /* Not all of these are actually distinct opcodes, but
22502 we distinguish them for clarity of the resulting assembler. */
22503 case NE
: case LTGT
:
22504 ccode
= "ne"; break;
22505 case EQ
: case UNEQ
:
22506 ccode
= "eq"; break;
22508 ccode
= "ge"; break;
22509 case GT
: case GTU
: case UNGT
:
22510 ccode
= "gt"; break;
22512 ccode
= "le"; break;
22513 case LT
: case LTU
: case UNLT
:
22514 ccode
= "lt"; break;
22515 case UNORDERED
: ccode
= "un"; break;
22516 case ORDERED
: ccode
= "nu"; break;
22517 case UNGE
: ccode
= "nl"; break;
22518 case UNLE
: ccode
= "ng"; break;
22520 gcc_unreachable ();
22523 /* Maybe we have a guess as to how likely the branch is. */
22525 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
22526 if (note
!= NULL_RTX
)
22528 /* PROB is the difference from 50%. */
22529 int prob
= profile_probability::from_reg_br_prob_note (XINT (note
, 0))
22530 .to_reg_br_prob_base () - REG_BR_PROB_BASE
/ 2;
22532 /* Only hint for highly probable/improbable branches on newer cpus when
22533 we have real profile data, as static prediction overrides processor
22534 dynamic prediction. For older cpus we may as well always hint, but
22535 assume not taken for branches that are very close to 50% as a
22536 mispredicted taken branch is more expensive than a
22537 mispredicted not-taken branch. */
22538 if (rs6000_always_hint
22539 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
22540 && (profile_status_for_fn (cfun
) != PROFILE_GUESSED
)
22541 && br_prob_note_reliable_p (note
)))
22543 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
22544 && ((prob
> 0) ^ need_longbranch
))
22552 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
22554 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
22556 /* We need to escape any '%' characters in the reg_names string.
22557 Assume they'd only be the first character.... */
22558 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
22560 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
22564 /* If the branch distance was too far, we may have to use an
22565 unconditional branch to go the distance. */
22566 if (need_longbranch
)
22567 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
22569 s
+= sprintf (s
, ",%s", label
);
22575 /* Return insn for VSX or Altivec comparisons. */
22578 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
22581 machine_mode mode
= GET_MODE (op0
);
22589 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
22600 mask
= gen_reg_rtx (mode
);
22601 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
22608 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22609 DMODE is expected destination mode. This is a recursive function. */
22612 rs6000_emit_vector_compare (enum rtx_code rcode
,
22614 machine_mode dmode
)
22617 bool swap_operands
= false;
22618 bool try_again
= false;
22620 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
22621 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
22623 /* See if the comparison works as is. */
22624 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22632 swap_operands
= true;
22637 swap_operands
= true;
22645 /* Invert condition and try again.
22646 e.g., A != B becomes ~(A==B). */
22648 enum rtx_code rev_code
;
22649 enum insn_code nor_code
;
22652 rev_code
= reverse_condition_maybe_unordered (rcode
);
22653 if (rev_code
== UNKNOWN
)
22656 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
22657 if (nor_code
== CODE_FOR_nothing
)
22660 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
22664 mask
= gen_reg_rtx (dmode
);
22665 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
22673 /* Try GT/GTU/LT/LTU OR EQ */
22676 enum insn_code ior_code
;
22677 enum rtx_code new_code
;
22698 gcc_unreachable ();
22701 ior_code
= optab_handler (ior_optab
, dmode
);
22702 if (ior_code
== CODE_FOR_nothing
)
22705 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
22709 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
22713 mask
= gen_reg_rtx (dmode
);
22714 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
22725 std::swap (op0
, op1
);
22727 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22732 /* You only get two chances. */
22736 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22737 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22738 operands for the relation operation COND. */
22741 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
22742 rtx cond
, rtx cc_op0
, rtx cc_op1
)
22744 machine_mode dest_mode
= GET_MODE (dest
);
22745 machine_mode mask_mode
= GET_MODE (cc_op0
);
22746 enum rtx_code rcode
= GET_CODE (cond
);
22747 machine_mode cc_mode
= CCmode
;
22750 bool invert_move
= false;
22752 if (VECTOR_UNIT_NONE_P (dest_mode
))
22755 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
22756 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
22760 /* Swap operands if we can, and fall back to doing the operation as
22761 specified, and doing a NOR to invert the test. */
22767 /* Invert condition and try again.
22768 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22769 invert_move
= true;
22770 rcode
= reverse_condition_maybe_unordered (rcode
);
22771 if (rcode
== UNKNOWN
)
22777 if (GET_MODE_CLASS (mask_mode
) == MODE_VECTOR_INT
)
22779 /* Invert condition to avoid compound test. */
22780 invert_move
= true;
22781 rcode
= reverse_condition (rcode
);
22789 /* Mark unsigned tests with CCUNSmode. */
22790 cc_mode
= CCUNSmode
;
22792 /* Invert condition to avoid compound test if necessary. */
22793 if (rcode
== GEU
|| rcode
== LEU
)
22795 invert_move
= true;
22796 rcode
= reverse_condition (rcode
);
22804 /* Get the vector mask for the given relational operations. */
22805 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
22811 std::swap (op_true
, op_false
);
22813 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22814 if (GET_MODE_CLASS (dest_mode
) == MODE_VECTOR_INT
22815 && (GET_CODE (op_true
) == CONST_VECTOR
22816 || GET_CODE (op_false
) == CONST_VECTOR
))
22818 rtx constant_0
= CONST0_RTX (dest_mode
);
22819 rtx constant_m1
= CONSTM1_RTX (dest_mode
);
22821 if (op_true
== constant_m1
&& op_false
== constant_0
)
22823 emit_move_insn (dest
, mask
);
22827 else if (op_true
== constant_0
&& op_false
== constant_m1
)
22829 emit_insn (gen_rtx_SET (dest
, gen_rtx_NOT (dest_mode
, mask
)));
22833 /* If we can't use the vector comparison directly, perhaps we can use
22834 the mask for the true or false fields, instead of loading up a
22836 if (op_true
== constant_m1
)
22839 if (op_false
== constant_0
)
22843 if (!REG_P (op_true
) && !SUBREG_P (op_true
))
22844 op_true
= force_reg (dest_mode
, op_true
);
22846 if (!REG_P (op_false
) && !SUBREG_P (op_false
))
22847 op_false
= force_reg (dest_mode
, op_false
);
22849 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
22850 CONST0_RTX (dest_mode
));
22851 emit_insn (gen_rtx_SET (dest
,
22852 gen_rtx_IF_THEN_ELSE (dest_mode
,
22859 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22860 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22861 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22862 hardware has no such operation. */
22865 rs6000_emit_p9_fp_minmax (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22867 enum rtx_code code
= GET_CODE (op
);
22868 rtx op0
= XEXP (op
, 0);
22869 rtx op1
= XEXP (op
, 1);
22870 machine_mode compare_mode
= GET_MODE (op0
);
22871 machine_mode result_mode
= GET_MODE (dest
);
22872 bool max_p
= false;
22874 if (result_mode
!= compare_mode
)
22877 if (code
== GE
|| code
== GT
)
22879 else if (code
== LE
|| code
== LT
)
22884 if (rtx_equal_p (op0
, true_cond
) && rtx_equal_p (op1
, false_cond
))
22887 else if (rtx_equal_p (op1
, true_cond
) && rtx_equal_p (op0
, false_cond
))
22893 rs6000_emit_minmax (dest
, max_p
? SMAX
: SMIN
, op0
, op1
);
22897 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22898 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22899 operands of the last comparison is nonzero/true, FALSE_COND if it is
22900 zero/false. Return 0 if the hardware has no such operation. */
22903 rs6000_emit_p9_fp_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22905 enum rtx_code code
= GET_CODE (op
);
22906 rtx op0
= XEXP (op
, 0);
22907 rtx op1
= XEXP (op
, 1);
22908 machine_mode result_mode
= GET_MODE (dest
);
22913 if (!can_create_pseudo_p ())
22926 code
= swap_condition (code
);
22927 std::swap (op0
, op1
);
22934 /* Generate: [(parallel [(set (dest)
22935 (if_then_else (op (cmp1) (cmp2))
22938 (clobber (scratch))])]. */
22940 compare_rtx
= gen_rtx_fmt_ee (code
, CCFPmode
, op0
, op1
);
22941 cmove_rtx
= gen_rtx_SET (dest
,
22942 gen_rtx_IF_THEN_ELSE (result_mode
,
22947 clobber_rtx
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (V2DImode
));
22948 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22949 gen_rtvec (2, cmove_rtx
, clobber_rtx
)));
22954 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22955 operands of the last comparison is nonzero/true, FALSE_COND if it
22956 is zero/false. Return 0 if the hardware has no such operation. */
22959 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22961 enum rtx_code code
= GET_CODE (op
);
22962 rtx op0
= XEXP (op
, 0);
22963 rtx op1
= XEXP (op
, 1);
22964 machine_mode compare_mode
= GET_MODE (op0
);
22965 machine_mode result_mode
= GET_MODE (dest
);
22967 bool is_against_zero
;
22969 /* These modes should always match. */
22970 if (GET_MODE (op1
) != compare_mode
22971 /* In the isel case however, we can use a compare immediate, so
22972 op1 may be a small constant. */
22973 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
22975 if (GET_MODE (true_cond
) != result_mode
)
22977 if (GET_MODE (false_cond
) != result_mode
)
22980 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22981 if (TARGET_P9_MINMAX
22982 && (compare_mode
== SFmode
|| compare_mode
== DFmode
)
22983 && (result_mode
== SFmode
|| result_mode
== DFmode
))
22985 if (rs6000_emit_p9_fp_minmax (dest
, op
, true_cond
, false_cond
))
22988 if (rs6000_emit_p9_fp_cmove (dest
, op
, true_cond
, false_cond
))
22992 /* Don't allow using floating point comparisons for integer results for
22994 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
22997 /* First, work out if the hardware can do this at all, or
22998 if it's too slow.... */
22999 if (!FLOAT_MODE_P (compare_mode
))
23002 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
23006 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
23008 /* A floating-point subtract might overflow, underflow, or produce
23009 an inexact result, thus changing the floating-point flags, so it
23010 can't be generated if we care about that. It's safe if one side
23011 of the construct is zero, since then no subtract will be
23013 if (SCALAR_FLOAT_MODE_P (compare_mode
)
23014 && flag_trapping_math
&& ! is_against_zero
)
23017 /* Eliminate half of the comparisons by switching operands, this
23018 makes the remaining code simpler. */
23019 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
23020 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
23022 code
= reverse_condition_maybe_unordered (code
);
23024 true_cond
= false_cond
;
23028 /* UNEQ and LTGT take four instructions for a comparison with zero,
23029 it'll probably be faster to use a branch here too. */
23030 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
23033 /* We're going to try to implement comparisons by performing
23034 a subtract, then comparing against zero. Unfortunately,
23035 Inf - Inf is NaN which is not zero, and so if we don't
23036 know that the operand is finite and the comparison
23037 would treat EQ different to UNORDERED, we can't do it. */
23038 if (HONOR_INFINITIES (compare_mode
)
23039 && code
!= GT
&& code
!= UNGE
23040 && (GET_CODE (op1
) != CONST_DOUBLE
23041 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1
)))
23042 /* Constructs of the form (a OP b ? a : b) are safe. */
23043 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
23044 || (! rtx_equal_p (op0
, true_cond
)
23045 && ! rtx_equal_p (op1
, true_cond
))))
23048 /* At this point we know we can use fsel. */
23050 /* Reduce the comparison to a comparison against zero. */
23051 if (! is_against_zero
)
23053 temp
= gen_reg_rtx (compare_mode
);
23054 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
23056 op1
= CONST0_RTX (compare_mode
);
23059 /* If we don't care about NaNs we can reduce some of the comparisons
23060 down to faster ones. */
23061 if (! HONOR_NANS (compare_mode
))
23067 true_cond
= false_cond
;
23080 /* Now, reduce everything down to a GE. */
23087 temp
= gen_reg_rtx (compare_mode
);
23088 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
23093 temp
= gen_reg_rtx (compare_mode
);
23094 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
23099 temp
= gen_reg_rtx (compare_mode
);
23100 emit_insn (gen_rtx_SET (temp
,
23101 gen_rtx_NEG (compare_mode
,
23102 gen_rtx_ABS (compare_mode
, op0
))));
23107 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23108 temp
= gen_reg_rtx (result_mode
);
23109 emit_insn (gen_rtx_SET (temp
,
23110 gen_rtx_IF_THEN_ELSE (result_mode
,
23111 gen_rtx_GE (VOIDmode
,
23113 true_cond
, false_cond
)));
23114 false_cond
= true_cond
;
23117 temp
= gen_reg_rtx (compare_mode
);
23118 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
23123 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23124 temp
= gen_reg_rtx (result_mode
);
23125 emit_insn (gen_rtx_SET (temp
,
23126 gen_rtx_IF_THEN_ELSE (result_mode
,
23127 gen_rtx_GE (VOIDmode
,
23129 true_cond
, false_cond
)));
23130 true_cond
= false_cond
;
23133 temp
= gen_reg_rtx (compare_mode
);
23134 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
23139 gcc_unreachable ();
23142 emit_insn (gen_rtx_SET (dest
,
23143 gen_rtx_IF_THEN_ELSE (result_mode
,
23144 gen_rtx_GE (VOIDmode
,
23146 true_cond
, false_cond
)));
23150 /* Same as above, but for ints (isel). */
23153 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
23155 rtx condition_rtx
, cr
;
23156 machine_mode mode
= GET_MODE (dest
);
23157 enum rtx_code cond_code
;
23158 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
23161 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
23164 /* We still have to do the compare, because isel doesn't do a
23165 compare, it just looks at the CRx bits set by a previous compare
23167 condition_rtx
= rs6000_generate_compare (op
, mode
);
23168 cond_code
= GET_CODE (condition_rtx
);
23169 cr
= XEXP (condition_rtx
, 0);
23170 signedp
= GET_MODE (cr
) == CCmode
;
23172 isel_func
= (mode
== SImode
23173 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
23174 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
23178 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
23179 /* isel handles these directly. */
23183 /* We need to swap the sense of the comparison. */
23185 std::swap (false_cond
, true_cond
);
23186 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
23191 false_cond
= force_reg (mode
, false_cond
);
23192 if (true_cond
!= const0_rtx
)
23193 true_cond
= force_reg (mode
, true_cond
);
23195 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
23201 output_isel (rtx
*operands
)
23203 enum rtx_code code
;
23205 code
= GET_CODE (operands
[1]);
23207 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
23209 gcc_assert (GET_CODE (operands
[2]) == REG
23210 && GET_CODE (operands
[3]) == REG
);
23211 PUT_CODE (operands
[1], reverse_condition (code
));
23212 return "isel %0,%3,%2,%j1";
23215 return "isel %0,%2,%3,%j1";
23219 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
23221 machine_mode mode
= GET_MODE (op0
);
23225 /* VSX/altivec have direct min/max insns. */
23226 if ((code
== SMAX
|| code
== SMIN
)
23227 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
23228 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
23230 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
23234 if (code
== SMAX
|| code
== SMIN
)
23239 if (code
== SMAX
|| code
== UMAX
)
23240 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
23241 op0
, op1
, mode
, 0);
23243 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
23244 op1
, op0
, mode
, 0);
23245 gcc_assert (target
);
23246 if (target
!= dest
)
23247 emit_move_insn (dest
, target
);
23250 /* Split a signbit operation on 64-bit machines with direct move. Also allow
23251 for the value to come from memory or if it is already loaded into a GPR. */
23254 rs6000_split_signbit (rtx dest
, rtx src
)
23256 machine_mode d_mode
= GET_MODE (dest
);
23257 machine_mode s_mode
= GET_MODE (src
);
23258 rtx dest_di
= (d_mode
== DImode
) ? dest
: gen_lowpart (DImode
, dest
);
23259 rtx shift_reg
= dest_di
;
23261 gcc_assert (FLOAT128_IEEE_P (s_mode
) && TARGET_POWERPC64
);
23265 rtx mem
= (WORDS_BIG_ENDIAN
23266 ? adjust_address (src
, DImode
, 0)
23267 : adjust_address (src
, DImode
, 8));
23268 emit_insn (gen_rtx_SET (dest_di
, mem
));
23273 unsigned int r
= reg_or_subregno (src
);
23275 if (INT_REGNO_P (r
))
23276 shift_reg
= gen_rtx_REG (DImode
, r
+ (BYTES_BIG_ENDIAN
== 0));
23280 /* Generate the special mfvsrd instruction to get it in a GPR. */
23281 gcc_assert (VSX_REGNO_P (r
));
23282 if (s_mode
== KFmode
)
23283 emit_insn (gen_signbitkf2_dm2 (dest_di
, src
));
23285 emit_insn (gen_signbittf2_dm2 (dest_di
, src
));
23289 emit_insn (gen_lshrdi3 (dest_di
, shift_reg
, GEN_INT (63)));
23293 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23294 COND is true. Mark the jump as unlikely to be taken. */
23297 emit_unlikely_jump (rtx cond
, rtx label
)
23299 rtx x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
23300 rtx_insn
*insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
23301 add_reg_br_prob_note (insn
, profile_probability::very_unlikely ());
23304 /* A subroutine of the atomic operation splitters. Emit a load-locked
23305 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23306 the zero_extend operation. */
23309 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
23311 rtx (*fn
) (rtx
, rtx
) = NULL
;
23316 fn
= gen_load_lockedqi
;
23319 fn
= gen_load_lockedhi
;
23322 if (GET_MODE (mem
) == QImode
)
23323 fn
= gen_load_lockedqi_si
;
23324 else if (GET_MODE (mem
) == HImode
)
23325 fn
= gen_load_lockedhi_si
;
23327 fn
= gen_load_lockedsi
;
23330 fn
= gen_load_lockeddi
;
23333 fn
= gen_load_lockedti
;
23336 gcc_unreachable ();
23338 emit_insn (fn (reg
, mem
));
23341 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23342 instruction in MODE. */
23345 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
23347 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
23352 fn
= gen_store_conditionalqi
;
23355 fn
= gen_store_conditionalhi
;
23358 fn
= gen_store_conditionalsi
;
23361 fn
= gen_store_conditionaldi
;
23364 fn
= gen_store_conditionalti
;
23367 gcc_unreachable ();
23370 /* Emit sync before stwcx. to address PPC405 Erratum. */
23371 if (PPC405_ERRATUM77
)
23372 emit_insn (gen_hwsync ());
23374 emit_insn (fn (res
, mem
, val
));
23377 /* Expand barriers before and after a load_locked/store_cond sequence. */
23380 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
23382 rtx addr
= XEXP (mem
, 0);
23384 if (!legitimate_indirect_address_p (addr
, reload_completed
)
23385 && !legitimate_indexed_address_p (addr
, reload_completed
))
23387 addr
= force_reg (Pmode
, addr
);
23388 mem
= replace_equiv_address_nv (mem
, addr
);
23393 case MEMMODEL_RELAXED
:
23394 case MEMMODEL_CONSUME
:
23395 case MEMMODEL_ACQUIRE
:
23397 case MEMMODEL_RELEASE
:
23398 case MEMMODEL_ACQ_REL
:
23399 emit_insn (gen_lwsync ());
23401 case MEMMODEL_SEQ_CST
:
23402 emit_insn (gen_hwsync ());
23405 gcc_unreachable ();
23411 rs6000_post_atomic_barrier (enum memmodel model
)
23415 case MEMMODEL_RELAXED
:
23416 case MEMMODEL_CONSUME
:
23417 case MEMMODEL_RELEASE
:
23419 case MEMMODEL_ACQUIRE
:
23420 case MEMMODEL_ACQ_REL
:
23421 case MEMMODEL_SEQ_CST
:
23422 emit_insn (gen_isync ());
23425 gcc_unreachable ();
23429 /* A subroutine of the various atomic expanders. For sub-word operations,
23430 we must adjust things to operate on SImode. Given the original MEM,
23431 return a new aligned memory. Also build and return the quantities by
23432 which to shift and mask. */
23435 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
23437 rtx addr
, align
, shift
, mask
, mem
;
23438 HOST_WIDE_INT shift_mask
;
23439 machine_mode mode
= GET_MODE (orig_mem
);
23441 /* For smaller modes, we have to implement this via SImode. */
23442 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
23444 addr
= XEXP (orig_mem
, 0);
23445 addr
= force_reg (GET_MODE (addr
), addr
);
23447 /* Aligned memory containing subword. Generate a new memory. We
23448 do not want any of the existing MEM_ATTR data, as we're now
23449 accessing memory outside the original object. */
23450 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
23451 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23452 mem
= gen_rtx_MEM (SImode
, align
);
23453 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
23454 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
23455 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
23457 /* Shift amount for subword relative to aligned word. */
23458 shift
= gen_reg_rtx (SImode
);
23459 addr
= gen_lowpart (SImode
, addr
);
23460 rtx tmp
= gen_reg_rtx (SImode
);
23461 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
23462 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
23463 if (BYTES_BIG_ENDIAN
)
23464 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
23465 shift
, 1, OPTAB_LIB_WIDEN
);
23468 /* Mask for insertion. */
23469 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
23470 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23476 /* A subroutine of the various atomic expanders. For sub-word operands,
23477 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23480 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
23484 x
= gen_reg_rtx (SImode
);
23485 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
23486 gen_rtx_NOT (SImode
, mask
),
23489 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
23494 /* A subroutine of the various atomic expanders. For sub-word operands,
23495 extract WIDE to NARROW via SHIFT. */
23498 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
23500 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
23501 wide
, 1, OPTAB_LIB_WIDEN
);
23502 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
23505 /* Expand an atomic compare and swap operation. */
23508 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
23510 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
23511 rtx label1
, label2
, x
, mask
, shift
;
23512 machine_mode mode
, orig_mode
;
23513 enum memmodel mod_s
, mod_f
;
23516 boolval
= operands
[0];
23517 retval
= operands
[1];
23519 oldval
= operands
[3];
23520 newval
= operands
[4];
23521 is_weak
= (INTVAL (operands
[5]) != 0);
23522 mod_s
= memmodel_base (INTVAL (operands
[6]));
23523 mod_f
= memmodel_base (INTVAL (operands
[7]));
23524 orig_mode
= mode
= GET_MODE (mem
);
23526 mask
= shift
= NULL_RTX
;
23527 if (mode
== QImode
|| mode
== HImode
)
23529 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23530 lwarx and shift/mask operations. With power8, we need to do the
23531 comparison in SImode, but the store is still done in QI/HImode. */
23532 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
23534 if (!TARGET_SYNC_HI_QI
)
23536 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23538 /* Shift and mask OLDVAL into position with the word. */
23539 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
23540 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23542 /* Shift and mask NEWVAL into position within the word. */
23543 newval
= convert_modes (SImode
, mode
, newval
, 1);
23544 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
23545 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23548 /* Prepare to adjust the return value. */
23549 retval
= gen_reg_rtx (SImode
);
23552 else if (reg_overlap_mentioned_p (retval
, oldval
))
23553 oldval
= copy_to_reg (oldval
);
23555 if (mode
!= TImode
&& !reg_or_short_operand (oldval
, mode
))
23556 oldval
= copy_to_mode_reg (mode
, oldval
);
23558 if (reg_overlap_mentioned_p (retval
, newval
))
23559 newval
= copy_to_reg (newval
);
23561 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
23566 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23567 emit_label (XEXP (label1
, 0));
23569 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23571 emit_load_locked (mode
, retval
, mem
);
23575 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
23576 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23578 cond
= gen_reg_rtx (CCmode
);
23579 /* If we have TImode, synthesize a comparison. */
23580 if (mode
!= TImode
)
23581 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
23584 rtx xor1_result
= gen_reg_rtx (DImode
);
23585 rtx xor2_result
= gen_reg_rtx (DImode
);
23586 rtx or_result
= gen_reg_rtx (DImode
);
23587 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
23588 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
23589 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
23590 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
23592 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
23593 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
23594 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
23595 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
23598 emit_insn (gen_rtx_SET (cond
, x
));
23600 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23601 emit_unlikely_jump (x
, label2
);
23605 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
23607 emit_store_conditional (orig_mode
, cond
, mem
, x
);
23611 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23612 emit_unlikely_jump (x
, label1
);
23615 if (!is_mm_relaxed (mod_f
))
23616 emit_label (XEXP (label2
, 0));
23618 rs6000_post_atomic_barrier (mod_s
);
23620 if (is_mm_relaxed (mod_f
))
23621 emit_label (XEXP (label2
, 0));
23624 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
23625 else if (mode
!= GET_MODE (operands
[1]))
23626 convert_move (operands
[1], retval
, 1);
23628 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23629 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
23630 emit_insn (gen_rtx_SET (boolval
, x
));
23633 /* Expand an atomic exchange operation. */
23636 rs6000_expand_atomic_exchange (rtx operands
[])
23638 rtx retval
, mem
, val
, cond
;
23640 enum memmodel model
;
23641 rtx label
, x
, mask
, shift
;
23643 retval
= operands
[0];
23646 model
= memmodel_base (INTVAL (operands
[3]));
23647 mode
= GET_MODE (mem
);
23649 mask
= shift
= NULL_RTX
;
23650 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
23652 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23654 /* Shift and mask VAL into position with the word. */
23655 val
= convert_modes (SImode
, mode
, val
, 1);
23656 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23657 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23659 /* Prepare to adjust the return value. */
23660 retval
= gen_reg_rtx (SImode
);
23664 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23666 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23667 emit_label (XEXP (label
, 0));
23669 emit_load_locked (mode
, retval
, mem
);
23673 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
23675 cond
= gen_reg_rtx (CCmode
);
23676 emit_store_conditional (mode
, cond
, mem
, x
);
23678 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23679 emit_unlikely_jump (x
, label
);
23681 rs6000_post_atomic_barrier (model
);
23684 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
23687 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23688 to perform. MEM is the memory on which to operate. VAL is the second
23689 operand of the binary operator. BEFORE and AFTER are optional locations to
23690 return the value of MEM either before of after the operation. MODEL_RTX
23691 is a CONST_INT containing the memory model to use. */
23694 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
23695 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
23697 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
23698 machine_mode mode
= GET_MODE (mem
);
23699 machine_mode store_mode
= mode
;
23700 rtx label
, x
, cond
, mask
, shift
;
23701 rtx before
= orig_before
, after
= orig_after
;
23703 mask
= shift
= NULL_RTX
;
23704 /* On power8, we want to use SImode for the operation. On previous systems,
23705 use the operation in a subword and shift/mask to get the proper byte or
23707 if (mode
== QImode
|| mode
== HImode
)
23709 if (TARGET_SYNC_HI_QI
)
23711 val
= convert_modes (SImode
, mode
, val
, 1);
23713 /* Prepare to adjust the return value. */
23714 before
= gen_reg_rtx (SImode
);
23716 after
= gen_reg_rtx (SImode
);
23721 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23723 /* Shift and mask VAL into position with the word. */
23724 val
= convert_modes (SImode
, mode
, val
, 1);
23725 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23726 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23732 /* We've already zero-extended VAL. That is sufficient to
23733 make certain that it does not affect other bits. */
23738 /* If we make certain that all of the other bits in VAL are
23739 set, that will be sufficient to not affect other bits. */
23740 x
= gen_rtx_NOT (SImode
, mask
);
23741 x
= gen_rtx_IOR (SImode
, x
, val
);
23742 emit_insn (gen_rtx_SET (val
, x
));
23749 /* These will all affect bits outside the field and need
23750 adjustment via MASK within the loop. */
23754 gcc_unreachable ();
23757 /* Prepare to adjust the return value. */
23758 before
= gen_reg_rtx (SImode
);
23760 after
= gen_reg_rtx (SImode
);
23761 store_mode
= mode
= SImode
;
23765 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23767 label
= gen_label_rtx ();
23768 emit_label (label
);
23769 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
23771 if (before
== NULL_RTX
)
23772 before
= gen_reg_rtx (mode
);
23774 emit_load_locked (mode
, before
, mem
);
23778 x
= expand_simple_binop (mode
, AND
, before
, val
,
23779 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23780 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
23784 after
= expand_simple_binop (mode
, code
, before
, val
,
23785 after
, 1, OPTAB_LIB_WIDEN
);
23791 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
23792 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23793 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
23795 else if (store_mode
!= mode
)
23796 x
= convert_modes (store_mode
, mode
, x
, 1);
23798 cond
= gen_reg_rtx (CCmode
);
23799 emit_store_conditional (store_mode
, cond
, mem
, x
);
23801 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23802 emit_unlikely_jump (x
, label
);
23804 rs6000_post_atomic_barrier (model
);
23808 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23809 then do the calcuations in a SImode register. */
23811 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
23813 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
23815 else if (store_mode
!= mode
)
23817 /* QImode/HImode on machines with lbarx/lharx where we do the native
23818 operation and then do the calcuations in a SImode register. */
23820 convert_move (orig_before
, before
, 1);
23822 convert_move (orig_after
, after
, 1);
23824 else if (orig_after
&& after
!= orig_after
)
23825 emit_move_insn (orig_after
, after
);
23828 /* Emit instructions to move SRC to DST. Called by splitters for
23829 multi-register moves. It will emit at most one instruction for
23830 each register that is accessed; that is, it won't emit li/lis pairs
23831 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23835 rs6000_split_multireg_move (rtx dst
, rtx src
)
23837 /* The register number of the first register being moved. */
23839 /* The mode that is to be moved. */
23841 /* The mode that the move is being done in, and its size. */
23842 machine_mode reg_mode
;
23844 /* The number of registers that will be moved. */
23847 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
23848 mode
= GET_MODE (dst
);
23849 nregs
= hard_regno_nregs
[reg
][mode
];
23850 if (FP_REGNO_P (reg
))
23851 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
23852 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
23853 else if (ALTIVEC_REGNO_P (reg
))
23854 reg_mode
= V16QImode
;
23856 reg_mode
= word_mode
;
23857 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
23859 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
23861 /* TDmode residing in FP registers is special, since the ISA requires that
23862 the lower-numbered word of a register pair is always the most significant
23863 word, even in little-endian mode. This does not match the usual subreg
23864 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23865 the appropriate constituent registers "by hand" in little-endian mode.
23867 Note we do not need to check for destructive overlap here since TDmode
23868 can only reside in even/odd register pairs. */
23869 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
23874 for (i
= 0; i
< nregs
; i
++)
23876 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
23877 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
23879 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
23880 i
* reg_mode_size
);
23882 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
23883 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
23885 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
23886 i
* reg_mode_size
);
23888 emit_insn (gen_rtx_SET (p_dst
, p_src
));
23894 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
23896 /* Move register range backwards, if we might have destructive
23899 for (i
= nregs
- 1; i
>= 0; i
--)
23900 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
23901 i
* reg_mode_size
),
23902 simplify_gen_subreg (reg_mode
, src
, mode
,
23903 i
* reg_mode_size
)));
23909 bool used_update
= false;
23910 rtx restore_basereg
= NULL_RTX
;
23912 if (MEM_P (src
) && INT_REGNO_P (reg
))
23916 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
23917 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
23920 breg
= XEXP (XEXP (src
, 0), 0);
23921 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
23922 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
23923 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
23924 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23925 src
= replace_equiv_address (src
, breg
);
23927 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
23929 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
23931 rtx basereg
= XEXP (XEXP (src
, 0), 0);
23934 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
23935 emit_insn (gen_rtx_SET (ndst
,
23936 gen_rtx_MEM (reg_mode
,
23938 used_update
= true;
23941 emit_insn (gen_rtx_SET (basereg
,
23942 XEXP (XEXP (src
, 0), 1)));
23943 src
= replace_equiv_address (src
, basereg
);
23947 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
23948 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
23949 src
= replace_equiv_address (src
, basereg
);
23953 breg
= XEXP (src
, 0);
23954 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
23955 breg
= XEXP (breg
, 0);
23957 /* If the base register we are using to address memory is
23958 also a destination reg, then change that register last. */
23960 && REGNO (breg
) >= REGNO (dst
)
23961 && REGNO (breg
) < REGNO (dst
) + nregs
)
23962 j
= REGNO (breg
) - REGNO (dst
);
23964 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
23968 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
23969 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
23972 breg
= XEXP (XEXP (dst
, 0), 0);
23973 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
23974 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
23975 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
23977 /* We have to update the breg before doing the store.
23978 Use store with update, if available. */
23982 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
23983 emit_insn (TARGET_32BIT
23984 ? (TARGET_POWERPC64
23985 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
23986 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
23987 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
23988 used_update
= true;
23991 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23992 dst
= replace_equiv_address (dst
, breg
);
23994 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
23995 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
23997 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
23999 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
24002 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
24003 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
24006 used_update
= true;
24009 emit_insn (gen_rtx_SET (basereg
,
24010 XEXP (XEXP (dst
, 0), 1)));
24011 dst
= replace_equiv_address (dst
, basereg
);
24015 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
24016 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
24017 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
24019 && REG_P (offsetreg
)
24020 && REGNO (basereg
) != REGNO (offsetreg
));
24021 if (REGNO (basereg
) == 0)
24023 rtx tmp
= offsetreg
;
24024 offsetreg
= basereg
;
24027 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
24028 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
24029 dst
= replace_equiv_address (dst
, basereg
);
24032 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
24033 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
24036 for (i
= 0; i
< nregs
; i
++)
24038 /* Calculate index to next subword. */
24043 /* If compiler already emitted move of first word by
24044 store with update, no need to do anything. */
24045 if (j
== 0 && used_update
)
24048 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
24049 j
* reg_mode_size
),
24050 simplify_gen_subreg (reg_mode
, src
, mode
,
24051 j
* reg_mode_size
)));
24053 if (restore_basereg
!= NULL_RTX
)
24054 emit_insn (restore_basereg
);
24059 /* This page contains routines that are used to determine what the
24060 function prologue and epilogue code will do and write them out. */
24062 /* Determine whether the REG is really used. */
24065 save_reg_p (int reg
)
24067 /* We need to mark the PIC offset register live for the same conditions
24068 as it is set up, or otherwise it won't be saved before we clobber it. */
24070 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
&& !TARGET_SINGLE_PIC_BASE
)
24072 /* When calling eh_return, we must return true for all the cases
24073 where conditional_register_usage marks the PIC offset reg
24075 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
24076 && (crtl
->calls_eh_return
24077 || df_regs_ever_live_p (reg
)
24078 || !constant_pool_empty_p ()))
24081 if ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
24086 return !call_used_regs
[reg
] && df_regs_ever_live_p (reg
);
24089 /* Return the first fixed-point register that is required to be
24090 saved. 32 if none. */
24093 first_reg_to_save (void)
24097 /* Find lowest numbered live register. */
24098 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
24099 if (save_reg_p (first_reg
))
24104 && crtl
->uses_pic_offset_table
24105 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
24106 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
24112 /* Similar, for FP regs. */
24115 first_fp_reg_to_save (void)
24119 /* Find lowest numbered live register. */
24120 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
24121 if (save_reg_p (first_reg
))
24127 /* Similar, for AltiVec regs. */
24130 first_altivec_reg_to_save (void)
24134 /* Stack frame remains as is unless we are in AltiVec ABI. */
24135 if (! TARGET_ALTIVEC_ABI
)
24136 return LAST_ALTIVEC_REGNO
+ 1;
24138 /* On Darwin, the unwind routines are compiled without
24139 TARGET_ALTIVEC, and use save_world to save/restore the
24140 altivec registers when necessary. */
24141 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
24142 && ! TARGET_ALTIVEC
)
24143 return FIRST_ALTIVEC_REGNO
+ 20;
24145 /* Find lowest numbered live register. */
24146 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24147 if (save_reg_p (i
))
24153 /* Return a 32-bit mask of the AltiVec registers we need to set in
24154 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24155 the 32-bit word is 0. */
24157 static unsigned int
24158 compute_vrsave_mask (void)
24160 unsigned int i
, mask
= 0;
24162 /* On Darwin, the unwind routines are compiled without
24163 TARGET_ALTIVEC, and use save_world to save/restore the
24164 call-saved altivec registers when necessary. */
24165 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
24166 && ! TARGET_ALTIVEC
)
24169 /* First, find out if we use _any_ altivec registers. */
24170 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24171 if (df_regs_ever_live_p (i
))
24172 mask
|= ALTIVEC_REG_BIT (i
);
24177 /* Next, remove the argument registers from the set. These must
24178 be in the VRSAVE mask set by the caller, so we don't need to add
24179 them in again. More importantly, the mask we compute here is
24180 used to generate CLOBBERs in the set_vrsave insn, and we do not
24181 wish the argument registers to die. */
24182 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
24183 mask
&= ~ALTIVEC_REG_BIT (i
);
24185 /* Similarly, remove the return value from the set. */
24188 diddle_return_value (is_altivec_return_reg
, &yes
);
24190 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
24196 /* For a very restricted set of circumstances, we can cut down the
24197 size of prologues/epilogues by calling our own save/restore-the-world
24201 compute_save_world_info (rs6000_stack_t
*info
)
24203 info
->world_save_p
= 1;
24205 = (WORLD_SAVE_P (info
)
24206 && DEFAULT_ABI
== ABI_DARWIN
24207 && !cfun
->has_nonlocal_label
24208 && info
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
24209 && info
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
24210 && info
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
24211 && info
->cr_save_p
);
24213 /* This will not work in conjunction with sibcalls. Make sure there
24214 are none. (This check is expensive, but seldom executed.) */
24215 if (WORLD_SAVE_P (info
))
24218 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
24219 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
24221 info
->world_save_p
= 0;
24226 if (WORLD_SAVE_P (info
))
24228 /* Even if we're not touching VRsave, make sure there's room on the
24229 stack for it, if it looks like we're calling SAVE_WORLD, which
24230 will attempt to save it. */
24231 info
->vrsave_size
= 4;
24233 /* If we are going to save the world, we need to save the link register too. */
24234 info
->lr_save_p
= 1;
24236 /* "Save" the VRsave register too if we're saving the world. */
24237 if (info
->vrsave_mask
== 0)
24238 info
->vrsave_mask
= compute_vrsave_mask ();
24240 /* Because the Darwin register save/restore routines only handle
24241 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24243 gcc_assert (info
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
24244 && (info
->first_altivec_reg_save
24245 >= FIRST_SAVED_ALTIVEC_REGNO
));
24253 is_altivec_return_reg (rtx reg
, void *xyes
)
24255 bool *yes
= (bool *) xyes
;
24256 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
24261 /* Return whether REG is a global user reg or has been specifed by
24262 -ffixed-REG. We should not restore these, and so cannot use
24263 lmw or out-of-line restore functions if there are any. We also
24264 can't save them (well, emit frame notes for them), because frame
24265 unwinding during exception handling will restore saved registers. */
24268 fixed_reg_p (int reg
)
24270 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24271 backend sets it, overriding anything the user might have given. */
24272 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
24273 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
)
24274 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
24275 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
24278 return fixed_regs
[reg
];
24281 /* Determine the strategy for savings/restoring registers. */
24284 SAVE_MULTIPLE
= 0x1,
24285 SAVE_INLINE_GPRS
= 0x2,
24286 SAVE_INLINE_FPRS
= 0x4,
24287 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x8,
24288 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x10,
24289 SAVE_INLINE_VRS
= 0x20,
24290 REST_MULTIPLE
= 0x100,
24291 REST_INLINE_GPRS
= 0x200,
24292 REST_INLINE_FPRS
= 0x400,
24293 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x800,
24294 REST_INLINE_VRS
= 0x1000
24298 rs6000_savres_strategy (rs6000_stack_t
*info
,
24299 bool using_static_chain_p
)
24303 /* Select between in-line and out-of-line save and restore of regs.
24304 First, all the obvious cases where we don't use out-of-line. */
24305 if (crtl
->calls_eh_return
24306 || cfun
->machine
->ra_need_lr
)
24307 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
24308 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
24309 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
24311 if (info
->first_gp_reg_save
== 32)
24312 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24314 if (info
->first_fp_reg_save
== 64
24315 /* The out-of-line FP routines use double-precision stores;
24316 we can't use those routines if we don't have such stores. */
24317 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
))
24318 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24320 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1)
24321 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24323 /* Define cutoff for using out-of-line functions to save registers. */
24324 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
24326 if (!optimize_size
)
24328 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24329 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24330 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24334 /* Prefer out-of-line restore if it will exit. */
24335 if (info
->first_fp_reg_save
> 61)
24336 strategy
|= SAVE_INLINE_FPRS
;
24337 if (info
->first_gp_reg_save
> 29)
24339 if (info
->first_fp_reg_save
== 64)
24340 strategy
|= SAVE_INLINE_GPRS
;
24342 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24344 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
24345 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24348 else if (DEFAULT_ABI
== ABI_DARWIN
)
24350 if (info
->first_fp_reg_save
> 60)
24351 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24352 if (info
->first_gp_reg_save
> 29)
24353 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24354 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24358 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
24359 if ((flag_shrink_wrap_separate
&& optimize_function_for_speed_p (cfun
))
24360 || info
->first_fp_reg_save
> 61)
24361 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24362 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24363 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24366 /* Don't bother to try to save things out-of-line if r11 is occupied
24367 by the static chain. It would require too much fiddling and the
24368 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24369 pointer on Darwin, and AIX uses r1 or r12. */
24370 if (using_static_chain_p
24371 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
24372 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
24374 | SAVE_INLINE_VRS
);
24376 /* Don't ever restore fixed regs. That means we can't use the
24377 out-of-line register restore functions if a fixed reg is in the
24378 range of regs restored. */
24379 if (!(strategy
& REST_INLINE_FPRS
))
24380 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
24383 strategy
|= REST_INLINE_FPRS
;
24387 /* We can only use the out-of-line routines to restore fprs if we've
24388 saved all the registers from first_fp_reg_save in the prologue.
24389 Otherwise, we risk loading garbage. Of course, if we have saved
24390 out-of-line then we know we haven't skipped any fprs. */
24391 if ((strategy
& SAVE_INLINE_FPRS
)
24392 && !(strategy
& REST_INLINE_FPRS
))
24393 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
24394 if (!save_reg_p (i
))
24396 strategy
|= REST_INLINE_FPRS
;
24400 /* Similarly, for altivec regs. */
24401 if (!(strategy
& REST_INLINE_VRS
))
24402 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
24405 strategy
|= REST_INLINE_VRS
;
24409 if ((strategy
& SAVE_INLINE_VRS
)
24410 && !(strategy
& REST_INLINE_VRS
))
24411 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
24412 if (!save_reg_p (i
))
24414 strategy
|= REST_INLINE_VRS
;
24418 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24419 saved is an out-of-line save or restore. Set up the value for
24420 the next test (excluding out-of-line gprs). */
24421 bool lr_save_p
= (info
->lr_save_p
24422 || !(strategy
& SAVE_INLINE_FPRS
)
24423 || !(strategy
& SAVE_INLINE_VRS
)
24424 || !(strategy
& REST_INLINE_FPRS
)
24425 || !(strategy
& REST_INLINE_VRS
));
24427 if (TARGET_MULTIPLE
24428 && !TARGET_POWERPC64
24429 && info
->first_gp_reg_save
< 31
24430 && !(flag_shrink_wrap
24431 && flag_shrink_wrap_separate
24432 && optimize_function_for_speed_p (cfun
)))
24435 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24436 if (save_reg_p (i
))
24440 /* Don't use store multiple if only one reg needs to be
24441 saved. This can occur for example when the ABI_V4 pic reg
24442 (r30) needs to be saved to make calls, but r31 is not
24444 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24447 /* Prefer store multiple for saves over out-of-line
24448 routines, since the store-multiple instruction will
24449 always be smaller. */
24450 strategy
|= SAVE_INLINE_GPRS
| SAVE_MULTIPLE
;
24452 /* The situation is more complicated with load multiple.
24453 We'd prefer to use the out-of-line routines for restores,
24454 since the "exit" out-of-line routines can handle the
24455 restore of LR and the frame teardown. However if doesn't
24456 make sense to use the out-of-line routine if that is the
24457 only reason we'd need to save LR, and we can't use the
24458 "exit" out-of-line gpr restore if we have saved some
24459 fprs; In those cases it is advantageous to use load
24460 multiple when available. */
24461 if (info
->first_fp_reg_save
!= 64 || !lr_save_p
)
24462 strategy
|= REST_INLINE_GPRS
| REST_MULTIPLE
;
24466 /* Using the "exit" out-of-line routine does not improve code size
24467 if using it would require lr to be saved and if only saving one
24469 else if (!lr_save_p
&& info
->first_gp_reg_save
> 29)
24470 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24472 /* Don't ever restore fixed regs. */
24473 if ((strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
24474 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24475 if (fixed_reg_p (i
))
24477 strategy
|= REST_INLINE_GPRS
;
24478 strategy
&= ~REST_MULTIPLE
;
24482 /* We can only use load multiple or the out-of-line routines to
24483 restore gprs if we've saved all the registers from
24484 first_gp_reg_save. Otherwise, we risk loading garbage.
24485 Of course, if we have saved out-of-line or used stmw then we know
24486 we haven't skipped any gprs. */
24487 if ((strategy
& (SAVE_INLINE_GPRS
| SAVE_MULTIPLE
)) == SAVE_INLINE_GPRS
24488 && (strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
24489 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24490 if (!save_reg_p (i
))
24492 strategy
|= REST_INLINE_GPRS
;
24493 strategy
&= ~REST_MULTIPLE
;
24497 if (TARGET_ELF
&& TARGET_64BIT
)
24499 if (!(strategy
& SAVE_INLINE_FPRS
))
24500 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24501 else if (!(strategy
& SAVE_INLINE_GPRS
)
24502 && info
->first_fp_reg_save
== 64)
24503 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
24505 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
24506 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
24508 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
24509 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24514 /* Calculate the stack information for the current function. This is
24515 complicated by having two separate calling sequences, the AIX calling
24516 sequence and the V.4 calling sequence.
24518 AIX (and Darwin/Mac OS X) stack frames look like:
24520 SP----> +---------------------------------------+
24521 | back chain to caller | 0 0
24522 +---------------------------------------+
24523 | saved CR | 4 8 (8-11)
24524 +---------------------------------------+
24526 +---------------------------------------+
24527 | reserved for compilers | 12 24
24528 +---------------------------------------+
24529 | reserved for binders | 16 32
24530 +---------------------------------------+
24531 | saved TOC pointer | 20 40
24532 +---------------------------------------+
24533 | Parameter save area (+padding*) (P) | 24 48
24534 +---------------------------------------+
24535 | Alloca space (A) | 24+P etc.
24536 +---------------------------------------+
24537 | Local variable space (L) | 24+P+A
24538 +---------------------------------------+
24539 | Float/int conversion temporary (X) | 24+P+A+L
24540 +---------------------------------------+
24541 | Save area for AltiVec registers (W) | 24+P+A+L+X
24542 +---------------------------------------+
24543 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24544 +---------------------------------------+
24545 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24546 +---------------------------------------+
24547 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24548 +---------------------------------------+
24549 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24550 +---------------------------------------+
24551 old SP->| back chain to caller's caller |
24552 +---------------------------------------+
24554 * If the alloca area is present, the parameter save area is
24555 padded so that the former starts 16-byte aligned.
24557 The required alignment for AIX configurations is two words (i.e., 8
24560 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24562 SP----> +---------------------------------------+
24563 | Back chain to caller | 0
24564 +---------------------------------------+
24565 | Save area for CR | 8
24566 +---------------------------------------+
24568 +---------------------------------------+
24569 | Saved TOC pointer | 24
24570 +---------------------------------------+
24571 | Parameter save area (+padding*) (P) | 32
24572 +---------------------------------------+
24573 | Alloca space (A) | 32+P
24574 +---------------------------------------+
24575 | Local variable space (L) | 32+P+A
24576 +---------------------------------------+
24577 | Save area for AltiVec registers (W) | 32+P+A+L
24578 +---------------------------------------+
24579 | AltiVec alignment padding (Y) | 32+P+A+L+W
24580 +---------------------------------------+
24581 | Save area for GP registers (G) | 32+P+A+L+W+Y
24582 +---------------------------------------+
24583 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24584 +---------------------------------------+
24585 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24586 +---------------------------------------+
24588 * If the alloca area is present, the parameter save area is
24589 padded so that the former starts 16-byte aligned.
24591 V.4 stack frames look like:
24593 SP----> +---------------------------------------+
24594 | back chain to caller | 0
24595 +---------------------------------------+
24596 | caller's saved LR | 4
24597 +---------------------------------------+
24598 | Parameter save area (+padding*) (P) | 8
24599 +---------------------------------------+
24600 | Alloca space (A) | 8+P
24601 +---------------------------------------+
24602 | Varargs save area (V) | 8+P+A
24603 +---------------------------------------+
24604 | Local variable space (L) | 8+P+A+V
24605 +---------------------------------------+
24606 | Float/int conversion temporary (X) | 8+P+A+V+L
24607 +---------------------------------------+
24608 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24609 +---------------------------------------+
24610 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24611 +---------------------------------------+
24612 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24613 +---------------------------------------+
24614 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24615 +---------------------------------------+
24616 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24617 +---------------------------------------+
24618 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24619 +---------------------------------------+
24620 old SP->| back chain to caller's caller |
24621 +---------------------------------------+
24623 * If the alloca area is present and the required alignment is
24624 16 bytes, the parameter save area is padded so that the
24625 alloca area starts 16-byte aligned.
24627 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24628 given. (But note below and in sysv4.h that we require only 8 and
24629 may round up the size of our stack frame anyways. The historical
24630 reason is early versions of powerpc-linux which didn't properly
24631 align the stack at program startup. A happy side-effect is that
24632 -mno-eabi libraries can be used with -meabi programs.)
24634 The EABI configuration defaults to the V.4 layout. However,
24635 the stack alignment requirements may differ. If -mno-eabi is not
24636 given, the required stack alignment is 8 bytes; if -mno-eabi is
24637 given, the required alignment is 16 bytes. (But see V.4 comment
24640 #ifndef ABI_STACK_BOUNDARY
24641 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24644 static rs6000_stack_t
*
24645 rs6000_stack_info (void)
24647 /* We should never be called for thunks, we are not set up for that. */
24648 gcc_assert (!cfun
->is_thunk
);
24650 rs6000_stack_t
*info
= &stack_info
;
24651 int reg_size
= TARGET_32BIT
? 4 : 8;
24656 HOST_WIDE_INT non_fixed_size
;
24657 bool using_static_chain_p
;
24659 if (reload_completed
&& info
->reload_completed
)
24662 memset (info
, 0, sizeof (*info
));
24663 info
->reload_completed
= reload_completed
;
24665 /* Select which calling sequence. */
24666 info
->abi
= DEFAULT_ABI
;
24668 /* Calculate which registers need to be saved & save area size. */
24669 info
->first_gp_reg_save
= first_reg_to_save ();
24670 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24671 even if it currently looks like we won't. Reload may need it to
24672 get at a constant; if so, it will have already created a constant
24673 pool entry for it. */
24674 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
24675 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
24676 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
24677 && crtl
->uses_const_pool
24678 && info
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
24679 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
24681 first_gp
= info
->first_gp_reg_save
;
24683 info
->gp_size
= reg_size
* (32 - first_gp
);
24685 info
->first_fp_reg_save
= first_fp_reg_to_save ();
24686 info
->fp_size
= 8 * (64 - info
->first_fp_reg_save
);
24688 info
->first_altivec_reg_save
= first_altivec_reg_to_save ();
24689 info
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
24690 - info
->first_altivec_reg_save
);
24692 /* Does this function call anything? */
24693 info
->calls_p
= (!crtl
->is_leaf
|| cfun
->machine
->ra_needs_full_frame
);
24695 /* Determine if we need to save the condition code registers. */
24696 if (save_reg_p (CR2_REGNO
)
24697 || save_reg_p (CR3_REGNO
)
24698 || save_reg_p (CR4_REGNO
))
24700 info
->cr_save_p
= 1;
24701 if (DEFAULT_ABI
== ABI_V4
)
24702 info
->cr_size
= reg_size
;
24705 /* If the current function calls __builtin_eh_return, then we need
24706 to allocate stack space for registers that will hold data for
24707 the exception handler. */
24708 if (crtl
->calls_eh_return
)
24711 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
24714 ehrd_size
= i
* UNITS_PER_WORD
;
24719 /* In the ELFv2 ABI, we also need to allocate space for separate
24720 CR field save areas if the function calls __builtin_eh_return. */
24721 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24723 /* This hard-codes that we have three call-saved CR fields. */
24724 ehcr_size
= 3 * reg_size
;
24725 /* We do *not* use the regular CR save mechanism. */
24726 info
->cr_save_p
= 0;
24731 /* Determine various sizes. */
24732 info
->reg_size
= reg_size
;
24733 info
->fixed_size
= RS6000_SAVE_AREA
;
24734 info
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
24735 if (cfun
->calls_alloca
)
24737 RS6000_ALIGN (crtl
->outgoing_args_size
+ info
->fixed_size
,
24738 STACK_BOUNDARY
/ BITS_PER_UNIT
) - info
->fixed_size
;
24740 info
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
24741 TARGET_ALTIVEC
? 16 : 8);
24742 if (FRAME_GROWS_DOWNWARD
)
24744 += RS6000_ALIGN (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
,
24745 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
24746 - (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
);
24748 if (TARGET_ALTIVEC_ABI
)
24749 info
->vrsave_mask
= compute_vrsave_mask ();
24751 if (TARGET_ALTIVEC_VRSAVE
&& info
->vrsave_mask
)
24752 info
->vrsave_size
= 4;
24754 compute_save_world_info (info
);
24756 /* Calculate the offsets. */
24757 switch (DEFAULT_ABI
)
24761 gcc_unreachable ();
24766 info
->fp_save_offset
= -info
->fp_size
;
24767 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24769 if (TARGET_ALTIVEC_ABI
)
24771 info
->vrsave_save_offset
= info
->gp_save_offset
- info
->vrsave_size
;
24773 /* Align stack so vector save area is on a quadword boundary.
24774 The padding goes above the vectors. */
24775 if (info
->altivec_size
!= 0)
24776 info
->altivec_padding_size
= info
->vrsave_save_offset
& 0xF;
24778 info
->altivec_save_offset
= info
->vrsave_save_offset
24779 - info
->altivec_padding_size
24780 - info
->altivec_size
;
24781 gcc_assert (info
->altivec_size
== 0
24782 || info
->altivec_save_offset
% 16 == 0);
24784 /* Adjust for AltiVec case. */
24785 info
->ehrd_offset
= info
->altivec_save_offset
- ehrd_size
;
24788 info
->ehrd_offset
= info
->gp_save_offset
- ehrd_size
;
24790 info
->ehcr_offset
= info
->ehrd_offset
- ehcr_size
;
24791 info
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
24792 info
->lr_save_offset
= 2*reg_size
;
24796 info
->fp_save_offset
= -info
->fp_size
;
24797 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24798 info
->cr_save_offset
= info
->gp_save_offset
- info
->cr_size
;
24800 if (TARGET_ALTIVEC_ABI
)
24802 info
->vrsave_save_offset
= info
->cr_save_offset
- info
->vrsave_size
;
24804 /* Align stack so vector save area is on a quadword boundary. */
24805 if (info
->altivec_size
!= 0)
24806 info
->altivec_padding_size
= 16 - (-info
->vrsave_save_offset
% 16);
24808 info
->altivec_save_offset
= info
->vrsave_save_offset
24809 - info
->altivec_padding_size
24810 - info
->altivec_size
;
24812 /* Adjust for AltiVec case. */
24813 info
->ehrd_offset
= info
->altivec_save_offset
;
24816 info
->ehrd_offset
= info
->cr_save_offset
;
24818 info
->ehrd_offset
-= ehrd_size
;
24819 info
->lr_save_offset
= reg_size
;
24822 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
24823 info
->save_size
= RS6000_ALIGN (info
->fp_size
24825 + info
->altivec_size
24826 + info
->altivec_padding_size
24830 + info
->vrsave_size
,
24833 non_fixed_size
= info
->vars_size
+ info
->parm_size
+ info
->save_size
;
24835 info
->total_size
= RS6000_ALIGN (non_fixed_size
+ info
->fixed_size
,
24836 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
24838 /* Determine if we need to save the link register. */
24840 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24842 && !TARGET_PROFILE_KERNEL
)
24843 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
24844 #ifdef TARGET_RELOCATABLE
24845 || (DEFAULT_ABI
== ABI_V4
24846 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
24847 && !constant_pool_empty_p ())
24849 || rs6000_ra_ever_killed ())
24850 info
->lr_save_p
= 1;
24852 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
24853 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
24854 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
24855 info
->savres_strategy
= rs6000_savres_strategy (info
, using_static_chain_p
);
24857 if (!(info
->savres_strategy
& SAVE_INLINE_GPRS
)
24858 || !(info
->savres_strategy
& SAVE_INLINE_FPRS
)
24859 || !(info
->savres_strategy
& SAVE_INLINE_VRS
)
24860 || !(info
->savres_strategy
& REST_INLINE_GPRS
)
24861 || !(info
->savres_strategy
& REST_INLINE_FPRS
)
24862 || !(info
->savres_strategy
& REST_INLINE_VRS
))
24863 info
->lr_save_p
= 1;
24865 if (info
->lr_save_p
)
24866 df_set_regs_ever_live (LR_REGNO
, true);
24868 /* Determine if we need to allocate any stack frame:
24870 For AIX we need to push the stack if a frame pointer is needed
24871 (because the stack might be dynamically adjusted), if we are
24872 debugging, if we make calls, or if the sum of fp_save, gp_save,
24873 and local variables are more than the space needed to save all
24874 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24875 + 18*8 = 288 (GPR13 reserved).
24877 For V.4 we don't have the stack cushion that AIX uses, but assume
24878 that the debugger can handle stackless frames. */
24883 else if (DEFAULT_ABI
== ABI_V4
)
24884 info
->push_p
= non_fixed_size
!= 0;
24886 else if (frame_pointer_needed
)
24889 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
24893 info
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
24899 debug_stack_info (rs6000_stack_t
*info
)
24901 const char *abi_string
;
24904 info
= rs6000_stack_info ();
24906 fprintf (stderr
, "\nStack information for function %s:\n",
24907 ((current_function_decl
&& DECL_NAME (current_function_decl
))
24908 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
24913 default: abi_string
= "Unknown"; break;
24914 case ABI_NONE
: abi_string
= "NONE"; break;
24915 case ABI_AIX
: abi_string
= "AIX"; break;
24916 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
24917 case ABI_DARWIN
: abi_string
= "Darwin"; break;
24918 case ABI_V4
: abi_string
= "V.4"; break;
24921 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
24923 if (TARGET_ALTIVEC_ABI
)
24924 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
24926 if (info
->first_gp_reg_save
!= 32)
24927 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
24929 if (info
->first_fp_reg_save
!= 64)
24930 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
24932 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
24933 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
24934 info
->first_altivec_reg_save
);
24936 if (info
->lr_save_p
)
24937 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
24939 if (info
->cr_save_p
)
24940 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
24942 if (info
->vrsave_mask
)
24943 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
24946 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
24949 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
24952 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
24955 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
24957 if (info
->altivec_size
)
24958 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
24959 info
->altivec_save_offset
);
24961 if (info
->vrsave_size
)
24962 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
24963 info
->vrsave_save_offset
);
24965 if (info
->lr_save_p
)
24966 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
24968 if (info
->cr_save_p
)
24969 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
24971 if (info
->varargs_save_offset
)
24972 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
24974 if (info
->total_size
)
24975 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
24978 if (info
->vars_size
)
24979 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
24982 if (info
->parm_size
)
24983 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
24985 if (info
->fixed_size
)
24986 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
24989 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
24992 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
24994 if (info
->altivec_size
)
24995 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
24997 if (info
->vrsave_size
)
24998 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
25000 if (info
->altivec_padding_size
)
25001 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
25002 info
->altivec_padding_size
);
25005 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
25007 if (info
->save_size
)
25008 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
25010 if (info
->reg_size
!= 4)
25011 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
25013 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
25015 fprintf (stderr
, "\n");
25019 rs6000_return_addr (int count
, rtx frame
)
25021 /* Currently we don't optimize very well between prolog and body
25022 code and for PIC code the code can be actually quite bad, so
25023 don't try to be too clever here. */
25025 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
25027 cfun
->machine
->ra_needs_full_frame
= 1;
25034 plus_constant (Pmode
,
25036 (gen_rtx_MEM (Pmode
,
25037 memory_address (Pmode
, frame
))),
25038 RETURN_ADDRESS_OFFSET
)));
25041 cfun
->machine
->ra_need_lr
= 1;
25042 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
25045 /* Say whether a function is a candidate for sibcall handling or not. */
25048 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
25053 fntype
= TREE_TYPE (decl
);
25055 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
25057 /* We can't do it if the called function has more vector parameters
25058 than the current function; there's nowhere to put the VRsave code. */
25059 if (TARGET_ALTIVEC_ABI
25060 && TARGET_ALTIVEC_VRSAVE
25061 && !(decl
&& decl
== current_function_decl
))
25063 function_args_iterator args_iter
;
25067 /* Functions with vector parameters are required to have a
25068 prototype, so the argument type info must be available
25070 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
25071 if (TREE_CODE (type
) == VECTOR_TYPE
25072 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
25075 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
25076 if (TREE_CODE (type
) == VECTOR_TYPE
25077 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
25084 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25085 functions, because the callee may have a different TOC pointer to
25086 the caller and there's no way to ensure we restore the TOC when
25087 we return. With the secure-plt SYSV ABI we can't make non-local
25088 calls when -fpic/PIC because the plt call stubs use r30. */
25089 if (DEFAULT_ABI
== ABI_DARWIN
25090 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25092 && !DECL_EXTERNAL (decl
)
25093 && !DECL_WEAK (decl
)
25094 && (*targetm
.binds_local_p
) (decl
))
25095 || (DEFAULT_ABI
== ABI_V4
25096 && (!TARGET_SECURE_PLT
25099 && (*targetm
.binds_local_p
) (decl
)))))
25101 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
25103 if (!lookup_attribute ("longcall", attr_list
)
25104 || lookup_attribute ("shortcall", attr_list
))
25112 rs6000_ra_ever_killed (void)
25118 if (cfun
->is_thunk
)
25121 if (cfun
->machine
->lr_save_state
)
25122 return cfun
->machine
->lr_save_state
- 1;
25124 /* regs_ever_live has LR marked as used if any sibcalls are present,
25125 but this should not force saving and restoring in the
25126 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25127 clobbers LR, so that is inappropriate. */
25129 /* Also, the prologue can generate a store into LR that
25130 doesn't really count, like this:
25133 bcl to set PIC register
25137 When we're called from the epilogue, we need to avoid counting
25138 this as a store. */
25140 push_topmost_sequence ();
25141 top
= get_insns ();
25142 pop_topmost_sequence ();
25143 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
25145 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
25151 if (!SIBLING_CALL_P (insn
))
25154 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
25156 else if (set_of (reg
, insn
) != NULL_RTX
25157 && !prologue_epilogue_contains (insn
))
25164 /* Emit instructions needed to load the TOC register.
25165 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25166 a constant pool; or for SVR4 -fpic. */
25169 rs6000_emit_load_toc_table (int fromprolog
)
25172 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
25174 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
25177 rtx lab
, tmp1
, tmp2
, got
;
25179 lab
= gen_label_rtx ();
25180 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
25181 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25184 got
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25188 got
= rs6000_got_sym ();
25189 tmp1
= tmp2
= dest
;
25192 tmp1
= gen_reg_rtx (Pmode
);
25193 tmp2
= gen_reg_rtx (Pmode
);
25195 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
25196 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
25197 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
25198 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
25200 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
25202 emit_insn (gen_load_toc_v4_pic_si ());
25203 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25205 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
25208 rtx temp0
= (fromprolog
25209 ? gen_rtx_REG (Pmode
, 0)
25210 : gen_reg_rtx (Pmode
));
25216 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
25217 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25219 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
25220 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25222 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
25223 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25224 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
25230 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25232 lab
= gen_label_rtx ();
25233 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
25234 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25235 if (TARGET_LINK_STACK
)
25236 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
25237 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
25239 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
25241 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
25243 /* This is for AIX code running in non-PIC ELF32. */
25244 rtx realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25247 emit_insn (gen_elf_high (dest
, realsym
));
25248 emit_insn (gen_elf_low (dest
, dest
, realsym
));
25252 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
25255 emit_insn (gen_load_toc_aix_si (dest
));
25257 emit_insn (gen_load_toc_aix_di (dest
));
25261 /* Emit instructions to restore the link register after determining where
25262 its value has been stored. */
25265 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
25267 rs6000_stack_t
*info
= rs6000_stack_info ();
25270 operands
[0] = source
;
25271 operands
[1] = scratch
;
25273 if (info
->lr_save_p
)
25275 rtx frame_rtx
= stack_pointer_rtx
;
25276 HOST_WIDE_INT sp_offset
= 0;
25279 if (frame_pointer_needed
25280 || cfun
->calls_alloca
25281 || info
->total_size
> 32767)
25283 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
25284 emit_move_insn (operands
[1], tmp
);
25285 frame_rtx
= operands
[1];
25287 else if (info
->push_p
)
25288 sp_offset
= info
->total_size
;
25290 tmp
= plus_constant (Pmode
, frame_rtx
,
25291 info
->lr_save_offset
+ sp_offset
);
25292 tmp
= gen_frame_mem (Pmode
, tmp
);
25293 emit_move_insn (tmp
, operands
[0]);
25296 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
25298 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25299 state of lr_save_p so any change from here on would be a bug. In
25300 particular, stop rs6000_ra_ever_killed from considering the SET
25301 of lr we may have added just above. */
25302 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
25305 static GTY(()) alias_set_type set
= -1;
25308 get_TOC_alias_set (void)
25311 set
= new_alias_set ();
25315 /* This returns nonzero if the current function uses the TOC. This is
25316 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25317 is generated by the ABI_V4 load_toc_* patterns. */
25324 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
25327 rtx pat
= PATTERN (insn
);
25330 if (GET_CODE (pat
) == PARALLEL
)
25331 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
25333 rtx sub
= XVECEXP (pat
, 0, i
);
25334 if (GET_CODE (sub
) == USE
)
25336 sub
= XEXP (sub
, 0);
25337 if (GET_CODE (sub
) == UNSPEC
25338 && XINT (sub
, 1) == UNSPEC_TOC
)
25348 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
25350 rtx tocrel
, tocreg
, hi
;
25352 if (TARGET_DEBUG_ADDR
)
25354 if (GET_CODE (symbol
) == SYMBOL_REF
)
25355 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25359 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
25360 GET_RTX_NAME (GET_CODE (symbol
)));
25361 debug_rtx (symbol
);
25365 if (!can_create_pseudo_p ())
25366 df_set_regs_ever_live (TOC_REGISTER
, true);
25368 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
25369 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
25370 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
25373 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
25374 if (largetoc_reg
!= NULL
)
25376 emit_move_insn (largetoc_reg
, hi
);
25379 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
25382 /* Issue assembly directives that create a reference to the given DWARF
25383 FRAME_TABLE_LABEL from the current function section. */
25385 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
25387 fprintf (asm_out_file
, "\t.ref %s\n",
25388 (* targetm
.strip_name_encoding
) (frame_table_label
));
25391 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25392 and the change to the stack pointer. */
25395 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
25402 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25403 if (hard_frame_needed
)
25404 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
25405 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
25406 || (hard_frame_needed
25407 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
25410 p
= rtvec_alloc (i
);
25413 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
25414 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
25417 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
25420 /* Emit the correct code for allocating stack space, as insns.
25421 If COPY_REG, make sure a copy of the old frame is left there.
25422 The generated code may use hard register 0 as a temporary. */
25425 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
25428 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25429 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
25430 rtx todec
= gen_int_mode (-size
, Pmode
);
25433 if (INTVAL (todec
) != -size
)
25435 warning (0, "stack frame too large");
25436 emit_insn (gen_trap ());
25440 if (crtl
->limit_stack
)
25442 if (REG_P (stack_limit_rtx
)
25443 && REGNO (stack_limit_rtx
) > 1
25444 && REGNO (stack_limit_rtx
) <= 31)
25447 = gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
));
25450 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
, const0_rtx
));
25452 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
25454 && DEFAULT_ABI
== ABI_V4
25457 rtx toload
= gen_rtx_CONST (VOIDmode
,
25458 gen_rtx_PLUS (Pmode
,
25462 emit_insn (gen_elf_high (tmp_reg
, toload
));
25463 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
25464 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
25468 warning (0, "stack limit expression is not supported");
25474 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
25476 emit_move_insn (copy_reg
, stack_reg
);
25481 /* Need a note here so that try_split doesn't get confused. */
25482 if (get_last_insn () == NULL_RTX
)
25483 emit_note (NOTE_INSN_DELETED
);
25484 insn
= emit_move_insn (tmp_reg
, todec
);
25485 try_split (PATTERN (insn
), insn
, 0);
25489 insn
= emit_insn (TARGET_32BIT
25490 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
25492 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
25493 todec
, stack_reg
));
25494 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25495 it now and set the alias set/attributes. The above gen_*_update
25496 calls will generate a PARALLEL with the MEM set being the first
25498 par
= PATTERN (insn
);
25499 gcc_assert (GET_CODE (par
) == PARALLEL
);
25500 set
= XVECEXP (par
, 0, 0);
25501 gcc_assert (GET_CODE (set
) == SET
);
25502 mem
= SET_DEST (set
);
25503 gcc_assert (MEM_P (mem
));
25504 MEM_NOTRAP_P (mem
) = 1;
25505 set_mem_alias_set (mem
, get_frame_alias_set ());
25507 RTX_FRAME_RELATED_P (insn
) = 1;
25508 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25509 gen_rtx_SET (stack_reg
, gen_rtx_PLUS (Pmode
, stack_reg
,
25510 GEN_INT (-size
))));
25514 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25516 #if PROBE_INTERVAL > 32768
25517 #error Cannot use indexed addressing mode for stack probing
25520 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25521 inclusive. These are offsets from the current stack pointer. */
25524 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
25526 /* See if we have a constant small number of probes to generate. If so,
25527 that's the easy case. */
25528 if (first
+ size
<= 32768)
25532 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25533 it exceeds SIZE. If only one probe is needed, this will not
25534 generate any code. Then probe at FIRST + SIZE. */
25535 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
25536 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25539 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25543 /* Otherwise, do the same as above, but in a loop. Note that we must be
25544 extra careful with variables wrapping around because we might be at
25545 the very top (or the very bottom) of the address space and we have
25546 to be able to handle this case properly; in particular, we use an
25547 equality test for the loop condition. */
25550 HOST_WIDE_INT rounded_size
;
25551 rtx r12
= gen_rtx_REG (Pmode
, 12);
25552 rtx r0
= gen_rtx_REG (Pmode
, 0);
25554 /* Sanity check for the addressing mode we're going to use. */
25555 gcc_assert (first
<= 32768);
25557 /* Step 1: round SIZE to the previous multiple of the interval. */
25559 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
25562 /* Step 2: compute initial and final value of the loop counter. */
25564 /* TEST_ADDR = SP + FIRST. */
25565 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
25568 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25569 if (rounded_size
> 32768)
25571 emit_move_insn (r0
, GEN_INT (-rounded_size
));
25572 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
25575 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
25579 /* Step 3: the loop
25583 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25586 while (TEST_ADDR != LAST_ADDR)
25588 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25589 until it is equal to ROUNDED_SIZE. */
25592 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
25594 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
25597 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25598 that SIZE is equal to ROUNDED_SIZE. */
25600 if (size
!= rounded_size
)
25601 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
25605 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25606 absolute addresses. */
25609 output_probe_stack_range (rtx reg1
, rtx reg2
)
25611 static int labelno
= 0;
25615 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25618 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25620 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25622 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
25623 output_asm_insn ("addi %0,%0,%1", xops
);
25625 /* Probe at TEST_ADDR. */
25626 xops
[1] = gen_rtx_REG (Pmode
, 0);
25627 output_asm_insn ("stw %1,0(%0)", xops
);
25629 /* Test if TEST_ADDR == LAST_ADDR. */
25632 output_asm_insn ("cmpd 0,%0,%1", xops
);
25634 output_asm_insn ("cmpw 0,%0,%1", xops
);
25637 fputs ("\tbne 0,", asm_out_file
);
25638 assemble_name_raw (asm_out_file
, loop_lab
);
25639 fputc ('\n', asm_out_file
);
25644 /* This function is called when rs6000_frame_related is processing
25645 SETs within a PARALLEL, and returns whether the REGNO save ought to
25646 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25647 for out-of-line register save functions, store multiple, and the
25648 Darwin world_save. They may contain registers that don't really
25652 interesting_frame_related_regno (unsigned int regno
)
25654 /* Saves apparently of r0 are actually saving LR. It doesn't make
25655 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25656 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25657 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25658 as frame related. */
25661 /* If we see CR2 then we are here on a Darwin world save. Saves of
25662 CR2 signify the whole CR is being saved. This is a long-standing
25663 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25664 that CR needs to be saved. */
25665 if (regno
== CR2_REGNO
)
25667 /* Omit frame info for any user-defined global regs. If frame info
25668 is supplied for them, frame unwinding will restore a user reg.
25669 Also omit frame info for any reg we don't need to save, as that
25670 bloats frame info and can cause problems with shrink wrapping.
25671 Since global regs won't be seen as needing to be saved, both of
25672 these conditions are covered by save_reg_p. */
25673 return save_reg_p (regno
);
25676 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25677 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25678 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25679 deduce these equivalences by itself so it wasn't necessary to hold
25680 its hand so much. Don't be tempted to always supply d2_f_d_e with
25681 the actual cfa register, ie. r31 when we are using a hard frame
25682 pointer. That fails when saving regs off r1, and sched moves the
25683 r31 setup past the reg saves. */
25686 rs6000_frame_related (rtx_insn
*insn
, rtx reg
, HOST_WIDE_INT val
,
25687 rtx reg2
, rtx repl2
)
25691 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
25693 gcc_checking_assert (val
== 0);
25697 repl
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
25700 rtx pat
= PATTERN (insn
);
25701 if (!repl
&& !reg2
)
25703 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25704 if (GET_CODE (pat
) == PARALLEL
)
25705 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
25706 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
25708 rtx set
= XVECEXP (pat
, 0, i
);
25710 if (!REG_P (SET_SRC (set
))
25711 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
25712 RTX_FRAME_RELATED_P (set
) = 1;
25714 RTX_FRAME_RELATED_P (insn
) = 1;
25718 /* We expect that 'pat' is either a SET or a PARALLEL containing
25719 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25720 are important so they all have to be marked RTX_FRAME_RELATED_P.
25721 Call simplify_replace_rtx on the SETs rather than the whole insn
25722 so as to leave the other stuff alone (for example USE of r12). */
25724 set_used_flags (pat
);
25725 if (GET_CODE (pat
) == SET
)
25728 pat
= simplify_replace_rtx (pat
, reg
, repl
);
25730 pat
= simplify_replace_rtx (pat
, reg2
, repl2
);
25732 else if (GET_CODE (pat
) == PARALLEL
)
25734 pat
= shallow_copy_rtx (pat
);
25735 XVEC (pat
, 0) = shallow_copy_rtvec (XVEC (pat
, 0));
25737 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
25738 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
25740 rtx set
= XVECEXP (pat
, 0, i
);
25743 set
= simplify_replace_rtx (set
, reg
, repl
);
25745 set
= simplify_replace_rtx (set
, reg2
, repl2
);
25746 XVECEXP (pat
, 0, i
) = set
;
25748 if (!REG_P (SET_SRC (set
))
25749 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
25750 RTX_FRAME_RELATED_P (set
) = 1;
25754 gcc_unreachable ();
25756 RTX_FRAME_RELATED_P (insn
) = 1;
25757 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, copy_rtx_if_shared (pat
));
25762 /* Returns an insn that has a vrsave set operation with the
25763 appropriate CLOBBERs. */
25766 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
25769 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
25770 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
25773 = gen_rtx_SET (vrsave
,
25774 gen_rtx_UNSPEC_VOLATILE (SImode
,
25775 gen_rtvec (2, reg
, vrsave
),
25776 UNSPECV_SET_VRSAVE
));
25780 /* We need to clobber the registers in the mask so the scheduler
25781 does not move sets to VRSAVE before sets of AltiVec registers.
25783 However, if the function receives nonlocal gotos, reload will set
25784 all call saved registers live. We will end up with:
25786 (set (reg 999) (mem))
25787 (parallel [ (set (reg vrsave) (unspec blah))
25788 (clobber (reg 999))])
25790 The clobber will cause the store into reg 999 to be dead, and
25791 flow will attempt to delete an epilogue insn. In this case, we
25792 need an unspec use/set of the register. */
25794 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25795 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25797 if (!epiloguep
|| call_used_regs
[i
])
25798 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
25799 gen_rtx_REG (V4SImode
, i
));
25802 rtx reg
= gen_rtx_REG (V4SImode
, i
);
25805 = gen_rtx_SET (reg
,
25806 gen_rtx_UNSPEC (V4SImode
,
25807 gen_rtvec (1, reg
), 27));
25811 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
25813 for (i
= 0; i
< nclobs
; ++i
)
25814 XVECEXP (insn
, 0, i
) = clobs
[i
];
25820 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
25824 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
25825 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
25826 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
25830 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
25832 return gen_frame_set (reg
, frame_reg
, offset
, false);
25836 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
25838 return gen_frame_set (reg
, frame_reg
, offset
, true);
25841 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25842 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25845 emit_frame_save (rtx frame_reg
, machine_mode mode
,
25846 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
25850 /* Some cases that need register indexed addressing. */
25851 gcc_checking_assert (!(TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
25852 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
)));
25854 reg
= gen_rtx_REG (mode
, regno
);
25855 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
25856 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
25857 NULL_RTX
, NULL_RTX
);
25860 /* Emit an offset memory reference suitable for a frame store, while
25861 converting to a valid addressing mode. */
25864 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
25866 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, GEN_INT (offset
)));
25869 #ifndef TARGET_FIX_AND_CONTINUE
25870 #define TARGET_FIX_AND_CONTINUE 0
25873 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25874 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25875 #define LAST_SAVRES_REGISTER 31
25876 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25887 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
25889 /* Temporary holding space for an out-of-line register save/restore
25891 static char savres_routine_name
[30];
25893 /* Return the name for an out-of-line register save/restore routine.
25894 We are saving/restoring GPRs if GPR is true. */
25897 rs6000_savres_routine_name (int regno
, int sel
)
25899 const char *prefix
= "";
25900 const char *suffix
= "";
25902 /* Different targets are supposed to define
25903 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25904 routine name could be defined with:
25906 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25908 This is a nice idea in practice, but in reality, things are
25909 complicated in several ways:
25911 - ELF targets have save/restore routines for GPRs.
25913 - PPC64 ELF targets have routines for save/restore of GPRs that
25914 differ in what they do with the link register, so having a set
25915 prefix doesn't work. (We only use one of the save routines at
25916 the moment, though.)
25918 - PPC32 elf targets have "exit" versions of the restore routines
25919 that restore the link register and can save some extra space.
25920 These require an extra suffix. (There are also "tail" versions
25921 of the restore routines and "GOT" versions of the save routines,
25922 but we don't generate those at present. Same problems apply,
25925 We deal with all this by synthesizing our own prefix/suffix and
25926 using that for the simple sprintf call shown above. */
25927 if (DEFAULT_ABI
== ABI_V4
)
25932 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25933 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
25934 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25935 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
25936 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25937 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
25941 if ((sel
& SAVRES_LR
))
25944 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25946 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25947 /* No out-of-line save/restore routines for GPRs on AIX. */
25948 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
25952 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25953 prefix
= ((sel
& SAVRES_SAVE
)
25954 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
25955 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
25956 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25958 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25959 if ((sel
& SAVRES_LR
))
25960 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
25964 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
25965 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
25968 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25969 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
25974 if (DEFAULT_ABI
== ABI_DARWIN
)
25976 /* The Darwin approach is (slightly) different, in order to be
25977 compatible with code generated by the system toolchain. There is a
25978 single symbol for the start of save sequence, and the code here
25979 embeds an offset into that code on the basis of the first register
25981 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
25982 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25983 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
25984 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
25985 (regno
- 13) * 4, prefix
, regno
);
25986 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25987 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
25988 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
25989 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25990 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
25991 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
25996 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
25998 return savres_routine_name
;
26001 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26002 We are saving/restoring GPRs if GPR is true. */
26005 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
26007 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26008 ? info
->first_gp_reg_save
26009 : (sel
& SAVRES_REG
) == SAVRES_FPR
26010 ? info
->first_fp_reg_save
- 32
26011 : (sel
& SAVRES_REG
) == SAVRES_VR
26012 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
26017 /* Don't generate bogus routine names. */
26018 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
26019 && regno
<= LAST_SAVRES_REGISTER
26020 && select
>= 0 && select
<= 12);
26022 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
26028 name
= rs6000_savres_routine_name (regno
, sel
);
26030 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
26031 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
26032 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
26038 /* Emit a sequence of insns, including a stack tie if needed, for
26039 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26040 reset the stack pointer, but move the base of the frame into
26041 reg UPDT_REGNO for use by out-of-line register restore routines. */
26044 rs6000_emit_stack_reset (rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
26045 unsigned updt_regno
)
26047 /* If there is nothing to do, don't do anything. */
26048 if (frame_off
== 0 && REGNO (frame_reg_rtx
) == updt_regno
)
26051 rtx updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
26053 /* This blockage is needed so that sched doesn't decide to move
26054 the sp change before the register restores. */
26055 if (DEFAULT_ABI
== ABI_V4
)
26056 return emit_insn (gen_stack_restore_tie (updt_reg_rtx
, frame_reg_rtx
,
26057 GEN_INT (frame_off
)));
26059 /* If we are restoring registers out-of-line, we will be using the
26060 "exit" variants of the restore routines, which will reset the
26061 stack for us. But we do need to point updt_reg into the
26062 right place for those routines. */
26063 if (frame_off
!= 0)
26064 return emit_insn (gen_add3_insn (updt_reg_rtx
,
26065 frame_reg_rtx
, GEN_INT (frame_off
)));
26067 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
26072 /* Return the register number used as a pointer by out-of-line
26073 save/restore functions. */
26075 static inline unsigned
26076 ptr_regno_for_savres (int sel
)
26078 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26079 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
26080 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
26083 /* Construct a parallel rtx describing the effect of a call to an
26084 out-of-line register save/restore routine, and emit the insn
26085 or jump_insn as appropriate. */
26088 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
26089 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
26090 machine_mode reg_mode
, int sel
)
26093 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
26094 int reg_size
= GET_MODE_SIZE (reg_mode
);
26101 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26102 ? info
->first_gp_reg_save
26103 : (sel
& SAVRES_REG
) == SAVRES_FPR
26104 ? info
->first_fp_reg_save
26105 : (sel
& SAVRES_REG
) == SAVRES_VR
26106 ? info
->first_altivec_reg_save
26108 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26110 : (sel
& SAVRES_REG
) == SAVRES_FPR
26112 : (sel
& SAVRES_REG
) == SAVRES_VR
26113 ? LAST_ALTIVEC_REGNO
+ 1
26115 n_regs
= end_reg
- start_reg
;
26116 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
26117 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
26120 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26121 RTVEC_ELT (p
, offset
++) = ret_rtx
;
26123 RTVEC_ELT (p
, offset
++)
26124 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
26126 sym
= rs6000_savres_routine_sym (info
, sel
);
26127 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
26129 use_reg
= ptr_regno_for_savres (sel
);
26130 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26132 /* Vector regs are saved/restored using [reg+reg] addressing. */
26133 RTVEC_ELT (p
, offset
++)
26134 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
26135 RTVEC_ELT (p
, offset
++)
26136 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
26139 RTVEC_ELT (p
, offset
++)
26140 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
26142 for (i
= 0; i
< end_reg
- start_reg
; i
++)
26143 RTVEC_ELT (p
, i
+ offset
)
26144 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
26145 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
26146 (sel
& SAVRES_SAVE
) != 0);
26148 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26149 RTVEC_ELT (p
, i
+ offset
)
26150 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
26152 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
26154 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26156 insn
= emit_jump_insn (par
);
26157 JUMP_LABEL (insn
) = ret_rtx
;
26160 insn
= emit_insn (par
);
26164 /* Emit code to store CR fields that need to be saved into REG. */
26167 rs6000_emit_move_from_cr (rtx reg
)
26169 /* Only the ELFv2 ABI allows storing only selected fields. */
26170 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
26172 int i
, cr_reg
[8], count
= 0;
26174 /* Collect CR fields that must be saved. */
26175 for (i
= 0; i
< 8; i
++)
26176 if (save_reg_p (CR0_REGNO
+ i
))
26177 cr_reg
[count
++] = i
;
26179 /* If it's just a single one, use mfcrf. */
26182 rtvec p
= rtvec_alloc (1);
26183 rtvec r
= rtvec_alloc (2);
26184 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
26185 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
26187 = gen_rtx_SET (reg
,
26188 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
26190 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26194 /* ??? It might be better to handle count == 2 / 3 cases here
26195 as well, using logical operations to combine the values. */
26198 emit_insn (gen_movesi_from_cr (reg
));
26201 /* Return whether the split-stack arg pointer (r12) is used. */
26204 split_stack_arg_pointer_used_p (void)
26206 /* If the pseudo holding the arg pointer is no longer a pseudo,
26207 then the arg pointer is used. */
26208 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
26209 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
26210 || (REGNO (cfun
->machine
->split_stack_arg_pointer
)
26211 < FIRST_PSEUDO_REGISTER
)))
26214 /* Unfortunately we also need to do some code scanning, since
26215 r12 may have been substituted for the pseudo. */
26217 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
26218 FOR_BB_INSNS (bb
, insn
)
26219 if (NONDEBUG_INSN_P (insn
))
26221 /* A call destroys r12. */
26226 FOR_EACH_INSN_USE (use
, insn
)
26228 rtx x
= DF_REF_REG (use
);
26229 if (REG_P (x
) && REGNO (x
) == 12)
26233 FOR_EACH_INSN_DEF (def
, insn
)
26235 rtx x
= DF_REF_REG (def
);
26236 if (REG_P (x
) && REGNO (x
) == 12)
26240 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
26243 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26246 rs6000_global_entry_point_needed_p (void)
26248 /* Only needed for the ELFv2 ABI. */
26249 if (DEFAULT_ABI
!= ABI_ELFv2
)
26252 /* With -msingle-pic-base, we assume the whole program shares the same
26253 TOC, so no global entry point prologues are needed anywhere. */
26254 if (TARGET_SINGLE_PIC_BASE
)
26257 /* Ensure we have a global entry point for thunks. ??? We could
26258 avoid that if the target routine doesn't need a global entry point,
26259 but we do not know whether this is the case at this point. */
26260 if (cfun
->is_thunk
)
26263 /* For regular functions, rs6000_emit_prologue sets this flag if the
26264 routine ever uses the TOC pointer. */
26265 return cfun
->machine
->r2_setup_needed
;
26268 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26270 rs6000_get_separate_components (void)
26272 rs6000_stack_t
*info
= rs6000_stack_info ();
26274 if (WORLD_SAVE_P (info
))
26277 gcc_assert (!(info
->savres_strategy
& SAVE_MULTIPLE
)
26278 && !(info
->savres_strategy
& REST_MULTIPLE
));
26280 /* Component 0 is the save/restore of LR (done via GPR0).
26281 Components 13..31 are the save/restore of GPR13..GPR31.
26282 Components 46..63 are the save/restore of FPR14..FPR31. */
26284 cfun
->machine
->n_components
= 64;
26286 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26287 bitmap_clear (components
);
26289 int reg_size
= TARGET_32BIT
? 4 : 8;
26290 int fp_reg_size
= 8;
26292 /* The GPRs we need saved to the frame. */
26293 if ((info
->savres_strategy
& SAVE_INLINE_GPRS
)
26294 && (info
->savres_strategy
& REST_INLINE_GPRS
))
26296 int offset
= info
->gp_save_offset
;
26298 offset
+= info
->total_size
;
26300 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26302 if (IN_RANGE (offset
, -0x8000, 0x7fff)
26303 && save_reg_p (regno
))
26304 bitmap_set_bit (components
, regno
);
26306 offset
+= reg_size
;
26310 /* Don't mess with the hard frame pointer. */
26311 if (frame_pointer_needed
)
26312 bitmap_clear_bit (components
, HARD_FRAME_POINTER_REGNUM
);
26314 /* Don't mess with the fixed TOC register. */
26315 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
26316 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
26317 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
26318 bitmap_clear_bit (components
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
26320 /* The FPRs we need saved to the frame. */
26321 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
)
26322 && (info
->savres_strategy
& REST_INLINE_FPRS
))
26324 int offset
= info
->fp_save_offset
;
26326 offset
+= info
->total_size
;
26328 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26330 if (IN_RANGE (offset
, -0x8000, 0x7fff) && save_reg_p (regno
))
26331 bitmap_set_bit (components
, regno
);
26333 offset
+= fp_reg_size
;
26337 /* Optimize LR save and restore if we can. This is component 0. Any
26338 out-of-line register save/restore routines need LR. */
26339 if (info
->lr_save_p
26340 && !(flag_pic
&& (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
26341 && (info
->savres_strategy
& SAVE_INLINE_GPRS
)
26342 && (info
->savres_strategy
& REST_INLINE_GPRS
)
26343 && (info
->savres_strategy
& SAVE_INLINE_FPRS
)
26344 && (info
->savres_strategy
& REST_INLINE_FPRS
)
26345 && (info
->savres_strategy
& SAVE_INLINE_VRS
)
26346 && (info
->savres_strategy
& REST_INLINE_VRS
))
26348 int offset
= info
->lr_save_offset
;
26350 offset
+= info
->total_size
;
26351 if (IN_RANGE (offset
, -0x8000, 0x7fff))
26352 bitmap_set_bit (components
, 0);
26358 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26360 rs6000_components_for_bb (basic_block bb
)
26362 rs6000_stack_t
*info
= rs6000_stack_info ();
26364 bitmap in
= DF_LIVE_IN (bb
);
26365 bitmap gen
= &DF_LIVE_BB_INFO (bb
)->gen
;
26366 bitmap kill
= &DF_LIVE_BB_INFO (bb
)->kill
;
26368 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26369 bitmap_clear (components
);
26371 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26374 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26375 if (bitmap_bit_p (in
, regno
)
26376 || bitmap_bit_p (gen
, regno
)
26377 || bitmap_bit_p (kill
, regno
))
26378 bitmap_set_bit (components
, regno
);
26381 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26382 if (bitmap_bit_p (in
, regno
)
26383 || bitmap_bit_p (gen
, regno
)
26384 || bitmap_bit_p (kill
, regno
))
26385 bitmap_set_bit (components
, regno
);
26387 /* The link register. */
26388 if (bitmap_bit_p (in
, LR_REGNO
)
26389 || bitmap_bit_p (gen
, LR_REGNO
)
26390 || bitmap_bit_p (kill
, LR_REGNO
))
26391 bitmap_set_bit (components
, 0);
26396 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26398 rs6000_disqualify_components (sbitmap components
, edge e
,
26399 sbitmap edge_components
, bool /*is_prologue*/)
26401 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26402 live where we want to place that code. */
26403 if (bitmap_bit_p (edge_components
, 0)
26404 && bitmap_bit_p (DF_LIVE_IN (e
->dest
), 0))
26407 fprintf (dump_file
, "Disqualifying LR because GPR0 is live "
26408 "on entry to bb %d\n", e
->dest
->index
);
26409 bitmap_clear_bit (components
, 0);
26413 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26415 rs6000_emit_prologue_components (sbitmap components
)
26417 rs6000_stack_t
*info
= rs6000_stack_info ();
26418 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26419 ? HARD_FRAME_POINTER_REGNUM
26420 : STACK_POINTER_REGNUM
);
26422 machine_mode reg_mode
= Pmode
;
26423 int reg_size
= TARGET_32BIT
? 4 : 8;
26424 machine_mode fp_reg_mode
= (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
26426 int fp_reg_size
= 8;
26428 /* Prologue for LR. */
26429 if (bitmap_bit_p (components
, 0))
26431 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26432 rtx_insn
*insn
= emit_move_insn (reg
, gen_rtx_REG (reg_mode
, LR_REGNO
));
26433 RTX_FRAME_RELATED_P (insn
) = 1;
26434 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
26436 int offset
= info
->lr_save_offset
;
26438 offset
+= info
->total_size
;
26440 insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26441 RTX_FRAME_RELATED_P (insn
) = 1;
26442 rtx lr
= gen_rtx_REG (reg_mode
, LR_REGNO
);
26443 rtx mem
= copy_rtx (SET_DEST (single_set (insn
)));
26444 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, lr
));
26447 /* Prologue for the GPRs. */
26448 int offset
= info
->gp_save_offset
;
26450 offset
+= info
->total_size
;
26452 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26454 if (bitmap_bit_p (components
, i
))
26456 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26457 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26458 RTX_FRAME_RELATED_P (insn
) = 1;
26459 rtx set
= copy_rtx (single_set (insn
));
26460 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26463 offset
+= reg_size
;
26466 /* Prologue for the FPRs. */
26467 offset
= info
->fp_save_offset
;
26469 offset
+= info
->total_size
;
26471 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26473 if (bitmap_bit_p (components
, i
))
26475 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26476 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26477 RTX_FRAME_RELATED_P (insn
) = 1;
26478 rtx set
= copy_rtx (single_set (insn
));
26479 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26482 offset
+= fp_reg_size
;
26486 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26488 rs6000_emit_epilogue_components (sbitmap components
)
26490 rs6000_stack_t
*info
= rs6000_stack_info ();
26491 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26492 ? HARD_FRAME_POINTER_REGNUM
26493 : STACK_POINTER_REGNUM
);
26495 machine_mode reg_mode
= Pmode
;
26496 int reg_size
= TARGET_32BIT
? 4 : 8;
26498 machine_mode fp_reg_mode
= (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
26500 int fp_reg_size
= 8;
26502 /* Epilogue for the FPRs. */
26503 int offset
= info
->fp_save_offset
;
26505 offset
+= info
->total_size
;
26507 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26509 if (bitmap_bit_p (components
, i
))
26511 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26512 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26513 RTX_FRAME_RELATED_P (insn
) = 1;
26514 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26517 offset
+= fp_reg_size
;
26520 /* Epilogue for the GPRs. */
26521 offset
= info
->gp_save_offset
;
26523 offset
+= info
->total_size
;
26525 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26527 if (bitmap_bit_p (components
, i
))
26529 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26530 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26531 RTX_FRAME_RELATED_P (insn
) = 1;
26532 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26535 offset
+= reg_size
;
26538 /* Epilogue for LR. */
26539 if (bitmap_bit_p (components
, 0))
26541 int offset
= info
->lr_save_offset
;
26543 offset
+= info
->total_size
;
26545 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26546 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26548 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
26549 insn
= emit_move_insn (lr
, reg
);
26550 RTX_FRAME_RELATED_P (insn
) = 1;
26551 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
26555 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26557 rs6000_set_handled_components (sbitmap components
)
26559 rs6000_stack_t
*info
= rs6000_stack_info ();
26561 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26562 if (bitmap_bit_p (components
, i
))
26563 cfun
->machine
->gpr_is_wrapped_separately
[i
] = true;
26565 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26566 if (bitmap_bit_p (components
, i
))
26567 cfun
->machine
->fpr_is_wrapped_separately
[i
- 32] = true;
26569 if (bitmap_bit_p (components
, 0))
26570 cfun
->machine
->lr_is_wrapped_separately
= true;
26573 /* VRSAVE is a bit vector representing which AltiVec registers
26574 are used. The OS uses this to determine which vector
26575 registers to save on a context switch. We need to save
26576 VRSAVE on the stack frame, add whatever AltiVec registers we
26577 used in this function, and do the corresponding magic in the
26580 emit_vrsave_prologue (rs6000_stack_t
*info
, int save_regno
,
26581 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26583 /* Get VRSAVE into a GPR. */
26584 rtx reg
= gen_rtx_REG (SImode
, save_regno
);
26585 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
26587 emit_insn (gen_get_vrsave_internal (reg
));
26589 emit_insn (gen_rtx_SET (reg
, vrsave
));
26592 int offset
= info
->vrsave_save_offset
+ frame_off
;
26593 emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
26595 /* Include the registers in the mask. */
26596 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT (info
->vrsave_mask
)));
26598 emit_insn (generate_set_vrsave (reg
, info
, 0));
26601 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26602 called, it left the arg pointer to the old stack in r29. Otherwise, the
26603 arg pointer is the top of the current frame. */
26605 emit_split_stack_prologue (rs6000_stack_t
*info
, rtx_insn
*sp_adjust
,
26606 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26608 cfun
->machine
->split_stack_argp_used
= true;
26612 rtx r12
= gen_rtx_REG (Pmode
, 12);
26613 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26614 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
26615 emit_insn_before (set_r12
, sp_adjust
);
26617 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
26619 rtx r12
= gen_rtx_REG (Pmode
, 12);
26620 if (frame_off
== 0)
26621 emit_move_insn (r12
, frame_reg_rtx
);
26623 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
26628 rtx r12
= gen_rtx_REG (Pmode
, 12);
26629 rtx r29
= gen_rtx_REG (Pmode
, 29);
26630 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
26631 rtx not_more
= gen_label_rtx ();
26634 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26635 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
26636 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
26638 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26639 JUMP_LABEL (jump
) = not_more
;
26640 LABEL_NUSES (not_more
) += 1;
26641 emit_move_insn (r12
, r29
);
26642 emit_label (not_more
);
26646 /* Emit function prologue as insns. */
26649 rs6000_emit_prologue (void)
26651 rs6000_stack_t
*info
= rs6000_stack_info ();
26652 machine_mode reg_mode
= Pmode
;
26653 int reg_size
= TARGET_32BIT
? 4 : 8;
26654 machine_mode fp_reg_mode
= (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
26656 int fp_reg_size
= 8;
26657 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26658 rtx frame_reg_rtx
= sp_reg_rtx
;
26659 unsigned int cr_save_regno
;
26660 rtx cr_save_rtx
= NULL_RTX
;
26663 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
26664 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
26665 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
26666 int using_split_stack
= (flag_split_stack
26667 && (lookup_attribute ("no_split_stack",
26668 DECL_ATTRIBUTES (cfun
->decl
))
26671 /* Offset to top of frame for frame_reg and sp respectively. */
26672 HOST_WIDE_INT frame_off
= 0;
26673 HOST_WIDE_INT sp_off
= 0;
26674 /* sp_adjust is the stack adjusting instruction, tracked so that the
26675 insn setting up the split-stack arg pointer can be emitted just
26676 prior to it, when r12 is not used here for other purposes. */
26677 rtx_insn
*sp_adjust
= 0;
26680 /* Track and check usage of r0, r11, r12. */
26681 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
26682 #define START_USE(R) do \
26684 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26685 reg_inuse |= 1 << (R); \
26687 #define END_USE(R) do \
26689 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26690 reg_inuse &= ~(1 << (R)); \
26692 #define NOT_INUSE(R) do \
26694 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26697 #define START_USE(R) do {} while (0)
26698 #define END_USE(R) do {} while (0)
26699 #define NOT_INUSE(R) do {} while (0)
26702 if (DEFAULT_ABI
== ABI_ELFv2
26703 && !TARGET_SINGLE_PIC_BASE
)
26705 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
26707 /* With -mminimal-toc we may generate an extra use of r2 below. */
26708 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
26709 && !constant_pool_empty_p ())
26710 cfun
->machine
->r2_setup_needed
= true;
26714 if (flag_stack_usage_info
)
26715 current_function_static_stack_size
= info
->total_size
;
26717 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
26719 HOST_WIDE_INT size
= info
->total_size
;
26721 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
26723 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
26724 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
26725 size
- STACK_CHECK_PROTECT
);
26728 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
26731 if (TARGET_FIX_AND_CONTINUE
)
26733 /* gdb on darwin arranges to forward a function from the old
26734 address by modifying the first 5 instructions of the function
26735 to branch to the overriding function. This is necessary to
26736 permit function pointers that point to the old function to
26737 actually forward to the new function. */
26738 emit_insn (gen_nop ());
26739 emit_insn (gen_nop ());
26740 emit_insn (gen_nop ());
26741 emit_insn (gen_nop ());
26742 emit_insn (gen_nop ());
26745 /* Handle world saves specially here. */
26746 if (WORLD_SAVE_P (info
))
26753 /* save_world expects lr in r0. */
26754 reg0
= gen_rtx_REG (Pmode
, 0);
26755 if (info
->lr_save_p
)
26757 insn
= emit_move_insn (reg0
,
26758 gen_rtx_REG (Pmode
, LR_REGNO
));
26759 RTX_FRAME_RELATED_P (insn
) = 1;
26762 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26763 assumptions about the offsets of various bits of the stack
26765 gcc_assert (info
->gp_save_offset
== -220
26766 && info
->fp_save_offset
== -144
26767 && info
->lr_save_offset
== 8
26768 && info
->cr_save_offset
== 4
26771 && (!crtl
->calls_eh_return
26772 || info
->ehrd_offset
== -432)
26773 && info
->vrsave_save_offset
== -224
26774 && info
->altivec_save_offset
== -416);
26776 treg
= gen_rtx_REG (SImode
, 11);
26777 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
26779 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26780 in R11. It also clobbers R12, so beware! */
26782 /* Preserve CR2 for save_world prologues */
26784 sz
+= 32 - info
->first_gp_reg_save
;
26785 sz
+= 64 - info
->first_fp_reg_save
;
26786 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
26787 p
= rtvec_alloc (sz
);
26789 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
26790 gen_rtx_REG (SImode
,
26792 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
26793 gen_rtx_SYMBOL_REF (Pmode
,
26795 /* We do floats first so that the instruction pattern matches
26797 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
26799 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
26801 info
->first_fp_reg_save
+ i
),
26803 info
->fp_save_offset
+ frame_off
+ 8 * i
);
26804 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
26806 = gen_frame_store (gen_rtx_REG (V4SImode
,
26807 info
->first_altivec_reg_save
+ i
),
26809 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
26810 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26812 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26814 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
26816 /* CR register traditionally saved as CR2. */
26818 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
26819 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
26820 /* Explain about use of R0. */
26821 if (info
->lr_save_p
)
26823 = gen_frame_store (reg0
,
26824 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
26825 /* Explain what happens to the stack pointer. */
26827 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
26828 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
26831 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26832 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26833 treg
, GEN_INT (-info
->total_size
));
26834 sp_off
= frame_off
= info
->total_size
;
26837 strategy
= info
->savres_strategy
;
26839 /* For V.4, update stack before we do any saving and set back pointer. */
26840 if (! WORLD_SAVE_P (info
)
26842 && (DEFAULT_ABI
== ABI_V4
26843 || crtl
->calls_eh_return
))
26845 bool need_r11
= (!(strategy
& SAVE_INLINE_FPRS
)
26846 || !(strategy
& SAVE_INLINE_GPRS
)
26847 || !(strategy
& SAVE_INLINE_VRS
));
26848 int ptr_regno
= -1;
26849 rtx ptr_reg
= NULL_RTX
;
26852 if (info
->total_size
< 32767)
26853 frame_off
= info
->total_size
;
26856 else if (info
->cr_save_p
26858 || info
->first_fp_reg_save
< 64
26859 || info
->first_gp_reg_save
< 32
26860 || info
->altivec_size
!= 0
26861 || info
->vrsave_size
!= 0
26862 || crtl
->calls_eh_return
)
26866 /* The prologue won't be saving any regs so there is no need
26867 to set up a frame register to access any frame save area.
26868 We also won't be using frame_off anywhere below, but set
26869 the correct value anyway to protect against future
26870 changes to this function. */
26871 frame_off
= info
->total_size
;
26873 if (ptr_regno
!= -1)
26875 /* Set up the frame offset to that needed by the first
26876 out-of-line save function. */
26877 START_USE (ptr_regno
);
26878 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26879 frame_reg_rtx
= ptr_reg
;
26880 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
26881 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
26882 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
26883 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
26884 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
26885 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
26886 frame_off
= -ptr_off
;
26888 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
26890 if (REGNO (frame_reg_rtx
) == 12)
26892 sp_off
= info
->total_size
;
26893 if (frame_reg_rtx
!= sp_reg_rtx
)
26894 rs6000_emit_stack_tie (frame_reg_rtx
, false);
26897 /* If we use the link register, get it into r0. */
26898 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
26899 && !cfun
->machine
->lr_is_wrapped_separately
)
26901 rtx addr
, reg
, mem
;
26903 reg
= gen_rtx_REG (Pmode
, 0);
26905 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
26906 RTX_FRAME_RELATED_P (insn
) = 1;
26908 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
26909 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
26911 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
26912 GEN_INT (info
->lr_save_offset
+ frame_off
));
26913 mem
= gen_rtx_MEM (Pmode
, addr
);
26914 /* This should not be of rs6000_sr_alias_set, because of
26915 __builtin_return_address. */
26917 insn
= emit_move_insn (mem
, reg
);
26918 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26919 NULL_RTX
, NULL_RTX
);
26924 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26925 r12 will be needed by out-of-line gpr restore. */
26926 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26927 && !(strategy
& (SAVE_INLINE_GPRS
26928 | SAVE_NOINLINE_GPRS_SAVES_LR
))
26930 if (!WORLD_SAVE_P (info
)
26932 && REGNO (frame_reg_rtx
) != cr_save_regno
26933 && !(using_static_chain_p
&& cr_save_regno
== 11)
26934 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
26936 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
26937 START_USE (cr_save_regno
);
26938 rs6000_emit_move_from_cr (cr_save_rtx
);
26941 /* Do any required saving of fpr's. If only one or two to save, do
26942 it ourselves. Otherwise, call function. */
26943 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
26945 int offset
= info
->fp_save_offset
+ frame_off
;
26946 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26949 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
26950 emit_frame_save (frame_reg_rtx
, fp_reg_mode
, i
, offset
,
26951 sp_off
- frame_off
);
26953 offset
+= fp_reg_size
;
26956 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
26958 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
26959 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
26960 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
26961 rtx ptr_reg
= frame_reg_rtx
;
26963 if (REGNO (frame_reg_rtx
) == ptr_regno
)
26964 gcc_checking_assert (frame_off
== 0);
26967 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26968 NOT_INUSE (ptr_regno
);
26969 emit_insn (gen_add3_insn (ptr_reg
,
26970 frame_reg_rtx
, GEN_INT (frame_off
)));
26972 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
26973 info
->fp_save_offset
,
26974 info
->lr_save_offset
,
26976 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
26977 NULL_RTX
, NULL_RTX
);
26982 /* Save GPRs. This is done as a PARALLEL if we are using
26983 the store-multiple instructions. */
26984 if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
26986 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
26987 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
26988 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
26989 rtx ptr_reg
= frame_reg_rtx
;
26990 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
26991 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
26994 if (ptr_regno
== 12)
26997 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26999 /* Need to adjust r11 (r12) if we saved any FPRs. */
27000 if (end_save
+ frame_off
!= 0)
27002 rtx offset
= GEN_INT (end_save
+ frame_off
);
27005 frame_off
= -end_save
;
27007 NOT_INUSE (ptr_regno
);
27008 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27010 else if (!ptr_set_up
)
27012 NOT_INUSE (ptr_regno
);
27013 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27015 ptr_off
= -end_save
;
27016 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
27017 info
->gp_save_offset
+ ptr_off
,
27018 info
->lr_save_offset
+ ptr_off
,
27020 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
27021 NULL_RTX
, NULL_RTX
);
27025 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_MULTIPLE
))
27029 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
27030 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
27032 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
27034 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
27035 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27036 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27037 NULL_RTX
, NULL_RTX
);
27039 else if (!WORLD_SAVE_P (info
))
27041 int offset
= info
->gp_save_offset
+ frame_off
;
27042 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
27045 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
27046 emit_frame_save (frame_reg_rtx
, reg_mode
, i
, offset
,
27047 sp_off
- frame_off
);
27049 offset
+= reg_size
;
27053 if (crtl
->calls_eh_return
)
27060 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
27061 if (regno
== INVALID_REGNUM
)
27065 p
= rtvec_alloc (i
);
27069 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
27070 if (regno
== INVALID_REGNUM
)
27074 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
27076 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
27077 RTVEC_ELT (p
, i
) = set
;
27078 RTX_FRAME_RELATED_P (set
) = 1;
27081 insn
= emit_insn (gen_blockage ());
27082 RTX_FRAME_RELATED_P (insn
) = 1;
27083 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
27086 /* In AIX ABI we need to make sure r2 is really saved. */
27087 if (TARGET_AIX
&& crtl
->calls_eh_return
)
27089 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
27090 rtx join_insn
, note
;
27091 rtx_insn
*save_insn
;
27092 long toc_restore_insn
;
27094 tmp_reg
= gen_rtx_REG (Pmode
, 11);
27095 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
27096 if (using_static_chain_p
)
27099 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
27103 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
27104 /* Peek at instruction to which this function returns. If it's
27105 restoring r2, then we know we've already saved r2. We can't
27106 unconditionally save r2 because the value we have will already
27107 be updated if we arrived at this function via a plt call or
27108 toc adjusting stub. */
27109 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
27110 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
27111 + RS6000_TOC_SAVE_SLOT
);
27112 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
27113 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
27114 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
27115 validate_condition_mode (EQ
, CCUNSmode
);
27116 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
27117 emit_insn (gen_rtx_SET (compare_result
,
27118 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
27119 toc_save_done
= gen_label_rtx ();
27120 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
27121 gen_rtx_EQ (VOIDmode
, compare_result
,
27123 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
27125 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
27126 JUMP_LABEL (jump
) = toc_save_done
;
27127 LABEL_NUSES (toc_save_done
) += 1;
27129 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
27130 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
27131 sp_off
- frame_off
);
27133 emit_label (toc_save_done
);
27135 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27136 have a CFG that has different saves along different paths.
27137 Move the note to a dummy blockage insn, which describes that
27138 R2 is unconditionally saved after the label. */
27139 /* ??? An alternate representation might be a special insn pattern
27140 containing both the branch and the store. That might let the
27141 code that minimizes the number of DW_CFA_advance opcodes better
27142 freedom in placing the annotations. */
27143 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
27145 remove_note (save_insn
, note
);
27147 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
27148 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
27149 RTX_FRAME_RELATED_P (save_insn
) = 0;
27151 join_insn
= emit_insn (gen_blockage ());
27152 REG_NOTES (join_insn
) = note
;
27153 RTX_FRAME_RELATED_P (join_insn
) = 1;
27155 if (using_static_chain_p
)
27157 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
27164 /* Save CR if we use any that must be preserved. */
27165 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
27167 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27168 GEN_INT (info
->cr_save_offset
+ frame_off
));
27169 rtx mem
= gen_frame_mem (SImode
, addr
);
27171 /* If we didn't copy cr before, do so now using r0. */
27172 if (cr_save_rtx
== NULL_RTX
)
27175 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
27176 rs6000_emit_move_from_cr (cr_save_rtx
);
27179 /* Saving CR requires a two-instruction sequence: one instruction
27180 to move the CR to a general-purpose register, and a second
27181 instruction that stores the GPR to memory.
27183 We do not emit any DWARF CFI records for the first of these,
27184 because we cannot properly represent the fact that CR is saved in
27185 a register. One reason is that we cannot express that multiple
27186 CR fields are saved; another reason is that on 64-bit, the size
27187 of the CR register in DWARF (4 bytes) differs from the size of
27188 a general-purpose register.
27190 This means if any intervening instruction were to clobber one of
27191 the call-saved CR fields, we'd have incorrect CFI. To prevent
27192 this from happening, we mark the store to memory as a use of
27193 those CR fields, which prevents any such instruction from being
27194 scheduled in between the two instructions. */
27199 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
27200 for (i
= 0; i
< 8; i
++)
27201 if (save_reg_p (CR0_REGNO
+ i
))
27202 crsave_v
[n_crsave
++]
27203 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27205 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
27206 gen_rtvec_v (n_crsave
, crsave_v
)));
27207 END_USE (REGNO (cr_save_rtx
));
27209 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27210 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27211 so we need to construct a frame expression manually. */
27212 RTX_FRAME_RELATED_P (insn
) = 1;
27214 /* Update address to be stack-pointer relative, like
27215 rs6000_frame_related would do. */
27216 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
27217 GEN_INT (info
->cr_save_offset
+ sp_off
));
27218 mem
= gen_frame_mem (SImode
, addr
);
27220 if (DEFAULT_ABI
== ABI_ELFv2
)
27222 /* In the ELFv2 ABI we generate separate CFI records for each
27223 CR field that was actually saved. They all point to the
27224 same 32-bit stack slot. */
27228 for (i
= 0; i
< 8; i
++)
27229 if (save_reg_p (CR0_REGNO
+ i
))
27232 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27234 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
27238 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27239 gen_rtx_PARALLEL (VOIDmode
,
27240 gen_rtvec_v (n_crframe
, crframe
)));
27244 /* In other ABIs, by convention, we use a single CR regnum to
27245 represent the fact that all call-saved CR fields are saved.
27246 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27247 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
27248 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
27252 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27253 *separate* slots if the routine calls __builtin_eh_return, so
27254 that they can be independently restored by the unwinder. */
27255 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
27257 int i
, cr_off
= info
->ehcr_offset
;
27260 /* ??? We might get better performance by using multiple mfocrf
27262 crsave
= gen_rtx_REG (SImode
, 0);
27263 emit_insn (gen_movesi_from_cr (crsave
));
27265 for (i
= 0; i
< 8; i
++)
27266 if (!call_used_regs
[CR0_REGNO
+ i
])
27268 rtvec p
= rtvec_alloc (2);
27270 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
27272 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27274 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27276 RTX_FRAME_RELATED_P (insn
) = 1;
27277 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27278 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
27279 sp_reg_rtx
, cr_off
+ sp_off
));
27281 cr_off
+= reg_size
;
27285 /* Update stack and set back pointer unless this is V.4,
27286 for which it was done previously. */
27287 if (!WORLD_SAVE_P (info
) && info
->push_p
27288 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
27290 rtx ptr_reg
= NULL
;
27293 /* If saving altivec regs we need to be able to address all save
27294 locations using a 16-bit offset. */
27295 if ((strategy
& SAVE_INLINE_VRS
) == 0
27296 || (info
->altivec_size
!= 0
27297 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
27298 + info
->total_size
- frame_off
) > 32767)
27299 || (info
->vrsave_size
!= 0
27300 && (info
->vrsave_save_offset
27301 + info
->total_size
- frame_off
) > 32767))
27303 int sel
= SAVRES_SAVE
| SAVRES_VR
;
27304 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27306 if (using_static_chain_p
27307 && ptr_regno
== STATIC_CHAIN_REGNUM
)
27309 if (REGNO (frame_reg_rtx
) != ptr_regno
)
27310 START_USE (ptr_regno
);
27311 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27312 frame_reg_rtx
= ptr_reg
;
27313 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
27314 frame_off
= -ptr_off
;
27316 else if (REGNO (frame_reg_rtx
) == 1)
27317 frame_off
= info
->total_size
;
27318 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
27320 if (REGNO (frame_reg_rtx
) == 12)
27322 sp_off
= info
->total_size
;
27323 if (frame_reg_rtx
!= sp_reg_rtx
)
27324 rs6000_emit_stack_tie (frame_reg_rtx
, false);
27327 /* Set frame pointer, if needed. */
27328 if (frame_pointer_needed
)
27330 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
27332 RTX_FRAME_RELATED_P (insn
) = 1;
27335 /* Save AltiVec registers if needed. Save here because the red zone does
27336 not always include AltiVec registers. */
27337 if (!WORLD_SAVE_P (info
)
27338 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
27340 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
27342 /* Oddly, the vector save/restore functions point r0 at the end
27343 of the save area, then use r11 or r12 to load offsets for
27344 [reg+reg] addressing. */
27345 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
27346 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
27347 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
27349 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
27351 if (scratch_regno
== 12)
27353 if (end_save
+ frame_off
!= 0)
27355 rtx offset
= GEN_INT (end_save
+ frame_off
);
27357 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27360 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27362 ptr_off
= -end_save
;
27363 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
27364 info
->altivec_save_offset
+ ptr_off
,
27365 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
27366 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
27367 NULL_RTX
, NULL_RTX
);
27368 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
27370 /* The oddity mentioned above clobbered our frame reg. */
27371 emit_move_insn (frame_reg_rtx
, ptr_reg
);
27372 frame_off
= ptr_off
;
27375 else if (!WORLD_SAVE_P (info
)
27376 && info
->altivec_size
!= 0)
27380 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27381 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
27383 rtx areg
, savereg
, mem
;
27384 HOST_WIDE_INT offset
;
27386 offset
= (info
->altivec_save_offset
+ frame_off
27387 + 16 * (i
- info
->first_altivec_reg_save
));
27389 savereg
= gen_rtx_REG (V4SImode
, i
);
27391 if (TARGET_P9_DFORM_VECTOR
&& quad_address_offset_p (offset
))
27393 mem
= gen_frame_mem (V4SImode
,
27394 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27395 GEN_INT (offset
)));
27396 insn
= emit_insn (gen_rtx_SET (mem
, savereg
));
27402 areg
= gen_rtx_REG (Pmode
, 0);
27403 emit_move_insn (areg
, GEN_INT (offset
));
27405 /* AltiVec addressing mode is [reg+reg]. */
27406 mem
= gen_frame_mem (V4SImode
,
27407 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
27409 /* Rather than emitting a generic move, force use of the stvx
27410 instruction, which we always want on ISA 2.07 (power8) systems.
27411 In particular we don't want xxpermdi/stxvd2x for little
27413 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
27416 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27417 areg
, GEN_INT (offset
));
27421 /* VRSAVE is a bit vector representing which AltiVec registers
27422 are used. The OS uses this to determine which vector
27423 registers to save on a context switch. We need to save
27424 VRSAVE on the stack frame, add whatever AltiVec registers we
27425 used in this function, and do the corresponding magic in the
27428 if (!WORLD_SAVE_P (info
) && info
->vrsave_size
!= 0)
27430 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27431 be using r12 as frame_reg_rtx and r11 as the static chain
27432 pointer for nested functions. */
27433 int save_regno
= 12;
27434 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27435 && !using_static_chain_p
)
27437 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
27440 if (using_static_chain_p
)
27443 NOT_INUSE (save_regno
);
27445 emit_vrsave_prologue (info
, save_regno
, frame_off
, frame_reg_rtx
);
27448 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27449 if (!TARGET_SINGLE_PIC_BASE
27450 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
27451 && !constant_pool_empty_p ())
27452 || (DEFAULT_ABI
== ABI_V4
27453 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
27454 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
27456 /* If emit_load_toc_table will use the link register, we need to save
27457 it. We use R12 for this purpose because emit_load_toc_table
27458 can use register 0. This allows us to use a plain 'blr' to return
27459 from the procedure more often. */
27460 int save_LR_around_toc_setup
= (TARGET_ELF
27461 && DEFAULT_ABI
== ABI_V4
27463 && ! info
->lr_save_p
27464 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
27465 if (save_LR_around_toc_setup
)
27467 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27468 rtx tmp
= gen_rtx_REG (Pmode
, 12);
27471 insn
= emit_move_insn (tmp
, lr
);
27472 RTX_FRAME_RELATED_P (insn
) = 1;
27474 rs6000_emit_load_toc_table (TRUE
);
27476 insn
= emit_move_insn (lr
, tmp
);
27477 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27478 RTX_FRAME_RELATED_P (insn
) = 1;
27481 rs6000_emit_load_toc_table (TRUE
);
27485 if (!TARGET_SINGLE_PIC_BASE
27486 && DEFAULT_ABI
== ABI_DARWIN
27487 && flag_pic
&& crtl
->uses_pic_offset_table
)
27489 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27490 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
27492 /* Save and restore LR locally around this call (in R0). */
27493 if (!info
->lr_save_p
)
27494 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
27496 emit_insn (gen_load_macho_picbase (src
));
27498 emit_move_insn (gen_rtx_REG (Pmode
,
27499 RS6000_PIC_OFFSET_TABLE_REGNUM
),
27502 if (!info
->lr_save_p
)
27503 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
27507 /* If we need to, save the TOC register after doing the stack setup.
27508 Do not emit eh frame info for this save. The unwinder wants info,
27509 conceptually attached to instructions in this function, about
27510 register values in the caller of this function. This R2 may have
27511 already been changed from the value in the caller.
27512 We don't attempt to write accurate DWARF EH frame info for R2
27513 because code emitted by gcc for a (non-pointer) function call
27514 doesn't save and restore R2. Instead, R2 is managed out-of-line
27515 by a linker generated plt call stub when the function resides in
27516 a shared library. This behavior is costly to describe in DWARF,
27517 both in terms of the size of DWARF info and the time taken in the
27518 unwinder to interpret it. R2 changes, apart from the
27519 calls_eh_return case earlier in this function, are handled by
27520 linux-unwind.h frob_update_context. */
27521 if (rs6000_save_toc_in_prologue_p ())
27523 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
27524 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
27527 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27528 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
27529 emit_split_stack_prologue (info
, sp_adjust
, frame_off
, frame_reg_rtx
);
27532 /* Output .extern statements for the save/restore routines we use. */
27535 rs6000_output_savres_externs (FILE *file
)
27537 rs6000_stack_t
*info
= rs6000_stack_info ();
27539 if (TARGET_DEBUG_STACK
)
27540 debug_stack_info (info
);
27542 /* Write .extern for any function we will call to save and restore
27544 if (info
->first_fp_reg_save
< 64
27549 int regno
= info
->first_fp_reg_save
- 32;
27551 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
27553 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
27554 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27555 name
= rs6000_savres_routine_name (regno
, sel
);
27556 fprintf (file
, "\t.extern %s\n", name
);
27558 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
27560 bool lr
= (info
->savres_strategy
27561 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
27562 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27563 name
= rs6000_savres_routine_name (regno
, sel
);
27564 fprintf (file
, "\t.extern %s\n", name
);
27569 /* Write function prologue. */
27572 rs6000_output_function_prologue (FILE *file
,
27573 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
27575 if (!cfun
->is_thunk
)
27576 rs6000_output_savres_externs (file
);
27578 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27579 immediately after the global entry point label. */
27580 if (rs6000_global_entry_point_needed_p ())
27582 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
27584 (*targetm
.asm_out
.internal_label
) (file
, "LCF", rs6000_pic_labelno
);
27586 if (TARGET_CMODEL
!= CMODEL_LARGE
)
27588 /* In the small and medium code models, we assume the TOC is less
27589 2 GB away from the text section, so it can be computed via the
27590 following two-instruction sequence. */
27593 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27594 fprintf (file
, "0:\taddis 2,12,.TOC.-");
27595 assemble_name (file
, buf
);
27596 fprintf (file
, "@ha\n");
27597 fprintf (file
, "\taddi 2,2,.TOC.-");
27598 assemble_name (file
, buf
);
27599 fprintf (file
, "@l\n");
27603 /* In the large code model, we allow arbitrary offsets between the
27604 TOC and the text section, so we have to load the offset from
27605 memory. The data field is emitted directly before the global
27606 entry point in rs6000_elf_declare_function_name. */
27609 #ifdef HAVE_AS_ENTRY_MARKERS
27610 /* If supported by the linker, emit a marker relocation. If the
27611 total code size of the final executable or shared library
27612 happens to fit into 2 GB after all, the linker will replace
27613 this code sequence with the sequence for the small or medium
27615 fprintf (file
, "\t.reloc .,R_PPC64_ENTRY\n");
27617 fprintf (file
, "\tld 2,");
27618 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
27619 assemble_name (file
, buf
);
27620 fprintf (file
, "-");
27621 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27622 assemble_name (file
, buf
);
27623 fprintf (file
, "(12)\n");
27624 fprintf (file
, "\tadd 2,2,12\n");
27627 fputs ("\t.localentry\t", file
);
27628 assemble_name (file
, name
);
27629 fputs (",.-", file
);
27630 assemble_name (file
, name
);
27631 fputs ("\n", file
);
27634 /* Output -mprofile-kernel code. This needs to be done here instead of
27635 in output_function_profile since it must go after the ELFv2 ABI
27636 local entry point. */
27637 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
27639 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
27640 gcc_assert (!TARGET_32BIT
);
27642 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
27644 /* In the ELFv2 ABI we have no compiler stack word. It must be
27645 the resposibility of _mcount to preserve the static chain
27646 register if required. */
27647 if (DEFAULT_ABI
!= ABI_ELFv2
27648 && cfun
->static_chain_decl
!= NULL
)
27650 asm_fprintf (file
, "\tstd %s,24(%s)\n",
27651 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27652 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27653 asm_fprintf (file
, "\tld %s,24(%s)\n",
27654 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27657 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27660 rs6000_pic_labelno
++;
27663 /* -mprofile-kernel code calls mcount before the function prolog,
27664 so a profiled leaf function should stay a leaf function. */
27666 rs6000_keep_leaf_when_profiled ()
27668 return TARGET_PROFILE_KERNEL
;
27671 /* Non-zero if vmx regs are restored before the frame pop, zero if
27672 we restore after the pop when possible. */
27673 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27675 /* Restoring cr is a two step process: loading a reg from the frame
27676 save, then moving the reg to cr. For ABI_V4 we must let the
27677 unwinder know that the stack location is no longer valid at or
27678 before the stack deallocation, but we can't emit a cfa_restore for
27679 cr at the stack deallocation like we do for other registers.
27680 The trouble is that it is possible for the move to cr to be
27681 scheduled after the stack deallocation. So say exactly where cr
27682 is located on each of the two insns. */
27685 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
27687 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
27688 rtx reg
= gen_rtx_REG (SImode
, regno
);
27689 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
27691 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
27693 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
27694 rtx set
= gen_rtx_SET (reg
, cr
);
27696 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
27697 RTX_FRAME_RELATED_P (insn
) = 1;
27702 /* Reload CR from REG. */
27705 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
27710 if (using_mfcr_multiple
)
27712 for (i
= 0; i
< 8; i
++)
27713 if (save_reg_p (CR0_REGNO
+ i
))
27715 gcc_assert (count
);
27718 if (using_mfcr_multiple
&& count
> 1)
27724 p
= rtvec_alloc (count
);
27727 for (i
= 0; i
< 8; i
++)
27728 if (save_reg_p (CR0_REGNO
+ i
))
27730 rtvec r
= rtvec_alloc (2);
27731 RTVEC_ELT (r
, 0) = reg
;
27732 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
27733 RTVEC_ELT (p
, ndx
) =
27734 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
27735 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
27738 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27739 gcc_assert (ndx
== count
);
27741 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27742 CR field separately. */
27743 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
27745 for (i
= 0; i
< 8; i
++)
27746 if (save_reg_p (CR0_REGNO
+ i
))
27747 add_reg_note (insn
, REG_CFA_RESTORE
,
27748 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27750 RTX_FRAME_RELATED_P (insn
) = 1;
27754 for (i
= 0; i
< 8; i
++)
27755 if (save_reg_p (CR0_REGNO
+ i
))
27757 rtx insn
= emit_insn (gen_movsi_to_cr_one
27758 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
27760 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27761 CR field separately, attached to the insn that in fact
27762 restores this particular CR field. */
27763 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
27765 add_reg_note (insn
, REG_CFA_RESTORE
,
27766 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27768 RTX_FRAME_RELATED_P (insn
) = 1;
27772 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27773 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
27774 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
27776 rtx_insn
*insn
= get_last_insn ();
27777 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
27779 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
27780 RTX_FRAME_RELATED_P (insn
) = 1;
27784 /* Like cr, the move to lr instruction can be scheduled after the
27785 stack deallocation, but unlike cr, its stack frame save is still
27786 valid. So we only need to emit the cfa_restore on the correct
27790 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
27792 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
27793 rtx reg
= gen_rtx_REG (Pmode
, regno
);
27795 emit_move_insn (reg
, mem
);
27799 restore_saved_lr (int regno
, bool exit_func
)
27801 rtx reg
= gen_rtx_REG (Pmode
, regno
);
27802 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27803 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
27805 if (!exit_func
&& flag_shrink_wrap
)
27807 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27808 RTX_FRAME_RELATED_P (insn
) = 1;
27813 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
27815 if (DEFAULT_ABI
== ABI_ELFv2
)
27818 for (i
= 0; i
< 8; i
++)
27819 if (save_reg_p (CR0_REGNO
+ i
))
27821 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
27822 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
27826 else if (info
->cr_save_p
)
27827 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27828 gen_rtx_REG (SImode
, CR2_REGNO
),
27831 if (info
->lr_save_p
)
27832 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27833 gen_rtx_REG (Pmode
, LR_REGNO
),
27835 return cfa_restores
;
27838 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27839 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27840 below stack pointer not cloberred by signals. */
27843 offset_below_red_zone_p (HOST_WIDE_INT offset
)
27845 return offset
< (DEFAULT_ABI
== ABI_V4
27847 : TARGET_32BIT
? -220 : -288);
27850 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27853 emit_cfa_restores (rtx cfa_restores
)
27855 rtx_insn
*insn
= get_last_insn ();
27856 rtx
*loc
= ®_NOTES (insn
);
27859 loc
= &XEXP (*loc
, 1);
27860 *loc
= cfa_restores
;
27861 RTX_FRAME_RELATED_P (insn
) = 1;
27864 /* Emit function epilogue as insns. */
27867 rs6000_emit_epilogue (int sibcall
)
27869 rs6000_stack_t
*info
;
27870 int restoring_GPRs_inline
;
27871 int restoring_FPRs_inline
;
27872 int using_load_multiple
;
27873 int using_mtcr_multiple
;
27874 int use_backchain_to_restore_sp
;
27877 HOST_WIDE_INT frame_off
= 0;
27878 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
27879 rtx frame_reg_rtx
= sp_reg_rtx
;
27880 rtx cfa_restores
= NULL_RTX
;
27882 rtx cr_save_reg
= NULL_RTX
;
27883 machine_mode reg_mode
= Pmode
;
27884 int reg_size
= TARGET_32BIT
? 4 : 8;
27885 machine_mode fp_reg_mode
= (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
27887 int fp_reg_size
= 8;
27890 unsigned ptr_regno
;
27892 info
= rs6000_stack_info ();
27894 strategy
= info
->savres_strategy
;
27895 using_load_multiple
= strategy
& REST_MULTIPLE
;
27896 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
27897 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
27898 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
27899 || rs6000_cpu
== PROCESSOR_PPC603
27900 || rs6000_cpu
== PROCESSOR_PPC750
27902 /* Restore via the backchain when we have a large frame, since this
27903 is more efficient than an addis, addi pair. The second condition
27904 here will not trigger at the moment; We don't actually need a
27905 frame pointer for alloca, but the generic parts of the compiler
27906 give us one anyway. */
27907 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
27908 ? info
->lr_save_offset
27910 || (cfun
->calls_alloca
27911 && !frame_pointer_needed
));
27912 restore_lr
= (info
->lr_save_p
27913 && (restoring_FPRs_inline
27914 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
27915 && (restoring_GPRs_inline
27916 || info
->first_fp_reg_save
< 64)
27917 && !cfun
->machine
->lr_is_wrapped_separately
);
27920 if (WORLD_SAVE_P (info
))
27924 const char *alloc_rname
;
27927 /* eh_rest_world_r10 will return to the location saved in the LR
27928 stack slot (which is not likely to be our caller.)
27929 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27930 rest_world is similar, except any R10 parameter is ignored.
27931 The exception-handling stuff that was here in 2.95 is no
27932 longer necessary. */
27935 + 32 - info
->first_gp_reg_save
27936 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
27937 + 63 + 1 - info
->first_fp_reg_save
);
27939 strcpy (rname
, ((crtl
->calls_eh_return
) ?
27940 "*eh_rest_world_r10" : "*rest_world"));
27941 alloc_rname
= ggc_strdup (rname
);
27944 RTVEC_ELT (p
, j
++) = ret_rtx
;
27946 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
27947 /* The instruction pattern requires a clobber here;
27948 it is shared with the restVEC helper. */
27950 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
27953 /* CR register traditionally saved as CR2. */
27954 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
27956 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
27957 if (flag_shrink_wrap
)
27959 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27960 gen_rtx_REG (Pmode
, LR_REGNO
),
27962 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27966 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
27968 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
27970 = gen_frame_load (reg
,
27971 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
27972 if (flag_shrink_wrap
27973 && save_reg_p (info
->first_gp_reg_save
+ i
))
27974 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27976 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
27978 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
27980 = gen_frame_load (reg
,
27981 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
27982 if (flag_shrink_wrap
27983 && save_reg_p (info
->first_altivec_reg_save
+ i
))
27984 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27986 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
27988 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
27989 ? DFmode
: SFmode
),
27990 info
->first_fp_reg_save
+ i
);
27992 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
27993 if (flag_shrink_wrap
27994 && save_reg_p (info
->first_fp_reg_save
+ i
))
27995 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27998 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
28000 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
28002 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
28004 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
28006 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
28007 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28009 if (flag_shrink_wrap
)
28011 REG_NOTES (insn
) = cfa_restores
;
28012 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28013 RTX_FRAME_RELATED_P (insn
) = 1;
28018 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28020 frame_off
= info
->total_size
;
28022 /* Restore AltiVec registers if we must do so before adjusting the
28024 if (info
->altivec_size
!= 0
28025 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28026 || (DEFAULT_ABI
!= ABI_V4
28027 && offset_below_red_zone_p (info
->altivec_save_offset
))))
28030 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28032 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
28033 if (use_backchain_to_restore_sp
)
28035 int frame_regno
= 11;
28037 if ((strategy
& REST_INLINE_VRS
) == 0)
28039 /* Of r11 and r12, select the one not clobbered by an
28040 out-of-line restore function for the frame register. */
28041 frame_regno
= 11 + 12 - scratch_regno
;
28043 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
28044 emit_move_insn (frame_reg_rtx
,
28045 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28048 else if (frame_pointer_needed
)
28049 frame_reg_rtx
= hard_frame_pointer_rtx
;
28051 if ((strategy
& REST_INLINE_VRS
) == 0)
28053 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28055 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28056 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28058 if (end_save
+ frame_off
!= 0)
28060 rtx offset
= GEN_INT (end_save
+ frame_off
);
28062 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28065 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28067 ptr_off
= -end_save
;
28068 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28069 info
->altivec_save_offset
+ ptr_off
,
28070 0, V4SImode
, SAVRES_VR
);
28074 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28075 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28077 rtx addr
, areg
, mem
, insn
;
28078 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28079 HOST_WIDE_INT offset
28080 = (info
->altivec_save_offset
+ frame_off
28081 + 16 * (i
- info
->first_altivec_reg_save
));
28083 if (TARGET_P9_DFORM_VECTOR
&& quad_address_offset_p (offset
))
28085 mem
= gen_frame_mem (V4SImode
,
28086 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28087 GEN_INT (offset
)));
28088 insn
= gen_rtx_SET (reg
, mem
);
28092 areg
= gen_rtx_REG (Pmode
, 0);
28093 emit_move_insn (areg
, GEN_INT (offset
));
28095 /* AltiVec addressing mode is [reg+reg]. */
28096 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28097 mem
= gen_frame_mem (V4SImode
, addr
);
28099 /* Rather than emitting a generic move, force use of the
28100 lvx instruction, which we always want. In particular we
28101 don't want lxvd2x/xxpermdi for little endian. */
28102 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28105 (void) emit_insn (insn
);
28109 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28110 if (((strategy
& REST_INLINE_VRS
) == 0
28111 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28112 && (flag_shrink_wrap
28113 || (offset_below_red_zone_p
28114 (info
->altivec_save_offset
28115 + 16 * (i
- info
->first_altivec_reg_save
))))
28118 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28119 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28123 /* Restore VRSAVE if we must do so before adjusting the stack. */
28124 if (info
->vrsave_size
!= 0
28125 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28126 || (DEFAULT_ABI
!= ABI_V4
28127 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
28131 if (frame_reg_rtx
== sp_reg_rtx
)
28133 if (use_backchain_to_restore_sp
)
28135 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28136 emit_move_insn (frame_reg_rtx
,
28137 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28140 else if (frame_pointer_needed
)
28141 frame_reg_rtx
= hard_frame_pointer_rtx
;
28144 reg
= gen_rtx_REG (SImode
, 12);
28145 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28146 info
->vrsave_save_offset
+ frame_off
));
28148 emit_insn (generate_set_vrsave (reg
, info
, 1));
28152 /* If we have a large stack frame, restore the old stack pointer
28153 using the backchain. */
28154 if (use_backchain_to_restore_sp
)
28156 if (frame_reg_rtx
== sp_reg_rtx
)
28158 /* Under V.4, don't reset the stack pointer until after we're done
28159 loading the saved registers. */
28160 if (DEFAULT_ABI
== ABI_V4
)
28161 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28163 insn
= emit_move_insn (frame_reg_rtx
,
28164 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28167 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28168 && DEFAULT_ABI
== ABI_V4
)
28169 /* frame_reg_rtx has been set up by the altivec restore. */
28173 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
28174 frame_reg_rtx
= sp_reg_rtx
;
28177 /* If we have a frame pointer, we can restore the old stack pointer
28179 else if (frame_pointer_needed
)
28181 frame_reg_rtx
= sp_reg_rtx
;
28182 if (DEFAULT_ABI
== ABI_V4
)
28183 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28184 /* Prevent reordering memory accesses against stack pointer restore. */
28185 else if (cfun
->calls_alloca
28186 || offset_below_red_zone_p (-info
->total_size
))
28187 rs6000_emit_stack_tie (frame_reg_rtx
, true);
28189 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
28190 GEN_INT (info
->total_size
)));
28193 else if (info
->push_p
28194 && DEFAULT_ABI
!= ABI_V4
28195 && !crtl
->calls_eh_return
)
28197 /* Prevent reordering memory accesses against stack pointer restore. */
28198 if (cfun
->calls_alloca
28199 || offset_below_red_zone_p (-info
->total_size
))
28200 rs6000_emit_stack_tie (frame_reg_rtx
, false);
28201 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
28202 GEN_INT (info
->total_size
)));
28205 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
28209 REG_NOTES (insn
) = cfa_restores
;
28210 cfa_restores
= NULL_RTX
;
28212 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28213 RTX_FRAME_RELATED_P (insn
) = 1;
28216 /* Restore AltiVec registers if we have not done so already. */
28217 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28218 && info
->altivec_size
!= 0
28219 && (DEFAULT_ABI
== ABI_V4
28220 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
28224 if ((strategy
& REST_INLINE_VRS
) == 0)
28226 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28228 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28229 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28230 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28232 if (end_save
+ frame_off
!= 0)
28234 rtx offset
= GEN_INT (end_save
+ frame_off
);
28236 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28239 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28241 ptr_off
= -end_save
;
28242 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28243 info
->altivec_save_offset
+ ptr_off
,
28244 0, V4SImode
, SAVRES_VR
);
28245 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
28247 /* Frame reg was clobbered by out-of-line save. Restore it
28248 from ptr_reg, and if we are calling out-of-line gpr or
28249 fpr restore set up the correct pointer and offset. */
28250 unsigned newptr_regno
= 1;
28251 if (!restoring_GPRs_inline
)
28253 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28254 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28255 newptr_regno
= ptr_regno_for_savres (sel
);
28256 end_save
= info
->gp_save_offset
+ info
->gp_size
;
28258 else if (!restoring_FPRs_inline
)
28260 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
28261 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28262 newptr_regno
= ptr_regno_for_savres (sel
);
28263 end_save
= info
->fp_save_offset
+ info
->fp_size
;
28266 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
28267 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
28269 if (end_save
+ ptr_off
!= 0)
28271 rtx offset
= GEN_INT (end_save
+ ptr_off
);
28273 frame_off
= -end_save
;
28275 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
28278 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
28283 frame_off
= ptr_off
;
28284 emit_move_insn (frame_reg_rtx
, ptr_reg
);
28290 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28291 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28293 rtx addr
, areg
, mem
, insn
;
28294 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28295 HOST_WIDE_INT offset
28296 = (info
->altivec_save_offset
+ frame_off
28297 + 16 * (i
- info
->first_altivec_reg_save
));
28299 if (TARGET_P9_DFORM_VECTOR
&& quad_address_offset_p (offset
))
28301 mem
= gen_frame_mem (V4SImode
,
28302 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28303 GEN_INT (offset
)));
28304 insn
= gen_rtx_SET (reg
, mem
);
28308 areg
= gen_rtx_REG (Pmode
, 0);
28309 emit_move_insn (areg
, GEN_INT (offset
));
28311 /* AltiVec addressing mode is [reg+reg]. */
28312 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28313 mem
= gen_frame_mem (V4SImode
, addr
);
28315 /* Rather than emitting a generic move, force use of the
28316 lvx instruction, which we always want. In particular we
28317 don't want lxvd2x/xxpermdi for little endian. */
28318 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28321 (void) emit_insn (insn
);
28325 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28326 if (((strategy
& REST_INLINE_VRS
) == 0
28327 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28328 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28331 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28332 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28336 /* Restore VRSAVE if we have not done so already. */
28337 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28338 && info
->vrsave_size
!= 0
28339 && (DEFAULT_ABI
== ABI_V4
28340 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
28344 reg
= gen_rtx_REG (SImode
, 12);
28345 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28346 info
->vrsave_save_offset
+ frame_off
));
28348 emit_insn (generate_set_vrsave (reg
, info
, 1));
28351 /* If we exit by an out-of-line restore function on ABI_V4 then that
28352 function will deallocate the stack, so we don't need to worry
28353 about the unwinder restoring cr from an invalid stack frame
28355 exit_func
= (!restoring_FPRs_inline
28356 || (!restoring_GPRs_inline
28357 && info
->first_fp_reg_save
== 64));
28359 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28360 *separate* slots if the routine calls __builtin_eh_return, so
28361 that they can be independently restored by the unwinder. */
28362 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
28364 int i
, cr_off
= info
->ehcr_offset
;
28366 for (i
= 0; i
< 8; i
++)
28367 if (!call_used_regs
[CR0_REGNO
+ i
])
28369 rtx reg
= gen_rtx_REG (SImode
, 0);
28370 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28371 cr_off
+ frame_off
));
28373 insn
= emit_insn (gen_movsi_to_cr_one
28374 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
28376 if (!exit_func
&& flag_shrink_wrap
)
28378 add_reg_note (insn
, REG_CFA_RESTORE
,
28379 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28381 RTX_FRAME_RELATED_P (insn
) = 1;
28384 cr_off
+= reg_size
;
28388 /* Get the old lr if we saved it. If we are restoring registers
28389 out-of-line, then the out-of-line routines can do this for us. */
28390 if (restore_lr
&& restoring_GPRs_inline
)
28391 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28393 /* Get the old cr if we saved it. */
28394 if (info
->cr_save_p
)
28396 unsigned cr_save_regno
= 12;
28398 if (!restoring_GPRs_inline
)
28400 /* Ensure we don't use the register used by the out-of-line
28401 gpr register restore below. */
28402 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28403 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28404 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
28406 if (gpr_ptr_regno
== 12)
28407 cr_save_regno
= 11;
28408 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
28410 else if (REGNO (frame_reg_rtx
) == 12)
28411 cr_save_regno
= 11;
28413 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
28414 info
->cr_save_offset
+ frame_off
,
28418 /* Set LR here to try to overlap restores below. */
28419 if (restore_lr
&& restoring_GPRs_inline
)
28420 restore_saved_lr (0, exit_func
);
28422 /* Load exception handler data registers, if needed. */
28423 if (crtl
->calls_eh_return
)
28425 unsigned int i
, regno
;
28429 rtx reg
= gen_rtx_REG (reg_mode
, 2);
28430 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28431 frame_off
+ RS6000_TOC_SAVE_SLOT
));
28438 regno
= EH_RETURN_DATA_REGNO (i
);
28439 if (regno
== INVALID_REGNUM
)
28442 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
28443 info
->ehrd_offset
+ frame_off
28444 + reg_size
* (int) i
);
28446 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
28450 /* Restore GPRs. This is done as a PARALLEL if we are using
28451 the load-multiple instructions. */
28452 if (!restoring_GPRs_inline
)
28454 /* We are jumping to an out-of-line function. */
28456 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
28457 bool can_use_exit
= end_save
== 0;
28458 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
28461 /* Emit stack reset code if we need it. */
28462 ptr_regno
= ptr_regno_for_savres (sel
);
28463 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28465 rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28466 else if (end_save
+ frame_off
!= 0)
28467 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
28468 GEN_INT (end_save
+ frame_off
)));
28469 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
28470 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28471 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28472 frame_off
= -end_save
;
28474 if (can_use_exit
&& info
->cr_save_p
)
28475 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
28477 ptr_off
= -end_save
;
28478 rs6000_emit_savres_rtx (info
, ptr_reg
,
28479 info
->gp_save_offset
+ ptr_off
,
28480 info
->lr_save_offset
+ ptr_off
,
28483 else if (using_load_multiple
)
28486 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
28487 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28489 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
28491 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
28492 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28496 int offset
= info
->gp_save_offset
+ frame_off
;
28497 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28500 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28502 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28503 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28506 offset
+= reg_size
;
28510 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28512 /* If the frame pointer was used then we can't delay emitting
28513 a REG_CFA_DEF_CFA note. This must happen on the insn that
28514 restores the frame pointer, r31. We may have already emitted
28515 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28516 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28517 be harmless if emitted. */
28518 if (frame_pointer_needed
)
28520 insn
= get_last_insn ();
28521 add_reg_note (insn
, REG_CFA_DEF_CFA
,
28522 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
28523 RTX_FRAME_RELATED_P (insn
) = 1;
28526 /* Set up cfa_restores. We always need these when
28527 shrink-wrapping. If not shrink-wrapping then we only need
28528 the cfa_restore when the stack location is no longer valid.
28529 The cfa_restores must be emitted on or before the insn that
28530 invalidates the stack, and of course must not be emitted
28531 before the insn that actually does the restore. The latter
28532 is why it is a bad idea to emit the cfa_restores as a group
28533 on the last instruction here that actually does a restore:
28534 That insn may be reordered with respect to others doing
28536 if (flag_shrink_wrap
28537 && !restoring_GPRs_inline
28538 && info
->first_fp_reg_save
== 64)
28539 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28541 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28543 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28545 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28546 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28550 if (!restoring_GPRs_inline
28551 && info
->first_fp_reg_save
== 64)
28553 /* We are jumping to an out-of-line function. */
28555 emit_cfa_restores (cfa_restores
);
28559 if (restore_lr
&& !restoring_GPRs_inline
)
28561 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28562 restore_saved_lr (0, exit_func
);
28565 /* Restore fpr's if we need to do it without calling a function. */
28566 if (restoring_FPRs_inline
)
28568 int offset
= info
->fp_save_offset
+ frame_off
;
28569 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
28572 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
28574 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
28575 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28576 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28577 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
28581 offset
+= fp_reg_size
;
28585 /* If we saved cr, restore it here. Just those that were used. */
28586 if (info
->cr_save_p
)
28587 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
28589 /* If this is V.4, unwind the stack pointer after all of the loads
28590 have been done, or set up r11 if we are restoring fp out of line. */
28592 if (!restoring_FPRs_inline
)
28594 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28595 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28596 ptr_regno
= ptr_regno_for_savres (sel
);
28599 insn
= rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28600 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28603 if (insn
&& restoring_FPRs_inline
)
28607 REG_NOTES (insn
) = cfa_restores
;
28608 cfa_restores
= NULL_RTX
;
28610 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28611 RTX_FRAME_RELATED_P (insn
) = 1;
28614 if (crtl
->calls_eh_return
)
28616 rtx sa
= EH_RETURN_STACKADJ_RTX
;
28617 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
28620 if (!sibcall
&& restoring_FPRs_inline
)
28624 /* We can't hang the cfa_restores off a simple return,
28625 since the shrink-wrap code sometimes uses an existing
28626 return. This means there might be a path from
28627 pre-prologue code to this return, and dwarf2cfi code
28628 wants the eh_frame unwinder state to be the same on
28629 all paths to any point. So we need to emit the
28630 cfa_restores before the return. For -m64 we really
28631 don't need epilogue cfa_restores at all, except for
28632 this irritating dwarf2cfi with shrink-wrap
28633 requirement; The stack red-zone means eh_frame info
28634 from the prologue telling the unwinder to restore
28635 from the stack is perfectly good right to the end of
28637 emit_insn (gen_blockage ());
28638 emit_cfa_restores (cfa_restores
);
28639 cfa_restores
= NULL_RTX
;
28642 emit_jump_insn (targetm
.gen_simple_return ());
28645 if (!sibcall
&& !restoring_FPRs_inline
)
28647 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28648 rtvec p
= rtvec_alloc (3 + !!lr
+ 64 - info
->first_fp_reg_save
);
28650 RTVEC_ELT (p
, elt
++) = ret_rtx
;
28652 RTVEC_ELT (p
, elt
++)
28653 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
28655 /* We have to restore more than two FP registers, so branch to the
28656 restore function. It will return to our caller. */
28661 if (flag_shrink_wrap
)
28662 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28664 sym
= rs6000_savres_routine_sym (info
, SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
28665 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, sym
);
28666 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
28667 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
28669 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
28671 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
28673 RTVEC_ELT (p
, elt
++)
28674 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
28675 if (flag_shrink_wrap
28676 && save_reg_p (info
->first_fp_reg_save
+ i
))
28677 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28680 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28686 /* Ensure the cfa_restores are hung off an insn that won't
28687 be reordered above other restores. */
28688 emit_insn (gen_blockage ());
28690 emit_cfa_restores (cfa_restores
);
28694 /* Write function epilogue. */
28697 rs6000_output_function_epilogue (FILE *file
,
28698 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
28701 macho_branch_islands ();
28704 rtx_insn
*insn
= get_last_insn ();
28705 rtx_insn
*deleted_debug_label
= NULL
;
28707 /* Mach-O doesn't support labels at the end of objects, so if
28708 it looks like we might want one, take special action.
28710 First, collect any sequence of deleted debug labels. */
28713 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
28715 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28716 notes only, instead set their CODE_LABEL_NUMBER to -1,
28717 otherwise there would be code generation differences
28718 in between -g and -g0. */
28719 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
28720 deleted_debug_label
= insn
;
28721 insn
= PREV_INSN (insn
);
28724 /* Second, if we have:
28727 then this needs to be detected, so skip past the barrier. */
28729 if (insn
&& BARRIER_P (insn
))
28730 insn
= PREV_INSN (insn
);
28732 /* Up to now we've only seen notes or barriers. */
28737 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
))
28738 /* Trailing label: <barrier>. */
28739 fputs ("\tnop\n", file
);
28742 /* Lastly, see if we have a completely empty function body. */
28743 while (insn
&& ! INSN_P (insn
))
28744 insn
= PREV_INSN (insn
);
28745 /* If we don't find any insns, we've got an empty function body;
28746 I.e. completely empty - without a return or branch. This is
28747 taken as the case where a function body has been removed
28748 because it contains an inline __builtin_unreachable(). GCC
28749 states that reaching __builtin_unreachable() means UB so we're
28750 not obliged to do anything special; however, we want
28751 non-zero-sized function bodies. To meet this, and help the
28752 user out, let's trap the case. */
28754 fputs ("\ttrap\n", file
);
28757 else if (deleted_debug_label
)
28758 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
28759 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
28760 CODE_LABEL_NUMBER (insn
) = -1;
28764 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28767 We don't output a traceback table if -finhibit-size-directive was
28768 used. The documentation for -finhibit-size-directive reads
28769 ``don't output a @code{.size} assembler directive, or anything
28770 else that would cause trouble if the function is split in the
28771 middle, and the two halves are placed at locations far apart in
28772 memory.'' The traceback table has this property, since it
28773 includes the offset from the start of the function to the
28774 traceback table itself.
28776 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28777 different traceback table. */
28778 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28779 && ! flag_inhibit_size_directive
28780 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
28782 const char *fname
= NULL
;
28783 const char *language_string
= lang_hooks
.name
;
28784 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
28786 int optional_tbtab
;
28787 rs6000_stack_t
*info
= rs6000_stack_info ();
28789 if (rs6000_traceback
== traceback_full
)
28790 optional_tbtab
= 1;
28791 else if (rs6000_traceback
== traceback_part
)
28792 optional_tbtab
= 0;
28794 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
28796 if (optional_tbtab
)
28798 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
28799 while (*fname
== '.') /* V.4 encodes . in the name */
28802 /* Need label immediately before tbtab, so we can compute
28803 its offset from the function start. */
28804 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
28805 ASM_OUTPUT_LABEL (file
, fname
);
28808 /* The .tbtab pseudo-op can only be used for the first eight
28809 expressions, since it can't handle the possibly variable
28810 length fields that follow. However, if you omit the optional
28811 fields, the assembler outputs zeros for all optional fields
28812 anyways, giving each variable length field is minimum length
28813 (as defined in sys/debug.h). Thus we can not use the .tbtab
28814 pseudo-op at all. */
28816 /* An all-zero word flags the start of the tbtab, for debuggers
28817 that have to find it by searching forward from the entry
28818 point or from the current pc. */
28819 fputs ("\t.long 0\n", file
);
28821 /* Tbtab format type. Use format type 0. */
28822 fputs ("\t.byte 0,", file
);
28824 /* Language type. Unfortunately, there does not seem to be any
28825 official way to discover the language being compiled, so we
28826 use language_string.
28827 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
28828 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28829 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
28830 either, so for now use 0. */
28832 || ! strcmp (language_string
, "GNU GIMPLE")
28833 || ! strcmp (language_string
, "GNU Go")
28834 || ! strcmp (language_string
, "libgccjit"))
28836 else if (! strcmp (language_string
, "GNU F77")
28837 || lang_GNU_Fortran ())
28839 else if (! strcmp (language_string
, "GNU Pascal"))
28841 else if (! strcmp (language_string
, "GNU Ada"))
28843 else if (lang_GNU_CXX ()
28844 || ! strcmp (language_string
, "GNU Objective-C++"))
28846 else if (! strcmp (language_string
, "GNU Java"))
28848 else if (! strcmp (language_string
, "GNU Objective-C"))
28851 gcc_unreachable ();
28852 fprintf (file
, "%d,", i
);
28854 /* 8 single bit fields: global linkage (not set for C extern linkage,
28855 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28856 from start of procedure stored in tbtab, internal function, function
28857 has controlled storage, function has no toc, function uses fp,
28858 function logs/aborts fp operations. */
28859 /* Assume that fp operations are used if any fp reg must be saved. */
28860 fprintf (file
, "%d,",
28861 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
28863 /* 6 bitfields: function is interrupt handler, name present in
28864 proc table, function calls alloca, on condition directives
28865 (controls stack walks, 3 bits), saves condition reg, saves
28867 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28868 set up as a frame pointer, even when there is no alloca call. */
28869 fprintf (file
, "%d,",
28870 ((optional_tbtab
<< 6)
28871 | ((optional_tbtab
& frame_pointer_needed
) << 5)
28872 | (info
->cr_save_p
<< 1)
28873 | (info
->lr_save_p
)));
28875 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28877 fprintf (file
, "%d,",
28878 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
28880 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28881 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
28883 if (optional_tbtab
)
28885 /* Compute the parameter info from the function decl argument
28888 int next_parm_info_bit
= 31;
28890 for (decl
= DECL_ARGUMENTS (current_function_decl
);
28891 decl
; decl
= DECL_CHAIN (decl
))
28893 rtx parameter
= DECL_INCOMING_RTL (decl
);
28894 machine_mode mode
= GET_MODE (parameter
);
28896 if (GET_CODE (parameter
) == REG
)
28898 if (SCALAR_FLOAT_MODE_P (mode
))
28921 gcc_unreachable ();
28924 /* If only one bit will fit, don't or in this entry. */
28925 if (next_parm_info_bit
> 0)
28926 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
28927 next_parm_info_bit
-= 2;
28931 fixed_parms
+= ((GET_MODE_SIZE (mode
)
28932 + (UNITS_PER_WORD
- 1))
28934 next_parm_info_bit
-= 1;
28940 /* Number of fixed point parameters. */
28941 /* This is actually the number of words of fixed point parameters; thus
28942 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28943 fprintf (file
, "%d,", fixed_parms
);
28945 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28947 /* This is actually the number of fp registers that hold parameters;
28948 and thus the maximum value is 13. */
28949 /* Set parameters on stack bit if parameters are not in their original
28950 registers, regardless of whether they are on the stack? Xlc
28951 seems to set the bit when not optimizing. */
28952 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
28954 if (optional_tbtab
)
28956 /* Optional fields follow. Some are variable length. */
28958 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28959 float, 11 double float. */
28960 /* There is an entry for each parameter in a register, in the order
28961 that they occur in the parameter list. Any intervening arguments
28962 on the stack are ignored. If the list overflows a long (max
28963 possible length 34 bits) then completely leave off all elements
28965 /* Only emit this long if there was at least one parameter. */
28966 if (fixed_parms
|| float_parms
)
28967 fprintf (file
, "\t.long %d\n", parm_info
);
28969 /* Offset from start of code to tb table. */
28970 fputs ("\t.long ", file
);
28971 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
28972 RS6000_OUTPUT_BASENAME (file
, fname
);
28974 rs6000_output_function_entry (file
, fname
);
28977 /* Interrupt handler mask. */
28978 /* Omit this long, since we never set the interrupt handler bit
28981 /* Number of CTL (controlled storage) anchors. */
28982 /* Omit this long, since the has_ctl bit is never set above. */
28984 /* Displacement into stack of each CTL anchor. */
28985 /* Omit this list of longs, because there are no CTL anchors. */
28987 /* Length of function name. */
28990 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
28992 /* Function name. */
28993 assemble_string (fname
, strlen (fname
));
28995 /* Register for alloca automatic storage; this is always reg 31.
28996 Only emit this if the alloca bit was set above. */
28997 if (frame_pointer_needed
)
28998 fputs ("\t.byte 31\n", file
);
29000 fputs ("\t.align 2\n", file
);
29004 /* Arrange to define .LCTOC1 label, if not already done. */
29008 if (!toc_initialized
)
29010 switch_to_section (toc_section
);
29011 switch_to_section (current_function_section ());
29016 /* -fsplit-stack support. */
29018 /* A SYMBOL_REF for __morestack. */
29019 static GTY(()) rtx morestack_ref
;
29022 gen_add3_const (rtx rt
, rtx ra
, long c
)
29025 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
29027 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
29030 /* Emit -fsplit-stack prologue, which goes before the regular function
29031 prologue (at local entry point in the case of ELFv2). */
29034 rs6000_expand_split_stack_prologue (void)
29036 rs6000_stack_t
*info
= rs6000_stack_info ();
29037 unsigned HOST_WIDE_INT allocate
;
29038 long alloc_hi
, alloc_lo
;
29039 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
29042 gcc_assert (flag_split_stack
&& reload_completed
);
29047 if (global_regs
[29])
29049 error ("%qs uses register r29", "-fsplit-stack");
29050 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
29051 "conflicts with %qD", global_regs_decl
[29]);
29054 allocate
= info
->total_size
;
29055 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
29057 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29060 if (morestack_ref
== NULL_RTX
)
29062 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
29063 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
29064 | SYMBOL_FLAG_FUNCTION
);
29067 r0
= gen_rtx_REG (Pmode
, 0);
29068 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29069 r12
= gen_rtx_REG (Pmode
, 12);
29070 emit_insn (gen_load_split_stack_limit (r0
));
29071 /* Always emit two insns here to calculate the requested stack,
29072 so that the linker can edit them when adjusting size for calling
29073 non-split-stack code. */
29074 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
29075 alloc_lo
= -allocate
- alloc_hi
;
29078 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
29080 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
29082 emit_insn (gen_nop ());
29086 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
29087 emit_insn (gen_nop ());
29090 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
29091 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
29092 ok_label
= gen_label_rtx ();
29093 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
29094 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
29095 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
29097 insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
29098 JUMP_LABEL (insn
) = ok_label
;
29099 /* Mark the jump as very likely to be taken. */
29100 add_reg_br_prob_note (insn
, profile_probability::very_likely ());
29102 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
29103 insn
= emit_move_insn (r0
, lr
);
29104 RTX_FRAME_RELATED_P (insn
) = 1;
29105 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
29106 RTX_FRAME_RELATED_P (insn
) = 1;
29108 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
29109 const0_rtx
, const0_rtx
));
29110 call_fusage
= NULL_RTX
;
29111 use_reg (&call_fusage
, r12
);
29112 /* Say the call uses r0, even though it doesn't, to stop regrename
29113 from twiddling with the insns saving lr, trashing args for cfun.
29114 The insns restoring lr are similarly protected by making
29115 split_stack_return use r0. */
29116 use_reg (&call_fusage
, r0
);
29117 add_function_usage_to (insn
, call_fusage
);
29118 /* Indicate that this function can't jump to non-local gotos. */
29119 make_reg_eh_region_note_nothrow_nononlocal (insn
);
29120 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
29121 insn
= emit_move_insn (lr
, r0
);
29122 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
29123 RTX_FRAME_RELATED_P (insn
) = 1;
29124 emit_insn (gen_split_stack_return ());
29126 emit_label (ok_label
);
29127 LABEL_NUSES (ok_label
) = 1;
29130 /* Return the internal arg pointer used for function incoming
29131 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29132 to copy it to a pseudo in order for it to be preserved over calls
29133 and suchlike. We'd really like to use a pseudo here for the
29134 internal arg pointer but data-flow analysis is not prepared to
29135 accept pseudos as live at the beginning of a function. */
29138 rs6000_internal_arg_pointer (void)
29140 if (flag_split_stack
29141 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
29145 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
29149 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
29150 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
29152 /* Put the pseudo initialization right after the note at the
29153 beginning of the function. */
29154 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
29155 gen_rtx_REG (Pmode
, 12));
29156 push_topmost_sequence ();
29157 emit_insn_after (pat
, get_insns ());
29158 pop_topmost_sequence ();
29160 return plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
29161 FIRST_PARM_OFFSET (current_function_decl
));
29163 return virtual_incoming_args_rtx
;
29166 /* We may have to tell the dataflow pass that the split stack prologue
29167 is initializing a register. */
29170 rs6000_live_on_entry (bitmap regs
)
29172 if (flag_split_stack
)
29173 bitmap_set_bit (regs
, 12);
29176 /* Emit -fsplit-stack dynamic stack allocation space check. */
29179 rs6000_split_stack_space_check (rtx size
, rtx label
)
29181 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29182 rtx limit
= gen_reg_rtx (Pmode
);
29183 rtx requested
= gen_reg_rtx (Pmode
);
29184 rtx cmp
= gen_reg_rtx (CCUNSmode
);
29187 emit_insn (gen_load_split_stack_limit (limit
));
29188 if (CONST_INT_P (size
))
29189 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
29192 size
= force_reg (Pmode
, size
);
29193 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
29195 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
29196 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
29197 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
29198 gen_rtx_LABEL_REF (VOIDmode
, label
),
29200 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
29201 JUMP_LABEL (jump
) = label
;
29204 /* A C compound statement that outputs the assembler code for a thunk
29205 function, used to implement C++ virtual function calls with
29206 multiple inheritance. The thunk acts as a wrapper around a virtual
29207 function, adjusting the implicit object parameter before handing
29208 control off to the real function.
29210 First, emit code to add the integer DELTA to the location that
29211 contains the incoming first argument. Assume that this argument
29212 contains a pointer, and is the one used to pass the `this' pointer
29213 in C++. This is the incoming argument *before* the function
29214 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29215 values of all other incoming arguments.
29217 After the addition, emit code to jump to FUNCTION, which is a
29218 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29219 not touch the return address. Hence returning from FUNCTION will
29220 return to whoever called the current `thunk'.
29222 The effect must be as if FUNCTION had been called directly with the
29223 adjusted first argument. This macro is responsible for emitting
29224 all of the code for a thunk function; output_function_prologue()
29225 and output_function_epilogue() are not invoked.
29227 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29228 been extracted from it.) It might possibly be useful on some
29229 targets, but probably not.
29231 If you do not define this macro, the target-independent code in the
29232 C++ frontend will generate a less efficient heavyweight thunk that
29233 calls FUNCTION instead of jumping to it. The generic approach does
29234 not support varargs. */
29237 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
29238 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
29241 rtx this_rtx
, funexp
;
29244 reload_completed
= 1;
29245 epilogue_completed
= 1;
29247 /* Mark the end of the (empty) prologue. */
29248 emit_note (NOTE_INSN_PROLOGUE_END
);
29250 /* Find the "this" pointer. If the function returns a structure,
29251 the structure return pointer is in r3. */
29252 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
29253 this_rtx
= gen_rtx_REG (Pmode
, 4);
29255 this_rtx
= gen_rtx_REG (Pmode
, 3);
29257 /* Apply the constant offset, if required. */
29259 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
29261 /* Apply the offset from the vtable, if required. */
29264 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
29265 rtx tmp
= gen_rtx_REG (Pmode
, 12);
29267 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
29268 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
29270 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
29271 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
29275 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
29277 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
29279 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
29282 /* Generate a tail call to the target function. */
29283 if (!TREE_USED (function
))
29285 assemble_external (function
);
29286 TREE_USED (function
) = 1;
29288 funexp
= XEXP (DECL_RTL (function
), 0);
29289 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
29292 if (MACHOPIC_INDIRECT
)
29293 funexp
= machopic_indirect_call_target (funexp
);
29296 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29297 generate sibcall RTL explicitly. */
29298 insn
= emit_call_insn (
29299 gen_rtx_PARALLEL (VOIDmode
,
29301 gen_rtx_CALL (VOIDmode
,
29302 funexp
, const0_rtx
),
29303 gen_rtx_USE (VOIDmode
, const0_rtx
),
29304 simple_return_rtx
)));
29305 SIBLING_CALL_P (insn
) = 1;
29308 /* Run just enough of rest_of_compilation to get the insns emitted.
29309 There's not really enough bulk here to make other passes such as
29310 instruction scheduling worth while. Note that use_thunk calls
29311 assemble_start_function and assemble_end_function. */
29312 insn
= get_insns ();
29313 shorten_branches (insn
);
29314 final_start_function (insn
, file
, 1);
29315 final (insn
, file
, 1);
29316 final_end_function ();
29318 reload_completed
= 0;
29319 epilogue_completed
= 0;
29322 /* A quick summary of the various types of 'constant-pool tables'
29325 Target Flags Name One table per
29326 AIX (none) AIX TOC object file
29327 AIX -mfull-toc AIX TOC object file
29328 AIX -mminimal-toc AIX minimal TOC translation unit
29329 SVR4/EABI (none) SVR4 SDATA object file
29330 SVR4/EABI -fpic SVR4 pic object file
29331 SVR4/EABI -fPIC SVR4 PIC translation unit
29332 SVR4/EABI -mrelocatable EABI TOC function
29333 SVR4/EABI -maix AIX TOC object file
29334 SVR4/EABI -maix -mminimal-toc
29335 AIX minimal TOC translation unit
29337 Name Reg. Set by entries contains:
29338 made by addrs? fp? sum?
29340 AIX TOC 2 crt0 as Y option option
29341 AIX minimal TOC 30 prolog gcc Y Y option
29342 SVR4 SDATA 13 crt0 gcc N Y N
29343 SVR4 pic 30 prolog ld Y not yet N
29344 SVR4 PIC 30 prolog gcc Y option option
29345 EABI TOC 30 prolog gcc Y option option
29349 /* Hash functions for the hash table. */
29352 rs6000_hash_constant (rtx k
)
29354 enum rtx_code code
= GET_CODE (k
);
29355 machine_mode mode
= GET_MODE (k
);
29356 unsigned result
= (code
<< 3) ^ mode
;
29357 const char *format
;
29360 format
= GET_RTX_FORMAT (code
);
29361 flen
= strlen (format
);
29367 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
29369 case CONST_WIDE_INT
:
29372 flen
= CONST_WIDE_INT_NUNITS (k
);
29373 for (i
= 0; i
< flen
; i
++)
29374 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
29379 if (mode
!= VOIDmode
)
29380 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
29392 for (; fidx
< flen
; fidx
++)
29393 switch (format
[fidx
])
29398 const char *str
= XSTR (k
, fidx
);
29399 len
= strlen (str
);
29400 result
= result
* 613 + len
;
29401 for (i
= 0; i
< len
; i
++)
29402 result
= result
* 613 + (unsigned) str
[i
];
29407 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
29411 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
29414 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
29415 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
29419 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
29420 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
29427 gcc_unreachable ();
29434 toc_hasher::hash (toc_hash_struct
*thc
)
29436 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
29439 /* Compare H1 and H2 for equivalence. */
29442 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
29447 if (h1
->key_mode
!= h2
->key_mode
)
29450 return rtx_equal_p (r1
, r2
);
29453 /* These are the names given by the C++ front-end to vtables, and
29454 vtable-like objects. Ideally, this logic should not be here;
29455 instead, there should be some programmatic way of inquiring as
29456 to whether or not an object is a vtable. */
29458 #define VTABLE_NAME_P(NAME) \
29459 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29460 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29461 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29462 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29463 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29465 #ifdef NO_DOLLAR_IN_LABEL
29466 /* Return a GGC-allocated character string translating dollar signs in
29467 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29470 rs6000_xcoff_strip_dollar (const char *name
)
29476 q
= (const char *) strchr (name
, '$');
29478 if (q
== 0 || q
== name
)
29481 len
= strlen (name
);
29482 strip
= XALLOCAVEC (char, len
+ 1);
29483 strcpy (strip
, name
);
29484 p
= strip
+ (q
- name
);
29488 p
= strchr (p
+ 1, '$');
29491 return ggc_alloc_string (strip
, len
);
29496 rs6000_output_symbol_ref (FILE *file
, rtx x
)
29498 const char *name
= XSTR (x
, 0);
29500 /* Currently C++ toc references to vtables can be emitted before it
29501 is decided whether the vtable is public or private. If this is
29502 the case, then the linker will eventually complain that there is
29503 a reference to an unknown section. Thus, for vtables only,
29504 we emit the TOC reference to reference the identifier and not the
29506 if (VTABLE_NAME_P (name
))
29508 RS6000_OUTPUT_BASENAME (file
, name
);
29511 assemble_name (file
, name
);
29514 /* Output a TOC entry. We derive the entry name from what is being
29518 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
29521 const char *name
= buf
;
29523 HOST_WIDE_INT offset
= 0;
29525 gcc_assert (!TARGET_NO_TOC
);
29527 /* When the linker won't eliminate them, don't output duplicate
29528 TOC entries (this happens on AIX if there is any kind of TOC,
29529 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29531 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
29533 struct toc_hash_struct
*h
;
29535 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29536 time because GGC is not initialized at that point. */
29537 if (toc_hash_table
== NULL
)
29538 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
29540 h
= ggc_alloc
<toc_hash_struct
> ();
29542 h
->key_mode
= mode
;
29543 h
->labelno
= labelno
;
29545 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
29546 if (*found
== NULL
)
29548 else /* This is indeed a duplicate.
29549 Set this label equal to that label. */
29551 fputs ("\t.set ", file
);
29552 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29553 fprintf (file
, "%d,", labelno
);
29554 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29555 fprintf (file
, "%d\n", ((*found
)->labelno
));
29558 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
29559 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
29560 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
29562 fputs ("\t.set ", file
);
29563 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29564 fprintf (file
, "%d,", labelno
);
29565 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29566 fprintf (file
, "%d\n", ((*found
)->labelno
));
29573 /* If we're going to put a double constant in the TOC, make sure it's
29574 aligned properly when strict alignment is on. */
29575 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
29576 && STRICT_ALIGNMENT
29577 && GET_MODE_BITSIZE (mode
) >= 64
29578 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
29579 ASM_OUTPUT_ALIGN (file
, 3);
29582 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
29584 /* Handle FP constants specially. Note that if we have a minimal
29585 TOC, things we put here aren't actually in the TOC, so we can allow
29587 if (GET_CODE (x
) == CONST_DOUBLE
&&
29588 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
29589 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
29593 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29594 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29596 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29600 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29601 fputs (DOUBLE_INT_ASM_OP
, file
);
29603 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29604 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29605 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29606 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
29607 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29608 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
29609 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
29610 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
29615 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29616 fputs ("\t.long ", file
);
29618 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29619 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29620 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29621 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29622 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29623 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29627 else if (GET_CODE (x
) == CONST_DOUBLE
&&
29628 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
29632 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29633 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29635 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29639 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29640 fputs (DOUBLE_INT_ASM_OP
, file
);
29642 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29643 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29644 fprintf (file
, "0x%lx%08lx\n",
29645 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29646 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
29651 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29652 fputs ("\t.long ", file
);
29654 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29655 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29656 fprintf (file
, "0x%lx,0x%lx\n",
29657 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29661 else if (GET_CODE (x
) == CONST_DOUBLE
&&
29662 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
29666 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29667 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29669 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29673 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29674 fputs (DOUBLE_INT_ASM_OP
, file
);
29676 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29677 if (WORDS_BIG_ENDIAN
)
29678 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
29680 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
29685 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29686 fputs ("\t.long ", file
);
29688 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29689 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
29693 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
29695 unsigned HOST_WIDE_INT low
;
29696 HOST_WIDE_INT high
;
29698 low
= INTVAL (x
) & 0xffffffff;
29699 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
29701 /* TOC entries are always Pmode-sized, so when big-endian
29702 smaller integer constants in the TOC need to be padded.
29703 (This is still a win over putting the constants in
29704 a separate constant pool, because then we'd have
29705 to have both a TOC entry _and_ the actual constant.)
29707 For a 32-bit target, CONST_INT values are loaded and shifted
29708 entirely within `low' and can be stored in one TOC entry. */
29710 /* It would be easy to make this work, but it doesn't now. */
29711 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
29713 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
29716 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
29717 high
= (HOST_WIDE_INT
) low
>> 32;
29723 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29724 fputs (DOUBLE_INT_ASM_OP
, file
);
29726 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
29727 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29728 fprintf (file
, "0x%lx%08lx\n",
29729 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29734 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
29736 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29737 fputs ("\t.long ", file
);
29739 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
29740 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29741 fprintf (file
, "0x%lx,0x%lx\n",
29742 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29746 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29747 fputs ("\t.long ", file
);
29749 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
29750 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
29756 if (GET_CODE (x
) == CONST
)
29758 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
29759 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
29761 base
= XEXP (XEXP (x
, 0), 0);
29762 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
29765 switch (GET_CODE (base
))
29768 name
= XSTR (base
, 0);
29772 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
29773 CODE_LABEL_NUMBER (XEXP (base
, 0)));
29777 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
29781 gcc_unreachable ();
29784 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29785 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
29788 fputs ("\t.tc ", file
);
29789 RS6000_OUTPUT_BASENAME (file
, name
);
29792 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
29794 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
29796 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29797 after other TOC symbols, reducing overflow of small TOC access
29798 to [TC] symbols. */
29799 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
29800 ? "[TE]," : "[TC],", file
);
29803 /* Currently C++ toc references to vtables can be emitted before it
29804 is decided whether the vtable is public or private. If this is
29805 the case, then the linker will eventually complain that there is
29806 a TOC reference to an unknown section. Thus, for vtables only,
29807 we emit the TOC reference to reference the symbol and not the
29809 if (VTABLE_NAME_P (name
))
29811 RS6000_OUTPUT_BASENAME (file
, name
);
29813 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
29814 else if (offset
> 0)
29815 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
29818 output_addr_const (file
, x
);
29821 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
)
29823 switch (SYMBOL_REF_TLS_MODEL (base
))
29827 case TLS_MODEL_LOCAL_EXEC
:
29828 fputs ("@le", file
);
29830 case TLS_MODEL_INITIAL_EXEC
:
29831 fputs ("@ie", file
);
29833 /* Use global-dynamic for local-dynamic. */
29834 case TLS_MODEL_GLOBAL_DYNAMIC
:
29835 case TLS_MODEL_LOCAL_DYNAMIC
:
29837 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
29838 fputs ("\t.tc .", file
);
29839 RS6000_OUTPUT_BASENAME (file
, name
);
29840 fputs ("[TC],", file
);
29841 output_addr_const (file
, x
);
29842 fputs ("@m", file
);
29845 gcc_unreachable ();
29853 /* Output an assembler pseudo-op to write an ASCII string of N characters
29854 starting at P to FILE.
29856 On the RS/6000, we have to do this using the .byte operation and
29857 write out special characters outside the quoted string.
29858 Also, the assembler is broken; very long strings are truncated,
29859 so we must artificially break them up early. */
29862 output_ascii (FILE *file
, const char *p
, int n
)
29865 int i
, count_string
;
29866 const char *for_string
= "\t.byte \"";
29867 const char *for_decimal
= "\t.byte ";
29868 const char *to_close
= NULL
;
29871 for (i
= 0; i
< n
; i
++)
29874 if (c
>= ' ' && c
< 0177)
29877 fputs (for_string
, file
);
29880 /* Write two quotes to get one. */
29888 for_decimal
= "\"\n\t.byte ";
29892 if (count_string
>= 512)
29894 fputs (to_close
, file
);
29896 for_string
= "\t.byte \"";
29897 for_decimal
= "\t.byte ";
29905 fputs (for_decimal
, file
);
29906 fprintf (file
, "%d", c
);
29908 for_string
= "\n\t.byte \"";
29909 for_decimal
= ", ";
29915 /* Now close the string if we have written one. Then end the line. */
29917 fputs (to_close
, file
);
29920 /* Generate a unique section name for FILENAME for a section type
29921 represented by SECTION_DESC. Output goes into BUF.
29923 SECTION_DESC can be any string, as long as it is different for each
29924 possible section type.
29926 We name the section in the same manner as xlc. The name begins with an
29927 underscore followed by the filename (after stripping any leading directory
29928 names) with the last period replaced by the string SECTION_DESC. If
29929 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29933 rs6000_gen_section_name (char **buf
, const char *filename
,
29934 const char *section_desc
)
29936 const char *q
, *after_last_slash
, *last_period
= 0;
29940 after_last_slash
= filename
;
29941 for (q
= filename
; *q
; q
++)
29944 after_last_slash
= q
+ 1;
29945 else if (*q
== '.')
29949 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
29950 *buf
= (char *) xmalloc (len
);
29955 for (q
= after_last_slash
; *q
; q
++)
29957 if (q
== last_period
)
29959 strcpy (p
, section_desc
);
29960 p
+= strlen (section_desc
);
29964 else if (ISALNUM (*q
))
29968 if (last_period
== 0)
29969 strcpy (p
, section_desc
);
29974 /* Emit profile function. */
29977 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
29979 /* Non-standard profiling for kernels, which just saves LR then calls
29980 _mcount without worrying about arg saves. The idea is to change
29981 the function prologue as little as possible as it isn't easy to
29982 account for arg save/restore code added just for _mcount. */
29983 if (TARGET_PROFILE_KERNEL
)
29986 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29988 #ifndef NO_PROFILE_COUNTERS
29989 # define NO_PROFILE_COUNTERS 0
29991 if (NO_PROFILE_COUNTERS
)
29992 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
29993 LCT_NORMAL
, VOIDmode
, 0);
29997 const char *label_name
;
30000 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
30001 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
30002 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
30004 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
30005 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
30008 else if (DEFAULT_ABI
== ABI_DARWIN
)
30010 const char *mcount_name
= RS6000_MCOUNT
;
30011 int caller_addr_regno
= LR_REGNO
;
30013 /* Be conservative and always set this, at least for now. */
30014 crtl
->uses_pic_offset_table
= 1;
30017 /* For PIC code, set up a stub and collect the caller's address
30018 from r0, which is where the prologue puts it. */
30019 if (MACHOPIC_INDIRECT
30020 && crtl
->uses_pic_offset_table
)
30021 caller_addr_regno
= 0;
30023 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
30024 LCT_NORMAL
, VOIDmode
, 1,
30025 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
30029 /* Write function profiler code. */
30032 output_function_profiler (FILE *file
, int labelno
)
30036 switch (DEFAULT_ABI
)
30039 gcc_unreachable ();
30044 warning (0, "no profiling of 64-bit code for this ABI");
30047 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
30048 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
30049 if (NO_PROFILE_COUNTERS
)
30051 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30052 reg_names
[0], reg_names
[1]);
30054 else if (TARGET_SECURE_PLT
&& flag_pic
)
30056 if (TARGET_LINK_STACK
)
30059 get_ppc476_thunk_name (name
);
30060 asm_fprintf (file
, "\tbl %s\n", name
);
30063 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
30064 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30065 reg_names
[0], reg_names
[1]);
30066 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
30067 asm_fprintf (file
, "\taddis %s,%s,",
30068 reg_names
[12], reg_names
[12]);
30069 assemble_name (file
, buf
);
30070 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
30071 assemble_name (file
, buf
);
30072 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
30074 else if (flag_pic
== 1)
30076 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
30077 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30078 reg_names
[0], reg_names
[1]);
30079 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
30080 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
30081 assemble_name (file
, buf
);
30082 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
30084 else if (flag_pic
> 1)
30086 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30087 reg_names
[0], reg_names
[1]);
30088 /* Now, we need to get the address of the label. */
30089 if (TARGET_LINK_STACK
)
30092 get_ppc476_thunk_name (name
);
30093 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
30094 assemble_name (file
, buf
);
30095 fputs ("-.\n1:", file
);
30096 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
30097 asm_fprintf (file
, "\taddi %s,%s,4\n",
30098 reg_names
[11], reg_names
[11]);
30102 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
30103 assemble_name (file
, buf
);
30104 fputs ("-.\n1:", file
);
30105 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
30107 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
30108 reg_names
[0], reg_names
[11]);
30109 asm_fprintf (file
, "\tadd %s,%s,%s\n",
30110 reg_names
[0], reg_names
[0], reg_names
[11]);
30114 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
30115 assemble_name (file
, buf
);
30116 fputs ("@ha\n", file
);
30117 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30118 reg_names
[0], reg_names
[1]);
30119 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
30120 assemble_name (file
, buf
);
30121 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
30124 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30125 fprintf (file
, "\tbl %s%s\n",
30126 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
30132 /* Don't do anything, done in output_profile_hook (). */
30139 /* The following variable value is the last issued insn. */
30141 static rtx_insn
*last_scheduled_insn
;
30143 /* The following variable helps to balance issuing of load and
30144 store instructions */
30146 static int load_store_pendulum
;
30148 /* The following variable helps pair divide insns during scheduling. */
30149 static int divide_cnt
;
30150 /* The following variable helps pair and alternate vector and vector load
30151 insns during scheduling. */
30152 static int vec_pairing
;
30155 /* Power4 load update and store update instructions are cracked into a
30156 load or store and an integer insn which are executed in the same cycle.
30157 Branches have their own dispatch slot which does not count against the
30158 GCC issue rate, but it changes the program flow so there are no other
30159 instructions to issue in this cycle. */
30162 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
30164 last_scheduled_insn
= insn
;
30165 if (GET_CODE (PATTERN (insn
)) == USE
30166 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30168 cached_can_issue_more
= more
;
30169 return cached_can_issue_more
;
30172 if (insn_terminates_group_p (insn
, current_group
))
30174 cached_can_issue_more
= 0;
30175 return cached_can_issue_more
;
30178 /* If no reservation, but reach here */
30179 if (recog_memoized (insn
) < 0)
30182 if (rs6000_sched_groups
)
30184 if (is_microcoded_insn (insn
))
30185 cached_can_issue_more
= 0;
30186 else if (is_cracked_insn (insn
))
30187 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
30189 cached_can_issue_more
= more
- 1;
30191 return cached_can_issue_more
;
30194 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
30197 cached_can_issue_more
= more
- 1;
30198 return cached_can_issue_more
;
30202 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
30204 int r
= rs6000_variable_issue_1 (insn
, more
);
30206 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
30210 /* Adjust the cost of a scheduling dependency. Return the new cost of
30211 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30214 rs6000_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
30217 enum attr_type attr_type
;
30219 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
30226 /* Data dependency; DEP_INSN writes a register that INSN reads
30227 some cycles later. */
30229 /* Separate a load from a narrower, dependent store. */
30230 if ((rs6000_sched_groups
|| rs6000_cpu_attr
== CPU_POWER9
)
30231 && GET_CODE (PATTERN (insn
)) == SET
30232 && GET_CODE (PATTERN (dep_insn
)) == SET
30233 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
30234 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
30235 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
30236 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
30239 attr_type
= get_attr_type (insn
);
30244 /* Tell the first scheduling pass about the latency between
30245 a mtctr and bctr (and mtlr and br/blr). The first
30246 scheduling pass will not know about this latency since
30247 the mtctr instruction, which has the latency associated
30248 to it, will be generated by reload. */
30251 /* Leave some extra cycles between a compare and its
30252 dependent branch, to inhibit expensive mispredicts. */
30253 if ((rs6000_cpu_attr
== CPU_PPC603
30254 || rs6000_cpu_attr
== CPU_PPC604
30255 || rs6000_cpu_attr
== CPU_PPC604E
30256 || rs6000_cpu_attr
== CPU_PPC620
30257 || rs6000_cpu_attr
== CPU_PPC630
30258 || rs6000_cpu_attr
== CPU_PPC750
30259 || rs6000_cpu_attr
== CPU_PPC7400
30260 || rs6000_cpu_attr
== CPU_PPC7450
30261 || rs6000_cpu_attr
== CPU_PPCE5500
30262 || rs6000_cpu_attr
== CPU_PPCE6500
30263 || rs6000_cpu_attr
== CPU_POWER4
30264 || rs6000_cpu_attr
== CPU_POWER5
30265 || rs6000_cpu_attr
== CPU_POWER7
30266 || rs6000_cpu_attr
== CPU_POWER8
30267 || rs6000_cpu_attr
== CPU_POWER9
30268 || rs6000_cpu_attr
== CPU_CELL
)
30269 && recog_memoized (dep_insn
)
30270 && (INSN_CODE (dep_insn
) >= 0))
30272 switch (get_attr_type (dep_insn
))
30275 case TYPE_FPCOMPARE
:
30276 case TYPE_CR_LOGICAL
:
30277 case TYPE_DELAYED_CR
:
30281 if (get_attr_dot (dep_insn
) == DOT_YES
)
30286 if (get_attr_dot (dep_insn
) == DOT_YES
30287 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
30298 if ((rs6000_cpu
== PROCESSOR_POWER6
)
30299 && recog_memoized (dep_insn
)
30300 && (INSN_CODE (dep_insn
) >= 0))
30303 if (GET_CODE (PATTERN (insn
)) != SET
)
30304 /* If this happens, we have to extend this to schedule
30305 optimally. Return default for now. */
30308 /* Adjust the cost for the case where the value written
30309 by a fixed point operation is used as the address
30310 gen value on a store. */
30311 switch (get_attr_type (dep_insn
))
30316 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30317 return get_attr_sign_extend (dep_insn
)
30318 == SIGN_EXTEND_YES
? 6 : 4;
30323 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30324 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30334 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30342 if (get_attr_update (dep_insn
) == UPDATE_YES
30343 && ! rs6000_store_data_bypass_p (dep_insn
, insn
))
30349 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30355 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30356 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30366 if ((rs6000_cpu
== PROCESSOR_POWER6
)
30367 && recog_memoized (dep_insn
)
30368 && (INSN_CODE (dep_insn
) >= 0))
30371 /* Adjust the cost for the case where the value written
30372 by a fixed point instruction is used within the address
30373 gen portion of a subsequent load(u)(x) */
30374 switch (get_attr_type (dep_insn
))
30379 if (set_to_load_agen (dep_insn
, insn
))
30380 return get_attr_sign_extend (dep_insn
)
30381 == SIGN_EXTEND_YES
? 6 : 4;
30386 if (set_to_load_agen (dep_insn
, insn
))
30387 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30397 if (set_to_load_agen (dep_insn
, insn
))
30405 if (get_attr_update (dep_insn
) == UPDATE_YES
30406 && set_to_load_agen (dep_insn
, insn
))
30412 if (set_to_load_agen (dep_insn
, insn
))
30418 if (set_to_load_agen (dep_insn
, insn
))
30419 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30429 if ((rs6000_cpu
== PROCESSOR_POWER6
)
30430 && get_attr_update (insn
) == UPDATE_NO
30431 && recog_memoized (dep_insn
)
30432 && (INSN_CODE (dep_insn
) >= 0)
30433 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
30440 /* Fall out to return default cost. */
30444 case REG_DEP_OUTPUT
:
30445 /* Output dependency; DEP_INSN writes a register that INSN writes some
30447 if ((rs6000_cpu
== PROCESSOR_POWER6
)
30448 && recog_memoized (dep_insn
)
30449 && (INSN_CODE (dep_insn
) >= 0))
30451 attr_type
= get_attr_type (insn
);
30456 case TYPE_FPSIMPLE
:
30457 if (get_attr_type (dep_insn
) == TYPE_FP
30458 || get_attr_type (dep_insn
) == TYPE_FPSIMPLE
)
30462 if (get_attr_update (insn
) == UPDATE_NO
30463 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
30470 /* Fall through, no cost for output dependency. */
30474 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30479 gcc_unreachable ();
30485 /* Debug version of rs6000_adjust_cost. */
30488 rs6000_debug_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
30489 int cost
, unsigned int dw
)
30491 int ret
= rs6000_adjust_cost (insn
, dep_type
, dep_insn
, cost
, dw
);
30499 default: dep
= "unknown depencency"; break;
30500 case REG_DEP_TRUE
: dep
= "data dependency"; break;
30501 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
30502 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
30506 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30507 "%s, insn:\n", ret
, cost
, dep
);
30515 /* The function returns a true if INSN is microcoded.
30516 Return false otherwise. */
30519 is_microcoded_insn (rtx_insn
*insn
)
30521 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30522 || GET_CODE (PATTERN (insn
)) == USE
30523 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30526 if (rs6000_cpu_attr
== CPU_CELL
)
30527 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
30529 if (rs6000_sched_groups
30530 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
30532 enum attr_type type
= get_attr_type (insn
);
30533 if ((type
== TYPE_LOAD
30534 && get_attr_update (insn
) == UPDATE_YES
30535 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
30536 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
30537 && get_attr_update (insn
) == UPDATE_YES
30538 && get_attr_indexed (insn
) == INDEXED_YES
)
30539 || type
== TYPE_MFCR
)
30546 /* The function returns true if INSN is cracked into 2 instructions
30547 by the processor (and therefore occupies 2 issue slots). */
30550 is_cracked_insn (rtx_insn
*insn
)
30552 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30553 || GET_CODE (PATTERN (insn
)) == USE
30554 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30557 if (rs6000_sched_groups
30558 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
30560 enum attr_type type
= get_attr_type (insn
);
30561 if ((type
== TYPE_LOAD
30562 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
30563 && get_attr_update (insn
) == UPDATE_NO
)
30564 || (type
== TYPE_LOAD
30565 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
30566 && get_attr_update (insn
) == UPDATE_YES
30567 && get_attr_indexed (insn
) == INDEXED_NO
)
30568 || (type
== TYPE_STORE
30569 && get_attr_update (insn
) == UPDATE_YES
30570 && get_attr_indexed (insn
) == INDEXED_NO
)
30571 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
30572 && get_attr_update (insn
) == UPDATE_YES
)
30573 || type
== TYPE_DELAYED_CR
30574 || (type
== TYPE_EXTS
30575 && get_attr_dot (insn
) == DOT_YES
)
30576 || (type
== TYPE_SHIFT
30577 && get_attr_dot (insn
) == DOT_YES
30578 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
30579 || (type
== TYPE_MUL
30580 && get_attr_dot (insn
) == DOT_YES
)
30581 || type
== TYPE_DIV
30582 || (type
== TYPE_INSERT
30583 && get_attr_size (insn
) == SIZE_32
))
30590 /* The function returns true if INSN can be issued only from
30591 the branch slot. */
30594 is_branch_slot_insn (rtx_insn
*insn
)
30596 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30597 || GET_CODE (PATTERN (insn
)) == USE
30598 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30601 if (rs6000_sched_groups
)
30603 enum attr_type type
= get_attr_type (insn
);
30604 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
30612 /* The function returns true if out_inst sets a value that is
30613 used in the address generation computation of in_insn */
30615 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
30617 rtx out_set
, in_set
;
30619 /* For performance reasons, only handle the simple case where
30620 both loads are a single_set. */
30621 out_set
= single_set (out_insn
);
30624 in_set
= single_set (in_insn
);
30626 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
30632 /* Try to determine base/offset/size parts of the given MEM.
30633 Return true if successful, false if all the values couldn't
30636 This function only looks for REG or REG+CONST address forms.
30637 REG+REG address form will return false. */
30640 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
30641 HOST_WIDE_INT
*size
)
30644 if MEM_SIZE_KNOWN_P (mem
)
30645 *size
= MEM_SIZE (mem
);
30649 addr_rtx
= (XEXP (mem
, 0));
30650 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
30651 addr_rtx
= XEXP (addr_rtx
, 1);
30654 while (GET_CODE (addr_rtx
) == PLUS
30655 && CONST_INT_P (XEXP (addr_rtx
, 1)))
30657 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
30658 addr_rtx
= XEXP (addr_rtx
, 0);
30660 if (!REG_P (addr_rtx
))
30667 /* The function returns true if the target storage location of
30668 mem1 is adjacent to the target storage location of mem2 */
30669 /* Return 1 if memory locations are adjacent. */
30672 adjacent_mem_locations (rtx mem1
, rtx mem2
)
30675 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30677 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30678 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30679 return ((REGNO (reg1
) == REGNO (reg2
))
30680 && ((off1
+ size1
== off2
)
30681 || (off2
+ size2
== off1
)));
30686 /* This function returns true if it can be determined that the two MEM
30687 locations overlap by at least 1 byte based on base reg/offset/size. */
30690 mem_locations_overlap (rtx mem1
, rtx mem2
)
30693 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30695 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30696 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30697 return ((REGNO (reg1
) == REGNO (reg2
))
30698 && (((off1
<= off2
) && (off1
+ size1
> off2
))
30699 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
30704 /* A C statement (sans semicolon) to update the integer scheduling
30705 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30706 INSN earlier, reduce the priority to execute INSN later. Do not
30707 define this macro if you do not need to adjust the scheduling
30708 priorities of insns. */
30711 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
30713 rtx load_mem
, str_mem
;
30714 /* On machines (like the 750) which have asymmetric integer units,
30715 where one integer unit can do multiply and divides and the other
30716 can't, reduce the priority of multiply/divide so it is scheduled
30717 before other integer operations. */
30720 if (! INSN_P (insn
))
30723 if (GET_CODE (PATTERN (insn
)) == USE
)
30726 switch (rs6000_cpu_attr
) {
30728 switch (get_attr_type (insn
))
30735 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
30736 priority
, priority
);
30737 if (priority
>= 0 && priority
< 0x01000000)
30744 if (insn_must_be_first_in_group (insn
)
30745 && reload_completed
30746 && current_sched_info
->sched_max_insns_priority
30747 && rs6000_sched_restricted_insns_priority
)
30750 /* Prioritize insns that can be dispatched only in the first
30752 if (rs6000_sched_restricted_insns_priority
== 1)
30753 /* Attach highest priority to insn. This means that in
30754 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30755 precede 'priority' (critical path) considerations. */
30756 return current_sched_info
->sched_max_insns_priority
;
30757 else if (rs6000_sched_restricted_insns_priority
== 2)
30758 /* Increase priority of insn by a minimal amount. This means that in
30759 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30760 considerations precede dispatch-slot restriction considerations. */
30761 return (priority
+ 1);
30764 if (rs6000_cpu
== PROCESSOR_POWER6
30765 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
30766 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
30767 /* Attach highest priority to insn if the scheduler has just issued two
30768 stores and this instruction is a load, or two loads and this instruction
30769 is a store. Power6 wants loads and stores scheduled alternately
30771 return current_sched_info
->sched_max_insns_priority
;
30776 /* Return true if the instruction is nonpipelined on the Cell. */
30778 is_nonpipeline_insn (rtx_insn
*insn
)
30780 enum attr_type type
;
30781 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30782 || GET_CODE (PATTERN (insn
)) == USE
30783 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30786 type
= get_attr_type (insn
);
30787 if (type
== TYPE_MUL
30788 || type
== TYPE_DIV
30789 || type
== TYPE_SDIV
30790 || type
== TYPE_DDIV
30791 || type
== TYPE_SSQRT
30792 || type
== TYPE_DSQRT
30793 || type
== TYPE_MFCR
30794 || type
== TYPE_MFCRF
30795 || type
== TYPE_MFJMPR
)
30803 /* Return how many instructions the machine can issue per cycle. */
30806 rs6000_issue_rate (void)
30808 /* Unless scheduling for register pressure, use issue rate of 1 for
30809 first scheduling pass to decrease degradation. */
30810 if (!reload_completed
&& !flag_sched_pressure
)
30813 switch (rs6000_cpu_attr
) {
30815 case CPU_PPC601
: /* ? */
30825 case CPU_PPCE300C2
:
30826 case CPU_PPCE300C3
:
30827 case CPU_PPCE500MC
:
30828 case CPU_PPCE500MC64
:
30853 /* Return how many instructions to look ahead for better insn
30857 rs6000_use_sched_lookahead (void)
30859 switch (rs6000_cpu_attr
)
30866 return (reload_completed
? 8 : 0);
30873 /* We are choosing insn from the ready queue. Return zero if INSN can be
30876 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
30878 if (ready_index
== 0)
30881 if (rs6000_cpu_attr
!= CPU_CELL
)
30884 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
30886 if (!reload_completed
30887 || is_nonpipeline_insn (insn
)
30888 || is_microcoded_insn (insn
))
30894 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30895 and return true. */
30898 find_mem_ref (rtx pat
, rtx
*mem_ref
)
30903 /* stack_tie does not produce any real memory traffic. */
30904 if (tie_operand (pat
, VOIDmode
))
30907 if (GET_CODE (pat
) == MEM
)
30913 /* Recursively process the pattern. */
30914 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
30916 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
30920 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
30923 else if (fmt
[i
] == 'E')
30924 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
30926 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
30934 /* Determine if PAT is a PATTERN of a load insn. */
30937 is_load_insn1 (rtx pat
, rtx
*load_mem
)
30939 if (!pat
|| pat
== NULL_RTX
)
30942 if (GET_CODE (pat
) == SET
)
30943 return find_mem_ref (SET_SRC (pat
), load_mem
);
30945 if (GET_CODE (pat
) == PARALLEL
)
30949 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
30950 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
30957 /* Determine if INSN loads from memory. */
30960 is_load_insn (rtx insn
, rtx
*load_mem
)
30962 if (!insn
|| !INSN_P (insn
))
30968 return is_load_insn1 (PATTERN (insn
), load_mem
);
30971 /* Determine if PAT is a PATTERN of a store insn. */
30974 is_store_insn1 (rtx pat
, rtx
*str_mem
)
30976 if (!pat
|| pat
== NULL_RTX
)
30979 if (GET_CODE (pat
) == SET
)
30980 return find_mem_ref (SET_DEST (pat
), str_mem
);
30982 if (GET_CODE (pat
) == PARALLEL
)
30986 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
30987 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
30994 /* Determine if INSN stores to memory. */
30997 is_store_insn (rtx insn
, rtx
*str_mem
)
30999 if (!insn
|| !INSN_P (insn
))
31002 return is_store_insn1 (PATTERN (insn
), str_mem
);
31005 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31008 is_power9_pairable_vec_type (enum attr_type type
)
31012 case TYPE_VECSIMPLE
:
31013 case TYPE_VECCOMPLEX
:
31017 case TYPE_VECFLOAT
:
31019 case TYPE_VECDOUBLE
:
31027 /* Returns whether the dependence between INSN and NEXT is considered
31028 costly by the given target. */
31031 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
31035 rtx load_mem
, str_mem
;
31037 /* If the flag is not enabled - no dependence is considered costly;
31038 allow all dependent insns in the same group.
31039 This is the most aggressive option. */
31040 if (rs6000_sched_costly_dep
== no_dep_costly
)
31043 /* If the flag is set to 1 - a dependence is always considered costly;
31044 do not allow dependent instructions in the same group.
31045 This is the most conservative option. */
31046 if (rs6000_sched_costly_dep
== all_deps_costly
)
31049 insn
= DEP_PRO (dep
);
31050 next
= DEP_CON (dep
);
31052 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
31053 && is_load_insn (next
, &load_mem
)
31054 && is_store_insn (insn
, &str_mem
))
31055 /* Prevent load after store in the same group. */
31058 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
31059 && is_load_insn (next
, &load_mem
)
31060 && is_store_insn (insn
, &str_mem
)
31061 && DEP_TYPE (dep
) == REG_DEP_TRUE
31062 && mem_locations_overlap(str_mem
, load_mem
))
31063 /* Prevent load after store in the same group if it is a true
31067 /* The flag is set to X; dependences with latency >= X are considered costly,
31068 and will not be scheduled in the same group. */
31069 if (rs6000_sched_costly_dep
<= max_dep_latency
31070 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
31076 /* Return the next insn after INSN that is found before TAIL is reached,
31077 skipping any "non-active" insns - insns that will not actually occupy
31078 an issue slot. Return NULL_RTX if such an insn is not found. */
31081 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
31083 if (insn
== NULL_RTX
|| insn
== tail
)
31088 insn
= NEXT_INSN (insn
);
31089 if (insn
== NULL_RTX
|| insn
== tail
)
31093 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
31094 || (NONJUMP_INSN_P (insn
)
31095 && GET_CODE (PATTERN (insn
)) != USE
31096 && GET_CODE (PATTERN (insn
)) != CLOBBER
31097 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
31103 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31106 power9_sched_reorder2 (rtx_insn
**ready
, int lastpos
)
31111 enum attr_type type
, type2
;
31113 type
= get_attr_type (last_scheduled_insn
);
31115 /* Try to issue fixed point divides back-to-back in pairs so they will be
31116 routed to separate execution units and execute in parallel. */
31117 if (type
== TYPE_DIV
&& divide_cnt
== 0)
31119 /* First divide has been scheduled. */
31122 /* Scan the ready list looking for another divide, if found move it
31123 to the end of the list so it is chosen next. */
31127 if (recog_memoized (ready
[pos
]) >= 0
31128 && get_attr_type (ready
[pos
]) == TYPE_DIV
)
31131 for (i
= pos
; i
< lastpos
; i
++)
31132 ready
[i
] = ready
[i
+ 1];
31133 ready
[lastpos
] = tmp
;
31141 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31144 /* The best dispatch throughput for vector and vector load insns can be
31145 achieved by interleaving a vector and vector load such that they'll
31146 dispatch to the same superslice. If this pairing cannot be achieved
31147 then it is best to pair vector insns together and vector load insns
31150 To aid in this pairing, vec_pairing maintains the current state with
31151 the following values:
31153 0 : Initial state, no vecload/vector pairing has been started.
31155 1 : A vecload or vector insn has been issued and a candidate for
31156 pairing has been found and moved to the end of the ready
31158 if (type
== TYPE_VECLOAD
)
31160 /* Issued a vecload. */
31161 if (vec_pairing
== 0)
31163 int vecload_pos
= -1;
31164 /* We issued a single vecload, look for a vector insn to pair it
31165 with. If one isn't found, try to pair another vecload. */
31169 if (recog_memoized (ready
[pos
]) >= 0)
31171 type2
= get_attr_type (ready
[pos
]);
31172 if (is_power9_pairable_vec_type (type2
))
31174 /* Found a vector insn to pair with, move it to the
31175 end of the ready list so it is scheduled next. */
31177 for (i
= pos
; i
< lastpos
; i
++)
31178 ready
[i
] = ready
[i
+ 1];
31179 ready
[lastpos
] = tmp
;
31181 return cached_can_issue_more
;
31183 else if (type2
== TYPE_VECLOAD
&& vecload_pos
== -1)
31184 /* Remember position of first vecload seen. */
31189 if (vecload_pos
>= 0)
31191 /* Didn't find a vector to pair with but did find a vecload,
31192 move it to the end of the ready list. */
31193 tmp
= ready
[vecload_pos
];
31194 for (i
= vecload_pos
; i
< lastpos
; i
++)
31195 ready
[i
] = ready
[i
+ 1];
31196 ready
[lastpos
] = tmp
;
31198 return cached_can_issue_more
;
31202 else if (is_power9_pairable_vec_type (type
))
31204 /* Issued a vector operation. */
31205 if (vec_pairing
== 0)
31208 /* We issued a single vector insn, look for a vecload to pair it
31209 with. If one isn't found, try to pair another vector. */
31213 if (recog_memoized (ready
[pos
]) >= 0)
31215 type2
= get_attr_type (ready
[pos
]);
31216 if (type2
== TYPE_VECLOAD
)
31218 /* Found a vecload insn to pair with, move it to the
31219 end of the ready list so it is scheduled next. */
31221 for (i
= pos
; i
< lastpos
; i
++)
31222 ready
[i
] = ready
[i
+ 1];
31223 ready
[lastpos
] = tmp
;
31225 return cached_can_issue_more
;
31227 else if (is_power9_pairable_vec_type (type2
)
31229 /* Remember position of first vector insn seen. */
31236 /* Didn't find a vecload to pair with but did find a vector
31237 insn, move it to the end of the ready list. */
31238 tmp
= ready
[vec_pos
];
31239 for (i
= vec_pos
; i
< lastpos
; i
++)
31240 ready
[i
] = ready
[i
+ 1];
31241 ready
[lastpos
] = tmp
;
31243 return cached_can_issue_more
;
31248 /* We've either finished a vec/vecload pair, couldn't find an insn to
31249 continue the current pair, or the last insn had nothing to do with
31250 with pairing. In any case, reset the state. */
31254 return cached_can_issue_more
;
31257 /* We are about to begin issuing insns for this clock cycle. */
31260 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
31261 rtx_insn
**ready ATTRIBUTE_UNUSED
,
31262 int *pn_ready ATTRIBUTE_UNUSED
,
31263 int clock_var ATTRIBUTE_UNUSED
)
31265 int n_ready
= *pn_ready
;
31268 fprintf (dump
, "// rs6000_sched_reorder :\n");
31270 /* Reorder the ready list, if the second to last ready insn
31271 is a nonepipeline insn. */
31272 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
31274 if (is_nonpipeline_insn (ready
[n_ready
- 1])
31275 && (recog_memoized (ready
[n_ready
- 2]) > 0))
31276 /* Simply swap first two insns. */
31277 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
31280 if (rs6000_cpu
== PROCESSOR_POWER6
)
31281 load_store_pendulum
= 0;
31283 return rs6000_issue_rate ();
31286 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31289 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
31290 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
31293 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
31295 /* For Power6, we need to handle some special cases to try and keep the
31296 store queue from overflowing and triggering expensive flushes.
31298 This code monitors how load and store instructions are being issued
31299 and skews the ready list one way or the other to increase the likelihood
31300 that a desired instruction is issued at the proper time.
31302 A couple of things are done. First, we maintain a "load_store_pendulum"
31303 to track the current state of load/store issue.
31305 - If the pendulum is at zero, then no loads or stores have been
31306 issued in the current cycle so we do nothing.
31308 - If the pendulum is 1, then a single load has been issued in this
31309 cycle and we attempt to locate another load in the ready list to
31312 - If the pendulum is -2, then two stores have already been
31313 issued in this cycle, so we increase the priority of the first load
31314 in the ready list to increase it's likelihood of being chosen first
31317 - If the pendulum is -1, then a single store has been issued in this
31318 cycle and we attempt to locate another store in the ready list to
31319 issue with it, preferring a store to an adjacent memory location to
31320 facilitate store pairing in the store queue.
31322 - If the pendulum is 2, then two loads have already been
31323 issued in this cycle, so we increase the priority of the first store
31324 in the ready list to increase it's likelihood of being chosen first
31327 - If the pendulum < -2 or > 2, then do nothing.
31329 Note: This code covers the most common scenarios. There exist non
31330 load/store instructions which make use of the LSU and which
31331 would need to be accounted for to strictly model the behavior
31332 of the machine. Those instructions are currently unaccounted
31333 for to help minimize compile time overhead of this code.
31335 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
31340 rtx load_mem
, str_mem
;
31342 if (is_store_insn (last_scheduled_insn
, &str_mem
))
31343 /* Issuing a store, swing the load_store_pendulum to the left */
31344 load_store_pendulum
--;
31345 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
31346 /* Issuing a load, swing the load_store_pendulum to the right */
31347 load_store_pendulum
++;
31349 return cached_can_issue_more
;
31351 /* If the pendulum is balanced, or there is only one instruction on
31352 the ready list, then all is well, so return. */
31353 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
31354 return cached_can_issue_more
;
31356 if (load_store_pendulum
== 1)
31358 /* A load has been issued in this cycle. Scan the ready list
31359 for another load to issue with it */
31364 if (is_load_insn (ready
[pos
], &load_mem
))
31366 /* Found a load. Move it to the head of the ready list,
31367 and adjust it's priority so that it is more likely to
31370 for (i
=pos
; i
<*pn_ready
-1; i
++)
31371 ready
[i
] = ready
[i
+ 1];
31372 ready
[*pn_ready
-1] = tmp
;
31374 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31375 INSN_PRIORITY (tmp
)++;
31381 else if (load_store_pendulum
== -2)
31383 /* Two stores have been issued in this cycle. Increase the
31384 priority of the first load in the ready list to favor it for
31385 issuing in the next cycle. */
31390 if (is_load_insn (ready
[pos
], &load_mem
)
31392 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31394 INSN_PRIORITY (ready
[pos
])++;
31396 /* Adjust the pendulum to account for the fact that a load
31397 was found and increased in priority. This is to prevent
31398 increasing the priority of multiple loads */
31399 load_store_pendulum
--;
31406 else if (load_store_pendulum
== -1)
31408 /* A store has been issued in this cycle. Scan the ready list for
31409 another store to issue with it, preferring a store to an adjacent
31411 int first_store_pos
= -1;
31417 if (is_store_insn (ready
[pos
], &str_mem
))
31420 /* Maintain the index of the first store found on the
31422 if (first_store_pos
== -1)
31423 first_store_pos
= pos
;
31425 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
31426 && adjacent_mem_locations (str_mem
, str_mem2
))
31428 /* Found an adjacent store. Move it to the head of the
31429 ready list, and adjust it's priority so that it is
31430 more likely to stay there */
31432 for (i
=pos
; i
<*pn_ready
-1; i
++)
31433 ready
[i
] = ready
[i
+ 1];
31434 ready
[*pn_ready
-1] = tmp
;
31436 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31437 INSN_PRIORITY (tmp
)++;
31439 first_store_pos
= -1;
31447 if (first_store_pos
>= 0)
31449 /* An adjacent store wasn't found, but a non-adjacent store was,
31450 so move the non-adjacent store to the front of the ready
31451 list, and adjust its priority so that it is more likely to
31453 tmp
= ready
[first_store_pos
];
31454 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
31455 ready
[i
] = ready
[i
+ 1];
31456 ready
[*pn_ready
-1] = tmp
;
31457 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31458 INSN_PRIORITY (tmp
)++;
31461 else if (load_store_pendulum
== 2)
31463 /* Two loads have been issued in this cycle. Increase the priority
31464 of the first store in the ready list to favor it for issuing in
31470 if (is_store_insn (ready
[pos
], &str_mem
)
31472 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31474 INSN_PRIORITY (ready
[pos
])++;
31476 /* Adjust the pendulum to account for the fact that a store
31477 was found and increased in priority. This is to prevent
31478 increasing the priority of multiple stores */
31479 load_store_pendulum
++;
31488 /* Do Power9 dependent reordering if necessary. */
31489 if (rs6000_cpu
== PROCESSOR_POWER9
&& last_scheduled_insn
31490 && recog_memoized (last_scheduled_insn
) >= 0)
31491 return power9_sched_reorder2 (ready
, *pn_ready
- 1);
31493 return cached_can_issue_more
;
31496 /* Return whether the presence of INSN causes a dispatch group termination
31497 of group WHICH_GROUP.
31499 If WHICH_GROUP == current_group, this function will return true if INSN
31500 causes the termination of the current group (i.e, the dispatch group to
31501 which INSN belongs). This means that INSN will be the last insn in the
31502 group it belongs to.
31504 If WHICH_GROUP == previous_group, this function will return true if INSN
31505 causes the termination of the previous group (i.e, the dispatch group that
31506 precedes the group to which INSN belongs). This means that INSN will be
31507 the first insn in the group it belongs to). */
31510 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
31517 first
= insn_must_be_first_in_group (insn
);
31518 last
= insn_must_be_last_in_group (insn
);
31523 if (which_group
== current_group
)
31525 else if (which_group
== previous_group
)
31533 insn_must_be_first_in_group (rtx_insn
*insn
)
31535 enum attr_type type
;
31539 || DEBUG_INSN_P (insn
)
31540 || GET_CODE (PATTERN (insn
)) == USE
31541 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31544 switch (rs6000_cpu
)
31546 case PROCESSOR_POWER5
:
31547 if (is_cracked_insn (insn
))
31550 case PROCESSOR_POWER4
:
31551 if (is_microcoded_insn (insn
))
31554 if (!rs6000_sched_groups
)
31557 type
= get_attr_type (insn
);
31564 case TYPE_DELAYED_CR
:
31565 case TYPE_CR_LOGICAL
:
31578 case PROCESSOR_POWER6
:
31579 type
= get_attr_type (insn
);
31588 case TYPE_FPCOMPARE
:
31599 if (get_attr_dot (insn
) == DOT_NO
31600 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31605 if (get_attr_size (insn
) == SIZE_32
)
31613 if (get_attr_update (insn
) == UPDATE_YES
)
31621 case PROCESSOR_POWER7
:
31622 type
= get_attr_type (insn
);
31626 case TYPE_CR_LOGICAL
:
31640 if (get_attr_dot (insn
) == DOT_YES
)
31645 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31646 || get_attr_update (insn
) == UPDATE_YES
)
31653 if (get_attr_update (insn
) == UPDATE_YES
)
31661 case PROCESSOR_POWER8
:
31662 type
= get_attr_type (insn
);
31666 case TYPE_CR_LOGICAL
:
31667 case TYPE_DELAYED_CR
:
31675 case TYPE_VECSTORE
:
31682 if (get_attr_dot (insn
) == DOT_YES
)
31687 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31688 || get_attr_update (insn
) == UPDATE_YES
)
31693 if (get_attr_update (insn
) == UPDATE_YES
31694 && get_attr_indexed (insn
) == INDEXED_YES
)
31710 insn_must_be_last_in_group (rtx_insn
*insn
)
31712 enum attr_type type
;
31716 || DEBUG_INSN_P (insn
)
31717 || GET_CODE (PATTERN (insn
)) == USE
31718 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31721 switch (rs6000_cpu
) {
31722 case PROCESSOR_POWER4
:
31723 case PROCESSOR_POWER5
:
31724 if (is_microcoded_insn (insn
))
31727 if (is_branch_slot_insn (insn
))
31731 case PROCESSOR_POWER6
:
31732 type
= get_attr_type (insn
);
31740 case TYPE_FPCOMPARE
:
31751 if (get_attr_dot (insn
) == DOT_NO
31752 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31757 if (get_attr_size (insn
) == SIZE_32
)
31765 case PROCESSOR_POWER7
:
31766 type
= get_attr_type (insn
);
31776 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31777 && get_attr_update (insn
) == UPDATE_YES
)
31782 if (get_attr_update (insn
) == UPDATE_YES
31783 && get_attr_indexed (insn
) == INDEXED_YES
)
31791 case PROCESSOR_POWER8
:
31792 type
= get_attr_type (insn
);
31804 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31805 && get_attr_update (insn
) == UPDATE_YES
)
31810 if (get_attr_update (insn
) == UPDATE_YES
31811 && get_attr_indexed (insn
) == INDEXED_YES
)
31826 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31827 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31830 is_costly_group (rtx
*group_insns
, rtx next_insn
)
31833 int issue_rate
= rs6000_issue_rate ();
31835 for (i
= 0; i
< issue_rate
; i
++)
31837 sd_iterator_def sd_it
;
31839 rtx insn
= group_insns
[i
];
31844 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
31846 rtx next
= DEP_CON (dep
);
31848 if (next
== next_insn
31849 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
31857 /* Utility of the function redefine_groups.
31858 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31859 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31860 to keep it "far" (in a separate group) from GROUP_INSNS, following
31861 one of the following schemes, depending on the value of the flag
31862 -minsert_sched_nops = X:
31863 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31864 in order to force NEXT_INSN into a separate group.
31865 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31866 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31867 insertion (has a group just ended, how many vacant issue slots remain in the
31868 last group, and how many dispatch groups were encountered so far). */
31871 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
31872 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
31877 int issue_rate
= rs6000_issue_rate ();
31878 bool end
= *group_end
;
31881 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
31882 return can_issue_more
;
31884 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
31885 return can_issue_more
;
31887 force
= is_costly_group (group_insns
, next_insn
);
31889 return can_issue_more
;
31891 if (sched_verbose
> 6)
31892 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
31893 *group_count
,can_issue_more
);
31895 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
31898 can_issue_more
= 0;
31900 /* Since only a branch can be issued in the last issue_slot, it is
31901 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31902 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31903 in this case the last nop will start a new group and the branch
31904 will be forced to the new group. */
31905 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
31908 /* Do we have a special group ending nop? */
31909 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
31910 || rs6000_cpu_attr
== CPU_POWER8
)
31912 nop
= gen_group_ending_nop ();
31913 emit_insn_before (nop
, next_insn
);
31914 can_issue_more
= 0;
31917 while (can_issue_more
> 0)
31920 emit_insn_before (nop
, next_insn
);
31928 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
31930 int n_nops
= rs6000_sched_insert_nops
;
31932 /* Nops can't be issued from the branch slot, so the effective
31933 issue_rate for nops is 'issue_rate - 1'. */
31934 if (can_issue_more
== 0)
31935 can_issue_more
= issue_rate
;
31937 if (can_issue_more
== 0)
31939 can_issue_more
= issue_rate
- 1;
31942 for (i
= 0; i
< issue_rate
; i
++)
31944 group_insns
[i
] = 0;
31951 emit_insn_before (nop
, next_insn
);
31952 if (can_issue_more
== issue_rate
- 1) /* new group begins */
31955 if (can_issue_more
== 0)
31957 can_issue_more
= issue_rate
- 1;
31960 for (i
= 0; i
< issue_rate
; i
++)
31962 group_insns
[i
] = 0;
31968 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31971 /* Is next_insn going to start a new group? */
31974 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
31975 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
31976 || (can_issue_more
< issue_rate
&&
31977 insn_terminates_group_p (next_insn
, previous_group
)));
31978 if (*group_end
&& end
)
31981 if (sched_verbose
> 6)
31982 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
31983 *group_count
, can_issue_more
);
31984 return can_issue_more
;
31987 return can_issue_more
;
31990 /* This function tries to synch the dispatch groups that the compiler "sees"
31991 with the dispatch groups that the processor dispatcher is expected to
31992 form in practice. It tries to achieve this synchronization by forcing the
31993 estimated processor grouping on the compiler (as opposed to the function
31994 'pad_goups' which tries to force the scheduler's grouping on the processor).
31996 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31997 examines the (estimated) dispatch groups that will be formed by the processor
31998 dispatcher. It marks these group boundaries to reflect the estimated
31999 processor grouping, overriding the grouping that the scheduler had marked.
32000 Depending on the value of the flag '-minsert-sched-nops' this function can
32001 force certain insns into separate groups or force a certain distance between
32002 them by inserting nops, for example, if there exists a "costly dependence"
32005 The function estimates the group boundaries that the processor will form as
32006 follows: It keeps track of how many vacant issue slots are available after
32007 each insn. A subsequent insn will start a new group if one of the following
32009 - no more vacant issue slots remain in the current dispatch group.
32010 - only the last issue slot, which is the branch slot, is vacant, but the next
32011 insn is not a branch.
32012 - only the last 2 or less issue slots, including the branch slot, are vacant,
32013 which means that a cracked insn (which occupies two issue slots) can't be
32014 issued in this group.
32015 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32016 start a new group. */
32019 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
32022 rtx_insn
*insn
, *next_insn
;
32024 int can_issue_more
;
32027 int group_count
= 0;
32031 issue_rate
= rs6000_issue_rate ();
32032 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
32033 for (i
= 0; i
< issue_rate
; i
++)
32035 group_insns
[i
] = 0;
32037 can_issue_more
= issue_rate
;
32039 insn
= get_next_active_insn (prev_head_insn
, tail
);
32042 while (insn
!= NULL_RTX
)
32044 slot
= (issue_rate
- can_issue_more
);
32045 group_insns
[slot
] = insn
;
32047 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
32048 if (insn_terminates_group_p (insn
, current_group
))
32049 can_issue_more
= 0;
32051 next_insn
= get_next_active_insn (insn
, tail
);
32052 if (next_insn
== NULL_RTX
)
32053 return group_count
+ 1;
32055 /* Is next_insn going to start a new group? */
32057 = (can_issue_more
== 0
32058 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
32059 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
32060 || (can_issue_more
< issue_rate
&&
32061 insn_terminates_group_p (next_insn
, previous_group
)));
32063 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
32064 next_insn
, &group_end
, can_issue_more
,
32070 can_issue_more
= 0;
32071 for (i
= 0; i
< issue_rate
; i
++)
32073 group_insns
[i
] = 0;
32077 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
32078 PUT_MODE (next_insn
, VOIDmode
);
32079 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
32080 PUT_MODE (next_insn
, TImode
);
32083 if (can_issue_more
== 0)
32084 can_issue_more
= issue_rate
;
32087 return group_count
;
32090 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32091 dispatch group boundaries that the scheduler had marked. Pad with nops
32092 any dispatch groups which have vacant issue slots, in order to force the
32093 scheduler's grouping on the processor dispatcher. The function
32094 returns the number of dispatch groups found. */
32097 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
32100 rtx_insn
*insn
, *next_insn
;
32103 int can_issue_more
;
32105 int group_count
= 0;
32107 /* Initialize issue_rate. */
32108 issue_rate
= rs6000_issue_rate ();
32109 can_issue_more
= issue_rate
;
32111 insn
= get_next_active_insn (prev_head_insn
, tail
);
32112 next_insn
= get_next_active_insn (insn
, tail
);
32114 while (insn
!= NULL_RTX
)
32117 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
32119 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
32121 if (next_insn
== NULL_RTX
)
32126 /* If the scheduler had marked group termination at this location
32127 (between insn and next_insn), and neither insn nor next_insn will
32128 force group termination, pad the group with nops to force group
32131 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
32132 && !insn_terminates_group_p (insn
, current_group
)
32133 && !insn_terminates_group_p (next_insn
, previous_group
))
32135 if (!is_branch_slot_insn (next_insn
))
32138 while (can_issue_more
)
32141 emit_insn_before (nop
, next_insn
);
32146 can_issue_more
= issue_rate
;
32151 next_insn
= get_next_active_insn (insn
, tail
);
32154 return group_count
;
32157 /* We're beginning a new block. Initialize data structures as necessary. */
32160 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
32161 int sched_verbose ATTRIBUTE_UNUSED
,
32162 int max_ready ATTRIBUTE_UNUSED
)
32164 last_scheduled_insn
= NULL
;
32165 load_store_pendulum
= 0;
32170 /* The following function is called at the end of scheduling BB.
32171 After reload, it inserts nops at insn group bundling. */
32174 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
32179 fprintf (dump
, "=== Finishing schedule.\n");
32181 if (reload_completed
&& rs6000_sched_groups
)
32183 /* Do not run sched_finish hook when selective scheduling enabled. */
32184 if (sel_sched_p ())
32187 if (rs6000_sched_insert_nops
== sched_finish_none
)
32190 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
32191 n_groups
= pad_groups (dump
, sched_verbose
,
32192 current_sched_info
->prev_head
,
32193 current_sched_info
->next_tail
);
32195 n_groups
= redefine_groups (dump
, sched_verbose
,
32196 current_sched_info
->prev_head
,
32197 current_sched_info
->next_tail
);
32199 if (sched_verbose
>= 6)
32201 fprintf (dump
, "ngroups = %d\n", n_groups
);
32202 print_rtl (dump
, current_sched_info
->prev_head
);
32203 fprintf (dump
, "Done finish_sched\n");
32208 struct rs6000_sched_context
32210 short cached_can_issue_more
;
32211 rtx_insn
*last_scheduled_insn
;
32212 int load_store_pendulum
;
32217 typedef struct rs6000_sched_context rs6000_sched_context_def
;
32218 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
32220 /* Allocate store for new scheduling context. */
32222 rs6000_alloc_sched_context (void)
32224 return xmalloc (sizeof (rs6000_sched_context_def
));
32227 /* If CLEAN_P is true then initializes _SC with clean data,
32228 and from the global context otherwise. */
32230 rs6000_init_sched_context (void *_sc
, bool clean_p
)
32232 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32236 sc
->cached_can_issue_more
= 0;
32237 sc
->last_scheduled_insn
= NULL
;
32238 sc
->load_store_pendulum
= 0;
32239 sc
->divide_cnt
= 0;
32240 sc
->vec_pairing
= 0;
32244 sc
->cached_can_issue_more
= cached_can_issue_more
;
32245 sc
->last_scheduled_insn
= last_scheduled_insn
;
32246 sc
->load_store_pendulum
= load_store_pendulum
;
32247 sc
->divide_cnt
= divide_cnt
;
32248 sc
->vec_pairing
= vec_pairing
;
32252 /* Sets the global scheduling context to the one pointed to by _SC. */
32254 rs6000_set_sched_context (void *_sc
)
32256 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32258 gcc_assert (sc
!= NULL
);
32260 cached_can_issue_more
= sc
->cached_can_issue_more
;
32261 last_scheduled_insn
= sc
->last_scheduled_insn
;
32262 load_store_pendulum
= sc
->load_store_pendulum
;
32263 divide_cnt
= sc
->divide_cnt
;
32264 vec_pairing
= sc
->vec_pairing
;
32269 rs6000_free_sched_context (void *_sc
)
32271 gcc_assert (_sc
!= NULL
);
32277 rs6000_sched_can_speculate_insn (rtx_insn
*insn
)
32279 switch (get_attr_type (insn
))
32294 /* Length in units of the trampoline for entering a nested function. */
32297 rs6000_trampoline_size (void)
32301 switch (DEFAULT_ABI
)
32304 gcc_unreachable ();
32307 ret
= (TARGET_32BIT
) ? 12 : 24;
32311 gcc_assert (!TARGET_32BIT
);
32317 ret
= (TARGET_32BIT
) ? 40 : 48;
32324 /* Emit RTL insns to initialize the variable parts of a trampoline.
32325 FNADDR is an RTX for the address of the function's pure code.
32326 CXT is an RTX for the static chain value for the function. */
32329 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
32331 int regsize
= (TARGET_32BIT
) ? 4 : 8;
32332 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
32333 rtx ctx_reg
= force_reg (Pmode
, cxt
);
32334 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
32336 switch (DEFAULT_ABI
)
32339 gcc_unreachable ();
32341 /* Under AIX, just build the 3 word function descriptor */
32344 rtx fnmem
, fn_reg
, toc_reg
;
32346 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32347 error ("you cannot take the address of a nested function if you use "
32348 "the %qs option", "-mno-pointers-to-nested-functions");
32350 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
32351 fn_reg
= gen_reg_rtx (Pmode
);
32352 toc_reg
= gen_reg_rtx (Pmode
);
32354 /* Macro to shorten the code expansions below. */
32355 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32357 m_tramp
= replace_equiv_address (m_tramp
, addr
);
32359 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
32360 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
32361 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
32362 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
32363 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
32369 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32373 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
32374 LCT_NORMAL
, VOIDmode
, 4,
32376 GEN_INT (rs6000_trampoline_size ()), SImode
,
32384 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32385 identifier as an argument, so the front end shouldn't look it up. */
32388 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
32390 return is_attribute_p ("altivec", attr_id
);
32393 /* Handle the "altivec" attribute. The attribute may have
32394 arguments as follows:
32396 __attribute__((altivec(vector__)))
32397 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32398 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32400 and may appear more than once (e.g., 'vector bool char') in a
32401 given declaration. */
32404 rs6000_handle_altivec_attribute (tree
*node
,
32405 tree name ATTRIBUTE_UNUSED
,
32407 int flags ATTRIBUTE_UNUSED
,
32408 bool *no_add_attrs
)
32410 tree type
= *node
, result
= NULL_TREE
;
32414 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
32415 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
32416 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
32419 while (POINTER_TYPE_P (type
)
32420 || TREE_CODE (type
) == FUNCTION_TYPE
32421 || TREE_CODE (type
) == METHOD_TYPE
32422 || TREE_CODE (type
) == ARRAY_TYPE
)
32423 type
= TREE_TYPE (type
);
32425 mode
= TYPE_MODE (type
);
32427 /* Check for invalid AltiVec type qualifiers. */
32428 if (type
== long_double_type_node
)
32429 error ("use of %<long double%> in AltiVec types is invalid");
32430 else if (type
== boolean_type_node
)
32431 error ("use of boolean types in AltiVec types is invalid");
32432 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
32433 error ("use of %<complex%> in AltiVec types is invalid");
32434 else if (DECIMAL_FLOAT_MODE_P (mode
))
32435 error ("use of decimal floating point types in AltiVec types is invalid");
32436 else if (!TARGET_VSX
)
32438 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
32441 error ("use of %<long%> in AltiVec types is invalid for "
32442 "64-bit code without %qs", "-mvsx");
32443 else if (rs6000_warn_altivec_long
)
32444 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32447 else if (type
== long_long_unsigned_type_node
32448 || type
== long_long_integer_type_node
)
32449 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32451 else if (type
== double_type_node
)
32452 error ("use of %<double%> in AltiVec types is invalid without %qs",
32456 switch (altivec_type
)
32459 unsigned_p
= TYPE_UNSIGNED (type
);
32463 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
32466 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
32469 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
32472 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
32475 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
32477 case SFmode
: result
= V4SF_type_node
; break;
32478 case DFmode
: result
= V2DF_type_node
; break;
32479 /* If the user says 'vector int bool', we may be handed the 'bool'
32480 attribute _before_ the 'vector' attribute, and so select the
32481 proper type in the 'b' case below. */
32482 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
32483 case V2DImode
: case V2DFmode
:
32491 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
32492 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
32493 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
32494 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
32501 case V8HImode
: result
= pixel_V8HI_type_node
;
32507 /* Propagate qualifiers attached to the element type
32508 onto the vector type. */
32509 if (result
&& result
!= type
&& TYPE_QUALS (type
))
32510 result
= build_qualified_type (result
, TYPE_QUALS (type
));
32512 *no_add_attrs
= true; /* No need to hang on to the attribute. */
32515 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
32520 /* AltiVec defines four built-in scalar types that serve as vector
32521 elements; we must teach the compiler how to mangle them. */
32523 static const char *
32524 rs6000_mangle_type (const_tree type
)
32526 type
= TYPE_MAIN_VARIANT (type
);
32528 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
32529 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
32532 if (type
== bool_char_type_node
) return "U6__boolc";
32533 if (type
== bool_short_type_node
) return "U6__bools";
32534 if (type
== pixel_type_node
) return "u7__pixel";
32535 if (type
== bool_int_type_node
) return "U6__booli";
32536 if (type
== bool_long_type_node
) return "U6__booll";
32538 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
32539 "g" for IBM extended double, no matter whether it is long double (using
32540 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
32541 if (TARGET_FLOAT128_TYPE
)
32543 if (type
== ieee128_float_type_node
)
32544 return "U10__float128";
32546 if (type
== ibm128_float_type_node
)
32549 if (type
== long_double_type_node
&& TARGET_LONG_DOUBLE_128
)
32550 return (TARGET_IEEEQUAD
) ? "U10__float128" : "g";
32553 /* Mangle IBM extended float long double as `g' (__float128) on
32554 powerpc*-linux where long-double-64 previously was the default. */
32555 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
32557 && TARGET_LONG_DOUBLE_128
32558 && !TARGET_IEEEQUAD
)
32561 /* For all other types, use normal C++ mangling. */
32565 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32566 struct attribute_spec.handler. */
32569 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
32570 tree args ATTRIBUTE_UNUSED
,
32571 int flags ATTRIBUTE_UNUSED
,
32572 bool *no_add_attrs
)
32574 if (TREE_CODE (*node
) != FUNCTION_TYPE
32575 && TREE_CODE (*node
) != FIELD_DECL
32576 && TREE_CODE (*node
) != TYPE_DECL
)
32578 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
32580 *no_add_attrs
= true;
32586 /* Set longcall attributes on all functions declared when
32587 rs6000_default_long_calls is true. */
32589 rs6000_set_default_type_attributes (tree type
)
32591 if (rs6000_default_long_calls
32592 && (TREE_CODE (type
) == FUNCTION_TYPE
32593 || TREE_CODE (type
) == METHOD_TYPE
))
32594 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
32596 TYPE_ATTRIBUTES (type
));
32599 darwin_set_default_type_attributes (type
);
32603 /* Return a reference suitable for calling a function with the
32604 longcall attribute. */
32607 rs6000_longcall_ref (rtx call_ref
)
32609 const char *call_name
;
32612 if (GET_CODE (call_ref
) != SYMBOL_REF
)
32615 /* System V adds '.' to the internal name, so skip them. */
32616 call_name
= XSTR (call_ref
, 0);
32617 if (*call_name
== '.')
32619 while (*call_name
== '.')
32622 node
= get_identifier (call_name
);
32623 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
32626 return force_reg (Pmode
, call_ref
);
32629 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32630 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32633 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32634 struct attribute_spec.handler. */
32636 rs6000_handle_struct_attribute (tree
*node
, tree name
,
32637 tree args ATTRIBUTE_UNUSED
,
32638 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
32641 if (DECL_P (*node
))
32643 if (TREE_CODE (*node
) == TYPE_DECL
)
32644 type
= &TREE_TYPE (*node
);
32649 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
32650 || TREE_CODE (*type
) == UNION_TYPE
)))
32652 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
32653 *no_add_attrs
= true;
32656 else if ((is_attribute_p ("ms_struct", name
)
32657 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
32658 || ((is_attribute_p ("gcc_struct", name
)
32659 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
32661 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
32663 *no_add_attrs
= true;
32670 rs6000_ms_bitfield_layout_p (const_tree record_type
)
32672 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
32673 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
32674 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
32677 #ifdef USING_ELFOS_H
32679 /* A get_unnamed_section callback, used for switching to toc_section. */
32682 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
32684 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
32685 && TARGET_MINIMAL_TOC
)
32687 if (!toc_initialized
)
32689 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
32690 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32691 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
32692 fprintf (asm_out_file
, "\t.tc ");
32693 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
32694 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32695 fprintf (asm_out_file
, "\n");
32697 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32698 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32699 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32700 fprintf (asm_out_file
, " = .+32768\n");
32701 toc_initialized
= 1;
32704 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32706 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
32708 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
32709 if (!toc_initialized
)
32711 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32712 toc_initialized
= 1;
32717 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32718 if (!toc_initialized
)
32720 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32721 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32722 fprintf (asm_out_file
, " = .+32768\n");
32723 toc_initialized
= 1;
32728 /* Implement TARGET_ASM_INIT_SECTIONS. */
32731 rs6000_elf_asm_init_sections (void)
32734 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
32737 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
32738 SDATA2_SECTION_ASM_OP
);
32741 /* Implement TARGET_SELECT_RTX_SECTION. */
32744 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
32745 unsigned HOST_WIDE_INT align
)
32747 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
32748 return toc_section
;
32750 return default_elf_select_rtx_section (mode
, x
, align
);
32753 /* For a SYMBOL_REF, set generic flags and then perform some
32754 target-specific processing.
32756 When the AIX ABI is requested on a non-AIX system, replace the
32757 function name with the real name (with a leading .) rather than the
32758 function descriptor name. This saves a lot of overriding code to
32759 read the prefixes. */
32761 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
32763 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
32765 default_encode_section_info (decl
, rtl
, first
);
32768 && TREE_CODE (decl
) == FUNCTION_DECL
32770 && DEFAULT_ABI
== ABI_AIX
)
32772 rtx sym_ref
= XEXP (rtl
, 0);
32773 size_t len
= strlen (XSTR (sym_ref
, 0));
32774 char *str
= XALLOCAVEC (char, len
+ 2);
32776 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
32777 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
32782 compare_section_name (const char *section
, const char *templ
)
32786 len
= strlen (templ
);
32787 return (strncmp (section
, templ
, len
) == 0
32788 && (section
[len
] == 0 || section
[len
] == '.'));
32792 rs6000_elf_in_small_data_p (const_tree decl
)
32794 if (rs6000_sdata
== SDATA_NONE
)
32797 /* We want to merge strings, so we never consider them small data. */
32798 if (TREE_CODE (decl
) == STRING_CST
)
32801 /* Functions are never in the small data area. */
32802 if (TREE_CODE (decl
) == FUNCTION_DECL
)
32805 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
32807 const char *section
= DECL_SECTION_NAME (decl
);
32808 if (compare_section_name (section
, ".sdata")
32809 || compare_section_name (section
, ".sdata2")
32810 || compare_section_name (section
, ".gnu.linkonce.s")
32811 || compare_section_name (section
, ".sbss")
32812 || compare_section_name (section
, ".sbss2")
32813 || compare_section_name (section
, ".gnu.linkonce.sb")
32814 || strcmp (section
, ".PPC.EMB.sdata0") == 0
32815 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
32820 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
32823 && size
<= g_switch_value
32824 /* If it's not public, and we're not going to reference it there,
32825 there's no need to put it in the small data section. */
32826 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
32833 #endif /* USING_ELFOS_H */
32835 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32838 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
32840 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
32843 /* Do not place thread-local symbols refs in the object blocks. */
32846 rs6000_use_blocks_for_decl_p (const_tree decl
)
32848 return !DECL_THREAD_LOCAL_P (decl
);
32851 /* Return a REG that occurs in ADDR with coefficient 1.
32852 ADDR can be effectively incremented by incrementing REG.
32854 r0 is special and we must not select it as an address
32855 register by this routine since our caller will try to
32856 increment the returned register via an "la" instruction. */
32859 find_addr_reg (rtx addr
)
32861 while (GET_CODE (addr
) == PLUS
)
32863 if (GET_CODE (XEXP (addr
, 0)) == REG
32864 && REGNO (XEXP (addr
, 0)) != 0)
32865 addr
= XEXP (addr
, 0);
32866 else if (GET_CODE (XEXP (addr
, 1)) == REG
32867 && REGNO (XEXP (addr
, 1)) != 0)
32868 addr
= XEXP (addr
, 1);
32869 else if (CONSTANT_P (XEXP (addr
, 0)))
32870 addr
= XEXP (addr
, 1);
32871 else if (CONSTANT_P (XEXP (addr
, 1)))
32872 addr
= XEXP (addr
, 0);
32874 gcc_unreachable ();
32876 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
32881 rs6000_fatal_bad_address (rtx op
)
32883 fatal_insn ("bad address", op
);
32888 typedef struct branch_island_d
{
32889 tree function_name
;
32895 static vec
<branch_island
, va_gc
> *branch_islands
;
32897 /* Remember to generate a branch island for far calls to the given
32901 add_compiler_branch_island (tree label_name
, tree function_name
,
32904 branch_island bi
= {function_name
, label_name
, line_number
};
32905 vec_safe_push (branch_islands
, bi
);
32908 /* Generate far-jump branch islands for everything recorded in
32909 branch_islands. Invoked immediately after the last instruction of
32910 the epilogue has been emitted; the branch islands must be appended
32911 to, and contiguous with, the function body. Mach-O stubs are
32912 generated in machopic_output_stub(). */
32915 macho_branch_islands (void)
32919 while (!vec_safe_is_empty (branch_islands
))
32921 branch_island
*bi
= &branch_islands
->last ();
32922 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
32923 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
32924 char name_buf
[512];
32925 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32926 if (name
[0] == '*' || name
[0] == '&')
32927 strcpy (name_buf
, name
+1);
32931 strcpy (name_buf
+1, name
);
32933 strcpy (tmp_buf
, "\n");
32934 strcat (tmp_buf
, label
);
32935 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32936 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
32937 dbxout_stabd (N_SLINE
, bi
->line_number
);
32938 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32941 if (TARGET_LINK_STACK
)
32944 get_ppc476_thunk_name (name
);
32945 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
32946 strcat (tmp_buf
, name
);
32947 strcat (tmp_buf
, "\n");
32948 strcat (tmp_buf
, label
);
32949 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
32953 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
32954 strcat (tmp_buf
, label
);
32955 strcat (tmp_buf
, "_pic\n");
32956 strcat (tmp_buf
, label
);
32957 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
32960 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
32961 strcat (tmp_buf
, name_buf
);
32962 strcat (tmp_buf
, " - ");
32963 strcat (tmp_buf
, label
);
32964 strcat (tmp_buf
, "_pic)\n");
32966 strcat (tmp_buf
, "\tmtlr r0\n");
32968 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
32969 strcat (tmp_buf
, name_buf
);
32970 strcat (tmp_buf
, " - ");
32971 strcat (tmp_buf
, label
);
32972 strcat (tmp_buf
, "_pic)\n");
32974 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
32978 strcat (tmp_buf
, ":\nlis r12,hi16(");
32979 strcat (tmp_buf
, name_buf
);
32980 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
32981 strcat (tmp_buf
, name_buf
);
32982 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
32984 output_asm_insn (tmp_buf
, 0);
32985 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32986 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
32987 dbxout_stabd (N_SLINE
, bi
->line_number
);
32988 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32989 branch_islands
->pop ();
32993 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32994 already there or not. */
32997 no_previous_def (tree function_name
)
33002 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
33003 if (function_name
== bi
->function_name
)
33008 /* GET_PREV_LABEL gets the label name from the previous definition of
33012 get_prev_label (tree function_name
)
33017 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
33018 if (function_name
== bi
->function_name
)
33019 return bi
->label_name
;
33023 /* INSN is either a function call or a millicode call. It may have an
33024 unconditional jump in its delay slot.
33026 CALL_DEST is the routine we are calling. */
33029 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
33030 int cookie_operand_number
)
33032 static char buf
[256];
33033 if (darwin_emit_branch_islands
33034 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
33035 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
33038 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
33040 if (no_previous_def (funname
))
33042 rtx label_rtx
= gen_label_rtx ();
33043 char *label_buf
, temp_buf
[256];
33044 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
33045 CODE_LABEL_NUMBER (label_rtx
));
33046 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
33047 labelname
= get_identifier (label_buf
);
33048 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
33051 labelname
= get_prev_label (funname
);
33053 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33054 instruction will reach 'foo', otherwise link as 'bl L42'".
33055 "L42" should be a 'branch island', that will do a far jump to
33056 'foo'. Branch islands are generated in
33057 macho_branch_islands(). */
33058 sprintf (buf
, "jbsr %%z%d,%.246s",
33059 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
33062 sprintf (buf
, "bl %%z%d", dest_operand_number
);
33066 /* Generate PIC and indirect symbol stubs. */
33069 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
33071 unsigned int length
;
33072 char *symbol_name
, *lazy_ptr_name
;
33073 char *local_label_0
;
33074 static int label
= 0;
33076 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33077 symb
= (*targetm
.strip_name_encoding
) (symb
);
33080 length
= strlen (symb
);
33081 symbol_name
= XALLOCAVEC (char, length
+ 32);
33082 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
33084 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
33085 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
33088 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
33090 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
33094 fprintf (file
, "\t.align 5\n");
33096 fprintf (file
, "%s:\n", stub
);
33097 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33100 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33101 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
33103 fprintf (file
, "\tmflr r0\n");
33104 if (TARGET_LINK_STACK
)
33107 get_ppc476_thunk_name (name
);
33108 fprintf (file
, "\tbl %s\n", name
);
33109 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
33113 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
33114 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
33116 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
33117 lazy_ptr_name
, local_label_0
);
33118 fprintf (file
, "\tmtlr r0\n");
33119 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
33120 (TARGET_64BIT
? "ldu" : "lwzu"),
33121 lazy_ptr_name
, local_label_0
);
33122 fprintf (file
, "\tmtctr r12\n");
33123 fprintf (file
, "\tbctr\n");
33127 fprintf (file
, "\t.align 4\n");
33129 fprintf (file
, "%s:\n", stub
);
33130 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33132 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
33133 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
33134 (TARGET_64BIT
? "ldu" : "lwzu"),
33136 fprintf (file
, "\tmtctr r12\n");
33137 fprintf (file
, "\tbctr\n");
33140 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
33141 fprintf (file
, "%s:\n", lazy_ptr_name
);
33142 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33143 fprintf (file
, "%sdyld_stub_binding_helper\n",
33144 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
33147 /* Legitimize PIC addresses. If the address is already
33148 position-independent, we return ORIG. Newly generated
33149 position-independent addresses go into a reg. This is REG if non
33150 zero, otherwise we allocate register(s) as necessary. */
33152 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33155 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
33160 if (reg
== NULL
&& !reload_completed
)
33161 reg
= gen_reg_rtx (Pmode
);
33163 if (GET_CODE (orig
) == CONST
)
33167 if (GET_CODE (XEXP (orig
, 0)) == PLUS
33168 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
33171 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
33173 /* Use a different reg for the intermediate value, as
33174 it will be marked UNCHANGING. */
33175 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
33176 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
33179 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
33182 if (GET_CODE (offset
) == CONST_INT
)
33184 if (SMALL_INT (offset
))
33185 return plus_constant (Pmode
, base
, INTVAL (offset
));
33186 else if (!reload_completed
)
33187 offset
= force_reg (Pmode
, offset
);
33190 rtx mem
= force_const_mem (Pmode
, orig
);
33191 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
33194 return gen_rtx_PLUS (Pmode
, base
, offset
);
33197 /* Fall back on generic machopic code. */
33198 return machopic_legitimize_pic_address (orig
, mode
, reg
);
33201 /* Output a .machine directive for the Darwin assembler, and call
33202 the generic start_file routine. */
33205 rs6000_darwin_file_start (void)
33207 static const struct
33211 HOST_WIDE_INT if_set
;
33213 { "ppc64", "ppc64", MASK_64BIT
},
33214 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
33215 { "power4", "ppc970", 0 },
33216 { "G5", "ppc970", 0 },
33217 { "7450", "ppc7450", 0 },
33218 { "7400", "ppc7400", MASK_ALTIVEC
},
33219 { "G4", "ppc7400", 0 },
33220 { "750", "ppc750", 0 },
33221 { "740", "ppc750", 0 },
33222 { "G3", "ppc750", 0 },
33223 { "604e", "ppc604e", 0 },
33224 { "604", "ppc604", 0 },
33225 { "603e", "ppc603", 0 },
33226 { "603", "ppc603", 0 },
33227 { "601", "ppc601", 0 },
33228 { NULL
, "ppc", 0 } };
33229 const char *cpu_id
= "";
33232 rs6000_file_start ();
33233 darwin_file_start ();
33235 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33237 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
33238 cpu_id
= rs6000_default_cpu
;
33240 if (global_options_set
.x_rs6000_cpu_index
)
33241 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
33243 /* Look through the mapping array. Pick the first name that either
33244 matches the argument, has a bit set in IF_SET that is also set
33245 in the target flags, or has a NULL name. */
33248 while (mapping
[i
].arg
!= NULL
33249 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
33250 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
33253 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
33256 #endif /* TARGET_MACHO */
33260 rs6000_elf_reloc_rw_mask (void)
33264 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
33270 /* Record an element in the table of global constructors. SYMBOL is
33271 a SYMBOL_REF of the function to be called; PRIORITY is a number
33272 between 0 and MAX_INIT_PRIORITY.
33274 This differs from default_named_section_asm_out_constructor in
33275 that we have special handling for -mrelocatable. */
33277 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
33279 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
33281 const char *section
= ".ctors";
33284 if (priority
!= DEFAULT_INIT_PRIORITY
)
33286 sprintf (buf
, ".ctors.%.5u",
33287 /* Invert the numbering so the linker puts us in the proper
33288 order; constructors are run from right to left, and the
33289 linker sorts in increasing order. */
33290 MAX_INIT_PRIORITY
- priority
);
33294 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33295 assemble_align (POINTER_SIZE
);
33297 if (DEFAULT_ABI
== ABI_V4
33298 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33300 fputs ("\t.long (", asm_out_file
);
33301 output_addr_const (asm_out_file
, symbol
);
33302 fputs (")@fixup\n", asm_out_file
);
33305 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33308 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
33310 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
33312 const char *section
= ".dtors";
33315 if (priority
!= DEFAULT_INIT_PRIORITY
)
33317 sprintf (buf
, ".dtors.%.5u",
33318 /* Invert the numbering so the linker puts us in the proper
33319 order; constructors are run from right to left, and the
33320 linker sorts in increasing order. */
33321 MAX_INIT_PRIORITY
- priority
);
33325 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33326 assemble_align (POINTER_SIZE
);
33328 if (DEFAULT_ABI
== ABI_V4
33329 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33331 fputs ("\t.long (", asm_out_file
);
33332 output_addr_const (asm_out_file
, symbol
);
33333 fputs (")@fixup\n", asm_out_file
);
33336 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33340 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
33342 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
33344 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
33345 ASM_OUTPUT_LABEL (file
, name
);
33346 fputs (DOUBLE_INT_ASM_OP
, file
);
33347 rs6000_output_function_entry (file
, name
);
33348 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
33351 fputs ("\t.size\t", file
);
33352 assemble_name (file
, name
);
33353 fputs (",24\n\t.type\t.", file
);
33354 assemble_name (file
, name
);
33355 fputs (",@function\n", file
);
33356 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
33358 fputs ("\t.globl\t.", file
);
33359 assemble_name (file
, name
);
33364 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33365 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33366 rs6000_output_function_entry (file
, name
);
33367 fputs (":\n", file
);
33371 if (DEFAULT_ABI
== ABI_V4
33372 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
33373 && !TARGET_SECURE_PLT
33374 && (!constant_pool_empty_p () || crtl
->profile
)
33379 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33381 fprintf (file
, "\t.long ");
33382 assemble_name (file
, toc_label_name
);
33385 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33386 assemble_name (file
, buf
);
33390 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33391 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33393 if (TARGET_CMODEL
== CMODEL_LARGE
&& rs6000_global_entry_point_needed_p ())
33397 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33399 fprintf (file
, "\t.quad .TOC.-");
33400 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33401 assemble_name (file
, buf
);
33405 if (DEFAULT_ABI
== ABI_AIX
)
33407 const char *desc_name
, *orig_name
;
33409 orig_name
= (*targetm
.strip_name_encoding
) (name
);
33410 desc_name
= orig_name
;
33411 while (*desc_name
== '.')
33414 if (TREE_PUBLIC (decl
))
33415 fprintf (file
, "\t.globl %s\n", desc_name
);
33417 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33418 fprintf (file
, "%s:\n", desc_name
);
33419 fprintf (file
, "\t.long %s\n", orig_name
);
33420 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
33421 fputs ("\t.long 0\n", file
);
33422 fprintf (file
, "\t.previous\n");
33424 ASM_OUTPUT_LABEL (file
, name
);
33427 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
33429 rs6000_elf_file_end (void)
33431 #ifdef HAVE_AS_GNU_ATTRIBUTE
33432 /* ??? The value emitted depends on options active at file end.
33433 Assume anyone using #pragma or attributes that might change
33434 options knows what they are doing. */
33435 if ((TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
33436 && rs6000_passes_float
)
33442 else if (TARGET_SF_FPR
)
33446 if (rs6000_passes_long_double
)
33448 if (!TARGET_LONG_DOUBLE_128
)
33450 else if (TARGET_IEEEQUAD
)
33455 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", fp
);
33457 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
33459 if (rs6000_passes_vector
)
33460 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
33461 (TARGET_ALTIVEC_ABI
? 2 : 1));
33462 if (rs6000_returns_struct
)
33463 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
33464 aix_struct_return
? 2 : 1);
33467 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33468 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
33469 file_end_indicate_exec_stack ();
33472 if (flag_split_stack
)
33473 file_end_indicate_split_stack ();
33477 /* We have expanded a CPU builtin, so we need to emit a reference to
33478 the special symbol that LIBC uses to declare it supports the
33479 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33480 switch_to_section (data_section
);
33481 fprintf (asm_out_file
, "\t.align %u\n", TARGET_32BIT
? 2 : 3);
33482 fprintf (asm_out_file
, "\t%s %s\n",
33483 TARGET_32BIT
? ".long" : ".quad", tcb_verification_symbol
);
33490 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33491 #define HAVE_XCOFF_DWARF_EXTRAS 0
33494 static enum unwind_info_type
33495 rs6000_xcoff_debug_unwind_info (void)
33501 rs6000_xcoff_asm_output_anchor (rtx symbol
)
33505 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
33506 SYMBOL_REF_BLOCK_OFFSET (symbol
));
33507 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
33508 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
33509 fprintf (asm_out_file
, ",");
33510 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
33511 fprintf (asm_out_file
, "\n");
33515 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
33517 fputs (GLOBAL_ASM_OP
, stream
);
33518 RS6000_OUTPUT_BASENAME (stream
, name
);
33519 putc ('\n', stream
);
33522 /* A get_unnamed_decl callback, used for read-only sections. PTR
33523 points to the section string variable. */
33526 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
33528 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
33529 *(const char *const *) directive
,
33530 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33533 /* Likewise for read-write sections. */
33536 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
33538 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
33539 *(const char *const *) directive
,
33540 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33544 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
33546 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
33547 *(const char *const *) directive
,
33548 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33551 /* A get_unnamed_section callback, used for switching to toc_section. */
33554 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
33556 if (TARGET_MINIMAL_TOC
)
33558 /* toc_section is always selected at least once from
33559 rs6000_xcoff_file_start, so this is guaranteed to
33560 always be defined once and only once in each file. */
33561 if (!toc_initialized
)
33563 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
33564 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
33565 toc_initialized
= 1;
33567 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
33568 (TARGET_32BIT
? "" : ",3"));
33571 fputs ("\t.toc\n", asm_out_file
);
33574 /* Implement TARGET_ASM_INIT_SECTIONS. */
33577 rs6000_xcoff_asm_init_sections (void)
33579 read_only_data_section
33580 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33581 &xcoff_read_only_section_name
);
33583 private_data_section
33584 = get_unnamed_section (SECTION_WRITE
,
33585 rs6000_xcoff_output_readwrite_section_asm_op
,
33586 &xcoff_private_data_section_name
);
33589 = get_unnamed_section (SECTION_TLS
,
33590 rs6000_xcoff_output_tls_section_asm_op
,
33591 &xcoff_tls_data_section_name
);
33593 tls_private_data_section
33594 = get_unnamed_section (SECTION_TLS
,
33595 rs6000_xcoff_output_tls_section_asm_op
,
33596 &xcoff_private_data_section_name
);
33598 read_only_private_data_section
33599 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33600 &xcoff_private_data_section_name
);
33603 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
33605 readonly_data_section
= read_only_data_section
;
33609 rs6000_xcoff_reloc_rw_mask (void)
33615 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
33616 tree decl ATTRIBUTE_UNUSED
)
33619 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
33621 if (flags
& SECTION_EXCLUDE
)
33623 else if (flags
& SECTION_DEBUG
)
33625 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
33628 else if (flags
& SECTION_CODE
)
33630 else if (flags
& SECTION_TLS
)
33632 else if (flags
& SECTION_WRITE
)
33637 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
33638 (flags
& SECTION_CODE
) ? "." : "",
33639 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
33642 #define IN_NAMED_SECTION(DECL) \
33643 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33644 && DECL_SECTION_NAME (DECL) != NULL)
33647 rs6000_xcoff_select_section (tree decl
, int reloc
,
33648 unsigned HOST_WIDE_INT align
)
33650 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33652 if (align
> BIGGEST_ALIGNMENT
)
33654 resolve_unique_section (decl
, reloc
, true);
33655 if (IN_NAMED_SECTION (decl
))
33656 return get_named_section (decl
, NULL
, reloc
);
33659 if (decl_readonly_section (decl
, reloc
))
33661 if (TREE_PUBLIC (decl
))
33662 return read_only_data_section
;
33664 return read_only_private_data_section
;
33669 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
33671 if (TREE_PUBLIC (decl
))
33672 return tls_data_section
;
33673 else if (bss_initializer_p (decl
))
33675 /* Convert to COMMON to emit in BSS. */
33676 DECL_COMMON (decl
) = 1;
33677 return tls_comm_section
;
33680 return tls_private_data_section
;
33684 if (TREE_PUBLIC (decl
))
33685 return data_section
;
33687 return private_data_section
;
33692 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
33696 /* Use select_section for private data and uninitialized data with
33697 alignment <= BIGGEST_ALIGNMENT. */
33698 if (!TREE_PUBLIC (decl
)
33699 || DECL_COMMON (decl
)
33700 || (DECL_INITIAL (decl
) == NULL_TREE
33701 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
33702 || DECL_INITIAL (decl
) == error_mark_node
33703 || (flag_zero_initialized_in_bss
33704 && initializer_zerop (DECL_INITIAL (decl
))))
33707 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
33708 name
= (*targetm
.strip_name_encoding
) (name
);
33709 set_decl_section_name (decl
, name
);
33712 /* Select section for constant in constant pool.
33714 On RS/6000, all constants are in the private read-only data area.
33715 However, if this is being placed in the TOC it must be output as a
33719 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
33720 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
33722 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
33723 return toc_section
;
33725 return read_only_private_data_section
;
33728 /* Remove any trailing [DS] or the like from the symbol name. */
33730 static const char *
33731 rs6000_xcoff_strip_name_encoding (const char *name
)
33736 len
= strlen (name
);
33737 if (name
[len
- 1] == ']')
33738 return ggc_alloc_string (name
, len
- 4);
33743 /* Section attributes. AIX is always PIC. */
33745 static unsigned int
33746 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
33748 unsigned int align
;
33749 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
33751 /* Align to at least UNIT size. */
33752 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
33753 align
= MIN_UNITS_PER_WORD
;
33755 /* Increase alignment of large objects if not already stricter. */
33756 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
33757 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
33758 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
33760 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
33763 /* Output at beginning of assembler file.
33765 Initialize the section names for the RS/6000 at this point.
33767 Specify filename, including full path, to assembler.
33769 We want to go into the TOC section so at least one .toc will be emitted.
33770 Also, in order to output proper .bs/.es pairs, we need at least one static
33771 [RW] section emitted.
33773 Finally, declare mcount when profiling to make the assembler happy. */
33776 rs6000_xcoff_file_start (void)
33778 rs6000_gen_section_name (&xcoff_bss_section_name
,
33779 main_input_filename
, ".bss_");
33780 rs6000_gen_section_name (&xcoff_private_data_section_name
,
33781 main_input_filename
, ".rw_");
33782 rs6000_gen_section_name (&xcoff_read_only_section_name
,
33783 main_input_filename
, ".ro_");
33784 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
33785 main_input_filename
, ".tls_");
33786 rs6000_gen_section_name (&xcoff_tbss_section_name
,
33787 main_input_filename
, ".tbss_[UL]");
33789 fputs ("\t.file\t", asm_out_file
);
33790 output_quoted_string (asm_out_file
, main_input_filename
);
33791 fputc ('\n', asm_out_file
);
33792 if (write_symbols
!= NO_DEBUG
)
33793 switch_to_section (private_data_section
);
33794 switch_to_section (toc_section
);
33795 switch_to_section (text_section
);
33797 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
33798 rs6000_file_start ();
33801 /* Output at end of assembler file.
33802 On the RS/6000, referencing data should automatically pull in text. */
33805 rs6000_xcoff_file_end (void)
33807 switch_to_section (text_section
);
33808 fputs ("_section_.text:\n", asm_out_file
);
33809 switch_to_section (data_section
);
33810 fputs (TARGET_32BIT
33811 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33815 struct declare_alias_data
33818 bool function_descriptor
;
33821 /* Declare alias N. A helper function for for_node_and_aliases. */
33824 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
33826 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
33827 /* Main symbol is output specially, because varasm machinery does part of
33828 the job for us - we do not need to declare .globl/lglobs and such. */
33829 if (!n
->alias
|| n
->weakref
)
33832 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
33835 /* Prevent assemble_alias from trying to use .set pseudo operation
33836 that does not behave as expected by the middle-end. */
33837 TREE_ASM_WRITTEN (n
->decl
) = true;
33839 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
33840 char *buffer
= (char *) alloca (strlen (name
) + 2);
33842 int dollar_inside
= 0;
33844 strcpy (buffer
, name
);
33845 p
= strchr (buffer
, '$');
33849 p
= strchr (p
+ 1, '$');
33851 if (TREE_PUBLIC (n
->decl
))
33853 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
33855 if (dollar_inside
) {
33856 if (data
->function_descriptor
)
33857 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33858 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33860 if (data
->function_descriptor
)
33862 fputs ("\t.globl .", data
->file
);
33863 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33864 putc ('\n', data
->file
);
33866 fputs ("\t.globl ", data
->file
);
33867 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33868 putc ('\n', data
->file
);
33870 #ifdef ASM_WEAKEN_DECL
33871 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
33872 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
33879 if (data
->function_descriptor
)
33880 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33881 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33883 if (data
->function_descriptor
)
33885 fputs ("\t.lglobl .", data
->file
);
33886 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33887 putc ('\n', data
->file
);
33889 fputs ("\t.lglobl ", data
->file
);
33890 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33891 putc ('\n', data
->file
);
33893 if (data
->function_descriptor
)
33894 fputs (".", data
->file
);
33895 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33896 fputs (":\n", data
->file
);
33901 #ifdef HAVE_GAS_HIDDEN
33902 /* Helper function to calculate visibility of a DECL
33903 and return the value as a const string. */
33905 static const char *
33906 rs6000_xcoff_visibility (tree decl
)
33908 static const char * const visibility_types
[] = {
33909 "", ",protected", ",hidden", ",internal"
33912 enum symbol_visibility vis
= DECL_VISIBILITY (decl
);
33914 if (TREE_CODE (decl
) == FUNCTION_DECL
33915 && cgraph_node::get (decl
)
33916 && cgraph_node::get (decl
)->instrumentation_clone
33917 && cgraph_node::get (decl
)->instrumented_version
)
33918 vis
= DECL_VISIBILITY (cgraph_node::get (decl
)->instrumented_version
->decl
);
33920 return visibility_types
[vis
];
33925 /* This macro produces the initial definition of a function name.
33926 On the RS/6000, we need to place an extra '.' in the function name and
33927 output the function descriptor.
33928 Dollar signs are converted to underscores.
33930 The csect for the function will have already been created when
33931 text_section was selected. We do have to go back to that csect, however.
33933 The third and fourth parameters to the .function pseudo-op (16 and 044)
33934 are placeholders which no longer have any use.
33936 Because AIX assembler's .set command has unexpected semantics, we output
33937 all aliases as alternative labels in front of the definition. */
33940 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
33942 char *buffer
= (char *) alloca (strlen (name
) + 1);
33944 int dollar_inside
= 0;
33945 struct declare_alias_data data
= {file
, false};
33947 strcpy (buffer
, name
);
33948 p
= strchr (buffer
, '$');
33952 p
= strchr (p
+ 1, '$');
33954 if (TREE_PUBLIC (decl
))
33956 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
33958 if (dollar_inside
) {
33959 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33960 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33962 fputs ("\t.globl .", file
);
33963 RS6000_OUTPUT_BASENAME (file
, buffer
);
33964 #ifdef HAVE_GAS_HIDDEN
33965 fputs (rs6000_xcoff_visibility (decl
), file
);
33972 if (dollar_inside
) {
33973 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33974 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33976 fputs ("\t.lglobl .", file
);
33977 RS6000_OUTPUT_BASENAME (file
, buffer
);
33980 fputs ("\t.csect ", file
);
33981 RS6000_OUTPUT_BASENAME (file
, buffer
);
33982 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
33983 RS6000_OUTPUT_BASENAME (file
, buffer
);
33984 fputs (":\n", file
);
33985 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
33987 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
33988 RS6000_OUTPUT_BASENAME (file
, buffer
);
33989 fputs (", TOC[tc0], 0\n", file
);
33991 switch_to_section (function_section (decl
));
33993 RS6000_OUTPUT_BASENAME (file
, buffer
);
33994 fputs (":\n", file
);
33995 data
.function_descriptor
= true;
33996 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
33998 if (!DECL_IGNORED_P (decl
))
34000 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
34001 xcoffout_declare_function (file
, decl
, buffer
);
34002 else if (write_symbols
== DWARF2_DEBUG
)
34004 name
= (*targetm
.strip_name_encoding
) (name
);
34005 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
34012 /* Output assembly language to globalize a symbol from a DECL,
34013 possibly with visibility. */
34016 rs6000_xcoff_asm_globalize_decl_name (FILE *stream
, tree decl
)
34018 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
34019 fputs (GLOBAL_ASM_OP
, stream
);
34020 RS6000_OUTPUT_BASENAME (stream
, name
);
34021 #ifdef HAVE_GAS_HIDDEN
34022 fputs (rs6000_xcoff_visibility (decl
), stream
);
34024 putc ('\n', stream
);
34027 /* Output assembly language to define a symbol as COMMON from a DECL,
34028 possibly with visibility. */
34031 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream
,
34032 tree decl ATTRIBUTE_UNUSED
,
34034 unsigned HOST_WIDE_INT size
,
34035 unsigned HOST_WIDE_INT align
)
34037 unsigned HOST_WIDE_INT align2
= 2;
34040 align2
= floor_log2 (align
/ BITS_PER_UNIT
);
34044 fputs (COMMON_ASM_OP
, stream
);
34045 RS6000_OUTPUT_BASENAME (stream
, name
);
34048 "," HOST_WIDE_INT_PRINT_UNSIGNED
"," HOST_WIDE_INT_PRINT_UNSIGNED
,
34051 #ifdef HAVE_GAS_HIDDEN
34052 fputs (rs6000_xcoff_visibility (decl
), stream
);
34054 putc ('\n', stream
);
34057 /* This macro produces the initial definition of a object (variable) name.
34058 Because AIX assembler's .set command has unexpected semantics, we output
34059 all aliases as alternative labels in front of the definition. */
34062 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
34064 struct declare_alias_data data
= {file
, false};
34065 RS6000_OUTPUT_BASENAME (file
, name
);
34066 fputs (":\n", file
);
34067 symtab_node::get_create (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34071 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34074 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
34076 fputs (integer_asm_op (size
, FALSE
), file
);
34077 assemble_name (file
, label
);
34078 fputs ("-$", file
);
34081 /* Output a symbol offset relative to the dbase for the current object.
34082 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34085 __gcc_unwind_dbase is embedded in all executables/libraries through
34086 libgcc/config/rs6000/crtdbase.S. */
34089 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
34091 fputs (integer_asm_op (size
, FALSE
), file
);
34092 assemble_name (file
, label
);
34093 fputs("-__gcc_unwind_dbase", file
);
34098 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
34102 const char *symname
;
34104 default_encode_section_info (decl
, rtl
, first
);
34106 /* Careful not to prod global register variables. */
34109 symbol
= XEXP (rtl
, 0);
34110 if (GET_CODE (symbol
) != SYMBOL_REF
)
34113 flags
= SYMBOL_REF_FLAGS (symbol
);
34115 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
34116 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
34118 SYMBOL_REF_FLAGS (symbol
) = flags
;
34120 /* Append mapping class to extern decls. */
34121 symname
= XSTR (symbol
, 0);
34122 if (decl
/* sync condition with assemble_external () */
34123 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
34124 && ((TREE_CODE (decl
) == VAR_DECL
&& !DECL_THREAD_LOCAL_P (decl
))
34125 || TREE_CODE (decl
) == FUNCTION_DECL
)
34126 && symname
[strlen (symname
) - 1] != ']')
34128 char *newname
= (char *) alloca (strlen (symname
) + 5);
34129 strcpy (newname
, symname
);
34130 strcat (newname
, (TREE_CODE (decl
) == FUNCTION_DECL
34131 ? "[DS]" : "[UA]"));
34132 XSTR (symbol
, 0) = ggc_strdup (newname
);
34135 #endif /* HAVE_AS_TLS */
34136 #endif /* TARGET_XCOFF */
34139 rs6000_asm_weaken_decl (FILE *stream
, tree decl
,
34140 const char *name
, const char *val
)
34142 fputs ("\t.weak\t", stream
);
34143 RS6000_OUTPUT_BASENAME (stream
, name
);
34144 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
34145 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
34148 fputs ("[DS]", stream
);
34149 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34151 fputs (rs6000_xcoff_visibility (decl
), stream
);
34153 fputs ("\n\t.weak\t.", stream
);
34154 RS6000_OUTPUT_BASENAME (stream
, name
);
34156 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34158 fputs (rs6000_xcoff_visibility (decl
), stream
);
34160 fputc ('\n', stream
);
34163 #ifdef ASM_OUTPUT_DEF
34164 ASM_OUTPUT_DEF (stream
, name
, val
);
34166 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
34167 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
34169 fputs ("\t.set\t.", stream
);
34170 RS6000_OUTPUT_BASENAME (stream
, name
);
34171 fputs (",.", stream
);
34172 RS6000_OUTPUT_BASENAME (stream
, val
);
34173 fputc ('\n', stream
);
34179 /* Return true if INSN should not be copied. */
34182 rs6000_cannot_copy_insn_p (rtx_insn
*insn
)
34184 return recog_memoized (insn
) >= 0
34185 && get_attr_cannot_copy (insn
);
34188 /* Compute a (partial) cost for rtx X. Return true if the complete
34189 cost has been computed, and false if subexpressions should be
34190 scanned. In either case, *TOTAL contains the cost result. */
34193 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34194 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
34196 int code
= GET_CODE (x
);
34200 /* On the RS/6000, if it is valid in the insn, it is free. */
34202 if (((outer_code
== SET
34203 || outer_code
== PLUS
34204 || outer_code
== MINUS
)
34205 && (satisfies_constraint_I (x
)
34206 || satisfies_constraint_L (x
)))
34207 || (outer_code
== AND
34208 && (satisfies_constraint_K (x
)
34210 ? satisfies_constraint_L (x
)
34211 : satisfies_constraint_J (x
))))
34212 || ((outer_code
== IOR
|| outer_code
== XOR
)
34213 && (satisfies_constraint_K (x
)
34215 ? satisfies_constraint_L (x
)
34216 : satisfies_constraint_J (x
))))
34217 || outer_code
== ASHIFT
34218 || outer_code
== ASHIFTRT
34219 || outer_code
== LSHIFTRT
34220 || outer_code
== ROTATE
34221 || outer_code
== ROTATERT
34222 || outer_code
== ZERO_EXTRACT
34223 || (outer_code
== MULT
34224 && satisfies_constraint_I (x
))
34225 || ((outer_code
== DIV
|| outer_code
== UDIV
34226 || outer_code
== MOD
|| outer_code
== UMOD
)
34227 && exact_log2 (INTVAL (x
)) >= 0)
34228 || (outer_code
== COMPARE
34229 && (satisfies_constraint_I (x
)
34230 || satisfies_constraint_K (x
)))
34231 || ((outer_code
== EQ
|| outer_code
== NE
)
34232 && (satisfies_constraint_I (x
)
34233 || satisfies_constraint_K (x
)
34235 ? satisfies_constraint_L (x
)
34236 : satisfies_constraint_J (x
))))
34237 || (outer_code
== GTU
34238 && satisfies_constraint_I (x
))
34239 || (outer_code
== LTU
34240 && satisfies_constraint_P (x
)))
34245 else if ((outer_code
== PLUS
34246 && reg_or_add_cint_operand (x
, VOIDmode
))
34247 || (outer_code
== MINUS
34248 && reg_or_sub_cint_operand (x
, VOIDmode
))
34249 || ((outer_code
== SET
34250 || outer_code
== IOR
34251 || outer_code
== XOR
)
34253 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
34255 *total
= COSTS_N_INSNS (1);
34261 case CONST_WIDE_INT
:
34265 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34269 /* When optimizing for size, MEM should be slightly more expensive
34270 than generating address, e.g., (plus (reg) (const)).
34271 L1 cache latency is about two instructions. */
34272 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34273 if (SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (x
)))
34274 *total
+= COSTS_N_INSNS (100);
34283 if (FLOAT_MODE_P (mode
))
34284 *total
= rs6000_cost
->fp
;
34286 *total
= COSTS_N_INSNS (1);
34290 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
34291 && satisfies_constraint_I (XEXP (x
, 1)))
34293 if (INTVAL (XEXP (x
, 1)) >= -256
34294 && INTVAL (XEXP (x
, 1)) <= 255)
34295 *total
= rs6000_cost
->mulsi_const9
;
34297 *total
= rs6000_cost
->mulsi_const
;
34299 else if (mode
== SFmode
)
34300 *total
= rs6000_cost
->fp
;
34301 else if (FLOAT_MODE_P (mode
))
34302 *total
= rs6000_cost
->dmul
;
34303 else if (mode
== DImode
)
34304 *total
= rs6000_cost
->muldi
;
34306 *total
= rs6000_cost
->mulsi
;
34310 if (mode
== SFmode
)
34311 *total
= rs6000_cost
->fp
;
34313 *total
= rs6000_cost
->dmul
;
34318 if (FLOAT_MODE_P (mode
))
34320 *total
= mode
== DFmode
? rs6000_cost
->ddiv
34321 : rs6000_cost
->sdiv
;
34328 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
34329 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
34331 if (code
== DIV
|| code
== MOD
)
34333 *total
= COSTS_N_INSNS (2);
34336 *total
= COSTS_N_INSNS (1);
34340 if (GET_MODE (XEXP (x
, 1)) == DImode
)
34341 *total
= rs6000_cost
->divdi
;
34343 *total
= rs6000_cost
->divsi
;
34345 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34346 if (!TARGET_MODULO
&& (code
== MOD
|| code
== UMOD
))
34347 *total
+= COSTS_N_INSNS (2);
34351 *total
= COSTS_N_INSNS (TARGET_CTZ
? 1 : 4);
34355 *total
= COSTS_N_INSNS (4);
34359 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
34363 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
34367 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
34370 *total
= COSTS_N_INSNS (1);
34374 if (CONST_INT_P (XEXP (x
, 1)))
34376 rtx left
= XEXP (x
, 0);
34377 rtx_code left_code
= GET_CODE (left
);
34379 /* rotate-and-mask: 1 insn. */
34380 if ((left_code
== ROTATE
34381 || left_code
== ASHIFT
34382 || left_code
== LSHIFTRT
)
34383 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
34385 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
34386 if (!CONST_INT_P (XEXP (left
, 1)))
34387 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
34388 *total
+= COSTS_N_INSNS (1);
34392 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34393 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
34394 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
34395 || (val
& 0xffff) == val
34396 || (val
& 0xffff0000) == val
34397 || ((val
& 0xffff) == 0 && mode
== SImode
))
34399 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34400 *total
+= COSTS_N_INSNS (1);
34405 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
34407 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34408 *total
+= COSTS_N_INSNS (2);
34413 *total
= COSTS_N_INSNS (1);
34418 *total
= COSTS_N_INSNS (1);
34424 *total
= COSTS_N_INSNS (1);
34428 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34429 the sign extend and shift separately within the insn. */
34430 if (TARGET_EXTSWSLI
&& mode
== DImode
34431 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
34432 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
34443 /* Handle mul_highpart. */
34444 if (outer_code
== TRUNCATE
34445 && GET_CODE (XEXP (x
, 0)) == MULT
)
34447 if (mode
== DImode
)
34448 *total
= rs6000_cost
->muldi
;
34450 *total
= rs6000_cost
->mulsi
;
34453 else if (outer_code
== AND
)
34456 *total
= COSTS_N_INSNS (1);
34461 if (GET_CODE (XEXP (x
, 0)) == MEM
)
34464 *total
= COSTS_N_INSNS (1);
34470 if (!FLOAT_MODE_P (mode
))
34472 *total
= COSTS_N_INSNS (1);
34478 case UNSIGNED_FLOAT
:
34481 case FLOAT_TRUNCATE
:
34482 *total
= rs6000_cost
->fp
;
34486 if (mode
== DFmode
)
34487 *total
= rs6000_cost
->sfdf_convert
;
34489 *total
= rs6000_cost
->fp
;
34493 switch (XINT (x
, 1))
34496 *total
= rs6000_cost
->fp
;
34508 *total
= COSTS_N_INSNS (1);
34511 else if (FLOAT_MODE_P (mode
) && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
)
34513 *total
= rs6000_cost
->fp
;
34522 /* Carry bit requires mode == Pmode.
34523 NEG or PLUS already counted so only add one. */
34525 && (outer_code
== NEG
|| outer_code
== PLUS
))
34527 *total
= COSTS_N_INSNS (1);
34530 if (outer_code
== SET
)
34532 if (XEXP (x
, 1) == const0_rtx
)
34534 if (TARGET_ISEL
&& !TARGET_MFCRF
)
34535 *total
= COSTS_N_INSNS (8);
34537 *total
= COSTS_N_INSNS (2);
34542 *total
= COSTS_N_INSNS (3);
34551 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
34553 if (TARGET_ISEL
&& !TARGET_MFCRF
)
34554 *total
= COSTS_N_INSNS (8);
34556 *total
= COSTS_N_INSNS (2);
34560 if (outer_code
== COMPARE
)
34574 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34577 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34578 int opno
, int *total
, bool speed
)
34580 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
34583 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34584 "opno = %d, total = %d, speed = %s, x:\n",
34585 ret
? "complete" : "scan inner",
34586 GET_MODE_NAME (mode
),
34587 GET_RTX_NAME (outer_code
),
34590 speed
? "true" : "false");
34597 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34600 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
34601 addr_space_t as
, bool speed
)
34603 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
34605 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34606 ret
, speed
? "true" : "false");
34613 /* A C expression returning the cost of moving data from a register of class
34614 CLASS1 to one of CLASS2. */
34617 rs6000_register_move_cost (machine_mode mode
,
34618 reg_class_t from
, reg_class_t to
)
34622 if (TARGET_DEBUG_COST
)
34625 /* Moves from/to GENERAL_REGS. */
34626 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
34627 || reg_classes_intersect_p (from
, GENERAL_REGS
))
34629 reg_class_t rclass
= from
;
34631 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
34634 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
34635 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
34636 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
34638 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34640 else if (rclass
== CR_REGS
)
34643 /* For those processors that have slow LR/CTR moves, make them more
34644 expensive than memory in order to bias spills to memory .*/
34645 else if ((rs6000_cpu
== PROCESSOR_POWER6
34646 || rs6000_cpu
== PROCESSOR_POWER7
34647 || rs6000_cpu
== PROCESSOR_POWER8
34648 || rs6000_cpu
== PROCESSOR_POWER9
)
34649 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
34650 ret
= 6 * hard_regno_nregs
[0][mode
];
34653 /* A move will cost one instruction per GPR moved. */
34654 ret
= 2 * hard_regno_nregs
[0][mode
];
34657 /* If we have VSX, we can easily move between FPR or Altivec registers. */
34658 else if (VECTOR_MEM_VSX_P (mode
)
34659 && reg_classes_intersect_p (to
, VSX_REGS
)
34660 && reg_classes_intersect_p (from
, VSX_REGS
))
34661 ret
= 2 * hard_regno_nregs
[FIRST_FPR_REGNO
][mode
];
34663 /* Moving between two similar registers is just one instruction. */
34664 else if (reg_classes_intersect_p (to
, from
))
34665 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
34667 /* Everything else has to go through GENERAL_REGS. */
34669 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
34670 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
34672 if (TARGET_DEBUG_COST
)
34674 if (dbg_cost_ctrl
== 1)
34676 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
34677 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
34678 reg_class_names
[to
]);
34685 /* A C expressions returning the cost of moving data of MODE from a register to
34689 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
34690 bool in ATTRIBUTE_UNUSED
)
34694 if (TARGET_DEBUG_COST
)
34697 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
34698 ret
= 4 * hard_regno_nregs
[0][mode
];
34699 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
34700 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
34701 ret
= 4 * hard_regno_nregs
[32][mode
];
34702 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
34703 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
34705 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
34707 if (TARGET_DEBUG_COST
)
34709 if (dbg_cost_ctrl
== 1)
34711 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34712 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
34719 /* Returns a code for a target-specific builtin that implements
34720 reciprocal of the function, or NULL_TREE if not available. */
34723 rs6000_builtin_reciprocal (tree fndecl
)
34725 switch (DECL_FUNCTION_CODE (fndecl
))
34727 case VSX_BUILTIN_XVSQRTDP
:
34728 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
34731 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
34733 case VSX_BUILTIN_XVSQRTSP
:
34734 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
34737 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
34744 /* Load up a constant. If the mode is a vector mode, splat the value across
34745 all of the vector elements. */
34748 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
34752 if (mode
== SFmode
|| mode
== DFmode
)
34754 rtx d
= const_double_from_real_value (dconst
, mode
);
34755 reg
= force_reg (mode
, d
);
34757 else if (mode
== V4SFmode
)
34759 rtx d
= const_double_from_real_value (dconst
, SFmode
);
34760 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
34761 reg
= gen_reg_rtx (mode
);
34762 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
34764 else if (mode
== V2DFmode
)
34766 rtx d
= const_double_from_real_value (dconst
, DFmode
);
34767 rtvec v
= gen_rtvec (2, d
, d
);
34768 reg
= gen_reg_rtx (mode
);
34769 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
34772 gcc_unreachable ();
34777 /* Generate an FMA instruction. */
34780 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
34782 machine_mode mode
= GET_MODE (target
);
34785 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
34786 gcc_assert (dst
!= NULL
);
34789 emit_move_insn (target
, dst
);
34792 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34795 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
34797 machine_mode mode
= GET_MODE (dst
);
34800 /* This is a tad more complicated, since the fnma_optab is for
34801 a different expression: fma(-m1, m2, a), which is the same
34802 thing except in the case of signed zeros.
34804 Fortunately we know that if FMA is supported that FNMSUB is
34805 also supported in the ISA. Just expand it directly. */
34807 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
34809 r
= gen_rtx_NEG (mode
, a
);
34810 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
34811 r
= gen_rtx_NEG (mode
, r
);
34812 emit_insn (gen_rtx_SET (dst
, r
));
34815 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34816 add a reg_note saying that this was a division. Support both scalar and
34817 vector divide. Assumes no trapping math and finite arguments. */
34820 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
34822 machine_mode mode
= GET_MODE (dst
);
34823 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
34826 /* Low precision estimates guarantee 5 bits of accuracy. High
34827 precision estimates guarantee 14 bits of accuracy. SFmode
34828 requires 23 bits of accuracy. DFmode requires 52 bits of
34829 accuracy. Each pass at least doubles the accuracy, leading
34830 to the following. */
34831 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
34832 if (mode
== DFmode
|| mode
== V2DFmode
)
34835 enum insn_code code
= optab_handler (smul_optab
, mode
);
34836 insn_gen_fn gen_mul
= GEN_FCN (code
);
34838 gcc_assert (code
!= CODE_FOR_nothing
);
34840 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
34842 /* x0 = 1./d estimate */
34843 x0
= gen_reg_rtx (mode
);
34844 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
34847 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34850 /* e0 = 1. - d * x0 */
34851 e0
= gen_reg_rtx (mode
);
34852 rs6000_emit_nmsub (e0
, d
, x0
, one
);
34854 /* x1 = x0 + e0 * x0 */
34855 x1
= gen_reg_rtx (mode
);
34856 rs6000_emit_madd (x1
, e0
, x0
, x0
);
34858 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
34859 ++i
, xprev
= xnext
, eprev
= enext
) {
34861 /* enext = eprev * eprev */
34862 enext
= gen_reg_rtx (mode
);
34863 emit_insn (gen_mul (enext
, eprev
, eprev
));
34865 /* xnext = xprev + enext * xprev */
34866 xnext
= gen_reg_rtx (mode
);
34867 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
34873 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34875 /* u = n * xprev */
34876 u
= gen_reg_rtx (mode
);
34877 emit_insn (gen_mul (u
, n
, xprev
));
34879 /* v = n - (d * u) */
34880 v
= gen_reg_rtx (mode
);
34881 rs6000_emit_nmsub (v
, d
, u
, n
);
34883 /* dst = (v * xprev) + u */
34884 rs6000_emit_madd (dst
, v
, xprev
, u
);
34887 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
34890 /* Goldschmidt's Algorithm for single/double-precision floating point
34891 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34894 rs6000_emit_swsqrt (rtx dst
, rtx src
, bool recip
)
34896 machine_mode mode
= GET_MODE (src
);
34897 rtx e
= gen_reg_rtx (mode
);
34898 rtx g
= gen_reg_rtx (mode
);
34899 rtx h
= gen_reg_rtx (mode
);
34901 /* Low precision estimates guarantee 5 bits of accuracy. High
34902 precision estimates guarantee 14 bits of accuracy. SFmode
34903 requires 23 bits of accuracy. DFmode requires 52 bits of
34904 accuracy. Each pass at least doubles the accuracy, leading
34905 to the following. */
34906 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
34907 if (mode
== DFmode
|| mode
== V2DFmode
)
34912 enum insn_code code
= optab_handler (smul_optab
, mode
);
34913 insn_gen_fn gen_mul
= GEN_FCN (code
);
34915 gcc_assert (code
!= CODE_FOR_nothing
);
34917 mhalf
= rs6000_load_constant_and_splat (mode
, dconsthalf
);
34919 /* e = rsqrt estimate */
34920 emit_insn (gen_rtx_SET (e
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
34923 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
34926 rtx zero
= force_reg (mode
, CONST0_RTX (mode
));
34928 if (mode
== SFmode
)
34930 rtx target
= emit_conditional_move (e
, GT
, src
, zero
, mode
,
34933 emit_move_insn (e
, target
);
34937 rtx cond
= gen_rtx_GT (VOIDmode
, e
, zero
);
34938 rs6000_emit_vector_cond_expr (e
, e
, zero
, cond
, src
, zero
);
34942 /* g = sqrt estimate. */
34943 emit_insn (gen_mul (g
, e
, src
));
34944 /* h = 1/(2*sqrt) estimate. */
34945 emit_insn (gen_mul (h
, e
, mhalf
));
34951 rtx t
= gen_reg_rtx (mode
);
34952 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
34953 /* Apply correction directly to 1/rsqrt estimate. */
34954 rs6000_emit_madd (dst
, e
, t
, e
);
34958 for (i
= 0; i
< passes
; i
++)
34960 rtx t1
= gen_reg_rtx (mode
);
34961 rtx g1
= gen_reg_rtx (mode
);
34962 rtx h1
= gen_reg_rtx (mode
);
34964 rs6000_emit_nmsub (t1
, g
, h
, mhalf
);
34965 rs6000_emit_madd (g1
, g
, t1
, g
);
34966 rs6000_emit_madd (h1
, h
, t1
, h
);
34971 /* Multiply by 2 for 1/rsqrt. */
34972 emit_insn (gen_add3_insn (dst
, h
, h
));
34977 rtx t
= gen_reg_rtx (mode
);
34978 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
34979 rs6000_emit_madd (dst
, g
, t
, g
);
34985 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
34986 (Power7) targets. DST is the target, and SRC is the argument operand. */
34989 rs6000_emit_popcount (rtx dst
, rtx src
)
34991 machine_mode mode
= GET_MODE (dst
);
34994 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
34995 if (TARGET_POPCNTD
)
34997 if (mode
== SImode
)
34998 emit_insn (gen_popcntdsi2 (dst
, src
));
35000 emit_insn (gen_popcntddi2 (dst
, src
));
35004 tmp1
= gen_reg_rtx (mode
);
35006 if (mode
== SImode
)
35008 emit_insn (gen_popcntbsi2 (tmp1
, src
));
35009 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
35011 tmp2
= force_reg (SImode
, tmp2
);
35012 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
35016 emit_insn (gen_popcntbdi2 (tmp1
, src
));
35017 tmp2
= expand_mult (DImode
, tmp1
,
35018 GEN_INT ((HOST_WIDE_INT
)
35019 0x01010101 << 32 | 0x01010101),
35021 tmp2
= force_reg (DImode
, tmp2
);
35022 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
35027 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35028 target, and SRC is the argument operand. */
35031 rs6000_emit_parity (rtx dst
, rtx src
)
35033 machine_mode mode
= GET_MODE (dst
);
35036 tmp
= gen_reg_rtx (mode
);
35038 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35041 if (mode
== SImode
)
35043 emit_insn (gen_popcntbsi2 (tmp
, src
));
35044 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
35048 emit_insn (gen_popcntbdi2 (tmp
, src
));
35049 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
35054 if (mode
== SImode
)
35056 /* Is mult+shift >= shift+xor+shift+xor? */
35057 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
35059 rtx tmp1
, tmp2
, tmp3
, tmp4
;
35061 tmp1
= gen_reg_rtx (SImode
);
35062 emit_insn (gen_popcntbsi2 (tmp1
, src
));
35064 tmp2
= gen_reg_rtx (SImode
);
35065 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
35066 tmp3
= gen_reg_rtx (SImode
);
35067 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
35069 tmp4
= gen_reg_rtx (SImode
);
35070 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
35071 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
35074 rs6000_emit_popcount (tmp
, src
);
35075 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
35079 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35080 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
35082 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
35084 tmp1
= gen_reg_rtx (DImode
);
35085 emit_insn (gen_popcntbdi2 (tmp1
, src
));
35087 tmp2
= gen_reg_rtx (DImode
);
35088 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
35089 tmp3
= gen_reg_rtx (DImode
);
35090 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
35092 tmp4
= gen_reg_rtx (DImode
);
35093 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
35094 tmp5
= gen_reg_rtx (DImode
);
35095 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
35097 tmp6
= gen_reg_rtx (DImode
);
35098 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
35099 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
35102 rs6000_emit_popcount (tmp
, src
);
35103 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
35107 /* Expand an Altivec constant permutation for little endian mode.
35108 There are two issues: First, the two input operands must be
35109 swapped so that together they form a double-wide array in LE
35110 order. Second, the vperm instruction has surprising behavior
35111 in LE mode: it interprets the elements of the source vectors
35112 in BE mode ("left to right") and interprets the elements of
35113 the destination vector in LE mode ("right to left"). To
35114 correct for this, we must subtract each element of the permute
35115 control vector from 31.
35117 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35118 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35119 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35120 serve as the permute control vector. Then, in BE mode,
35124 places the desired result in vr9. However, in LE mode the
35125 vector contents will be
35127 vr10 = 00000003 00000002 00000001 00000000
35128 vr11 = 00000007 00000006 00000005 00000004
35130 The result of the vperm using the same permute control vector is
35132 vr9 = 05000000 07000000 01000000 03000000
35134 That is, the leftmost 4 bytes of vr10 are interpreted as the
35135 source for the rightmost 4 bytes of vr9, and so on.
35137 If we change the permute control vector to
35139 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35147 vr9 = 00000006 00000004 00000002 00000000. */
35150 altivec_expand_vec_perm_const_le (rtx operands
[4])
35154 rtx constv
, unspec
;
35155 rtx target
= operands
[0];
35156 rtx op0
= operands
[1];
35157 rtx op1
= operands
[2];
35158 rtx sel
= operands
[3];
35160 /* Unpack and adjust the constant selector. */
35161 for (i
= 0; i
< 16; ++i
)
35163 rtx e
= XVECEXP (sel
, 0, i
);
35164 unsigned int elt
= 31 - (INTVAL (e
) & 31);
35165 perm
[i
] = GEN_INT (elt
);
35168 /* Expand to a permute, swapping the inputs and using the
35169 adjusted selector. */
35171 op0
= force_reg (V16QImode
, op0
);
35173 op1
= force_reg (V16QImode
, op1
);
35175 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
35176 constv
= force_reg (V16QImode
, constv
);
35177 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
35179 if (!REG_P (target
))
35181 rtx tmp
= gen_reg_rtx (V16QImode
);
35182 emit_move_insn (tmp
, unspec
);
35186 emit_move_insn (target
, unspec
);
35189 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35190 permute control vector. But here it's not a constant, so we must
35191 generate a vector NAND or NOR to do the adjustment. */
35194 altivec_expand_vec_perm_le (rtx operands
[4])
35196 rtx notx
, iorx
, unspec
;
35197 rtx target
= operands
[0];
35198 rtx op0
= operands
[1];
35199 rtx op1
= operands
[2];
35200 rtx sel
= operands
[3];
35202 rtx norreg
= gen_reg_rtx (V16QImode
);
35203 machine_mode mode
= GET_MODE (target
);
35205 /* Get everything in regs so the pattern matches. */
35207 op0
= force_reg (mode
, op0
);
35209 op1
= force_reg (mode
, op1
);
35211 sel
= force_reg (V16QImode
, sel
);
35212 if (!REG_P (target
))
35213 tmp
= gen_reg_rtx (mode
);
35215 if (TARGET_P9_VECTOR
)
35217 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op0
, op1
, sel
),
35222 /* Invert the selector with a VNAND if available, else a VNOR.
35223 The VNAND is preferred for future fusion opportunities. */
35224 notx
= gen_rtx_NOT (V16QImode
, sel
);
35225 iorx
= (TARGET_P8_VECTOR
35226 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
35227 : gen_rtx_AND (V16QImode
, notx
, notx
));
35228 emit_insn (gen_rtx_SET (norreg
, iorx
));
35230 /* Permute with operands reversed and adjusted selector. */
35231 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
35235 /* Copy into target, possibly by way of a register. */
35236 if (!REG_P (target
))
35238 emit_move_insn (tmp
, unspec
);
35242 emit_move_insn (target
, unspec
);
35245 /* Expand an Altivec constant permutation. Return true if we match
35246 an efficient implementation; false to fall back to VPERM. */
35249 altivec_expand_vec_perm_const (rtx operands
[4])
35251 struct altivec_perm_insn
{
35252 HOST_WIDE_INT mask
;
35253 enum insn_code impl
;
35254 unsigned char perm
[16];
35256 static const struct altivec_perm_insn patterns
[] = {
35257 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
35258 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35259 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
35260 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35261 { OPTION_MASK_ALTIVEC
,
35262 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
35263 : CODE_FOR_altivec_vmrglb_direct
),
35264 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35265 { OPTION_MASK_ALTIVEC
,
35266 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
35267 : CODE_FOR_altivec_vmrglh_direct
),
35268 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35269 { OPTION_MASK_ALTIVEC
,
35270 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
35271 : CODE_FOR_altivec_vmrglw_direct
),
35272 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35273 { OPTION_MASK_ALTIVEC
,
35274 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
35275 : CODE_FOR_altivec_vmrghb_direct
),
35276 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35277 { OPTION_MASK_ALTIVEC
,
35278 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
35279 : CODE_FOR_altivec_vmrghh_direct
),
35280 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35281 { OPTION_MASK_ALTIVEC
,
35282 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
35283 : CODE_FOR_altivec_vmrghw_direct
),
35284 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35285 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew_v4si
,
35286 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35287 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
35288 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35291 unsigned int i
, j
, elt
, which
;
35292 unsigned char perm
[16];
35293 rtx target
, op0
, op1
, sel
, x
;
35296 target
= operands
[0];
35301 /* Unpack the constant selector. */
35302 for (i
= which
= 0; i
< 16; ++i
)
35304 rtx e
= XVECEXP (sel
, 0, i
);
35305 elt
= INTVAL (e
) & 31;
35306 which
|= (elt
< 16 ? 1 : 2);
35310 /* Simplify the constant selector based on operands. */
35314 gcc_unreachable ();
35318 if (!rtx_equal_p (op0
, op1
))
35323 for (i
= 0; i
< 16; ++i
)
35335 /* Look for splat patterns. */
35340 for (i
= 0; i
< 16; ++i
)
35341 if (perm
[i
] != elt
)
35345 if (!BYTES_BIG_ENDIAN
)
35347 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
35353 for (i
= 0; i
< 16; i
+= 2)
35354 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
35358 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
35359 x
= gen_reg_rtx (V8HImode
);
35360 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
35362 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35369 for (i
= 0; i
< 16; i
+= 4)
35371 || perm
[i
+ 1] != elt
+ 1
35372 || perm
[i
+ 2] != elt
+ 2
35373 || perm
[i
+ 3] != elt
+ 3)
35377 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
35378 x
= gen_reg_rtx (V4SImode
);
35379 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
35381 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35387 /* Look for merge and pack patterns. */
35388 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
35392 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
35395 elt
= patterns
[j
].perm
[0];
35396 if (perm
[0] == elt
)
35398 else if (perm
[0] == elt
+ 16)
35402 for (i
= 1; i
< 16; ++i
)
35404 elt
= patterns
[j
].perm
[i
];
35406 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
35407 else if (one_vec
&& elt
>= 16)
35409 if (perm
[i
] != elt
)
35414 enum insn_code icode
= patterns
[j
].impl
;
35415 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
35416 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
35418 /* For little-endian, don't use vpkuwum and vpkuhum if the
35419 underlying vector type is not V4SI and V8HI, respectively.
35420 For example, using vpkuwum with a V8HI picks up the even
35421 halfwords (BE numbering) when the even halfwords (LE
35422 numbering) are what we need. */
35423 if (!BYTES_BIG_ENDIAN
35424 && icode
== CODE_FOR_altivec_vpkuwum_direct
35425 && ((GET_CODE (op0
) == REG
35426 && GET_MODE (op0
) != V4SImode
)
35427 || (GET_CODE (op0
) == SUBREG
35428 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
35430 if (!BYTES_BIG_ENDIAN
35431 && icode
== CODE_FOR_altivec_vpkuhum_direct
35432 && ((GET_CODE (op0
) == REG
35433 && GET_MODE (op0
) != V8HImode
)
35434 || (GET_CODE (op0
) == SUBREG
35435 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
35438 /* For little-endian, the two input operands must be swapped
35439 (or swapped back) to ensure proper right-to-left numbering
35441 if (swapped
^ !BYTES_BIG_ENDIAN
)
35442 std::swap (op0
, op1
);
35443 if (imode
!= V16QImode
)
35445 op0
= gen_lowpart (imode
, op0
);
35446 op1
= gen_lowpart (imode
, op1
);
35448 if (omode
== V16QImode
)
35451 x
= gen_reg_rtx (omode
);
35452 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
35453 if (omode
!= V16QImode
)
35454 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35459 if (!BYTES_BIG_ENDIAN
)
35461 altivec_expand_vec_perm_const_le (operands
);
35468 /* Expand a Paired Single or VSX Permute Doubleword constant permutation.
35469 Return true if we match an efficient implementation. */
35472 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
35473 unsigned char perm0
, unsigned char perm1
)
35477 /* If both selectors come from the same operand, fold to single op. */
35478 if ((perm0
& 2) == (perm1
& 2))
35485 /* If both operands are equal, fold to simpler permutation. */
35486 if (rtx_equal_p (op0
, op1
))
35489 perm1
= (perm1
& 1) + 2;
35491 /* If the first selector comes from the second operand, swap. */
35492 else if (perm0
& 2)
35498 std::swap (op0
, op1
);
35500 /* If the second selector does not come from the second operand, fail. */
35501 else if ((perm1
& 2) == 0)
35505 if (target
!= NULL
)
35507 machine_mode vmode
, dmode
;
35510 vmode
= GET_MODE (target
);
35511 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
35512 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
35513 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
35514 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
35515 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
35516 emit_insn (gen_rtx_SET (target
, x
));
35522 rs6000_expand_vec_perm_const (rtx operands
[4])
35524 rtx target
, op0
, op1
, sel
;
35525 unsigned char perm0
, perm1
;
35527 target
= operands
[0];
35532 /* Unpack the constant selector. */
35533 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
35534 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
35536 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
35539 /* Test whether a constant permutation is supported. */
35542 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode
,
35543 const unsigned char *sel
)
35545 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35546 if (TARGET_ALTIVEC
)
35549 /* Check for ps_merge* or evmerge* insns. */
35550 if (TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
35552 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
35553 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
35554 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
35560 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
35563 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
35564 machine_mode vmode
, unsigned nelt
, rtx perm
[])
35566 machine_mode imode
;
35570 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
35572 imode
= mode_for_size (GET_MODE_UNIT_BITSIZE (vmode
), MODE_INT
, 0);
35573 imode
= mode_for_vector (imode
, nelt
);
35576 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
35577 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
35579 emit_move_insn (target
, x
);
35582 /* Expand an extract even operation. */
35585 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
35587 machine_mode vmode
= GET_MODE (target
);
35588 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
35591 for (i
= 0; i
< nelt
; i
++)
35592 perm
[i
] = GEN_INT (i
* 2);
35594 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
35597 /* Expand a vector interleave operation. */
35600 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
35602 machine_mode vmode
= GET_MODE (target
);
35603 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
35606 high
= (highp
? 0 : nelt
/ 2);
35607 for (i
= 0; i
< nelt
/ 2; i
++)
35609 perm
[i
* 2] = GEN_INT (i
+ high
);
35610 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
35613 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
35616 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35618 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
35620 HOST_WIDE_INT
hwi_scale (scale
);
35621 REAL_VALUE_TYPE r_pow
;
35622 rtvec v
= rtvec_alloc (2);
35624 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
35625 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
35626 elt
= const_double_from_real_value (r_pow
, DFmode
);
35627 RTVEC_ELT (v
, 0) = elt
;
35628 RTVEC_ELT (v
, 1) = elt
;
35629 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
35630 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
35633 /* Return an RTX representing where to find the function value of a
35634 function returning MODE. */
35636 rs6000_complex_function_value (machine_mode mode
)
35638 unsigned int regno
;
35640 machine_mode inner
= GET_MODE_INNER (mode
);
35641 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
35643 if (TARGET_FLOAT128_TYPE
35645 || (mode
== TCmode
&& TARGET_IEEEQUAD
)))
35646 regno
= ALTIVEC_ARG_RETURN
;
35648 else if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35649 regno
= FP_ARG_RETURN
;
35653 regno
= GP_ARG_RETURN
;
35655 /* 32-bit is OK since it'll go in r3/r4. */
35656 if (TARGET_32BIT
&& inner_bytes
>= 4)
35657 return gen_rtx_REG (mode
, regno
);
35660 if (inner_bytes
>= 8)
35661 return gen_rtx_REG (mode
, regno
);
35663 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
35665 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
35666 GEN_INT (inner_bytes
));
35667 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
35670 /* Return an rtx describing a return value of MODE as a PARALLEL
35671 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35672 stride REG_STRIDE. */
35675 rs6000_parallel_return (machine_mode mode
,
35676 int n_elts
, machine_mode elt_mode
,
35677 unsigned int regno
, unsigned int reg_stride
)
35679 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
35682 for (i
= 0; i
< n_elts
; i
++)
35684 rtx r
= gen_rtx_REG (elt_mode
, regno
);
35685 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
35686 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
35687 regno
+= reg_stride
;
35693 /* Target hook for TARGET_FUNCTION_VALUE.
35695 An integer value is in r3 and a floating-point value is in fp1,
35696 unless -msoft-float. */
35699 rs6000_function_value (const_tree valtype
,
35700 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
35701 bool outgoing ATTRIBUTE_UNUSED
)
35704 unsigned int regno
;
35705 machine_mode elt_mode
;
35708 /* Special handling for structs in darwin64. */
35710 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
35712 CUMULATIVE_ARGS valcum
;
35716 valcum
.fregno
= FP_ARG_MIN_REG
;
35717 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
35718 /* Do a trial code generation as if this were going to be passed as
35719 an argument; if any part goes in memory, we return NULL. */
35720 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
35723 /* Otherwise fall through to standard ABI rules. */
35726 mode
= TYPE_MODE (valtype
);
35728 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35729 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
35731 int first_reg
, n_regs
;
35733 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
35735 /* _Decimal128 must use even/odd register pairs. */
35736 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35737 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
35741 first_reg
= ALTIVEC_ARG_RETURN
;
35745 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
35748 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35749 if (TARGET_32BIT
&& TARGET_POWERPC64
)
35758 int count
= GET_MODE_SIZE (mode
) / 4;
35759 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
35762 if ((INTEGRAL_TYPE_P (valtype
)
35763 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
35764 || POINTER_TYPE_P (valtype
))
35765 mode
= TARGET_32BIT
? SImode
: DImode
;
35767 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35768 /* _Decimal128 must use an even/odd register pair. */
35769 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35770 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
35771 && !FLOAT128_VECTOR_P (mode
)
35772 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
35773 regno
= FP_ARG_RETURN
;
35774 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
35775 && targetm
.calls
.split_complex_arg
)
35776 return rs6000_complex_function_value (mode
);
35777 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35778 return register is used in both cases, and we won't see V2DImode/V2DFmode
35779 for pure altivec, combine the two cases. */
35780 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
35781 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
35782 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
35783 regno
= ALTIVEC_ARG_RETURN
;
35785 regno
= GP_ARG_RETURN
;
35787 return gen_rtx_REG (mode
, regno
);
35790 /* Define how to find the value returned by a library function
35791 assuming the value has mode MODE. */
35793 rs6000_libcall_value (machine_mode mode
)
35795 unsigned int regno
;
35797 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35798 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
35799 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
35801 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35802 /* _Decimal128 must use an even/odd register pair. */
35803 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35804 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
)
35805 && TARGET_HARD_FLOAT
35806 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
35807 regno
= FP_ARG_RETURN
;
35808 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35809 return register is used in both cases, and we won't see V2DImode/V2DFmode
35810 for pure altivec, combine the two cases. */
35811 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
35812 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
35813 regno
= ALTIVEC_ARG_RETURN
;
35814 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
35815 return rs6000_complex_function_value (mode
);
35817 regno
= GP_ARG_RETURN
;
35819 return gen_rtx_REG (mode
, regno
);
35822 /* Compute register pressure classes. We implement the target hook to avoid
35823 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
35824 lead to incorrect estimates of number of available registers and therefor
35825 increased register pressure/spill. */
35827 rs6000_compute_pressure_classes (enum reg_class
*pressure_classes
)
35832 pressure_classes
[n
++] = GENERAL_REGS
;
35834 pressure_classes
[n
++] = VSX_REGS
;
35837 if (TARGET_ALTIVEC
)
35838 pressure_classes
[n
++] = ALTIVEC_REGS
;
35839 if (TARGET_HARD_FLOAT
)
35840 pressure_classes
[n
++] = FLOAT_REGS
;
35842 pressure_classes
[n
++] = CR_REGS
;
35843 pressure_classes
[n
++] = SPECIAL_REGS
;
35848 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35849 Frame pointer elimination is automatically handled.
35851 For the RS/6000, if frame pointer elimination is being done, we would like
35852 to convert ap into fp, not sp.
35854 We need r30 if -mminimal-toc was specified, and there are constant pool
35858 rs6000_can_eliminate (const int from
, const int to
)
35860 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
35861 ? ! frame_pointer_needed
35862 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
35863 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
35864 || constant_pool_empty_p ()
35868 /* Define the offset between two registers, FROM to be eliminated and its
35869 replacement TO, at the start of a routine. */
35871 rs6000_initial_elimination_offset (int from
, int to
)
35873 rs6000_stack_t
*info
= rs6000_stack_info ();
35874 HOST_WIDE_INT offset
;
35876 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
35877 offset
= info
->push_p
? 0 : -info
->total_size
;
35878 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
35880 offset
= info
->push_p
? 0 : -info
->total_size
;
35881 if (FRAME_GROWS_DOWNWARD
)
35882 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
35884 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
35885 offset
= FRAME_GROWS_DOWNWARD
35886 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
35888 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
35889 offset
= info
->total_size
;
35890 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
35891 offset
= info
->push_p
? info
->total_size
: 0;
35892 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
35895 gcc_unreachable ();
35900 /* Fill in sizes of registers used by unwinder. */
35903 rs6000_init_dwarf_reg_sizes_extra (tree address
)
35905 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
35908 machine_mode mode
= TYPE_MODE (char_type_node
);
35909 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
35910 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
35911 rtx value
= gen_int_mode (16, mode
);
35913 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35914 The unwinder still needs to know the size of Altivec registers. */
35916 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
35918 int column
= DWARF_REG_TO_UNWIND_COLUMN
35919 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
35920 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
35922 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
35927 /* Map internal gcc register numbers to debug format register numbers.
35928 FORMAT specifies the type of debug register number to use:
35929 0 -- debug information, except for frame-related sections
35930 1 -- DWARF .debug_frame section
35931 2 -- DWARF .eh_frame section */
35934 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
35936 /* Except for the above, we use the internal number for non-DWARF
35937 debug information, and also for .eh_frame. */
35938 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
35941 /* On some platforms, we use the standard DWARF register
35942 numbering for .debug_info and .debug_frame. */
35943 #ifdef RS6000_USE_DWARF_NUMBERING
35946 if (regno
== LR_REGNO
)
35948 if (regno
== CTR_REGNO
)
35950 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
35951 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
35952 The actual code emitted saves the whole of CR, so we map CR2_REGNO
35953 to the DWARF reg for CR. */
35954 if (format
== 1 && regno
== CR2_REGNO
)
35956 if (CR_REGNO_P (regno
))
35957 return regno
- CR0_REGNO
+ 86;
35958 if (regno
== CA_REGNO
)
35959 return 101; /* XER */
35960 if (ALTIVEC_REGNO_P (regno
))
35961 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
35962 if (regno
== VRSAVE_REGNO
)
35964 if (regno
== VSCR_REGNO
)
35970 /* target hook eh_return_filter_mode */
35971 static machine_mode
35972 rs6000_eh_return_filter_mode (void)
35974 return TARGET_32BIT
? SImode
: word_mode
;
35977 /* Target hook for scalar_mode_supported_p. */
35979 rs6000_scalar_mode_supported_p (machine_mode mode
)
35981 /* -m32 does not support TImode. This is the default, from
35982 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
35983 same ABI as for -m32. But default_scalar_mode_supported_p allows
35984 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
35985 for -mpowerpc64. */
35986 if (TARGET_32BIT
&& mode
== TImode
)
35989 if (DECIMAL_FLOAT_MODE_P (mode
))
35990 return default_decimal_float_supported_p ();
35991 else if (TARGET_FLOAT128_TYPE
&& (mode
== KFmode
|| mode
== IFmode
))
35994 return default_scalar_mode_supported_p (mode
);
35997 /* Target hook for vector_mode_supported_p. */
35999 rs6000_vector_mode_supported_p (machine_mode mode
)
36002 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
36005 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36006 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36008 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
36015 /* Target hook for floatn_mode. */
36016 static machine_mode
36017 rs6000_floatn_mode (int n
, bool extended
)
36027 if (TARGET_FLOAT128_KEYWORD
)
36028 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36036 /* Those are the only valid _FloatNx types. */
36037 gcc_unreachable ();
36051 if (TARGET_FLOAT128_KEYWORD
)
36052 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36063 /* Target hook for c_mode_for_suffix. */
36064 static machine_mode
36065 rs6000_c_mode_for_suffix (char suffix
)
36067 if (TARGET_FLOAT128_TYPE
)
36069 if (suffix
== 'q' || suffix
== 'Q')
36070 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36072 /* At the moment, we are not defining a suffix for IBM extended double.
36073 If/when the default for -mabi=ieeelongdouble is changed, and we want
36074 to support __ibm128 constants in legacy library code, we may need to
36075 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36076 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36077 __float80 constants. */
36083 /* Target hook for invalid_arg_for_unprototyped_fn. */
36084 static const char *
36085 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
36087 return (!rs6000_darwin64_abi
36089 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
36090 && (funcdecl
== NULL_TREE
36091 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
36092 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
36093 ? N_("AltiVec argument passed to unprototyped function")
36097 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36098 setup by using __stack_chk_fail_local hidden function instead of
36099 calling __stack_chk_fail directly. Otherwise it is better to call
36100 __stack_chk_fail directly. */
36102 static tree ATTRIBUTE_UNUSED
36103 rs6000_stack_protect_fail (void)
36105 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
36106 ? default_hidden_stack_protect_fail ()
36107 : default_external_stack_protect_fail ();
36110 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36113 static unsigned HOST_WIDE_INT
36114 rs6000_asan_shadow_offset (void)
36116 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
36120 /* Mask options that we want to support inside of attribute((target)) and
36121 #pragma GCC target operations. Note, we do not include things like
36122 64/32-bit, endianness, hard/soft floating point, etc. that would have
36123 different calling sequences. */
36125 struct rs6000_opt_mask
{
36126 const char *name
; /* option name */
36127 HOST_WIDE_INT mask
; /* mask to set */
36128 bool invert
; /* invert sense of mask */
36129 bool valid_target
; /* option is a target option */
36132 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
36134 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
36135 { "cmpb", OPTION_MASK_CMPB
, false, true },
36136 { "crypto", OPTION_MASK_CRYPTO
, false, true },
36137 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
36138 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
36139 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
36141 { "float128", OPTION_MASK_FLOAT128_KEYWORD
, false, false },
36142 { "float128-type", OPTION_MASK_FLOAT128_TYPE
, false, false },
36143 { "float128-hardware", OPTION_MASK_FLOAT128_HW
, false, false },
36144 { "fprnd", OPTION_MASK_FPRND
, false, true },
36145 { "hard-dfp", OPTION_MASK_DFP
, false, true },
36146 { "htm", OPTION_MASK_HTM
, false, true },
36147 { "isel", OPTION_MASK_ISEL
, false, true },
36148 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
36149 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
36150 { "modulo", OPTION_MASK_MODULO
, false, true },
36151 { "mulhw", OPTION_MASK_MULHW
, false, true },
36152 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
36153 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
36154 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
36155 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
36156 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
36157 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
36158 { "power9-dform-scalar", OPTION_MASK_P9_DFORM_SCALAR
, false, true },
36159 { "power9-dform-vector", OPTION_MASK_P9_DFORM_VECTOR
, false, true },
36160 { "power9-fusion", OPTION_MASK_P9_FUSION
, false, true },
36161 { "power9-minmax", OPTION_MASK_P9_MINMAX
, false, true },
36162 { "power9-misc", OPTION_MASK_P9_MISC
, false, true },
36163 { "power9-vector", OPTION_MASK_P9_VECTOR
, false, true },
36164 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
36165 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
36166 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
36167 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
36168 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
36169 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
36170 { "string", OPTION_MASK_STRING
, false, true },
36171 { "toc-fusion", OPTION_MASK_TOC_FUSION
, false, true },
36172 { "update", OPTION_MASK_NO_UPDATE
, true , true },
36173 { "vsx", OPTION_MASK_VSX
, false, true },
36174 #ifdef OPTION_MASK_64BIT
36176 { "aix64", OPTION_MASK_64BIT
, false, false },
36177 { "aix32", OPTION_MASK_64BIT
, true, false },
36179 { "64", OPTION_MASK_64BIT
, false, false },
36180 { "32", OPTION_MASK_64BIT
, true, false },
36183 #ifdef OPTION_MASK_EABI
36184 { "eabi", OPTION_MASK_EABI
, false, false },
36186 #ifdef OPTION_MASK_LITTLE_ENDIAN
36187 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
36188 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
36190 #ifdef OPTION_MASK_RELOCATABLE
36191 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
36193 #ifdef OPTION_MASK_STRICT_ALIGN
36194 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
36196 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
36197 { "string", OPTION_MASK_STRING
, false, false },
36200 /* Builtin mask mapping for printing the flags. */
36201 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
36203 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
36204 { "vsx", RS6000_BTM_VSX
, false, false },
36205 { "paired", RS6000_BTM_PAIRED
, false, false },
36206 { "fre", RS6000_BTM_FRE
, false, false },
36207 { "fres", RS6000_BTM_FRES
, false, false },
36208 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
36209 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
36210 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
36211 { "cell", RS6000_BTM_CELL
, false, false },
36212 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
36213 { "power9-vector", RS6000_BTM_P9_VECTOR
, false, false },
36214 { "power9-misc", RS6000_BTM_P9_MISC
, false, false },
36215 { "crypto", RS6000_BTM_CRYPTO
, false, false },
36216 { "htm", RS6000_BTM_HTM
, false, false },
36217 { "hard-dfp", RS6000_BTM_DFP
, false, false },
36218 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
36219 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
36220 { "float128", RS6000_BTM_FLOAT128
, false, false },
36223 /* Option variables that we want to support inside attribute((target)) and
36224 #pragma GCC target operations. */
36226 struct rs6000_opt_var
{
36227 const char *name
; /* option name */
36228 size_t global_offset
; /* offset of the option in global_options. */
36229 size_t target_offset
; /* offset of the option in target options. */
36232 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
36235 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
36236 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
36237 { "avoid-indexed-addresses",
36238 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
36239 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
36241 offsetof (struct gcc_options
, x_rs6000_paired_float
),
36242 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
36244 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
36245 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
36246 { "optimize-swaps",
36247 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
36248 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
36249 { "allow-movmisalign",
36250 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
36251 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
36252 { "allow-df-permute",
36253 offsetof (struct gcc_options
, x_TARGET_ALLOW_DF_PERMUTE
),
36254 offsetof (struct cl_target_option
, x_TARGET_ALLOW_DF_PERMUTE
), },
36256 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
36257 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
36259 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
36260 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
36261 { "align-branch-targets",
36262 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
36263 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
36264 { "vectorize-builtins",
36265 offsetof (struct gcc_options
, x_TARGET_VECTORIZE_BUILTINS
),
36266 offsetof (struct cl_target_option
, x_TARGET_VECTORIZE_BUILTINS
), },
36268 offsetof (struct gcc_options
, x_tls_markers
),
36269 offsetof (struct cl_target_option
, x_tls_markers
), },
36271 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36272 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36274 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36275 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36278 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36279 parsing. Return true if there were no errors. */
36282 rs6000_inner_target_options (tree args
, bool attr_p
)
36286 if (args
== NULL_TREE
)
36289 else if (TREE_CODE (args
) == STRING_CST
)
36291 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36294 while ((q
= strtok (p
, ",")) != NULL
)
36296 bool error_p
= false;
36297 bool not_valid_p
= false;
36298 const char *cpu_opt
= NULL
;
36301 if (strncmp (q
, "cpu=", 4) == 0)
36303 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
36304 if (cpu_index
>= 0)
36305 rs6000_cpu_index
= cpu_index
;
36312 else if (strncmp (q
, "tune=", 5) == 0)
36314 int tune_index
= rs6000_cpu_name_lookup (q
+5);
36315 if (tune_index
>= 0)
36316 rs6000_tune_index
= tune_index
;
36326 bool invert
= false;
36330 if (strncmp (r
, "no-", 3) == 0)
36336 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
36337 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
36339 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
36341 if (!rs6000_opt_masks
[i
].valid_target
)
36342 not_valid_p
= true;
36346 rs6000_isa_flags_explicit
|= mask
;
36348 /* VSX needs altivec, so -mvsx automagically sets
36349 altivec and disables -mavoid-indexed-addresses. */
36352 if (mask
== OPTION_MASK_VSX
)
36354 mask
|= OPTION_MASK_ALTIVEC
;
36355 TARGET_AVOID_XFORM
= 0;
36359 if (rs6000_opt_masks
[i
].invert
)
36363 rs6000_isa_flags
&= ~mask
;
36365 rs6000_isa_flags
|= mask
;
36370 if (error_p
&& !not_valid_p
)
36372 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
36373 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
36375 size_t j
= rs6000_opt_vars
[i
].global_offset
;
36376 *((int *) ((char *)&global_options
+ j
)) = !invert
;
36378 not_valid_p
= false;
36386 const char *eprefix
, *esuffix
;
36391 eprefix
= "__attribute__((__target__(";
36396 eprefix
= "#pragma GCC target ";
36401 error ("invalid cpu %qs for %s%qs%s", cpu_opt
, eprefix
,
36403 else if (not_valid_p
)
36404 error ("%s%qs%s is not allowed", eprefix
, q
, esuffix
);
36406 error ("%s%qs%s is invalid", eprefix
, q
, esuffix
);
36411 else if (TREE_CODE (args
) == TREE_LIST
)
36415 tree value
= TREE_VALUE (args
);
36418 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
36422 args
= TREE_CHAIN (args
);
36424 while (args
!= NULL_TREE
);
36429 error ("attribute %<target%> argument not a string");
36436 /* Print out the target options as a list for -mdebug=target. */
36439 rs6000_debug_target_options (tree args
, const char *prefix
)
36441 if (args
== NULL_TREE
)
36442 fprintf (stderr
, "%s<NULL>", prefix
);
36444 else if (TREE_CODE (args
) == STRING_CST
)
36446 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36449 while ((q
= strtok (p
, ",")) != NULL
)
36452 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
36457 else if (TREE_CODE (args
) == TREE_LIST
)
36461 tree value
= TREE_VALUE (args
);
36464 rs6000_debug_target_options (value
, prefix
);
36467 args
= TREE_CHAIN (args
);
36469 while (args
!= NULL_TREE
);
36473 gcc_unreachable ();
36479 /* Hook to validate attribute((target("..."))). */
36482 rs6000_valid_attribute_p (tree fndecl
,
36483 tree
ARG_UNUSED (name
),
36487 struct cl_target_option cur_target
;
36489 tree old_optimize
= build_optimization_node (&global_options
);
36490 tree new_target
, new_optimize
;
36491 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
36493 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
36495 if (TARGET_DEBUG_TARGET
)
36497 tree tname
= DECL_NAME (fndecl
);
36498 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
36500 fprintf (stderr
, "function: %.*s\n",
36501 (int) IDENTIFIER_LENGTH (tname
),
36502 IDENTIFIER_POINTER (tname
));
36504 fprintf (stderr
, "function: unknown\n");
36506 fprintf (stderr
, "args:");
36507 rs6000_debug_target_options (args
, " ");
36508 fprintf (stderr
, "\n");
36511 fprintf (stderr
, "flags: 0x%x\n", flags
);
36513 fprintf (stderr
, "--------------------\n");
36516 /* attribute((target("default"))) does nothing, beyond
36517 affecting multi-versioning. */
36518 if (TREE_VALUE (args
)
36519 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
36520 && TREE_CHAIN (args
) == NULL_TREE
36521 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
36524 old_optimize
= build_optimization_node (&global_options
);
36525 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
36527 /* If the function changed the optimization levels as well as setting target
36528 options, start with the optimizations specified. */
36529 if (func_optimize
&& func_optimize
!= old_optimize
)
36530 cl_optimization_restore (&global_options
,
36531 TREE_OPTIMIZATION (func_optimize
));
36533 /* The target attributes may also change some optimization flags, so update
36534 the optimization options if necessary. */
36535 cl_target_option_save (&cur_target
, &global_options
);
36536 rs6000_cpu_index
= rs6000_tune_index
= -1;
36537 ret
= rs6000_inner_target_options (args
, true);
36539 /* Set up any additional state. */
36542 ret
= rs6000_option_override_internal (false);
36543 new_target
= build_target_option_node (&global_options
);
36548 new_optimize
= build_optimization_node (&global_options
);
36555 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
36557 if (old_optimize
!= new_optimize
)
36558 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
36561 cl_target_option_restore (&global_options
, &cur_target
);
36563 if (old_optimize
!= new_optimize
)
36564 cl_optimization_restore (&global_options
,
36565 TREE_OPTIMIZATION (old_optimize
));
36571 /* Hook to validate the current #pragma GCC target and set the state, and
36572 update the macros based on what was changed. If ARGS is NULL, then
36573 POP_TARGET is used to reset the options. */
36576 rs6000_pragma_target_parse (tree args
, tree pop_target
)
36578 tree prev_tree
= build_target_option_node (&global_options
);
36580 struct cl_target_option
*prev_opt
, *cur_opt
;
36581 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
36582 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
36584 if (TARGET_DEBUG_TARGET
)
36586 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
36587 fprintf (stderr
, "args:");
36588 rs6000_debug_target_options (args
, " ");
36589 fprintf (stderr
, "\n");
36593 fprintf (stderr
, "pop_target:\n");
36594 debug_tree (pop_target
);
36597 fprintf (stderr
, "pop_target: <NULL>\n");
36599 fprintf (stderr
, "--------------------\n");
36604 cur_tree
= ((pop_target
)
36606 : target_option_default_node
);
36607 cl_target_option_restore (&global_options
,
36608 TREE_TARGET_OPTION (cur_tree
));
36612 rs6000_cpu_index
= rs6000_tune_index
= -1;
36613 if (!rs6000_inner_target_options (args
, false)
36614 || !rs6000_option_override_internal (false)
36615 || (cur_tree
= build_target_option_node (&global_options
))
36618 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
36619 fprintf (stderr
, "invalid pragma\n");
36625 target_option_current_node
= cur_tree
;
36627 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36628 change the macros that are defined. */
36629 if (rs6000_target_modify_macros_ptr
)
36631 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
36632 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
36633 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
36635 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
36636 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
36637 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
36639 diff_bumask
= (prev_bumask
^ cur_bumask
);
36640 diff_flags
= (prev_flags
^ cur_flags
);
36642 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
36644 /* Delete old macros. */
36645 rs6000_target_modify_macros_ptr (false,
36646 prev_flags
& diff_flags
,
36647 prev_bumask
& diff_bumask
);
36649 /* Define new macros. */
36650 rs6000_target_modify_macros_ptr (true,
36651 cur_flags
& diff_flags
,
36652 cur_bumask
& diff_bumask
);
36660 /* Remember the last target of rs6000_set_current_function. */
36661 static GTY(()) tree rs6000_previous_fndecl
;
36663 /* Establish appropriate back-end context for processing the function
36664 FNDECL. The argument might be NULL to indicate processing at top
36665 level, outside of any function scope. */
36667 rs6000_set_current_function (tree fndecl
)
36669 tree old_tree
= (rs6000_previous_fndecl
36670 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
36673 tree new_tree
= (fndecl
36674 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
36677 if (TARGET_DEBUG_TARGET
)
36679 bool print_final
= false;
36680 fprintf (stderr
, "\n==================== rs6000_set_current_function");
36683 fprintf (stderr
, ", fndecl %s (%p)",
36684 (DECL_NAME (fndecl
)
36685 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
36686 : "<unknown>"), (void *)fndecl
);
36688 if (rs6000_previous_fndecl
)
36689 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
36691 fprintf (stderr
, "\n");
36694 fprintf (stderr
, "\nnew fndecl target specific options:\n");
36695 debug_tree (new_tree
);
36696 print_final
= true;
36701 fprintf (stderr
, "\nold fndecl target specific options:\n");
36702 debug_tree (old_tree
);
36703 print_final
= true;
36707 fprintf (stderr
, "--------------------\n");
36710 /* Only change the context if the function changes. This hook is called
36711 several times in the course of compiling a function, and we don't want to
36712 slow things down too much or call target_reinit when it isn't safe. */
36713 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
36715 rs6000_previous_fndecl
= fndecl
;
36716 if (old_tree
== new_tree
)
36719 else if (new_tree
&& new_tree
!= target_option_default_node
)
36721 cl_target_option_restore (&global_options
,
36722 TREE_TARGET_OPTION (new_tree
));
36723 if (TREE_TARGET_GLOBALS (new_tree
))
36724 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
36726 TREE_TARGET_GLOBALS (new_tree
)
36727 = save_target_globals_default_opts ();
36730 else if (old_tree
&& old_tree
!= target_option_default_node
)
36732 new_tree
= target_option_current_node
;
36733 cl_target_option_restore (&global_options
,
36734 TREE_TARGET_OPTION (new_tree
));
36735 if (TREE_TARGET_GLOBALS (new_tree
))
36736 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
36737 else if (new_tree
== target_option_default_node
)
36738 restore_target_globals (&default_target_globals
);
36740 TREE_TARGET_GLOBALS (new_tree
)
36741 = save_target_globals_default_opts ();
36747 /* Save the current options */
36750 rs6000_function_specific_save (struct cl_target_option
*ptr
,
36751 struct gcc_options
*opts
)
36753 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
36754 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
36757 /* Restore the current options */
36760 rs6000_function_specific_restore (struct gcc_options
*opts
,
36761 struct cl_target_option
*ptr
)
36764 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
36765 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
36766 (void) rs6000_option_override_internal (false);
36769 /* Print the current options */
36772 rs6000_function_specific_print (FILE *file
, int indent
,
36773 struct cl_target_option
*ptr
)
36775 rs6000_print_isa_options (file
, indent
, "Isa options set",
36776 ptr
->x_rs6000_isa_flags
);
36778 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
36779 ptr
->x_rs6000_isa_flags_explicit
);
36782 /* Helper function to print the current isa or misc options on a line. */
36785 rs6000_print_options_internal (FILE *file
,
36787 const char *string
,
36788 HOST_WIDE_INT flags
,
36789 const char *prefix
,
36790 const struct rs6000_opt_mask
*opts
,
36791 size_t num_elements
)
36794 size_t start_column
= 0;
36796 size_t max_column
= 120;
36797 size_t prefix_len
= strlen (prefix
);
36798 size_t comma_len
= 0;
36799 const char *comma
= "";
36802 start_column
+= fprintf (file
, "%*s", indent
, "");
36806 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
36810 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
36812 /* Print the various mask options. */
36813 cur_column
= start_column
;
36814 for (i
= 0; i
< num_elements
; i
++)
36816 bool invert
= opts
[i
].invert
;
36817 const char *name
= opts
[i
].name
;
36818 const char *no_str
= "";
36819 HOST_WIDE_INT mask
= opts
[i
].mask
;
36820 size_t len
= comma_len
+ prefix_len
+ strlen (name
);
36824 if ((flags
& mask
) == 0)
36827 len
+= sizeof ("no-") - 1;
36835 if ((flags
& mask
) != 0)
36838 len
+= sizeof ("no-") - 1;
36845 if (cur_column
> max_column
)
36847 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
36848 cur_column
= start_column
+ len
;
36852 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
, name
);
36854 comma_len
= sizeof (", ") - 1;
36857 fputs ("\n", file
);
36860 /* Helper function to print the current isa options on a line. */
36863 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
36864 HOST_WIDE_INT flags
)
36866 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
36867 &rs6000_opt_masks
[0],
36868 ARRAY_SIZE (rs6000_opt_masks
));
36872 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
36873 HOST_WIDE_INT flags
)
36875 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
36876 &rs6000_builtin_mask_names
[0],
36877 ARRAY_SIZE (rs6000_builtin_mask_names
));
36880 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36881 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36882 -mupper-regs-df, etc.).
36884 If the user used -mno-power8-vector, we need to turn off all of the implicit
36885 ISA 2.07 and 3.0 options that relate to the vector unit.
36887 If the user used -mno-power9-vector, we need to turn off all of the implicit
36888 ISA 3.0 options that relate to the vector unit.
36890 This function does not handle explicit options such as the user specifying
36891 -mdirect-move. These are handled in rs6000_option_override_internal, and
36892 the appropriate error is given if needed.
36894 We return a mask of all of the implicit options that should not be enabled
36897 static HOST_WIDE_INT
36898 rs6000_disable_incompatible_switches (void)
36900 HOST_WIDE_INT ignore_masks
= rs6000_isa_flags_explicit
;
36903 static const struct {
36904 const HOST_WIDE_INT no_flag
; /* flag explicitly turned off. */
36905 const HOST_WIDE_INT dep_flags
; /* flags that depend on this option. */
36906 const char *const name
; /* name of the switch. */
36908 { OPTION_MASK_P9_VECTOR
, OTHER_P9_VECTOR_MASKS
, "power9-vector" },
36909 { OPTION_MASK_P8_VECTOR
, OTHER_P8_VECTOR_MASKS
, "power8-vector" },
36910 { OPTION_MASK_VSX
, OTHER_VSX_VECTOR_MASKS
, "vsx" },
36913 for (i
= 0; i
< ARRAY_SIZE (flags
); i
++)
36915 HOST_WIDE_INT no_flag
= flags
[i
].no_flag
;
36917 if ((rs6000_isa_flags
& no_flag
) == 0
36918 && (rs6000_isa_flags_explicit
& no_flag
) != 0)
36920 HOST_WIDE_INT dep_flags
= flags
[i
].dep_flags
;
36921 HOST_WIDE_INT set_flags
= (rs6000_isa_flags_explicit
36927 for (j
= 0; j
< ARRAY_SIZE (rs6000_opt_masks
); j
++)
36928 if ((set_flags
& rs6000_opt_masks
[j
].mask
) != 0)
36930 set_flags
&= ~rs6000_opt_masks
[j
].mask
;
36931 error ("%<-mno-%s%> turns off %<-m%s%>",
36933 rs6000_opt_masks
[j
].name
);
36936 gcc_assert (!set_flags
);
36939 rs6000_isa_flags
&= ~dep_flags
;
36940 ignore_masks
|= no_flag
| dep_flags
;
36944 if (!TARGET_P9_VECTOR
36945 && (rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) != 0
36946 && TARGET_P9_DFORM_BOTH
> 0)
36948 error ("%qs turns off %qs", "-mno-power9-vector", "-mpower9-dform");
36949 TARGET_P9_DFORM_BOTH
= 0;
36952 return ignore_masks
;
36956 /* Helper function for printing the function name when debugging. */
36958 static const char *
36959 get_decl_name (tree fn
)
36966 name
= DECL_NAME (fn
);
36968 return "<no-name>";
36970 return IDENTIFIER_POINTER (name
);
36973 /* Return the clone id of the target we are compiling code for in a target
36974 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
36975 the priority list for the target clones (ordered from lowest to
36979 rs6000_clone_priority (tree fndecl
)
36981 tree fn_opts
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
36982 HOST_WIDE_INT isa_masks
;
36983 int ret
= CLONE_DEFAULT
;
36984 tree attrs
= lookup_attribute ("target", DECL_ATTRIBUTES (fndecl
));
36985 const char *attrs_str
= NULL
;
36987 attrs
= TREE_VALUE (TREE_VALUE (attrs
));
36988 attrs_str
= TREE_STRING_POINTER (attrs
);
36990 /* Return priority zero for default function. Return the ISA needed for the
36991 function if it is not the default. */
36992 if (strcmp (attrs_str
, "default") != 0)
36994 if (fn_opts
== NULL_TREE
)
36995 fn_opts
= target_option_default_node
;
36997 if (!fn_opts
|| !TREE_TARGET_OPTION (fn_opts
))
36998 isa_masks
= rs6000_isa_flags
;
37000 isa_masks
= TREE_TARGET_OPTION (fn_opts
)->x_rs6000_isa_flags
;
37002 for (ret
= CLONE_MAX
- 1; ret
!= 0; ret
--)
37003 if ((rs6000_clone_map
[ret
].isa_mask
& isa_masks
) != 0)
37007 if (TARGET_DEBUG_TARGET
)
37008 fprintf (stderr
, "rs6000_get_function_version_priority (%s) => %d\n",
37009 get_decl_name (fndecl
), ret
);
37014 /* This compares the priority of target features in function DECL1 and DECL2.
37015 It returns positive value if DECL1 is higher priority, negative value if
37016 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37017 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37020 rs6000_compare_version_priority (tree decl1
, tree decl2
)
37022 int priority1
= rs6000_clone_priority (decl1
);
37023 int priority2
= rs6000_clone_priority (decl2
);
37024 int ret
= priority1
- priority2
;
37026 if (TARGET_DEBUG_TARGET
)
37027 fprintf (stderr
, "rs6000_compare_version_priority (%s, %s) => %d\n",
37028 get_decl_name (decl1
), get_decl_name (decl2
), ret
);
37033 /* Make a dispatcher declaration for the multi-versioned function DECL.
37034 Calls to DECL function will be replaced with calls to the dispatcher
37035 by the front-end. Returns the decl of the dispatcher function. */
37038 rs6000_get_function_versions_dispatcher (void *decl
)
37040 tree fn
= (tree
) decl
;
37041 struct cgraph_node
*node
= NULL
;
37042 struct cgraph_node
*default_node
= NULL
;
37043 struct cgraph_function_version_info
*node_v
= NULL
;
37044 struct cgraph_function_version_info
*first_v
= NULL
;
37046 tree dispatch_decl
= NULL
;
37048 struct cgraph_function_version_info
*default_version_info
= NULL
;
37049 gcc_assert (fn
!= NULL
&& DECL_FUNCTION_VERSIONED (fn
));
37051 if (TARGET_DEBUG_TARGET
)
37052 fprintf (stderr
, "rs6000_get_function_versions_dispatcher (%s)\n",
37053 get_decl_name (fn
));
37055 node
= cgraph_node::get (fn
);
37056 gcc_assert (node
!= NULL
);
37058 node_v
= node
->function_version ();
37059 gcc_assert (node_v
!= NULL
);
37061 if (node_v
->dispatcher_resolver
!= NULL
)
37062 return node_v
->dispatcher_resolver
;
37064 /* Find the default version and make it the first node. */
37066 /* Go to the beginning of the chain. */
37067 while (first_v
->prev
!= NULL
)
37068 first_v
= first_v
->prev
;
37070 default_version_info
= first_v
;
37071 while (default_version_info
!= NULL
)
37073 const tree decl2
= default_version_info
->this_node
->decl
;
37074 if (is_function_default_version (decl2
))
37076 default_version_info
= default_version_info
->next
;
37079 /* If there is no default node, just return NULL. */
37080 if (default_version_info
== NULL
)
37083 /* Make default info the first node. */
37084 if (first_v
!= default_version_info
)
37086 default_version_info
->prev
->next
= default_version_info
->next
;
37087 if (default_version_info
->next
)
37088 default_version_info
->next
->prev
= default_version_info
->prev
;
37089 first_v
->prev
= default_version_info
;
37090 default_version_info
->next
= first_v
;
37091 default_version_info
->prev
= NULL
;
37094 default_node
= default_version_info
->this_node
;
37096 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37097 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
37098 "target_clones attribute needs GLIBC (2.23 and newer) that "
37099 "exports hardware capability bits");
37102 if (targetm
.has_ifunc_p ())
37104 struct cgraph_function_version_info
*it_v
= NULL
;
37105 struct cgraph_node
*dispatcher_node
= NULL
;
37106 struct cgraph_function_version_info
*dispatcher_version_info
= NULL
;
37108 /* Right now, the dispatching is done via ifunc. */
37109 dispatch_decl
= make_dispatcher_decl (default_node
->decl
);
37111 dispatcher_node
= cgraph_node::get_create (dispatch_decl
);
37112 gcc_assert (dispatcher_node
!= NULL
);
37113 dispatcher_node
->dispatcher_function
= 1;
37114 dispatcher_version_info
37115 = dispatcher_node
->insert_new_function_version ();
37116 dispatcher_version_info
->next
= default_version_info
;
37117 dispatcher_node
->definition
= 1;
37119 /* Set the dispatcher for all the versions. */
37120 it_v
= default_version_info
;
37121 while (it_v
!= NULL
)
37123 it_v
->dispatcher_resolver
= dispatch_decl
;
37129 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
37130 "multiversioning needs ifunc which is not supported "
37135 return dispatch_decl
;
37138 /* Make the resolver function decl to dispatch the versions of a multi-
37139 versioned function, DEFAULT_DECL. Create an empty basic block in the
37140 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37144 make_resolver_func (const tree default_decl
,
37145 const tree dispatch_decl
,
37146 basic_block
*empty_bb
)
37148 /* Make the resolver function static. The resolver function returns
37150 tree decl_name
= clone_function_name (default_decl
, "resolver");
37151 const char *resolver_name
= IDENTIFIER_POINTER (decl_name
);
37152 tree type
= build_function_type_list (ptr_type_node
, NULL_TREE
);
37153 tree decl
= build_fn_decl (resolver_name
, type
);
37154 SET_DECL_ASSEMBLER_NAME (decl
, decl_name
);
37156 DECL_NAME (decl
) = decl_name
;
37157 TREE_USED (decl
) = 1;
37158 DECL_ARTIFICIAL (decl
) = 1;
37159 DECL_IGNORED_P (decl
) = 0;
37160 TREE_PUBLIC (decl
) = 0;
37161 DECL_UNINLINABLE (decl
) = 1;
37163 /* Resolver is not external, body is generated. */
37164 DECL_EXTERNAL (decl
) = 0;
37165 DECL_EXTERNAL (dispatch_decl
) = 0;
37167 DECL_CONTEXT (decl
) = NULL_TREE
;
37168 DECL_INITIAL (decl
) = make_node (BLOCK
);
37169 DECL_STATIC_CONSTRUCTOR (decl
) = 0;
37171 /* Build result decl and add to function_decl. */
37172 tree t
= build_decl (UNKNOWN_LOCATION
, RESULT_DECL
, NULL_TREE
, ptr_type_node
);
37173 DECL_ARTIFICIAL (t
) = 1;
37174 DECL_IGNORED_P (t
) = 1;
37175 DECL_RESULT (decl
) = t
;
37177 gimplify_function_tree (decl
);
37178 push_cfun (DECL_STRUCT_FUNCTION (decl
));
37179 *empty_bb
= init_lowered_empty_function (decl
, false,
37180 profile_count::uninitialized ());
37182 cgraph_node::add_new_function (decl
, true);
37183 symtab
->call_cgraph_insertion_hooks (cgraph_node::get_create (decl
));
37187 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37188 DECL_ATTRIBUTES (dispatch_decl
)
37189 = make_attribute ("ifunc", resolver_name
, DECL_ATTRIBUTES (dispatch_decl
));
37191 cgraph_node::create_same_body_alias (dispatch_decl
, decl
);
37196 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37197 return a pointer to VERSION_DECL if we are running on a machine that
37198 supports the index CLONE_ISA hardware architecture bits. This function will
37199 be called during version dispatch to decide which function version to
37200 execute. It returns the basic block at the end, to which more conditions
37204 add_condition_to_bb (tree function_decl
, tree version_decl
,
37205 int clone_isa
, basic_block new_bb
)
37207 push_cfun (DECL_STRUCT_FUNCTION (function_decl
));
37209 gcc_assert (new_bb
!= NULL
);
37210 gimple_seq gseq
= bb_seq (new_bb
);
37213 tree convert_expr
= build1 (CONVERT_EXPR
, ptr_type_node
,
37214 build_fold_addr_expr (version_decl
));
37215 tree result_var
= create_tmp_var (ptr_type_node
);
37216 gimple
*convert_stmt
= gimple_build_assign (result_var
, convert_expr
);
37217 gimple
*return_stmt
= gimple_build_return (result_var
);
37219 if (clone_isa
== CLONE_DEFAULT
)
37221 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37222 gimple_seq_add_stmt (&gseq
, return_stmt
);
37223 set_bb_seq (new_bb
, gseq
);
37224 gimple_set_bb (convert_stmt
, new_bb
);
37225 gimple_set_bb (return_stmt
, new_bb
);
37230 tree bool_zero
= build_int_cst (bool_int_type_node
, 0);
37231 tree cond_var
= create_tmp_var (bool_int_type_node
);
37232 tree predicate_decl
= rs6000_builtin_decls
[(int) RS6000_BUILTIN_CPU_SUPPORTS
];
37233 const char *arg_str
= rs6000_clone_map
[clone_isa
].name
;
37234 tree predicate_arg
= build_string_literal (strlen (arg_str
) + 1, arg_str
);
37235 gimple
*call_cond_stmt
= gimple_build_call (predicate_decl
, 1, predicate_arg
);
37236 gimple_call_set_lhs (call_cond_stmt
, cond_var
);
37238 gimple_set_block (call_cond_stmt
, DECL_INITIAL (function_decl
));
37239 gimple_set_bb (call_cond_stmt
, new_bb
);
37240 gimple_seq_add_stmt (&gseq
, call_cond_stmt
);
37242 gimple
*if_else_stmt
= gimple_build_cond (NE_EXPR
, cond_var
, bool_zero
,
37243 NULL_TREE
, NULL_TREE
);
37244 gimple_set_block (if_else_stmt
, DECL_INITIAL (function_decl
));
37245 gimple_set_bb (if_else_stmt
, new_bb
);
37246 gimple_seq_add_stmt (&gseq
, if_else_stmt
);
37248 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37249 gimple_seq_add_stmt (&gseq
, return_stmt
);
37250 set_bb_seq (new_bb
, gseq
);
37252 basic_block bb1
= new_bb
;
37253 edge e12
= split_block (bb1
, if_else_stmt
);
37254 basic_block bb2
= e12
->dest
;
37255 e12
->flags
&= ~EDGE_FALLTHRU
;
37256 e12
->flags
|= EDGE_TRUE_VALUE
;
37258 edge e23
= split_block (bb2
, return_stmt
);
37259 gimple_set_bb (convert_stmt
, bb2
);
37260 gimple_set_bb (return_stmt
, bb2
);
37262 basic_block bb3
= e23
->dest
;
37263 make_edge (bb1
, bb3
, EDGE_FALSE_VALUE
);
37266 make_edge (bb2
, EXIT_BLOCK_PTR_FOR_FN (cfun
), 0);
37272 /* This function generates the dispatch function for multi-versioned functions.
37273 DISPATCH_DECL is the function which will contain the dispatch logic.
37274 FNDECLS are the function choices for dispatch, and is a tree chain.
37275 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37276 code is generated. */
37279 dispatch_function_versions (tree dispatch_decl
,
37281 basic_block
*empty_bb
)
37285 vec
<tree
> *fndecls
;
37286 tree clones
[CLONE_MAX
];
37288 if (TARGET_DEBUG_TARGET
)
37289 fputs ("dispatch_function_versions, top\n", stderr
);
37291 gcc_assert (dispatch_decl
!= NULL
37292 && fndecls_p
!= NULL
37293 && empty_bb
!= NULL
);
37295 /* fndecls_p is actually a vector. */
37296 fndecls
= static_cast<vec
<tree
> *> (fndecls_p
);
37298 /* At least one more version other than the default. */
37299 gcc_assert (fndecls
->length () >= 2);
37301 /* The first version in the vector is the default decl. */
37302 memset ((void *) clones
, '\0', sizeof (clones
));
37303 clones
[CLONE_DEFAULT
] = (*fndecls
)[0];
37305 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37306 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37307 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37308 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37309 to insert the code here to do the call. */
37311 for (ix
= 1; fndecls
->iterate (ix
, &ele
); ++ix
)
37313 int priority
= rs6000_clone_priority (ele
);
37314 if (!clones
[priority
])
37315 clones
[priority
] = ele
;
37318 for (ix
= CLONE_MAX
- 1; ix
>= 0; ix
--)
37321 if (TARGET_DEBUG_TARGET
)
37322 fprintf (stderr
, "dispatch_function_versions, clone %d, %s\n",
37323 ix
, get_decl_name (clones
[ix
]));
37325 *empty_bb
= add_condition_to_bb (dispatch_decl
, clones
[ix
], ix
,
37332 /* Generate the dispatching code body to dispatch multi-versioned function
37333 DECL. The target hook is called to process the "target" attributes and
37334 provide the code to dispatch the right function at run-time. NODE points
37335 to the dispatcher decl whose body will be created. */
37338 rs6000_generate_version_dispatcher_body (void *node_p
)
37341 basic_block empty_bb
;
37342 struct cgraph_node
*node
= (cgraph_node
*) node_p
;
37343 struct cgraph_function_version_info
*ninfo
= node
->function_version ();
37345 if (ninfo
->dispatcher_resolver
)
37346 return ninfo
->dispatcher_resolver
;
37348 /* node is going to be an alias, so remove the finalized bit. */
37349 node
->definition
= false;
37351 /* The first version in the chain corresponds to the default version. */
37352 ninfo
->dispatcher_resolver
= resolver
37353 = make_resolver_func (ninfo
->next
->this_node
->decl
, node
->decl
, &empty_bb
);
37355 if (TARGET_DEBUG_TARGET
)
37356 fprintf (stderr
, "rs6000_get_function_versions_dispatcher, %s\n",
37357 get_decl_name (resolver
));
37359 push_cfun (DECL_STRUCT_FUNCTION (resolver
));
37360 auto_vec
<tree
, 2> fn_ver_vec
;
37362 for (struct cgraph_function_version_info
*vinfo
= ninfo
->next
;
37364 vinfo
= vinfo
->next
)
37366 struct cgraph_node
*version
= vinfo
->this_node
;
37367 /* Check for virtual functions here again, as by this time it should
37368 have been determined if this function needs a vtable index or
37369 not. This happens for methods in derived classes that override
37370 virtual methods in base classes but are not explicitly marked as
37372 if (DECL_VINDEX (version
->decl
))
37373 sorry ("Virtual function multiversioning not supported");
37375 fn_ver_vec
.safe_push (version
->decl
);
37378 dispatch_function_versions (resolver
, &fn_ver_vec
, &empty_bb
);
37379 cgraph_edge::rebuild_edges ();
37385 /* Hook to determine if one function can safely inline another. */
37388 rs6000_can_inline_p (tree caller
, tree callee
)
37391 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
37392 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
37394 /* If callee has no option attributes, then it is ok to inline. */
37398 /* If caller has no option attributes, but callee does then it is not ok to
37400 else if (!caller_tree
)
37405 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
37406 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
37408 /* Callee's options should a subset of the caller's, i.e. a vsx function
37409 can inline an altivec function but a non-vsx function can't inline a
37411 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
37412 == callee_opts
->x_rs6000_isa_flags
)
37416 if (TARGET_DEBUG_TARGET
)
37417 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37418 get_decl_name (caller
), get_decl_name (callee
),
37419 (ret
? "can" : "cannot"));
37424 /* Allocate a stack temp and fixup the address so it meets the particular
37425 memory requirements (either offetable or REG+REG addressing). */
37428 rs6000_allocate_stack_temp (machine_mode mode
,
37429 bool offsettable_p
,
37432 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
37433 rtx addr
= XEXP (stack
, 0);
37434 int strict_p
= reload_completed
;
37436 if (!legitimate_indirect_address_p (addr
, strict_p
))
37439 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
37440 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37442 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
37443 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37449 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37450 to such a form to deal with memory reference instructions like STFIWX that
37451 only take reg+reg addressing. */
37454 rs6000_address_for_fpconvert (rtx x
)
37458 gcc_assert (MEM_P (x
));
37459 addr
= XEXP (x
, 0);
37460 if (! legitimate_indirect_address_p (addr
, reload_completed
)
37461 && ! legitimate_indexed_address_p (addr
, reload_completed
))
37463 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
37465 rtx reg
= XEXP (addr
, 0);
37466 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
37467 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
37468 gcc_assert (REG_P (reg
));
37469 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
37472 else if (GET_CODE (addr
) == PRE_MODIFY
)
37474 rtx reg
= XEXP (addr
, 0);
37475 rtx expr
= XEXP (addr
, 1);
37476 gcc_assert (REG_P (reg
));
37477 gcc_assert (GET_CODE (expr
) == PLUS
);
37478 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
37482 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
37488 /* Given a memory reference, if it is not in the form for altivec memory
37489 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
37490 convert to the altivec format. */
37493 rs6000_address_for_altivec (rtx x
)
37495 gcc_assert (MEM_P (x
));
37496 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
37498 rtx addr
= XEXP (x
, 0);
37500 if (!legitimate_indexed_address_p (addr
, reload_completed
)
37501 && !legitimate_indirect_address_p (addr
, reload_completed
))
37502 addr
= copy_to_mode_reg (Pmode
, addr
);
37504 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
37505 x
= change_address (x
, GET_MODE (x
), addr
);
37511 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37513 On the RS/6000, all integer constants are acceptable, most won't be valid
37514 for particular insns, though. Only easy FP constants are acceptable. */
37517 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
37519 if (TARGET_ELF
&& tls_referenced_p (x
))
37522 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
37523 || GET_MODE (x
) == VOIDmode
37524 || (TARGET_POWERPC64
&& mode
== DImode
)
37525 || easy_fp_constant (x
, mode
)
37526 || easy_vector_constant (x
, mode
));
37530 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37533 chain_already_loaded (rtx_insn
*last
)
37535 for (; last
!= NULL
; last
= PREV_INSN (last
))
37537 if (NONJUMP_INSN_P (last
))
37539 rtx patt
= PATTERN (last
);
37541 if (GET_CODE (patt
) == SET
)
37543 rtx lhs
= XEXP (patt
, 0);
37545 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
37553 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37556 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
37558 const bool direct_call_p
37559 = GET_CODE (func_desc
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (func_desc
);
37560 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
37561 rtx toc_load
= NULL_RTX
;
37562 rtx toc_restore
= NULL_RTX
;
37564 rtx abi_reg
= NULL_RTX
;
37569 /* Handle longcall attributes. */
37570 if (INTVAL (cookie
) & CALL_LONG
)
37571 func_desc
= rs6000_longcall_ref (func_desc
);
37573 /* Handle indirect calls. */
37574 if (GET_CODE (func_desc
) != SYMBOL_REF
37575 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
37577 /* Save the TOC into its reserved slot before the call,
37578 and prepare to restore it after the call. */
37579 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
37580 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
37581 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
37582 gen_rtx_PLUS (Pmode
, stack_ptr
,
37583 stack_toc_offset
));
37584 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
37585 gen_rtvec (1, stack_toc_offset
),
37587 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
37589 /* Can we optimize saving the TOC in the prologue or
37590 do we need to do it at every call? */
37591 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
37592 cfun
->machine
->save_toc_in_prologue
= true;
37595 MEM_VOLATILE_P (stack_toc_mem
) = 1;
37596 emit_move_insn (stack_toc_mem
, toc_reg
);
37599 if (DEFAULT_ABI
== ABI_ELFv2
)
37601 /* A function pointer in the ELFv2 ABI is just a plain address, but
37602 the ABI requires it to be loaded into r12 before the call. */
37603 func_addr
= gen_rtx_REG (Pmode
, 12);
37604 emit_move_insn (func_addr
, func_desc
);
37605 abi_reg
= func_addr
;
37609 /* A function pointer under AIX is a pointer to a data area whose
37610 first word contains the actual address of the function, whose
37611 second word contains a pointer to its TOC, and whose third word
37612 contains a value to place in the static chain register (r11).
37613 Note that if we load the static chain, our "trampoline" need
37614 not have any executable code. */
37616 /* Load up address of the actual function. */
37617 func_desc
= force_reg (Pmode
, func_desc
);
37618 func_addr
= gen_reg_rtx (Pmode
);
37619 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
37621 /* Prepare to load the TOC of the called function. Note that the
37622 TOC load must happen immediately before the actual call so
37623 that unwinding the TOC registers works correctly. See the
37624 comment in frob_update_context. */
37625 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
37626 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
37627 gen_rtx_PLUS (Pmode
, func_desc
,
37629 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
37631 /* If we have a static chain, load it up. But, if the call was
37632 originally direct, the 3rd word has not been written since no
37633 trampoline has been built, so we ought not to load it, lest we
37634 override a static chain value. */
37636 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37637 && !chain_already_loaded (get_current_sequence ()->next
->last
))
37639 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
37640 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
37641 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
37642 gen_rtx_PLUS (Pmode
, func_desc
,
37644 emit_move_insn (sc_reg
, func_sc_mem
);
37651 /* Direct calls use the TOC: for local calls, the callee will
37652 assume the TOC register is set; for non-local calls, the
37653 PLT stub needs the TOC register. */
37655 func_addr
= func_desc
;
37658 /* Create the call. */
37659 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
37660 if (value
!= NULL_RTX
)
37661 call
[0] = gen_rtx_SET (value
, call
[0]);
37665 call
[n_call
++] = toc_load
;
37667 call
[n_call
++] = toc_restore
;
37669 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
37671 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
37672 insn
= emit_call_insn (insn
);
37674 /* Mention all registers defined by the ABI to hold information
37675 as uses in CALL_INSN_FUNCTION_USAGE. */
37677 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
37680 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37683 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
37688 gcc_assert (INTVAL (cookie
) == 0);
37690 /* Create the call. */
37691 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
37692 if (value
!= NULL_RTX
)
37693 call
[0] = gen_rtx_SET (value
, call
[0]);
37695 call
[1] = simple_return_rtx
;
37697 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
37698 insn
= emit_call_insn (insn
);
37700 /* Note use of the TOC register. */
37701 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
37704 /* Return whether we need to always update the saved TOC pointer when we update
37705 the stack pointer. */
37708 rs6000_save_toc_in_prologue_p (void)
37710 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
37713 #ifdef HAVE_GAS_HIDDEN
37714 # define USE_HIDDEN_LINKONCE 1
37716 # define USE_HIDDEN_LINKONCE 0
37719 /* Fills in the label name that should be used for a 476 link stack thunk. */
37722 get_ppc476_thunk_name (char name
[32])
37724 gcc_assert (TARGET_LINK_STACK
);
37726 if (USE_HIDDEN_LINKONCE
)
37727 sprintf (name
, "__ppc476.get_thunk");
37729 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
37732 /* This function emits the simple thunk routine that is used to preserve
37733 the link stack on the 476 cpu. */
37735 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
37737 rs6000_code_end (void)
37742 if (!TARGET_LINK_STACK
)
37745 get_ppc476_thunk_name (name
);
37747 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
37748 build_function_type_list (void_type_node
, NULL_TREE
));
37749 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
37750 NULL_TREE
, void_type_node
);
37751 TREE_PUBLIC (decl
) = 1;
37752 TREE_STATIC (decl
) = 1;
37755 if (USE_HIDDEN_LINKONCE
&& !TARGET_XCOFF
)
37757 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
37758 targetm
.asm_out
.unique_section (decl
, 0);
37759 switch_to_section (get_named_section (decl
, NULL
, 0));
37760 DECL_WEAK (decl
) = 1;
37761 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
37762 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
37763 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
37764 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
37769 switch_to_section (text_section
);
37770 ASM_OUTPUT_LABEL (asm_out_file
, name
);
37773 DECL_INITIAL (decl
) = make_node (BLOCK
);
37774 current_function_decl
= decl
;
37775 allocate_struct_function (decl
, false);
37776 init_function_start (decl
);
37777 first_function_block_is_cold
= false;
37778 /* Make sure unwind info is emitted for the thunk if needed. */
37779 final_start_function (emit_barrier (), asm_out_file
, 1);
37781 fputs ("\tblr\n", asm_out_file
);
37783 final_end_function ();
37784 init_insn_lengths ();
37785 free_after_compilation (cfun
);
37787 current_function_decl
= NULL
;
37790 /* Add r30 to hard reg set if the prologue sets it up and it is not
37791 pic_offset_table_rtx. */
37794 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
37796 if (!TARGET_SINGLE_PIC_BASE
37798 && TARGET_MINIMAL_TOC
37799 && !constant_pool_empty_p ())
37800 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
37801 if (cfun
->machine
->split_stack_argp_used
)
37802 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
37806 /* Helper function for rs6000_split_logical to emit a logical instruction after
37807 spliting the operation to single GPR registers.
37809 DEST is the destination register.
37810 OP1 and OP2 are the input source registers.
37811 CODE is the base operation (AND, IOR, XOR, NOT).
37812 MODE is the machine mode.
37813 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37814 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37815 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37818 rs6000_split_logical_inner (rtx dest
,
37821 enum rtx_code code
,
37823 bool complement_final_p
,
37824 bool complement_op1_p
,
37825 bool complement_op2_p
)
37829 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
37830 if (op2
&& GET_CODE (op2
) == CONST_INT
37831 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
37832 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
37834 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
37835 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
37837 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
37842 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
37846 else if (value
== mask
)
37848 if (!rtx_equal_p (dest
, op1
))
37849 emit_insn (gen_rtx_SET (dest
, op1
));
37854 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
37855 into separate ORI/ORIS or XORI/XORIS instrucitons. */
37856 else if (code
== IOR
|| code
== XOR
)
37860 if (!rtx_equal_p (dest
, op1
))
37861 emit_insn (gen_rtx_SET (dest
, op1
));
37867 if (code
== AND
&& mode
== SImode
37868 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
37870 emit_insn (gen_andsi3 (dest
, op1
, op2
));
37874 if (complement_op1_p
)
37875 op1
= gen_rtx_NOT (mode
, op1
);
37877 if (complement_op2_p
)
37878 op2
= gen_rtx_NOT (mode
, op2
);
37880 /* For canonical RTL, if only one arm is inverted it is the first. */
37881 if (!complement_op1_p
&& complement_op2_p
)
37882 std::swap (op1
, op2
);
37884 bool_rtx
= ((code
== NOT
)
37885 ? gen_rtx_NOT (mode
, op1
)
37886 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
37888 if (complement_final_p
)
37889 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
37891 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
37894 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
37895 operations are split immediately during RTL generation to allow for more
37896 optimizations of the AND/IOR/XOR.
37898 OPERANDS is an array containing the destination and two input operands.
37899 CODE is the base operation (AND, IOR, XOR, NOT).
37900 MODE is the machine mode.
37901 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37902 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37903 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
37904 CLOBBER_REG is either NULL or a scratch register of type CC to allow
37905 formation of the AND instructions. */
37908 rs6000_split_logical_di (rtx operands
[3],
37909 enum rtx_code code
,
37910 bool complement_final_p
,
37911 bool complement_op1_p
,
37912 bool complement_op2_p
)
37914 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
37915 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
37916 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
37917 enum hi_lo
{ hi
= 0, lo
= 1 };
37918 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
37921 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
37922 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
37923 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
37924 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
37927 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
37930 if (GET_CODE (operands
[2]) != CONST_INT
)
37932 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
37933 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
37937 HOST_WIDE_INT value
= INTVAL (operands
[2]);
37938 HOST_WIDE_INT value_hi_lo
[2];
37940 gcc_assert (!complement_final_p
);
37941 gcc_assert (!complement_op1_p
);
37942 gcc_assert (!complement_op2_p
);
37944 value_hi_lo
[hi
] = value
>> 32;
37945 value_hi_lo
[lo
] = value
& lower_32bits
;
37947 for (i
= 0; i
< 2; i
++)
37949 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
37951 if (sub_value
& sign_bit
)
37952 sub_value
|= upper_32bits
;
37954 op2_hi_lo
[i
] = GEN_INT (sub_value
);
37956 /* If this is an AND instruction, check to see if we need to load
37957 the value in a register. */
37958 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
37959 && !and_operand (op2_hi_lo
[i
], SImode
))
37960 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
37965 for (i
= 0; i
< 2; i
++)
37967 /* Split large IOR/XOR operations. */
37968 if ((code
== IOR
|| code
== XOR
)
37969 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
37970 && !complement_final_p
37971 && !complement_op1_p
37972 && !complement_op2_p
37973 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
37975 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
37976 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
37977 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
37978 rtx tmp
= gen_reg_rtx (SImode
);
37980 /* Make sure the constant is sign extended. */
37981 if ((hi_16bits
& sign_bit
) != 0)
37982 hi_16bits
|= upper_32bits
;
37984 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
37985 code
, SImode
, false, false, false);
37987 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
37988 code
, SImode
, false, false, false);
37991 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
37992 code
, SImode
, complement_final_p
,
37993 complement_op1_p
, complement_op2_p
);
37999 /* Split the insns that make up boolean operations operating on multiple GPR
38000 registers. The boolean MD patterns ensure that the inputs either are
38001 exactly the same as the output registers, or there is no overlap.
38003 OPERANDS is an array containing the destination and two input operands.
38004 CODE is the base operation (AND, IOR, XOR, NOT).
38005 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38006 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38007 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38010 rs6000_split_logical (rtx operands
[3],
38011 enum rtx_code code
,
38012 bool complement_final_p
,
38013 bool complement_op1_p
,
38014 bool complement_op2_p
)
38016 machine_mode mode
= GET_MODE (operands
[0]);
38017 machine_mode sub_mode
;
38019 int sub_size
, regno0
, regno1
, nregs
, i
;
38021 /* If this is DImode, use the specialized version that can run before
38022 register allocation. */
38023 if (mode
== DImode
&& !TARGET_POWERPC64
)
38025 rs6000_split_logical_di (operands
, code
, complement_final_p
,
38026 complement_op1_p
, complement_op2_p
);
38032 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
38033 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
38034 sub_size
= GET_MODE_SIZE (sub_mode
);
38035 regno0
= REGNO (op0
);
38036 regno1
= REGNO (op1
);
38038 gcc_assert (reload_completed
);
38039 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38040 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38042 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
38043 gcc_assert (nregs
> 1);
38045 if (op2
&& REG_P (op2
))
38046 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38048 for (i
= 0; i
< nregs
; i
++)
38050 int offset
= i
* sub_size
;
38051 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
38052 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
38053 rtx sub_op2
= ((code
== NOT
)
38055 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
38057 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
38058 complement_final_p
, complement_op1_p
,
38066 /* Return true if the peephole2 can combine a load involving a combination of
38067 an addis instruction and a load with an offset that can be fused together on
38071 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
38072 rtx addis_value
, /* addis value. */
38073 rtx target
, /* target register that is loaded. */
38074 rtx mem
) /* bottom part of the memory addr. */
38079 /* Validate arguments. */
38080 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
38083 if (!base_reg_operand (target
, GET_MODE (target
)))
38086 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
38089 /* Allow sign/zero extension. */
38090 if (GET_CODE (mem
) == ZERO_EXTEND
38091 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
38092 mem
= XEXP (mem
, 0);
38097 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
38100 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
38101 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
38104 /* Validate that the register used to load the high value is either the
38105 register being loaded, or we can safely replace its use.
38107 This function is only called from the peephole2 pass and we assume that
38108 there are 2 instructions in the peephole (addis and load), so we want to
38109 check if the target register was not used in the memory address and the
38110 register to hold the addis result is dead after the peephole. */
38111 if (REGNO (addis_reg
) != REGNO (target
))
38113 if (reg_mentioned_p (target
, mem
))
38116 if (!peep2_reg_dead_p (2, addis_reg
))
38119 /* If the target register being loaded is the stack pointer, we must
38120 avoid loading any other value into it, even temporarily. */
38121 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
38125 base_reg
= XEXP (addr
, 0);
38126 return REGNO (addis_reg
) == REGNO (base_reg
);
38129 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38130 sequence. We adjust the addis register to use the target register. If the
38131 load sign extends, we adjust the code to do the zero extending load, and an
38132 explicit sign extension later since the fusion only covers zero extending
38136 operands[0] register set with addis (to be replaced with target)
38137 operands[1] value set via addis
38138 operands[2] target register being loaded
38139 operands[3] D-form memory reference using operands[0]. */
38142 expand_fusion_gpr_load (rtx
*operands
)
38144 rtx addis_value
= operands
[1];
38145 rtx target
= operands
[2];
38146 rtx orig_mem
= operands
[3];
38147 rtx new_addr
, new_mem
, orig_addr
, offset
;
38148 enum rtx_code plus_or_lo_sum
;
38149 machine_mode target_mode
= GET_MODE (target
);
38150 machine_mode extend_mode
= target_mode
;
38151 machine_mode ptr_mode
= Pmode
;
38152 enum rtx_code extend
= UNKNOWN
;
38154 if (GET_CODE (orig_mem
) == ZERO_EXTEND
38155 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
38157 extend
= GET_CODE (orig_mem
);
38158 orig_mem
= XEXP (orig_mem
, 0);
38159 target_mode
= GET_MODE (orig_mem
);
38162 gcc_assert (MEM_P (orig_mem
));
38164 orig_addr
= XEXP (orig_mem
, 0);
38165 plus_or_lo_sum
= GET_CODE (orig_addr
);
38166 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38168 offset
= XEXP (orig_addr
, 1);
38169 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38170 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38172 if (extend
!= UNKNOWN
)
38173 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
38175 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
38176 UNSPEC_FUSION_GPR
);
38177 emit_insn (gen_rtx_SET (target
, new_mem
));
38179 if (extend
== SIGN_EXTEND
)
38181 int sub_off
= ((BYTES_BIG_ENDIAN
)
38182 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
38185 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
38187 emit_insn (gen_rtx_SET (target
,
38188 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
38194 /* Emit the addis instruction that will be part of a fused instruction
38198 emit_fusion_addis (rtx target
, rtx addis_value
, const char *comment
,
38199 const char *mode_name
)
38202 char insn_template
[80];
38203 const char *addis_str
= NULL
;
38204 const char *comment_str
= ASM_COMMENT_START
;
38206 if (*comment_str
== ' ')
38209 /* Emit the addis instruction. */
38210 fuse_ops
[0] = target
;
38211 if (satisfies_constraint_L (addis_value
))
38213 fuse_ops
[1] = addis_value
;
38214 addis_str
= "lis %0,%v1";
38217 else if (GET_CODE (addis_value
) == PLUS
)
38219 rtx op0
= XEXP (addis_value
, 0);
38220 rtx op1
= XEXP (addis_value
, 1);
38222 if (REG_P (op0
) && CONST_INT_P (op1
)
38223 && satisfies_constraint_L (op1
))
38227 addis_str
= "addis %0,%1,%v2";
38231 else if (GET_CODE (addis_value
) == HIGH
)
38233 rtx value
= XEXP (addis_value
, 0);
38234 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
38236 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
38237 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
38239 addis_str
= "addis %0,%2,%1@toc@ha";
38241 else if (TARGET_XCOFF
)
38242 addis_str
= "addis %0,%1@u(%2)";
38245 gcc_unreachable ();
38248 else if (GET_CODE (value
) == PLUS
)
38250 rtx op0
= XEXP (value
, 0);
38251 rtx op1
= XEXP (value
, 1);
38253 if (GET_CODE (op0
) == UNSPEC
38254 && XINT (op0
, 1) == UNSPEC_TOCREL
38255 && CONST_INT_P (op1
))
38257 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
38258 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
38261 addis_str
= "addis %0,%2,%1+%3@toc@ha";
38263 else if (TARGET_XCOFF
)
38264 addis_str
= "addis %0,%1+%3@u(%2)";
38267 gcc_unreachable ();
38271 else if (satisfies_constraint_L (value
))
38273 fuse_ops
[1] = value
;
38274 addis_str
= "lis %0,%v1";
38277 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
38279 fuse_ops
[1] = value
;
38280 addis_str
= "lis %0,%1@ha";
38285 fatal_insn ("Could not generate addis value for fusion", addis_value
);
38287 sprintf (insn_template
, "%s\t\t%s %s, type %s", addis_str
, comment_str
,
38288 comment
, mode_name
);
38289 output_asm_insn (insn_template
, fuse_ops
);
38292 /* Emit a D-form load or store instruction that is the second instruction
38293 of a fusion sequence. */
38296 emit_fusion_load_store (rtx load_store_reg
, rtx addis_reg
, rtx offset
,
38297 const char *insn_str
)
38300 char insn_template
[80];
38302 fuse_ops
[0] = load_store_reg
;
38303 fuse_ops
[1] = addis_reg
;
38305 if (CONST_INT_P (offset
) && satisfies_constraint_I (offset
))
38307 sprintf (insn_template
, "%s %%0,%%2(%%1)", insn_str
);
38308 fuse_ops
[2] = offset
;
38309 output_asm_insn (insn_template
, fuse_ops
);
38312 else if (GET_CODE (offset
) == UNSPEC
38313 && XINT (offset
, 1) == UNSPEC_TOCREL
)
38316 sprintf (insn_template
, "%s %%0,%%2@toc@l(%%1)", insn_str
);
38318 else if (TARGET_XCOFF
)
38319 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38322 gcc_unreachable ();
38324 fuse_ops
[2] = XVECEXP (offset
, 0, 0);
38325 output_asm_insn (insn_template
, fuse_ops
);
38328 else if (GET_CODE (offset
) == PLUS
38329 && GET_CODE (XEXP (offset
, 0)) == UNSPEC
38330 && XINT (XEXP (offset
, 0), 1) == UNSPEC_TOCREL
38331 && CONST_INT_P (XEXP (offset
, 1)))
38333 rtx tocrel_unspec
= XEXP (offset
, 0);
38335 sprintf (insn_template
, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str
);
38337 else if (TARGET_XCOFF
)
38338 sprintf (insn_template
, "%s %%0,%%2+%%3@l(%%1)", insn_str
);
38341 gcc_unreachable ();
38343 fuse_ops
[2] = XVECEXP (tocrel_unspec
, 0, 0);
38344 fuse_ops
[3] = XEXP (offset
, 1);
38345 output_asm_insn (insn_template
, fuse_ops
);
38348 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (offset
))
38350 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38352 fuse_ops
[2] = offset
;
38353 output_asm_insn (insn_template
, fuse_ops
);
38357 fatal_insn ("Unable to generate load/store offset for fusion", offset
);
38362 /* Wrap a TOC address that can be fused to indicate that special fusion
38363 processing is needed. */
38366 fusion_wrap_memory_address (rtx old_mem
)
38368 rtx old_addr
= XEXP (old_mem
, 0);
38369 rtvec v
= gen_rtvec (1, old_addr
);
38370 rtx new_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_FUSION_ADDIS
);
38371 return replace_equiv_address_nv (old_mem
, new_addr
, false);
38374 /* Given an address, convert it into the addis and load offset parts. Addresses
38375 created during the peephole2 process look like:
38376 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38377 (unspec [(...)] UNSPEC_TOCREL))
38379 Addresses created via toc fusion look like:
38380 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38383 fusion_split_address (rtx addr
, rtx
*p_hi
, rtx
*p_lo
)
38387 if (GET_CODE (addr
) == UNSPEC
&& XINT (addr
, 1) == UNSPEC_FUSION_ADDIS
)
38389 lo
= XVECEXP (addr
, 0, 0);
38390 hi
= gen_rtx_HIGH (Pmode
, lo
);
38392 else if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
38394 hi
= XEXP (addr
, 0);
38395 lo
= XEXP (addr
, 1);
38398 gcc_unreachable ();
38404 /* Return a string to fuse an addis instruction with a gpr load to the same
38405 register that we loaded up the addis instruction. The address that is used
38406 is the logical address that was formed during peephole2:
38407 (lo_sum (high) (low-part))
38409 Or the address is the TOC address that is wrapped before register allocation:
38410 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38412 The code is complicated, so we call output_asm_insn directly, and just
38416 emit_fusion_gpr_load (rtx target
, rtx mem
)
38421 const char *load_str
= NULL
;
38422 const char *mode_name
= NULL
;
38425 if (GET_CODE (mem
) == ZERO_EXTEND
)
38426 mem
= XEXP (mem
, 0);
38428 gcc_assert (REG_P (target
) && MEM_P (mem
));
38430 addr
= XEXP (mem
, 0);
38431 fusion_split_address (addr
, &addis_value
, &load_offset
);
38433 /* Now emit the load instruction to the same register. */
38434 mode
= GET_MODE (mem
);
38438 mode_name
= "char";
38443 mode_name
= "short";
38449 mode_name
= (mode
== SFmode
) ? "float" : "int";
38455 gcc_assert (TARGET_POWERPC64
);
38456 mode_name
= (mode
== DFmode
) ? "double" : "long";
38461 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target
, mem
));
38464 /* Emit the addis instruction. */
38465 emit_fusion_addis (target
, addis_value
, "gpr load fusion", mode_name
);
38467 /* Emit the D-form load instruction. */
38468 emit_fusion_load_store (target
, target
, load_offset
, load_str
);
38474 /* Return true if the peephole2 can combine a load/store involving a
38475 combination of an addis instruction and the memory operation. This was
38476 added to the ISA 3.0 (power9) hardware. */
38479 fusion_p9_p (rtx addis_reg
, /* register set via addis. */
38480 rtx addis_value
, /* addis value. */
38481 rtx dest
, /* destination (memory or register). */
38482 rtx src
) /* source (register or memory). */
38484 rtx addr
, mem
, offset
;
38485 machine_mode mode
= GET_MODE (src
);
38487 /* Validate arguments. */
38488 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
38491 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
38494 /* Ignore extend operations that are part of the load. */
38495 if (GET_CODE (src
) == FLOAT_EXTEND
|| GET_CODE (src
) == ZERO_EXTEND
)
38496 src
= XEXP (src
, 0);
38498 /* Test for memory<-register or register<-memory. */
38499 if (fpr_reg_operand (src
, mode
) || int_reg_operand (src
, mode
))
38507 else if (MEM_P (src
))
38509 if (!fpr_reg_operand (dest
, mode
) && !int_reg_operand (dest
, mode
))
38518 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
38519 if (GET_CODE (addr
) == PLUS
)
38521 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
38524 return satisfies_constraint_I (XEXP (addr
, 1));
38527 else if (GET_CODE (addr
) == LO_SUM
)
38529 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
38532 offset
= XEXP (addr
, 1);
38533 if (TARGET_XCOFF
|| (TARGET_ELF
&& TARGET_POWERPC64
))
38534 return small_toc_ref (offset
, GET_MODE (offset
));
38536 else if (TARGET_ELF
&& !TARGET_POWERPC64
)
38537 return CONSTANT_P (offset
);
38543 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38547 operands[0] register set with addis
38548 operands[1] value set via addis
38549 operands[2] target register being loaded
38550 operands[3] D-form memory reference using operands[0].
38552 This is similar to the fusion introduced with power8, except it scales to
38553 both loads/stores and does not require the result register to be the same as
38554 the base register. At the moment, we only do this if register set with addis
38558 expand_fusion_p9_load (rtx
*operands
)
38560 rtx tmp_reg
= operands
[0];
38561 rtx addis_value
= operands
[1];
38562 rtx target
= operands
[2];
38563 rtx orig_mem
= operands
[3];
38564 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
;
38565 enum rtx_code plus_or_lo_sum
;
38566 machine_mode target_mode
= GET_MODE (target
);
38567 machine_mode extend_mode
= target_mode
;
38568 machine_mode ptr_mode
= Pmode
;
38569 enum rtx_code extend
= UNKNOWN
;
38571 if (GET_CODE (orig_mem
) == FLOAT_EXTEND
|| GET_CODE (orig_mem
) == ZERO_EXTEND
)
38573 extend
= GET_CODE (orig_mem
);
38574 orig_mem
= XEXP (orig_mem
, 0);
38575 target_mode
= GET_MODE (orig_mem
);
38578 gcc_assert (MEM_P (orig_mem
));
38580 orig_addr
= XEXP (orig_mem
, 0);
38581 plus_or_lo_sum
= GET_CODE (orig_addr
);
38582 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38584 offset
= XEXP (orig_addr
, 1);
38585 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38586 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38588 if (extend
!= UNKNOWN
)
38589 new_mem
= gen_rtx_fmt_e (extend
, extend_mode
, new_mem
);
38591 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
38594 set
= gen_rtx_SET (target
, new_mem
);
38595 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
38596 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
38602 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38606 operands[0] register set with addis
38607 operands[1] value set via addis
38608 operands[2] target D-form memory being stored to
38609 operands[3] register being stored
38611 This is similar to the fusion introduced with power8, except it scales to
38612 both loads/stores and does not require the result register to be the same as
38613 the base register. At the moment, we only do this if register set with addis
38617 expand_fusion_p9_store (rtx
*operands
)
38619 rtx tmp_reg
= operands
[0];
38620 rtx addis_value
= operands
[1];
38621 rtx orig_mem
= operands
[2];
38622 rtx src
= operands
[3];
38623 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
, new_src
;
38624 enum rtx_code plus_or_lo_sum
;
38625 machine_mode target_mode
= GET_MODE (orig_mem
);
38626 machine_mode ptr_mode
= Pmode
;
38628 gcc_assert (MEM_P (orig_mem
));
38630 orig_addr
= XEXP (orig_mem
, 0);
38631 plus_or_lo_sum
= GET_CODE (orig_addr
);
38632 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38634 offset
= XEXP (orig_addr
, 1);
38635 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38636 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38638 new_src
= gen_rtx_UNSPEC (target_mode
, gen_rtvec (1, src
),
38641 set
= gen_rtx_SET (new_mem
, new_src
);
38642 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
38643 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
38649 /* Return a string to fuse an addis instruction with a load using extended
38650 fusion. The address that is used is the logical address that was formed
38651 during peephole2: (lo_sum (high) (low-part))
38653 The code is complicated, so we call output_asm_insn directly, and just
38657 emit_fusion_p9_load (rtx reg
, rtx mem
, rtx tmp_reg
)
38659 machine_mode mode
= GET_MODE (reg
);
38663 const char *load_string
;
38666 if (GET_CODE (mem
) == FLOAT_EXTEND
|| GET_CODE (mem
) == ZERO_EXTEND
)
38668 mem
= XEXP (mem
, 0);
38669 mode
= GET_MODE (mem
);
38672 if (GET_CODE (reg
) == SUBREG
)
38674 gcc_assert (SUBREG_BYTE (reg
) == 0);
38675 reg
= SUBREG_REG (reg
);
38679 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg
);
38682 if (FP_REGNO_P (r
))
38684 if (mode
== SFmode
)
38685 load_string
= "lfs";
38686 else if (mode
== DFmode
|| mode
== DImode
)
38687 load_string
= "lfd";
38689 gcc_unreachable ();
38691 else if (ALTIVEC_REGNO_P (r
) && TARGET_P9_DFORM_SCALAR
)
38693 if (mode
== SFmode
)
38694 load_string
= "lxssp";
38695 else if (mode
== DFmode
|| mode
== DImode
)
38696 load_string
= "lxsd";
38698 gcc_unreachable ();
38700 else if (INT_REGNO_P (r
))
38705 load_string
= "lbz";
38708 load_string
= "lhz";
38712 load_string
= "lwz";
38716 if (!TARGET_POWERPC64
)
38717 gcc_unreachable ();
38718 load_string
= "ld";
38721 gcc_unreachable ();
38725 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg
);
38728 fatal_insn ("emit_fusion_p9_load not MEM", mem
);
38730 addr
= XEXP (mem
, 0);
38731 fusion_split_address (addr
, &hi
, &lo
);
38733 /* Emit the addis instruction. */
38734 emit_fusion_addis (tmp_reg
, hi
, "power9 load fusion", GET_MODE_NAME (mode
));
38736 /* Emit the D-form load instruction. */
38737 emit_fusion_load_store (reg
, tmp_reg
, lo
, load_string
);
38742 /* Return a string to fuse an addis instruction with a store using extended
38743 fusion. The address that is used is the logical address that was formed
38744 during peephole2: (lo_sum (high) (low-part))
38746 The code is complicated, so we call output_asm_insn directly, and just
38750 emit_fusion_p9_store (rtx mem
, rtx reg
, rtx tmp_reg
)
38752 machine_mode mode
= GET_MODE (reg
);
38756 const char *store_string
;
38759 if (GET_CODE (reg
) == SUBREG
)
38761 gcc_assert (SUBREG_BYTE (reg
) == 0);
38762 reg
= SUBREG_REG (reg
);
38766 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg
);
38769 if (FP_REGNO_P (r
))
38771 if (mode
== SFmode
)
38772 store_string
= "stfs";
38773 else if (mode
== DFmode
)
38774 store_string
= "stfd";
38776 gcc_unreachable ();
38778 else if (ALTIVEC_REGNO_P (r
) && TARGET_P9_DFORM_SCALAR
)
38780 if (mode
== SFmode
)
38781 store_string
= "stxssp";
38782 else if (mode
== DFmode
|| mode
== DImode
)
38783 store_string
= "stxsd";
38785 gcc_unreachable ();
38787 else if (INT_REGNO_P (r
))
38792 store_string
= "stb";
38795 store_string
= "sth";
38799 store_string
= "stw";
38803 if (!TARGET_POWERPC64
)
38804 gcc_unreachable ();
38805 store_string
= "std";
38808 gcc_unreachable ();
38812 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg
);
38815 fatal_insn ("emit_fusion_p9_store not MEM", mem
);
38817 addr
= XEXP (mem
, 0);
38818 fusion_split_address (addr
, &hi
, &lo
);
38820 /* Emit the addis instruction. */
38821 emit_fusion_addis (tmp_reg
, hi
, "power9 store fusion", GET_MODE_NAME (mode
));
38823 /* Emit the D-form load instruction. */
38824 emit_fusion_load_store (reg
, tmp_reg
, lo
, store_string
);
38829 #ifdef RS6000_GLIBC_ATOMIC_FENV
38830 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38831 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
38834 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38837 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
38839 if (!TARGET_HARD_FLOAT
)
38841 #ifdef RS6000_GLIBC_ATOMIC_FENV
38842 if (atomic_hold_decl
== NULL_TREE
)
38845 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38846 get_identifier ("__atomic_feholdexcept"),
38847 build_function_type_list (void_type_node
,
38848 double_ptr_type_node
,
38850 TREE_PUBLIC (atomic_hold_decl
) = 1;
38851 DECL_EXTERNAL (atomic_hold_decl
) = 1;
38854 if (atomic_clear_decl
== NULL_TREE
)
38857 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38858 get_identifier ("__atomic_feclearexcept"),
38859 build_function_type_list (void_type_node
,
38861 TREE_PUBLIC (atomic_clear_decl
) = 1;
38862 DECL_EXTERNAL (atomic_clear_decl
) = 1;
38865 tree const_double
= build_qualified_type (double_type_node
,
38867 tree const_double_ptr
= build_pointer_type (const_double
);
38868 if (atomic_update_decl
== NULL_TREE
)
38871 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38872 get_identifier ("__atomic_feupdateenv"),
38873 build_function_type_list (void_type_node
,
38876 TREE_PUBLIC (atomic_update_decl
) = 1;
38877 DECL_EXTERNAL (atomic_update_decl
) = 1;
38880 tree fenv_var
= create_tmp_var_raw (double_type_node
);
38881 TREE_ADDRESSABLE (fenv_var
) = 1;
38882 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
38884 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
38885 *clear
= build_call_expr (atomic_clear_decl
, 0);
38886 *update
= build_call_expr (atomic_update_decl
, 1,
38887 fold_convert (const_double_ptr
, fenv_addr
));
38892 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
38893 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
38894 tree call_mffs
= build_call_expr (mffs
, 0);
38896 /* Generates the equivalent of feholdexcept (&fenv_var)
38898 *fenv_var = __builtin_mffs ();
38900 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38901 __builtin_mtfsf (0xff, fenv_hold); */
38903 /* Mask to clear everything except for the rounding modes and non-IEEE
38904 arithmetic flag. */
38905 const unsigned HOST_WIDE_INT hold_exception_mask
=
38906 HOST_WIDE_INT_C (0xffffffff00000007);
38908 tree fenv_var
= create_tmp_var_raw (double_type_node
);
38910 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
38912 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
38913 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
38914 build_int_cst (uint64_type_node
,
38915 hold_exception_mask
));
38917 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38920 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
38921 build_int_cst (unsigned_type_node
, 0xff),
38924 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
38926 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38928 double fenv_clear = __builtin_mffs ();
38929 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38930 __builtin_mtfsf (0xff, fenv_clear); */
38932 /* Mask to clear everything except for the rounding modes and non-IEEE
38933 arithmetic flag. */
38934 const unsigned HOST_WIDE_INT clear_exception_mask
=
38935 HOST_WIDE_INT_C (0xffffffff00000000);
38937 tree fenv_clear
= create_tmp_var_raw (double_type_node
);
38939 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
38941 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
38942 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
38944 build_int_cst (uint64_type_node
,
38945 clear_exception_mask
));
38947 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38948 fenv_clear_llu_and
);
38950 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
38951 build_int_cst (unsigned_type_node
, 0xff),
38954 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
38956 /* Generates the equivalent of feupdateenv (&fenv_var)
38958 double old_fenv = __builtin_mffs ();
38959 double fenv_update;
38960 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38961 (*(uint64_t*)fenv_var 0x1ff80fff);
38962 __builtin_mtfsf (0xff, fenv_update); */
38964 const unsigned HOST_WIDE_INT update_exception_mask
=
38965 HOST_WIDE_INT_C (0xffffffff1fffff00);
38966 const unsigned HOST_WIDE_INT new_exception_mask
=
38967 HOST_WIDE_INT_C (0x1ff80fff);
38969 tree old_fenv
= create_tmp_var_raw (double_type_node
);
38970 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
38972 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
38973 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
38974 build_int_cst (uint64_type_node
,
38975 update_exception_mask
));
38977 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
38978 build_int_cst (uint64_type_node
,
38979 new_exception_mask
));
38981 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
38982 old_llu_and
, new_llu_and
);
38984 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38987 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
38988 build_int_cst (unsigned_type_node
, 0xff),
38989 fenv_update_mtfsf
);
38991 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
38995 rs6000_generate_float2_code (bool signed_convert
, rtx dst
, rtx src1
, rtx src2
)
38997 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38999 rtx_tmp0
= gen_reg_rtx (V2DImode
);
39000 rtx_tmp1
= gen_reg_rtx (V2DImode
);
39002 /* The destination of the vmrgew instruction layout is:
39003 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39004 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39005 vmrgew instruction will be correct. */
39006 if (VECTOR_ELT_ORDER_BIG
)
39008 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
39009 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
39013 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
39014 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
39017 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
39018 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
39020 if (signed_convert
)
39022 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2
, rtx_tmp0
));
39023 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3
, rtx_tmp1
));
39027 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2
, rtx_tmp0
));
39028 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3
, rtx_tmp1
));
39031 if (VECTOR_ELT_ORDER_BIG
)
39032 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
39034 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
39038 rs6000_generate_vsigned2_code (bool signed_convert
, rtx dst
, rtx src1
,
39041 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
39043 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
39044 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
39046 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
39047 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
39049 rtx_tmp2
= gen_reg_rtx (V4SImode
);
39050 rtx_tmp3
= gen_reg_rtx (V4SImode
);
39052 if (signed_convert
)
39054 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2
, rtx_tmp0
));
39055 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3
, rtx_tmp1
));
39059 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2
, rtx_tmp0
));
39060 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3
, rtx_tmp1
));
39063 emit_insn (gen_p8_vmrgew_v4si (dst
, rtx_tmp2
, rtx_tmp3
));
39066 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39069 rs6000_optab_supported_p (int op
, machine_mode mode1
, machine_mode
,
39070 optimization_type opt_type
)
39075 return (opt_type
== OPTIMIZE_FOR_SPEED
39076 && RS6000_RECIP_AUTO_RSQRTE_P (mode1
));
39083 struct gcc_target targetm
= TARGET_INITIALIZER
;
39085 #include "gt-rs6000.h"