gcc/ChangeLog

   1 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
   2
   3         PR tree-optimization/110199
   4         * tree-ssa-scopedtables.cc
   5         (avail_exprs_stack::simplify_binary_operation): Generalize handling
   6         of MIN_EXPR/MAX_EXPR to allow additional simplifications.  Canonicalize
   7         comparison operands for other cases.
   8
   9 2024-03-10  Pan Li  <pan2.li@intel.com>
  10
  11         * tree-vect-stmts.cc (vectorizable_store): Enable the assert
  12         during transform process.
  13         (vectorizable_load): Ditto.
  14
  15 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
  16
  17         PR target/102250
  18         * doc/install.texi: Document need for python when building
  19         RISC-V compilers.
  20
  21 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
  22
  23         PR target/111362
  24         * mode-switching.cc (optimize_mode_switching): Only process
  25         NONDEBUG insns.
  26
  27 2024-03-09  Georg-Johann Lay  <avr@gjlay.de>
  28
  29         * config/avr/avr.md: Fix typos in comment, indentation glitches
  30         and some other nits.
  31
  32 2024-03-09  Jakub Jelinek  <jakub@redhat.com>
  33
  34         PR target/114284
  35         * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
  36         src containing MEMs unless prop.likely_profitable_p ().
  37
  38 2024-03-09  Xi Ruoyao  <xry111@xry111.site>
  39
  40         * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
  41         Support 'Q' for R_LARCH_RELAX for TLS IE.
  42         (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
  43         IE.
  44         * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
  45
  46 2024-03-09  Georg-Johann Lay  <avr@gjlay.de>
  47
  48         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
  49         usum_widenqihi and add_zero_extend1.
  50         [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
  51         sub+sign_extend.
  52         * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
  53         Compute exact insn lengths.
  54         (*usum_widenqihi3): Allow input operands to commute.
  55
  56 2024-03-09  Jakub Jelinek  <jakub@redhat.com>
  57
  58         * config/i386/i386.opt.urls: Regenerate.
  59
  60 2024-03-09  Lulu Cheng  <chenglulu@loongson.cn>
  61
  62         * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
  63         In loongarch64, a sign extension operation is added when
  64         operands[2] is a register operand and the mode is SImode.
  65
  66 2024-03-08  Martin Jambor  <mjambor@suse.cz>
  67
  68         PR ipa/113757
  69         * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
  70         id->killed_new_ssa_names.
  71
  72 2024-03-08  Vladimir N. Makarov  <vmakarov@redhat.com>
  73
  74         PR target/113790
  75         * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
  76         for non-reload pseudo too.
  77
  78 2024-03-08  David Faust  <david.faust@oracle.com>
  79
  80         * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
  81         not attempt inline expansion if size is above threshold.
  82         * config/bpf/bpf.opt (-minline-memops-threshold): New option.
  83         * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
  84         Document.
  85
  86 2024-03-08  Richard Biener  <rguenther@suse.de>
  87
  88         PR tree-optimization/114269
  89         PR tree-optimization/114074
  90         * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
  91         in the third CASE_CONVERT case as well.
  92         (chrec_fold_multiply): Handle sign-conversions from unsigned
  93         by performing the operation in the unsigned type.
  94
  95 2024-03-08  Georg-Johann Lay  <avr@gjlay.de>
  96
  97         * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
  98         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
  99
 100 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
 101
 102         * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
 103         asm_noperands < 0 means it is not asm goto too.
 104
 105 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
 106
 107         PR target/38534
 108         * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
 109         option.
 110         * config/i386/i386-options.cc (ix86_set_func_type): Don't use
 111         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
 112         ix86_noreturn_no_callee_saved_registers is enabled.
 113         * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
 114
 115 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
 116
 117         PR debug/113918
 118         * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
 119         on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
 120
 121 2024-03-08  demin.han  <demin.han@starfivetech.com>
 122
 123         PR target/114264
 124         * config/riscv/riscv-vector-costs.cc: Fix ICE
 125
 126 2024-03-08  Haochen Gui  <guihaoc@gcc.gnu.org>
 127
 128         * fwprop.cc (forward_propagate_into): Return false for volatile set
 129         source rtx.
 130
 131 2024-03-07  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 132
 133         PR target/113618
 134         * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
 135         (aarch64_expand_cpymem): Emit single load/store only.
 136         (aarch64_set_one_block): Emit single stores only.
 137
 138 2024-03-07  Robin Dapp  <rdapp@ventanamicro.com>
 139
 140         PR middle-end/114196
 141         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
 142         vectorization guards.
 143
 144 2024-03-07  Jonathan Wakely  <jwakely@redhat.com>
 145
 146         * doc/cppopts.texi: Remove incorrect claim about -dD not
 147         outputting predefined macros.
 148
 149 2024-03-07  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
 150
 151         PR target/113950
 152         * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
 153         and simplify else if with else.
 154
 155 2024-03-07  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
 156
 157         * system.h: Include safe-ctype.h after C++ standard headers.
 158
 159 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
 160
 161         PR rtl-optimization/110079
 162         * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
 163         asm goto.
 164
 165 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
 166
 167         PR middle-end/105533
 168         * expmed.cc (choose_mult_variant): Only try the val - 1 variant
 169         if val is not HOST_WIDE_INT_MIN or if mode has exactly
 170         HOST_BITS_PER_WIDE_INT precision.  Avoid triggering UB while computing
 171         val - 1.
 172
 173 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
 174
 175         PR middle-end/105533
 176         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
 177         Multiple op->off by BITS_PER_UNIT instead of shifting it left by
 178         LOG2_BITS_PER_UNIT.
 179
 180 2024-03-07  Yang Yujie  <yangyujie@loongson.cn>
 181
 182         * config.gcc: Add a case for loongarch*-*-linux-musl*.
 183         * config/loongarch/linux.h: Disable the multilib-compatible
 184         treatment for *musl* targets.
 185         * config/loongarch/musl.h: New file.
 186
 187 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
 188
 189         PR tree-optimization/114009
 190         * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
 191         argument even for GENERIC, not just for GIMPLE.
 192         * match.pd (a * !a -> 0): New simplifications.
 193
 194 2024-03-07  demin.han  <demin.han@starfivetech.com>
 195
 196         * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
 197         * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
 198         (expand_vec_cmp_float): Adapt arguments
 199
 200 2024-03-06  Uros Bizjak  <ubizjak@gmail.com>
 201
 202         PR target/114232
 203         * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
 204         of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
 205         (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
 206         (<plusminus:insn>v2qi3): Enable for optimize_size instead
 207         of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
 208         (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
 209         (<any_shift:insn>v2qi3): Enable for optimize_size instead
 210         of optimize_function_for_size_p.
 211
 212 2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>
 213
 214         PR target/114200
 215         PR target/114202
 216         * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
 217
 218 2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>
 219
 220         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
 221         (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
 222         offset handling.
 223         (costs::add_stmt_cost): Also adjust cost for statements without
 224         stmt_info.
 225         * config/riscv/riscv-vector-costs.h: Define zero constant.
 226
 227 2024-03-06  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 228
 229         PR target/113915
 230         * config/arm/arm.md (NOCOND): Improve comment.
 231         (arm_rev*) Add predicable.
 232         * config/arm/arm.cc (arm_final_prescan_insn): Add check for
 233         PREDICABLE_YES.
 234
 235 2024-03-06  Jeff Law  <jlaw@ventanamicro.com>
 236
 237         PR target/113001
 238         PR target/112871
 239         * config/riscv/riscv.cc (expand_conditional_move): Do not swap
 240         operands when the comparison operand is the same as the false
 241         arm for a NE test.
 242
 243 2024-03-06  Uros Bizjak  <ubizjak@gmail.com>
 244
 245         * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
 246         Eliminate common code and use generic code instead.
 247
 248 2024-03-06  Georg-Johann Lay  <avr@gjlay.de>
 249
 250         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
 251         rtx cost.
 252
 253 2024-03-06  Richard Biener  <rguenther@suse.de>
 254
 255         PR tree-optimization/114239
 256         * tree-vect-loop.cc (vect_get_vect_def): Remove.
 257         (vect_create_epilog_for_reduction): The passed in stmt_info
 258         should now be the live stmt that produces the scalar reduction
 259         result.  Revert PR114192 fix.  Base reduction info off
 260         info_for_reduction.  Remove special handling of
 261         early-break/peeled, restore original vector def gathering.
 262         Make sure to pick the correct exit PHIs.
 263         (vectorizable_live_operation): Pass in the proper stmt_info
 264         for early break exits.
 265
 266 2024-03-06  Richard Sandiford  <richard.sandiford@arm.com>
 267
 268         * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
 269         out-of-class definitions of static constants.
 270
 271 2024-03-06  Richard Biener  <rguenther@suse.de>
 272
 273         PR tree-optimization/114249
 274         * tree-vect-slp.cc (vect_build_slp_instance): Move making
 275         a BB reduction lane number even ...
 276         (vect_slp_check_for_roots): ... here to avoid leaking
 277         pattern defs.
 278
 279 2024-03-06  Richard Biener  <rguenther@suse.de>
 280
 281         PR tree-optimization/114246
 282         * tree-ssa-dse.cc (increment_start_addr): Strip useless
 283         type conversions from the adjusted address.
 284
 285 2024-03-06  Jakub Jelinek  <jakub@redhat.com>
 286
 287         PR rtl-optimization/114190
 288         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
 289         Call df_remove_problem for df_note before calling df_analyze.
 290
 291 2024-03-05  Cupertino Miranda  <cupertino.miranda@oracle.com>
 292             Indu Bhagat  <indu.bhagat@oracle.com>
 293
 294         PR debug/114186
 295         * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
 296         in the correct order of the dimensions.
 297         (gen_ctf_subrange_type): Refactor out handling of
 298         DW_TAG_subrange_type DIE to here.
 299
 300 2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>
 301
 302         PR sanitizer/97696
 303         * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
 304
 305 2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>
 306
 307         * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
 308         and luti_strided.
 309         * config/aarch64/aarch64-sme.md
 310         (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
 311         (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
 312         (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
 313         * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
 314         (early_ra::maybe_convert_to_strided_access): Remove support for
 315         strided LUTI2 and LUTI4.
 316
 317 2024-03-05  Richard Earnshaw  <rearnsha@arm.com>
 318
 319         PR target/113510
 320         * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
 321         low_register_operand.
 322
 323 2024-03-05  Georg-Johann Lay  <avr@gjlay.de>
 324
 325         * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
 326         in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
 327         to "X = Y, X o= CST".
 328
 329 2024-03-05  Xi Ruoyao  <xry111@xry111.site>
 330
 331         * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
 332         s9 as an alias of r22.
 333
 334 2024-03-05  Roger Sayle  <roger@nextmovesoftware.com>
 335
 336         * config/avr/avr-protos.h (avr_out_insv): New proto.
 337         * config/avr/avr.cc (avr_out_insv): New function.
 338         (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
 339         (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
 340         * config/avr/avr.md (define_attr "adjust_len") Add insv.
 341         (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
 342         Add constraint alternative where the 3rd operand is a power
 343         of 2, and the source register may differ from the destination.
 344         (*insv.any_shift.<mode>_split): Call avr_out_insv to output
 345         instructions.  Set attr "length" to "insv".
 346         * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
 347
 348 2024-03-05  Richard Biener  <rguenther@suse.de>
 349
 350         PR tree-optimization/114231
 351         * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
 352         processing a BB SLP root.
 353
 354 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
 355
 356         PR rtl-optimization/114211
 357         * lower-subreg.cc (resolve_simple_move): For double-word
 358         rotates by BITS_PER_WORD if there is overlap between source
 359         and destination use a temporary.
 360
 361 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
 362
 363         PR middle-end/114157
 364         * gimple-lower-bitint.cc: Include stor-layout.h.
 365         (mergeable_op): Return true for BIT_FIELD_REF.
 366         (struct bitint_large_huge): Declare handle_bit_field_ref method.
 367         (bitint_large_huge::handle_bit_field_ref): New method.
 368         (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
 369
 370 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
 371
 372         PR target/114116
 373         * config/i386/i386.h (enum call_saved_registers_type): Add
 374         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
 375         * config/i386/i386-options.cc (ix86_set_func_type): Remove
 376         has_no_callee_saved_registers variable, add no_callee_saved_registers
 377         instead, initialize it depending on whether it is
 378         no_callee_saved_registers function or not.  Don't set it if
 379         no_caller_saved_registers attribute is present.  Adjust users.
 380         * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
 381         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
 382         TYPE_NO_CALLEE_SAVED_REGISTERS.
 383         (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
 384
 385 2024-03-05  Pan Li  <pan2.li@intel.com>
 386
 387         * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
 388         mode_size related code.
 389
 390 2024-03-05  Patrick Palka  <ppalka@redhat.com>
 391
 392         * doc/invoke.texi (-Wno-global-module): Document.
 393
 394 2024-03-04  David Faust  <david.faust@oracle.com>
 395
 396         * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
 397         * config/bpf/bpf.cc (bpf_expand_setmem): New.
 398         * config/bpf/bpf.md (setmemdi): New define_expand.
 399
 400 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
 401
 402         PR rtl-optimization/113010
 403         * combine.cc (simplify_comparison): Guard the
 404         WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
 405         and initialize inner_mode.
 406
 407 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 408
 409         * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
 410         VMLALDAVAXQ_U cases.
 411         (VMLALDAVXQ): Remove iterator.
 412         (VMLALDAVXQ_P): Likewise.
 413         (VMLALDAVAXQ): Likewise.
 414         * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
 415         mode iterator attribute with V4BI mode.
 416         * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
 417         VMLALDAVAXQ_U): Remove unused unspecs.
 418
 419 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 420
 421         * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
 422         * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
 423         attribute.
 424         * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
 425         vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
 426         vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
 427         vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
 428         vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
 429         vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
 430         vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
 431         vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
 432         vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
 433         vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
 434
 435 2024-03-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 436
 437         * config/arm/arm.md (mve_unpredicated_insn): New attribute.
 438         * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
 439         (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
 440         (MVE_VPT_PREDICABLE_INSN_P): Likewise.
 441         * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
 442         * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
 443         (arm_vcx1q<a>v16qi): Likewise.
 444         (arm_vcx1qav16qi): Likewise.
 445         (arm_vcx1qv16qi): Likewise.
 446         (arm_vcx2q<a>_p_v16qi): Likewise.
 447         (arm_vcx2q<a>v16qi): Likewise.
 448         (arm_vcx2qav16qi): Likewise.
 449         (arm_vcx2qv16qi): Likewise.
 450         (arm_vcx3q<a>_p_v16qi): Likewise.
 451         (arm_vcx3q<a>v16qi): Likewise.
 452         (arm_vcx3qav16qi): Likewise.
 453         (arm_vcx3qv16qi): Likewise.
 454         (@mve_<mve_insn>q_<supf><mode>): Likewise.
 455         (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
 456         (@mve_<mve_insn>q_<supf>v4si): Likewise.
 457         (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
 458         (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
 459         (@mve_<mve_insn>q_f<mode>): Likewise.
 460         (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
 461         (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
 462         (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
 463         (@mve_<mve_insn>q_m_f<mode>): Likewise.
 464         (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
 465         (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
 466         (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
 467         (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
 468         (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
 469         (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
 470         (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
 471         (mve_v<absneg_str>q_f<mode>): Likewise.
 472         (mve_<mve_addsubmul>q<mode>): Likewise.
 473         (mve_<mve_addsubmul>q_f<mode>): Likewise.
 474         (mve_vadciq_<supf>v4si): Likewise.
 475         (mve_vadciq_m_<supf>v4si): Likewise.
 476         (mve_vadcq_<supf>v4si): Likewise.
 477         (mve_vadcq_m_<supf>v4si): Likewise.
 478         (mve_vandq_<supf><mode>): Likewise.
 479         (mve_vandq_f<mode>): Likewise.
 480         (mve_vandq_m_<supf><mode>): Likewise.
 481         (mve_vandq_m_f<mode>): Likewise.
 482         (mve_vandq_s<mode>): Likewise.
 483         (mve_vandq_u<mode>): Likewise.
 484         (mve_vbicq_<supf><mode>): Likewise.
 485         (mve_vbicq_f<mode>): Likewise.
 486         (mve_vbicq_m_<supf><mode>): Likewise.
 487         (mve_vbicq_m_f<mode>): Likewise.
 488         (mve_vbicq_m_n_<supf><mode>): Likewise.
 489         (mve_vbicq_n_<supf><mode>): Likewise.
 490         (mve_vbicq_s<mode>): Likewise.
 491         (mve_vbicq_u<mode>): Likewise.
 492         (@mve_vclzq_s<mode>): Likewise.
 493         (mve_vclzq_u<mode>): Likewise.
 494         (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
 495         (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
 496         (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
 497         (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
 498         (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
 499         (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
 500         (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
 501         (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
 502         (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
 503         (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
 504         (mve_vcvtaq_<supf><mode>): Likewise.
 505         (mve_vcvtaq_m_<supf><mode>): Likewise.
 506         (mve_vcvtbq_f16_f32v8hf): Likewise.
 507         (mve_vcvtbq_f32_f16v4sf): Likewise.
 508         (mve_vcvtbq_m_f16_f32v8hf): Likewise.
 509         (mve_vcvtbq_m_f32_f16v4sf): Likewise.
 510         (mve_vcvtmq_<supf><mode>): Likewise.
 511         (mve_vcvtmq_m_<supf><mode>): Likewise.
 512         (mve_vcvtnq_<supf><mode>): Likewise.
 513         (mve_vcvtnq_m_<supf><mode>): Likewise.
 514         (mve_vcvtpq_<supf><mode>): Likewise.
 515         (mve_vcvtpq_m_<supf><mode>): Likewise.
 516         (mve_vcvtq_from_f_<supf><mode>): Likewise.
 517         (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
 518         (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
 519         (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
 520         (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
 521         (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
 522         (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
 523         (mve_vcvtq_to_f_<supf><mode>): Likewise.
 524         (mve_vcvttq_f16_f32v8hf): Likewise.
 525         (mve_vcvttq_f32_f16v4sf): Likewise.
 526         (mve_vcvttq_m_f16_f32v8hf): Likewise.
 527         (mve_vcvttq_m_f32_f16v4sf): Likewise.
 528         (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
 529         (mve_vdwdupq_wb_u<mode>_insn): Likewise.
 530         (mve_veorq_s><mode>): Likewise.
 531         (mve_veorq_u><mode>): Likewise.
 532         (mve_veorq_f<mode>): Likewise.
 533         (mve_vidupq_m_wb_u<mode>_insn): Likewise.
 534         (mve_vidupq_u<mode>_insn): Likewise.
 535         (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
 536         (mve_viwdupq_wb_u<mode>_insn): Likewise.
 537         (mve_vldrbq_<supf><mode>): Likewise.
 538         (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
 539         (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
 540         (mve_vldrbq_z_<supf><mode>): Likewise.
 541         (mve_vldrdq_gather_base_<supf>v2di): Likewise.
 542         (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
 543         (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
 544         (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
 545         (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
 546         (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
 547         (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
 548         (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
 549         (mve_vldrhq_<supf><mode>): Likewise.
 550         (mve_vldrhq_fv8hf): Likewise.
 551         (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
 552         (mve_vldrhq_gather_offset_fv8hf): Likewise.
 553         (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
 554         (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
 555         (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
 556         (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
 557         (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
 558         (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
 559         (mve_vldrhq_z_<supf><mode>): Likewise.
 560         (mve_vldrhq_z_fv8hf): Likewise.
 561         (mve_vldrwq_<supf>v4si): Likewise.
 562         (mve_vldrwq_fv4sf): Likewise.
 563         (mve_vldrwq_gather_base_<supf>v4si): Likewise.
 564         (mve_vldrwq_gather_base_fv4sf): Likewise.
 565         (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
 566         (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
 567         (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
 568         (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
 569         (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
 570         (mve_vldrwq_gather_base_z_fv4sf): Likewise.
 571         (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
 572         (mve_vldrwq_gather_offset_fv4sf): Likewise.
 573         (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
 574         (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
 575         (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
 576         (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
 577         (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
 578         (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
 579         (mve_vldrwq_z_<supf>v4si): Likewise.
 580         (mve_vldrwq_z_fv4sf): Likewise.
 581         (mve_vmvnq_s<mode>): Likewise.
 582         (mve_vmvnq_u<mode>): Likewise.
 583         (mve_vornq_<supf><mode>): Likewise.
 584         (mve_vornq_f<mode>): Likewise.
 585         (mve_vornq_m_<supf><mode>): Likewise.
 586         (mve_vornq_m_f<mode>): Likewise.
 587         (mve_vornq_s<mode>): Likewise.
 588         (mve_vornq_u<mode>): Likewise.
 589         (mve_vorrq_<supf><mode>): Likewise.
 590         (mve_vorrq_f<mode>): Likewise.
 591         (mve_vorrq_m_<supf><mode>): Likewise.
 592         (mve_vorrq_m_f<mode>): Likewise.
 593         (mve_vorrq_m_n_<supf><mode>): Likewise.
 594         (mve_vorrq_n_<supf><mode>): Likewise.
 595         (mve_vorrq_s<mode>): Likewise.
 596         (mve_vorrq_s<mode>): Likewise.
 597         (mve_vsbciq_<supf>v4si): Likewise.
 598         (mve_vsbciq_m_<supf>v4si): Likewise.
 599         (mve_vsbcq_<supf>v4si): Likewise.
 600         (mve_vsbcq_m_<supf>v4si): Likewise.
 601         (mve_vshlcq_<supf><mode>): Likewise.
 602         (mve_vshlcq_m_<supf><mode>): Likewise.
 603         (mve_vshrq_m_n_<supf><mode>): Likewise.
 604         (mve_vshrq_n_<supf><mode>): Likewise.
 605         (mve_vstrbq_<supf><mode>): Likewise.
 606         (mve_vstrbq_p_<supf><mode>): Likewise.
 607         (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
 608         (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
 609         (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
 610         (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
 611         (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
 612         (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
 613         (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
 614         (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
 615         (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
 616         (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
 617         (mve_vstrhq_<supf><mode>): Likewise.
 618         (mve_vstrhq_fv8hf): Likewise.
 619         (mve_vstrhq_p_<supf><mode>): Likewise.
 620         (mve_vstrhq_p_fv8hf): Likewise.
 621         (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
 622         (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
 623         (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
 624         (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
 625         (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
 626         (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
 627         (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
 628         (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
 629         (mve_vstrwq_<supf>v4si): Likewise.
 630         (mve_vstrwq_fv4sf): Likewise.
 631         (mve_vstrwq_p_<supf>v4si): Likewise.
 632         (mve_vstrwq_p_fv4sf): Likewise.
 633         (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
 634         (mve_vstrwq_scatter_base_fv4sf): Likewise.
 635         (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
 636         (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
 637         (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
 638         (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
 639         (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
 640         (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
 641         (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
 642         (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
 643         (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
 644         (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
 645         (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
 646         (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
 647         (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
 648         (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
 649
 650 2024-03-04  Marek Polacek  <polacek@redhat.com>
 651
 652         * doc/extend.texi: Update [[gnu::no_dangling]].
 653
 654 2024-03-04  Andrew Stubbs  <ams@baylibre.com>
 655
 656         * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
 657         * expr.cc (store_constructor): Likewise.
 658         (do_store_flag): Likewise.
 659
 660 2024-03-04  Mark Wielaard  <mark@klomp.org>
 661
 662         * common.opt.urls: Regenerate.
 663         * config/avr/avr.opt.urls: Likewise.
 664         * config/i386/i386.opt.urls: Likewise.
 665         * config/pru/pru.opt.urls: Likewise.
 666         * config/riscv/riscv.opt.urls: Likewise.
 667         * config/rs6000/rs6000.opt.urls: Likewise.
 668
 669 2024-03-04  Richard Biener  <rguenther@suse.de>
 670
 671         PR tree-optimization/114197
 672         * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
 673         there are volatile bitfield accesses.
 674         (pass_if_conversion::execute): Throw away result if the
 675         if-converted and original loops are not nested as expected.
 676
 677 2024-03-04  Richard Biener  <rguenther@suse.de>
 678
 679         PR tree-optimization/114164
 680         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
 681         the code generated for mask argument setup is not supported.
 682
 683 2024-03-04  Richard Biener  <rguenther@suse.de>
 684
 685         PR tree-optimization/114203
 686         * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
 687         adjustment before making the result defined at zero.
 688
 689 2024-03-04  Richard Biener  <rguenther@suse.de>
 690
 691         PR tree-optimization/114192
 692         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
 693         appropriate def for the live out stmt in case of an alternate
 694         exit.
 695
 696 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
 697
 698         PR middle-end/114209
 699         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
 700         unshare_expr when creating a MEM_REF from MEM_REF.
 701         (bitint_large_huge::lower_stmt): Call unshare_expr.
 702
 703 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
 704
 705         PR target/114184
 706         * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
 707         is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
 708         register.
 709
 710 2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>
 711
 712         PR target/114187
 713         * simplify-rtx.cc (simplify_context::simplify_subreg): Call
 714         lowpart_subreg to perform type conversion, to avoid confusion
 715         over the offset to use in the call to simplify_reg_subreg.
 716
 717 2024-03-03  Greg McGary  <gkm@rivosinc.com>
 718
 719         PR rtl-optimization/113010
 720         * combine.cc (simplify_comparison): Simplify a SUBREG on
 721         WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
 722         MEM load.
 723
 724 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 725
 726         * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
 727         Use bool in place of int for boolean logic (if possible).
 728         Move declarations to definitions (if possible).
 729         * config/avr/avr.md: Use C++ comments.  Fix some indentation glitches.
 730         * config/avr/avr-dimode.md: Same.
 731         * config/avr/constraints.md: Same.
 732         * config/avr/predicates.md: Same.
 733
 734 2024-03-03  Uros Bizjak  <ubizjak@gmail.com>
 735
 736         PR target/113720
 737         * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
 738         (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
 739         simplify insn RTX using UMUL_HIGHPART rtx_code.
 740         (*umuldi3_highpart_const): Remove.
 741
 742 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 743
 744         PR target/114100
 745         * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
 746         * config/avr/avr.cc (_reg_unused_after): Make static.  And
 747         add 3rd argument to skip the current insn.
 748         (reg_unused_after): Adjust call of reg_unused_after.
 749         (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
 750         unneeded frame pointer adjustments.
 751
 752 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 753
 754         PR target/92729
 755         * config/avr/avr.md (define_attr "cc"): Remove.
 756         * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
 757         from prototype.
 758         * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
 759         its uses.  Add insn argument.
 760         (avr_out_plus_symbol): Remove pcc argument and its uses.
 761         (avr_out_plus): Remove pcc argument and its uses.
 762         Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
 763         (avr_out_round): Adjust call of avr_out_plus.
 764
 765 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
 766
 767         * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
 768         from  r14-9273.
 769
 770 2024-03-03  Oleg Endo  <olegendo@gcc.gnu.org>
 771
 772         PR target/101737
 773         * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
 774         is not an insn, but e.g. a code label.
 775
 776 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
 777
 778         * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
 779         * config/avr/avr.cc: Use them instead of magic numbers when it
 780         means a register number.
 781
 782 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
 783
 784         * config/avr/avr.cc: Adjust some comments.
 785
 786 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
 787
 788         PR target/114100
 789         * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
 790         the low part of the frame pointer with 8-bit stack pointer.
 791
 792 2024-03-01  Patrick Palka  <ppalka@redhat.com>
 793
 794         PR c++/104919
 795         PR c++/106009
 796         * tree-inline.cc (remap_decl): Handle copy_decl returning the
 797         original decl.
 798         (remap_decls): Handle remap_decl returning the original decl.
 799         (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
 800         CONST_DECL.
 801
 802 2024-03-01  Jeff Law  <jlaw@ventanamicro.com>
 803
 804         * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
 805         type attribute.
 806         (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
 807         (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
 808         (movhi_internal, movqi_internal): Likewise.
 809         (movsf_softfloat, movsf_hardfloat): Likewise.
 810         (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
 811         (movdf_softfloat): Likewise.
 812
 813 2024-03-01  Marek Polacek  <polacek@redhat.com>
 814
 815         PR c++/110358
 816         PR c++/109642
 817         * doc/extend.texi: Document gnu::no_dangling.
 818         * doc/invoke.texi: Mention that gnu::no_dangling disables
 819         -Wdangling-reference.
 820
 821 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
 822
 823         * config/avr/avr.opt: Overhaul help screen.
 824
 825 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 826             Tobias Burnus  <tburnus@baylibre.com>
 827
 828         PR c++/110347
 829         * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
 830         lang_hooks.decls.omp_disregard_value_expr for
 831         (first)private in target regions.
 832
 833 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 834
 835         PR middle-end/114136
 836         * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
 837         n_named_args initially before INIT_CUMULATIVE_ARGS to
 838         structure_value_addr_parm rather than 0, after it don't modify
 839         it if strict_argument_naming and clear only if
 840         !pretend_outgoing_varargs_named.
 841
 842 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 843
 844         PR debug/114015
 845         * dwarf2out.cc (should_move_die_to_comdat): Return false for
 846         aggregates without DW_AT_byte_size attribute or with non-constant
 847         DW_AT_byte_size.
 848
 849 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
 850
 851         * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
 852         valid values for level.
 853
 854 2024-03-01  Richard Biener  <rguenther@suse.de>
 855
 856         PR middle-end/114070
 857         * match.pd ((c ? a : b) op d  -->  c ? (a op d) : (b op d)):
 858         Allow the folding if before lowering and the current IL
 859         isn't supported with vcond_mask.
 860
 861 2024-03-01  xuli  <xuli1@eswincomputing.com>
 862
 863         * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
 864         attribute to riscv_attribute_table.
 865         (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
 866         (riscv_fntype_abi): Add riscv_vector_cc attribute check.
 867         * doc/extend.texi: Add riscv_vector_cc attribute description.
 868
 869 2024-03-01  Pan Li  <pan2.li@intel.com>
 870
 871         PR target/112817
 872         * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
 873         RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
 874         * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
 875         (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
 876         * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
 877         comments for option replacement.
 878         * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
 879         riscv_autovec_preference to rvv_vector_bits.
 880         (vls_mode_valid_p): Ditto.
 881         (estimated_poly_value): Ditto.
 882         * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
 883         vector chunks and honor new option mrvv-vector-bits.
 884         (riscv_override_options_internal): Update comments and rename the
 885         vector chunks.
 886         * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
 887         internal option param=riscv-autovec-preference.
 888
 889 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 890
 891         * function.cc (assign_parms): Only call assign_parms_setup_varargs
 892         early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
 893
 894 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
 895
 896         PR middle-end/114156
 897         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
 898         rhs1 of a VCE to have no underlying variable if it is a load and
 899         handle that case.
 900
 901 2024-02-29  David Malcolm  <dmalcolm@redhat.com>
 902
 903         PR analyzer/114159
 904         * function.cc (function_name): Make param const.
 905         * function.h (function_name): Likewise.
 906
 907 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
 908
 909         PR target/114100
 910         * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
 911         * config/avr/avr.opt (-mfuse-add=): New target option.
 912         * common/config/avr/avr-common.cc (avr_option_optimization_table)
 913         [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
 914         [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
 915         * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
 916         * config/avr/avr-protos.h (avr_split_tiny_move)
 917         (make_avr_pass_fuse_add): New protos.
 918         * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
 919         avr_split_tiny_move to split indirect memory accesses.
 920         (gen_move_clobbercc): New define_expand helper.
 921         * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
 922         (avr_pass_fuse_add): New class from rtl_opt_pass.
 923         (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
 924         (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
 925         (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
 926         of PLUS addressing for AVR_TINY.
 927         (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
 928         (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
 929         (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
 930
 931 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
 932
 933         PR target/114132
 934         * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
 935         * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
 936         (avr_function_arg): Set it.
 937         (avr_frame_pointer_required_p): Use it instead of .nregs.
 938
 939 2024-02-29  Andrew Pinski  <quic_apinski@quicinc.com>
 940
 941         PR target/108174
 942         * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
 943         static and mark with GTY.
 944
 945 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
 946
 947         * config/loongarch/loongarch.md
 948         (loongarch_<crc>_w_<size>_w_extended): New define_insn.
 949
 950 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
 951
 952         * config/loongarch/loongarch.md (CRC): New define_int_iterator.
 953         (crc): New define_int_attr.
 954         (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
 955         into ...
 956         (loongarch_<crc>_w_<size>_w): ... here.
 957
 958 2024-02-29  Kito Cheng  <kito.cheng@sifive.com>
 959
 960         PR target/114130
 961         * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
 962         extend the expected value if needed.
 963
 964 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 965
 966         * config.gcc (target_gtfiles): Change coreout to btfext-out.
 967         (extra_objs): Change coreout to btfext-out.
 968         * config/bpf/coreout.cc: Rename to btfext-out.cc.
 969         * config/bpf/btfext-out.cc: Add.
 970         * config/bpf/coreout.h: Rename to btfext-out.h.
 971         * config/bpf/btfext-out.h: Add.
 972         * config/bpf/core-builtins.cc: Change include.
 973         * config/bpf/core-builtins.h: Change include.
 974         * config/bpf/t-bpf: Accomodate renamed files.
 975
 976 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 977
 978         PR target/113453
 979         * config/bpf/bpf.cc (bpf_function_prologue): Define target
 980         hook.
 981         * config/bpf/coreout.cc (brf_ext_info_section)
 982         (btf_ext_info): Move from coreout.h
 983         (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
 984         (bpf_core_reloc): Rename to btf_ext_core_reloc.
 985         (btf_ext): Add static variable.
 986         (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
 987         (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
 988         (btf_ext_add_string, btf_funcinfo_type_callback)
 989         (btf_add_func_info_for, btf_validate_funcinfo)
 990         (btf_ext_info_len, output_btfext_func_info): Add function.
 991         (output_btfext_header, bpf_core_reloc_add)
 992         (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
 993         Change to support new structs.
 994         * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
 995         Move and change in coreout.cc.
 996         (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
 997
 998 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
 999
1000         * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
1001         enabled by default for BPF.
1002         (bpf_file_end): Call BTF deallocation.
1003         (bpf_asm_init_sections): Correct condition.
1004         * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
1005         deallocation.
1006         (ctf_debuf_finish): Correct condition for calling
1007         ctf_debug_finalize.
1008
1009 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1010
1011         * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
1012         (traverse_btf_func_types): Define function.
1013         * ctfc.h (funcs_traverse_callback): Typedef for function
1014         prototype.
1015         (traverse_btf_func_types): Add prototype.
1016
1017 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1018
1019         * btfout.cc (btf_collect_dataset): Corrects BTF type id.
1020
1021 2024-02-28  Richard Biener  <rguenther@suse.de>
1022
1023         PR tree-optimization/113831
1024         PR tree-optimization/108355
1025         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
1026         PR113831 fix.
1027
1028 2024-02-28  Richard Biener  <rguenther@suse.de>
1029
1030         PR tree-optimization/114121
1031         * tree-ssa-sccvn.h (vn_reference_s::offset,
1032         vn_reference_s::max_size): New fields.
1033         (vn_reference_insert_pieces): Adjust prototype.
1034         * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
1035         * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
1036         size, allow using "don't know" state.
1037         (vn_walk_cb_data::finish): Pass along offset/max_size.
1038         (vn_reference_lookup_or_insert_for_pieces): Take offset and
1039         max_size as argument and use it.
1040         (vn_reference_lookup_3): Properly adjust offset and max_size
1041         according to the adjusted ao_ref.
1042         (vn_reference_lookup_pieces): Initialize offset and max_size.
1043         (vn_reference_lookup): Likewise.
1044         (vn_reference_lookup_call): Likewise.
1045         (vn_reference_insert): Likewise.
1046         (visit_reference_op_call): Likewise.
1047         (vn_reference_insert_pieces): Take offset and max_size
1048         as argument and use it.
1049
1050 2024-02-28  Juergen Christ  <jchrist@linux.ibm.com>
1051
1052         PR tree-optimization/114075
1053         * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
1054         point vectors
1055
1056 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
1057
1058         PR tree-optimization/114041
1059         * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
1060         INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
1061
1062 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
1063
1064         PR tree-optimization/113988
1065         * stor-layout.h (bitwise_mode_for_size): Declare.
1066         * stor-layout.cc (bitwise_mode_for_size): New function.
1067         * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
1068         Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
1069         Use BITS_PER_UNIT instead of 8.
1070
1071 2024-02-27  Uros Bizjak  <ubizjak@gmail.com>
1072
1073         PR target/113871
1074         * config/i386/mmx.md (V248FI): Add V2BF mode.
1075         (V24FI_32): Ditto.
1076
1077 2024-02-27  Eric Botcazou  <ebotcazou@adacore.com>
1078
1079         * tree-ssa-dse.cc (compute_trims): Fix description.  Return early
1080         if either ref->offset is not byte aligned or ref->size is not known
1081         to be equal to ref->max_size.
1082         (maybe_trim_complex_store): Fix description.
1083         (maybe_trim_constructor_store): Likewise.
1084         (maybe_trim_partially_dead_store): Likewise.
1085
1086 2024-02-27  Richard Earnshaw  <rearnsha@arm.com>
1087
1088         * config/arm/mmintrin.h: Warn if this header is included without
1089         defining __ENABLE_DEPRECATED_IWMMXT.
1090
1091 2024-02-27  Richard Biener  <rguenther@suse.de>
1092
1093         PR tree-optimization/114074
1094         * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
1095         * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
1096         Handle poly vs. non-poly multiplication correctly with respect
1097         to undefined behavior on overflow.
1098
1099 2024-02-27  Jakub Jelinek  <jakub@redhat.com>
1100
1101         PR rtl-optimization/114044
1102         * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
1103         DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
1104         * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
1105         expand_PARITY): Declare.
1106         * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
1107         expand_CTZ, expand_FFS, expand_PARITY): New functions.
1108         (expand_POPCOUNT): Use expand_bitquery.
1109
1110 2024-02-27  Richard Biener  <rguenther@suse.de>
1111
1112         PR tree-optimization/114081
1113         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1114         Perform manual dominator update for prologue peeling.
1115         (vect_do_peeling): Properly update dominators after adding the
1116         prologue-around guard.
1117
1118 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
1119
1120         * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
1121         (mstrict-X): Tag as "Optimization".
1122
1123 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
1124
1125         * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
1126         an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
1127
1128 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
1129             H.J. Lu  <hjl.tools@gmail.com>
1130
1131         PR rtl-optimization/113617
1132         * varasm.cc (default_elf_select_rtx_section): For
1133         references to private symbols in comdat sections
1134         use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
1135         or .rodata.<comdat> comdat sections.
1136
1137 2024-02-26  Richard Biener  <rguenther@suse.de>
1138
1139         PR tree-optimization/114099
1140         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1141         Create and fill in a needed virtual LC PHI for the alternate
1142         exits.  Remove code dealing with that missing.
1143
1144 2024-02-26  Richard Biener  <rguenther@suse.de>
1145
1146         PR tree-optimization/114068
1147         * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
1148         New function.
1149         (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
1150         on the main exit if needed.  Remove band-aid for the case
1151         it was missing.
1152
1153 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
1154
1155         PR target/114097
1156         * config/i386/i386-options.cc (ix86_set_func_type): Check
1157         interrupt instead of noreturn attribute.
1158
1159 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
1160
1161         * config/i386/i386.cc (ix86_bitint_type_info): Add support for
1162         !TARGET_64BIT.
1163
1164 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
1165
1166         PR tree-optimization/114090
1167         * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
1168         Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
1169         types.
1170         ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
1171
1172 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
1173
1174         PR middle-end/114084
1175         * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
1176         if all subtrees of var0 come from one of the op0 or op1 operands
1177         and all subtrees of con0 come from the other one.  Don't clear
1178         variables which are never used afterwards.
1179
1180 2024-02-26  Richard Biener  <rguenther@suse.de>
1181
1182         PR middle-end/114070
1183         * genmatch.cc (parser::parse_c_expr): Do not record operand
1184         lists but only mark operators used.
1185         * match.pd ((c ? a : b) op (c ? d : e)  -->  c ? (a op d) : (b op e)):
1186         Properly guard the case of tcc_comparison changing the VEC_COND
1187         value operand type.
1188
1189 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
1190
1191         PR target/114094
1192         * config/i386/i386.cc (x86_function_profiler): Add missing new-line
1193         to printed instruction.
1194
1195 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
1196
1197         PR target/114098
1198         * config/i386/amxtileintrin.h (_tile_loadconfig): Use
1199         __builtin_ia32_ldtilecfg.
1200         (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
1201         * config/i386/i386-builtin.def (BDESC): Add
1202         __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
1203         * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
1204         IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
1205         * config/i386/i386.md (ldtilecfg): New pattern.
1206         (sttilecfg): Likewise.
1207
1208 2024-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1209
1210         PR tree-optimization/113205
1211         * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
1212         the proposed layout if it does not allow a source partition with
1213         layout 2 to keep that layout.
1214
1215 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
1216
1217         * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
1218         * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
1219         * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
1220         * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
1221         (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
1222         * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
1223         macros.
1224         * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
1225         * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
1226         * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
1227         HOST_WIDE_INT_UC macros.
1228         * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
1229         * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
1230         * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
1231         * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
1232         macros.
1233         * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
1234         * config/i386/constraints.md (define_constraint "L"): Use
1235         HOST_WIDE_INT_C macro.
1236         * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
1237         macro.
1238         (movl + movb peephole2): Likewise.
1239         * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
1240         (const_32bit_mask): Likewise.
1241
1242 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
1243
1244         PR middle-end/114073
1245         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
1246         VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
1247         types like vector or complex types.
1248         (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
1249         types.  Fix up VIEW_CONVERT_EXPR handling.  Allow merging
1250         VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
1251
1252 2024-02-23  Robin Dapp  <rdapp@ventanamicro.com>
1253
1254         PR target/114028
1255         * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
1256         Return false if inner mode is already Pmode.
1257         (rvv_builder::is_all_same_sequence): New function.
1258         (expand_vec_init): Emit broadcast if sequence is all same.
1259
1260 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
1261
1262         PR target/113613
1263         * config/aarch64/aarch64-early-ra.cc
1264         (early_ra::m_current_region): New member variable.
1265         (early_ra::m_fpr_recency): Likewise.
1266         (early_ra::start_new_region): Bump m_current_region.
1267         (early_ra::allocate_colors): Prefer less recently used registers
1268         in the event of a tie.  Add a comment to explain why we prefer(ed)
1269         higher-numbered registers.
1270         (early_ra::find_oldest_color): Prefer less recently used registers
1271         here too.
1272         (early_ra::finalize_allocation): Update recency information for
1273         allocated registers.
1274         (early_ra::process_blocks): Initialize m_current_region and
1275         m_fpr_recency.
1276
1277 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
1278
1279         PR target/113295
1280         * config/aarch64/aarch64-early-ra.cc
1281         (early_ra::test_strictness): New enum.
1282         (early_ra::is_chain_candidate): Add a strictness parameter to
1283         control whether only correctness matters, or whether both correctness
1284         and heuristics should be used.  Handle multiple levels of equivalence.
1285         (early_ra::find_related_start): Update call accordingly.
1286         (early_ra::strided_polarity_pref): Likewise.
1287         (early_ra::form_chains): Likewise.
1288         (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
1289         correctness mode rather than trying to inline the test.
1290
1291 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
1292
1293         PR target/113295
1294         * config/aarch64/aarch64-early-ra.cc
1295         (early_ra::find_related_start): Account for definitions by shared
1296         registers when testing for a single register definition.
1297         (early_ra::accumulate_defs): New function.
1298         (early_ra::record_copy): If A shares B's register, fold A's
1299         definition information into B's.  Fold A's use information into B's.
1300
1301 2024-02-23  H.J. Lu  <hjl.tools@gmail.com>
1302
1303         * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
1304         if R_X86_64_CODE_6_GOTTPOFF is supported.
1305         * config.in: Regenerated.
1306         * configure: Likewise.
1307         * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
1308         UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
1309
1310 2024-02-23  Richard Earnshaw  <rearnsha@arm.com>
1311
1312         PR target/108120
1313         * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
1314         Gate with ARM_HAVE_NEON_<MODE>_ARITH.
1315
1316 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
1317
1318         PR rtl-optimization/114054
1319         * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
1320         temp variable instead of target parameter for result.
1321
1322 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
1323
1324         PR tree-optimization/114040
1325         * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
1326         Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
1327         probability from likely to unlikely.  When handling the true true
1328         store, first cast to limb_access_type and then to l's type.
1329
1330 2024-02-23  Richard Biener  <rguenther@suse.de>
1331
1332         PR target/90785
1333         * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
1334
1335 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
1336
1337         PR other/109668
1338         * config/riscv/arch-canonicalize: Move to python3
1339         * config/riscv/multilib-generator: Likewise
1340
1341 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
1342
1343         * doc/invoke.texi: Document -mcpu.
1344
1345 2024-02-23  Lulu Cheng  <chenglulu@loongson.cn>
1346
1347         * configure: Regenerate.
1348         * configure.ac: Add parameter "--fatal-warnings" to assemble
1349         when checking whether the assemble support conditional branch
1350         relaxation.
1351
1352 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
1353
1354         PR c/114007
1355         * doc/extend.texi: (__extension__): Remove comments about scope
1356         tokens vs. two colons.
1357
1358 2024-02-22  Andrew Pinski  <quic_apinski@quicinc.com>
1359
1360         PR tree-optimization/109804
1361         * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
1362         DEMANGLE_COMPONENT_UNNAMED_TYPE.
1363
1364 2024-02-22  Richard Biener  <rguenther@suse.de>
1365
1366         PR tree-optimization/114048
1367         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
1368         can also produce -1 off.
1369
1370 2024-02-22  Richard Biener  <rguenther@suse.de>
1371
1372         PR tree-optimization/114027
1373         * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
1374         condition reduction classification only for single-element
1375         chains.
1376
1377 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
1378
1379         PR ipa/111960
1380         * profile-count.h (profile_count::dump): Remove overload with
1381         char * first argument.
1382         * profile-count.cc (profile_count::dump): Change overload with char *
1383         first argument which uses sprintf into the overfload with FILE *
1384         first argument and use fprintf instead.  Remove overload which wrapped
1385         it.
1386
1387 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
1388
1389         PR tree-optimization/113993
1390         * tree-call-cdce.cc (get_no_error_domain): Handle
1391         BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}.  Handle
1392         BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
1393         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1394         the as the F128 suffixed cases, otherwise as non-suffixed ones.
1395         Handle BUILT_IN_{EXP,POW}10L for
1396         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1397         as (-inf, 4932).
1398
1399 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
1400
1401         PR tree-optimization/114038
1402         * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
1403         loop exit condition if end is divisible by limb_prec.
1404
1405 2024-02-22  YunQiang Su  <syq@gcc.gnu.org>
1406
1407         * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
1408         problem of mabi=, mno-flush-func, mexplicit-relocs;
1409         add missing leading - of mbranch-cost option.
1410         * config/mips/mips.opt.urls: Regenerate.
1411
1412 2024-02-22  Kewen Lin  <linkw@linux.ibm.com>
1413
1414         PR target/109987
1415         * config/rs6000/constraints.md (we): Update internal doc without
1416         referring to option -mpower9-vector.
1417         * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
1418         special handlings.
1419         * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
1420         OTHER_P8_VECTOR_MASKS): Merge to ...
1421         (OTHER_VSX_VECTOR_MASKS): ... here.
1422         * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
1423         some error message handlings and explicit option mask adjustments on
1424         explicit option power{8,9}-vector conflicting with other options.
1425         (rs6000_print_isa_options): Update comments.
1426         (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
1427         related array items and handlings.
1428         * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
1429         special handlings.
1430         * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
1431         WarnRemoved.
1432         * doc/extend.texi: Remove documentation referring to option
1433         -mpower8-vector.
1434         * doc/invoke.texi: Remove documentation for option
1435         -mpower{8,9}-vector and adjust some documentation referring to them.
1436         * doc/md.texi: Update documentation for constraint we.
1437         * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
1438
1439 2024-02-22  Pan Li  <pan2.li@intel.com>
1440
1441         PR target/114017
1442         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
1443         the version to 0.12.
1444
1445 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
1446
1447         * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
1448
1449 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
1450             Robin Dapp  <rdapp.gcc@gmail.com>
1451
1452         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1453         (generic_ooo_vec_load): Ditto
1454         (generic_ooo_vec_store): Ditto
1455         (generic_ooo_vec_loadstore_seg): Ditto
1456         (generic_ooo_vec_alu): Ditto
1457         (generic_ooo_vec_fcmp): Ditto
1458         (generic_ooo_vec_imul): Ditto
1459         (generic_ooo_vec_fadd): Ditto
1460         (generic_ooo_vec_fmul): Ditto
1461         (generic_ooo_crypto): Ditto
1462         (generic_ooo_perm): Ditto
1463         (generic_ooo_vec_reduction): Ditto
1464         (generic_ooo_vec_ordered_reduction): Ditto
1465         (generic_ooo_vec_idiv): Ditto
1466         (generic_ooo_vec_float_divsqrt): Ditto
1467         (generic_ooo_vec_mask): Ditto
1468         (generic_ooo_vec_vesetvl): Ditto
1469         (generic_ooo_vec_setrm): Ditto
1470         (generic_ooo_vec_readlen): Ditto
1471         * config/riscv/riscv.md: Include generic-vector-ooo
1472         * config/riscv/generic-vector-ooo.md: New file. To here
1473
1474 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
1475
1476         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1477         (generic_ooo_branch): Ditto
1478         * config/riscv/generic.md (generic_sfb_alu): Ditto
1479         (generic_fmul_half): Ditto
1480         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1481         * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
1482         (sifive_7_popcount): Ditto
1483         * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
1484         * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
1485         * config/riscv/vector.md: Change rdfrm to fmove
1486         * config/riscv/zc.md: Change pushpop to load/store
1487
1488 2024-02-21  Jonathan Wakely  <jwakely@redhat.com>
1489
1490         * doc/invoke.texi (Warning Options): Fix typos.
1491
1492 2024-02-21  David Faust  <david.faust@oracle.com>
1493
1494         * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
1495         * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
1496         * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
1497
1498 2024-02-21  Martin Jambor  <mjambor@suse.cz>
1499
1500         PR ipa/113476
1501         * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
1502         initializers in the contructor.
1503         (ipa_node_params::~ipa_node_params): Release lattices as a vector.
1504         * ipa-cp.h: New file.
1505         * ipa-cp.cc: Include sreal.h and ipa-cp.h.
1506         (ipcp_value_source): Move to ipa-cp.h.
1507         (ipcp_value_base): Likewise.
1508         (ipcp_value): Likewise.
1509         (ipcp_lattice): Likewise.
1510         (ipcp_agg_lattice): Likewise.
1511         (ipcp_bits_lattice): Likewise.
1512         (ipcp_vr_lattice): Likewise.
1513         (ipcp_param_lattices): Likewise.
1514         (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
1515         (ipa_value_from_jfunc): Adjust a check for empty lattices.
1516         (ipa_context_from_jfunc): Likewise.
1517         (ipa_agg_value_from_jfunc): Likewise.
1518         (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
1519         (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
1520         just in contiguous memory.
1521         (ipcp_store_vr_results): Adjust a check for empty lattices.
1522         * auto-profile.cc: Include sreal.h and ipa-cp.h.
1523         * cgraph.cc: Likewise.
1524         * cgraphclones.cc: Likewise.
1525         * cgraphunit.cc: Likewise.
1526         * config/aarch64/aarch64.cc: Likewise.
1527         * config/i386/i386-builtins.cc: Likewise.
1528         * config/i386/i386-expand.cc: Likewise.
1529         * config/i386/i386-features.cc: Likewise.
1530         * config/i386/i386-options.cc: Likewise.
1531         * config/i386/i386.cc: Likewise.
1532         * config/rs6000/rs6000.cc: Likewise.
1533         * config/s390/s390.cc: Likewise.
1534         * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
1535         files to be included in gtype-desc.cc.
1536         * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
1537         * ipa-devirt.cc: Likewise.
1538         * ipa-fnsummary.cc: Likewise.
1539         * ipa-icf.cc: Likewise.
1540         * ipa-inline-analysis.cc: Likewise.
1541         * ipa-inline-transform.cc: Likewise.
1542         * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
1543         * ipa-modref.cc: Include sreal.h and ipa-cp.h.
1544         * ipa-param-manipulation.cc: Likewise.
1545         * ipa-predicate.cc: Likewise.
1546         * ipa-profile.cc: Likewise.
1547         * ipa-prop.cc: Likewise.
1548         (ipa_node_params_t::duplicate): Assert new lattices remain empty
1549         instead of setting them to NULL.
1550         * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
1551         * ipa-split.cc: Likewise.
1552         * ipa-sra.cc: Likewise.
1553         * ipa-strub.cc: Likewise.
1554         * ipa-utils.cc: Likewise.
1555         * ipa.cc: Likewise.
1556         * toplev.cc: Likewise.
1557         * tree-ssa-ccp.cc: Likewise.
1558         * tree-ssa-sccvn.cc: Likewise.
1559         * tree-vrp.cc: Likewise.
1560
1561 2024-02-21  Tamar Christina  <tamar.christina@arm.com>
1562
1563         * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
1564         Armv8.7-a.
1565
1566 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1567
1568         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1569         Use aarch64_gen_compare_zero_and_branch rather than emitting
1570         a CBZ directly.
1571
1572 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1573
1574         * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
1575         Remove duplicated call.
1576
1577 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1578
1579         * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
1580         Check that each individual piece of state is shared in the same
1581         way, rather than using an aggregate check for PSTATE.ZA.
1582
1583 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1584
1585         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1586         In the code that commits a lazy save, only zero ZA if the function
1587         has ZA state.  Similarly zero ZT0 if the function has ZT0 state.
1588
1589 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1590
1591         * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
1592         directly inserting the associated sequence
1593         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1594         ...here instead.
1595
1596 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1597
1598         PR target/113995
1599         * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
1600         fold the SVE allocation into the initial allocation if the
1601         initial allocation includes a VG save.
1602
1603 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
1604
1605         PR target/113220
1606         * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
1607         contain jumps even if called after initial RTL expansion.
1608         * mode-switching.cc: Include cfgbuild.h.
1609         (optimize_mode_switching): Allow the sequence returned by the
1610         emit hook to contain internal jumps.  Record which blocks
1611         contain such jumps and split the blocks at the end.
1612         * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
1613         non-debug insns when scanning the sequence.
1614
1615 2024-02-21  Tobias Burnus  <tburnus@baylibre.com>
1616
1617         * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
1618         * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
1619
1620 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
1621
1622         * doc/invoke.texi (-mmcu): Add information about MCU specs.
1623
1624 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
1625
1626         * doc/invoke.texi (-minrt): Clarify that main
1627         must take no arguments.
1628
1629 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
1630
1631         * config/avr/builtins.def: Use function prototypes of given size
1632         and signedness.
1633         * config/avr/avr.cc (avr_init_builtins): Adjust types required
1634         by builtins.def.
1635         * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
1636
1637 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
1638
1639         * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
1640         instead of @table.
1641
1642 2024-02-20  Will Hawkins  <hawkinsw@obs.cr>
1643
1644         * config/bpf/bpf.opt: Add help information for -mcpu.
1645
1646 2024-02-20  Richard Sandiford  <richard.sandiford@arm.com>
1647
1648         PR target/113805
1649         * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
1650         New pass.
1651         * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
1652         Declare.
1653         * config/aarch64/aarch64.md (is_call): New attribute.
1654         (*and<mode>3nr_compare0): Rename to...
1655         (@aarch64_and<mode>3nr_compare0): ...this.
1656         * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
1657         (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
1658         * config/aarch64/aarch64-speculation.cc: Update file comment to
1659         describe the new late pass.
1660         (aarch64_do_track_speculation): Handle is_call insns like other calls.
1661         (pass_track_speculation): Add an is_late member variable.
1662         (pass_track_speculation::gate): Run the late pass for streaming-
1663         compatible functions and the early pass for other functions.
1664         (make_pass_track_speculation): Update accordingly.
1665         (make_pass_late_track_speculation): New function.
1666         * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
1667         function.
1668         (aarch64_guard_switch_pstate_sm): Use it.
1669
1670 2024-02-19  Iain Sandoe  <iain@sandoe.co.uk>
1671
1672         * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
1673         Register these builtins with a pointer to uint64_t rather than unsigned
1674         DI mode.
1675
1676 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
1677
1678         PR target/113615
1679         * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
1680         Conditionalize on '!TARGET_RDNA2_PLUS'.
1681         * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
1682         (gcn_expand_reduc_scalar):
1683         'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
1684
1685 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
1686
1687         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
1688         '__gfx90a__' target CPU definition.  Add some safeguards for the future.
1689
1690 2024-02-19  Richard Biener  <rguenther@suse.de>
1691
1692         PR rtl-optimization/54052
1693         * rtl-ssa/blocks.cc (function_info::place_phis): Filter
1694         local defs by LR_OUT.
1695
1696 2024-02-19  Jakub Jelinek  <jakub@redhat.com>
1697
1698         PR tree-optimization/113967
1699         * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
1700         in condition that @rpos is multiple of vector element size.
1701
1702 2024-02-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1703
1704         PR target/113696
1705         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
1706         Suppress vsetvl fusion.
1707
1708 2024-02-18  H.J. Lu  <hjl.tools@gmail.com>
1709
1710         PR target/113912
1711         * config/i386/i386.cc (ix86_can_use_push2pop2): New.
1712         (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
1713         (ix86_emit_save_regs): Don't generate push2 if
1714         ix86_can_use_push2pop2 return false.
1715         (ix86_expand_epilogue): Don't generate pop2 if
1716         ix86_can_use_push2pop2 return false.
1717
1718 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
1719
1720         * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
1721         Note on complete device support.
1722
1723 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
1724
1725         * doc/extend.texi (AVR Function Attributes): Fuse description
1726         of "signal" and "interrupt" attribute.  Link pseudo instruction.
1727
1728 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
1729
1730         * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
1731         symbol type conversions.
1732         (__cacop_d): Likewise.
1733         (__cpucfg): Likewise.
1734         (__asrtle_d): Likewise.
1735         (__asrtgt_d): Likewise.
1736         (__lddir_d): Likewise.
1737         (__ldpte_d): Likewise.
1738         (__crc_w_b_w): Likewise.
1739         (__crc_w_h_w): Likewise.
1740         (__crc_w_w_w): Likewise.
1741         (__crc_w_d_w): Likewise.
1742         (__crcc_w_b_w): Likewise.
1743         (__crcc_w_h_w): Likewise.
1744         (__crcc_w_w_w): Likewise.
1745         (__crcc_w_d_w): Likewise.
1746         (__csrrd_w): Likewise.
1747         (__csrwr_w): Likewise.
1748         (__csrxchg_w): Likewise.
1749         (__csrrd_d): Likewise.
1750         (__csrwr_d): Likewise.
1751         (__csrxchg_d): Likewise.
1752         (__iocsrrd_b): Likewise.
1753         (__iocsrrd_h): Likewise.
1754         (__iocsrrd_w): Likewise.
1755         (__iocsrrd_d): Likewise.
1756         (__iocsrwr_b): Likewise.
1757         (__iocsrwr_h): Likewise.
1758         (__iocsrwr_w): Likewise.
1759         (__iocsrwr_d): Likewise.
1760         (__frecipe_s): Likewise.
1761         (__frecipe_d): Likewise.
1762         (__frsqrte_s): Likewise.
1763         (__frsqrte_d): Likewise.
1764
1765 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
1766
1767         * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
1768         function return value type to unsigned short.
1769
1770 2024-02-16  Edwin Lu  <ewlu@rivosinc.com>
1771
1772         * doc/sourcebuild.texi: add scan-assembler-bound
1773
1774 2024-02-16  Jason Merrill  <jason@redhat.com>
1775
1776         * gdbhooks.py: Fix regex syntax.
1777
1778 2024-02-16  Richard Biener  <rguenther@suse.de>
1779
1780         PR tree-optimization/113895
1781         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
1782         consistency checking when there are out-of-bound array
1783         accesses.  Allow -1 off when from an array reference with
1784         constant index.
1785
1786 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
1787
1788         PR target/106543
1789         * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
1790         pattern.
1791
1792 2024-02-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
1793
1794         * doc/sourcebuild.texi (Effective-Target Keywords, Other
1795         attribugs): Document linker_plugin.
1796         (Require Support): Document dg-require-linker-plugin.
1797
1798 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
1799
1800         PR target/109349
1801         * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
1802         * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
1803         (RISCV_MINOR_VERSION_BASE): Ditto.
1804         (RISCV_REVISION_VERSION_BASE): Ditto.
1805         * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
1806         rather than magic number.
1807         * config/riscv/riscv.h (riscv_arch_help): New.
1808         (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
1809         (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
1810         --print-supported-extensions.
1811         * config/riscv/riscv.opt (march=help): New.
1812         (print-supported-extensions): New.
1813         (-print-supported-extensions): New.
1814         * doc/invoke.texi (RISC-V Options): Document -march=help.
1815
1816 2024-02-16  Tejas Belagod  <tejas.belagod@arm.com>
1817
1818         PR target/113780
1819         * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
1820         for indirect calls with 4 or more arguments in pac-enabled functions.
1821
1822 2024-02-15  David Faust  <david.faust@oracle.com>
1823
1824         * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
1825         use ldxb instead of ldxh.
1826
1827 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
1828
1829         PR middle-end/113921
1830         * cfgrtl.h (prepend_insn_to_edge): New declaration.
1831         * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
1832         comment.
1833         (prepend_insn_to_edge): New function.
1834         * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
1835         insert_insn_on_edge.
1836
1837 2024-02-15  Richard Biener  <rguenther@suse.de>
1838
1839         PR tree-optimization/111156
1840         * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
1841         at the pattern stmt if any.
1842
1843 2024-02-15  Georg-Johann Lay  <avr@gjlay.de>
1844
1845         PR target/113927
1846         * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
1847         * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
1848         * config/avr/avr.cc (avr_adiw_reg_p): New function.
1849         (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
1850         Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
1851         * config/avr/avr.md: Same.
1852         (attr "isa") <tiny, no_tiny>: Remove.
1853         <adiw, no_adiw>: Add.
1854         (define_insn, define_insn_and_split): When an alternative has
1855         constraint "w", then set attribute "isa" to "adiw".
1856         * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
1857         Built-in define __AVR_HAVE_ADIW__.
1858         * doc/invoke.texi (AVR Options): Document it.
1859
1860 2024-02-15  Andrew Stubbs  <ams@baylibre.com>
1861
1862         * config/gcn/gcn-valu.md
1863         (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
1864         * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
1865         details are supported on RDNA devices.
1866
1867 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
1868
1869         PR middle-end/113508
1870         * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
1871         usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
1872         smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
1873         Add sentence about what the mode m is.
1874
1875 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
1876
1877         * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
1878         smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
1879         var.
1880
1881 2024-02-15  Richard Biener  <rguenther@suse.de>
1882
1883         * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
1884         stmts.
1885
1886 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
1887
1888         PR tree-optimization/113567
1889         * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
1890         _BitInt multiplication, division or modulo with
1891         SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
1892         force the affected inputs into a new SSA_NAME.
1893
1894 2024-02-14  Uros Bizjak  <ubizjak@gmail.com>
1895
1896         PR target/113871
1897         * config/i386/mmx.md (V248FI): New mode iterator.
1898         (V24FI_32): DItto.
1899         (vec_shl_<V248FI:mode>): New expander.
1900         (vec_shl_<V24FI_32:mode>): Ditto.
1901         (vec_shr_<V248FI:mode>): Ditto.
1902         (vec_shr_<V24FI_32:mode>): Ditto.
1903         * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
1904         (vec_shr_<V248FI:mode>): Ditto.
1905
1906 2024-02-14  Jan Hubicka  <jh@suse.cz>
1907
1908         PR tree-optimization/111054
1909         * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
1910
1911 2024-02-14  Tamar Christina  <tamar.christina@arm.com>
1912
1913         * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
1914
1915 2024-02-14  Richard Biener  <rguenther@suse.de>
1916
1917         PR tree-optimization/113910
1918         * bitmap.cc (bitmap_hash): Mix the full element "hash" to
1919         the hashval_t hash.
1920
1921 2024-02-14  Jakub Jelinek  <jakub@redhat.com>
1922
1923         * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
1924         (pp_integer_with_precision): For unsigned ptrdiff_t printing
1925         with u, o or x print ptrdiff_t argument converted to
1926         unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
1927
1928 2024-02-14  Richard Biener  <rguenther@suse.de>
1929
1930         PR middle-end/113576
1931         * expr.cc (do_store_flag): For vector bool compares of vectors
1932         with padding zero that.
1933         * dojump.cc (do_compare_and_jump): Likewise.
1934
1935 2024-02-14  Gerald Pfeifer  <gerald@pfeifer.com>
1936
1937         * doc/install.texi (Prerequisites): Update gettext link.
1938
1939 2024-02-13  H.J. Lu  <hjl.tools@gmail.com>
1940
1941         PR target/113876
1942         * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
1943         Return false if the incoming stack isn't 16-byte aligned.
1944
1945 2024-02-13  Tobias Burnus  <tburnus@baylibre.com>
1946
1947         PR middle-end/113904
1948         * omp-general.cc (struct omp_ts_info): Update for splitting of
1949         OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1950         * omp-selectors.h (enum omp_tp_type): Replace
1951         OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1952
1953 2024-02-13  Monk Chiang  <monk.chiang@sifive.com>
1954
1955         PR target/113742
1956         * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
1957         recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
1958
1959 2024-02-13  Richard Biener  <rguenther@suse.de>
1960
1961         PR tree-optimization/113895
1962         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1963         offset to discover constant array indices in bits, handle
1964         COMPONENT_REF to bitfields.
1965
1966 2024-02-13  Richard Biener  <rguenther@suse.de>
1967
1968         PR tree-optimization/113831
1969         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1970         typo in comment.
1971
1972 2024-02-13  Richard Biener  <rguenther@suse.de>
1973
1974         PR tree-optimization/113902
1975         * tree-vect-loop.cc (move_early_exit_stmts): Track
1976         last_seen_vuse for VUSE updating.
1977
1978 2024-02-13  Tamar Christina  <tamar.christina@arm.com>
1979
1980         PR tree-optimization/113734
1981         * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1982         an early break loop as partial.
1983
1984 2024-02-13  Richard Biener  <rguenther@suse.de>
1985
1986         PR tree-optimization/113898
1987         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1988         missing accumulated off adjustment.
1989
1990 2024-02-13  Jakub Jelinek  <jakub@redhat.com>
1991
1992         * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1993         instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1994         it against UINT_MAX and ULONG_MAX.
1995
1996 2024-02-13  David Malcolm  <dmalcolm@redhat.com>
1997
1998         * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1999         to...
2000         (emit_diagnostic_valist_meta): ...this.
2001         * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
2002         (emit_diagnostic_valist_meta): ...this.
2003
2004 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
2005
2006         PR tree-optimization/113849
2007         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
2008         fast path for widening casts where !m_upwards_2limb and lhs_type
2009         has precision which is a multiple of limb_prec.
2010
2011 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
2012
2013         PR c++/113674
2014         * attribs.cc (extract_attribute_substring): Remove.
2015         (lookup_scoped_attribute_spec): Don't call it.
2016
2017 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
2018
2019         * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
2020         and cast to fmt_size_t instead of %lu and cast to unsigned long.
2021
2022 2024-02-12  Christophe Lyon  <christophe.lyon@linaro.org>
2023
2024         * Makefile.in: Add no-info dependency.
2025         * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
2026         available.
2027         * configure: Regenerate.
2028
2029 2024-02-12  Iain Sandoe  <iain@sandoe.co.uk>
2030
2031         PR target/113855
2032         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
2033         available to all sub-targets.
2034         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2035         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2036
2037 2024-02-12  Richard Biener  <rguenther@suse.de>
2038
2039         PR tree-optimization/113831
2040         PR tree-optimization/108355
2041         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
2042         we see variable array indices and get_ref_base_and_extent
2043         can resolve those to constants fix up the ops to constants
2044         as well.
2045         (ao_ref_init_from_vn_reference): Use 'off' member for
2046         ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
2047         (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
2048
2049 2024-02-12  Pan Li  <pan2.li@intel.com>
2050
2051         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
2052         Replace args to arguments for misspelled term.
2053
2054 2024-02-12  Georg-Johann Lay  <avr@gjlay.de>
2055
2056         PR target/112944
2057         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
2058         <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
2059         when not linked with -mrodata-in-ram.
2060
2061 2024-02-12  Richard Biener  <rguenther@suse.de>
2062
2063         PR tree-optimization/113863
2064         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2065         Record crossed virtual PHIs.
2066         * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
2067         virtual PHIs.
2068
2069 2024-02-10  Marek Polacek  <polacek@redhat.com>
2070
2071         DR 2237
2072         PR c++/107126
2073         PR c++/97202
2074         * doc/invoke.texi: Document -Wtemplate-id-cdtor.
2075
2076 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
2077
2078         * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
2079         computation of idx for i == 4 of bitint_prec_huge.
2080
2081 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
2082
2083         PR middle-end/110754
2084         * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
2085         decls create PARM_DECL with pointer to original type, set
2086         TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
2087         DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
2088         (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
2089         wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
2090         (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
2091         of the var as argument.
2092
2093 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
2094
2095         * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
2096         size_t and precision 4 for ptrdiff_t.  Formatting fix.
2097         (pp_format): Document %{t,z}{d,i,u,o,x}.  Implement t and z modifiers.
2098         Formatting fixes.
2099         (test_pp_format): Test t and z modifiers.
2100         * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
2101
2102 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
2103
2104         * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
2105         sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
2106         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2107         * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
2108         and casts to fmt_size_t instead of "%ld" and casts to long.
2109         (print_value_expr_statistics, print_type_hash_statistics): Likewise.
2110         * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
2111         instead of "%lu" and casts to unsigned long.
2112         * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
2113         unsigned long.
2114         * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2115         and casts to fmt_size_t instead of "%ld" and casts to long.
2116         * cfgexpand.cc (dump_stack_var_partition): Use
2117         HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
2118         and casts to unsigned long.
2119         * gengtype.cc (adjust_field_rtx_def): Likewise.
2120         * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2121         and casts to fmt_size_t instead of "%ld" and casts to long.
2122         * postreload-gcse.cc (dump_hash_table): Likewise.
2123         * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
2124         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2125         (ggc_internal_alloc, ggc_free): Likewise.
2126         * genpreds.cc (write_lookup_constraint_1): Likewise.
2127         (write_insn_constraint_len): Likewise.
2128         * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
2129         and casts to fmt_size_t instead of "%ld" and casts to long.
2130         * varasm.cc (output_constant_pool_contents): Use
2131         HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
2132         * var-tracking.cc (dump_var): Likewise.
2133
2134 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
2135
2136         PR tree-optimization/113783
2137         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
2138         through VIEW_CONVERT_EXPR for final cast checks.  Handle
2139         VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
2140         INTEGER_TYPEs.
2141         (gimple_lower_bitint): Don't merge mergeable operations or other
2142         casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
2143         * expr.cc (expand_expr_real_1): Don't use convert_modes if either
2144         mode is BLKmode.
2145
2146 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
2147
2148         * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
2149         HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
2150         HOST_SIZE_T_PRINT_HEX_PURE): Define.
2151         * ira-conflicts.cc (build_conflict_bit_table): Use it.  Formatting
2152         fixes.
2153
2154 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
2155
2156         PR middle-end/113415
2157         * cfgexpand.cc (expand_asm_stmt): For asm goto, use
2158         duplicate_insn_chain to duplicate after_rtl_seq sequence instead
2159         of hand written loop with emit_insn of copy_insn and emit original
2160         after_rtl_seq on the last edge.
2161
2162 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
2163
2164         PR tree-optimization/113818
2165         * gimple-lower-bitint.cc (add_eh_edge): New function.
2166         (bitint_large_huge::handle_load,
2167         bitint_large_huge::lower_mergeable_stmt,
2168         bitint_large_huge::lower_muldiv_stmt): Use it.
2169
2170 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
2171
2172         PR tree-optimization/113774
2173         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
2174         emit any comparison if m_first and low + 1 is equal to
2175         m_upwards_2limb, simplify condition for that.  If not
2176         single_comparison, not m_first and we can prove that the idx <= low
2177         comparison will be always true, emit instead of idx <= low
2178         comparison low <= low such that cfg cleanup will optimize it at
2179         the end of the pass.
2180
2181 2024-02-08  Aldy Hernandez  <aldyh@redhat.com>
2182
2183         PR tree-optimization/113735
2184         * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
2185         limit_check().
2186
2187 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
2188
2189         * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
2190         (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
2191
2192 2024-02-08  H.J. Lu  <hjl.tools@gmail.com>
2193
2194         PR target/113711
2195         PR target/113733
2196         * config/i386/constraints.md: List all constraints with j prefix.
2197         (j>): Change auto-dec to auto-inc in documentation.
2198         (je): Changed to a memory constraint with APX NDD TLS operand
2199         check.
2200         (jM): New memory constraint for APX NDD instructions.
2201         (jO): Likewise.
2202         * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
2203         * config/i386/i386.cc (x86_poff_operand_p): Likewise.
2204         * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
2205         (*add<mode>_1[SWI48]): Use je and jM.
2206         (addsi_1_zext): Use jM.
2207         (*addv<dwi>4_doubleword_1[DWI]): Likewise.
2208         (*sub<mode>_1[SWI]): Use jM.
2209         (@add<mode>3_cc_overflow_1[SWI]): Likewise.
2210         (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
2211         (*and<dwi>3_doubleword): Likewise.
2212         (*anddi_1): Use jM.
2213         (*andsi_1_zext): Likewise.
2214         (*and<mode>_1[SWI24]): Likewise.
2215         (*<code><dwi>3_doubleword[any_or]): Use rjO
2216         (*code<mode>_1[any_or SWI248]): Use jM.
2217         (*<code>si_1_zext[zero_extend + any_or]): Likewise.
2218         * config/i386/predicates.md (apx_ndd_memory_operand): New.
2219         (apx_ndd_add_memory_operand): Likewise.
2220
2221 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
2222
2223         PR target/113824
2224         * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
2225         * doc/avr-mmcu.texi: Rebuild.
2226
2227 2024-02-08  Tamar Christina  <tamar.christina@arm.com>
2228
2229         PR tree-optimization/113808
2230         * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
2231         value cross iterations.
2232
2233 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
2234
2235         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
2236         defines __AVR_PM_BASE_ADDRESS__ if the core has it.
2237
2238 2024-02-08  Richard Biener  <rguenther@suse.de>
2239
2240         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2241         Revert last change to dr_may_alias_p.
2242
2243 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
2244
2245         * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
2246         cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
2247         Remove spec asm_misc.
2248         * config/avr/specs.h: Same.
2249
2250 2024-02-08  Pan Li  <pan2.li@intel.com>
2251
2252         PR target/113766
2253         * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
2254         sure the c.arg_num is >= 2 before checking.
2255         (struct build_frm_base): Ditto.
2256         (struct narrow_alu_def): Ditto.
2257
2258 2024-02-07  Richard Biener  <rguenther@suse.de>
2259
2260         PR tree-optimization/113796
2261         * tree-if-conv.cc (combine_blocks): Wipe range-info before
2262         replacing PHIs and inserting predicates.
2263
2264 2024-02-07  Roger Sayle  <roger@nextmovesoftware.com>
2265             Uros Bizjak  <ubizjak@gmail.com>
2266
2267         PR target/113690
2268         * config/i386/i386-features.cc (timode_convert_cst): New helper
2269         function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
2270         CONST_VECTOR.
2271         (timode_scalar_chain::convert_op): Use timode_convert_cst.
2272         (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
2273         Use timode_convert_cst.
2274
2275 2024-02-07  Victor Do Nascimento  <victor.donascimento@arm.com>
2276
2277         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
2278         * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
2279         (AARCH64_FL_DEBUGv8p9): Likewise.
2280         (AARCH64_FL_FGT2): Likewise.Likewise.
2281         (AARCH64_FL_ITE): Likewise.
2282         (AARCH64_FL_PFAR): Likewise.
2283         (AARCH64_FL_PMUv3_ICNTR): Likewise.
2284         (AARCH64_FL_PMUv3_SS): Likewise.
2285         (AARCH64_FL_PMUv3p9): Likewise.
2286         (AARCH64_FL_RASv2): Likewise.
2287         (AARCH64_FL_S1PIE): Likewise.
2288         (AARCH64_FL_S1POE): Likewise.
2289         (AARCH64_FL_S2PIE): Likewise.
2290         (AARCH64_FL_S2POE): Likewise.
2291         (AARCH64_FL_SCTLR2): Likewise.
2292         (AARCH64_FL_SEBEP): Likewise.
2293         (AARCH64_FL_SPE_FDS): Likewise.
2294         (AARCH64_FL_TCR2): Likewise.
2295
2296 2024-02-07  Richard Biener  <rguenther@suse.de>
2297
2298         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2299         Only check whether reads are in-bound in places that are not safe.
2300         Fix dependence check.  Add missing newline.  Clarify comments.
2301
2302 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
2303
2304         PR tree-optimization/113750
2305         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
2306         for single predecessor when doing early break vect.
2307         * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
2308         after labels.
2309
2310 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
2311
2312         PR tree-optimization/113731
2313         * gimple-iterator.cc (gsi_move_before): Take new parameter for update
2314         method.
2315         * gimple-iterator.h (gsi_move_before): Default new param to
2316         GSI_SAME_STMT.
2317         * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
2318         GSI_NEW_STMT.
2319
2320 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
2321
2322         PR tree-optimization/113756
2323         * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
2324         use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
2325         of lh_bits value and mask.
2326
2327 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
2328
2329         PR tree-optimization/113753
2330         * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
2331         UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
2332         not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
2333         so that they start with r[half_blocks_needed] lowest bit.  Fix up
2334         computation of top mask for SIGNED.
2335
2336 2024-02-07  Pan Li  <pan2.li@intel.com>
2337
2338         PR target/113766
2339         * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
2340         the signature of func.
2341         * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
2342         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
2343         overloaded func with empty args error.
2344
2345 2024-02-06  H.J. Lu  <hjl.tools@gmail.com>
2346
2347         PR target/113689
2348         * config/i386/i386.cc (x86_64_select_profile_regnum): Return
2349         R10_REG after sorry.
2350
2351 2024-02-06  Andrew Carlotti  <andrew.carlotti@arm.com>
2352
2353         * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
2354         Move before new caller, and add ".default" suffix.
2355         (get_suffixed_assembler_name): New.
2356         (make_resolver_func): Use get_suffixed_assembler_name.
2357         (aarch64_generate_version_dispatcher_body): Redo name mangling.
2358
2359 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
2360
2361         PR target/113763
2362         * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
2363         element from std::pair<unsigned int, char> to an unnamed struct.
2364         Adjust uses of tile range variable.
2365
2366 2024-02-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2367
2368         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
2369         (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
2370
2371 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
2372
2373         PR sanitizer/110676
2374         * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
2375         reset maxlen to sizetype maximum.
2376
2377 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
2378
2379         PR tree-optimization/113736
2380         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2381         var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
2382
2383 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
2384
2385         PR tree-optimization/113759
2386         * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
2387         or from_unsignedN differs from properties of typeN, update typeN
2388         to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
2389         uselessly convertible to typeN, convert it using fold_convert or
2390         build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
2391         (convert_plusminus_to_widen): Likewise.
2392
2393 2024-02-06  Tejas Belagod  <tejas.belagod@arm.com>
2394
2395         PR target/112577
2396         * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
2397         vector structure modes correctly.
2398
2399 2024-02-05  Christoph Müllner  <christoph.muellner@vrull.eu>
2400
2401         * config/riscv/thead.cc (th_print_operand_address): Fix compiler
2402         warning.
2403
2404 2024-02-05  H.J. Lu  <hjl.tools@gmail.com>
2405
2406         PR target/113689
2407         * config/i386/i386.cc (x86_64_select_profile_regnum): New.
2408         (x86_function_profiler): Call x86_64_select_profile_regnum to
2409         get a scratch register for large model profiling.
2410
2411 2024-02-05  Richard Ball  <richard.ball@arm.com>
2412
2413         * config/arm/arm.cc (arm_output_mi_thunk): Emit
2414         insn for bti_c when bti is enabled.
2415
2416 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
2417
2418         * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
2419         neg.
2420
2421 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
2422
2423         * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
2424         (neg<mode>2): Change the mode iterator from MSA to IMSA because
2425         in FP arithmetic we cannot use (0 - x) for -x.
2426         (neg<mode>2): New define_insn to implement FP vector negation,
2427         using a bnegi instruction to negate the sign bit.
2428
2429 2024-02-05  Richard Biener  <rguenther@suse.de>
2430
2431         PR tree-optimization/113707
2432         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
2433         checking the avail set treat out-of-region defines as
2434         available.
2435
2436 2024-02-05  Richard Biener  <rguenther@suse.de>
2437
2438         * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
2439         the default mode when building a pointer.
2440
2441 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
2442
2443         PR tree-optimization/113737
2444         * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
2445         has just a single label, remove it and make single successor edge
2446         EDGE_FALLTHRU.
2447
2448 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
2449
2450         PR target/113059
2451         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2452         Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
2453         df_analyze call.
2454
2455 2024-02-05  Richard Biener  <rguenther@suse.de>
2456
2457         PR target/113255
2458         * config/i386/i386-expand.cc
2459         (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
2460         Use a new pseudo for the skipped number of bytes.
2461
2462 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
2463
2464         * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
2465         * doc/invoke.texi (RISC-V Options): Add sifive-p450,
2466         sifive-p670.
2467
2468 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
2469
2470         * config/riscv/riscv.md: Include sifive-p400.md.
2471         * config/riscv/sifive-p400.md: New file.
2472         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2473         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2474         Add sifive_p400.
2475         * config/riscv/riscv.cc (sifive_p400_tune_info): New.
2476         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2477         * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2478
2479 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
2480
2481         * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
2482         Add missing ":SI" to the match_operator.
2483
2484 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
2485
2486         * config/xtensa/xtensa.md (SHI): New mode iterator.
2487         (2 split patterns related to constsynth):
2488         Change to also accept HImode operands.
2489
2490 2024-02-04  Jeff Law  <jlaw@ventanamicro.com>
2491
2492         * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
2493         similarly.
2494
2495 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
2496
2497         * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
2498         incorrect expand.
2499         * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
2500         (elmsgnbit): Likewise.
2501         (neg<mode:FVEC>2): New define_insn.
2502         * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
2503         are now instantiated in simd.md.
2504
2505 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
2506
2507         * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
2508         use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
2509         MAX_MACHINE_MODE.
2510
2511 2024-02-04  Li Wei  <liwei@loongson.cn>
2512
2513         * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
2514         (loongarch_expand_vselect_vconcat): Ditto.
2515         (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
2516         all 128-bit constant permutation situations.
2517         (loongarch_expand_lsx_shuffle): Adjust and rename function name.
2518         (loongarch_is_imm_set_shuffle): Renamed function name.
2519         (loongarch_expand_vec_perm_even_odd): Function forward declaration.
2520         (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
2521         extract-even and extract-odd permutations.
2522         (loongarch_is_odd_extraction): Delete.
2523         (loongarch_is_even_extraction): Ditto.
2524         (loongarch_expand_vec_perm_const): Adjust.
2525
2526 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
2527
2528         PR middle-end/113722
2529         * wide-int.cc (wi::bswap_large): Rename third argument from
2530         len to xlen and adjust use in safe_uhwi.  Add len variable, set
2531         it to BLOCKS_NEEDED (precision) and use it for clearing of val
2532         and as canonize argument.  Clear val using memset instead of
2533         a loop.
2534
2535 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
2536
2537         * ggc-common.cc (gt_pch_save): Allow addr to be equal to
2538         mmi.preferred_base + mmi.size - sizeof (void *).
2539
2540 2024-02-03  Xi Ruoyao  <xry111@xry111.site>
2541
2542         * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
2543         * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
2544         the ODR-violating locale declaration.
2545
2546 2024-02-02  Tamar Christina  <tamar.christina@arm.com>
2547
2548         PR tree-optimization/113588
2549         PR tree-optimization/113467
2550         * tree-vect-data-refs.cc
2551         (vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
2552         (vect_analyze_early_break_dependences): Update comments.
2553
2554 2024-02-02  John David Anglin  <danglin@gcc.gnu.org>
2555
2556         PR target/59778
2557         * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
2558         and PA_BUILTIN_SET_FPSR builtins.
2559         * (pa_builtins_icode): Declare.
2560         * (def_builtin, pa_fpu_init_builtins): New.
2561         * (pa_init_builtins): Initialize FPU builtins.
2562         * (pa_builtin_decl, pa_expand_builtin_1): New.
2563         * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
2564         PA_BUILTIN_SET_FPSR builtins.
2565         * (pa_atomic_assign_expand_fenv): New.
2566         * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
2567         UNSPECV constants.
2568         (get_fpsr, put_fpsr): New expanders.
2569         (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
2570         insn patterns.
2571
2572 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2573
2574         PR target/113697
2575         * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
2576
2577 2024-02-02  Jonathan Wakely  <jwakely@redhat.com>
2578
2579         * doc/extend.texi (Common Type Attributes): Fix typo in
2580         description of hardbool.
2581
2582 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
2583
2584         PR tree-optimization/113692
2585         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
2586         from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
2587         final_cast_p.
2588
2589 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
2590
2591         PR middle-end/113699
2592         * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
2593         uninitialized large/huge _BitInt SSA_NAME inputs.
2594
2595 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
2596
2597         PR middle-end/113705
2598         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
2599         around wi::to_wide in order to compare value in prec precision.
2600
2601 2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>
2602
2603         Revert:
2604         2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2605
2606         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2607
2608 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2609
2610         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2611
2612 2024-02-02  Pan Li  <pan2.li@intel.com>
2613
2614         * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
2615         (riscv_pass_by_reference): Ditto.
2616         (riscv_fntype_abi): Ditto.
2617
2618 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2619
2620         * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
2621         (pre_vsetvl::cleaup): Remove vsetvl_pre.
2622         (pre_vsetvl::remove_vsetvl_pre_insns): New function.
2623
2624 2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>
2625
2626         * config/loongarch/larchintrin.h
2627         (__frecipe_s): Update function return type.
2628         (__frecipe_d): Ditto.
2629         (__frsqrte_s): Ditto.
2630         (__frsqrte_d): Ditto.
2631
2632 2024-02-02  Li Wei  <liwei@loongson.cn>
2633
2634         * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
2635         (loongarch_vector_costs::add_stmt_cost): Adjust.
2636
2637 2024-02-02  Xi Ruoyao  <xry111@xry111.site>
2638
2639         * config/loongarch/loongarch.md (unspec): Add
2640         UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
2641         (la_pcrel64_two_parts): New define_insn.
2642         * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
2643         typo in the comment.
2644         (loongarch_call_tls_get_addr): If -mcmodel=extreme
2645         -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
2646         addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
2647         note to allow CSE addressing __tls_get_addr.
2648         (loongarch_legitimize_tls_address): If -mcmodel=extreme
2649         -mexplicit-relocs={always,auto}, address TLS IE symbols with
2650         la_pcrel64_two_parts.
2651         (loongarch_split_symbol): If -mcmodel=extreme
2652         -mexplicit-relocs={always,auto}, address symbols with
2653         la_pcrel64_two_parts.
2654         (loongarch_output_mi_thunk): Clean up unreachable code.  If
2655         -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
2656         thunks with la_pcrel64_two_parts.
2657
2658 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2659
2660         * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
2661         Add support for call36.
2662
2663 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2664
2665         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2666         When the code model of the symbol is extreme and -mexplicit-relocs=auto,
2667         the macro instruction loading symbol address is not applicable.
2668         (loongarch_call_tls_get_addr): Adjust code.
2669         (loongarch_legitimize_tls_address): Likewise.
2670
2671 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2672
2673         * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
2674         Add function declaration.
2675         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2676         For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
2677         is not allowed
2678         (loongarch_load_tls): Added macro support in extreme mode.
2679         (loongarch_call_tls_get_addr): Likewise.
2680         (loongarch_legitimize_tls_address): Likewise.
2681         (loongarch_force_address): Likewise.
2682         (loongarch_legitimize_move): Likewise.
2683         (loongarch_output_mi_thunk): Likewise.
2684         (loongarch_option_override_internal): Remove the code that detects
2685         explicit relocs status.
2686         (loongarch_handle_model_attribute): Likewise.
2687         * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
2688         * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
2689         (symbolic_off64_or_reg_operand): Likewise.
2690
2691 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2692
2693         * config/loongarch/loongarch.cc (loongarch_load_tls):
2694         Load all types of tls symbols through one function.
2695         (loongarch_got_load_tls_gd): Delete.
2696         (loongarch_got_load_tls_ld): Delete.
2697         (loongarch_got_load_tls_ie): Delete.
2698         (loongarch_got_load_tls_le): Delete.
2699         (loongarch_call_tls_get_addr): Modify the called function name.
2700         (loongarch_legitimize_tls_address): Likewise.
2701         * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
2702         (@load_tls<mode>): New template.
2703         (@got_load_tls_ld<mode>): Delete.
2704         (@got_load_tls_le<mode>): Delete.
2705         (@got_load_tls_ie<mode>): Delete.
2706
2707 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
2708
2709         * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
2710         (loongarch_legitimize_address): Add logical transformation code.
2711
2712 2024-02-01  Marek Polacek  <polacek@redhat.com>
2713
2714         * doc/invoke.texi: Update -Wdangling-reference documentation.
2715
2716 2024-02-01  Uros Bizjak  <ubizjak@gmail.com>
2717
2718         PR target/113701
2719         * config/i386/i386.md (*cmp<dwi>_doubleword):
2720         Do not force SUBREG pieces to pseudos.
2721
2722 2024-02-01  John David Anglin  <danglin@gcc.gnu.org>
2723
2724         * config/pa/pa.md (atomic_storedi_1): Fix bug in
2725         alternative 1.
2726
2727 2024-02-01  Georg-Johann Lay  <avr@gjlay.de>
2728
2729         * config/avr/avr.cc: Tabify.
2730
2731 2024-02-01  Richard Ball  <richard.ball@arm.com>
2732
2733         PR tree-optimization/111268
2734         * tree-vect-slp.cc (vectorizable_slp_permutation_1):
2735         Add variable-length check for vector input arguments
2736         to a function.
2737
2738 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2739
2740         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
2741         hard-code number of SGPR/VGPR/AVGPR registers.
2742         * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
2743         SGPR/VGPR/AVGPR registers.
2744
2745 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
2746
2747         * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
2748         attribute, and include sifive-p600.md.
2749         * config/riscv/generic-ooo.md: Update type attribute.
2750         * config/riscv/generic.md: Update type attribute.
2751         * config/riscv/sifive-7.md: Update type attribute.
2752         * config/riscv/sifive-p600.md: New file.
2753         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2754         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2755         Add sifive_p600.
2756         * config/riscv/riscv.cc (sifive_p600_tune_info): New.
2757         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2758         * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2759
2760 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
2761
2762         * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
2763         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
2764         * config/riscv/riscv.opt: New macro for 7 new unprivileged
2765         extensions.
2766         * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
2767         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
2768
2769 2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
2770
2771         * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
2772         -static-libasan.  Add missing whitespace.
2773
2774 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2775
2776         * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
2777         (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
2778         Don't 'define_constants'.
2779
2780 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2781
2782         * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
2783
2784 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
2785
2786         * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
2787         [TARGET_RDNA3]: Adjust.
2788
2789 2024-02-01  Richard Biener  <rguenther@suse.de>
2790
2791         PR tree-optimization/113693
2792         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
2793         data when available.
2794
2795 2024-02-01  Jakub Jelinek  <jakub@redhat.com>
2796             Jason Merrill  <jason@redhat.com>
2797
2798         PR c++/113531
2799         * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
2800         on variables which were promoted to TREE_STATIC.
2801
2802 2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
2803             Richard Biener  <rguenther@suse.de>
2804
2805         PR target/113560
2806         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
2807         information via tree_non_zero_bits to check if this operand
2808         is suitably extended for a widening (or highpart) multiplication.
2809         (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
2810         isn't already of the claimed type.
2811
2812 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2813
2814         Revert:
2815         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2816
2817         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2818         (generic_ooo_branch): ditto
2819         * config/riscv/generic.md (generic_sfb_alu): ditto
2820         (generic_fmul_half): ditto
2821         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2822         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2823         (sifive_7_popcount): ditto
2824         * config/riscv/vector.md: change rdfrm to fmove
2825         * config/riscv/zc.md: change pushpop to load/store
2826
2827 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2828
2829         Revert:
2830         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2831                     Robin Dapp  <rdapp.gcc@gmail.com>
2832
2833         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2834         (generic_ooo_vec_load): ditto
2835         (generic_ooo_vec_store): ditto
2836         (generic_ooo_vec_loadstore_seg): ditto
2837         (generic_ooo_vec_alu): ditto
2838         (generic_ooo_vec_fcmp): ditto
2839         (generic_ooo_vec_imul): ditto
2840         (generic_ooo_vec_fadd): ditto
2841         (generic_ooo_vec_fmul): ditto
2842         (generic_ooo_crypto): ditto
2843         (generic_ooo_perm): ditto
2844         (generic_ooo_vec_reduction): ditto
2845         (generic_ooo_vec_ordered_reduction): ditto
2846         (generic_ooo_vec_idiv): ditto
2847         (generic_ooo_vec_float_divsqrt): ditto
2848         (generic_ooo_vec_mask): ditto
2849         (generic_ooo_vec_vesetvl): ditto
2850         (generic_ooo_vec_setrm): ditto
2851         (generic_ooo_vec_readlen): ditto
2852         * config/riscv/riscv.md: include generic-vector-ooo
2853         * config/riscv/generic-vector-ooo.md: New file. to here
2854
2855 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2856
2857         Revert:
2858         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2859
2860         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2861
2862 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2863
2864         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2865
2866 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2867             Robin Dapp  <rdapp.gcc@gmail.com>
2868
2869         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2870         (generic_ooo_vec_load): ditto
2871         (generic_ooo_vec_store): ditto
2872         (generic_ooo_vec_loadstore_seg): ditto
2873         (generic_ooo_vec_alu): ditto
2874         (generic_ooo_vec_fcmp): ditto
2875         (generic_ooo_vec_imul): ditto
2876         (generic_ooo_vec_fadd): ditto
2877         (generic_ooo_vec_fmul): ditto
2878         (generic_ooo_crypto): ditto
2879         (generic_ooo_perm): ditto
2880         (generic_ooo_vec_reduction): ditto
2881         (generic_ooo_vec_ordered_reduction): ditto
2882         (generic_ooo_vec_idiv): ditto
2883         (generic_ooo_vec_float_divsqrt): ditto
2884         (generic_ooo_vec_mask): ditto
2885         (generic_ooo_vec_vesetvl): ditto
2886         (generic_ooo_vec_setrm): ditto
2887         (generic_ooo_vec_readlen): ditto
2888         * config/riscv/riscv.md: include generic-vector-ooo
2889         * config/riscv/generic-vector-ooo.md: New file. to here
2890
2891 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
2892
2893         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2894         (generic_ooo_branch): ditto
2895         * config/riscv/generic.md (generic_sfb_alu): ditto
2896         (generic_fmul_half): ditto
2897         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2898         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2899         (sifive_7_popcount): ditto
2900         * config/riscv/vector.md: change rdfrm to fmove
2901         * config/riscv/zc.md: change pushpop to load/store
2902
2903 2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>
2904
2905         PR target/113657
2906         * config/aarch64/aarch64-simd.md (split for movv8di):
2907         For strict aligned mode, use DImode instead of TImode.
2908
2909 2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>
2910
2911         PR middle-end/113607
2912         * match.pd: Make sure else values match when folding a
2913         vec_cond into a conditional operation.
2914
2915 2024-01-31  Marek Polacek  <polacek@redhat.com>
2916
2917         * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2918
2919 2024-01-31  Tamar Christina  <tamar.christina@arm.com>
2920             Matthew Malcomson  <matthew.malcomson@arm.com>
2921
2922         PR sanitizer/112644
2923         * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
2924         memcmp.
2925         * builtins.cc (expand_builtin): Include HWASAN when checking for
2926         builtin inlining.
2927
2928 2024-01-31  Richard Biener  <rguenther@suse.de>
2929
2930         PR middle-end/110176
2931         * match.pd (zext (bool) <= (int) 4294967295u): Make sure
2932         to match INTEGER_CST only without outstanding conversion.
2933
2934 2024-01-31  Alex Coplan  <alex.coplan@arm.com>
2935
2936         PR target/111677
2937         * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
2938         V16QImode for the full 16-byte FPR saves in the vector PCS case.
2939
2940 2024-01-31  Richard Biener  <rguenther@suse.de>
2941
2942         PR tree-optimization/111444
2943         * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
2944         vn_reference_lookup_2 when optimistically skipping may-defs.
2945
2946 2024-01-31  Richard Biener  <rguenther@suse.de>
2947
2948         PR tree-optimization/113630
2949         * tree-ssa-pre.cc (compute_avail): Avoid registering a
2950         reference with a representation with not matching base
2951         access size.
2952
2953 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
2954
2955         PR rtl-optimization/113656
2956         * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
2957         <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
2958
2959 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
2960
2961         PR debug/113637
2962         * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2963         with BLKmode are larger than DWARF2_ADDR_SIZE.
2964
2965 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
2966
2967         PR tree-optimization/113639
2968         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2969         For VIEW_CONVERT_EXPR set rhs1 to its operand.
2970
2971 2024-01-31  Richard Biener  <rguenther@suse.de>
2972
2973         PR tree-optimization/113670
2974         * tree-vect-data-refs.cc (vect_check_gather_scatter):
2975         Make sure we can take the address of the reference base.
2976
2977 2024-01-31  Georg-Johann Lay  <avr@gjlay.de>
2978
2979         * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2980         ATA5835, ATtiny64AUTO, ATA5700M322.
2981         * doc/avr-mmcu.texi: Rebuild.
2982
2983 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
2984
2985         PR debug/113394
2986         * ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
2987         caller.
2988
2989 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
2990
2991         PR middle-end/112917
2992         PR middle-end/113100
2993         * builtins.cc (expand_builtin_stack_address): Use
2994         STACK_ADDRESS_OFFSET.
2995         * doc/extend.texi (__builtin_stack_address): Adjust.
2996         * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2997         * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2998         * doc/tm.texi: Rebuilt.
2999
3000 2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3001
3002         PR target/113495
3003         * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
3004         (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
3005         (pre_vsetvl::compute_transparent): New function.
3006         (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
3007
3008 2024-01-30  Fangrui Song  <maskray@google.com>
3009
3010         PR target/105576
3011         * config/i386/constraints.md: Define constraint "Ws".
3012         * doc/md.texi: Document it.
3013
3014 2024-01-30  Marek Polacek  <polacek@redhat.com>
3015
3016         PR c++/110358
3017         PR c++/109640
3018         * doc/invoke.texi: Update -Wdangling-reference description.
3019
3020 2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
3021
3022         * config/xtensa/constraints.md (R, T, U):
3023         Change define_constraint to define_memory_constraint.
3024         * config/xtensa/predicates.md (move_operand): Don't check that a
3025         constant pool operand size is a multiple of UNITS_PER_WORD.
3026         * config/xtensa/xtensa.cc
3027         (xtensa_lra_p, TARGET_LRA_P): Remove.
3028         (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
3029         clause as it can no longer be true.
3030         (fixup_subreg_mem): Drop function.
3031         (xtensa_output_integer_literal_parts): Consider 16-bit wide
3032         constants.
3033         (xtensa_legitimate_constant_p): Add short-circuit path for
3034         integer load instructions. Don't check that mode size is
3035         at least UNITS_PER_WORD.
3036         * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
3037         rather reload_in_progress and reload_completed.
3038         (doloop_end): Drop operand 2.
3039         (movhi_internal): Add alternative loading constant from a
3040         literal pool.
3041         (define_split for DI register_operand): Don't limit to
3042         !TARGET_AUTO_LITPOOLS.
3043         * config/xtensa/xtensa.opt (mlra): Change to no effect.
3044
3045 2024-01-30  Pan Li  <pan2.li@intel.com>
3046
3047         * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
3048         calculate the gpr count required by vls mode.
3049         (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
3050         (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
3051         for vls mode.
3052         (riscv_get_arg_info): Add vls mode handling.
3053         (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
3054
3055 2024-01-30  Richard Biener  <rguenther@suse.de>
3056
3057         PR tree-optimization/113659
3058         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3059         Handle main exit without virtual use.
3060
3061 2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>
3062
3063         * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
3064
3065 2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>
3066
3067         PR libgcc/113403
3068         * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
3069         (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
3070         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
3071         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
3072         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
3073         * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
3074
3075 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
3076
3077         PR target/113623
3078         * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
3079         Mark all registers that occur in addresses as needing a GPR.
3080
3081 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
3082
3083         PR target/113636
3084         * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
3085         the containing insn as an extra parameter.  Reset debug instructions
3086         if they reference a register that is no longer used by real insns.
3087         (early_ra::apply_allocation): Update calls accordingly.
3088
3089 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
3090
3091         PR tree-optimization/113603
3092         * tree-ssa-strlen.cc (strlen_pass::handle_store): After
3093         count_nonzero_bytes call refetch si using get_strinfo in case it
3094         has been unshared in the meantime.
3095
3096 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
3097
3098         PR middle-end/101195
3099         * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
3100         fit into unsigned HOST_WIDE_INT, return constm1_rtx.
3101
3102 2024-01-30  Jin Ma  <jinma@linux.alibaba.com>
3103
3104         * config/riscv/thead.cc (th_print_operand_address): Change %ld
3105         to %lld.
3106
3107 2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
3108             Manolis Tsamis  <manolis.tsamis@vrull.eu>
3109             Philipp Tomsich  <philipp.tomsich@vrull.eu>
3110
3111         * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
3112         * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
3113         Likewise.
3114         * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
3115         Call on framework moved later.
3116
3117 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
3118
3119         * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
3120         instruction in naked function epilogues.
3121
3122 2024-01-29  YunQiang Su  <syq@gcc.gnu.org>
3123
3124         PR target/113655
3125         * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
3126         gcc_cv_as_mips_explicit_relocs.
3127         * configure: Regnerated.
3128
3129 2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>
3130
3131         PR target/108933
3132         * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
3133         Correct generated RTL.
3134         (arm_rev16si2_alt1): Correctly handle conditional execution.
3135         (arm_rev16si2_alt2): Likewise.
3136
3137 2024-01-29  Richard Biener  <rguenther@suse.de>
3138
3139         PR middle-end/113622
3140         * expr.cc (expand_assignment): Spill hard registers if
3141         we index them with a variable offset.
3142
3143 2024-01-29  Richard Biener  <rguenther@suse.de>
3144
3145         PR middle-end/113622
3146         * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
3147         Also allow DECL_HARD_REGISTER variables.
3148
3149 2024-01-29  Alex Coplan  <alex.coplan@arm.com>
3150
3151         PR target/113616
3152         * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
3153         Use iterate_safely when iterating over debug uses.
3154         (fixup_debug_uses): Likewise.
3155         (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
3156         over nondebug insns instead of manually maintaining the next insn.
3157         * iterator-utils.h (class safe_iterator): New.
3158         (iterate_safely): New.
3159
3160 2024-01-29  H.J. Lu  <hjl.tools@gmail.com>
3161
3162         PR target/38534
3163         * config/i386/i386-options.cc (ix86_set_func_type): Save
3164         callee-saved registers in noreturn functions for -O0/-Og.
3165
3166 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
3167
3168         PR target/113615
3169         * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
3170         define for !TARGET_RDNA2_PLUS.
3171
3172 2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
3173
3174         PR target/113281
3175         * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
3176         workaround for right shifts.
3177         (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
3178         (vect_determine_precisions_from_range): Be more selective about
3179         which codes can be narrowed based on their input and output ranges.
3180         For shifts, require at least one more bit of precision than the
3181         maximum shift amount.
3182
3183 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
3184
3185         * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
3186
3187 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
3188
3189         * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
3190         but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
3191         LLVM 13.0.1+.
3192
3193 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
3194
3195         PR other/111966
3196         * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
3197         (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
3198         (SET_SRAM_ECC_UNSET): ... this.
3199         (copy_early_debug_info): Remove gfx900 special case, now handled as
3200         part of the generic handling.
3201         (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
3202
3203 2024-01-29  Jakub Jelinek  <jakub@redhat.com>
3204
3205         PR tree-optimization/110603
3206         * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
3207         setting of pdata->maxlen to vr.upper_bound (which is unconditionally
3208         overwritten anyway).  Avoid creating invalid range with minlen
3209         larger than maxlen.  Formatting fix.
3210
3211 2024-01-29  Richard Biener  <rguenther@suse.de>
3212
3213         PR debug/103047
3214         * tree-inline.cc (initialize_inlined_parameters): Reverse
3215         the decl chain of inlined parameters.
3216
3217 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
3218
3219         * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
3220         alignment of CFString constants by setting DECL_USER_ALIGN.
3221
3222 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
3223             Jakub Jelinek   <jakub@redhat.com>
3224
3225         PR libgcc/113402
3226         * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
3227         and BUILT_IN_GCC_NESTED_PTR_DELETED.
3228         * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
3229         BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
3230         rename the library fallbacks to __gcc_nested_func_ptr_created and
3231         __gcc_nested_func_ptr_deleted.
3232         * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
3233         and __gcc_nested_func_ptr_deleted.
3234         * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
3235         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
3236         * tree.cc (build_common_builtin_nodes): Build the
3237         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
3238         builtins only for non-explicit.
3239
3240 2024-01-28  YunQiang Su  <syq@gcc.gnu.org>
3241
3242         * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
3243
3244 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
3245
3246         PR target/38534
3247         * config/i386/i386-options.cc (ix86_set_func_type): Don't
3248         save and restore callee saved registers for a noreturn function
3249         with nothrow or compiled with -fno-exceptions.
3250
3251 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
3252
3253         PR target/103503
3254         PR target/113312
3255         * config/i386/i386-expand.cc (ix86_expand_call): Replace
3256         no_caller_saved_registers check with call_saved_registers check.
3257         Clobber all registers that are not used by the callee with
3258         no_callee_saved_registers attribute.
3259         * config/i386/i386-options.cc (ix86_set_func_type): Set
3260         call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
3261         noreturn function.  Disallow no_callee_saved_registers with
3262         interrupt or no_caller_saved_registers attributes together.
3263         (ix86_set_current_function): Replace no_caller_saved_registers
3264         check with call_saved_registers check.
3265         (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
3266         (ix86_handle_call_saved_registers_attribute): This.
3267         (ix86_gnu_attributes): Add
3268         ix86_handle_call_saved_registers_attribute.
3269         * config/i386/i386.cc (ix86_conditional_register_usage): Replace
3270         no_caller_saved_registers check with call_saved_registers check.
3271         (ix86_function_ok_for_sibcall): Don't allow callee with
3272         no_callee_saved_registers attribute when the calling function
3273         has callee-saved registers.
3274         (ix86_comp_type_attributes): Also check
3275         no_callee_saved_registers.
3276         (ix86_epilogue_uses): Replace no_caller_saved_registers check
3277         with call_saved_registers check.
3278         (ix86_hard_regno_scratch_ok): Likewise.
3279         (ix86_save_reg): Replace no_caller_saved_registers check with
3280         call_saved_registers check.  Don't save any registers for
3281         TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
3282         TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
3283         no_callee_saved_registers attribute is called.
3284         (find_drap_reg): Replace no_caller_saved_registers check with
3285         call_saved_registers check.
3286         * config/i386/i386.h (call_saved_registers_type): New enum.
3287         (machine_function): Replace no_caller_saved_registers with
3288         call_saved_registers.
3289         * doc/extend.texi: Document no_callee_saved_registers attribute.
3290
3291 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
3292
3293         PR tree-optimization/113614
3294         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
3295         widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
3296         TRUNC_MOD_EXPR or FLOAT_EXPR uses.
3297
3298 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
3299
3300         PR tree-optimization/113568
3301         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
3302         For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
3303         in the widening extension checks.
3304
3305 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
3306
3307         * gimple-lower-bitint.cc (gimple_lower_bitint): For
3308         TDF_DETAILS dump mapping of SSA_NAMEs to decls.
3309
3310 2024-01-26  Hans-Peter Nilsson  <hp@axis.com>
3311
3312         * cgraphunit.cc (process_function_and_variable_attributes): Tweak
3313         the warning for an attribute-always_inline without inline declaration.
3314
3315 2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>
3316
3317         PR other/113575
3318         * genopinit.cc (main): Split init_all_optabs into functions
3319         of 1000 patterns each.
3320
3321 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
3322
3323         * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
3324         TM_MULTILIB_CONFIG.
3325         * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
3326         * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
3327         -march/-mtune.
3328
3329 2024-01-26  Andrew Stubbs  <ams@baylibre.com>
3330
3331         * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
3332         * config/gcn/gcn-valu.md (all_convert): New iterator.
3333         (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
3334         define_expand, and rename the old one to ...
3335         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
3336         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
3337         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
3338         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
3339         * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
3340         (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
3341         * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
3342         (<u>mulqihi3_scalar): Likewise.
3343
3344 2024-01-26  Richard Biener  <rguenther@suse.de>
3345
3346         PR tree-optimization/113602
3347         * tree-data-ref.cc (dr_analyze_innermost): Fail when
3348         the base object isn't addressable.
3349
3350 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
3351
3352         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
3353         "--amdhsa-code-object-version=" argument.
3354         (ASM_SPEC): Use it; replace previous version of it.
3355
3356 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3357
3358         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
3359         (pre_vsetvl::emit_vsetvl): Ditto.
3360
3361 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
3362
3363         * config/loongarch/lasx.md (vec_extract<mode>_0):
3364         New define_insn_and_split patten.
3365
3366 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
3367
3368         * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
3369
3370 2024-01-26  Li Wei  <liwei@loongson.cn>
3371
3372         * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
3373
3374 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3375
3376         PR target/113469
3377         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
3378
3379 2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>
3380
3381         PR target/100212
3382         * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
3383         undefined shift after the call to exact_log2.
3384
3385 2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>
3386
3387         PR target/100204
3388         * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
3389         before taking the negative of it.
3390
3391 2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>
3392
3393         PR target/113526
3394         * lra-constraints.cc (curr_insn_transform): Change class even for
3395         spilled pseudo successfully matched with with NO_REGS.
3396
3397 2024-01-25  Georg-Johann Lay  <avr@gjlay.de>
3398
3399         PR target/113601
3400         * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
3401
3402 2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
3403
3404         PR target/112987
3405         * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
3406         (aarch64_expand_epilogue): Use the new function.
3407         (aarch64_split_compare_and_swap): Likewise.
3408         (aarch64_split_atomic_op): Likewise.
3409
3410 2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>
3411
3412         PR middle-end/112971
3413         * fold-const.cc (simplify_const_binop): New function for binop
3414         simplification of two constant vectors when element-wise
3415         handling is not necessary.
3416         (const_binop): Call new function.
3417
3418 2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>
3419
3420         * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
3421         * config/riscv/constraints.md: Likewise.
3422         * config/riscv/corev.def: Likewise.
3423         * config/riscv/corev.md: Likewise.
3424         * config/riscv/predicates.md: Likewise.
3425         * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
3426         * config/riscv/riscv-ftypes.def: Likewise.
3427         * config/riscv/riscv.opt: Likewise.
3428         * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
3429         * doc/extend.texi: Add XCVbitmanip builtin documentation.
3430         * doc/sourcebuild.texi: Likewise.
3431
3432 2024-01-25  Tobias Burnus  <tburnus@baylibre.com>
3433
3434         * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
3435
3436 2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>
3437
3438         PR target/113538
3439         * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
3440         (riscv_fntype_abi): Ditto.
3441         * config/riscv/riscv.opt: Ditto.
3442
3443 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
3444
3445         PR middle-end/113574
3446         * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
3447         count against TYPE_PRECISION rather than TYPE_SIZE.
3448
3449 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
3450
3451         PR target/113572
3452         * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
3453         Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
3454
3455 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
3456
3457         PR target/113550
3458         * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
3459         whether each split instruction is a load that clobbers the source
3460         address.  Emit that instruction last if so.
3461
3462 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
3463
3464         PR target/113485
3465         * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
3466         pattern.
3467         (<optab><Vnarrowq><mode>2): Use it instead of generating a
3468         paradoxical subreg for the input.
3469
3470 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3471
3472         * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
3473         (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
3474         predecessors dump information.
3475
3476 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3477
3478         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
3479         redundant full available computation.
3480         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3481
3482 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
3483
3484         * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
3485         * doc/rtl.texi (CONST_VECTOR): Likewise.
3486
3487 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3488
3489         * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
3490         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
3491         (pass_vsetvl::execute): Ditto.
3492         * config/riscv/riscv.opt: Ditto.
3493
3494 2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>
3495
3496         * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
3497         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
3498
3499 2024-01-25  Richard Biener  <rguenther@suse.de>
3500
3501         PR tree-optimization/113576
3502         * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
3503         exits with may_be_zero niters when its the last one.
3504
3505 2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>
3506
3507         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3508         For symbols of type tls, non-zero Offset is not generated.
3509
3510 2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>
3511
3512         * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
3513         P9 with m32 and mpowerpc64.
3514
3515 2024-01-25  liuhongt  <hongtao.liu@intel.com>
3516
3517         * config/i386/i386-options.cc (ix86_option_override_internal):
3518         Enable -mlam=u57 by default when compiled with
3519         -fsanitize=hwaddress.
3520
3521 2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>
3522
3523         * common/config/riscv/riscv-common.cc (riscv_implied_info):
3524         Remove {"ztso", "a"}.
3525
3526 2024-01-24  Martin Jambor  <mjambor@suse.cz>
3527
3528         PR ipa/108007
3529         PR ipa/112616
3530         * cgraph.h (cgraph_edge): Add a parameter to
3531         redirect_call_stmt_to_callee.
3532         * ipa-param-manipulation.h (ipa_param_adjustments): Add a
3533         parameter to modify_call.
3534         (ipa_release_ssas_in_hash): Declare.
3535         * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
3536         parameter killed_ssas, pass it to padjs->modify_call.
3537         * ipa-param-manipulation.cc (purge_all_uses): New function.
3538         (ipa_param_adjustments::modify_call): New parameter killed_ssas.
3539         Instead of substituting uses, invoke purge_all_uses.  If
3540         hash of killed SSAs has not been provided, create a temporary one
3541         and release SSAs that have been added to it.
3542         (compare_ssa_versions): New function.
3543         (ipa_release_ssas_in_hash): Likewise.
3544         * tree-inline.cc (redirect_all_calls): Create
3545         id->killed_new_ssa_names earlier, pass it to edge redirection,
3546         adjust a comment.
3547         (copy_body): Release SSAs in id->killed_new_ssa_names.
3548
3549 2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>
3550
3551         PR target/113486
3552         * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
3553         TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
3554
3555 2024-01-24  Monk Chiang  <monk.chiang@sifive.com>
3556
3557         PR target/113095
3558         * config/riscv/sfb.md: New splitters to rewrite single bit
3559         sign extension as the condition to SFB instructions.
3560
3561 2024-01-24  Jan Hubicka  <jh@suse.cz>
3562
3563         PR middle-end/88345
3564         * common.opt: (flimit-function-alignment): Reorder alphabeticaly
3565         (fmin-function-alignment): New parameter.
3566         * doc/invoke.texi: (-fmin-function-alignment): Document.
3567         (-falign-functions,-falign-loops,-falign-labels): Mention that
3568         aglinments are ignored in cold code.
3569         * varasm.cc (assemble_start_function): Handle min-function-alignment.
3570
3571 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3572
3573         PR target/109636
3574         * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
3575         mulv2di3): Remove.
3576         * config/aarch64/iterators.md (VQDIV): Remove.
3577         (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
3578         SVE_I_SIMD_DI): New.
3579         (VPRED, sve_lane_con): Add V4SI and V2DI.
3580         * config/aarch64/aarch64-sve.md (<optab><mode>3,
3581         @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
3582         (mul<mode>3): New, split from <optab><mode>3.
3583         (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
3584         * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
3585         *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
3586         SVE_FULL_HSDI_SIMD_DI.
3587
3588 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3589
3590         PR tree-optimization/113552
3591         * config/aarch64/aarch64.cc
3592         (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
3593
3594 2024-01-24  Martin Jambor  <mjambor@suse.cz>
3595
3596         PR ipa/113490
3597         * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
3598         count is equal or greater than the limit.  Use the limit from the
3599         callee.
3600
3601 2024-01-24  YunQiang Su  <syq@gcc.gnu.org>
3602
3603         * configure.ac: Detect the explicit relocs support for
3604         mips, and define C macro MIPS_EXPLICIT_RELOCS.
3605         * config.in: Regenerated.
3606         * configure: Regenerated.
3607         * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
3608         * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
3609         * config/mips/mips.cc(mips_set_compression_mode): Sorry if
3610         !TARGET_EXPLICIT_RELOCS instead of just set it.
3611         * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
3612         TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
3613         * config/mips/mips.opt: Introduce -mexplicit-relocs= option
3614         and define -m(no-)explicit-relocs as aliases.
3615
3616 2024-01-24  Alex Coplan  <alex.coplan@arm.com>
3617
3618         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3619         to 1.
3620         (-mlate-ldp-fusion): Likewise.
3621
3622 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3623
3624         * tree-vect-loop.cc (vect_get_vect_def,
3625         vect_create_epilog_for_reduction): Rename main_exit_p to
3626         last_val_reduc_p.
3627
3628 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
3629
3630         PR tree-optimization/113364
3631         * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
3632         early exits then we must reduce from the first offset for all of them.
3633
3634 2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3635
3636         PR target/113495
3637         * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
3638         (get_regno): Ditto.
3639         (get_bb_index): Ditto.
3640         (pre_vsetvl::compute_avl_def_data): Ditto.
3641         (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
3642         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3643
3644 2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
3645             Richard Sandiford  <richard.sandiford@arm.com>
3646
3647         PR target/100942
3648         * ccmp.cc (ccmp_candidate_p): Add outer argument.
3649         Allow if the outer is true and the lhs is used more
3650         than once.
3651         (expand_ccmp_expr): Update call to ccmp_candidate_p.
3652         * expr.h (expand_expr_real_gassign): Declare.
3653         * expr.cc (expand_expr_real_gassign): New function, split out from...
3654         (expand_expr_real_1): ...here.
3655         * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
3656
3657 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3658
3659         PR target/113089
3660         * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
3661         (fixup_debug_use): New.
3662         (fixup_debug_uses_trailing_add): New.
3663         (fixup_debug_uses): New. Use it ...
3664         (ldp_bb_info::fuse_pair): ... here.
3665         (try_promote_writeback): Call fixup_debug_uses_trailing_add to
3666         fix up debug uses of the base register that are affected by
3667         folding in the trailing add insn.
3668
3669 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3670
3671         PR target/113089
3672         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
3673         Update trailing nondebug uses of the base register in the case
3674         of cancelling writeback.
3675
3676 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3677
3678         PR target/113089
3679         * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
3680         (debug_insn_use_iterator): New.
3681         (set_info::first_debug_insn_use): New.
3682         (set_info::debug_insn_uses): New.
3683         * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
3684         (set_info::first_debug_insn_use): New.
3685         (set_info::debug_insn_uses): New.
3686
3687 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3688
3689         PR target/113356
3690         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
3691         Don't record hazards against the opposite insn in the pair.
3692
3693 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3694
3695         PR target/113070
3696         * config/aarch64/aarch64-ldp-fusion.cc
3697         (struct stp_change_builder): New.
3698         (decide_stp_strategy): Reanme to ...
3699         (try_repurpose_store): ... this.
3700         (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
3701         construct stp changes.  Fix up uses when inserting new stp insns.
3702
3703 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3704
3705         PR target/113070
3706         * rtl-ssa.h: Include hash-set.h.
3707         * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
3708         new_sets parameter and use it to keep track of new user-created sets.
3709         (function_info::apply_changes_to_insn): Also call add_def on new sets.
3710         (function_info::change_insns): Add hash_set to keep track of new
3711         user-created defs.  Plumb it through.
3712         * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
3713         apply_changes_to_insn.
3714
3715 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3716
3717         PR target/113070
3718         * rtl-ssa/accesses.cc (function_info::create_use): New.
3719         * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
3720         Ensure new uses end up referring to permanent defs.
3721         * rtl-ssa/functions.h (function_info::create_use): Declare.
3722
3723 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3724
3725         PR target/113070
3726         * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
3727         to finalize_new_accesses from the backwards placement loop, run it
3728         forwards in a separate loop.
3729
3730 2024-01-23  Richard Biener  <rguenther@suse.de>
3731
3732         PR tree-optimization/113552
3733         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
3734         floor_log2 instead of exact_log2 on the number of calls.
3735
3736 2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
3737             Jakub Jelinek  <jakub@redhat.com>
3738
3739         * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
3740         decl.
3741
3742 2024-01-23  Richard Biener  <rguenther@suse.de>
3743
3744         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3745         Separate single and multi-exit case when creating PHIs between
3746         the main and epilogue.
3747
3748 2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>
3749
3750         PR target/112989
3751         * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
3752         MODE_single variants of functions that don't take tuple arguments.
3753
3754 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
3755
3756         PR target/113114
3757         * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
3758         Don't assert recog success, just punt if the writeback pair
3759         isn't recognized.
3760
3761 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
3762
3763         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
3764         ATTRIBUTE_UNUSED to decl.
3765
3766 2024-01-23  Richard Biener  <rguenther@suse.de>
3767
3768         PR debug/107058
3769         * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
3770         handle unexpected but bogus DIE contexts when not checking
3771         enabled.
3772
3773 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
3774
3775         PR tree-optimization/113462
3776         * fold-const.cc (native_interpret_int): Don't punt if total_bytes
3777         is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
3778         (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
3779         sizes between 129 and 8192 bytes.
3780
3781 2024-01-23  Xi Ruoyao  <xry111@xry111.site>
3782
3783         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3784         If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
3785         for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
3786         (loongarch_call_tls_get_addr): Do not split symbols of
3787         SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
3788         EXPLICIT_RELOCS_AUTO.
3789
3790 2024-01-23  Richard Biener  <rguenther@suse.de>
3791
3792         * alias.cc (known_base_value_p): Remove.
3793         (find_base_value): Remove PLUS/MINUS handling
3794         when both operands are not CONST_INT_P.
3795
3796 2024-01-23  Richard Biener  <rguenther@suse.de>
3797
3798         PR rtl-optimization/113255
3799         * alias.cc (find_base_term): Remove PLUS/MINUS handling
3800         when both operands are not CONST_INT_P.
3801
3802 2024-01-23  Richard Biener  <rguenther@suse.de>
3803
3804         PR debug/112718
3805         * dwarf2out.cc (dwarf2out_finish): Reset all type units
3806         for the fat part of an LTO compile.
3807
3808 2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>
3809
3810         * doc/sourcebuild.texi: Add attributes for keywords.
3811
3812 2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>
3813
3814         PR c++/90463
3815         * doc/invoke.texi (Warning Options): Correct lists of options
3816         enabled by -Wall and -Wextra by checking against common.opt
3817         and c-family/c.opt.
3818
3819 2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>
3820
3821         PR target/113030
3822         * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
3823         instead of cpu_optaliases.
3824         (check_arch): Use arch_opt_alias instead of arch_optaliases.
3825
3826 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3827
3828         * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
3829         * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
3830         * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
3831
3832 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3833
3834         PR target/109092
3835         * config/riscv/riscv.md: Use reg instead of subreg.
3836
3837 2024-01-22  Tobias Burnus  <tburnus@baylibre.com>
3838
3839         PR other/111966
3840         * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
3841         to match the compiler default.
3842         (simple_object_copy_lto_debug_sections): Never unlink the outfile
3843         on error as the caller does so.
3844         (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
3845         (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
3846
3847 2024-01-22  Richard Biener  <rguenther@suse.de>
3848
3849         PR tree-optimization/113373
3850         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3851         Create LC PHIs in the exit blocks where necessary.
3852         * tree-vect-loop.cc (vectorizable_live_operation): Do not try
3853         to handle missing LC PHIs.
3854         (find_connected_edge): Remove.
3855         (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
3856
3857 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3858
3859         * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
3860
3861 2024-01-22  xuli  <xuli1@eswincomputing.com>
3862
3863         PR target/113420
3864         * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
3865         (registered_function::overloaded_hash):refactor.
3866         (resolve_overloaded_builtin):avoid internal ICE.
3867
3868 2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>
3869
3870         PR target/82420
3871         PR target/111279
3872         * calls.cc (emit_library_call_value_1): Pass valid TYPE
3873         to emit_push_insn.
3874         * expr.cc (emit_push_insn): Likewise.
3875
3876 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
3877
3878         * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
3879         correcction version of last change.
3880
3881 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
3882
3883         * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
3884         fix bugs in signature.
3885
3886 2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
3887             Richard Biener  <rguenther@suse.de>
3888
3889         PR rtl-optimization/111267
3890         * fwprop.cc (fwprop_propagation::profitabe_p): Rename
3891         profitable_p method to likely_profitable_p.
3892         (try_fwprop_subst_node): Update call to likely_profitable_p.
3893         Only bail-out early when !prop.likely_profitable_p for instructions
3894         that are not single sets.  When comparing costs, bail-out if the
3895         cost is unchanged and !prop.likely_profitable_p.
3896
3897 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
3898
3899         PR c++/90464
3900         * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
3901         isn't enabled by -Wunused unless -Wextra is provided, and that
3902         -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
3903         -Wunused doesn't enable -Wunused-* options documented as behaving
3904         otherwise, and list them explicitly.
3905
3906 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
3907
3908         PR c/109708
3909         * doc/invoke.texi (Warning Options): Fix broken example and
3910         clean up/reorganize the others.  Also describe what the short-form
3911         options mean.
3912
3913 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
3914
3915         PR c/102998
3916         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
3917         (Warning Options): Correct/edit discussion of -Warray-parameter
3918         to make the first example less confusing, and fill in missing info.
3919
3920 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
3921
3922         PR tree-optimization/113462
3923         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
3924         Handle rhs1 INTEGER_CST like SSA_NAME.
3925
3926 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
3927
3928         PR tree-optimization/113491
3929         * tree-switch-conversion.cc (switch_conversion::build_constructors):
3930         If elt.index has precision higher than sizetype, fold_convert it to
3931         sizetype.
3932         (switch_conversion::array_value_type): Return type if type is
3933         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
3934         (switch_conversion::build_arrays): Use unsigned_type_for rather than
3935         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
3936         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
3937         higher than sizetype, use sizetype as tidx type and fold_convert the
3938         subtraction to sizetype.
3939
3940 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3941
3942         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
3943         (riscv_vector_mode_supported_any_target_p): Ditto.
3944
3945 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
3946
3947         PR target/110934
3948         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
3949         (TARGET_ZERO_CALL_USED_REGS): Define.
3950
3951 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
3952
3953         PR target/108640
3954         * config/m68k/m68k.cc (output_andsi3): Use QImode for
3955         address adjusted for 1-byte RMW access.
3956         (output_iorsi3): Likewise.
3957         (output_xorsi3): Likewise.
3958
3959 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
3960
3961         * doc/invoke.texi (RISC-V Options): Add list of supported
3962         extensions.
3963
3964 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3965
3966         PR target/113495
3967         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3968         (RVV_VUNDEF): Ditto.
3969         * config/riscv/riscv-vsetvl.cc: Add timevar.
3970
3971 2024-01-19  Richard Biener  <rguenther@suse.de>
3972
3973         PR debug/113488
3974         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3975         an early DIE but there should be, do not pretend there is.
3976
3977 2024-01-19  Richard Biener  <rguenther@suse.de>
3978
3979         PR tree-optimization/113494
3980         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3981         Handle endless loop on exit.  Handle re-allocated PHI.
3982
3983 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3984
3985         PR tree-optimization/113464
3986         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3987         optimize loads into GIMPLE_ASM stmts.
3988
3989 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3990
3991         PR tree-optimization/113463
3992         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3993         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3994         lhs.
3995
3996 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
3997
3998         PR tree-optimization/113459
3999         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
4000         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
4001         of SCALAR_INT_TYPE_MODE if type has BLKmode.
4002         (vn_reference_lookup_3): Likewise.  Formatting fix.
4003
4004 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
4005             Richard Biener  <rguenther@suse.de>
4006
4007         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
4008         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
4009         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
4010         but adjust_address also for BLKmode mode and MEM op0.
4011
4012 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
4013
4014         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
4015         extensions.
4016
4017 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4018
4019         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
4020
4021 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4022
4023         * common/config/riscv/riscv-common.cc
4024         (riscv_subset_list::parse_std_ext): Remove.
4025         (riscv_subset_list::parse_multiletter_ext): Remove.
4026         * config/riscv/riscv-subset.h
4027         (riscv_subset_list::parse_std_ext): Remove.
4028         (riscv_subset_list::parse_multiletter_ext): Remove.
4029
4030 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4031
4032         * common/config/riscv/riscv-common.cc
4033         (riscv_subset_list::parse_single_std_ext): New parameter.
4034         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4035         (riscv_subset_list::parse_single_ext): Ditto.
4036         (riscv_subset_list::parse): Relax the order for the input of ISA
4037         string.
4038         * config/riscv/riscv-subset.h
4039         (riscv_subset_list::parse_single_std_ext): New parameter.
4040         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4041         (riscv_subset_list::parse_single_ext): Ditto.
4042
4043 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4044
4045         * common/config/riscv/riscv-common.cc
4046         (riscv_subset_list::parse_base_ext): New.
4047         (riscv_subset_list::parse): Extract part of logic into
4048         riscv_subset_list::parse_base_ext.
4049         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
4050         New.
4051
4052 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4053
4054         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
4055         sorry message.
4056
4057 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
4058
4059         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
4060         UNSPEC_CLMUL_VC.
4061
4062 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
4063
4064         PR c/110029
4065         * doc/extend.texi (Common Variable Attributes): Explain what
4066         happens when multiple variables with cleanups are in the same scope.
4067
4068 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
4069
4070         PR ipa/108470
4071         * doc/extend.texi (Common Function Attributes): Document that
4072         noinline also disables some interprocedural optimizations and
4073         improve flow to the part about using inline asm instead to
4074         disable calls from being optimized away completely.  Remove the
4075         sentence that says noipa is mainly for internal compiler testing.
4076
4077 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
4078
4079         PR tree-optimization/69807
4080         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
4081
4082 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
4083
4084         PR target/108521
4085         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
4086         from x86 Windows Options.
4087
4088 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
4089
4090         PR c/107942
4091         * doc/extend.texi (C Extensions): Add new section to menu.
4092         (Function Attributes):  Move dangling index entries to....
4093         (Const and Volatile Functions): New section.
4094
4095 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
4096
4097         PR middle-end/112684
4098         * toplev.cc (toplev::main): Don't ICE in
4099         -fdiagnostics-generate-patch when exiting after options,
4100         since no edit context will have been created.
4101
4102 2024-01-18  Richard Biener  <rguenther@suse.de>
4103
4104         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
4105         operands vector.
4106
4107 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
4108
4109         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
4110         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
4111
4112 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4113             Jin Ma  <jinma@linux.alibaba.com>
4114             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4115             Christoph Müllner  <christoph.muellner@vrull.eu>
4116
4117         * config/riscv/thead.cc
4118         (th_asm_output_opcode): Rewrite some instructions.
4119
4120 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4121             Jin Ma  <jinma@linux.alibaba.com>
4122             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4123             Christoph Müllner  <christoph.muellner@vrull.eu>
4124
4125         * config/riscv/riscv.md (none,thv,rvv): New attribute.
4126         (no,yes): Add an attribute to disable alternative
4127         for xtheadvector or RVV1.0.
4128         * config/riscv/vector.md:
4129         Disable alternatives that destination register overlaps
4130         source register group for xtheadvector.
4131
4132 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4133             Jin Ma  <jinma@linux.alibaba.com>
4134             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4135             Christoph Müllner  <christoph.muellner@vrull.eu>
4136
4137         * config/riscv/riscv-vector-builtins-bases.cc
4138         (class th_loadstore_width): Define new builtin bases.
4139         (class th_extract): Define new builtin bases.
4140         (BASE): Define new builtin bases.
4141         * config/riscv/riscv-vector-builtins-bases.h:
4142         Define new builtin class.
4143         * config/riscv/riscv-vector-builtins-shapes.cc
4144         (struct th_loadstore_width_def): Define new builtin shapes.
4145         (struct th_indexed_loadstore_width_def):
4146         Define new builtin shapes.
4147         (struct th_extract_def): Define new builtin shapes.
4148         (SHAPE): Define new builtin shapes.
4149         * config/riscv/riscv-vector-builtins-shapes.h:
4150         Define new builtin shapes.
4151         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
4152         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
4153         * config/riscv/riscv-vector-builtins.h
4154         (enum required_ext): Add new XTheadVector member.
4155         (struct function_group_info): Likewise.
4156         * config/riscv/t-riscv:
4157         Add thead-vector-builtins-functions.def
4158         * config/riscv/thead-vector.md
4159         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
4160         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
4161         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
4162         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
4163         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
4164         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
4165         (@pred_th_extract<mode>): Likewise.
4166         (*pred_th_extract<mode>): Likewise.
4167         * config/riscv/thead-vector-builtins-functions.def: New file.
4168
4169 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4170             Jin Ma  <jinma@linux.alibaba.com>
4171             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4172             Christoph Müllner  <christoph.muellner@vrull.eu>
4173
4174         * config.gcc:  Add files for XTheadVector intrinsics.
4175         * config/riscv/autovec.md: Guard XTheadVector.
4176         * config/riscv/predicates.md: Disable immediate vl
4177         for XTheadVector.
4178         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
4179         Add pragma for XTheadVector.
4180         * config/riscv/riscv-string.cc (riscv_expand_block_move):
4181         Guard XTheadVector.
4182         * config/riscv/riscv-v.cc (vls_mode_valid_p):
4183         Avoid autovec.
4184         * config/riscv/riscv-vector-builtins-bases.cc:
4185         Do not normalize vsetvl instructions for XTheadVector.
4186         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
4187         New check type function.
4188         (build_one): Adjust for XTheadVector.
4189         * config/riscv/riscv-vector-switch.def (ENTRY):
4190         Disable fractional mode for the XTheadVector extension.
4191         (TUPLE_ENTRY): Likewise.
4192         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
4193         Guard XTheadVector.
4194         (riscv_preferred_simd_mode): Likewsie.
4195         (riscv_autovectorize_vector_modes): Likewise.
4196         (riscv_vector_mode_supported_any_target_p): Likewise.
4197         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
4198         * config/riscv/thead.cc (th_asm_output_opcode):
4199         Rewrite vsetvl instructions.
4200         * config/riscv/vector.md:
4201         Include thead-vector.md and change fractional LMUL
4202         into 1 for vbool.
4203         * config/riscv/riscv_th_vector.h: New file.
4204         * config/riscv/thead-vector.md: New file.
4205
4206 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4207             Jin Ma  <jinma@linux.alibaba.com>
4208             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4209             Christoph Müllner  <christoph.muellner@vrull.eu>
4210
4211         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
4212         Add new function to add assembler insn code prefix/suffix.
4213         (th_asm_output_opcode):
4214         Add Thead function to add assembler insn code prefix/suffix.
4215         * config/riscv/riscv.cc (riscv_asm_output_opcode):
4216         Implement function to add assembler insn code prefix/suffix.
4217         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
4218         Add new function to add assembler insn code prefix/suffix.
4219         * config/riscv/thead.cc (th_asm_output_opcode):
4220         Implement Thead function to add assembler insn code
4221         prefix/suffix.
4222
4223 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4224             Jin Ma  <jinma@linux.alibaba.com>
4225             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4226             Christoph Müllner  <christoph.muellner@vrull.eu>
4227
4228         * common/config/riscv/riscv-common.cc
4229         (riscv_subset_list::parse): Add new vendor extension.
4230         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
4231         Add test marco.
4232         * config/riscv/riscv.opt:  Add new mask.
4233
4234 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
4235
4236         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
4237         to be conditional on macosx-version-min.
4238
4239 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
4240
4241         * config/darwin.cc (darwin_objc1_section): Use the correct
4242         meta-data version for constant strings.
4243         (machopic_select_section): Assert if we fail to handle CFString
4244         sections as Obejctive-C meta-data or drectly.
4245
4246 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
4247
4248         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
4249         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
4250         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
4251         versions when the object format is Mach-O.
4252
4253 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
4254
4255         PR target/105522
4256         * config/darwin.cc (machopic_select_section): Handle C and C++
4257         CFStrings.
4258         (darwin_rename_builtins): Move this out of the CFString code.
4259         (darwin_libc_has_function): Likewise.
4260         (darwin_build_constant_cfstring): Create an anonymous var to
4261         hold each CFString.
4262         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
4263         CFstrings.
4264
4265 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
4266
4267         PR bootstrap/113445
4268         * haifa-sched.cc (dep_list_size): Make global.
4269         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
4270         * sched-int.h (dep_list_size): Declare.
4271
4272 2024-01-18  Martin Jambor  <mjambor@suse.cz>
4273
4274         PR tree-optimization/110422
4275         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
4276         gotos.
4277
4278 2024-01-18  Richard Biener  <rguenther@suse.de>
4279
4280         PR tree-optimization/113475
4281         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
4282         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
4283         (phi_analyzer::~phi_analyzer): Deallocate and free collected
4284         phi_grous.
4285         (phi_analyzer::process_phi): Record allocated phi_groups.
4286
4287 2024-01-18  Richard Biener  <rguenther@suse.de>
4288
4289         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
4290         storage for gvec_oprnds elements.
4291
4292 2024-01-18  Richard Biener  <rguenther@suse.de>
4293
4294         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
4295         prefer all later exits we can handle.
4296         (vect_analyze_loop_form): Free the allocated loop body.
4297         Adjust comments.
4298
4299 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4300
4301         * config/avr/avr-log.cc: Tabify.
4302
4303 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4304
4305         * config/riscv/autovec.md: Support vi variant.
4306
4307 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4308
4309         * config/avr/avr-devices.cc: Tabify.
4310
4311 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4312
4313         * config/avr/avr-c.cc: Tabify.
4314
4315 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4316
4317         * config/avr/driver-avr.cc: Tabify.
4318
4319 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4320
4321         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
4322
4323 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4324
4325         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
4326
4327 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
4328
4329         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
4330         minline-strcmp, minline-strncmp, minline-strlen,
4331         -param=riscv-vector-abi): Remove Bool keywords.
4332
4333 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
4334
4335         PR target/113122
4336         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
4337         support.  Add missing space after , in emitted assembly in some
4338         cases.  Formatting fixes.
4339
4340 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
4341
4342         * config/loongarch/loongarch.md (movsi_internal): Remove
4343         constraint z.
4344
4345 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
4346
4347         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
4348         in the diagnostic, and capitalize the device name.
4349         (print_mcu): Generate specs such that:
4350         <*check_rodata_in_ram>: New.
4351         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
4352         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
4353         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
4354
4355 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
4356
4357         PR other/113399
4358         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
4359         Common and Optimization.
4360
4361 2024-01-18  Richard Biener  <rguenther@suse.de>
4362
4363         PR tree-optimization/113431
4364         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
4365         When there is an invariant load we might not preserve
4366         scalar order.
4367
4368 2024-01-18  Richard Biener  <rguenther@suse.de>
4369
4370         PR tree-optimization/113374
4371         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
4372         * tree-vect-loop.cc (move_early_exit_stmts): Update
4373         virtual LC PHIs.
4374         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4375         Refactor.  Preserve virtual LC PHIs on all exits.
4376
4377 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
4378
4379         * config/loongarch/loongarch.cc (loongarch_split_symbol):
4380         Assign the '/u' attribute to the mem.
4381
4382 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
4383
4384         PR middle-end/110847
4385         * doc/invoke.texi (Option Summary): Document negative forms of
4386         -Wtsan and -Wxor-used-as-pow.
4387         (Warning Options): Likewise.
4388
4389 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4390
4391         PR target/113429
4392         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
4393
4394 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
4395
4396         * doc/extend.texi (Common Function Attributes): Re-alphabetize
4397         the table.
4398         (Common Variable Attributes): Likewise.
4399         (Common Type Attributes): Likewise.
4400
4401 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
4402
4403         PR middle-end/111659
4404         * doc/extend.texi (Common Variable Attributes): Fix long lines
4405         in documentation of strict_flex_array + other minor copy-editing.
4406         Add a cross-reference to -Wstrict-flex-arrays.
4407         * doc/invoke.texi (Option Summary): Fix whitespace in tables
4408         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
4409         (C Dialect Options): Combine the docs for the two
4410         -fstrict-flex-arrays forms into a single entry.  Note this option
4411         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
4412         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
4413         Minor copy-editing.  Add cross references to the strict_flex_array
4414         attribute and -fstrict-flex-arrays option.  Add note that this
4415         option depends on -ftree-vrp.
4416
4417 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
4418
4419         PR target/113221
4420         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
4421         only allow REG operands instead of allowing all.
4422
4423 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
4424
4425         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
4426         Remove redundant checks in else condition for readablity.
4427         (earliest_fuse_vsetvl_info) Print iteration count in debug
4428         prints.
4429         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
4430         dump details in certain cases.
4431
4432 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
4433
4434         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
4435         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
4436         * config/riscv/riscv-vsetvl.cc
4437         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
4438         (pass_vsetvl::execute): Use vsetvl_strategy.
4439
4440 2024-01-17  Jan Hubicka  <jh@suse.cz>
4441
4442         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
4443         accidental hack reseting offset.
4444
4445 2024-01-17  Jan Hubicka  <jh@suse.cz>
4446
4447         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
4448         handling of X86_TUNE_AVOID_512FMA_CHAINS.
4449
4450 2024-01-17  Jan Hubicka  <jh@suse.cz>
4451             Jakub Jelinek  <jakub@redhat.com>
4452
4453         PR tree-optimization/110852
4454         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
4455         binary operations
4456         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
4457         PRED_COMBINED_VALUE_PREDICTIONS_PHI
4458         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
4459         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
4460
4461 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4462
4463         PR tree-optimization/113421
4464         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
4465         comment.
4466         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
4467         formatting.  Start at vop rather than cvop even if stmt is a store
4468         and needs_operand_addr.
4469
4470 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4471
4472         PR middle-end/113410
4473         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
4474         If access_nelts is integral with larger precision than sizetype,
4475         fold_convert it to sizetype.
4476
4477 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4478
4479         PR tree-optimization/113408
4480         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
4481         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
4482         to handle_cast.
4483
4484 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4485
4486         PR middle-end/113406
4487         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
4488         regardless of whether is_gimple_reg_type (restype) or not.
4489
4490 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4491
4492         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
4493         funcions -> functions, and use were instead of was.
4494         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
4495         and guaranteee -> guarantee.
4496         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
4497
4498 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
4499
4500         PR middle-end/113409
4501         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
4502         INTEGER_TYPE.
4503         (omp_extract_for_data): Use build_bitint_type rather than
4504         build_nonstandard_integer_type if either iter_type or loop->v type
4505         is BITINT_TYPE.
4506         * omp-expand.cc (expand_omp_for_generic,
4507         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
4508         BITINT_TYPE like INTEGER_TYPE.
4509
4510 2024-01-17  Richard Biener  <rguenther@suse.de>
4511
4512         PR tree-optimization/113371
4513         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
4514         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4515         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
4516         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4517
4518 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
4519
4520         PR rtl-optimization/96388
4521         PR rtl-optimization/111554
4522         * sched-deps.cc (find_inc): Avoid exponential behavior.
4523
4524 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
4525
4526         PR c/111693
4527         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
4528         from C++ Language Options to Warning Options.  Add entry for
4529         -Wuse-after-free.
4530         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
4531         from here....
4532         (Warning Options): ...to here.  Minor copy-editing to fix typo
4533         and grammar.
4534
4535 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
4536
4537         * config/mips/mips.cc (mips_compute_frame_info): If another
4538         register is used as global_pointer, mark $GP live false.
4539
4540 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
4541
4542         PR target/112973
4543         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
4544         give the section a light copy-editing pass.
4545
4546 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
4547
4548         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
4549         * config/aarch64/aarch64-tune.md: Regenerated.
4550         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
4551
4552 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
4553
4554         PR target/112573
4555         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
4556         badly formed CONST expressions.
4557
4558 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
4559
4560         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
4561
4562 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
4563
4564         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
4565         * config/sparc/sync.md (membar_storeload): Turn into named insn
4566         and add GR712RC errata workaround.
4567         (membar_v8): Add GR712RC errata workaround.
4568
4569 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
4570
4571         * config/sparc/sync.md (*membar_storeload_leon3): Remove
4572         (*membar_storeload): Enable for LEON
4573
4574 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
4575
4576         PR tree-optimization/113372
4577         PR middle-end/90348
4578         PR middle-end/110115
4579         PR middle-end/111422
4580         * cfgexpand.cc (add_scope_conflicts_2): New function.
4581         (add_scope_conflicts_1): Use it.
4582
4583 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
4584
4585         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
4586         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
4587         * doc/avr-mmcu.texi: Regenerate.
4588
4589 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
4590
4591         PR tree-optimization/113091
4592         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
4593         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
4594         scalar use with new function.
4595         (vect_bb_slp_mark_live_stmts): New function as entry to existing
4596         overriden functions with same name.
4597         (vect_slp_analyze_operations): Call new entry function to mark
4598         live statements.
4599
4600 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4601
4602         PR target/113404
4603         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
4604         for RVV in big-endian mode.
4605
4606 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
4607
4608         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
4609         (riscv_pass_in_vector_p): Delete.
4610         (riscv_init_cumulative_args): Delete the checking.
4611         (riscv_get_arg_info): Delete the checking.
4612         (riscv_function_value): Delete the checking.
4613         * config/riscv/riscv.h: Delete the member for checking.
4614
4615 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
4616
4617         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
4618
4619 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
4620
4621         * config.gcc: Include riscv_bitmanip.h.
4622         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
4623         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
4624         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
4625         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
4626         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
4627         * config/riscv/riscv-ftypes.def (2): New ftypes.
4628         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
4629         (RISCV_BUILTIN_NO_PREFIX): Likewise.
4630         * config/riscv/riscv_bitmanip.h: New file.
4631
4632 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
4633
4634         * config.gcc: Include riscv_crypto.h.
4635         * config/riscv/riscv_crypto.h: New file.
4636
4637 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
4638
4639         PR middle-end/113354
4640         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
4641         in the insn if the corresponding operand does not require hard
4642         register anymore.
4643
4644 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
4645
4646         PR target/107201
4647         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
4648         * config/avr/driver-avr.cc (avr_no_devlib): New function.
4649         (avr_devicespecs_file): Use it to remove -nodevicelib from the
4650         options for cores only.
4651         * config/avr/avr-arch.h (avr_get_parch): New prototype.
4652         * config/avr/avr-devices.cc (avr_get_parch): New function.
4653
4654 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4655
4656         PR target/113247
4657         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
4658         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
4659         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
4660
4661 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4662
4663         PR target/113281
4664         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
4665         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
4666         * config/riscv/riscv-vector-costs.h: New function.
4667
4668 2024-01-15  Richard Biener  <rguenther@suse.de>
4669
4670         PR tree-optimization/113385
4671         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4672         First redirect, then split the exit edge.
4673
4674 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4675
4676         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
4677         Remove m_num_vector_iterations.
4678         * config/riscv/riscv-vector-costs.h: Ditto.
4679
4680 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
4681
4682         PR target/113156
4683         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
4684         (-mbranch-cost): Set "Optimization" flag.
4685
4686 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
4687
4688         PR tree-optimization/113370
4689         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
4690         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
4691         set it to just prec % limb_prec.
4692
4693 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4694
4695         PR target/113393
4696         * config/riscv/vector.md: Fix ternary attributes.
4697
4698 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
4699
4700         PR target/112944
4701         * configure.ac [target=avr]: Check availability of emulations
4702         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
4703         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
4704         * configure: Regenerate.
4705         * config.in: Regenerate.
4706         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
4707         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
4708         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
4709         * config/avr/avr-arch.h (enum avr_device_specific_features):
4710         Add AVR_ISA_FLMAP.
4711         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
4712         AVR_ISA_FLMAP.
4713         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
4714         (avr_set_core_architecture): Set avr_arch_index.
4715         (have_avrxmega2_flmap, have_avrxmega4_flmap)
4716         (have_avrxmega3_rodata_in_flash): Set new static const bool according
4717         to configure results.
4718         (avr_rodata_in_flash_p): New function using them.
4719         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
4720         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
4721         (avr_asm_named_section): Track avr_has_rodata_p.
4722         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
4723         and not avr_rodata_in_flash_p ().
4724         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
4725         (LINK_SPEC): Add %(link_rodata_in_ram).
4726         (LINK_ARCH_SPEC): Remove.
4727         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
4728         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
4729         const bool according to configure results.
4730         (diagnose_mrodata_in_ram): New function.
4731         (print_mcu): Generate specs with the following changes:
4732         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
4733         need to extend avr/specs.h each time we add a new bell or whistle.
4734         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
4735         -m[no-]rodata-in-ram.
4736         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
4737         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
4738         <*cpp>: Add %(cpp_rodata_in_ram).
4739         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
4740         requested.
4741         <*self_spec>: Add -mflmap or %<mflmap as needed.
4742
4743 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
4744
4745         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
4746         not the GPR iterator.  Adjust pattern name and mode attribute
4747         accordingly.
4748
4749 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
4750
4751         PR tree-optimization/113361
4752         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4753         Fix up determination of the type for > limb_prec constants.
4754
4755 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
4756
4757         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
4758         Add web-link to the avr-gcc wiki.
4759
4760 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
4761
4762         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
4763         documentation for a version without argument, which is not supported.
4764
4765 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4766
4767         * config/arm/arm_neon.h
4768         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
4769         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
4770         (vld1_f16_x4, vld1_f32_x4): New.
4771         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
4772         (vld1_bf16_x4): New.
4773         (vld1q_types_x4): Updated to use vld1q_x4
4774         from arm_neon_builtins.def
4775         * config/arm/arm_neon_builtins.def
4776         (vld1_x4): Updated entries.
4777         (vld1q_x4): New entries, but comes from the old vld1_x4
4778         * config/arm/neon.md
4779         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
4780
4781 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4782
4783         * config/arm/arm_neon.h
4784         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
4785         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
4786         (vld1_f16_x3, vld1_f32_x3): New.
4787         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
4788         (vld1_bf16_x3): New.
4789         (vld1q_types_x3): Updated to use vld1q_x3 from
4790         arm_neon_builtins.def
4791         * config/arm/arm_neon_builtins.def
4792         (vld1_x3): Updated entries.
4793         (vld1q_x3): New entries, but comes from the old vld1_x2
4794         * config/arm/neon.md
4795         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
4796
4797 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4798
4799         * config/arm/arm_neon.h
4800         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
4801         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
4802         (vld1_f16_x2, vld1_f32_x2): New.
4803         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
4804         (vld1_bf16_x2): New.
4805         (vld1q_types_x2): Updated to use vld1q_x2 from
4806         arm_neon_builtins.def
4807         * config/arm/arm_neon_builtins.def
4808         (vld1_x2): Updated entries.
4809         (vld1q_x2): New entries, but comes from the old vld1_x2
4810         * config/arm/neon.md
4811         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4812         neon_vld1_x2<mode>.
4813
4814 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4815
4816         * config/arm/arm_neon.h
4817         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
4818         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
4819         (vst1q_f16_x4, vst1q_f32_x4): New.
4820         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
4821         (vst1q_bf16_x4): New.
4822         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
4823         * config/arm/neon.md
4824         (neon_vst1q_x4<mode>): New.
4825         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
4826         * config/arm/unspecs.md
4827         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
4828
4829 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4830
4831         * config/arm/arm_neon.h
4832         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
4833         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
4834         (vst1q_f16_x3, vst1q_f32_x3): New.
4835         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
4836         (vst1q_bf16_x3): New.
4837         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
4838         * config/arm/neon.md
4839         (neon_vst1q_x3<mode>): New.
4840         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
4841         * config/arm/unspecs.md
4842         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
4843
4844 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4845
4846         * config/arm/arm_neon.h
4847         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
4848         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
4849         (vst1q_f16_x2, vst1q_f32_x2): New.
4850         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
4851         (vst1q_bf16_x2): New.
4852         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
4853         * config/arm/neon.md
4854         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4855         neon_vst1_x2<mode>.
4856         * config/arm/iterators.md
4857         (VMEMX2): New mode iterator.
4858         (VMEMX2_q): New mode attribute.
4859
4860 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4861
4862         * config/arm/arm_neon.h
4863         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
4864         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
4865         (vst1_f16_x4, vst1_f32_x4): New.
4866         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
4867         (vst1_bf16_x4): New.
4868         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
4869         * config/arm/neon.md (vst1_x4<mode>): New.
4870
4871 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4872
4873         * config/arm/arm_neon.h
4874         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
4875         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
4876         (vst1_f16_x3, vst1_f32_x3): New.
4877         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
4878         (vst1_bf16_x3): New.
4879         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
4880         * config/arm/neon.md (vst1_x3<mode>): New.
4881
4882 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4883
4884         * config/arm/arm_neon.h
4885         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
4886         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
4887         (vst1_f16_x2, vst1_f32_x2): New.
4888         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
4889         (vst1_bf16_x2): New.
4890         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
4891         * config/arm/neon.md (vst1_x2<mode>): New.
4892
4893 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4894
4895         * config/arm/arm_neon.h
4896         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
4897         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
4898         (vld1q_f16_x4, vld1q_f32_x4): New.
4899         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
4900         (vld1q_bf16_x4): New.
4901         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
4902         * config/arm/neon.md
4903         (neon_vld1_x4<mode>): New.
4904         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
4905         * config/arm/unspecs.md
4906         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
4907
4908 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4909
4910         * config/arm/arm_neon.h
4911         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
4912         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
4913         (vld1q_f16_x3, vld1q_f32_x3): New.
4914         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
4915         (vld1q_bf16_x3): New.
4916         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
4917         * config/arm/neon.md
4918         (neon_vld1_x3<mode>): New.
4919         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
4920         * config/arm/unspecs.md
4921         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
4922
4923 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
4924
4925         * config/arm/arm_neon.h
4926         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
4927         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
4928         (vld1q_f16_x2, vld1q_f32_x2): New.
4929         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
4930         (vld1q_bf16_x2): New.
4931         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
4932         * config/arm/neon.md (vld1_x2<mode>): New.
4933
4934 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4935
4936         PR tree-optimization/113287
4937         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
4938
4939 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4940
4941         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
4942         * tree-vect-loop.cc (vect_transform_loop): Likewise.
4943
4944 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4945
4946         PR tree-optimization/113178
4947         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
4948         alternate exits.
4949
4950 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4951
4952         PR tree-optimization/113237
4953         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
4954         existing LCSSA variable for exit when all exits are early break.
4955
4956 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4957
4958         PR tree-optimization/113137
4959         PR tree-optimization/113136
4960         PR tree-optimization/113172
4961         PR tree-optimization/113178
4962         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4963         Maintain PHIs on inverted loops.
4964         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4965         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4966         latch.
4967         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4968
4969 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
4970
4971         PR tree-optimization/113135
4972         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4973         dependency analysis.
4974
4975 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
4976
4977         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4978         diagnostics class member name for abort of error.
4979
4980 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
4981
4982         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4983         format string to %s argument.
4984
4985 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
4986             Jakub Jelinek  <jakub@redhat.com>
4987
4988         PR middle-end/113182
4989         * varasm.cc (process_pending_assemble_externals,
4990         assemble_external_libcall): Use targetm.strip_name_encoding
4991         before calling get_identifier.
4992
4993 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
4994
4995         PR target/113196
4996         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4997         New member variable.
4998         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4999         Declare.
5000         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
5001         * config/aarch64/aarch64-simd.md
5002         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
5003         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
5004         zip2 for zero-extends to...
5005         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
5006         instruction.  Fix big-endian handling.
5007         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
5008         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
5009         zip1 for zero-extends to...
5010         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
5011         Fix big-endian handling.
5012         (*aarch64_zip1_uxtl): New pattern.
5013         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
5014         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
5015         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
5016         (aarch64_gen_shareable_zero): Use it.
5017         (aarch64_split_simd_shift_p): New function.
5018
5019 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5020
5021         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
5022         (function_beg_insn): New macro.
5023         * function.cc (expand_function_start): Initialize function_beg_insn.
5024
5025 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5026
5027         PR target/112989
5028         * config/aarch64/aarch64-sve-builtins.h
5029         (function_builder::m_overload_names): Replace with...
5030         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
5031         new global.
5032         (add_overloaded_function): Update accordingly, using get_identifier
5033         to get a GGC-friendly record of the name.
5034
5035 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5036
5037         PR target/112989
5038         * config/aarch64/aarch64-sve-builtins.def: Don't include
5039         aarch64-sve-builtins-sme.def.
5040         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
5041         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
5042         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
5043         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
5044         requires AARCH64_FL_SME2.
5045         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
5046         AARCH64_FL_SME adjustment here.
5047         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
5048         include SME intrinsics.
5049         (sme_function_groups): New array.
5050         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
5051         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
5052
5053 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5054
5055         PR target/113281
5056         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
5057         (struct cpu_vector_cost): Add regmove struct.
5058         (get_vector_costs): Export as global.
5059         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
5060         (costs::add_stmt_cost): Ditto.
5061         * config/riscv/riscv.cc (get_common_costs): Export global function.
5062
5063 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5064
5065         PR tree-optimization/113334
5066         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
5067         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
5068         to determine if number should be extended by all ones rather than zero
5069         extended.
5070
5071 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5072
5073         PR tree-optimization/113330
5074         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
5075         too large size.
5076
5077 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5078
5079         PR tree-optimization/113323
5080         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
5081         check for lhs being large/huge _BitInt not in m_names.
5082
5083 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5084
5085         PR tree-optimization/113316
5086         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
5087         uninitialized large/huge _BitInt arguments to calls.
5088
5089 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5090
5091         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
5092         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
5093         CEIL (TYPE_PRECISION (t), limb_prec).
5094         (bitint_large_huge::handle_cast): Likewise.
5095
5096 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
5097
5098         PR sanitizer/113284
5099         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5100         Use assemble_function_label_final () for Power ELF V1 ABI.
5101         * output.h (assemble_function_label_final): New function.
5102         * varasm.cc (assemble_function_label_raw): Use
5103         assemble_function_label_final ().
5104         (assemble_function_label_final): New function.
5105
5106 2024-01-12  Richard Biener  <rguenther@suse.de>
5107
5108         PR middle-end/113344
5109         * match.pd ((double)float CMP (double)float -> float CMP float):
5110         Perform result type check only for vectors.
5111         * fold-const.cc (fold_binary_loc): Likewise.
5112
5113 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
5114
5115         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
5116         (usdot_prod<mode>): Ditto.
5117         (sdot_prod<mode>): Ditto.
5118         (udot_prod<mode>): Ditto.
5119
5120 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
5121
5122         PR target/113288
5123         * config/i386/i386-c.cc (ix86_target_macros_internal):
5124         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
5125
5126 2024-01-12  Richard Biener  <rguenther@suse.de>
5127
5128         PR target/112280
5129         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
5130         Do not generate code when d.testing_p.
5131
5132 2024-01-12  liuhongt  <hongtao.liu@intel.com>
5133
5134         PR target/113039
5135         * doc/invoke.texi (fcf-protection=): Update documents.
5136
5137 2024-01-12  Pan Li  <pan2.li@intel.com>
5138
5139         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
5140         comments of predicate func riscv_v_ext_mode_p.
5141
5142 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
5143
5144         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
5145                         Modify ABI-name length of vfloat16m8_t
5146
5147 2024-01-12  Li Wei  <liwei@loongson.cn>
5148
5149         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
5150         Adjust.
5151
5152 2024-01-12  Li Wei  <liwei@loongson.cn>
5153
5154         * config/loongarch/loongarch.md (add<mode>3): Removed.
5155         (*addsi3): New.
5156         (addsi3): Ditto.
5157         (adddi3): Ditto.
5158         (*addsi3_extended): Removed.
5159         (addsi3_extended): New.
5160
5161 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
5162
5163         * config/riscv/thead.md: Add limits for splits.
5164
5165 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
5166
5167         PR middle-end/113322
5168         * expr.cc (do_store_flag): Don't try single bit tests with
5169         comparison on vector types.
5170
5171 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
5172
5173         PR tree-optimization/113301
5174         * match.pd (`1/x`): Delay signed case until late.
5175
5176 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
5177
5178         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
5179         and -msp8 to...
5180         (AVR Internal Options): ...this new @subsubsection.
5181
5182 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
5183
5184         PR rtl-optimization/112918
5185         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
5186         (in_class_p): Restrict condition for narrowing class in case of
5187         allow_all_reload_class_changes_p.
5188         (process_alt_operands): Try to match operand without and with
5189         narrowing reg class.  Discourage narrowing the class.  Finish insn
5190         matching only if there is no class narrowing.
5191         (curr_insn_transform): Pass true to in_class_p for reg operand win.
5192
5193 2024-01-11  Richard Biener  <rguenther@suse.de>
5194
5195         PR tree-optimization/112505
5196         * tree-vect-loop.cc (vectorizable_induction): Reject
5197         bit-precision induction.
5198
5199 2024-01-11  Richard Biener  <rguenther@suse.de>
5200
5201         PR tree-optimization/113126
5202         * match.pd ((double)float CMP (double)float -> float CMP float):
5203         Make sure the boolean type is the same.
5204         * fold-const.cc (fold_binary_loc): Likewise.
5205
5206 2024-01-11  Richard Biener  <rguenther@suse.de>
5207
5208         PR tree-optimization/112636
5209         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
5210         estimate_numbers_of_iterations before querying
5211         get_max_loop_iterations_int.
5212         (pass_ch::execute): Initialize SCEV and loops appropriately.
5213
5214 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
5215
5216         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
5217         Reduced Tiny.
5218         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
5219         * doc/extend.texi (AVR Variable Attributes): Improve documentation
5220         of io, io_low and address attributes.
5221         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
5222         * doc/avr-mmcu.texi: Rebuild.
5223
5224 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
5225
5226         PR target/113233
5227         * config/loongarch/genopts/loongarch.opt.in: Mark options with
5228         the "Save" property.
5229         * config/loongarch/loongarch.opt: Same.
5230         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
5231         according to la_target.
5232         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
5233         RESTORE} for the la_target structure; Rename option conditions
5234         to have the same "la_" prefix.
5235         * config/loongarch/loongarch.h: Same.
5236
5237 2024-01-11  Pan Li  <pan2.li@intel.com>
5238
5239         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
5240         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
5241
5242 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
5243
5244         PR target/113077
5245         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
5246         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
5247         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
5248         synthesize these if needed.  Update caller ...
5249         (ldp_bb_info::fuse_pair): ... here.
5250         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
5251         and either insn is frame-related.
5252         (find_trailing_add): Punt on frame-related insns.
5253         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
5254         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
5255
5256 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
5257
5258         * config/mips/mips.cc (mips_start_function_definition):
5259         Add ATTRIBUTE_UNUSED.
5260
5261 2024-01-11  Richard Biener  <rguenther@suse.de>
5262
5263         PR middle-end/112740
5264         * expr.cc (store_constructor): Check the integer vector
5265         mask has a single bit per element before using sign-extension
5266         to expand an uniform vector.
5267
5268 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5269
5270         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
5271         preempt VLS on unknown NITERS loop.
5272
5273 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
5274
5275         * doc/invoke.texi: Add -mevex512.
5276
5277 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
5278
5279         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
5280         (*nor<mode>3): Likewise.
5281         (nor<mode>3): Likewise.
5282         (*negsi2_extended): New template.
5283         (*<optab>si3_internal): Likewise.
5284         (*one_cmplsi2_internal): Likewise.
5285         (*norsi3_internal): Likewise.
5286         (*<optab>nsi_internal): Likewise.
5287         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
5288         modified bit operation to make the optimization work.
5289
5290 2024-01-11  liuhongt  <hongtao.liu@intel.com>
5291
5292         PR target/104401
5293         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
5294
5295 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5296
5297         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
5298         (get_vector_costs): Ditto.
5299         (riscv_builtin_vectorization_cost): Ditto.
5300
5301 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5302
5303         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
5304
5305 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
5306
5307         PR jit/111396
5308         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
5309         ipa_free_size_summary.
5310         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
5311         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
5312         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
5313         * ipa-prop.h (ipa_prop_cc_finalize): New function.
5314         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
5315         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
5316         ipa_sra_cc_finalize): New functions.
5317         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
5318         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
5319         ipa_sra_cc_finalize
5320         Include ipa-utils.h.
5321
5322 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
5323
5324         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
5325         (th_int_get_save_adjustment): Likewise.
5326         (th_int_adjust_cfi_prologue): Likewise.
5327         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
5328         (TH_INT_INTERRUPT): New macro.
5329         (riscv_expand_prologue): Add the processing of XTheadInt.
5330         (riscv_expand_epilogue): Likewise.
5331         * config/riscv/riscv.h (BITSET_P): Moved to here.
5332         * config/riscv/riscv.md: New unspec.
5333         * config/riscv/thead.cc (th_int_get_mask): New function.
5334         (th_int_get_save_adjustment): Likewise.
5335         (th_int_adjust_cfi_prologue): Likewise.
5336         * config/riscv/thead.md (th_int_push): New pattern.
5337         (th_int_pop): new pattern.
5338
5339 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
5340
5341         PR tree-optimization/112468
5342         * doc/sourcebuild.texi: Document ifn_copysign.
5343         * match.pd: Only apply transformation if target supports the IFN.
5344
5345 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
5346
5347         PR tree-optimization/112581
5348         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
5349         mark_ssa_maybe_undefs.
5350         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
5351         variables can not be reassociated.
5352         (init_range_entry): Check for uninitialized variables too.
5353         (init_reassoc): Call mark_ssa_maybe_undefs.
5354
5355 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
5356
5357         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
5358         Also handle sign extension.
5359
5360 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
5361
5362         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5363         to 0.
5364         (-mlate-ldp-fusion): Likewise.
5365
5366 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
5367
5368         PR tree-optimization/113287
5369         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
5370         instead of using BRANCH_EDGE to determine true edge.
5371
5372 2024-01-10  Richard Biener  <rguenther@suse.de>
5373
5374         PR tree-optimization/113078
5375         * tree-vect-loop.cc (check_reduction_path): Canonicalize
5376         .COND_SUB to .COND_ADD.
5377
5378 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
5379
5380         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
5381         Handle prefix mappings before calling find_opt.
5382         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
5383         "-fno-"-prefixed command-line option.
5384         * opts-common.cc (get_option_prefix_remapping): New.
5385         * opts.h (get_option_prefix_remapping): New decl.
5386
5387 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
5388
5389         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
5390         m_urlifier to pp_output_formatted_text.
5391         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
5392         (obstack_append_string): New overload, taking a length.
5393         (urlify_quoted_string): Pass in an obstack ptr, rather than using
5394         that of the pp's buffer.  Generalize to handle trailing text in
5395         the buffer beyond the run of quoted text.
5396         (class quoting_info): New.
5397         (on_begin_quote): New.
5398         (on_end_quote): New.
5399         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
5400         it to calls to on_begin_quote and on_end_quote.
5401         (struct auto_obstack): New.
5402         (quoting_info::handle_phase_3): New.
5403         (pp_output_formatted_text): Add urlifier param.  Use it if there
5404         is deferred urlification.  Delete m_quotes.
5405         (selftest::pp_printf_with_urlifier): Pass urlifier to
5406         pp_output_formatted_text.
5407         (selftest::test_urlification): Update results for the existing
5408         case of quoted text stradding chunks; add more such test cases.
5409         * pretty-print.h (class quoting_info): New forward decl.
5410         (chunk_info::m_quotes): New field.
5411         (pp_output_formatted_text): Add optional urlifier param.
5412
5413 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
5414
5415         * pretty-print.cc (selftest::test_pp_format): Add selftest
5416         coverage for numbered args.
5417
5418 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
5419
5420         PR tree-optimization/113144
5421         PR tree-optimization/113145
5422         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5423         Update all BB that the original exits dominated.
5424
5425 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
5426
5427         * dwarf2out.cc (modified_type_die): Extend the support of reverse
5428         storage order to enumeration types if -gstrict-dwarf is not passed.
5429         (gen_enumeration_type_die): Add REVERSE parameter and generate the
5430         DIE immediately after the existing one if it is true.
5431         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
5432         call to gen_enumeration_type_die.
5433         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
5434         first recursive call as well as the call to gen_tagged_type_die.
5435         (gen_type_die): Add REVERSE parameter and pass it in the call to
5436         gen_type_die_with_usage.
5437
5438 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
5439
5440         PR tree-optimization/113120
5441         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
5442         with root->size TYPE_PRECISION don't build anything new.
5443         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
5444         rather than build_nonstandard_integer_type.
5445
5446 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
5447
5448         * config/i386/i386.opt: Adjust document.
5449         * doc/invoke.texi: Add description for
5450         -mapx-inline-asm-use-gpr32.
5451
5452 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5453
5454         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
5455         (avg<v_double_trunc>3_floor): New pattern.
5456         (<u>avg<v_double_trunc>3_ceil): Remove.
5457         (avg<v_double_trunc>3_ceil): New pattern.
5458         (uavg<mode>3_floor): Ditto.
5459         (uavg<mode>3_ceil): Ditto.
5460         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
5461         (enum insn_type): Ditto.
5462         * config/riscv/riscv-v.cc: Ditto.
5463         * config/riscv/vector-iterators.md (ashiftrt): Remove.
5464         (ASHIFTRT): Ditto.
5465         * config/riscv/vector.md: Add VLS modes.
5466
5467 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
5468
5469         PR target/111480
5470         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
5471         (vczlsbb_char): New int attribute.
5472         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
5473         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
5474         (*vctzlsbb_zext_<mode>): Rename to ...
5475         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
5476         cover vclzlsbb.
5477
5478 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
5479
5480         PR target/112606
5481         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
5482         of the last argument from altivec_register_operand to any_operand.  If
5483         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
5484         otherwise if it doesn't satisfy altivec_register_operand, force it to
5485         REG using copy_to_mode_reg.
5486
5487 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
5488
5489         PR middle-end/113100
5490         * builtins.cc (expand_builtin_stack_address): Guard stack point
5491         adjustment with SPARC_STACK_BOUNDARY_HACK.
5492
5493 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5494
5495         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
5496         argument string definitions.
5497         * config/loongarch/loongarch-str.h: Same.
5498         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
5499         as aliases to -mexplicit-relocs={always,none}
5500         * config/loongarch/loongarch.opt: Regenerate.
5501         * config/loongarch/loongarch.cc: Same.
5502
5503 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5504
5505         * config/loongarch/loongarch-def.h: Define constants with
5506         enums instead of Macros.
5507
5508 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5509
5510         * config/loongarch/genopts/loongarch-strings: Rename.
5511         * config/loongarch/genopts/loongarch.opt.in: Same.
5512         * config/loongarch/loongarch-cpu.cc: Same.
5513         * config/loongarch/loongarch-def.cc: Same.
5514         * config/loongarch/loongarch-def.h: Same.
5515         * config/loongarch/loongarch-opts.cc: Same.
5516         * config/loongarch/loongarch-opts.h: Same.
5517         * config/loongarch/loongarch-str.h: Same.
5518         * config/loongarch/loongarch.opt: Same.
5519
5520 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
5521
5522         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
5523         variable with the common la_ prefix.
5524         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
5525         flags as saved using TargetVariable.
5526         * config/loongarch/loongarch.opt: Same.
5527         * config/loongarch/loongarch-def.h: Define evolution_set to
5528         mark changes to the -march default.
5529         * config/loongarch/loongarch-driver.cc: Same.
5530         * config/loongarch/loongarch-opts.cc: Same.
5531         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
5532         conditions around the la_target structure.
5533         * config/loongarch/loongarch.cc: Same.
5534         * config/loongarch/loongarch.md: Same.
5535         * config/loongarch/loongarch-builtins.cc: Same.
5536         * config/loongarch/loongarch-c.cc: Same.
5537         * config/loongarch/lasx.md: Same.
5538         * config/loongarch/lsx.md: Same.
5539         * config/loongarch/sync.md: Same.
5540
5541 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
5542
5543         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
5544         no less.
5545
5546 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
5547
5548         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
5549
5550 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
5551
5552         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
5553         restart_loop.
5554         (vectorizable_live_operation): Likewise.
5555
5556 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
5557
5558         PR tree-optimization/113199
5559         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
5560         BIT_FIELD_REF.
5561
5562 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
5563
5564         PR target/113270
5565         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
5566         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
5567         GTY(()) declaration before the definition, drop GTY(()) drom the
5568         definition.
5569
5570 2024-01-09  Richard Biener  <rguenther@suse.de>
5571
5572         PR tree-optimization/113026
5573         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
5574         redundant and wrong niter bound setting.  Move niter
5575         bound adjustment down.
5576
5577 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
5578
5579         PR middle-end/113163
5580         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
5581         Reject non-linear inductions that aren't supported.
5582
5583 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
5584
5585         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
5586         left shift implementation strategies.
5587         (arc_shift_info): Type for each entry of the shift strategy table.
5588         (arc_shift_context_idx): Return a integer value for each code
5589         generation context, used as an index
5590         (arc_ashl_alg): Table indexed by context and shifted bit count.
5591         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
5592         left shift implementation.
5593         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
5594         provide accurate costs, when optimizing for speed or size.
5595
5596 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5597
5598         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
5599
5600 2024-01-09  Julian Brown  <julian@codesourcery.com>
5601
5602         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
5603         processed out before gimplification.
5604         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
5605         * tree.def (OMP_ARRAY_SECTION): New tree code.
5606
5607 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
5608
5609         PR tree-optimization/113210
5610         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
5611         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
5612         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
5613         minus 1.
5614
5615 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
5616
5617         PR rtl-optimization/113140
5618         * reorg.cc (fill_slots_from_thread): If we are to branch after the
5619         last instruction of the function, create an end label.
5620
5621 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
5622             Hongtao Liu  <hongtao.liu@intel.com>
5623
5624         PR target/112992
5625         * config/i386/i386-expand.cc
5626         (ix86_convert_const_wide_int_to_broadcast): Allow call to
5627         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
5628         (ix86_broadcast_from_constant): Revert recent change; Return a
5629         suitable MEMREF independently of mode/target combinations.
5630         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
5631         to decide whether expansion is possible/preferrable.  Only try
5632         forcing DImode constants to memory (and trying again) if calling
5633         ix86_expand_vector_init_duplicate fails with an DImode immediate
5634         constant.
5635         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
5636         V4SImode for suitable immediate constants.
5637         <case E_V4DImode>: Try using V8SImode for suitable constants.
5638         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
5639         <case E_V2HImode>: Likewise.
5640         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
5641         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
5642         <label widen>: Handle CONT_INTs via simplify_binary_operation.
5643         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
5644         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
5645         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
5646         (ix86_expand_vector_init): Move try using a broadcast for all_same
5647         with ix86_expand_vector_init_duplicate before using constant pool.
5648
5649 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
5650
5651         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
5652
5653 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
5654
5655         * config/arm/arm-cpus.in (cortex-m52): New cpu.
5656         * config/arm/arm-tables.opt: Regenerate.
5657         * config/arm/arm-tune.md: Regenerate.
5658
5659 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
5660
5661         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
5662         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
5663         (@vec_concatz<mode>): New insn pattern.
5664         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
5665         Handle VALS containing two vectors.
5666
5667 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5668
5669         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
5670         (vundefined): Ditto.
5671
5672 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
5673
5674         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5675                                 Add new function_base for crypto vector.
5676         (class bitmanip): Ditto.
5677         (class b_reverse):Ditto.
5678         (class vwsll):   Ditto.
5679         (class clmul):   Ditto.
5680         (class vg_nhab):  Ditto.
5681         (class crypto_vv):Ditto.
5682         (class crypto_vi):Ditto.
5683         (class vaeskf2_vsm3c):Ditto.
5684         (class vsm3me): Ditto.
5685         (BASE): Add BASE declaration for crypto vector.
5686         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5687         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5688                                 Add crypto vector intrinsic definition.
5689         (vbrev): Ditto.
5690         (vclz): Ditto.
5691         (vctz): Ditto.
5692         (vwsll): Ditto.
5693         (vandn): Ditto.
5694         (vbrev8): Ditto.
5695         (vrev8): Ditto.
5696         (vrol): Ditto.
5697         (vror): Ditto.
5698         (vclmul): Ditto.
5699         (vclmulh): Ditto.
5700         (vghsh): Ditto.
5701         (vgmul): Ditto.
5702         (vaesef): Ditto.
5703         (vaesem): Ditto.
5704         (vaesdf): Ditto.
5705         (vaesdm): Ditto.
5706         (vaesz): Ditto.
5707         (vaeskf1): Ditto.
5708         (vaeskf2): Ditto.
5709         (vsha2ms): Ditto.
5710         (vsha2ch): Ditto.
5711         (vsha2cl): Ditto.
5712         (vsm4k): Ditto.
5713         (vsm4r): Ditto.
5714         (vsm3me): Ditto.
5715         (vsm3c): Ditto.
5716         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5717                                 Add new function_shape for crypto vector.
5718         (struct crypto_vi_def): Ditto.
5719         (struct crypto_vv_no_op_type_def): Ditto.
5720         (SHAPE): Add SHAPE declaration of crypto vector.
5721         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5722         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5723                                 Add new data type for crypto vector.
5724         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5725         (vuint32mf2_t): Ditto.
5726         (vuint32m1_t): Ditto.
5727         (vuint32m2_t): Ditto.
5728         (vuint32m4_t): Ditto.
5729         (vuint32m8_t): Ditto.
5730         (vuint64m1_t): Ditto.
5731         (vuint64m2_t): Ditto.
5732         (vuint64m4_t): Ditto.
5733         (vuint64m8_t): Ditto.
5734         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5735                                 Add new data struct for crypto vector.
5736         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5737         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5738         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5739
5740 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
5741
5742         PR sanitizer/113251
5743         * varasm.cc (assemble_function_label_raw): Do not call
5744         asan_function_start () without the current function.
5745
5746 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
5747
5748         PR target/113225
5749         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
5750         extern and kernel_helper attributed function decls.
5751
5752 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
5753
5754         * btfout.cc (output_btf_strs): Changed.
5755
5756 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
5757
5758         * config/gcn/mkoffload.cc (main): Handle gfx1100
5759         when setting the default XNACK.
5760
5761 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
5762
5763         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
5764         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
5765         (ASM_SPEC): Handle gfx1100.
5766         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
5767         (enum gcn_isa): Add ISA_RDNA3.
5768         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
5769         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5770         * config/gcn/gcn.cc (gcn_option_override,
5771         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
5772         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
5773         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5774         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
5775         with gfx1100.
5776         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
5777         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
5778         __gfx1100__.
5779         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5780         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
5781         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
5782         (isa_has_combined_avgprs, main): Handle gfx1100.
5783         * config/gcn/t-omp-device (isa): Add gfx1100.
5784
5785 2024-01-08  Richard Biener  <rguenther@suse.de>
5786
5787         * doc/invoke.texi (-mmovbe): Clarify.
5788
5789 2024-01-08  Richard Biener  <rguenther@suse.de>
5790
5791         PR tree-optimization/113026
5792         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
5793         Avoid an epilog in more cases.
5794         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
5795         epilogues niter upper bounds and estimates.
5796
5797 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
5798
5799         PR tree-optimization/113228
5800         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
5801
5802 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
5803
5804         PR tree-optimization/113120
5805         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
5806         large _BitInt zero INTEGER_CST PHI argument.
5807
5808 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
5809
5810         PR tree-optimization/113119
5811         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
5812         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
5813         is before REALPART_EXPR.
5814
5815 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
5816
5817         PR target/112952
5818         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
5819         range when diagnosing attribute "io" and "io_low" are out of range.
5820         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
5821         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
5822         in contexts other than static storage.
5823         (avr_asm_output_aligned_decl_common): Move output of decls with
5824         attribute "address", "io", and "io_low" to...
5825         (avr_output_addr_attrib): ...this new function.
5826         (avr_asm_asm_output_aligned_bss): Remove output for decls with
5827         attribute "address", "io", and "io_low".
5828         (avr_encode_section_info): Rectify handling of decls with attribute
5829         "address", "io", and "io_low".
5830
5831 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
5832
5833         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
5834         (elf_flags): Remove XNACK from the default value.
5835         (main): Set a default XNACK according to the arch.
5836
5837 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
5838
5839         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
5840         (process_asm): Don't count avgprs.
5841
5842 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
5843
5844         * config/i386/i386.opt: Add supported sub-features.
5845         * doc/extend.texi: Add description for target attribute.
5846
5847 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
5848
5849         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
5850
5851 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
5852             Uros Bizjak  <ubizjak@gmail.com>
5853
5854         PR target/113231
5855         * config/i386/i386-features.cc (compute_convert_gain): Include
5856         the overhead of explicit load and store (movd) instructions when
5857         converting non-store scalar operations with memory destinations.
5858         Various indentation whitespace fixes.
5859
5860 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
5861
5862         * config/arm/neon.md (cbranch<mode>4): New.
5863
5864 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5865
5866         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
5867
5868 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
5869
5870         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
5871
5872 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5873
5874         PR target/113248
5875         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
5876         Update the MAX_SEW.
5877
5878 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5879
5880         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
5881         (variable_vectorized_p): Teach loop invariant.
5882         (has_unexpected_spills_p): Ditto.
5883
5884 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5885
5886         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
5887         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
5888         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
5889
5890 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
5891
5892         PR target/113104
5893         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
5894         (aarch64-vect-compare-costs): ...this.
5895         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
5896         Replace with...
5897         (-param=aarch64-vect-compare-costs=): ...this new param.
5898         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
5899         Don't disable it when vectorizing for Advanced SIMD only.
5900         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
5901         whenever aarch64_vect_compare_costs is true.
5902
5903 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
5904
5905         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
5906         Modify the method of determining the memory offset of [x]vld/[x]vst.
5907         (lasx_mxst_<lasxfmt_f>): Likewise.
5908         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
5909         (loongarch_address_insns): Likewise.
5910         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
5911         (lsx_st_<lsxfmt_f>): Likewise.
5912         * config/loongarch/predicates.md (aq10b_operand): Likewise.
5913         (aq10h_operand): Likewise.
5914         (aq10w_operand): Likewise.
5915         (aq10d_operand): Likewise.
5916
5917 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
5918
5919         PR target/113217
5920         * config/aarch64/aarch64-ldp-fusion.cc
5921         (ldp_bb_info::try_fuse_pair): If the second access can throw,
5922         narrow the move range to exactly that insn.
5923
5924 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
5925
5926         * asan.cc (asan_function_start): Drop switch_to_section ().
5927         (asan_emit_stack_protection): Set .LASANPC alignment.
5928         * config/i386/i386.cc: Use assemble_function_label_raw ()
5929         instead of ASM_OUTPUT_LABEL ().
5930         * config/s390/s390.cc (s390_asm_output_function_label):
5931         Likewise.
5932         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
5933         * final.cc (final_start_function_1): Drop
5934         asan_function_start ().
5935         * output.h (assemble_function_label_raw): New function.
5936         * varasm.cc (assemble_function_label_raw): Likewise.
5937
5938 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
5939
5940         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
5941         Use ASM_OUTPUT_FUNCTION_LABEL ().
5942         * config/alpha/alpha.cc (alpha_start_function): Likewise.
5943         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5944         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
5945         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5946         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5947         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
5948         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5949         * config/ia64/ia64.cc (ia64_start_function): Likewise.
5950         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
5951         Likewise.
5952         * config/microblaze/microblaze.cc (microblaze_function_prologue):
5953         Likewise.
5954         * config/mips/mips.cc (mips_start_unique_function): Return the
5955         tree.
5956         (mips_start_function_definition): Use
5957         ASM_OUTPUT_FUNCTION_LABEL ().
5958         (mips_finish_stub): Pass the tree to
5959         mips_start_function_definition ().
5960         (mips16_build_function_stub): Likewise.
5961         (mips16_build_call_stub): Likewise.
5962         (mips_output_function_prologue): Likewise.
5963         * config/pa/pa.cc (pa_output_function_label): Use
5964         ASM_OUTPUT_FUNCTION_LABEL ().
5965         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5966         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5967         Likewise.
5968         (rs6000_xcoff_declare_function_name): Likewise.
5969
5970 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
5971
5972         PR tree-optimization/113201
5973         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5974         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5975
5976 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
5977
5978         PR tree-optimization/90693
5979         * tree-ssa-math-opts.cc (match_single_bit_test): If
5980         tree_expr_nonzero_p (arg), remember it in the second argument to
5981         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5982         arg ^ (arg - 1) > arg - 1.
5983         * internal-fn.cc (expand_POPCOUNT): If second argument to
5984         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5985         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5986
5987 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
5988
5989         * config/riscv/riscv-v.cc (expand_load_store):
5990         Remove `value`.
5991         (expand_cond_len_op): Ditto.
5992         (expand_gather_scatter): Ditto.
5993         (expand_lanes_load_store): Ditto.
5994         (expand_fold_extract_last): Ditto.
5995
5996 2024-01-05  Pan Li  <pan2.li@intel.com>
5997
5998         Revert:
5999         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
6000
6001         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6002                                 Add new function_base for crypto vector.
6003         (class bitmanip): Ditto.
6004         (class b_reverse):Ditto.
6005         (class vwsll):   Ditto.
6006         (class clmul):   Ditto.
6007         (class vg_nhab):  Ditto.
6008         (class crypto_vv):Ditto.
6009         (class crypto_vi):Ditto.
6010         (class vaeskf2_vsm3c):Ditto.
6011         (class vsm3me): Ditto.
6012         (BASE): Add BASE declaration for crypto vector.
6013         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6014         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6015                                 Add crypto vector intrinsic definition.
6016         (vbrev): Ditto.
6017         (vclz): Ditto.
6018         (vctz): Ditto.
6019         (vwsll): Ditto.
6020         (vandn): Ditto.
6021         (vbrev8): Ditto.
6022         (vrev8): Ditto.
6023         (vrol): Ditto.
6024         (vror): Ditto.
6025         (vclmul): Ditto.
6026         (vclmulh): Ditto.
6027         (vghsh): Ditto.
6028         (vgmul): Ditto.
6029         (vaesef): Ditto.
6030         (vaesem): Ditto.
6031         (vaesdf): Ditto.
6032         (vaesdm): Ditto.
6033         (vaesz): Ditto.
6034         (vaeskf1): Ditto.
6035         (vaeskf2): Ditto.
6036         (vsha2ms): Ditto.
6037         (vsha2ch): Ditto.
6038         (vsha2cl): Ditto.
6039         (vsm4k): Ditto.
6040         (vsm4r): Ditto.
6041         (vsm3me): Ditto.
6042         (vsm3c): Ditto.
6043         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6044                                 Add new function_shape for crypto vector.
6045         (struct crypto_vi_def): Ditto.
6046         (struct crypto_vv_no_op_type_def): Ditto.
6047         (SHAPE): Add SHAPE declaration of crypto vector.
6048         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6049         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6050                                 Add new data type for crypto vector.
6051         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6052         (vuint32mf2_t): Ditto.
6053         (vuint32m1_t): Ditto.
6054         (vuint32m2_t): Ditto.
6055         (vuint32m4_t): Ditto.
6056         (vuint32m8_t): Ditto.
6057         (vuint64m1_t): Ditto.
6058         (vuint64m2_t): Ditto.
6059         (vuint64m4_t): Ditto.
6060         (vuint64m8_t): Ditto.
6061         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6062                                 Add new data struct for crypto vector.
6063         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6064         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6065         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6066
6067 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
6068
6069         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6070                                 Add new function_base for crypto vector.
6071         (class bitmanip): Ditto.
6072         (class b_reverse):Ditto.
6073         (class vwsll):   Ditto.
6074         (class clmul):   Ditto.
6075         (class vg_nhab):  Ditto.
6076         (class crypto_vv):Ditto.
6077         (class crypto_vi):Ditto.
6078         (class vaeskf2_vsm3c):Ditto.
6079         (class vsm3me): Ditto.
6080         (BASE): Add BASE declaration for crypto vector.
6081         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6082         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6083                                 Add crypto vector intrinsic definition.
6084         (vbrev): Ditto.
6085         (vclz): Ditto.
6086         (vctz): Ditto.
6087         (vwsll): Ditto.
6088         (vandn): Ditto.
6089         (vbrev8): Ditto.
6090         (vrev8): Ditto.
6091         (vrol): Ditto.
6092         (vror): Ditto.
6093         (vclmul): Ditto.
6094         (vclmulh): Ditto.
6095         (vghsh): Ditto.
6096         (vgmul): Ditto.
6097         (vaesef): Ditto.
6098         (vaesem): Ditto.
6099         (vaesdf): Ditto.
6100         (vaesdm): Ditto.
6101         (vaesz): Ditto.
6102         (vaeskf1): Ditto.
6103         (vaeskf2): Ditto.
6104         (vsha2ms): Ditto.
6105         (vsha2ch): Ditto.
6106         (vsha2cl): Ditto.
6107         (vsm4k): Ditto.
6108         (vsm4r): Ditto.
6109         (vsm3me): Ditto.
6110         (vsm3c): Ditto.
6111         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6112                                 Add new function_shape for crypto vector.
6113         (struct crypto_vi_def): Ditto.
6114         (struct crypto_vv_no_op_type_def): Ditto.
6115         (SHAPE): Add SHAPE declaration of crypto vector.
6116         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6117         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6118                                 Add new data type for crypto vector.
6119         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6120         (vuint32mf2_t): Ditto.
6121         (vuint32m1_t): Ditto.
6122         (vuint32m2_t): Ditto.
6123         (vuint32m4_t): Ditto.
6124         (vuint32m8_t): Ditto.
6125         (vuint64m1_t): Ditto.
6126         (vuint64m2_t): Ditto.
6127         (vuint64m4_t): Ditto.
6128         (vuint64m8_t): Ditto.
6129         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6130                                 Add new data struct for crypto vector.
6131         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6132         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6133         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6134
6135 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6136
6137         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6138
6139 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
6140
6141         PR tree-optimization/113186
6142         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
6143         Match `^` with the `==` for 1bit integral types.
6144         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
6145         integral types.
6146
6147 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6148
6149         * toplev.cc (general_init): Pass lang_mask to urlifier.
6150
6151 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6152
6153         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
6154         param.
6155         (diagnostic_context::make_option_url): Update for lang_mask param.
6156         * gcc-urlifier.cc: Include "opts.h" and "options.h".
6157         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
6158         (gcc_urlifier::m_lang_mask): New field.
6159         (doc_urls): Make static.
6160         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
6161         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6162         Look for an option by name before trying a binary search in
6163         doc_urls.
6164         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6165         (gcc_urlifier::get_url_suffix_for_option): New.
6166         (make_gcc_urlifier): Add lang_mask param.
6167         (selftest::gcc_urlifier_cc_tests): Update for above changes.
6168         Verify that a URL is found for "-fpack-struct".
6169         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
6170         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
6171         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
6172         to make_gcc_urlifier.
6173         * opts-diagnostic.h (get_option_url): Add lang_mask param.
6174         * opts.cc (get_option_html_page): Remove special-casing for
6175         analyzer and LTO.
6176         (get_option_url_suffix): New.
6177         (get_option_url): Reimplement.
6178         (selftest::test_get_option_html_page): Rename to...
6179         (selftest::test_get_option_url_suffix): ...this and update for
6180         above changes.
6181         (selftest::opts_cc_tests): Update for renaming.
6182         * opts.h: Include "rich-location.h".
6183         (get_option_url_suffix): New decl.
6184
6185 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6186
6187         * Makefile.in (ALL_OPT_URL_FILES): New.
6188         (GCC_OBJS): Add options-urls.o.
6189         (OBJS): Likewise.
6190         (OBJS-libcommon): Likewise.
6191         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
6192         inputs to opt-gather.awk.
6193         (options-urls.cc): New Makefile target.
6194         * opt-functions.awk (url_suffix): New function.
6195         (lang_url_suffix): New function.
6196         * options-urls-cc-gen.awk: New file.
6197         * opts.h (get_opt_url_suffix): New decl.
6198
6199 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6200
6201         * params.opt.urls: New file, autogenerated by
6202         regenerate-opt-urls.py.
6203
6204 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6205
6206         * common.opt.urls: New file, autogenerated by
6207         regenerate-opt-urls.py.
6208         * config/aarch64/aarch64.opt.urls: Likewise.
6209         * config/alpha/alpha.opt.urls: Likewise.
6210         * config/alpha/elf.opt.urls: Likewise.
6211         * config/arc/arc-tables.opt.urls: Likewise.
6212         * config/arc/arc.opt.urls: Likewise.
6213         * config/arm/arm-tables.opt.urls: Likewise.
6214         * config/arm/arm.opt.urls: Likewise.
6215         * config/arm/vxworks.opt.urls: Likewise.
6216         * config/avr/avr.opt.urls: Likewise.
6217         * config/bpf/bpf.opt.urls: Likewise.
6218         * config/c6x/c6x-tables.opt.urls: Likewise.
6219         * config/c6x/c6x.opt.urls: Likewise.
6220         * config/cris/cris.opt.urls: Likewise.
6221         * config/cris/elf.opt.urls: Likewise.
6222         * config/csky/csky.opt.urls: Likewise.
6223         * config/csky/csky_tables.opt.urls: Likewise.
6224         * config/darwin.opt.urls: Likewise.
6225         * config/dragonfly.opt.urls: Likewise.
6226         * config/epiphany/epiphany.opt.urls: Likewise.
6227         * config/fr30/fr30.opt.urls: Likewise.
6228         * config/freebsd.opt.urls: Likewise.
6229         * config/frv/frv.opt.urls: Likewise.
6230         * config/ft32/ft32.opt.urls: Likewise.
6231         * config/fused-madd.opt.urls: Likewise.
6232         * config/g.opt.urls: Likewise.
6233         * config/gcn/gcn.opt.urls: Likewise.
6234         * config/gnu-user.opt.urls: Likewise.
6235         * config/h8300/h8300.opt.urls: Likewise.
6236         * config/hpux11.opt.urls: Likewise.
6237         * config/i386/cygming.opt.urls: Likewise.
6238         * config/i386/cygwin.opt.urls: Likewise.
6239         * config/i386/djgpp.opt.urls: Likewise.
6240         * config/i386/i386.opt.urls: Likewise.
6241         * config/i386/mingw-w64.opt.urls: Likewise.
6242         * config/i386/mingw.opt.urls: Likewise.
6243         * config/i386/nto.opt.urls: Likewise.
6244         * config/ia64/ia64.opt.urls: Likewise.
6245         * config/ia64/ilp32.opt.urls: Likewise.
6246         * config/ia64/vms.opt.urls: Likewise.
6247         * config/iq2000/iq2000.opt.urls: Likewise.
6248         * config/linux-android.opt.urls: Likewise.
6249         * config/linux.opt.urls: Likewise.
6250         * config/lm32/lm32.opt.urls: Likewise.
6251         * config/loongarch/loongarch.opt.urls: Likewise.
6252         * config/lynx.opt.urls: Likewise.
6253         * config/m32c/m32c.opt.urls: Likewise.
6254         * config/m32r/m32r.opt.urls: Likewise.
6255         * config/m68k/ieee.opt.urls: Likewise.
6256         * config/m68k/m68k-tables.opt.urls: Likewise.
6257         * config/m68k/m68k.opt.urls: Likewise.
6258         * config/m68k/uclinux.opt.urls: Likewise.
6259         * config/mcore/mcore.opt.urls: Likewise.
6260         * config/microblaze/microblaze.opt.urls: Likewise.
6261         * config/mips/mips-tables.opt.urls: Likewise.
6262         * config/mips/mips.opt.urls: Likewise.
6263         * config/mips/sde.opt.urls: Likewise.
6264         * config/mmix/mmix.opt.urls: Likewise.
6265         * config/mn10300/mn10300.opt.urls: Likewise.
6266         * config/moxie/moxie.opt.urls: Likewise.
6267         * config/msp430/msp430.opt.urls: Likewise.
6268         * config/nds32/nds32-elf.opt.urls: Likewise.
6269         * config/nds32/nds32-linux.opt.urls: Likewise.
6270         * config/nds32/nds32.opt.urls: Likewise.
6271         * config/netbsd-elf.opt.urls: Likewise.
6272         * config/netbsd.opt.urls: Likewise.
6273         * config/nios2/elf.opt.urls: Likewise.
6274         * config/nios2/nios2.opt.urls: Likewise.
6275         * config/nvptx/nvptx-gen.opt.urls: Likewise.
6276         * config/nvptx/nvptx.opt.urls: Likewise.
6277         * config/openbsd.opt.urls: Likewise.
6278         * config/or1k/elf.opt.urls: Likewise.
6279         * config/or1k/or1k.opt.urls: Likewise.
6280         * config/pa/pa-hpux.opt.urls: Likewise.
6281         * config/pa/pa-hpux1010.opt.urls: Likewise.
6282         * config/pa/pa-hpux1111.opt.urls: Likewise.
6283         * config/pa/pa-hpux1131.opt.urls: Likewise.
6284         * config/pa/pa.opt.urls: Likewise.
6285         * config/pa/pa64-hpux.opt.urls: Likewise.
6286         * config/pdp11/pdp11.opt.urls: Likewise.
6287         * config/pru/pru.opt.urls: Likewise.
6288         * config/riscv/riscv.opt.urls: Likewise.
6289         * config/rl78/rl78.opt.urls: Likewise.
6290         * config/rpath.opt.urls: Likewise.
6291         * config/rs6000/476.opt.urls: Likewise.
6292         * config/rs6000/aix64.opt.urls: Likewise.
6293         * config/rs6000/darwin.opt.urls: Likewise.
6294         * config/rs6000/linux64.opt.urls: Likewise.
6295         * config/rs6000/rs6000-tables.opt.urls: Likewise.
6296         * config/rs6000/rs6000.opt.urls: Likewise.
6297         * config/rs6000/sysv4.opt.urls: Likewise.
6298         * config/rtems.opt.urls: Likewise.
6299         * config/rx/elf.opt.urls: Likewise.
6300         * config/rx/rx.opt.urls: Likewise.
6301         * config/s390/s390.opt.urls: Likewise.
6302         * config/s390/tpf.opt.urls: Likewise.
6303         * config/sh/sh.opt.urls: Likewise.
6304         * config/sh/superh.opt.urls: Likewise.
6305         * config/sol2.opt.urls: Likewise.
6306         * config/sparc/long-double-switch.opt.urls: Likewise.
6307         * config/sparc/sparc.opt.urls: Likewise.
6308         * config/stormy16/stormy16.opt.urls: Likewise.
6309         * config/v850/v850.opt.urls: Likewise.
6310         * config/vax/elf.opt.urls: Likewise.
6311         * config/vax/vax.opt.urls: Likewise.
6312         * config/visium/visium.opt.urls: Likewise.
6313         * config/vms/vms.opt.urls: Likewise.
6314         * config/vxworks-smp.opt.urls: Likewise.
6315         * config/vxworks.opt.urls: Likewise.
6316         * config/xtensa/elf.opt.urls: Likewise.
6317         * config/xtensa/uclinux.opt.urls: Likewise.
6318         * config/xtensa/xtensa.opt.urls: Likewise.
6319         * config/bfin/bfin.opt.urls: New file.
6320
6321 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6322
6323         * Makefile.in (OPT_URLS_HTML_DEPS): New.
6324         (regenerate-opt-urls): New target.
6325         (regenerate-opt-urls-unit-test): New target.
6326         * doc/options.texi (Option properties): Add UrlSuffix and
6327         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
6328         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
6329         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
6330         and Makefile.in's OPT_URLS_HTML_DEPS.
6331         (Anatomy of a Target Back End): Add
6332         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
6333         * regenerate-opt-urls.py: New file.
6334
6335 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
6336
6337         * diagnostic-format-sarif.cc
6338         (sarif_builder::make_logical_location_object): Convert to...
6339         (make_sarif_logical_location_object): ...this.
6340         (sarif_builder::set_any_logical_locs_arr): Update for above
6341         change.
6342         (sarif_builder::make_thread_flow_location_object): Call
6343         maybe_add_sarif_properties on each diagnostic_event.
6344         * diagnostic-format-sarif.h (class logical_location): New forward
6345         decl.
6346         (make_sarif_logical_location_object): New decl.
6347         * diagnostic-path.h (class sarif_object): New forward decl.
6348         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
6349
6350 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
6351             Patrick Lin  <patrick@andestech.com>
6352             Rufus Chen  <rufus@andestech.com>
6353             Monk Chiang  <monk.chiang@sifive.com>
6354
6355         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
6356         with Nan-boxing value.
6357         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
6358
6359 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
6360             Jeff Law  <jlaw@ventanamicro.com>
6361
6362         PR rtl-optimization/104914
6363         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
6364         a sign or zero extension is only required if the modified field
6365         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
6366         targets, don't refer to the temporarily incorrectly extended value
6367         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
6368
6369 2024-01-04  Pan Li  <pan2.li@intel.com>
6370
6371         Revert:
6372         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6373
6374         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6375
6376 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6377
6378         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6379
6380 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
6381
6382         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
6383         offset of fcsr.
6384
6385 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6386
6387         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
6388         (compute_nregs_for_mode): Refine LMUL.
6389         (max_number_of_live_regs): Ditto.
6390         (compute_estimated_lmul): Ditto.
6391         (has_unexpected_spills_p): Ditto.
6392
6393 2024-01-04  Li Wei  <liwei@loongson.cn>
6394
6395         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
6396         Remove useless forward declaration.
6397         (loongarch_is_even_extraction): Remove useless forward declaration.
6398         (loongarch_try_expand_lsx_vshuf_const): Removed.
6399         (loongarch_expand_vec_perm_const_1): Merged.
6400         (loongarch_is_double_duplicate): Removed.
6401         (loongarch_is_center_extraction): Ditto.
6402         (loongarch_is_reversing_permutation): Ditto.
6403         (loongarch_is_di_misalign_extract): Ditto.
6404         (loongarch_is_si_misalign_extract): Ditto.
6405         (loongarch_is_lasx_lowpart_extract): Ditto.
6406         (loongarch_is_op_reverse_perm): Ditto.
6407         (loongarch_is_single_op_perm): Ditto.
6408         (loongarch_is_divisible_perm): Ditto.
6409         (loongarch_is_triple_stride_extract): Ditto.
6410         (loongarch_expand_vec_perm_const_2): Merged.
6411         (loongarch_expand_vec_perm_const): New.
6412         (loongarch_vectorize_vec_perm_const): Adjust.
6413
6414 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
6415
6416         * omp-general.cc: Fix comment typos and misplaced/confusing
6417         comments.  Delete redundant include of omp-general.h.
6418
6419 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
6420
6421         PR rtl-optimization/104914
6422         * config/mips/mips.md (insqisi_extended): New patterns.
6423         (inshisi_extended): Ditto.
6424
6425 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
6426
6427         * config/mips/mips.cc (mips_insn_cost): New function.
6428
6429 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
6430
6431         * config/mips/mips.md (perf_ratio): New attribute.
6432
6433 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6434
6435         PR target/113206
6436         PR target/113209
6437         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
6438         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
6439         blocks belong to infinite loop.
6440         (pre_vsetvl::emit_vsetvl): Remove fake edges.
6441         * config/riscv/t-riscv: Add a new include file.
6442
6443 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6444
6445         * config/riscv/vector.md: Fix indent.
6446
6447 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
6448
6449         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
6450         OMP_CLAUSE__SIMDUID_.
6451         * tree.cc (omp_clause_num_ops): Update position of entry for
6452         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
6453         (omp_clause_code_name): Likewise.
6454
6455 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
6456
6457         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
6458         printing of FUNC_MAP/IND_FUNC_MAP labels.
6459
6460 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
6461
6462         * gcc.cc (process_command): Update copyright notice dates.
6463         * gcov-dump.cc (print_version): Ditto.
6464         * gcov.cc (print_version): Ditto.
6465         * gcov-tool.cc (print_version): Ditto.
6466         * gengtype.cc (create_file): Ditto.
6467         * doc/cpp.texi: Bump @copying's copyright year.
6468         * doc/cppinternals.texi: Ditto.
6469         * doc/gcc.texi: Ditto.
6470         * doc/gccint.texi: Ditto.
6471         * doc/gcov.texi: Ditto.
6472         * doc/install.texi: Ditto.
6473         * doc/invoke.texi: Ditto.
6474
6475 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
6476
6477         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
6478         (fmin<mode>3): Likewise.
6479         (reduc_fmax_scal_<mode>3): New define_expand.
6480         (reduc_fmin_scal_<mode>3): Likewise.
6481
6482 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6483
6484         PR target/113112
6485         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
6486         (max_number_of_live_regs): Ditto.
6487         (has_unexpected_spills_p): Ditto.
6488
6489 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6490             Jin Ma  <jinma@linux.alibaba.com>
6491             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6492             Christoph Müllner  <christoph.muellner@vrull.eu>
6493
6494         * config/riscv/vector.md:
6495         Use vector_length_operand for vsetvl patterns.
6496
6497 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6498
6499         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
6500         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
6501
6502 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
6503
6504         * config/aarch64/aarch64-tuning-flags.def
6505         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
6506         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
6507         * config/aarch64/aarch64.cc
6508         (aarch64_override_options_internal): Set
6509         param_fully_pipelined_fma according to tuning option.
6510         * config/aarch64/tuning_models/ampere1.h: Add
6511         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
6512         * config/aarch64/tuning_models/ampere1a.h: Likewise.
6513         * config/aarch64/tuning_models/ampere1b.h: Likewise.
6514
6515 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
6516
6517         * config/riscv/vector-crypto.md: Modify copyright year.
6518
6519 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6520
6521         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
6522
6523 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
6524
6525         * config.in: Regenerate.
6526         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
6527         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
6528         Added TLS Le Relax support.
6529         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
6530         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
6531         * configure: Regenerate.
6532         * configure.ac: Check if binutils supports TLS le relax.
6533
6534 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
6535
6536         * config/riscv/iterators.md: Add rotate insn name.
6537         * config/riscv/riscv.md: Add new insns name for crypto vector.
6538         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
6539         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
6540         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
6541
6542 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6543
6544         PR target/113112
6545         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
6546         pointer type liveness count.
6547 \f
6548 Copyright (C) 2024 Free Software Foundation, Inc.
6549
6550 Copying and distribution of this file, with or without modification,
6551 are permitted in any medium without royalty provided the copyright
6552 notice and this notice are preserved.