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PR testsuite/35843
[official-gcc.git] / gcc / config / arm / arm.h
blobb6e182c0d22e41bc76014b777b2bec26abca4c8a
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
16
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 #include "config/vxworks-dummy.h"
30
31 /* The architecture define. */
32 extern char arm_arch_name[];
33
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do \
37 { \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
42 if (TARGET_THUMB) \
43 builtin_define ("__thumb__"); \
44 if (TARGET_THUMB2) \
45 builtin_define ("__thumb2__"); \
46 \
47 if (TARGET_BIG_END) \
48 { \
49 builtin_define ("__ARMEB__"); \
50 if (TARGET_THUMB) \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
54 } \
55 else \
56 { \
57 builtin_define ("__ARMEL__"); \
58 if (TARGET_THUMB) \
59 builtin_define ("__THUMBEL__"); \
60 } \
61 \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
64 \
65 if (TARGET_VFP) \
66 builtin_define ("__VFP_FP__"); \
67 \
68 if (TARGET_NEON) \
69 builtin_define ("__ARM_NEON__"); \
70 \
71 /* Add a define for interworking. \
72 Needed when building libgcc.a. */ \
73 if (arm_cpp_interwork) \
74 builtin_define ("__THUMB_INTERWORK__"); \
75 \
76 builtin_assert ("cpu=arm"); \
77 builtin_assert ("machine=arm"); \
78 \
79 builtin_define (arm_arch_name); \
80 if (arm_arch_cirrus) \
81 builtin_define ("__MAVERICK__"); \
82 if (arm_arch_xscale) \
83 builtin_define ("__XSCALE__"); \
84 if (arm_arch_iwmmxt) \
85 builtin_define ("__IWMMXT__"); \
86 if (TARGET_AAPCS_BASED) \
87 builtin_define ("__ARM_EABI__"); \
88 } while (0)
89
90 /* The various ARM cores. */
91 enum processor_type
92 {
93 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
94 IDENT,
95 #include "arm-cores.def"
96 #undef ARM_CORE
97 /* Used to indicate that no processor has been specified. */
98 arm_none
99 };
100
101 enum target_cpus
102 {
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
104 TARGET_CPU_##IDENT,
105 #include "arm-cores.def"
106 #undef ARM_CORE
107 TARGET_CPU_generic
108 };
109
110 /* The processor for which instructions should be scheduled. */
111 extern enum processor_type arm_tune;
112
113 typedef enum arm_cond_code
114 {
115 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
116 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
117 }
118 arm_cc;
119
120 extern arm_cc arm_current_cc;
121
122 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
123
124 extern int arm_target_label;
125 extern int arm_ccfsm_state;
126 extern GTY(()) rtx arm_target_insn;
127 /* Define the information needed to generate branch insns. This is
128 stored from the compare operation. */
129 extern GTY(()) rtx arm_compare_op0;
130 extern GTY(()) rtx arm_compare_op1;
131 /* The label of the current constant pool. */
132 extern rtx pool_vector_label;
133 /* Set to 1 when a return insn is output, this means that the epilogue
134 is not needed. */
135 extern int return_used_this_function;
136 /* Callback to output language specific object attributes. */
137 extern void (*arm_lang_output_object_attributes_hook)(void);
138 \f
139 /* Just in case configure has failed to define anything. */
140 #ifndef TARGET_CPU_DEFAULT
141 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
142 #endif
143
144
145 #undef CPP_SPEC
146 #define CPP_SPEC "%(subtarget_cpp_spec) \
147 %{msoft-float:%{mhard-float: \
148 %e-msoft-float and -mhard_float may not be used together}} \
149 %{mbig-endian:%{mlittle-endian: \
150 %e-mbig-endian and -mlittle-endian may not be used together}}"
151
152 #ifndef CC1_SPEC
153 #define CC1_SPEC ""
154 #endif
155
156 /* This macro defines names of additional specifications to put in the specs
157 that can be used in various specifications like CC1_SPEC. Its definition
158 is an initializer with a subgrouping for each command option.
159
160 Each subgrouping contains a string constant, that defines the
161 specification name, and a string constant that used by the GCC driver
162 program.
163
164 Do not define this macro if it does not need to do anything. */
165 #define EXTRA_SPECS \
166 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
167 SUBTARGET_EXTRA_SPECS
168
169 #ifndef SUBTARGET_EXTRA_SPECS
170 #define SUBTARGET_EXTRA_SPECS
171 #endif
172
173 #ifndef SUBTARGET_CPP_SPEC
174 #define SUBTARGET_CPP_SPEC ""
175 #endif
176 \f
177 /* Run-time Target Specification. */
178 #ifndef TARGET_VERSION
179 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
180 #endif
181
182 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
183 /* Use hardware floating point instructions. */
184 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
185 /* Use hardware floating point calling convention. */
186 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
187 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
188 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
189 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
190 #define TARGET_IWMMXT (arm_arch_iwmmxt)
191 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
192 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
193 #define TARGET_ARM (! TARGET_THUMB)
194 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
195 #define TARGET_BACKTRACE (leaf_function_p () \
196 ? TARGET_TPCS_LEAF_FRAME \
197 : TARGET_TPCS_FRAME)
198 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
199 #define TARGET_AAPCS_BASED \
200 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
201
202 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
203 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
204
205 /* Only 16-bit thumb code. */
206 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
207 /* Arm or Thumb-2 32-bit code. */
208 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
209 /* 32-bit Thumb-2 code. */
210 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
211 /* Thumb-1 only. */
212 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
213
214 /* The following two macros concern the ability to execute coprocessor
215 instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever
216 tested when we know we are generating for VFP hardware; we need to
217 be more careful with TARGET_NEON as noted below. */
218
219 /* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to
220 Neon automatically enables VFPv3 too. */
221 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
222 && (arm_fpu_arch == FPUTYPE_VFP3 \
223 || arm_fpu_arch == FPUTYPE_NEON))
224 /* FPU supports Neon instructions. The setting of this macro gets
225 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
226 and TARGET_HARD_FLOAT to ensure that NEON instructions are
227 available. */
228 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
229 && arm_fp_model == ARM_FP_MODEL_VFP \
230 && arm_fpu_arch == FPUTYPE_NEON)
231
232 /* "DSP" multiply instructions, eg. SMULxy. */
233 #define TARGET_DSP_MULTIPLY \
234 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
235 /* Integer SIMD instructions, and extend-accumulate instructions. */
236 #define TARGET_INT_SIMD \
237 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
238
239 /* We could use unified syntax for arm mode, but for now we just use it
240 for Thumb-2. */
241 #define TARGET_UNIFIED_ASM TARGET_THUMB2
242
243
244 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
245 then TARGET_AAPCS_BASED must be true -- but the converse does not
246 hold. TARGET_BPABI implies the use of the BPABI runtime library,
247 etc., in addition to just the AAPCS calling conventions. */
248 #ifndef TARGET_BPABI
249 #define TARGET_BPABI false
250 #endif
251
252 /* Support for a compile-time default CPU, et cetera. The rules are:
253 --with-arch is ignored if -march or -mcpu are specified.
254 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
255 by --with-arch.
256 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
257 by -march).
258 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
259 specified.
260 --with-fpu is ignored if -mfpu is specified.
261 --with-abi is ignored is -mabi is specified. */
262 #define OPTION_DEFAULT_SPECS \
263 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
264 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
265 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
266 {"float", \
267 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
268 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
269 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
270 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
271
272 /* Which floating point model to use. */
273 enum arm_fp_model
274 {
275 ARM_FP_MODEL_UNKNOWN,
276 /* FPA model (Hardware or software). */
277 ARM_FP_MODEL_FPA,
278 /* Cirrus Maverick floating point model. */
279 ARM_FP_MODEL_MAVERICK,
280 /* VFP floating point model. */
281 ARM_FP_MODEL_VFP
282 };
283
284 extern enum arm_fp_model arm_fp_model;
285
286 /* Which floating point hardware is available. Also update
287 fp_model_for_fpu in arm.c when adding entries to this list. */
288 enum fputype
289 {
290 /* No FP hardware. */
291 FPUTYPE_NONE,
292 /* Full FPA support. */
293 FPUTYPE_FPA,
294 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
295 FPUTYPE_FPA_EMU2,
296 /* Emulated FPA hardware, Issue 3 emulator. */
297 FPUTYPE_FPA_EMU3,
298 /* Cirrus Maverick floating point co-processor. */
299 FPUTYPE_MAVERICK,
300 /* VFP. */
301 FPUTYPE_VFP,
302 /* VFPv3. */
303 FPUTYPE_VFP3,
304 /* Neon. */
305 FPUTYPE_NEON
306 };
307
308 /* Recast the floating point class to be the floating point attribute. */
309 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
310
311 /* What type of floating point to tune for */
312 extern enum fputype arm_fpu_tune;
313
314 /* What type of floating point instructions are available */
315 extern enum fputype arm_fpu_arch;
316
317 enum float_abi_type
318 {
319 ARM_FLOAT_ABI_SOFT,
320 ARM_FLOAT_ABI_SOFTFP,
321 ARM_FLOAT_ABI_HARD
322 };
323
324 extern enum float_abi_type arm_float_abi;
325
326 #ifndef TARGET_DEFAULT_FLOAT_ABI
327 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
328 #endif
329
330 /* Which ABI to use. */
331 enum arm_abi_type
332 {
333 ARM_ABI_APCS,
334 ARM_ABI_ATPCS,
335 ARM_ABI_AAPCS,
336 ARM_ABI_IWMMXT,
337 ARM_ABI_AAPCS_LINUX
338 };
339
340 extern enum arm_abi_type arm_abi;
341
342 #ifndef ARM_DEFAULT_ABI
343 #define ARM_DEFAULT_ABI ARM_ABI_APCS
344 #endif
345
346 /* Which thread pointer access sequence to use. */
347 enum arm_tp_type {
348 TP_AUTO,
349 TP_SOFT,
350 TP_CP15
351 };
352
353 extern enum arm_tp_type target_thread_pointer;
354
355 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
356 extern int arm_arch3m;
357
358 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
359 extern int arm_arch4;
360
361 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
362 extern int arm_arch4t;
363
364 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
365 extern int arm_arch5;
366
367 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
368 extern int arm_arch5e;
369
370 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
371 extern int arm_arch6;
372
373 /* Nonzero if instructions not present in the 'M' profile can be used. */
374 extern int arm_arch_notm;
375
376 /* Nonzero if this chip can benefit from load scheduling. */
377 extern int arm_ld_sched;
378
379 /* Nonzero if generating thumb code. */
380 extern int thumb_code;
381
382 /* Nonzero if this chip is a StrongARM. */
383 extern int arm_tune_strongarm;
384
385 /* Nonzero if this chip is a Cirrus variant. */
386 extern int arm_arch_cirrus;
387
388 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
389 extern int arm_arch_iwmmxt;
390
391 /* Nonzero if this chip is an XScale. */
392 extern int arm_arch_xscale;
393
394 /* Nonzero if tuning for XScale. */
395 extern int arm_tune_xscale;
396
397 /* Nonzero if tuning for stores via the write buffer. */
398 extern int arm_tune_wbuf;
399
400 /* Nonzero if we should define __THUMB_INTERWORK__ in the
401 preprocessor.
402 XXX This is a bit of a hack, it's intended to help work around
403 problems in GLD which doesn't understand that armv5t code is
404 interworking clean. */
405 extern int arm_cpp_interwork;
406
407 /* Nonzero if chip supports Thumb 2. */
408 extern int arm_arch_thumb2;
409
410 /* Nonzero if chip supports integer division instruction. */
411 extern int arm_arch_hwdiv;
412
413 #ifndef TARGET_DEFAULT
414 #define TARGET_DEFAULT (MASK_APCS_FRAME)
415 #endif
416
417 /* The frame pointer register used in gcc has nothing to do with debugging;
418 that is controlled by the APCS-FRAME option. */
419 #define CAN_DEBUG_WITHOUT_FP
420
421 #define OVERRIDE_OPTIONS arm_override_options ()
422
423 /* Nonzero if PIC code requires explicit qualifiers to generate
424 PLT and GOT relocs rather than the assembler doing so implicitly.
425 Subtargets can override these if required. */
426 #ifndef NEED_GOT_RELOC
427 #define NEED_GOT_RELOC 0
428 #endif
429 #ifndef NEED_PLT_RELOC
430 #define NEED_PLT_RELOC 0
431 #endif
432
433 /* Nonzero if we need to refer to the GOT with a PC-relative
434 offset. In other words, generate
435
436 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
437
438 rather than
439
440 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
441
442 The default is true, which matches NetBSD. Subtargets can
443 override this if required. */
444 #ifndef GOT_PCREL
445 #define GOT_PCREL 1
446 #endif
447 \f
448 /* Target machine storage Layout. */
449
450
451 /* Define this macro if it is advisable to hold scalars in registers
452 in a wider mode than that declared by the program. In such cases,
453 the value is constrained to be within the bounds of the declared
454 type, but kept valid in the wider mode. The signedness of the
455 extension may differ from that of the type. */
456
457 /* It is far faster to zero extend chars than to sign extend them */
458
459 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
460 if (GET_MODE_CLASS (MODE) == MODE_INT \
461 && GET_MODE_SIZE (MODE) < 4) \
462 { \
463 if (MODE == QImode) \
464 UNSIGNEDP = 1; \
465 else if (MODE == HImode) \
466 UNSIGNEDP = 1; \
467 (MODE) = SImode; \
468 }
469
470 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
471 if ((GET_MODE_CLASS (MODE) == MODE_INT \
472 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
473 && GET_MODE_SIZE (MODE) < 4) \
474 (MODE) = SImode; \
475
476 /* Define this if most significant bit is lowest numbered
477 in instructions that operate on numbered bit-fields. */
478 #define BITS_BIG_ENDIAN 0
479
480 /* Define this if most significant byte of a word is the lowest numbered.
481 Most ARM processors are run in little endian mode, so that is the default.
482 If you want to have it run-time selectable, change the definition in a
483 cover file to be TARGET_BIG_ENDIAN. */
484 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
485
486 /* Define this if most significant word of a multiword number is the lowest
487 numbered.
488 This is always false, even when in big-endian mode. */
489 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
490
491 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
492 on processor pre-defineds when compiling libgcc2.c. */
493 #if defined(__ARMEB__) && !defined(__ARMWEL__)
494 #define LIBGCC2_WORDS_BIG_ENDIAN 1
495 #else
496 #define LIBGCC2_WORDS_BIG_ENDIAN 0
497 #endif
498
499 /* Define this if most significant word of doubles is the lowest numbered.
500 The rules are different based on whether or not we use FPA-format,
501 VFP-format or some other floating point co-processor's format doubles. */
502 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
503
504 #define UNITS_PER_WORD 4
505
506 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
507 registers when autovectorizing for Neon, at least until multiple vector
508 widths are supported properly by the middle-end. */
509 #define UNITS_PER_SIMD_WORD \
510 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
511
512 /* True if natural alignment is used for doubleword types. */
513 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
514
515 #define DOUBLEWORD_ALIGNMENT 64
516
517 #define PARM_BOUNDARY 32
518
519 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
520
521 #define PREFERRED_STACK_BOUNDARY \
522 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
523
524 #define FUNCTION_BOUNDARY 32
525
526 /* The lowest bit is used to indicate Thumb-mode functions, so the
527 vbit must go into the delta field of pointers to member
528 functions. */
529 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
530
531 #define EMPTY_FIELD_BOUNDARY 32
532
533 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
534
535 /* XXX Blah -- this macro is used directly by libobjc. Since it
536 supports no vector modes, cut out the complexity and fall back
537 on BIGGEST_FIELD_ALIGNMENT. */
538 #ifdef IN_TARGET_LIBS
539 #define BIGGEST_FIELD_ALIGNMENT 64
540 #endif
541
542 /* Make strings word-aligned so strcpy from constants will be faster. */
543 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
544
545 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
546 ((TREE_CODE (EXP) == STRING_CST \
547 && !optimize_size \
548 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
549 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
550
551 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
552 value set in previous versions of this toolchain was 8, which produces more
553 compact structures. The command line option -mstructure_size_boundary=<n>
554 can be used to change this value. For compatibility with the ARM SDK
555 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
556 0020D) page 2-20 says "Structures are aligned on word boundaries".
557 The AAPCS specifies a value of 8. */
558 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
559 extern int arm_structure_size_boundary;
560
561 /* This is the value used to initialize arm_structure_size_boundary. If a
562 particular arm target wants to change the default value it should change
563 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
564 for an example of this. */
565 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
566 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
567 #endif
568
569 /* Nonzero if move instructions will actually fail to work
570 when given unaligned data. */
571 #define STRICT_ALIGNMENT 1
572
573 /* wchar_t is unsigned under the AAPCS. */
574 #ifndef WCHAR_TYPE
575 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
576
577 #define WCHAR_TYPE_SIZE BITS_PER_WORD
578 #endif
579
580 #ifndef SIZE_TYPE
581 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
582 #endif
583
584 #ifndef PTRDIFF_TYPE
585 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
586 #endif
587
588 /* AAPCS requires that structure alignment is affected by bitfields. */
589 #ifndef PCC_BITFIELD_TYPE_MATTERS
590 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
591 #endif
592
593 \f
594 /* Standard register usage. */
595
596 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
597 (S - saved over call).
598
599 r0 * argument word/integer result
600 r1-r3 argument word
601
602 r4-r8 S register variable
603 r9 S (rfp) register variable (real frame pointer)
604
605 r10 F S (sl) stack limit (used by -mapcs-stack-check)
606 r11 F S (fp) argument pointer
607 r12 (ip) temp workspace
608 r13 F S (sp) lower end of current stack frame
609 r14 (lr) link address/workspace
610 r15 F (pc) program counter
611
612 f0 floating point result
613 f1-f3 floating point scratch
614
615 f4-f7 S floating point variable
616
617 cc This is NOT a real register, but is used internally
618 to represent things that use or set the condition
619 codes.
620 sfp This isn't either. It is used during rtl generation
621 since the offset between the frame pointer and the
622 auto's isn't known until after register allocation.
623 afp Nor this, we only need this because of non-local
624 goto. Without it fp appears to be used and the
625 elimination code won't get rid of sfp. It tracks
626 fp exactly at all times.
627
628 *: See CONDITIONAL_REGISTER_USAGE */
629
630 /*
631 mvf0 Cirrus floating point result
632 mvf1-mvf3 Cirrus floating point scratch
633 mvf4-mvf15 S Cirrus floating point variable. */
634
635 /* s0-s15 VFP scratch (aka d0-d7).
636 s16-s31 S VFP variable (aka d8-d15).
637 vfpcc Not a real register. Represents the VFP condition
638 code flags. */
639
640 /* The stack backtrace structure is as follows:
641 fp points to here: | save code pointer | [fp]
642 | return link value | [fp, #-4]
643 | return sp value | [fp, #-8]
644 | return fp value | [fp, #-12]
645 [| saved r10 value |]
646 [| saved r9 value |]
647 [| saved r8 value |]
648 [| saved r7 value |]
649 [| saved r6 value |]
650 [| saved r5 value |]
651 [| saved r4 value |]
652 [| saved r3 value |]
653 [| saved r2 value |]
654 [| saved r1 value |]
655 [| saved r0 value |]
656 [| saved f7 value |] three words
657 [| saved f6 value |] three words
658 [| saved f5 value |] three words
659 [| saved f4 value |] three words
660 r0-r3 are not normally saved in a C function. */
661
662 /* 1 for registers that have pervasive standard uses
663 and are not available for the register allocator. */
664 #define FIXED_REGISTERS \
665 { \
666 0,0,0,0,0,0,0,0, \
667 0,0,0,0,0,1,0,1, \
668 0,0,0,0,0,0,0,0, \
669 1,1,1, \
670 1,1,1,1,1,1,1,1, \
671 1,1,1,1,1,1,1,1, \
672 1,1,1,1,1,1,1,1, \
673 1,1,1,1,1,1,1,1, \
674 1,1,1,1, \
675 1,1,1,1,1,1,1,1, \
676 1,1,1,1,1,1,1,1, \
677 1,1,1,1,1,1,1,1, \
678 1,1,1,1,1,1,1,1, \
679 1,1,1,1,1,1,1,1, \
680 1,1,1,1,1,1,1,1, \
681 1,1,1,1,1,1,1,1, \
682 1,1,1,1,1,1,1,1, \
683 1 \
684 }
685
686 /* 1 for registers not available across function calls.
687 These must include the FIXED_REGISTERS and also any
688 registers that can be used without being saved.
689 The latter must include the registers where values are returned
690 and the register where structure-value addresses are passed.
691 Aside from that, you can include as many other registers as you like.
692 The CC is not preserved over function calls on the ARM 6, so it is
693 easier to assume this for all. SFP is preserved, since FP is. */
694 #define CALL_USED_REGISTERS \
695 { \
696 1,1,1,1,0,0,0,0, \
697 0,0,0,0,1,1,1,1, \
698 1,1,1,1,0,0,0,0, \
699 1,1,1, \
700 1,1,1,1,1,1,1,1, \
701 1,1,1,1,1,1,1,1, \
702 1,1,1,1,1,1,1,1, \
703 1,1,1,1,1,1,1,1, \
704 1,1,1,1, \
705 1,1,1,1,1,1,1,1, \
706 1,1,1,1,1,1,1,1, \
707 1,1,1,1,1,1,1,1, \
708 1,1,1,1,1,1,1,1, \
709 1,1,1,1,1,1,1,1, \
710 1,1,1,1,1,1,1,1, \
711 1,1,1,1,1,1,1,1, \
712 1,1,1,1,1,1,1,1, \
713 1 \
714 }
715
716 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
717 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
718 #endif
719
720 #define CONDITIONAL_REGISTER_USAGE \
721 { \
722 int regno; \
723 \
724 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
725 { \
726 for (regno = FIRST_FPA_REGNUM; \
727 regno <= LAST_FPA_REGNUM; ++regno) \
728 fixed_regs[regno] = call_used_regs[regno] = 1; \
729 } \
730 \
731 if (TARGET_THUMB && optimize_size) \
732 { \
733 /* When optimizing for size, it's better not to use \
734 the HI regs, because of the overhead of stacking \
735 them. */ \
736 /* ??? Is this still true for thumb2? */ \
737 for (regno = FIRST_HI_REGNUM; \
738 regno <= LAST_HI_REGNUM; ++regno) \
739 fixed_regs[regno] = call_used_regs[regno] = 1; \
740 } \
741 \
742 /* The link register can be clobbered by any branch insn, \
743 but we have no way to track that at present, so mark \
744 it as unavailable. */ \
745 if (TARGET_THUMB1) \
746 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
747 \
748 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
749 { \
750 if (TARGET_MAVERICK) \
751 { \
752 for (regno = FIRST_FPA_REGNUM; \
753 regno <= LAST_FPA_REGNUM; ++ regno) \
754 fixed_regs[regno] = call_used_regs[regno] = 1; \
755 for (regno = FIRST_CIRRUS_FP_REGNUM; \
756 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
757 { \
758 fixed_regs[regno] = 0; \
759 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
760 } \
761 } \
762 if (TARGET_VFP) \
763 { \
764 /* VFPv3 registers are disabled when earlier VFP \
765 versions are selected due to the definition of \
766 LAST_VFP_REGNUM. */ \
767 for (regno = FIRST_VFP_REGNUM; \
768 regno <= LAST_VFP_REGNUM; ++ regno) \
769 { \
770 fixed_regs[regno] = 0; \
771 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
772 || regno >= FIRST_VFP_REGNUM + 32; \
773 } \
774 } \
775 } \
776 \
777 if (TARGET_REALLY_IWMMXT) \
778 { \
779 regno = FIRST_IWMMXT_GR_REGNUM; \
780 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
781 and wCG1 as call-preserved registers. The 2002/11/21 \
782 revision changed this so that all wCG registers are \
783 scratch registers. */ \
784 for (regno = FIRST_IWMMXT_GR_REGNUM; \
785 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
786 fixed_regs[regno] = 0; \
787 /* The XScale ABI has wR0 - wR9 as scratch registers, \
788 the rest as call-preserved registers. */ \
789 for (regno = FIRST_IWMMXT_REGNUM; \
790 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
791 { \
792 fixed_regs[regno] = 0; \
793 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
794 } \
795 } \
796 \
797 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
798 { \
799 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
800 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
801 } \
802 else if (TARGET_APCS_STACK) \
803 { \
804 fixed_regs[10] = 1; \
805 call_used_regs[10] = 1; \
806 } \
807 /* -mcaller-super-interworking reserves r11 for calls to \
808 _interwork_r11_call_via_rN(). Making the register global \
809 is an easy way of ensuring that it remains valid for all \
810 calls. */ \
811 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
812 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
813 { \
814 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
815 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
816 if (TARGET_CALLER_INTERWORKING) \
817 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
818 } \
819 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
820 }
821
822 /* These are a couple of extensions to the formats accepted
823 by asm_fprintf:
824 %@ prints out ASM_COMMENT_START
825 %r prints out REGISTER_PREFIX reg_names[arg] */
826 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
827 case '@': \
828 fputs (ASM_COMMENT_START, FILE); \
829 break; \
830 \
831 case 'r': \
832 fputs (REGISTER_PREFIX, FILE); \
833 fputs (reg_names [va_arg (ARGS, int)], FILE); \
834 break;
835
836 /* Round X up to the nearest word. */
837 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
838
839 /* Convert fron bytes to ints. */
840 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
841
842 /* The number of (integer) registers required to hold a quantity of type MODE.
843 Also used for VFP registers. */
844 #define ARM_NUM_REGS(MODE) \
845 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
846
847 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
848 #define ARM_NUM_REGS2(MODE, TYPE) \
849 ARM_NUM_INTS ((MODE) == BLKmode ? \
850 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
851
852 /* The number of (integer) argument register available. */
853 #define NUM_ARG_REGS 4
854
855 /* Return the register number of the N'th (integer) argument. */
856 #define ARG_REGISTER(N) (N - 1)
857
858 /* Specify the registers used for certain standard purposes.
859 The values of these macros are register numbers. */
860
861 /* The number of the last argument register. */
862 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
863
864 /* The numbers of the Thumb register ranges. */
865 #define FIRST_LO_REGNUM 0
866 #define LAST_LO_REGNUM 7
867 #define FIRST_HI_REGNUM 8
868 #define LAST_HI_REGNUM 11
869
870 #ifndef TARGET_UNWIND_INFO
871 /* We use sjlj exceptions for backwards compatibility. */
872 #define MUST_USE_SJLJ_EXCEPTIONS 1
873 #endif
874
875 /* We can generate DWARF2 Unwind info, even though we don't use it. */
876 #define DWARF2_UNWIND_INFO 1
877
878 /* Use r0 and r1 to pass exception handling information. */
879 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
880
881 /* The register that holds the return address in exception handlers. */
882 #define ARM_EH_STACKADJ_REGNUM 2
883 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
884
885 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
886 as an invisible last argument (possible since varargs don't exist in
887 Pascal), so the following is not true. */
888 #define STATIC_CHAIN_REGNUM 12
889
890 /* Define this to be where the real frame pointer is if it is not possible to
891 work out the offset between the frame pointer and the automatic variables
892 until after register allocation has taken place. FRAME_POINTER_REGNUM
893 should point to a special register that we will make sure is eliminated.
894
895 For the Thumb we have another problem. The TPCS defines the frame pointer
896 as r11, and GCC believes that it is always possible to use the frame pointer
897 as base register for addressing purposes. (See comments in
898 find_reloads_address()). But - the Thumb does not allow high registers,
899 including r11, to be used as base address registers. Hence our problem.
900
901 The solution used here, and in the old thumb port is to use r7 instead of
902 r11 as the hard frame pointer and to have special code to generate
903 backtrace structures on the stack (if required to do so via a command line
904 option) using r11. This is the only 'user visible' use of r11 as a frame
905 pointer. */
906 #define ARM_HARD_FRAME_POINTER_REGNUM 11
907 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
908
909 #define HARD_FRAME_POINTER_REGNUM \
910 (TARGET_ARM \
911 ? ARM_HARD_FRAME_POINTER_REGNUM \
912 : THUMB_HARD_FRAME_POINTER_REGNUM)
913
914 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
915
916 /* Register to use for pushing function arguments. */
917 #define STACK_POINTER_REGNUM SP_REGNUM
918
919 /* ARM floating pointer registers. */
920 #define FIRST_FPA_REGNUM 16
921 #define LAST_FPA_REGNUM 23
922 #define IS_FPA_REGNUM(REGNUM) \
923 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
924
925 #define FIRST_IWMMXT_GR_REGNUM 43
926 #define LAST_IWMMXT_GR_REGNUM 46
927 #define FIRST_IWMMXT_REGNUM 47
928 #define LAST_IWMMXT_REGNUM 62
929 #define IS_IWMMXT_REGNUM(REGNUM) \
930 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
931 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
932 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
933
934 /* Base register for access to local variables of the function. */
935 #define FRAME_POINTER_REGNUM 25
936
937 /* Base register for access to arguments of the function. */
938 #define ARG_POINTER_REGNUM 26
939
940 #define FIRST_CIRRUS_FP_REGNUM 27
941 #define LAST_CIRRUS_FP_REGNUM 42
942 #define IS_CIRRUS_REGNUM(REGNUM) \
943 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
944
945 #define FIRST_VFP_REGNUM 63
946 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
947 #define LAST_VFP_REGNUM \
948 (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
949
950 #define IS_VFP_REGNUM(REGNUM) \
951 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
952
953 /* VFP registers are split into two types: those defined by VFP versions < 3
954 have D registers overlaid on consecutive pairs of S registers. VFP version 3
955 defines 16 new D registers (d16-d31) which, for simplicity and correctness
956 in various parts of the backend, we implement as "fake" single-precision
957 registers (which would be S32-S63, but cannot be used in that way). The
958 following macros define these ranges of registers. */
959 #define LAST_LO_VFP_REGNUM 94
960 #define FIRST_HI_VFP_REGNUM 95
961 #define LAST_HI_VFP_REGNUM 126
962
963 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
964 ((REGNUM) <= LAST_LO_VFP_REGNUM)
965
966 /* DFmode values are only valid in even register pairs. */
967 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
968 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
969
970 /* Neon Quad values must start at a multiple of four registers. */
971 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
972 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
973
974 /* Neon structures of vectors must be in even register pairs and there
975 must be enough registers available. Because of various patterns
976 requiring quad registers, we require them to start at a multiple of
977 four. */
978 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
979 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
980 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
981
982 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
983 /* + 16 Cirrus registers take us up to 43. */
984 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
985 /* VFP (VFP3) adds 32 (64) + 1 more. */
986 #define FIRST_PSEUDO_REGISTER 128
987
988 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
989
990 /* Value should be nonzero if functions must have frame pointers.
991 Zero means the frame pointer need not be set up (and parms may be accessed
992 via the stack pointer) in functions that seem suitable.
993 If we have to have a frame pointer we might as well make use of it.
994 APCS says that the frame pointer does not need to be pushed in leaf
995 functions, or simple tail call functions. */
996
997 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
998 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
999 #endif
1000
1001 #define FRAME_POINTER_REQUIRED \
1002 (cfun->has_nonlocal_label \
1003 || SUBTARGET_FRAME_POINTER_REQUIRED \
1004 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1005
1006 /* Return number of consecutive hard regs needed starting at reg REGNO
1007 to hold something of mode MODE.
1008 This is ordinarily the length in words of a value of mode MODE
1009 but can be less for certain modes in special long registers.
1010
1011 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1012 mode. */
1013 #define HARD_REGNO_NREGS(REGNO, MODE) \
1014 ((TARGET_32BIT \
1015 && REGNO >= FIRST_FPA_REGNUM \
1016 && REGNO != FRAME_POINTER_REGNUM \
1017 && REGNO != ARG_POINTER_REGNUM) \
1018 && !IS_VFP_REGNUM (REGNO) \
1019 ? 1 : ARM_NUM_REGS (MODE))
1020
1021 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1022 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1023 arm_hard_regno_mode_ok ((REGNO), (MODE))
1024
1025 /* Value is 1 if it is a good idea to tie two pseudo registers
1026 when one has mode MODE1 and one has mode MODE2.
1027 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1028 for any hard reg, then this must be 0 for correct output. */
1029 #define MODES_TIEABLE_P(MODE1, MODE2) \
1030 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1031
1032 #define VALID_IWMMXT_REG_MODE(MODE) \
1033 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1034
1035 /* Modes valid for Neon D registers. */
1036 #define VALID_NEON_DREG_MODE(MODE) \
1037 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1038 || (MODE) == V2SFmode || (MODE) == DImode)
1039
1040 /* Modes valid for Neon Q registers. */
1041 #define VALID_NEON_QREG_MODE(MODE) \
1042 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1043 || (MODE) == V4SFmode || (MODE) == V2DImode)
1044
1045 /* Structure modes valid for Neon registers. */
1046 #define VALID_NEON_STRUCT_MODE(MODE) \
1047 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1048 || (MODE) == CImode || (MODE) == XImode)
1049
1050 /* The order in which register should be allocated. It is good to use ip
1051 since no saving is required (though calls clobber it) and it never contains
1052 function parameters. It is quite good to use lr since other calls may
1053 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1054 least likely to contain a function parameter; in addition results are
1055 returned in r0.
1056 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1057 then D8-D15. The reason for doing this is to attempt to reduce register
1058 pressure when both single- and double-precision registers are used in a
1059 function. */
1060
1061 #define REG_ALLOC_ORDER \
1062 { \
1063 3, 2, 1, 0, 12, 14, 4, 5, \
1064 6, 7, 8, 10, 9, 11, 13, 15, \
1065 16, 17, 18, 19, 20, 21, 22, 23, \
1066 27, 28, 29, 30, 31, 32, 33, 34, \
1067 35, 36, 37, 38, 39, 40, 41, 42, \
1068 43, 44, 45, 46, 47, 48, 49, 50, \
1069 51, 52, 53, 54, 55, 56, 57, 58, \
1070 59, 60, 61, 62, \
1071 24, 25, 26, \
1072 95, 96, 97, 98, 99, 100, 101, 102, \
1073 103, 104, 105, 106, 107, 108, 109, 110, \
1074 111, 112, 113, 114, 115, 116, 117, 118, \
1075 119, 120, 121, 122, 123, 124, 125, 126, \
1076 78, 77, 76, 75, 74, 73, 72, 71, \
1077 70, 69, 68, 67, 66, 65, 64, 63, \
1078 79, 80, 81, 82, 83, 84, 85, 86, \
1079 87, 88, 89, 90, 91, 92, 93, 94, \
1080 127 \
1081 }
1082
1083 /* Interrupt functions can only use registers that have already been
1084 saved by the prologue, even if they would normally be
1085 call-clobbered. */
1086 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1087 (! IS_INTERRUPT (cfun->machine->func_type) || \
1088 df_regs_ever_live_p (DST))
1089 \f
1090 /* Register and constant classes. */
1091
1092 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1093 Now that the Thumb is involved it has become more complicated. */
1094 enum reg_class
1095 {
1096 NO_REGS,
1097 FPA_REGS,
1098 CIRRUS_REGS,
1099 VFP_D0_D7_REGS,
1100 VFP_LO_REGS,
1101 VFP_HI_REGS,
1102 VFP_REGS,
1103 IWMMXT_GR_REGS,
1104 IWMMXT_REGS,
1105 LO_REGS,
1106 STACK_REG,
1107 BASE_REGS,
1108 HI_REGS,
1109 CC_REG,
1110 VFPCC_REG,
1111 GENERAL_REGS,
1112 CORE_REGS,
1113 ALL_REGS,
1114 LIM_REG_CLASSES
1115 };
1116
1117 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1118
1119 /* Give names of register classes as strings for dump file. */
1120 #define REG_CLASS_NAMES \
1121 { \
1122 "NO_REGS", \
1123 "FPA_REGS", \
1124 "CIRRUS_REGS", \
1125 "VFP_D0_D7_REGS", \
1126 "VFP_LO_REGS", \
1127 "VFP_HI_REGS", \
1128 "VFP_REGS", \
1129 "IWMMXT_GR_REGS", \
1130 "IWMMXT_REGS", \
1131 "LO_REGS", \
1132 "STACK_REG", \
1133 "BASE_REGS", \
1134 "HI_REGS", \
1135 "CC_REG", \
1136 "VFPCC_REG", \
1137 "GENERAL_REGS", \
1138 "CORE_REGS", \
1139 "ALL_REGS", \
1140 }
1141
1142 /* Define which registers fit in which classes.
1143 This is an initializer for a vector of HARD_REG_SET
1144 of length N_REG_CLASSES. */
1145 #define REG_CLASS_CONTENTS \
1146 { \
1147 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1148 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1149 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1150 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1151 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1152 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1153 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1154 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1155 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1156 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1157 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1158 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1159 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1160 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1162 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1163 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1164 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1165 }
1166
1167 /* Any of the VFP register classes. */
1168 #define IS_VFP_CLASS(X) \
1169 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1170 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1171
1172 /* The same information, inverted:
1173 Return the class number of the smallest class containing
1174 reg number REGNO. This could be a conditional expression
1175 or could index an array. */
1176 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1177
1178 /* FPA registers can't do subreg as all values are reformatted to internal
1179 precision. VFP registers may only be accessed in the mode they
1180 were set. */
1181 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1182 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1183 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1184 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1185 : 0)
1186
1187 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1188 using r0-r4 for function arguments, r7 for the stack frame and don't
1189 have enough left over to do doubleword arithmetic. */
1190 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1191 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1192 || (CLASS) == CC_REG)
1193
1194 /* The class value for index registers, and the one for base regs. */
1195 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1196 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1197
1198 /* For the Thumb the high registers cannot be used as base registers
1199 when addressing quantities in QI or HI mode; if we don't know the
1200 mode, then we must be conservative. */
1201 #define MODE_BASE_REG_CLASS(MODE) \
1202 (TARGET_32BIT ? CORE_REGS : \
1203 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1204
1205 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1206 instead of BASE_REGS. */
1207 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1208
1209 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1210 registers explicitly used in the rtl to be used as spill registers
1211 but prevents the compiler from extending the lifetime of these
1212 registers. */
1213 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1214
1215 /* Given an rtx X being reloaded into a reg required to be
1216 in class CLASS, return the class of reg to actually use.
1217 In general this is just CLASS, but for the Thumb core registers and
1218 immediate constants we prefer a LO_REGS class or a subset. */
1219 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1220 (TARGET_ARM ? (CLASS) : \
1221 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1222 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1223 ? LO_REGS : (CLASS)))
1224
1225 /* Must leave BASE_REGS reloads alone */
1226 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1227 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1228 ? ((true_regnum (X) == -1 ? LO_REGS \
1229 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1230 : NO_REGS)) \
1231 : NO_REGS)
1232
1233 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1234 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1235 ? ((true_regnum (X) == -1 ? LO_REGS \
1236 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1237 : NO_REGS)) \
1238 : NO_REGS)
1239
1240 /* Return the register class of a scratch register needed to copy IN into
1241 or out of a register in CLASS in MODE. If it can be done directly,
1242 NO_REGS is returned. */
1243 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1244 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1245 ((TARGET_VFP && TARGET_HARD_FLOAT \
1246 && IS_VFP_CLASS (CLASS)) \
1247 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1248 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1249 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1250 : TARGET_32BIT \
1251 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1252 ? GENERAL_REGS : NO_REGS) \
1253 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1254
1255 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1256 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1257 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1258 ((TARGET_VFP && TARGET_HARD_FLOAT \
1259 && IS_VFP_CLASS (CLASS)) \
1260 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1261 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1262 coproc_secondary_reload_class (MODE, X, TRUE) : \
1263 /* Cannot load constants into Cirrus registers. */ \
1264 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1265 && (CLASS) == CIRRUS_REGS \
1266 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1267 ? GENERAL_REGS : \
1268 (TARGET_32BIT ? \
1269 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1270 && CONSTANT_P (X)) \
1271 ? GENERAL_REGS : \
1272 (((MODE) == HImode && ! arm_arch4 \
1273 && (GET_CODE (X) == MEM \
1274 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1275 && true_regnum (X) == -1))) \
1276 ? GENERAL_REGS : NO_REGS) \
1277 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1278
1279 /* Try a machine-dependent way of reloading an illegitimate address
1280 operand. If we find one, push the reload and jump to WIN. This
1281 macro is used in only one place: `find_reloads_address' in reload.c.
1282
1283 For the ARM, we wish to handle large displacements off a base
1284 register by splitting the addend across a MOV and the mem insn.
1285 This can cut the number of reloads needed. */
1286 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1287 do \
1288 { \
1289 if (GET_CODE (X) == PLUS \
1290 && GET_CODE (XEXP (X, 0)) == REG \
1291 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1292 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1293 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1294 { \
1295 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1296 HOST_WIDE_INT low, high; \
1297 \
1298 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1299 low = ((val & 0xf) ^ 0x8) - 0x8; \
1300 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1301 /* Need to be careful, -256 is not a valid offset. */ \
1302 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1303 else if (MODE == SImode \
1304 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1305 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1306 /* Need to be careful, -4096 is not a valid offset. */ \
1307 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1308 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1309 /* Need to be careful, -256 is not a valid offset. */ \
1310 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1311 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1312 && TARGET_HARD_FLOAT && TARGET_FPA) \
1313 /* Need to be careful, -1024 is not a valid offset. */ \
1314 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1315 else \
1316 break; \
1317 \
1318 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1319 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1320 - (unsigned HOST_WIDE_INT) 0x80000000); \
1321 /* Check for overflow or zero */ \
1322 if (low == 0 || high == 0 || (high + low != val)) \
1323 break; \
1324 \
1325 /* Reload the high part into a base reg; leave the low part \
1326 in the mem. */ \
1327 X = gen_rtx_PLUS (GET_MODE (X), \
1328 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1329 GEN_INT (high)), \
1330 GEN_INT (low)); \
1331 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1332 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1333 VOIDmode, 0, 0, OPNUM, TYPE); \
1334 goto WIN; \
1335 } \
1336 } \
1337 while (0)
1338
1339 /* XXX If an HImode FP+large_offset address is converted to an HImode
1340 SP+large_offset address, then reload won't know how to fix it. It sees
1341 only that SP isn't valid for HImode, and so reloads the SP into an index
1342 register, but the resulting address is still invalid because the offset
1343 is too big. We fix it here instead by reloading the entire address. */
1344 /* We could probably achieve better results by defining PROMOTE_MODE to help
1345 cope with the variances between the Thumb's signed and unsigned byte and
1346 halfword load instructions. */
1347 /* ??? This should be safe for thumb2, but we may be able to do better. */
1348 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1349 do { \
1350 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1351 if (new_x) \
1352 { \
1353 X = new_x; \
1354 goto WIN; \
1355 } \
1356 } while (0)
1357
1358 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1359 if (TARGET_ARM) \
1360 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1361 else \
1362 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1363
1364 /* Return the maximum number of consecutive registers
1365 needed to represent mode MODE in a register of class CLASS.
1366 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1367 #define CLASS_MAX_NREGS(CLASS, MODE) \
1368 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1369
1370 /* If defined, gives a class of registers that cannot be used as the
1371 operand of a SUBREG that changes the mode of the object illegally. */
1372
1373 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1374 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1375 (TARGET_32BIT ? \
1376 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1377 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1378 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1379 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1380 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1381 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1382 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1383 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1384 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1385 2) \
1386 : \
1387 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1388 \f
1389 /* Stack layout; function entry, exit and calling. */
1390
1391 /* Define this if pushing a word on the stack
1392 makes the stack pointer a smaller address. */
1393 #define STACK_GROWS_DOWNWARD 1
1394
1395 /* Define this to nonzero if the nominal address of the stack frame
1396 is at the high-address end of the local variables;
1397 that is, each additional local variable allocated
1398 goes at a more negative offset in the frame. */
1399 #define FRAME_GROWS_DOWNWARD 1
1400
1401 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1402 When present, it is one word in size, and sits at the top of the frame,
1403 between the soft frame pointer and either r7 or r11.
1404
1405 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1406 and only then if some outgoing arguments are passed on the stack. It would
1407 be tempting to also check whether the stack arguments are passed by indirect
1408 calls, but there seems to be no reason in principle why a post-reload pass
1409 couldn't convert a direct call into an indirect one. */
1410 #define CALLER_INTERWORKING_SLOT_SIZE \
1411 (TARGET_CALLER_INTERWORKING \
1412 && crtl->outgoing_args_size != 0 \
1413 ? UNITS_PER_WORD : 0)
1414
1415 /* Offset within stack frame to start allocating local variables at.
1416 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1417 first local allocated. Otherwise, it is the offset to the BEGINNING
1418 of the first local allocated. */
1419 #define STARTING_FRAME_OFFSET 0
1420
1421 /* If we generate an insn to push BYTES bytes,
1422 this says how many the stack pointer really advances by. */
1423 /* The push insns do not do this rounding implicitly.
1424 So don't define this. */
1425 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1426
1427 /* Define this if the maximum size of all the outgoing args is to be
1428 accumulated and pushed during the prologue. The amount can be
1429 found in the variable crtl->outgoing_args_size. */
1430 #define ACCUMULATE_OUTGOING_ARGS 1
1431
1432 /* Offset of first parameter from the argument pointer register value. */
1433 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1434
1435 /* Value is the number of byte of arguments automatically
1436 popped when returning from a subroutine call.
1437 FUNDECL is the declaration node of the function (as a tree),
1438 FUNTYPE is the data type of the function (as a tree),
1439 or for a library call it is an identifier node for the subroutine name.
1440 SIZE is the number of bytes of arguments passed on the stack.
1441
1442 On the ARM, the caller does not pop any of its arguments that were passed
1443 on the stack. */
1444 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1445
1446 /* Define how to find the value returned by a library function
1447 assuming the value has mode MODE. */
1448 #define LIBCALL_VALUE(MODE) \
1449 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1450 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1451 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1452 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1453 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1454 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1455 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1456 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1457 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1458
1459 /* Define how to find the value returned by a function.
1460 VALTYPE is the data type of the value (as a tree).
1461 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1462 otherwise, FUNC is 0. */
1463 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1464 arm_function_value (VALTYPE, FUNC);
1465
1466 /* 1 if N is a possible register number for a function value.
1467 On the ARM, only r0 and f0 can return results. */
1468 /* On a Cirrus chip, mvf0 can return results. */
1469 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1470 ((REGNO) == ARG_REGISTER (1) \
1471 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1472 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1473 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1474 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1475 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1476
1477 /* Amount of memory needed for an untyped call to save all possible return
1478 registers. */
1479 #define APPLY_RESULT_SIZE arm_apply_result_size()
1480
1481 /* How large values are returned */
1482 /* A C expression which can inhibit the returning of certain function values
1483 in registers, based on the type of value. */
1484 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1485
1486 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1487 values must be in memory. On the ARM, they need only do so if larger
1488 than a word, or if they contain elements offset from zero in the struct. */
1489 #define DEFAULT_PCC_STRUCT_RETURN 0
1490
1491 /* These bits describe the different types of function supported
1492 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1493 normal function and an interworked function, for example. Knowing the
1494 type of a function is important for determining its prologue and
1495 epilogue sequences.
1496 Note value 7 is currently unassigned. Also note that the interrupt
1497 function types all have bit 2 set, so that they can be tested for easily.
1498 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1499 machine_function structure is initialized (to zero) func_type will
1500 default to unknown. This will force the first use of arm_current_func_type
1501 to call arm_compute_func_type. */
1502 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1503 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1504 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1505 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1506 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1507 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1508
1509 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1510
1511 /* In addition functions can have several type modifiers,
1512 outlined by these bit masks: */
1513 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1514 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1515 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1516 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1517 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1518
1519 /* Some macros to test these flags. */
1520 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1521 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1522 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1523 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1524 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1525 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1526
1527
1528 /* Structure used to hold the function stack frame layout. Offsets are
1529 relative to the stack pointer on function entry. Positive offsets are
1530 in the direction of stack growth.
1531 Only soft_frame is used in thumb mode. */
1532
1533 typedef struct arm_stack_offsets GTY(())
1534 {
1535 int saved_args; /* ARG_POINTER_REGNUM. */
1536 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1537 int saved_regs;
1538 int soft_frame; /* FRAME_POINTER_REGNUM. */
1539 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1540 int outgoing_args; /* STACK_POINTER_REGNUM. */
1541 unsigned int saved_regs_mask;
1542 }
1543 arm_stack_offsets;
1544
1545 /* A C structure for machine-specific, per-function data.
1546 This is added to the cfun structure. */
1547 typedef struct machine_function GTY(())
1548 {
1549 /* Additional stack adjustment in __builtin_eh_throw. */
1550 rtx eh_epilogue_sp_ofs;
1551 /* Records if LR has to be saved for far jumps. */
1552 int far_jump_used;
1553 /* Records if ARG_POINTER was ever live. */
1554 int arg_pointer_live;
1555 /* Records if the save of LR has been eliminated. */
1556 int lr_save_eliminated;
1557 /* The size of the stack frame. Only valid after reload. */
1558 arm_stack_offsets stack_offsets;
1559 /* Records the type of the current function. */
1560 unsigned long func_type;
1561 /* Record if the function has a variable argument list. */
1562 int uses_anonymous_args;
1563 /* Records if sibcalls are blocked because an argument
1564 register is needed to preserve stack alignment. */
1565 int sibcall_blocked;
1566 /* The PIC register for this function. This might be a pseudo. */
1567 rtx pic_reg;
1568 /* Labels for per-function Thumb call-via stubs. One per potential calling
1569 register. We can never call via LR or PC. We can call via SP if a
1570 trampoline happens to be on the top of the stack. */
1571 rtx call_via[14];
1572 }
1573 machine_function;
1574
1575 /* As in the machine_function, a global set of call-via labels, for code
1576 that is in text_section. */
1577 extern GTY(()) rtx thumb_call_via_label[14];
1578
1579 /* A C type for declaring a variable that is used as the first argument of
1580 `FUNCTION_ARG' and other related values. For some target machines, the
1581 type `int' suffices and can hold the number of bytes of argument so far. */
1582 typedef struct
1583 {
1584 /* This is the number of registers of arguments scanned so far. */
1585 int nregs;
1586 /* This is the number of iWMMXt register arguments scanned so far. */
1587 int iwmmxt_nregs;
1588 int named_count;
1589 int nargs;
1590 int can_split;
1591 } CUMULATIVE_ARGS;
1592
1593 /* Define where to put the arguments to a function.
1594 Value is zero to push the argument on the stack,
1595 or a hard register in which to store the argument.
1596
1597 MODE is the argument's machine mode.
1598 TYPE is the data type of the argument (as a tree).
1599 This is null for libcalls where that information may
1600 not be available.
1601 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1602 the preceding args and about the function being called.
1603 NAMED is nonzero if this argument is a named parameter
1604 (otherwise it is an extra parameter matching an ellipsis).
1605
1606 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1607 other arguments are passed on the stack. If (NAMED == 0) (which happens
1608 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1609 defined), say it is passed in the stack (function_prologue will
1610 indeed make it pass in the stack if necessary). */
1611 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1612 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1613
1614 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1615 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1616
1617 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1618 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1619
1620 /* For AAPCS, padding should never be below the argument. For other ABIs,
1621 * mimic the default. */
1622 #define PAD_VARARGS_DOWN \
1623 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1624
1625 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1626 for a call to a function whose data type is FNTYPE.
1627 For a library call, FNTYPE is 0.
1628 On the ARM, the offset starts at 0. */
1629 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1630 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1631
1632 /* Update the data in CUM to advance over an argument
1633 of mode MODE and data type TYPE.
1634 (TYPE is null for libcalls where that information may not be available.) */
1635 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1636 (CUM).nargs += 1; \
1637 if (arm_vector_mode_supported_p (MODE) \
1638 && (CUM).named_count > (CUM).nargs \
1639 && TARGET_IWMMXT_ABI) \
1640 (CUM).iwmmxt_nregs += 1; \
1641 else \
1642 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1643
1644 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1645 argument with the specified mode and type. If it is not defined,
1646 `PARM_BOUNDARY' is used for all arguments. */
1647 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1648 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1649 ? DOUBLEWORD_ALIGNMENT \
1650 : PARM_BOUNDARY )
1651
1652 /* 1 if N is a possible register number for function argument passing.
1653 On the ARM, r0-r3 are used to pass args. */
1654 #define FUNCTION_ARG_REGNO_P(REGNO) \
1655 (IN_RANGE ((REGNO), 0, 3) \
1656 || (TARGET_IWMMXT_ABI \
1657 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1658
1659 \f
1660 /* If your target environment doesn't prefix user functions with an
1661 underscore, you may wish to re-define this to prevent any conflicts. */
1662 #ifndef ARM_MCOUNT_NAME
1663 #define ARM_MCOUNT_NAME "*mcount"
1664 #endif
1665
1666 /* Call the function profiler with a given profile label. The Acorn
1667 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1668 On the ARM the full profile code will look like:
1669 .data
1670 LP1
1671 .word 0
1672 .text
1673 mov ip, lr
1674 bl mcount
1675 .word LP1
1676
1677 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1678 will output the .text section.
1679
1680 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1681 ``prof'' doesn't seem to mind about this!
1682
1683 Note - this version of the code is designed to work in both ARM and
1684 Thumb modes. */
1685 #ifndef ARM_FUNCTION_PROFILER
1686 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1687 { \
1688 char temp[20]; \
1689 rtx sym; \
1690 \
1691 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1692 IP_REGNUM, LR_REGNUM); \
1693 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1694 fputc ('\n', STREAM); \
1695 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1696 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1697 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1698 }
1699 #endif
1700
1701 #ifdef THUMB_FUNCTION_PROFILER
1702 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1703 if (TARGET_ARM) \
1704 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1705 else \
1706 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1707 #else
1708 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1709 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1710 #endif
1711
1712 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1713 the stack pointer does not matter. The value is tested only in
1714 functions that have frame pointers.
1715 No definition is equivalent to always zero.
1716
1717 On the ARM, the function epilogue recovers the stack pointer from the
1718 frame. */
1719 #define EXIT_IGNORE_STACK 1
1720
1721 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1722
1723 /* Determine if the epilogue should be output as RTL.
1724 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1725 /* This is disabled for Thumb-2 because it will confuse the
1726 conditional insn counter. */
1727 #define USE_RETURN_INSN(ISCOND) \
1728 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1729
1730 /* Definitions for register eliminations.
1731
1732 This is an array of structures. Each structure initializes one pair
1733 of eliminable registers. The "from" register number is given first,
1734 followed by "to". Eliminations of the same "from" register are listed
1735 in order of preference.
1736
1737 We have two registers that can be eliminated on the ARM. First, the
1738 arg pointer register can often be eliminated in favor of the stack
1739 pointer register. Secondly, the pseudo frame pointer register can always
1740 be eliminated; it is replaced with either the stack or the real frame
1741 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1742 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1743
1744 #define ELIMINABLE_REGS \
1745 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1746 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1747 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1748 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1749 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1750 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1751 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1752
1753 /* Given FROM and TO register numbers, say whether this elimination is
1754 allowed. Frame pointer elimination is automatically handled.
1755
1756 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1757 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1758 pointer, we must eliminate FRAME_POINTER_REGNUM into
1759 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1760 ARG_POINTER_REGNUM. */
1761 #define CAN_ELIMINATE(FROM, TO) \
1762 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1763 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1764 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1765 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1766 1)
1767
1768 /* Define the offset between two registers, one to be eliminated, and the
1769 other its replacement, at the start of a routine. */
1770 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1771 if (TARGET_ARM) \
1772 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1773 else \
1774 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1775
1776 /* Special case handling of the location of arguments passed on the stack. */
1777 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1778
1779 /* Initialize data used by insn expanders. This is called from insn_emit,
1780 once for every function before code is generated. */
1781 #define INIT_EXPANDERS arm_init_expanders ()
1782
1783 /* Output assembler code for a block containing the constant parts
1784 of a trampoline, leaving space for the variable parts.
1785
1786 On the ARM, (if r8 is the static chain regnum, and remembering that
1787 referencing pc adds an offset of 8) the trampoline looks like:
1788 ldr r8, [pc, #0]
1789 ldr pc, [pc]
1790 .word static chain value
1791 .word function's address
1792 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1793 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1794 { \
1795 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1796 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1797 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1798 PC_REGNUM, PC_REGNUM); \
1799 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1800 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1801 }
1802
1803 /* The Thumb-2 trampoline is similar to the arm implementation.
1804 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1805 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1806 { \
1807 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1808 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1809 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1810 PC_REGNUM, PC_REGNUM); \
1811 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1812 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1813 }
1814
1815 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1816 { \
1817 ASM_OUTPUT_ALIGN(FILE, 2); \
1818 fprintf (FILE, "\t.code\t16\n"); \
1819 fprintf (FILE, ".Ltrampoline_start:\n"); \
1820 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1821 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1822 PC_REGNUM); \
1823 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1824 STATIC_CHAIN_REGNUM); \
1825 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1826 PC_REGNUM); \
1827 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1828 SP_REGNUM); \
1829 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1830 PC_REGNUM); \
1831 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1832 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1833 }
1834
1835 #define TRAMPOLINE_TEMPLATE(FILE) \
1836 if (TARGET_ARM) \
1837 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1838 else if (TARGET_THUMB2) \
1839 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1840 else \
1841 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1842
1843 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1844 of the address. */
1845 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1846 { \
1847 if (TARGET_THUMB) \
1848 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1849 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1850 } while(0)
1851
1852 /* Length in units of the trampoline for entering a nested function. */
1853 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1854
1855 /* Alignment required for a trampoline in bits. */
1856 #define TRAMPOLINE_ALIGNMENT 32
1857
1858
1859 /* Emit RTL insns to initialize the variable parts of a trampoline.
1860 FNADDR is an RTX for the address of the function's pure code.
1861 CXT is an RTX for the static chain value for the function. */
1862 #ifndef INITIALIZE_TRAMPOLINE
1863 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1864 { \
1865 emit_move_insn (gen_rtx_MEM (SImode, \
1866 plus_constant (TRAMP, \
1867 TARGET_32BIT ? 8 : 12)), \
1868 CXT); \
1869 emit_move_insn (gen_rtx_MEM (SImode, \
1870 plus_constant (TRAMP, \
1871 TARGET_32BIT ? 12 : 16)), \
1872 FNADDR); \
1873 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1874 0, VOIDmode, 2, TRAMP, Pmode, \
1875 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1876 }
1877 #endif
1878
1879 \f
1880 /* Addressing modes, and classification of registers for them. */
1881 #define HAVE_POST_INCREMENT 1
1882 #define HAVE_PRE_INCREMENT TARGET_32BIT
1883 #define HAVE_POST_DECREMENT TARGET_32BIT
1884 #define HAVE_PRE_DECREMENT TARGET_32BIT
1885 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1886 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1887 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1888 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1889
1890 /* Macros to check register numbers against specific register classes. */
1891
1892 /* These assume that REGNO is a hard or pseudo reg number.
1893 They give nonzero only if REGNO is a hard reg of the suitable class
1894 or a pseudo reg currently allocated to a suitable hard reg.
1895 Since they use reg_renumber, they are safe only once reg_renumber
1896 has been allocated, which happens in local-alloc.c. */
1897 #define TEST_REGNO(R, TEST, VALUE) \
1898 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1899
1900 /* Don't allow the pc to be used. */
1901 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1902 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1903 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1904 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1905
1906 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1907 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1908 || (GET_MODE_SIZE (MODE) >= 4 \
1909 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1910
1911 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1912 (TARGET_THUMB1 \
1913 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1914 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1915
1916 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1917 For Thumb, we can not use SP + reg, so reject SP. */
1918 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1919 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1920
1921 /* For ARM code, we don't care about the mode, but for Thumb, the index
1922 must be suitable for use in a QImode load. */
1923 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1924 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1925 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1926
1927 /* Maximum number of registers that can appear in a valid memory address.
1928 Shifts in addresses can't be by a register. */
1929 #define MAX_REGS_PER_ADDRESS 2
1930
1931 /* Recognize any constant value that is a valid address. */
1932 /* XXX We can address any constant, eventually... */
1933 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1934 #define CONSTANT_ADDRESS_P(X) \
1935 (GET_CODE (X) == SYMBOL_REF \
1936 && (CONSTANT_POOL_ADDRESS_P (X) \
1937 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1938
1939 /* True if SYMBOL + OFFSET constants must refer to something within
1940 SYMBOL's section. */
1941 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1942
1943 /* Nonzero if the constant value X is a legitimate general operand.
1944 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1945
1946 On the ARM, allow any integer (invalid ones are removed later by insn
1947 patterns), nice doubles and symbol_refs which refer to the function's
1948 constant pool XXX.
1949
1950 When generating pic allow anything. */
1951 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1952
1953 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1954 ( GET_CODE (X) == CONST_INT \
1955 || GET_CODE (X) == CONST_DOUBLE \
1956 || CONSTANT_ADDRESS_P (X) \
1957 || flag_pic)
1958
1959 #define LEGITIMATE_CONSTANT_P(X) \
1960 (!arm_cannot_force_const_mem (X) \
1961 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1962 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1963
1964 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1965 #define SUBTARGET_NAME_ENCODING_LENGTHS
1966 #endif
1967
1968 /* This is a C fragment for the inside of a switch statement.
1969 Each case label should return the number of characters to
1970 be stripped from the start of a function's name, if that
1971 name starts with the indicated character. */
1972 #define ARM_NAME_ENCODING_LENGTHS \
1973 case '*': return 1; \
1974 SUBTARGET_NAME_ENCODING_LENGTHS
1975
1976 /* This is how to output a reference to a user-level label named NAME.
1977 `assemble_name' uses this. */
1978 #undef ASM_OUTPUT_LABELREF
1979 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1980 arm_asm_output_labelref (FILE, NAME)
1981
1982 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1983 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1984 if (TARGET_THUMB2) \
1985 thumb2_asm_output_opcode (STREAM);
1986
1987 /* The EABI specifies that constructors should go in .init_array.
1988 Other targets use .ctors for compatibility. */
1989 #ifndef ARM_EABI_CTORS_SECTION_OP
1990 #define ARM_EABI_CTORS_SECTION_OP \
1991 "\t.section\t.init_array,\"aw\",%init_array"
1992 #endif
1993 #ifndef ARM_EABI_DTORS_SECTION_OP
1994 #define ARM_EABI_DTORS_SECTION_OP \
1995 "\t.section\t.fini_array,\"aw\",%fini_array"
1996 #endif
1997 #define ARM_CTORS_SECTION_OP \
1998 "\t.section\t.ctors,\"aw\",%progbits"
1999 #define ARM_DTORS_SECTION_OP \
2000 "\t.section\t.dtors,\"aw\",%progbits"
2001
2002 /* Define CTORS_SECTION_ASM_OP. */
2003 #undef CTORS_SECTION_ASM_OP
2004 #undef DTORS_SECTION_ASM_OP
2005 #ifndef IN_LIBGCC2
2006 # define CTORS_SECTION_ASM_OP \
2007 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2008 # define DTORS_SECTION_ASM_OP \
2009 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2010 #else /* !defined (IN_LIBGCC2) */
2011 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2012 so we cannot use the definition above. */
2013 # ifdef __ARM_EABI__
2014 /* The .ctors section is not part of the EABI, so we do not define
2015 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2016 from trying to use it. We do define it when doing normal
2017 compilation, as .init_array can be used instead of .ctors. */
2018 /* There is no need to emit begin or end markers when using
2019 init_array; the dynamic linker will compute the size of the
2020 array itself based on special symbols created by the static
2021 linker. However, we do need to arrange to set up
2022 exception-handling here. */
2023 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2024 # define CTOR_LIST_END /* empty */
2025 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2026 # define DTOR_LIST_END /* empty */
2027 # else /* !defined (__ARM_EABI__) */
2028 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2029 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2030 # endif /* !defined (__ARM_EABI__) */
2031 #endif /* !defined (IN_LIBCC2) */
2032
2033 /* True if the operating system can merge entities with vague linkage
2034 (e.g., symbols in COMDAT group) during dynamic linking. */
2035 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2036 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2037 #endif
2038
2039 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2040
2041 #ifdef TARGET_UNWIND_INFO
2042 #define ARM_EABI_UNWIND_TABLES \
2043 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2044 #else
2045 #define ARM_EABI_UNWIND_TABLES 0
2046 #endif
2047
2048 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2049 and check its validity for a certain class.
2050 We have two alternate definitions for each of them.
2051 The usual definition accepts all pseudo regs; the other rejects
2052 them unless they have been allocated suitable hard regs.
2053 The symbol REG_OK_STRICT causes the latter definition to be used.
2054 Thumb-2 has the same restrictions as arm. */
2055 #ifndef REG_OK_STRICT
2056
2057 #define ARM_REG_OK_FOR_BASE_P(X) \
2058 (REGNO (X) <= LAST_ARM_REGNUM \
2059 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2060 || REGNO (X) == FRAME_POINTER_REGNUM \
2061 || REGNO (X) == ARG_POINTER_REGNUM)
2062
2063 #define ARM_REG_OK_FOR_INDEX_P(X) \
2064 ((REGNO (X) <= LAST_ARM_REGNUM \
2065 && REGNO (X) != STACK_POINTER_REGNUM) \
2066 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2067 || REGNO (X) == FRAME_POINTER_REGNUM \
2068 || REGNO (X) == ARG_POINTER_REGNUM)
2069
2070 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2071 (REGNO (X) <= LAST_LO_REGNUM \
2072 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2073 || (GET_MODE_SIZE (MODE) >= 4 \
2074 && (REGNO (X) == STACK_POINTER_REGNUM \
2075 || (X) == hard_frame_pointer_rtx \
2076 || (X) == arg_pointer_rtx)))
2077
2078 #define REG_STRICT_P 0
2079
2080 #else /* REG_OK_STRICT */
2081
2082 #define ARM_REG_OK_FOR_BASE_P(X) \
2083 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2084
2085 #define ARM_REG_OK_FOR_INDEX_P(X) \
2086 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2087
2088 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2089 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2090
2091 #define REG_STRICT_P 1
2092
2093 #endif /* REG_OK_STRICT */
2094
2095 /* Now define some helpers in terms of the above. */
2096
2097 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2098 (TARGET_THUMB1 \
2099 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2100 : ARM_REG_OK_FOR_BASE_P (X))
2101
2102 /* For 16-bit Thumb, a valid index register is anything that can be used in
2103 a byte load instruction. */
2104 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2105 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2106
2107 /* Nonzero if X is a hard reg that can be used as an index
2108 or if it is a pseudo reg. On the Thumb, the stack pointer
2109 is not suitable. */
2110 #define REG_OK_FOR_INDEX_P(X) \
2111 (TARGET_THUMB1 \
2112 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2113 : ARM_REG_OK_FOR_INDEX_P (X))
2114
2115 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2116 For Thumb, we can not use SP + reg, so reject SP. */
2117 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2118 REG_OK_FOR_INDEX_P (X)
2119 \f
2120 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2121 that is a valid memory address for an instruction.
2122 The MODE argument is the machine mode for the MEM expression
2123 that wants to use this address. */
2124
2125 #define ARM_BASE_REGISTER_RTX_P(X) \
2126 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2127
2128 #define ARM_INDEX_REGISTER_RTX_P(X) \
2129 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2130
2131 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2132 { \
2133 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2134 goto WIN; \
2135 }
2136
2137 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2138 { \
2139 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2140 goto WIN; \
2141 }
2142
2143 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2144 { \
2145 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2146 goto WIN; \
2147 }
2148
2149 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2150 if (TARGET_ARM) \
2151 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2152 else if (TARGET_THUMB2) \
2153 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2154 else /* if (TARGET_THUMB1) */ \
2155 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2156
2157 \f
2158 /* Try machine-dependent ways of modifying an illegitimate address
2159 to be legitimate. If we find one, return the new, valid address. */
2160 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2161 do { \
2162 X = arm_legitimize_address (X, OLDX, MODE); \
2163 } while (0)
2164
2165 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2166 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2167 do { \
2168 } while (0)
2169
2170 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2171 do { \
2172 X = thumb_legitimize_address (X, OLDX, MODE); \
2173 } while (0)
2174
2175 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2176 do { \
2177 if (TARGET_ARM) \
2178 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2179 else if (TARGET_THUMB2) \
2180 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2181 else \
2182 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2183 \
2184 if (memory_address_p (MODE, X)) \
2185 goto WIN; \
2186 } while (0)
2187
2188 /* Go to LABEL if ADDR (a legitimate address expression)
2189 has an effect that depends on the machine mode it is used for. */
2190 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2191 { \
2192 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2193 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2194 goto LABEL; \
2195 }
2196
2197 /* Nothing helpful to do for the Thumb */
2198 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2199 if (TARGET_32BIT) \
2200 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2201 \f
2202
2203 /* Specify the machine mode that this machine uses
2204 for the index in the tablejump instruction. */
2205 #define CASE_VECTOR_MODE Pmode
2206
2207 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2208
2209 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2210 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2211 : (max >= 0x200) ? HImode \
2212 : QImode)
2213
2214 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2215 unsigned is probably best, but may break some code. */
2216 #ifndef DEFAULT_SIGNED_CHAR
2217 #define DEFAULT_SIGNED_CHAR 0
2218 #endif
2219
2220 /* Max number of bytes we can move from memory to memory
2221 in one reasonably fast instruction. */
2222 #define MOVE_MAX 4
2223
2224 #undef MOVE_RATIO
2225 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2226
2227 /* Define if operations between registers always perform the operation
2228 on the full register even if a narrower mode is specified. */
2229 #define WORD_REGISTER_OPERATIONS
2230
2231 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2232 will either zero-extend or sign-extend. The value of this macro should
2233 be the code that says which one of the two operations is implicitly
2234 done, UNKNOWN if none. */
2235 #define LOAD_EXTEND_OP(MODE) \
2236 (TARGET_THUMB ? ZERO_EXTEND : \
2237 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2238 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2239
2240 /* Nonzero if access to memory by bytes is slow and undesirable. */
2241 #define SLOW_BYTE_ACCESS 0
2242
2243 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2244
2245 /* Immediate shift counts are truncated by the output routines (or was it
2246 the assembler?). Shift counts in a register are truncated by ARM. Note
2247 that the native compiler puts too large (> 32) immediate shift counts
2248 into a register and shifts by the register, letting the ARM decide what
2249 to do instead of doing that itself. */
2250 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2251 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2252 On the arm, Y in a register is used modulo 256 for the shift. Only for
2253 rotates is modulo 32 used. */
2254 /* #define SHIFT_COUNT_TRUNCATED 1 */
2255
2256 /* All integers have the same format so truncation is easy. */
2257 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2258
2259 /* Calling from registers is a massive pain. */
2260 #define NO_FUNCTION_CSE 1
2261
2262 /* The machine modes of pointers and functions */
2263 #define Pmode SImode
2264 #define FUNCTION_MODE Pmode
2265
2266 #define ARM_FRAME_RTX(X) \
2267 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2268 || (X) == arg_pointer_rtx)
2269
2270 /* Moves to and from memory are quite expensive */
2271 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2272 (TARGET_32BIT ? 10 : \
2273 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2274 * (CLASS == LO_REGS ? 1 : 2)))
2275
2276 /* Try to generate sequences that don't involve branches, we can then use
2277 conditional instructions */
2278 #define BRANCH_COST \
2279 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2280 \f
2281 /* Position Independent Code. */
2282 /* We decide which register to use based on the compilation options and
2283 the assembler in use; this is more general than the APCS restriction of
2284 using sb (r9) all the time. */
2285 extern unsigned arm_pic_register;
2286
2287 /* The register number of the register used to address a table of static
2288 data addresses in memory. */
2289 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2290
2291 /* We can't directly access anything that contains a symbol,
2292 nor can we indirect via the constant pool. One exception is
2293 UNSPEC_TLS, which is always PIC. */
2294 #define LEGITIMATE_PIC_OPERAND_P(X) \
2295 (!(symbol_mentioned_p (X) \
2296 || label_mentioned_p (X) \
2297 || (GET_CODE (X) == SYMBOL_REF \
2298 && CONSTANT_POOL_ADDRESS_P (X) \
2299 && (symbol_mentioned_p (get_pool_constant (X)) \
2300 || label_mentioned_p (get_pool_constant (X))))) \
2301 || tls_mentioned_p (X))
2302
2303 /* We need to know when we are making a constant pool; this determines
2304 whether data needs to be in the GOT or can be referenced via a GOT
2305 offset. */
2306 extern int making_const_table;
2307 \f
2308 /* Handle pragmas for compatibility with Intel's compilers. */
2309 /* Also abuse this to register additional C specific EABI attributes. */
2310 #define REGISTER_TARGET_PRAGMAS() do { \
2311 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2312 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2313 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2314 arm_lang_object_attributes_init(); \
2315 } while (0)
2316
2317 /* Condition code information. */
2318 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2319 return the mode to be used for the comparison. */
2320
2321 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2322
2323 #define REVERSIBLE_CC_MODE(MODE) 1
2324
2325 #define REVERSE_CONDITION(CODE,MODE) \
2326 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2327 ? reverse_condition_maybe_unordered (code) \
2328 : reverse_condition (code))
2329
2330 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2331 do \
2332 { \
2333 if (GET_CODE (OP1) == CONST_INT \
2334 && ! (const_ok_for_arm (INTVAL (OP1)) \
2335 || (const_ok_for_arm (- INTVAL (OP1))))) \
2336 { \
2337 rtx const_op = OP1; \
2338 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2339 &const_op); \
2340 OP1 = const_op; \
2341 } \
2342 } \
2343 while (0)
2344
2345 /* The arm5 clz instruction returns 32. */
2346 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2347 \f
2348 #undef ASM_APP_OFF
2349 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2350 TARGET_THUMB2 ? "\t.thumb\n" : "")
2351
2352 /* Output a push or a pop instruction (only used when profiling). */
2353 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2354 do \
2355 { \
2356 if (TARGET_ARM) \
2357 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2358 STACK_POINTER_REGNUM, REGNO); \
2359 else \
2360 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2361 } while (0)
2362
2363
2364 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2365 do \
2366 { \
2367 if (TARGET_ARM) \
2368 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2369 STACK_POINTER_REGNUM, REGNO); \
2370 else \
2371 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2372 } while (0)
2373
2374 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2375 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2376
2377 /* This is how to output a label which precedes a jumptable. Since
2378 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2379 #undef ASM_OUTPUT_CASE_LABEL
2380 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2381 do \
2382 { \
2383 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2384 ASM_OUTPUT_ALIGN (FILE, 2); \
2385 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2386 } \
2387 while (0)
2388
2389 /* Make sure subsequent insns are aligned after a TBB. */
2390 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2391 do \
2392 { \
2393 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2394 ASM_OUTPUT_ALIGN (FILE, 1); \
2395 } \
2396 while (0)
2397
2398 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2399 do \
2400 { \
2401 if (TARGET_THUMB) \
2402 { \
2403 if (is_called_in_ARM_mode (DECL) \
2404 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2405 && crtl->is_thunk)) \
2406 fprintf (STREAM, "\t.code 32\n") ; \
2407 else if (TARGET_THUMB1) \
2408 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2409 else \
2410 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2411 } \
2412 if (TARGET_POKE_FUNCTION_NAME) \
2413 arm_poke_function_name (STREAM, (const char *) NAME); \
2414 } \
2415 while (0)
2416
2417 /* For aliases of functions we use .thumb_set instead. */
2418 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2419 do \
2420 { \
2421 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2422 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2423 \
2424 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2425 { \
2426 fprintf (FILE, "\t.thumb_set "); \
2427 assemble_name (FILE, LABEL1); \
2428 fprintf (FILE, ","); \
2429 assemble_name (FILE, LABEL2); \
2430 fprintf (FILE, "\n"); \
2431 } \
2432 else \
2433 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2434 } \
2435 while (0)
2436
2437 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2438 /* To support -falign-* switches we need to use .p2align so
2439 that alignment directives in code sections will be padded
2440 with no-op instructions, rather than zeroes. */
2441 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2442 if ((LOG) != 0) \
2443 { \
2444 if ((MAX_SKIP) == 0) \
2445 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2446 else \
2447 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2448 (int) (LOG), (int) (MAX_SKIP)); \
2449 }
2450 #endif
2451 \f
2452 /* Add two bytes to the length of conditionally executed Thumb-2
2453 instructions for the IT instruction. */
2454 #define ADJUST_INSN_LENGTH(insn, length) \
2455 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2456 length += 2;
2457
2458 /* Only perform branch elimination (by making instructions conditional) if
2459 we're optimizing. For Thumb-2 check if any IT instructions need
2460 outputting. */
2461 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2462 if (TARGET_ARM && optimize) \
2463 arm_final_prescan_insn (INSN); \
2464 else if (TARGET_THUMB2) \
2465 thumb2_final_prescan_insn (INSN); \
2466 else if (TARGET_THUMB1) \
2467 thumb1_final_prescan_insn (INSN)
2468
2469 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2470 (CODE == '@' || CODE == '|' || CODE == '.' \
2471 || CODE == '(' || CODE == ')' || CODE == '#' \
2472 || (TARGET_32BIT && (CODE == '?')) \
2473 || (TARGET_THUMB2 && (CODE == '!')) \
2474 || (TARGET_THUMB && (CODE == '_')))
2475
2476 /* Output an operand of an instruction. */
2477 #define PRINT_OPERAND(STREAM, X, CODE) \
2478 arm_print_operand (STREAM, X, CODE)
2479
2480 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2481 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2482 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2483 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2484 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2485 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2486 : 0))))
2487
2488 /* Output the address of an operand. */
2489 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2490 { \
2491 int is_minus = GET_CODE (X) == MINUS; \
2492 \
2493 if (GET_CODE (X) == REG) \
2494 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2495 else if (GET_CODE (X) == PLUS || is_minus) \
2496 { \
2497 rtx base = XEXP (X, 0); \
2498 rtx index = XEXP (X, 1); \
2499 HOST_WIDE_INT offset = 0; \
2500 if (GET_CODE (base) != REG \
2501 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2502 { \
2503 /* Ensure that BASE is a register. */ \
2504 /* (one of them must be). */ \
2505 /* Also ensure the SP is not used as in index register. */ \
2506 rtx temp = base; \
2507 base = index; \
2508 index = temp; \
2509 } \
2510 switch (GET_CODE (index)) \
2511 { \
2512 case CONST_INT: \
2513 offset = INTVAL (index); \
2514 if (is_minus) \
2515 offset = -offset; \
2516 asm_fprintf (STREAM, "[%r, #%wd]", \
2517 REGNO (base), offset); \
2518 break; \
2519 \
2520 case REG: \
2521 asm_fprintf (STREAM, "[%r, %s%r]", \
2522 REGNO (base), is_minus ? "-" : "", \
2523 REGNO (index)); \
2524 break; \
2525 \
2526 case MULT: \
2527 case ASHIFTRT: \
2528 case LSHIFTRT: \
2529 case ASHIFT: \
2530 case ROTATERT: \
2531 { \
2532 asm_fprintf (STREAM, "[%r, %s%r", \
2533 REGNO (base), is_minus ? "-" : "", \
2534 REGNO (XEXP (index, 0))); \
2535 arm_print_operand (STREAM, index, 'S'); \
2536 fputs ("]", STREAM); \
2537 break; \
2538 } \
2539 \
2540 default: \
2541 gcc_unreachable (); \
2542 } \
2543 } \
2544 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2545 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2546 { \
2547 extern enum machine_mode output_memory_reference_mode; \
2548 \
2549 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2550 \
2551 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2552 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2553 REGNO (XEXP (X, 0)), \
2554 GET_CODE (X) == PRE_DEC ? "-" : "", \
2555 GET_MODE_SIZE (output_memory_reference_mode)); \
2556 else \
2557 asm_fprintf (STREAM, "[%r], #%s%d", \
2558 REGNO (XEXP (X, 0)), \
2559 GET_CODE (X) == POST_DEC ? "-" : "", \
2560 GET_MODE_SIZE (output_memory_reference_mode)); \
2561 } \
2562 else if (GET_CODE (X) == PRE_MODIFY) \
2563 { \
2564 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2565 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2566 asm_fprintf (STREAM, "#%wd]!", \
2567 INTVAL (XEXP (XEXP (X, 1), 1))); \
2568 else \
2569 asm_fprintf (STREAM, "%r]!", \
2570 REGNO (XEXP (XEXP (X, 1), 1))); \
2571 } \
2572 else if (GET_CODE (X) == POST_MODIFY) \
2573 { \
2574 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2575 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2576 asm_fprintf (STREAM, "#%wd", \
2577 INTVAL (XEXP (XEXP (X, 1), 1))); \
2578 else \
2579 asm_fprintf (STREAM, "%r", \
2580 REGNO (XEXP (XEXP (X, 1), 1))); \
2581 } \
2582 else output_addr_const (STREAM, X); \
2583 }
2584
2585 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2586 { \
2587 if (GET_CODE (X) == REG) \
2588 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2589 else if (GET_CODE (X) == POST_INC) \
2590 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2591 else if (GET_CODE (X) == PLUS) \
2592 { \
2593 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2594 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2595 asm_fprintf (STREAM, "[%r, #%wd]", \
2596 REGNO (XEXP (X, 0)), \
2597 INTVAL (XEXP (X, 1))); \
2598 else \
2599 asm_fprintf (STREAM, "[%r, %r]", \
2600 REGNO (XEXP (X, 0)), \
2601 REGNO (XEXP (X, 1))); \
2602 } \
2603 else \
2604 output_addr_const (STREAM, X); \
2605 }
2606
2607 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2608 if (TARGET_32BIT) \
2609 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2610 else \
2611 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2612
2613 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2614 if (arm_output_addr_const_extra (file, x) == FALSE) \
2615 goto fail
2616
2617 /* A C expression whose value is RTL representing the value of the return
2618 address for the frame COUNT steps up from the current frame. */
2619
2620 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2621 arm_return_addr (COUNT, FRAME)
2622
2623 /* Mask of the bits in the PC that contain the real return address
2624 when running in 26-bit mode. */
2625 #define RETURN_ADDR_MASK26 (0x03fffffc)
2626
2627 /* Pick up the return address upon entry to a procedure. Used for
2628 dwarf2 unwind information. This also enables the table driven
2629 mechanism. */
2630 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2631 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2632
2633 /* Used to mask out junk bits from the return address, such as
2634 processor state, interrupt status, condition codes and the like. */
2635 #define MASK_RETURN_ADDR \
2636 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2637 in 26 bit mode, the condition codes must be masked out of the \
2638 return address. This does not apply to ARM6 and later processors \
2639 when running in 32 bit mode. */ \
2640 ((arm_arch4 || TARGET_THUMB) \
2641 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2642 : arm_gen_return_addr_mask ())
2643
2644 \f
2645 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2646 symbolic names defined here (which would require too much duplication).
2647 FIXME? */
2648 enum arm_builtins
2649 {
2650 ARM_BUILTIN_GETWCX,
2651 ARM_BUILTIN_SETWCX,
2652
2653 ARM_BUILTIN_WZERO,
2654
2655 ARM_BUILTIN_WAVG2BR,
2656 ARM_BUILTIN_WAVG2HR,
2657 ARM_BUILTIN_WAVG2B,
2658 ARM_BUILTIN_WAVG2H,
2659
2660 ARM_BUILTIN_WACCB,
2661 ARM_BUILTIN_WACCH,
2662 ARM_BUILTIN_WACCW,
2663
2664 ARM_BUILTIN_WMACS,
2665 ARM_BUILTIN_WMACSZ,
2666 ARM_BUILTIN_WMACU,
2667 ARM_BUILTIN_WMACUZ,
2668
2669 ARM_BUILTIN_WSADB,
2670 ARM_BUILTIN_WSADBZ,
2671 ARM_BUILTIN_WSADH,
2672 ARM_BUILTIN_WSADHZ,
2673
2674 ARM_BUILTIN_WALIGN,
2675
2676 ARM_BUILTIN_TMIA,
2677 ARM_BUILTIN_TMIAPH,
2678 ARM_BUILTIN_TMIABB,
2679 ARM_BUILTIN_TMIABT,
2680 ARM_BUILTIN_TMIATB,
2681 ARM_BUILTIN_TMIATT,
2682
2683 ARM_BUILTIN_TMOVMSKB,
2684 ARM_BUILTIN_TMOVMSKH,
2685 ARM_BUILTIN_TMOVMSKW,
2686
2687 ARM_BUILTIN_TBCSTB,
2688 ARM_BUILTIN_TBCSTH,
2689 ARM_BUILTIN_TBCSTW,
2690
2691 ARM_BUILTIN_WMADDS,
2692 ARM_BUILTIN_WMADDU,
2693
2694 ARM_BUILTIN_WPACKHSS,
2695 ARM_BUILTIN_WPACKWSS,
2696 ARM_BUILTIN_WPACKDSS,
2697 ARM_BUILTIN_WPACKHUS,
2698 ARM_BUILTIN_WPACKWUS,
2699 ARM_BUILTIN_WPACKDUS,
2700
2701 ARM_BUILTIN_WADDB,
2702 ARM_BUILTIN_WADDH,
2703 ARM_BUILTIN_WADDW,
2704 ARM_BUILTIN_WADDSSB,
2705 ARM_BUILTIN_WADDSSH,
2706 ARM_BUILTIN_WADDSSW,
2707 ARM_BUILTIN_WADDUSB,
2708 ARM_BUILTIN_WADDUSH,
2709 ARM_BUILTIN_WADDUSW,
2710 ARM_BUILTIN_WSUBB,
2711 ARM_BUILTIN_WSUBH,
2712 ARM_BUILTIN_WSUBW,
2713 ARM_BUILTIN_WSUBSSB,
2714 ARM_BUILTIN_WSUBSSH,
2715 ARM_BUILTIN_WSUBSSW,
2716 ARM_BUILTIN_WSUBUSB,
2717 ARM_BUILTIN_WSUBUSH,
2718 ARM_BUILTIN_WSUBUSW,
2719
2720 ARM_BUILTIN_WAND,
2721 ARM_BUILTIN_WANDN,
2722 ARM_BUILTIN_WOR,
2723 ARM_BUILTIN_WXOR,
2724
2725 ARM_BUILTIN_WCMPEQB,
2726 ARM_BUILTIN_WCMPEQH,
2727 ARM_BUILTIN_WCMPEQW,
2728 ARM_BUILTIN_WCMPGTUB,
2729 ARM_BUILTIN_WCMPGTUH,
2730 ARM_BUILTIN_WCMPGTUW,
2731 ARM_BUILTIN_WCMPGTSB,
2732 ARM_BUILTIN_WCMPGTSH,
2733 ARM_BUILTIN_WCMPGTSW,
2734
2735 ARM_BUILTIN_TEXTRMSB,
2736 ARM_BUILTIN_TEXTRMSH,
2737 ARM_BUILTIN_TEXTRMSW,
2738 ARM_BUILTIN_TEXTRMUB,
2739 ARM_BUILTIN_TEXTRMUH,
2740 ARM_BUILTIN_TEXTRMUW,
2741 ARM_BUILTIN_TINSRB,
2742 ARM_BUILTIN_TINSRH,
2743 ARM_BUILTIN_TINSRW,
2744
2745 ARM_BUILTIN_WMAXSW,
2746 ARM_BUILTIN_WMAXSH,
2747 ARM_BUILTIN_WMAXSB,
2748 ARM_BUILTIN_WMAXUW,
2749 ARM_BUILTIN_WMAXUH,
2750 ARM_BUILTIN_WMAXUB,
2751 ARM_BUILTIN_WMINSW,
2752 ARM_BUILTIN_WMINSH,
2753 ARM_BUILTIN_WMINSB,
2754 ARM_BUILTIN_WMINUW,
2755 ARM_BUILTIN_WMINUH,
2756 ARM_BUILTIN_WMINUB,
2757
2758 ARM_BUILTIN_WMULUM,
2759 ARM_BUILTIN_WMULSM,
2760 ARM_BUILTIN_WMULUL,
2761
2762 ARM_BUILTIN_PSADBH,
2763 ARM_BUILTIN_WSHUFH,
2764
2765 ARM_BUILTIN_WSLLH,
2766 ARM_BUILTIN_WSLLW,
2767 ARM_BUILTIN_WSLLD,
2768 ARM_BUILTIN_WSRAH,
2769 ARM_BUILTIN_WSRAW,
2770 ARM_BUILTIN_WSRAD,
2771 ARM_BUILTIN_WSRLH,
2772 ARM_BUILTIN_WSRLW,
2773 ARM_BUILTIN_WSRLD,
2774 ARM_BUILTIN_WRORH,
2775 ARM_BUILTIN_WRORW,
2776 ARM_BUILTIN_WRORD,
2777 ARM_BUILTIN_WSLLHI,
2778 ARM_BUILTIN_WSLLWI,
2779 ARM_BUILTIN_WSLLDI,
2780 ARM_BUILTIN_WSRAHI,
2781 ARM_BUILTIN_WSRAWI,
2782 ARM_BUILTIN_WSRADI,
2783 ARM_BUILTIN_WSRLHI,
2784 ARM_BUILTIN_WSRLWI,
2785 ARM_BUILTIN_WSRLDI,
2786 ARM_BUILTIN_WRORHI,
2787 ARM_BUILTIN_WRORWI,
2788 ARM_BUILTIN_WRORDI,
2789
2790 ARM_BUILTIN_WUNPCKIHB,
2791 ARM_BUILTIN_WUNPCKIHH,
2792 ARM_BUILTIN_WUNPCKIHW,
2793 ARM_BUILTIN_WUNPCKILB,
2794 ARM_BUILTIN_WUNPCKILH,
2795 ARM_BUILTIN_WUNPCKILW,
2796
2797 ARM_BUILTIN_WUNPCKEHSB,
2798 ARM_BUILTIN_WUNPCKEHSH,
2799 ARM_BUILTIN_WUNPCKEHSW,
2800 ARM_BUILTIN_WUNPCKEHUB,
2801 ARM_BUILTIN_WUNPCKEHUH,
2802 ARM_BUILTIN_WUNPCKEHUW,
2803 ARM_BUILTIN_WUNPCKELSB,
2804 ARM_BUILTIN_WUNPCKELSH,
2805 ARM_BUILTIN_WUNPCKELSW,
2806 ARM_BUILTIN_WUNPCKELUB,
2807 ARM_BUILTIN_WUNPCKELUH,
2808 ARM_BUILTIN_WUNPCKELUW,
2809
2810 ARM_BUILTIN_THREAD_POINTER,
2811
2812 ARM_BUILTIN_NEON_BASE,
2813
2814 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2815 };
2816
2817 /* Do not emit .note.GNU-stack by default. */
2818 #ifndef NEED_INDICATE_EXEC_STACK
2819 #define NEED_INDICATE_EXEC_STACK 0
2820 #endif
2821
2822 #endif /* ! GCC_ARM_H */
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