| blob | 8c34084e1fd20f637868fd52593f2e63af131e50 |
1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
27 #define TARGET_VERSION \
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
35 /* Generate SDB debugging information. */
37 #define SDB_DEBUGGING_INFO
39 /* Output DBX (stabs) debugging information if doing -gstabs. */
46 %{m1:-D__sh1__} \
47 %{m2:-D__sh2__} \
48 %{m3:-D__sh3__} \
49 %{m3e:-D__SH3E__} \
50 %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
51 %{m4-single:-D__SH4_SINGLE__} \
52 %{m4-nofpu:-D__sh3__ -D__SH4_NOFPU__} \
53 %{m4:-D__SH4__} \
54 %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:%{!m4-nofpu:-D__sh1__}}}}}}}} \
55 %{mnomacsave:-D__NOMACSAVE__} \
56 %{mhitachi:-D__HITACHI__}"
64 /* We can not debug without a frame pointer. */
65 /* #define CAN_DEBUG_WITHOUT_FP */
67 #define CONDITIONAL_REGISTER_USAGE do \
68 { \
69 int regno; \
70 if (! TARGET_SH4 || ! TARGET_FMOVD) \
71 { \
72 for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
73 fixed_regs[regno] = call_used_regs[regno] = 1; \
74 if (! TARGET_SH4) \
75 { \
76 if (! TARGET_SH3E) \
77 { \
78 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
79 fixed_regs[regno] = call_used_regs[regno] = 1; \
80 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
81 } \
82 } \
83 } \
84 if (flag_pic) \
85 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
87 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
88 { \
89 call_used_regs[MACH_REG] = 0; \
90 call_used_regs[MACL_REG] = 0; \
91 } \
92 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
93 if (! fixed_regs[regno] && call_used_regs[regno]) \
94 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
95 } while (0)
96 \f
97 /* ??? Need to write documentation for all SH options and add it to the
98 invoke.texi file. */
100 /* Run-time compilation parameters selecting different hardware subsets. */
103 #define ISIZE_BIT (1<<1)
104 #define DALIGN_BIT (1<<6)
105 #define SH1_BIT (1<<8)
106 #define SH2_BIT (1<<9)
107 #define SH3_BIT (1<<10)
108 #define SH3E_BIT (1<<11)
109 #define HARD_SH4_BIT (1<<5)
110 #define FPU_SINGLE_BIT (1<<7)
111 #define SH4_BIT (1<<12)
112 #define FMOVD_BIT (1<<4)
113 #define SPACE_BIT (1<<13)
114 #define BIGTABLE_BIT (1<<14)
115 #define RELAX_BIT (1<<15)
116 #define USERMODE_BIT (1<<16)
117 #define HITACHI_BIT (1<<22)
118 #define NOMACSAVE_BIT (1<<23)
119 #define PREFERGOT_BIT (1<<24)
120 #define PADSTRUCT_BIT (1<<28)
121 #define LITTLE_ENDIAN_BIT (1<<29)
122 #define IEEE_BIT (1<<30)
124 /* Nonzero if we should dump out instruction size info. */
125 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
127 /* Nonzero to align doubles on 64 bit boundaries. */
128 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
130 /* Nonzero if we should generate code using type 1 insns. */
131 #define TARGET_SH1 (target_flags & SH1_BIT)
133 /* Nonzero if we should generate code using type 2 insns. */
134 #define TARGET_SH2 (target_flags & SH2_BIT)
136 /* Nonzero if we should generate code using type 3 insns. */
137 #define TARGET_SH3 (target_flags & SH3_BIT)
139 /* Nonzero if we should generate code using type 3E insns. */
140 #define TARGET_SH3E (target_flags & SH3E_BIT)
142 /* Nonzero if the cache line size is 32. */
143 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
145 /* Nonzero if we schedule for a superscalar implementation. */
146 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
148 /* Nonzero if the target has separate instruction and data caches. */
149 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
151 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
152 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
154 /* Nonzero if the default precision of th FPU is single */
155 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
157 /* Nonzero if we should generate code using type 4 insns. */
158 #define TARGET_SH4 (target_flags & SH4_BIT)
160 /* Nonzero if we should generate fmovd. */
161 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
163 /* Nonzero if we respect NANs. */
164 #define TARGET_IEEE (target_flags & IEEE_BIT)
166 /* Nonzero if we should generate smaller code rather than faster code. */
167 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
169 /* Nonzero to use long jump tables. */
170 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
172 /* Nonzero to generate pseudo-ops needed by the assembler and linker
173 to do function call relaxing. */
174 #define TARGET_RELAX (target_flags & RELAX_BIT)
176 /* Nonzero if using Hitachi's calling convention. */
177 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
179 /* Nonzero if not saving macl/mach when using -mhitachi */
180 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
182 /* Nonzero if padding structures to a multiple of 4 bytes. This is
183 incompatible with Hitachi's compiler, and gives unusual structure layouts
184 which confuse programmers.
185 ??? This option is not useful, but is retained in case there are people
186 who are still relying on it. It may be deleted in the future. */
187 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
189 /* Nonzero if generating code for a little endian SH. */
190 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
192 /* Nonzero if we should do everything in userland. */
193 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
195 /* Nonzero if we should prefer @GOT calls when generating PIC. */
196 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
198 /* Reset all target-selection flags. */
199 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
200 | HARD_SH4_BIT | FPU_SINGLE_BIT)
202 #define TARGET_SWITCHES \
234 SUBTARGET_SWITCHES \
236 }
238 /* This are meant to be redefined in the host dependent files */
239 #define SUBTARGET_SWITCHES
241 #define TARGET_DEFAULT (SH1_BIT)
243 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
244 do { \
245 if (LEVEL) \
246 flag_omit_frame_pointer = -1; \
247 if (SIZE) \
248 target_flags |= SPACE_BIT; \
249 } while (0)
251 #define ASSEMBLER_DIALECT assembler_dialect
255 #define OVERRIDE_OPTIONS \
256 do { \
257 sh_cpu = CPU_SH1; \
258 assembler_dialect = 0; \
259 if (TARGET_SH2) \
260 sh_cpu = CPU_SH2; \
261 if (TARGET_SH3) \
262 sh_cpu = CPU_SH3; \
263 if (TARGET_SH3E) \
264 sh_cpu = CPU_SH3E; \
265 if (TARGET_SH4) \
266 { \
267 assembler_dialect = 1; \
268 sh_cpu = CPU_SH4; \
269 } \
270 if (! TARGET_SH4 || ! TARGET_FMOVD) \
271 { \
272 /* Prevent usage of explicit register names for variables \
273 for registers not present / not addressable in the \
275 int regno; \
276 for (regno = (TARGET_SH3E) ? 17 : 0; \
277 regno <= 24; regno++) \
278 fp_reg_names[regno][0] = 0; \
279 } \
280 if (flag_omit_frame_pointer < 0) \
281 /* The debugging information is sufficient, \
283 if (0) \
284 flag_omit_frame_pointer \
285 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
286 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
287 else \
288 flag_omit_frame_pointer = 0; \
289 \
290 if (flag_pic && ! TARGET_PREFERGOT) \
291 flag_no_function_cse = 1; \
292 \
293 /* Never run scheduling before reload, since that can \
294 break global alloc, and generates slower code anyway due \
296 flag_schedule_insns = 0; \
297 } while (0)
298 \f
299 /* Target machine storage layout. */
301 /* Define to use software floating point emulator for REAL_ARITHMETIC and
302 decimal <-> binary conversion. */
303 #define REAL_ARITHMETIC
305 /* Define this if most significant bit is lowest numbered
306 in instructions that operate on numbered bit-fields. */
308 #define BITS_BIG_ENDIAN 0
310 /* Define this if most significant byte of a word is the lowest numbered. */
311 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
313 /* Define this if most significant word of a multiword number is the lowest
314 numbered. */
315 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
317 /* Define this to set the endianness to use in libgcc2.c, which can
318 not depend on target_flags. */
319 #if defined(__LITTLE_ENDIAN__)
320 #define LIBGCC2_WORDS_BIG_ENDIAN 0
321 #else
322 #define LIBGCC2_WORDS_BIG_ENDIAN 1
323 #endif
325 /* Number of bits in an addressable storage unit. */
326 #define BITS_PER_UNIT 8
328 /* Width in bits of a "word", which is the contents of a machine register.
329 Note that this is not necessarily the width of data type `int';
330 if using 16-bit ints on a 68000, this would still be 32.
331 But on a machine with 16-bit registers, this would be 16. */
332 #define BITS_PER_WORD 32
333 #define MAX_BITS_PER_WORD 32
335 /* Width of a word, in units (bytes). */
336 #define UNITS_PER_WORD 4
338 /* Width in bits of a pointer.
339 See also the macro `Pmode' defined below. */
340 #define POINTER_SIZE 32
342 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
343 #define PARM_BOUNDARY 32
345 /* Boundary (in *bits*) on which stack pointer should be aligned. */
346 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
348 /* The log (base 2) of the cache line size, in bytes. Processors prior to
349 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
350 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
351 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
353 /* Allocation boundary (in *bits*) for the code of a function.
354 32 bit alignment is faster, because instructions are always fetched as a
355 pair from a longword boundary. */
356 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
358 /* Alignment of field after `int : 0' in a structure. */
359 #define EMPTY_FIELD_BOUNDARY 32
361 /* No data type wants to be aligned rounder than this. */
362 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
364 /* The best alignment to use in cases where we have a choice. */
365 #define FASTEST_ALIGNMENT 32
367 /* Make strings word-aligned so strcpy from constants will be faster. */
368 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
369 ((TREE_CODE (EXP) == STRING_CST \
370 && (ALIGN) < FASTEST_ALIGNMENT) \
371 ? FASTEST_ALIGNMENT : (ALIGN))
373 #ifndef MAX_OFILE_ALIGNMENT
374 #define MAX_OFILE_ALIGNMENT 128
375 #endif
377 /* Make arrays of chars word-aligned for the same reasons. */
378 #define DATA_ALIGNMENT(TYPE, ALIGN) \
379 (TREE_CODE (TYPE) == ARRAY_TYPE \
380 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
381 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
383 /* Number of bits which any structure or union's size must be a
384 multiple of. Each structure or union's size is rounded up to a
385 multiple of this. */
386 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
388 /* Set this nonzero if move instructions will actually fail to work
389 when given unaligned data. */
390 #define STRICT_ALIGNMENT 1
392 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
393 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
394 barrier_align (LABEL_AFTER_BARRIER)
396 #define LOOP_ALIGN(A_LABEL) \
397 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
398 ? 0 : sh_loop_align (A_LABEL))
400 #define LABEL_ALIGN(A_LABEL) \
401 ( \
402 (PREV_INSN (A_LABEL) \
403 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
404 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
405 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
407 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
408 : 0)
410 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
411 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
413 /* The base two logarithm of the known minimum alignment of an insn length. */
414 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
415 (GET_CODE (A_INSN) == INSN \
416 ? 1 \
417 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
418 ? 1 \
419 : CACHE_LOG)
420 \f
421 /* Standard register usage. */
423 /* Register allocation for the Hitachi calling convention:
425 r0 arg return
426 r1..r3 scratch
427 r4..r7 args in
428 r8..r13 call saved
429 r14 frame pointer/call saved
430 r15 stack pointer
431 ap arg pointer (doesn't really exist, always eliminated)
432 pr subroutine return address
433 t t bit
434 mach multiply/accumulate result, high part
435 macl multiply/accumulate result, low part.
436 fpul fp/int communication register
437 rap return address pointer register
438 fr0 fp arg return
439 fr1..fr3 scratch floating point registers
440 fr4..fr11 fp args in
441 fr12..fr15 call saved floating point registers */
443 /* Number of actual hardware registers.
444 The hardware registers are assigned numbers for the compiler
445 from 0 to just below FIRST_PSEUDO_REGISTER.
446 All registers that the compiler knows about must be given numbers,
447 even those that are not normally considered general registers. */
449 /* There are many other relevant definitions in sh.md's md_constants. */
451 #define FIRST_GENERAL_REG R0_REG
452 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + 15)
453 #define FIRST_FP_REG DR0_REG
454 #define LAST_FP_REG (FIRST_FP_REG + 15)
455 #define FIRST_XD_REG XD0_REG
456 #define LAST_XD_REG (FIRST_XD_REG + 7)
458 #define GENERAL_REGISTER_P(REGNO) \
459 ((REGNO) >= FIRST_GENERAL_REG && (REGNO) <= LAST_GENERAL_REG)
461 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
462 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
464 #define FP_REGISTER_P(REGNO) \
465 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
467 #define XD_REGISTER_P(REGNO) \
468 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
470 #define FP_OR_XD_REGISTER_P(REGNO) \
471 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
473 #define FP_ANY_REGISTER_P(REGNO) \
474 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
476 #define SPECIAL_REGISTER_P(REGNO) \
477 ((REGNO) == GBR_REG || (REGNO) == T_REG \
478 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
480 #define FIRST_PSEUDO_REGISTER 49
482 /* 1 for registers that have pervasive standard uses
483 and are not available for the register allocator.
485 Mach register is fixed 'cause it's only 10 bits wide for SH1.
486 It is 32 bits wide for SH2. */
488 #define FIXED_REGISTERS \
489 { 0, 0, 0, 0, \
490 0, 0, 0, 0, \
491 0, 0, 0, 0, \
492 0, 0, 0, 1, \
493 1, 1, 1, 1, \
494 1, 1, 0, 1, \
495 0, 0, 0, 0, \
496 0, 0, 0, 0, \
497 0, 0, 0, 0, \
498 0, 0, 0, 0, \
499 0, 0, 0, 0, \
500 0, 0, 0, 0, \
501 1, \
502 }
504 /* 1 for registers not available across function calls.
505 These must include the FIXED_REGISTERS and also any
506 registers that can be used without being saved.
507 The latter must include the registers where values are returned
508 and the register where structure-value addresses are passed.
509 Aside from that, you can include as many other registers as you like. */
511 #define CALL_USED_REGISTERS \
512 { 1, 1, 1, 1, \
513 1, 1, 1, 1, \
514 0, 0, 0, 0, \
515 0, 0, 0, 1, \
516 1, 0, 1, 1, \
517 1, 1, 1, 1, \
518 1, 1, 1, 1, \
519 1, 1, 1, 1, \
520 1, 1, 1, 1, \
521 0, 0, 0, 0, \
522 1, 1, 1, 1, \
523 1, 1, 0, 0, \
524 1, \
525 }
527 /* Return number of consecutive hard regs needed starting at reg REGNO
528 to hold something of mode MODE.
529 This is ordinarily the length in words of a value of mode MODE
530 but can be less for certain modes in special long registers.
532 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
534 #define HARD_REGNO_NREGS(REGNO, MODE) \
535 (XD_REGISTER_P (REGNO) \
536 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
537 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
539 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
540 We can allow any mode in any general register. The special registers
541 only allow SImode. Don't allow any mode in the PR. */
543 /* We cannot hold DCmode values in the XD registers because alter_reg
544 handles subregs of them incorrectly. We could work around this by
545 spacing the XD registers like the DR registers, but this would require
546 additional memory in every compilation to hold larger register vectors.
547 We could hold SFmode / SCmode values in XD registers, but that
548 would require a tertiary reload when reloading from / to memory,
549 and a secondary reload to reload from / to general regs; that
550 seems to be a loosing proposition. */
551 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
552 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
553 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
554 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
555 ? 1 \
556 : FP_REGISTER_P (REGNO) \
557 ? ((MODE) == SFmode \
558 || (TARGET_SH3E && (MODE) == SCmode) \
559 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
560 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
561 : XD_REGISTER_P (REGNO) \
562 ? (MODE) == DFmode \
563 : (REGNO) == PR_REG ? 0 \
564 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
565 : 1)
567 /* Value is 1 if it is a good idea to tie two pseudo registers
568 when one has mode MODE1 and one has mode MODE2.
569 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
570 for any hard reg, then this must be 0 for correct output.
571 That's the case for xd registers: we don't hold SFmode values in
572 them, so we can't tie an SFmode pseudos with one in another
573 floating-point mode. */
575 #define MODES_TIEABLE_P(MODE1, MODE2) \
576 ((MODE1) == (MODE2) \
577 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
578 && (MODE1) != SFmode && (MODE2) != SFmode))
580 /* Specify the registers used for certain standard purposes.
581 The values of these macros are register numbers. */
583 /* Define this if the program counter is overloaded on a register. */
584 /* #define PC_REGNUM 15*/
586 /* Register to use for pushing function arguments. */
587 #define STACK_POINTER_REGNUM SP_REG
589 /* Base register for access to local variables of the function. */
590 #define FRAME_POINTER_REGNUM FP_REG
592 /* Fake register that holds the address on the stack of the
593 current function's return address. */
594 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
596 /* Register to hold the addressing base for position independent
597 code access to data items. */
598 #define PIC_OFFSET_TABLE_REGNUM PIC_REG
602 /* Value should be nonzero if functions must have frame pointers.
603 Zero means the frame pointer need not be set up (and parms may be accessed
604 via the stack pointer) in functions that seem suitable. */
606 #define FRAME_POINTER_REQUIRED 0
608 /* Definitions for register eliminations.
610 We have three registers that can be eliminated on the SH. First, the
611 frame pointer register can often be eliminated in favor of the stack
612 pointer register. Secondly, the argument pointer register can always be
613 eliminated; it is replaced with either the stack or frame pointer.
614 Third, there is the return address pointer, which can also be replaced
615 with either the stack or the frame pointer. */
617 /* This is an array of structures. Each structure initializes one pair
618 of eliminable registers. The "from" register number is given first,
619 followed by "to". Eliminations of the same "from" register are listed
620 in order of preference. */
622 /* If you add any registers here that are not actually hard registers,
623 and that have any alternative of elimination that doesn't always
624 apply, you need to amend calc_live_regs to exclude it, because
625 reload spills all eliminable registers where it sees an
626 can_eliminate == 0 entry, thus making them 'live' .
627 If you add any hard registers that can be eliminated in different
628 ways, you have to patch reload to spill them only when all alternatives
629 of elimination fail. */
631 #define ELIMINABLE_REGS \
632 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
633 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
634 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
635 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
636 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
638 /* Given FROM and TO register numbers, say whether this elimination
639 is allowed. */
640 #define CAN_ELIMINATE(FROM, TO) \
641 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
643 /* Define the offset between two registers, one to be eliminated, and the other
644 its replacement, at the start of a routine. */
646 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
647 OFFSET = initial_elimination_offset ((FROM), (TO))
649 /* Base register for access to arguments of the function. */
650 #define ARG_POINTER_REGNUM AP_REG
652 /* Register in which the static-chain is passed to a function. */
653 #define STATIC_CHAIN_REGNUM 3
655 /* The register in which a struct value address is passed. */
657 #define STRUCT_VALUE_REGNUM 2
659 /* If the structure value address is not passed in a register, define
660 `STRUCT_VALUE' as an expression returning an RTX for the place
661 where the address is passed. If it returns 0, the address is
662 passed as an "invisible" first argument. */
664 /* The Hitachi calling convention doesn't quite fit into this scheme since
665 the address is passed like an invisible argument, but one that is always
666 passed in memory. */
667 #define STRUCT_VALUE \
668 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
670 #define RETURN_IN_MEMORY(TYPE) \
671 (TYPE_MODE (TYPE) == BLKmode \
672 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE)
674 /* Don't default to pcc-struct-return, because we have already specified
675 exactly how to return structures in the RETURN_IN_MEMORY macro. */
677 #define DEFAULT_PCC_STRUCT_RETURN 0
678 \f
679 /* Define the classes of registers for register constraints in the
680 machine description. Also define ranges of constants.
682 One of the classes must always be named ALL_REGS and include all hard regs.
683 If there is more than one class, another class must be named NO_REGS
684 and contain no registers.
686 The name GENERAL_REGS must be the name of a class (or an alias for
687 another name such as ALL_REGS). This is the class of registers
688 that is allowed by "g" or "r" in a register constraint.
689 Also, registers outside this class are allocated only when
690 instructions express preferences for them.
692 The classes must be numbered in nondecreasing order; that is,
693 a larger-numbered class must never be contained completely
694 in a smaller-numbered class.
696 For any two classes, it is very desirable that there be another
697 class that represents their union. */
699 /* The SH has two sorts of general registers, R0 and the rest. R0 can
700 be used as the destination of some of the arithmetic ops. There are
701 also some special purpose registers; the T bit register, the
702 Procedure Return Register and the Multiply Accumulate Registers. */
703 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
704 reg_class_subunion. We don't want to have an actual union class
705 of these, because it would only be used when both classes are calculated
706 to give the same cost, but there is only one FPUL register.
707 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
708 applying to the actual instruction alternative considered. E.g., the
709 y/r alternative of movsi_ie is considered to have no more cost that
710 the r/r alternative, which is patently untrue. */
712 enum reg_class
713 {
714 NO_REGS,
715 R0_REGS,
716 PR_REGS,
717 T_REGS,
718 MAC_REGS,
719 FPUL_REGS,
720 SIBCALL_REGS,
721 GENERAL_REGS,
722 FP0_REGS,
723 FP_REGS,
724 DF_REGS,
725 FPSCR_REGS,
726 GENERAL_FP_REGS,
727 ALL_REGS,
728 LIM_REG_CLASSES
729 };
731 #define N_REG_CLASSES (int) LIM_REG_CLASSES
733 /* Give names of register classes as strings for dump file. */
734 #define REG_CLASS_NAMES \
735 { \
750 }
752 /* Define which registers fit in which classes.
753 This is an initializer for a vector of HARD_REG_SET
754 of length N_REG_CLASSES. */
756 #define REG_CLASS_CONTENTS \
757 { \
773 }
775 /* The same information, inverted:
776 Return the class number of the smallest class containing
777 reg number REGNO. This could be a conditional expression
778 or could index an array. */
781 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
783 /* When defined, the compiler allows registers explicitly used in the
784 rtl to be used as spill registers but prevents the compiler from
785 extending the lifetime of these registers. */
787 #define SMALL_REGISTER_CLASSES 1
789 /* The order in which register should be allocated. */
790 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
791 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
792 spilled or used otherwise, we better have the FP_REGS allocated first. */
793 #define REG_ALLOC_ORDER \
794 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \
795 40,41,42,43,44,45,46,47,48, \
796 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
797 22,15,16,17,18,19,20,21,23 }
799 /* The class value for index registers, and the one for base regs. */
800 #define INDEX_REG_CLASS R0_REGS
801 #define BASE_REG_CLASS GENERAL_REGS
803 /* Get reg_class from a letter such as appears in the machine
804 description. */
807 #define REG_CLASS_FROM_LETTER(C) \
809 \f
810 /* The letters I, J, K, L and M in a register constraint string
811 can be used to stand for particular ranges of immediate operands.
812 This macro defines what the ranges are.
813 C is the letter, and VALUE is a constant value.
814 Return 1 if VALUE is in the range specified by C.
815 I: arithmetic operand -127..128, as used in add, sub, etc
816 K: shift operand 1,2,8 or 16
817 L: logical operand 0..255, as used in and, or, etc.
818 M: constant 1
819 N: constant 0 */
821 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
822 && ((HOST_WIDE_INT)(VALUE)) <= 127)
823 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
824 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
825 && ((HOST_WIDE_INT)(VALUE)) <= 255)
826 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
827 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
828 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
834 : 0)
836 /* Similar, but for floating constants, and defining letters G and H.
837 Here VALUE is the CONST_DOUBLE rtx itself. */
839 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
844 /* Given an rtx X being reloaded into a reg required to be
845 in class CLASS, return the class of reg to actually use.
846 In general this is just CLASS; but on some machines
847 in some cases it is preferable to use a more restrictive class. */
849 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
851 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
852 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
853 || (CLASS) == DF_REGS) \
854 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
855 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
856 && GET_CODE (X) == REG \
857 && FP_REGISTER_P (REGNO (X)))) \
858 && MODE == SFmode) \
859 ? FPUL_REGS \
860 : ((CLASS) == FPUL_REGS \
861 && (GET_CODE (X) == MEM \
862 || (GET_CODE (X) == REG \
863 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
864 || REGNO (X) == T_REG \
865 || system_reg_operand (X, VOIDmode))))) \
866 ? GENERAL_REGS \
867 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
868 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
869 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
870 ? GENERAL_REGS : NO_REGS)
872 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
873 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
874 && immediate_operand ((X), (MODE)) \
875 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
876 && (MODE) == SFmode && fldi_ok ())) \
877 ? R0_REGS \
878 : (CLASS == FPUL_REGS \
879 && ((GET_CODE (X) == REG \
880 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
881 || REGNO (X) == T_REG)))) \
882 ? GENERAL_REGS \
883 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
884 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
885 ? GENERAL_REGS \
886 : R0_REGS) \
887 : (CLASS == FPSCR_REGS \
888 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
889 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
890 ? GENERAL_REGS \
891 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
893 /* Return the maximum number of consecutive registers
894 needed to represent mode MODE in a register of class CLASS.
896 On SH this is the size of MODE in words. */
897 #define CLASS_MAX_NREGS(CLASS, MODE) \
898 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
900 /* If defined, gives a class of registers that cannot be used as the
901 operand of a SUBREG that changes the mode of the object illegally. */
903 #define CLASS_CANNOT_CHANGE_MODE DF_REGS
905 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
907 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
908 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
909 \f
910 /* Stack layout; function entry, exit and calling. */
912 /* Define the number of registers that can hold parameters.
913 These macros are used only in other macro definitions below. */
915 #define NPARM_REGS(MODE) \
916 (TARGET_SH3E && (MODE) == SFmode \
917 ? 8 \
918 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
919 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
920 ? 8 \
921 : 4)
923 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
924 #define FIRST_RET_REG FIRST_GENERAL_REG
926 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
927 #define FIRST_FP_RET_REG FIRST_FP_REG
929 /* Define this if pushing a word on the stack
930 makes the stack pointer a smaller address. */
931 #define STACK_GROWS_DOWNWARD
933 /* Define this macro if the addresses of local variable slots are at
934 negative offsets from the frame pointer.
936 The SH only has positive indexes, so grow the frame up. */
937 /* #define FRAME_GROWS_DOWNWARD */
939 /* Offset from the frame pointer to the first local variable slot to
940 be allocated. */
941 #define STARTING_FRAME_OFFSET 0
943 /* If we generate an insn to push BYTES bytes,
944 this says how many the stack pointer really advances by. */
945 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
946 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
947 do correct alignment. */
948 #if 0
949 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
950 #endif
952 /* Offset of first parameter from the argument pointer register value. */
953 #define FIRST_PARM_OFFSET(FNDECL) 0
955 /* Value is the number of byte of arguments automatically
956 popped when returning from a subroutine call.
957 FUNDECL is the declaration node of the function (as a tree),
958 FUNTYPE is the data type of the function (as a tree),
959 or for a library call it is an identifier node for the subroutine name.
960 SIZE is the number of bytes of arguments passed on the stack.
962 On the SH, the caller does not pop any of its arguments that were passed
963 on the stack. */
964 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
966 /* Nonzero if we do not know how to pass TYPE solely in registers.
967 Values that come in registers with inconvenient padding are stored
968 to memory at the function start. */
970 #define MUST_PASS_IN_STACK(MODE,TYPE) \
971 ((TYPE) != 0 \
972 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
973 || TREE_ADDRESSABLE (TYPE)))
974 /* Some subroutine macros specific to this machine. */
976 #define BASE_RETURN_VALUE_REG(MODE) \
977 ((TARGET_SH3E && ((MODE) == SFmode)) \
978 ? FIRST_FP_RET_REG \
979 : TARGET_SH3E && (MODE) == SCmode \
980 ? FIRST_FP_RET_REG \
981 : (TARGET_SH4 \
982 && ((MODE) == DFmode || (MODE) == SFmode \
983 || (MODE) == DCmode || (MODE) == SCmode )) \
984 ? FIRST_FP_RET_REG \
985 : FIRST_RET_REG)
987 #define BASE_ARG_REG(MODE) \
988 ((TARGET_SH3E && ((MODE) == SFmode)) \
989 ? FIRST_FP_PARM_REG \
990 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
991 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
992 ? FIRST_FP_PARM_REG \
993 : FIRST_PARM_REG)
995 /* Define how to find the value returned by a function.
996 VALTYPE is the data type of the value (as a tree).
997 If the precise function being called is known, FUNC is its FUNCTION_DECL;
998 otherwise, FUNC is 0.
999 For the SH, this is like LIBCALL_VALUE, except that we must change the
1000 mode like PROMOTE_MODE does.
1001 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1002 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1004 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1005 gen_rtx (REG, \
1006 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1007 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1008 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1009 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1010 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1011 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1012 || TREE_CODE (VALTYPE) == REAL_TYPE \
1013 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1014 ? SImode : TYPE_MODE (VALTYPE)), \
1015 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1017 /* Define how to find the value returned by a library function
1018 assuming the value has mode MODE. */
1019 #define LIBCALL_VALUE(MODE) \
1020 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1022 /* 1 if N is a possible register number for a function value. */
1023 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1024 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
1026 /* 1 if N is a possible register number for function argument passing. */
1027 #define FUNCTION_ARG_REGNO_P(REGNO) \
1028 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
1029 || (TARGET_SH3E \
1030 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
1031 \f
1032 /* Define a data type for recording info about an argument list
1033 during the scan of that argument list. This data type should
1034 hold all necessary information about the function itself
1035 and about the args processed so far, enough to enable macros
1036 such as FUNCTION_ARG to determine where the next arg should go.
1038 On SH, this is a single integer, which is a number of words
1039 of arguments scanned so far (including the invisible argument,
1040 if any, which holds the structure-value-address).
1041 Thus NARGREGS or more means all following args should go on the stack. */
1047 };
1049 #define CUMULATIVE_ARGS struct sh_args
1051 #define GET_SH_ARG_CLASS(MODE) \
1052 ((TARGET_SH3E && (MODE) == SFmode) \
1053 ? SH_ARG_FLOAT \
1054 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1055 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1056 ? SH_ARG_FLOAT : SH_ARG_INT)
1058 #define ROUND_ADVANCE(SIZE) \
1059 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1061 /* Round a register number up to a proper boundary for an arg of mode
1062 MODE.
1064 The SH doesn't care about double alignment, so we only
1065 round doubles to even regs when asked to explicitly. */
1067 #define ROUND_REG(CUM, MODE) \
1068 (((TARGET_ALIGN_DOUBLE \
1069 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1070 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1071 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1072 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1073 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1074 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1076 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1077 for a call to a function whose data type is FNTYPE.
1078 For a library call, FNTYPE is 0.
1080 On SH, the offset always starts at 0: the first parm reg is always
1081 the same reg for a given argument class.
1083 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1085 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1086 do { \
1087 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1088 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1089 (CUM).force_mem \
1090 = (TARGET_HITACHI && FNTYPE \
1091 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1092 } while (0)
1094 /* Update the data in CUM to advance over an argument
1095 of mode MODE and data type TYPE.
1096 (TYPE is null for libcalls where that information may not be
1097 available.) */
1099 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1100 if ((CUM).force_mem) \
1101 (CUM).force_mem = 0; \
1102 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1103 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1104 = (ROUND_REG ((CUM), (MODE)) \
1105 + ((MODE) == BLKmode \
1106 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1107 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1109 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1110 This macro is only used in this file. */
1112 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1113 (((TYPE) == 0 \
1114 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1115 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1116 && ! (CUM).force_mem \
1117 && (TARGET_SH3E \
1118 ? ((MODE) == BLKmode \
1119 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1120 + int_size_in_bytes (TYPE)) \
1121 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1122 : ((ROUND_REG((CUM), (MODE)) \
1123 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1124 <= NPARM_REGS (MODE))) \
1125 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1127 /* Define where to put the arguments to a function.
1128 Value is zero to push the argument on the stack,
1129 or a hard register in which to store the argument.
1131 MODE is the argument's machine mode.
1132 TYPE is the data type of the argument (as a tree).
1133 This is null for libcalls where that information may
1134 not be available.
1135 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1136 the preceding args and about the function being called.
1137 NAMED is nonzero if this argument is a named parameter
1138 (otherwise it is an extra parameter matching an ellipsis).
1140 On SH the first args are normally in registers
1141 and the rest are pushed. Any arg that starts within the first
1142 NPARM_REGS words is at least partially passed in a register unless
1143 its data type forbids. */
1145 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1146 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1147 && ((NAMED) \
1148 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1149 ? gen_rtx_REG ((MODE), \
1150 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1151 ^ ((MODE) == SFmode && TARGET_SH4 \
1152 && TARGET_LITTLE_ENDIAN != 0))) \
1153 : 0)
1155 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI)
1157 /* For an arg passed partly in registers and partly in memory,
1158 this is the number of registers used.
1159 For args passed entirely in registers or entirely in memory, zero.
1161 We sometimes split args. */
1163 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1164 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1165 && ! TARGET_SH4 \
1166 && (ROUND_REG ((CUM), (MODE)) \
1167 + ((MODE) != BLKmode \
1168 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1169 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1170 > NPARM_REGS (MODE))) \
1171 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1172 : 0)
1176 /* Perform any needed actions needed for a function that is receiving a
1177 variable number of arguments. */
1179 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
1180 current_function_anonymous_args = 1;
1182 /* Define the `__builtin_va_list' type for the ABI. */
1183 #define BUILD_VA_LIST_TYPE(VALIST) \
1184 (VALIST) = sh_build_va_list ()
1186 /* Implement `va_start' for varargs and stdarg. */
1187 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1188 sh_va_start (stdarg, valist, nextarg)
1190 /* Implement `va_arg'. */
1191 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1192 sh_va_arg (valist, type)
1194 /* Call the function profiler with a given profile label.
1195 We use two .aligns, so as to make sure that both the .long is aligned
1196 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1197 from the trapa instruction. */
1199 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1200 { \
1205 }
1207 /* Define this macro if the code for function profiling should come
1208 before the function prologue. Normally, the profiling code comes
1209 after. */
1211 #define PROFILE_BEFORE_PROLOGUE
1213 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1214 the stack pointer does not matter. The value is tested only in
1215 functions that have frame pointers.
1216 No definition is equivalent to always zero. */
1218 #define EXIT_IGNORE_STACK 1
1220 /*
1221 On the SH, the trampoline looks like
1222 2 0002 D202 mov.l l2,r2
1223 1 0000 D301 mov.l l1,r3
1224 3 0004 422B jmp @r2
1225 4 0006 0009 nop
1226 5 0008 00000000 l1: .long area
1227 6 000c 00000000 l2: .long function */
1229 /* Length in units of the trampoline for entering a nested function. */
1230 #define TRAMPOLINE_SIZE 16
1232 /* Alignment required for a trampoline in bits . */
1233 #define TRAMPOLINE_ALIGNMENT \
1234 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
1236 /* Emit RTL insns to initialize the variable parts of a trampoline.
1237 FNADDR is an RTX for the address of the function's pure code.
1238 CXT is an RTX for the static chain value for the function. */
1240 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) do \
1241 { \
1242 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
1243 GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301));\
1244 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
1245 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009));\
1246 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1247 (CXT)); \
1248 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1249 (FNADDR)); \
1250 if (TARGET_HARVARD) \
1251 { \
1252 if (TARGET_USERMODE) \
1254 0, VOIDmode, 1, (TRAMP), SImode); \
1255 else \
1256 emit_insn (gen_ic_invalidate_line (TRAMP)); \
1257 } \
1258 } while (0)
1260 /* A C expression whose value is RTL representing the value of the return
1261 address for the frame COUNT steps up from the current frame.
1262 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1263 can ignore COUNT. */
1265 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1266 (((COUNT) == 0) \
1267 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
1268 : (rtx) 0)
1269 \f
1270 /* Generate necessary RTL for __builtin_saveregs(). */
1271 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
1272 \f
1273 /* Addressing modes, and classification of registers for them. */
1274 #define HAVE_POST_INCREMENT 1
1275 /*#define HAVE_PRE_INCREMENT 1*/
1276 /*#define HAVE_POST_DECREMENT 1*/
1277 #define HAVE_PRE_DECREMENT 1
1279 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1280 ? 0 : 1)
1281 #define USE_LOAD_PRE_DECREMENT(mode) 0
1282 #define USE_STORE_POST_INCREMENT(mode) 0
1283 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1284 ? 0 : 1)
1286 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
1287 < (TARGET_SMALLCODE ? 2 : \
1288 ((ALIGN >= 32) ? 16 : 2)))
1290 /* Macros to check register numbers against specific register classes. */
1292 /* These assume that REGNO is a hard or pseudo reg number.
1293 They give nonzero only if REGNO is a hard reg of the suitable class
1294 or a pseudo reg currently allocated to a suitable hard reg.
1295 Since they use reg_renumber, they are safe only once reg_renumber
1296 has been allocated, which happens in local-alloc.c. */
1298 #define REGNO_OK_FOR_BASE_P(REGNO) \
1299 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1300 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1301 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1302 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1304 /* Maximum number of registers that can appear in a valid memory
1305 address. */
1307 #define MAX_REGS_PER_ADDRESS 2
1309 /* Recognize any constant value that is a valid address. */
1311 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1313 /* Nonzero if the constant value X is a legitimate general operand. */
1315 #define LEGITIMATE_CONSTANT_P(X) \
1316 (GET_CODE (X) != CONST_DOUBLE \
1317 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1318 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
1320 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1321 and check its validity for a certain class.
1322 We have two alternate definitions for each of them.
1323 The usual definition accepts all pseudo regs; the other rejects
1324 them unless they have been allocated suitable hard regs.
1325 The symbol REG_OK_STRICT causes the latter definition to be used. */
1327 #ifndef REG_OK_STRICT
1329 /* Nonzero if X is a hard reg that can be used as a base reg
1330 or if it is a pseudo reg. */
1331 #define REG_OK_FOR_BASE_P(X) \
1332 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1334 /* Nonzero if X is a hard reg that can be used as an index
1335 or if it is a pseudo reg. */
1336 #define REG_OK_FOR_INDEX_P(X) \
1337 (REGNO (X) == R0_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1339 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
1340 or if X is a pseudo reg. */
1341 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1342 ((REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1344 #else
1346 /* Nonzero if X is a hard reg that can be used as a base reg. */
1347 #define REG_OK_FOR_BASE_P(X) \
1348 REGNO_OK_FOR_BASE_P (REGNO (X))
1350 /* Nonzero if X is a hard reg that can be used as an index. */
1351 #define REG_OK_FOR_INDEX_P(X) \
1352 REGNO_OK_FOR_INDEX_P (REGNO (X))
1354 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
1355 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1356 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
1358 #endif
1360 /* The 'Q' constraint is a pc relative load operand. */
1361 #define EXTRA_CONSTRAINT_Q(OP) \
1362 (GET_CODE (OP) == MEM \
1363 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
1364 || (GET_CODE (XEXP ((OP), 0)) == CONST \
1365 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
1366 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
1367 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
1369 #define EXTRA_CONSTRAINT(OP, C) \
1371 : 0)
1372 \f
1373 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1374 that is a valid memory address for an instruction.
1375 The MODE argument is the machine mode for the MEM expression
1376 that wants to use this address. */
1378 #define MODE_DISP_OK_4(X,MODE) \
1379 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1380 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
1382 #define MODE_DISP_OK_8(X,MODE) \
1383 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
1384 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
1386 #define BASE_REGISTER_RTX_P(X) \
1387 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1388 || (GET_CODE (X) == SUBREG \
1389 && GET_CODE (SUBREG_REG (X)) == REG \
1390 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1392 /* Since this must be r0, which is a single register class, we must check
1393 SUBREGs more carefully, to be sure that we don't accept one that extends
1394 outside the class. */
1395 #define INDEX_REGISTER_RTX_P(X) \
1396 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1397 || (GET_CODE (X) == SUBREG \
1398 && GET_CODE (SUBREG_REG (X)) == REG \
1399 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
1401 /* Jump to LABEL if X is a valid address RTX. This must also take
1402 REG_OK_STRICT into account when deciding about valid registers, but it uses
1403 the above macros so we are in luck.
1405 Allow REG
1406 REG+disp
1407 REG+r0
1408 REG++
1409 --REG */
1411 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1412 into the FRx registers. We implement this by setting the maximum offset
1413 to zero when the value is SFmode. This also restricts loading of SFmode
1414 values into the integer registers, but that can't be helped. */
1416 /* The SH allows a displacement in a QI or HI amode, but only when the
1417 other operand is R0. GCC doesn't handle this very well, so we forgo
1418 all of that.
1420 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1421 DI can be any number 0..60. */
1423 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1424 do { \
1425 if (GET_CODE (OP) == CONST_INT) \
1426 { \
1427 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
1428 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
1429 } \
1430 } while(0)
1432 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1433 { \
1434 if (BASE_REGISTER_RTX_P (X)) \
1435 goto LABEL; \
1436 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1437 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
1438 goto LABEL; \
1439 else if (GET_CODE (X) == PLUS \
1440 && ((MODE) != PSImode || reload_completed)) \
1441 { \
1442 rtx xop0 = XEXP ((X), 0); \
1443 rtx xop1 = XEXP ((X), 1); \
1444 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1445 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
1446 if (GET_MODE_SIZE (MODE) <= 4 \
1447 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
1448 { \
1449 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1450 goto LABEL; \
1451 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1452 goto LABEL; \
1453 } \
1454 } \
1455 }
1456 \f
1457 /* Try machine-dependent ways of modifying an illegitimate address
1458 to be legitimate. If we find one, return the new, valid address.
1459 This macro is used in only one place: `memory_address' in explow.c.
1461 OLDX is the address as it was before break_out_memory_refs was called.
1462 In some cases it is useful to look at this to decide what needs to be done.
1464 MODE and WIN are passed so that this macro can use
1465 GO_IF_LEGITIMATE_ADDRESS.
1467 It is always safe for this macro to do nothing. It exists to recognize
1468 opportunities to optimize the output.
1470 For the SH, if X is almost suitable for indexing, but the offset is
1471 out of range, convert it into a normal form so that cse has a chance
1472 of reducing the number of address registers used. */
1474 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1475 { \
1476 if (flag_pic) \
1477 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1478 if (GET_CODE (X) == PLUS \
1479 && (GET_MODE_SIZE (MODE) == 4 \
1480 || GET_MODE_SIZE (MODE) == 8) \
1481 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
1482 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
1483 && ! (TARGET_SH4 && (MODE) == DFmode) \
1484 && ! (TARGET_SH3E && (MODE) == SFmode)) \
1485 { \
1486 rtx index_rtx = XEXP ((X), 1); \
1487 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1488 rtx sum; \
1489 \
1490 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
1491 /* On rare occasions, we might get an unaligned pointer \
1492 that is indexed in a way to give an aligned address. \
1494 /* Instead of offset_base 128..131 use 124..127, so that \
1496 if (offset > 127) \
1497 { \
1498 offset_base = ((offset + 4) & ~60) - 4; \
1499 } \
1500 else \
1501 offset_base = offset & ~60; \
1502 /* Sometimes the normal form does not suit DImode. We \
1503 could avoid that by using smaller ranges, but that \
1504 would give less optimized code when SImode is \
1506 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1507 { \
1508 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
1509 GEN_INT (offset_base), NULL_RTX, 0, \
1510 OPTAB_LIB_WIDEN); \
1511 \
1512 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
1513 goto WIN; \
1514 } \
1515 } \
1516 }
1518 /* A C compound statement that attempts to replace X, which is an address
1519 that needs reloading, with a valid memory address for an operand of
1520 mode MODE. WIN is a C statement label elsewhere in the code.
1522 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
1523 of the address. That will allow inheritance of the address reloads. */
1525 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1526 { \
1527 if (GET_CODE (X) == PLUS \
1528 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1529 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1530 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1531 && ! (TARGET_SH4 && (MODE) == DFmode) \
1532 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
1533 { \
1534 rtx index_rtx = XEXP (X, 1); \
1535 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1536 rtx sum; \
1537 \
1538 if (TARGET_SH3E && MODE == SFmode) \
1539 { \
1540 X = copy_rtx (X); \
1541 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
1542 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1543 (TYPE)); \
1544 goto WIN; \
1545 } \
1546 /* Instead of offset_base 128..131 use 124..127, so that \
1548 if (offset > 127) \
1549 { \
1550 offset_base = ((offset + 4) & ~60) - 4; \
1551 } \
1552 else \
1553 offset_base = offset & ~60; \
1554 /* Sometimes the normal form does not suit DImode. We \
1555 could avoid that by using smaller ranges, but that \
1556 would give less optimized code when SImode is \
1558 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1559 { \
1560 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1561 GEN_INT (offset_base)); \
1562 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
1563 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
1564 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1565 (TYPE)); \
1566 goto WIN; \
1567 } \
1568 } \
1570 else if (GET_CODE (X) == PLUS \
1571 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1572 && GET_CODE (XEXP (X, 0)) == PLUS \
1573 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1574 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
1575 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1576 && ! (TARGET_SH3E && MODE == SFmode)) \
1577 { \
1578 /* Because this address is so complex, we know it must have \
1579 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
1581 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
1582 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
1583 goto WIN; \
1584 } \
1585 }
1587 /* Go to LABEL if ADDR (a legitimate address expression)
1588 has an effect that depends on the machine mode it is used for.
1590 ??? Strictly speaking, we should also include all indexed addressing,
1591 because the index scale factor is the length of the operand.
1592 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
1593 high if we did that. So we rely on reload to fix things up. */
1595 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1596 { \
1597 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1598 goto LABEL; \
1599 }
1600 \f
1601 /* Specify the machine mode that this machine uses
1602 for the index in the tablejump instruction. */
1603 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1605 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1606 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1607 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1608 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1609 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1610 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1611 : SImode)
1613 /* Define as C expression which evaluates to nonzero if the tablejump
1614 instruction expects the table to contain offsets from the address of the
1615 table.
1616 Do not define this if the table should contain absolute addresses. */
1617 #define CASE_VECTOR_PC_RELATIVE 1
1619 /* Specify the tree operation to be used to convert reals to integers. */
1620 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1622 /* This is the kind of divide that is easiest to do in the general case. */
1623 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1625 /* Since the SH3e has only `float' support, it is desirable to make all
1626 floating point types equivalent to `float'. */
1627 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
1629 /* 'char' is signed by default. */
1630 #define DEFAULT_SIGNED_CHAR 1
1632 /* The type of size_t unsigned int. */
1636 #define WCHAR_TYPE_SIZE 16
1638 /* Don't cse the address of the function being compiled. */
1639 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1641 /* Max number of bytes we can move from memory to memory
1642 in one reasonably fast instruction. */
1643 #define MOVE_MAX 4
1645 /* Max number of bytes we want move_by_pieces to be able to copy
1646 efficiently. */
1647 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1649 /* Define if operations between registers always perform the operation
1650 on the full register even if a narrower mode is specified. */
1651 #define WORD_REGISTER_OPERATIONS
1653 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1654 will either zero-extend or sign-extend. The value of this macro should
1655 be the code that says which one of the two operations is implicitly
1656 done, NIL if none. */
1657 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1659 /* Define if loading short immediate values into registers sign extends. */
1660 #define SHORT_IMMEDIATES_SIGN_EXTEND
1662 /* Define this if zero-extension is slow (more than one real instruction).
1663 On the SH, it's only one instruction. */
1664 /* #define SLOW_ZERO_EXTEND */
1666 /* Nonzero if access to memory by bytes is no faster than for words. */
1667 #define SLOW_BYTE_ACCESS 1
1669 /* We assume that the store-condition-codes instructions store 0 for false
1670 and some other value for true. This is the value stored for true. */
1672 #define STORE_FLAG_VALUE 1
1674 /* Immediate shift counts are truncated by the output routines (or was it
1675 the assembler?). Shift counts in a register are truncated by SH. Note
1676 that the native compiler puts too large (> 32) immediate shift counts
1677 into a register and shifts by the register, letting the SH decide what
1678 to do instead of doing that itself. */
1679 /* ??? The library routines in lib1funcs.asm truncate the shift count.
1680 However, the SH3 has hardware shifts that do not truncate exactly as gcc
1681 expects - the sign bit is significant - so it appears that we need to
1682 leave this zero for correct SH3 code. */
1683 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
1685 /* All integers have the same format so truncation is easy. */
1686 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1688 /* Define this if addresses of constant functions
1689 shouldn't be put through pseudo regs where they can be cse'd.
1690 Desirable on machines where ordinary constants are expensive
1691 but a CALL with constant address is cheap. */
1692 /*#define NO_FUNCTION_CSE 1*/
1694 /* Chars and shorts should be passed as ints. */
1695 #define PROMOTE_PROTOTYPES 1
1697 /* The machine modes of pointers and functions. */
1698 #define Pmode SImode
1699 #define FUNCTION_MODE Pmode
1701 /* The relative costs of various types of constants. */
1703 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1704 case CONST_INT: \
1705 if (CONST_OK_FOR_I (INTVAL (RTX))) \
1706 return 0; \
1707 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
1708 && CONST_OK_FOR_L (INTVAL (RTX))) \
1709 return 1; \
1710 else \
1711 return 8; \
1712 case CONST: \
1713 case LABEL_REF: \
1714 case SYMBOL_REF: \
1715 return 5; \
1716 case CONST_DOUBLE: \
1717 return 10;
1719 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1720 case PLUS: \
1721 return COSTS_N_INSNS (addsubcosts (X)); \
1722 case AND: \
1723 return COSTS_N_INSNS (andcosts (X)); \
1724 case MULT: \
1725 return COSTS_N_INSNS (multcosts (X)); \
1726 case ASHIFT: \
1727 case ASHIFTRT: \
1728 case LSHIFTRT: \
1729 return COSTS_N_INSNS (shiftcosts (X)); \
1730 case DIV: \
1731 case UDIV: \
1732 case MOD: \
1733 case UMOD: \
1734 return COSTS_N_INSNS (20); \
1735 case FLOAT: \
1736 case FIX: \
1737 return 100;
1739 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1740 are actually function calls with some special constraints on arguments
1741 and register usage.
1743 These macros tell reorg that the references to arguments and
1744 register clobbers for insns of type sfunc do not appear to happen
1745 until after the millicode call. This allows reorg to put insns
1746 which set the argument registers into the delay slot of the millicode
1747 call -- thus they act more like traditional CALL_INSNs.
1749 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1750 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1751 in particular. */
1753 #define INSN_SETS_ARE_DELAYED(X) \
1754 ((GET_CODE (X) == INSN \
1755 && GET_CODE (PATTERN (X)) != SEQUENCE \
1756 && GET_CODE (PATTERN (X)) != USE \
1757 && GET_CODE (PATTERN (X)) != CLOBBER \
1758 && get_attr_is_sfunc (X)))
1760 #define INSN_REFERENCES_ARE_DELAYED(X) \
1761 ((GET_CODE (X) == INSN \
1762 && GET_CODE (PATTERN (X)) != SEQUENCE \
1763 && GET_CODE (PATTERN (X)) != USE \
1764 && GET_CODE (PATTERN (X)) != CLOBBER \
1765 && get_attr_is_sfunc (X)))
1767 \f
1768 /* Position Independent Code. */
1769 /* Define this macro if references to a symbol must be treated
1770 differently depending on something about the variable or function
1771 named by the symbol (such as what section it is in).
1773 On SH, if using PIC, mark a SYMBOL_REF for a non-global symbol
1774 so that we may access it using GOTOFF instead of GOT. */
1776 #define ENCODE_SECTION_INFO(DECL) \
1777 do \
1778 { \
1779 if (flag_pic) \
1780 { \
1782 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
1783 \
1784 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = \
1786 || ! TREE_PUBLIC (DECL)); \
1787 } \
1788 } \
1789 while (0)
1791 /* We can't directly access anything that contains a symbol,
1792 nor can we indirect via the constant pool. */
1793 #define LEGITIMATE_PIC_OPERAND_P(X) \
1794 (! nonpic_symbol_mentioned_p (X) \
1795 && (! CONSTANT_POOL_ADDRESS_P (X) \
1796 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
1798 #define SYMBOLIC_CONST_P(X) \
1799 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1800 && nonpic_symbol_mentioned_p (X))
1801 \f
1802 /* Compute the cost of an address. For the SH, all valid addresses are
1803 the same cost. Use a slightly higher cost for reg + reg addressing,
1804 since it increases pressure on r0. */
1806 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
1807 ? 1 : 0)
1809 /* Compute extra cost of moving data between one register class
1810 and another. */
1812 /* Regclass always uses 2 for moves in the same register class;
1813 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
1814 it uses this information. Hence, the general register <-> floating point
1815 register information here is not used for SFmode. */
1816 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
1817 ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
1818 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
1819 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1820 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
1821 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
1822 || (SRCCLASS) == DF_REGS))) \
1823 ? TARGET_FMOVD ? 8 : 12 \
1824 : (((DSTCLASS) == FPUL_REGS \
1825 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1826 || (SRCCLASS == FPUL_REGS \
1827 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
1828 ? 5 \
1829 : (((DSTCLASS) == FPUL_REGS \
1830 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
1831 || (SRCCLASS) == T_REGS)) \
1832 || ((SRCCLASS) == FPUL_REGS \
1833 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
1834 ? 7 \
1835 : 2)
1837 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1838 would be so that people with slow memory systems could generate
1839 different code that does fewer memory accesses. */
1841 /* A C expression for the cost of a branch instruction. A value of 1
1842 is the default; other values are interpreted relative to that.
1843 The SH1 does not have delay slots, hence we get a pipeline stall
1844 at every branch. The SH4 is superscalar, so the single delay slot
1845 is not sufficient to keep both pipelines filled. */
1846 #define BRANCH_COST (! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
1847 \f
1848 /* Assembler output control. */
1850 /* A C string constant describing how to begin a comment in the target
1851 assembler language. The compiler assumes that the comment will end at
1852 the end of the line. */
1855 /* The text to go at the start of the assembler file. */
1856 #define ASM_FILE_START(STREAM) \
1857 output_file_start (STREAM)
1859 #define ASM_FILE_END(STREAM)
1867 /* How to change between sections. */
1873 #define EXTRA_SECTIONS in_ctors, in_dtors
1874 #define EXTRA_SECTION_FUNCTIONS \
1875 void \
1876 ctors_section() \
1877 { \
1878 if (in_section != in_ctors) \
1879 { \
1881 in_section = in_ctors; \
1882 } \
1883 } \
1884 void \
1885 dtors_section() \
1886 { \
1887 if (in_section != in_dtors) \
1888 { \
1890 in_section = in_dtors; \
1891 } \
1892 }
1894 /* If defined, a C expression whose value is a string containing the
1895 assembler operation to identify the following data as
1896 uninitialized global data. If not defined, and neither
1897 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
1898 uninitialized global data will be output in the data section if
1899 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
1900 used. */
1901 #ifndef BSS_SECTION_ASM_OP
1903 #endif
1905 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1906 separate, explicit argument. If you define this macro, it is used
1907 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1908 handling the required alignment of the variable. The alignment is
1909 specified as the number of bits.
1911 Try to use function `asm_output_aligned_bss' defined in file
1912 `varasm.c' when defining this macro. */
1913 #ifndef ASM_OUTPUT_ALIGNED_BSS
1914 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1915 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1916 #endif
1918 /* Define this so that jump tables go in same section as the current function,
1919 which could be text or it could be a user defined section. */
1920 #define JUMP_TABLES_IN_TEXT_SECTION 1
1922 /* A C statement to output something to the assembler file to switch to section
1923 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1924 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1925 define this macro in such cases. */
1927 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1930 /* This is the pseudo-op used to generate a reference to a specific
1931 symbol in some section. */
1935 /* A C statement (sans semicolon) to output an
1936 element in the table of global constructors. */
1937 #define ASM_OUTPUT_CONSTRUCTOR(FILE, NAME) \
1938 do \
1939 { \
1940 ctors_section (); \
1942 assemble_name (FILE, NAME); \
1944 } \
1945 while (0)
1947 /* A C statement (sans semicolon) to output an
1948 element in the table of global destructors. */
1949 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1950 do \
1951 { \
1952 dtors_section (); \
1954 assemble_name (FILE, NAME); \
1956 } \
1957 while (0)
1959 #undef DO_GLOBAL_CTORS_BODY
1961 #define DO_GLOBAL_CTORS_BODY \
1962 { \
1963 typedef (*pfunc)(); \
1964 extern pfunc __ctors[]; \
1965 extern pfunc __ctors_end[]; \
1966 pfunc *p; \
1967 for (p = __ctors_end; p > __ctors; ) \
1968 { \
1969 (*--p)(); \
1970 } \
1971 }
1973 #undef DO_GLOBAL_DTORS_BODY
1974 #define DO_GLOBAL_DTORS_BODY \
1975 { \
1976 typedef (*pfunc)(); \
1977 extern pfunc __dtors[]; \
1978 extern pfunc __dtors_end[]; \
1979 pfunc *p; \
1980 for (p = __dtors; p < __dtors_end; p++) \
1981 { \
1982 (*p)(); \
1983 } \
1984 }
1986 #define ASM_OUTPUT_REG_PUSH(file, v) \
1989 #define ASM_OUTPUT_REG_POP(file, v) \
1992 /* The assembler's names for the registers. RFP need not always be used as
1993 the Real framepointer; it can also be used as a normal general register.
1994 Note that the name `fp' is horribly misleading since `fp' is in fact only
1995 the argument-and-return-context pointer. */
1999 #define REGISTER_NAMES \
2000 { \
2004 fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \
2005 fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \
2006 fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \
2007 fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \
2008 fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \
2009 fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \
2011 }
2013 #define DEBUG_REGISTER_NAMES \
2014 { \
2022 }
2024 /* DBX register number for a given compiler register number. */
2025 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2026 to match gdb. */
2027 #define DBX_REGISTER_NUMBER(REGNO) \
2028 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
2030 /* Output a label definition. */
2031 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2034 /* This is how to output an assembler line
2035 that says to advance the location counter
2036 to a multiple of 2**LOG bytes. */
2038 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2039 if ((LOG) != 0) \
2042 /* Output a function label definition. */
2043 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
2044 ASM_OUTPUT_LABEL((STREAM), (NAME))
2046 /* Output a globalising directive for a label. */
2047 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2049 assemble_name ((STREAM), (NAME)), \
2052 /* The prefix to add to user-visible assembler symbols. */
2056 /* The prefix to add to an internally generated label. */
2060 /* Make an internal label into a string. */
2061 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
2064 /* Output an internal label definition. */
2065 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2068 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2070 /* Construct a private name. */
2071 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
2072 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
2075 /* Output a relative address table. */
2077 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2078 switch (GET_MODE (BODY)) \
2079 { \
2080 case SImode: \
2082 break; \
2083 case HImode: \
2085 break; \
2086 case QImode: \
2088 break; \
2089 default: \
2090 break; \
2091 }
2093 /* Output an absolute table element. */
2095 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2096 if (TARGET_BIGTABLE) \
2098 else \
2101 /* Output various types of constants. */
2103 /* This is how to output an assembler line defining a `double'. */
2105 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2106 do { char dstr[30]; \
2109 } while (0)
2111 /* This is how to output an assembler line defining a `float' constant. */
2112 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2113 do { char dstr[30]; \
2116 } while (0)
2118 #define ASM_OUTPUT_INT(STREAM, EXP) \
2120 output_addr_const ((STREAM), (EXP)), \
2123 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
2125 output_addr_const ((STREAM), (EXP)), \
2128 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
2130 output_addr_const ((STREAM), (EXP)), \
2133 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
2136 /* The next two are used for debug info when compiling with -gdwarf. */
2140 /* Loop alignment is now done in machine_dependent_reorg, so that
2141 branch shortening can know about it. */
2143 /* This is how to output an assembler line
2144 that says to advance the location counter by SIZE bytes. */
2146 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2149 /* This says how to output an assembler line
2150 to define a global common symbol. */
2152 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2154 assemble_name ((FILE), (NAME)), \
2157 /* This says how to output an assembler line
2158 to define a local common symbol. */
2160 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2162 assemble_name ((FILE), (NAME)), \
2165 /* The assembler's parentheses characters. */
2168 \f
2169 /* A C statement to be executed just prior to the output of
2170 assembler code for INSN, to modify the extracted operands so
2171 they will be output differently.
2173 Here the argument OPVEC is the vector containing the operands
2174 extracted from INSN, and NOPERANDS is the number of elements of
2175 the vector which contain meaningful data for this insn.
2176 The contents of this vector are what will be used to convert the insn
2177 template into assembler code, so you can change the assembler output
2178 by changing the contents of the vector. */
2180 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2181 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2183 /* Print operand X (an rtx) in assembler syntax to file FILE.
2184 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2185 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2187 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2189 /* Print a memory address as an operand to reference that memory location. */
2191 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2193 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2197 /* Recognize machine-specific patterns that may appear within
2198 constants. Used for PIC-specific UNSPECs. */
2199 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2200 do \
2201 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
2202 { \
2203 switch (XINT ((X), 1)) \
2204 { \
2205 case UNSPEC_PIC: \
2207 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2208 break; \
2209 case UNSPEC_GOT: \
2210 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2212 break; \
2213 case UNSPEC_GOTOFF: \
2214 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2216 break; \
2217 case UNSPEC_PLT: \
2218 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2220 break; \
2221 case UNSPEC_CALLER: \
2222 { \
2223 char name[32]; \
2225 ASM_GENERATE_INTERNAL_LABEL \
2227 assemble_name ((STREAM), name); \
2228 } \
2229 break; \
2230 default: \
2231 goto FAIL; \
2232 } \
2233 break; \
2234 } \
2235 else \
2236 goto FAIL; \
2237 while (0)
2239 \f
2243 /* Which processor to schedule for. The elements of the enumeration must
2244 match exactly the cpu attribute in the sh.md file. */
2247 PROCESSOR_SH1,
2248 PROCESSOR_SH2,
2249 PROCESSOR_SH3,
2250 PROCESSOR_SH3E,
2251 PROCESSOR_SH4
2252 };
2254 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2259 enum mdep_reorg_phase_e
2260 {
2261 SH_BEFORE_MDEP_REORG,
2262 SH_INSERT_USES_LABELS,
2263 SH_SHORTEN_BRANCHES0,
2264 SH_FIXUP_PCLOAD,
2265 SH_SHORTEN_BRANCHES1,
2266 SH_AFTER_MDEP_REORG
2267 };
2271 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
2273 /* Generate calls to memcpy, memcmp and memset. */
2275 #define TARGET_MEM_FUNCTIONS
2277 /* Handle Hitachi compiler's pragmas. */
2278 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2282 } while (0)
2284 /* Set when processing a function with pragma interrupt turned on. */
2288 /* Set when processing a function with interrupt attribute. */
2292 /* Set to an RTX containing the address of the stack to switch to
2293 for interrupt functions. */
2296 #define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \
2297 sh_pragma_insert_attributes (node, pattr, prefix_attr)
2302 \f
2303 /* Instructions with unfilled delay slots take up an
2304 extra two bytes for the nop in the delay slot.
2305 sh-dsp parallel processing insns are four bytes long. */
2307 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2308 (LENGTH) += sh_insn_length_adjustment (X);
2309 \f
2310 /* Define the codes that are matched by predicates in sh.c. */
2311 #define PREDICATE_CODES \
2327 /* Define this macro if it is advisable to hold scalars in registers
2328 in a wider mode than that declared by the program. In such cases,
2329 the value is constrained to be within the bounds of the declared
2330 type, but kept valid in the wider mode. The signedness of the
2331 extension may differ from that of the type.
2333 Leaving the unsignedp unchanged gives better code than always setting it
2334 to 0. This is despite the fact that we have only signed char and short
2335 load instructions. */
2336 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2337 if (GET_MODE_CLASS (MODE) == MODE_INT \
2338 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
2339 (MODE) = SImode;
2341 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
2342 extensions applied to char/short functions arguments. Defining
2343 PROMOTE_FUNCTION_RETURN does the same for function returns. */
2345 #define PROMOTE_FUNCTION_ARGS
2346 #define PROMOTE_FUNCTION_RETURN
2348 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2349 and poping arguments. However, we do have push/pop instructions, and
2350 rather limited offsets (4 bits) in load/store instructions, so it isn't
2351 clear if this would give better code. If implemented, should check for
2352 compatibility problems. */
2354 /* A C statement (sans semicolon) to update the integer variable COST
2355 based on the relationship between INSN that is dependent on
2356 DEP_INSN through the dependence LINK. The default is to make no
2357 adjustment to COST. This can be used for example to specify to
2358 the scheduler that an output- or anti-dependence does not incur
2359 the same cost as a data-dependence. */
2361 #define ADJUST_COST(insn,link,dep_insn,cost) \
2362 do { \
2363 rtx reg; \
2364 \
2365 if (GET_CODE(insn) == CALL_INSN) \
2366 { \
2367 /* The only input for a call that is timing-critical is the \
2369 rtx call = PATTERN (insn); \
2370 \
2371 if (GET_CODE (call) == PARALLEL) \
2372 call = XVECEXP (call, 0 ,0); \
2373 if (GET_CODE (call) == SET) \
2374 call = SET_SRC (call); \
2375 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \
2376 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \
2377 (cost) = 0; \
2378 } \
2379 /* All sfunc calls are parallels with at least four components. \
2381 else if (GET_CODE (PATTERN (insn)) == PARALLEL \
2382 && XVECLEN (PATTERN (insn), 0) >= 4 \
2383 && (reg = sfunc_uses_reg (insn))) \
2384 { \
2385 /* Likewise, the most timing critical input for an sfuncs call \
2386 is the function address. However, sfuncs typically start \
2387 using their arguments pretty quickly. \
2389 if (! reg_set_p (reg, dep_insn)) \
2390 cost -= TARGET_SUPERSCALAR ? 40 : 4; \
2391 } \
2392 /* Adjust load_si / pcload_si type insns latency. Use the known \
2394 else if (cost == 3 \
2395 && GET_CODE (PATTERN (dep_insn)) == SET \
2396 /* Latency for dmpy type insns is also 3, so check the that \
2398 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\
2399 cost = 2; \
2400 else if (cost == 30 \
2401 && GET_CODE (PATTERN (dep_insn)) == SET \
2402 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) \
2403 cost = 20; \
2404 } while (0) \
2406 #define SH_DYNAMIC_SHIFT_COST \
2407 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2410 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2412 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
2414 #define NORMAL_MODE(ENTITY) \
2415 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2417 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
2418 && (REGNO) == FPSCR_REG)
2420 #define MODE_NEEDED(ENTITY, INSN) \
2421 (recog_memoized (INSN) >= 0 \
2422 ? get_attr_fp_mode (INSN) \
2423 : FP_MODE_NONE)
2425 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2426 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2428 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2429 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2431 #define DWARF_LINE_MIN_INSTR_LENGTH 2
2433 /* SH constant pool breaks the devices in crtstuff.c to control section
2434 in where code resides. We have to write it as asm code. */
2435 #define CRT_CALL_STATIC_FUNCTION(func) \
2436 if (0) \
2438 func (); \
2439 else \
2440 /* We should be passing FUNC to the asm statement as an asm input \
2442 asm \