gcc/config/mips/mips.c

   1 /* Subroutines for insn-output.c for MIPS
   2    Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001 Free Software Foundation, Inc.
   4    Contributed by A. Lichnewsky, lich@inria.inria.fr.
   5    Changes by Michael Meissner, meissner@osf.org.
   6    64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
   7    Brendan Eich, brendan@microunity.com.
   8
   9 This file is part of GNU CC.
  10
  11 GNU CC is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 GNU CC is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with GNU CC; see the file COPYING.  If not, write to
  23 the Free Software Foundation, 59 Temple Place - Suite 330,
  24 Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
  27    calling convention in 64 bit mode.  It doesn't work though, and should
  28    be replaced with something better designed.  */
  29
  30 #include "config.h"
  31 #include "system.h"
  32 #include <signal.h>
  33 #include "rtl.h"
  34 #include "regs.h"
  35 #include "hard-reg-set.h"
  36 #include "real.h"
  37 #include "insn-config.h"
  38 #include "conditions.h"
  39 #include "insn-attr.h"
  40 #include "recog.h"
  41 #include "toplev.h"
  42 #include "output.h"
  43
  44 #include "tree.h"
  45 #include "function.h"
  46 #include "expr.h"
  47 #include "flags.h"
  48 #include "reload.h"
  49 #include "output.h"
  50 #include "tm_p.h"
  51 #include "ggc.h"
  52 #include "gstab.h"
  53 #include "target.h"
  54 #include "target-def.h"
  55
  56 #ifdef __GNU_STAB__
  57 #define STAB_CODE_TYPE enum __stab_debug_code
  58 #else
  59 #define STAB_CODE_TYPE int
  60 #endif
  61
  62 extern tree   lookup_name PARAMS ((tree));
  63
  64 /* Enumeration for all of the relational tests, so that we can build
  65    arrays indexed by the test type, and not worry about the order
  66    of EQ, NE, etc. */
  67
  68 enum internal_test {
  69     ITEST_EQ,
  70     ITEST_NE,
  71     ITEST_GT,
  72     ITEST_GE,
  73     ITEST_LT,
  74     ITEST_LE,
  75     ITEST_GTU,
  76     ITEST_GEU,
  77     ITEST_LTU,
  78     ITEST_LEU,
  79     ITEST_MAX
  80   };
  81
  82
  83 struct constant;
  84 static enum internal_test map_test_to_internal_test     PARAMS ((enum rtx_code));
  85 static int mips16_simple_memory_operand         PARAMS ((rtx, rtx,
  86                                                         enum machine_mode));
  87 static int m16_check_op                         PARAMS ((rtx, int, int, int));
  88 static void block_move_loop                     PARAMS ((rtx, rtx,
  89                                                          unsigned int,
  90                                                          int,
  91                                                          rtx, rtx));
  92 static void block_move_call                     PARAMS ((rtx, rtx, rtx));
  93 static FILE *mips_make_temp_file                PARAMS ((void));
  94 static void save_restore_insns                  PARAMS ((int, rtx,
  95                                                         long, FILE *));
  96 static void mips16_output_gp_offset             PARAMS ((FILE *, rtx));
  97 static void mips16_fp_args                      PARAMS ((FILE *, int, int));
  98 static void build_mips16_function_stub          PARAMS ((FILE *));
  99 static void mips16_optimize_gp                  PARAMS ((rtx));
 100 static rtx add_constant                         PARAMS ((struct constant **,
 101                                                         rtx,
 102                                                         enum machine_mode));
 103 static void dump_constants                      PARAMS ((struct constant *,
 104                                                         rtx));
 105 static rtx mips_find_symbol                     PARAMS ((rtx));
 106 static void abort_with_insn                     PARAMS ((rtx, const char *))
 107   ATTRIBUTE_NORETURN;
 108 static int symbolic_expression_p                PARAMS ((rtx));
 109 static void mips_add_gc_roots                   PARAMS ((void));
 110 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
 111 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
 112 static enum processor_type mips_parse_cpu       PARAMS ((const char *));
 113
 114 /* Global variables for machine-dependent things.  */
 115
 116 /* Threshold for data being put into the small data/bss area, instead
 117    of the normal data area (references to the small data/bss area take
 118    1 instruction, and use the global pointer, references to the normal
 119    data area takes 2 instructions).  */
 120 int mips_section_threshold = -1;
 121
 122 /* Count the number of .file directives, so that .loc is up to date.  */
 123 int num_source_filenames = 0;
 124
 125 /* Count the number of sdb related labels are generated (to find block
 126    start and end boundaries).  */
 127 int sdb_label_count = 0;
 128
 129 /* Next label # for each statement for Silicon Graphics IRIS systems. */
 130 int sym_lineno = 0;
 131
 132 /* Non-zero if inside of a function, because the stupid MIPS asm can't
 133    handle .files inside of functions.  */
 134 int inside_function = 0;
 135
 136 /* Files to separate the text and the data output, so that all of the data
 137    can be emitted before the text, which will mean that the assembler will
 138    generate smaller code, based on the global pointer.  */
 139 FILE *asm_out_data_file;
 140 FILE *asm_out_text_file;
 141
 142 /* Linked list of all externals that are to be emitted when optimizing
 143    for the global pointer if they haven't been declared by the end of
 144    the program with an appropriate .comm or initialization.  */
 145
 146 struct extern_list
 147 {
 148   struct extern_list *next;     /* next external */
 149   const char *name;             /* name of the external */
 150   int size;                     /* size in bytes */
 151 } *extern_head = 0;
 152
 153 /* Name of the file containing the current function.  */
 154 const char *current_function_file = "";
 155
 156 /* Warning given that Mips ECOFF can't support changing files
 157    within a function.  */
 158 int file_in_function_warning = FALSE;
 159
 160 /* Whether to suppress issuing .loc's because the user attempted
 161    to change the filename within a function.  */
 162 int ignore_line_number = FALSE;
 163
 164 /* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */
 165 int set_noreorder;
 166 int set_noat;
 167 int set_nomacro;
 168 int set_volatile;
 169
 170 /* The next branch instruction is a branch likely, not branch normal.  */
 171 int mips_branch_likely;
 172
 173 /* Count of delay slots and how many are filled.  */
 174 int dslots_load_total;
 175 int dslots_load_filled;
 176 int dslots_jump_total;
 177 int dslots_jump_filled;
 178
 179 /* # of nops needed by previous insn */
 180 int dslots_number_nops;
 181
 182 /* Number of 1/2/3 word references to data items (ie, not jal's).  */
 183 int num_refs[3];
 184
 185 /* registers to check for load delay */
 186 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
 187
 188 /* Cached operands, and operator to compare for use in set/branch/trap
 189    on condition codes.  */
 190 rtx branch_cmp[2];
 191
 192 /* what type of branch to use */
 193 enum cmp_type branch_type;
 194
 195 /* Number of previously seen half-pic pointers and references.  */
 196 static int prev_half_pic_ptrs = 0;
 197 static int prev_half_pic_refs = 0;
 198
 199 /* The target cpu for code generation.  */
 200 enum processor_type mips_arch;
 201
 202 /* The target cpu for optimization and scheduling.  */
 203 enum processor_type mips_tune;
 204
 205 /* Historical option for code generation and scheduling.  */
 206 enum processor_type mips_cpu;
 207
 208 /* which instruction set architecture to use.  */
 209 int mips_isa;
 210
 211 #ifdef MIPS_ABI_DEFAULT
 212 /* Which ABI to use.  This is defined to a constant in mips.h if the target
 213    doesn't support multiple ABIs.  */
 214 int mips_abi;
 215 #endif
 216
 217 /* Strings to hold which cpu and instruction set architecture to use.  */
 218 const char *mips_cpu_string;    /* for -mcpu=<xxx> */
 219 const char *mips_arch_string;   /* for -march=<xxx> */
 220 const char *mips_tune_string;   /* for -mtune=<xxx> */
 221 const char *mips_isa_string;    /* for -mips{1,2,3,4} */
 222 const char *mips_abi_string;    /* for -mabi={32,n32,64,eabi} */
 223
 224 /* Whether we are generating mips16 code.  This is a synonym for
 225    TARGET_MIPS16, and exists for use as an attribute.  */
 226 int mips16;
 227
 228 /* This variable is set by -mno-mips16.  We only care whether
 229    -mno-mips16 appears or not, and using a string in this fashion is
 230    just a way to avoid using up another bit in target_flags.  */
 231 const char *mips_no_mips16_string;
 232
 233 /* This is only used to determine if an type size setting option was
 234    explicitly specified (-mlong64, -mint64, -mlong32).  The specs
 235    set this option if such an option is used. */
 236 const char *mips_explicit_type_size_string;
 237
 238 /* Whether we are generating mips16 hard float code.  In mips16 mode
 239    we always set TARGET_SOFT_FLOAT; this variable is nonzero if
 240    -msoft-float was not specified by the user, which means that we
 241    should arrange to call mips32 hard floating point code.  */
 242 int mips16_hard_float;
 243
 244 /* This variable is set by -mentry.  We only care whether -mentry
 245    appears or not, and using a string in this fashion is just a way to
 246    avoid using up another bit in target_flags.  */
 247 const char *mips_entry_string;
 248
 249 /* Whether we should entry and exit pseudo-ops in mips16 mode.  */
 250 int mips_entry;
 251
 252 /* If TRUE, we split addresses into their high and low parts in the RTL.  */
 253 int mips_split_addresses;
 254
 255 /* Generating calls to position independent functions?  */
 256 enum mips_abicalls_type mips_abicalls;
 257
 258 /* High and low marks for floating point values which we will accept
 259    as legitimate constants for LEGITIMATE_CONSTANT_P.  These are
 260    initialized in override_options.  */
 261 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
 262
 263 /* Mode used for saving/restoring general purpose registers.  */
 264 static enum machine_mode gpr_mode;
 265
 266 /* Array giving truth value on whether or not a given hard register
 267    can support a given mode.  */
 268 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
 269
 270 /* Current frame information calculated by compute_frame_size.  */
 271 struct mips_frame_info current_frame_info;
 272
 273 /* Zero structure to initialize current_frame_info.  */
 274 struct mips_frame_info zero_frame_info;
 275
 276 /* Temporary filename used to buffer .text until end of program
 277    for -mgpopt.  */
 278 static char *temp_filename;
 279
 280 /* Pseudo-reg holding the address of the current function when
 281    generating embedded PIC code.  Created by LEGITIMIZE_ADDRESS, used
 282    by mips_finalize_pic if it was created.  */
 283 rtx embedded_pic_fnaddr_rtx;
 284
 285 /* The length of all strings seen when compiling for the mips16.  This
 286    is used to tell how many strings are in the constant pool, so that
 287    we can see if we may have an overflow.  This is reset each time the
 288    constant pool is output.  */
 289 int mips_string_length;
 290
 291 /* Pseudo-reg holding the value of $28 in a mips16 function which
 292    refers to GP relative global variables.  */
 293 rtx mips16_gp_pseudo_rtx;
 294
 295 /* In mips16 mode, we build a list of all the string constants we see
 296    in a particular function.  */
 297
 298 struct string_constant
 299 {
 300   struct string_constant *next;
 301   const char *label;
 302 };
 303
 304 static struct string_constant *string_constants;
 305
 306 /* List of all MIPS punctuation characters used by print_operand.  */
 307 char mips_print_operand_punct[256];
 308
 309 /* Map GCC register number to debugger register number.  */
 310 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
 311
 312 /* Buffer to use to enclose a load/store operation with %{ %} to
 313    turn on .set volatile.  */
 314 static char volatile_buffer[60];
 315
 316 /* Hardware names for the registers.  If -mrnames is used, this
 317    will be overwritten with mips_sw_reg_names.  */
 318
 319 char mips_reg_names[][8] =
 320 {
 321  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
 322  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
 323  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
 324  "$24",  "$25",  "$26",  "$27",  "$28",  "$sp",  "$fp",  "$31",
 325  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
 326  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
 327  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
 328  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
 329  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
 330  "$fcc5","$fcc6","$fcc7","$rap"
 331 };
 332
 333 /* Mips software names for the registers, used to overwrite the
 334    mips_reg_names array.  */
 335
 336 char mips_sw_reg_names[][8] =
 337 {
 338   "$zero","$at",  "$v0",  "$v1",  "$a0",  "$a1",  "$a2",  "$a3",
 339   "$t0",  "$t1",  "$t2",  "$t3",  "$t4",  "$t5",  "$t6",  "$t7",
 340   "$s0",  "$s1",  "$s2",  "$s3",  "$s4",  "$s5",  "$s6",  "$s7",
 341   "$t8",  "$t9",  "$k0",  "$k1",  "$gp",  "$sp",  "$fp",  "$ra",
 342   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
 343   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
 344   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
 345   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
 346   "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
 347   "$fcc5","$fcc6","$fcc7","$rap"
 348 };
 349
 350 /* Map hard register number to register class */
 351 enum reg_class mips_regno_to_class[] =
 352 {
 353   GR_REGS,      GR_REGS,        M16_NA_REGS,    M16_NA_REGS,
 354   M16_REGS,     M16_REGS,       M16_REGS,       M16_REGS,
 355   GR_REGS,      GR_REGS,        GR_REGS,        GR_REGS,
 356   GR_REGS,      GR_REGS,        GR_REGS,        GR_REGS,
 357   M16_NA_REGS,  M16_NA_REGS,    GR_REGS,        GR_REGS,
 358   GR_REGS,      GR_REGS,        GR_REGS,        GR_REGS,
 359   T_REG,        GR_REGS,        GR_REGS,        GR_REGS,
 360   GR_REGS,      GR_REGS,        GR_REGS,        GR_REGS,
 361   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 362   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 363   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 364   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 365   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 366   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 367   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 368   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 369   HI_REG,       LO_REG,         HILO_REG,       ST_REGS,
 370   ST_REGS,      ST_REGS,        ST_REGS,        ST_REGS,
 371   ST_REGS,      ST_REGS,        ST_REGS,        GR_REGS
 372 };
 373
 374 /* Map register constraint character to register class.  */
 375 enum reg_class mips_char_to_class[256] =
 376 {
 377   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 378   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 379   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 380   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 381   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 382   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 383   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 384   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 385   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 386   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 387   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 388   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 389   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 390   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 391   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 392   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 393   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 394   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 395   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 396   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 397   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 398   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 399   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 400   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 401   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 402   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 403   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 404   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 405   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 406   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 407   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 408   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 409   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 410   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 411   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 412   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 413   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 414   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 415   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 416   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 417   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 418   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 419   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 420   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 421   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 422   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 423   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 424   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 425   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 426   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 427   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 428   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 429   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 430   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 431   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 432   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 433   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 434   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 435   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 436   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 437   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 438   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 439   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 440   NO_REGS,      NO_REGS,        NO_REGS,        NO_REGS,
 441 };
 442 \f
 443 /* Initialize the GCC target structure.  */
 444 #undef TARGET_ASM_FUNCTION_PROLOGUE
 445 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
 446 #undef TARGET_ASM_FUNCTION_EPILOGUE
 447 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
 448
 449 struct gcc_target target = TARGET_INITIALIZER;
 450 \f
 451 /* Return truth value of whether OP can be used as an operands
 452    where a register or 16 bit unsigned integer is needed.  */
 453
 454 int
 455 uns_arith_operand (op, mode)
 456      rtx op;
 457      enum machine_mode mode;
 458 {
 459   if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
 460     return 1;
 461
 462   return register_operand (op, mode);
 463 }
 464
 465 /* Return truth value of whether OP can be used as an operands
 466    where a 16 bit integer is needed  */
 467
 468 int
 469 arith_operand (op, mode)
 470      rtx op;
 471      enum machine_mode mode;
 472 {
 473   if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
 474     return 1;
 475
 476   /* On the mips16, a GP relative value is a signed 16 bit offset.  */
 477   if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
 478     return 1;
 479
 480   return register_operand (op, mode);
 481 }
 482
 483 /* Return truth value of whether OP can be used as an operand in a two
 484    address arithmetic insn (such as set 123456,%o4) of mode MODE.  */
 485
 486 int
 487 arith32_operand (op, mode)
 488      rtx op;
 489      enum machine_mode mode;
 490 {
 491   if (GET_CODE (op) == CONST_INT)
 492     return 1;
 493
 494   return register_operand (op, mode);
 495 }
 496
 497 /* Return truth value of whether OP is a integer which fits in 16 bits  */
 498
 499 int
 500 small_int (op, mode)
 501      rtx op;
 502      enum machine_mode mode ATTRIBUTE_UNUSED;
 503 {
 504   return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
 505 }
 506
 507 /* Return truth value of whether OP is a 32 bit integer which is too big to
 508    be loaded with one instruction.  */
 509
 510 int
 511 large_int (op, mode)
 512      rtx op;
 513      enum machine_mode mode ATTRIBUTE_UNUSED;
 514 {
 515   HOST_WIDE_INT value;
 516
 517   if (GET_CODE (op) != CONST_INT)
 518     return 0;
 519
 520   value = INTVAL (op);
 521
 522   /* ior reg,$r0,value */
 523   if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
 524     return 0;
 525
 526   /* subu reg,$r0,value */
 527   if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
 528     return 0;
 529
 530   /* lui reg,value>>16 */
 531   if ((value & 0x0000ffff) == 0)
 532     return 0;
 533
 534   return 1;
 535 }
 536
 537 /* Return truth value of whether OP is a register or the constant 0.
 538    In mips16 mode, we only accept a register, since the mips16 does
 539    not have $0.  */
 540
 541 int
 542 reg_or_0_operand (op, mode)
 543      rtx op;
 544      enum machine_mode mode;
 545 {
 546   switch (GET_CODE (op))
 547     {
 548     case CONST_INT:
 549       if (TARGET_MIPS16)
 550         return 0;
 551       return INTVAL (op) == 0;
 552
 553     case CONST_DOUBLE:
 554       if (TARGET_MIPS16)
 555         return 0;
 556       return op == CONST0_RTX (mode);
 557
 558     case REG:
 559     case SUBREG:
 560       return register_operand (op, mode);
 561
 562     default:
 563       break;
 564     }
 565
 566   return 0;
 567 }
 568
 569 /* Return truth value of whether OP is a register or the constant 0,
 570    even in mips16 mode. */
 571
 572 int
 573 true_reg_or_0_operand (op, mode)
 574      rtx op;
 575      enum machine_mode mode;
 576 {
 577   switch (GET_CODE (op))
 578     {
 579     case CONST_INT:
 580       return INTVAL (op) == 0;
 581
 582     case CONST_DOUBLE:
 583       return op == CONST0_RTX (mode);
 584
 585     case REG:
 586     case SUBREG:
 587       return register_operand (op, mode);
 588
 589     default:
 590       break;
 591     }
 592
 593   return 0;
 594 }
 595
 596 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
 597
 598 int
 599 mips_const_double_ok (op, mode)
 600      rtx op;
 601      enum machine_mode mode;
 602 {
 603   REAL_VALUE_TYPE d;
 604
 605   if (GET_CODE (op) != CONST_DOUBLE)
 606     return 0;
 607
 608   if (mode == VOIDmode)
 609     return 1;
 610
 611   if (mode != SFmode && mode != DFmode)
 612     return 0;
 613
 614   if (op == CONST0_RTX (mode))
 615     return 1;
 616
 617   /* ??? li.s does not work right with SGI's Irix 6 assembler.  */
 618   if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
 619     return 0;
 620
 621   REAL_VALUE_FROM_CONST_DOUBLE (d, op);
 622
 623   if (REAL_VALUE_ISNAN (d))
 624     return FALSE;
 625
 626   if (REAL_VALUE_NEGATIVE (d))
 627     d = REAL_VALUE_NEGATE (d);
 628
 629   if (mode == DFmode)
 630     {
 631       if (REAL_VALUES_LESS (d, dfhigh)
 632           && REAL_VALUES_LESS (dflow, d))
 633         return 1;
 634     }
 635   else
 636     {
 637       if (REAL_VALUES_LESS (d, sfhigh)
 638           && REAL_VALUES_LESS (sflow, d))
 639         return 1;
 640     }
 641
 642   return 0;
 643 }
 644
 645 /* Accept the floating point constant 1 in the appropriate mode.  */
 646
 647 int
 648 const_float_1_operand (op, mode)
 649      rtx op;
 650      enum machine_mode mode;
 651 {
 652   REAL_VALUE_TYPE d;
 653   static REAL_VALUE_TYPE onedf;
 654   static REAL_VALUE_TYPE onesf;
 655   static int one_initialized;
 656
 657   if (GET_CODE (op) != CONST_DOUBLE
 658       || mode != GET_MODE (op)
 659       || (mode != DFmode && mode != SFmode))
 660     return 0;
 661
 662   REAL_VALUE_FROM_CONST_DOUBLE (d, op);
 663
 664   /* We only initialize these values if we need them, since we will
 665      never get called unless mips_isa >= 4.  */
 666   if (! one_initialized)
 667     {
 668       onedf = REAL_VALUE_ATOF ("1.0", DFmode);
 669       onesf = REAL_VALUE_ATOF ("1.0", SFmode);
 670       one_initialized = 1;
 671     }
 672
 673   if (mode == DFmode)
 674     return REAL_VALUES_EQUAL (d, onedf);
 675   else
 676     return REAL_VALUES_EQUAL (d, onesf);
 677 }
 678
 679 /* Return true if a memory load or store of REG plus OFFSET in MODE
 680    can be represented in a single word on the mips16.  */
 681
 682 static int
 683 mips16_simple_memory_operand (reg, offset, mode)
 684      rtx reg;
 685      rtx offset;
 686      enum machine_mode mode;
 687 {
 688   unsigned int size;
 689   int off;
 690
 691   if (mode == BLKmode)
 692     {
 693       /* We can't tell, because we don't know how the value will
 694          eventually be accessed.  Returning 0 here does no great
 695          harm; it just prevents some possible instruction scheduling.  */
 696       return 0;
 697     }
 698
 699   size = GET_MODE_SIZE (mode);
 700
 701   if (INTVAL (offset) % size != 0)
 702     return 0;
 703   if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
 704     off = 0x100;
 705   else
 706     off = 0x20;
 707   if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
 708     return 1;
 709   return 0;
 710 }
 711
 712 /* Return truth value if a memory operand fits in a single instruction
 713    (ie, register + small offset).  */
 714
 715 int
 716 simple_memory_operand (op, mode)
 717      rtx op;
 718      enum machine_mode mode;
 719 {
 720   rtx addr, plus0, plus1;
 721
 722   /* Eliminate non-memory operations */
 723   if (GET_CODE (op) != MEM)
 724     return 0;
 725
 726   /* dword operations really put out 2 instructions, so eliminate them.  */
 727   /* ??? This isn't strictly correct.  It is OK to accept multiword modes
 728      here, since the length attributes are being set correctly, but only
 729      if the address is offsettable.  LO_SUM is not offsettable.  */
 730   if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
 731     return 0;
 732
 733   /* Decode the address now.  */
 734   addr = XEXP (op, 0);
 735   switch (GET_CODE (addr))
 736     {
 737     case REG:
 738     case LO_SUM:
 739       return 1;
 740
 741     case CONST_INT:
 742       if (TARGET_MIPS16)
 743         return 0;
 744       return SMALL_INT (addr);
 745
 746     case PLUS:
 747       plus0 = XEXP (addr, 0);
 748       plus1 = XEXP (addr, 1);
 749       if (GET_CODE (plus0) == REG
 750           && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
 751           && (! TARGET_MIPS16
 752               || mips16_simple_memory_operand (plus0, plus1, mode)))
 753         return 1;
 754
 755       else if (GET_CODE (plus1) == REG
 756                && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
 757                && (! TARGET_MIPS16
 758                    || mips16_simple_memory_operand (plus1, plus0, mode)))
 759         return 1;
 760
 761       else
 762         return 0;
 763
 764 #if 0
 765       /* We used to allow small symbol refs here (ie, stuff in .sdata
 766          or .sbss), but this causes some bugs in G++.  Also, it won't
 767          interfere if the MIPS linker rewrites the store instruction
 768          because the function is PIC.  */
 769
 770     case LABEL_REF:             /* never gp relative */
 771       break;
 772
 773     case CONST:
 774       /* If -G 0, we can never have a GP relative memory operation.
 775          Also, save some time if not optimizing.  */
 776       if (!TARGET_GP_OPT)
 777         return 0;
 778
 779       {
 780         rtx offset = const0_rtx;
 781         addr = eliminate_constant_term (XEXP (addr, 0), &offset);
 782         if (GET_CODE (op) != SYMBOL_REF)
 783           return 0;
 784
 785         /* let's be paranoid.... */
 786         if (! SMALL_INT (offset))
 787           return 0;
 788       }
 789
 790       /* fall through */
 791
 792     case SYMBOL_REF:
 793       return SYMBOL_REF_FLAG (addr);
 794 #endif
 795
 796       /* This SYMBOL_REF case is for the mips16.  If the above case is
 797          reenabled, this one should be merged in.  */
 798     case SYMBOL_REF:
 799       /* References to the constant pool on the mips16 use a small
 800          offset if the function is small.  The only time we care about
 801          getting this right is during delayed branch scheduling, so
 802          don't need to check until then.  The machine_dependent_reorg
 803          function will set the total length of the instructions used
 804          in the function in current_frame_info.  If that is small
 805          enough, we know for sure that this is a small offset.  It
 806          would be better if we could take into account the location of
 807          the instruction within the function, but we can't, because we
 808          don't know where we are.  */
 809       if (TARGET_MIPS16
 810           && CONSTANT_POOL_ADDRESS_P (addr)
 811           && current_frame_info.insns_len > 0)
 812         {
 813           long size;
 814
 815           size = current_frame_info.insns_len + get_pool_size ();
 816           if (GET_MODE_SIZE (mode) == 4)
 817             return size < 4 * 0x100;
 818           else if (GET_MODE_SIZE (mode) == 8)
 819             return size < 8 * 0x20;
 820           else
 821             return 0;
 822         }
 823
 824       return 0;
 825
 826     default:
 827       break;
 828     }
 829
 830   return 0;
 831 }
 832
 833 /* Return nonzero for a memory address that can be used to load or store
 834    a doubleword.  */
 835
 836 int
 837 double_memory_operand (op, mode)
 838      rtx op;
 839      enum machine_mode mode;
 840 {
 841   rtx addr;
 842
 843   if (GET_CODE (op) != MEM
 844       || ! memory_operand (op, mode))
 845     {
 846       /* During reload, we accept a pseudo register if it has an
 847          appropriate memory address.  If we don't do this, we will
 848          wind up reloading into a register, and then reloading that
 849          register from memory, when we could just reload directly from
 850          memory.  */
 851       if (reload_in_progress
 852           && GET_CODE (op) == REG
 853           && REGNO (op) >= FIRST_PSEUDO_REGISTER
 854           && reg_renumber[REGNO (op)] < 0
 855           && reg_equiv_mem[REGNO (op)] != 0
 856           && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
 857         return 1;
 858
 859       /* All reloaded addresses are valid in TARGET_64BIT mode.  This is
 860          the same test performed for 'm' in find_reloads.  */
 861
 862       if (reload_in_progress
 863           && TARGET_64BIT
 864           && (GET_CODE (op) == MEM
 865               || (GET_CODE (op) == REG
 866                   && REGNO (op) >= FIRST_PSEUDO_REGISTER
 867                   && reg_renumber[REGNO (op)] < 0)))
 868         return 1;
 869
 870       if (reload_in_progress
 871           && TARGET_MIPS16
 872           && GET_CODE (op) == MEM)
 873         {
 874           rtx addr;
 875
 876           addr = XEXP (op, 0);
 877
 878           /* During reload on the mips16, we accept a large offset
 879              from the frame pointer or the stack pointer.  This large
 880              address will get reloaded anyhow.  */
 881           if (GET_CODE (addr) == PLUS
 882               && GET_CODE (XEXP (addr, 0)) == REG
 883               && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
 884                   || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
 885               && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
 886                    && ! SMALL_INT (XEXP (addr, 1)))
 887                   || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
 888                       && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
 889             return 1;
 890
 891           /* Similarly, we accept a case where the memory address is
 892              itself on the stack, and will be reloaded. */
 893           if (GET_CODE (addr) == MEM)
 894             {
 895               rtx maddr;
 896
 897               maddr = XEXP (addr, 0);
 898               if (GET_CODE (maddr) == PLUS
 899                   && GET_CODE (XEXP (maddr, 0)) == REG
 900                   && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
 901                       || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
 902                   && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
 903                        && ! SMALL_INT (XEXP (maddr, 1)))
 904                       || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
 905                           && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
 906                 return 1;
 907             }
 908
 909           /* We also accept the same case when we have a 16 bit signed
 910              offset mixed in as well.  The large address will get
 911              reloaded, and the 16 bit offset will be OK.  */
 912           if (GET_CODE (addr) == PLUS
 913               && GET_CODE (XEXP (addr, 0)) == MEM
 914               && GET_CODE (XEXP (addr, 1)) == CONST_INT
 915               && SMALL_INT (XEXP (addr, 1)))
 916             {
 917               addr = XEXP (XEXP (addr, 0), 0);
 918               if (GET_CODE (addr) == PLUS
 919                   && GET_CODE (XEXP (addr, 0)) == REG
 920                   && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
 921                       || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
 922                   && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
 923                        && ! SMALL_INT (XEXP (addr, 1)))
 924                       || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
 925                           && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
 926                 return 1;
 927             }
 928         }
 929
 930       return 0;
 931     }
 932
 933   if (TARGET_64BIT)
 934     {
 935       /* In this case we can use an instruction like sd.  */
 936       return 1;
 937     }
 938
 939   /* Make sure that 4 added to the address is a valid memory address.
 940      This essentially just checks for overflow in an added constant.  */
 941
 942   addr = XEXP (op, 0);
 943
 944   if (CONSTANT_ADDRESS_P (addr))
 945     return 1;
 946
 947   return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
 948                             ? SImode : SFmode),
 949                            plus_constant (addr, 4));
 950 }
 951
 952 /* Return nonzero if the code of this rtx pattern is EQ or NE.  */
 953
 954 int
 955 equality_op (op, mode)
 956      rtx op;
 957      enum machine_mode mode;
 958 {
 959   if (mode != GET_MODE (op))
 960     return 0;
 961
 962   return GET_CODE (op) == EQ || GET_CODE (op) == NE;
 963 }
 964
 965 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
 966
 967 int
 968 cmp_op (op, mode)
 969      rtx op;
 970      enum machine_mode mode;
 971 {
 972   if (mode != GET_MODE (op))
 973     return 0;
 974
 975   return GET_RTX_CLASS (GET_CODE (op)) == '<';
 976 }
 977
 978 /* Return nonzero if the code is a relational operation suitable for a
 979    conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
 980    We need this in the insn that expands `trap_if' in order to prevent
 981    combine from erroneously altering the condition.  */
 982
 983 int
 984 trap_cmp_op (op, mode)
 985      rtx op;
 986      enum machine_mode mode;
 987 {
 988   if (mode != GET_MODE (op))
 989     return 0;
 990
 991   switch (GET_CODE (op))
 992     {
 993     case EQ:
 994     case NE:
 995     case LT:
 996     case LTU:
 997     case GE:
 998     case GEU:
 999       return 1;
1000
1001     default:
1002       return 0;
1003     }
1004 }
1005
1006 /* Return nonzero if the operand is either the PC or a label_ref.  */
1007
1008 int
1009 pc_or_label_operand (op, mode)
1010      rtx op;
1011      enum machine_mode mode ATTRIBUTE_UNUSED;
1012 {
1013   if (op == pc_rtx)
1014     return 1;
1015
1016   if (GET_CODE (op) == LABEL_REF)
1017     return 1;
1018
1019   return 0;
1020 }
1021
1022 /* Test for a valid operand for a call instruction.
1023    Don't allow the arg pointer register or virtual regs
1024    since they may change into reg + const, which the patterns
1025    can't handle yet.  */
1026
1027 int
1028 call_insn_operand (op, mode)
1029      rtx op;
1030      enum machine_mode mode ATTRIBUTE_UNUSED;
1031 {
1032   return (CONSTANT_ADDRESS_P (op)
1033           || (GET_CODE (op) == REG && op != arg_pointer_rtx
1034               && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1035                     && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1036 }
1037
1038 /* Return nonzero if OPERAND is valid as a source operand for a move
1039    instruction.  */
1040
1041 int
1042 move_operand (op, mode)
1043      rtx op;
1044      enum machine_mode mode;
1045 {
1046   /* Accept any general operand after reload has started; doing so
1047      avoids losing if reload does an in-place replacement of a register
1048      with a SYMBOL_REF or CONST.  */
1049   return (general_operand (op, mode)
1050           && (! (mips_split_addresses && mips_check_split (op, mode))
1051               || reload_in_progress || reload_completed)
1052           && ! (TARGET_MIPS16
1053                 && GET_CODE (op) == SYMBOL_REF
1054                 && ! mips16_constant (op, mode, 1, 0)));
1055 }
1056
1057 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1058    This accepts not only general_operand, but also sign extended
1059    constants and registers.  We need to accept sign extended constants
1060    in case a sign extended register which is used in an expression,
1061    and is equivalent to a constant, is spilled.  */
1062
1063 int
1064 movdi_operand (op, mode)
1065      rtx op;
1066      enum machine_mode mode;
1067 {
1068   if (TARGET_64BIT
1069       && mode == DImode
1070       && GET_CODE (op) == SIGN_EXTEND
1071       && GET_MODE (op) == DImode
1072       && (GET_MODE (XEXP (op, 0)) == SImode
1073           || (GET_CODE (XEXP (op, 0)) == CONST_INT
1074               && GET_MODE (XEXP (op, 0)) == VOIDmode))
1075       && (register_operand (XEXP (op, 0), SImode)
1076           || immediate_operand (XEXP (op, 0), SImode)))
1077     return 1;
1078
1079   return (general_operand (op, mode)
1080           && ! (TARGET_MIPS16
1081                 && GET_CODE (op) == SYMBOL_REF
1082                 && ! mips16_constant (op, mode, 1, 0)));
1083 }
1084
1085 /* Like register_operand, but when in 64 bit mode also accept a sign
1086    extend of a 32 bit register, since the value is known to be already
1087    sign extended.  */
1088
1089 int
1090 se_register_operand (op, mode)
1091      rtx op;
1092      enum machine_mode mode;
1093 {
1094   if (TARGET_64BIT
1095       && mode == DImode
1096       && GET_CODE (op) == SIGN_EXTEND
1097       && GET_MODE (op) == DImode
1098       && GET_MODE (XEXP (op, 0)) == SImode
1099       && register_operand (XEXP (op, 0), SImode))
1100     return 1;
1101
1102   return register_operand (op, mode);
1103 }
1104
1105 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1106    extend of a 32 bit register, since the value is known to be already
1107    sign extended.  */
1108
1109 int
1110 se_reg_or_0_operand (op, mode)
1111      rtx op;
1112      enum machine_mode mode;
1113 {
1114   if (TARGET_64BIT
1115       && mode == DImode
1116       && GET_CODE (op) == SIGN_EXTEND
1117       && GET_MODE (op) == DImode
1118       && GET_MODE (XEXP (op, 0)) == SImode
1119       && register_operand (XEXP (op, 0), SImode))
1120     return 1;
1121
1122   return reg_or_0_operand (op, mode);
1123 }
1124
1125 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1126    extend of a 32 bit register, since the value is known to be already
1127    sign extended.  */
1128
1129 int
1130 se_uns_arith_operand (op, mode)
1131      rtx op;
1132      enum machine_mode mode;
1133 {
1134   if (TARGET_64BIT
1135       && mode == DImode
1136       && GET_CODE (op) == SIGN_EXTEND
1137       && GET_MODE (op) == DImode
1138       && GET_MODE (XEXP (op, 0)) == SImode
1139       && register_operand (XEXP (op, 0), SImode))
1140     return 1;
1141
1142   return uns_arith_operand (op, mode);
1143 }
1144
1145 /* Like arith_operand, but when in 64 bit mode also accept a sign
1146    extend of a 32 bit register, since the value is known to be already
1147    sign extended.  */
1148
1149 int
1150 se_arith_operand (op, mode)
1151      rtx op;
1152      enum machine_mode mode;
1153 {
1154   if (TARGET_64BIT
1155       && mode == DImode
1156       && GET_CODE (op) == SIGN_EXTEND
1157       && GET_MODE (op) == DImode
1158       && GET_MODE (XEXP (op, 0)) == SImode
1159       && register_operand (XEXP (op, 0), SImode))
1160     return 1;
1161
1162   return arith_operand (op, mode);
1163 }
1164
1165 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1166    extend of a 32 bit register, since the value is known to be already
1167    sign extended.  */
1168
1169 int
1170 se_nonmemory_operand (op, mode)
1171      rtx op;
1172      enum machine_mode mode;
1173 {
1174   if (TARGET_64BIT
1175       && mode == DImode
1176       && GET_CODE (op) == SIGN_EXTEND
1177       && GET_MODE (op) == DImode
1178       && GET_MODE (XEXP (op, 0)) == SImode
1179       && register_operand (XEXP (op, 0), SImode))
1180     return 1;
1181
1182   return nonmemory_operand (op, mode);
1183 }
1184
1185 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1186    sign extend of a 32 bit register, since the value is known to be
1187    already sign extended.  */
1188
1189 int
1190 se_nonimmediate_operand (op, mode)
1191      rtx op;
1192      enum machine_mode mode;
1193 {
1194   if (TARGET_64BIT
1195       && mode == DImode
1196       && GET_CODE (op) == SIGN_EXTEND
1197       && GET_MODE (op) == DImode
1198       && GET_MODE (XEXP (op, 0)) == SImode
1199       && register_operand (XEXP (op, 0), SImode))
1200     return 1;
1201
1202   return nonimmediate_operand (op, mode);
1203 }
1204
1205 /* Accept any operand that can appear in a mips16 constant table
1206    instruction.  We can't use any of the standard operand functions
1207    because for these instructions we accept values that are not
1208    accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs.  */
1209
1210 int
1211 consttable_operand (op, mode)
1212      rtx op;
1213      enum machine_mode mode ATTRIBUTE_UNUSED;
1214 {
1215   return CONSTANT_P (op);
1216 }
1217
1218 /* Return nonzero if we split the address into high and low parts.  */
1219
1220 /* ??? We should also handle reg+array somewhere.  We get four
1221    instructions currently, lui %hi/addui %lo/addui reg/lw.  Better is
1222    lui %hi/addui reg/lw %lo.  Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1223    (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1224    out of the address, then we have 4 instructions to combine.  Perhaps
1225    add a 3->2 define_split for combine.  */
1226
1227 /* ??? We could also split a CONST_INT here if it is a large_int().
1228    However, it doesn't seem to be very useful to have %hi(constant).
1229    We would be better off by doing the masking ourselves and then putting
1230    the explicit high part of the constant in the RTL.  This will give better
1231    optimization.  Also, %hi(constant) needs assembler changes to work.
1232    There is already a define_split that does this.  */
1233
1234 int
1235 mips_check_split (address, mode)
1236      rtx address;
1237      enum machine_mode mode;
1238 {
1239   /* ??? This is the same check used in simple_memory_operand.
1240      We use it here because LO_SUM is not offsettable.  */
1241   if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1242     return 0;
1243
1244   if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1245       || (GET_CODE (address) == CONST
1246           && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1247           && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1248       || GET_CODE (address) == LABEL_REF)
1249     return 1;
1250
1251   return 0;
1252 }
1253
1254 /* This function is used to implement REG_MODE_OK_FOR_BASE_P.  */
1255
1256 int
1257 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1258      rtx reg;
1259      enum machine_mode mode;
1260      int strict;
1261 {
1262   return (strict
1263           ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1264           : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1265 }
1266
1267 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS.  It
1268    returns a nonzero value if XINSN is a legitimate address for a
1269    memory operand of the indicated MODE.  STRICT is non-zero if this
1270    function is called during reload.  */
1271
1272 int
1273 mips_legitimate_address_p (mode, xinsn, strict)
1274      enum machine_mode mode;
1275      rtx xinsn;
1276      int strict;
1277 {
1278   if (TARGET_DEBUG_B_MODE)
1279     {
1280       GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1281                   strict ? "" : "not ");
1282       GO_DEBUG_RTX (xinsn);
1283     }
1284
1285   /* Check for constant before stripping off SUBREG, so that we don't
1286      accept (subreg (const_int)) which will fail to reload. */
1287   if (CONSTANT_ADDRESS_P (xinsn)
1288       && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1289       && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1290     return 1;
1291
1292   while (GET_CODE (xinsn) == SUBREG)
1293     xinsn = SUBREG_REG (xinsn);
1294
1295   /* The mips16 can only use the stack pointer as a base register when
1296      loading SImode or DImode values.  */
1297   if (GET_CODE (xinsn) == REG
1298       && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1299     return 1;
1300
1301   if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1302     {
1303       register rtx xlow0 = XEXP (xinsn, 0);
1304       register rtx xlow1 = XEXP (xinsn, 1);
1305
1306       while (GET_CODE (xlow0) == SUBREG)
1307         xlow0 = SUBREG_REG (xlow0);
1308       if (GET_CODE (xlow0) == REG
1309           && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1310           && mips_check_split (xlow1, mode))
1311         return 1;
1312     }
1313
1314   if (GET_CODE (xinsn) == PLUS)
1315     {
1316       register rtx xplus0 = XEXP (xinsn, 0);
1317       register rtx xplus1 = XEXP (xinsn, 1);
1318       register enum rtx_code code0;
1319       register enum rtx_code code1;
1320
1321       while (GET_CODE (xplus0) == SUBREG)
1322         xplus0 = SUBREG_REG (xplus0);
1323       code0 = GET_CODE (xplus0);
1324
1325       while (GET_CODE (xplus1) == SUBREG)
1326         xplus1 = SUBREG_REG (xplus1);
1327       code1 = GET_CODE (xplus1);
1328
1329       /* The mips16 can only use the stack pointer as a base register
1330          when loading SImode or DImode values.  */
1331       if (code0 == REG
1332           && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1333         {
1334           if (code1 == CONST_INT && SMALL_INT (xplus1))
1335             return 1;
1336
1337           /* On the mips16, we represent GP relative offsets in RTL.
1338              These are 16 bit signed values, and can serve as register
1339              offsets.  */
1340           if (TARGET_MIPS16
1341               && mips16_gp_offset_p (xplus1))
1342             return 1;
1343
1344           /* For some code sequences, you actually get better code by
1345              pretending that the MIPS supports an address mode of a
1346              constant address + a register, even though the real
1347              machine doesn't support it.  This is because the
1348              assembler can use $r1 to load just the high 16 bits, add
1349              in the register, and fold the low 16 bits into the memory
1350              reference, whereas the compiler generates a 4 instruction
1351              sequence.  On the other hand, CSE is not as effective.
1352              It would be a win to generate the lui directly, but the
1353              MIPS assembler does not have syntax to generate the
1354              appropriate relocation.  */
1355
1356           /* Also accept CONST_INT addresses here, so no else.  */
1357           /* Reject combining an embedded PIC text segment reference
1358              with a register.  That requires an additional
1359              instruction.  */
1360           /* ??? Reject combining an address with a register for the MIPS
1361              64 bit ABI, because the SGI assembler can not handle this.  */
1362           if (!TARGET_DEBUG_A_MODE
1363               && (mips_abi == ABI_32
1364                   || mips_abi == ABI_O64
1365                   || mips_abi == ABI_EABI)
1366               && CONSTANT_ADDRESS_P (xplus1)
1367               && ! mips_split_addresses
1368               && (!TARGET_EMBEDDED_PIC
1369                   || code1 != CONST
1370                   || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1371               /* When assembling for machines with 64 bit registers,
1372                  the assembler will not sign-extend the constant "foo"
1373                  in "la x, foo(x)" */
1374               && (!TARGET_64BIT || (INTVAL (xplus1) > 0))
1375               && !TARGET_MIPS16)
1376             return 1;
1377         }
1378     }
1379
1380   if (TARGET_DEBUG_B_MODE)
1381     GO_PRINTF ("Not a legitimate address\n");
1382
1383   /* The address was not legitimate.  */
1384   return 0;
1385 }
1386
1387 \f
1388 /* We need a lot of little routines to check constant values on the
1389    mips16.  These are used to figure out how long the instruction will
1390    be.  It would be much better to do this using constraints, but
1391    there aren't nearly enough letters available.  */
1392
1393 static int
1394 m16_check_op (op, low, high, mask)
1395      rtx op;
1396      int low;
1397      int high;
1398      int mask;
1399 {
1400   return (GET_CODE (op) == CONST_INT
1401           && INTVAL (op) >= low
1402           && INTVAL (op) <= high
1403           && (INTVAL (op) & mask) == 0);
1404 }
1405
1406 int
1407 m16_uimm3_b (op, mode)
1408      rtx op;
1409      enum machine_mode mode ATTRIBUTE_UNUSED;
1410 {
1411   return m16_check_op (op, 0x1, 0x8, 0);
1412 }
1413
1414 int
1415 m16_simm4_1 (op, mode)
1416      rtx op;
1417      enum machine_mode mode ATTRIBUTE_UNUSED;
1418 {
1419   return m16_check_op (op, - 0x8, 0x7, 0);
1420 }
1421
1422 int
1423 m16_nsimm4_1 (op, mode)
1424      rtx op;
1425      enum machine_mode mode ATTRIBUTE_UNUSED;
1426 {
1427   return m16_check_op (op, - 0x7, 0x8, 0);
1428 }
1429
1430 int
1431 m16_simm5_1 (op, mode)
1432      rtx op;
1433      enum machine_mode mode ATTRIBUTE_UNUSED;
1434 {
1435   return m16_check_op (op, - 0x10, 0xf, 0);
1436 }
1437
1438 int
1439 m16_nsimm5_1 (op, mode)
1440      rtx op;
1441      enum machine_mode mode ATTRIBUTE_UNUSED;
1442 {
1443   return m16_check_op (op, - 0xf, 0x10, 0);
1444 }
1445
1446 int
1447 m16_uimm5_4 (op, mode)
1448      rtx op;
1449      enum machine_mode mode ATTRIBUTE_UNUSED;
1450 {
1451   return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1452 }
1453
1454 int
1455 m16_nuimm5_4 (op, mode)
1456      rtx op;
1457      enum machine_mode mode ATTRIBUTE_UNUSED;
1458 {
1459   return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1460 }
1461
1462 int
1463 m16_simm8_1 (op, mode)
1464      rtx op;
1465      enum machine_mode mode ATTRIBUTE_UNUSED;
1466 {
1467   return m16_check_op (op, - 0x80, 0x7f, 0);
1468 }
1469
1470 int
1471 m16_nsimm8_1 (op, mode)
1472      rtx op;
1473      enum machine_mode mode ATTRIBUTE_UNUSED;
1474 {
1475   return m16_check_op (op, - 0x7f, 0x80, 0);
1476 }
1477
1478 int
1479 m16_uimm8_1 (op, mode)
1480      rtx op;
1481      enum machine_mode mode ATTRIBUTE_UNUSED;
1482 {
1483   return m16_check_op (op, 0x0, 0xff, 0);
1484 }
1485
1486 int
1487 m16_nuimm8_1 (op, mode)
1488      rtx op;
1489      enum machine_mode mode ATTRIBUTE_UNUSED;
1490 {
1491   return m16_check_op (op, - 0xff, 0x0, 0);
1492 }
1493
1494 int
1495 m16_uimm8_m1_1 (op, mode)
1496      rtx op;
1497      enum machine_mode mode ATTRIBUTE_UNUSED;
1498 {
1499   return m16_check_op (op, - 0x1, 0xfe, 0);
1500 }
1501
1502 int
1503 m16_uimm8_4 (op, mode)
1504      rtx op;
1505      enum machine_mode mode ATTRIBUTE_UNUSED;
1506 {
1507   return m16_check_op (op, 0x0, 0xff << 2, 3);
1508 }
1509
1510 int
1511 m16_nuimm8_4 (op, mode)
1512      rtx op;
1513      enum machine_mode mode ATTRIBUTE_UNUSED;
1514 {
1515   return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1516 }
1517
1518 int
1519 m16_simm8_8 (op, mode)
1520      rtx op;
1521      enum machine_mode mode ATTRIBUTE_UNUSED;
1522 {
1523   return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1524 }
1525
1526 int
1527 m16_nsimm8_8 (op, mode)
1528      rtx op;
1529      enum machine_mode mode ATTRIBUTE_UNUSED;
1530 {
1531   return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1532 }
1533
1534 /* References to the string table on the mips16 only use a small
1535    offset if the function is small.  See the comment in the SYMBOL_REF
1536    case in simple_memory_operand.  We can't check for LABEL_REF here,
1537    because the offset is always large if the label is before the
1538    referencing instruction.  */
1539
1540 int
1541 m16_usym8_4 (op, mode)
1542      rtx op;
1543      enum machine_mode mode ATTRIBUTE_UNUSED;
1544 {
1545   if (GET_CODE (op) == SYMBOL_REF
1546       && SYMBOL_REF_FLAG (op)
1547       && current_frame_info.insns_len > 0
1548       && XSTR (op, 0)[0] == '*'
1549       && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1550                   sizeof LOCAL_LABEL_PREFIX - 1) == 0
1551       && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1552           < 4 * 0x100))
1553     {
1554       struct string_constant *l;
1555
1556       /* Make sure this symbol is on thelist of string constants to be
1557          output for this function.  It is possible that it has already
1558          been output, in which case this requires a large offset.  */
1559       for (l = string_constants; l != NULL; l = l->next)
1560         if (strcmp (l->label, XSTR (op, 0)) == 0)
1561           return 1;
1562     }
1563
1564   return 0;
1565 }
1566
1567 int
1568 m16_usym5_4 (op, mode)
1569      rtx op;
1570      enum machine_mode mode ATTRIBUTE_UNUSED;
1571 {
1572   if (GET_CODE (op) == SYMBOL_REF
1573       && SYMBOL_REF_FLAG (op)
1574       && current_frame_info.insns_len > 0
1575       && XSTR (op, 0)[0] == '*'
1576       && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1577                   sizeof LOCAL_LABEL_PREFIX - 1) == 0
1578       && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1579           < 4 * 0x20))
1580     {
1581       struct string_constant *l;
1582
1583       /* Make sure this symbol is on thelist of string constants to be
1584          output for this function.  It is possible that it has already
1585          been output, in which case this requires a large offset.  */
1586       for (l = string_constants; l != NULL; l = l->next)
1587         if (strcmp (l->label, XSTR (op, 0)) == 0)
1588           return 1;
1589     }
1590
1591   return 0;
1592 }
1593 \f
1594 /* Returns an operand string for the given instruction's delay slot,
1595    after updating filled delay slot statistics.
1596
1597    We assume that operands[0] is the target register that is set.
1598
1599    In order to check the next insn, most of this functionality is moved
1600    to FINAL_PRESCAN_INSN, and we just set the global variables that
1601    it needs.  */
1602
1603 /* ??? This function no longer does anything useful, because final_prescan_insn
1604    now will never emit a nop.  */
1605
1606 const char *
1607 mips_fill_delay_slot (ret, type, operands, cur_insn)
1608      const char *ret;           /* normal string to return */
1609      enum delay_type type;      /* type of delay */
1610      rtx operands[];            /* operands to use */
1611      rtx cur_insn;              /* current insn */
1612 {
1613   register rtx set_reg;
1614   register enum machine_mode mode;
1615   register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1616   register int num_nops;
1617
1618   if (type == DELAY_LOAD || type == DELAY_FCMP)
1619     num_nops = 1;
1620
1621   else if (type == DELAY_HILO)
1622     num_nops = 2;
1623
1624   else
1625     num_nops = 0;
1626
1627   /* Make sure that we don't put nop's after labels.  */
1628   next_insn = NEXT_INSN (cur_insn);
1629   while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1630     next_insn = NEXT_INSN (next_insn);
1631
1632   dslots_load_total += num_nops;
1633   if (TARGET_DEBUG_F_MODE
1634       || !optimize
1635       || type == DELAY_NONE
1636       || operands == 0
1637       || cur_insn == 0
1638       || next_insn == 0
1639       || GET_CODE (next_insn) == CODE_LABEL
1640       || (set_reg = operands[0]) == 0)
1641     {
1642       dslots_number_nops = 0;
1643       mips_load_reg  = 0;
1644       mips_load_reg2 = 0;
1645       mips_load_reg3 = 0;
1646       mips_load_reg4 = 0;
1647       return ret;
1648     }
1649
1650   set_reg = operands[0];
1651   if (set_reg == 0)
1652     return ret;
1653
1654   while (GET_CODE (set_reg) == SUBREG)
1655     set_reg = SUBREG_REG (set_reg);
1656
1657   mode = GET_MODE (set_reg);
1658   dslots_number_nops = num_nops;
1659   mips_load_reg = set_reg;
1660   if (GET_MODE_SIZE (mode)
1661       > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1662     mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1663   else
1664     mips_load_reg2 = 0;
1665
1666   if (type == DELAY_HILO)
1667     {
1668       mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1669       mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1670     }
1671   else
1672     {
1673       mips_load_reg3 = 0;
1674       mips_load_reg4 = 0;
1675     }
1676
1677   return ret;
1678 }
1679
1680 \f
1681 /* Determine whether a memory reference takes one (based off of the GP
1682    pointer), two (normal), or three (label + reg) instructions, and bump the
1683    appropriate counter for -mstats.  */
1684
1685 void
1686 mips_count_memory_refs (op, num)
1687      rtx op;
1688      int num;
1689 {
1690   int additional = 0;
1691   int n_words = 0;
1692   rtx addr, plus0, plus1;
1693   enum rtx_code code0, code1;
1694   int looping;
1695
1696   if (TARGET_DEBUG_B_MODE)
1697     {
1698       fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1699       debug_rtx (op);
1700     }
1701
1702   /* Skip MEM if passed, otherwise handle movsi of address.  */
1703   addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1704
1705   /* Loop, going through the address RTL.  */
1706   do
1707     {
1708       looping = FALSE;
1709       switch (GET_CODE (addr))
1710         {
1711         case REG:
1712         case CONST_INT:
1713         case LO_SUM:
1714           break;
1715
1716         case PLUS:
1717           plus0 = XEXP (addr, 0);
1718           plus1 = XEXP (addr, 1);
1719           code0 = GET_CODE (plus0);
1720           code1 = GET_CODE (plus1);
1721
1722           if (code0 == REG)
1723             {
1724               additional++;
1725               addr = plus1;
1726               looping = 1;
1727               continue;
1728             }
1729
1730           if (code0 == CONST_INT)
1731             {
1732               addr = plus1;
1733               looping = 1;
1734               continue;
1735             }
1736
1737           if (code1 == REG)
1738             {
1739               additional++;
1740               addr = plus0;
1741               looping = 1;
1742               continue;
1743             }
1744
1745           if (code1 == CONST_INT)
1746             {
1747               addr = plus0;
1748               looping = 1;
1749               continue;
1750             }
1751
1752           if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1753             {
1754               addr = plus0;
1755               looping = 1;
1756               continue;
1757             }
1758
1759           if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1760             {
1761               addr = plus1;
1762               looping = 1;
1763               continue;
1764             }
1765
1766           break;
1767
1768         case LABEL_REF:
1769           n_words = 2;          /* always 2 words */
1770           break;
1771
1772         case CONST:
1773           addr = XEXP (addr, 0);
1774           looping = 1;
1775           continue;
1776
1777         case SYMBOL_REF:
1778           n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1779           break;
1780
1781         default:
1782           break;
1783         }
1784     }
1785   while (looping);
1786
1787   if (n_words == 0)
1788     return;
1789
1790   n_words += additional;
1791   if (n_words > 3)
1792     n_words = 3;
1793
1794   num_refs[n_words-1] += num;
1795 }
1796
1797 \f
1798 /* Return RTL for the offset from the current function to the argument.
1799
1800    ??? Which argument is this?  */
1801
1802 rtx
1803 embedded_pic_offset (x)
1804      rtx x;
1805 {
1806   if (embedded_pic_fnaddr_rtx == NULL)
1807     {
1808       rtx seq;
1809
1810       embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1811
1812       /* Output code at function start to initialize the pseudo-reg.  */
1813       /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1814          inline functions, because it is called after RTL for the function
1815          has been copied.  The pseudo-reg in embedded_pic_fnaddr_rtx however
1816          does not get copied, and ends up not matching the rest of the RTL.
1817          This solution works, but means that we get unnecessary code to
1818          initialize this value every time a function is inlined into another
1819          function.  */
1820       start_sequence ();
1821       emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1822                                  XEXP (DECL_RTL (current_function_decl), 0)));
1823       seq = gen_sequence ();
1824       end_sequence ();
1825       push_topmost_sequence ();
1826       emit_insn_after (seq, get_insns ());
1827       pop_topmost_sequence ();
1828     }
1829
1830   return
1831     gen_rtx_CONST (Pmode,
1832                    gen_rtx_MINUS (Pmode, x,
1833                                   XEXP (DECL_RTL (current_function_decl), 0)));
1834 }
1835
1836 /* Return the appropriate instructions to move one operand to another.  */
1837
1838 const char *
1839 mips_move_1word (operands, insn, unsignedp)
1840      rtx operands[];
1841      rtx insn;
1842      int unsignedp;
1843 {
1844   const char *ret = 0;
1845   rtx op0 = operands[0];
1846   rtx op1 = operands[1];
1847   enum rtx_code code0 = GET_CODE (op0);
1848   enum rtx_code code1 = GET_CODE (op1);
1849   enum machine_mode mode = GET_MODE (op0);
1850   int subreg_offset0 = 0;
1851   int subreg_offset1 = 0;
1852   enum delay_type delay = DELAY_NONE;
1853
1854   while (code0 == SUBREG)
1855     {
1856       subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
1857                                              GET_MODE (SUBREG_REG (op0)),
1858                                              SUBREG_BYTE (op0),
1859                                              GET_MODE (op0));
1860       op0 = SUBREG_REG (op0);
1861       code0 = GET_CODE (op0);
1862     }
1863
1864   while (code1 == SUBREG)
1865     {
1866       subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
1867                                              GET_MODE (SUBREG_REG (op1)),
1868                                              SUBREG_BYTE (op1),
1869                                              GET_MODE (op1));
1870       op1 = SUBREG_REG (op1);
1871       code1 = GET_CODE (op1);
1872     }
1873
1874   /* For our purposes, a condition code mode is the same as SImode.  */
1875   if (mode == CCmode)
1876     mode = SImode;
1877
1878   if (code0 == REG)
1879     {
1880       int regno0 = REGNO (op0) + subreg_offset0;
1881
1882       if (code1 == REG)
1883         {
1884           int regno1 = REGNO (op1) + subreg_offset1;
1885
1886           /* Just in case, don't do anything for assigning a register
1887              to itself, unless we are filling a delay slot.  */
1888           if (regno0 == regno1 && set_nomacro == 0)
1889             ret = "";
1890
1891           else if (GP_REG_P (regno0))
1892             {
1893               if (GP_REG_P (regno1))
1894                 ret = "move\t%0,%1";
1895
1896               else if (MD_REG_P (regno1))
1897                 {
1898                   delay = DELAY_HILO;
1899                   if (regno1 != HILO_REGNUM)
1900                     ret = "mf%1\t%0";
1901                   else
1902                     ret = "mflo\t%0";
1903                 }
1904
1905               else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1906                 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1907
1908               else
1909                 {
1910                   delay = DELAY_LOAD;
1911                   if (FP_REG_P (regno1))
1912                     ret = "mfc1\t%0,%1";
1913
1914                   else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1915                     ret = "cfc1\t%0,$31";
1916                 }
1917             }
1918
1919           else if (FP_REG_P (regno0))
1920             {
1921               if (GP_REG_P (regno1))
1922                 {
1923                   delay = DELAY_LOAD;
1924                   ret = "mtc1\t%1,%0";
1925                 }
1926
1927               if (FP_REG_P (regno1))
1928                 ret = "mov.s\t%0,%1";
1929             }
1930
1931           else if (MD_REG_P (regno0))
1932             {
1933               if (GP_REG_P (regno1))
1934                 {
1935                   delay = DELAY_HILO;
1936                   if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1937                     ret = "mt%0\t%1";
1938                 }
1939             }
1940
1941           else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1942             {
1943               if (GP_REG_P (regno1))
1944                 {
1945                   delay = DELAY_LOAD;
1946                   ret = "ctc1\t%0,$31";
1947                 }
1948             }
1949         }
1950
1951       else if (code1 == MEM)
1952         {
1953           delay = DELAY_LOAD;
1954
1955           if (TARGET_STATS)
1956             mips_count_memory_refs (op1, 1);
1957
1958           if (GP_REG_P (regno0))
1959             {
1960               /* For loads, use the mode of the memory item, instead of the
1961                  target, so zero/sign extend can use this code as well.  */
1962               switch (GET_MODE (op1))
1963                 {
1964                 default:
1965                   break;
1966                 case SFmode:
1967                   ret = "lw\t%0,%1";
1968                   break;
1969                 case SImode:
1970                 case CCmode:
1971                   ret = ((unsignedp && TARGET_64BIT)
1972                          ? "lwu\t%0,%1"
1973                          : "lw\t%0,%1");
1974                   break;
1975                 case HImode:
1976                   ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1977                   break;
1978                 case QImode:
1979                   ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1980                   break;
1981                 }
1982             }
1983
1984           else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1985             ret = "l.s\t%0,%1";
1986
1987           if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1988             {
1989               size_t i = strlen (ret);
1990               if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1991                 abort ();
1992
1993               sprintf (volatile_buffer, "%%{%s%%}", ret);
1994               ret = volatile_buffer;
1995             }
1996         }
1997
1998       else if (code1 == CONST_INT
1999                || (code1 == CONST_DOUBLE
2000                    && GET_MODE (op1) == VOIDmode))
2001         {
2002           if (code1 == CONST_DOUBLE)
2003             {
2004               /* This can happen when storing constants into long long
2005                  bitfields.  Just store the least significant word of
2006                  the value.  */
2007               operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2008             }
2009
2010           if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2011             {
2012               if (GP_REG_P (regno0))
2013                 ret = "move\t%0,%z1";
2014
2015               else if (FP_REG_P (regno0))
2016                 {
2017                   delay = DELAY_LOAD;
2018                   ret = "mtc1\t%z1,%0";
2019                 }
2020
2021               else if (MD_REG_P (regno0))
2022                 {
2023                   delay = DELAY_HILO;
2024                   ret = "mt%0\t%.";
2025                 }
2026             }
2027
2028           else if (GP_REG_P (regno0))
2029             {
2030               /* Don't use X format, because that will give out of
2031                  range numbers for 64 bit host and 32 bit target.  */
2032               if (! TARGET_MIPS16)
2033                 ret = "li\t%0,%1\t\t\t# %X1";
2034               else
2035                 {
2036                   if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2037                     ret = "li\t%0,%1";
2038                   else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2039                     ret = "li\t%0,%n1\n\tneg\t%0";
2040                 }
2041             }
2042         }
2043
2044       else if (code1 == CONST_DOUBLE && mode == SFmode)
2045         {
2046           if (op1 == CONST0_RTX (SFmode))
2047             {
2048               if (GP_REG_P (regno0))
2049                 ret = "move\t%0,%.";
2050
2051               else if (FP_REG_P (regno0))
2052                 {
2053                   delay = DELAY_LOAD;
2054                   ret = "mtc1\t%.,%0";
2055                 }
2056             }
2057
2058           else
2059             {
2060               delay = DELAY_LOAD;
2061               ret = "li.s\t%0,%1";
2062             }
2063         }
2064
2065       else if (code1 == LABEL_REF)
2066         {
2067           if (TARGET_STATS)
2068             mips_count_memory_refs (op1, 1);
2069
2070           ret = "la\t%0,%a1";
2071         }
2072
2073       else if (code1 == SYMBOL_REF || code1 == CONST)
2074         {
2075           if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2076             {
2077               rtx offset = const0_rtx;
2078
2079               if (GET_CODE (op1) == CONST)
2080                 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2081
2082               if (GET_CODE (op1) == SYMBOL_REF)
2083                 {
2084                   operands[2] = HALF_PIC_PTR (op1);
2085
2086                   if (TARGET_STATS)
2087                     mips_count_memory_refs (operands[2], 1);
2088
2089                   if (INTVAL (offset) == 0)
2090                     {
2091                       delay = DELAY_LOAD;
2092                       ret = (unsignedp && TARGET_64BIT
2093                              ? "lwu\t%0,%2"
2094                              : "lw\t%0,%2");
2095                     }
2096                   else
2097                     {
2098                       dslots_load_total++;
2099                       operands[3] = offset;
2100                       if (unsignedp && TARGET_64BIT)
2101                         ret = (SMALL_INT (offset)
2102                                ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2103                                : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2104                       else
2105                         ret = (SMALL_INT (offset)
2106                                ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2107                                : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2108                     }
2109                 }
2110             }
2111           else if (TARGET_MIPS16
2112                    && code1 == CONST
2113                    && GET_CODE (XEXP (op1, 0)) == REG
2114                    && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2115             {
2116               /* This case arises on the mips16; see
2117                  mips16_gp_pseudo_reg.  */
2118               ret = "move\t%0,%+";
2119             }
2120           else if (TARGET_MIPS16
2121                    && code1 == SYMBOL_REF
2122                    && SYMBOL_REF_FLAG (op1)
2123                    && (XSTR (op1, 0)[0] != '*'
2124                        || strncmp (XSTR (op1, 0) + 1,
2125                                    LOCAL_LABEL_PREFIX,
2126                                    sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2127             {
2128               /* This can occur when reloading the address of a GP
2129                  relative symbol on the mips16.  */
2130               ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2131             }
2132           else
2133             {
2134               if (TARGET_STATS)
2135                 mips_count_memory_refs (op1, 1);
2136
2137               ret = "la\t%0,%a1";
2138             }
2139         }
2140
2141       else if (code1 == PLUS)
2142         {
2143           rtx add_op0 = XEXP (op1, 0);
2144           rtx add_op1 = XEXP (op1, 1);
2145
2146           if (GET_CODE (XEXP (op1, 1)) == REG
2147               && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2148             add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2149
2150           operands[2] = add_op0;
2151           operands[3] = add_op1;
2152           ret = "add%:\t%0,%2,%3";
2153         }
2154
2155       else if (code1 == HIGH)
2156         {
2157           operands[1] = XEXP (op1, 0);
2158           ret = "lui\t%0,%%hi(%1)";
2159         }
2160     }
2161
2162   else if (code0 == MEM)
2163     {
2164       if (TARGET_STATS)
2165         mips_count_memory_refs (op0, 1);
2166
2167       if (code1 == REG)
2168         {
2169           int regno1 = REGNO (op1) + subreg_offset1;
2170
2171           if (GP_REG_P (regno1))
2172             {
2173               switch (mode)
2174                 {
2175                 case SFmode: ret = "sw\t%1,%0"; break;
2176                 case SImode: ret = "sw\t%1,%0"; break;
2177                 case HImode: ret = "sh\t%1,%0"; break;
2178                 case QImode: ret = "sb\t%1,%0"; break;
2179                 default: break;
2180                 }
2181             }
2182
2183           else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2184             ret = "s.s\t%1,%0";
2185         }
2186
2187       else if (code1 == CONST_INT && INTVAL (op1) == 0)
2188         {
2189           switch (mode)
2190             {
2191             case SFmode: ret = "sw\t%z1,%0"; break;
2192             case SImode: ret = "sw\t%z1,%0"; break;
2193             case HImode: ret = "sh\t%z1,%0"; break;
2194             case QImode: ret = "sb\t%z1,%0"; break;
2195             default: break;
2196             }
2197         }
2198
2199       else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2200         {
2201           switch (mode)
2202             {
2203             case SFmode: ret = "sw\t%.,%0"; break;
2204             case SImode: ret = "sw\t%.,%0"; break;
2205             case HImode: ret = "sh\t%.,%0"; break;
2206             case QImode: ret = "sb\t%.,%0"; break;
2207             default: break;
2208             }
2209         }
2210
2211       if (ret != 0 && MEM_VOLATILE_P (op0))
2212         {
2213           size_t i = strlen (ret);
2214
2215           if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2216             abort ();
2217
2218           sprintf (volatile_buffer, "%%{%s%%}", ret);
2219           ret = volatile_buffer;
2220         }
2221     }
2222
2223   if (ret == 0)
2224     {
2225       abort_with_insn (insn, "Bad move");
2226       return 0;
2227     }
2228
2229   if (delay != DELAY_NONE)
2230     return mips_fill_delay_slot (ret, delay, operands, insn);
2231
2232   return ret;
2233 }
2234
2235 \f
2236 /* Return the appropriate instructions to move 2 words */
2237
2238 const char *
2239 mips_move_2words (operands, insn)
2240      rtx operands[];
2241      rtx insn;
2242 {
2243   const char *ret = 0;
2244   rtx op0 = operands[0];
2245   rtx op1 = operands[1];
2246   enum rtx_code code0 = GET_CODE (operands[0]);
2247   enum rtx_code code1 = GET_CODE (operands[1]);
2248   int subreg_offset0 = 0;
2249   int subreg_offset1 = 0;
2250   enum delay_type delay = DELAY_NONE;
2251
2252   while (code0 == SUBREG)
2253     {
2254       subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2255                                              GET_MODE (SUBREG_REG (op0)),
2256                                              SUBREG_BYTE (op0),
2257                                              GET_MODE (op0));
2258       op0 = SUBREG_REG (op0);
2259       code0 = GET_CODE (op0);
2260     }
2261
2262   if (code1 == SIGN_EXTEND)
2263     {
2264       op1 = XEXP (op1, 0);
2265       code1 = GET_CODE (op1);
2266     }
2267
2268   while (code1 == SUBREG)
2269     {
2270       subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2271                                              GET_MODE (SUBREG_REG (op1)),
2272                                              SUBREG_BYTE (op1),
2273                                              GET_MODE (op1));
2274       op1 = SUBREG_REG (op1);
2275       code1 = GET_CODE (op1);
2276     }
2277
2278   /* Sanity check.  */
2279   if (GET_CODE (operands[1]) == SIGN_EXTEND
2280       && code1 != REG
2281       && code1 != CONST_INT
2282       /* The following three can happen as the result of a questionable
2283          cast.  */
2284       && code1 != LABEL_REF
2285       && code1 != SYMBOL_REF
2286       && code1 != CONST)
2287     abort ();
2288
2289   if (code0 == REG)
2290     {
2291       int regno0 = REGNO (op0) + subreg_offset0;
2292
2293       if (code1 == REG)
2294         {
2295           int regno1 = REGNO (op1) + subreg_offset1;
2296
2297           /* Just in case, don't do anything for assigning a register
2298              to itself, unless we are filling a delay slot.  */
2299           if (regno0 == regno1 && set_nomacro == 0)
2300             ret = "";
2301
2302           else if (FP_REG_P (regno0))
2303             {
2304               if (FP_REG_P (regno1))
2305                 ret = "mov.d\t%0,%1";
2306
2307               else
2308                 {
2309                   delay = DELAY_LOAD;
2310                   if (TARGET_FLOAT64)
2311                     {
2312                       if (!TARGET_64BIT)
2313                         abort_with_insn (insn, "Bad move");
2314
2315 #ifdef TARGET_FP_CALL_32
2316                       if (FP_CALL_GP_REG_P (regno1))
2317                         ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2318                       else
2319 #endif
2320                         ret = "dmtc1\t%1,%0";
2321                     }
2322                   else
2323                     ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2324                 }
2325             }
2326
2327           else if (FP_REG_P (regno1))
2328             {
2329               delay = DELAY_LOAD;
2330               if (TARGET_FLOAT64)
2331                 {
2332                   if (!TARGET_64BIT)
2333                     abort_with_insn (insn, "Bad move");
2334
2335 #ifdef TARGET_FP_CALL_32
2336                   if (FP_CALL_GP_REG_P (regno0))
2337                     ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2338                   else
2339 #endif
2340                     ret = "dmfc1\t%0,%1";
2341                 }
2342               else
2343                 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2344             }
2345
2346           else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2347             {
2348               delay = DELAY_HILO;
2349               if (TARGET_64BIT)
2350                 {
2351                   if (regno0 != HILO_REGNUM)
2352                     ret = "mt%0\t%1";
2353                   else if (regno1 == 0)
2354                     ret = "mtlo\t%.\n\tmthi\t%.";
2355                 }
2356               else
2357                 ret = "mthi\t%M1\n\tmtlo\t%L1";
2358             }
2359
2360           else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2361             {
2362               delay = DELAY_HILO;
2363               if (TARGET_64BIT)
2364                 {
2365                   if (regno1 != HILO_REGNUM)
2366                     ret = "mf%1\t%0";
2367                 }
2368               else
2369                 ret = "mfhi\t%M0\n\tmflo\t%L0";
2370             }
2371
2372           else if (TARGET_64BIT)
2373             ret = "move\t%0,%1";
2374
2375           else if (regno0 != (regno1+1))
2376             ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2377
2378           else
2379             ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2380         }
2381
2382       else if (code1 == CONST_DOUBLE)
2383         {
2384           /* Move zero from $0 unless !TARGET_64BIT and recipient
2385              is 64-bit fp reg, in which case generate a constant.  */
2386           if (op1 != CONST0_RTX (GET_MODE (op1))
2387               || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2388             {
2389               if (GET_MODE (op1) == DFmode)
2390                 {
2391                   delay = DELAY_LOAD;
2392
2393 #ifdef TARGET_FP_CALL_32
2394                   if (FP_CALL_GP_REG_P (regno0))
2395                     {
2396                       if (TARGET_FLOAT64 && !TARGET_64BIT)
2397                         {
2398                           split_double (op1, operands + 2, operands + 3);
2399                           ret = "li\t%0,%2\n\tli\t%D0,%3";
2400                         }
2401                       else
2402                         ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2403                     }
2404                   else
2405 #endif
2406                     /* GNU as emits 64-bit code for li.d if the ISA is 3
2407                        or higher.  For !TARGET_64BIT && gp registers we
2408                        need to avoid this by using two li instructions
2409                        instead.  */
2410                     if (ISA_HAS_64BIT_REGS
2411                         && ! TARGET_64BIT
2412                         && ! FP_REG_P (regno0))
2413                       {
2414                         split_double (op1, operands + 2, operands + 3);
2415                         ret = "li\t%0,%2\n\tli\t%D0,%3";
2416                       }
2417                     else
2418                       ret = "li.d\t%0,%1";
2419                 }
2420
2421               else if (TARGET_64BIT)
2422                 {
2423                   if (! TARGET_MIPS16)
2424                     ret = "dli\t%0,%1";
2425                 }
2426
2427               else
2428                 {
2429                   split_double (op1, operands + 2, operands + 3);
2430                   ret = "li\t%0,%2\n\tli\t%D0,%3";
2431                 }
2432             }
2433
2434           else
2435             {
2436               if (GP_REG_P (regno0))
2437                 ret = (TARGET_64BIT
2438 #ifdef TARGET_FP_CALL_32
2439                        && ! FP_CALL_GP_REG_P (regno0)
2440 #endif
2441                        ? "move\t%0,%."
2442                        : "move\t%0,%.\n\tmove\t%D0,%.");
2443
2444               else if (FP_REG_P (regno0))
2445                 {
2446                   delay = DELAY_LOAD;
2447                   ret = (TARGET_64BIT
2448                          ? "dmtc1\t%.,%0"
2449                          : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2450                 }
2451             }
2452         }
2453
2454       else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2455         {
2456           if (GP_REG_P (regno0))
2457             ret = (TARGET_64BIT
2458                    ? "move\t%0,%."
2459                    : "move\t%0,%.\n\tmove\t%D0,%.");
2460
2461           else if (FP_REG_P (regno0))
2462             {
2463               delay = DELAY_LOAD;
2464               ret = (TARGET_64BIT
2465                      ? "dmtc1\t%.,%0"
2466                      : (TARGET_FLOAT64
2467                         ? "li.d\t%0,%1"
2468                         : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2469             }
2470           else if (MD_REG_P (regno0))
2471             {
2472               delay = DELAY_HILO;
2473               ret =  (regno0 == HILO_REGNUM
2474                       ? "mtlo\t%.\n\tmthi\t%."
2475                       : "mt%0\t%.\n");
2476             }
2477         }
2478
2479       else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2480                && GP_REG_P (regno0))
2481         {
2482           if (TARGET_64BIT)
2483             {
2484               if (TARGET_MIPS16)
2485                 {
2486                   if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2487                     ret = "li\t%0,%1";
2488                   else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2489                     ret = "li\t%0,%n1\n\tneg\t%0";
2490                 }
2491               else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2492                 ret = "li\t%0,%1\t\t# %X1";
2493               else if (HOST_BITS_PER_WIDE_INT < 64)
2494                 /* We can't use 'X' for negative numbers, because then we won't
2495                    get the right value for the upper 32 bits.  */
2496                 ret = (INTVAL (op1) < 0
2497                        ? "dli\t%0,%1\t\t\t# %X1"
2498                        : "dli\t%0,%X1\t\t# %1");
2499               else
2500                 /* We must use 'X', because otherwise LONG_MIN will print as
2501                    a number that the assembler won't accept.  */
2502                 ret = "dli\t%0,%X1\t\t# %1";
2503             }
2504           else if (HOST_BITS_PER_WIDE_INT < 64)
2505             {
2506               operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2507               if (TARGET_MIPS16)
2508                 {
2509                   if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2510                     ret = "li\t%M0,%2\n\tli\t%L0,%1";
2511                   else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2512                     {
2513                       operands[2] = GEN_INT (1);
2514                       ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2515                     }
2516                 }
2517               else
2518                 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2519             }
2520           else
2521             {
2522               /* We use multiple shifts here, to avoid warnings about out
2523                  of range shifts on 32 bit hosts.  */
2524               operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2525               operands[1]
2526                 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2527               ret = "li\t%M0,%2\n\tli\t%L0,%1";
2528             }
2529         }
2530
2531       else if (code1 == MEM)
2532         {
2533           delay = DELAY_LOAD;
2534
2535           if (TARGET_STATS)
2536             mips_count_memory_refs (op1, 2);
2537
2538           if (FP_REG_P (regno0))
2539             ret = "l.d\t%0,%1";
2540
2541           else if (TARGET_64BIT)
2542             {
2543
2544 #ifdef TARGET_FP_CALL_32
2545               if (FP_CALL_GP_REG_P (regno0))
2546                 ret = (double_memory_operand (op1, GET_MODE (op1))
2547                        ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2548                        : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2549               else
2550 #endif
2551                 ret = "ld\t%0,%1";
2552             }
2553
2554           else if (double_memory_operand (op1, GET_MODE (op1)))
2555             {
2556               operands[2] = adjust_address (op1, SImode, 4);
2557               ret = (reg_mentioned_p (op0, op1)
2558                      ? "lw\t%D0,%2\n\tlw\t%0,%1"
2559                      : "lw\t%0,%1\n\tlw\t%D0,%2");
2560             }
2561
2562           if (ret != 0 && MEM_VOLATILE_P (op1))
2563             {
2564               size_t i = strlen (ret);
2565
2566               if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2567                 abort ();
2568
2569               sprintf (volatile_buffer, "%%{%s%%}", ret);
2570               ret = volatile_buffer;
2571             }
2572         }
2573
2574       else if (code1 == LABEL_REF)
2575         {
2576           if (TARGET_STATS)
2577             mips_count_memory_refs (op1, 2);
2578
2579           if (GET_CODE (operands[1]) == SIGN_EXTEND)
2580             /* We deliberately remove the 'a' from '%1', so that we don't
2581                have to add SIGN_EXTEND support to print_operand_address.
2582                print_operand will just call print_operand_address in this
2583                case, so there is no problem.  */
2584             ret = "la\t%0,%1";
2585           else
2586             ret = "dla\t%0,%a1";
2587         }
2588       else if (code1 == SYMBOL_REF || code1 == CONST)
2589         {
2590           if (TARGET_MIPS16
2591               && code1 == CONST
2592               && GET_CODE (XEXP (op1, 0)) == REG
2593               && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2594             {
2595               /* This case arises on the mips16; see
2596                  mips16_gp_pseudo_reg.  */
2597               ret = "move\t%0,%+";
2598             }
2599           else if (TARGET_MIPS16
2600                    && code1 == SYMBOL_REF
2601                    && SYMBOL_REF_FLAG (op1)
2602                    && (XSTR (op1, 0)[0] != '*'
2603                        || strncmp (XSTR (op1, 0) + 1,
2604                                    LOCAL_LABEL_PREFIX,
2605                                    sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2606             {
2607               /* This can occur when reloading the address of a GP
2608                  relative symbol on the mips16.  */
2609               ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2610             }
2611           else
2612             {
2613               if (TARGET_STATS)
2614                 mips_count_memory_refs (op1, 2);
2615
2616               if (GET_CODE (operands[1]) == SIGN_EXTEND)
2617                 /* We deliberately remove the 'a' from '%1', so that we don't
2618                    have to add SIGN_EXTEND support to print_operand_address.
2619                    print_operand will just call print_operand_address in this
2620                    case, so there is no problem.  */
2621                 ret = "la\t%0,%1";
2622               else
2623                 ret = "dla\t%0,%a1";
2624             }
2625         }
2626     }
2627
2628   else if (code0 == MEM)
2629     {
2630       if (code1 == REG)
2631         {
2632           int regno1 = REGNO (op1) + subreg_offset1;
2633
2634           if (FP_REG_P (regno1))
2635             ret = "s.d\t%1,%0";
2636
2637           else if (TARGET_64BIT)
2638             {
2639
2640 #ifdef TARGET_FP_CALL_32
2641               if (FP_CALL_GP_REG_P (regno1))
2642                 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2643               else
2644 #endif
2645                 ret = "sd\t%1,%0";
2646             }
2647
2648           else if (double_memory_operand (op0, GET_MODE (op0)))
2649             {
2650               operands[2] = adjust_address (op0, SImode, 4);
2651               ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2652             }
2653         }
2654
2655       else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2656                 || (code1 == CONST_DOUBLE
2657                     && op1 == CONST0_RTX (GET_MODE (op1))))
2658                && (TARGET_64BIT
2659                    || double_memory_operand (op0, GET_MODE (op0))))
2660         {
2661           if (TARGET_64BIT)
2662             ret = "sd\t%.,%0";
2663           else
2664             {
2665               operands[2] = adjust_address (op0, SImode, 4);
2666               ret = "sw\t%.,%0\n\tsw\t%.,%2";
2667             }
2668         }
2669
2670       if (TARGET_STATS)
2671         mips_count_memory_refs (op0, 2);
2672
2673       if (ret != 0 && MEM_VOLATILE_P (op0))
2674         {
2675           size_t i = strlen (ret);
2676
2677           if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2678             abort ();
2679
2680           sprintf (volatile_buffer, "%%{%s%%}", ret);
2681           ret = volatile_buffer;
2682         }
2683     }
2684
2685   if (ret == 0)
2686     {
2687       abort_with_insn (insn, "Bad move");
2688       return 0;
2689     }
2690
2691   if (delay != DELAY_NONE)
2692     return mips_fill_delay_slot (ret, delay, operands, insn);
2693
2694   return ret;
2695 }
2696 \f
2697 /* Provide the costs of an addressing mode that contains ADDR.
2698    If ADDR is not a valid address, its cost is irrelevant.  */
2699
2700 int
2701 mips_address_cost (addr)
2702      rtx addr;
2703 {
2704   switch (GET_CODE (addr))
2705     {
2706     case LO_SUM:
2707       return 1;
2708
2709     case LABEL_REF:
2710       return 2;
2711
2712     case CONST:
2713       {
2714         rtx offset = const0_rtx;
2715         addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2716         if (GET_CODE (addr) == LABEL_REF)
2717           return 2;
2718
2719         if (GET_CODE (addr) != SYMBOL_REF)
2720           return 4;
2721
2722         if (! SMALL_INT (offset))
2723           return 2;
2724       }
2725
2726       /* ... fall through ... */
2727
2728     case SYMBOL_REF:
2729       return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2730
2731     case PLUS:
2732       {
2733         register rtx plus0 = XEXP (addr, 0);
2734         register rtx plus1 = XEXP (addr, 1);
2735
2736         if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2737           plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2738
2739         if (GET_CODE (plus0) != REG)
2740           break;
2741
2742         switch (GET_CODE (plus1))
2743           {
2744           case CONST_INT:
2745             return SMALL_INT (plus1) ? 1 : 2;
2746
2747           case CONST:
2748           case SYMBOL_REF:
2749           case LABEL_REF:
2750           case HIGH:
2751           case LO_SUM:
2752             return mips_address_cost (plus1) + 1;
2753
2754           default:
2755             break;
2756           }
2757       }
2758
2759     default:
2760       break;
2761     }
2762
2763   return 4;
2764 }
2765
2766 /* Return nonzero if X is an address which needs a temporary register when
2767    reloaded while generating PIC code.  */
2768
2769 int
2770 pic_address_needs_scratch (x)
2771      rtx x;
2772 {
2773   /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
2774   if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2775       && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2776       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2777       && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2778     return 1;
2779
2780   return 0;
2781 }
2782 \f
2783 /* Make normal rtx_code into something we can index from an array */
2784
2785 static enum internal_test
2786 map_test_to_internal_test (test_code)
2787      enum rtx_code test_code;
2788 {
2789   enum internal_test test = ITEST_MAX;
2790
2791   switch (test_code)
2792     {
2793     case EQ:  test = ITEST_EQ;  break;
2794     case NE:  test = ITEST_NE;  break;
2795     case GT:  test = ITEST_GT;  break;
2796     case GE:  test = ITEST_GE;  break;
2797     case LT:  test = ITEST_LT;  break;
2798     case LE:  test = ITEST_LE;  break;
2799     case GTU: test = ITEST_GTU; break;
2800     case GEU: test = ITEST_GEU; break;
2801     case LTU: test = ITEST_LTU; break;
2802     case LEU: test = ITEST_LEU; break;
2803     default:                    break;
2804     }
2805
2806   return test;
2807 }
2808
2809 \f
2810 /* Generate the code to compare two integer values.  The return value is:
2811    (reg:SI xx)          The pseudo register the comparison is in
2812    0                    No register, generate a simple branch.
2813
2814    ??? This is called with result nonzero by the Scond patterns in
2815    mips.md.  These patterns are called with a target in the mode of
2816    the Scond instruction pattern.  Since this must be a constant, we
2817    must use SImode.  This means that if RESULT is non-zero, it will
2818    always be an SImode register, even if TARGET_64BIT is true.  We
2819    cope with this by calling convert_move rather than emit_move_insn.
2820    This will sometimes lead to an unnecessary extension of the result;
2821    for example:
2822
2823    long long
2824    foo (long long i)
2825    {
2826      return i < 5;
2827    }
2828
2829    */
2830
2831 rtx
2832 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2833      enum rtx_code test_code;   /* relational test (EQ, etc) */
2834      rtx result;                /* result to store comp. or 0 if branch */
2835      rtx cmp0;                  /* first operand to compare */
2836      rtx cmp1;                  /* second operand to compare */
2837      int *p_invert;             /* NULL or ptr to hold whether branch needs */
2838                                 /* to reverse its test */
2839 {
2840   struct cmp_info
2841   {
2842     enum rtx_code test_code;    /* code to use in instruction (LT vs. LTU) */
2843     int const_low;              /* low bound of constant we can accept */
2844     int const_high;             /* high bound of constant we can accept */
2845     int const_add;              /* constant to add (convert LE -> LT) */
2846     int reverse_regs;           /* reverse registers in test */
2847     int invert_const;           /* != 0 if invert value if cmp1 is constant */
2848     int invert_reg;             /* != 0 if invert value if cmp1 is register */
2849     int unsignedp;              /* != 0 for unsigned comparisons.  */
2850   };
2851
2852   static struct cmp_info info[ (int)ITEST_MAX ] = {
2853
2854     { XOR,       0,  65535,  0,  0,  0,  0, 0 },        /* EQ  */
2855     { XOR,       0,  65535,  0,  0,  1,  1, 0 },        /* NE  */
2856     { LT,   -32769,  32766,  1,  1,  1,  0, 0 },        /* GT  */
2857     { LT,   -32768,  32767,  0,  0,  1,  1, 0 },        /* GE  */
2858     { LT,   -32768,  32767,  0,  0,  0,  0, 0 },        /* LT  */
2859     { LT,   -32769,  32766,  1,  1,  0,  1, 0 },        /* LE  */
2860     { LTU,  -32769,  32766,  1,  1,  1,  0, 1 },        /* GTU */
2861     { LTU,  -32768,  32767,  0,  0,  1,  1, 1 },        /* GEU */
2862     { LTU,  -32768,  32767,  0,  0,  0,  0, 1 },        /* LTU */
2863     { LTU,  -32769,  32766,  1,  1,  0,  1, 1 },        /* LEU */
2864   };
2865
2866   enum internal_test test;
2867   enum machine_mode mode;
2868   struct cmp_info *p_info;
2869   int branch_p;
2870   int eqne_p;
2871   int invert;
2872   rtx reg;
2873   rtx reg2;
2874
2875   test = map_test_to_internal_test (test_code);
2876   if (test == ITEST_MAX)
2877     abort ();
2878
2879   p_info = &info[(int) test];
2880   eqne_p = (p_info->test_code == XOR);
2881
2882   mode = GET_MODE (cmp0);
2883   if (mode == VOIDmode)
2884     mode = GET_MODE (cmp1);
2885
2886   /* Eliminate simple branches */
2887   branch_p = (result == 0);
2888   if (branch_p)
2889     {
2890       if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2891         {
2892           /* Comparisons against zero are simple branches */
2893           if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2894               && (! TARGET_MIPS16 || eqne_p))
2895             return 0;
2896
2897           /* Test for beq/bne.  */
2898           if (eqne_p && ! TARGET_MIPS16)
2899             return 0;
2900         }
2901
2902       /* allocate a pseudo to calculate the value in.  */
2903       result = gen_reg_rtx (mode);
2904     }
2905
2906   /* Make sure we can handle any constants given to us.  */
2907   if (GET_CODE (cmp0) == CONST_INT)
2908     cmp0 = force_reg (mode, cmp0);
2909
2910   if (GET_CODE (cmp1) == CONST_INT)
2911     {
2912       HOST_WIDE_INT value = INTVAL (cmp1);
2913
2914       if (value < p_info->const_low
2915           || value > p_info->const_high
2916           /* ??? Why?  And why wasn't the similar code below modified too?  */
2917           || (TARGET_64BIT
2918               && HOST_BITS_PER_WIDE_INT < 64
2919               && p_info->const_add != 0
2920               && ((p_info->unsignedp
2921                    ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2922                       > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2923                    : (value + p_info->const_add) > INTVAL (cmp1))
2924                   != (p_info->const_add > 0))))
2925         cmp1 = force_reg (mode, cmp1);
2926     }
2927
2928   /* See if we need to invert the result.  */
2929   invert = (GET_CODE (cmp1) == CONST_INT
2930             ? p_info->invert_const : p_info->invert_reg);
2931
2932   if (p_invert != (int *)0)
2933     {
2934       *p_invert = invert;
2935       invert = 0;
2936     }
2937
2938   /* Comparison to constants, may involve adding 1 to change a LT into LE.
2939      Comparison between two registers, may involve switching operands.  */
2940   if (GET_CODE (cmp1) == CONST_INT)
2941     {
2942       if (p_info->const_add != 0)
2943         {
2944           HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2945
2946           /* If modification of cmp1 caused overflow,
2947              we would get the wrong answer if we follow the usual path;
2948              thus, x > 0xffffffffU would turn into x > 0U.  */
2949           if ((p_info->unsignedp
2950                ? (unsigned HOST_WIDE_INT) new >
2951                (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2952                : new > INTVAL (cmp1))
2953               != (p_info->const_add > 0))
2954             {
2955               /* This test is always true, but if INVERT is true then
2956                  the result of the test needs to be inverted so 0 should
2957                  be returned instead.  */
2958               emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2959               return result;
2960             }
2961           else
2962             cmp1 = GEN_INT (new);
2963         }
2964     }
2965
2966   else if (p_info->reverse_regs)
2967     {
2968       rtx temp = cmp0;
2969       cmp0 = cmp1;
2970       cmp1 = temp;
2971     }
2972
2973   if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2974     reg = cmp0;
2975   else
2976     {
2977       reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2978       convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2979     }
2980
2981   if (test == ITEST_NE)
2982     {
2983       if (! TARGET_MIPS16)
2984         {
2985           convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2986           invert = 0;
2987         }
2988       else
2989         {
2990           reg2 = invert ? gen_reg_rtx (mode) : result;
2991           convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2992           reg = reg2;
2993         }
2994     }
2995
2996   else if (test == ITEST_EQ)
2997     {
2998       reg2 = invert ? gen_reg_rtx (mode) : result;
2999       convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3000       reg = reg2;
3001     }
3002
3003   if (invert)
3004     {
3005       rtx one;
3006
3007       if (! TARGET_MIPS16)
3008         one = const1_rtx;
3009       else
3010         {
3011           /* The value is in $24.  Copy it to another register, so
3012              that reload doesn't think it needs to store the $24 and
3013              the input to the XOR in the same location.  */
3014           reg2 = gen_reg_rtx (mode);
3015           emit_move_insn (reg2, reg);
3016           reg = reg2;
3017           one = force_reg (mode, const1_rtx);
3018         }
3019       convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3020     }
3021
3022   return result;
3023 }
3024 \f
3025 /* Emit the common code for doing conditional branches.
3026    operand[0] is the label to jump to.
3027    The comparison operands are saved away by cmp{si,di,sf,df}.  */
3028
3029 void
3030 gen_conditional_branch (operands, test_code)
3031      rtx operands[];
3032      enum rtx_code test_code;
3033 {
3034   enum cmp_type type = branch_type;
3035   rtx cmp0 = branch_cmp[0];
3036   rtx cmp1 = branch_cmp[1];
3037   enum machine_mode mode;
3038   rtx reg;
3039   int invert;
3040   rtx label1, label2;
3041
3042   switch (type)
3043     {
3044     case CMP_SI:
3045     case CMP_DI:
3046       mode = type == CMP_SI ? SImode : DImode;
3047       invert = 0;
3048       reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3049
3050       if (reg)
3051         {
3052           cmp0 = reg;
3053           cmp1 = const0_rtx;
3054           test_code = NE;
3055         }
3056       else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3057         /* We don't want to build a comparison against a non-zero
3058            constant.  */
3059         cmp1 = force_reg (mode, cmp1);
3060
3061       break;
3062
3063     case CMP_SF:
3064     case CMP_DF:
3065       if (! ISA_HAS_8CC)
3066         reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3067       else
3068         reg = gen_reg_rtx (CCmode);
3069
3070       /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3071          0 in the instruction built below.  The MIPS FPU handles
3072          inequality testing by testing for equality and looking for a
3073          false result.  */
3074       emit_insn (gen_rtx_SET (VOIDmode, reg,
3075                               gen_rtx (test_code == NE ? EQ : test_code,
3076                                        CCmode, cmp0, cmp1)));
3077
3078       test_code = test_code == NE ? EQ : NE;
3079       mode = CCmode;
3080       cmp0 = reg;
3081       cmp1 = const0_rtx;
3082       invert = 0;
3083       break;
3084
3085     default:
3086       abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3087     }
3088
3089   /* Generate the branch.  */
3090
3091   label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3092   label2 = pc_rtx;
3093
3094   if (invert)
3095     {
3096       label2 = label1;
3097       label1 = pc_rtx;
3098     }
3099
3100   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3101                                gen_rtx_IF_THEN_ELSE (VOIDmode,
3102                                                      gen_rtx (test_code, mode,
3103                                                               cmp0, cmp1),
3104                                                      label1, label2)));
3105 }
3106
3107 /* Emit the common code for conditional moves.  OPERANDS is the array
3108    of operands passed to the conditional move defined_expand.  */
3109
3110 void
3111 gen_conditional_move (operands)
3112      rtx *operands;
3113 {
3114   rtx op0 = branch_cmp[0];
3115   rtx op1 = branch_cmp[1];
3116   enum machine_mode mode = GET_MODE (branch_cmp[0]);
3117   enum rtx_code cmp_code = GET_CODE (operands[1]);
3118   enum rtx_code move_code = NE;
3119   enum machine_mode op_mode = GET_MODE (operands[0]);
3120   enum machine_mode cmp_mode;
3121   rtx cmp_reg;
3122
3123   if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3124     {
3125       switch (cmp_code)
3126         {
3127         case EQ:
3128           cmp_code = XOR;
3129           move_code = EQ;
3130           break;
3131         case NE:
3132           cmp_code = XOR;
3133           break;
3134         case LT:
3135           break;
3136         case GE:
3137           cmp_code = LT;
3138           move_code = EQ;
3139           break;
3140         case GT:
3141           cmp_code = LT;
3142           op0 = force_reg (mode, branch_cmp[1]);
3143           op1 = branch_cmp[0];
3144           break;
3145         case LE:
3146           cmp_code = LT;
3147           op0 = force_reg (mode, branch_cmp[1]);
3148           op1 = branch_cmp[0];
3149           move_code = EQ;
3150           break;
3151         case LTU:
3152           break;
3153         case GEU:
3154           cmp_code = LTU;
3155           move_code = EQ;
3156           break;
3157         case GTU:
3158           cmp_code = LTU;
3159           op0 = force_reg (mode, branch_cmp[1]);
3160           op1 = branch_cmp[0];
3161           break;
3162         case LEU:
3163           cmp_code = LTU;
3164           op0 = force_reg (mode, branch_cmp[1]);
3165           op1 = branch_cmp[0];
3166           move_code = EQ;
3167           break;
3168         default:
3169           abort ();
3170         }
3171     }
3172   else if (cmp_code == NE)
3173     cmp_code = EQ, move_code = EQ;
3174
3175   if (mode == SImode || mode == DImode)
3176     cmp_mode = mode;
3177   else if (mode == SFmode || mode == DFmode)
3178     cmp_mode = CCmode;
3179   else
3180     abort ();
3181
3182   cmp_reg = gen_reg_rtx (cmp_mode);
3183   emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3184                           gen_rtx (cmp_code, cmp_mode, op0, op1)));
3185
3186   emit_insn (gen_rtx_SET (op_mode, operands[0],
3187                           gen_rtx_IF_THEN_ELSE (op_mode,
3188                                                 gen_rtx (move_code, VOIDmode,
3189                                                          cmp_reg,
3190                                                          CONST0_RTX (SImode)),
3191                                                 operands[2], operands[3])));
3192 }
3193
3194 /* Emit the common code for conditional moves.  OPERANDS is the array
3195    of operands passed to the conditional move defined_expand.  */
3196
3197 void
3198 mips_gen_conditional_trap (operands)
3199      rtx operands[];
3200 {
3201   rtx op0, op1;
3202   enum rtx_code cmp_code = GET_CODE (operands[0]);
3203   enum machine_mode mode = GET_MODE (branch_cmp[0]);
3204
3205   /* MIPS conditional trap machine instructions don't have GT or LE
3206      flavors, so we must invert the comparison and convert to LT and
3207      GE, respectively.  */
3208   switch (cmp_code)
3209     {
3210     case GT: cmp_code = LT; break;
3211     case LE: cmp_code = GE; break;
3212     case GTU: cmp_code = LTU; break;
3213     case LEU: cmp_code = GEU; break;
3214     default: break;
3215     }
3216   if (cmp_code == GET_CODE (operands[0]))
3217     {
3218       op0 = force_reg (mode, branch_cmp[0]);
3219       op1 = branch_cmp[1];
3220     }
3221   else
3222     {
3223       op0 = force_reg (mode, branch_cmp[1]);
3224       op1 = branch_cmp[0];
3225     }
3226   if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3227     op1 = force_reg (mode, op1);
3228
3229   emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3230                               gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3231                               operands[1]));
3232 }
3233 \f
3234 /* Write a loop to move a constant number of bytes.
3235    Generate load/stores as follows:
3236
3237    do {
3238      temp1 = src[0];
3239      temp2 = src[1];
3240      ...
3241      temp<last> = src[MAX_MOVE_REGS-1];
3242      dest[0] = temp1;
3243      dest[1] = temp2;
3244      ...
3245      dest[MAX_MOVE_REGS-1] = temp<last>;
3246      src += MAX_MOVE_REGS;
3247      dest += MAX_MOVE_REGS;
3248    } while (src != final);
3249
3250    This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3251    registers are needed.
3252
3253    Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3254    cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3255    (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses.  */
3256
3257 #define MAX_MOVE_REGS 4
3258 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3259
3260 static void
3261 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3262      rtx dest_reg;              /* register holding destination address */
3263      rtx src_reg;               /* register holding source address */
3264      unsigned int bytes;        /* # bytes to move */
3265      int align;                 /* alignment */
3266      rtx orig_dest;             /* original dest */
3267      rtx orig_src;              /* original source for making a reg note */
3268 {
3269   rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3270   rtx src_mem = replace_equiv_address (orig_src, src_reg);
3271   rtx align_rtx = GEN_INT (align);
3272   rtx label;
3273   rtx final_src;
3274   rtx bytes_rtx;
3275   int leftover;
3276
3277   if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3278     abort ();
3279
3280   leftover = bytes % MAX_MOVE_BYTES;
3281   bytes -= leftover;
3282
3283   label = gen_label_rtx ();
3284   final_src = gen_reg_rtx (Pmode);
3285   bytes_rtx = GEN_INT (bytes);
3286
3287   if (bytes > 0x7fff)
3288     {
3289       if (Pmode == DImode)
3290         {
3291           emit_insn (gen_movdi (final_src, bytes_rtx));
3292           emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3293         }
3294       else
3295         {
3296           emit_insn (gen_movsi (final_src, bytes_rtx));
3297           emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3298         }
3299     }
3300   else
3301     {
3302       if (Pmode == DImode)
3303         emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3304       else
3305         emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3306     }
3307
3308   emit_label (label);
3309
3310   bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3311   emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3312
3313   if (Pmode == DImode)
3314     {
3315       emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3316       emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3317       emit_insn (gen_cmpdi (src_reg, final_src));
3318     }
3319   else
3320     {
3321       emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3322       emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3323       emit_insn (gen_cmpsi (src_reg, final_src));
3324     }
3325
3326   emit_jump_insn (gen_bne (label));
3327
3328   if (leftover)
3329     emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3330                                       align_rtx));
3331 }
3332 \f
3333 /* Use a library function to move some bytes.  */
3334
3335 static void
3336 block_move_call (dest_reg, src_reg, bytes_rtx)
3337      rtx dest_reg;
3338      rtx src_reg;
3339      rtx bytes_rtx;
3340 {
3341   /* We want to pass the size as Pmode, which will normally be SImode
3342      but will be DImode if we are using 64 bit longs and pointers.  */
3343   if (GET_MODE (bytes_rtx) != VOIDmode
3344       && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3345     bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3346
3347 #ifdef TARGET_MEM_FUNCTIONS
3348   emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3349                      VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3350                      convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3351                                       TREE_UNSIGNED (sizetype)),
3352                      TYPE_MODE (sizetype));
3353 #else
3354   emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3355                      VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3356                      convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3357                                       TREE_UNSIGNED (integer_type_node)),
3358                      TYPE_MODE (integer_type_node));
3359 #endif
3360 }
3361 \f
3362 /* Expand string/block move operations.
3363
3364    operands[0] is the pointer to the destination.
3365    operands[1] is the pointer to the source.
3366    operands[2] is the number of bytes to move.
3367    operands[3] is the alignment.  */
3368
3369 void
3370 expand_block_move (operands)
3371      rtx operands[];
3372 {
3373   rtx bytes_rtx = operands[2];
3374   rtx align_rtx = operands[3];
3375   int constp = GET_CODE (bytes_rtx) == CONST_INT;
3376   unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3377   unsigned int align = INTVAL (align_rtx);
3378   rtx orig_src  = operands[1];
3379   rtx orig_dest = operands[0];
3380   rtx src_reg;
3381   rtx dest_reg;
3382
3383   if (constp && bytes == 0)
3384     return;
3385
3386   if (align > (unsigned) UNITS_PER_WORD)
3387     align = UNITS_PER_WORD;
3388
3389   /* Move the address into scratch registers.  */
3390   dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3391   src_reg  = copy_addr_to_reg (XEXP (orig_src, 0));
3392
3393   if (TARGET_MEMCPY)
3394     block_move_call (dest_reg, src_reg, bytes_rtx);
3395
3396   else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3397            && align == (unsigned) UNITS_PER_WORD)
3398     move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3399
3400   else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3401     emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3402                                                              dest_reg),
3403                                       replace_equiv_address (orig_src,
3404                                                              src_reg),
3405                                       bytes_rtx, align_rtx));
3406
3407   else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3408     block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3409
3410   else if (constp && optimize)
3411     {
3412       /* If the alignment is not word aligned, generate a test at
3413          runtime, to see whether things wound up aligned, and we
3414          can use the faster lw/sw instead ulw/usw.  */
3415
3416       rtx temp = gen_reg_rtx (Pmode);
3417       rtx aligned_label = gen_label_rtx ();
3418       rtx join_label = gen_label_rtx ();
3419       int leftover = bytes % MAX_MOVE_BYTES;
3420
3421       bytes -= leftover;
3422
3423       if (Pmode == DImode)
3424         {
3425           emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3426           emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3427           emit_insn (gen_cmpdi (temp, const0_rtx));
3428         }
3429       else
3430         {
3431           emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3432           emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3433           emit_insn (gen_cmpsi (temp, const0_rtx));
3434         }
3435
3436       emit_jump_insn (gen_beq (aligned_label));
3437
3438       /* Unaligned loop.  */
3439       block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3440       emit_jump_insn (gen_jump (join_label));
3441       emit_barrier ();
3442
3443       /* Aligned loop.  */
3444       emit_label (aligned_label);
3445       block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3446                        orig_src);
3447       emit_label (join_label);
3448
3449       /* Bytes at the end of the loop.  */
3450       if (leftover)
3451         emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3452                                                                  dest_reg),
3453                                           replace_equiv_address (orig_src,
3454                                                                  src_reg),
3455                                           GEN_INT (leftover),
3456                                           GEN_INT (align)));
3457     }
3458
3459   else
3460     block_move_call (dest_reg, src_reg, bytes_rtx);
3461 }
3462 \f
3463 /* Emit load/stores for a small constant block_move.
3464
3465    operands[0] is the memory address of the destination.
3466    operands[1] is the memory address of the source.
3467    operands[2] is the number of bytes to move.
3468    operands[3] is the alignment.
3469    operands[4] is a temp register.
3470    operands[5] is a temp register.
3471    ...
3472    operands[3+num_regs] is the last temp register.
3473
3474    The block move type can be one of the following:
3475         BLOCK_MOVE_NORMAL       Do all of the block move.
3476         BLOCK_MOVE_NOT_LAST     Do all but the last store.
3477         BLOCK_MOVE_LAST         Do just the last store. */
3478
3479 const char *
3480 output_block_move (insn, operands, num_regs, move_type)
3481      rtx insn;
3482      rtx operands[];
3483      int num_regs;
3484      enum block_move_type move_type;
3485 {
3486   rtx dest_reg = XEXP (operands[0], 0);
3487   rtx src_reg = XEXP (operands[1], 0);
3488   HOST_WIDE_INT bytes = INTVAL (operands[2]);
3489   int align = INTVAL (operands[3]);
3490   int num = 0;
3491   int offset = 0;
3492   int use_lwl_lwr = 0;
3493   int last_operand = num_regs + 4;
3494   int safe_regs = 4;
3495   int i;
3496   rtx xoperands[10];
3497
3498   struct {
3499     const char *load;           /* load insn without nop */
3500     const char *load_nop;       /* load insn with trailing nop */
3501     const char *store;          /* store insn */
3502     const char *final;          /* if last_store used: NULL or swr */
3503     const char *last_store;     /* last store instruction */
3504     int offset;                 /* current offset */
3505     enum machine_mode mode;     /* mode to use on (MEM) */
3506   } load_store[4];
3507
3508   /* ??? Detect a bug in GCC, where it can give us a register
3509      the same as one of the addressing registers and reduce
3510      the number of registers available.  */
3511   for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3512     if (! reg_mentioned_p (operands[i], operands[0])
3513         && ! reg_mentioned_p (operands[i], operands[1]))
3514       xoperands[safe_regs++] = operands[i];
3515
3516   if (safe_regs < last_operand)
3517     {
3518       xoperands[0] = operands[0];
3519       xoperands[1] = operands[1];
3520       xoperands[2] = operands[2];
3521       xoperands[3] = operands[3];
3522       return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3523     }
3524
3525   /* If we are given global or static addresses, and we would be
3526      emitting a few instructions, try to save time by using a
3527      temporary register for the pointer.  */
3528   /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3529      an ldl/ldr instruction pair.  We play it safe, and always move
3530      constant addresses into registers when generating N32/N64 code, just
3531      in case we might emit an unaligned load instruction.  */
3532   if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3533                        || mips_abi == ABI_N32 || mips_abi == ABI_64))
3534     {
3535       if (CONSTANT_P (src_reg))
3536         {
3537           if (TARGET_STATS)
3538             mips_count_memory_refs (operands[1], 1);
3539
3540           src_reg = operands[3 + num_regs--];
3541           if (move_type != BLOCK_MOVE_LAST)
3542             {
3543               xoperands[1] = operands[1];
3544               xoperands[0] = src_reg;
3545               if (Pmode == DImode)
3546                 output_asm_insn ("dla\t%0,%1", xoperands);
3547               else
3548                 output_asm_insn ("la\t%0,%1", xoperands);
3549             }
3550         }
3551
3552       if (CONSTANT_P (dest_reg))
3553         {
3554           if (TARGET_STATS)
3555             mips_count_memory_refs (operands[0], 1);
3556
3557           dest_reg = operands[3 + num_regs--];
3558           if (move_type != BLOCK_MOVE_LAST)
3559             {
3560               xoperands[1] = operands[0];
3561               xoperands[0] = dest_reg;
3562               if (Pmode == DImode)
3563                 output_asm_insn ("dla\t%0,%1", xoperands);
3564               else
3565                 output_asm_insn ("la\t%0,%1", xoperands);
3566             }
3567         }
3568     }
3569
3570   /* ??? We really shouldn't get any LO_SUM addresses here, because they
3571      are not offsettable, however, offsettable_address_p says they are
3572      offsettable. I think this is a bug in offsettable_address_p.
3573      For expediency, we fix this by just loading the address into a register
3574      if we happen to get one.  */
3575
3576   if (GET_CODE (src_reg) == LO_SUM)
3577     {
3578       src_reg = operands[3 + num_regs--];
3579       if (move_type != BLOCK_MOVE_LAST)
3580         {
3581           xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3582           xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3583           xoperands[0] = src_reg;
3584           if (Pmode == DImode)
3585             output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3586           else
3587             output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3588         }
3589     }
3590
3591   if (GET_CODE (dest_reg) == LO_SUM)
3592     {
3593       dest_reg = operands[3 + num_regs--];
3594       if (move_type != BLOCK_MOVE_LAST)
3595         {
3596           xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3597           xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3598           xoperands[0] = dest_reg;
3599           if (Pmode == DImode)
3600             output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3601           else
3602             output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3603         }
3604     }
3605
3606   if (num_regs > (int) ARRAY_SIZE (load_store))
3607     num_regs = ARRAY_SIZE (load_store);
3608
3609   else if (num_regs < 1)
3610     abort_with_insn (insn,
3611                      "Cannot do block move, not enough scratch registers");
3612
3613   while (bytes > 0)
3614     {
3615       load_store[num].offset = offset;
3616
3617       if (TARGET_64BIT && bytes >= 8 && align >= 8)
3618         {
3619           load_store[num].load = "ld\t%0,%1";
3620           load_store[num].load_nop = "ld\t%0,%1%#";
3621           load_store[num].store = "sd\t%0,%1";
3622           load_store[num].last_store = "sd\t%0,%1";
3623           load_store[num].final = 0;
3624           load_store[num].mode = DImode;
3625           offset += 8;
3626           bytes -= 8;
3627         }
3628
3629       /* ??? Fails because of a MIPS assembler bug?  */
3630       else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3631         {
3632           if (BYTES_BIG_ENDIAN)
3633             {
3634               load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3635               load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3636               load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3637               load_store[num].last_store = "sdr\t%0,%2";
3638               load_store[num].final = "sdl\t%0,%1";
3639             }
3640           else
3641             {
3642               load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3643               load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3644               load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3645               load_store[num].last_store = "sdr\t%0,%1";
3646               load_store[num].final = "sdl\t%0,%2";
3647             }
3648
3649           load_store[num].mode = DImode;
3650           offset += 8;
3651           bytes -= 8;
3652           use_lwl_lwr = 1;
3653         }
3654
3655       else if (bytes >= 4 && align >= 4)
3656         {
3657           load_store[num].load = "lw\t%0,%1";
3658           load_store[num].load_nop = "lw\t%0,%1%#";
3659           load_store[num].store = "sw\t%0,%1";
3660           load_store[num].last_store = "sw\t%0,%1";
3661           load_store[num].final = 0;
3662           load_store[num].mode = SImode;
3663           offset += 4;
3664           bytes -= 4;
3665         }
3666
3667       else if (bytes >= 4 && ! TARGET_MIPS16)
3668         {
3669           if (BYTES_BIG_ENDIAN)
3670             {
3671               load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3672               load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3673               load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3674               load_store[num].last_store = "swr\t%0,%2";
3675               load_store[num].final = "swl\t%0,%1";
3676             }
3677           else
3678             {
3679               load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3680               load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3681               load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3682               load_store[num].last_store = "swr\t%0,%1";
3683               load_store[num].final = "swl\t%0,%2";
3684             }
3685
3686           load_store[num].mode = SImode;
3687           offset += 4;
3688           bytes -= 4;
3689           use_lwl_lwr = 1;
3690         }
3691
3692       else if (bytes >= 2 && align >= 2)
3693         {
3694           load_store[num].load = "lh\t%0,%1";
3695           load_store[num].load_nop = "lh\t%0,%1%#";
3696           load_store[num].store = "sh\t%0,%1";
3697           load_store[num].last_store = "sh\t%0,%1";
3698           load_store[num].final = 0;
3699           load_store[num].mode = HImode;
3700           offset += 2;
3701           bytes -= 2;
3702         }
3703       else
3704         {
3705           load_store[num].load = "lb\t%0,%1";
3706           load_store[num].load_nop = "lb\t%0,%1%#";
3707           load_store[num].store = "sb\t%0,%1";
3708           load_store[num].last_store = "sb\t%0,%1";
3709           load_store[num].final = 0;
3710           load_store[num].mode = QImode;
3711           offset++;
3712           bytes--;
3713         }
3714
3715       if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3716         {
3717           dslots_load_total++;
3718           dslots_load_filled++;
3719
3720           if (CONSTANT_P (src_reg))
3721             mips_count_memory_refs (src_reg, 1);
3722
3723           if (CONSTANT_P (dest_reg))
3724             mips_count_memory_refs (dest_reg, 1);
3725         }
3726
3727       /* Emit load/stores now if we have run out of registers or are
3728          at the end of the move.  */
3729
3730       if (++num == num_regs || bytes == 0)
3731         {
3732           /* If only load/store, we need a NOP after the load.  */
3733           if (num == 1)
3734             {
3735               load_store[0].load = load_store[0].load_nop;
3736               if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3737                 dslots_load_filled--;
3738             }
3739
3740           if (move_type != BLOCK_MOVE_LAST)
3741             {
3742               for (i = 0; i < num; i++)
3743                 {
3744                   int offset;
3745
3746                   if (!operands[i + 4])
3747                     abort ();
3748
3749                   if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3750                     operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3751                                                    REGNO (operands[i + 4]));
3752
3753                   offset = load_store[i].offset;
3754                   xoperands[0] = operands[i + 4];
3755                   xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3756                                               plus_constant (src_reg, offset));
3757
3758                   if (use_lwl_lwr)
3759                     {
3760                       int extra_offset
3761                         = GET_MODE_SIZE (load_store[i].mode) - 1;
3762
3763                       xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3764                                                   plus_constant (src_reg,
3765                                                                  extra_offset
3766                                                                  + offset));
3767                     }
3768
3769                   output_asm_insn (load_store[i].load, xoperands);
3770                 }
3771             }
3772
3773           for (i = 0; i < num; i++)
3774             {
3775               int last_p = (i == num-1 && bytes == 0);
3776               int offset = load_store[i].offset;
3777
3778               xoperands[0] = operands[i + 4];
3779               xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3780                                           plus_constant (dest_reg, offset));
3781
3782
3783               if (use_lwl_lwr)
3784                 {
3785                   int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3786                   xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3787                                               plus_constant (dest_reg,
3788                                                              extra_offset
3789                                                              + offset));
3790                 }
3791
3792               if (move_type == BLOCK_MOVE_NORMAL)
3793                 output_asm_insn (load_store[i].store, xoperands);
3794
3795               else if (move_type == BLOCK_MOVE_NOT_LAST)
3796                 {
3797                   if (!last_p)
3798                     output_asm_insn (load_store[i].store, xoperands);
3799
3800                   else if (load_store[i].final != 0)
3801                     output_asm_insn (load_store[i].final, xoperands);
3802                 }
3803
3804               else if (last_p)
3805                 output_asm_insn (load_store[i].last_store, xoperands);
3806             }
3807
3808           num = 0;              /* reset load_store */
3809           use_lwl_lwr = 0;
3810         }
3811     }
3812
3813   return "";
3814 }
3815 \f
3816 /* Argument support functions.  */
3817
3818 /* Initialize CUMULATIVE_ARGS for a function.  */
3819
3820 void
3821 init_cumulative_args (cum, fntype, libname)
3822      CUMULATIVE_ARGS *cum;              /* argument info to initialize */
3823      tree fntype;                       /* tree ptr for function decl */
3824      rtx libname ATTRIBUTE_UNUSED;      /* SYMBOL_REF of library name or 0 */
3825 {
3826   static CUMULATIVE_ARGS zero_cum;
3827   tree param, next_param;
3828
3829   if (TARGET_DEBUG_E_MODE)
3830     {
3831       fprintf (stderr,
3832                "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3833
3834       if (!fntype)
3835         fputc ('\n', stderr);
3836
3837       else
3838         {
3839           tree ret_type = TREE_TYPE (fntype);
3840           fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3841                    tree_code_name[(int)TREE_CODE (fntype)],
3842                    tree_code_name[(int)TREE_CODE (ret_type)]);
3843         }
3844     }
3845
3846   *cum = zero_cum;
3847
3848   /* Determine if this function has variable arguments.  This is
3849      indicated by the last argument being 'void_type_mode' if there
3850      are no variable arguments.  The standard MIPS calling sequence
3851      passes all arguments in the general purpose registers in this case. */
3852
3853   for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3854        param != 0; param = next_param)
3855     {
3856       next_param = TREE_CHAIN (param);
3857       if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3858         cum->gp_reg_found = 1;
3859     }
3860 }
3861
3862 /* Advance the argument to the next argument position.  */
3863
3864 void
3865 function_arg_advance (cum, mode, type, named)
3866      CUMULATIVE_ARGS *cum;      /* current arg information */
3867      enum machine_mode mode;    /* current arg mode */
3868      tree type;                 /* type of the argument or 0 if lib support */
3869      int named;                 /* whether or not the argument was named */
3870 {
3871   if (TARGET_DEBUG_E_MODE)
3872     {
3873       fprintf (stderr,
3874                "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3875                cum->gp_reg_found, cum->arg_number, cum->arg_words,
3876                GET_MODE_NAME (mode));
3877       fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3878       fprintf (stderr, ", %d )\n\n", named);
3879     }
3880
3881   cum->arg_number++;
3882   switch (mode)
3883     {
3884     case VOIDmode:
3885       break;
3886
3887     default:
3888       if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3889           && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3890         abort ();
3891
3892       cum->gp_reg_found = 1;
3893       cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3894                          / UNITS_PER_WORD);
3895       break;
3896
3897     case BLKmode:
3898       cum->gp_reg_found = 1;
3899       cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3900                          / UNITS_PER_WORD);
3901       break;
3902
3903     case SFmode:
3904       if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3905         cum->fp_arg_words++;
3906       else
3907         cum->arg_words++;
3908       if (! cum->gp_reg_found && cum->arg_number <= 2)
3909         cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3910       break;
3911
3912     case DFmode:
3913       if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3914         cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3915       else
3916         cum->arg_words += (TARGET_64BIT ? 1 : 2);
3917       if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3918         cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3919       break;
3920
3921     case DImode:
3922       cum->gp_reg_found = 1;
3923       cum->arg_words += (TARGET_64BIT ? 1 : 2);
3924       break;
3925
3926     case QImode:
3927     case HImode:
3928     case SImode:
3929       cum->gp_reg_found = 1;
3930       cum->arg_words++;
3931       break;
3932     }
3933 }
3934
3935 /* Return an RTL expression containing the register for the given mode,
3936    or 0 if the argument is to be passed on the stack.  */
3937
3938 struct rtx_def *
3939 function_arg (cum, mode, type, named)
3940      CUMULATIVE_ARGS *cum;      /* current arg information */
3941      enum machine_mode mode;    /* current arg mode */
3942      tree type;                 /* type of the argument or 0 if lib support */
3943      int named;                 /* != 0 for normal args, == 0 for ... args */
3944 {
3945   rtx ret;
3946   int regbase = -1;
3947   int bias = 0;
3948   unsigned int *arg_words = &cum->arg_words;
3949   int struct_p = (type != 0
3950                   && (TREE_CODE (type) == RECORD_TYPE
3951                       || TREE_CODE (type) == UNION_TYPE
3952                       || TREE_CODE (type) == QUAL_UNION_TYPE));
3953
3954   if (TARGET_DEBUG_E_MODE)
3955     {
3956       fprintf (stderr,
3957                "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3958                cum->gp_reg_found, cum->arg_number, cum->arg_words,
3959                GET_MODE_NAME (mode));
3960       fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3961       fprintf (stderr, ", %d ) = ", named);
3962     }
3963
3964
3965   cum->last_arg_fp = 0;
3966   switch (mode)
3967     {
3968     case SFmode:
3969       if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3970         {
3971           if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3972             regbase = GP_ARG_FIRST;
3973           else
3974             {
3975               regbase = FP_ARG_FIRST;
3976
3977               /* If the first arg was a float in a floating point register,
3978                  then set bias to align this float arg properly.  */
3979               if (cum->arg_words == 1)
3980                 bias = 1;
3981             }
3982         }
3983       else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3984         {
3985           if (! TARGET_64BIT)
3986             cum->fp_arg_words += cum->fp_arg_words & 1;
3987           cum->last_arg_fp = 1;
3988           arg_words = &cum->fp_arg_words;
3989           regbase = FP_ARG_FIRST;
3990         }
3991       else
3992         regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3993       break;
3994
3995     case DFmode:
3996       if (! TARGET_64BIT)
3997         {
3998           if (mips_abi == ABI_EABI
3999               && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4000             cum->fp_arg_words += cum->fp_arg_words & 1;
4001           else
4002             cum->arg_words += cum->arg_words & 1;
4003         }
4004
4005       if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4006         regbase = ((cum->gp_reg_found
4007                     || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
4008                     || cum->arg_number >= 2)
4009                    ? GP_ARG_FIRST : FP_ARG_FIRST);
4010       else if (mips_abi == ABI_EABI
4011                && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4012         {
4013           cum->last_arg_fp = 1;
4014           arg_words = &cum->fp_arg_words;
4015           regbase = FP_ARG_FIRST;
4016         }
4017       else
4018         regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
4019                    ? GP_ARG_FIRST : FP_ARG_FIRST);
4020       break;
4021
4022     default:
4023       if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4024           && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4025         abort ();
4026
4027       /* Drops through.  */
4028     case BLKmode:
4029       if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
4030           && ! TARGET_64BIT && mips_abi != ABI_EABI)
4031         cum->arg_words += (cum->arg_words & 1);
4032       regbase = GP_ARG_FIRST;
4033       break;
4034
4035     case VOIDmode:
4036     case QImode:
4037     case HImode:
4038     case SImode:
4039       regbase = GP_ARG_FIRST;
4040       break;
4041
4042     case DImode:
4043       if (! TARGET_64BIT)
4044         cum->arg_words += (cum->arg_words & 1);
4045       regbase = GP_ARG_FIRST;
4046     }
4047
4048   if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
4049     {
4050       if (TARGET_DEBUG_E_MODE)
4051         fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
4052
4053       ret = 0;
4054     }
4055   else
4056     {
4057       if (regbase == -1)
4058         abort ();
4059
4060       if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
4061           || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
4062           || ! TYPE_SIZE_UNIT (type)
4063           || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
4064         ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4065       else
4066         {
4067           /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4068              structure contains a double in its entirety, then that 64 bit
4069              chunk is passed in a floating point register.  */
4070           tree field;
4071
4072           /* First check to see if there is any such field.  */
4073           for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4074             if (TREE_CODE (field) == FIELD_DECL
4075                 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4076                 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4077                 && host_integerp (bit_position (field), 0)
4078                 && int_bit_position (field) % BITS_PER_WORD == 0)
4079               break;
4080
4081           /* If the whole struct fits a DFmode register,
4082              we don't need the PARALLEL.  */
4083           if (! field || mode == DFmode)
4084             ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4085           else
4086             {
4087               /* Now handle the special case by returning a PARALLEL
4088                  indicating where each 64 bit chunk goes.  */
4089               unsigned int chunks;
4090               HOST_WIDE_INT bitpos;
4091               unsigned int regno;
4092               unsigned int i;
4093
4094               /* ??? If this is a packed structure, then the last hunk won't
4095                  be 64 bits.  */
4096
4097               chunks
4098                 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4099               if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
4100                 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4101
4102               /* assign_parms checks the mode of ENTRY_PARM, so we must
4103                  use the actual mode here.  */
4104               ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4105
4106               bitpos = 0;
4107               regno = regbase + *arg_words + bias;
4108               field = TYPE_FIELDS (type);
4109               for (i = 0; i < chunks; i++)
4110                 {
4111                   rtx reg;
4112
4113                   for (; field; field = TREE_CHAIN (field))
4114                     if (TREE_CODE (field) == FIELD_DECL
4115                         && int_bit_position (field) >= bitpos)
4116                       break;
4117
4118                   if (field
4119                       && int_bit_position (field) == bitpos
4120                       && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4121                       && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4122                     reg = gen_rtx_REG (DFmode,
4123                                        regno + FP_ARG_FIRST - GP_ARG_FIRST);
4124                   else
4125                     reg = gen_rtx_REG (word_mode, regno);
4126
4127                   XVECEXP (ret, 0, i)
4128                     = gen_rtx_EXPR_LIST (VOIDmode, reg,
4129                                          GEN_INT (bitpos / BITS_PER_UNIT));
4130
4131                   bitpos += 64;
4132                   regno++;
4133                 }
4134             }
4135         }
4136
4137       if (TARGET_DEBUG_E_MODE)
4138         fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4139                  struct_p ? ", [struct]" : "");
4140
4141       /* The following is a hack in order to pass 1 byte structures
4142          the same way that the MIPS compiler does (namely by passing
4143          the structure in the high byte or half word of the register).
4144          This also makes varargs work.  If we have such a structure,
4145          we save the adjustment RTL, and the call define expands will
4146          emit them.  For the VOIDmode argument (argument after the
4147          last real argument), pass back a parallel vector holding each
4148          of the adjustments.  */
4149
4150       /* ??? function_arg can be called more than once for each argument.
4151          As a result, we compute more adjustments than we need here.
4152          See the CUMULATIVE_ARGS definition in mips.h.  */
4153
4154       /* ??? This scheme requires everything smaller than the word size to
4155          shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4156          that would mean every int needs to be shifted left, which is very
4157          inefficient.  Let's not carry this compatibility to the 64 bit
4158          calling convention for now.  */
4159
4160       if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4161           && ! TARGET_64BIT && mips_abi != ABI_EABI)
4162         {
4163           rtx amount = GEN_INT (BITS_PER_WORD
4164                                 - int_size_in_bytes (type) * BITS_PER_UNIT);
4165           rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4166
4167           if (TARGET_64BIT)
4168             cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4169           else
4170             cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4171         }
4172     }
4173
4174   /* We will be called with a mode of VOIDmode after the last argument
4175      has been seen.  Whatever we return will be passed to the call
4176      insn.  If we need any shifts for small structures, return them in
4177      a PARALLEL; in that case, stuff the mips16 fp_code in as the
4178      mode.  Otherwise, if we have need a mips16 fp_code, return a REG
4179      with the code stored as the mode.  */
4180   if (mode == VOIDmode)
4181     {
4182       if (cum->num_adjusts > 0)
4183         ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4184                        gen_rtvec_v (cum->num_adjusts, cum->adjust));
4185       else if (TARGET_MIPS16 && cum->fp_code != 0)
4186         ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4187     }
4188
4189   return ret;
4190 }
4191
4192 int
4193 function_arg_partial_nregs (cum, mode, type, named)
4194      CUMULATIVE_ARGS *cum;      /* current arg information */
4195      enum machine_mode mode;    /* current arg mode */
4196      tree type;                 /* type of the argument or 0 if lib support */
4197      int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4198 {
4199   if ((mode == BLKmode
4200        || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4201        || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4202       && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
4203       && mips_abi != ABI_EABI)
4204     {
4205       int words;
4206       if (mode == BLKmode)
4207         words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4208                  / UNITS_PER_WORD);
4209       else
4210         words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4211
4212       if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
4213         return 0;               /* structure fits in registers */
4214
4215       if (TARGET_DEBUG_E_MODE)
4216         fprintf (stderr, "function_arg_partial_nregs = %d\n",
4217                  MAX_ARGS_IN_REGISTERS - cum->arg_words);
4218
4219       return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4220     }
4221
4222   else if (mode == DImode
4223            && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
4224            && ! TARGET_64BIT && mips_abi != ABI_EABI)
4225     {
4226       if (TARGET_DEBUG_E_MODE)
4227         fprintf (stderr, "function_arg_partial_nregs = 1\n");
4228
4229       return 1;
4230     }
4231
4232   return 0;
4233 }
4234 \f
4235 /* Create the va_list data type.
4236    We keep 3 pointers, and two offsets.
4237    Two pointers are to the overflow area, which starts at the CFA.
4238      One of these is constant, for addressing into the GPR save area below it.
4239      The other is advanced up the stack through the overflow region.
4240    The third pointer is to the GPR save area.  Since the FPR save area
4241      is just below it, we can address FPR slots off this pointer.
4242    We also keep two one-byte offsets, which are to be subtracted from the
4243      constant pointers to yield addresses in the GPR and FPR save areas.
4244      These are downcounted as float or non-float arguments are used,
4245      and when they get to zero, the argument must be obtained from the
4246      overflow region.
4247    If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4248      and a single pointer is enough.  It's started at the GPR save area,
4249      and is advanced, period.
4250    Note that the GPR save area is not constant size, due to optimization
4251      in the prologue.  Hence, we can't use a design with two pointers
4252      and two offsets, although we could have designed this with two pointers
4253      and three offsets. */
4254
4255
4256 tree
4257 mips_build_va_list ()
4258 {
4259   if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4260     {
4261       tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4262
4263       record = make_node (RECORD_TYPE);
4264
4265       f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4266                           ptr_type_node);
4267       f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4268                           ptr_type_node);
4269       f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4270                           ptr_type_node);
4271       f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4272                           unsigned_char_type_node);
4273       f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4274                           unsigned_char_type_node);
4275
4276
4277       DECL_FIELD_CONTEXT (f_ovfl) = record;
4278       DECL_FIELD_CONTEXT (f_gtop) = record;
4279       DECL_FIELD_CONTEXT (f_ftop) = record;
4280       DECL_FIELD_CONTEXT (f_goff) = record;
4281       DECL_FIELD_CONTEXT (f_foff) = record;
4282
4283       TYPE_FIELDS (record) = f_ovfl;
4284       TREE_CHAIN (f_ovfl) = f_gtop;
4285       TREE_CHAIN (f_gtop) = f_ftop;
4286       TREE_CHAIN (f_ftop) = f_goff;
4287       TREE_CHAIN (f_goff) = f_foff;
4288
4289       layout_type (record);
4290       return record;
4291     }
4292   else
4293     return ptr_type_node;
4294 }
4295
4296 /* Implement va_start.   stdarg_p is 0 if implementing
4297    __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4298    Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4299      (It doesn't have "...", so it inherits the pointers of its caller.) */
4300
4301 void
4302 mips_va_start (stdarg_p, valist, nextarg)
4303      int stdarg_p;
4304      tree valist;
4305      rtx nextarg;
4306 {
4307   int int_arg_words;
4308   tree t;
4309
4310   /* Find out how many non-float named formals */
4311   int_arg_words = current_function_args_info.arg_words;
4312
4313   if (mips_abi == ABI_EABI)
4314     {
4315       int gpr_save_area_size;
4316       /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4317       if (int_arg_words < 8 )
4318         /* Adjust for the prologue's economy measure */
4319         gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4320       else
4321         gpr_save_area_size = 0;
4322
4323       if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4324         {
4325           tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4326           tree ovfl, gtop, ftop, goff, foff;
4327           tree gprv;
4328           int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4329           int fpr_save_offset;
4330
4331           float_formals = current_function_args_info.fp_arg_words;
4332           /* If mips2, the number of formals is half the reported # of words */
4333           if (!TARGET_64BIT)
4334             float_formals /= 2;
4335           floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4336
4337           f_ovfl  = TYPE_FIELDS (va_list_type_node);
4338           f_gtop = TREE_CHAIN (f_ovfl);
4339           f_ftop = TREE_CHAIN (f_gtop);
4340           f_goff = TREE_CHAIN (f_ftop);
4341           f_foff = TREE_CHAIN (f_goff);
4342
4343           ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4344           gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4345           ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4346           goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4347           foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4348
4349           /* Emit code setting a pointer into the overflow (shared-stack) area.
4350              If there were more than 8 non-float formals, or more than 8
4351              float formals, then this pointer isn't to the base of the area.
4352              In that case, it must point to where the first vararg is. */
4353           size_excess = 0;
4354           if (float_formals > floats_passed_in_regs)
4355             size_excess += (float_formals-floats_passed_in_regs) * 8;
4356           if (int_arg_words > 8)
4357             size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4358
4359           /* FIXME: for mips2, the above size_excess can be wrong.  Because the
4360              overflow stack holds mixed size items, there can be alignments,
4361              so that an 8 byte double following a 4 byte int will be on an
4362              8 byte boundary.  This means that the above calculation should
4363              take into account the exact sequence of floats and non-floats
4364              which make up the excess.  That calculation should be rolled
4365              into the code which sets the current_function_args_info struct.
4366              The above then reduces to a fetch from that struct. */
4367
4368
4369           t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4370           if (size_excess)
4371             t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4372                 build_int_2 (size_excess, 0));
4373           t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4374           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4375
4376           /* Emit code setting a ptr to the base of the overflow area. */
4377           t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4378           t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4379           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4380
4381           /* Emit code setting a pointer to the GPR save area.
4382              More precisely, a pointer to off-the-end of the FPR save area.
4383              If mips4, this is gpr_save_area_size below the overflow area.
4384              If mips2, also round down to an 8-byte boundary, since the FPR
4385              save area is 8-byte aligned, and GPR is 4-byte-aligned.
4386              Therefore there can be a 4-byte gap between the save areas. */
4387           gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4388           fpr_save_offset = gpr_save_area_size;
4389           if (!TARGET_64BIT)
4390             {
4391               if (fpr_save_offset & 7)
4392                 fpr_save_offset += 4;
4393             }
4394           if (fpr_save_offset)
4395             gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4396                 build_int_2 (-fpr_save_offset,-1));
4397           t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
4398           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4399
4400           /* Emit code initting an offset to the size of the GPR save area */
4401           t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4402                 build_int_2 (gpr_save_area_size,0));
4403           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4404
4405           /* Emit code initting an offset from ftop to the first float
4406              vararg.  This varies in size, since any float
4407              varargs are put in the FPR save area after the formals.
4408              Note it's 8 bytes/formal regardless of TARGET_64BIT.
4409              However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4410              If there are 8 or more float formals, init to zero.
4411              (In fact, the formals aren't stored in the bottom of the
4412              FPR save area: they are elsewhere, and the size of the FPR
4413              save area is economized by the prologue.  But this code doesn't
4414              care.  This design is unaffected by that fact.) */
4415           if (float_formals >= floats_passed_in_regs)
4416             fpr_offset = 0;
4417           else
4418             fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4419           t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4420                      build_int_2 (fpr_offset,0));
4421           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4422         }
4423       else
4424         {
4425           /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4426
4427           /* Everything is in the GPR save area, or in the overflow
4428              area which is contiguous with it. */
4429
4430           int offset = -gpr_save_area_size;
4431           if (gpr_save_area_size == 0)
4432             offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4433           nextarg = plus_constant (nextarg, offset);
4434           std_expand_builtin_va_start (1, valist, nextarg);
4435         }
4436     }
4437   else
4438     {
4439       /* not EABI */
4440       int ofs;
4441
4442       if (stdarg_p)
4443         ofs = 0;
4444       else
4445         {
4446           /* ??? This had been conditional on
4447                _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4448              and both iris5.h and iris6.h define _MIPS_SIM.  */
4449           if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4450             ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4451           else
4452             ofs = -UNITS_PER_WORD;
4453         }
4454
4455       nextarg = plus_constant (nextarg, ofs);
4456       std_expand_builtin_va_start (1, valist, nextarg);
4457     }
4458 }
4459
4460 /* Implement va_arg.  */
4461
4462 rtx
4463 mips_va_arg (valist, type)
4464      tree valist, type;
4465 {
4466   HOST_WIDE_INT size, rsize;
4467   rtx addr_rtx;
4468   tree t;
4469
4470   size = int_size_in_bytes (type);
4471   rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4472
4473   if (mips_abi == ABI_EABI)
4474     {
4475       int indirect;
4476       rtx r, lab_over = NULL_RTX, lab_false;
4477       tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4478       tree ovfl, gtop, ftop, goff, foff;
4479
4480       indirect
4481         = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4482       if (indirect)
4483         {
4484           size = POINTER_SIZE / BITS_PER_UNIT;
4485           rsize = UNITS_PER_WORD;
4486         }
4487
4488       addr_rtx = gen_reg_rtx (Pmode);
4489
4490       if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4491         {
4492           /* Case of all args in a merged stack. No need to check bounds,
4493              just advance valist along the stack. */
4494
4495           tree gpr = valist;
4496           if (! indirect
4497               && ! TARGET_64BIT
4498               && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4499             {
4500               t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4501                      build_int_2 (2*UNITS_PER_WORD - 1, 0));
4502               t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4503                      build_int_2 (-2*UNITS_PER_WORD, -1));
4504               t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4505               expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4506             }
4507
4508           t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4509                 size_int (rsize));
4510           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4511           if (r != addr_rtx)
4512             emit_move_insn (addr_rtx, r);
4513
4514           /* flush the POSTINCREMENT */
4515           emit_queue();
4516
4517           if (indirect)
4518             {
4519               r = gen_rtx_MEM (Pmode, addr_rtx);
4520               MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4521               emit_move_insn (addr_rtx, r);
4522             }
4523           else
4524             {
4525               if (BYTES_BIG_ENDIAN && rsize != size)
4526               addr_rtx = plus_constant (addr_rtx, rsize - size);
4527             }
4528           return addr_rtx;
4529         }
4530
4531       /* Not a simple merged stack.  Need ptrs and indexes left by va_start. */
4532
4533       f_ovfl  = TYPE_FIELDS (va_list_type_node);
4534       f_gtop = TREE_CHAIN (f_ovfl);
4535       f_ftop = TREE_CHAIN (f_gtop);
4536       f_goff = TREE_CHAIN (f_ftop);
4537       f_foff = TREE_CHAIN (f_goff);
4538
4539       ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4540       gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4541       ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4542       goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4543       foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4544
4545       lab_false = gen_label_rtx ();
4546       lab_over = gen_label_rtx ();
4547
4548       if (TREE_CODE (type) == REAL_TYPE)
4549         {
4550
4551           /* Emit code to branch if foff == 0. */
4552           r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4553                 EXPAND_NORMAL);
4554           emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4555                 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4556
4557           /* Emit code for addr_rtx = ftop - foff */
4558           t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4559           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4560           if (r != addr_rtx)
4561             emit_move_insn (addr_rtx, r);
4562
4563           /* Emit code for foff-=8.
4564              Advances the offset up FPR save area by one double */
4565           t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4566           t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4567           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4568
4569           emit_queue();
4570           emit_jump (lab_over);
4571           emit_barrier ();
4572           emit_label (lab_false);
4573
4574           if (!TARGET_64BIT)
4575             {
4576               /* For mips2, the overflow area contains mixed size items.
4577                  If a 4-byte int is followed by an 8-byte float, then
4578                  natural alignment causes a 4 byte gap.
4579                  So, dynamically adjust ovfl up to a multiple of 8. */
4580               t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4581                         build_int_2 (7, 0));
4582               t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4583               t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4584               expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4585             }
4586
4587           /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4588              Regardless of mips2, postincrement the ovfl pointer by 8. */
4589           t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4590                 size_int (8));
4591           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4592           if (r != addr_rtx)
4593             emit_move_insn (addr_rtx, r);
4594
4595           emit_queue();
4596           emit_label (lab_over);
4597           return addr_rtx;
4598         }
4599       else
4600         {
4601           /* not REAL_TYPE */
4602           int step_size;
4603
4604           if (! TARGET_64BIT
4605               && TREE_CODE (type) == INTEGER_TYPE
4606               && TYPE_PRECISION (type) == 64)
4607             {
4608               /* In mips2, int takes 32 bits of the GPR save area, but
4609                  longlong takes an aligned 64 bits.  So, emit code
4610                  to zero the low order bits of goff, thus aligning
4611                  the later calculation of (gtop-goff) upwards. */
4612                t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4613                         build_int_2 (-8, -1));
4614                t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4615                expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4616             }
4617
4618           /* Emit code to branch if goff == 0. */
4619           r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4620                 EXPAND_NORMAL);
4621           emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4622                 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4623
4624           /* Emit code for addr_rtx = gtop - goff. */
4625           t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4626           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4627           if (r != addr_rtx)
4628             emit_move_insn (addr_rtx, r);
4629
4630           /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4631           if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4632             step_size = 8;
4633           else
4634             step_size = UNITS_PER_WORD;
4635
4636           /* Emit code for goff = goff - step_size.
4637              Advances the offset up GPR save area over the item. */
4638           t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4639                 build_int_2 (step_size, 0));
4640           t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4641           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4642
4643           emit_queue();
4644           emit_jump (lab_over);
4645           emit_barrier ();
4646           emit_label (lab_false);
4647
4648           /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4649           t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4650                 size_int (step_size));
4651           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4652           if (r != addr_rtx)
4653             emit_move_insn (addr_rtx, r);
4654
4655           emit_queue();
4656           emit_label (lab_over);
4657
4658           if (indirect)
4659             {
4660               r = gen_rtx_MEM (Pmode, addr_rtx);
4661               MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4662               emit_move_insn (addr_rtx, r);
4663             }
4664           else
4665             {
4666               if (BYTES_BIG_ENDIAN && rsize != size)
4667               addr_rtx = plus_constant (addr_rtx, rsize - size);
4668             }
4669           return addr_rtx;
4670         }
4671     }
4672   else
4673     {
4674       /* Not EABI. */
4675       int align;
4676
4677       /* ??? The original va-mips.h did always align, despite the fact
4678          that alignments <= UNITS_PER_WORD are preserved by the va_arg
4679          increment mechanism.  */
4680
4681       if (TARGET_64BIT)
4682         align = 8;
4683       else if (TYPE_ALIGN (type) > 32)
4684         align = 8;
4685       else
4686         align = 4;
4687
4688       t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4689                  build_int_2 (align - 1, 0));
4690       t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4691       t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4692       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4693
4694       /* Everything past the alignment is standard.  */
4695       return std_expand_builtin_va_arg (valist, type);
4696     }
4697 }
4698 \f
4699 /* Abort after printing out a specific insn.  */
4700
4701 static void
4702 abort_with_insn (insn, reason)
4703      rtx insn;
4704      const char *reason;
4705 {
4706   error (reason);
4707   debug_rtx (insn);
4708   abort ();
4709 }
4710 \f
4711 /* Set up the threshold for data to go into the small data area, instead
4712    of the normal data area, and detect any conflicts in the switches.  */
4713
4714 void
4715 override_options ()
4716 {
4717   register int i, start;
4718   register int regno;
4719   register enum machine_mode mode;
4720
4721   mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4722
4723   if (mips_section_threshold <= 0)
4724     target_flags &= ~MASK_GPOPT;
4725   else if (optimize)
4726     target_flags |= MASK_GPOPT;
4727
4728   /* If both single-float and soft-float are set, then clear the one that
4729      was set by TARGET_DEFAULT, leaving the one that was set by the
4730      user.  We assume here that the specs prevent both being set by the
4731      user. */
4732 #ifdef TARGET_DEFAULT
4733   if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4734     target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4735 #endif
4736
4737   /* Get the architectural level.  */
4738   if (mips_isa_string == 0)
4739     mips_isa = MIPS_ISA_DEFAULT;
4740
4741   else if (ISDIGIT (*mips_isa_string))
4742     {
4743       mips_isa = atoi (mips_isa_string);
4744       if (mips_isa == 16)
4745         {
4746           /* -mno-mips16 overrides -mips16.  */
4747           if (mips_no_mips16_string == NULL)
4748             {
4749               target_flags |= MASK_MIPS16;
4750               if (TARGET_64BIT)
4751                 mips_isa = 3;
4752               else
4753                 mips_isa = MIPS_ISA_DEFAULT;
4754             }
4755           else
4756             {
4757               mips_isa = MIPS_ISA_DEFAULT;
4758             }
4759         }
4760       else if (mips_isa < 1 || mips_isa > 4)
4761         {
4762           error ("-mips%d not supported", mips_isa);
4763           mips_isa = 1;
4764         }
4765     }
4766
4767   else
4768     {
4769       error ("bad value (%s) for -mips switch", mips_isa_string);
4770       mips_isa = 1;
4771     }
4772
4773 #ifdef MIPS_ABI_DEFAULT
4774   /* Get the ABI to use. */
4775   if (mips_abi_string == (char *) 0)
4776     mips_abi = MIPS_ABI_DEFAULT;
4777   else if (! strcmp (mips_abi_string, "32"))
4778     mips_abi = ABI_32;
4779   else if (! strcmp (mips_abi_string, "o64"))
4780     mips_abi = ABI_O64;
4781   else if (! strcmp (mips_abi_string, "n32"))
4782     mips_abi = ABI_N32;
4783   else if (! strcmp (mips_abi_string, "64"))
4784     mips_abi = ABI_64;
4785   else if (! strcmp (mips_abi_string, "eabi"))
4786     mips_abi = ABI_EABI;
4787   else
4788     error ("bad value (%s) for -mabi= switch", mips_abi_string);
4789
4790   /* A specified ISA defaults the ABI if it was not specified.  */
4791   if (mips_abi_string == 0 && mips_isa_string
4792       && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4793     {
4794       if (! ISA_HAS_64BIT_REGS)
4795         mips_abi = ABI_32;
4796       else
4797         mips_abi = ABI_64;
4798     }
4799
4800   /* A specified ABI defaults the ISA if it was not specified.  */
4801   else if (mips_isa_string == 0 && mips_abi_string
4802            && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4803     {
4804       if (mips_abi == ABI_32)
4805         mips_isa = 1;
4806       else if (mips_abi == ABI_N32)
4807         mips_isa = 3;
4808       else
4809         mips_isa = 4;
4810     }
4811
4812   /* If both ABI and ISA were specified, check for conflicts.  */
4813   else if (mips_isa_string && mips_abi_string)
4814     {
4815       if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4816                              || mips_abi == ABI_O64))
4817           || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
4818         error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4819     }
4820
4821   /* Override TARGET_DEFAULT if necessary.  */
4822   if (mips_abi == ABI_32)
4823     target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4824
4825   /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4826      then set the type sizes.  In the EABI in 64 bit mode, longs and
4827      pointers are 64 bits.  Likewise for the SGI Irix6 N64 ABI.  */
4828   if (mips_explicit_type_size_string == NULL
4829       && ((mips_abi == ABI_EABI && TARGET_64BIT)
4830           || mips_abi == ABI_64))
4831     target_flags |= MASK_LONG64;
4832
4833   /* ??? This doesn't work yet, so don't let people try to use it.  */
4834   if (mips_abi == ABI_32)
4835     error ("The -mabi=32 support does not work yet.");
4836
4837 #else
4838   if (mips_abi_string)
4839     error ("This target does not support the -mabi switch.");
4840 #endif
4841
4842 #ifdef MIPS_CPU_STRING_DEFAULT
4843   /* ??? There is a minor inconsistency here.  If the user specifies an ISA
4844      greater than that supported by the default processor, then the user gets
4845      an error.  Normally, the compiler will just default to the base level cpu
4846      for the indicated isa.  */
4847   if (mips_arch_string == 0)
4848     mips_arch_string = MIPS_CPU_STRING_DEFAULT;
4849   if (mips_tune_string == 0)
4850     mips_tune_string = MIPS_CPU_STRING_DEFAULT;
4851 #endif
4852
4853   /* Identify the processor type.  */
4854
4855   if (mips_cpu_string != 0)
4856     {
4857       mips_cpu = mips_parse_cpu (mips_cpu_string);
4858       if (mips_cpu == PROCESSOR_DEFAULT)
4859         {
4860           error ("bad value (%s) for -mcpu= switch", mips_arch_string);
4861           mips_cpu_string = "default";
4862         }
4863       mips_arch = mips_cpu;
4864       mips_tune = mips_cpu;
4865     }
4866
4867   if (mips_arch_string == 0
4868       || ! strcmp (mips_arch_string, "default")
4869       || ! strcmp (mips_arch_string, "DEFAULT"))
4870     {
4871       switch (mips_isa)
4872         {
4873         default:
4874           mips_arch_string = "3000";
4875           mips_arch = PROCESSOR_R3000;
4876           break;
4877         case 2:
4878           mips_arch_string = "6000";
4879           mips_arch = PROCESSOR_R6000;
4880           break;
4881         case 3:
4882           mips_arch_string = "4000";
4883           mips_arch = PROCESSOR_R4000;
4884           break;
4885         case 4:
4886           mips_arch_string = "8000";
4887           mips_arch = PROCESSOR_R8000;
4888           break;
4889         }
4890     }
4891   else
4892     {
4893       mips_arch = mips_parse_cpu (mips_arch_string);
4894       if (mips_arch == PROCESSOR_DEFAULT)
4895         {
4896           error ("bad value (%s) for -march= switch", mips_arch_string);
4897           mips_arch_string = "default";
4898         }
4899     }
4900   if (mips_tune_string == 0
4901       || ! strcmp (mips_tune_string, "default")
4902       || ! strcmp (mips_tune_string, "DEFAULT"))
4903     {
4904       if (mips_arch != PROCESSOR_DEFAULT)
4905         mips_tune == mips_arch;
4906       else
4907       switch (mips_isa)
4908         {
4909         default:
4910           mips_tune_string = "3000";
4911           mips_tune = PROCESSOR_R3000;
4912           break;
4913         case 2:
4914           mips_tune_string = "6000";
4915           mips_tune = PROCESSOR_R6000;
4916           break;
4917         case 3:
4918           mips_tune_string = "4000";
4919           mips_tune = PROCESSOR_R4000;
4920           break;
4921         case 4:
4922           mips_tune_string = "8000";
4923           mips_tune = PROCESSOR_R8000;
4924           break;
4925         }
4926
4927     }
4928   else
4929     {
4930        mips_tune = mips_parse_cpu (mips_tune_string);
4931       if (mips_tune == PROCESSOR_DEFAULT)
4932         {
4933           error ("bad value (%s) for -mtune= switch", mips_tune_string);
4934           mips_tune_string = "default";
4935         }
4936     }
4937
4938    /* Handle processor configuration based on architecture.  */
4939    if (TARGET_MIPS4100 || TARGET_MIPS3900)
4940      target_flags |= MASK_SOFT_FLOAT;
4941
4942
4943   if ((mips_arch == PROCESSOR_R3000 && (mips_isa != 1))
4944       || (mips_arch == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
4945       || ((mips_arch == PROCESSOR_R4000
4946            || mips_arch == PROCESSOR_R4100
4947            || mips_arch == PROCESSOR_R4300
4948            || mips_arch == PROCESSOR_R4600
4949            || mips_arch == PROCESSOR_R4650)
4950           && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
4951     error ("-march=%s does not support -mips%d", mips_arch_string, mips_isa);
4952
4953   /* make sure sizes of ints/longs/etc. are ok */
4954   if (! ISA_HAS_64BIT_REGS)
4955     {
4956       if (TARGET_FLOAT64)
4957         {
4958           error ("-mips%d does not support 64 bit fp registers", mips_isa);
4959           target_flags &= ~ MASK_FLOAT64;
4960         }
4961
4962       else if (TARGET_64BIT)
4963         {
4964           error ("-mips%d does not support 64 bit gp registers", mips_isa);
4965           target_flags &= ~MASK_64BIT;
4966         }
4967     }
4968
4969   if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4970     flag_pcc_struct_return = 0;
4971
4972   /* Tell halfpic.c that we have half-pic code if we do.  */
4973   if (TARGET_HALF_PIC)
4974     HALF_PIC_INIT ();
4975
4976   /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
4977      to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
4978   /* ??? -non_shared turns off pic code generation, but this is not
4979      implemented.  */
4980   if (TARGET_ABICALLS)
4981     {
4982       mips_abicalls = MIPS_ABICALLS_YES;
4983       flag_pic = 1;
4984       if (mips_section_threshold > 0)
4985         warning ("-G is incompatible with PIC code which is the default");
4986     }
4987   else
4988     mips_abicalls = MIPS_ABICALLS_NO;
4989
4990   /* -membedded-pic is a form of PIC code suitable for embedded
4991      systems.  All calls are made using PC relative addressing, and
4992      all data is addressed using the $gp register.  This requires gas,
4993      which does most of the work, and GNU ld, which automatically
4994      expands PC relative calls which are out of range into a longer
4995      instruction sequence.  All gcc really does differently is
4996      generate a different sequence for a switch.  */
4997   if (TARGET_EMBEDDED_PIC)
4998     {
4999       flag_pic = 1;
5000       if (TARGET_ABICALLS)
5001         warning ("-membedded-pic and -mabicalls are incompatible");
5002
5003       if (g_switch_set)
5004         warning ("-G and -membedded-pic are incompatible");
5005
5006       /* Setting mips_section_threshold is not required, because gas
5007          will force everything to be GP addressable anyhow, but
5008          setting it will cause gcc to make better estimates of the
5009          number of instructions required to access a particular data
5010          item.  */
5011       mips_section_threshold = 0x7fffffff;
5012     }
5013
5014   /* This optimization requires a linker that can support a R_MIPS_LO16
5015      relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5016      GNU ld has this support, but not all other MIPS linkers do, so we enable
5017      this optimization only if the user requests it, or if GNU ld is the
5018      standard linker for this configuration.  */
5019   /* ??? This does not work when target addresses are DImode.
5020      This is because we are missing DImode high/lo_sum patterns.  */
5021   if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5022       && Pmode == SImode)
5023     mips_split_addresses = 1;
5024   else
5025     mips_split_addresses = 0;
5026
5027   /* -mrnames says to use the MIPS software convention for register
5028      names instead of the hardware names (ie, $a0 instead of $4).
5029      We do this by switching the names in mips_reg_names, which the
5030      reg_names points into via the REGISTER_NAMES macro.  */
5031
5032   if (TARGET_NAME_REGS)
5033     memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5034
5035   /* When compiling for the mips16, we can not use floating point.  We
5036      record the original hard float value in mips16_hard_float.  */
5037   if (TARGET_MIPS16)
5038     {
5039       if (TARGET_SOFT_FLOAT)
5040         mips16_hard_float = 0;
5041       else
5042         mips16_hard_float = 1;
5043       target_flags |= MASK_SOFT_FLOAT;
5044
5045       /* Don't run the scheduler before reload, since it tends to
5046          increase register pressure.  */
5047       flag_schedule_insns = 0;
5048     }
5049
5050   /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5051      to avoid using up another bit in target_flags.  */
5052   if (mips_entry_string != NULL)
5053     {
5054       if (*mips_entry_string != '\0')
5055         error ("Invalid option `entry%s'", mips_entry_string);
5056
5057       if (! TARGET_MIPS16)
5058         warning ("-mentry is only meaningful with -mips-16");
5059       else
5060         mips_entry = 1;
5061     }
5062
5063   /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5064      attributes can access it.  */
5065   if (TARGET_MIPS16)
5066     mips16 = 1;
5067   else
5068     mips16 = 0;
5069
5070   /* Initialize the high and low values for legitimate floating point
5071      constants.  Rather than trying to get the accuracy down to the
5072      last bit, just use approximate ranges.  */
5073   dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5074   dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5075   sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5076   sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5077
5078   mips_print_operand_punct['?'] = 1;
5079   mips_print_operand_punct['#'] = 1;
5080   mips_print_operand_punct['&'] = 1;
5081   mips_print_operand_punct['!'] = 1;
5082   mips_print_operand_punct['*'] = 1;
5083   mips_print_operand_punct['@'] = 1;
5084   mips_print_operand_punct['.'] = 1;
5085   mips_print_operand_punct['('] = 1;
5086   mips_print_operand_punct[')'] = 1;
5087   mips_print_operand_punct['['] = 1;
5088   mips_print_operand_punct[']'] = 1;
5089   mips_print_operand_punct['<'] = 1;
5090   mips_print_operand_punct['>'] = 1;
5091   mips_print_operand_punct['{'] = 1;
5092   mips_print_operand_punct['}'] = 1;
5093   mips_print_operand_punct['^'] = 1;
5094   mips_print_operand_punct['$'] = 1;
5095   mips_print_operand_punct['+'] = 1;
5096   mips_print_operand_punct['~'] = 1;
5097
5098   mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5099   mips_char_to_class['e'] = M16_NA_REGS;
5100   mips_char_to_class['t'] = T_REG;
5101   mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5102   mips_char_to_class['h'] = HI_REG;
5103   mips_char_to_class['l'] = LO_REG;
5104   mips_char_to_class['a'] = HILO_REG;
5105   mips_char_to_class['x'] = MD_REGS;
5106   mips_char_to_class['b'] = ALL_REGS;
5107   mips_char_to_class['y'] = GR_REGS;
5108   mips_char_to_class['z'] = ST_REGS;
5109
5110   /* Set up array to map GCC register number to debug register number.
5111      Ignore the special purpose register numbers.  */
5112
5113   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5114     mips_dbx_regno[i] = -1;
5115
5116   start = GP_DBX_FIRST - GP_REG_FIRST;
5117   for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5118     mips_dbx_regno[i] = i + start;
5119
5120   start = FP_DBX_FIRST - FP_REG_FIRST;
5121   for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5122     mips_dbx_regno[i] = i + start;
5123
5124   /* Set up array giving whether a given register can hold a given mode.
5125      At present, restrict ints from being in FP registers, because reload
5126      is a little enthusiastic about storing extra values in FP registers,
5127      and this is not good for things like OS kernels.  Also, due to the
5128      mandatory delay, it is as fast to load from cached memory as to move
5129      from the FP register.  */
5130
5131   for (mode = VOIDmode;
5132        mode != MAX_MACHINE_MODE;
5133        mode = (enum machine_mode) ((int)mode + 1))
5134     {
5135       register int size              = GET_MODE_SIZE (mode);
5136       register enum mode_class class = GET_MODE_CLASS (mode);
5137
5138       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5139         {
5140           register int temp;
5141
5142           if (mode == CCmode)
5143             {
5144               if (! ISA_HAS_8CC)
5145                 temp = (regno == FPSW_REGNUM);
5146               else
5147                 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5148                         || FP_REG_P (regno));
5149             }
5150
5151           else if (GP_REG_P (regno))
5152             temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5153
5154           else if (FP_REG_P (regno))
5155             temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
5156                     && (class == MODE_FLOAT
5157                         || class == MODE_COMPLEX_FLOAT
5158                         || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5159                     && (! TARGET_SINGLE_FLOAT || size <= 4));
5160
5161           else if (MD_REG_P (regno))
5162             temp = (class == MODE_INT
5163                     && (size <= UNITS_PER_WORD
5164                         || (regno == MD_REG_FIRST
5165                             && size == 2 * UNITS_PER_WORD)));
5166
5167           else
5168             temp = 0;
5169
5170           mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5171         }
5172     }
5173
5174   /* Save GPR registers in word_mode sized hunks.  word_mode hasn't been
5175      initialized yet, so we can't use that here.  */
5176   gpr_mode = TARGET_64BIT ? DImode : SImode;
5177
5178   /* Provide default values for align_* for 64-bit targets.  */
5179   if (TARGET_64BIT && !TARGET_MIPS16)
5180     {
5181       if (align_loops == 0)
5182         align_loops = 8;
5183       if (align_jumps == 0)
5184         align_jumps = 8;
5185       if (align_functions == 0)
5186         align_functions = 8;
5187     }
5188
5189   /* Register global variables with the garbage collector.  */
5190   mips_add_gc_roots ();
5191 }
5192
5193 /* On the mips16, we want to allocate $24 (T_REG) before other
5194    registers for instructions for which it is possible.  This helps
5195    avoid shuffling registers around in order to set up for an xor,
5196    encouraging the compiler to use a cmp instead.  */
5197
5198 void
5199 mips_order_regs_for_local_alloc ()
5200 {
5201   register int i;
5202
5203   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5204     reg_alloc_order[i] = i;
5205
5206   if (TARGET_MIPS16)
5207     {
5208       /* It really doesn't matter where we put register 0, since it is
5209          a fixed register anyhow.  */
5210       reg_alloc_order[0] = 24;
5211       reg_alloc_order[24] = 0;
5212     }
5213 }
5214
5215 \f
5216 /* The MIPS debug format wants all automatic variables and arguments
5217    to be in terms of the virtual frame pointer (stack pointer before
5218    any adjustment in the function), while the MIPS 3.0 linker wants
5219    the frame pointer to be the stack pointer after the initial
5220    adjustment.  So, we do the adjustment here.  The arg pointer (which
5221    is eliminated) points to the virtual frame pointer, while the frame
5222    pointer (which may be eliminated) points to the stack pointer after
5223    the initial adjustments.  */
5224
5225 HOST_WIDE_INT
5226 mips_debugger_offset (addr, offset)
5227      rtx addr;
5228      HOST_WIDE_INT offset;
5229 {
5230   rtx offset2 = const0_rtx;
5231   rtx reg = eliminate_constant_term (addr, &offset2);
5232
5233   if (offset == 0)
5234     offset = INTVAL (offset2);
5235
5236   if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5237       || reg == hard_frame_pointer_rtx)
5238     {
5239       HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5240                                   ? compute_frame_size (get_frame_size ())
5241                                   : current_frame_info.total_size;
5242
5243       /* MIPS16 frame is smaller */
5244       if (frame_pointer_needed && TARGET_MIPS16)
5245         frame_size -= current_function_outgoing_args_size;
5246
5247       offset = offset - frame_size;
5248     }
5249
5250   /* sdbout_parms does not want this to crash for unrecognized cases.  */
5251 #if 0
5252   else if (reg != arg_pointer_rtx)
5253     abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
5254 #endif
5255
5256   return offset;
5257 }
5258 \f
5259 /* A C compound statement to output to stdio stream STREAM the
5260    assembler syntax for an instruction operand X.  X is an RTL
5261    expression.
5262
5263    CODE is a value that can be used to specify one of several ways
5264    of printing the operand.  It is used when identical operands
5265    must be printed differently depending on the context.  CODE
5266    comes from the `%' specification that was used to request
5267    printing of the operand.  If the specification was just `%DIGIT'
5268    then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5269    is the ASCII code for LTR.
5270
5271    If X is a register, this macro should print the register's name.
5272    The names can be found in an array `reg_names' whose type is
5273    `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
5274
5275    When the machine description has a specification `%PUNCT' (a `%'
5276    followed by a punctuation character), this macro is called with
5277    a null pointer for X and the punctuation character for CODE.
5278
5279    The MIPS specific codes are:
5280
5281    'X'  X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5282    'x'  X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5283    'd'  output integer constant in decimal,
5284    'z'  if the operand is 0, use $0 instead of normal operand.
5285    'D'  print second register of double-word register operand.
5286    'L'  print low-order register of double-word register operand.
5287    'M'  print high-order register of double-word register operand.
5288    'C'  print part of opcode for a branch condition.
5289    'F'  print part of opcode for a floating-point branch condition.
5290    'N'  print part of opcode for a branch condition, inverted.
5291    'W'  print part of opcode for a floating-point branch condition, inverted.
5292    'S'  X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5293    'B'  print 'z' for EQ, 'n' for NE
5294    'b'  print 'n' for EQ, 'z' for NE
5295    'T'  print 'f' for EQ, 't' for NE
5296    't'  print 't' for EQ, 'f' for NE
5297    'Z'  print register and a comma, but print nothing for $fcc0
5298    '('  Turn on .set noreorder
5299    ')'  Turn on .set reorder
5300    '['  Turn on .set noat
5301    ']'  Turn on .set at
5302    '<'  Turn on .set nomacro
5303    '>'  Turn on .set macro
5304    '{'  Turn on .set volatile (not GAS)
5305    '}'  Turn on .set novolatile (not GAS)
5306    '&'  Turn on .set noreorder if filling delay slots
5307    '*'  Turn on both .set noreorder and .set nomacro if filling delay slots
5308    '!'  Turn on .set nomacro if filling delay slots
5309    '#'  Print nop if in a .set noreorder section.
5310    '?'  Print 'l' if we are to use a branch likely instead of normal branch.
5311    '@'  Print the name of the assembler temporary register (at or $1).
5312    '.'  Print the name of the register with a hard-wired zero (zero or $0).
5313    '^'  Print the name of the pic call-through register (t9 or $25).
5314    '$'  Print the name of the stack pointer register (sp or $29).
5315    '+'  Print the name of the gp register (gp or $28).
5316    '~'  Output an branch alignment to LABEL_ALIGN(NULL).  */
5317
5318 void
5319 print_operand (file, op, letter)
5320      FILE *file;                /* file to write to */
5321      rtx op;                    /* operand to print */
5322      int letter;                /* %<letter> or 0 */
5323 {
5324   register enum rtx_code code;
5325
5326   if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5327     {
5328       switch (letter)
5329         {
5330         case '?':
5331           if (mips_branch_likely)
5332             putc ('l', file);
5333           break;
5334
5335         case '@':
5336           fputs (reg_names [GP_REG_FIRST + 1], file);
5337           break;
5338
5339         case '^':
5340           fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5341           break;
5342
5343         case '.':
5344           fputs (reg_names [GP_REG_FIRST + 0], file);
5345           break;
5346
5347         case '$':
5348           fputs (reg_names[STACK_POINTER_REGNUM], file);
5349           break;
5350
5351         case '+':
5352           fputs (reg_names[GP_REG_FIRST + 28], file);
5353           break;
5354
5355         case '&':
5356           if (final_sequence != 0 && set_noreorder++ == 0)
5357             fputs (".set\tnoreorder\n\t", file);
5358           break;
5359
5360         case '*':
5361           if (final_sequence != 0)
5362             {
5363               if (set_noreorder++ == 0)
5364                 fputs (".set\tnoreorder\n\t", file);
5365
5366               if (set_nomacro++ == 0)
5367                 fputs (".set\tnomacro\n\t", file);
5368             }
5369           break;
5370
5371         case '!':
5372           if (final_sequence != 0 && set_nomacro++ == 0)
5373             fputs ("\n\t.set\tnomacro", file);
5374           break;
5375
5376         case '#':
5377           if (set_noreorder != 0)
5378             fputs ("\n\tnop", file);
5379           else if (TARGET_STATS)
5380             fputs ("\n\t#nop", file);
5381
5382           break;
5383
5384         case '(':
5385           if (set_noreorder++ == 0)
5386             fputs (".set\tnoreorder\n\t", file);
5387           break;
5388
5389         case ')':
5390           if (set_noreorder == 0)
5391             error ("internal error: %%) found without a %%( in assembler pattern");
5392
5393           else if (--set_noreorder == 0)
5394             fputs ("\n\t.set\treorder", file);
5395
5396           break;
5397
5398         case '[':
5399           if (set_noat++ == 0)
5400             fputs (".set\tnoat\n\t", file);
5401           break;
5402
5403         case ']':
5404           if (set_noat == 0)
5405             error ("internal error: %%] found without a %%[ in assembler pattern");
5406           else if (--set_noat == 0)
5407             fputs ("\n\t.set\tat", file);
5408
5409           break;
5410
5411         case '<':
5412           if (set_nomacro++ == 0)
5413             fputs (".set\tnomacro\n\t", file);
5414           break;
5415
5416         case '>':
5417           if (set_nomacro == 0)
5418             error ("internal error: %%> found without a %%< in assembler pattern");
5419           else if (--set_nomacro == 0)
5420             fputs ("\n\t.set\tmacro", file);
5421
5422           break;
5423
5424         case '{':
5425           if (set_volatile++ == 0)
5426             fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5427           break;
5428
5429         case '}':
5430           if (set_volatile == 0)
5431             error ("internal error: %%} found without a %%{ in assembler pattern");
5432           else if (--set_volatile == 0)
5433             fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5434
5435           break;
5436
5437         case '~':
5438           {
5439             if (align_labels_log > 0)
5440               ASM_OUTPUT_ALIGN (file, align_labels_log);
5441           }
5442         break;
5443
5444         default:
5445           error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5446           break;
5447         }
5448
5449       return;
5450     }
5451
5452   if (! op)
5453     {
5454       error ("PRINT_OPERAND null pointer");
5455       return;
5456     }
5457
5458   code = GET_CODE (op);
5459
5460   if (code == SIGN_EXTEND)
5461     op = XEXP (op, 0), code = GET_CODE (op);
5462
5463   if (letter == 'C')
5464     switch (code)
5465       {
5466       case EQ:  fputs ("eq",  file); break;
5467       case NE:  fputs ("ne",  file); break;
5468       case GT:  fputs ("gt",  file); break;
5469       case GE:  fputs ("ge",  file); break;
5470       case LT:  fputs ("lt",  file); break;
5471       case LE:  fputs ("le",  file); break;
5472       case GTU: fputs ("gtu", file); break;
5473       case GEU: fputs ("geu", file); break;
5474       case LTU: fputs ("ltu", file); break;
5475       case LEU: fputs ("leu", file); break;
5476       default:
5477         abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5478       }
5479
5480   else if (letter == 'N')
5481     switch (code)
5482       {
5483       case EQ:  fputs ("ne",  file); break;
5484       case NE:  fputs ("eq",  file); break;
5485       case GT:  fputs ("le",  file); break;
5486       case GE:  fputs ("lt",  file); break;
5487       case LT:  fputs ("ge",  file); break;
5488       case LE:  fputs ("gt",  file); break;
5489       case GTU: fputs ("leu", file); break;
5490       case GEU: fputs ("ltu", file); break;
5491       case LTU: fputs ("geu", file); break;
5492       case LEU: fputs ("gtu", file); break;
5493       default:
5494         abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5495       }
5496
5497   else if (letter == 'F')
5498     switch (code)
5499       {
5500       case EQ: fputs ("c1f", file); break;
5501       case NE: fputs ("c1t", file); break;
5502       default:
5503         abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5504       }
5505
5506   else if (letter == 'W')
5507     switch (code)
5508       {
5509       case EQ: fputs ("c1t", file); break;
5510       case NE: fputs ("c1f", file); break;
5511       default:
5512         abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5513       }
5514
5515   else if (letter == 'S')
5516     {
5517       char buffer[100];
5518
5519       ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5520       assemble_name (file, buffer);
5521     }
5522
5523   else if (letter == 'Z')
5524     {
5525       register int regnum;
5526
5527       if (code != REG)
5528         abort ();
5529
5530       regnum = REGNO (op);
5531       if (! ST_REG_P (regnum))
5532         abort ();
5533
5534       if (regnum != ST_REG_FIRST)
5535         fprintf (file, "%s,", reg_names[regnum]);
5536     }
5537
5538   else if (code == REG || code == SUBREG)
5539     {
5540       register int regnum;
5541
5542       if (code == REG)
5543         regnum = REGNO (op);
5544       else
5545         regnum = true_regnum (op);
5546
5547       if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5548           || (letter == 'L' && WORDS_BIG_ENDIAN)
5549           || letter == 'D')
5550         regnum++;
5551
5552       fprintf (file, "%s", reg_names[regnum]);
5553     }
5554
5555   else if (code == MEM)
5556     output_address (XEXP (op, 0));
5557
5558   else if (code == CONST_DOUBLE
5559            && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5560     {
5561       REAL_VALUE_TYPE d;
5562       char s[30];
5563
5564       REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5565       REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5566       fprintf (file, s);
5567     }
5568
5569   else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5570     fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5571
5572   else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5573     fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5574
5575   else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5576     fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5577
5578   else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5579     fputs (reg_names[GP_REG_FIRST], file);
5580
5581   else if (letter == 'd' || letter == 'x' || letter == 'X')
5582     output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5583
5584   else if (letter == 'B')
5585     fputs (code == EQ ? "z" : "n", file);
5586   else if (letter == 'b')
5587     fputs (code == EQ ? "n" : "z", file);
5588   else if (letter == 'T')
5589     fputs (code == EQ ? "f" : "t", file);
5590   else if (letter == 't')
5591     fputs (code == EQ ? "t" : "f", file);
5592
5593   else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5594     {
5595       /* This case arises on the mips16; see mips16_gp_pseudo_reg.  */
5596       print_operand (file, XEXP (op, 0), letter);
5597     }
5598
5599   else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5600     {
5601       fputs ("%gprel(", file);
5602       mips16_output_gp_offset (file, op);
5603       fputs (")", file);
5604     }
5605
5606   else
5607     output_addr_const (file, op);
5608 }
5609 \f
5610 /* A C compound statement to output to stdio stream STREAM the
5611    assembler syntax for an instruction operand that is a memory
5612    reference whose address is ADDR.  ADDR is an RTL expression.
5613
5614    On some machines, the syntax for a symbolic address depends on
5615    the section that the address refers to.  On these machines,
5616    define the macro `ENCODE_SECTION_INFO' to store the information
5617    into the `symbol_ref', and then check for it here.  */
5618
5619 void
5620 print_operand_address (file, addr)
5621      FILE *file;
5622      rtx addr;
5623 {
5624   if (!addr)
5625     error ("PRINT_OPERAND_ADDRESS, null pointer");
5626
5627   else
5628     switch (GET_CODE (addr))
5629       {
5630       case REG:
5631         if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5632           abort_with_insn (addr, "Arg pointer not eliminated.");
5633
5634         fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5635         break;
5636
5637       case LO_SUM:
5638         {
5639           register rtx arg0 = XEXP (addr, 0);
5640           register rtx arg1 = XEXP (addr, 1);
5641
5642           if (! mips_split_addresses)
5643             abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5644
5645           if (GET_CODE (arg0) != REG)
5646             abort_with_insn (addr,
5647                              "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5648
5649           fprintf (file, "%%lo(");
5650           print_operand_address (file, arg1);
5651           fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5652         }
5653         break;
5654
5655       case PLUS:
5656         {
5657           register rtx reg = 0;
5658           register rtx offset = 0;
5659           register rtx arg0 = XEXP (addr, 0);
5660           register rtx arg1 = XEXP (addr, 1);
5661
5662           if (GET_CODE (arg0) == REG)
5663             {
5664               reg = arg0;
5665               offset = arg1;
5666               if (GET_CODE (offset) == REG)
5667                 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5668             }
5669
5670           else if (GET_CODE (arg1) == REG)
5671               reg = arg1, offset = arg0;
5672           else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5673             {
5674               output_addr_const (file, addr);
5675               break;
5676             }
5677           else
5678             abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5679
5680           if (! CONSTANT_P (offset))
5681             abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5682
5683           if (REGNO (reg) == ARG_POINTER_REGNUM)
5684             abort_with_insn (addr, "Arg pointer not eliminated.");
5685
5686           if (TARGET_MIPS16
5687               && GET_CODE (offset) == CONST
5688               && mips16_gp_offset_p (offset))
5689             {
5690               fputs ("%gprel(", file);
5691               mips16_output_gp_offset (file, offset);
5692               fputs (")", file);
5693             }
5694           else
5695             output_addr_const (file, offset);
5696           fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5697         }
5698         break;
5699
5700       case LABEL_REF:
5701       case SYMBOL_REF:
5702       case CONST_INT:
5703       case CONST:
5704         output_addr_const (file, addr);
5705         break;
5706
5707       default:
5708         abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5709         break;
5710     }
5711 }
5712
5713 \f
5714 /* If optimizing for the global pointer, keep track of all of the externs, so
5715    that at the end of the file, we can emit the appropriate .extern
5716    declaration for them, before writing out the text section.  We assume all
5717    names passed to us are in the permanent obstack, so they will be valid at
5718    the end of the compilation.
5719
5720    If we have -G 0, or the extern size is unknown, or the object is in a user
5721    specified section that is not .sbss/.sdata, don't bother emitting the
5722    .externs.  In the case of user specified sections this behaviour is
5723    required as otherwise GAS will think the object lives in .sbss/.sdata.  */
5724
5725 int
5726 mips_output_external (file, decl, name)
5727      FILE *file ATTRIBUTE_UNUSED;
5728      tree decl;
5729      const char *name;
5730 {
5731   register struct extern_list *p;
5732   int len;
5733   tree section_name;
5734
5735   if (TARGET_GP_OPT
5736       && TREE_CODE (decl) != FUNCTION_DECL
5737       && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5738       && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5739           || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5740           || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5741     {
5742       p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5743       p->next = extern_head;
5744       p->name = name;
5745       p->size = len;
5746       extern_head = p;
5747     }
5748
5749 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5750   if (TREE_CODE (decl) == FUNCTION_DECL
5751       /* ??? Don't include alloca, since gcc will always expand it
5752          inline.  If we don't do this, the C++ library fails to build.  */
5753       && strcmp (name, "alloca")
5754       /* ??? Don't include __builtin_next_arg, because then gcc will not
5755          bootstrap under Irix 5.1.  */
5756       && strcmp (name, "__builtin_next_arg"))
5757     {
5758       p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5759       p->next = extern_head;
5760       p->name = name;
5761       p->size = -1;
5762       extern_head = p;
5763     }
5764 #endif
5765
5766   return 0;
5767 }
5768
5769 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5770 int
5771 mips_output_external_libcall (file, name)
5772      FILE *file;
5773      const char *name;
5774 {
5775   register struct extern_list *p;
5776
5777   p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5778   p->next = extern_head;
5779   p->name = name;
5780   p->size = -1;
5781   extern_head = p;
5782
5783   return 0;
5784 }
5785 #endif
5786 \f
5787 /* Compute a string to use as a temporary file name.  */
5788
5789 static FILE *
5790 mips_make_temp_file ()
5791 {
5792   FILE *stream;
5793
5794   temp_filename = make_temp_file (0);
5795   stream = fopen (temp_filename, "w+");
5796   if (!stream)
5797     fatal_io_error ("can't open %s", temp_filename);
5798   return stream;
5799 }
5800 \f
5801 /* Emit a new filename to a stream.  If this is MIPS ECOFF, watch out
5802    for .file's that start within a function.  If we are smuggling stabs, try to
5803    put out a MIPS ECOFF file and a stab.  */
5804
5805 void
5806 mips_output_filename (stream, name)
5807      FILE *stream;
5808      const char *name;
5809 {
5810   static int first_time = 1;
5811   char ltext_label_name[100];
5812
5813   if (first_time)
5814     {
5815       first_time = 0;
5816       SET_FILE_NUMBER ();
5817       current_function_file = name;
5818       ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5819       /* This tells mips-tfile that stabs will follow.  */
5820       if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5821         fprintf (stream, "\t#@stabs\n");
5822     }
5823
5824   else if (write_symbols == DBX_DEBUG)
5825     {
5826       ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5827       fprintf (stream, "%s", ASM_STABS_OP);
5828       output_quoted_string (stream, name);
5829       fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
5830     }
5831
5832   else if (name != current_function_file
5833       && strcmp (name, current_function_file) != 0)
5834     {
5835       if (inside_function && !TARGET_GAS)
5836         {
5837           if (!file_in_function_warning)
5838             {
5839               file_in_function_warning = 1;
5840               ignore_line_number = 1;
5841               warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5842             }
5843         }
5844       else
5845         {
5846           SET_FILE_NUMBER ();
5847           current_function_file = name;
5848           ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5849         }
5850     }
5851 }
5852 \f
5853 /* Emit a linenumber.  For encapsulated stabs, we need to put out a stab
5854    as well as a .loc, since it is possible that MIPS ECOFF might not be
5855    able to represent the location for inlines that come from a different
5856    file.  */
5857
5858 void
5859 mips_output_lineno (stream, line)
5860      FILE *stream;
5861      int line;
5862 {
5863   if (write_symbols == DBX_DEBUG)
5864     {
5865       ++sym_lineno;
5866       fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5867                LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5868                LOCAL_LABEL_PREFIX, sym_lineno);
5869     }
5870
5871   else
5872     {
5873       fprintf (stream, "\n\t%s.loc\t%d %d\n",
5874                (ignore_line_number) ? "#" : "",
5875                num_source_filenames, line);
5876
5877       LABEL_AFTER_LOC (stream);
5878     }
5879 }
5880 \f
5881 /* Output an ASCII string, in a space-saving way.  */
5882
5883 void
5884 mips_output_ascii (stream, string_param, len)
5885      FILE *stream;
5886      const char *string_param;
5887      size_t len;
5888 {
5889   size_t i;
5890   int cur_pos = 17;
5891   register const unsigned char *string =
5892     (const unsigned char *)string_param;
5893
5894   fprintf (stream, "\t.ascii\t\"");
5895   for (i = 0; i < len; i++)
5896     {
5897       register int c = string[i];
5898
5899       switch (c)
5900         {
5901         case '\"':
5902         case '\\':
5903           putc ('\\', stream);
5904           putc (c, stream);
5905           cur_pos += 2;
5906           break;
5907
5908         case TARGET_NEWLINE:
5909           fputs ("\\n", stream);
5910           if (i+1 < len
5911               && (((c = string[i+1]) >= '\040' && c <= '~')
5912                   || c == TARGET_TAB))
5913             cur_pos = 32767;            /* break right here */
5914           else
5915             cur_pos += 2;
5916           break;
5917
5918         case TARGET_TAB:
5919           fputs ("\\t", stream);
5920           cur_pos += 2;
5921           break;
5922
5923         case TARGET_FF:
5924           fputs ("\\f", stream);
5925           cur_pos += 2;
5926           break;
5927
5928         case TARGET_BS:
5929           fputs ("\\b", stream);
5930           cur_pos += 2;
5931           break;
5932
5933         case TARGET_CR:
5934           fputs ("\\r", stream);
5935           cur_pos += 2;
5936           break;
5937
5938         default:
5939           if (c >= ' ' && c < 0177)
5940             {
5941               putc (c, stream);
5942               cur_pos++;
5943             }
5944           else
5945             {
5946               fprintf (stream, "\\%03o", c);
5947               cur_pos += 4;
5948             }
5949         }
5950
5951       if (cur_pos > 72 && i+1 < len)
5952         {
5953           cur_pos = 17;
5954           fprintf (stream, "\"\n\t.ascii\t\"");
5955         }
5956     }
5957   fprintf (stream, "\"\n");
5958 }
5959 \f
5960 /* If defined, a C statement to be executed just prior to the output of
5961    assembler code for INSN, to modify the extracted operands so they will be
5962    output differently.
5963
5964    Here the argument OPVEC is the vector containing the operands extracted
5965    from INSN, and NOPERANDS is the number of elements of the vector which
5966    contain meaningful data for this insn.  The contents of this vector are
5967    what will be used to convert the insn template into assembler code, so you
5968    can change the assembler output by changing the contents of the vector.
5969
5970    We use it to check if the current insn needs a nop in front of it because
5971    of load delays, and also to update the delay slot statistics.  */
5972
5973 /* ??? There is no real need for this function, because it never actually
5974    emits a NOP anymore.  */
5975
5976 void
5977 final_prescan_insn (insn, opvec, noperands)
5978      rtx insn;
5979      rtx opvec[] ATTRIBUTE_UNUSED;
5980      int noperands ATTRIBUTE_UNUSED;
5981 {
5982   if (dslots_number_nops > 0)
5983     {
5984       rtx pattern = PATTERN (insn);
5985       int length = get_attr_length (insn);
5986
5987       /* Do we need to emit a NOP? */
5988       if (length == 0
5989           || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg,  pattern))
5990           || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5991           || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5992           || (mips_load_reg4 != 0
5993               && reg_mentioned_p (mips_load_reg4, pattern)))
5994         fputs ("\t#nop\n", asm_out_file);
5995
5996       else
5997         dslots_load_filled++;
5998
5999       while (--dslots_number_nops > 0)
6000         fputs ("\t#nop\n", asm_out_file);
6001
6002       mips_load_reg = 0;
6003       mips_load_reg2 = 0;
6004       mips_load_reg3 = 0;
6005       mips_load_reg4 = 0;
6006     }
6007
6008   if (TARGET_STATS
6009       && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6010     dslots_jump_total++;
6011 }
6012 \f
6013 /* Output at beginning of assembler file.
6014
6015    If we are optimizing to use the global pointer, create a temporary file to
6016    hold all of the text stuff, and write it out to the end. This is needed
6017    because the MIPS assembler is evidently one pass, and if it hasn't seen the
6018    relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6019    processed, it generates a two instruction sequence.  */
6020
6021 void
6022 mips_asm_file_start (stream)
6023      FILE *stream;
6024 {
6025   ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6026
6027   /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6028      inside of a .set noreorder section jumps to a label outside of the .set
6029      noreorder section.  Revision 2.20 just set nobopt silently rather than
6030      fixing the bug.  */
6031
6032   if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6033     fprintf (stream, "\t.set\tnobopt\n");
6034
6035   /* Generate the pseudo ops that System V.4 wants.  */
6036 #ifndef ABICALLS_ASM_OP
6037 #define ABICALLS_ASM_OP "\t.abicalls"
6038 #endif
6039   if (TARGET_ABICALLS)
6040     /* ??? but do not want this (or want pic0) if -non-shared? */
6041     fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6042
6043   if (TARGET_MIPS16)
6044     fprintf (stream, "\t.set\tmips16\n");
6045
6046   /* Start a section, so that the first .popsection directive is guaranteed
6047      to have a previously defined section to pop back to.  */
6048   if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
6049     fprintf (stream, "\t.section\t.text\n");
6050
6051   /* This code exists so that we can put all externs before all symbol
6052      references.  This is necessary for the MIPS assembler's global pointer
6053      optimizations to work.  */
6054   if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
6055     {
6056       asm_out_data_file = stream;
6057       asm_out_text_file = mips_make_temp_file ();
6058     }
6059
6060   else
6061     asm_out_data_file = asm_out_text_file = stream;
6062
6063   if (flag_verbose_asm)
6064     fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6065              ASM_COMMENT_START,
6066              mips_section_threshold, mips_arch_string, mips_isa);
6067 }
6068 \f
6069 /* If we are optimizing the global pointer, emit the text section now and any
6070    small externs which did not have .comm, etc that are needed.  Also, give a
6071    warning if the data area is more than 32K and -pic because 3 instructions
6072    are needed to reference the data pointers.  */
6073
6074 void
6075 mips_asm_file_end (file)
6076      FILE *file;
6077 {
6078   char buffer[8192];
6079   tree name_tree;
6080   struct extern_list *p;
6081   int len;
6082
6083   if (HALF_PIC_P ())
6084     {
6085       HALF_PIC_FINISH (file);
6086     }
6087
6088   if (extern_head)
6089     {
6090       fputs ("\n", file);
6091
6092       for (p = extern_head; p != 0; p = p->next)
6093         {
6094           name_tree = get_identifier (p->name);
6095
6096           /* Positively ensure only one .extern for any given symbol.  */
6097           if (! TREE_ASM_WRITTEN (name_tree))
6098             {
6099               TREE_ASM_WRITTEN (name_tree) = 1;
6100 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6101               if (p->size == -1)
6102                 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6103               else
6104 #endif
6105                 {
6106                   fputs ("\t.extern\t", file);
6107                   assemble_name (file, p->name);
6108                   fprintf (file, ", %d\n", p->size);
6109                 }
6110             }
6111         }
6112     }
6113
6114   if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
6115     {
6116       fprintf (file, "\n\t.text\n");
6117       rewind (asm_out_text_file);
6118       if (ferror (asm_out_text_file))
6119         fatal_io_error ("can't rewind %s", temp_filename);
6120
6121       while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
6122         if ((int) fwrite (buffer, 1, len, file) != len)
6123           fatal_io_error ("can't write to %s", asm_file_name);
6124
6125       if (len < 0)
6126         fatal_io_error ("can't read from %s", temp_filename);
6127
6128       if (fclose (asm_out_text_file) != 0)
6129         fatal_io_error ("can't close %s", temp_filename);
6130
6131       unlink (temp_filename);
6132       free (temp_filename);
6133     }
6134 }
6135
6136 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6137    is used, so that we don't emit an .extern for it in mips_asm_file_end.  */
6138
6139 void
6140 mips_declare_object (stream, name, init_string, final_string, size)
6141      FILE *stream;
6142      const char *name;
6143      const char *init_string;
6144      const char *final_string;
6145      int size;
6146 {
6147   fputs (init_string, stream);          /* "", "\t.comm\t", or "\t.lcomm\t" */
6148   assemble_name (stream, name);
6149   fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6150
6151   if (TARGET_GP_OPT)
6152     {
6153       tree name_tree = get_identifier (name);
6154       TREE_ASM_WRITTEN (name_tree) = 1;
6155     }
6156 }
6157 \f
6158 /* Output a double precision value to the assembler.  If both the
6159    host and target are IEEE, emit the values in hex.  */
6160
6161 void
6162 mips_output_double (stream, value)
6163      FILE *stream;
6164      REAL_VALUE_TYPE value;
6165 {
6166 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
6167   long value_long[2];
6168   REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
6169
6170   fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
6171            value_long[0], value, value_long[1]);
6172 #else
6173   fprintf (stream, "\t.double\t%.20g\n", value);
6174 #endif
6175 }
6176
6177 /* Output a single precision value to the assembler.  If both the
6178    host and target are IEEE, emit the values in hex.  */
6179
6180 void
6181 mips_output_float (stream, value)
6182      FILE *stream;
6183      REAL_VALUE_TYPE value;
6184 {
6185 #ifdef REAL_VALUE_TO_TARGET_SINGLE
6186   long value_long;
6187   REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
6188
6189   fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
6190 #else
6191   fprintf (stream, "\t.float\t%.12g\n", value);
6192 #endif
6193 }
6194 \f
6195 /* Return the bytes needed to compute the frame pointer from the current
6196    stack pointer.
6197
6198    Mips stack frames look like:
6199
6200              Before call                        After call
6201         +-----------------------+       +-----------------------+
6202    high |                       |       |                       |
6203    mem. |                       |       |                       |
6204         |  caller's temps.      |       |  caller's temps.      |
6205         |                       |       |                       |
6206         +-----------------------+       +-----------------------+
6207         |                       |       |                       |
6208         |  arguments on stack.  |       |  arguments on stack.  |
6209         |                       |       |                       |
6210         +-----------------------+       +-----------------------+
6211         |  4 words to save      |       |  4 words to save      |
6212         |  arguments passed     |       |  arguments passed     |
6213         |  in registers, even   |       |  in registers, even   |
6214     SP->|  if not passed.       |  VFP->|  if not passed.       |
6215         +-----------------------+       +-----------------------+
6216                                         |                       |
6217                                         |  fp register save     |
6218                                         |                       |
6219                                         +-----------------------+
6220                                         |                       |
6221                                         |  gp register save     |
6222                                         |                       |
6223                                         +-----------------------+
6224                                         |                       |
6225                                         |  local variables      |
6226                                         |                       |
6227                                         +-----------------------+
6228                                         |                       |
6229                                         |  alloca allocations   |
6230                                         |                       |
6231                                         +-----------------------+
6232                                         |                       |
6233                                         |  GP save for V.4 abi  |
6234                                         |                       |
6235                                         +-----------------------+
6236                                         |                       |
6237                                         |  arguments on stack   |
6238                                         |                       |
6239                                         +-----------------------+
6240                                         |  4 words to save      |
6241                                         |  arguments passed     |
6242                                         |  in registers, even   |
6243    low                              SP->|  if not passed.       |
6244    memory                               +-----------------------+
6245
6246 */
6247
6248 HOST_WIDE_INT
6249 compute_frame_size (size)
6250      HOST_WIDE_INT size;        /* # of var. bytes allocated */
6251 {
6252   int regno;
6253   HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */
6254   HOST_WIDE_INT var_size;       /* # bytes that variables take up */
6255   HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */
6256   HOST_WIDE_INT extra_size;     /* # extra bytes */
6257   HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6258   HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */
6259   HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */
6260   long mask;                    /* mask of saved gp registers */
6261   long fmask;                   /* mask of saved fp registers */
6262   int  fp_inc;                  /* 1 or 2 depending on the size of fp regs */
6263   long fp_bits;                 /* bitmask to use for each fp register */
6264
6265   gp_reg_size = 0;
6266   fp_reg_size = 0;
6267   mask = 0;
6268   fmask = 0;
6269   extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6270   var_size = MIPS_STACK_ALIGN (size);
6271   args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6272
6273   /* The MIPS 3.0 linker does not like functions that dynamically
6274      allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6275      looks like we are trying to create a second frame pointer to the
6276      function, so allocate some stack space to make it happy.  */
6277
6278   if (args_size == 0 && current_function_calls_alloca)
6279     args_size = 4 * UNITS_PER_WORD;
6280
6281   total_size = var_size + args_size + extra_size;
6282
6283   /* Calculate space needed for gp registers.  */
6284   for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6285     {
6286       /* $18 is a special case on the mips16.  It may be used to call
6287          a function which returns a floating point value, but it is
6288          marked in call_used_regs.  $31 is also a special case.  When
6289          not using -mentry, it will be used to copy a return value
6290          into the floating point registers if the return value is
6291          floating point.  */
6292       if (MUST_SAVE_REGISTER (regno)
6293           || (TARGET_MIPS16
6294               && regno == GP_REG_FIRST + 18
6295               && regs_ever_live[regno])
6296           || (TARGET_MIPS16
6297               && regno == GP_REG_FIRST + 31
6298               && mips16_hard_float
6299               && ! mips_entry
6300               && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6301               && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6302                   == MODE_FLOAT)
6303               && (! TARGET_SINGLE_FLOAT
6304                   || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6305                       <= 4))))
6306         {
6307           gp_reg_size += GET_MODE_SIZE (gpr_mode);
6308           mask |= 1L << (regno - GP_REG_FIRST);
6309
6310           /* The entry and exit pseudo instructions can not save $17
6311              without also saving $16.  */
6312           if (mips_entry
6313               && regno == GP_REG_FIRST + 17
6314               && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6315             {
6316               gp_reg_size += UNITS_PER_WORD;
6317               mask |= 1L << 16;
6318             }
6319         }
6320     }
6321
6322   /* We need to restore these for the handler.  */
6323   if (current_function_calls_eh_return)
6324     {
6325       int i;
6326       for (i = 0; ; ++i)
6327         {
6328           regno = EH_RETURN_DATA_REGNO (i);
6329           if (regno == INVALID_REGNUM)
6330             break;
6331           gp_reg_size += GET_MODE_SIZE (gpr_mode);
6332           mask |= 1L << (regno - GP_REG_FIRST);
6333         }
6334     }
6335
6336   /* Calculate space needed for fp registers.  */
6337   if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6338     {
6339       fp_inc = 1;
6340       fp_bits = 1;
6341     }
6342   else
6343     {
6344       fp_inc = 2;
6345       fp_bits = 3;
6346     }
6347
6348   /* This loop must iterate over the same space as its companion in
6349      save_restore_regs.  */
6350   for (regno = (FP_REG_LAST - fp_inc + 1);
6351        regno >= FP_REG_FIRST;
6352        regno -= fp_inc)
6353     {
6354       if (regs_ever_live[regno] && !call_used_regs[regno])
6355         {
6356           fp_reg_size += fp_inc * UNITS_PER_FPREG;
6357           fmask |= fp_bits << (regno - FP_REG_FIRST);
6358         }
6359     }
6360
6361   gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6362   total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6363
6364   /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6365      for leaf routines (total_size == extra_size) to save the gp reg.
6366      The gp reg is callee saved in the 64 bit ABI, so all routines must
6367      save the gp reg.  This is not a leaf routine if -p, because of the
6368      call to mcount.  */
6369   if (total_size == extra_size
6370       && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6371       && ! profile_flag)
6372     total_size = extra_size = 0;
6373   else if (TARGET_ABICALLS)
6374     {
6375       /* Add the context-pointer to the saved registers.  */
6376       gp_reg_size += UNITS_PER_WORD;
6377       mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6378       total_size -= gp_reg_rounded;
6379       gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6380       total_size += gp_reg_rounded;
6381     }
6382
6383   /* Add in space reserved on the stack by the callee for storing arguments
6384      passed in registers.  */
6385   if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6386     total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6387
6388   /* The entry pseudo instruction will allocate 32 bytes on the stack.  */
6389   if (mips_entry && total_size > 0 && total_size < 32)
6390     total_size = 32;
6391
6392   /* Save other computed information.  */
6393   current_frame_info.total_size = total_size;
6394   current_frame_info.var_size = var_size;
6395   current_frame_info.args_size = args_size;
6396   current_frame_info.extra_size = extra_size;
6397   current_frame_info.gp_reg_size = gp_reg_size;
6398   current_frame_info.fp_reg_size = fp_reg_size;
6399   current_frame_info.mask = mask;
6400   current_frame_info.fmask = fmask;
6401   current_frame_info.initialized = reload_completed;
6402   current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6403   current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6404
6405   if (mask)
6406     {
6407       unsigned long offset;
6408
6409       /* When using mips_entry, the registers are always saved at the
6410          top of the stack.  */
6411       if (! mips_entry)
6412         offset = (args_size + extra_size + var_size
6413                   + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6414       else
6415         offset = total_size - GET_MODE_SIZE (gpr_mode);
6416
6417       current_frame_info.gp_sp_offset = offset;
6418       current_frame_info.gp_save_offset = offset - total_size;
6419     }
6420   else
6421     {
6422       current_frame_info.gp_sp_offset = 0;
6423       current_frame_info.gp_save_offset = 0;
6424     }
6425
6426   if (fmask)
6427     {
6428       unsigned long offset = (args_size + extra_size + var_size
6429                               + gp_reg_rounded + fp_reg_size
6430                               - fp_inc * UNITS_PER_FPREG);
6431       current_frame_info.fp_sp_offset = offset;
6432       current_frame_info.fp_save_offset = offset - total_size;
6433     }
6434   else
6435     {
6436       current_frame_info.fp_sp_offset = 0;
6437       current_frame_info.fp_save_offset = 0;
6438     }
6439
6440   /* Ok, we're done.  */
6441   return total_size;
6442 }
6443 \f
6444 /* Common code to emit the insns (or to write the instructions to a file)
6445    to save/restore registers.
6446
6447    Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6448    is not modified within save_restore_insns.  */
6449
6450 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6451
6452 static void
6453 save_restore_insns (store_p, large_reg, large_offset, file)
6454      int store_p;       /* true if this is prologue */
6455      rtx large_reg;     /* register holding large offset constant or NULL */
6456      long large_offset; /* large constant offset value */
6457      FILE *file;        /* file to write instructions instead of making RTL */
6458 {
6459   long mask = current_frame_info.mask;
6460   long fmask = current_frame_info.fmask;
6461   int regno;
6462   rtx base_reg_rtx;
6463   HOST_WIDE_INT base_offset;
6464   HOST_WIDE_INT gp_offset;
6465   HOST_WIDE_INT fp_offset;
6466   HOST_WIDE_INT end_offset;
6467   rtx insn;
6468
6469   if (frame_pointer_needed
6470       && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6471     abort ();
6472
6473   if (mask == 0 && fmask == 0)
6474     return;
6475
6476   /* Save registers starting from high to low.  The debuggers prefer at least
6477      the return register be stored at func+4, and also it allows us not to
6478      need a nop in the epilog if at least one register is reloaded in
6479      addition to return address.  */
6480
6481   /* Save GP registers if needed.  */
6482   if (mask)
6483     {
6484       /* Pick which pointer to use as a base register.  For small frames, just
6485          use the stack pointer.  Otherwise, use a temporary register.  Save 2
6486          cycles if the save area is near the end of a large frame, by reusing
6487          the constant created in the prologue/epilogue to adjust the stack
6488          frame.  */
6489
6490       gp_offset = current_frame_info.gp_sp_offset;
6491       end_offset
6492         = gp_offset - (current_frame_info.gp_reg_size
6493                        - GET_MODE_SIZE (gpr_mode));
6494
6495       if (gp_offset < 0 || end_offset < 0)
6496         internal_error
6497           ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6498            (long) gp_offset, (long) end_offset);
6499
6500       /* If we see a large frame in mips16 mode, we save the registers
6501          before adjusting the stack pointer, and load them afterward.  */
6502       else if (TARGET_MIPS16 && large_offset > 32767)
6503         base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6504
6505       else if (gp_offset < 32768)
6506         base_reg_rtx = stack_pointer_rtx, base_offset  = 0;
6507
6508       else if (large_reg != 0
6509                && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6510                && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6511         {
6512           base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6513           base_offset = large_offset;
6514           if (file == 0)
6515             {
6516               if (Pmode == DImode)
6517                 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6518                                               stack_pointer_rtx));
6519               else
6520                 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6521                                               stack_pointer_rtx));
6522               if (store_p)
6523                 RTX_FRAME_RELATED_P (insn) = 1;
6524             }
6525           else
6526             fprintf (file, "\t%s\t%s,%s,%s\n",
6527                      Pmode == DImode ? "daddu" : "addu",
6528                      reg_names[MIPS_TEMP2_REGNUM],
6529                      reg_names[REGNO (large_reg)],
6530                      reg_names[STACK_POINTER_REGNUM]);
6531         }
6532
6533       else
6534         {
6535           base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6536           base_offset = gp_offset;
6537           if (file == 0)
6538             {
6539               rtx gp_offset_rtx = GEN_INT (gp_offset);
6540
6541               /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6542                  bit, so make sure that we don't emit anything that can be
6543                  split.  */
6544               /* ??? There is no DImode ori immediate pattern, so we can only
6545                  do this for 32 bit code.  */
6546               if (large_int (gp_offset_rtx, GET_MODE (gp_offset_rtx))
6547                   && GET_MODE (base_reg_rtx) == SImode)
6548                 {
6549                   insn = emit_move_insn (base_reg_rtx,
6550                                          GEN_INT (gp_offset & BITMASK_UPPER16));
6551                   if (store_p)
6552                     RTX_FRAME_RELATED_P (insn) = 1;
6553                   insn
6554                     = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6555                                              GEN_INT (gp_offset
6556                                                       & BITMASK_LOWER16)));
6557                   if (store_p)
6558                     RTX_FRAME_RELATED_P (insn) = 1;
6559                 }
6560               else
6561                 {
6562                   insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
6563                   if (store_p)
6564                     RTX_FRAME_RELATED_P (insn) = 1;
6565                 }
6566
6567               if (Pmode == DImode)
6568                 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6569                                               stack_pointer_rtx));
6570               else
6571                 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6572                                               stack_pointer_rtx));
6573               if (store_p)
6574                 RTX_FRAME_RELATED_P (insn) = 1;
6575             }
6576           else
6577             {
6578               fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6579                        reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6580               fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6581               fprintf (file, "\n\t%s\t%s,%s,%s\n",
6582                        Pmode == DImode ? "daddu" : "addu",
6583                        reg_names[MIPS_TEMP2_REGNUM],
6584                        reg_names[MIPS_TEMP2_REGNUM],
6585                        reg_names[STACK_POINTER_REGNUM]);
6586             }
6587         }
6588
6589       /* When we restore the registers in MIPS16 mode, then if we are
6590          using a frame pointer, and this is not a large frame, the
6591          current stack pointer will be offset by
6592          current_function_outgoing_args_size.  Doing it this way lets
6593          us avoid offsetting the frame pointer before copying it into
6594          the stack pointer; there is no instruction to set the stack
6595          pointer to the sum of a register and a constant.  */
6596       if (TARGET_MIPS16
6597           && ! store_p
6598           && frame_pointer_needed
6599           && large_offset <= 32767)
6600         base_offset += current_function_outgoing_args_size;
6601
6602       for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6603         if (BITSET_P (mask, regno - GP_REG_FIRST))
6604           {
6605             if (file == 0)
6606               {
6607                 rtx reg_rtx;
6608                 rtx mem_rtx
6609                   = gen_rtx (MEM, gpr_mode,
6610                              gen_rtx (PLUS, Pmode, base_reg_rtx,
6611                                       GEN_INT (gp_offset - base_offset)));
6612
6613                 RTX_UNCHANGING_P (mem_rtx) = 1;
6614
6615                 /* The mips16 does not have an instruction to load
6616                    $31, so we load $7 instead, and work things out
6617                    in the caller.  */
6618                 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6619                   reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6620                 /* The mips16 sometimes needs to save $18.  */
6621                 else if (TARGET_MIPS16
6622                          && regno != GP_REG_FIRST + 31
6623                          && ! M16_REG_P (regno))
6624                   {
6625                     if (! store_p)
6626                       reg_rtx = gen_rtx (REG, gpr_mode, 6);
6627                     else
6628                       {
6629                         reg_rtx = gen_rtx (REG, gpr_mode, 3);
6630                         emit_move_insn (reg_rtx,
6631                                         gen_rtx (REG, gpr_mode, regno));
6632                       }
6633                   }
6634                 else
6635                   reg_rtx = gen_rtx (REG, gpr_mode, regno);
6636
6637                 if (store_p)
6638                   {
6639                     insn = emit_move_insn (mem_rtx, reg_rtx);
6640                     RTX_FRAME_RELATED_P (insn) = 1;
6641                   }
6642                 else if (!TARGET_ABICALLS
6643                          || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6644                          || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6645                   {
6646                     emit_move_insn (reg_rtx, mem_rtx);
6647                     if (TARGET_MIPS16
6648                         && regno != GP_REG_FIRST + 31
6649                         && ! M16_REG_P (regno))
6650                       emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6651                                       reg_rtx);
6652                   }
6653               }
6654             else
6655               {
6656                 if (store_p || !TARGET_ABICALLS
6657                     || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6658                     || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6659                   {
6660                     int r = regno;
6661
6662                     /* The mips16 does not have an instruction to
6663                        load $31, so we load $7 instead, and work
6664                        things out in the caller.  */
6665                     if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6666                       r = GP_REG_FIRST + 7;
6667                       /* The mips16 sometimes needs to save $18.  */
6668                     if (TARGET_MIPS16
6669                         && regno != GP_REG_FIRST + 31
6670                         && ! M16_REG_P (regno))
6671                       {
6672                         if (! store_p)
6673                           r = GP_REG_FIRST + 6;
6674                         else
6675                           {
6676                             r = GP_REG_FIRST + 3;
6677                             fprintf (file, "\tmove\t%s,%s\n",
6678                                      reg_names[r], reg_names[regno]);
6679                           }
6680                       }
6681                     fprintf (file, "\t%s\t%s,",
6682                              (TARGET_64BIT
6683                               ? (store_p) ? "sd" : "ld"
6684                               : (store_p) ? "sw" : "lw"),
6685                              reg_names[r]);
6686                     fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6687                              gp_offset - base_offset);
6688                     fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6689                     if (! store_p
6690                         && TARGET_MIPS16
6691                         && regno != GP_REG_FIRST + 31
6692                         && ! M16_REG_P (regno))
6693                       fprintf (file, "\tmove\t%s,%s\n",
6694                                reg_names[regno], reg_names[r]);
6695                   }
6696
6697               }
6698             gp_offset -= GET_MODE_SIZE (gpr_mode);
6699           }
6700     }
6701   else
6702     base_reg_rtx = 0, base_offset  = 0;
6703
6704   /* Save floating point registers if needed.  */
6705   if (fmask)
6706     {
6707       int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6708       int fp_size = fp_inc * UNITS_PER_FPREG;
6709
6710       /* Pick which pointer to use as a base register.  */
6711       fp_offset = current_frame_info.fp_sp_offset;
6712       end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6713
6714       if (fp_offset < 0 || end_offset < 0)
6715         internal_error
6716           ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6717            (long) fp_offset, (long) end_offset);
6718
6719       else if (fp_offset < 32768)
6720         base_reg_rtx = stack_pointer_rtx, base_offset  = 0;
6721
6722       else if (base_reg_rtx != 0
6723                && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6724                && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6725         ;                       /* already set up for gp registers above */
6726
6727       else if (large_reg != 0
6728                && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6729                && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6730         {
6731           base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6732           base_offset = large_offset;
6733           if (file == 0)
6734             {
6735               if (Pmode == DImode)
6736                 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6737                                               stack_pointer_rtx));
6738               else
6739                 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6740                                               stack_pointer_rtx));
6741               if (store_p)
6742                 RTX_FRAME_RELATED_P (insn) = 1;
6743             }
6744
6745           else
6746             fprintf (file, "\t%s\t%s,%s,%s\n",
6747                      Pmode == DImode ? "daddu" : "addu",
6748                      reg_names[MIPS_TEMP2_REGNUM],
6749                      reg_names[REGNO (large_reg)],
6750                      reg_names[STACK_POINTER_REGNUM]);
6751         }
6752
6753       else
6754         {
6755           base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6756           base_offset = fp_offset;
6757           if (file == 0)
6758             {
6759               rtx fp_offset_rtx = GEN_INT (fp_offset);
6760
6761               /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6762                  bit, so make sure that we don't emit anything that can be
6763                  split.  */
6764               /* ??? There is no DImode ori immediate pattern, so we can only
6765                  do this for 32 bit code.  */
6766               if (large_int (fp_offset_rtx, GET_MODE (fp_offset_rtx))
6767                   && GET_MODE (base_reg_rtx) == SImode)
6768                 {
6769                   insn = emit_move_insn (base_reg_rtx,
6770                                          GEN_INT (fp_offset & BITMASK_UPPER16));
6771                   if (store_p)
6772                     RTX_FRAME_RELATED_P (insn) = 1;
6773                   insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6774                                                 GEN_INT (fp_offset
6775                                                          & BITMASK_LOWER16)));
6776                   if (store_p)
6777                     RTX_FRAME_RELATED_P (insn) = 1;
6778                 }
6779               else
6780                 {
6781                   insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6782                   if (store_p)
6783                     RTX_FRAME_RELATED_P (insn) = 1;
6784                 }
6785
6786               if (store_p)
6787                 RTX_FRAME_RELATED_P (insn) = 1;
6788               if (Pmode == DImode)
6789                 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6790                                               stack_pointer_rtx));
6791               else
6792                 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6793                                               stack_pointer_rtx));
6794               if (store_p)
6795                 RTX_FRAME_RELATED_P (insn) = 1;
6796             }
6797           else
6798             {
6799               fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6800                        reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6801               fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6802               fprintf (file, "\n\t%s\t%s,%s,%s\n",
6803                        Pmode == DImode ? "daddu" : "addu",
6804                        reg_names[MIPS_TEMP2_REGNUM],
6805                        reg_names[MIPS_TEMP2_REGNUM],
6806                        reg_names[STACK_POINTER_REGNUM]);
6807             }
6808         }
6809
6810       /* This loop must iterate over the same space as its companion in
6811          compute_frame_size.  */
6812       for (regno = (FP_REG_LAST - fp_inc + 1);
6813            regno >= FP_REG_FIRST;
6814            regno -= fp_inc)
6815         if (BITSET_P (fmask, regno - FP_REG_FIRST))
6816           {
6817             if (file == 0)
6818               {
6819                 enum machine_mode sz
6820                   = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6821                 rtx reg_rtx = gen_rtx (REG, sz, regno);
6822                 rtx mem_rtx = gen_rtx (MEM, sz,
6823                                        gen_rtx (PLUS, Pmode, base_reg_rtx,
6824                                                 GEN_INT (fp_offset
6825                                                          - base_offset)));
6826                 RTX_UNCHANGING_P (mem_rtx) = 1;
6827
6828                 if (store_p)
6829                   {
6830                     insn = emit_move_insn (mem_rtx, reg_rtx);
6831                     RTX_FRAME_RELATED_P (insn) = 1;
6832                   }
6833                 else
6834                   emit_move_insn (reg_rtx, mem_rtx);
6835               }
6836             else
6837               {
6838                 fprintf (file, "\t%s\t%s,",
6839                          (TARGET_SINGLE_FLOAT
6840                           ? (store_p ? "s.s" : "l.s")
6841                           : (store_p ? "s.d" : "l.d")),
6842                          reg_names[regno]);
6843                 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6844                          fp_offset - base_offset);
6845                 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6846               }
6847
6848             fp_offset -= fp_size;
6849           }
6850     }
6851 }
6852 \f
6853 /* Set up the stack and frame (if desired) for the function.  */
6854
6855 static void
6856 mips_output_function_prologue (file, size)
6857      FILE *file;
6858      HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6859 {
6860 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6861   const char *fnname;
6862 #endif
6863   long tsize = current_frame_info.total_size;
6864
6865   ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6866
6867 #ifdef SDB_DEBUGGING_INFO
6868   if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6869     ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6870 #endif
6871
6872   /* In mips16 mode, we may need to generate a 32 bit to handle
6873      floating point arguments.  The linker will arrange for any 32 bit
6874      functions to call this stub, which will then jump to the 16 bit
6875      function proper.  */
6876   if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6877       && current_function_args_info.fp_code != 0)
6878     build_mips16_function_stub (file);
6879
6880   inside_function = 1;
6881
6882 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6883   /* Get the function name the same way that toplev.c does before calling
6884      assemble_start_function.  This is needed so that the name used here
6885      exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
6886   fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6887
6888   if (!flag_inhibit_size_directive)
6889     {
6890       fputs ("\t.ent\t", file);
6891       assemble_name (file, fnname);
6892       fputs ("\n", file);
6893     }
6894
6895   assemble_name (file, fnname);
6896   fputs (":\n", file);
6897 #endif
6898
6899   if (!flag_inhibit_size_directive)
6900     {
6901       /* .frame FRAMEREG, FRAMESIZE, RETREG */
6902       fprintf (file,
6903                "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6904                (reg_names[(frame_pointer_needed)
6905                           ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6906                ((frame_pointer_needed && TARGET_MIPS16)
6907                 ? (tsize - current_function_outgoing_args_size)
6908                 : tsize),
6909                reg_names[31 + GP_REG_FIRST],
6910                current_frame_info.var_size,
6911                current_frame_info.num_gp,
6912                current_frame_info.num_fp,
6913                current_function_outgoing_args_size,
6914                current_frame_info.extra_size);
6915
6916       /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6917       fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6918                current_frame_info.mask,
6919                current_frame_info.gp_save_offset,
6920                current_frame_info.fmask,
6921                current_frame_info.fp_save_offset);
6922
6923       /* Require:
6924          OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6925          HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6926     }
6927
6928   if (mips_entry && ! mips_can_use_return_insn ())
6929     {
6930       int save16 = BITSET_P (current_frame_info.mask, 16);
6931       int save17 = BITSET_P (current_frame_info.mask, 17);
6932       int save31 = BITSET_P (current_frame_info.mask, 31);
6933       int savearg = 0;
6934       rtx insn;
6935
6936       /* Look through the initial insns to see if any of them store
6937          the function parameters into the incoming parameter storage
6938          area.  If they do, we delete the insn, and save the register
6939          using the entry pseudo-instruction instead.  We don't try to
6940          look past a label, jump, or call.  */
6941       for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6942         {
6943           rtx note, set, src, dest, base, offset;
6944           int hireg;
6945
6946           if (GET_CODE (insn) == CODE_LABEL
6947               || GET_CODE (insn) == JUMP_INSN
6948               || GET_CODE (insn) == CALL_INSN)
6949             break;
6950           if (GET_CODE (insn) != INSN)
6951             continue;
6952           set = PATTERN (insn);
6953           if (GET_CODE (set) != SET)
6954             continue;
6955
6956           /* An insn storing a function parameter will still have a
6957              REG_EQUIV note on it mentioning the argument pointer.  */
6958           note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6959           if (note == NULL_RTX)
6960             continue;
6961           if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6962             continue;
6963
6964           src = SET_SRC (set);
6965           if (GET_CODE (src) != REG
6966               || REGNO (src) < GP_REG_FIRST + 4
6967               || REGNO (src) > GP_REG_FIRST + 7)
6968             continue;
6969
6970           dest = SET_DEST (set);
6971           if (GET_CODE (dest) != MEM)
6972             continue;
6973           if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
6974             ;
6975           else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
6976                    && REGNO (src) < GP_REG_FIRST + 7)
6977             ;
6978           else
6979             continue;
6980           offset = const0_rtx;
6981           base = eliminate_constant_term (XEXP (dest, 0), &offset);
6982           if (GET_CODE (base) != REG
6983               || GET_CODE (offset) != CONST_INT)
6984             continue;
6985           if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
6986               && (unsigned HOST_WIDE_INT) INTVAL (offset)
6987               == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6988             ;
6989           else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
6990                    && ((unsigned HOST_WIDE_INT) INTVAL (offset)
6991                        == (tsize
6992                            + (REGNO (src) - 4) * UNITS_PER_WORD
6993                            - current_function_outgoing_args_size)))
6994             ;
6995           else
6996             continue;
6997
6998           /* This insn stores a parameter onto the stack, in the same
6999              location where the entry pseudo-instruction will put it.
7000              Delete the insn, and arrange to tell the entry
7001              instruction to save the register.  */
7002           PUT_CODE (insn, NOTE);
7003           NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7004           NOTE_SOURCE_FILE (insn) = 0;
7005
7006           hireg = (REGNO (src)
7007                    + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7008                    - 1);
7009           if (hireg > savearg)
7010             savearg = hireg;
7011         }
7012
7013       /* If this is a varargs function, we need to save all the
7014          registers onto the stack anyhow.  */
7015       if (current_function_stdarg || current_function_varargs)
7016         savearg = GP_REG_FIRST + 7;
7017
7018       fprintf (file, "\tentry\t");
7019       if (savearg > 0)
7020         {
7021           if (savearg == GP_REG_FIRST + 4)
7022             fprintf (file, "%s", reg_names[savearg]);
7023           else
7024             fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7025                      reg_names[savearg]);
7026         }
7027       if (save16 || save17)
7028         {
7029           if (savearg > 0)
7030             fprintf (file, ",");
7031           fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7032           if (save17)
7033             fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7034         }
7035       if (save31)
7036         {
7037           if (savearg > 0 || save16 || save17)
7038             fprintf (file, ",");
7039           fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7040         }
7041       fprintf (file, "\n");
7042     }
7043
7044   if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7045     {
7046       const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7047
7048       fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7049                reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7050       if (tsize > 0)
7051         {
7052           fprintf (file, "\t%s\t%s,%s,%ld\n",
7053                    (Pmode == DImode ? "dsubu" : "subu"),
7054                    sp_str, sp_str, tsize);
7055           fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
7056         }
7057
7058       if (dwarf2out_do_frame ())
7059         dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7060     }
7061 }
7062 \f
7063 /* Expand the prologue into a bunch of separate insns.  */
7064
7065 void
7066 mips_expand_prologue ()
7067 {
7068   int regno;
7069   HOST_WIDE_INT tsize;
7070   rtx tmp_rtx = 0;
7071   int last_arg_is_vararg_marker = 0;
7072   tree fndecl = current_function_decl;
7073   tree fntype = TREE_TYPE (fndecl);
7074   tree fnargs = DECL_ARGUMENTS (fndecl);
7075   rtx next_arg_reg;
7076   int i;
7077   tree next_arg;
7078   tree cur_arg;
7079   CUMULATIVE_ARGS args_so_far;
7080   rtx reg_18_save = NULL_RTX;
7081   int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7082                             && (! mips_entry || mips_can_use_return_insn ());
7083
7084   /* If struct value address is treated as the first argument, make it so.  */
7085   if (aggregate_value_p (DECL_RESULT (fndecl))
7086       && ! current_function_returns_pcc_struct
7087       && struct_value_incoming_rtx == 0)
7088     {
7089       tree type = build_pointer_type (fntype);
7090       tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7091
7092       DECL_ARG_TYPE (function_result_decl) = type;
7093       TREE_CHAIN (function_result_decl) = fnargs;
7094       fnargs = function_result_decl;
7095     }
7096
7097   /* For arguments passed in registers, find the register number
7098      of the first argument in the variable part of the argument list,
7099      otherwise GP_ARG_LAST+1.  Note also if the last argument is
7100      the varargs special argument, and treat it as part of the
7101      variable arguments.
7102
7103      This is only needed if store_args_on_stack is true. */
7104
7105   INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7106   regno = GP_ARG_FIRST;
7107
7108   for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7109     {
7110       tree passed_type = DECL_ARG_TYPE (cur_arg);
7111       enum machine_mode passed_mode = TYPE_MODE (passed_type);
7112       rtx entry_parm;
7113
7114       if (TREE_ADDRESSABLE (passed_type))
7115         {
7116           passed_type = build_pointer_type (passed_type);
7117           passed_mode = Pmode;
7118         }
7119
7120       entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7121
7122       FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7123       next_arg = TREE_CHAIN (cur_arg);
7124
7125       if (entry_parm && store_args_on_stack)
7126         {
7127           if (next_arg == 0
7128               && DECL_NAME (cur_arg)
7129               && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7130                                 "__builtin_va_alist"))
7131                   || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7132                                    "va_alist"))))
7133             {
7134               last_arg_is_vararg_marker = 1;
7135               break;
7136             }
7137           else
7138             {
7139               int words;
7140
7141               if (GET_CODE (entry_parm) != REG)
7142                 abort ();
7143
7144               /* passed in a register, so will get homed automatically */
7145               if (GET_MODE (entry_parm) == BLKmode)
7146                 words = (int_size_in_bytes (passed_type) + 3) / 4;
7147               else
7148                 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7149
7150               regno = REGNO (entry_parm) + words - 1;
7151             }
7152         }
7153       else
7154         {
7155           regno = GP_ARG_LAST+1;
7156           break;
7157         }
7158     }
7159
7160   /* In order to pass small structures by value in registers compatibly with
7161      the MIPS compiler, we need to shift the value into the high part of the
7162      register.  Function_arg has encoded a PARALLEL rtx, holding a vector of
7163      adjustments to be made as the next_arg_reg variable, so we split up the
7164      insns, and emit them separately.  */
7165
7166   next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7167   if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7168     {
7169       rtvec adjust = XVEC (next_arg_reg, 0);
7170       int num = GET_NUM_ELEM (adjust);
7171
7172       for (i = 0; i < num; i++)
7173         {
7174           rtx insn, pattern;
7175
7176           pattern = RTVEC_ELT (adjust, i);
7177           if (GET_CODE (pattern) != SET
7178               || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7179             abort_with_insn (pattern, "Insn is not a shift");
7180           PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7181
7182           insn = emit_insn (pattern);
7183
7184           /* Global life information isn't valid at this point, so we
7185              can't check whether these shifts are actually used.  Mark
7186              them MAYBE_DEAD so that flow2 will remove them, and not
7187              complain about dead code in the prologue.  */
7188           REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7189                                                REG_NOTES (insn));
7190         }
7191     }
7192
7193   tsize = compute_frame_size (get_frame_size ());
7194
7195   /* If this function is a varargs function, store any registers that
7196      would normally hold arguments ($4 - $7) on the stack.  */
7197   if (store_args_on_stack
7198       && ((TYPE_ARG_TYPES (fntype) != 0
7199            && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7200                != void_type_node))
7201           || last_arg_is_vararg_marker))
7202     {
7203       int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7204       rtx ptr = stack_pointer_rtx;
7205
7206       /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7207       if (TARGET_ABICALLS)
7208         offset += tsize;
7209
7210       for (; regno <= GP_ARG_LAST; regno++)
7211         {
7212           if (offset != 0)
7213             ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7214           emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7215                           gen_rtx (REG, gpr_mode, regno));
7216
7217           offset += GET_MODE_SIZE (gpr_mode);
7218         }
7219     }
7220
7221   /* If we are using the entry pseudo instruction, it will
7222      automatically subtract 32 from the stack pointer, so we don't
7223      need to.  The entry pseudo instruction is emitted by
7224      function_prologue.  */
7225   if (mips_entry && ! mips_can_use_return_insn ())
7226     {
7227       if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7228         {
7229           rtx insn;
7230
7231           /* If we are using a frame pointer with a small stack frame,
7232              we need to initialize it here since it won't be done
7233              below.  */
7234           if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7235             {
7236               rtx incr = GEN_INT (current_function_outgoing_args_size);
7237               if (Pmode == DImode)
7238                 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7239                                               stack_pointer_rtx,
7240                                               incr));
7241               else
7242                 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7243                                               stack_pointer_rtx,
7244                                               incr));
7245             }
7246           else if (Pmode == DImode)
7247             insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7248                                          stack_pointer_rtx));
7249           else
7250             insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7251                                          stack_pointer_rtx));
7252
7253           RTX_FRAME_RELATED_P (insn) = 1;
7254         }
7255
7256       /* We may need to save $18, if it is used to call a function
7257          which may return a floating point value.  Set up a sequence
7258          of instructions to do so.  Later on we emit them at the right
7259          moment.  */
7260       if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7261         {
7262           rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7263           long gp_offset, base_offset;
7264
7265           gp_offset = current_frame_info.gp_sp_offset;
7266           if (BITSET_P (current_frame_info.mask, 16))
7267             gp_offset -= UNITS_PER_WORD;
7268           if (BITSET_P (current_frame_info.mask, 17))
7269             gp_offset -= UNITS_PER_WORD;
7270           if (BITSET_P (current_frame_info.mask, 31))
7271             gp_offset -= UNITS_PER_WORD;
7272           if (tsize > 32767)
7273             base_offset = tsize;
7274           else
7275             base_offset = 0;
7276           start_sequence ();
7277           emit_move_insn (reg_rtx,
7278                           gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7279           emit_move_insn (gen_rtx (MEM, gpr_mode,
7280                                    gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7281                                             GEN_INT (gp_offset
7282                                                      - base_offset))),
7283                           reg_rtx);
7284           reg_18_save = gen_sequence ();
7285           end_sequence ();
7286         }
7287
7288       if (tsize > 32)
7289         tsize -= 32;
7290       else
7291         {
7292           tsize = 0;
7293           if (reg_18_save != NULL_RTX)
7294             emit_insn (reg_18_save);
7295         }
7296     }
7297
7298   if (tsize > 0)
7299     {
7300       rtx tsize_rtx = GEN_INT (tsize);
7301
7302       /* If we are doing svr4-abi, sp move is done by
7303          function_prologue.  In mips16 mode with a large frame, we
7304          save the registers before adjusting the stack.  */
7305       if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7306           && (!TARGET_MIPS16 || tsize <= 32767))
7307         {
7308           rtx insn;
7309
7310           if (tsize > 32767)
7311             {
7312               tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7313
7314               /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
7315                  bit, so make sure that we don't emit anything that can be
7316                  split.  */
7317               /* ??? There is no DImode ori immediate pattern, so we can only
7318                  do this for 32 bit code.  */
7319               if (large_int (tsize_rtx, GET_MODE (tsize_rtx))
7320                   && GET_MODE (tmp_rtx) == SImode)
7321                 {
7322                   insn = emit_move_insn (tmp_rtx,
7323                                          GEN_INT (tsize & BITMASK_UPPER16));
7324                   RTX_FRAME_RELATED_P (insn) = 1;
7325                   insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
7326                                                 GEN_INT (tsize
7327                                                          & BITMASK_LOWER16)));
7328                   RTX_FRAME_RELATED_P (insn) = 1;
7329                 }
7330               else
7331                 {
7332                   insn = emit_move_insn (tmp_rtx, tsize_rtx);
7333                   RTX_FRAME_RELATED_P (insn) = 1;
7334                 }
7335
7336               tsize_rtx = tmp_rtx;
7337             }
7338
7339           if (Pmode == DImode)
7340             insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7341                                           tsize_rtx));
7342           else
7343             insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7344                                           tsize_rtx));
7345
7346           RTX_FRAME_RELATED_P (insn) = 1;
7347         }
7348
7349       if (! mips_entry)
7350         save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7351       else if (reg_18_save != NULL_RTX)
7352         emit_insn (reg_18_save);
7353
7354       if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7355           && TARGET_MIPS16
7356           && tsize > 32767)
7357         {
7358           rtx reg_rtx;
7359
7360           if (!frame_pointer_needed)
7361             abort ();
7362
7363           reg_rtx = gen_rtx (REG, Pmode, 3);
7364           emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7365           emit_move_insn (reg_rtx, tsize_rtx);
7366           if (Pmode == DImode)
7367             emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7368                                    hard_frame_pointer_rtx,
7369                                    reg_rtx));
7370           else
7371             emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7372                                    hard_frame_pointer_rtx,
7373                                    reg_rtx));
7374           emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7375         }
7376
7377       if (frame_pointer_needed)
7378         {
7379           rtx insn = 0;
7380
7381           /* On the mips16, we encourage the use of unextended
7382              instructions when using the frame pointer by pointing the
7383              frame pointer ahead of the argument space allocated on
7384              the stack.  */
7385           if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7386               && TARGET_MIPS16
7387               && tsize > 32767)
7388             {
7389               /* In this case, we have already copied the stack
7390                  pointer into the frame pointer, above.  We need only
7391                  adjust for the outgoing argument size.  */
7392               if (current_function_outgoing_args_size != 0)
7393                 {
7394                   rtx incr = GEN_INT (current_function_outgoing_args_size);
7395                   if (Pmode == DImode)
7396                     insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7397                                                   hard_frame_pointer_rtx,
7398                                                   incr));
7399                   else
7400                     insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7401                                                   hard_frame_pointer_rtx,
7402                                                   incr));
7403                 }
7404             }
7405           else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7406             {
7407               rtx incr = GEN_INT (current_function_outgoing_args_size);
7408               if (Pmode == DImode)
7409                 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7410                                               stack_pointer_rtx,
7411                                               incr));
7412               else
7413                 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7414                                               stack_pointer_rtx,
7415                                               incr));
7416             }
7417           else if (Pmode == DImode)
7418             insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7419                                          stack_pointer_rtx));
7420           else
7421             insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7422                                          stack_pointer_rtx));
7423
7424           if (insn)
7425             RTX_FRAME_RELATED_P (insn) = 1;
7426         }
7427
7428       if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7429         emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7430                                gen_rtx_REG (DImode, 25)));
7431     }
7432
7433   /* If we are profiling, make sure no instructions are scheduled before
7434      the call to mcount.  */
7435
7436   if (profile_flag || profile_block_flag)
7437     emit_insn (gen_blockage ());
7438 }
7439 \f
7440 /* Do any necessary cleanup after a function to restore stack, frame,
7441    and regs. */
7442
7443 #define RA_MASK BITMASK_HIGH    /* 1 << 31 */
7444 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7445
7446 static void
7447 mips_output_function_epilogue (file, size)
7448      FILE *file ATTRIBUTE_UNUSED;
7449      HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7450 {
7451   const char *fnname = "";      /* FIXME: Correct initialisation?  */
7452
7453 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7454   /* Get the function name the same way that toplev.c does before calling
7455      assemble_start_function.  This is needed so that the name used here
7456      exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
7457   fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7458
7459   if (!flag_inhibit_size_directive)
7460     {
7461       fputs ("\t.end\t", file);
7462       assemble_name (file, fnname);
7463       fputs ("\n", file);
7464     }
7465 #endif
7466
7467   if (TARGET_STATS)
7468     {
7469       int num_gp_regs = current_frame_info.gp_reg_size / 4;
7470       int num_fp_regs = current_frame_info.fp_reg_size / 8;
7471       int num_regs = num_gp_regs + num_fp_regs;
7472       const char *name = fnname;
7473
7474       if (name[0] == '*')
7475         name++;
7476
7477       dslots_load_total += num_regs;
7478
7479       fprintf (stderr,
7480                "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7481                name, frame_pointer_needed ? 'y' : 'n',
7482                (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7483                current_function_calls_alloca ? 'y' : 'n',
7484                current_function_calls_setjmp ? 'y' : 'n',
7485                current_frame_info.total_size,
7486                current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7487                dslots_load_total, dslots_load_filled,
7488                dslots_jump_total, dslots_jump_filled,
7489                num_refs[0], num_refs[1], num_refs[2]);
7490
7491       if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7492         {
7493           fprintf (stderr,
7494                    " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7495           prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7496         }
7497
7498       if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7499         {
7500           fprintf (stderr,
7501                    " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7502           prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7503         }
7504
7505       fputc ('\n', stderr);
7506     }
7507
7508   /* Reset state info for each function.  */
7509   inside_function = 0;
7510   ignore_line_number = 0;
7511   dslots_load_total = 0;
7512   dslots_jump_total = 0;
7513   dslots_load_filled = 0;
7514   dslots_jump_filled = 0;
7515   num_refs[0] = 0;
7516   num_refs[1] = 0;
7517   num_refs[2] = 0;
7518   mips_load_reg = 0;
7519   mips_load_reg2 = 0;
7520   current_frame_info = zero_frame_info;
7521
7522   while (string_constants != NULL)
7523     {
7524       struct string_constant *next;
7525
7526       next = string_constants->next;
7527       free (string_constants);
7528       string_constants = next;
7529     }
7530
7531   /* Restore the output file if optimizing the GP (optimizing the GP causes
7532      the text to be diverted to a tempfile, so that data decls come before
7533      references to the data).  */
7534
7535   if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
7536     asm_out_file = asm_out_data_file;
7537 }
7538 \f
7539 /* Expand the epilogue into a bunch of separate insns.  */
7540
7541 void
7542 mips_expand_epilogue ()
7543 {
7544   HOST_WIDE_INT tsize = current_frame_info.total_size;
7545   rtx tsize_rtx = GEN_INT (tsize);
7546   rtx tmp_rtx = (rtx)0;
7547
7548   if (mips_can_use_return_insn ())
7549     {
7550       emit_insn (gen_return ());
7551       return;
7552     }
7553
7554   if (mips_entry && ! mips_can_use_return_insn ())
7555     tsize -= 32;
7556
7557   if (tsize > 32767 && ! TARGET_MIPS16)
7558     {
7559       tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7560       emit_move_insn (tmp_rtx, tsize_rtx);
7561       tsize_rtx = tmp_rtx;
7562     }
7563
7564   if (tsize > 0)
7565     {
7566       long orig_tsize = tsize;
7567
7568       if (frame_pointer_needed)
7569         {
7570           emit_insn (gen_blockage ());
7571
7572           /* On the mips16, the frame pointer is offset from the stack
7573              pointer by current_function_outgoing_args_size.  We
7574              account for that by changing tsize.  Note that this can
7575              actually make tsize negative.  */
7576           if (TARGET_MIPS16)
7577             {
7578               tsize -= current_function_outgoing_args_size;
7579
7580               /* If we have a large frame, it's easier to add to $17
7581                  than to $sp, since the mips16 has no instruction to
7582                  add a register to $sp.  */
7583               if (orig_tsize > 32767)
7584                 {
7585                   rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7586
7587                   emit_move_insn (g6_rtx, GEN_INT (tsize));
7588                   if (Pmode == DImode)
7589                     emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7590                                            hard_frame_pointer_rtx,
7591                                            g6_rtx));
7592                   else
7593                     emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7594                                            hard_frame_pointer_rtx,
7595                                            g6_rtx));
7596                   tsize = 0;
7597                 }
7598
7599               if (tsize && tsize != orig_tsize)
7600                 tsize_rtx = GEN_INT (tsize);
7601             }
7602
7603           if (Pmode == DImode)
7604             emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7605           else
7606             emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7607         }
7608
7609       /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7610          are going to restore it, then we must emit a blockage insn to
7611          prevent the scheduler from moving the restore out of the epilogue.  */
7612       else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7613                && (current_frame_info.mask
7614                    & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7615         emit_insn (gen_blockage ());
7616
7617       save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7618
7619       /* In mips16 mode with a large frame, we adjust the stack
7620          pointer before restoring the registers.  In this case, we
7621          should always be using a frame pointer, so everything should
7622          have been handled above.  */
7623       if (tsize > 32767 && TARGET_MIPS16)
7624         abort ();
7625
7626       if (current_function_calls_eh_return)
7627         {
7628           rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7629           if (Pmode == DImode)
7630             emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7631           else
7632             emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7633           tsize_rtx = eh_ofs;
7634         }
7635
7636       emit_insn (gen_blockage ());
7637
7638       if (tsize != 0 || current_function_calls_eh_return)
7639         {
7640           if (Pmode == DImode)
7641             emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7642                                    tsize_rtx));
7643           else
7644             emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7645                                    tsize_rtx));
7646         }
7647     }
7648
7649   /* The mips16 loads the return address into $7, not $31.  */
7650   if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7651     emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7652                                                   GP_REG_FIRST + 7)));
7653   else
7654     emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7655                                                   GP_REG_FIRST + 31)));
7656 }
7657 \f
7658 /* Return nonzero if this function is known to have a null epilogue.
7659    This allows the optimizer to omit jumps to jumps if no stack
7660    was created.  */
7661
7662 int
7663 mips_can_use_return_insn ()
7664 {
7665   if (! reload_completed)
7666     return 0;
7667
7668   if (regs_ever_live[31] || profile_flag)
7669     return 0;
7670
7671   /* In mips16 mode, a function which returns a floating point value
7672      needs to arrange to copy the return value into the floating point
7673      registers.  */
7674   if (TARGET_MIPS16
7675       && mips16_hard_float
7676       && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7677       && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7678           == MODE_FLOAT)
7679       && (! TARGET_SINGLE_FLOAT
7680           || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7681               <= 4)))
7682     return 0;
7683
7684   if (current_frame_info.initialized)
7685     return current_frame_info.total_size == 0;
7686
7687   return compute_frame_size (get_frame_size ()) == 0;
7688 }
7689 \f
7690 /* Returns non-zero if X contains a SYMBOL_REF.  */
7691
7692 static int
7693 symbolic_expression_p (x)
7694      rtx x;
7695 {
7696   if (GET_CODE (x) == SYMBOL_REF)
7697     return 1;
7698
7699   if (GET_CODE (x) == CONST)
7700     return symbolic_expression_p (XEXP (x, 0));
7701
7702   if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7703     return symbolic_expression_p (XEXP (x, 0));
7704
7705   if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7706       || GET_RTX_CLASS (GET_CODE (x)) == '2')
7707     return (symbolic_expression_p (XEXP (x, 0))
7708             || symbolic_expression_p (XEXP (x, 1)));
7709
7710   return 0;
7711 }
7712
7713 /* Choose the section to use for the constant rtx expression X that has
7714    mode MODE.  */
7715
7716 void
7717 mips_select_rtx_section (mode, x)
7718      enum machine_mode mode;
7719      rtx x ATTRIBUTE_UNUSED;
7720 {
7721   if (TARGET_MIPS16)
7722     {
7723       /* In mips16 mode, the constant table always goes in the same section
7724          as the function, so that constants can be loaded using PC relative
7725          addressing.  */
7726       function_section (current_function_decl);
7727     }
7728   else if (TARGET_EMBEDDED_DATA)
7729     {
7730       /* For embedded applications, always put constants in read-only data,
7731          in order to reduce RAM usage.  */
7732       READONLY_DATA_SECTION ();
7733     }
7734   else
7735     {
7736       /* For hosted applications, always put constants in small data if
7737          possible, as this gives the best performance.  */
7738
7739       if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7740           && mips_section_threshold > 0)
7741         SMALL_DATA_SECTION ();
7742       else if (flag_pic && symbolic_expression_p (x))
7743         /* Any expression involving a SYMBOL_REF might need a run-time
7744            relocation.  (The symbol might be defined in a shared
7745            library loaded at an unexpected base address.)  So, we must
7746            put such expressions in the data segment (which is
7747            writable), rather than the text segment (which is
7748            read-only).  */
7749         data_section ();
7750       else
7751         READONLY_DATA_SECTION ();
7752     }
7753 }
7754
7755 /* Choose the section to use for DECL.  RELOC is true if its value contains
7756    any relocatable expression.
7757
7758    Some of the logic used here needs to be replicated in
7759    ENCODE_SECTION_INFO in mips.h so that references to these symbols
7760    are done correctly.  Specifically, at least all symbols assigned
7761    here to rom (.text and/or .rodata) must not be referenced via
7762    ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7763
7764    If you need to make a change here, you probably should check
7765    ENCODE_SECTION_INFO to see if it needs a similar change.  */
7766
7767 void
7768 mips_select_section (decl, reloc)
7769      tree decl;
7770      int reloc;
7771 {
7772   int size = int_size_in_bytes (TREE_TYPE (decl));
7773
7774   if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7775       && TREE_CODE (decl) == STRING_CST
7776       && !flag_writable_strings)
7777     /* For embedded position independent code, put constant strings in the
7778        text section, because the data section is limited to 64K in size.
7779        For mips16 code, put strings in the text section so that a PC
7780        relative load instruction can be used to get their address.  */
7781     text_section ();
7782   else if (TARGET_EMBEDDED_DATA)
7783     {
7784       /* For embedded applications, always put an object in read-only data
7785          if possible, in order to reduce RAM usage.  */
7786
7787       if (((TREE_CODE (decl) == VAR_DECL
7788             && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7789             && DECL_INITIAL (decl)
7790             && (DECL_INITIAL (decl) == error_mark_node
7791                 || TREE_CONSTANT (DECL_INITIAL (decl))))
7792            /* Deal with calls from output_constant_def_contents.  */
7793            || (TREE_CODE (decl) != VAR_DECL
7794                && (TREE_CODE (decl) != STRING_CST
7795                    || !flag_writable_strings)))
7796           && ! (flag_pic && reloc))
7797         READONLY_DATA_SECTION ();
7798       else if (size > 0 && size <= mips_section_threshold)
7799         SMALL_DATA_SECTION ();
7800       else
7801         data_section ();
7802     }
7803   else
7804     {
7805       /* For hosted applications, always put an object in small data if
7806          possible, as this gives the best performance.  */
7807
7808       if (size > 0 && size <= mips_section_threshold)
7809         SMALL_DATA_SECTION ();
7810       else if (((TREE_CODE (decl) == VAR_DECL
7811                  && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7812                  && DECL_INITIAL (decl)
7813                  && (DECL_INITIAL (decl) == error_mark_node
7814                      || TREE_CONSTANT (DECL_INITIAL (decl))))
7815                 /* Deal with calls from output_constant_def_contents.  */
7816                 || (TREE_CODE (decl) != VAR_DECL
7817                     && (TREE_CODE (decl) != STRING_CST
7818                         || !flag_writable_strings)))
7819                && ! (flag_pic && reloc))
7820         READONLY_DATA_SECTION ();
7821       else
7822         data_section ();
7823     }
7824 }
7825 \f
7826 #ifdef MIPS_ABI_DEFAULT
7827
7828 /* Support functions for the 64 bit ABI.  */
7829
7830 /* Return register to use for a function return value with VALTYPE for function
7831    FUNC.  */
7832
7833 rtx
7834 mips_function_value (valtype, func)
7835      tree valtype;
7836      tree func ATTRIBUTE_UNUSED;
7837 {
7838   int reg = GP_RETURN;
7839   enum machine_mode mode = TYPE_MODE (valtype);
7840   enum mode_class mclass = GET_MODE_CLASS (mode);
7841   int unsignedp = TREE_UNSIGNED (valtype);
7842
7843   /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7844      just as PROMOTE_MODE does.  */
7845   mode = promote_mode (valtype, mode, &unsignedp, 1);
7846
7847   /* ??? How should we return complex float?  */
7848   if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7849     {
7850       if (TARGET_SINGLE_FLOAT
7851           && (mclass == MODE_FLOAT
7852               ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7853         reg = GP_RETURN;
7854       else
7855         reg = FP_RETURN;
7856     }
7857
7858   else if (TREE_CODE (valtype) == RECORD_TYPE
7859            && mips_abi != ABI_32
7860            && mips_abi != ABI_O64
7861            && mips_abi != ABI_EABI)
7862     {
7863       /* A struct with only one or two floating point fields is returned in
7864          the floating point registers.  */
7865       tree field, fields[2];
7866       int i;
7867
7868       for (i = 0, field = TYPE_FIELDS (valtype); field;
7869            field = TREE_CHAIN (field))
7870         {
7871           if (TREE_CODE (field) != FIELD_DECL)
7872             continue;
7873
7874           if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7875             break;
7876
7877           fields[i++] = field;
7878         }
7879
7880       /* Must check i, so that we reject structures with no elements.  */
7881       if (! field)
7882         {
7883           if (i == 1)
7884             {
7885               /* The structure has DImode, but we don't allow DImode values
7886                  in FP registers, so we use a PARALLEL even though it isn't
7887                  strictly necessary.  */
7888               enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7889
7890               return gen_rtx_PARALLEL
7891                 (mode,
7892                  gen_rtvec (1,
7893                             gen_rtx_EXPR_LIST (VOIDmode,
7894                                                gen_rtx_REG (field_mode,
7895                                                             FP_RETURN),
7896                                                const0_rtx)));
7897             }
7898
7899           else if (i == 2)
7900             {
7901               enum machine_mode first_mode
7902                 = TYPE_MODE (TREE_TYPE (fields[0]));
7903               enum machine_mode second_mode
7904                 = TYPE_MODE (TREE_TYPE (fields[1]));
7905               HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7906               HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
7907
7908               return gen_rtx_PARALLEL
7909                 (mode,
7910                  gen_rtvec (2,
7911                             gen_rtx_EXPR_LIST (VOIDmode,
7912                                                gen_rtx_REG (first_mode,
7913                                                             FP_RETURN),
7914                                                GEN_INT (first_offset)),
7915                             gen_rtx_EXPR_LIST (VOIDmode,
7916                                                gen_rtx_REG (second_mode,
7917                                                             FP_RETURN + 2),
7918                                                GEN_INT (second_offset))));
7919             }
7920         }
7921     }
7922
7923   return gen_rtx_REG (mode, reg);
7924 }
7925 #endif
7926
7927 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE.  Return
7928    nonzero when an argument must be passed by reference.  */
7929
7930 int
7931 function_arg_pass_by_reference (cum, mode, type, named)
7932      CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7933      enum machine_mode mode;
7934      tree type;
7935      int named ATTRIBUTE_UNUSED;
7936 {
7937   int size;
7938
7939   /* We must pass by reference if we would be both passing in registers
7940      and the stack.  This is because any subsequent partial arg would be
7941      handled incorrectly in this case.
7942
7943      ??? This is really a kludge.  We should either fix GCC so that such
7944      a situation causes an abort and then do something in the MIPS port
7945      to prevent it, or add code to function.c to properly handle the case.  */
7946   /* ??? cum can be NULL when called from mips_va_arg.  The problem handled
7947      here hopefully is not relevant to mips_va_arg.  */
7948   if (cum && MUST_PASS_IN_STACK (mode, type))
7949      {
7950        /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7951           get double copies of any offsets generated for small structs
7952           passed in registers. */
7953        CUMULATIVE_ARGS temp;
7954        temp = *cum;
7955        if (FUNCTION_ARG (temp, mode, type, named) != 0)
7956          return 1;
7957      }
7958
7959   /* Otherwise, we only do this if EABI is selected.  */
7960   if (mips_abi != ABI_EABI)
7961     return 0;
7962
7963   /* ??? How should SCmode be handled?  */
7964   if (type == NULL_TREE || mode == DImode || mode == DFmode)
7965     return 0;
7966
7967   size = int_size_in_bytes (type);
7968   return size == -1 || size > UNITS_PER_WORD;
7969 }
7970
7971 /* This function returns the register class required for a secondary
7972    register when copying between one of the registers in CLASS, and X,
7973    using MODE.  If IN_P is nonzero, the copy is going from X to the
7974    register, otherwise the register is the source.  A return value of
7975    NO_REGS means that no secondary register is required.  */
7976
7977 enum reg_class
7978 mips_secondary_reload_class (class, mode, x, in_p)
7979      enum reg_class class;
7980      enum machine_mode mode;
7981      rtx x;
7982      int in_p;
7983 {
7984   enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7985   int regno = -1;
7986   int gp_reg_p;
7987
7988   if (GET_CODE (x) == SIGN_EXTEND)
7989     {
7990       int off = 0;
7991
7992       x = XEXP (x, 0);
7993
7994       /* We may be called with reg_renumber NULL from regclass.
7995          ??? This is probably a bug.  */
7996       if (reg_renumber)
7997         regno = true_regnum (x);
7998       else
7999         {
8000           while (GET_CODE (x) == SUBREG)
8001             {
8002               off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8003                                           GET_MODE (SUBREG_REG (x)),
8004                                           SUBREG_BYTE (x),
8005                                           GET_MODE (x));
8006               x = SUBREG_REG (x);
8007             }
8008
8009           if (GET_CODE (x) == REG)
8010             regno = REGNO (x) + off;
8011         }
8012     }
8013
8014   else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8015     regno = true_regnum (x);
8016
8017   gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8018
8019   /* We always require a general register when copying anything to
8020      HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8021      to a general register, or when copying from register 0.  */
8022   if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8023     return ((! in_p
8024              && gp_reg_p
8025              && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8026             ? NO_REGS : gr_regs);
8027   else if (regno == HILO_REGNUM)
8028     return ((in_p
8029              && class == gr_regs
8030              && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8031             ? NO_REGS : gr_regs);
8032
8033   /* Copying from HI or LO to anywhere other than a general register
8034      requires a general register.  */
8035   if (class == HI_REG || class == LO_REG || class == MD_REGS)
8036     {
8037       if (TARGET_MIPS16 && in_p)
8038         {
8039           /* We can't really copy to HI or LO at all in mips16 mode.  */
8040           return M16_REGS;
8041         }
8042       return gp_reg_p ? NO_REGS : gr_regs;
8043     }
8044   if (MD_REG_P (regno))
8045     {
8046       if (TARGET_MIPS16 && ! in_p)
8047         {
8048           /* We can't really copy to HI or LO at all in mips16 mode.  */
8049           return M16_REGS;
8050         }
8051       return class == gr_regs ? NO_REGS : gr_regs;
8052     }
8053
8054   /* We can only copy a value to a condition code register from a
8055      floating point register, and even then we require a scratch
8056      floating point register.  We can only copy a value out of a
8057      condition code register into a general register.  */
8058   if (class == ST_REGS)
8059     {
8060       if (in_p)
8061         return FP_REGS;
8062       return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8063     }
8064   if (ST_REG_P (regno))
8065     {
8066       if (! in_p)
8067         return FP_REGS;
8068       return class == GR_REGS ? NO_REGS : GR_REGS;
8069     }
8070
8071   /* In mips16 mode, going between memory and anything but M16_REGS
8072      requires an M16_REG.  */
8073   if (TARGET_MIPS16)
8074     {
8075       if (class != M16_REGS && class != M16_NA_REGS)
8076         {
8077           if (gp_reg_p)
8078             return NO_REGS;
8079           return M16_REGS;
8080         }
8081       if (! gp_reg_p)
8082         {
8083           /* The stack pointer isn't a valid operand to an add instruction,
8084              so we need to load it into M16_REGS first.  This can happen as
8085              a result of register elimination and form_sum converting
8086              (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST).  We
8087              need an extra register if the dest is the same as the other
8088              register.  In that case, we can't fix the problem by loading SP
8089              into the dest first.  */
8090           if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8091               && GET_CODE (XEXP (x, 1)) == REG
8092               && (XEXP (x, 0) == stack_pointer_rtx
8093                   || XEXP (x, 1) == stack_pointer_rtx))
8094             return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8095
8096           if (class == M16_REGS || class == M16_NA_REGS)
8097             return NO_REGS;
8098           return M16_REGS;
8099         }
8100     }
8101
8102   return NO_REGS;
8103 }
8104 \f
8105 /* For each mips16 function which refers to GP relative symbols, we
8106    use a pseudo register, initialized at the start of the function, to
8107    hold the $gp value.  */
8108
8109 rtx
8110 mips16_gp_pseudo_reg ()
8111 {
8112   if (mips16_gp_pseudo_rtx == NULL_RTX)
8113     {
8114       rtx const_gp;
8115       rtx insn, scan;
8116
8117       mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8118       RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8119
8120       /* We want to initialize this to a value which gcc will believe
8121          is constant.  */
8122       const_gp = gen_rtx (CONST, Pmode,
8123                           gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8124
8125       start_sequence ();
8126       emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8127       insn = gen_sequence ();
8128       end_sequence ();
8129
8130       push_topmost_sequence ();
8131       /* We need to emit the initialization after the FUNCTION_BEG
8132          note, so that it will be integrated.  */
8133       for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8134         if (GET_CODE (scan) == NOTE
8135             && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8136           break;
8137       if (scan == NULL_RTX)
8138         scan = get_insns ();
8139       insn = emit_insn_after (insn, scan);
8140       pop_topmost_sequence ();
8141     }
8142
8143   return mips16_gp_pseudo_rtx;
8144 }
8145
8146 /* Return an RTX which represents the signed 16 bit offset from the
8147    $gp register for the given symbol.  This is only used on the
8148    mips16.  */
8149
8150 rtx
8151 mips16_gp_offset (sym)
8152      rtx sym;
8153 {
8154   tree gp;
8155
8156   if (GET_CODE (sym) != SYMBOL_REF
8157       || ! SYMBOL_REF_FLAG (sym))
8158     abort ();
8159
8160   /* We use a special identifier to represent the value of the gp
8161      register.  */
8162   gp = get_identifier ("__mips16_gp_value");
8163
8164   return gen_rtx (CONST, Pmode,
8165                   gen_rtx (MINUS, Pmode, sym,
8166                            gen_rtx (SYMBOL_REF, Pmode,
8167                                     IDENTIFIER_POINTER (gp))));
8168 }
8169
8170 /* Return nonzero if the given RTX represents a signed 16 bit offset
8171    from the $gp register.  */
8172
8173 int
8174 mips16_gp_offset_p (x)
8175      rtx x;
8176 {
8177   if (GET_CODE (x) == CONST)
8178     x = XEXP (x, 0);
8179
8180   /* It's OK to add a small integer value to a gp offset.  */
8181   if (GET_CODE (x) == PLUS)
8182     {
8183       if (GET_CODE (XEXP (x, 1)) == CONST_INT
8184           && SMALL_INT (XEXP (x, 1)))
8185         return mips16_gp_offset_p (XEXP (x, 0));
8186       if (GET_CODE (XEXP (x, 0)) == CONST_INT
8187           && SMALL_INT (XEXP (x, 0)))
8188         return mips16_gp_offset_p (XEXP (x, 1));
8189       return 0;
8190     }
8191
8192   /* Make sure it is in the form SYM - __mips16_gp_value.  */
8193   return (GET_CODE (x) == MINUS
8194           && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8195           && SYMBOL_REF_FLAG (XEXP (x, 0))
8196           && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8197           && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8198 }
8199
8200 /* Output a GP offset.  We don't want to print the subtraction of
8201    __mips16_gp_value; it is implicitly represented by the %gprel which
8202    should have been printed by the caller.  */
8203
8204 static void
8205 mips16_output_gp_offset (file, x)
8206      FILE *file;
8207      rtx x;
8208 {
8209   if (GET_CODE (x) == CONST)
8210     x = XEXP (x, 0);
8211
8212   if (GET_CODE (x) == PLUS)
8213     {
8214       mips16_output_gp_offset (file, XEXP (x, 0));
8215       fputs ("+", file);
8216       mips16_output_gp_offset (file, XEXP (x, 1));
8217       return;
8218     }
8219
8220   if (GET_CODE (x) == MINUS
8221       && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8222       && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8223     {
8224       mips16_output_gp_offset (file, XEXP (x, 0));
8225       return;
8226     }
8227
8228   output_addr_const (file, x);
8229 }
8230
8231 /* Return nonzero if a constant should not be output until after the
8232    function.  This is true of most string constants, so that we can
8233    use a more efficient PC relative reference.  However, a static
8234    inline function may never call assemble_function_end to write out
8235    the constant pool, so don't try to postpone the constant in that
8236    case.
8237
8238    ??? It's really a bug that a static inline function can put stuff
8239    in the constant pool even if the function itself is not output.
8240
8241    We record which string constants we've seen, so that we know which
8242    ones might use the more efficient reference.  */
8243
8244 int
8245 mips16_constant_after_function_p (x)
8246      tree x;
8247 {
8248   if (TREE_CODE (x) == STRING_CST
8249       && ! flag_writable_strings
8250       && current_function_decl != 0
8251       && ! DECL_DEFER_OUTPUT (current_function_decl)
8252       && ! (DECL_INLINE (current_function_decl)
8253             && ((! TREE_PUBLIC (current_function_decl)
8254                  && ! TREE_ADDRESSABLE (current_function_decl)
8255                  && ! flag_keep_inline_functions)
8256                 || DECL_EXTERNAL (current_function_decl))))
8257     {
8258       struct string_constant *n;
8259
8260       n = (struct string_constant *) xmalloc (sizeof *n);
8261       n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8262       n->next = string_constants;
8263       string_constants = n;
8264
8265       return 1;
8266     }
8267
8268   return 0;
8269 }
8270
8271 /* Validate a constant for the mips16.  This rejects general symbolic
8272    addresses, which must be loaded from memory.  If ADDR is nonzero,
8273    this should reject anything which is not a legal address.  If
8274    ADDEND is nonzero, this is being added to something else.  */
8275
8276 int
8277 mips16_constant (x, mode, addr, addend)
8278      rtx x;
8279      enum machine_mode mode;
8280      int addr;
8281      int addend;
8282 {
8283   while (GET_CODE (x) == CONST)
8284     x = XEXP (x, 0);
8285
8286   switch (GET_CODE (x))
8287     {
8288     default:
8289       return 0;
8290
8291     case PLUS:
8292       return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8293               && mips16_constant (XEXP (x, 1), mode, addr, 1));
8294
8295     case SYMBOL_REF:
8296       if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8297         return 0;
8298       if (CONSTANT_POOL_ADDRESS_P (x))
8299         return 1;
8300
8301       /* If we aren't looking for a memory address, we can accept a GP
8302          relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8303          knows how to handle this.  We can always accept a string
8304          constant, which is the other case in which SYMBOL_REF_FLAG
8305          will be set.  */
8306       if (! addr
8307           && ! addend
8308           && SYMBOL_REF_FLAG (x)
8309           && mode == (enum machine_mode) Pmode)
8310         return 1;
8311
8312       /* We can accept a string constant, which will have
8313          SYMBOL_REF_FLAG set but must be recognized by name to
8314          distinguish from a GP accessible symbol.  The name of a
8315          string constant will have been generated by
8316          ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def.  */
8317       if (SYMBOL_REF_FLAG (x))
8318         {
8319           const char *name = XSTR (x, 0);
8320
8321           return (name[0] == '*'
8322                   && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8323                               sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8324         }
8325
8326       return 0;
8327
8328     case LABEL_REF:
8329       if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8330         return 0;
8331       return 1;
8332
8333     case CONST_INT:
8334       if (addr && ! addend)
8335         return 0;
8336       return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8337
8338     case REG:
8339       /* We need to treat $gp as a legitimate constant, because
8340          mips16_gp_pseudo_reg assumes that.  */
8341       return REGNO (x) == GP_REG_FIRST + 28;
8342     }
8343 }
8344
8345 /* Write out code to move floating point arguments in or out of
8346    general registers.  Output the instructions to FILE.  FP_CODE is
8347    the code describing which arguments are present (see the comment at
8348    the definition of CUMULATIVE_ARGS in mips.h).  FROM_FP_P is non-zero if
8349    we are copying from the floating point registers.  */
8350
8351 static void
8352 mips16_fp_args (file, fp_code, from_fp_p)
8353      FILE *file;
8354      int fp_code;
8355      int from_fp_p;
8356 {
8357   const char *s;
8358   int gparg, fparg;
8359   unsigned int f;
8360
8361   /* This code only works for the original 32 bit ABI and the O64 ABI.  */
8362   if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8363     abort ();
8364
8365   if (from_fp_p)
8366     s = "mfc1";
8367   else
8368     s = "mtc1";
8369   gparg = GP_ARG_FIRST;
8370   fparg = FP_ARG_FIRST;
8371   for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8372     {
8373       if ((f & 3) == 1)
8374         {
8375           if ((fparg & 1) != 0)
8376             ++fparg;
8377           fprintf (file, "\t%s\t%s,%s\n", s,
8378                    reg_names[gparg], reg_names[fparg]);
8379         }
8380       else if ((f & 3) == 2)
8381         {
8382           if (TARGET_64BIT)
8383             fprintf (file, "\td%s\t%s,%s\n", s,
8384                      reg_names[gparg], reg_names[fparg]);
8385           else
8386             {
8387               if ((fparg & 1) != 0)
8388                 ++fparg;
8389               if (TARGET_BIG_ENDIAN)
8390                 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8391                          reg_names[gparg], reg_names[fparg + 1], s,
8392                          reg_names[gparg + 1], reg_names[fparg]);
8393               else
8394                 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8395                          reg_names[gparg], reg_names[fparg], s,
8396                          reg_names[gparg + 1], reg_names[fparg + 1]);
8397               ++gparg;
8398               ++fparg;
8399             }
8400         }
8401       else
8402         abort ();
8403
8404       ++gparg;
8405       ++fparg;
8406     }
8407 }
8408
8409 /* Build a mips16 function stub.  This is used for functions which
8410    take aruments in the floating point registers.  It is 32 bit code
8411    that moves the floating point args into the general registers, and
8412    then jumps to the 16 bit code.  */
8413
8414 static void
8415 build_mips16_function_stub (file)
8416      FILE *file;
8417 {
8418   const char *fnname;
8419   char *secname, *stubname;
8420   tree stubid, stubdecl;
8421   int need_comma;
8422   unsigned int f;
8423
8424   fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8425   secname = (char *) alloca (strlen (fnname) + 20);
8426   sprintf (secname, ".mips16.fn.%s", fnname);
8427   stubname = (char *) alloca (strlen (fnname) + 20);
8428   sprintf (stubname, "__fn_stub_%s", fnname);
8429   stubid = get_identifier (stubname);
8430   stubdecl = build_decl (FUNCTION_DECL, stubid,
8431                          build_function_type (void_type_node, NULL_TREE));
8432   DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8433
8434   fprintf (file, "\t# Stub function for %s (", current_function_name);
8435   need_comma = 0;
8436   for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8437     {
8438       fprintf (file, "%s%s",
8439                need_comma ? ", " : "",
8440                (f & 3) == 1 ? "float" : "double");
8441       need_comma = 1;
8442     }
8443   fprintf (file, ")\n");
8444
8445   fprintf (file, "\t.set\tnomips16\n");
8446   function_section (stubdecl);
8447   ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8448
8449   /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8450      within a .ent, and we can not emit another .ent.  */
8451 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8452   fputs ("\t.ent\t", file);
8453   assemble_name (file, stubname);
8454   fputs ("\n", file);
8455 #endif
8456
8457   assemble_name (file, stubname);
8458   fputs (":\n", file);
8459
8460   /* We don't want the assembler to insert any nops here.  */
8461   fprintf (file, "\t.set\tnoreorder\n");
8462
8463   mips16_fp_args (file, current_function_args_info.fp_code, 1);
8464
8465   fprintf (asm_out_file, "\t.set\tnoat\n");
8466   fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8467   assemble_name (file, fnname);
8468   fprintf (file, "\n");
8469   fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8470   fprintf (asm_out_file, "\t.set\tat\n");
8471
8472   /* Unfortunately, we can't fill the jump delay slot.  We can't fill
8473      with one of the mfc1 instructions, because the result is not
8474      available for one instruction, so if the very first instruction
8475      in the function refers to the register, it will see the wrong
8476      value.  */
8477   fprintf (file, "\tnop\n");
8478
8479   fprintf (file, "\t.set\treorder\n");
8480
8481 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8482   fputs ("\t.end\t", file);
8483   assemble_name (file, stubname);
8484   fputs ("\n", file);
8485 #endif
8486
8487   fprintf (file, "\t.set\tmips16\n");
8488
8489   function_section (current_function_decl);
8490 }
8491
8492 /* We keep a list of functions for which we have already built stubs
8493    in build_mips16_call_stub.  */
8494
8495 struct mips16_stub
8496 {
8497   struct mips16_stub *next;
8498   char *name;
8499   int fpret;
8500 };
8501
8502 static struct mips16_stub *mips16_stubs;
8503
8504 /* Build a call stub for a mips16 call.  A stub is needed if we are
8505    passing any floating point values which should go into the floating
8506    point registers.  If we are, and the call turns out to be to a 32
8507    bit function, the stub will be used to move the values into the
8508    floating point registers before calling the 32 bit function.  The
8509    linker will magically adjust the function call to either the 16 bit
8510    function or the 32 bit stub, depending upon where the function call
8511    is actually defined.
8512
8513    Similarly, we need a stub if the return value might come back in a
8514    floating point register.
8515
8516    RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8517    (RETVAL is NULL if this is call rather than call_value).  FP_CODE
8518    is the code built by function_arg.  This function returns a nonzero
8519    value if it builds the call instruction itself.  */
8520
8521 int
8522 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8523      rtx retval;
8524      rtx fnmem;
8525      rtx arg_size;
8526      int fp_code;
8527 {
8528   int fpret;
8529   rtx fn;
8530   const char *fnname;
8531   char *secname, *stubname;
8532   struct mips16_stub *l;
8533   tree stubid, stubdecl;
8534   int need_comma;
8535   unsigned int f;
8536
8537   /* We don't need to do anything if we aren't in mips16 mode, or if
8538      we were invoked with the -msoft-float option.  */
8539   if (! TARGET_MIPS16 || ! mips16_hard_float)
8540     return 0;
8541
8542   /* Figure out whether the value might come back in a floating point
8543      register.  */
8544   fpret = (retval != 0
8545            && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8546            && (! TARGET_SINGLE_FLOAT
8547                || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8548
8549   /* We don't need to do anything if there were no floating point
8550      arguments and the value will not be returned in a floating point
8551      register.  */
8552   if (fp_code == 0 && ! fpret)
8553     return 0;
8554
8555   if (GET_CODE (fnmem) != MEM)
8556     abort ();
8557   fn = XEXP (fnmem, 0);
8558
8559   /* We don't need to do anything if this is a call to a special
8560      mips16 support function.  */
8561   if (GET_CODE (fn) == SYMBOL_REF
8562       && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8563     return 0;
8564
8565   /* This code will only work for o32 and o64 abis.  The other ABI's
8566      require more sophisticated support.  */
8567   if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8568     abort ();
8569
8570   /* We can only handle SFmode and DFmode floating point return
8571      values.  */
8572   if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8573     abort ();
8574
8575   /* If we're calling via a function pointer, then we must always call
8576      via a stub.  There are magic stubs provided in libgcc.a for each
8577      of the required cases.  Each of them expects the function address
8578      to arrive in register $2.  */
8579
8580   if (GET_CODE (fn) != SYMBOL_REF)
8581     {
8582       char buf[30];
8583       tree id;
8584       rtx stub_fn, stub_mem, insn;
8585
8586       /* ??? If this code is modified to support other ABI's, we need
8587          to handle PARALLEL return values here.  */
8588
8589       sprintf (buf, "__mips16_call_stub_%s%d",
8590                (fpret
8591                 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8592                 : ""),
8593                fp_code);
8594       id = get_identifier (buf);
8595       stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8596       stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8597
8598       emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8599
8600       if (retval == NULL_RTX)
8601         insn = gen_call_internal0 (stub_mem, arg_size,
8602                                    gen_rtx (REG, SImode,
8603                                             GP_REG_FIRST + 31));
8604       else
8605         insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8606                                          gen_rtx (REG, SImode,
8607                                                   GP_REG_FIRST + 31));
8608       insn = emit_call_insn (insn);
8609
8610       /* Put the register usage information on the CALL.  */
8611       if (GET_CODE (insn) != CALL_INSN)
8612         abort ();
8613       CALL_INSN_FUNCTION_USAGE (insn) =
8614         gen_rtx (EXPR_LIST, VOIDmode,
8615                  gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8616                  CALL_INSN_FUNCTION_USAGE (insn));
8617
8618       /* If we are handling a floating point return value, we need to
8619          save $18 in the function prologue.  Putting a note on the
8620          call will mean that regs_ever_live[$18] will be true if the
8621          call is not eliminated, and we can check that in the prologue
8622          code.  */
8623       if (fpret)
8624         CALL_INSN_FUNCTION_USAGE (insn) =
8625           gen_rtx (EXPR_LIST, VOIDmode,
8626                    gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8627                    CALL_INSN_FUNCTION_USAGE (insn));
8628
8629       /* Return 1 to tell the caller that we've generated the call
8630          insn.  */
8631       return 1;
8632     }
8633
8634   /* We know the function we are going to call.  If we have already
8635      built a stub, we don't need to do anything further.  */
8636
8637   fnname = XSTR (fn, 0);
8638   for (l = mips16_stubs; l != NULL; l = l->next)
8639     if (strcmp (l->name, fnname) == 0)
8640       break;
8641
8642   if (l == NULL)
8643     {
8644       /* Build a special purpose stub.  When the linker sees a
8645          function call in mips16 code, it will check where the target
8646          is defined.  If the target is a 32 bit call, the linker will
8647          search for the section defined here.  It can tell which
8648          symbol this section is associated with by looking at the
8649          relocation information (the name is unreliable, since this
8650          might be a static function).  If such a section is found, the
8651          linker will redirect the call to the start of the magic
8652          section.
8653
8654          If the function does not return a floating point value, the
8655          special stub section is named
8656              .mips16.call.FNNAME
8657
8658          If the function does return a floating point value, the stub
8659          section is named
8660              .mips16.call.fp.FNNAME
8661          */
8662
8663       secname = (char *) alloca (strlen (fnname) + 40);
8664       sprintf (secname, ".mips16.call.%s%s",
8665                fpret ? "fp." : "",
8666                fnname);
8667       stubname = (char *) alloca (strlen (fnname) + 20);
8668       sprintf (stubname, "__call_stub_%s%s",
8669                fpret ? "fp_" : "",
8670                fnname);
8671       stubid = get_identifier (stubname);
8672       stubdecl = build_decl (FUNCTION_DECL, stubid,
8673                              build_function_type (void_type_node, NULL_TREE));
8674       DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8675
8676       fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8677                (fpret
8678                 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8679                 : ""),
8680                fnname);
8681       need_comma = 0;
8682       for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8683         {
8684           fprintf (asm_out_file, "%s%s",
8685                    need_comma ? ", " : "",
8686                    (f & 3) == 1 ? "float" : "double");
8687           need_comma = 1;
8688         }
8689       fprintf (asm_out_file, ")\n");
8690
8691       fprintf (asm_out_file, "\t.set\tnomips16\n");
8692       assemble_start_function (stubdecl, stubname);
8693
8694 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8695       fputs ("\t.ent\t", asm_out_file);
8696       assemble_name (asm_out_file, stubname);
8697       fputs ("\n", asm_out_file);
8698
8699       assemble_name (asm_out_file, stubname);
8700       fputs (":\n", asm_out_file);
8701 #endif
8702
8703       /* We build the stub code by hand.  That's the only way we can
8704          do it, since we can't generate 32 bit code during a 16 bit
8705          compilation. */
8706
8707       /* We don't want the assembler to insert any nops here.  */
8708       fprintf (asm_out_file, "\t.set\tnoreorder\n");
8709
8710       mips16_fp_args (asm_out_file, fp_code, 0);
8711
8712       if (! fpret)
8713         {
8714           fprintf (asm_out_file, "\t.set\tnoat\n");
8715           fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8716                    fnname);
8717           fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8718           fprintf (asm_out_file, "\t.set\tat\n");
8719           /* Unfortunately, we can't fill the jump delay slot.  We
8720              can't fill with one of the mtc1 instructions, because the
8721              result is not available for one instruction, so if the
8722              very first instruction in the function refers to the
8723              register, it will see the wrong value.  */
8724           fprintf (asm_out_file, "\tnop\n");
8725         }
8726       else
8727         {
8728           fprintf (asm_out_file, "\tmove\t%s,%s\n",
8729                    reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8730           fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8731           /* As above, we can't fill the delay slot.  */
8732           fprintf (asm_out_file, "\tnop\n");
8733           if (GET_MODE (retval) == SFmode)
8734             fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8735                      reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8736           else
8737             {
8738               if (TARGET_BIG_ENDIAN)
8739                 {
8740                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8741                            reg_names[GP_REG_FIRST + 2],
8742                            reg_names[FP_REG_FIRST + 1]);
8743                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8744                            reg_names[GP_REG_FIRST + 3],
8745                            reg_names[FP_REG_FIRST + 0]);
8746                 }
8747               else
8748                 {
8749                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8750                            reg_names[GP_REG_FIRST + 2],
8751                            reg_names[FP_REG_FIRST + 0]);
8752                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8753                            reg_names[GP_REG_FIRST + 3],
8754                            reg_names[FP_REG_FIRST + 1]);
8755                 }
8756             }
8757           fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8758           /* As above, we can't fill the delay slot.  */
8759           fprintf (asm_out_file, "\tnop\n");
8760         }
8761
8762       fprintf (asm_out_file, "\t.set\treorder\n");
8763
8764 #ifdef ASM_DECLARE_FUNCTION_SIZE
8765       ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8766 #endif
8767
8768 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8769       fputs ("\t.end\t", asm_out_file);
8770       assemble_name (asm_out_file, stubname);
8771       fputs ("\n", asm_out_file);
8772 #endif
8773
8774       fprintf (asm_out_file, "\t.set\tmips16\n");
8775
8776       /* Record this stub.  */
8777       l = (struct mips16_stub *) xmalloc (sizeof *l);
8778       l->name = xstrdup (fnname);
8779       l->fpret = fpret;
8780       l->next = mips16_stubs;
8781       mips16_stubs = l;
8782     }
8783
8784   /* If we expect a floating point return value, but we've built a
8785      stub which does not expect one, then we're in trouble.  We can't
8786      use the existing stub, because it won't handle the floating point
8787      value.  We can't build a new stub, because the linker won't know
8788      which stub to use for the various calls in this object file.
8789      Fortunately, this case is illegal, since it means that a function
8790      was declared in two different ways in a single compilation.  */
8791   if (fpret && ! l->fpret)
8792     error ("can not handle inconsistent calls to `%s'", fnname);
8793
8794   /* If we are calling a stub which handles a floating point return
8795      value, we need to arrange to save $18 in the prologue.  We do
8796      this by marking the function call as using the register.  The
8797      prologue will later see that it is used, and emit code to save
8798      it.  */
8799
8800   if (l->fpret)
8801     {
8802       rtx insn;
8803
8804       if (retval == NULL_RTX)
8805         insn = gen_call_internal0 (fnmem, arg_size,
8806                                    gen_rtx (REG, SImode,
8807                                             GP_REG_FIRST + 31));
8808       else
8809         insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8810                                          gen_rtx (REG, SImode,
8811                                                   GP_REG_FIRST + 31));
8812       insn = emit_call_insn (insn);
8813
8814       if (GET_CODE (insn) != CALL_INSN)
8815         abort ();
8816
8817       CALL_INSN_FUNCTION_USAGE (insn) =
8818         gen_rtx (EXPR_LIST, VOIDmode,
8819                  gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8820                  CALL_INSN_FUNCTION_USAGE (insn));
8821
8822       /* Return 1 to tell the caller that we've generated the call
8823          insn.  */
8824       return 1;
8825     }
8826
8827   /* Return 0 to let the caller generate the call insn.  */
8828   return 0;
8829 }
8830
8831 /* This function looks through the code for a function, and tries to
8832    optimize the usage of the $gp register.  We arrange to copy $gp
8833    into a pseudo-register, and then let gcc's normal reload handling
8834    deal with the pseudo-register.  Unfortunately, if reload choose to
8835    put the pseudo-register into a call-clobbered register, it will
8836    emit saves and restores for that register around any function
8837    calls.  We don't need the saves, and it's faster to copy $gp than
8838    to do an actual restore.  ??? This still means that we waste a
8839    stack slot.
8840
8841    This is an optimization, and the code which gcc has actually
8842    generated is correct, so we do not need to catch all cases.  */
8843
8844 static void
8845 mips16_optimize_gp (first)
8846      rtx first;
8847 {
8848   rtx gpcopy, slot, insn;
8849
8850   /* Look through the instructions.  Set GPCOPY to the register which
8851      holds a copy of $gp.  Set SLOT to the stack slot where it is
8852      saved.  If we find an instruction which sets GPCOPY to anything
8853      other than $gp or SLOT, then we can't use it.  If we find an
8854      instruction which sets SLOT to anything other than GPCOPY, we
8855      can't use it.  */
8856
8857   gpcopy = NULL_RTX;
8858   slot = NULL_RTX;
8859   for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8860     {
8861       rtx set;
8862
8863       if (! INSN_P (insn))
8864         continue;
8865
8866       set = PATTERN (insn);
8867
8868       /* We know that all references to memory will be inside a SET,
8869          because there is no other way to access memory on the mips16.
8870          We don't have to worry about a PARALLEL here, because the
8871          mips.md file will never generate them for memory references.  */
8872       if (GET_CODE (set) != SET)
8873         continue;
8874
8875       if (gpcopy == NULL_RTX
8876           && GET_CODE (SET_SRC (set)) == CONST
8877           && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8878           && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8879           && GET_CODE (SET_DEST (set)) == REG
8880           && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8881         gpcopy = SET_DEST (set);
8882       else if (slot == NULL_RTX
8883                && gpcopy != NULL_RTX
8884                && GET_CODE (SET_DEST (set)) == MEM
8885                && GET_CODE (SET_SRC (set)) == REG
8886                && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8887                && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8888         {
8889           rtx base, offset;
8890
8891           offset = const0_rtx;
8892           base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8893           if (GET_CODE (base) == REG
8894               && (REGNO (base) == STACK_POINTER_REGNUM
8895                   || REGNO (base) == FRAME_POINTER_REGNUM))
8896             slot = SET_DEST (set);
8897         }
8898       else if (gpcopy != NULL_RTX
8899                && (GET_CODE (SET_DEST (set)) == REG
8900                    || GET_CODE (SET_DEST (set)) == SUBREG)
8901                && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8902                && (GET_CODE (SET_DEST (set)) != REG
8903                    || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8904                    || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
8905                    || ((GET_CODE (SET_SRC (set)) != CONST
8906                         || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8907                         || (REGNO (XEXP (SET_SRC (set), 0))
8908                             != GP_REG_FIRST + 28))
8909                        && ! rtx_equal_p (SET_SRC (set), slot))))
8910         break;
8911       else if (slot != NULL_RTX
8912                && GET_CODE (SET_DEST (set)) == MEM
8913                && rtx_equal_p (SET_DEST (set), slot)
8914                && (GET_CODE (SET_SRC (set)) != REG
8915                    || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8916         break;
8917     }
8918
8919   /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8920      different optimization.  Any time we find a copy of $28 into a
8921      register, followed by an add of a symbol_ref to that register, we
8922      convert it to load the value from the constant table instead.
8923      The copy and add will take six bytes, just as the load and
8924      constant table entry will take six bytes.  However, it is
8925      possible that the constant table entry will be shared.
8926
8927      This could be a peephole optimization, but I don't know if the
8928      peephole code can call force_const_mem.
8929
8930      Using the same register for the copy of $28 and the add of the
8931      symbol_ref is actually pretty likely, since the add instruction
8932      requires the destination and the first addend to be the same
8933      register.  */
8934
8935   if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8936     {
8937       rtx next;
8938
8939       /* This optimization is only reasonable if the constant table
8940          entries are only 4 bytes.  */
8941       if (Pmode != SImode)
8942         return;
8943
8944       for (insn = first; insn != NULL_RTX; insn = next)
8945         {
8946           rtx set1, set2;
8947
8948           next = insn;
8949           do
8950             {
8951               next = NEXT_INSN (next);
8952             }
8953           while (next != NULL_RTX
8954                  && (GET_CODE (next) == NOTE
8955                      || (GET_CODE (next) == INSN
8956                          && (GET_CODE (PATTERN (next)) == USE
8957                              || GET_CODE (PATTERN (next)) == CLOBBER))));
8958
8959           if (next == NULL_RTX)
8960             break;
8961
8962           if (! INSN_P (insn))
8963             continue;
8964
8965           if (! INSN_P (next))
8966             continue;
8967
8968           set1 = PATTERN (insn);
8969           if (GET_CODE (set1) != SET)
8970             continue;
8971           set2 = PATTERN (next);
8972           if (GET_CODE (set2) != SET)
8973             continue;
8974
8975           if (GET_CODE (SET_DEST (set1)) == REG
8976               && GET_CODE (SET_SRC (set1)) == CONST
8977               && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8978               && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8979               && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8980               && GET_CODE (SET_SRC (set2)) == PLUS
8981               && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8982               && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8983               && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8984             {
8985               rtx sym;
8986
8987               /* We've found a case we can change to load from the
8988                  constant table.  */
8989
8990               sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8991               if (GET_CODE (sym) != SYMBOL_REF)
8992                 abort ();
8993               emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8994                                         force_const_mem (Pmode, sym)),
8995                                next);
8996
8997               PUT_CODE (insn, NOTE);
8998               NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8999               NOTE_SOURCE_FILE (insn) = 0;
9000
9001               PUT_CODE (next, NOTE);
9002               NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9003               NOTE_SOURCE_FILE (next) = 0;
9004             }
9005         }
9006
9007       return;
9008     }
9009
9010   /* We can safely remove all assignments to SLOT from GPCOPY, and
9011      replace all assignments from SLOT to GPCOPY with assignments from
9012      $28.  */
9013
9014   for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9015     {
9016       rtx set;
9017
9018       if (! INSN_P (insn))
9019         continue;
9020
9021       set = PATTERN (insn);
9022       if (GET_CODE (set) != SET
9023           || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9024         continue;
9025
9026       if (GET_CODE (SET_DEST (set)) == MEM
9027           && rtx_equal_p (SET_DEST (set), slot)
9028           && GET_CODE (SET_SRC (set)) == REG
9029           && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9030         {
9031           PUT_CODE (insn, NOTE);
9032           NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9033           NOTE_SOURCE_FILE (insn) = 0;
9034         }
9035       else if (GET_CODE (SET_DEST (set)) == REG
9036                && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9037                && GET_CODE (SET_SRC (set)) == MEM
9038                && rtx_equal_p (SET_SRC (set), slot))
9039         {
9040           emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9041                                     gen_rtx (CONST, Pmode,
9042                                              gen_rtx (REG, Pmode,
9043                                                       GP_REG_FIRST + 28))),
9044                            insn);
9045           PUT_CODE (insn, NOTE);
9046           NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9047           NOTE_SOURCE_FILE (insn) = 0;
9048         }
9049     }
9050 }
9051
9052 /* We keep a list of constants we which we have to add to internal
9053    constant tables in the middle of large functions.  */
9054
9055 struct constant
9056 {
9057   struct constant *next;
9058   rtx value;
9059   rtx label;
9060   enum machine_mode mode;
9061 };
9062
9063 /* Add a constant to the list in *PCONSTANTS.  */
9064
9065 static rtx
9066 add_constant (pconstants, val, mode)
9067      struct constant **pconstants;
9068      rtx val;
9069      enum machine_mode mode;
9070 {
9071   struct constant *c;
9072
9073   for (c = *pconstants; c != NULL; c = c->next)
9074     if (mode == c->mode && rtx_equal_p (val, c->value))
9075       return c->label;
9076
9077   c = (struct constant *) xmalloc (sizeof *c);
9078   c->value = val;
9079   c->mode = mode;
9080   c->label = gen_label_rtx ();
9081   c->next = *pconstants;
9082   *pconstants = c;
9083   return c->label;
9084 }
9085
9086 /* Dump out the constants in CONSTANTS after INSN.  */
9087
9088 static void
9089 dump_constants (constants, insn)
9090      struct constant *constants;
9091      rtx insn;
9092 {
9093   struct constant *c;
9094   int align;
9095
9096   c = constants;
9097   align = 0;
9098   while (c != NULL)
9099     {
9100       rtx r;
9101       struct constant *next;
9102
9103       switch (GET_MODE_SIZE (c->mode))
9104         {
9105         case 1:
9106           align = 0;
9107           break;
9108         case 2:
9109           if (align < 1)
9110             insn = emit_insn_after (gen_align_2 (), insn);
9111           align = 1;
9112           break;
9113         case 4:
9114           if (align < 2)
9115             insn = emit_insn_after (gen_align_4 (), insn);
9116           align = 2;
9117           break;
9118         default:
9119           if (align < 3)
9120             insn = emit_insn_after (gen_align_8 (), insn);
9121           align = 3;
9122           break;
9123         }
9124
9125       insn = emit_label_after (c->label, insn);
9126
9127       switch (c->mode)
9128         {
9129         case QImode:
9130           r = gen_consttable_qi (c->value);
9131           break;
9132         case HImode:
9133           r = gen_consttable_hi (c->value);
9134           break;
9135         case SImode:
9136           r = gen_consttable_si (c->value);
9137           break;
9138         case SFmode:
9139           r = gen_consttable_sf (c->value);
9140           break;
9141         case DImode:
9142           r = gen_consttable_di (c->value);
9143           break;
9144         case DFmode:
9145           r = gen_consttable_df (c->value);
9146           break;
9147         default:
9148           abort ();
9149         }
9150
9151       insn = emit_insn_after (r, insn);
9152
9153       next = c->next;
9154       free (c);
9155       c = next;
9156     }
9157
9158   emit_barrier_after (insn);
9159 }
9160
9161 /* Find the symbol in an address expression.  */
9162
9163 static rtx
9164 mips_find_symbol (addr)
9165      rtx addr;
9166 {
9167   if (GET_CODE (addr) == MEM)
9168     addr = XEXP (addr, 0);
9169   while (GET_CODE (addr) == CONST)
9170     addr = XEXP (addr, 0);
9171   if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9172     return addr;
9173   if (GET_CODE (addr) == PLUS)
9174     {
9175       rtx l1, l2;
9176
9177       l1 = mips_find_symbol (XEXP (addr, 0));
9178       l2 = mips_find_symbol (XEXP (addr, 1));
9179       if (l1 != NULL_RTX && l2 == NULL_RTX)
9180         return l1;
9181       else if (l1 == NULL_RTX && l2 != NULL_RTX)
9182         return l2;
9183     }
9184   return NULL_RTX;
9185 }
9186
9187 /* Exported to toplev.c.
9188
9189    Do a final pass over the function, just before delayed branch
9190    scheduling.  */
9191
9192 void
9193 machine_dependent_reorg (first)
9194      rtx first;
9195 {
9196   int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9197   rtx insn;
9198   struct constant *constants;
9199
9200   if (! TARGET_MIPS16)
9201     return;
9202
9203   /* If $gp is used, try to remove stores, and replace loads with
9204      copies from $gp.  */
9205   if (optimize)
9206     mips16_optimize_gp (first);
9207
9208   /* Scan the function looking for PC relative loads which may be out
9209      of range.  All such loads will either be from the constant table,
9210      or be getting the address of a constant string.  If the size of
9211      the function plus the size of the constant table is less than
9212      0x8000, then all loads are in range.  */
9213
9214   insns_len = 0;
9215   for (insn = first; insn; insn = NEXT_INSN (insn))
9216     {
9217       insns_len += get_attr_length (insn);
9218
9219       /* ??? We put switch tables in .text, but we don't define
9220          JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9221          compute their lengths correctly.  */
9222       if (GET_CODE (insn) == JUMP_INSN)
9223         {
9224           rtx body;
9225
9226           body = PATTERN (insn);
9227           if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9228             insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9229                           * GET_MODE_SIZE (GET_MODE (body)));
9230           insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9231         }
9232     }
9233
9234   /* Store the original value of insns_len in current_frame_info, so
9235      that simple_memory_operand can look at it.  */
9236   current_frame_info.insns_len = insns_len;
9237
9238   pool_size = get_pool_size ();
9239   if (insns_len + pool_size + mips_string_length < 0x8000)
9240     return;
9241
9242   /* Loop over the insns and figure out what the maximum internal pool
9243      size could be.  */
9244   max_internal_pool_size = 0;
9245   for (insn = first; insn; insn = NEXT_INSN (insn))
9246     {
9247       if (GET_CODE (insn) == INSN
9248           && GET_CODE (PATTERN (insn)) == SET)
9249         {
9250           rtx src;
9251
9252           src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9253           if (src == NULL_RTX)
9254             continue;
9255           if (CONSTANT_POOL_ADDRESS_P (src))
9256             max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9257           else if (SYMBOL_REF_FLAG (src))
9258             max_internal_pool_size += GET_MODE_SIZE (Pmode);
9259         }
9260     }
9261
9262   constants = NULL;
9263   addr = 0;
9264   first_constant_ref = -1;
9265
9266   for (insn = first; insn; insn = NEXT_INSN (insn))
9267     {
9268       if (GET_CODE (insn) == INSN
9269           && GET_CODE (PATTERN (insn)) == SET)
9270         {
9271           rtx val, src;
9272           enum machine_mode mode = VOIDmode;
9273
9274           val = NULL_RTX;
9275           src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9276           if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9277             {
9278               /* ??? This is very conservative, which means that we
9279                  will generate too many copies of the constant table.
9280                  The only solution would seem to be some form of
9281                  relaxing.  */
9282               if (((insns_len - addr)
9283                    + max_internal_pool_size
9284                    + get_pool_offset (src))
9285                   >= 0x8000)
9286                 {
9287                   val = get_pool_constant (src);
9288                   mode = get_pool_mode (src);
9289                 }
9290               max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9291             }
9292           else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9293             {
9294               /* Including all of mips_string_length is conservative,
9295                  and so is including all of max_internal_pool_size.  */
9296               if (((insns_len - addr)
9297                    + max_internal_pool_size
9298                    + pool_size
9299                    + mips_string_length)
9300                   >= 0x8000)
9301                 {
9302                   val = src;
9303                   mode = Pmode;
9304                 }
9305               max_internal_pool_size -= Pmode;
9306             }
9307
9308           if (val != NULL_RTX)
9309             {
9310               rtx lab, newsrc;
9311
9312               /* This PC relative load is out of range.  ??? In the
9313                  case of a string constant, we are only guessing that
9314                  it is range, since we don't know the offset of a
9315                  particular string constant.  */
9316
9317               lab = add_constant (&constants, val, mode);
9318               newsrc = gen_rtx (MEM, mode,
9319                                 gen_rtx (LABEL_REF, VOIDmode, lab));
9320               RTX_UNCHANGING_P (newsrc) = 1;
9321               PATTERN (insn) = gen_rtx (SET, VOIDmode,
9322                                         SET_DEST (PATTERN (insn)),
9323                                         newsrc);
9324               INSN_CODE (insn) = -1;
9325
9326               if (first_constant_ref < 0)
9327                 first_constant_ref = addr;
9328             }
9329         }
9330
9331       addr += get_attr_length (insn);
9332
9333       /* ??? We put switch tables in .text, but we don't define
9334          JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9335          compute their lengths correctly.  */
9336       if (GET_CODE (insn) == JUMP_INSN)
9337         {
9338           rtx body;
9339
9340           body = PATTERN (insn);
9341           if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9342             addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9343                           * GET_MODE_SIZE (GET_MODE (body)));
9344           addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9345         }
9346
9347       if (GET_CODE (insn) == BARRIER)
9348         {
9349           /* Output any constants we have accumulated.  Note that we
9350              don't need to change ADDR, since its only use is
9351              subtraction from INSNS_LEN, and both would be changed by
9352              the same amount.
9353              ??? If the instructions up to the next barrier reuse a
9354              constant, it would often be better to continue
9355              accumulating.  */
9356           if (constants != NULL)
9357             dump_constants (constants, insn);
9358           constants = NULL;
9359           first_constant_ref = -1;
9360         }
9361
9362       if (constants != NULL
9363                && (NEXT_INSN (insn) == NULL
9364                    || (first_constant_ref >= 0
9365                        && (((addr - first_constant_ref)
9366                             + 2 /* for alignment */
9367                             + 2 /* for a short jump insn */
9368                             + pool_size)
9369                            >= 0x8000))))
9370         {
9371           /* If we haven't had a barrier within 0x8000 bytes of a
9372              constant reference or we are at the end of the function,
9373              emit a barrier now. */
9374
9375           rtx label, jump, barrier;
9376
9377           label = gen_label_rtx ();
9378           jump = emit_jump_insn_after (gen_jump (label), insn);
9379           JUMP_LABEL (jump) = label;
9380           LABEL_NUSES (label) = 1;
9381           barrier = emit_barrier_after (jump);
9382           emit_label_after (label, barrier);
9383           first_constant_ref = -1;
9384         }
9385      }
9386
9387   /* ??? If we output all references to a constant in internal
9388      constants table, we don't need to output the constant in the real
9389      constant table, but we have no way to prevent that.  */
9390 }
9391
9392 /* Return nonzero if X is a SIGN or ZERO extend operator.  */
9393 int
9394 extend_operator (x, mode)
9395      rtx x;
9396      enum machine_mode mode ATTRIBUTE_UNUSED;
9397 {
9398   enum rtx_code code = GET_CODE (x);
9399   return code == SIGN_EXTEND || code == ZERO_EXTEND;
9400 }
9401
9402 /* Accept any operator that can be used to shift the high half of the
9403    input value to the lower half, suitable for truncation.  The
9404    remainder (the lower half of the input, and the upper half of the
9405    output) will be discarded.  */
9406 int
9407 highpart_shift_operator (x, mode)
9408      rtx x;
9409      enum machine_mode mode ATTRIBUTE_UNUSED;
9410 {
9411   enum rtx_code code = GET_CODE (x);
9412   return (code == LSHIFTRT
9413           || code == ASHIFTRT
9414           || code == ROTATERT
9415           || code == ROTATE);
9416 }
9417
9418 /* Return the length of INSN.  LENGTH is the initial length computed by
9419    attributes in the machine-description file.  */
9420
9421 int
9422 mips_adjust_insn_length (insn, length)
9423      rtx insn;
9424      int length;
9425 {
9426   /* A unconditional jump has an unfilled delay slot if it is not part
9427      of a sequence.  A conditional jump normally has a delay slot, but
9428      does not on MIPS16.  */
9429   if (simplejump_p (insn)
9430       || (!TARGET_MIPS16  && (GET_CODE (insn) == JUMP_INSN
9431                               || GET_CODE (insn) == CALL_INSN)))
9432     length += 4;
9433
9434   /* All MIPS16 instructions are a measly two bytes.  */
9435   if (TARGET_MIPS16)
9436     length /= 2;
9437
9438   return length;
9439 }
9440
9441 /* Output assembly instructions to peform a conditional branch.
9442
9443    INSN is the branch instruction.  OPERANDS[0] is the condition.
9444    OPERANDS[1] is the target of the branch.  OPERANDS[2] is the target
9445    of the first operand to the condition.  If TWO_OPERANDS_P is
9446    non-zero the comparison takes two operands; OPERANDS[3] will be the
9447    second operand.
9448
9449    If INVERTED_P is non-zero we are to branch if the condition does
9450    not hold.  If FLOAT_P is non-zero this is a floating-point comparison.
9451
9452    LENGTH is the length (in bytes) of the sequence we are to generate.
9453    That tells us whether to generate a simple conditional branch, or a
9454    reversed conditional branch around a `jr' instruction.  */
9455 char *
9456 mips_output_conditional_branch (insn,
9457                                 operands,
9458                                 two_operands_p,
9459                                 float_p,
9460                                 inverted_p,
9461                                 length)
9462      rtx insn;
9463      rtx *operands;
9464      int two_operands_p;
9465      int float_p;
9466      int inverted_p;
9467      int length;
9468 {
9469   static char buffer[200];
9470   /* The kind of comparison we are doing.  */
9471   enum rtx_code code = GET_CODE (operands[0]);
9472   /* Non-zero if the opcode for the comparison needs a `z' indicating
9473      that it is a comparision against zero.  */
9474   int need_z_p;
9475   /* A string to use in the assembly output to represent the first
9476      operand.  */
9477   const char *op1 = "%z2";
9478   /* A string to use in the assembly output to represent the second
9479      operand.  Use the hard-wired zero register if there's no second
9480      operand.  */
9481   const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9482   /* The operand-printing string for the comparison.  */
9483   const char *comp = (float_p ? "%F0" : "%C0");
9484   /* The operand-printing string for the inverted comparison.  */
9485   const char *inverted_comp = (float_p ? "%W0" : "%N0");
9486
9487   /* The MIPS processors (for levels of the ISA at least two), have
9488      "likely" variants of each branch instruction.  These instructions
9489      annul the instruction in the delay slot if the branch is not
9490      taken.  */
9491   mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9492
9493   if (!two_operands_p)
9494     {
9495       /* To compute whether than A > B, for example, we normally
9496          subtract B from A and then look at the sign bit.  But, if we
9497          are doing an unsigned comparison, and B is zero, we don't
9498          have to do the subtraction.  Instead, we can just check to
9499          see if A is non-zero.  Thus, we change the CODE here to
9500          reflect the simpler comparison operation.  */
9501       switch (code)
9502         {
9503         case GTU:
9504           code = NE;
9505           break;
9506
9507         case LEU:
9508           code = EQ;
9509           break;
9510
9511         case GEU:
9512           /* A condition which will always be true.  */
9513           code = EQ;
9514           op1 = "%.";
9515           break;
9516
9517         case LTU:
9518           /* A condition which will always be false. */
9519           code = NE;
9520           op1 = "%.";
9521           break;
9522
9523         default:
9524           /* Not a special case.  */
9525           break;
9526         }
9527     }
9528
9529   /* Relative comparisons are always done against zero.  But
9530      equality comparisons are done between two operands, and therefore
9531      do not require a `z' in the assembly language output.  */
9532   need_z_p = (!float_p && code != EQ && code != NE);
9533   /* For comparisons against zero, the zero is not provided
9534      explicitly.  */
9535   if (need_z_p)
9536     op2 = "";
9537
9538   /* Begin by terminating the buffer.  That way we can always use
9539      strcat to add to it.  */
9540   buffer[0] = '\0';
9541
9542   switch (length)
9543     {
9544     case 4:
9545     case 8:
9546       /* Just a simple conditional branch.  */
9547       if (float_p)
9548         sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9549                  inverted_p ? inverted_comp : comp);
9550       else
9551         sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9552                  inverted_p ? inverted_comp : comp,
9553                  need_z_p ? "z" : "",
9554                  op1,
9555                  op2);
9556       return buffer;
9557
9558     case 12:
9559     case 16:
9560       {
9561         /* Generate a reversed conditional branch around ` j'
9562            instruction:
9563
9564                 .set noreorder
9565                 .set nomacro
9566                 bc    l
9567                 nop
9568                 j     target
9569                 .set macro
9570                 .set reorder
9571              l:
9572
9573            Because we have to jump four bytes *past* the following
9574            instruction if this branch was annulled, we can't just use
9575            a label, as in the picture above; there's no way to put the
9576            label after the next instruction, as the assembler does not
9577            accept `.L+4' as the target of a branch.  (We can't just
9578            wait until the next instruction is output; it might be a
9579            macro and take up more than four bytes.  Once again, we see
9580            why we want to eliminate macros.)
9581
9582            If the branch is annulled, we jump four more bytes that we
9583            would otherwise; that way we skip the annulled instruction
9584            in the delay slot.  */
9585
9586         const char *target
9587           = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9588         char *c;
9589
9590         strcpy (buffer, "%(%<");
9591         c = strchr (buffer, '\0');
9592         /* Generate the reversed comparision.  This takes four
9593            bytes.  */
9594         if (float_p)
9595           sprintf (c, "%%*b%s\t%%Z2%s",
9596                    inverted_p ? comp : inverted_comp,
9597                    target);
9598         else
9599           sprintf (c, "%%*b%s%s\t%s%s,%s",
9600                    inverted_p ? comp : inverted_comp,
9601                    need_z_p ? "z" : "",
9602                    op1,
9603                    op2,
9604                    target);
9605         strcat (c, "\n\tnop\n\tj\t%1");
9606         if (length == 16)
9607           /* The delay slot was unfilled.  Since we're inside
9608              .noreorder, the assembler will not fill in the NOP for
9609              us, so we must do it ourselves.  */
9610           strcat (buffer, "\n\tnop");
9611         strcat (buffer, "%>%)");
9612         return buffer;
9613       }
9614
9615     /* We do not currently use this code.  It handles jumps to
9616        arbitrary locations, using `jr', even across a 256MB boundary.
9617        We could add a -mhuge switch, and then use this code instead of
9618        the `j' alternative above when -mhuge was used.  */
9619 #if 0
9620     case 16:
9621     case 20:
9622       {
9623         /* Generate a reversed conditional branch around a `jr'
9624            instruction:
9625
9626                  .set noreorder
9627                  .set nomacro
9628                  .set noat
9629                  bc    l
9630                  la    $at, target
9631                  jr    $at
9632                  .set at
9633                  .set macro
9634                  .set reorder
9635               l:
9636
9637            Not pretty, but allows a conditional branch anywhere in the
9638            32-bit address space.  If the original branch is annulled,
9639            then the instruction in the delay slot should be executed
9640            only if the branch is taken.  The la instruction is really
9641            a macro which will usually take eight bytes, but sometimes
9642            takes only four, if the instruction to which we're jumping
9643            gets its own entry in the global pointer table, which will
9644            happen if its a case label.  The assembler will then
9645            generate only a four-byte sequence, rather than eight, and
9646            there seems to be no way to tell it not to.  Thus, we can't
9647            just use a `.+x' addressing form; we don't know what value
9648            to give for `x'.
9649
9650            So, we resort to using the explicit relocation syntax
9651            available in the assembler and do:
9652
9653               lw $at,%got_page(target)($gp)
9654               daddiu $at,$at,%got_ofst(target)
9655
9656            That way, this always takes up eight bytes, and we can use
9657            the `.+x' form.  Of course, these explicit machinations
9658            with relocation will not work with old assemblers.  Then
9659            again, neither do out-of-range branches, so we haven't lost
9660            anything.  */
9661
9662         /* The target of the reversed branch.  */
9663         const char *target
9664           = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9665         const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9666         const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9667         char *c;
9668
9669         strcpy (buffer, "%(%<%[");
9670         c = strchr (buffer, '\0');
9671         /* Generate the reversed comparision.  This takes four
9672            bytes.  */
9673         if (float_p)
9674           sprintf (c, "%%*b%s\t%%Z2%s",
9675                    inverted_p ? comp : inverted_comp,
9676                    target);
9677         else
9678           sprintf (c, "%%*b%s%s\t%s%s,%s",
9679                    inverted_p ? comp : inverted_comp,
9680                    need_z_p ? "z" : "",
9681                    op1,
9682                    op2,
9683                    target);
9684         c = strchr (buffer, '\0');
9685         /* Generate the load-address, and jump.  This takes twelve
9686            bytes, for a total of 16.  */
9687         sprintf (c,
9688                  "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9689                  at_register,
9690                  gp_register,
9691                  at_register,
9692                  at_register,
9693                  at_register);
9694         if (length == 20)
9695           /* The delay slot was unfilled.  Since we're inside
9696              .noreorder, the assembler will not fill in the NOP for
9697              us, so we must do it ourselves.  */
9698           strcat (buffer, "\n\tnop");
9699         strcat (buffer, "%]%>%)");
9700         return buffer;
9701       }
9702 #endif
9703
9704     default:
9705       abort ();
9706     }
9707
9708   /* NOTREACHED */
9709   return 0;
9710 }
9711
9712 /* Called to register all of our global variables with the garbage
9713    collector.  */
9714
9715 static void
9716 mips_add_gc_roots ()
9717 {
9718   ggc_add_rtx_root (&mips_load_reg, 1);
9719   ggc_add_rtx_root (&mips_load_reg2, 1);
9720   ggc_add_rtx_root (&mips_load_reg3, 1);
9721   ggc_add_rtx_root (&mips_load_reg4, 1);
9722   ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9723   ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9724   ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
9725 }
9726
9727 static enum processor_type
9728 mips_parse_cpu (cpu_string)
9729      const char *cpu_string;
9730 {
9731   const char *p = cpu_string;
9732   int seen_v = 0;
9733   enum processor_type cpu;
9734
9735   /* We need to cope with the various "vr" prefixes for the NEC 4300
9736      and 4100 processors.  */
9737   if (*p == 'v' || *p == 'V')
9738     seen_v = 1, p++;
9739
9740   if (*p == 'r' || *p == 'R')
9741     p++;
9742
9743   /* Since there is no difference between a R2000 and R3000 in
9744      terms of the scheduler, we collapse them into just an R3000.  */
9745
9746   cpu = PROCESSOR_DEFAULT;
9747   switch (*p)
9748     {
9749     case '2':
9750       if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
9751         cpu = PROCESSOR_R3000;
9752       break;
9753
9754     case '3':
9755       if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
9756         cpu = PROCESSOR_R3000;
9757       else if (!strcmp (p, "3900"))
9758         cpu = PROCESSOR_R3900;
9759       break;
9760
9761     case '4':
9762       if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
9763         cpu = PROCESSOR_R4000;
9764       /* The vr4100 is a non-FP ISA III processor with some extra
9765          instructions.  */
9766       else if (!strcmp (p, "4100"))
9767           cpu = PROCESSOR_R4100;
9768       /* The vr4300 is a standard ISA III processor, but with a different
9769          pipeline.  */
9770       else if (!strcmp (p, "4300"))
9771         cpu = PROCESSOR_R4300;
9772       /* The r4400 is exactly the same as the r4000 from the compiler's
9773          viewpoint.  */
9774       else if (!strcmp (p, "4400"))
9775         cpu = PROCESSOR_R4000;
9776       else if (!strcmp (p, "4600"))
9777         cpu = PROCESSOR_R4600;
9778       else if (!strcmp (p, "4650"))
9779         cpu = PROCESSOR_R4650;
9780       break;
9781
9782     case '5':
9783       if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
9784         cpu = PROCESSOR_R5000;
9785       break;
9786
9787     case '6':
9788       if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
9789         cpu = PROCESSOR_R6000;
9790       break;
9791
9792     case '8':
9793       if (!strcmp (p, "8000"))
9794         cpu = PROCESSOR_R8000;
9795       break;
9796
9797     case 'o':
9798       if (!strcmp (p, "orion"))
9799         cpu = PROCESSOR_R4600;
9800       break;
9801     }
9802
9803   if (seen_v
9804       && cpu != PROCESSOR_R4300
9805       && cpu != PROCESSOR_R4100
9806       && cpu != PROCESSOR_R5000)
9807     cpu = PROCESSOR_DEFAULT;
9808
9809   return cpu;
9810 }