1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
51 #include "tree-gimple.h"
52 #include "langhooks.h"
56 struct processor_costs cypress_costs
= {
57 COSTS_N_INSNS (2), /* int load */
58 COSTS_N_INSNS (2), /* int signed load */
59 COSTS_N_INSNS (2), /* int zeroed load */
60 COSTS_N_INSNS (2), /* float load */
61 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
62 COSTS_N_INSNS (5), /* fadd, fsub */
63 COSTS_N_INSNS (1), /* fcmp */
64 COSTS_N_INSNS (1), /* fmov, fmovr */
65 COSTS_N_INSNS (7), /* fmul */
66 COSTS_N_INSNS (37), /* fdivs */
67 COSTS_N_INSNS (37), /* fdivd */
68 COSTS_N_INSNS (63), /* fsqrts */
69 COSTS_N_INSNS (63), /* fsqrtd */
70 COSTS_N_INSNS (1), /* imul */
71 COSTS_N_INSNS (1), /* imulX */
72 0, /* imul bit factor */
73 COSTS_N_INSNS (1), /* idiv */
74 COSTS_N_INSNS (1), /* idivX */
75 COSTS_N_INSNS (1), /* movcc/movr */
76 0, /* shift penalty */
80 struct processor_costs supersparc_costs
= {
81 COSTS_N_INSNS (1), /* int load */
82 COSTS_N_INSNS (1), /* int signed load */
83 COSTS_N_INSNS (1), /* int zeroed load */
84 COSTS_N_INSNS (0), /* float load */
85 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
86 COSTS_N_INSNS (3), /* fadd, fsub */
87 COSTS_N_INSNS (3), /* fcmp */
88 COSTS_N_INSNS (1), /* fmov, fmovr */
89 COSTS_N_INSNS (3), /* fmul */
90 COSTS_N_INSNS (6), /* fdivs */
91 COSTS_N_INSNS (9), /* fdivd */
92 COSTS_N_INSNS (12), /* fsqrts */
93 COSTS_N_INSNS (12), /* fsqrtd */
94 COSTS_N_INSNS (4), /* imul */
95 COSTS_N_INSNS (4), /* imulX */
96 0, /* imul bit factor */
97 COSTS_N_INSNS (4), /* idiv */
98 COSTS_N_INSNS (4), /* idivX */
99 COSTS_N_INSNS (1), /* movcc/movr */
100 1, /* shift penalty */
104 struct processor_costs hypersparc_costs
= {
105 COSTS_N_INSNS (1), /* int load */
106 COSTS_N_INSNS (1), /* int signed load */
107 COSTS_N_INSNS (1), /* int zeroed load */
108 COSTS_N_INSNS (1), /* float load */
109 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
110 COSTS_N_INSNS (1), /* fadd, fsub */
111 COSTS_N_INSNS (1), /* fcmp */
112 COSTS_N_INSNS (1), /* fmov, fmovr */
113 COSTS_N_INSNS (1), /* fmul */
114 COSTS_N_INSNS (8), /* fdivs */
115 COSTS_N_INSNS (12), /* fdivd */
116 COSTS_N_INSNS (17), /* fsqrts */
117 COSTS_N_INSNS (17), /* fsqrtd */
118 COSTS_N_INSNS (17), /* imul */
119 COSTS_N_INSNS (17), /* imulX */
120 0, /* imul bit factor */
121 COSTS_N_INSNS (17), /* idiv */
122 COSTS_N_INSNS (17), /* idivX */
123 COSTS_N_INSNS (1), /* movcc/movr */
124 0, /* shift penalty */
128 struct processor_costs sparclet_costs
= {
129 COSTS_N_INSNS (3), /* int load */
130 COSTS_N_INSNS (3), /* int signed load */
131 COSTS_N_INSNS (1), /* int zeroed load */
132 COSTS_N_INSNS (1), /* float load */
133 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
134 COSTS_N_INSNS (1), /* fadd, fsub */
135 COSTS_N_INSNS (1), /* fcmp */
136 COSTS_N_INSNS (1), /* fmov, fmovr */
137 COSTS_N_INSNS (1), /* fmul */
138 COSTS_N_INSNS (1), /* fdivs */
139 COSTS_N_INSNS (1), /* fdivd */
140 COSTS_N_INSNS (1), /* fsqrts */
141 COSTS_N_INSNS (1), /* fsqrtd */
142 COSTS_N_INSNS (5), /* imul */
143 COSTS_N_INSNS (5), /* imulX */
144 0, /* imul bit factor */
145 COSTS_N_INSNS (5), /* idiv */
146 COSTS_N_INSNS (5), /* idivX */
147 COSTS_N_INSNS (1), /* movcc/movr */
148 0, /* shift penalty */
152 struct processor_costs ultrasparc_costs
= {
153 COSTS_N_INSNS (2), /* int load */
154 COSTS_N_INSNS (3), /* int signed load */
155 COSTS_N_INSNS (2), /* int zeroed load */
156 COSTS_N_INSNS (2), /* float load */
157 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
158 COSTS_N_INSNS (4), /* fadd, fsub */
159 COSTS_N_INSNS (1), /* fcmp */
160 COSTS_N_INSNS (2), /* fmov, fmovr */
161 COSTS_N_INSNS (4), /* fmul */
162 COSTS_N_INSNS (13), /* fdivs */
163 COSTS_N_INSNS (23), /* fdivd */
164 COSTS_N_INSNS (13), /* fsqrts */
165 COSTS_N_INSNS (23), /* fsqrtd */
166 COSTS_N_INSNS (4), /* imul */
167 COSTS_N_INSNS (4), /* imulX */
168 2, /* imul bit factor */
169 COSTS_N_INSNS (37), /* idiv */
170 COSTS_N_INSNS (68), /* idivX */
171 COSTS_N_INSNS (2), /* movcc/movr */
172 2, /* shift penalty */
176 struct processor_costs ultrasparc3_costs
= {
177 COSTS_N_INSNS (2), /* int load */
178 COSTS_N_INSNS (3), /* int signed load */
179 COSTS_N_INSNS (3), /* int zeroed load */
180 COSTS_N_INSNS (2), /* float load */
181 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
182 COSTS_N_INSNS (4), /* fadd, fsub */
183 COSTS_N_INSNS (5), /* fcmp */
184 COSTS_N_INSNS (3), /* fmov, fmovr */
185 COSTS_N_INSNS (4), /* fmul */
186 COSTS_N_INSNS (17), /* fdivs */
187 COSTS_N_INSNS (20), /* fdivd */
188 COSTS_N_INSNS (20), /* fsqrts */
189 COSTS_N_INSNS (29), /* fsqrtd */
190 COSTS_N_INSNS (6), /* imul */
191 COSTS_N_INSNS (6), /* imulX */
192 0, /* imul bit factor */
193 COSTS_N_INSNS (40), /* idiv */
194 COSTS_N_INSNS (71), /* idivX */
195 COSTS_N_INSNS (2), /* movcc/movr */
196 0, /* shift penalty */
199 const struct processor_costs
*sparc_costs
= &cypress_costs
;
201 #ifdef HAVE_AS_RELAX_OPTION
202 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
203 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
204 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
205 somebody does not branch between the sethi and jmp. */
206 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
208 #define LEAF_SIBCALL_SLOT_RESERVED_P \
209 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
212 /* Global variables for machine-dependent things. */
214 /* Size of frame. Need to know this to emit return insns from leaf procedures.
215 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
216 reload pass. This is important as the value is later used for scheduling
217 (to see what can go in a delay slot).
218 APPARENT_FSIZE is the size of the stack less the register save area and less
219 the outgoing argument area. It is used when saving call preserved regs. */
220 static HOST_WIDE_INT apparent_fsize
;
221 static HOST_WIDE_INT actual_fsize
;
223 /* Number of live general or floating point registers needed to be
224 saved (as 4-byte quantities). */
225 static int num_gfregs
;
227 /* The alias set for prologue/epilogue register save/restore. */
228 static GTY(()) int sparc_sr_alias_set
;
230 /* Save the operands last given to a compare for use when we
231 generate a scc or bcc insn. */
232 rtx sparc_compare_op0
, sparc_compare_op1
;
234 /* Vector to say how input registers are mapped to output registers.
235 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
236 eliminate it. You must use -fomit-frame-pointer to get that. */
237 char leaf_reg_remap
[] =
238 { 0, 1, 2, 3, 4, 5, 6, 7,
239 -1, -1, -1, -1, -1, -1, 14, -1,
240 -1, -1, -1, -1, -1, -1, -1, -1,
241 8, 9, 10, 11, 12, 13, -1, 15,
243 32, 33, 34, 35, 36, 37, 38, 39,
244 40, 41, 42, 43, 44, 45, 46, 47,
245 48, 49, 50, 51, 52, 53, 54, 55,
246 56, 57, 58, 59, 60, 61, 62, 63,
247 64, 65, 66, 67, 68, 69, 70, 71,
248 72, 73, 74, 75, 76, 77, 78, 79,
249 80, 81, 82, 83, 84, 85, 86, 87,
250 88, 89, 90, 91, 92, 93, 94, 95,
251 96, 97, 98, 99, 100};
253 /* Vector, indexed by hard register number, which contains 1
254 for a register that is allowable in a candidate for leaf
255 function treatment. */
256 char sparc_leaf_regs
[] =
257 { 1, 1, 1, 1, 1, 1, 1, 1,
258 0, 0, 0, 0, 0, 0, 1, 0,
259 0, 0, 0, 0, 0, 0, 0, 0,
260 1, 1, 1, 1, 1, 1, 0, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1, 1, 1, 1,
268 1, 1, 1, 1, 1, 1, 1, 1,
271 struct machine_function
GTY(())
273 /* Some local-dynamic TLS symbol name. */
274 const char *some_ld_name
;
276 /* True if the current function is leaf and uses only leaf regs,
277 so that the SPARC leaf function optimization can be applied.
278 Private version of current_function_uses_only_leaf_regs, see
279 sparc_expand_prologue for the rationale. */
282 /* True if the data calculated by sparc_expand_prologue are valid. */
283 bool prologue_data_valid_p
;
286 #define sparc_leaf_function_p cfun->machine->leaf_function_p
287 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
289 /* Register we pretend to think the frame pointer is allocated to.
290 Normally, this is %fp, but if we are in a leaf procedure, this
291 is %sp+"something". We record "something" separately as it may
292 be too big for reg+constant addressing. */
293 static rtx frame_base_reg
;
294 static HOST_WIDE_INT frame_base_offset
;
296 /* 1 if the next opcode is to be specially indented. */
297 int sparc_indent_opcode
= 0;
299 static void sparc_init_modes (void);
300 static void scan_record_type (tree
, int *, int *, int *);
301 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
302 tree
, int, int, int *, int *);
304 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
305 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
307 static void sparc_output_addr_vec (rtx
);
308 static void sparc_output_addr_diff_vec (rtx
);
309 static void sparc_output_deferred_case_vectors (void);
310 static rtx
sparc_builtin_saveregs (void);
311 static int epilogue_renumber (rtx
*, int);
312 static bool sparc_assemble_integer (rtx
, unsigned int, int);
313 static int set_extends (rtx
);
314 static void load_pic_register (void);
315 static int save_or_restore_regs (int, int, rtx
, int, int);
316 static void emit_save_regs (void);
317 static void emit_restore_regs (void);
318 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
319 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
320 #ifdef OBJECT_FORMAT_ELF
321 static void sparc_elf_asm_named_section (const char *, unsigned int, tree
);
324 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
325 static int sparc_issue_rate (void);
326 static void sparc_sched_init (FILE *, int, int);
327 static int sparc_use_sched_lookahead (void);
329 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
330 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
331 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
332 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
333 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
335 static bool sparc_function_ok_for_sibcall (tree
, tree
);
336 static void sparc_init_libfuncs (void);
337 static void sparc_init_builtins (void);
338 static void sparc_vis_init_builtins (void);
339 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
340 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
341 HOST_WIDE_INT
, tree
);
342 static bool sparc_can_output_mi_thunk (tree
, HOST_WIDE_INT
,
343 HOST_WIDE_INT
, tree
);
344 static struct machine_function
* sparc_init_machine_status (void);
345 static bool sparc_cannot_force_const_mem (rtx
);
346 static rtx
sparc_tls_get_addr (void);
347 static rtx
sparc_tls_got (void);
348 static const char *get_some_local_dynamic_name (void);
349 static int get_some_local_dynamic_name_1 (rtx
*, void *);
350 static bool sparc_rtx_costs (rtx
, int, int, int *);
351 static bool sparc_promote_prototypes (tree
);
352 static rtx
sparc_struct_value_rtx (tree
, int);
353 static bool sparc_return_in_memory (tree
, tree
);
354 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS
*);
355 static tree
sparc_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
356 static bool sparc_vector_mode_supported_p (enum machine_mode
);
357 static bool sparc_pass_by_reference (CUMULATIVE_ARGS
*,
358 enum machine_mode
, tree
, bool);
359 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS
*,
360 enum machine_mode
, tree
, bool);
361 static void sparc_dwarf_handle_frame_unspec (const char *, rtx
, int);
362 #ifdef SUBTARGET_ATTRIBUTE_TABLE
363 const struct attribute_spec sparc_attribute_table
[];
366 /* Option handling. */
368 /* Code model option as passed by user. */
369 const char *sparc_cmodel_string
;
371 enum cmodel sparc_cmodel
;
373 char sparc_hard_reg_printed
[8];
375 struct sparc_cpu_select sparc_select
[] =
377 /* switch name, tune arch */
378 { (char *)0, "default", 1, 1 },
379 { (char *)0, "-mcpu=", 1, 1 },
380 { (char *)0, "-mtune=", 1, 0 },
384 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
385 enum processor_type sparc_cpu
;
387 /* Initialize the GCC target structure. */
389 /* The sparc default is to use .half rather than .short for aligned
390 HI objects. Use .word instead of .long on non-ELF systems. */
391 #undef TARGET_ASM_ALIGNED_HI_OP
392 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
393 #ifndef OBJECT_FORMAT_ELF
394 #undef TARGET_ASM_ALIGNED_SI_OP
395 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
398 #undef TARGET_ASM_UNALIGNED_HI_OP
399 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
400 #undef TARGET_ASM_UNALIGNED_SI_OP
401 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
402 #undef TARGET_ASM_UNALIGNED_DI_OP
403 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
405 /* The target hook has to handle DI-mode values. */
406 #undef TARGET_ASM_INTEGER
407 #define TARGET_ASM_INTEGER sparc_assemble_integer
409 #undef TARGET_ASM_FUNCTION_PROLOGUE
410 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
411 #undef TARGET_ASM_FUNCTION_EPILOGUE
412 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
414 #undef TARGET_SCHED_ADJUST_COST
415 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
416 #undef TARGET_SCHED_ISSUE_RATE
417 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
418 #undef TARGET_SCHED_INIT
419 #define TARGET_SCHED_INIT sparc_sched_init
420 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
421 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
423 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
424 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
426 #undef TARGET_INIT_LIBFUNCS
427 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
428 #undef TARGET_INIT_BUILTINS
429 #define TARGET_INIT_BUILTINS sparc_init_builtins
431 #undef TARGET_EXPAND_BUILTIN
432 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
435 #undef TARGET_HAVE_TLS
436 #define TARGET_HAVE_TLS true
438 #undef TARGET_CANNOT_FORCE_CONST_MEM
439 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
441 #undef TARGET_ASM_OUTPUT_MI_THUNK
442 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
443 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
444 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
446 #undef TARGET_RTX_COSTS
447 #define TARGET_RTX_COSTS sparc_rtx_costs
448 #undef TARGET_ADDRESS_COST
449 #define TARGET_ADDRESS_COST hook_int_rtx_0
451 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
452 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
453 test for this value. */
454 #undef TARGET_PROMOTE_FUNCTION_ARGS
455 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
457 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
458 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
459 test for this value. */
460 #undef TARGET_PROMOTE_FUNCTION_RETURN
461 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
463 #undef TARGET_PROMOTE_PROTOTYPES
464 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
466 #undef TARGET_STRUCT_VALUE_RTX
467 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
468 #undef TARGET_RETURN_IN_MEMORY
469 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
470 #undef TARGET_MUST_PASS_IN_STACK
471 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
472 #undef TARGET_PASS_BY_REFERENCE
473 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
474 #undef TARGET_ARG_PARTIAL_BYTES
475 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
477 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
478 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
479 #undef TARGET_STRICT_ARGUMENT_NAMING
480 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
482 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
483 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
485 #undef TARGET_VECTOR_MODE_SUPPORTED_P
486 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
488 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
489 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
491 #ifdef SUBTARGET_INSERT_ATTRIBUTES
492 #undef TARGET_INSERT_ATTRIBUTES
493 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
496 #ifdef SUBTARGET_ATTRIBUTE_TABLE
497 #undef TARGET_ATTRIBUTE_TABLE
498 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
501 #undef TARGET_RELAXED_ORDERING
502 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
504 struct gcc_target targetm
= TARGET_INITIALIZER
;
506 /* Validate and override various options, and do some machine dependent
510 sparc_override_options (void)
512 static struct code_model
{
513 const char *const name
;
515 } const cmodels
[] = {
517 { "medlow", CM_MEDLOW
},
518 { "medmid", CM_MEDMID
},
519 { "medany", CM_MEDANY
},
520 { "embmedany", CM_EMBMEDANY
},
523 const struct code_model
*cmodel
;
524 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
525 static struct cpu_default
{
527 const char *const name
;
528 } const cpu_default
[] = {
529 /* There must be one entry here for each TARGET_CPU value. */
530 { TARGET_CPU_sparc
, "cypress" },
531 { TARGET_CPU_sparclet
, "tsc701" },
532 { TARGET_CPU_sparclite
, "f930" },
533 { TARGET_CPU_v8
, "v8" },
534 { TARGET_CPU_hypersparc
, "hypersparc" },
535 { TARGET_CPU_sparclite86x
, "sparclite86x" },
536 { TARGET_CPU_supersparc
, "supersparc" },
537 { TARGET_CPU_v9
, "v9" },
538 { TARGET_CPU_ultrasparc
, "ultrasparc" },
539 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
542 const struct cpu_default
*def
;
543 /* Table of values for -m{cpu,tune}=. */
544 static struct cpu_table
{
545 const char *const name
;
546 const enum processor_type processor
;
549 } const cpu_table
[] = {
550 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
551 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
552 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
553 /* TI TMS390Z55 supersparc */
554 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
555 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
556 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
557 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
558 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
559 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
560 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
561 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
563 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
565 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
566 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
567 /* TI ultrasparc I, II, IIi */
568 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
569 /* Although insns using %y are deprecated, it is a clear win on current
571 |MASK_DEPRECATED_V8_INSNS
},
572 /* TI ultrasparc III */
573 /* ??? Check if %y issue still holds true in ultra3. */
574 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
577 const struct cpu_table
*cpu
;
578 const struct sparc_cpu_select
*sel
;
581 #ifndef SPARC_BI_ARCH
582 /* Check for unsupported architecture size. */
583 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
584 error ("%s is not supported by this configuration",
585 DEFAULT_ARCH32_P
? "-m64" : "-m32");
588 /* We force all 64bit archs to use 128 bit long double */
589 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
591 error ("-mlong-double-64 not allowed with -m64");
592 target_flags
|= MASK_LONG_DOUBLE_128
;
595 /* Code model selection. */
596 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
600 sparc_cmodel
= CM_32
;
603 if (sparc_cmodel_string
!= NULL
)
607 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
608 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
610 if (cmodel
->name
== NULL
)
611 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
613 sparc_cmodel
= cmodel
->value
;
616 error ("-mcmodel= is not supported on 32 bit systems");
619 fpu
= TARGET_FPU
; /* save current -mfpu status */
621 /* Set the default CPU. */
622 for (def
= &cpu_default
[0]; def
->name
; ++def
)
623 if (def
->cpu
== TARGET_CPU_DEFAULT
)
627 sparc_select
[0].string
= def
->name
;
629 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
633 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
634 if (! strcmp (sel
->string
, cpu
->name
))
637 sparc_cpu
= cpu
->processor
;
641 target_flags
&= ~cpu
->disable
;
642 target_flags
|= cpu
->enable
;
648 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
652 /* If -mfpu or -mno-fpu was explicitly used, don't override with
653 the processor default. Clear MASK_FPU_SET to avoid confusing
654 the reverse mapping from switch values to names. */
657 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
658 target_flags
&= ~MASK_FPU_SET
;
661 /* Don't allow -mvis if FPU is disabled. */
663 target_flags
&= ~MASK_VIS
;
665 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
667 -m64 also implies v9. */
668 if (TARGET_VIS
|| TARGET_ARCH64
)
670 target_flags
|= MASK_V9
;
671 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
674 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
675 if (TARGET_V9
&& TARGET_ARCH32
)
676 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
678 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
679 if (! TARGET_V9
|| TARGET_ARCH64
)
680 target_flags
&= ~MASK_V8PLUS
;
682 /* Don't use stack biasing in 32 bit mode. */
684 target_flags
&= ~MASK_STACK_BIAS
;
686 /* Supply a default value for align_functions. */
687 if (align_functions
== 0
688 && (sparc_cpu
== PROCESSOR_ULTRASPARC
689 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
690 align_functions
= 32;
692 /* Validate PCC_STRUCT_RETURN. */
693 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
694 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
696 /* Only use .uaxword when compiling for a 64-bit target. */
698 targetm
.asm_out
.unaligned_op
.di
= NULL
;
700 /* Do various machine dependent initializations. */
703 /* Acquire a unique set number for our register saves and restores. */
704 sparc_sr_alias_set
= new_alias_set ();
706 /* Set up function hooks. */
707 init_machine_status
= sparc_init_machine_status
;
712 case PROCESSOR_CYPRESS
:
713 sparc_costs
= &cypress_costs
;
716 case PROCESSOR_SPARCLITE
:
717 case PROCESSOR_SUPERSPARC
:
718 sparc_costs
= &supersparc_costs
;
722 case PROCESSOR_HYPERSPARC
:
723 case PROCESSOR_SPARCLITE86X
:
724 sparc_costs
= &hypersparc_costs
;
726 case PROCESSOR_SPARCLET
:
727 case PROCESSOR_TSC701
:
728 sparc_costs
= &sparclet_costs
;
731 case PROCESSOR_ULTRASPARC
:
732 sparc_costs
= &ultrasparc_costs
;
734 case PROCESSOR_ULTRASPARC3
:
735 sparc_costs
= &ultrasparc3_costs
;
740 #ifdef SUBTARGET_ATTRIBUTE_TABLE
741 /* Table of valid machine attributes. */
742 const struct attribute_spec sparc_attribute_table
[] =
744 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
745 SUBTARGET_ATTRIBUTE_TABLE
,
746 { NULL
, 0, 0, false, false, false, NULL
}
750 /* Miscellaneous utilities. */
752 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
753 or branch on register contents instructions. */
756 v9_regcmp_p (enum rtx_code code
)
758 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
759 || code
== LE
|| code
== GT
);
763 /* Operand constraints. */
765 /* Return nonzero only if OP is a register of mode MODE,
769 reg_or_0_operand (rtx op
, enum machine_mode mode
)
771 if (register_operand (op
, mode
))
773 if (op
== const0_rtx
)
775 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
776 && CONST_DOUBLE_HIGH (op
) == 0
777 && CONST_DOUBLE_LOW (op
) == 0)
779 if (fp_zero_operand (op
, mode
))
784 /* Return nonzero only if OP is const1_rtx. */
787 const1_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
789 return op
== const1_rtx
;
792 /* Nonzero if OP is a floating point value with value 0.0. */
795 fp_zero_operand (rtx op
, enum machine_mode mode
)
797 enum mode_class mclass
= GET_MODE_CLASS (GET_MODE (op
));
798 if (mclass
!= MODE_FLOAT
&& mclass
!= MODE_VECTOR_INT
)
800 return op
== CONST0_RTX (mode
);
803 /* Nonzero if OP is a register operand in floating point register. */
806 fp_register_operand (rtx op
, enum machine_mode mode
)
808 if (! register_operand (op
, mode
))
810 if (GET_CODE (op
) == SUBREG
)
811 op
= SUBREG_REG (op
);
812 return GET_CODE (op
) == REG
&& SPARC_FP_REG_P (REGNO (op
));
815 /* Nonzero if OP is a floating point constant which can
816 be loaded into an integer register using a single
817 sethi instruction. */
822 if (GET_CODE (op
) == CONST_DOUBLE
)
827 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
828 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
829 ! REAL_VALUE_MINUS_ZERO (r
))
831 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
832 if (SPARC_SETHI_P (i
))
839 /* Nonzero if OP is a floating point constant which can
840 be loaded into an integer register using a single
846 if (GET_CODE (op
) == CONST_DOUBLE
)
851 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
852 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
853 ! REAL_VALUE_MINUS_ZERO (r
))
855 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
856 if (SPARC_SIMM13_P (i
))
863 /* Nonzero if OP is a floating point constant which can
864 be loaded into an integer register using a high/losum
865 instruction sequence. */
868 fp_high_losum_p (rtx op
)
870 /* The constraints calling this should only be in
871 SFmode move insns, so any constant which cannot
872 be moved using a single insn will do. */
873 if (GET_CODE (op
) == CONST_DOUBLE
)
878 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
879 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
880 ! REAL_VALUE_MINUS_ZERO (r
))
882 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
883 if (! SPARC_SETHI_P (i
)
884 && ! SPARC_SIMM13_P (i
))
891 /* Nonzero if OP is an integer register. */
894 intreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
896 return (register_operand (op
, SImode
)
897 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
900 /* Nonzero if OP is a floating point condition code register. */
903 fcc_reg_operand (rtx op
, enum machine_mode mode
)
905 /* This can happen when recog is called from combine. Op may be a MEM.
906 Fail instead of calling abort in this case. */
907 if (GET_CODE (op
) != REG
)
910 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
913 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
916 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
917 if (reg_renumber
== 0)
918 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
919 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
921 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
925 /* Nonzero if OP is a floating point condition code fcc0 register. */
928 fcc0_reg_operand (rtx op
, enum machine_mode mode
)
930 /* This can happen when recog is called from combine. Op may be a MEM.
931 Fail instead of calling abort in this case. */
932 if (GET_CODE (op
) != REG
)
935 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
938 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
941 return REGNO (op
) == SPARC_FCC_REG
;
944 /* Nonzero if OP is an integer or floating point condition code register. */
947 icc_or_fcc_reg_operand (rtx op
, enum machine_mode mode
)
949 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
951 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
954 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
959 return fcc_reg_operand (op
, mode
);
962 /* Call insn on SPARC can take a PC-relative constant address, or any regular
966 call_operand (rtx op
, enum machine_mode mode
)
968 if (GET_CODE (op
) != MEM
)
971 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
975 call_operand_address (rtx op
, enum machine_mode mode
)
977 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
980 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
981 otherwise return 0. */
984 tls_symbolic_operand (rtx op
)
986 if (GET_CODE (op
) != SYMBOL_REF
)
988 return SYMBOL_REF_TLS_MODEL (op
);
992 tgd_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
994 return tls_symbolic_operand (op
) == TLS_MODEL_GLOBAL_DYNAMIC
;
998 tld_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1000 return tls_symbolic_operand (op
) == TLS_MODEL_LOCAL_DYNAMIC
;
1004 tie_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1006 return tls_symbolic_operand (op
) == TLS_MODEL_INITIAL_EXEC
;
1010 tle_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1012 return tls_symbolic_operand (op
) == TLS_MODEL_LOCAL_EXEC
;
1015 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1016 reference and a constant. */
1019 symbolic_operand (register rtx op
, enum machine_mode mode
)
1021 enum machine_mode omode
= GET_MODE (op
);
1023 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
1026 switch (GET_CODE (op
))
1029 return !SYMBOL_REF_TLS_MODEL (op
);
1036 return (((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1037 && !SYMBOL_REF_TLS_MODEL (XEXP (op
, 0)))
1038 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1039 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1046 /* Return truth value of statement that OP is a symbolic memory
1047 operand of mode MODE. */
1050 symbolic_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1052 if (GET_CODE (op
) == SUBREG
)
1053 op
= SUBREG_REG (op
);
1054 if (GET_CODE (op
) != MEM
)
1057 return ((GET_CODE (op
) == SYMBOL_REF
&& !SYMBOL_REF_TLS_MODEL (op
))
1058 || GET_CODE (op
) == CONST
|| GET_CODE (op
) == HIGH
1059 || GET_CODE (op
) == LABEL_REF
);
1062 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1065 label_ref_operand (rtx op
, enum machine_mode mode
)
1067 if (GET_CODE (op
) != LABEL_REF
)
1069 if (GET_MODE (op
) != mode
)
1074 /* Return 1 if the operand is an argument used in generating pic references
1075 in either the medium/low or medium/anywhere code models of sparc64. */
1078 sp64_medium_pic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1080 /* Check for (const (minus (symbol_ref:GOT)
1081 (const (minus (label) (pc))))). */
1082 if (GET_CODE (op
) != CONST
)
1085 if (GET_CODE (op
) != MINUS
)
1087 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
1089 /* ??? Ensure symbol is GOT. */
1090 if (GET_CODE (XEXP (op
, 1)) != CONST
)
1092 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
1097 /* Return 1 if the operand is a data segment reference. This includes
1098 the readonly data segment, or in other words anything but the text segment.
1099 This is needed in the medium/anywhere code model on v9. These values
1100 are accessed with EMBMEDANY_BASE_REG. */
1103 data_segment_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1105 switch (GET_CODE (op
))
1108 return ! SYMBOL_REF_FUNCTION_P (op
);
1110 /* Assume canonical format of symbol + constant.
1113 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
1119 /* Return 1 if the operand is a text segment reference.
1120 This is needed in the medium/anywhere code model on v9. */
1123 text_segment_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1125 switch (GET_CODE (op
))
1130 return SYMBOL_REF_FUNCTION_P (op
);
1132 /* Assume canonical format of symbol + constant.
1135 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
1141 /* Return 1 if the operand is either a register or a memory operand that is
1145 reg_or_nonsymb_mem_operand (register rtx op
, enum machine_mode mode
)
1147 if (register_operand (op
, mode
))
1150 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
1157 splittable_symbolic_memory_operand (rtx op
,
1158 enum machine_mode mode ATTRIBUTE_UNUSED
)
1160 if (GET_CODE (op
) != MEM
)
1162 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
1168 splittable_immediate_memory_operand (rtx op
,
1169 enum machine_mode mode ATTRIBUTE_UNUSED
)
1171 if (GET_CODE (op
) != MEM
)
1173 if (! immediate_operand (XEXP (op
, 0), Pmode
))
1178 /* Return truth value of whether OP is EQ or NE. */
1181 eq_or_neq (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1183 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
1186 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1187 or LTU for non-floating-point. We handle those specially. */
1190 normal_comp_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1194 if (!COMPARISON_P (op
))
1197 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
1198 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
1201 code
= GET_CODE (op
);
1202 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
1205 /* Return 1 if this is a comparison operator. This allows the use of
1206 MATCH_OPERATOR to recognize all the branch insns. */
1209 noov_compare_op (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1213 if (!COMPARISON_P (op
))
1216 code
= GET_CODE (op
);
1217 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
1218 || GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
1219 /* These are the only branches which work with CC_NOOVmode. */
1220 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
1224 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1225 MATCH_OPERATOR to recognize all the branch insns. */
1228 noov_compare64_op (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1235 if (!COMPARISON_P (op
))
1238 code
= GET_CODE (op
);
1239 if (GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
1240 /* These are the only branches which work with CCX_NOOVmode. */
1241 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
1242 return (GET_MODE (XEXP (op
, 0)) == CCXmode
);
1245 /* Nonzero if OP is a comparison operator suitable for use in v9
1246 conditional move or branch on register contents instructions. */
1249 v9_regcmp_op (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1253 if (!COMPARISON_P (op
))
1256 code
= GET_CODE (op
);
1257 return v9_regcmp_p (code
);
1260 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1263 extend_op (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1265 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
1268 /* Return nonzero if OP is an operator of mode MODE which can set
1269 the condition codes explicitly. We do not include PLUS and MINUS
1270 because these require CC_NOOVmode, which we handle explicitly. */
1273 cc_arithop (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1275 if (GET_CODE (op
) == AND
1276 || GET_CODE (op
) == IOR
1277 || GET_CODE (op
) == XOR
)
1283 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1284 complement its second operand and set the condition codes explicitly. */
1287 cc_arithopn (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1289 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1290 and (xor ... (not ...)) to (not (xor ...)). */
1291 return (GET_CODE (op
) == AND
1292 || GET_CODE (op
) == IOR
);
1295 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1296 signed 13 bit immediate field. This is an acceptable SImode operand for
1297 most 3 address instructions. */
1300 arith_operand (rtx op
, enum machine_mode mode
)
1302 if (register_operand (op
, mode
))
1304 if (GET_CODE (op
) != CONST_INT
)
1306 return SMALL_INT32 (op
);
1309 /* Return true if OP is a constant 4096 */
1312 arith_4096_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1314 if (GET_CODE (op
) != CONST_INT
)
1317 return INTVAL (op
) == 4096;
1320 /* Return true if OP is suitable as second operand for add/sub */
1323 arith_add_operand (rtx op
, enum machine_mode mode
)
1325 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
1328 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1329 immediate field of OR and XOR instructions. Used for 64-bit
1330 constant formation patterns. */
1332 const64_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1334 return ((GET_CODE (op
) == CONST_INT
1335 && SPARC_SIMM13_P (INTVAL (op
)))
1336 #if HOST_BITS_PER_WIDE_INT != 64
1337 || (GET_CODE (op
) == CONST_DOUBLE
1338 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1339 && (CONST_DOUBLE_HIGH (op
) ==
1340 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
1341 (HOST_WIDE_INT
)-1 : 0)))
1346 /* The same, but only for sethi instructions. */
1348 const64_high_operand (rtx op
, enum machine_mode mode
)
1350 return ((GET_CODE (op
) == CONST_INT
1351 && (INTVAL (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1352 && SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1354 || (GET_CODE (op
) == CONST_DOUBLE
1355 && CONST_DOUBLE_HIGH (op
) == 0
1356 && (CONST_DOUBLE_LOW (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1357 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
1360 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1361 signed 11 bit immediate field. This is an acceptable SImode operand for
1362 the movcc instructions. */
1365 arith11_operand (rtx op
, enum machine_mode mode
)
1367 return (register_operand (op
, mode
)
1368 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
1371 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1372 signed 10 bit immediate field. This is an acceptable SImode operand for
1373 the movrcc instructions. */
1376 arith10_operand (rtx op
, enum machine_mode mode
)
1378 return (register_operand (op
, mode
)
1379 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
1382 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1383 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1385 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1386 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1387 for most 3 address instructions. */
1390 arith_double_operand (rtx op
, enum machine_mode mode
)
1392 return (register_operand (op
, mode
)
1393 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1395 && GET_CODE (op
) == CONST_DOUBLE
1396 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1397 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1399 && GET_CODE (op
) == CONST_DOUBLE
1400 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1401 && ((CONST_DOUBLE_HIGH (op
) == -1
1402 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1403 || (CONST_DOUBLE_HIGH (op
) == 0
1404 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1407 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1410 arith_double_4096_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1412 return (TARGET_ARCH64
&&
1413 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1414 (GET_CODE (op
) == CONST_DOUBLE
&&
1415 CONST_DOUBLE_LOW (op
) == 4096 &&
1416 CONST_DOUBLE_HIGH (op
) == 0)));
1419 /* Return true if OP is suitable as second operand for add/sub in DImode */
1422 arith_double_add_operand (rtx op
, enum machine_mode mode
)
1424 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1427 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1428 can fit in an 11 bit immediate field. This is an acceptable DImode
1429 operand for the movcc instructions. */
1430 /* ??? Replace with arith11_operand? */
1433 arith11_double_operand (rtx op
, enum machine_mode mode
)
1435 return (register_operand (op
, mode
)
1436 || (GET_CODE (op
) == CONST_DOUBLE
1437 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1438 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1439 && ((CONST_DOUBLE_HIGH (op
) == -1
1440 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1441 || (CONST_DOUBLE_HIGH (op
) == 0
1442 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1443 || (GET_CODE (op
) == CONST_INT
1444 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1445 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1448 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1449 can fit in an 10 bit immediate field. This is an acceptable DImode
1450 operand for the movrcc instructions. */
1451 /* ??? Replace with arith10_operand? */
1454 arith10_double_operand (rtx op
, enum machine_mode mode
)
1456 return (register_operand (op
, mode
)
1457 || (GET_CODE (op
) == CONST_DOUBLE
1458 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1459 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1460 && ((CONST_DOUBLE_HIGH (op
) == -1
1461 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1462 || (CONST_DOUBLE_HIGH (op
) == 0
1463 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1464 || (GET_CODE (op
) == CONST_INT
1465 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1466 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1469 /* Return truth value of whether OP is an integer which fits the
1470 range constraining immediate operands in most three-address insns,
1471 which have a 13 bit immediate field. */
1474 small_int (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1476 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1480 small_int_or_double (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1482 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1483 || (GET_CODE (op
) == CONST_DOUBLE
1484 && CONST_DOUBLE_HIGH (op
) == 0
1485 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1488 /* Recognize operand values for the umul instruction. That instruction sign
1489 extends immediate values just like all other sparc instructions, but
1490 interprets the extended result as an unsigned number. */
1493 uns_small_int (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1495 #if HOST_BITS_PER_WIDE_INT > 32
1496 /* All allowed constants will fit a CONST_INT. */
1497 return (GET_CODE (op
) == CONST_INT
1498 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1499 || (INTVAL (op
) >= 0xFFFFF000
1500 && INTVAL (op
) <= 0xFFFFFFFF)));
1502 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1503 || (GET_CODE (op
) == CONST_DOUBLE
1504 && CONST_DOUBLE_HIGH (op
) == 0
1505 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1510 uns_arith_operand (rtx op
, enum machine_mode mode
)
1512 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1515 /* Return truth value of statement that OP is a call-clobbered register. */
1517 clobbered_register (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1519 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1522 /* Return 1 if OP is a valid operand for the source of a move insn. */
1525 input_operand (rtx op
, enum machine_mode mode
)
1527 enum mode_class mclass
;
1529 /* If both modes are non-void they must be the same. */
1530 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1533 /* Allow any one instruction integer constant, and all CONST_INT
1534 variants when we are working in DImode and !arch64. */
1535 if (GET_MODE_CLASS (mode
) == MODE_INT
1536 && ((GET_CODE (op
) == CONST_INT
1537 && (SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1538 || SPARC_SIMM13_P (INTVAL (op
))
1540 && ! TARGET_ARCH64
)))
1542 && GET_CODE (op
) == CONST_DOUBLE
1543 && ((CONST_DOUBLE_HIGH (op
) == 0
1544 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1546 #if HOST_BITS_PER_WIDE_INT == 64
1547 (CONST_DOUBLE_HIGH (op
) == 0
1548 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1550 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1551 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1552 && CONST_DOUBLE_HIGH (op
) == 0)
1553 || (CONST_DOUBLE_HIGH (op
) == -1
1554 && CONST_DOUBLE_LOW (op
) & 0x80000000) != 0))
1559 /* If !arch64 and this is a DImode const, allow it so that
1560 the splits can be generated. */
1563 && GET_CODE (op
) == CONST_DOUBLE
)
1566 if (register_operand (op
, mode
))
1569 mclass
= GET_MODE_CLASS (mode
);
1570 if ((mclass
== MODE_FLOAT
&& GET_CODE (op
) == CONST_DOUBLE
)
1571 || (mclass
== MODE_VECTOR_INT
&& GET_CODE (op
) == CONST_VECTOR
))
1574 /* If this is a SUBREG, look inside so that we handle
1575 paradoxical ones. */
1576 if (GET_CODE (op
) == SUBREG
)
1577 op
= SUBREG_REG (op
);
1579 /* Check for valid MEM forms. */
1580 if (GET_CODE (op
) == MEM
)
1581 return memory_address_p (mode
, XEXP (op
, 0));
1586 /* Return 1 if OP is valid for the lhs of a compare insn. */
1589 compare_operand (rtx op
, enum machine_mode mode
)
1591 if (GET_CODE (op
) == ZERO_EXTRACT
)
1592 return (register_operand (XEXP (op
, 0), mode
)
1593 && small_int_or_double (XEXP (op
, 1), mode
)
1594 && small_int_or_double (XEXP (op
, 2), mode
)
1595 /* This matches cmp_zero_extract. */
1597 && ((GET_CODE (XEXP (op
, 2)) == CONST_INT
1598 && INTVAL (XEXP (op
, 2)) > 19)
1599 || (GET_CODE (XEXP (op
, 2)) == CONST_DOUBLE
1600 && CONST_DOUBLE_LOW (XEXP (op
, 2)) > 19)))
1601 /* This matches cmp_zero_extract_sp64. */
1604 && ((GET_CODE (XEXP (op
, 2)) == CONST_INT
1605 && INTVAL (XEXP (op
, 2)) > 51)
1606 || (GET_CODE (XEXP (op
, 2)) == CONST_DOUBLE
1607 && CONST_DOUBLE_LOW (XEXP (op
, 2)) > 51)))));
1609 return register_operand (op
, mode
);
1613 /* We know it can't be done in one insn when we get here,
1614 the movsi expander guarantees this. */
1616 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1618 enum machine_mode mode
= GET_MODE (op0
);
1621 if (GET_CODE (op1
) == CONST_INT
)
1623 HOST_WIDE_INT value
= INTVAL (op1
);
1625 if (SPARC_SETHI_P (value
& GET_MODE_MASK (mode
))
1626 || SPARC_SIMM13_P (value
))
1630 /* Full 2-insn decomposition is needed. */
1631 if (reload_in_progress
|| reload_completed
)
1634 temp
= gen_reg_rtx (mode
);
1636 if (GET_CODE (op1
) == CONST_INT
)
1638 /* Emit them as real moves instead of a HIGH/LO_SUM,
1639 this way CSE can see everything and reuse intermediate
1640 values if it wants. */
1642 && HOST_BITS_PER_WIDE_INT
!= 64
1643 && (INTVAL (op1
) & 0x80000000) != 0)
1644 emit_insn (gen_rtx_SET
1646 immed_double_const (INTVAL (op1
) & ~(HOST_WIDE_INT
)0x3ff,
1649 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1650 GEN_INT (INTVAL (op1
)
1651 & ~(HOST_WIDE_INT
)0x3ff)));
1653 emit_insn (gen_rtx_SET (VOIDmode
,
1655 gen_rtx_IOR (mode
, temp
,
1656 GEN_INT (INTVAL (op1
) & 0x3ff))));
1660 /* A symbol, emit in the traditional way. */
1661 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1662 gen_rtx_HIGH (mode
, op1
)));
1663 emit_insn (gen_rtx_SET (VOIDmode
,
1664 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1670 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1671 If TEMP is nonzero, we are forbidden to use any other scratch
1672 registers. Otherwise, we are allowed to generate them as needed.
1674 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1675 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1677 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1679 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1682 if (temp
&& GET_MODE (temp
) == TImode
)
1685 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1688 /* SPARC-V9 code-model support. */
1689 switch (sparc_cmodel
)
1692 /* The range spanned by all instructions in the object is less
1693 than 2^31 bytes (2GB) and the distance from any instruction
1694 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1695 than 2^31 bytes (2GB).
1697 The executable must be in the low 4TB of the virtual address
1700 sethi %hi(symbol), %temp1
1701 or %temp1, %lo(symbol), %reg */
1703 temp1
= temp
; /* op0 is allowed. */
1705 temp1
= gen_reg_rtx (DImode
);
1707 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1708 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1712 /* The range spanned by all instructions in the object is less
1713 than 2^31 bytes (2GB) and the distance from any instruction
1714 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1715 than 2^31 bytes (2GB).
1717 The executable must be in the low 16TB of the virtual address
1720 sethi %h44(symbol), %temp1
1721 or %temp1, %m44(symbol), %temp2
1722 sllx %temp2, 12, %temp3
1723 or %temp3, %l44(symbol), %reg */
1728 temp3
= temp
; /* op0 is allowed. */
1732 temp1
= gen_reg_rtx (DImode
);
1733 temp2
= gen_reg_rtx (DImode
);
1734 temp3
= gen_reg_rtx (DImode
);
1737 emit_insn (gen_seth44 (temp1
, op1
));
1738 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1739 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1740 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1741 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1745 /* The range spanned by all instructions in the object is less
1746 than 2^31 bytes (2GB) and the distance from any instruction
1747 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1748 than 2^31 bytes (2GB).
1750 The executable can be placed anywhere in the virtual address
1753 sethi %hh(symbol), %temp1
1754 sethi %lm(symbol), %temp2
1755 or %temp1, %hm(symbol), %temp3
1756 sllx %temp3, 32, %temp4
1757 or %temp4, %temp2, %temp5
1758 or %temp5, %lo(symbol), %reg */
1761 /* It is possible that one of the registers we got for operands[2]
1762 might coincide with that of operands[0] (which is why we made
1763 it TImode). Pick the other one to use as our scratch. */
1764 if (rtx_equal_p (temp
, op0
))
1767 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1772 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1779 temp1
= gen_reg_rtx (DImode
);
1780 temp2
= gen_reg_rtx (DImode
);
1781 temp3
= gen_reg_rtx (DImode
);
1782 temp4
= gen_reg_rtx (DImode
);
1783 temp5
= gen_reg_rtx (DImode
);
1786 emit_insn (gen_sethh (temp1
, op1
));
1787 emit_insn (gen_setlm (temp2
, op1
));
1788 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1789 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1790 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1791 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1792 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1793 emit_insn (gen_setlo (op0
, temp5
, op1
));
1797 /* Old old old backwards compatibility kruft here.
1798 Essentially it is MEDLOW with a fixed 64-bit
1799 virtual base added to all data segment addresses.
1800 Text-segment stuff is computed like MEDANY, we can't
1801 reuse the code above because the relocation knobs
1804 Data segment: sethi %hi(symbol), %temp1
1805 add %temp1, EMBMEDANY_BASE_REG, %temp2
1806 or %temp2, %lo(symbol), %reg */
1807 if (data_segment_operand (op1
, GET_MODE (op1
)))
1811 temp1
= temp
; /* op0 is allowed. */
1816 temp1
= gen_reg_rtx (DImode
);
1817 temp2
= gen_reg_rtx (DImode
);
1820 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1821 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1822 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1825 /* Text segment: sethi %uhi(symbol), %temp1
1826 sethi %hi(symbol), %temp2
1827 or %temp1, %ulo(symbol), %temp3
1828 sllx %temp3, 32, %temp4
1829 or %temp4, %temp2, %temp5
1830 or %temp5, %lo(symbol), %reg */
1835 /* It is possible that one of the registers we got for operands[2]
1836 might coincide with that of operands[0] (which is why we made
1837 it TImode). Pick the other one to use as our scratch. */
1838 if (rtx_equal_p (temp
, op0
))
1841 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1846 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1853 temp1
= gen_reg_rtx (DImode
);
1854 temp2
= gen_reg_rtx (DImode
);
1855 temp3
= gen_reg_rtx (DImode
);
1856 temp4
= gen_reg_rtx (DImode
);
1857 temp5
= gen_reg_rtx (DImode
);
1860 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1861 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1862 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1863 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1864 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1865 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1866 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1867 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1876 /* These avoid problems when cross compiling. If we do not
1877 go through all this hair then the optimizer will see
1878 invalid REG_EQUAL notes or in some cases none at all. */
1879 static void sparc_emit_set_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1880 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1881 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1882 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1884 #if HOST_BITS_PER_WIDE_INT == 64
1885 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1886 #define GEN_INT64(__x) GEN_INT (__x)
1888 #define GEN_HIGHINT64(__x) \
1889 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1890 #define GEN_INT64(__x) \
1891 immed_double_const ((__x) & 0xffffffff, \
1892 ((__x) & 0x80000000 ? -1 : 0), DImode)
1895 /* The optimizer is not to assume anything about exactly
1896 which bits are set for a HIGH, they are unspecified.
1897 Unfortunately this leads to many missed optimizations
1898 during CSE. We mask out the non-HIGH bits, and matches
1899 a plain movdi, to alleviate this problem. */
1901 sparc_emit_set_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1903 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1907 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1909 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1913 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1915 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1919 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1921 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1924 /* Worker routines for 64-bit constant formation on arch64.
1925 One of the key things to be doing in these emissions is
1926 to create as many temp REGs as possible. This makes it
1927 possible for half-built constants to be used later when
1928 such values are similar to something required later on.
1929 Without doing this, the optimizer cannot see such
1932 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1933 unsigned HOST_WIDE_INT
, int);
1936 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1937 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1939 unsigned HOST_WIDE_INT high_bits
;
1942 high_bits
= (~low_bits
) & 0xffffffff;
1944 high_bits
= low_bits
;
1946 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1949 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1950 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1954 /* If we are XOR'ing with -1, then we should emit a one's complement
1955 instead. This way the combiner will notice logical operations
1956 such as ANDN later on and substitute. */
1957 if ((low_bits
& 0x3ff) == 0x3ff)
1959 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1960 gen_rtx_NOT (DImode
, temp
)));
1964 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1965 gen_safe_XOR64 (temp
,
1966 (-(HOST_WIDE_INT
)0x400
1967 | (low_bits
& 0x3ff)))));
1972 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1973 unsigned HOST_WIDE_INT
, int);
1976 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1977 unsigned HOST_WIDE_INT high_bits
,
1978 unsigned HOST_WIDE_INT low_immediate
,
1983 if ((high_bits
& 0xfffffc00) != 0)
1985 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1986 if ((high_bits
& ~0xfffffc00) != 0)
1987 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1988 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1994 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1998 /* Now shift it up into place. */
1999 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2000 gen_rtx_ASHIFT (DImode
, temp2
,
2001 GEN_INT (shift_count
))));
2003 /* If there is a low immediate part piece, finish up by
2004 putting that in as well. */
2005 if (low_immediate
!= 0)
2006 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2007 gen_safe_OR64 (op0
, low_immediate
)));
2010 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2011 unsigned HOST_WIDE_INT
);
2013 /* Full 64-bit constant decomposition. Even though this is the
2014 'worst' case, we still optimize a few things away. */
2016 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2017 unsigned HOST_WIDE_INT high_bits
,
2018 unsigned HOST_WIDE_INT low_bits
)
2022 if (reload_in_progress
|| reload_completed
)
2025 sub_temp
= gen_reg_rtx (DImode
);
2027 if ((high_bits
& 0xfffffc00) != 0)
2029 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
2030 if ((high_bits
& ~0xfffffc00) != 0)
2031 emit_insn (gen_rtx_SET (VOIDmode
,
2033 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2039 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2043 if (!reload_in_progress
&& !reload_completed
)
2045 rtx temp2
= gen_reg_rtx (DImode
);
2046 rtx temp3
= gen_reg_rtx (DImode
);
2047 rtx temp4
= gen_reg_rtx (DImode
);
2049 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2050 gen_rtx_ASHIFT (DImode
, sub_temp
,
2053 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
2054 if ((low_bits
& ~0xfffffc00) != 0)
2056 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
2057 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2058 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2059 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2063 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2064 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2069 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2070 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2071 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2074 /* We are in the middle of reload, so this is really
2075 painful. However we do still make an attempt to
2076 avoid emitting truly stupid code. */
2077 if (low1
!= const0_rtx
)
2079 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2080 gen_rtx_ASHIFT (DImode
, sub_temp
,
2081 GEN_INT (to_shift
))));
2082 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2083 gen_rtx_IOR (DImode
, op0
, low1
)));
2091 if (low2
!= const0_rtx
)
2093 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2094 gen_rtx_ASHIFT (DImode
, sub_temp
,
2095 GEN_INT (to_shift
))));
2096 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2097 gen_rtx_IOR (DImode
, op0
, low2
)));
2105 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2106 gen_rtx_ASHIFT (DImode
, sub_temp
,
2107 GEN_INT (to_shift
))));
2108 if (low3
!= const0_rtx
)
2109 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2110 gen_rtx_IOR (DImode
, op0
, low3
)));
2115 /* Analyze a 64-bit constant for certain properties. */
2116 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2117 unsigned HOST_WIDE_INT
,
2118 int *, int *, int *);
2121 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2122 unsigned HOST_WIDE_INT low_bits
,
2123 int *hbsp
, int *lbsp
, int *abbasp
)
2125 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2128 lowest_bit_set
= highest_bit_set
= -1;
2132 if ((lowest_bit_set
== -1)
2133 && ((low_bits
>> i
) & 1))
2135 if ((highest_bit_set
== -1)
2136 && ((high_bits
>> (32 - i
- 1)) & 1))
2137 highest_bit_set
= (64 - i
- 1);
2140 && ((highest_bit_set
== -1)
2141 || (lowest_bit_set
== -1)));
2147 if ((lowest_bit_set
== -1)
2148 && ((high_bits
>> i
) & 1))
2149 lowest_bit_set
= i
+ 32;
2150 if ((highest_bit_set
== -1)
2151 && ((low_bits
>> (32 - i
- 1)) & 1))
2152 highest_bit_set
= 32 - i
- 1;
2155 && ((highest_bit_set
== -1)
2156 || (lowest_bit_set
== -1)));
2158 /* If there are no bits set this should have gone out
2159 as one instruction! */
2160 if (lowest_bit_set
== -1
2161 || highest_bit_set
== -1)
2163 all_bits_between_are_set
= 1;
2164 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2168 if ((low_bits
& (1 << i
)) != 0)
2173 if ((high_bits
& (1 << (i
- 32))) != 0)
2176 all_bits_between_are_set
= 0;
2179 *hbsp
= highest_bit_set
;
2180 *lbsp
= lowest_bit_set
;
2181 *abbasp
= all_bits_between_are_set
;
2184 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2187 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2188 unsigned HOST_WIDE_INT low_bits
)
2190 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2193 || high_bits
== 0xffffffff)
2196 analyze_64bit_constant (high_bits
, low_bits
,
2197 &highest_bit_set
, &lowest_bit_set
,
2198 &all_bits_between_are_set
);
2200 if ((highest_bit_set
== 63
2201 || lowest_bit_set
== 0)
2202 && all_bits_between_are_set
!= 0)
2205 if ((highest_bit_set
- lowest_bit_set
) < 21)
2211 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2212 unsigned HOST_WIDE_INT
,
2215 static unsigned HOST_WIDE_INT
2216 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2217 unsigned HOST_WIDE_INT low_bits
,
2218 int lowest_bit_set
, int shift
)
2220 HOST_WIDE_INT hi
, lo
;
2222 if (lowest_bit_set
< 32)
2224 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2225 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2230 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2237 /* Here we are sure to be arch64 and this is an integer constant
2238 being loaded into a register. Emit the most efficient
2239 insn sequence possible. Detection of all the 1-insn cases
2240 has been done already. */
2242 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2244 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2245 int lowest_bit_set
, highest_bit_set
;
2246 int all_bits_between_are_set
;
2249 /* Sanity check that we know what we are working with. */
2250 if (! TARGET_ARCH64
)
2253 if (GET_CODE (op0
) != SUBREG
)
2255 if (GET_CODE (op0
) != REG
2256 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
2257 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
2261 if (reload_in_progress
|| reload_completed
)
2264 if (GET_CODE (op1
) != CONST_DOUBLE
2265 && GET_CODE (op1
) != CONST_INT
)
2267 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2272 temp
= gen_reg_rtx (DImode
);
2274 if (GET_CODE (op1
) == CONST_DOUBLE
)
2276 #if HOST_BITS_PER_WIDE_INT == 64
2277 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
2278 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
2280 high_bits
= CONST_DOUBLE_HIGH (op1
);
2281 low_bits
= CONST_DOUBLE_LOW (op1
);
2286 #if HOST_BITS_PER_WIDE_INT == 64
2287 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2288 low_bits
= (INTVAL (op1
) & 0xffffffff);
2290 high_bits
= ((INTVAL (op1
) < 0) ?
2293 low_bits
= INTVAL (op1
);
2297 /* low_bits bits 0 --> 31
2298 high_bits bits 32 --> 63 */
2300 analyze_64bit_constant (high_bits
, low_bits
,
2301 &highest_bit_set
, &lowest_bit_set
,
2302 &all_bits_between_are_set
);
2304 /* First try for a 2-insn sequence. */
2306 /* These situations are preferred because the optimizer can
2307 * do more things with them:
2309 * sllx %reg, shift, %reg
2311 * srlx %reg, shift, %reg
2312 * 3) mov some_small_const, %reg
2313 * sllx %reg, shift, %reg
2315 if (((highest_bit_set
== 63
2316 || lowest_bit_set
== 0)
2317 && all_bits_between_are_set
!= 0)
2318 || ((highest_bit_set
- lowest_bit_set
) < 12))
2320 HOST_WIDE_INT the_const
= -1;
2321 int shift
= lowest_bit_set
;
2323 if ((highest_bit_set
!= 63
2324 && lowest_bit_set
!= 0)
2325 || all_bits_between_are_set
== 0)
2328 create_simple_focus_bits (high_bits
, low_bits
,
2331 else if (lowest_bit_set
== 0)
2332 shift
= -(63 - highest_bit_set
);
2334 if (! SPARC_SIMM13_P (the_const
))
2337 emit_insn (gen_safe_SET64 (temp
, the_const
));
2339 emit_insn (gen_rtx_SET (VOIDmode
,
2341 gen_rtx_ASHIFT (DImode
,
2345 emit_insn (gen_rtx_SET (VOIDmode
,
2347 gen_rtx_LSHIFTRT (DImode
,
2349 GEN_INT (-shift
))));
2355 /* Now a range of 22 or less bits set somewhere.
2356 * 1) sethi %hi(focus_bits), %reg
2357 * sllx %reg, shift, %reg
2358 * 2) sethi %hi(focus_bits), %reg
2359 * srlx %reg, shift, %reg
2361 if ((highest_bit_set
- lowest_bit_set
) < 21)
2363 unsigned HOST_WIDE_INT focus_bits
=
2364 create_simple_focus_bits (high_bits
, low_bits
,
2365 lowest_bit_set
, 10);
2367 if (! SPARC_SETHI_P (focus_bits
))
2370 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
2372 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2373 if (lowest_bit_set
< 10)
2374 emit_insn (gen_rtx_SET (VOIDmode
,
2376 gen_rtx_LSHIFTRT (DImode
, temp
,
2377 GEN_INT (10 - lowest_bit_set
))));
2378 else if (lowest_bit_set
> 10)
2379 emit_insn (gen_rtx_SET (VOIDmode
,
2381 gen_rtx_ASHIFT (DImode
, temp
,
2382 GEN_INT (lowest_bit_set
- 10))));
2388 /* 1) sethi %hi(low_bits), %reg
2389 * or %reg, %lo(low_bits), %reg
2390 * 2) sethi %hi(~low_bits), %reg
2391 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2394 || high_bits
== 0xffffffff)
2396 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2397 (high_bits
== 0xffffffff));
2401 /* Now, try 3-insn sequences. */
2403 /* 1) sethi %hi(high_bits), %reg
2404 * or %reg, %lo(high_bits), %reg
2405 * sllx %reg, 32, %reg
2409 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2413 /* We may be able to do something quick
2414 when the constant is negated, so try that. */
2415 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2416 (~low_bits
) & 0xfffffc00))
2418 /* NOTE: The trailing bits get XOR'd so we need the
2419 non-negated bits, not the negated ones. */
2420 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2422 if ((((~high_bits
) & 0xffffffff) == 0
2423 && ((~low_bits
) & 0x80000000) == 0)
2424 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2425 && ((~low_bits
) & 0x80000000) != 0))
2427 int fast_int
= (~low_bits
& 0xffffffff);
2429 if ((SPARC_SETHI_P (fast_int
)
2430 && (~high_bits
& 0xffffffff) == 0)
2431 || SPARC_SIMM13_P (fast_int
))
2432 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2434 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2439 #if HOST_BITS_PER_WIDE_INT == 64
2440 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2441 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2443 negated_const
= immed_double_const ((~low_bits
) & 0xfffffc00,
2444 (~high_bits
) & 0xffffffff,
2447 sparc_emit_set_const64 (temp
, negated_const
);
2450 /* If we are XOR'ing with -1, then we should emit a one's complement
2451 instead. This way the combiner will notice logical operations
2452 such as ANDN later on and substitute. */
2453 if (trailing_bits
== 0x3ff)
2455 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2456 gen_rtx_NOT (DImode
, temp
)));
2460 emit_insn (gen_rtx_SET (VOIDmode
,
2462 gen_safe_XOR64 (temp
,
2463 (-0x400 | trailing_bits
))));
2468 /* 1) sethi %hi(xxx), %reg
2469 * or %reg, %lo(xxx), %reg
2470 * sllx %reg, yyy, %reg
2472 * ??? This is just a generalized version of the low_bits==0
2473 * thing above, FIXME...
2475 if ((highest_bit_set
- lowest_bit_set
) < 32)
2477 unsigned HOST_WIDE_INT focus_bits
=
2478 create_simple_focus_bits (high_bits
, low_bits
,
2481 /* We can't get here in this state. */
2482 if (highest_bit_set
< 32
2483 || lowest_bit_set
>= 32)
2486 /* So what we know is that the set bits straddle the
2487 middle of the 64-bit word. */
2488 sparc_emit_set_const64_quick2 (op0
, temp
,
2494 /* 1) sethi %hi(high_bits), %reg
2495 * or %reg, %lo(high_bits), %reg
2496 * sllx %reg, 32, %reg
2497 * or %reg, low_bits, %reg
2499 if (SPARC_SIMM13_P(low_bits
)
2500 && ((int)low_bits
> 0))
2502 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2506 /* The easiest way when all else fails, is full decomposition. */
2508 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2509 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2511 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2514 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2515 return the mode to be used for the comparison. For floating-point,
2516 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2517 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2518 processing is needed. */
2521 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2523 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2549 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2550 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2552 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2553 return CCX_NOOVmode
;
2559 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2566 /* X and Y are two things to compare using CODE. Emit the compare insn and
2567 return the rtx for the cc reg in the proper mode. */
2570 gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
2572 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2575 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2576 fcc regs (cse can't tell they're really call clobbered regs and will
2577 remove a duplicate comparison even if there is an intervening function
2578 call - it will then try to reload the cc reg via an int reg which is why
2579 we need the movcc patterns). It is possible to provide the movcc
2580 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2581 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2582 to tell cse that CCFPE mode registers (even pseudos) are call
2585 /* ??? This is an experiment. Rather than making changes to cse which may
2586 or may not be easy/clean, we do our own cse. This is possible because
2587 we will generate hard registers. Cse knows they're call clobbered (it
2588 doesn't know the same thing about pseudos). If we guess wrong, no big
2589 deal, but if we win, great! */
2591 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2592 #if 1 /* experiment */
2595 /* We cycle through the registers to ensure they're all exercised. */
2596 static int next_fcc_reg
= 0;
2597 /* Previous x,y for each fcc reg. */
2598 static rtx prev_args
[4][2];
2600 /* Scan prev_args for x,y. */
2601 for (reg
= 0; reg
< 4; reg
++)
2602 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2607 prev_args
[reg
][0] = x
;
2608 prev_args
[reg
][1] = y
;
2609 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2611 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2614 cc_reg
= gen_reg_rtx (mode
);
2615 #endif /* ! experiment */
2616 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2617 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2619 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2621 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2622 gen_rtx_COMPARE (mode
, x
, y
)));
2627 /* This function is used for v9 only.
2628 CODE is the code for an Scc's comparison.
2629 OPERANDS[0] is the target of the Scc insn.
2630 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2631 been generated yet).
2633 This function is needed to turn
2636 (gt (reg:CCX 100 %icc)
2640 (gt:DI (reg:CCX 100 %icc)
2643 IE: The instruction recognizer needs to see the mode of the comparison to
2644 find the right instruction. We could use "gt:DI" right in the
2645 define_expand, but leaving it out allows us to handle DI, SI, etc.
2647 We refer to the global sparc compare operands sparc_compare_op0 and
2648 sparc_compare_op1. */
2651 gen_v9_scc (enum rtx_code compare_code
, register rtx
*operands
)
2656 && (GET_MODE (sparc_compare_op0
) == DImode
2657 || GET_MODE (operands
[0]) == DImode
))
2660 op0
= sparc_compare_op0
;
2661 op1
= sparc_compare_op1
;
2663 /* Try to use the movrCC insns. */
2665 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2666 && op1
== const0_rtx
2667 && v9_regcmp_p (compare_code
))
2669 /* Special case for op0 != 0. This can be done with one instruction if
2670 operands[0] == sparc_compare_op0. */
2672 if (compare_code
== NE
2673 && GET_MODE (operands
[0]) == DImode
2674 && rtx_equal_p (op0
, operands
[0]))
2676 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2677 gen_rtx_IF_THEN_ELSE (DImode
,
2678 gen_rtx_fmt_ee (compare_code
, DImode
,
2685 if (reg_overlap_mentioned_p (operands
[0], op0
))
2687 /* Handle the case where operands[0] == sparc_compare_op0.
2688 We "early clobber" the result. */
2689 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2690 emit_move_insn (op0
, sparc_compare_op0
);
2693 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2694 if (GET_MODE (op0
) != DImode
)
2696 temp
= gen_reg_rtx (DImode
);
2697 convert_move (temp
, op0
, 0);
2701 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2702 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2703 gen_rtx_fmt_ee (compare_code
, DImode
,
2711 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2713 switch (GET_MODE (operands
[1]))
2723 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2724 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2725 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2726 gen_rtx_fmt_ee (compare_code
,
2727 GET_MODE (operands
[1]),
2728 operands
[1], const0_rtx
),
2729 const1_rtx
, operands
[0])));
2734 /* Emit a conditional jump insn for the v9 architecture using comparison code
2735 CODE and jump target LABEL.
2736 This function exists to take advantage of the v9 brxx insns. */
2739 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2741 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2743 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2744 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2746 gen_rtx_LABEL_REF (VOIDmode
, label
),
2750 /* Generate a DFmode part of a hard TFmode register.
2751 REG is the TFmode hard register, LOW is 1 for the
2752 low 64bit of the register and 0 otherwise.
2755 gen_df_reg (rtx reg
, int low
)
2757 int regno
= REGNO (reg
);
2759 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2760 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2761 return gen_rtx_REG (DFmode
, regno
);
2764 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2765 Unlike normal calls, TFmode operands are passed by reference. It is
2766 assumed that no more than 3 operands are required. */
2769 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2771 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2774 /* We only expect to be called for conversions, unary, and binary ops. */
2775 if (nargs
< 2 || nargs
> 3)
2778 for (i
= 0; i
< nargs
; ++i
)
2780 rtx this_arg
= operands
[i
];
2783 /* TFmode arguments and return values are passed by reference. */
2784 if (GET_MODE (this_arg
) == TFmode
)
2786 int force_stack_temp
;
2788 force_stack_temp
= 0;
2789 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2790 force_stack_temp
= 1;
2792 if (GET_CODE (this_arg
) == MEM
2793 && ! force_stack_temp
)
2794 this_arg
= XEXP (this_arg
, 0);
2795 else if (CONSTANT_P (this_arg
)
2796 && ! force_stack_temp
)
2798 this_slot
= force_const_mem (TFmode
, this_arg
);
2799 this_arg
= XEXP (this_slot
, 0);
2803 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2805 /* Operand 0 is the return value. We'll copy it out later. */
2807 emit_move_insn (this_slot
, this_arg
);
2809 ret_slot
= this_slot
;
2811 this_arg
= XEXP (this_slot
, 0);
2818 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2820 if (GET_MODE (operands
[0]) == TFmode
)
2823 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2824 arg
[0], GET_MODE (arg
[0]),
2825 arg
[1], GET_MODE (arg
[1]));
2827 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2828 arg
[0], GET_MODE (arg
[0]),
2829 arg
[1], GET_MODE (arg
[1]),
2830 arg
[2], GET_MODE (arg
[2]));
2833 emit_move_insn (operands
[0], ret_slot
);
2842 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2843 GET_MODE (operands
[0]), 1,
2844 arg
[1], GET_MODE (arg
[1]));
2846 if (ret
!= operands
[0])
2847 emit_move_insn (operands
[0], ret
);
2851 /* Expand soft-float TFmode calls to sparc abi routines. */
2854 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2876 emit_soft_tfmode_libcall (func
, 3, operands
);
2880 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2893 emit_soft_tfmode_libcall (func
, 2, operands
);
2897 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2904 switch (GET_MODE (operands
[1]))
2917 case FLOAT_TRUNCATE
:
2918 switch (GET_MODE (operands
[0]))
2932 switch (GET_MODE (operands
[1]))
2945 case UNSIGNED_FLOAT
:
2946 switch (GET_MODE (operands
[1]))
2960 switch (GET_MODE (operands
[0]))
2974 switch (GET_MODE (operands
[0]))
2991 emit_soft_tfmode_libcall (func
, 2, operands
);
2994 /* Expand a hard-float tfmode operation. All arguments must be in
2998 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3002 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3004 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3005 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3009 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3010 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3011 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3012 operands
[1], operands
[2]);
3015 if (register_operand (operands
[0], VOIDmode
))
3018 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3020 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
3022 if (dest
!= operands
[0])
3023 emit_move_insn (operands
[0], dest
);
3027 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3029 if (TARGET_HARD_QUAD
)
3030 emit_hard_tfmode_operation (code
, operands
);
3032 emit_soft_tfmode_binop (code
, operands
);
3036 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3038 if (TARGET_HARD_QUAD
)
3039 emit_hard_tfmode_operation (code
, operands
);
3041 emit_soft_tfmode_unop (code
, operands
);
3045 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3047 if (TARGET_HARD_QUAD
)
3048 emit_hard_tfmode_operation (code
, operands
);
3050 emit_soft_tfmode_cvt (code
, operands
);
3053 /* Return nonzero if a branch/jump/call instruction will be emitting
3054 nop into its delay slot. */
3057 empty_delay_slot (rtx insn
)
3061 /* If no previous instruction (should not happen), return true. */
3062 if (PREV_INSN (insn
) == NULL
)
3065 seq
= NEXT_INSN (PREV_INSN (insn
));
3066 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3072 /* Return nonzero if TRIAL can go into the call delay slot. */
3075 tls_call_delay (rtx trial
)
3080 call __tls_get_addr, %tgd_call (foo)
3081 add %l7, %o0, %o0, %tgd_add (foo)
3082 while Sun as/ld does not. */
3083 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3086 pat
= PATTERN (trial
);
3087 if (GET_CODE (pat
) != SET
|| GET_CODE (SET_DEST (pat
)) != PLUS
)
3090 unspec
= XEXP (SET_DEST (pat
), 1);
3091 if (GET_CODE (unspec
) != UNSPEC
3092 || (XINT (unspec
, 1) != UNSPEC_TLSGD
3093 && XINT (unspec
, 1) != UNSPEC_TLSLDM
))
3099 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3100 instruction. RETURN_P is true if the v9 variant 'return' is to be
3101 considered in the test too.
3103 TRIAL must be a SET whose destination is a REG appropriate for the
3104 'restore' instruction or, if RETURN_P is true, for the 'return'
3108 eligible_for_restore_insn (rtx trial
, bool return_p
)
3110 rtx pat
= PATTERN (trial
);
3111 rtx src
= SET_SRC (pat
);
3113 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3114 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3115 && arith_operand (src
, GET_MODE (src
)))
3118 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3120 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3123 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3124 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3125 && arith_double_operand (src
, GET_MODE (src
)))
3126 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3128 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3129 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3132 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3133 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3136 /* If we have the 'return' instruction, anything that does not use
3137 local or output registers and can go into a delay slot wins. */
3138 else if (return_p
&& TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
3139 && (get_attr_in_uncond_branch_delay (trial
)
3140 == IN_UNCOND_BRANCH_DELAY_TRUE
))
3143 /* The 'restore src1,src2,dest' pattern for SImode. */
3144 else if (GET_CODE (src
) == PLUS
3145 && register_operand (XEXP (src
, 0), SImode
)
3146 && arith_operand (XEXP (src
, 1), SImode
))
3149 /* The 'restore src1,src2,dest' pattern for DImode. */
3150 else if (GET_CODE (src
) == PLUS
3151 && register_operand (XEXP (src
, 0), DImode
)
3152 && arith_double_operand (XEXP (src
, 1), DImode
))
3155 /* The 'restore src1,%lo(src2),dest' pattern. */
3156 else if (GET_CODE (src
) == LO_SUM
3157 && ! TARGET_CM_MEDMID
3158 && ((register_operand (XEXP (src
, 0), SImode
)
3159 && immediate_operand (XEXP (src
, 1), SImode
))
3161 && register_operand (XEXP (src
, 0), DImode
)
3162 && immediate_operand (XEXP (src
, 1), DImode
))))
3165 /* The 'restore src,src,dest' pattern. */
3166 else if (GET_CODE (src
) == ASHIFT
3167 && (register_operand (XEXP (src
, 0), SImode
)
3168 || register_operand (XEXP (src
, 0), DImode
))
3169 && XEXP (src
, 1) == const1_rtx
)
3175 /* Return nonzero if TRIAL can go into the function return's
3179 eligible_for_return_delay (rtx trial
)
3183 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
3186 if (get_attr_length (trial
) != 1)
3189 /* If there are any call-saved registers, we should scan TRIAL if it
3190 does not reference them. For now just make it easy. */
3194 /* If the function uses __builtin_eh_return, the eh_return machinery
3195 occupies the delay slot. */
3196 if (current_function_calls_eh_return
)
3199 /* In the case of a true leaf function, anything can go into the slot. */
3200 if (sparc_leaf_function_p
)
3201 return get_attr_in_uncond_branch_delay (trial
)
3202 == IN_UNCOND_BRANCH_DELAY_TRUE
;
3204 pat
= PATTERN (trial
);
3206 /* Otherwise, only operations which can be done in tandem with
3207 a `restore' or `return' insn can go into the delay slot. */
3208 if (GET_CODE (SET_DEST (pat
)) != REG
3209 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
3212 /* If this instruction sets up floating point register and we have a return
3213 instruction, it can probably go in. But restore will not work
3215 if (REGNO (SET_DEST (pat
)) >= 32)
3217 && ! epilogue_renumber (&pat
, 1)
3218 && (get_attr_in_uncond_branch_delay (trial
)
3219 == IN_UNCOND_BRANCH_DELAY_TRUE
));
3221 return eligible_for_restore_insn (trial
, true);
3224 /* Return nonzero if TRIAL can go into the sibling call's
3228 eligible_for_sibcall_delay (rtx trial
)
3232 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
3235 if (get_attr_length (trial
) != 1)
3238 pat
= PATTERN (trial
);
3240 if (sparc_leaf_function_p
)
3242 /* If the tail call is done using the call instruction,
3243 we have to restore %o7 in the delay slot. */
3244 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3247 /* %g1 is used to build the function address */
3248 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3254 /* Otherwise, only operations which can be done in tandem with
3255 a `restore' insn can go into the delay slot. */
3256 if (GET_CODE (SET_DEST (pat
)) != REG
3257 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3258 || REGNO (SET_DEST (pat
)) >= 32)
3261 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3263 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3266 return eligible_for_restore_insn (trial
, false);
3270 short_branch (int uid1
, int uid2
)
3272 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3274 /* Leave a few words of "slop". */
3275 if (delta
>= -1023 && delta
<= 1022)
3281 /* Return nonzero if REG is not used after INSN.
3282 We assume REG is a reload reg, and therefore does
3283 not live past labels or calls or jumps. */
3285 reg_unused_after (rtx reg
, rtx insn
)
3287 enum rtx_code code
, prev_code
= UNKNOWN
;
3289 while ((insn
= NEXT_INSN (insn
)))
3291 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3294 code
= GET_CODE (insn
);
3295 if (GET_CODE (insn
) == CODE_LABEL
)
3300 rtx set
= single_set (insn
);
3301 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3304 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3306 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3314 /* Determine if it's legal to put X into the constant pool. This
3315 is not possible if X contains the address of a symbol that is
3316 not constant (TLS) or not known at final link time (PIC). */
3319 sparc_cannot_force_const_mem (rtx x
)
3321 switch (GET_CODE (x
))
3326 /* Accept all non-symbolic constants. */
3330 /* Labels are OK iff we are non-PIC. */
3331 return flag_pic
!= 0;
3334 /* 'Naked' TLS symbol references are never OK,
3335 non-TLS symbols are OK iff we are non-PIC. */
3336 if (SYMBOL_REF_TLS_MODEL (x
))
3339 return flag_pic
!= 0;
3342 return sparc_cannot_force_const_mem (XEXP (x
, 0));
3345 return sparc_cannot_force_const_mem (XEXP (x
, 0))
3346 || sparc_cannot_force_const_mem (XEXP (x
, 1));
3354 /* The table we use to reference PIC data. */
3355 static GTY(()) rtx global_offset_table
;
3357 /* The function we use to get at it. */
3358 static GTY(()) rtx add_pc_to_pic_symbol
;
3359 static GTY(()) char add_pc_to_pic_symbol_name
[256];
3361 /* Ensure that we are not using patterns that are not OK with PIC. */
3369 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
3370 || (GET_CODE (recog_data
.operand
[i
]) == CONST
3371 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
3372 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
3373 == global_offset_table
)
3374 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
3383 /* Return true if X is an address which needs a temporary register when
3384 reloaded while generating PIC code. */
3387 pic_address_needs_scratch (rtx x
)
3389 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3390 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3391 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3392 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3393 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3399 /* Determine if a given RTX is a valid constant. We already know this
3400 satisfies CONSTANT_P. */
3403 legitimate_constant_p (rtx x
)
3407 switch (GET_CODE (x
))
3410 /* TLS symbols are not constant. */
3411 if (SYMBOL_REF_TLS_MODEL (x
))
3416 inner
= XEXP (x
, 0);
3418 /* Offsets of TLS symbols are never valid.
3419 Discourage CSE from creating them. */
3420 if (GET_CODE (inner
) == PLUS
3421 && tls_symbolic_operand (XEXP (inner
, 0)))
3426 if (GET_MODE (x
) == VOIDmode
)
3429 /* Floating point constants are generally not ok.
3430 The only exception is 0.0 in VIS. */
3432 && (GET_MODE (x
) == SFmode
3433 || GET_MODE (x
) == DFmode
3434 || GET_MODE (x
) == TFmode
)
3435 && fp_zero_operand (x
, GET_MODE (x
)))
3447 /* Determine if a given RTX is a valid constant address. */
3450 constant_address_p (rtx x
)
3452 switch (GET_CODE (x
))
3460 if (flag_pic
&& pic_address_needs_scratch (x
))
3462 return legitimate_constant_p (x
);
3465 return !flag_pic
&& legitimate_constant_p (x
);
3472 /* Nonzero if the constant value X is a legitimate general operand
3473 when generating PIC code. It is given that flag_pic is on and
3474 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3477 legitimate_pic_operand_p (rtx x
)
3479 if (pic_address_needs_scratch (x
))
3481 if (tls_symbolic_operand (x
)
3482 || (GET_CODE (x
) == CONST
3483 && GET_CODE (XEXP (x
, 0)) == PLUS
3484 && tls_symbolic_operand (XEXP (XEXP (x
, 0), 0))))
3489 /* Return nonzero if ADDR is a valid memory address.
3490 STRICT specifies whether strict register checking applies. */
3493 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
3495 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
, imm2
;
3497 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3499 else if (GET_CODE (addr
) == PLUS
)
3501 rs1
= XEXP (addr
, 0);
3502 rs2
= XEXP (addr
, 1);
3504 /* Canonicalize. REG comes first, if there are no regs,
3505 LO_SUM comes first. */
3507 && GET_CODE (rs1
) != SUBREG
3509 || GET_CODE (rs2
) == SUBREG
3510 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3512 rs1
= XEXP (addr
, 1);
3513 rs2
= XEXP (addr
, 0);
3517 && rs1
== pic_offset_table_rtx
3519 && GET_CODE (rs2
) != SUBREG
3520 && GET_CODE (rs2
) != LO_SUM
3521 && GET_CODE (rs2
) != MEM
3522 && !tls_symbolic_operand (rs2
)
3523 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3524 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3526 || GET_CODE (rs1
) == SUBREG
)
3527 && RTX_OK_FOR_OFFSET_P (rs2
)))
3532 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3533 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3535 /* We prohibit REG + REG for TFmode when there are no quad move insns
3536 and we consequently need to split. We do this because REG+REG
3537 is not an offsettable address. If we get the situation in reload
3538 where source and destination of a movtf pattern are both MEMs with
3539 REG+REG address, then only one of them gets converted to an
3540 offsettable address. */
3542 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3545 /* We prohibit REG + REG on ARCH32 if not optimizing for
3546 DFmode/DImode because then mem_min_alignment is likely to be zero
3547 after reload and the forced split would lack a matching splitter
3549 if (TARGET_ARCH32
&& !optimize
3550 && (mode
== DFmode
|| mode
== DImode
))
3553 else if (USE_AS_OFFSETABLE_LO10
3554 && GET_CODE (rs1
) == LO_SUM
3556 && ! TARGET_CM_MEDMID
3557 && RTX_OK_FOR_OLO10_P (rs2
))
3561 imm1
= XEXP (rs1
, 1);
3562 rs1
= XEXP (rs1
, 0);
3563 if (! CONSTANT_P (imm1
) || tls_symbolic_operand (rs1
))
3567 else if (GET_CODE (addr
) == LO_SUM
)
3569 rs1
= XEXP (addr
, 0);
3570 imm1
= XEXP (addr
, 1);
3572 if (! CONSTANT_P (imm1
) || tls_symbolic_operand (rs1
))
3575 if (USE_AS_OFFSETABLE_LO10
)
3577 /* We can't allow TFmode, because an offset greater than or equal to
3578 the alignment (8) may cause the LO_SUM to overflow if !v9. */
3579 if (mode
== TFmode
&& ! TARGET_V9
)
3584 /* We prohibit LO_SUM for TFmode when there are no quad move insns
3585 and we consequently need to split. We do this because LO_SUM
3586 is not an offsettable address. If we get the situation in reload
3587 where source and destination of a movtf pattern are both MEMs with
3588 LO_SUM address, then only one of them gets converted to an
3589 offsettable address. */
3591 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3595 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3600 if (GET_CODE (rs1
) == SUBREG
)
3601 rs1
= SUBREG_REG (rs1
);
3607 if (GET_CODE (rs2
) == SUBREG
)
3608 rs2
= SUBREG_REG (rs2
);
3615 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3616 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3621 if ((REGNO (rs1
) >= 32
3622 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3623 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3625 && (REGNO (rs2
) >= 32
3626 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3627 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3633 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3635 static GTY(()) rtx sparc_tls_symbol
;
3637 sparc_tls_get_addr (void)
3639 if (!sparc_tls_symbol
)
3640 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3642 return sparc_tls_symbol
;
3646 sparc_tls_got (void)
3651 current_function_uses_pic_offset_table
= 1;
3652 return pic_offset_table_rtx
;
3655 if (!global_offset_table
)
3656 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3657 temp
= gen_reg_rtx (Pmode
);
3658 emit_move_insn (temp
, global_offset_table
);
3663 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3664 this (thread-local) address. */
3667 legitimize_tls_address (rtx addr
)
3669 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3674 if (GET_CODE (addr
) == SYMBOL_REF
)
3675 switch (SYMBOL_REF_TLS_MODEL (addr
))
3677 case TLS_MODEL_GLOBAL_DYNAMIC
:
3679 temp1
= gen_reg_rtx (SImode
);
3680 temp2
= gen_reg_rtx (SImode
);
3681 ret
= gen_reg_rtx (Pmode
);
3682 o0
= gen_rtx_REG (Pmode
, 8);
3683 got
= sparc_tls_got ();
3684 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3685 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3688 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3689 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3694 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3695 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3698 CALL_INSN_FUNCTION_USAGE (insn
)
3699 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3700 CALL_INSN_FUNCTION_USAGE (insn
));
3701 insn
= get_insns ();
3703 emit_libcall_block (insn
, ret
, o0
, addr
);
3706 case TLS_MODEL_LOCAL_DYNAMIC
:
3708 temp1
= gen_reg_rtx (SImode
);
3709 temp2
= gen_reg_rtx (SImode
);
3710 temp3
= gen_reg_rtx (Pmode
);
3711 ret
= gen_reg_rtx (Pmode
);
3712 o0
= gen_rtx_REG (Pmode
, 8);
3713 got
= sparc_tls_got ();
3714 emit_insn (gen_tldm_hi22 (temp1
));
3715 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3718 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3719 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3724 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3725 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3728 CALL_INSN_FUNCTION_USAGE (insn
)
3729 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3730 CALL_INSN_FUNCTION_USAGE (insn
));
3731 insn
= get_insns ();
3733 emit_libcall_block (insn
, temp3
, o0
,
3734 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3735 UNSPEC_TLSLD_BASE
));
3736 temp1
= gen_reg_rtx (SImode
);
3737 temp2
= gen_reg_rtx (SImode
);
3738 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3739 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3741 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3743 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3746 case TLS_MODEL_INITIAL_EXEC
:
3747 temp1
= gen_reg_rtx (SImode
);
3748 temp2
= gen_reg_rtx (SImode
);
3749 temp3
= gen_reg_rtx (Pmode
);
3750 got
= sparc_tls_got ();
3751 emit_insn (gen_tie_hi22 (temp1
, addr
));
3752 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3754 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3756 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3759 ret
= gen_reg_rtx (Pmode
);
3761 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3764 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3768 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3771 case TLS_MODEL_LOCAL_EXEC
:
3772 temp1
= gen_reg_rtx (Pmode
);
3773 temp2
= gen_reg_rtx (Pmode
);
3776 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3777 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3781 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3782 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3784 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3792 abort (); /* for now ... */
3798 /* Legitimize PIC addresses. If the address is already position-independent,
3799 we return ORIG. Newly generated position-independent addresses go into a
3800 reg. This is REG if nonzero, otherwise we allocate register(s) as
3804 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3807 if (GET_CODE (orig
) == SYMBOL_REF
)
3809 rtx pic_ref
, address
;
3814 if (reload_in_progress
|| reload_completed
)
3817 reg
= gen_reg_rtx (Pmode
);
3822 /* If not during reload, allocate another temp reg here for loading
3823 in the address, so that these instructions can be optimized
3825 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3826 ? reg
: gen_reg_rtx (Pmode
));
3828 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3829 won't get confused into thinking that these two instructions
3830 are loading in the true address of the symbol. If in the
3831 future a PIC rtx exists, that should be used instead. */
3832 if (Pmode
== SImode
)
3834 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3835 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3839 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3840 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3847 pic_ref
= gen_const_mem (Pmode
,
3848 gen_rtx_PLUS (Pmode
,
3849 pic_offset_table_rtx
, address
));
3850 current_function_uses_pic_offset_table
= 1;
3851 insn
= emit_move_insn (reg
, pic_ref
);
3852 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3854 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3858 else if (GET_CODE (orig
) == CONST
)
3862 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3863 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3868 if (reload_in_progress
|| reload_completed
)
3871 reg
= gen_reg_rtx (Pmode
);
3874 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3876 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3877 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3878 base
== reg
? 0 : reg
);
3883 if (GET_CODE (offset
) == CONST_INT
)
3885 if (SMALL_INT (offset
))
3886 return plus_constant (base
, INTVAL (offset
));
3887 else if (! reload_in_progress
&& ! reload_completed
)
3888 offset
= force_reg (Pmode
, offset
);
3890 /* If we reach here, then something is seriously wrong. */
3893 return gen_rtx_PLUS (Pmode
, base
, offset
);
3895 else if (GET_CODE (orig
) == LABEL_REF
)
3896 /* ??? Why do we do this? */
3897 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3898 the register is live instead, in case it is eliminated. */
3899 current_function_uses_pic_offset_table
= 1;
3904 /* Try machine-dependent ways of modifying an illegitimate address X
3905 to be legitimate. If we find one, return the new, valid address.
3907 OLDX is the address as it was before break_out_memory_refs was called.
3908 In some cases it is useful to look at this to decide what needs to be done.
3910 MODE is the mode of the operand pointed to by X. */
3913 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
, enum machine_mode mode
)
3917 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3918 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3919 force_operand (XEXP (x
, 0), NULL_RTX
));
3920 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3921 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3922 force_operand (XEXP (x
, 1), NULL_RTX
));
3923 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3924 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3926 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3927 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3928 force_operand (XEXP (x
, 1), NULL_RTX
));
3930 if (x
!= orig_x
&& legitimate_address_p (mode
, x
, FALSE
))
3933 if (tls_symbolic_operand (x
))
3934 x
= legitimize_tls_address (x
);
3936 x
= legitimize_pic_address (x
, mode
, 0);
3937 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3938 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3939 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3940 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3941 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3942 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3943 else if (GET_CODE (x
) == SYMBOL_REF
3944 || GET_CODE (x
) == CONST
3945 || GET_CODE (x
) == LABEL_REF
)
3946 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3950 /* Emit the special PIC prologue. */
3953 load_pic_register (void)
3955 int orig_flag_pic
= flag_pic
;
3957 /* If we haven't emitted the special helper function, do so now. */
3958 if (add_pc_to_pic_symbol_name
[0] == 0)
3960 const char *pic_name
= reg_names
[REGNO (pic_offset_table_rtx
)];
3963 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name
, "LADDPC", 0);
3966 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3968 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3969 ASM_OUTPUT_LABEL (asm_out_file
, add_pc_to_pic_symbol_name
);
3970 if (flag_delayed_branch
)
3971 fprintf (asm_out_file
, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3972 pic_name
, pic_name
);
3974 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3975 pic_name
, pic_name
);
3978 /* Initialize every time through, since we can't easily
3979 know this to be permanent. */
3980 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3981 add_pc_to_pic_symbol
= gen_rtx_SYMBOL_REF (Pmode
, add_pc_to_pic_symbol_name
);
3985 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx
, global_offset_table
,
3986 add_pc_to_pic_symbol
));
3988 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx
, global_offset_table
,
3989 add_pc_to_pic_symbol
));
3990 flag_pic
= orig_flag_pic
;
3992 /* Need to emit this whether or not we obey regdecls,
3993 since setjmp/longjmp can cause life info to screw up.
3994 ??? In the case where we don't obey regdecls, this is not sufficient
3995 since we may not fall out the bottom. */
3996 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3999 /* Return 1 if RTX is a MEM which is known to be aligned to at
4000 least a DESIRED byte boundary. */
4003 mem_min_alignment (rtx mem
, int desired
)
4005 rtx addr
, base
, offset
;
4007 /* If it's not a MEM we can't accept it. */
4008 if (GET_CODE (mem
) != MEM
)
4012 if (MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4015 /* ??? The rest of the function predates MEM_ALIGN so
4016 there is probably a bit of redundancy. */
4017 addr
= XEXP (mem
, 0);
4018 base
= offset
= NULL_RTX
;
4019 if (GET_CODE (addr
) == PLUS
)
4021 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4023 base
= XEXP (addr
, 0);
4025 /* What we are saying here is that if the base
4026 REG is aligned properly, the compiler will make
4027 sure any REG based index upon it will be so
4029 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4030 offset
= XEXP (addr
, 1);
4032 offset
= const0_rtx
;
4035 else if (GET_CODE (addr
) == REG
)
4038 offset
= const0_rtx
;
4041 if (base
!= NULL_RTX
)
4043 int regno
= REGNO (base
);
4045 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4047 /* Check if the compiler has recorded some information
4048 about the alignment of the base REG. If reload has
4049 completed, we already matched with proper alignments.
4050 If not running global_alloc, reload might give us
4051 unaligned pointer to local stack though. */
4053 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4054 || (optimize
&& reload_completed
))
4055 && (INTVAL (offset
) & (desired
- 1)) == 0)
4060 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4064 else if (! TARGET_UNALIGNED_DOUBLES
4065 || CONSTANT_P (addr
)
4066 || GET_CODE (addr
) == LO_SUM
)
4068 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4069 is true, in which case we can only assume that an access is aligned if
4070 it is to a constant address, or the address involves a LO_SUM. */
4074 /* An obviously unaligned address. */
4079 /* Vectors to keep interesting information about registers where it can easily
4080 be got. We used to use the actual mode value as the bit number, but there
4081 are more than 32 modes now. Instead we use two tables: one indexed by
4082 hard register number, and one indexed by mode. */
4084 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4085 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4086 mapped into one sparc_mode_class mode. */
4088 enum sparc_mode_class
{
4089 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4090 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4094 /* Modes for single-word and smaller quantities. */
4095 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4097 /* Modes for double-word and smaller quantities. */
4098 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4100 /* Modes for quad-word and smaller quantities. */
4101 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4103 /* Modes for 8-word and smaller quantities. */
4104 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4106 /* Modes for single-float quantities. We must allow any single word or
4107 smaller quantity. This is because the fix/float conversion instructions
4108 take integer inputs/outputs from the float registers. */
4109 #define SF_MODES (S_MODES)
4111 /* Modes for double-float and smaller quantities. */
4112 #define DF_MODES (S_MODES | D_MODES)
4114 /* Modes for double-float only quantities. */
4115 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4117 /* Modes for quad-float only quantities. */
4118 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4120 /* Modes for quad-float and smaller quantities. */
4121 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4123 /* Modes for quad-float and double-float quantities. */
4124 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4126 /* Modes for quad-float pair only quantities. */
4127 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4129 /* Modes for quad-float pairs and smaller quantities. */
4130 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4132 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4134 /* Modes for condition codes. */
4135 #define CC_MODES (1 << (int) CC_MODE)
4136 #define CCFP_MODES (1 << (int) CCFP_MODE)
4138 /* Value is 1 if register/mode pair is acceptable on sparc.
4139 The funny mixture of D and T modes is because integer operations
4140 do not specially operate on tetra quantities, so non-quad-aligned
4141 registers can hold quadword quantities (except %o4 and %i4 because
4142 they cross fixed registers). */
4144 /* This points to either the 32 bit or the 64 bit version. */
4145 const int *hard_regno_mode_classes
;
4147 static const int hard_32bit_mode_classes
[] = {
4148 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4149 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4150 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4151 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4153 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4154 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4155 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4156 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4158 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4159 and none can hold SFmode/SImode values. */
4160 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4161 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4162 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4163 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4166 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4172 static const int hard_64bit_mode_classes
[] = {
4173 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4174 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4175 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4176 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4178 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4179 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4180 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4181 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4183 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4184 and none can hold SFmode/SImode values. */
4185 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4186 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4187 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4188 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4191 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4197 int sparc_mode_class
[NUM_MACHINE_MODES
];
4199 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4202 sparc_init_modes (void)
4206 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4208 switch (GET_MODE_CLASS (i
))
4211 case MODE_PARTIAL_INT
:
4212 case MODE_COMPLEX_INT
:
4213 if (GET_MODE_SIZE (i
) <= 4)
4214 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4215 else if (GET_MODE_SIZE (i
) == 8)
4216 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4217 else if (GET_MODE_SIZE (i
) == 16)
4218 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4219 else if (GET_MODE_SIZE (i
) == 32)
4220 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4222 sparc_mode_class
[i
] = 0;
4224 case MODE_VECTOR_INT
:
4225 if (GET_MODE_SIZE (i
) <= 4)
4226 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4227 else if (GET_MODE_SIZE (i
) == 8)
4228 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4231 case MODE_COMPLEX_FLOAT
:
4232 if (GET_MODE_SIZE (i
) <= 4)
4233 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4234 else if (GET_MODE_SIZE (i
) == 8)
4235 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4236 else if (GET_MODE_SIZE (i
) == 16)
4237 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4238 else if (GET_MODE_SIZE (i
) == 32)
4239 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4241 sparc_mode_class
[i
] = 0;
4244 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4245 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4247 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4250 sparc_mode_class
[i
] = 0;
4256 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4258 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4260 /* Initialize the array used by REGNO_REG_CLASS. */
4261 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4263 if (i
< 16 && TARGET_V8PLUS
)
4264 sparc_regno_reg_class
[i
] = I64_REGS
;
4265 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4266 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4268 sparc_regno_reg_class
[i
] = FP_REGS
;
4270 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4272 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4274 sparc_regno_reg_class
[i
] = NO_REGS
;
4278 /* Compute the frame size required by the function. This function is called
4279 during the reload pass and also by sparc_expand_prologue. */
4282 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function_p
)
4284 int outgoing_args_size
= (current_function_outgoing_args_size
4285 + REG_PARM_STACK_SPACE (current_function_decl
));
4286 int n_regs
= 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4291 for (i
= 0; i
< 8; i
++)
4292 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4297 for (i
= 0; i
< 8; i
+= 2)
4298 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
4299 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
4303 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4304 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
4305 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
4308 /* Set up values for use in prologue and epilogue. */
4309 num_gfregs
= n_regs
;
4314 && current_function_outgoing_args_size
== 0)
4315 actual_fsize
= apparent_fsize
= 0;
4318 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4319 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4320 apparent_fsize
+= n_regs
* 4;
4321 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
4324 /* Make sure nothing can clobber our register windows.
4325 If a SAVE must be done, or there is a stack-local variable,
4326 the register window area must be allocated.
4327 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4328 if (! leaf_function_p
|| size
> 0)
4329 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
4331 return SPARC_STACK_ALIGN (actual_fsize
);
4334 /* Output any necessary .register pseudo-ops. */
4337 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4339 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4345 /* Check if %g[2367] were used without
4346 .register being printed for them already. */
4347 for (i
= 2; i
< 8; i
++)
4349 if (regs_ever_live
[i
]
4350 && ! sparc_hard_reg_printed
[i
])
4352 sparc_hard_reg_printed
[i
] = 1;
4353 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
4360 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4361 as needed. LOW should be double-word aligned for 32-bit registers.
4362 Return the new OFFSET. */
4365 #define SORR_RESTORE 1
4368 save_or_restore_regs (int low
, int high
, rtx base
, int offset
, int action
)
4373 if (TARGET_ARCH64
&& high
<= 32)
4375 for (i
= low
; i
< high
; i
++)
4377 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4379 mem
= gen_rtx_MEM (DImode
, plus_constant (base
, offset
));
4380 set_mem_alias_set (mem
, sparc_sr_alias_set
);
4381 if (action
== SORR_SAVE
)
4383 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4384 RTX_FRAME_RELATED_P (insn
) = 1;
4386 else /* action == SORR_RESTORE */
4387 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4394 for (i
= low
; i
< high
; i
+= 2)
4396 bool reg0
= regs_ever_live
[i
] && ! call_used_regs
[i
];
4397 bool reg1
= regs_ever_live
[i
+1] && ! call_used_regs
[i
+1];
4398 enum machine_mode mode
;
4403 mode
= i
< 32 ? DImode
: DFmode
;
4408 mode
= i
< 32 ? SImode
: SFmode
;
4413 mode
= i
< 32 ? SImode
: SFmode
;
4420 mem
= gen_rtx_MEM (mode
, plus_constant (base
, offset
));
4421 set_mem_alias_set (mem
, sparc_sr_alias_set
);
4422 if (action
== SORR_SAVE
)
4424 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4425 RTX_FRAME_RELATED_P (insn
) = 1;
4427 else /* action == SORR_RESTORE */
4428 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4430 /* Always preserve double-word alignment. */
4431 offset
= (offset
+ 7) & -8;
4438 /* Emit code to save call-saved registers. */
4441 emit_save_regs (void)
4443 HOST_WIDE_INT offset
;
4446 offset
= frame_base_offset
- apparent_fsize
;
4448 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
4450 /* ??? This might be optimized a little as %g1 might already have a
4451 value close enough that a single add insn will do. */
4452 /* ??? Although, all of this is probably only a temporary fix
4453 because if %g1 can hold a function result, then
4454 sparc_expand_epilogue will lose (the result will be
4456 base
= gen_rtx_REG (Pmode
, 1);
4457 emit_move_insn (base
, GEN_INT (offset
));
4458 emit_insn (gen_rtx_SET (VOIDmode
,
4460 gen_rtx_PLUS (Pmode
, frame_base_reg
, base
)));
4464 base
= frame_base_reg
;
4466 offset
= save_or_restore_regs (0, 8, base
, offset
, SORR_SAVE
);
4467 save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, SORR_SAVE
);
4470 /* Emit code to restore call-saved registers. */
4473 emit_restore_regs (void)
4475 HOST_WIDE_INT offset
;
4478 offset
= frame_base_offset
- apparent_fsize
;
4480 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
4482 base
= gen_rtx_REG (Pmode
, 1);
4483 emit_move_insn (base
, GEN_INT (offset
));
4484 emit_insn (gen_rtx_SET (VOIDmode
,
4486 gen_rtx_PLUS (Pmode
, frame_base_reg
, base
)));
4490 base
= frame_base_reg
;
4492 offset
= save_or_restore_regs (0, 8, base
, offset
, SORR_RESTORE
);
4493 save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, SORR_RESTORE
);
4496 /* Generate a save_register_window insn. */
4499 gen_save_register_window (rtx increment
)
4502 return gen_save_register_windowdi (increment
);
4504 return gen_save_register_windowsi (increment
);
4507 /* Generate an increment for the stack pointer. */
4510 gen_stack_pointer_inc (rtx increment
)
4513 return gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
, increment
);
4515 return gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, increment
);
4518 /* Generate a decrement for the stack pointer. */
4521 gen_stack_pointer_dec (rtx decrement
)
4524 return gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
, decrement
);
4526 return gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, decrement
);
4529 /* Expand the function prologue. The prologue is responsible for reserving
4530 storage for the frame, saving the call-saved registers and loading the
4531 PIC register if needed. */
4534 sparc_expand_prologue (void)
4539 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4540 on the final value of the flag means deferring the prologue/epilogue
4541 expansion until just before the second scheduling pass, which is too
4542 late to emit multiple epilogues or return insns.
4544 Of course we are making the assumption that the value of the flag
4545 will not change between now and its final value. Of the three parts
4546 of the formula, only the last one can reasonably vary. Let's take a
4547 closer look, after assuming that the first two ones are set to true
4548 (otherwise the last value is effectively silenced).
4550 If only_leaf_regs_used returns false, the global predicate will also
4551 be false so the actual frame size calculated below will be positive.
4552 As a consequence, the save_register_window insn will be emitted in
4553 the instruction stream; now this insn explicitly references %fp
4554 which is not a leaf register so only_leaf_regs_used will always
4555 return false subsequently.
4557 If only_leaf_regs_used returns true, we hope that the subsequent
4558 optimization passes won't cause non-leaf registers to pop up. For
4559 example, the regrename pass has special provisions to not rename to
4560 non-leaf registers in a leaf function. */
4561 sparc_leaf_function_p
4562 = optimize
> 0 && leaf_function_p () && only_leaf_regs_used ();
4564 /* Need to use actual_fsize, since we are also allocating
4565 space for our callee (and our own register save area). */
4567 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4569 /* Advertise that the data calculated just above are now valid. */
4570 sparc_prologue_data_valid_p
= true;
4572 if (sparc_leaf_function_p
)
4574 frame_base_reg
= stack_pointer_rtx
;
4575 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
4579 frame_base_reg
= hard_frame_pointer_rtx
;
4580 frame_base_offset
= SPARC_STACK_BIAS
;
4583 if (actual_fsize
== 0)
4585 else if (sparc_leaf_function_p
)
4587 if (actual_fsize
<= 4096)
4588 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize
)));
4589 else if (actual_fsize
<= 8192)
4591 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4592 /* %sp is still the CFA register. */
4593 RTX_FRAME_RELATED_P (insn
) = 1;
4595 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
4599 rtx reg
= gen_rtx_REG (Pmode
, 1);
4600 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4601 insn
= emit_insn (gen_stack_pointer_inc (reg
));
4603 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
4604 PATTERN (gen_stack_pointer_inc (GEN_INT (-actual_fsize
))),
4608 RTX_FRAME_RELATED_P (insn
) = 1;
4612 if (actual_fsize
<= 4096)
4613 insn
= emit_insn (gen_save_register_window (GEN_INT (-actual_fsize
)));
4614 else if (actual_fsize
<= 8192)
4616 insn
= emit_insn (gen_save_register_window (GEN_INT (-4096)));
4617 /* %sp is not the CFA register anymore. */
4618 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
4622 rtx reg
= gen_rtx_REG (Pmode
, 1);
4623 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4624 insn
= emit_insn (gen_save_register_window (reg
));
4627 RTX_FRAME_RELATED_P (insn
) = 1;
4628 for (i
=0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
4629 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, i
)) = 1;
4632 /* Call-saved registers are saved just above the outgoing argument area. */
4636 /* Load the PIC register if needed. */
4637 if (flag_pic
&& current_function_uses_pic_offset_table
)
4638 load_pic_register ();
4641 /* This function generates the assembly code for function entry, which boils
4642 down to emitting the necessary .register directives.
4644 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4645 an 8-byte block of memory. If any fpu reg is used in the function, we
4646 allocate such a block here, at the bottom of the frame, just in case it's
4647 needed." Could this explain the -8 in emit_restore_regs? */
4650 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4652 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4653 if (sparc_leaf_function_p
!= current_function_uses_only_leaf_regs
)
4656 sparc_output_scratch_registers (file
);
4659 /* Expand the function epilogue, either normal or part of a sibcall.
4660 We emit all the instructions except the return or the call. */
4663 sparc_expand_epilogue (void)
4666 emit_restore_regs ();
4668 if (actual_fsize
== 0)
4670 else if (sparc_leaf_function_p
)
4672 if (actual_fsize
<= 4096)
4673 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize
)));
4674 else if (actual_fsize
<= 8192)
4676 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4677 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize
)));
4681 rtx reg
= gen_rtx_REG (Pmode
, 1);
4682 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4683 emit_insn (gen_stack_pointer_dec (reg
));
4688 /* Return true if it is appropriate to emit `return' instructions in the
4689 body of a function. */
4692 sparc_can_use_return_insn_p (void)
4694 return sparc_prologue_data_valid_p
4695 && (actual_fsize
== 0 || !sparc_leaf_function_p
);
4698 /* This function generates the assembly code for function exit. */
4701 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4703 /* If code does not drop into the epilogue, we have to still output
4704 a dummy nop for the sake of sane backtraces. Otherwise, if the
4705 last two instructions of a function were "call foo; dslot;" this
4706 can make the return PC of foo (i.e. address of call instruction
4707 plus 8) point to the first instruction in the next function. */
4709 rtx insn
, last_real_insn
;
4711 insn
= get_last_insn ();
4713 last_real_insn
= prev_real_insn (insn
);
4715 && GET_CODE (last_real_insn
) == INSN
4716 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
4717 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
4719 if (last_real_insn
&& GET_CODE (last_real_insn
) == CALL_INSN
)
4720 fputs("\tnop\n", file
);
4722 sparc_output_deferred_case_vectors ();
4725 /* Output a 'restore' instruction. */
4728 output_restore (rtx pat
)
4734 fputs ("\t restore\n", asm_out_file
);
4738 if (GET_CODE (pat
) != SET
)
4741 operands
[0] = SET_DEST (pat
);
4742 pat
= SET_SRC (pat
);
4744 switch (GET_CODE (pat
))
4747 operands
[1] = XEXP (pat
, 0);
4748 operands
[2] = XEXP (pat
, 1);
4749 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4752 operands
[1] = XEXP (pat
, 0);
4753 operands
[2] = XEXP (pat
, 1);
4754 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4757 operands
[1] = XEXP (pat
, 0);
4758 if (XEXP (pat
, 1) != const1_rtx
)
4760 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4764 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4769 /* Output a return. */
4772 output_return (rtx insn
)
4774 if (sparc_leaf_function_p
)
4776 /* This is a leaf function so we don't have to bother restoring the
4777 register window, which frees us from dealing with the convoluted
4778 semantics of restore/return. We simply output the jump to the
4779 return address and the insn in the delay slot (if any). */
4781 if (current_function_calls_eh_return
)
4784 return "jmp\t%%o7+%)%#";
4788 /* This is a regular function so we have to restore the register window.
4789 We may have a pending insn for the delay slot, which will be either
4790 combined with the 'restore' instruction or put in the delay slot of
4791 the 'return' instruction. */
4793 if (current_function_calls_eh_return
)
4795 /* If the function uses __builtin_eh_return, the eh_return
4796 machinery occupies the delay slot. */
4800 if (! flag_delayed_branch
)
4801 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file
);
4804 fputs ("\treturn\t%i7+8\n", asm_out_file
);
4806 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file
);
4808 if (flag_delayed_branch
)
4809 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
4811 fputs ("\t nop\n", asm_out_file
);
4813 else if (final_sequence
)
4817 delay
= NEXT_INSN (insn
);
4821 pat
= PATTERN (delay
);
4823 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
4825 epilogue_renumber (&pat
, 0);
4826 return "return\t%%i7+%)%#";
4830 output_asm_insn ("jmp\t%%i7+%)", NULL
);
4831 output_restore (pat
);
4832 PATTERN (delay
) = gen_blockage ();
4833 INSN_CODE (delay
) = -1;
4838 /* The delay slot is empty. */
4840 return "return\t%%i7+%)\n\t nop";
4841 else if (flag_delayed_branch
)
4842 return "jmp\t%%i7+%)\n\t restore";
4844 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4851 /* Output a sibling call. */
4854 output_sibcall (rtx insn
, rtx call_operand
)
4858 if (! flag_delayed_branch
)
4861 operands
[0] = call_operand
;
4863 if (sparc_leaf_function_p
)
4865 /* This is a leaf function so we don't have to bother restoring the
4866 register window. We simply output the jump to the function and
4867 the insn in the delay slot (if any). */
4869 if (LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
)
4873 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4876 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4877 it into branch if possible. */
4878 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4883 /* This is a regular function so we have to restore the register window.
4884 We may have a pending insn for the delay slot, which will be combined
4885 with the 'restore' instruction. */
4887 output_asm_insn ("call\t%a0, 0", operands
);
4891 rtx delay
= NEXT_INSN (insn
);
4895 output_restore (PATTERN (delay
));
4897 PATTERN (delay
) = gen_blockage ();
4898 INSN_CODE (delay
) = -1;
4901 output_restore (NULL_RTX
);
4907 /* Functions for handling argument passing.
4909 For 32-bit, the first 6 args are normally in registers and the rest are
4910 pushed. Any arg that starts within the first 6 words is at least
4911 partially passed in a register unless its data type forbids.
4913 For 64-bit, the argument registers are laid out as an array of 16 elements
4914 and arguments are added sequentially. The first 6 int args and up to the
4915 first 16 fp args (depending on size) are passed in regs.
4917 Slot Stack Integral Float Float in structure Double Long Double
4918 ---- ----- -------- ----- ------------------ ------ -----------
4919 15 [SP+248] %f31 %f30,%f31 %d30
4920 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4921 13 [SP+232] %f27 %f26,%f27 %d26
4922 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4923 11 [SP+216] %f23 %f22,%f23 %d22
4924 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4925 9 [SP+200] %f19 %f18,%f19 %d18
4926 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4927 7 [SP+184] %f15 %f14,%f15 %d14
4928 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4929 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4930 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4931 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4932 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4933 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4934 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4936 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4938 Integral arguments are always passed as 64-bit quantities appropriately
4941 Passing of floating point values is handled as follows.
4942 If a prototype is in scope:
4943 If the value is in a named argument (i.e. not a stdarg function or a
4944 value not part of the `...') then the value is passed in the appropriate
4946 If the value is part of the `...' and is passed in one of the first 6
4947 slots then the value is passed in the appropriate int reg.
4948 If the value is part of the `...' and is not passed in one of the first 6
4949 slots then the value is passed in memory.
4950 If a prototype is not in scope:
4951 If the value is one of the first 6 arguments the value is passed in the
4952 appropriate integer reg and the appropriate fp reg.
4953 If the value is not one of the first 6 arguments the value is passed in
4954 the appropriate fp reg and in memory.
4957 Summary of the calling conventions implemented by GCC on SPARC:
4960 size argument return value
4962 small integer <4 int. reg. int. reg.
4963 word 4 int. reg. int. reg.
4964 double word 8 int. reg. int. reg.
4966 _Complex small integer <8 int. reg. int. reg.
4967 _Complex word 8 int. reg. int. reg.
4968 _Complex double word 16 memory int. reg.
4970 vector integer <=8 int. reg. FP reg.
4971 vector integer >8 memory memory
4973 float 4 int. reg. FP reg.
4974 double 8 int. reg. FP reg.
4975 long double 16 memory memory
4977 _Complex float 8 memory FP reg.
4978 _Complex double 16 memory FP reg.
4979 _Complex long double 32 memory FP reg.
4981 vector float any memory memory
4983 aggregate any memory memory
4988 size argument return value
4990 small integer <8 int. reg. int. reg.
4991 word 8 int. reg. int. reg.
4992 double word 16 int. reg. int. reg.
4994 _Complex small integer <16 int. reg. int. reg.
4995 _Complex word 16 int. reg. int. reg.
4996 _Complex double word 32 memory int. reg.
4998 vector integer <=16 FP reg. FP reg.
4999 vector integer 16<s<=32 memory FP reg.
5000 vector integer >32 memory memory
5002 float 4 FP reg. FP reg.
5003 double 8 FP reg. FP reg.
5004 long double 16 FP reg. FP reg.
5006 _Complex float 8 FP reg. FP reg.
5007 _Complex double 16 FP reg. FP reg.
5008 _Complex long double 32 memory FP reg.
5010 vector float <=16 FP reg. FP reg.
5011 vector float 16<s<=32 memory FP reg.
5012 vector float >32 memory memory
5014 aggregate <=16 reg. reg.
5015 aggregate 16<s<=32 memory reg.
5016 aggregate >32 memory memory
5020 Note #1: complex floating-point types follow the extended SPARC ABIs as
5021 implemented by the Sun compiler.
5023 Note #2: integral vector types follow the scalar floating-point types
5024 conventions to match what is implemented by the Sun VIS SDK.
5026 Note #3: floating-point vector types follow the aggregate types
5030 /* Maximum number of int regs for args. */
5031 #define SPARC_INT_ARG_MAX 6
5032 /* Maximum number of fp regs for args. */
5033 #define SPARC_FP_ARG_MAX 16
5035 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5037 /* Handle the INIT_CUMULATIVE_ARGS macro.
5038 Initialize a variable CUM of type CUMULATIVE_ARGS
5039 for a call to a function whose data type is FNTYPE.
5040 For a library call, FNTYPE is 0. */
5043 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5044 rtx libname ATTRIBUTE_UNUSED
,
5045 tree fndecl ATTRIBUTE_UNUSED
)
5048 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
5049 cum
->libcall_p
= fntype
== 0;
5052 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
5053 When a prototype says `char' or `short', really pass an `int'. */
5056 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED
)
5058 return TARGET_ARCH32
? true : false;
5061 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5064 sparc_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
5066 return TARGET_ARCH64
? true : false;
5069 /* Scan the record type TYPE and return the following predicates:
5070 - INTREGS_P: the record contains at least one field or sub-field
5071 that is eligible for promotion in integer registers.
5072 - FP_REGS_P: the record contains at least one field or sub-field
5073 that is eligible for promotion in floating-point registers.
5074 - PACKED_P: the record contains at least one field that is packed.
5076 Sub-fields are not taken into account for the PACKED_P predicate. */
5079 scan_record_type (tree type
, int *intregs_p
, int *fpregs_p
, int *packed_p
)
5083 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5085 if (TREE_CODE (field
) == FIELD_DECL
)
5087 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5088 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5089 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5090 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5096 if (packed_p
&& DECL_PACKED (field
))
5102 /* Compute the slot number to pass an argument in.
5103 Return the slot number or -1 if passing on the stack.
5105 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5106 the preceding args and about the function being called.
5107 MODE is the argument's machine mode.
5108 TYPE is the data type of the argument (as a tree).
5109 This is null for libcalls where that information may
5111 NAMED is nonzero if this argument is a named parameter
5112 (otherwise it is an extra parameter matching an ellipsis).
5113 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5114 *PREGNO records the register number to use if scalar type.
5115 *PPADDING records the amount of padding needed in words. */
5118 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5119 tree type
, int named
, int incoming_p
,
5120 int *pregno
, int *ppadding
)
5122 int regbase
= (incoming_p
5123 ? SPARC_INCOMING_INT_ARG_FIRST
5124 : SPARC_OUTGOING_INT_ARG_FIRST
);
5125 int slotno
= cum
->words
;
5126 enum mode_class mclass
;
5131 if (type
&& TREE_ADDRESSABLE (type
))
5137 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5140 /* For SPARC64, objects requiring 16-byte alignment get it. */
5142 && GET_MODE_ALIGNMENT (mode
) >= 2 * BITS_PER_WORD
5143 && (slotno
& 1) != 0)
5144 slotno
++, *ppadding
= 1;
5146 mclass
= GET_MODE_CLASS (mode
);
5147 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5149 /* Vector types deserve special treatment because they are
5150 polymorphic wrt their mode, depending upon whether VIS
5151 instructions are enabled. */
5152 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5154 /* The SPARC port defines no floating-point vector modes. */
5155 if (mode
!= BLKmode
)
5160 /* Integral vector types should either have a vector
5161 mode or an integral mode, because we are guaranteed
5162 by pass_by_reference that their size is not greater
5163 than 16 bytes and TImode is 16-byte wide. */
5164 if (mode
== BLKmode
)
5167 /* Vector integers are handled like floats according to
5169 mclass
= MODE_FLOAT
;
5176 case MODE_COMPLEX_FLOAT
:
5177 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5179 if (slotno
>= SPARC_FP_ARG_MAX
)
5181 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5182 /* Arguments filling only one single FP register are
5183 right-justified in the outer double FP register. */
5184 if (GET_MODE_SIZE (mode
) <= 4)
5191 case MODE_COMPLEX_INT
:
5192 if (slotno
>= SPARC_INT_ARG_MAX
)
5194 regno
= regbase
+ slotno
;
5198 if (mode
== VOIDmode
)
5199 /* MODE is VOIDmode when generating the actual call. */
5202 if (mode
!= BLKmode
)
5205 /* For SPARC64, objects requiring 16-byte alignment get it. */
5208 && TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5209 && (slotno
& 1) != 0)
5210 slotno
++, *ppadding
= 1;
5212 if (TARGET_ARCH32
|| !type
|| (TREE_CODE (type
) == UNION_TYPE
))
5214 if (slotno
>= SPARC_INT_ARG_MAX
)
5216 regno
= regbase
+ slotno
;
5218 else /* TARGET_ARCH64 && type */
5220 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5222 /* First see what kinds of registers we would need. */
5223 if (TREE_CODE (type
) == VECTOR_TYPE
)
5226 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5228 /* The ABI obviously doesn't specify how packed structures
5229 are passed. These are defined to be passed in int regs
5230 if possible, otherwise memory. */
5231 if (packed_p
|| !named
)
5232 fpregs_p
= 0, intregs_p
= 1;
5234 /* If all arg slots are filled, then must pass on stack. */
5235 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5238 /* If there are only int args and all int arg slots are filled,
5239 then must pass on stack. */
5240 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5243 /* Note that even if all int arg slots are filled, fp members may
5244 still be passed in regs if such regs are available.
5245 *PREGNO isn't set because there may be more than one, it's up
5246 to the caller to compute them. */
5259 /* Handle recursive register counting for structure field layout. */
5261 struct function_arg_record_value_parms
5263 rtx ret
; /* return expression being built. */
5264 int slotno
; /* slot number of the argument. */
5265 int named
; /* whether the argument is named. */
5266 int regbase
; /* regno of the base register. */
5267 int stack
; /* 1 if part of the argument is on the stack. */
5268 int intoffset
; /* offset of the first pending integer field. */
5269 unsigned int nregs
; /* number of words passed in registers. */
5272 static void function_arg_record_value_3
5273 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5274 static void function_arg_record_value_2
5275 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5276 static void function_arg_record_value_1
5277 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5278 static rtx
function_arg_record_value (tree
, enum machine_mode
, int, int, int);
5279 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5281 /* A subroutine of function_arg_record_value. Traverse the structure
5282 recursively and determine how many registers will be required. */
5285 function_arg_record_value_1 (tree type
, HOST_WIDE_INT startbitpos
,
5286 struct function_arg_record_value_parms
*parms
,
5291 /* We need to compute how many registers are needed so we can
5292 allocate the PARALLEL but before we can do that we need to know
5293 whether there are any packed fields. The ABI obviously doesn't
5294 specify how structures are passed in this case, so they are
5295 defined to be passed in int regs if possible, otherwise memory,
5296 regardless of whether there are fp values present. */
5299 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5301 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5308 /* Compute how many registers we need. */
5309 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5311 if (TREE_CODE (field
) == FIELD_DECL
)
5313 HOST_WIDE_INT bitpos
= startbitpos
;
5315 if (DECL_SIZE (field
) != 0)
5317 if (integer_zerop (DECL_SIZE (field
)))
5320 if (host_integerp (bit_position (field
), 1))
5321 bitpos
+= int_bit_position (field
);
5324 /* ??? FIXME: else assume zero offset. */
5326 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5327 function_arg_record_value_1 (TREE_TYPE (field
),
5331 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5332 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5337 if (parms
->intoffset
!= -1)
5339 unsigned int startbit
, endbit
;
5340 int intslots
, this_slotno
;
5342 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5343 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5345 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5346 this_slotno
= parms
->slotno
+ parms
->intoffset
5349 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5351 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5352 /* We need to pass this field on the stack. */
5356 parms
->nregs
+= intslots
;
5357 parms
->intoffset
= -1;
5360 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5361 If it wasn't true we wouldn't be here. */
5362 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5363 && DECL_MODE (field
) == BLKmode
)
5364 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5365 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5372 if (parms
->intoffset
== -1)
5373 parms
->intoffset
= bitpos
;
5379 /* A subroutine of function_arg_record_value. Assign the bits of the
5380 structure between parms->intoffset and bitpos to integer registers. */
5383 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5384 struct function_arg_record_value_parms
*parms
)
5386 enum machine_mode mode
;
5388 unsigned int startbit
, endbit
;
5389 int this_slotno
, intslots
, intoffset
;
5392 if (parms
->intoffset
== -1)
5395 intoffset
= parms
->intoffset
;
5396 parms
->intoffset
= -1;
5398 startbit
= intoffset
& -BITS_PER_WORD
;
5399 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5400 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5401 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5403 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5407 /* If this is the trailing part of a word, only load that much into
5408 the register. Otherwise load the whole register. Note that in
5409 the latter case we may pick up unwanted bits. It's not a problem
5410 at the moment but may wish to revisit. */
5412 if (intoffset
% BITS_PER_WORD
!= 0)
5413 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5418 intoffset
/= BITS_PER_UNIT
;
5421 regno
= parms
->regbase
+ this_slotno
;
5422 reg
= gen_rtx_REG (mode
, regno
);
5423 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5424 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5427 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5432 while (intslots
> 0);
5435 /* A subroutine of function_arg_record_value. Traverse the structure
5436 recursively and assign bits to floating point registers. Track which
5437 bits in between need integer registers; invoke function_arg_record_value_3
5438 to make that happen. */
5441 function_arg_record_value_2 (tree type
, HOST_WIDE_INT startbitpos
,
5442 struct function_arg_record_value_parms
*parms
,
5448 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5450 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5457 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5459 if (TREE_CODE (field
) == FIELD_DECL
)
5461 HOST_WIDE_INT bitpos
= startbitpos
;
5463 if (DECL_SIZE (field
) != 0)
5465 if (integer_zerop (DECL_SIZE (field
)))
5468 if (host_integerp (bit_position (field
), 1))
5469 bitpos
+= int_bit_position (field
);
5472 /* ??? FIXME: else assume zero offset. */
5474 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5475 function_arg_record_value_2 (TREE_TYPE (field
),
5479 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5480 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5485 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5486 int regno
, nregs
, pos
;
5487 enum machine_mode mode
= DECL_MODE (field
);
5490 function_arg_record_value_3 (bitpos
, parms
);
5492 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5495 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5496 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5498 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5500 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5506 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5507 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5509 reg
= gen_rtx_REG (mode
, regno
);
5510 pos
= bitpos
/ BITS_PER_UNIT
;
5511 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5512 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5516 regno
+= GET_MODE_SIZE (mode
) / 4;
5517 reg
= gen_rtx_REG (mode
, regno
);
5518 pos
+= GET_MODE_SIZE (mode
);
5519 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5520 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5526 if (parms
->intoffset
== -1)
5527 parms
->intoffset
= bitpos
;
5533 /* Used by function_arg and function_value to implement the complex
5534 conventions of the 64-bit ABI for passing and returning structures.
5535 Return an expression valid as a return value for the two macros
5536 FUNCTION_ARG and FUNCTION_VALUE.
5538 TYPE is the data type of the argument (as a tree).
5539 This is null for libcalls where that information may
5541 MODE is the argument's machine mode.
5542 SLOTNO is the index number of the argument's slot in the parameter array.
5543 NAMED is nonzero if this argument is a named parameter
5544 (otherwise it is an extra parameter matching an ellipsis).
5545 REGBASE is the regno of the base register for the parameter array. */
5548 function_arg_record_value (tree type
, enum machine_mode mode
,
5549 int slotno
, int named
, int regbase
)
5551 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5552 struct function_arg_record_value_parms parms
;
5555 parms
.ret
= NULL_RTX
;
5556 parms
.slotno
= slotno
;
5557 parms
.named
= named
;
5558 parms
.regbase
= regbase
;
5561 /* Compute how many registers we need. */
5563 parms
.intoffset
= 0;
5564 function_arg_record_value_1 (type
, 0, &parms
, false);
5566 /* Take into account pending integer fields. */
5567 if (parms
.intoffset
!= -1)
5569 unsigned int startbit
, endbit
;
5570 int intslots
, this_slotno
;
5572 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5573 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5574 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5575 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5577 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5579 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5580 /* We need to pass this field on the stack. */
5584 parms
.nregs
+= intslots
;
5586 nregs
= parms
.nregs
;
5588 /* Allocate the vector and handle some annoying special cases. */
5591 /* ??? Empty structure has no value? Duh? */
5594 /* Though there's nothing really to store, return a word register
5595 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5596 leads to breakage due to the fact that there are zero bytes to
5598 return gen_rtx_REG (mode
, regbase
);
5602 /* ??? C++ has structures with no fields, and yet a size. Give up
5603 for now and pass everything back in integer registers. */
5604 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5606 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5607 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5612 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5614 /* If at least one field must be passed on the stack, generate
5615 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5616 also be passed on the stack. We can't do much better because the
5617 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5618 of structures for which the fields passed exclusively in registers
5619 are not at the beginning of the structure. */
5621 XVECEXP (parms
.ret
, 0, 0)
5622 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5624 /* Fill in the entries. */
5626 parms
.intoffset
= 0;
5627 function_arg_record_value_2 (type
, 0, &parms
, false);
5628 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
5630 if (parms
.nregs
!= nregs
)
5636 /* Used by function_arg and function_value to implement the conventions
5637 of the 64-bit ABI for passing and returning unions.
5638 Return an expression valid as a return value for the two macros
5639 FUNCTION_ARG and FUNCTION_VALUE.
5641 SIZE is the size in bytes of the union.
5642 MODE is the argument's machine mode.
5643 REGNO is the hard register the union will be passed in. */
5646 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
5649 int nwords
= ROUND_ADVANCE (size
), i
;
5652 /* See comment in previous function for empty structures. */
5654 return gen_rtx_REG (mode
, regno
);
5656 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5659 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
5661 for (i
= 0; i
< nwords
; i
++)
5663 /* Unions are passed left-justified. */
5664 XVECEXP (regs
, 0, i
)
5665 = gen_rtx_EXPR_LIST (VOIDmode
,
5666 gen_rtx_REG (word_mode
, regno
),
5667 GEN_INT (UNITS_PER_WORD
* i
));
5674 /* Used by function_arg and function_value to implement the conventions
5675 for passing and returning large (BLKmode) vectors.
5676 Return an expression valid as a return value for the two macros
5677 FUNCTION_ARG and FUNCTION_VALUE.
5679 SIZE is the size in bytes of the vector.
5680 BASE_MODE is the argument's base machine mode.
5681 REGNO is the FP hard register the vector will be passed in. */
5684 function_arg_vector_value (int size
, enum machine_mode base_mode
, int regno
)
5686 unsigned short base_mode_size
= GET_MODE_SIZE (base_mode
);
5687 int nregs
= size
/ base_mode_size
, i
;
5690 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
5692 for (i
= 0; i
< nregs
; i
++)
5694 XVECEXP (regs
, 0, i
)
5695 = gen_rtx_EXPR_LIST (VOIDmode
,
5696 gen_rtx_REG (base_mode
, regno
),
5697 GEN_INT (base_mode_size
* i
));
5698 regno
+= base_mode_size
/ 4;
5704 /* Handle the FUNCTION_ARG macro.
5705 Determine where to put an argument to a function.
5706 Value is zero to push the argument on the stack,
5707 or a hard register in which to store the argument.
5709 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5710 the preceding args and about the function being called.
5711 MODE is the argument's machine mode.
5712 TYPE is the data type of the argument (as a tree).
5713 This is null for libcalls where that information may
5715 NAMED is nonzero if this argument is a named parameter
5716 (otherwise it is an extra parameter matching an ellipsis).
5717 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5720 function_arg (const struct sparc_args
*cum
, enum machine_mode mode
,
5721 tree type
, int named
, int incoming_p
)
5723 int regbase
= (incoming_p
5724 ? SPARC_INCOMING_INT_ARG_FIRST
5725 : SPARC_OUTGOING_INT_ARG_FIRST
);
5726 int slotno
, regno
, padding
;
5727 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5730 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
5738 reg
= gen_rtx_REG (mode
, regno
);
5742 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
5744 /* Structures up to 16 bytes in size are passed in arg slots on the
5745 stack and are promoted to registers where possible. */
5747 if (int_size_in_bytes (type
) > 16)
5748 abort (); /* shouldn't get here */
5750 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
5752 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
5754 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5757 abort (); /* shouldn't get here */
5759 return function_arg_union_value (size
, mode
, slotno
, regno
);
5761 else if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5763 /* Vector types deserve special treatment because they are
5764 polymorphic wrt their mode, depending upon whether VIS
5765 instructions are enabled. */
5766 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5769 abort (); /* shouldn't get here */
5771 if (mode
== BLKmode
)
5772 return function_arg_vector_value (size
,
5773 TYPE_MODE (TREE_TYPE (type
)),
5774 SPARC_FP_ARG_FIRST
+ 2*slotno
);
5776 mclass
= MODE_FLOAT
;
5779 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5780 but also have the slot allocated for them.
5781 If no prototype is in scope fp values in register slots get passed
5782 in two places, either fp regs and int regs or fp regs and memory. */
5783 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5784 && SPARC_FP_REG_P (regno
))
5786 reg
= gen_rtx_REG (mode
, regno
);
5787 if (cum
->prototype_p
|| cum
->libcall_p
)
5789 /* "* 2" because fp reg numbers are recorded in 4 byte
5792 /* ??? This will cause the value to be passed in the fp reg and
5793 in the stack. When a prototype exists we want to pass the
5794 value in the reg but reserve space on the stack. That's an
5795 optimization, and is deferred [for a bit]. */
5796 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
5797 return gen_rtx_PARALLEL (mode
,
5799 gen_rtx_EXPR_LIST (VOIDmode
,
5800 NULL_RTX
, const0_rtx
),
5801 gen_rtx_EXPR_LIST (VOIDmode
,
5805 /* ??? It seems that passing back a register even when past
5806 the area declared by REG_PARM_STACK_SPACE will allocate
5807 space appropriately, and will not copy the data onto the
5808 stack, exactly as we desire.
5810 This is due to locate_and_pad_parm being called in
5811 expand_call whenever reg_parm_stack_space > 0, which
5812 while beneficial to our example here, would seem to be
5813 in error from what had been intended. Ho hum... -- r~ */
5821 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
5825 /* On incoming, we don't need to know that the value
5826 is passed in %f0 and %i0, and it confuses other parts
5827 causing needless spillage even on the simplest cases. */
5831 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
5832 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
5834 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5835 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
5837 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5841 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5842 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5843 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5849 /* Scalar or complex int. */
5850 reg
= gen_rtx_REG (mode
, regno
);
5856 /* For an arg passed partly in registers and partly in memory,
5857 this is the number of bytes of registers used.
5858 For args passed entirely in registers or entirely in memory, zero.
5860 Any arg that starts in the first 6 regs but won't entirely fit in them
5861 needs partial registers on v8. On v9, structures with integer
5862 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5863 values that begin in the last fp reg [where "last fp reg" varies with the
5864 mode] will be split between that reg and memory. */
5867 sparc_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5868 tree type
, bool named
)
5870 int slotno
, regno
, padding
;
5872 /* We pass 0 for incoming_p here, it doesn't matter. */
5873 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5880 if ((slotno
+ (mode
== BLKmode
5881 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5882 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5883 > SPARC_INT_ARG_MAX
)
5884 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
5888 /* We are guaranteed by pass_by_reference that the size of the
5889 argument is not greater than 16 bytes, so we only need to return
5890 one word if the argument is partially passed in registers. */
5892 if (type
&& AGGREGATE_TYPE_P (type
))
5894 int size
= int_size_in_bytes (type
);
5896 if (size
> UNITS_PER_WORD
5897 && slotno
== SPARC_INT_ARG_MAX
- 1)
5898 return UNITS_PER_WORD
;
5900 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5901 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5902 && ! (TARGET_FPU
&& named
)))
5904 /* The complex types are passed as packed types. */
5905 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
5906 && slotno
== SPARC_INT_ARG_MAX
- 1)
5907 return UNITS_PER_WORD
;
5909 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5911 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5913 return UNITS_PER_WORD
;
5920 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5921 Specify whether to pass the argument by reference. */
5924 sparc_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5925 enum machine_mode mode
, tree type
,
5926 bool named ATTRIBUTE_UNUSED
)
5930 /* Original SPARC 32-bit ABI says that structures and unions,
5931 and quad-precision floats are passed by reference. For Pascal,
5932 also pass arrays by reference. All other base types are passed
5935 Extended ABI (as implemented by the Sun compiler) says that all
5936 complex floats are passed by reference. Pass complex integers
5937 in registers up to 8 bytes. More generally, enforce the 2-word
5938 cap for passing arguments in registers.
5940 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5941 integers are passed like floats of the same size, that is in
5942 registers up to 8 bytes. Pass all vector floats by reference
5943 like structure and unions. */
5944 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
5946 /* Catch CDImode, TFmode, DCmode and TCmode. */
5947 || GET_MODE_SIZE (mode
) > 8
5949 && TREE_CODE (type
) == VECTOR_TYPE
5950 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5954 /* Original SPARC 64-bit ABI says that structures and unions
5955 smaller than 16 bytes are passed in registers, as well as
5956 all other base types. For Pascal, pass arrays by reference.
5958 Extended ABI (as implemented by the Sun compiler) says that
5959 complex floats are passed in registers up to 16 bytes. Pass
5960 all complex integers in registers up to 16 bytes. More generally,
5961 enforce the 2-word cap for passing arguments in registers.
5963 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5964 integers are passed like floats of the same size, that is in
5965 registers (up to 16 bytes). Pass all vector floats like structure
5967 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5969 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
5970 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
5971 /* Catch CTImode and TCmode. */
5972 || GET_MODE_SIZE (mode
) > 16);
5976 /* Handle the FUNCTION_ARG_ADVANCE macro.
5977 Update the data in CUM to advance over an argument
5978 of mode MODE and data type TYPE.
5979 TYPE is null for libcalls where that information may not be available. */
5982 function_arg_advance (struct sparc_args
*cum
, enum machine_mode mode
,
5983 tree type
, int named
)
5985 int slotno
, regno
, padding
;
5987 /* We pass 0 for incoming_p here, it doesn't matter. */
5988 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5990 /* If register required leading padding, add it. */
5992 cum
->words
+= padding
;
5996 cum
->words
+= (mode
!= BLKmode
5997 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5998 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6002 if (type
&& AGGREGATE_TYPE_P (type
))
6004 int size
= int_size_in_bytes (type
);
6008 else if (size
<= 16)
6010 else /* passed by reference */
6015 cum
->words
+= (mode
!= BLKmode
6016 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6017 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6022 /* Handle the FUNCTION_ARG_PADDING macro.
6023 For the 64 bit ABI structs are always stored left shifted in their
6027 function_arg_padding (enum machine_mode mode
, tree type
)
6029 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6032 /* Fall back to the default. */
6033 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6036 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6037 Specify whether to return the return value in memory. */
6040 sparc_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
6043 /* Original SPARC 32-bit ABI says that structures and unions,
6044 and quad-precision floats are returned in memory. All other
6045 base types are returned in registers.
6047 Extended ABI (as implemented by the Sun compiler) says that
6048 all complex floats are returned in registers (8 FP registers
6049 at most for '_Complex long double'). Return all complex integers
6050 in registers (4 at most for '_Complex long long').
6052 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6053 integers are returned like floats of the same size, that is in
6054 registers up to 8 bytes and in memory otherwise. Return all
6055 vector floats in memory like structure and unions; note that
6056 they always have BLKmode like the latter. */
6057 return (TYPE_MODE (type
) == BLKmode
6058 || TYPE_MODE (type
) == TFmode
6059 || (TREE_CODE (type
) == VECTOR_TYPE
6060 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6062 /* Original SPARC 64-bit ABI says that structures and unions
6063 smaller than 32 bytes are returned in registers, as well as
6064 all other base types.
6066 Extended ABI (as implemented by the Sun compiler) says that all
6067 complex floats are returned in registers (8 FP registers at most
6068 for '_Complex long double'). Return all complex integers in
6069 registers (4 at most for '_Complex TItype').
6071 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6072 integers are returned like floats of the same size, that is in
6073 registers. Return all vector floats like structure and unions;
6074 note that they always have BLKmode like the latter. */
6075 return ((TYPE_MODE (type
) == BLKmode
6076 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32));
6079 /* Handle the TARGET_STRUCT_VALUE target hook.
6080 Return where to find the structure return value address. */
6083 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
, int incoming
)
6090 return gen_rtx_MEM (Pmode
, plus_constant (frame_pointer_rtx
,
6091 STRUCT_VALUE_OFFSET
));
6093 return gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
,
6094 STRUCT_VALUE_OFFSET
));
6098 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
6099 For v9, function return values are subject to the same rules as arguments,
6100 except that up to 32 bytes may be returned in registers. */
6103 function_value (tree type
, enum machine_mode mode
, int incoming_p
)
6105 /* Beware that the two values are swapped here wrt function_arg. */
6106 int regbase
= (incoming_p
6107 ? SPARC_OUTGOING_INT_ARG_FIRST
6108 : SPARC_INCOMING_INT_ARG_FIRST
);
6109 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6112 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6114 /* Vector types deserve special treatment because they are
6115 polymorphic wrt their mode, depending upon whether VIS
6116 instructions are enabled. */
6117 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6119 if ((TARGET_ARCH32
&& size
> 8) || (TARGET_ARCH64
&& size
> 32))
6120 abort (); /* shouldn't get here */
6122 if (mode
== BLKmode
)
6123 return function_arg_vector_value (size
,
6124 TYPE_MODE (TREE_TYPE (type
)),
6125 SPARC_FP_ARG_FIRST
);
6127 mclass
= MODE_FLOAT
;
6129 else if (type
&& TARGET_ARCH64
)
6131 if (TREE_CODE (type
) == RECORD_TYPE
)
6133 /* Structures up to 32 bytes in size are passed in registers,
6134 promoted to fp registers where possible. */
6136 if (int_size_in_bytes (type
) > 32)
6137 abort (); /* shouldn't get here */
6139 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6141 else if (TREE_CODE (type
) == UNION_TYPE
)
6143 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6146 abort (); /* shouldn't get here */
6148 return function_arg_union_value (size
, mode
, 0, regbase
);
6150 else if (AGGREGATE_TYPE_P (type
))
6152 /* All other aggregate types are passed in an integer register
6153 in a mode corresponding to the size of the type. */
6154 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
6157 abort (); /* shouldn't get here */
6159 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
6161 /* ??? We probably should have made the same ABI change in
6162 3.4.0 as the one we made for unions. The latter was
6163 required by the SCD though, while the former is not
6164 specified, so we favored compatibility and efficiency.
6166 Now we're stuck for aggregates larger than 16 bytes,
6167 because OImode vanished in the meantime. Let's not
6168 try to be unduly clever, and simply follow the ABI
6169 for unions in that case. */
6170 if (mode
== BLKmode
)
6171 return function_arg_union_value (bytes
, mode
, 0, regbase
);
6175 else if (mclass
== MODE_INT
6176 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6180 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6182 regno
= SPARC_FP_ARG_FIRST
;
6186 return gen_rtx_REG (mode
, regno
);
6189 /* Do what is necessary for `va_start'. We look at the current function
6190 to determine if stdarg or varargs is used and return the address of
6191 the first unnamed parameter. */
6194 sparc_builtin_saveregs (void)
6196 int first_reg
= current_function_args_info
.words
;
6200 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6201 emit_move_insn (gen_rtx_MEM (word_mode
,
6202 gen_rtx_PLUS (Pmode
,
6204 GEN_INT (FIRST_PARM_OFFSET (0)
6207 gen_rtx_REG (word_mode
,
6208 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6210 address
= gen_rtx_PLUS (Pmode
,
6212 GEN_INT (FIRST_PARM_OFFSET (0)
6213 + UNITS_PER_WORD
* first_reg
));
6218 /* Implement `va_start' for stdarg. */
6221 sparc_va_start (tree valist
, rtx nextarg
)
6223 nextarg
= expand_builtin_saveregs ();
6224 std_expand_builtin_va_start (valist
, nextarg
);
6227 /* Implement `va_arg' for stdarg. */
6230 sparc_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6232 HOST_WIDE_INT size
, rsize
, align
;
6235 tree ptrtype
= build_pointer_type (type
);
6237 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6240 size
= rsize
= UNITS_PER_WORD
;
6246 size
= int_size_in_bytes (type
);
6247 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6252 /* For SPARC64, objects requiring 16-byte alignment get it. */
6253 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6254 align
= 2 * UNITS_PER_WORD
;
6256 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6257 are left-justified in their slots. */
6258 if (AGGREGATE_TYPE_P (type
))
6261 size
= rsize
= UNITS_PER_WORD
;
6271 incr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
,
6272 ssize_int (align
- 1)));
6273 incr
= fold (build2 (BIT_AND_EXPR
, ptr_type_node
, incr
,
6274 ssize_int (-align
)));
6277 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6280 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6281 addr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
,
6282 ssize_int (rsize
- size
)));
6286 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6287 addr
= build_va_arg_indirect_ref (addr
);
6289 /* If the address isn't aligned properly for the type,
6290 we may need to copy to a temporary.
6291 FIXME: This is inefficient. Usually we can do this
6294 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6296 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6297 tree dest_addr
= build_fold_addr_expr (tmp
);
6299 tree copy
= build_function_call_expr
6300 (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6301 tree_cons (NULL_TREE
, dest_addr
,
6302 tree_cons (NULL_TREE
, addr
,
6303 tree_cons (NULL_TREE
, size_int (rsize
),
6306 gimplify_and_add (copy
, pre_p
);
6310 addr
= fold_convert (ptrtype
, addr
);
6312 incr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
, ssize_int (rsize
)));
6313 incr
= build2 (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
6314 gimplify_and_add (incr
, post_p
);
6316 return build_va_arg_indirect_ref (addr
);
6319 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6320 Specify whether the vector mode is supported by the hardware. */
6323 sparc_vector_mode_supported_p (enum machine_mode mode
)
6325 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6328 /* Return the string to output an unconditional branch to LABEL, which is
6329 the operand number of the label.
6331 DEST is the destination insn (i.e. the label), INSN is the source. */
6334 output_ubranch (rtx dest
, int label
, rtx insn
)
6336 static char string
[64];
6337 bool v9_form
= false;
6340 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6342 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6343 - INSN_ADDRESSES (INSN_UID (insn
)));
6344 /* Leave some instructions for "slop". */
6345 if (delta
>= -260000 && delta
< 260000)
6350 strcpy (string
, "ba%*,pt\t%%xcc, ");
6352 strcpy (string
, "b%*\t");
6354 p
= strchr (string
, '\0');
6365 /* Return the string to output a conditional branch to LABEL, which is
6366 the operand number of the label. OP is the conditional expression.
6367 XEXP (OP, 0) is assumed to be a condition code register (integer or
6368 floating point) and its mode specifies what kind of comparison we made.
6370 DEST is the destination insn (i.e. the label), INSN is the source.
6372 REVERSED is nonzero if we should reverse the sense of the comparison.
6374 ANNUL is nonzero if we should generate an annulling branch. */
6377 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6380 static char string
[64];
6381 enum rtx_code code
= GET_CODE (op
);
6382 rtx cc_reg
= XEXP (op
, 0);
6383 enum machine_mode mode
= GET_MODE (cc_reg
);
6384 const char *labelno
, *branch
;
6385 int spaces
= 8, far
;
6388 /* v9 branches are limited to +-1MB. If it is too far away,
6401 fbne,a,pn %fcc2, .LC29
6409 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6412 /* Reversal of FP compares takes care -- an ordered compare
6413 becomes an unordered compare and vice versa. */
6414 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6415 code
= reverse_condition_maybe_unordered (code
);
6417 code
= reverse_condition (code
);
6420 /* Start by writing the branch condition. */
6421 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6472 /* ??? !v9: FP branches cannot be preceded by another floating point
6473 insn. Because there is currently no concept of pre-delay slots,
6474 we can fix this only by always emitting a nop before a floating
6479 strcpy (string
, "nop\n\t");
6480 strcat (string
, branch
);
6493 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6505 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6526 strcpy (string
, branch
);
6528 spaces
-= strlen (branch
);
6529 p
= strchr (string
, '\0');
6531 /* Now add the annulling, the label, and a possible noop. */
6544 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
6546 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6547 - INSN_ADDRESSES (INSN_UID (insn
)));
6548 /* Leave some instructions for "slop". */
6549 if (delta
< -260000 || delta
>= 260000)
6553 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6555 static char v9_fcc_labelno
[] = "%%fccX, ";
6556 /* Set the char indicating the number of the fcc reg to use. */
6557 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
6558 labelno
= v9_fcc_labelno
;
6561 if (REGNO (cc_reg
) == SPARC_FCC_REG
)
6567 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
6569 labelno
= "%%xcc, ";
6575 labelno
= "%%icc, ";
6580 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6583 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6596 strcpy (p
, labelno
);
6597 p
= strchr (p
, '\0');
6600 strcpy (p
, ".+12\n\t nop\n\tb\t");
6601 /* Skip the next insn if requested or
6602 if we know that it will be a nop. */
6603 if (annul
|| ! final_sequence
)
6617 /* Emit a library call comparison between floating point X and Y.
6618 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6619 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6620 values as arguments instead of the TFmode registers themselves,
6621 that's why we cannot call emit_float_lib_cmp. */
6623 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
6626 rtx slot0
, slot1
, result
, tem
, tem2
;
6627 enum machine_mode mode
;
6632 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
6636 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
6640 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
6644 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
6648 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
6652 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
6663 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
6673 if (GET_CODE (x
) != MEM
)
6675 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
6676 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
6681 if (GET_CODE (y
) != MEM
)
6683 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
6684 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
6689 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
6691 XEXP (slot0
, 0), Pmode
,
6692 XEXP (slot1
, 0), Pmode
);
6698 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
6700 x
, TFmode
, y
, TFmode
);
6706 /* Immediately move the result of the libcall into a pseudo
6707 register so reload doesn't clobber the value if it needs
6708 the return register for a spill reg. */
6709 result
= gen_reg_rtx (mode
);
6710 emit_move_insn (result
, hard_libcall_value (mode
));
6715 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6719 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
6724 emit_cmp_insn (result
, const1_rtx
,
6725 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
6728 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
6731 tem
= gen_reg_rtx (mode
);
6733 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
6735 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
6736 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6740 tem
= gen_reg_rtx (mode
);
6742 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
6744 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
6745 tem2
= gen_reg_rtx (mode
);
6747 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
6749 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
6750 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
6756 /* Generate an unsigned DImode to FP conversion. This is the same code
6757 optabs would emit if we didn't have TFmode patterns. */
6760 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
6762 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
6765 in
= force_reg (DImode
, operands
[1]);
6766 neglab
= gen_label_rtx ();
6767 donelab
= gen_label_rtx ();
6768 i0
= gen_reg_rtx (DImode
);
6769 i1
= gen_reg_rtx (DImode
);
6770 f0
= gen_reg_rtx (mode
);
6772 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
6774 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
6775 emit_jump_insn (gen_jump (donelab
));
6778 emit_label (neglab
);
6780 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
6781 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
6782 emit_insn (gen_iordi3 (i0
, i0
, i1
));
6783 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
6784 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
6786 emit_label (donelab
);
6789 /* Generate an FP to unsigned DImode conversion. This is the same code
6790 optabs would emit if we didn't have TFmode patterns. */
6793 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
6795 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
6798 in
= force_reg (mode
, operands
[1]);
6799 neglab
= gen_label_rtx ();
6800 donelab
= gen_label_rtx ();
6801 i0
= gen_reg_rtx (DImode
);
6802 i1
= gen_reg_rtx (DImode
);
6803 limit
= gen_reg_rtx (mode
);
6804 f0
= gen_reg_rtx (mode
);
6806 emit_move_insn (limit
,
6807 CONST_DOUBLE_FROM_REAL_VALUE (
6808 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
6809 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
6811 emit_insn (gen_rtx_SET (VOIDmode
,
6813 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
6814 emit_jump_insn (gen_jump (donelab
));
6817 emit_label (neglab
);
6819 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
6820 emit_insn (gen_rtx_SET (VOIDmode
,
6822 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
6823 emit_insn (gen_movdi (i1
, const1_rtx
));
6824 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
6825 emit_insn (gen_xordi3 (out
, i0
, i1
));
6827 emit_label (donelab
);
6830 /* Return the string to output a conditional branch to LABEL, testing
6831 register REG. LABEL is the operand number of the label; REG is the
6832 operand number of the reg. OP is the conditional expression. The mode
6833 of REG says what kind of comparison we made.
6835 DEST is the destination insn (i.e. the label), INSN is the source.
6837 REVERSED is nonzero if we should reverse the sense of the comparison.
6839 ANNUL is nonzero if we should generate an annulling branch. */
6842 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
6843 int annul
, rtx insn
)
6845 static char string
[64];
6846 enum rtx_code code
= GET_CODE (op
);
6847 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
6852 /* branch on register are limited to +-128KB. If it is too far away,
6865 brgez,a,pn %o1, .LC29
6871 ba,pt %xcc, .LC29 */
6873 far
= get_attr_length (insn
) >= 3;
6875 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6877 code
= reverse_condition (code
);
6879 /* Only 64 bit versions of these instructions exist. */
6883 /* Start by writing the branch condition. */
6888 strcpy (string
, "brnz");
6892 strcpy (string
, "brz");
6896 strcpy (string
, "brgez");
6900 strcpy (string
, "brlz");
6904 strcpy (string
, "brlez");
6908 strcpy (string
, "brgz");
6915 p
= strchr (string
, '\0');
6917 /* Now add the annulling, reg, label, and nop. */
6924 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6927 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6932 *p
= p
< string
+ 8 ? '\t' : ' ';
6940 int veryfar
= 1, delta
;
6942 if (INSN_ADDRESSES_SET_P ())
6944 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6945 - INSN_ADDRESSES (INSN_UID (insn
)));
6946 /* Leave some instructions for "slop". */
6947 if (delta
>= -260000 && delta
< 260000)
6951 strcpy (p
, ".+12\n\t nop\n\t");
6952 /* Skip the next insn if requested or
6953 if we know that it will be a nop. */
6954 if (annul
|| ! final_sequence
)
6964 strcpy (p
, "ba,pt\t%%xcc, ");
6978 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6979 Such instructions cannot be used in the delay slot of return insn on v9.
6980 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6984 epilogue_renumber (register rtx
*where
, int test
)
6986 register const char *fmt
;
6988 register enum rtx_code code
;
6993 code
= GET_CODE (*where
);
6998 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7000 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7001 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7009 /* Do not replace the frame pointer with the stack pointer because
7010 it can cause the delayed instruction to load below the stack.
7011 This occurs when instructions like:
7013 (set (reg/i:SI 24 %i0)
7014 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7015 (const_int -20 [0xffffffec])) 0))
7017 are in the return delayed slot. */
7019 if (GET_CODE (XEXP (*where
, 0)) == REG
7020 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7021 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7022 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7027 if (SPARC_STACK_BIAS
7028 && GET_CODE (XEXP (*where
, 0)) == REG
7029 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7037 fmt
= GET_RTX_FORMAT (code
);
7039 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7044 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7045 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7048 else if (fmt
[i
] == 'e'
7049 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7055 /* Leaf functions and non-leaf functions have different needs. */
7058 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7061 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7063 static const int *const reg_alloc_orders
[] = {
7064 reg_leaf_alloc_order
,
7065 reg_nonleaf_alloc_order
};
7068 order_regs_for_local_alloc (void)
7070 static int last_order_nonleaf
= 1;
7072 if (regs_ever_live
[15] != last_order_nonleaf
)
7074 last_order_nonleaf
= !last_order_nonleaf
;
7075 memcpy ((char *) reg_alloc_order
,
7076 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7077 FIRST_PSEUDO_REGISTER
* sizeof (int));
7081 /* Return 1 if REG and MEM are legitimate enough to allow the various
7082 mem<-->reg splits to be run. */
7085 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7087 /* Punt if we are here by mistake. */
7088 if (! reload_completed
)
7091 /* We must have an offsettable memory reference. */
7092 if (! offsettable_memref_p (mem
))
7095 /* If we have legitimate args for ldd/std, we do not want
7096 the split to happen. */
7097 if ((REGNO (reg
) % 2) == 0
7098 && mem_min_alignment (mem
, 8))
7105 /* Return 1 if x and y are some kind of REG and they refer to
7106 different hard registers. This test is guaranteed to be
7107 run after reload. */
7110 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7112 if (GET_CODE (x
) != REG
)
7114 if (GET_CODE (y
) != REG
)
7116 if (REGNO (x
) == REGNO (y
))
7121 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7122 This makes them candidates for using ldd and std insns.
7124 Note reg1 and reg2 *must* be hard registers. */
7127 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7129 /* We might have been passed a SUBREG. */
7130 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7133 if (REGNO (reg1
) % 2 != 0)
7136 /* Integer ldd is deprecated in SPARC V9 */
7137 if (TARGET_V9
&& REGNO (reg1
) < 32)
7140 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7143 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7146 This can only happen when addr1 and addr2, the addresses in mem1
7147 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7148 addr1 must also be aligned on a 64-bit boundary.
7150 Also iff dependent_reg_rtx is not null it should not be used to
7151 compute the address for mem1, i.e. we cannot optimize a sequence
7163 But, note that the transformation from:
7168 is perfectly fine. Thus, the peephole2 patterns always pass us
7169 the destination register of the first load, never the second one.
7171 For stores we don't have a similar problem, so dependent_reg_rtx is
7175 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7179 HOST_WIDE_INT offset1
;
7181 /* The mems cannot be volatile. */
7182 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7185 /* MEM1 should be aligned on a 64-bit boundary. */
7186 if (MEM_ALIGN (mem1
) < 64)
7189 addr1
= XEXP (mem1
, 0);
7190 addr2
= XEXP (mem2
, 0);
7192 /* Extract a register number and offset (if used) from the first addr. */
7193 if (GET_CODE (addr1
) == PLUS
)
7195 /* If not a REG, return zero. */
7196 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7200 reg1
= REGNO (XEXP (addr1
, 0));
7201 /* The offset must be constant! */
7202 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7204 offset1
= INTVAL (XEXP (addr1
, 1));
7207 else if (GET_CODE (addr1
) != REG
)
7211 reg1
= REGNO (addr1
);
7212 /* This was a simple (mem (reg)) expression. Offset is 0. */
7216 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7217 if (GET_CODE (addr2
) != PLUS
)
7220 if (GET_CODE (XEXP (addr2
, 0)) != REG
7221 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7224 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7227 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7230 /* The first offset must be evenly divisible by 8 to ensure the
7231 address is 64 bit aligned. */
7232 if (offset1
% 8 != 0)
7235 /* The offset for the second addr must be 4 more than the first addr. */
7236 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7239 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7244 /* Return 1 if reg is a pseudo, or is the first register in
7245 a hard register pair. This makes it a candidate for use in
7246 ldd and std insns. */
7249 register_ok_for_ldd (rtx reg
)
7251 /* We might have been passed a SUBREG. */
7252 if (GET_CODE (reg
) != REG
)
7255 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7256 return (REGNO (reg
) % 2 == 0);
7261 /* Print operand X (an rtx) in assembler syntax to file FILE.
7262 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7263 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7266 print_operand (FILE *file
, rtx x
, int code
)
7271 /* Output an insn in a delay slot. */
7273 sparc_indent_opcode
= 1;
7275 fputs ("\n\t nop", file
);
7278 /* Output an annul flag if there's nothing for the delay slot and we
7279 are optimizing. This is always used with '(' below.
7280 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7281 this is a dbx bug. So, we only do this when optimizing.
7282 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7283 Always emit a nop in case the next instruction is a branch. */
7284 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7288 /* Output a 'nop' if there's nothing for the delay slot and we are
7289 not optimizing. This is always used with '*' above. */
7290 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7291 fputs ("\n\t nop", file
);
7292 else if (final_sequence
)
7293 sparc_indent_opcode
= 1;
7296 /* Output the right displacement from the saved PC on function return.
7297 The caller may have placed an "unimp" insn immediately after the call
7298 so we have to account for it. This insn is used in the 32-bit ABI
7299 when calling a function that returns a non zero-sized structure. The
7300 64-bit ABI doesn't have it. Be careful to have this test be the same
7301 as that used on the call. */
7303 && current_function_returns_struct
7304 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7306 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7312 /* Output the Embedded Medium/Anywhere code model base register. */
7313 fputs (EMBMEDANY_BASE_REG
, file
);
7316 /* Print some local dynamic TLS name. */
7317 assemble_name (file
, get_some_local_dynamic_name ());
7321 /* Adjust the operand to take into account a RESTORE operation. */
7322 if (GET_CODE (x
) == CONST_INT
)
7324 else if (GET_CODE (x
) != REG
)
7325 output_operand_lossage ("invalid %%Y operand");
7326 else if (REGNO (x
) < 8)
7327 fputs (reg_names
[REGNO (x
)], file
);
7328 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7329 fputs (reg_names
[REGNO (x
)-16], file
);
7331 output_operand_lossage ("invalid %%Y operand");
7334 /* Print out the low order register name of a register pair. */
7335 if (WORDS_BIG_ENDIAN
)
7336 fputs (reg_names
[REGNO (x
)+1], file
);
7338 fputs (reg_names
[REGNO (x
)], file
);
7341 /* Print out the high order register name of a register pair. */
7342 if (WORDS_BIG_ENDIAN
)
7343 fputs (reg_names
[REGNO (x
)], file
);
7345 fputs (reg_names
[REGNO (x
)+1], file
);
7348 /* Print out the second register name of a register pair or quad.
7349 I.e., R (%o0) => %o1. */
7350 fputs (reg_names
[REGNO (x
)+1], file
);
7353 /* Print out the third register name of a register quad.
7354 I.e., S (%o0) => %o2. */
7355 fputs (reg_names
[REGNO (x
)+2], file
);
7358 /* Print out the fourth register name of a register quad.
7359 I.e., T (%o0) => %o3. */
7360 fputs (reg_names
[REGNO (x
)+3], file
);
7363 /* Print a condition code register. */
7364 if (REGNO (x
) == SPARC_ICC_REG
)
7366 /* We don't handle CC[X]_NOOVmode because they're not supposed
7368 if (GET_MODE (x
) == CCmode
)
7369 fputs ("%icc", file
);
7370 else if (GET_MODE (x
) == CCXmode
)
7371 fputs ("%xcc", file
);
7376 /* %fccN register */
7377 fputs (reg_names
[REGNO (x
)], file
);
7380 /* Print the operand's address only. */
7381 output_address (XEXP (x
, 0));
7384 /* In this case we need a register. Use %g0 if the
7385 operand is const0_rtx. */
7387 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7389 fputs ("%g0", file
);
7396 switch (GET_CODE (x
))
7398 case IOR
: fputs ("or", file
); break;
7399 case AND
: fputs ("and", file
); break;
7400 case XOR
: fputs ("xor", file
); break;
7401 default: output_operand_lossage ("invalid %%A operand");
7406 switch (GET_CODE (x
))
7408 case IOR
: fputs ("orn", file
); break;
7409 case AND
: fputs ("andn", file
); break;
7410 case XOR
: fputs ("xnor", file
); break;
7411 default: output_operand_lossage ("invalid %%B operand");
7415 /* These are used by the conditional move instructions. */
7419 enum rtx_code rc
= GET_CODE (x
);
7423 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7424 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7425 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7427 rc
= reverse_condition (GET_CODE (x
));
7431 case NE
: fputs ("ne", file
); break;
7432 case EQ
: fputs ("e", file
); break;
7433 case GE
: fputs ("ge", file
); break;
7434 case GT
: fputs ("g", file
); break;
7435 case LE
: fputs ("le", file
); break;
7436 case LT
: fputs ("l", file
); break;
7437 case GEU
: fputs ("geu", file
); break;
7438 case GTU
: fputs ("gu", file
); break;
7439 case LEU
: fputs ("leu", file
); break;
7440 case LTU
: fputs ("lu", file
); break;
7441 case LTGT
: fputs ("lg", file
); break;
7442 case UNORDERED
: fputs ("u", file
); break;
7443 case ORDERED
: fputs ("o", file
); break;
7444 case UNLT
: fputs ("ul", file
); break;
7445 case UNLE
: fputs ("ule", file
); break;
7446 case UNGT
: fputs ("ug", file
); break;
7447 case UNGE
: fputs ("uge", file
); break;
7448 case UNEQ
: fputs ("ue", file
); break;
7449 default: output_operand_lossage (code
== 'c'
7450 ? "invalid %%c operand"
7451 : "invalid %%C operand");
7456 /* These are used by the movr instruction pattern. */
7460 enum rtx_code rc
= (code
== 'd'
7461 ? reverse_condition (GET_CODE (x
))
7465 case NE
: fputs ("ne", file
); break;
7466 case EQ
: fputs ("e", file
); break;
7467 case GE
: fputs ("gez", file
); break;
7468 case LT
: fputs ("lz", file
); break;
7469 case LE
: fputs ("lez", file
); break;
7470 case GT
: fputs ("gz", file
); break;
7471 default: output_operand_lossage (code
== 'd'
7472 ? "invalid %%d operand"
7473 : "invalid %%D operand");
7480 /* Print a sign-extended character. */
7481 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
7482 fprintf (file
, "%d", i
);
7487 /* Operand must be a MEM; write its address. */
7488 if (GET_CODE (x
) != MEM
)
7489 output_operand_lossage ("invalid %%f operand");
7490 output_address (XEXP (x
, 0));
7495 /* Print a sign-extended 32-bit value. */
7497 if (GET_CODE(x
) == CONST_INT
)
7499 else if (GET_CODE(x
) == CONST_DOUBLE
)
7500 i
= CONST_DOUBLE_LOW (x
);
7503 output_operand_lossage ("invalid %%s operand");
7506 i
= trunc_int_for_mode (i
, SImode
);
7507 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
7512 /* Do nothing special. */
7516 /* Undocumented flag. */
7517 output_operand_lossage ("invalid operand output code");
7520 if (GET_CODE (x
) == REG
)
7521 fputs (reg_names
[REGNO (x
)], file
);
7522 else if (GET_CODE (x
) == MEM
)
7525 /* Poor Sun assembler doesn't understand absolute addressing. */
7526 if (CONSTANT_P (XEXP (x
, 0)))
7527 fputs ("%g0+", file
);
7528 output_address (XEXP (x
, 0));
7531 else if (GET_CODE (x
) == HIGH
)
7533 fputs ("%hi(", file
);
7534 output_addr_const (file
, XEXP (x
, 0));
7537 else if (GET_CODE (x
) == LO_SUM
)
7539 print_operand (file
, XEXP (x
, 0), 0);
7540 if (TARGET_CM_MEDMID
)
7541 fputs ("+%l44(", file
);
7543 fputs ("+%lo(", file
);
7544 output_addr_const (file
, XEXP (x
, 1));
7547 else if (GET_CODE (x
) == CONST_DOUBLE
7548 && (GET_MODE (x
) == VOIDmode
7549 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
7551 if (CONST_DOUBLE_HIGH (x
) == 0)
7552 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
7553 else if (CONST_DOUBLE_HIGH (x
) == -1
7554 && CONST_DOUBLE_LOW (x
) < 0)
7555 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
7557 output_operand_lossage ("long long constant not a valid immediate operand");
7559 else if (GET_CODE (x
) == CONST_DOUBLE
)
7560 output_operand_lossage ("floating point constant not a valid immediate operand");
7561 else { output_addr_const (file
, x
); }
7564 /* Target hook for assembling integer objects. The sparc version has
7565 special handling for aligned DI-mode objects. */
7568 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
7570 /* ??? We only output .xword's for symbols and only then in environments
7571 where the assembler can handle them. */
7572 if (aligned_p
&& size
== 8
7573 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
7577 assemble_integer_with_op ("\t.xword\t", x
);
7582 assemble_aligned_integer (4, const0_rtx
);
7583 assemble_aligned_integer (4, x
);
7587 return default_assemble_integer (x
, size
, aligned_p
);
7590 /* Return the value of a code used in the .proc pseudo-op that says
7591 what kind of result this function returns. For non-C types, we pick
7592 the closest C type. */
7594 #ifndef SHORT_TYPE_SIZE
7595 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7598 #ifndef INT_TYPE_SIZE
7599 #define INT_TYPE_SIZE BITS_PER_WORD
7602 #ifndef LONG_TYPE_SIZE
7603 #define LONG_TYPE_SIZE BITS_PER_WORD
7606 #ifndef LONG_LONG_TYPE_SIZE
7607 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7610 #ifndef FLOAT_TYPE_SIZE
7611 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7614 #ifndef DOUBLE_TYPE_SIZE
7615 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7618 #ifndef LONG_DOUBLE_TYPE_SIZE
7619 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7623 sparc_type_code (register tree type
)
7625 register unsigned long qualifiers
= 0;
7626 register unsigned shift
;
7628 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7629 setting more, since some assemblers will give an error for this. Also,
7630 we must be careful to avoid shifts of 32 bits or more to avoid getting
7631 unpredictable results. */
7633 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
7635 switch (TREE_CODE (type
))
7641 qualifiers
|= (3 << shift
);
7646 qualifiers
|= (2 << shift
);
7650 case REFERENCE_TYPE
:
7652 qualifiers
|= (1 << shift
);
7656 return (qualifiers
| 8);
7659 case QUAL_UNION_TYPE
:
7660 return (qualifiers
| 9);
7663 return (qualifiers
| 10);
7666 return (qualifiers
| 16);
7669 /* If this is a range type, consider it to be the underlying
7671 if (TREE_TYPE (type
) != 0)
7674 /* Carefully distinguish all the standard types of C,
7675 without messing up if the language is not C. We do this by
7676 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7677 look at both the names and the above fields, but that's redundant.
7678 Any type whose size is between two C types will be considered
7679 to be the wider of the two types. Also, we do not have a
7680 special code to use for "long long", so anything wider than
7681 long is treated the same. Note that we can't distinguish
7682 between "int" and "long" in this code if they are the same
7683 size, but that's fine, since neither can the assembler. */
7685 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
7686 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
7688 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
7689 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
7691 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
7692 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
7695 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
7698 /* If this is a range type, consider it to be the underlying
7700 if (TREE_TYPE (type
) != 0)
7703 /* Carefully distinguish all the standard types of C,
7704 without messing up if the language is not C. */
7706 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
7707 return (qualifiers
| 6);
7710 return (qualifiers
| 7);
7712 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
7713 /* ??? We need to distinguish between double and float complex types,
7714 but I don't know how yet because I can't reach this code from
7715 existing front-ends. */
7716 return (qualifiers
| 7); /* Who knows? */
7719 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
7720 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
7721 case FILE_TYPE
: /* GNU Pascal FILE type. */
7722 case LANG_TYPE
: /* ? */
7726 abort (); /* Not a type! */
7733 /* Nested function support. */
7735 /* Emit RTL insns to initialize the variable parts of a trampoline.
7736 FNADDR is an RTX for the address of the function's pure code.
7737 CXT is an RTX for the static chain value for the function.
7739 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7740 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7741 (to store insns). This is a bit excessive. Perhaps a different
7742 mechanism would be better here.
7744 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7747 sparc_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7749 /* SPARC 32-bit trampoline:
7752 sethi %hi(static), %g2
7754 or %g2, %lo(static), %g2
7756 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7757 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7761 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
7762 expand_binop (SImode
, ior_optab
,
7763 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
7764 size_int (10), 0, 1),
7765 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
7766 NULL_RTX
, 1, OPTAB_DIRECT
));
7769 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7770 expand_binop (SImode
, ior_optab
,
7771 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
7772 size_int (10), 0, 1),
7773 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
7774 NULL_RTX
, 1, OPTAB_DIRECT
));
7777 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7778 expand_binop (SImode
, ior_optab
,
7779 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
7780 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
7781 NULL_RTX
, 1, OPTAB_DIRECT
));
7784 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7785 expand_binop (SImode
, ior_optab
,
7786 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
7787 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
7788 NULL_RTX
, 1, OPTAB_DIRECT
));
7790 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7791 aligned on a 16 byte boundary so one flush clears it all. */
7792 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
7793 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7794 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7795 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
7796 plus_constant (tramp
, 8)))));
7798 /* Call __enable_execute_stack after writing onto the stack to make sure
7799 the stack address is accessible. */
7800 #ifdef ENABLE_EXECUTE_STACK
7801 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7802 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7807 /* The 64-bit version is simpler because it makes more sense to load the
7808 values as "immediate" data out of the trampoline. It's also easier since
7809 we can read the PC without clobbering a register. */
7812 sparc64_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7814 /* SPARC 64-bit trampoline:
7823 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
7824 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
7825 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7826 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
7827 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7828 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
7829 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7830 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
7831 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
7832 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
7833 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
7835 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7836 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7837 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
7839 /* Call __enable_execute_stack after writing onto the stack to make sure
7840 the stack address is accessible. */
7841 #ifdef ENABLE_EXECUTE_STACK
7842 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7843 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7847 /* Adjust the cost of a scheduling dependency. Return the new cost of
7848 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7851 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7853 enum attr_type insn_type
;
7855 if (! recog_memoized (insn
))
7858 insn_type
= get_attr_type (insn
);
7860 if (REG_NOTE_KIND (link
) == 0)
7862 /* Data dependency; DEP_INSN writes a register that INSN reads some
7865 /* if a load, then the dependence must be on the memory address;
7866 add an extra "cycle". Note that the cost could be two cycles
7867 if the reg was written late in an instruction group; we ca not tell
7869 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7872 /* Get the delay only if the address of the store is the dependence. */
7873 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7875 rtx pat
= PATTERN(insn
);
7876 rtx dep_pat
= PATTERN (dep_insn
);
7878 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7879 return cost
; /* This should not happen! */
7881 /* The dependency between the two instructions was on the data that
7882 is being stored. Assume that this implies that the address of the
7883 store is not dependent. */
7884 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7887 return cost
+ 3; /* An approximation. */
7890 /* A shift instruction cannot receive its data from an instruction
7891 in the same cycle; add a one cycle penalty. */
7892 if (insn_type
== TYPE_SHIFT
)
7893 return cost
+ 3; /* Split before cascade into shift. */
7897 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7898 INSN writes some cycles later. */
7900 /* These are only significant for the fpu unit; writing a fp reg before
7901 the fpu has finished with it stalls the processor. */
7903 /* Reusing an integer register causes no problems. */
7904 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7912 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7914 enum attr_type insn_type
, dep_type
;
7915 rtx pat
= PATTERN(insn
);
7916 rtx dep_pat
= PATTERN (dep_insn
);
7918 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7921 insn_type
= get_attr_type (insn
);
7922 dep_type
= get_attr_type (dep_insn
);
7924 switch (REG_NOTE_KIND (link
))
7927 /* Data dependency; DEP_INSN writes a register that INSN reads some
7934 /* Get the delay iff the address of the store is the dependence. */
7935 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7938 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7945 /* If a load, then the dependence must be on the memory address. If
7946 the addresses aren't equal, then it might be a false dependency */
7947 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7949 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7950 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7951 || GET_CODE (SET_SRC (pat
)) != MEM
7952 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7953 XEXP (SET_SRC (pat
), 0)))
7961 /* Compare to branch latency is 0. There is no benefit from
7962 separating compare and branch. */
7963 if (dep_type
== TYPE_COMPARE
)
7965 /* Floating point compare to branch latency is less than
7966 compare to conditional move. */
7967 if (dep_type
== TYPE_FPCMP
)
7976 /* Anti-dependencies only penalize the fpu unit. */
7977 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7989 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
7993 case PROCESSOR_SUPERSPARC
:
7994 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7996 case PROCESSOR_HYPERSPARC
:
7997 case PROCESSOR_SPARCLITE86X
:
7998 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8007 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8008 int sched_verbose ATTRIBUTE_UNUSED
,
8009 int max_ready ATTRIBUTE_UNUSED
)
8014 sparc_use_sched_lookahead (void)
8016 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8017 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8019 if ((1 << sparc_cpu
) &
8020 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8021 (1 << PROCESSOR_SPARCLITE86X
)))
8027 sparc_issue_rate (void)
8034 /* Assume V9 processors are capable of at least dual-issue. */
8036 case PROCESSOR_SUPERSPARC
:
8038 case PROCESSOR_HYPERSPARC
:
8039 case PROCESSOR_SPARCLITE86X
:
8041 case PROCESSOR_ULTRASPARC
:
8042 case PROCESSOR_ULTRASPARC3
:
8048 set_extends (rtx insn
)
8050 register rtx pat
= PATTERN (insn
);
8052 switch (GET_CODE (SET_SRC (pat
)))
8054 /* Load and some shift instructions zero extend. */
8057 /* sethi clears the high bits */
8059 /* LO_SUM is used with sethi. sethi cleared the high
8060 bits and the values used with lo_sum are positive */
8062 /* Store flag stores 0 or 1 */
8072 rtx op0
= XEXP (SET_SRC (pat
), 0);
8073 rtx op1
= XEXP (SET_SRC (pat
), 1);
8074 if (GET_CODE (op1
) == CONST_INT
)
8075 return INTVAL (op1
) >= 0;
8076 if (GET_CODE (op0
) != REG
)
8078 if (sparc_check_64 (op0
, insn
) == 1)
8080 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8085 rtx op0
= XEXP (SET_SRC (pat
), 0);
8086 rtx op1
= XEXP (SET_SRC (pat
), 1);
8087 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8089 if (GET_CODE (op1
) == CONST_INT
)
8090 return INTVAL (op1
) >= 0;
8091 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8094 return GET_MODE (SET_SRC (pat
)) == SImode
;
8095 /* Positive integers leave the high bits zero. */
8097 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8099 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8102 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8104 return sparc_check_64 (SET_SRC (pat
), insn
);
8110 /* We _ought_ to have only one kind per function, but... */
8111 static GTY(()) rtx sparc_addr_diff_list
;
8112 static GTY(()) rtx sparc_addr_list
;
8115 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8117 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8119 sparc_addr_diff_list
8120 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8122 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8126 sparc_output_addr_vec (rtx vec
)
8128 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8129 int idx
, vlen
= XVECLEN (body
, 0);
8131 #ifdef ASM_OUTPUT_ADDR_VEC_START
8132 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8135 #ifdef ASM_OUTPUT_CASE_LABEL
8136 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8139 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8142 for (idx
= 0; idx
< vlen
; idx
++)
8144 ASM_OUTPUT_ADDR_VEC_ELT
8145 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8148 #ifdef ASM_OUTPUT_ADDR_VEC_END
8149 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8154 sparc_output_addr_diff_vec (rtx vec
)
8156 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8157 rtx base
= XEXP (XEXP (body
, 0), 0);
8158 int idx
, vlen
= XVECLEN (body
, 1);
8160 #ifdef ASM_OUTPUT_ADDR_VEC_START
8161 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8164 #ifdef ASM_OUTPUT_CASE_LABEL
8165 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8168 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8171 for (idx
= 0; idx
< vlen
; idx
++)
8173 ASM_OUTPUT_ADDR_DIFF_ELT
8176 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8177 CODE_LABEL_NUMBER (base
));
8180 #ifdef ASM_OUTPUT_ADDR_VEC_END
8181 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8186 sparc_output_deferred_case_vectors (void)
8191 if (sparc_addr_list
== NULL_RTX
8192 && sparc_addr_diff_list
== NULL_RTX
)
8195 /* Align to cache line in the function's code section. */
8196 function_section (current_function_decl
);
8198 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8200 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8202 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8203 sparc_output_addr_vec (XEXP (t
, 0));
8204 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8205 sparc_output_addr_diff_vec (XEXP (t
, 0));
8207 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8210 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8211 unknown. Return 1 if the high bits are zero, -1 if the register is
8214 sparc_check_64 (rtx x
, rtx insn
)
8216 /* If a register is set only once it is safe to ignore insns this
8217 code does not know how to handle. The loop will either recognize
8218 the single set and return the correct value or fail to recognize
8223 if (GET_CODE (x
) != REG
)
8226 if (GET_MODE (x
) == DImode
)
8227 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8229 if (flag_expensive_optimizations
8230 && REG_N_SETS (REGNO (y
)) == 1)
8236 insn
= get_last_insn_anywhere ();
8241 while ((insn
= PREV_INSN (insn
)))
8243 switch (GET_CODE (insn
))
8256 rtx pat
= PATTERN (insn
);
8257 if (GET_CODE (pat
) != SET
)
8259 if (rtx_equal_p (x
, SET_DEST (pat
)))
8260 return set_extends (insn
);
8261 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8262 return set_extends (insn
);
8263 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8271 /* Returns assembly code to perform a DImode shift using
8272 a 64-bit global or out register on SPARC-V8+. */
8274 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8276 static char asm_code
[60];
8278 /* The scratch register is only required when the destination
8279 register is not a 64-bit global or out register. */
8280 if (which_alternative
!= 2)
8281 operands
[3] = operands
[0];
8283 /* We can only shift by constants <= 63. */
8284 if (GET_CODE (operands
[2]) == CONST_INT
)
8285 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8287 if (GET_CODE (operands
[1]) == CONST_INT
)
8289 output_asm_insn ("mov\t%1, %3", operands
);
8293 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8294 if (sparc_check_64 (operands
[1], insn
) <= 0)
8295 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8296 output_asm_insn ("or\t%L1, %3, %3", operands
);
8299 strcpy(asm_code
, opcode
);
8301 if (which_alternative
!= 2)
8302 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8304 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8307 /* Output rtl to increment the profiler label LABELNO
8308 for profiling a function entry. */
8311 sparc_profile_hook (int labelno
)
8316 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8317 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8318 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8320 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8323 #ifdef OBJECT_FORMAT_ELF
8325 sparc_elf_asm_named_section (const char *name
, unsigned int flags
,
8328 if (flags
& SECTION_MERGE
)
8330 /* entsize cannot be expressed in this section attributes
8332 default_elf_asm_named_section (name
, flags
, decl
);
8336 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8338 if (!(flags
& SECTION_DEBUG
))
8339 fputs (",#alloc", asm_out_file
);
8340 if (flags
& SECTION_WRITE
)
8341 fputs (",#write", asm_out_file
);
8342 if (flags
& SECTION_TLS
)
8343 fputs (",#tls", asm_out_file
);
8344 if (flags
& SECTION_CODE
)
8345 fputs (",#execinstr", asm_out_file
);
8347 /* ??? Handle SECTION_BSS. */
8349 fputc ('\n', asm_out_file
);
8351 #endif /* OBJECT_FORMAT_ELF */
8353 /* We do not allow indirect calls to be optimized into sibling calls.
8355 We cannot use sibling calls when delayed branches are disabled
8356 because they will likely require the call delay slot to be filled.
8358 Also, on SPARC 32-bit we cannot emit a sibling call when the
8359 current function returns a structure. This is because the "unimp
8360 after call" convention would cause the callee to return to the
8361 wrong place. The generic code already disallows cases where the
8362 function being called returns a structure.
8364 It may seem strange how this last case could occur. Usually there
8365 is code after the call which jumps to epilogue code which dumps the
8366 return value into the struct return area. That ought to invalidate
8367 the sibling call right? Well, in the C++ case we can end up passing
8368 the pointer to the struct return area to a constructor (which returns
8369 void) and then nothing else happens. Such a sibling call would look
8370 valid without the added check here. */
8372 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
8375 && flag_delayed_branch
8376 && (TARGET_ARCH64
|| ! current_function_returns_struct
));
8379 /* libfunc renaming. */
8380 #include "config/gofast.h"
8383 sparc_init_libfuncs (void)
8387 /* Use the subroutines that Sun's library provides for integer
8388 multiply and divide. The `*' prevents an underscore from
8389 being prepended by the compiler. .umul is a little faster
8391 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
8392 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
8393 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
8394 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
8395 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
8397 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8398 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
8399 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
8400 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
8401 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
8402 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
8404 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8405 is because with soft-float, the SFmode and DFmode sqrt
8406 instructions will be absent, and the compiler will notice and
8407 try to use the TFmode sqrt instruction for calls to the
8408 builtin function sqrt, but this fails. */
8410 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
8412 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
8413 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
8414 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
8415 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
8416 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
8417 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
8419 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
8420 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
8421 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
8422 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
8424 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
8425 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
8426 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
8428 if (DITF_CONVERSION_LIBFUNCS
)
8430 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
8431 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
8432 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
8435 if (SUN_CONVERSION_LIBFUNCS
)
8437 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8438 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8439 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8440 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8445 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8446 do not exist in the library. Make sure the compiler does not
8447 emit calls to them by accident. (It should always use the
8448 hardware instructions.) */
8449 set_optab_libfunc (smul_optab
, SImode
, 0);
8450 set_optab_libfunc (sdiv_optab
, SImode
, 0);
8451 set_optab_libfunc (udiv_optab
, SImode
, 0);
8452 set_optab_libfunc (smod_optab
, SImode
, 0);
8453 set_optab_libfunc (umod_optab
, SImode
, 0);
8455 if (SUN_INTEGER_MULTIPLY_64
)
8457 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
8458 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
8459 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
8460 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
8461 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
8464 if (SUN_CONVERSION_LIBFUNCS
)
8466 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
8467 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
8468 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
8469 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
8473 gofast_maybe_init_libfuncs ();
8476 #define def_builtin(NAME, CODE, TYPE) \
8477 lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
8480 /* Implement the TARGET_INIT_BUILTINS target hook.
8481 Create builtin functions for special SPARC instructions. */
8484 sparc_init_builtins (void)
8487 sparc_vis_init_builtins ();
8490 /* Create builtin functions for VIS 1.0 instructions. */
8493 sparc_vis_init_builtins (void)
8495 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
8496 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
8497 tree v4hi
= build_vector_type (intHI_type_node
, 4);
8498 tree v2hi
= build_vector_type (intHI_type_node
, 2);
8499 tree v2si
= build_vector_type (intSI_type_node
, 2);
8501 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
8502 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
8503 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
8504 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
8505 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
8506 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
8507 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
8508 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
8509 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
8510 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
8511 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
8512 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
8513 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
8515 intDI_type_node
, 0);
8516 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
8518 intDI_type_node
, 0);
8519 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
8521 intSI_type_node
, 0);
8522 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
8524 intDI_type_node
, 0);
8526 /* Packing and expanding vectors. */
8527 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
, v4qi_ftype_v4hi
);
8528 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
8529 v8qi_ftype_v2si_v8qi
);
8530 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
8532 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
, v4hi_ftype_v4qi
);
8533 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
8534 v8qi_ftype_v4qi_v4qi
);
8536 /* Multiplications. */
8537 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
8538 v4hi_ftype_v4qi_v4hi
);
8539 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
8540 v4hi_ftype_v4qi_v2hi
);
8541 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
8542 v4hi_ftype_v4qi_v2hi
);
8543 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
8544 v4hi_ftype_v8qi_v4hi
);
8545 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
8546 v4hi_ftype_v8qi_v4hi
);
8547 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
8548 v2si_ftype_v4qi_v2hi
);
8549 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
8550 v2si_ftype_v4qi_v2hi
);
8552 /* Data aligning. */
8553 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
8554 v4hi_ftype_v4hi_v4hi
);
8555 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
8556 v8qi_ftype_v8qi_v8qi
);
8557 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
8558 v2si_ftype_v2si_v2si
);
8559 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
8562 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
8565 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
8568 /* Pixel distance. */
8569 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
8570 di_ftype_v8qi_v8qi_di
);
8573 /* Handle TARGET_EXPAND_BUILTIN target hook.
8574 Expand builtin functions for sparc instrinsics. */
8577 sparc_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8578 enum machine_mode tmode
, int ignore ATTRIBUTE_UNUSED
)
8581 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8582 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
8584 enum machine_mode mode
[4];
8587 mode
[arg_count
] = tmode
;
8590 || GET_MODE (target
) != tmode
8591 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8592 op
[arg_count
] = gen_reg_rtx (tmode
);
8594 op
[arg_count
] = target
;
8596 for (arglist
= TREE_OPERAND (exp
, 1); arglist
;
8597 arglist
= TREE_CHAIN (arglist
))
8599 tree arg
= TREE_VALUE (arglist
);
8602 mode
[arg_count
] = insn_data
[icode
].operand
[arg_count
].mode
;
8603 op
[arg_count
] = expand_expr (arg
, NULL_RTX
, VOIDmode
, 0);
8605 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
8607 op
[arg_count
] = copy_to_mode_reg (mode
[arg_count
], op
[arg_count
]);
8613 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
8616 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
8619 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
8634 sparc_extra_constraint_check (rtx op
, int c
, int strict
)
8639 && (c
== 'T' || c
== 'U'))
8645 return fp_sethi_p (op
);
8648 return fp_mov_p (op
);
8651 return fp_high_losum_p (op
);
8655 || (GET_CODE (op
) == REG
8656 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8657 || reg_renumber
[REGNO (op
)] >= 0)))
8658 return register_ok_for_ldd (op
);
8667 return fp_zero_operand (op
, GET_MODE (op
));
8673 /* Our memory extra constraints have to emulate the
8674 behavior of 'm' and 'o' in order for reload to work
8676 if (GET_CODE (op
) == MEM
)
8679 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8681 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8686 reload_ok_mem
= (reload_in_progress
8687 && GET_CODE (op
) == REG
8688 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8689 && reg_renumber
[REGNO (op
)] < 0);
8692 return reload_ok_mem
;
8695 /* ??? This duplicates information provided to the compiler by the
8696 ??? scheduler description. Some day, teach genautomata to output
8697 ??? the latencies and then CSE will just use that. */
8700 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
8702 enum machine_mode mode
= GET_MODE (x
);
8703 bool float_mode_p
= FLOAT_MODE_P (mode
);
8708 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8726 if (GET_MODE (x
) == DImode
8727 && ((XINT (x
, 3) == 0
8728 && (unsigned HOST_WIDE_INT
) XINT (x
, 2) < 0x1000)
8729 || (XINT (x
, 3) == -1
8731 && XINT (x
, 2) >= -0x1000)))
8738 /* If outer-code was a sign or zero extension, a cost
8739 of COSTS_N_INSNS (1) was already added in. This is
8740 why we are subtracting it back out. */
8741 if (outer_code
== ZERO_EXTEND
)
8743 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
8745 else if (outer_code
== SIGN_EXTEND
)
8747 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
8749 else if (float_mode_p
)
8751 *total
= sparc_costs
->float_load
;
8755 *total
= sparc_costs
->int_load
;
8763 *total
= sparc_costs
->float_plusminus
;
8765 *total
= COSTS_N_INSNS (1);
8770 *total
= sparc_costs
->float_mul
;
8771 else if (! TARGET_HARD_MUL
)
8772 *total
= COSTS_N_INSNS (25);
8778 if (sparc_costs
->int_mul_bit_factor
)
8782 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8784 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
8785 for (nbits
= 0; value
!= 0; value
&= value
- 1)
8788 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
8789 && GET_MODE (XEXP (x
, 1)) == DImode
)
8791 rtx x1
= XEXP (x
, 1);
8792 unsigned HOST_WIDE_INT value1
= XINT (x1
, 2);
8793 unsigned HOST_WIDE_INT value2
= XINT (x1
, 3);
8795 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
8797 for (; value2
!= 0; value2
&= value2
- 1)
8805 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
8806 bit_cost
= COSTS_N_INSNS (bit_cost
);
8810 *total
= sparc_costs
->int_mulX
+ bit_cost
;
8812 *total
= sparc_costs
->int_mul
+ bit_cost
;
8819 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
8829 *total
= sparc_costs
->float_div_df
;
8831 *total
= sparc_costs
->float_div_sf
;
8836 *total
= sparc_costs
->int_divX
;
8838 *total
= sparc_costs
->int_div
;
8845 *total
= COSTS_N_INSNS (1);
8852 case UNSIGNED_FLOAT
:
8856 case FLOAT_TRUNCATE
:
8857 *total
= sparc_costs
->float_move
;
8862 *total
= sparc_costs
->float_sqrt_df
;
8864 *total
= sparc_costs
->float_sqrt_sf
;
8869 *total
= sparc_costs
->float_cmp
;
8871 *total
= COSTS_N_INSNS (1);
8876 *total
= sparc_costs
->float_cmove
;
8878 *total
= sparc_costs
->int_cmove
;
8882 /* Handle the NAND vector patterns. */
8883 if (sparc_vector_mode_supported_p (GET_MODE (x
))
8884 && GET_CODE (XEXP (x
, 0)) == NOT
8885 && GET_CODE (XEXP (x
, 1)) == NOT
)
8887 *total
= COSTS_N_INSNS (1);
8898 /* Emit the sequence of insns SEQ while preserving the register REG. */
8901 emit_and_preserve (rtx seq
, rtx reg
)
8903 rtx slot
= gen_rtx_MEM (word_mode
,
8904 plus_constant (stack_pointer_rtx
, SPARC_STACK_BIAS
));
8906 emit_insn (gen_stack_pointer_dec (GEN_INT (STACK_BOUNDARY
/BITS_PER_UNIT
)));
8907 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
8909 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
8910 emit_insn (gen_stack_pointer_inc (GEN_INT (STACK_BOUNDARY
/BITS_PER_UNIT
)));
8913 /* Output the assembler code for a thunk function. THUNK_DECL is the
8914 declaration for the thunk function itself, FUNCTION is the decl for
8915 the target function. DELTA is an immediate constant offset to be
8916 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8917 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8920 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8921 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8924 rtx
this, insn
, funexp
;
8925 unsigned int int_arg_first
;
8927 reload_completed
= 1;
8928 epilogue_completed
= 1;
8930 reset_block_changes ();
8932 emit_note (NOTE_INSN_PROLOGUE_END
);
8934 if (flag_delayed_branch
)
8936 /* We will emit a regular sibcall below, so we need to instruct
8937 output_sibcall that we are in a leaf function. */
8938 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
8940 /* This will cause final.c to invoke leaf_renumber_regs so we
8941 must behave as if we were in a not-yet-leafified function. */
8942 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
8946 /* We will emit the sibcall manually below, so we will need to
8947 manually spill non-leaf registers. */
8948 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
8950 /* We really are in a leaf function. */
8951 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
8954 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8955 returns a structure, the structure return pointer is there instead. */
8956 if (TARGET_ARCH64
&& aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8957 this = gen_rtx_REG (Pmode
, int_arg_first
+ 1);
8959 this = gen_rtx_REG (Pmode
, int_arg_first
);
8961 /* Add DELTA. When possible use a plain add, otherwise load it into
8962 a register first. */
8965 rtx delta_rtx
= GEN_INT (delta
);
8967 if (! SPARC_SIMM13_P (delta
))
8969 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8970 emit_move_insn (scratch
, delta_rtx
);
8971 delta_rtx
= scratch
;
8974 /* THIS += DELTA. */
8975 emit_insn (gen_add2_insn (this, delta_rtx
));
8978 /* Add the word at address (*THIS + VCALL_OFFSET). */
8981 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8982 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8984 if (vcall_offset
>= 0)
8987 /* SCRATCH = *THIS. */
8988 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this));
8990 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8991 may not have any available scratch register at this point. */
8992 if (SPARC_SIMM13_P (vcall_offset
))
8994 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8995 else if (! fixed_regs
[5]
8996 /* The below sequence is made up of at least 2 insns,
8997 while the default method may need only one. */
8998 && vcall_offset
< -8192)
9000 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
9001 emit_move_insn (scratch2
, vcall_offset_rtx
);
9002 vcall_offset_rtx
= scratch2
;
9006 rtx increment
= GEN_INT (-4096);
9008 /* VCALL_OFFSET is a negative number whose typical range can be
9009 estimated as -32768..0 in 32-bit mode. In almost all cases
9010 it is therefore cheaper to emit multiple add insns than
9011 spilling and loading the constant into a register (at least
9013 while (! SPARC_SIMM13_P (vcall_offset
))
9015 emit_insn (gen_add2_insn (scratch
, increment
));
9016 vcall_offset
+= 4096;
9018 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
9021 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
9022 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
9023 gen_rtx_PLUS (Pmode
,
9025 vcall_offset_rtx
)));
9027 /* THIS += *(*THIS + VCALL_OFFSET). */
9028 emit_insn (gen_add2_insn (this, scratch
));
9031 /* Generate a tail call to the target function. */
9032 if (! TREE_USED (function
))
9034 assemble_external (function
);
9035 TREE_USED (function
) = 1;
9037 funexp
= XEXP (DECL_RTL (function
), 0);
9039 if (flag_delayed_branch
)
9041 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
9042 insn
= emit_call_insn (gen_sibcall (funexp
));
9043 SIBLING_CALL_P (insn
) = 1;
9047 /* The hoops we have to jump through in order to generate a sibcall
9048 without using delay slots... */
9049 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
9053 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
9055 load_pic_register (); /* clobbers %o7 */
9056 scratch
= legitimize_pic_address (funexp
, Pmode
, scratch
);
9059 emit_and_preserve (seq
, spill_reg
);
9061 else if (TARGET_ARCH32
)
9063 emit_insn (gen_rtx_SET (VOIDmode
,
9065 gen_rtx_HIGH (SImode
, funexp
)));
9066 emit_insn (gen_rtx_SET (VOIDmode
,
9068 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
9070 else /* TARGET_ARCH64 */
9072 switch (sparc_cmodel
)
9076 /* The destination can serve as a temporary. */
9077 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
9082 /* The destination cannot serve as a temporary. */
9083 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
9085 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
9088 emit_and_preserve (seq
, spill_reg
);
9096 emit_jump_insn (gen_indirect_jump (scratch
));
9101 /* Run just enough of rest_of_compilation to get the insns emitted.
9102 There's not really enough bulk here to make other passes such as
9103 instruction scheduling worth while. Note that use_thunk calls
9104 assemble_start_function and assemble_end_function. */
9105 insn
= get_insns ();
9106 insn_locators_initialize ();
9107 shorten_branches (insn
);
9108 final_start_function (insn
, file
, 1);
9109 final (insn
, file
, 1, 0);
9110 final_end_function ();
9112 reload_completed
= 0;
9113 epilogue_completed
= 0;
9117 /* Return true if sparc_output_mi_thunk would be able to output the
9118 assembler code for the thunk function specified by the arguments
9119 it is passed, and false otherwise. */
9121 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED
,
9122 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
9123 HOST_WIDE_INT vcall_offset
,
9124 tree function ATTRIBUTE_UNUSED
)
9126 /* Bound the loop used in the default method above. */
9127 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
9130 /* How to allocate a 'struct machine_function'. */
9132 static struct machine_function
*
9133 sparc_init_machine_status (void)
9135 return ggc_alloc_cleared (sizeof (struct machine_function
));
9138 /* Locate some local-dynamic symbol still in use by this function
9139 so that we can print its name in local-dynamic base patterns. */
9142 get_some_local_dynamic_name (void)
9146 if (cfun
->machine
->some_ld_name
)
9147 return cfun
->machine
->some_ld_name
;
9149 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9151 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
9152 return cfun
->machine
->some_ld_name
;
9158 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
9163 && GET_CODE (x
) == SYMBOL_REF
9164 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
9166 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
9173 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
9174 This is called from dwarf2out.c to emit call frame instructions
9175 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
9177 sparc_dwarf_handle_frame_unspec (const char *label
,
9178 rtx pattern ATTRIBUTE_UNUSED
,
9179 int index ATTRIBUTE_UNUSED
)
9181 gcc_assert (index
== UNSPECV_SAVEW
);
9182 dwarf2out_window_save (label
);
9185 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9186 We need to emit DTP-relative relocations. */
9189 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9194 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
9197 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
9202 output_addr_const (file
, x
);
9206 #include "gt-sparc.h"