?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge from mainline (gomp-merge-2005-02-26).
[official-gcc.git] / gcc / config / s390 / s390.h
bloba6b7a3afd519142ecde5568561bacccb3bb45f60
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 02111-1307, USA. */
23
24 #ifndef _S390_H
25 #define _S390_H
26
27 /* Override the __fixdfdi etc. routines when building libgcc2.
28 ??? This should be done in a cleaner way ... */
29 #if defined (IN_LIBGCC2) && !defined (__s390x__)
30 #include <config/s390/fixdfdi.h>
31 #endif
32
33 /* Which processor to generate code or schedule for. The cpu attribute
34 defines a list that mirrors this list, so changes to s390.md must be
35 made at the same time. */
36
37 enum processor_type
38 {
39 PROCESSOR_9672_G5,
40 PROCESSOR_9672_G6,
41 PROCESSOR_2064_Z900,
42 PROCESSOR_2084_Z990,
43 PROCESSOR_max
44 };
45
46 /* Optional architectural facilities supported by the processor. */
47
48 enum processor_flags
49 {
50 PF_IEEE_FLOAT = 1,
51 PF_ZARCH = 2,
52 PF_LONG_DISPLACEMENT = 4
53 };
54
55 extern enum processor_type s390_tune;
56 extern enum processor_flags s390_tune_flags;
57 extern const char *s390_tune_string;
58
59 extern enum processor_type s390_arch;
60 extern enum processor_flags s390_arch_flags;
61 extern const char *s390_arch_string;
62
63 extern const char *s390_warn_framesize_string;
64 extern const char *s390_warn_dynamicstack_string;
65 extern const char *s390_stack_size_string;
66 extern const char *s390_stack_guard_string;
67
68 #define TARGET_CPU_IEEE_FLOAT \
69 (s390_arch_flags & PF_IEEE_FLOAT)
70 #define TARGET_CPU_ZARCH \
71 (s390_arch_flags & PF_ZARCH)
72 #define TARGET_CPU_LONG_DISPLACEMENT \
73 (s390_arch_flags & PF_LONG_DISPLACEMENT)
74
75 #define TARGET_LONG_DISPLACEMENT \
76 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
77
78
79 /* Run-time target specification. */
80
81 /* This will be overridden by OS headers. */
82 #define TARGET_TPF 0
83
84 /* Target CPU builtins. */
85 #define TARGET_CPU_CPP_BUILTINS() \
86 do \
87 { \
88 builtin_assert ("cpu=s390"); \
89 builtin_assert ("machine=s390"); \
90 builtin_define ("__s390__"); \
91 if (TARGET_64BIT) \
92 builtin_define ("__s390x__"); \
93 } \
94 while (0)
95
96 /* Optional target features. */
97 extern int target_flags;
98
99 #define MASK_HARD_FLOAT 0x01
100 #define MASK_SMALL_EXEC 0x04
101 #define MASK_DEBUG_ARG 0x08
102 #define MASK_64BIT 0x10
103 #define MASK_ZARCH 0x20
104 #define MASK_MVCLE 0x40
105 #define MASK_TPF_PROFILING 0x80
106 #define MASK_NO_FUSED_MADD 0x100
107 #define MASK_BACKCHAIN 0x200
108 #define MASK_PACKED_STACK 0x400
109
110 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
111 #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
112 #define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC)
113 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
114 #define TARGET_64BIT (target_flags & MASK_64BIT)
115 #define TARGET_ZARCH (target_flags & MASK_ZARCH)
116 #define TARGET_MVCLE (target_flags & MASK_MVCLE)
117 #define TARGET_TPF_PROFILING (target_flags & MASK_TPF_PROFILING)
118 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
119 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
120 #define TARGET_BACKCHAIN (target_flags & MASK_BACKCHAIN)
121 #define TARGET_PACKED_STACK (target_flags & MASK_PACKED_STACK)
122
123 /* ??? Once this actually works, it could be made a runtime option. */
124 #define TARGET_IBM_FLOAT 0
125 #define TARGET_IEEE_FLOAT 1
126
127 #ifdef DEFAULT_TARGET_64BIT
128 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_FLOAT)
129 #else
130 #define TARGET_DEFAULT MASK_HARD_FLOAT
131 #endif
132
133 #define TARGET_SWITCHES \
134 { { "hard-float", 1, N_("Use hardware fp")}, \
135 { "soft-float", -1, N_("Don't use hardware fp")}, \
136 { "small-exec", 4, N_("Use bras for executable < 64k")}, \
137 { "no-small-exec", -4, N_("Don't use bras")}, \
138 { "debug", 8, N_("Additional debug prints")}, \
139 { "no-debug", -8, N_("Don't print additional debug prints")}, \
140 { "64", 16, N_("64 bit ABI")}, \
141 { "31", -16, N_("31 bit ABI")}, \
142 { "zarch", 32, N_("z/Architecture")}, \
143 { "esa", -32, N_("ESA/390 architecture")}, \
144 { "mvcle", 64, N_("mvcle use")}, \
145 { "no-mvcle", -64, N_("mvc&ex")}, \
146 { "tpf-trace", 128, N_("Enable tpf OS tracing code")}, \
147 { "no-tpf-trace", -128, N_("Disable tpf OS tracing code")}, \
148 { "no-fused-madd", 256, N_("Disable fused multiply/add instructions")},\
149 { "fused-madd", -256, N_("Enable fused multiply/add instructions")}, \
150 { "backchain", 512, N_("Maintain backchain pointer")}, \
151 { "no-backchain", -512, N_("Don't maintain backchain pointer")}, \
152 { "packed-stack", 1024, N_("Use packed stack layout")}, \
153 { "no-packed-stack", -1024, N_("Don't use packed stack layout")}, \
154 { "", TARGET_DEFAULT, 0 } }
155
156 #define TARGET_OPTIONS \
157 { { "tune=", &s390_tune_string, \
158 N_("Schedule code for given CPU"), 0}, \
159 { "arch=", &s390_arch_string, \
160 N_("Generate code for given CPU"), 0}, \
161 { "warn-framesize=", &s390_warn_framesize_string, \
162 N_("Warn if a single function's framesize exceeds the given framesize"), \
163 0}, \
164 { "warn-dynamicstack", &s390_warn_dynamicstack_string, \
165 N_("Warn if a function uses alloca or creates an array with dynamic size"),\
166 0}, \
167 { "stack-size=", &s390_stack_size_string, \
168 N_("Emit extra code in the function prologue in order to trap if the stack"\
169 "size exceeds the given limit"), 0}, \
170 { "stack-guard=", &s390_stack_guard_string, \
171 N_("Set the max. number of bytes which has to be left to stack size " \
172 "before a trap instruction is triggered"), 0}, \
173 }
174
175 /* Support for configure-time defaults. */
176 #define OPTION_DEFAULT_SPECS \
177 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \
178 { "arch", "%{!march=*:-march=%(VALUE)}" }, \
179 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
180
181 /* Defaulting rules. */
182 #ifdef DEFAULT_TARGET_64BIT
183 #define DRIVER_SELF_SPECS \
184 "%{!m31:%{!m64:-m64}}", \
185 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
186 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
187 #else
188 #define DRIVER_SELF_SPECS \
189 "%{!m31:%{!m64:-m31}}", \
190 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
191 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
192 #endif
193
194 /* Target version string. Overridden by the OS header. */
195 #ifdef DEFAULT_TARGET_64BIT
196 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
197 #else
198 #define TARGET_VERSION fprintf (stderr, " (S/390)");
199 #endif
200
201 /* Hooks to override options. */
202 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
203 #define OVERRIDE_OPTIONS override_options ()
204
205 /* Frame pointer is not used for debugging. */
206 #define CAN_DEBUG_WITHOUT_FP
207
208
209 /* In libgcc2, determine target settings as compile-time constants. */
210 #ifdef IN_LIBGCC2
211 #undef TARGET_64BIT
212 #ifdef __s390x__
213 #define TARGET_64BIT 1
214 #else
215 #define TARGET_64BIT 0
216 #endif
217 #endif
218
219
220 /* Target machine storage layout. */
221
222 /* Everything is big-endian. */
223 #define BITS_BIG_ENDIAN 1
224 #define BYTES_BIG_ENDIAN 1
225 #define WORDS_BIG_ENDIAN 1
226
227 /* Width of a word, in units (bytes). */
228 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
229 #ifndef IN_LIBGCC2
230 #define MIN_UNITS_PER_WORD 4
231 #endif
232 #define MAX_BITS_PER_WORD 64
233
234 /* Function arguments and return values are promoted to word size. */
235 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
236 if (INTEGRAL_MODE_P (MODE) && \
237 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
238 (MODE) = Pmode; \
239 }
240
241 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
242 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
243
244 /* Boundary (in *bits*) on which stack pointer should be aligned. */
245 #define STACK_BOUNDARY 64
246
247 /* Allocation boundary (in *bits*) for the code of a function. */
248 #define FUNCTION_BOUNDARY 32
249
250 /* There is no point aligning anything to a rounder boundary than this. */
251 #define BIGGEST_ALIGNMENT 64
252
253 /* Alignment of field after `int : 0' in a structure. */
254 #define EMPTY_FIELD_BOUNDARY 32
255
256 /* Alignment on even addresses for LARL instruction. */
257 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
258 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
259
260 /* Alignment is not required by the hardware. */
261 #define STRICT_ALIGNMENT 0
262
263 /* Mode of stack savearea.
264 FUNCTION is VOIDmode because calling convention maintains SP.
265 BLOCK needs Pmode for SP.
266 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
267 #define STACK_SAVEAREA_MODE(LEVEL) \
268 (LEVEL == SAVE_FUNCTION ? VOIDmode \
269 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
270
271 /* Define target floating point format. */
272 #define TARGET_FLOAT_FORMAT \
273 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
274
275
276 /* Type layout. */
277
278 /* Sizes in bits of the source language data types. */
279 #define SHORT_TYPE_SIZE 16
280 #define INT_TYPE_SIZE 32
281 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
282 #define LONG_LONG_TYPE_SIZE 64
283 #define FLOAT_TYPE_SIZE 32
284 #define DOUBLE_TYPE_SIZE 64
285 #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */
286
287 /* We use "unsigned char" as default. */
288 #define DEFAULT_SIGNED_CHAR 0
289
290
291 /* Register usage. */
292
293 /* We have 16 general purpose registers (registers 0-15),
294 and 16 floating point registers (registers 16-31).
295 (On non-IEEE machines, we have only 4 fp registers.)
296
297 Amongst the general purpose registers, some are used
298 for specific purposes:
299 GPR 11: Hard frame pointer (if needed)
300 GPR 12: Global offset table pointer (if needed)
301 GPR 13: Literal pool base register
302 GPR 14: Return address register
303 GPR 15: Stack pointer
304
305 Registers 32-35 are 'fake' hard registers that do not
306 correspond to actual hardware:
307 Reg 32: Argument pointer
308 Reg 33: Condition code
309 Reg 34: Frame pointer
310 Reg 35: Return address pointer
311
312 Registers 36 and 37 are mapped to access registers
313 0 and 1, used to implement thread-local storage. */
314
315 #define FIRST_PSEUDO_REGISTER 38
316
317 /* Standard register usage. */
318 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
319 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
320 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
321 #define CC_REGNO_P(N) ((N) == 33)
322 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35)
323 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37)
324
325 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
326 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
327 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
328 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
329 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
330 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
331
332 #define SIBCALL_REGNUM 1
333 #define BASE_REGNUM 13
334 #define RETURN_REGNUM 14
335 #define CC_REGNUM 33
336 #define TP_REGNUM 36
337
338 /* Set up fixed registers and calling convention:
339
340 GPRs 0-5 are always call-clobbered,
341 GPRs 6-15 are always call-saved.
342 GPR 12 is fixed if used as GOT pointer.
343 GPR 13 is always fixed (as literal pool pointer).
344 GPR 14 is always fixed on S/390 machines (as return address).
345 GPR 15 is always fixed (as stack pointer).
346 The 'fake' hard registers are call-clobbered and fixed.
347 The access registers are call-saved and fixed.
348
349 On 31-bit, FPRs 18-19 are call-clobbered;
350 on 64-bit, FPRs 24-31 are call-clobbered.
351 The remaining FPRs are call-saved. */
352
353 #define FIXED_REGISTERS \
354 { 0, 0, 0, 0, \
355 0, 0, 0, 0, \
356 0, 0, 0, 0, \
357 0, 1, 1, 1, \
358 0, 0, 0, 0, \
359 0, 0, 0, 0, \
360 0, 0, 0, 0, \
361 0, 0, 0, 0, \
362 1, 1, 1, 1, \
363 1, 1 }
364
365 #define CALL_USED_REGISTERS \
366 { 1, 1, 1, 1, \
367 1, 1, 0, 0, \
368 0, 0, 0, 0, \
369 0, 1, 1, 1, \
370 1, 1, 1, 1, \
371 1, 1, 1, 1, \
372 1, 1, 1, 1, \
373 1, 1, 1, 1, \
374 1, 1, 1, 1, \
375 1, 1 }
376
377 #define CALL_REALLY_USED_REGISTERS \
378 { 1, 1, 1, 1, \
379 1, 1, 0, 0, \
380 0, 0, 0, 0, \
381 0, 0, 0, 0, \
382 1, 1, 1, 1, \
383 1, 1, 1, 1, \
384 1, 1, 1, 1, \
385 1, 1, 1, 1, \
386 1, 1, 1, 1, \
387 0, 0 }
388
389 #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage ()
390
391 /* Preferred register allocation order. */
392 #define REG_ALLOC_ORDER \
393 { 1, 2, 3, 4, 5, 0, 13, 12, 11, 10, 9, 8, 7, 6, 14, \
394 16, 17, 18, 19, 20, 21, 22, 23, \
395 24, 25, 26, 27, 28, 29, 30, 31, \
396 15, 32, 33, 34, 35, 36, 37 }
397
398
399 /* Fitting values into registers. */
400
401 /* Integer modes <= word size fit into any GPR.
402 Integer modes > word size fit into successive GPRs, starting with
403 an even-numbered register.
404 SImode and DImode fit into FPRs as well.
405
406 Floating point modes <= word size fit into any FPR or GPR.
407 Floating point modes > word size (i.e. DFmode on 32-bit) fit
408 into any FPR, or an even-odd GPR pair.
409
410 Complex floating point modes fit either into two FPRs, or into
411 successive GPRs (again starting with an even number).
412
413 Condition code modes fit only into the CC register. */
414
415 #define HARD_REGNO_NREGS(REGNO, MODE) \
416 (FP_REGNO_P(REGNO)? \
417 (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
418 GENERAL_REGNO_P(REGNO)? \
419 ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
420 ACCESS_REGNO_P(REGNO)? \
421 ((GET_MODE_SIZE(MODE)+4-1) / 4) : \
422 1)
423
424 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
425 (FP_REGNO_P(REGNO)? \
426 ((MODE) == SImode || (MODE) == DImode || \
427 GET_MODE_CLASS(MODE) == MODE_FLOAT || \
428 GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \
429 GENERAL_REGNO_P(REGNO)? \
430 (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \
431 CC_REGNO_P(REGNO)? \
432 GET_MODE_CLASS (MODE) == MODE_CC : \
433 FRAME_REGNO_P(REGNO)? \
434 (enum machine_mode) (MODE) == Pmode : \
435 ACCESS_REGNO_P(REGNO)? \
436 (((MODE) == SImode || ((enum machine_mode) (MODE) == Pmode)) \
437 && (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1))) : \
438 0)
439
440 #define MODES_TIEABLE_P(MODE1, MODE2) \
441 (((MODE1) == SFmode || (MODE1) == DFmode) \
442 == ((MODE2) == SFmode || (MODE2) == DFmode))
443
444 /* Maximum number of registers to represent a value of mode MODE
445 in a register of class CLASS. */
446 #define CLASS_MAX_NREGS(CLASS, MODE) \
447 ((CLASS) == FP_REGS ? \
448 (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
449 (CLASS) == ACCESS_REGS ? \
450 (GET_MODE_SIZE (MODE) + 4 - 1) / 4 : \
451 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
452
453 /* If a 4-byte value is loaded into a FPR, it is placed into the
454 *upper* half of the register, not the lower. Therefore, we
455 cannot use SUBREGs to switch between modes in FP registers.
456 Likewise for access registers, since they have only half the
457 word size on 64-bit. */
458 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
459 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
460 ? reg_classes_intersect_p (FP_REGS, CLASS) \
461 || reg_classes_intersect_p (ACCESS_REGS, CLASS) : 0)
462
463 /* Register classes. */
464
465 /* We use the following register classes:
466 GENERAL_REGS All general purpose registers
467 ADDR_REGS All general purpose registers except %r0
468 (These registers can be used in address generation)
469 FP_REGS All floating point registers
470 CC_REGS The condition code register
471 ACCESS_REGS The access registers
472
473 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
474 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
475 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS
476 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS
477
478 NO_REGS No registers
479 ALL_REGS All registers
480
481 Note that the 'fake' frame pointer and argument pointer registers
482 are included amongst the address registers here. */
483
484 enum reg_class
485 {
486 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
487 ADDR_CC_REGS, GENERAL_CC_REGS,
488 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
489 ALL_REGS, LIM_REG_CLASSES
490 };
491 #define N_REG_CLASSES (int) LIM_REG_CLASSES
492
493 #define REG_CLASS_NAMES \
494 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \
495 "ADDR_CC_REGS", "GENERAL_CC_REGS", \
496 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
497
498 /* Class -> register mapping. */
499 #define REG_CLASS_CONTENTS \
500 { \
501 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
502 { 0x00000000, 0x00000002 }, /* CC_REGS */ \
503 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \
504 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \
505 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \
506 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \
507 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \
508 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
509 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \
510 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \
511 { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \
512 }
513
514 /* Register -> class mapping. */
515 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
516 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
517
518 /* ADDR_REGS can be used as base or index register. */
519 #define INDEX_REG_CLASS ADDR_REGS
520 #define BASE_REG_CLASS ADDR_REGS
521
522 /* Check whether REGNO is a hard register of the suitable class
523 or a pseudo register currently allocated to one such. */
524 #define REGNO_OK_FOR_INDEX_P(REGNO) \
525 (((REGNO) < FIRST_PSEUDO_REGISTER \
526 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
527 || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
528 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
529
530
531 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
532 return the class of reg to actually use. */
533 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
534 s390_preferred_reload_class ((X), (CLASS))
535
536 /* We need a secondary reload when loading a PLUS which is
537 not a valid operand for LOAD ADDRESS. */
538 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
539 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
540
541 /* We need a secondary reload when storing a double-word
542 to a non-offsettable memory address. */
543 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
544 s390_secondary_output_reload_class ((CLASS), (MODE), (OUT))
545
546 /* We need secondary memory to move data between GPRs and FPRs. */
547 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
548 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
549
550 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
551 because the movsi and movsf patterns don't handle r/f moves. */
552 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
553 (GET_MODE_BITSIZE (MODE) < 32 \
554 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
555 : MODE)
556
557
558 /* Define various machine-dependent constraint letters. */
559
560 #define REG_CLASS_FROM_LETTER(C) \
561 ((C) == 'a' ? ADDR_REGS : \
562 (C) == 'd' ? GENERAL_REGS : \
563 (C) == 'f' ? FP_REGS : \
564 (C) == 'c' ? CC_REGS : \
565 (C) == 't' ? ACCESS_REGS : NO_REGS)
566
567 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
568 s390_const_ok_for_constraint_p ((VALUE), (C), (STR))
569
570 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE, C, STR) 1
571
572 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
573 s390_extra_constraint_str ((OP), (C), (STR))
574 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
575 ((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T' || (C) == 'A')
576 #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
577 ((C) == 'U' || (C) == 'W' || (C) == 'Y')
578
579 #define CONSTRAINT_LEN(C, STR) \
580 ((C) == 'N' ? 5 : \
581 (C) == 'A' ? 2 : \
582 (C) == 'B' ? 2 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
583
584 /* Stack layout and calling conventions. */
585
586 /* Our stack grows from higher to lower addresses. However, local variables
587 are accessed by positive offsets, and function arguments are stored at
588 increasing addresses. */
589 #define STACK_GROWS_DOWNWARD
590 /* #undef FRAME_GROWS_DOWNWARD */
591 /* #undef ARGS_GROW_DOWNWARD */
592
593 /* The basic stack layout looks like this: the stack pointer points
594 to the register save area for called functions. Above that area
595 is the location to place outgoing arguments. Above those follow
596 dynamic allocations (alloca), and finally the local variables. */
597
598 /* Offset from stack-pointer to first location of outgoing args. */
599 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
600
601 /* Offset within stack frame to start allocating local variables at. */
602 extern int current_function_outgoing_args_size;
603 #define STARTING_FRAME_OFFSET \
604 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
605
606 /* Offset from the stack pointer register to an item dynamically
607 allocated on the stack, e.g., by `alloca'. */
608 #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET)
609
610 /* Offset of first parameter from the argument pointer register value.
611 We have a fake argument pointer register that points directly to
612 the argument area. */
613 #define FIRST_PARM_OFFSET(FNDECL) 0
614
615 /* Defining this macro makes __builtin_frame_address(0) and
616 __builtin_return_address(0) work with -fomit-frame-pointer. */
617 #define INITIAL_FRAME_ADDRESS_RTX \
618 (TARGET_PACKED_STACK ? \
619 plus_constant (arg_pointer_rtx, -UNITS_PER_WORD) : \
620 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
621
622 /* The return address of the current frame is retrieved
623 from the initial value of register RETURN_REGNUM.
624 For frames farther back, we use the stack slot where
625 the corresponding RETURN_REGNUM register was saved. */
626 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
627 (TARGET_PACKED_STACK ? \
628 plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME))
629
630 #define RETURN_ADDR_RTX(COUNT, FRAME) \
631 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
632
633 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
634 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
635
636
637 /* Exception handling. */
638
639 /* Describe calling conventions for DWARF-2 exception handling. */
640 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
641 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
642 #define DWARF_FRAME_RETURN_COLUMN 14
643
644 /* Describe how we implement __builtin_eh_return. */
645 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
646 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
647
648 /* Select a format to encode pointers in exception handling data. */
649 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
650 (flag_pic \
651 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
652 : DW_EH_PE_absptr)
653
654
655 /* Frame registers. */
656
657 #define STACK_POINTER_REGNUM 15
658 #define FRAME_POINTER_REGNUM 34
659 #define HARD_FRAME_POINTER_REGNUM 11
660 #define ARG_POINTER_REGNUM 32
661 #define RETURN_ADDRESS_POINTER_REGNUM 35
662
663 /* The static chain must be call-clobbered, but not used for
664 function argument passing. As register 1 is clobbered by
665 the trampoline code, we only have one option. */
666 #define STATIC_CHAIN_REGNUM 0
667
668 /* Number of hardware registers that go into the DWARF-2 unwind info.
669 To avoid ABI incompatibility, this number must not change even as
670 'fake' hard registers are added or removed. */
671 #define DWARF_FRAME_REGISTERS 34
672
673
674 /* Frame pointer and argument pointer elimination. */
675
676 #define FRAME_POINTER_REQUIRED 0
677
678 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
679
680 #define ELIMINABLE_REGS \
681 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
682 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
683 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
684 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
685 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
686 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
687
688 #define CAN_ELIMINATE(FROM, TO) \
689 s390_can_eliminate ((FROM), (TO))
690
691 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
692 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
693
694
695 /* Stack arguments. */
696
697 /* We need current_function_outgoing_args to be valid. */
698 #define ACCUMULATE_OUTGOING_ARGS 1
699
700 /* Return doesn't modify the stack. */
701 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
702
703
704 /* Register arguments. */
705
706 typedef struct s390_arg_structure
707 {
708 int gprs; /* gpr so far */
709 int fprs; /* fpr so far */
710 }
711 CUMULATIVE_ARGS;
712
713 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
714 ((CUM).gprs=0, (CUM).fprs=0)
715
716 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
717 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
718
719 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
720 s390_function_arg (&CUM, MODE, TYPE, NAMED)
721
722 /* Arguments can be placed in general registers 2 to 6,
723 or in floating point registers 0 and 2. */
724 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
725 (N) == 16 || (N) == 17)
726
727
728 /* Scalar return values. */
729
730 #define FUNCTION_VALUE(VALTYPE, FUNC) \
731 s390_function_value ((VALTYPE), VOIDmode)
732
733 #define LIBCALL_VALUE(MODE) \
734 s390_function_value (NULL, (MODE))
735
736 /* Only gpr 2 and fpr 0 are ever used as return registers. */
737 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
738
739
740 /* Function entry and exit. */
741
742 /* When returning from a function, the stack pointer does not matter. */
743 #define EXIT_IGNORE_STACK 1
744
745
746 /* Profiling. */
747
748 #define FUNCTION_PROFILER(FILE, LABELNO) \
749 s390_function_profiler ((FILE), ((LABELNO)))
750
751 #define PROFILE_BEFORE_PROLOGUE 1
752
753
754 /* Implementing the varargs macros. */
755
756 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
757 s390_va_start (valist, nextarg)
758
759 /* Trampolines for nested functions. */
760
761 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16)
762
763 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
764 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
765
766 #define TRAMPOLINE_TEMPLATE(FILE) \
767 s390_trampoline_template (FILE)
768
769
770 /* Addressing modes, and classification of registers for them. */
771
772 /* Recognize any constant value that is a valid address. */
773 #define CONSTANT_ADDRESS_P(X) 0
774
775 /* Maximum number of registers that can appear in a valid memory address. */
776 #define MAX_REGS_PER_ADDRESS 2
777
778 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
779 its validity for a certain class. We have two alternate definitions
780 for each of them. The usual definition accepts all pseudo regs; the
781 other rejects them all. The symbol REG_OK_STRICT causes the latter
782 definition to be used.
783
784 Most source files want to accept pseudo regs in the hope that they will
785 get allocated to the class that the insn wants them to be in.
786 Some source files that are used after register allocation
787 need to be strict. */
788
789 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
790 ((GET_MODE (X) == Pmode) && \
791 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
792 || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
793
794 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
795
796 #define REG_OK_FOR_INDEX_STRICT_P(X) \
797 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X))))
798
799 #define REG_OK_FOR_BASE_STRICT_P(X) \
800 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X))))
801
802 #ifndef REG_OK_STRICT
803 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
804 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
805 #else
806 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
807 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
808 #endif
809
810 /* S/390 has no mode dependent addresses. */
811 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
812
813 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
814 valid memory address for an instruction.
815 The MODE argument is the machine mode for the MEM expression
816 that wants to use this address. */
817 #ifdef REG_OK_STRICT
818 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
819 { \
820 if (legitimate_address_p (MODE, X, 1)) \
821 goto ADDR; \
822 }
823 #else
824 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
825 { \
826 if (legitimate_address_p (MODE, X, 0)) \
827 goto ADDR; \
828 }
829 #endif
830
831 /* Try machine-dependent ways of modifying an illegitimate address
832 to be legitimate. If we find one, return the new, valid address.
833 This macro is used in only one place: `memory_address' in explow.c. */
834 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
835 { \
836 (X) = legitimize_address (X, OLDX, MODE); \
837 if (memory_address_p (MODE, X)) \
838 goto WIN; \
839 }
840
841 /* Try a machine-dependent way of reloading an illegitimate address
842 operand. If we find one, push the reload and jump to WIN. This
843 macro is used in only one place: `find_reloads_address' in reload.c. */
844 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
845 do { \
846 rtx new = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \
847 if (new) \
848 { \
849 (AD) = new; \
850 goto WIN; \
851 } \
852 } while (0)
853
854 /* Nonzero if the constant value X is a legitimate general operand.
855 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
856 #define LEGITIMATE_CONSTANT_P(X) \
857 legitimate_constant_p (X)
858
859 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
860 #define SYMBOLIC_CONST(X) \
861 (GET_CODE (X) == SYMBOL_REF \
862 || GET_CODE (X) == LABEL_REF \
863 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
864
865 #define TLS_SYMBOLIC_CONST(X) \
866 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
867 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
868
869
870 /* Condition codes. */
871
872 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
873 return the mode to be used for the comparison. */
874 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
875
876 /* Canonicalize a comparison from one we don't have to one we do have. */
877 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
878 s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
879
880 /* Define the information needed to generate branch and scc insns. This is
881 stored from the compare operation. Note that we can't use "rtx" here
882 since it hasn't been defined! */
883 extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
884
885
886 /* Relative costs of operations. */
887
888 /* On s390, copy between fprs and gprs is expensive. */
889 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
890 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
891 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
892 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
893 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
894
895 /* A C expression for the cost of moving data of mode M between a
896 register and memory. A value of 2 is the default; this cost is
897 relative to those in `REGISTER_MOVE_COST'. */
898 #define MEMORY_MOVE_COST(M, C, I) 1
899
900 /* A C expression for the cost of a branch instruction. A value of 1
901 is the default; other values are interpreted relative to that. */
902 #define BRANCH_COST 1
903
904 /* Nonzero if access to memory by bytes is slow and undesirable. */
905 #define SLOW_BYTE_ACCESS 1
906
907 /* An integer expression for the size in bits of the largest integer machine
908 mode that should actually be used. We allow pairs of registers. */
909 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
910
911 /* The maximum number of bytes that a single instruction can move quickly
912 between memory and registers or between two memory locations. */
913 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
914 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
915 #define MAX_MOVE_MAX 16
916
917 /* Determine whether to use move_by_pieces or block move insn. */
918 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
919 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
920 || (TARGET_64BIT && (SIZE) == 8) )
921
922 /* Determine whether to use clear_by_pieces or block clear insn. */
923 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
924 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
925 || (TARGET_64BIT && (SIZE) == 8) )
926
927 /* This macro is used to determine whether store_by_pieces should be
928 called to "memset" storage with byte values other than zero, or
929 to "memcpy" storage when the source is a constant string. */
930 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
931
932 /* Don't perform CSE on function addresses. */
933 #define NO_FUNCTION_CSE
934
935
936 /* Sections. */
937
938 /* Output before read-only data. */
939 #define TEXT_SECTION_ASM_OP ".text"
940
941 /* Output before writable (initialized) data. */
942 #define DATA_SECTION_ASM_OP ".data"
943
944 /* Output before writable (uninitialized) data. */
945 #define BSS_SECTION_ASM_OP ".bss"
946
947 /* S/390 constant pool breaks the devices in crtstuff.c to control section
948 in where code resides. We have to write it as asm code. */
949 #ifndef __s390x__
950 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
951 asm (SECTION_OP "\n\
952 bras\t%r2,1f\n\
953 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
954 1: l\t%r3,0(%r2)\n\
955 bas\t%r14,0(%r3,%r2)\n\
956 .previous");
957 #endif
958
959
960 /* Position independent code. */
961
962 extern int flag_pic;
963
964 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
965
966 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
967
968
969 /* Assembler file format. */
970
971 /* Character to start a comment. */
972 #define ASM_COMMENT_START "#"
973
974 /* Declare an uninitialized external linkage data object. */
975 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
976 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
977
978 /* Globalizing directive for a label. */
979 #define GLOBAL_ASM_OP ".globl "
980
981 /* Advance the location counter to a multiple of 2**LOG bytes. */
982 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
983 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
984
985 /* Advance the location counter by SIZE bytes. */
986 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
987 fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
988
989 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
990 #define LOCAL_LABEL_PREFIX "."
991
992 /* How to refer to registers in assembler output. This sequence is
993 indexed by compiler's hard-register-number (see above). */
994 #define REGISTER_NAMES \
995 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
996 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
997 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
998 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
999 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \
1000 }
1001
1002 /* Emit a dtp-relative reference to a TLS variable. */
1003
1004 #ifdef HAVE_AS_TLS
1005 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
1006 s390_output_dwarf_dtprel (FILE, SIZE, X)
1007 #endif
1008
1009 /* Print operand X (an rtx) in assembler syntax to file FILE. */
1010 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1011 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1012
1013 /* Output machine-dependent UNSPECs in address constants. */
1014 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
1015 do { \
1016 if (!s390_output_addr_const_extra (FILE, (X))) \
1017 goto FAIL; \
1018 } while (0);
1019
1020 /* Output an element of a case-vector that is absolute. */
1021 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1022 do { \
1023 char buf[32]; \
1024 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
1025 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
1026 assemble_name ((FILE), buf); \
1027 fputc ('\n', (FILE)); \
1028 } while (0)
1029
1030 /* Output an element of a case-vector that is relative. */
1031 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1032 do { \
1033 char buf[32]; \
1034 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
1035 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
1036 assemble_name ((FILE), buf); \
1037 fputc ('-', (FILE)); \
1038 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
1039 assemble_name ((FILE), buf); \
1040 fputc ('\n', (FILE)); \
1041 } while (0)
1042
1043
1044 /* Miscellaneous parameters. */
1045
1046 /* Define the codes that are matched by predicates in aux-output.c. */
1047 #define PREDICATE_CODES \
1048 {"s_operand", { SUBREG, MEM }}, \
1049 {"shift_count_operand", { REG, SUBREG, PLUS, CONST_INT }}, \
1050 {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
1051 {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
1052 {"load_multiple_operation", {PARALLEL}}, \
1053 {"store_multiple_operation", {PARALLEL}}, \
1054 {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
1055 {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
1056 CONST_INT, CONST_DOUBLE }}, \
1057 {"s390_plus_operand", { PLUS }}, \
1058 {"s390_comparison", { EQ, NE, LT, GT, LE, GE, LTU, GTU, LEU, GEU, \
1059 UNEQ, UNLT, UNGT, UNLE, UNGE, LTGT, \
1060 UNORDERED, ORDERED }}, \
1061 {"s390_alc_comparison", { ZERO_EXTEND, SIGN_EXTEND, \
1062 LTU, GTU, LEU, GEU }}, \
1063 {"s390_slb_comparison", { ZERO_EXTEND, SIGN_EXTEND, \
1064 LTU, GTU, LEU, GEU }},
1065
1066 /* Specify the machine mode that this machine uses for the index in the
1067 tablejump instruction. */
1068 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
1069
1070 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1071 is done just by pretending it is already truncated. */
1072 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1073
1074 /* Specify the machine mode that pointers have.
1075 After generation of rtl, the compiler makes no further distinction
1076 between pointers and any other objects of this machine mode. */
1077 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
1078
1079 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */
1080 #define POINTERS_EXTEND_UNSIGNED -1
1081
1082 /* A function address in a call instruction is a byte address (for
1083 indexing purposes) so give the MEM rtx a byte's mode. */
1084 #define FUNCTION_MODE QImode
1085
1086 #endif
Mirror of the offical gcc git repository hosted at gcc.gnu.org