1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack
{
75 int first_gp_reg_save
; /* first callee saved GP register used */
76 int first_fp_reg_save
; /* first callee saved FP register used */
77 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
78 int lr_save_p
; /* true if the link reg needs to be saved */
79 int cr_save_p
; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask
; /* mask of vec registers to save */
81 int toc_save_p
; /* true if the TOC needs to be saved */
82 int push_p
; /* true if we need to allocate stack space */
83 int calls_p
; /* true if the function makes any calls */
84 int world_save_p
; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi
; /* which ABI to use */
87 int gp_save_offset
; /* offset to save GP regs from initial SP */
88 int fp_save_offset
; /* offset to save FP regs from initial SP */
89 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset
; /* offset to save LR from initial SP */
91 int cr_save_offset
; /* offset to save CR from initial SP */
92 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
94 int toc_save_offset
; /* offset to save the TOC pointer */
95 int varargs_save_offset
; /* offset to save the varargs registers */
96 int ehrd_offset
; /* offset to EH return data */
97 int reg_size
; /* register size (4 or 8) */
98 int varargs_size
; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size
; /* variable save area size */
100 int parm_size
; /* outgoing parameter size */
101 int save_size
; /* save area size */
102 int fixed_size
; /* fixed size of stack frame */
103 int gp_size
; /* size of saved GP registers */
104 int fp_size
; /* size of saved FP registers */
105 int altivec_size
; /* size of saved AltiVec registers */
106 int cr_size
; /* size to hold CR if not in save_size */
107 int lr_size
; /* size to hold LR if not in save_size */
108 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size
; /* size of altivec alignment padding if
111 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size
;
113 int toc_size
; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
115 int spe_64bit_regs_used
;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu
;
121 struct rs6000_cpu_select rs6000_select
[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint
;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups
;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str
;
138 int rs6000_sched_restricted_insns_priority
;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str
;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str
;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load
;
151 /* Size of long double */
152 const char *rs6000_long_double_size_string
;
153 int rs6000_long_double_type_size
;
155 /* Whether -mabi=altivec has appeared */
156 int rs6000_altivec_abi
;
158 /* Whether VRSAVE instructions should be generated. */
159 int rs6000_altivec_vrsave
;
161 /* String from -mvrsave= option. */
162 const char *rs6000_altivec_vrsave_string
;
164 /* Nonzero if we want SPE ABI extensions. */
167 /* Whether isel instructions should be generated. */
170 /* Whether SPE simd instructions should be generated. */
173 /* Nonzero if floating point operations are done in the GPRs. */
174 int rs6000_float_gprs
= 0;
176 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
177 int rs6000_darwin64_abi
;
179 /* String from -mfloat-gprs=. */
180 const char *rs6000_float_gprs_string
;
182 /* String from -misel=. */
183 const char *rs6000_isel_string
;
185 /* String from -mspe=. */
186 const char *rs6000_spe_string
;
188 /* Set to nonzero once AIX common-mode calls have been defined. */
189 static GTY(()) int common_mode_defined
;
191 /* Save information from a "cmpxx" operation until the branch or scc is
193 rtx rs6000_compare_op0
, rs6000_compare_op1
;
194 int rs6000_compare_fp_p
;
196 /* Label number of label created for -mrelocatable, to call to so we can
197 get the address of the GOT section */
198 int rs6000_pic_labelno
;
201 /* Which abi to adhere to */
202 const char *rs6000_abi_name
;
204 /* Semantics of the small data area */
205 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
207 /* Which small data model to use */
208 const char *rs6000_sdata_name
= (char *)0;
210 /* Counter for labels which are to be placed in .fixup. */
211 int fixuplabelno
= 0;
214 /* Bit size of immediate TLS offsets and string from which it is decoded. */
215 int rs6000_tls_size
= 32;
216 const char *rs6000_tls_size_string
;
218 /* ABI enumeration available for subtarget to use. */
219 enum rs6000_abi rs6000_current_abi
;
221 /* ABI string from -mabi= option. */
222 const char *rs6000_abi_string
;
224 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
228 const char *rs6000_debug_name
;
229 int rs6000_debug_stack
; /* debug stack applications */
230 int rs6000_debug_arg
; /* debug argument handling */
232 /* Value is TRUE if register/mode pair is accepatable. */
233 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
236 static GTY(()) tree opaque_V2SI_type_node
;
237 static GTY(()) tree opaque_V2SF_type_node
;
238 static GTY(()) tree opaque_p_V2SI_type_node
;
239 static GTY(()) tree V16QI_type_node
;
240 static GTY(()) tree V2SI_type_node
;
241 static GTY(()) tree V2SF_type_node
;
242 static GTY(()) tree V4HI_type_node
;
243 static GTY(()) tree V4SI_type_node
;
244 static GTY(()) tree V4SF_type_node
;
245 static GTY(()) tree V8HI_type_node
;
246 static GTY(()) tree unsigned_V16QI_type_node
;
247 static GTY(()) tree unsigned_V8HI_type_node
;
248 static GTY(()) tree unsigned_V4SI_type_node
;
249 static GTY(()) tree bool_char_type_node
; /* __bool char */
250 static GTY(()) tree bool_short_type_node
; /* __bool short */
251 static GTY(()) tree bool_int_type_node
; /* __bool int */
252 static GTY(()) tree pixel_type_node
; /* __pixel */
253 static GTY(()) tree bool_V16QI_type_node
; /* __vector __bool char */
254 static GTY(()) tree bool_V8HI_type_node
; /* __vector __bool short */
255 static GTY(()) tree bool_V4SI_type_node
; /* __vector __bool int */
256 static GTY(()) tree pixel_V8HI_type_node
; /* __vector __pixel */
258 int rs6000_warn_altivec_long
= 1; /* On by default. */
259 const char *rs6000_warn_altivec_long_switch
;
261 const char *rs6000_traceback_name
;
263 traceback_default
= 0,
269 /* Flag to say the TOC is initialized */
271 char toc_label_name
[10];
273 /* Alias set for saves and restores from the rs6000 stack. */
274 static GTY(()) int rs6000_sr_alias_set
;
276 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
277 The only place that looks at this is rs6000_set_default_type_attributes;
278 everywhere else should rely on the presence or absence of a longcall
279 attribute on the function declaration. Exception: init_cumulative_args
280 looks at it too, for libcalls. */
281 int rs6000_default_long_calls
;
282 const char *rs6000_longcall_switch
;
284 /* Control alignment for fields within structures. */
285 /* String from -malign-XXXXX. */
286 const char *rs6000_alignment_string
;
287 int rs6000_alignment_flags
;
289 struct builtin_description
291 /* mask is not const because we're going to alter it below. This
292 nonsense will go away when we rewrite the -march infrastructure
293 to give us more target flag bits. */
295 const enum insn_code icode
;
296 const char *const name
;
297 const enum rs6000_builtins code
;
300 /* Target cpu costs. */
302 struct processor_costs
{
303 const int mulsi
; /* cost of SImode multiplication. */
304 const int mulsi_const
; /* cost of SImode multiplication by constant. */
305 const int mulsi_const9
; /* cost of SImode mult by short constant. */
306 const int muldi
; /* cost of DImode multiplication. */
307 const int divsi
; /* cost of SImode division. */
308 const int divdi
; /* cost of DImode division. */
309 const int fp
; /* cost of simple SFmode and DFmode insns. */
310 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
311 const int sdiv
; /* cost of SFmode division (fdivs). */
312 const int ddiv
; /* cost of DFmode division (fdiv). */
315 const struct processor_costs
*rs6000_cost
;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost
= {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
334 /* Instruction size costs on 64bit processors. */
336 struct processor_costs size64_cost
= {
337 COSTS_N_INSNS (1), /* mulsi */
338 COSTS_N_INSNS (1), /* mulsi_const */
339 COSTS_N_INSNS (1), /* mulsi_const9 */
340 COSTS_N_INSNS (1), /* muldi */
341 COSTS_N_INSNS (1), /* divsi */
342 COSTS_N_INSNS (1), /* divdi */
343 COSTS_N_INSNS (1), /* fp */
344 COSTS_N_INSNS (1), /* dmul */
345 COSTS_N_INSNS (1), /* sdiv */
346 COSTS_N_INSNS (1), /* ddiv */
349 /* Instruction costs on RIOS1 processors. */
351 struct processor_costs rios1_cost
= {
352 COSTS_N_INSNS (5), /* mulsi */
353 COSTS_N_INSNS (4), /* mulsi_const */
354 COSTS_N_INSNS (3), /* mulsi_const9 */
355 COSTS_N_INSNS (5), /* muldi */
356 COSTS_N_INSNS (19), /* divsi */
357 COSTS_N_INSNS (19), /* divdi */
358 COSTS_N_INSNS (2), /* fp */
359 COSTS_N_INSNS (2), /* dmul */
360 COSTS_N_INSNS (19), /* sdiv */
361 COSTS_N_INSNS (19), /* ddiv */
364 /* Instruction costs on RIOS2 processors. */
366 struct processor_costs rios2_cost
= {
367 COSTS_N_INSNS (2), /* mulsi */
368 COSTS_N_INSNS (2), /* mulsi_const */
369 COSTS_N_INSNS (2), /* mulsi_const9 */
370 COSTS_N_INSNS (2), /* muldi */
371 COSTS_N_INSNS (13), /* divsi */
372 COSTS_N_INSNS (13), /* divdi */
373 COSTS_N_INSNS (2), /* fp */
374 COSTS_N_INSNS (2), /* dmul */
375 COSTS_N_INSNS (17), /* sdiv */
376 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost
= {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
394 /* Instruction costs on MPCCORE processors. */
396 struct processor_costs mpccore_cost
= {
397 COSTS_N_INSNS (2), /* mulsi */
398 COSTS_N_INSNS (2), /* mulsi_const */
399 COSTS_N_INSNS (2), /* mulsi_const9 */
400 COSTS_N_INSNS (2), /* muldi */
401 COSTS_N_INSNS (6), /* divsi */
402 COSTS_N_INSNS (6), /* divdi */
403 COSTS_N_INSNS (4), /* fp */
404 COSTS_N_INSNS (5), /* dmul */
405 COSTS_N_INSNS (10), /* sdiv */
406 COSTS_N_INSNS (17), /* ddiv */
409 /* Instruction costs on PPC403 processors. */
411 struct processor_costs ppc403_cost
= {
412 COSTS_N_INSNS (4), /* mulsi */
413 COSTS_N_INSNS (4), /* mulsi_const */
414 COSTS_N_INSNS (4), /* mulsi_const9 */
415 COSTS_N_INSNS (4), /* muldi */
416 COSTS_N_INSNS (33), /* divsi */
417 COSTS_N_INSNS (33), /* divdi */
418 COSTS_N_INSNS (11), /* fp */
419 COSTS_N_INSNS (11), /* dmul */
420 COSTS_N_INSNS (11), /* sdiv */
421 COSTS_N_INSNS (11), /* ddiv */
424 /* Instruction costs on PPC405 processors. */
426 struct processor_costs ppc405_cost
= {
427 COSTS_N_INSNS (5), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (3), /* mulsi_const9 */
430 COSTS_N_INSNS (5), /* muldi */
431 COSTS_N_INSNS (35), /* divsi */
432 COSTS_N_INSNS (35), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
439 /* Instruction costs on PPC440 processors. */
441 struct processor_costs ppc440_cost
= {
442 COSTS_N_INSNS (3), /* mulsi */
443 COSTS_N_INSNS (2), /* mulsi_const */
444 COSTS_N_INSNS (2), /* mulsi_const9 */
445 COSTS_N_INSNS (3), /* muldi */
446 COSTS_N_INSNS (34), /* divsi */
447 COSTS_N_INSNS (34), /* divdi */
448 COSTS_N_INSNS (5), /* fp */
449 COSTS_N_INSNS (5), /* dmul */
450 COSTS_N_INSNS (19), /* sdiv */
451 COSTS_N_INSNS (33), /* ddiv */
454 /* Instruction costs on PPC601 processors. */
456 struct processor_costs ppc601_cost
= {
457 COSTS_N_INSNS (5), /* mulsi */
458 COSTS_N_INSNS (5), /* mulsi_const */
459 COSTS_N_INSNS (5), /* mulsi_const9 */
460 COSTS_N_INSNS (5), /* muldi */
461 COSTS_N_INSNS (36), /* divsi */
462 COSTS_N_INSNS (36), /* divdi */
463 COSTS_N_INSNS (4), /* fp */
464 COSTS_N_INSNS (5), /* dmul */
465 COSTS_N_INSNS (17), /* sdiv */
466 COSTS_N_INSNS (31), /* ddiv */
469 /* Instruction costs on PPC603 processors. */
471 struct processor_costs ppc603_cost
= {
472 COSTS_N_INSNS (5), /* mulsi */
473 COSTS_N_INSNS (3), /* mulsi_const */
474 COSTS_N_INSNS (2), /* mulsi_const9 */
475 COSTS_N_INSNS (5), /* muldi */
476 COSTS_N_INSNS (37), /* divsi */
477 COSTS_N_INSNS (37), /* divdi */
478 COSTS_N_INSNS (3), /* fp */
479 COSTS_N_INSNS (4), /* dmul */
480 COSTS_N_INSNS (18), /* sdiv */
481 COSTS_N_INSNS (33), /* ddiv */
484 /* Instruction costs on PPC604 processors. */
486 struct processor_costs ppc604_cost
= {
487 COSTS_N_INSNS (4), /* mulsi */
488 COSTS_N_INSNS (4), /* mulsi_const */
489 COSTS_N_INSNS (4), /* mulsi_const9 */
490 COSTS_N_INSNS (4), /* muldi */
491 COSTS_N_INSNS (20), /* divsi */
492 COSTS_N_INSNS (20), /* divdi */
493 COSTS_N_INSNS (3), /* fp */
494 COSTS_N_INSNS (3), /* dmul */
495 COSTS_N_INSNS (18), /* sdiv */
496 COSTS_N_INSNS (32), /* ddiv */
499 /* Instruction costs on PPC604e processors. */
501 struct processor_costs ppc604e_cost
= {
502 COSTS_N_INSNS (2), /* mulsi */
503 COSTS_N_INSNS (2), /* mulsi_const */
504 COSTS_N_INSNS (2), /* mulsi_const9 */
505 COSTS_N_INSNS (2), /* muldi */
506 COSTS_N_INSNS (20), /* divsi */
507 COSTS_N_INSNS (20), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (3), /* dmul */
510 COSTS_N_INSNS (18), /* sdiv */
511 COSTS_N_INSNS (32), /* ddiv */
514 /* Instruction costs on PPC620 processors. */
516 struct processor_costs ppc620_cost
= {
517 COSTS_N_INSNS (5), /* mulsi */
518 COSTS_N_INSNS (4), /* mulsi_const */
519 COSTS_N_INSNS (3), /* mulsi_const9 */
520 COSTS_N_INSNS (7), /* muldi */
521 COSTS_N_INSNS (21), /* divsi */
522 COSTS_N_INSNS (37), /* divdi */
523 COSTS_N_INSNS (3), /* fp */
524 COSTS_N_INSNS (3), /* dmul */
525 COSTS_N_INSNS (18), /* sdiv */
526 COSTS_N_INSNS (32), /* ddiv */
529 /* Instruction costs on PPC630 processors. */
531 struct processor_costs ppc630_cost
= {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (4), /* mulsi_const */
534 COSTS_N_INSNS (3), /* mulsi_const9 */
535 COSTS_N_INSNS (7), /* muldi */
536 COSTS_N_INSNS (21), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (17), /* sdiv */
541 COSTS_N_INSNS (21), /* ddiv */
544 /* Instruction costs on PPC750 and PPC7400 processors. */
546 struct processor_costs ppc750_cost
= {
547 COSTS_N_INSNS (5), /* mulsi */
548 COSTS_N_INSNS (3), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (5), /* muldi */
551 COSTS_N_INSNS (17), /* divsi */
552 COSTS_N_INSNS (17), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (17), /* sdiv */
556 COSTS_N_INSNS (31), /* ddiv */
559 /* Instruction costs on PPC7450 processors. */
561 struct processor_costs ppc7450_cost
= {
562 COSTS_N_INSNS (4), /* mulsi */
563 COSTS_N_INSNS (3), /* mulsi_const */
564 COSTS_N_INSNS (3), /* mulsi_const9 */
565 COSTS_N_INSNS (4), /* muldi */
566 COSTS_N_INSNS (23), /* divsi */
567 COSTS_N_INSNS (23), /* divdi */
568 COSTS_N_INSNS (5), /* fp */
569 COSTS_N_INSNS (5), /* dmul */
570 COSTS_N_INSNS (21), /* sdiv */
571 COSTS_N_INSNS (35), /* ddiv */
574 /* Instruction costs on PPC8540 processors. */
576 struct processor_costs ppc8540_cost
= {
577 COSTS_N_INSNS (4), /* mulsi */
578 COSTS_N_INSNS (4), /* mulsi_const */
579 COSTS_N_INSNS (4), /* mulsi_const9 */
580 COSTS_N_INSNS (4), /* muldi */
581 COSTS_N_INSNS (19), /* divsi */
582 COSTS_N_INSNS (19), /* divdi */
583 COSTS_N_INSNS (4), /* fp */
584 COSTS_N_INSNS (4), /* dmul */
585 COSTS_N_INSNS (29), /* sdiv */
586 COSTS_N_INSNS (29), /* ddiv */
589 /* Instruction costs on POWER4 and POWER5 processors. */
591 struct processor_costs power4_cost
= {
592 COSTS_N_INSNS (3), /* mulsi */
593 COSTS_N_INSNS (2), /* mulsi_const */
594 COSTS_N_INSNS (2), /* mulsi_const9 */
595 COSTS_N_INSNS (4), /* muldi */
596 COSTS_N_INSNS (18), /* divsi */
597 COSTS_N_INSNS (34), /* divdi */
598 COSTS_N_INSNS (3), /* fp */
599 COSTS_N_INSNS (3), /* dmul */
600 COSTS_N_INSNS (17), /* sdiv */
601 COSTS_N_INSNS (17), /* ddiv */
605 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
606 static int num_insns_constant_wide (HOST_WIDE_INT
);
607 static void validate_condition_mode (enum rtx_code
, enum machine_mode
);
608 static rtx
rs6000_generate_compare (enum rtx_code
);
609 static void rs6000_maybe_dead (rtx
);
610 static void rs6000_emit_stack_tie (void);
611 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
612 static rtx
spe_synthesize_frame_save (rtx
);
613 static bool spe_func_has_64bit_regs_p (void);
614 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
616 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
617 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
618 static unsigned rs6000_hash_constant (rtx
);
619 static unsigned toc_hash_function (const void *);
620 static int toc_hash_eq (const void *, const void *);
621 static int constant_pool_expr_1 (rtx
, int *, int *);
622 static bool constant_pool_expr_p (rtx
);
623 static bool toc_relative_expr_p (rtx
);
624 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
625 static bool legitimate_indexed_address_p (rtx
, int);
626 static bool legitimate_indirect_address_p (rtx
, int);
627 static bool macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
);
628 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
629 static struct machine_function
* rs6000_init_machine_status (void);
630 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
631 #ifdef HAVE_GAS_HIDDEN
632 static void rs6000_assemble_visibility (tree
, int);
634 static int rs6000_ra_ever_killed (void);
635 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
636 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
637 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
638 static const char *rs6000_mangle_fundamental_type (tree
);
639 extern const struct attribute_spec rs6000_attribute_table
[];
640 static void rs6000_set_default_type_attributes (tree
);
641 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
642 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
643 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
645 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
646 static bool rs6000_return_in_memory (tree
, tree
);
647 static void rs6000_file_start (void);
649 static unsigned int rs6000_elf_section_type_flags (tree
, const char *, int);
650 static void rs6000_elf_asm_out_constructor (rtx
, int);
651 static void rs6000_elf_asm_out_destructor (rtx
, int);
652 static void rs6000_elf_select_section (tree
, int, unsigned HOST_WIDE_INT
);
653 static void rs6000_elf_unique_section (tree
, int);
654 static void rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
655 unsigned HOST_WIDE_INT
);
656 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
658 static bool rs6000_elf_in_small_data_p (tree
);
661 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
662 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
663 static void rs6000_xcoff_select_section (tree
, int, unsigned HOST_WIDE_INT
);
664 static void rs6000_xcoff_unique_section (tree
, int);
665 static void rs6000_xcoff_select_rtx_section (enum machine_mode
, rtx
,
666 unsigned HOST_WIDE_INT
);
667 static const char * rs6000_xcoff_strip_name_encoding (const char *);
668 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
669 static void rs6000_xcoff_file_start (void);
670 static void rs6000_xcoff_file_end (void);
673 static bool rs6000_binds_local_p (tree
);
675 static int rs6000_variable_issue (FILE *, int, rtx
, int);
676 static bool rs6000_rtx_costs (rtx
, int, int, int *);
677 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
678 static bool is_microcoded_insn (rtx
);
679 static int is_dispatch_slot_restricted (rtx
);
680 static bool is_cracked_insn (rtx
);
681 static bool is_branch_slot_insn (rtx
);
682 static int rs6000_adjust_priority (rtx
, int);
683 static int rs6000_issue_rate (void);
684 static bool rs6000_is_costly_dependence (rtx
, rtx
, rtx
, int, int);
685 static rtx
get_next_active_insn (rtx
, rtx
);
686 static bool insn_terminates_group_p (rtx
, enum group_termination
);
687 static bool is_costly_group (rtx
*, rtx
);
688 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
689 static int redefine_groups (FILE *, int, rtx
, rtx
);
690 static int pad_groups (FILE *, int, rtx
, rtx
);
691 static void rs6000_sched_finish (FILE *, int);
692 static int rs6000_use_sched_lookahead (void);
693 static tree
rs6000_builtin_mask_for_load (void);
695 static void rs6000_init_builtins (void);
696 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
697 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
698 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
699 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
700 static void altivec_init_builtins (void);
701 static void rs6000_common_init_builtins (void);
702 static void rs6000_init_libfuncs (void);
704 static void enable_mask_for_builtins (struct builtin_description
*, int,
705 enum rs6000_builtins
,
706 enum rs6000_builtins
);
707 static tree
build_opaque_vector_type (tree
, int);
708 static void spe_init_builtins (void);
709 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
710 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
711 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
712 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
713 static bool invalid_e500_subreg (rtx
, enum machine_mode
);
714 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
715 static rs6000_stack_t
*rs6000_stack_info (void);
716 static void debug_stack_info (rs6000_stack_t
*);
718 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
719 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
720 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
721 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
722 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
723 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
724 const char *, tree
, rtx
);
725 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
726 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
727 static void rs6000_parse_abi_options (void);
728 static void rs6000_parse_alignment_option (void);
729 static void rs6000_parse_tls_size_option (void);
730 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
731 static void rs6000_parse_float_gprs_option (void);
732 static int first_altivec_reg_to_save (void);
733 static unsigned int compute_vrsave_mask (void);
734 static void compute_save_world_info(rs6000_stack_t
*info_ptr
);
735 static void is_altivec_return_reg (rtx
, void *);
736 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
737 int easy_vector_constant (rtx
, enum machine_mode
);
738 static int easy_vector_same (rtx
, enum machine_mode
);
739 static int easy_vector_splat_const (int, enum machine_mode
);
740 static bool is_ev64_opaque_type (tree
);
741 static rtx
rs6000_dwarf_register_span (rtx
);
742 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
743 static rtx
rs6000_tls_get_addr (void);
744 static rtx
rs6000_got_sym (void);
745 static inline int rs6000_tls_symbol_ref_1 (rtx
*, void *);
746 static const char *rs6000_get_some_local_dynamic_name (void);
747 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
748 static rtx
rs6000_complex_function_value (enum machine_mode
);
749 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
750 enum machine_mode
, tree
);
751 static rtx
rs6000_darwin64_function_arg (CUMULATIVE_ARGS
*,
752 enum machine_mode
, tree
, int);
753 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
754 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
755 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
756 enum machine_mode
, tree
,
758 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
760 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree
, tree
, int);
765 static int no_previous_def (tree function_name
);
766 static tree
get_prev_label (tree function_name
);
767 static void rs6000_darwin_file_start (void);
770 static tree
rs6000_build_builtin_va_list (void);
771 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
772 static bool rs6000_must_pass_in_stack (enum machine_mode
, tree
);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
774 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
776 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
778 static int get_vsel_insn (enum machine_mode
);
779 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
782 const int INSN_NOT_AVAILABLE
= -1;
783 static enum machine_mode
rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct
GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode
;
796 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
798 /* Default register names. */
799 char rs6000_reg_names
[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names
[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Return 1 for a symbol ref for a thread-local storage symbol. */
858 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
859 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
861 /* Initialize the GCC target structure. */
862 #undef TARGET_ATTRIBUTE_TABLE
863 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
864 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
865 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
867 #undef TARGET_ASM_ALIGNED_DI_OP
868 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
870 /* Default unaligned ops are only provided for ELF. Find the ops needed
871 for non-ELF systems. */
872 #ifndef OBJECT_FORMAT_ELF
874 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
876 #undef TARGET_ASM_UNALIGNED_HI_OP
877 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
878 #undef TARGET_ASM_UNALIGNED_SI_OP
879 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
880 #undef TARGET_ASM_UNALIGNED_DI_OP
881 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
884 #undef TARGET_ASM_UNALIGNED_HI_OP
885 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
886 #undef TARGET_ASM_UNALIGNED_SI_OP
887 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
888 #undef TARGET_ASM_UNALIGNED_DI_OP
889 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
890 #undef TARGET_ASM_ALIGNED_DI_OP
891 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
895 /* This hook deals with fixups for relocatable code and DI-mode objects
897 #undef TARGET_ASM_INTEGER
898 #define TARGET_ASM_INTEGER rs6000_assemble_integer
900 #ifdef HAVE_GAS_HIDDEN
901 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
902 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
905 #undef TARGET_HAVE_TLS
906 #define TARGET_HAVE_TLS HAVE_AS_TLS
908 #undef TARGET_CANNOT_FORCE_CONST_MEM
909 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
911 #undef TARGET_ASM_FUNCTION_PROLOGUE
912 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
913 #undef TARGET_ASM_FUNCTION_EPILOGUE
914 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
916 #undef TARGET_SCHED_VARIABLE_ISSUE
917 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
919 #undef TARGET_SCHED_ISSUE_RATE
920 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
921 #undef TARGET_SCHED_ADJUST_COST
922 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
923 #undef TARGET_SCHED_ADJUST_PRIORITY
924 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
925 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
926 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
927 #undef TARGET_SCHED_FINISH
928 #define TARGET_SCHED_FINISH rs6000_sched_finish
930 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
931 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
933 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
934 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
936 #undef TARGET_INIT_BUILTINS
937 #define TARGET_INIT_BUILTINS rs6000_init_builtins
939 #undef TARGET_EXPAND_BUILTIN
940 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
942 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
943 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
945 #undef TARGET_INIT_LIBFUNCS
946 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
949 #undef TARGET_BINDS_LOCAL_P
950 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
953 #undef TARGET_ASM_OUTPUT_MI_THUNK
954 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
956 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
957 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
959 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
960 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
962 #undef TARGET_RTX_COSTS
963 #define TARGET_RTX_COSTS rs6000_rtx_costs
964 #undef TARGET_ADDRESS_COST
965 #define TARGET_ADDRESS_COST hook_int_rtx_0
967 #undef TARGET_VECTOR_OPAQUE_P
968 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
970 #undef TARGET_DWARF_REGISTER_SPAN
971 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
973 /* On rs6000, function arguments are promoted, as are function return
975 #undef TARGET_PROMOTE_FUNCTION_ARGS
976 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
977 #undef TARGET_PROMOTE_FUNCTION_RETURN
978 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
980 #undef TARGET_RETURN_IN_MEMORY
981 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
983 #undef TARGET_SETUP_INCOMING_VARARGS
984 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
986 /* Always strict argument naming on rs6000. */
987 #undef TARGET_STRICT_ARGUMENT_NAMING
988 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
989 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
990 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
991 #undef TARGET_SPLIT_COMPLEX_ARG
992 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
993 #undef TARGET_MUST_PASS_IN_STACK
994 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
995 #undef TARGET_PASS_BY_REFERENCE
996 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
997 #undef TARGET_ARG_PARTIAL_BYTES
998 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1000 #undef TARGET_BUILD_BUILTIN_VA_LIST
1001 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1003 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1004 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1006 #undef TARGET_EH_RETURN_FILTER_MODE
1007 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1009 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1010 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1012 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1013 The PowerPC architecture requires only weak consistency among
1014 processors--that is, memory accesses between processors need not be
1015 sequentially consistent and memory accesses among processors can occur
1016 in any order. The ability to order memory accesses weakly provides
1017 opportunities for more efficient use of the system bus. Unless a
1018 dependency exists, the 604e allows read operations to precede store
1020 #undef TARGET_RELAXED_ORDERING
1021 #define TARGET_RELAXED_ORDERING true
1023 struct gcc_target targetm
= TARGET_INITIALIZER
;
1026 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1029 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1031 /* The GPRs can hold any mode, but values bigger than one register
1032 cannot go past R31. */
1033 if (INT_REGNO_P (regno
))
1034 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1036 /* The float registers can only hold floating modes and DImode. */
1037 if (FP_REGNO_P (regno
))
1039 (GET_MODE_CLASS (mode
) == MODE_FLOAT
1040 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1041 || (GET_MODE_CLASS (mode
) == MODE_INT
1042 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
);
1044 /* The CR register can only hold CC modes. */
1045 if (CR_REGNO_P (regno
))
1046 return GET_MODE_CLASS (mode
) == MODE_CC
;
1048 if (XER_REGNO_P (regno
))
1049 return mode
== PSImode
;
1051 /* AltiVec only in AldyVec registers. */
1052 if (ALTIVEC_REGNO_P (regno
))
1053 return ALTIVEC_VECTOR_MODE (mode
);
1055 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1056 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1059 /* We cannot put TImode anywhere except general register and it must be
1060 able to fit within the register set. */
1062 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1065 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1067 rs6000_init_hard_regno_mode_ok (void)
1071 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1072 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1073 if (rs6000_hard_regno_mode_ok (r
, m
))
1074 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1077 /* If not otherwise specified by a target, make 'long double' equivalent to
1080 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1081 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1084 /* Override command line options. Mostly we process the processor
1085 type and sometimes adjust other TARGET_ options. */
1088 rs6000_override_options (const char *default_cpu
)
1091 struct rs6000_cpu_select
*ptr
;
1094 /* Simplifications for entries below. */
1097 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1098 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1101 /* This table occasionally claims that a processor does not support
1102 a particular feature even though it does, but the feature is slower
1103 than the alternative. Thus, it shouldn't be relied on as a
1104 complete description of the processor's support.
1106 Please keep this list in order, and don't forget to update the
1107 documentation in invoke.texi when adding a new processor or
1111 const char *const name
; /* Canonical processor name. */
1112 const enum processor_type processor
; /* Processor type enum value. */
1113 const int target_enable
; /* Target flags to enable. */
1114 } const processor_target_table
[]
1115 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1116 {"403", PROCESSOR_PPC403
,
1117 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1118 {"405", PROCESSOR_PPC405
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1119 {"405fp", PROCESSOR_PPC405
, POWERPC_BASE_MASK
},
1120 {"440", PROCESSOR_PPC440
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1121 {"440fp", PROCESSOR_PPC440
, POWERPC_BASE_MASK
},
1122 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1123 {"601", PROCESSOR_PPC601
,
1124 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1125 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1126 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1127 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1128 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1129 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1130 {"620", PROCESSOR_PPC620
,
1131 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1132 {"630", PROCESSOR_PPC630
,
1133 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1134 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1135 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1136 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1137 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1138 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1139 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1140 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1141 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1142 /* 8548 has a dummy entry for now. */
1143 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1144 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1145 {"970", PROCESSOR_POWER4
,
1146 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1147 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1148 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1149 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1150 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1151 {"G5", PROCESSOR_POWER4
,
1152 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1153 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1154 {"power2", PROCESSOR_POWER
,
1155 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1156 {"power3", PROCESSOR_PPC630
,
1157 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1158 {"power4", PROCESSOR_POWER4
,
1159 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1160 {"power5", PROCESSOR_POWER5
,
1161 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1162 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1163 {"powerpc64", PROCESSOR_POWERPC64
,
1164 POWERPC_BASE_MASK
| MASK_POWERPC64
},
1165 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1166 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1167 {"rios2", PROCESSOR_RIOS2
,
1168 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1169 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1170 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1171 {"rs64a", PROCESSOR_RS64A
, POWERPC_BASE_MASK
| MASK_POWERPC64
},
1174 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1176 /* Some OSs don't support saving the high part of 64-bit registers on
1177 context switch. Other OSs don't support saving Altivec registers.
1178 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1179 settings; if the user wants either, the user must explicitly specify
1180 them and we won't interfere with the user's specification. */
1183 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1184 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
1185 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1189 rs6000_init_hard_regno_mode_ok ();
1191 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1192 #ifdef OS_MISSING_POWERPC64
1193 if (OS_MISSING_POWERPC64
)
1194 set_masks
&= ~MASK_POWERPC64
;
1196 #ifdef OS_MISSING_ALTIVEC
1197 if (OS_MISSING_ALTIVEC
)
1198 set_masks
&= ~MASK_ALTIVEC
;
1201 /* Don't override these by the processor default if given explicitly. */
1202 set_masks
&= ~(target_flags_explicit
1203 & (MASK_MULTIPLE
| MASK_STRING
| MASK_SOFT_FLOAT
));
1205 /* Identify the processor type. */
1206 rs6000_select
[0].string
= default_cpu
;
1207 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1209 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1211 ptr
= &rs6000_select
[i
];
1212 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1214 for (j
= 0; j
< ptt_size
; j
++)
1215 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1217 if (ptr
->set_tune_p
)
1218 rs6000_cpu
= processor_target_table
[j
].processor
;
1220 if (ptr
->set_arch_p
)
1222 target_flags
&= ~set_masks
;
1223 target_flags
|= (processor_target_table
[j
].target_enable
1230 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1237 /* If we are optimizing big endian systems for space, use the load/store
1238 multiple and string instructions. */
1239 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1240 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1242 /* Don't allow -mmultiple or -mstring on little endian systems
1243 unless the cpu is a 750, because the hardware doesn't support the
1244 instructions used in little endian mode, and causes an alignment
1245 trap. The 750 does not cause an alignment trap (except when the
1246 target is unaligned). */
1248 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1250 if (TARGET_MULTIPLE
)
1252 target_flags
&= ~MASK_MULTIPLE
;
1253 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1254 warning ("-mmultiple is not supported on little endian systems");
1259 target_flags
&= ~MASK_STRING
;
1260 if ((target_flags_explicit
& MASK_STRING
) != 0)
1261 warning ("-mstring is not supported on little endian systems");
1265 /* Set debug flags */
1266 if (rs6000_debug_name
)
1268 if (! strcmp (rs6000_debug_name
, "all"))
1269 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1270 else if (! strcmp (rs6000_debug_name
, "stack"))
1271 rs6000_debug_stack
= 1;
1272 else if (! strcmp (rs6000_debug_name
, "arg"))
1273 rs6000_debug_arg
= 1;
1275 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1278 if (rs6000_traceback_name
)
1280 if (! strncmp (rs6000_traceback_name
, "full", 4))
1281 rs6000_traceback
= traceback_full
;
1282 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1283 rs6000_traceback
= traceback_part
;
1284 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1285 rs6000_traceback
= traceback_none
;
1287 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1288 rs6000_traceback_name
);
1291 /* Set size of long double */
1292 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1293 if (rs6000_long_double_size_string
)
1296 int size
= strtol (rs6000_long_double_size_string
, &tail
, 10);
1297 if (*tail
!= '\0' || (size
!= 64 && size
!= 128))
1298 error ("Unknown switch -mlong-double-%s",
1299 rs6000_long_double_size_string
);
1301 rs6000_long_double_type_size
= size
;
1304 /* Set Altivec ABI as default for powerpc64 linux. */
1305 if (TARGET_ELF
&& TARGET_64BIT
)
1307 rs6000_altivec_abi
= 1;
1308 rs6000_altivec_vrsave
= 1;
1311 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1312 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1314 rs6000_darwin64_abi
= 1;
1315 /* Setting to empty string is same as "-mone-byte-bool". */
1317 darwin_one_byte_bool
= "";
1319 /* Default to natural alignment, for better performance. */
1320 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1323 /* Handle -mabi= options. */
1324 rs6000_parse_abi_options ();
1326 /* Handle -malign-XXXXX option. */
1327 rs6000_parse_alignment_option ();
1329 rs6000_parse_float_gprs_option ();
1331 /* Handle generic -mFOO=YES/NO options. */
1332 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string
,
1333 &rs6000_altivec_vrsave
);
1334 rs6000_parse_yes_no_option ("isel", rs6000_isel_string
,
1336 rs6000_parse_yes_no_option ("spe", rs6000_spe_string
, &rs6000_spe
);
1338 /* Handle -mtls-size option. */
1339 rs6000_parse_tls_size_option ();
1341 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1342 SUBTARGET_OVERRIDE_OPTIONS
;
1344 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1345 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1347 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1348 SUB3TARGET_OVERRIDE_OPTIONS
;
1354 error ("AltiVec and E500 instructions cannot coexist");
1356 /* The e500 does not have string instructions, and we set
1357 MASK_STRING above when optimizing for size. */
1358 if ((target_flags
& MASK_STRING
) != 0)
1359 target_flags
= target_flags
& ~MASK_STRING
;
1361 /* No SPE means 64-bit long doubles, even if an E500. */
1362 if (rs6000_spe_string
!= 0
1363 && !strcmp (rs6000_spe_string
, "no"))
1364 rs6000_long_double_type_size
= 64;
1366 else if (rs6000_select
[1].string
!= NULL
)
1368 /* For the powerpc-eabispe configuration, we set all these by
1369 default, so let's unset them if we manually set another
1370 CPU that is not the E500. */
1371 if (rs6000_abi_string
== 0)
1373 if (rs6000_spe_string
== 0)
1375 if (rs6000_float_gprs_string
== 0)
1376 rs6000_float_gprs
= 0;
1377 if (rs6000_isel_string
== 0)
1379 if (rs6000_long_double_size_string
== 0)
1380 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1383 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1384 && rs6000_cpu
!= PROCESSOR_POWER5
);
1385 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1386 || rs6000_cpu
== PROCESSOR_POWER5
);
1388 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1389 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1390 bits in target_flags so TARGET_SWITCHES cannot be used.
1391 Assumption here is that rs6000_longcall_switch points into the
1392 text of the complete option, rather than being a copy, so we can
1393 scan back for the presence or absence of the no- modifier. */
1394 if (rs6000_longcall_switch
)
1396 const char *base
= rs6000_longcall_switch
;
1397 while (base
[-1] != 'm') base
--;
1399 if (*rs6000_longcall_switch
!= '\0')
1400 error ("invalid option %qs", base
);
1401 rs6000_default_long_calls
= (base
[0] != 'n');
1404 /* Handle -m(no-)warn-altivec-long similarly. */
1405 if (rs6000_warn_altivec_long_switch
)
1407 const char *base
= rs6000_warn_altivec_long_switch
;
1408 while (base
[-1] != 'm') base
--;
1410 if (*rs6000_warn_altivec_long_switch
!= '\0')
1411 error ("invalid option %qs", base
);
1412 rs6000_warn_altivec_long
= (base
[0] != 'n');
1415 /* Handle -mprioritize-restricted-insns option. */
1416 rs6000_sched_restricted_insns_priority
1417 = (rs6000_sched_groups
? 1 : 0);
1418 if (rs6000_sched_restricted_insns_priority_str
)
1419 rs6000_sched_restricted_insns_priority
=
1420 atoi (rs6000_sched_restricted_insns_priority_str
);
1422 /* Handle -msched-costly-dep option. */
1423 rs6000_sched_costly_dep
1424 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1425 if (rs6000_sched_costly_dep_str
)
1427 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1428 rs6000_sched_costly_dep
= no_dep_costly
;
1429 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1430 rs6000_sched_costly_dep
= all_deps_costly
;
1431 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1432 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1433 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1434 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1436 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1439 /* Handle -minsert-sched-nops option. */
1440 rs6000_sched_insert_nops
1441 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1442 if (rs6000_sched_insert_nops_str
)
1444 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1445 rs6000_sched_insert_nops
= sched_finish_none
;
1446 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1447 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1448 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1449 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1451 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1454 #ifdef TARGET_REGNAMES
1455 /* If the user desires alternate register names, copy in the
1456 alternate names now. */
1457 if (TARGET_REGNAMES
)
1458 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1461 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1462 If -maix-struct-return or -msvr4-struct-return was explicitly
1463 used, don't override with the ABI default. */
1464 if ((target_flags_explicit
& MASK_AIX_STRUCT_RET
) == 0)
1466 if (DEFAULT_ABI
== ABI_V4
&& !DRAFT_V4_STRUCT_RET
)
1467 target_flags
= (target_flags
& ~MASK_AIX_STRUCT_RET
);
1469 target_flags
|= MASK_AIX_STRUCT_RET
;
1472 if (TARGET_LONG_DOUBLE_128
1473 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
))
1474 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1476 /* Allocate an alias set for register saves & restores from stack. */
1477 rs6000_sr_alias_set
= new_alias_set ();
1480 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1482 /* We can only guarantee the availability of DI pseudo-ops when
1483 assembling for 64-bit targets. */
1486 targetm
.asm_out
.aligned_op
.di
= NULL
;
1487 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1490 /* Set branch target alignment, if not optimizing for size. */
1493 if (rs6000_sched_groups
)
1495 if (align_functions
<= 0)
1496 align_functions
= 16;
1497 if (align_jumps
<= 0)
1499 if (align_loops
<= 0)
1502 if (align_jumps_max_skip
<= 0)
1503 align_jumps_max_skip
= 15;
1504 if (align_loops_max_skip
<= 0)
1505 align_loops_max_skip
= 15;
1508 /* Arrange to save and restore machine status around nested functions. */
1509 init_machine_status
= rs6000_init_machine_status
;
1511 /* We should always be splitting complex arguments, but we can't break
1512 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1513 if (DEFAULT_ABI
!= ABI_AIX
)
1514 targetm
.calls
.split_complex_arg
= NULL
;
1516 /* Initialize rs6000_cost with the appropriate target costs. */
1518 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1522 case PROCESSOR_RIOS1
:
1523 rs6000_cost
= &rios1_cost
;
1526 case PROCESSOR_RIOS2
:
1527 rs6000_cost
= &rios2_cost
;
1530 case PROCESSOR_RS64A
:
1531 rs6000_cost
= &rs64a_cost
;
1534 case PROCESSOR_MPCCORE
:
1535 rs6000_cost
= &mpccore_cost
;
1538 case PROCESSOR_PPC403
:
1539 rs6000_cost
= &ppc403_cost
;
1542 case PROCESSOR_PPC405
:
1543 rs6000_cost
= &ppc405_cost
;
1546 case PROCESSOR_PPC440
:
1547 rs6000_cost
= &ppc440_cost
;
1550 case PROCESSOR_PPC601
:
1551 rs6000_cost
= &ppc601_cost
;
1554 case PROCESSOR_PPC603
:
1555 rs6000_cost
= &ppc603_cost
;
1558 case PROCESSOR_PPC604
:
1559 rs6000_cost
= &ppc604_cost
;
1562 case PROCESSOR_PPC604e
:
1563 rs6000_cost
= &ppc604e_cost
;
1566 case PROCESSOR_PPC620
:
1567 rs6000_cost
= &ppc620_cost
;
1570 case PROCESSOR_PPC630
:
1571 rs6000_cost
= &ppc630_cost
;
1574 case PROCESSOR_PPC750
:
1575 case PROCESSOR_PPC7400
:
1576 rs6000_cost
= &ppc750_cost
;
1579 case PROCESSOR_PPC7450
:
1580 rs6000_cost
= &ppc7450_cost
;
1583 case PROCESSOR_PPC8540
:
1584 rs6000_cost
= &ppc8540_cost
;
1587 case PROCESSOR_POWER4
:
1588 case PROCESSOR_POWER5
:
1589 rs6000_cost
= &power4_cost
;
1597 /* Implement targetm.vectorize.builtin_mask_for_load. */
1599 rs6000_builtin_mask_for_load (void)
1602 return altivec_builtin_mask_for_load
;
1607 /* Handle generic options of the form -mfoo=yes/no.
1608 NAME is the option name.
1609 VALUE is the option value.
1610 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1611 whether the option value is 'yes' or 'no' respectively. */
1613 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1617 else if (!strcmp (value
, "yes"))
1619 else if (!strcmp (value
, "no"))
1622 error ("unknown -m%s= option specified: '%s'", name
, value
);
1625 /* Handle -mabi= options. */
1627 rs6000_parse_abi_options (void)
1629 if (rs6000_abi_string
== 0)
1631 else if (! strcmp (rs6000_abi_string
, "altivec"))
1633 rs6000_altivec_abi
= 1;
1636 else if (! strcmp (rs6000_abi_string
, "no-altivec"))
1637 rs6000_altivec_abi
= 0;
1638 else if (! strcmp (rs6000_abi_string
, "spe"))
1641 rs6000_altivec_abi
= 0;
1642 if (!TARGET_SPE_ABI
)
1643 error ("not configured for ABI: '%s'", rs6000_abi_string
);
1646 /* These are here for testing during development only, do not
1647 document in the manual please. */
1648 else if (! strcmp (rs6000_abi_string
, "d64"))
1650 rs6000_darwin64_abi
= 1;
1651 warning ("Using darwin64 ABI");
1653 else if (! strcmp (rs6000_abi_string
, "d32"))
1655 rs6000_darwin64_abi
= 0;
1656 warning ("Using old darwin ABI");
1659 else if (! strcmp (rs6000_abi_string
, "no-spe"))
1662 error ("unknown ABI specified: '%s'", rs6000_abi_string
);
1665 /* Handle -mfloat-gprs= options. */
1667 rs6000_parse_float_gprs_option (void)
1669 if (rs6000_float_gprs_string
== 0)
1671 else if (! strcmp (rs6000_float_gprs_string
, "yes")
1672 || ! strcmp (rs6000_float_gprs_string
, "single"))
1673 rs6000_float_gprs
= 1;
1674 else if (! strcmp (rs6000_float_gprs_string
, "double"))
1675 rs6000_float_gprs
= 2;
1676 else if (! strcmp (rs6000_float_gprs_string
, "no"))
1677 rs6000_float_gprs
= 0;
1679 error ("invalid option for -mfloat-gprs");
1682 /* Handle -malign-XXXXXX options. */
1684 rs6000_parse_alignment_option (void)
1686 if (rs6000_alignment_string
== 0)
1688 else if (! strcmp (rs6000_alignment_string
, "power"))
1690 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1691 some C library functions, so warn about it. The flag may be
1692 useful for performance studies from time to time though, so
1693 don't disable it entirely. */
1694 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1695 warning ("-malign-power is not supported for 64-bit Darwin;"
1696 " it is incompatible with the installed C and C++ libraries");
1697 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
1699 else if (! strcmp (rs6000_alignment_string
, "natural"))
1700 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1702 error ("unknown -malign-XXXXX option specified: '%s'",
1703 rs6000_alignment_string
);
1706 /* Validate and record the size specified with the -mtls-size option. */
1709 rs6000_parse_tls_size_option (void)
1711 if (rs6000_tls_size_string
== 0)
1713 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
1714 rs6000_tls_size
= 16;
1715 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
1716 rs6000_tls_size
= 32;
1717 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
1718 rs6000_tls_size
= 64;
1720 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
1724 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1728 /* Do anything needed at the start of the asm file. */
1731 rs6000_file_start (void)
1735 const char *start
= buffer
;
1736 struct rs6000_cpu_select
*ptr
;
1737 const char *default_cpu
= TARGET_CPU_DEFAULT
;
1738 FILE *file
= asm_out_file
;
1740 default_file_start ();
1742 #ifdef TARGET_BI_ARCH
1743 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
1747 if (flag_verbose_asm
)
1749 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
1750 rs6000_select
[0].string
= default_cpu
;
1752 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1754 ptr
= &rs6000_select
[i
];
1755 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1757 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
1762 #ifdef USING_ELFOS_H
1763 switch (rs6000_sdata
)
1765 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
1766 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
1767 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
1768 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
1771 if (rs6000_sdata
&& g_switch_value
)
1773 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
1783 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
1791 /* Return nonzero if this function is known to have a null epilogue. */
1794 direct_return (void)
1796 if (reload_completed
)
1798 rs6000_stack_t
*info
= rs6000_stack_info ();
1800 if (info
->first_gp_reg_save
== 32
1801 && info
->first_fp_reg_save
== 64
1802 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
1803 && ! info
->lr_save_p
1804 && ! info
->cr_save_p
1805 && info
->vrsave_mask
== 0
1813 /* Returns 1 always. */
1816 any_operand (rtx op ATTRIBUTE_UNUSED
,
1817 enum machine_mode mode ATTRIBUTE_UNUSED
)
1822 /* Returns 1 always. */
1825 any_parallel_operand (rtx op ATTRIBUTE_UNUSED
,
1826 enum machine_mode mode ATTRIBUTE_UNUSED
)
1831 /* Returns 1 if op is the count register. */
1834 count_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1836 if (GET_CODE (op
) != REG
)
1839 if (REGNO (op
) == COUNT_REGISTER_REGNUM
)
1842 if (REGNO (op
) > FIRST_PSEUDO_REGISTER
)
1848 /* Returns 1 if op is an altivec register. */
1851 altivec_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1853 return (register_operand (op
, mode
)
1854 && (GET_CODE (op
) != REG
1855 || REGNO (op
) > FIRST_PSEUDO_REGISTER
1856 || ALTIVEC_REGNO_P (REGNO (op
))));
1860 xer_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1862 if (GET_CODE (op
) != REG
)
1865 if (XER_REGNO_P (REGNO (op
)))
1871 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1872 by such constants completes more quickly. */
1875 s8bit_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1877 return (GET_CODE (op
) == CONST_INT
1878 && (INTVAL (op
) >= -128 && INTVAL (op
) <= 127));
1881 /* Return 1 if OP is a constant that can fit in a D field. */
1884 short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1886 return (GET_CODE (op
) == CONST_INT
1887 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'));
1890 /* Similar for an unsigned D field. */
1893 u_short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1895 return (GET_CODE (op
) == CONST_INT
1896 && CONST_OK_FOR_LETTER_P (INTVAL (op
) & GET_MODE_MASK (mode
), 'K'));
1899 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1902 non_short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1904 return (GET_CODE (op
) == CONST_INT
1905 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x8000) >= 0x10000);
1908 /* Returns 1 if OP is a CONST_INT that is a positive value
1909 and an exact power of 2. */
1912 exact_log2_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1914 return (GET_CODE (op
) == CONST_INT
1916 && exact_log2 (INTVAL (op
)) >= 0);
1919 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1923 gpc_reg_operand (rtx op
, enum machine_mode mode
)
1925 return (register_operand (op
, mode
)
1926 && (GET_CODE (op
) != REG
1927 || (REGNO (op
) >= ARG_POINTER_REGNUM
1928 && !XER_REGNO_P (REGNO (op
)))
1929 || REGNO (op
) < MQ_REGNO
));
1932 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1936 cc_reg_operand (rtx op
, enum machine_mode mode
)
1938 return (register_operand (op
, mode
)
1939 && (GET_CODE (op
) != REG
1940 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
1941 || CR_REGNO_P (REGNO (op
))));
1944 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1945 CR field that isn't CR0. */
1948 cc_reg_not_cr0_operand (rtx op
, enum machine_mode mode
)
1950 return (register_operand (op
, mode
)
1951 && (GET_CODE (op
) != REG
1952 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
1953 || CR_REGNO_NOT_CR0_P (REGNO (op
))));
1956 /* Returns 1 if OP is either a constant integer valid for a D-field or
1957 a non-special register. If a register, it must be in the proper
1958 mode unless MODE is VOIDmode. */
1961 reg_or_short_operand (rtx op
, enum machine_mode mode
)
1963 return short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
1966 /* Similar, except check if the negation of the constant would be
1967 valid for a D-field. Don't allow a constant zero, since all the
1968 patterns that call this predicate use "addic r1,r2,-constant" on
1969 a constant value to set a carry when r2 is greater or equal to
1970 "constant". That doesn't work for zero. */
1973 reg_or_neg_short_operand (rtx op
, enum machine_mode mode
)
1975 if (GET_CODE (op
) == CONST_INT
)
1976 return CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P') && INTVAL (op
) != 0;
1978 return gpc_reg_operand (op
, mode
);
1981 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1982 a non-special register. If a register, it must be in the proper
1983 mode unless MODE is VOIDmode. */
1986 reg_or_aligned_short_operand (rtx op
, enum machine_mode mode
)
1988 if (gpc_reg_operand (op
, mode
))
1990 else if (short_cint_operand (op
, mode
) && !(INTVAL (op
) & 3))
1997 /* Return 1 if the operand is either a register or an integer whose
1998 high-order 16 bits are zero. */
2001 reg_or_u_short_operand (rtx op
, enum machine_mode mode
)
2003 return u_short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
2006 /* Return 1 is the operand is either a non-special register or ANY
2007 constant integer. */
2010 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
2012 return (GET_CODE (op
) == CONST_INT
|| gpc_reg_operand (op
, mode
));
2015 /* Return 1 is the operand is either a non-special register or ANY
2016 32-bit signed constant integer. */
2019 reg_or_arith_cint_operand (rtx op
, enum machine_mode mode
)
2021 return (gpc_reg_operand (op
, mode
)
2022 || (GET_CODE (op
) == CONST_INT
2023 #if HOST_BITS_PER_WIDE_INT != 32
2024 && ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x80000000)
2025 < (unsigned HOST_WIDE_INT
) 0x100000000ll
)
2030 /* Return 1 is the operand is either a non-special register or a 32-bit
2031 signed constant integer valid for 64-bit addition. */
2034 reg_or_add_cint64_operand (rtx op
, enum machine_mode mode
)
2036 return (gpc_reg_operand (op
, mode
)
2037 || (GET_CODE (op
) == CONST_INT
2038 #if HOST_BITS_PER_WIDE_INT == 32
2039 && INTVAL (op
) < 0x7fff8000
2041 && ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x80008000)
2047 /* Return 1 is the operand is either a non-special register or a 32-bit
2048 signed constant integer valid for 64-bit subtraction. */
2051 reg_or_sub_cint64_operand (rtx op
, enum machine_mode mode
)
2053 return (gpc_reg_operand (op
, mode
)
2054 || (GET_CODE (op
) == CONST_INT
2055 #if HOST_BITS_PER_WIDE_INT == 32
2056 && (- INTVAL (op
)) < 0x7fff8000
2058 && ((unsigned HOST_WIDE_INT
) ((- INTVAL (op
)) + 0x80008000)
2064 /* Return 1 is the operand is either a non-special register or ANY
2065 32-bit unsigned constant integer. */
2068 reg_or_logical_cint_operand (rtx op
, enum machine_mode mode
)
2070 if (GET_CODE (op
) == CONST_INT
)
2072 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
2074 if (GET_MODE_BITSIZE (mode
) <= 32)
2077 if (INTVAL (op
) < 0)
2081 return ((INTVAL (op
) & GET_MODE_MASK (mode
)
2082 & (~ (unsigned HOST_WIDE_INT
) 0xffffffff)) == 0);
2084 else if (GET_CODE (op
) == CONST_DOUBLE
)
2086 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2090 return CONST_DOUBLE_HIGH (op
) == 0;
2093 return gpc_reg_operand (op
, mode
);
2096 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2099 got_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2101 return (GET_CODE (op
) == SYMBOL_REF
2102 || GET_CODE (op
) == CONST
2103 || GET_CODE (op
) == LABEL_REF
);
2106 /* Return 1 if the operand is a simple references that can be loaded via
2107 the GOT (labels involving addition aren't allowed). */
2110 got_no_const_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2112 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
);
2115 /* Return the number of instructions it takes to form a constant in an
2116 integer register. */
2119 num_insns_constant_wide (HOST_WIDE_INT value
)
2121 /* signed constant loadable with {cal|addi} */
2122 if (CONST_OK_FOR_LETTER_P (value
, 'I'))
2125 /* constant loadable with {cau|addis} */
2126 else if (CONST_OK_FOR_LETTER_P (value
, 'L'))
2129 #if HOST_BITS_PER_WIDE_INT == 64
2130 else if (TARGET_POWERPC64
)
2132 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2133 HOST_WIDE_INT high
= value
>> 31;
2135 if (high
== 0 || high
== -1)
2141 return num_insns_constant_wide (high
) + 1;
2143 return (num_insns_constant_wide (high
)
2144 + num_insns_constant_wide (low
) + 1);
2153 num_insns_constant (rtx op
, enum machine_mode mode
)
2155 if (GET_CODE (op
) == CONST_INT
)
2157 #if HOST_BITS_PER_WIDE_INT == 64
2158 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2159 && mask64_operand (op
, mode
))
2163 return num_insns_constant_wide (INTVAL (op
));
2166 else if (GET_CODE (op
) == CONST_DOUBLE
&& mode
== SFmode
)
2171 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2172 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2173 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2176 else if (GET_CODE (op
) == CONST_DOUBLE
)
2182 int endian
= (WORDS_BIG_ENDIAN
== 0);
2184 if (mode
== VOIDmode
|| mode
== DImode
)
2186 high
= CONST_DOUBLE_HIGH (op
);
2187 low
= CONST_DOUBLE_LOW (op
);
2191 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2192 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2194 low
= l
[1 - endian
];
2198 return (num_insns_constant_wide (low
)
2199 + num_insns_constant_wide (high
));
2203 if (high
== 0 && low
>= 0)
2204 return num_insns_constant_wide (low
);
2206 else if (high
== -1 && low
< 0)
2207 return num_insns_constant_wide (low
);
2209 else if (mask64_operand (op
, mode
))
2213 return num_insns_constant_wide (high
) + 1;
2216 return (num_insns_constant_wide (high
)
2217 + num_insns_constant_wide (low
) + 1);
2225 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2226 register with one instruction per word. We only do this if we can
2227 safely read CONST_DOUBLE_{LOW,HIGH}. */
2230 easy_fp_constant (rtx op
, enum machine_mode mode
)
2232 if (GET_CODE (op
) != CONST_DOUBLE
2233 || GET_MODE (op
) != mode
2234 || (GET_MODE_CLASS (mode
) != MODE_FLOAT
&& mode
!= DImode
))
2237 /* Consider all constants with -msoft-float to be easy. */
2238 if ((TARGET_SOFT_FLOAT
|| TARGET_E500_SINGLE
)
2242 /* If we are using V.4 style PIC, consider all constants to be hard. */
2243 if (flag_pic
&& DEFAULT_ABI
== ABI_V4
)
2246 #ifdef TARGET_RELOCATABLE
2247 /* Similarly if we are using -mrelocatable, consider all constants
2249 if (TARGET_RELOCATABLE
)
2258 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2259 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
2261 return (num_insns_constant_wide ((HOST_WIDE_INT
) k
[0]) == 1
2262 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[1]) == 1
2263 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[2]) == 1
2264 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[3]) == 1);
2267 else if (mode
== DFmode
)
2272 if (TARGET_E500_DOUBLE
)
2275 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2276 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
2278 return (num_insns_constant_wide ((HOST_WIDE_INT
) k
[0]) == 1
2279 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[1]) == 1);
2282 else if (mode
== SFmode
)
2287 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2288 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2290 return num_insns_constant_wide (l
) == 1;
2293 else if (mode
== DImode
)
2294 return ((TARGET_POWERPC64
2295 && GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_LOW (op
) == 0)
2296 || (num_insns_constant (op
, DImode
) <= 2));
2298 else if (mode
== SImode
)
2304 /* Returns the constant for the splat instruction, if exists. */
2307 easy_vector_splat_const (int cst
, enum machine_mode mode
)
2312 if (EASY_VECTOR_15 (cst
)
2313 || EASY_VECTOR_15_ADD_SELF (cst
))
2315 if ((cst
& 0xffff) != ((cst
>> 16) & 0xffff))
2321 if (EASY_VECTOR_15 (cst
)
2322 || EASY_VECTOR_15_ADD_SELF (cst
))
2324 if ((cst
& 0xff) != ((cst
>> 8) & 0xff))
2330 if (EASY_VECTOR_15 (cst
)
2331 || EASY_VECTOR_15_ADD_SELF (cst
))
2340 /* Return nonzero if all elements of a vector have the same value. */
2343 easy_vector_same (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2347 units
= CONST_VECTOR_NUNITS (op
);
2349 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
2350 for (i
= 1; i
< units
; ++i
)
2351 if (INTVAL (CONST_VECTOR_ELT (op
, i
)) != cst
)
2353 if (i
== units
&& easy_vector_splat_const (cst
, mode
))
2358 /* Return 1 if the operand is a CONST_INT and can be put into a
2359 register without using memory. */
2362 easy_vector_constant (rtx op
, enum machine_mode mode
)
2366 if (GET_CODE (op
) != CONST_VECTOR
2371 if (zero_constant (op
, mode
)
2372 && ((TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
2373 || (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))))
2376 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2379 if (TARGET_SPE
&& mode
== V1DImode
)
2382 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
2383 cst2
= INTVAL (CONST_VECTOR_ELT (op
, 1));
2385 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2387 evmergelo r0, r0, r0
2390 I don't know how efficient it would be to allow bigger constants,
2391 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2392 instructions is better than a 64-bit memory load, but I don't
2393 have the e500 timing specs. */
2394 if (TARGET_SPE
&& mode
== V2SImode
2395 && cst
>= -0x7fff && cst
<= 0x7fff
2396 && cst2
>= -0x7fff && cst2
<= 0x7fff)
2400 && easy_vector_same (op
, mode
))
2402 cst
= easy_vector_splat_const (cst
, mode
);
2403 if (EASY_VECTOR_15_ADD_SELF (cst
)
2404 || EASY_VECTOR_15 (cst
))
2410 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2413 easy_vector_constant_add_self (rtx op
, enum machine_mode mode
)
2417 && GET_CODE (op
) == CONST_VECTOR
2418 && easy_vector_same (op
, mode
))
2420 cst
= easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op
, 0)), mode
);
2421 if (EASY_VECTOR_15_ADD_SELF (cst
))
2427 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2430 gen_easy_vector_constant_add_self (rtx op
)
2434 units
= GET_MODE_NUNITS (GET_MODE (op
));
2435 v
= rtvec_alloc (units
);
2437 for (i
= 0; i
< units
; i
++)
2439 GEN_INT (INTVAL (CONST_VECTOR_ELT (op
, i
)) >> 1);
2440 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op
), v
);
2444 output_vec_const_move (rtx
*operands
)
2447 enum machine_mode mode
;
2453 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2454 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2455 mode
= GET_MODE (dest
);
2459 if (zero_constant (vec
, mode
))
2460 return "vxor %0,%0,%0";
2461 else if (easy_vector_constant (vec
, mode
))
2463 operands
[1] = GEN_INT (cst
);
2467 if (EASY_VECTOR_15 (cst
))
2469 operands
[1] = GEN_INT (cst
);
2470 return "vspltisw %0,%1";
2472 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2478 if (EASY_VECTOR_15 (cst
))
2480 operands
[1] = GEN_INT (cst
);
2481 return "vspltish %0,%1";
2483 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2489 if (EASY_VECTOR_15 (cst
))
2491 operands
[1] = GEN_INT (cst
);
2492 return "vspltisb %0,%1";
2494 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2507 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2508 pattern of V1DI, V4HI, and V2SF.
2510 FIXME: We should probably return # and add post reload
2511 splitters for these, but this way is so easy ;-). */
2512 operands
[1] = GEN_INT (cst
);
2513 operands
[2] = GEN_INT (cst2
);
2515 return "li %0,%1\n\tevmergelo %0,%0,%0";
2517 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2523 /* Return 1 if the operand is the constant 0. This works for scalars
2524 as well as vectors. */
2526 zero_constant (rtx op
, enum machine_mode mode
)
2528 return op
== CONST0_RTX (mode
);
2531 /* Return 1 if the operand is 0.0. */
2533 zero_fp_constant (rtx op
, enum machine_mode mode
)
2535 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
2538 /* Return 1 if the operand is in volatile memory. Note that during
2539 the RTL generation phase, memory_operand does not return TRUE for
2540 volatile memory references. So this function allows us to
2541 recognize volatile references where its safe. */
2544 volatile_mem_operand (rtx op
, enum machine_mode mode
)
2546 if (GET_CODE (op
) != MEM
)
2549 if (!MEM_VOLATILE_P (op
))
2552 if (mode
!= GET_MODE (op
))
2555 if (reload_completed
)
2556 return memory_operand (op
, mode
);
2558 if (reload_in_progress
)
2559 return strict_memory_address_p (mode
, XEXP (op
, 0));
2561 return memory_address_p (mode
, XEXP (op
, 0));
2564 /* Return 1 if the operand is an offsettable memory operand. */
2567 offsettable_mem_operand (rtx op
, enum machine_mode mode
)
2569 return ((GET_CODE (op
) == MEM
)
2570 && offsettable_address_p (reload_completed
|| reload_in_progress
,
2571 mode
, XEXP (op
, 0)));
2574 /* Return 1 if the operand is either an easy FP constant (see above) or
2578 mem_or_easy_const_operand (rtx op
, enum machine_mode mode
)
2580 return memory_operand (op
, mode
) || easy_fp_constant (op
, mode
);
2583 /* Return 1 if the operand is either a non-special register or an item
2584 that can be used as the operand of a `mode' add insn. */
2587 add_operand (rtx op
, enum machine_mode mode
)
2589 if (GET_CODE (op
) == CONST_INT
)
2590 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
2591 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
2593 return gpc_reg_operand (op
, mode
);
2596 /* Return 1 if OP is a constant but not a valid add_operand. */
2599 non_add_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2601 return (GET_CODE (op
) == CONST_INT
2602 && !CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
2603 && !CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
2606 /* Return 1 if the operand is a non-special register or a constant that
2607 can be used as the operand of an OR or XOR insn on the RS/6000. */
2610 logical_operand (rtx op
, enum machine_mode mode
)
2612 HOST_WIDE_INT opl
, oph
;
2614 if (gpc_reg_operand (op
, mode
))
2617 if (GET_CODE (op
) == CONST_INT
)
2619 opl
= INTVAL (op
) & GET_MODE_MASK (mode
);
2621 #if HOST_BITS_PER_WIDE_INT <= 32
2622 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
&& opl
< 0)
2626 else if (GET_CODE (op
) == CONST_DOUBLE
)
2628 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
2631 opl
= CONST_DOUBLE_LOW (op
);
2632 oph
= CONST_DOUBLE_HIGH (op
);
2639 return ((opl
& ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0
2640 || (opl
& ~ (unsigned HOST_WIDE_INT
) 0xffff0000) == 0);
2643 /* Return 1 if C is a constant that is not a logical operand (as
2644 above), but could be split into one. */
2647 non_logical_cint_operand (rtx op
, enum machine_mode mode
)
2649 return ((GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
)
2650 && ! logical_operand (op
, mode
)
2651 && reg_or_logical_cint_operand (op
, mode
));
2654 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2655 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2656 Reject all ones and all zeros, since these should have been optimized
2657 away and confuse the making of MB and ME. */
2660 mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2662 HOST_WIDE_INT c
, lsb
;
2664 if (GET_CODE (op
) != CONST_INT
)
2669 /* Fail in 64-bit mode if the mask wraps around because the upper
2670 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2671 if (TARGET_POWERPC64
&& (c
& 0x80000001) == 0x80000001)
2674 /* We don't change the number of transitions by inverting,
2675 so make sure we start with the LS bit zero. */
2679 /* Reject all zeros or all ones. */
2683 /* Find the first transition. */
2686 /* Invert to look for a second transition. */
2689 /* Erase first transition. */
2692 /* Find the second transition (if any). */
2695 /* Match if all the bits above are 1's (or c is zero). */
2699 /* Return 1 for the PowerPC64 rlwinm corner case. */
2702 mask_operand_wrap (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2704 HOST_WIDE_INT c
, lsb
;
2706 if (GET_CODE (op
) != CONST_INT
)
2711 if ((c
& 0x80000001) != 0x80000001)
2725 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2726 It is if there are no more than one 1->0 or 0->1 transitions.
2727 Reject all zeros, since zero should have been optimized away and
2728 confuses the making of MB and ME. */
2731 mask64_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2733 if (GET_CODE (op
) == CONST_INT
)
2735 HOST_WIDE_INT c
, lsb
;
2739 /* Reject all zeros. */
2743 /* We don't change the number of transitions by inverting,
2744 so make sure we start with the LS bit zero. */
2748 /* Find the transition, and check that all bits above are 1's. */
2751 /* Match if all the bits above are 1's (or c is zero). */
2758 mask64_1or2_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2761 if (GET_CODE (op
) == CONST_INT
)
2763 HOST_WIDE_INT c
, lsb
;
2768 /* Disallow all zeros. */
2772 /* We can use a single rlwinm insn if no upper bits of C are set
2773 AND there are zero, one or two transitions in the _whole_ of
2775 one_ok
= !(c
& ~(HOST_WIDE_INT
)0xffffffff);
2777 /* We don't change the number of transitions by inverting,
2778 so make sure we start with the LS bit zero. */
2782 /* Find the first transition. */
2785 /* Invert to look for a second transition. */
2788 /* Erase first transition. */
2791 /* Find the second transition. */
2794 /* Invert to look for a third transition. */
2797 /* Erase second transition. */
2800 if (one_ok
&& !(allow_one
|| c
))
2803 /* Find the third transition (if any). */
2806 /* Match if all the bits above are 1's (or c is zero). */
2812 /* Like mask64_operand, but allow up to three transitions. This
2813 predicate is used by insn patterns that generate two rldicl or
2814 rldicr machine insns. */
2815 int mask64_2_operand (rtx op
, enum machine_mode mode
)
2817 return mask64_1or2_operand (op
, mode
, false);
2820 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2821 implement ANDing by the mask IN. */
2823 build_mask64_2_operands (rtx in
, rtx
*out
)
2825 #if HOST_BITS_PER_WIDE_INT >= 64
2826 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
2829 if (GET_CODE (in
) != CONST_INT
)
2835 /* Assume c initially something like 0x00fff000000fffff. The idea
2836 is to rotate the word so that the middle ^^^^^^ group of zeros
2837 is at the MS end and can be cleared with an rldicl mask. We then
2838 rotate back and clear off the MS ^^ group of zeros with a
2840 c
= ~c
; /* c == 0xff000ffffff00000 */
2841 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
2842 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
2843 c
= ~c
; /* c == 0x00fff000000fffff */
2844 c
&= -lsb
; /* c == 0x00fff00000000000 */
2845 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2846 c
= ~c
; /* c == 0xff000fffffffffff */
2847 c
&= -lsb
; /* c == 0xff00000000000000 */
2849 while ((lsb
>>= 1) != 0)
2850 shift
++; /* shift == 44 on exit from loop */
2851 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
2852 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
2853 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
2857 /* Assume c initially something like 0xff000f0000000000. The idea
2858 is to rotate the word so that the ^^^ middle group of zeros
2859 is at the LS end and can be cleared with an rldicr mask. We then
2860 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2862 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
2863 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
2864 c
= ~c
; /* c == 0x00fff0ffffffffff */
2865 c
&= -lsb
; /* c == 0x00fff00000000000 */
2866 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2867 c
= ~c
; /* c == 0xff000fffffffffff */
2868 c
&= -lsb
; /* c == 0xff00000000000000 */
2870 while ((lsb
>>= 1) != 0)
2871 shift
++; /* shift == 44 on exit from loop */
2872 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
2873 m1
>>= shift
; /* m1 == 0x0000000000000fff */
2874 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
2877 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2878 masks will be all 1's. We are guaranteed more than one transition. */
2879 out
[0] = GEN_INT (64 - shift
);
2880 out
[1] = GEN_INT (m1
);
2881 out
[2] = GEN_INT (shift
);
2882 out
[3] = GEN_INT (m2
);
2890 /* Return 1 if the operand is either a non-special register or a constant
2891 that can be used as the operand of a PowerPC64 logical AND insn. */
2894 and64_operand (rtx op
, enum machine_mode mode
)
2896 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2897 return (gpc_reg_operand (op
, mode
) || mask64_operand (op
, mode
));
2899 return (logical_operand (op
, mode
) || mask64_operand (op
, mode
));
2902 /* Like the above, but also match constants that can be implemented
2903 with two rldicl or rldicr insns. */
2906 and64_2_operand (rtx op
, enum machine_mode mode
)
2908 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2909 return gpc_reg_operand (op
, mode
) || mask64_1or2_operand (op
, mode
, true);
2911 return logical_operand (op
, mode
) || mask64_1or2_operand (op
, mode
, true);
2914 /* Return 1 if the operand is either a non-special register or a
2915 constant that can be used as the operand of an RS/6000 logical AND insn. */
2918 and_operand (rtx op
, enum machine_mode mode
)
2920 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2921 return (gpc_reg_operand (op
, mode
) || mask_operand (op
, mode
));
2923 return (logical_operand (op
, mode
) || mask_operand (op
, mode
));
2926 /* Return 1 if the operand is a general register or memory operand. */
2929 reg_or_mem_operand (rtx op
, enum machine_mode mode
)
2931 return (gpc_reg_operand (op
, mode
)
2932 || memory_operand (op
, mode
)
2933 || macho_lo_sum_memory_operand (op
, mode
)
2934 || volatile_mem_operand (op
, mode
));
2937 /* Return 1 if the operand is a general register or memory operand without
2938 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2942 lwa_operand (rtx op
, enum machine_mode mode
)
2946 if (reload_completed
&& GET_CODE (inner
) == SUBREG
)
2947 inner
= SUBREG_REG (inner
);
2949 return gpc_reg_operand (inner
, mode
)
2950 || (memory_operand (inner
, mode
)
2951 && GET_CODE (XEXP (inner
, 0)) != PRE_INC
2952 && GET_CODE (XEXP (inner
, 0)) != PRE_DEC
2953 && (GET_CODE (XEXP (inner
, 0)) != PLUS
2954 || GET_CODE (XEXP (XEXP (inner
, 0), 1)) != CONST_INT
2955 || INTVAL (XEXP (XEXP (inner
, 0), 1)) % 4 == 0));
2958 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2961 symbol_ref_operand (rtx op
, enum machine_mode mode
)
2963 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2966 return (GET_CODE (op
) == SYMBOL_REF
2967 && (DEFAULT_ABI
!= ABI_AIX
|| SYMBOL_REF_FUNCTION_P (op
)));
2970 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2971 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2974 call_operand (rtx op
, enum machine_mode mode
)
2976 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2979 return (GET_CODE (op
) == SYMBOL_REF
2980 || (GET_CODE (op
) == REG
2981 && (REGNO (op
) == LINK_REGISTER_REGNUM
2982 || REGNO (op
) == COUNT_REGISTER_REGNUM
2983 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
2986 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2990 current_file_function_operand (rtx op
,
2991 enum machine_mode mode ATTRIBUTE_UNUSED
)
2993 return (GET_CODE (op
) == SYMBOL_REF
2994 && (DEFAULT_ABI
!= ABI_AIX
|| SYMBOL_REF_FUNCTION_P (op
))
2995 && (SYMBOL_REF_LOCAL_P (op
)
2996 || (DECL_RTL_SET_P (current_function_decl
)
2997 && op
== XEXP (DECL_RTL (current_function_decl
), 0))));
3000 /* Return 1 if this operand is a valid input for a move insn. */
3003 input_operand (rtx op
, enum machine_mode mode
)
3005 /* Memory is always valid. */
3006 if (memory_operand (op
, mode
))
3009 /* For floating-point, easy constants are valid. */
3010 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3012 && easy_fp_constant (op
, mode
))
3015 /* Allow any integer constant. */
3016 if (GET_MODE_CLASS (mode
) == MODE_INT
3017 && (GET_CODE (op
) == CONST_INT
3018 || GET_CODE (op
) == CONST_DOUBLE
))
3021 /* Allow easy vector constants. */
3022 if (GET_CODE (op
) == CONST_VECTOR
3023 && easy_vector_constant (op
, mode
))
3026 /* For floating-point or multi-word mode, the only remaining valid type
3028 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3029 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3030 return register_operand (op
, mode
);
3032 /* The only cases left are integral modes one word or smaller (we
3033 do not get called for MODE_CC values). These can be in any
3035 if (register_operand (op
, mode
))
3038 /* A SYMBOL_REF referring to the TOC is valid. */
3039 if (legitimate_constant_pool_address_p (op
))
3042 /* A constant pool expression (relative to the TOC) is valid */
3043 if (toc_relative_expr_p (op
))
3046 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3048 if (DEFAULT_ABI
== ABI_V4
3049 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
)
3050 && small_data_operand (op
, Pmode
))
3056 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3058 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
3060 /* Reject (subreg:SI (reg:DF)). */
3061 if (GET_CODE (op
) == SUBREG
3063 && REG_P (SUBREG_REG (op
))
3064 && GET_MODE (SUBREG_REG (op
)) == DFmode
)
3067 /* Reject (subreg:DF (reg:DI)). */
3068 if (GET_CODE (op
) == SUBREG
3070 && REG_P (SUBREG_REG (op
))
3071 && GET_MODE (SUBREG_REG (op
)) == DImode
)
3077 /* Just like nonimmediate_operand, but return 0 for invalid SUBREG's
3080 rs6000_nonimmediate_operand (rtx op
, enum machine_mode mode
)
3082 if (TARGET_E500_DOUBLE
3083 && GET_CODE (op
) == SUBREG
3084 && invalid_e500_subreg (op
, mode
))
3087 return nonimmediate_operand (op
, mode
);
3090 /* Darwin, AIX increases natural record alignment to doubleword if the first
3091 field is an FP double while the FP fields remain word aligned. */
3094 rs6000_special_round_type_align (tree type
, int computed
, int specified
)
3096 tree field
= TYPE_FIELDS (type
);
3098 /* Skip all non field decls */
3099 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3100 field
= TREE_CHAIN (field
);
3102 if (field
== NULL
|| field
== type
|| DECL_MODE (field
) != DFmode
)
3103 return MAX (computed
, specified
);
3105 return MAX (MAX (computed
, specified
), 64);
3108 /* Return 1 for an operand in small memory on V.4/eabi. */
3111 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3112 enum machine_mode mode ATTRIBUTE_UNUSED
)
3117 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3120 if (DEFAULT_ABI
!= ABI_V4
)
3123 if (GET_CODE (op
) == SYMBOL_REF
)
3126 else if (GET_CODE (op
) != CONST
3127 || GET_CODE (XEXP (op
, 0)) != PLUS
3128 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3129 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3134 rtx sum
= XEXP (op
, 0);
3135 HOST_WIDE_INT summand
;
3137 /* We have to be careful here, because it is the referenced address
3138 that must be 32k from _SDA_BASE_, not just the symbol. */
3139 summand
= INTVAL (XEXP (sum
, 1));
3140 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3143 sym_ref
= XEXP (sum
, 0);
3146 return SYMBOL_REF_SMALL_P (sym_ref
);
3152 /* Return true, if operand is a memory operand and has a
3153 displacement divisible by 4. */
3156 word_offset_memref_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3161 if (!memory_operand (op
, mode
))
3164 addr
= XEXP (op
, 0);
3165 if (GET_CODE (addr
) == PLUS
3166 && GET_CODE (XEXP (addr
, 0)) == REG
3167 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3168 off
= INTVAL (XEXP (addr
, 1));
3170 return (off
% 4) == 0;
3173 /* Return true if either operand is a general purpose register. */
3176 gpr_or_gpr_p (rtx op0
, rtx op1
)
3178 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3179 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3183 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3186 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3188 switch (GET_CODE(op
))
3191 if (RS6000_SYMBOL_REF_TLS_P (op
))
3193 else if (CONSTANT_POOL_ADDRESS_P (op
))
3195 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3203 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3212 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3213 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3215 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3224 constant_pool_expr_p (rtx op
)
3228 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3232 toc_relative_expr_p (rtx op
)
3236 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3240 legitimate_constant_pool_address_p (rtx x
)
3243 && GET_CODE (x
) == PLUS
3244 && GET_CODE (XEXP (x
, 0)) == REG
3245 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3246 && constant_pool_expr_p (XEXP (x
, 1)));
3250 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3252 return (DEFAULT_ABI
== ABI_V4
3253 && !flag_pic
&& !TARGET_TOC
3254 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3255 && small_data_operand (x
, mode
));
3258 /* SPE offset addressing is limited to 5-bits worth of double words. */
3259 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3262 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3264 unsigned HOST_WIDE_INT offset
, extra
;
3266 if (GET_CODE (x
) != PLUS
)
3268 if (GET_CODE (XEXP (x
, 0)) != REG
)
3270 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3272 if (legitimate_constant_pool_address_p (x
))
3274 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3277 offset
= INTVAL (XEXP (x
, 1));
3285 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3286 which leaves the only valid constant offset of zero, which by
3287 canonicalization rules is also invalid. */
3294 /* SPE vector modes. */
3295 return SPE_CONST_OFFSET_OK (offset
);
3298 if (TARGET_E500_DOUBLE
)
3299 return SPE_CONST_OFFSET_OK (offset
);
3302 /* On e500v2, we may have:
3304 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3306 Which gets addressed with evldd instructions. */
3307 if (TARGET_E500_DOUBLE
)
3308 return SPE_CONST_OFFSET_OK (offset
);
3310 if (mode
== DFmode
|| !TARGET_POWERPC64
)
3312 else if (offset
& 3)
3318 if (mode
== TFmode
|| !TARGET_POWERPC64
)
3320 else if (offset
& 3)
3331 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3335 legitimate_indexed_address_p (rtx x
, int strict
)
3339 if (GET_CODE (x
) != PLUS
)
3345 if (!REG_P (op0
) || !REG_P (op1
))
3348 return ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3349 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3350 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3351 && INT_REG_OK_FOR_INDEX_P (op0
, strict
)));
3355 legitimate_indirect_address_p (rtx x
, int strict
)
3357 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3361 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3363 if (!TARGET_MACHO
|| !flag_pic
3364 || mode
!= SImode
|| GET_CODE(x
) != MEM
)
3368 if (GET_CODE (x
) != LO_SUM
)
3370 if (GET_CODE (XEXP (x
, 0)) != REG
)
3372 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3376 return CONSTANT_P (x
);
3380 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3382 if (GET_CODE (x
) != LO_SUM
)
3384 if (GET_CODE (XEXP (x
, 0)) != REG
)
3386 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3388 /* Restrict addressing for DI because of our SUBREG hackery. */
3389 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
3393 if (TARGET_ELF
|| TARGET_MACHO
)
3395 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3399 if (GET_MODE_NUNITS (mode
) != 1)
3401 if (GET_MODE_BITSIZE (mode
) > 64
3402 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3403 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& mode
== DFmode
)))
3406 return CONSTANT_P (x
);
3413 /* Try machine-dependent ways of modifying an illegitimate address
3414 to be legitimate. If we find one, return the new, valid address.
3415 This is used from only one place: `memory_address' in explow.c.
3417 OLDX is the address as it was before break_out_memory_refs was
3418 called. In some cases it is useful to look at this to decide what
3421 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3423 It is always safe for this function to do nothing. It exists to
3424 recognize opportunities to optimize the output.
3426 On RS/6000, first check for the sum of a register with a constant
3427 integer that is out of range. If so, generate code to add the
3428 constant with the low-order 16 bits masked to the register and force
3429 this result into another register (this can be done with `cau').
3430 Then generate an address of REG+(CONST&0xffff), allowing for the
3431 possibility of bit 16 being a one.
3433 Then check for the sum of a register and something not constant, try to
3434 load the other things into a register and return the sum. */
3437 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3438 enum machine_mode mode
)
3440 if (GET_CODE (x
) == SYMBOL_REF
)
3442 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3444 return rs6000_legitimize_tls_address (x
, model
);
3447 if (GET_CODE (x
) == PLUS
3448 && GET_CODE (XEXP (x
, 0)) == REG
3449 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3450 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000)
3452 HOST_WIDE_INT high_int
, low_int
;
3454 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3455 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3456 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3457 GEN_INT (high_int
)), 0);
3458 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3460 else if (GET_CODE (x
) == PLUS
3461 && GET_CODE (XEXP (x
, 0)) == REG
3462 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3463 && GET_MODE_NUNITS (mode
) == 1
3464 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3466 || (((mode
!= DImode
&& mode
!= DFmode
) || TARGET_E500_DOUBLE
)
3468 && (TARGET_POWERPC64
|| mode
!= DImode
)
3471 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3472 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3474 else if (ALTIVEC_VECTOR_MODE (mode
))
3478 /* Make sure both operands are registers. */
3479 if (GET_CODE (x
) == PLUS
)
3480 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3481 force_reg (Pmode
, XEXP (x
, 1)));
3483 reg
= force_reg (Pmode
, x
);
3486 else if (SPE_VECTOR_MODE (mode
)
3487 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
3488 || mode
== DImode
)))
3492 /* We accept [reg + reg] and [reg + OFFSET]. */
3494 if (GET_CODE (x
) == PLUS
)
3496 rtx op1
= XEXP (x
, 0);
3497 rtx op2
= XEXP (x
, 1);
3499 op1
= force_reg (Pmode
, op1
);
3501 if (GET_CODE (op2
) != REG
3502 && (GET_CODE (op2
) != CONST_INT
3503 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
3504 op2
= force_reg (Pmode
, op2
);
3506 return gen_rtx_PLUS (Pmode
, op1
, op2
);
3509 return force_reg (Pmode
, x
);
3515 && GET_CODE (x
) != CONST_INT
3516 && GET_CODE (x
) != CONST_DOUBLE
3518 && GET_MODE_NUNITS (mode
) == 1
3519 && (GET_MODE_BITSIZE (mode
) <= 32
3520 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) && mode
== DFmode
)))
3522 rtx reg
= gen_reg_rtx (Pmode
);
3523 emit_insn (gen_elf_high (reg
, x
));
3524 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3526 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3529 && ! MACHO_DYNAMIC_NO_PIC_P
3531 && GET_CODE (x
) != CONST_INT
3532 && GET_CODE (x
) != CONST_DOUBLE
3534 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) || mode
!= DFmode
)
3538 rtx reg
= gen_reg_rtx (Pmode
);
3539 emit_insn (gen_macho_high (reg
, x
));
3540 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3543 && constant_pool_expr_p (x
)
3544 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3546 return create_TOC_reference (x
);
3552 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3553 We need to emit DTP-relative relocations. */
3556 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3561 fputs ("\t.long\t", file
);
3564 fputs (DOUBLE_INT_ASM_OP
, file
);
3569 output_addr_const (file
, x
);
3570 fputs ("@dtprel+0x8000", file
);
3573 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3575 static GTY(()) rtx rs6000_tls_symbol
;
3577 rs6000_tls_get_addr (void)
3579 if (!rs6000_tls_symbol
)
3580 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3582 return rs6000_tls_symbol
;
3585 /* Construct the SYMBOL_REF for TLS GOT references. */
3587 static GTY(()) rtx rs6000_got_symbol
;
3589 rs6000_got_sym (void)
3591 if (!rs6000_got_symbol
)
3593 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3594 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3595 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3598 return rs6000_got_symbol
;
3601 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3602 this (thread-local) address. */
3605 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3609 dest
= gen_reg_rtx (Pmode
);
3610 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3616 tlsreg
= gen_rtx_REG (Pmode
, 13);
3617 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3621 tlsreg
= gen_rtx_REG (Pmode
, 2);
3622 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3626 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3630 tmp
= gen_reg_rtx (Pmode
);
3633 tlsreg
= gen_rtx_REG (Pmode
, 13);
3634 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3638 tlsreg
= gen_rtx_REG (Pmode
, 2);
3639 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3643 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3645 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3650 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3653 got
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
3657 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3660 rtx gsym
= rs6000_got_sym ();
3661 got
= gen_reg_rtx (Pmode
);
3663 rs6000_emit_move (got
, gsym
, Pmode
);
3667 static int tls_got_labelno
= 0;
3668 rtx tempLR
, lab
, tmp3
, mem
;
3671 ASM_GENERATE_INTERNAL_LABEL (buf
, "LTLS", tls_got_labelno
++);
3672 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
3673 tempLR
= gen_reg_rtx (Pmode
);
3674 tmp1
= gen_reg_rtx (Pmode
);
3675 tmp2
= gen_reg_rtx (Pmode
);
3676 tmp3
= gen_reg_rtx (Pmode
);
3677 mem
= gen_const_mem (Pmode
, tmp1
);
3679 first
= emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, lab
,
3681 emit_move_insn (tmp1
, tempLR
);
3682 emit_move_insn (tmp2
, mem
);
3683 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3684 last
= emit_move_insn (got
, tmp3
);
3685 REG_NOTES (last
) = gen_rtx_EXPR_LIST (REG_EQUAL
, gsym
,
3687 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3689 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
3695 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3697 r3
= gen_rtx_REG (Pmode
, 3);
3699 insn
= gen_tls_gd_64 (r3
, got
, addr
);
3701 insn
= gen_tls_gd_32 (r3
, got
, addr
);
3704 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3705 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3706 insn
= emit_call_insn (insn
);
3707 CONST_OR_PURE_CALL_P (insn
) = 1;
3708 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3709 insn
= get_insns ();
3711 emit_libcall_block (insn
, dest
, r3
, addr
);
3713 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3715 r3
= gen_rtx_REG (Pmode
, 3);
3717 insn
= gen_tls_ld_64 (r3
, got
);
3719 insn
= gen_tls_ld_32 (r3
, got
);
3722 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3723 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3724 insn
= emit_call_insn (insn
);
3725 CONST_OR_PURE_CALL_P (insn
) = 1;
3726 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3727 insn
= get_insns ();
3729 tmp1
= gen_reg_rtx (Pmode
);
3730 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3732 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3733 if (rs6000_tls_size
== 16)
3736 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3738 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3740 else if (rs6000_tls_size
== 32)
3742 tmp2
= gen_reg_rtx (Pmode
);
3744 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3746 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3749 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3751 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
3755 tmp2
= gen_reg_rtx (Pmode
);
3757 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
3759 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
3761 insn
= gen_rtx_SET (Pmode
, dest
,
3762 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
3768 /* IE, or 64 bit offset LE. */
3769 tmp2
= gen_reg_rtx (Pmode
);
3771 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
3773 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
3776 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
3778 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
3786 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3787 instruction definitions. */
3790 rs6000_tls_symbol_ref (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3792 return RS6000_SYMBOL_REF_TLS_P (x
);
3795 /* Return 1 if X contains a thread-local symbol. */
3798 rs6000_tls_referenced_p (rtx x
)
3800 if (! TARGET_HAVE_TLS
)
3803 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
3806 /* Return 1 if *X is a thread-local symbol. This is the same as
3807 rs6000_tls_symbol_ref except for the type of the unused argument. */
3810 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3812 return RS6000_SYMBOL_REF_TLS_P (*x
);
3815 /* The convention appears to be to define this wherever it is used.
3816 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3817 is now used here. */
3818 #ifndef REG_MODE_OK_FOR_BASE_P
3819 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3822 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3823 replace the input X, or the original X if no replacement is called for.
3824 The output parameter *WIN is 1 if the calling macro should goto WIN,
3827 For RS/6000, we wish to handle large displacements off a base
3828 register by splitting the addend across an addiu/addis and the mem insn.
3829 This cuts number of extra insns needed from 3 to 1.
3831 On Darwin, we use this to generate code for floating point constants.
3832 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3833 The Darwin code is inside #if TARGET_MACHO because only then is
3834 machopic_function_base_name() defined. */
3836 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3837 int opnum
, int type
,
3838 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3840 /* We must recognize output that we have already generated ourselves. */
3841 if (GET_CODE (x
) == PLUS
3842 && GET_CODE (XEXP (x
, 0)) == PLUS
3843 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3844 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3845 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3847 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3848 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3849 opnum
, (enum reload_type
)type
);
3855 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
3856 && GET_CODE (x
) == LO_SUM
3857 && GET_CODE (XEXP (x
, 0)) == PLUS
3858 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
3859 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
3860 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
3861 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
3862 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
3863 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
3864 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
3866 /* Result of previous invocation of this function on Darwin
3867 floating point constant. */
3868 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3869 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3870 opnum
, (enum reload_type
)type
);
3876 /* Force ld/std non-word aligned offset into base register by wrapping
3878 if (GET_CODE (x
) == PLUS
3879 && GET_CODE (XEXP (x
, 0)) == REG
3880 && REGNO (XEXP (x
, 0)) < 32
3881 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3882 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3883 && (INTVAL (XEXP (x
, 1)) & 3) != 0
3884 && !ALTIVEC_VECTOR_MODE (mode
)
3885 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
3886 && TARGET_POWERPC64
)
3888 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
3889 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3890 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3891 opnum
, (enum reload_type
) type
);
3896 if (GET_CODE (x
) == PLUS
3897 && GET_CODE (XEXP (x
, 0)) == REG
3898 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3899 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3900 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3901 && !SPE_VECTOR_MODE (mode
)
3902 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
3904 && !ALTIVEC_VECTOR_MODE (mode
))
3906 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
3907 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
3909 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3911 /* Check for 32-bit overflow. */
3912 if (high
+ low
!= val
)
3918 /* Reload the high part into a base reg; leave the low part
3919 in the mem directly. */
3921 x
= gen_rtx_PLUS (GET_MODE (x
),
3922 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
3926 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3927 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3928 opnum
, (enum reload_type
)type
);
3934 if (GET_CODE (x
) == SYMBOL_REF
3935 && DEFAULT_ABI
== ABI_DARWIN
3936 && !ALTIVEC_VECTOR_MODE (mode
)
3937 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
3938 /* Don't do this for TFmode, since the result isn't offsettable.
3939 The same goes for DImode without 64-bit gprs. */
3941 && (mode
!= DImode
|| TARGET_POWERPC64
))
3945 rtx offset
= gen_rtx_CONST (Pmode
,
3946 gen_rtx_MINUS (Pmode
, x
,
3947 machopic_function_base_sym ()));
3948 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3949 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3950 gen_rtx_HIGH (Pmode
, offset
)), offset
);
3953 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3954 gen_rtx_HIGH (Pmode
, x
), x
);
3956 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3957 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3958 opnum
, (enum reload_type
)type
);
3965 && constant_pool_expr_p (x
)
3966 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
3968 (x
) = create_TOC_reference (x
);
3976 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3977 that is a valid memory address for an instruction.
3978 The MODE argument is the machine mode for the MEM expression
3979 that wants to use this address.
3981 On the RS/6000, there are four valid address: a SYMBOL_REF that
3982 refers to a constant pool entry of an address (or the sum of it
3983 plus a constant), a short (16-bit signed) constant plus a register,
3984 the sum of two registers, or a register indirect, possibly with an
3985 auto-increment. For DFmode and DImode with a constant plus register,
3986 we must ensure that both words are addressable or PowerPC64 with offset
3989 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3990 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3991 adjacent memory cells are accessed by adding word-sized offsets
3992 during assembly output. */
3994 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
3996 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3998 && ALTIVEC_VECTOR_MODE (mode
)
3999 && GET_CODE (x
) == AND
4000 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4001 && INTVAL (XEXP (x
, 1)) == -16)
4004 if (RS6000_SYMBOL_REF_TLS_P (x
))
4006 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
4008 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
4009 && !ALTIVEC_VECTOR_MODE (mode
)
4010 && !SPE_VECTOR_MODE (mode
)
4011 /* Restrict addressing for DI because of our SUBREG hackery. */
4012 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
4014 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
4016 if (legitimate_small_data_p (mode
, x
))
4018 if (legitimate_constant_pool_address_p (x
))
4020 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4022 && GET_CODE (x
) == PLUS
4023 && GET_CODE (XEXP (x
, 0)) == REG
4024 && (XEXP (x
, 0) == virtual_stack_vars_rtx
4025 || XEXP (x
, 0) == arg_pointer_rtx
)
4026 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4028 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
4032 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4034 || ((mode
!= DFmode
|| TARGET_E500_DOUBLE
) && mode
!= TFmode
))
4035 && (TARGET_POWERPC64
|| mode
!= DImode
)
4036 && legitimate_indexed_address_p (x
, reg_ok_strict
))
4038 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4043 /* Go to LABEL if ADDR (a legitimate address expression)
4044 has an effect that depends on the machine mode it is used for.
4046 On the RS/6000 this is true of all integral offsets (since AltiVec
4047 modes don't allow them) or is a pre-increment or decrement.
4049 ??? Except that due to conceptual problems in offsettable_address_p
4050 we can't really report the problems of integral offsets. So leave
4051 this assuming that the adjustable offset must be valid for the
4052 sub-words of a TFmode operand, which is what we had before. */
4055 rs6000_mode_dependent_address (rtx addr
)
4057 switch (GET_CODE (addr
))
4060 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4062 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4063 return val
+ 12 + 0x8000 >= 0x10000;
4072 return TARGET_UPDATE
;
4081 /* Return number of consecutive hard regs needed starting at reg REGNO
4082 to hold something of mode MODE.
4083 This is ordinarily the length in words of a value of mode MODE
4084 but can be less for certain modes in special long registers.
4086 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4087 scalar instructions. The upper 32 bits are only available to the
4090 POWER and PowerPC GPRs hold 32 bits worth;
4091 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4094 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4096 if (FP_REGNO_P (regno
))
4097 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4099 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
4102 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4103 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4105 if (ALTIVEC_REGNO_P (regno
))
4107 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4109 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4112 /* Change register usage conditional on target flags. */
4114 rs6000_conditional_register_usage (void)
4118 /* Set MQ register fixed (already call_used) if not POWER
4119 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4124 /* 64-bit AIX reserves GPR13 for thread-private data. */
4126 fixed_regs
[13] = call_used_regs
[13]
4127 = call_really_used_regs
[13] = 1;
4129 /* Conditionally disable FPRs. */
4130 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4131 for (i
= 32; i
< 64; i
++)
4132 fixed_regs
[i
] = call_used_regs
[i
]
4133 = call_really_used_regs
[i
] = 1;
4135 if (DEFAULT_ABI
== ABI_V4
4136 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4138 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4140 if (DEFAULT_ABI
== ABI_V4
4141 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4143 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4144 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4145 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4147 if (DEFAULT_ABI
== ABI_DARWIN
4148 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4149 global_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4150 = fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4151 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4152 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4154 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4155 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4156 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4159 global_regs
[VSCR_REGNO
] = 1;
4163 global_regs
[SPEFSCR_REGNO
] = 1;
4164 fixed_regs
[FIXED_SCRATCH
]
4165 = call_used_regs
[FIXED_SCRATCH
]
4166 = call_really_used_regs
[FIXED_SCRATCH
] = 1;
4169 if (! TARGET_ALTIVEC
)
4171 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4172 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4173 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4176 if (TARGET_ALTIVEC_ABI
)
4177 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4178 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4181 /* Try to output insns to set TARGET equal to the constant C if it can
4182 be done in less than N insns. Do all computations in MODE.
4183 Returns the place where the output has been placed if it can be
4184 done and the insns have been emitted. If it would take more than N
4185 insns, zero is returned and no insns and emitted. */
4188 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4189 rtx source
, int n ATTRIBUTE_UNUSED
)
4191 rtx result
, insn
, set
;
4192 HOST_WIDE_INT c0
, c1
;
4194 if (mode
== QImode
|| mode
== HImode
)
4197 dest
= gen_reg_rtx (mode
);
4198 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4201 else if (mode
== SImode
)
4203 result
= no_new_pseudos
? dest
: gen_reg_rtx (SImode
);
4205 emit_insn (gen_rtx_SET (VOIDmode
, result
,
4206 GEN_INT (INTVAL (source
)
4207 & (~ (HOST_WIDE_INT
) 0xffff))));
4208 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4209 gen_rtx_IOR (SImode
, result
,
4210 GEN_INT (INTVAL (source
) & 0xffff))));
4213 else if (mode
== DImode
)
4215 if (GET_CODE (source
) == CONST_INT
)
4217 c0
= INTVAL (source
);
4220 else if (GET_CODE (source
) == CONST_DOUBLE
)
4222 #if HOST_BITS_PER_WIDE_INT >= 64
4223 c0
= CONST_DOUBLE_LOW (source
);
4226 c0
= CONST_DOUBLE_LOW (source
);
4227 c1
= CONST_DOUBLE_HIGH (source
);
4233 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4238 insn
= get_last_insn ();
4239 set
= single_set (insn
);
4240 if (! CONSTANT_P (SET_SRC (set
)))
4241 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4246 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4247 fall back to a straight forward decomposition. We do this to avoid
4248 exponential run times encountered when looking for longer sequences
4249 with rs6000_emit_set_const. */
4251 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4253 if (!TARGET_POWERPC64
)
4255 rtx operand1
, operand2
;
4257 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4259 operand2
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
4261 emit_move_insn (operand1
, GEN_INT (c1
));
4262 emit_move_insn (operand2
, GEN_INT (c2
));
4266 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4269 ud2
= (c1
& 0xffff0000) >> 16;
4270 #if HOST_BITS_PER_WIDE_INT >= 64
4274 ud4
= (c2
& 0xffff0000) >> 16;
4276 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4277 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4280 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4282 emit_move_insn (dest
, GEN_INT (ud1
));
4285 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4286 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4289 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4292 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4294 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4296 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4297 || (ud4
== 0 && ! (ud3
& 0x8000)))
4300 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4303 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4306 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud2
)));
4307 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (16)));
4309 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4314 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4317 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4320 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud3
)));
4322 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (32)));
4324 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
,
4325 GEN_INT (ud2
<< 16)));
4327 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4333 /* Helper for the following. Get rid of [r+r] memory refs
4334 in cases where it won't work (TImode, TFmode). */
4337 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4339 if (GET_CODE (operands
[0]) == MEM
4340 && GET_CODE (XEXP (operands
[0], 0)) != REG
4341 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4342 && ! reload_in_progress
)
4344 = replace_equiv_address (operands
[0],
4345 copy_addr_to_reg (XEXP (operands
[0], 0)));
4347 if (GET_CODE (operands
[1]) == MEM
4348 && GET_CODE (XEXP (operands
[1], 0)) != REG
4349 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4350 && ! reload_in_progress
)
4352 = replace_equiv_address (operands
[1],
4353 copy_addr_to_reg (XEXP (operands
[1], 0)));
4356 /* Emit a move from SOURCE to DEST in mode MODE. */
4358 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4362 operands
[1] = source
;
4364 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4365 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4366 && ! FLOAT_MODE_P (mode
)
4367 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4369 /* FIXME. This should never happen. */
4370 /* Since it seems that it does, do the safe thing and convert
4372 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4374 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4375 && ! FLOAT_MODE_P (mode
)
4376 && ((CONST_DOUBLE_HIGH (operands
[1]) == 0
4377 && CONST_DOUBLE_LOW (operands
[1]) >= 0)
4378 || (CONST_DOUBLE_HIGH (operands
[1]) == -1
4379 && CONST_DOUBLE_LOW (operands
[1]) < 0)))
4382 /* Check if GCC is setting up a block move that will end up using FP
4383 registers as temporaries. We must make sure this is acceptable. */
4384 if (GET_CODE (operands
[0]) == MEM
4385 && GET_CODE (operands
[1]) == MEM
4387 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4388 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4389 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4390 ? 32 : MEM_ALIGN (operands
[0])))
4391 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4393 : MEM_ALIGN (operands
[1]))))
4394 && ! MEM_VOLATILE_P (operands
[0])
4395 && ! MEM_VOLATILE_P (operands
[1]))
4397 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4398 adjust_address (operands
[1], SImode
, 0));
4399 emit_move_insn (adjust_address (operands
[0], SImode
, 4),
4400 adjust_address (operands
[1], SImode
, 4));
4404 if (!no_new_pseudos
&& GET_CODE (operands
[0]) == MEM
4405 && !gpc_reg_operand (operands
[1], mode
))
4406 operands
[1] = force_reg (mode
, operands
[1]);
4408 if (mode
== SFmode
&& ! TARGET_POWERPC
4409 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4410 && GET_CODE (operands
[0]) == MEM
)
4414 if (reload_in_progress
|| reload_completed
)
4415 regnum
= true_regnum (operands
[1]);
4416 else if (GET_CODE (operands
[1]) == REG
)
4417 regnum
= REGNO (operands
[1]);
4421 /* If operands[1] is a register, on POWER it may have
4422 double-precision data in it, so truncate it to single
4424 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4427 newreg
= (no_new_pseudos
? operands
[1] : gen_reg_rtx (mode
));
4428 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4429 operands
[1] = newreg
;
4433 /* Recognize the case where operand[1] is a reference to thread-local
4434 data and load its address to a register. */
4435 if (GET_CODE (operands
[1]) == SYMBOL_REF
)
4437 enum tls_model model
= SYMBOL_REF_TLS_MODEL (operands
[1]);
4439 operands
[1] = rs6000_legitimize_tls_address (operands
[1], model
);
4442 /* Handle the case where reload calls us with an invalid address. */
4443 if (reload_in_progress
&& mode
== Pmode
4444 && (! general_operand (operands
[1], mode
)
4445 || ! nonimmediate_operand (operands
[0], mode
)))
4448 /* 128-bit constant floating-point values on Darwin should really be
4449 loaded as two parts. */
4450 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
4451 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
4452 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4454 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4455 know how to get a DFmode SUBREG of a TFmode. */
4456 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
, 0),
4457 simplify_gen_subreg (DImode
, operands
[1], mode
, 0),
4459 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
,
4460 GET_MODE_SIZE (DImode
)),
4461 simplify_gen_subreg (DImode
, operands
[1], mode
,
4462 GET_MODE_SIZE (DImode
)),
4467 /* FIXME: In the long term, this switch statement should go away
4468 and be replaced by a sequence of tests based on things like
4474 if (CONSTANT_P (operands
[1])
4475 && GET_CODE (operands
[1]) != CONST_INT
)
4476 operands
[1] = force_const_mem (mode
, operands
[1]);
4480 rs6000_eliminate_indexed_memrefs (operands
);
4485 if (CONSTANT_P (operands
[1])
4486 && ! easy_fp_constant (operands
[1], mode
))
4487 operands
[1] = force_const_mem (mode
, operands
[1]);
4498 if (CONSTANT_P (operands
[1])
4499 && !easy_vector_constant (operands
[1], mode
))
4500 operands
[1] = force_const_mem (mode
, operands
[1]);
4505 /* Use default pattern for address of ELF small data */
4508 && DEFAULT_ABI
== ABI_V4
4509 && (GET_CODE (operands
[1]) == SYMBOL_REF
4510 || GET_CODE (operands
[1]) == CONST
)
4511 && small_data_operand (operands
[1], mode
))
4513 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4517 if (DEFAULT_ABI
== ABI_V4
4518 && mode
== Pmode
&& mode
== SImode
4519 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4521 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4525 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4529 && CONSTANT_P (operands
[1])
4530 && GET_CODE (operands
[1]) != HIGH
4531 && GET_CODE (operands
[1]) != CONST_INT
)
4533 rtx target
= (no_new_pseudos
? operands
[0] : gen_reg_rtx (mode
));
4535 /* If this is a function address on -mcall-aixdesc,
4536 convert it to the address of the descriptor. */
4537 if (DEFAULT_ABI
== ABI_AIX
4538 && GET_CODE (operands
[1]) == SYMBOL_REF
4539 && XSTR (operands
[1], 0)[0] == '.')
4541 const char *name
= XSTR (operands
[1], 0);
4543 while (*name
== '.')
4545 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4546 CONSTANT_POOL_ADDRESS_P (new_ref
)
4547 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4548 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4549 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4550 SYMBOL_REF_DECL (new_ref
) = SYMBOL_REF_DECL (operands
[1]);
4551 operands
[1] = new_ref
;
4554 if (DEFAULT_ABI
== ABI_DARWIN
)
4557 if (MACHO_DYNAMIC_NO_PIC_P
)
4559 /* Take care of any required data indirection. */
4560 operands
[1] = rs6000_machopic_legitimize_pic_address (
4561 operands
[1], mode
, operands
[0]);
4562 if (operands
[0] != operands
[1])
4563 emit_insn (gen_rtx_SET (VOIDmode
,
4564 operands
[0], operands
[1]));
4568 emit_insn (gen_macho_high (target
, operands
[1]));
4569 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
4573 emit_insn (gen_elf_high (target
, operands
[1]));
4574 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
4578 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4579 and we have put it in the TOC, we just need to make a TOC-relative
4582 && GET_CODE (operands
[1]) == SYMBOL_REF
4583 && constant_pool_expr_p (operands
[1])
4584 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
4585 get_pool_mode (operands
[1])))
4587 operands
[1] = create_TOC_reference (operands
[1]);
4589 else if (mode
== Pmode
4590 && CONSTANT_P (operands
[1])
4591 && ((GET_CODE (operands
[1]) != CONST_INT
4592 && ! easy_fp_constant (operands
[1], mode
))
4593 || (GET_CODE (operands
[1]) == CONST_INT
4594 && num_insns_constant (operands
[1], mode
) > 2)
4595 || (GET_CODE (operands
[0]) == REG
4596 && FP_REGNO_P (REGNO (operands
[0]))))
4597 && GET_CODE (operands
[1]) != HIGH
4598 && ! legitimate_constant_pool_address_p (operands
[1])
4599 && ! toc_relative_expr_p (operands
[1]))
4601 /* Emit a USE operation so that the constant isn't deleted if
4602 expensive optimizations are turned on because nobody
4603 references it. This should only be done for operands that
4604 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4605 This should not be done for operands that contain LABEL_REFs.
4606 For now, we just handle the obvious case. */
4607 if (GET_CODE (operands
[1]) != LABEL_REF
)
4608 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
4611 /* Darwin uses a special PIC legitimizer. */
4612 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
4615 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
4617 if (operands
[0] != operands
[1])
4618 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4623 /* If we are to limit the number of things we put in the TOC and
4624 this is a symbol plus a constant we can add in one insn,
4625 just put the symbol in the TOC and add the constant. Don't do
4626 this if reload is in progress. */
4627 if (GET_CODE (operands
[1]) == CONST
4628 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
4629 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
4630 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
4631 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
4632 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
4633 && ! side_effects_p (operands
[0]))
4636 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
4637 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
4639 sym
= force_reg (mode
, sym
);
4641 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
4643 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
4647 operands
[1] = force_const_mem (mode
, operands
[1]);
4650 && constant_pool_expr_p (XEXP (operands
[1], 0))
4651 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4652 get_pool_constant (XEXP (operands
[1], 0)),
4653 get_pool_mode (XEXP (operands
[1], 0))))
4656 = gen_const_mem (mode
,
4657 create_TOC_reference (XEXP (operands
[1], 0)));
4658 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
4664 rs6000_eliminate_indexed_memrefs (operands
);
4668 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4670 gen_rtx_SET (VOIDmode
,
4671 operands
[0], operands
[1]),
4672 gen_rtx_CLOBBER (VOIDmode
,
4673 gen_rtx_SCRATCH (SImode
)))));
4682 /* Above, we may have called force_const_mem which may have returned
4683 an invalid address. If we can, fix this up; otherwise, reload will
4684 have to deal with it. */
4685 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
4686 operands
[1] = validize_mem (operands
[1]);
4689 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4692 /* Nonzero if we can use a floating-point register to pass this arg. */
4693 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4694 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4695 && (CUM)->fregno <= FP_ARG_MAX_REG \
4696 && TARGET_HARD_FLOAT && TARGET_FPRS)
4698 /* Nonzero if we can use an AltiVec register to pass this arg. */
4699 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4700 (ALTIVEC_VECTOR_MODE (MODE) \
4701 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4702 && TARGET_ALTIVEC_ABI \
4705 /* Return a nonzero value to say to return the function value in
4706 memory, just as large structures are always returned. TYPE will be
4707 the data type of the value, and FNTYPE will be the type of the
4708 function doing the returning, or @code{NULL} for libcalls.
4710 The AIX ABI for the RS/6000 specifies that all structures are
4711 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4712 specifies that structures <= 8 bytes are returned in r3/r4, but a
4713 draft put them in memory, and GCC used to implement the draft
4714 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4715 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4716 compatibility can change DRAFT_V4_STRUCT_RET to override the
4717 default, and -m switches get the final word. See
4718 rs6000_override_options for more details.
4720 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4721 long double support is enabled. These values are returned in memory.
4723 int_size_in_bytes returns -1 for variable size objects, which go in
4724 memory always. The cast to unsigned makes -1 > 8. */
4727 rs6000_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
4729 /* In the darwin64 abi, try to use registers for larger structs
4731 if (AGGREGATE_TYPE_P (type
)
4732 && rs6000_darwin64_abi
4733 && TREE_CODE (type
) == RECORD_TYPE
4734 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 32)
4735 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 0))
4738 if (AGGREGATE_TYPE_P (type
)
4739 && (TARGET_AIX_STRUCT_RET
4740 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
4743 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4744 modes only exist for GCC vector types if -maltivec. */
4745 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
4746 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
4749 /* Return synthetic vectors in memory. */
4750 if (TREE_CODE (type
) == VECTOR_TYPE
4751 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
4753 static bool warned_for_return_big_vectors
= false;
4754 if (!warned_for_return_big_vectors
)
4756 warning ("GCC vector returned by reference: "
4757 "non-standard ABI extension with no compatibility guarantee");
4758 warned_for_return_big_vectors
= true;
4763 if (DEFAULT_ABI
== ABI_V4
&& TYPE_MODE (type
) == TFmode
)
4769 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4770 for a call to a function whose data type is FNTYPE.
4771 For a library call, FNTYPE is 0.
4773 For incoming args we set the number of arguments in the prototype large
4774 so we never return a PARALLEL. */
4777 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
4778 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
4779 int libcall
, int n_named_args
)
4781 static CUMULATIVE_ARGS zero_cumulative
;
4783 *cum
= zero_cumulative
;
4785 cum
->fregno
= FP_ARG_MIN_REG
;
4786 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
4787 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4788 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
4789 ? CALL_LIBCALL
: CALL_NORMAL
);
4790 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
4791 cum
->stdarg
= fntype
4792 && (TYPE_ARG_TYPES (fntype
) != 0
4793 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4794 != void_type_node
));
4796 cum
->nargs_prototype
= 0;
4797 if (incoming
|| cum
->prototype
)
4798 cum
->nargs_prototype
= n_named_args
;
4800 /* Check for a longcall attribute. */
4801 if ((!fntype
&& rs6000_default_long_calls
)
4803 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
4804 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
4805 cum
->call_cookie
|= CALL_LONG
;
4807 if (TARGET_DEBUG_ARG
)
4809 fprintf (stderr
, "\ninit_cumulative_args:");
4812 tree ret_type
= TREE_TYPE (fntype
);
4813 fprintf (stderr
, " ret code = %s,",
4814 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
4817 if (cum
->call_cookie
& CALL_LONG
)
4818 fprintf (stderr
, " longcall,");
4820 fprintf (stderr
, " proto = %d, nargs = %d\n",
4821 cum
->prototype
, cum
->nargs_prototype
);
4826 && TARGET_ALTIVEC_ABI
4827 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
4829 error ("Cannot return value in vector register because"
4830 " altivec instructions are disabled, use -maltivec"
4831 " to enable them.");
4835 /* Return true if TYPE must be passed on the stack and not in registers. */
4838 rs6000_must_pass_in_stack (enum machine_mode mode
, tree type
)
4840 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
4841 return must_pass_in_stack_var_size (mode
, type
);
4843 return must_pass_in_stack_var_size_or_pad (mode
, type
);
4846 /* If defined, a C expression which determines whether, and in which
4847 direction, to pad out an argument with extra space. The value
4848 should be of type `enum direction': either `upward' to pad above
4849 the argument, `downward' to pad below, or `none' to inhibit
4852 For the AIX ABI structs are always stored left shifted in their
4856 function_arg_padding (enum machine_mode mode
, tree type
)
4858 #ifndef AGGREGATE_PADDING_FIXED
4859 #define AGGREGATE_PADDING_FIXED 0
4861 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4862 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4865 if (!AGGREGATE_PADDING_FIXED
)
4867 /* GCC used to pass structures of the same size as integer types as
4868 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4869 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4870 passed padded downward, except that -mstrict-align further
4871 muddied the water in that multi-component structures of 2 and 4
4872 bytes in size were passed padded upward.
4874 The following arranges for best compatibility with previous
4875 versions of gcc, but removes the -mstrict-align dependency. */
4876 if (BYTES_BIG_ENDIAN
)
4878 HOST_WIDE_INT size
= 0;
4880 if (mode
== BLKmode
)
4882 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4883 size
= int_size_in_bytes (type
);
4886 size
= GET_MODE_SIZE (mode
);
4888 if (size
== 1 || size
== 2 || size
== 4)
4894 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
4896 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
4900 /* Fall back to the default. */
4901 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
4904 /* If defined, a C expression that gives the alignment boundary, in bits,
4905 of an argument with the specified mode and type. If it is not defined,
4906 PARM_BOUNDARY is used for all arguments.
4908 V.4 wants long longs to be double word aligned.
4909 Doubleword align SPE vectors.
4910 Quadword align Altivec vectors.
4911 Quadword align large synthetic vector types. */
4914 function_arg_boundary (enum machine_mode mode
, tree type
)
4916 if (DEFAULT_ABI
== ABI_V4
&& GET_MODE_SIZE (mode
) == 8)
4918 else if (SPE_VECTOR_MODE (mode
)
4919 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4920 && int_size_in_bytes (type
) >= 8
4921 && int_size_in_bytes (type
) < 16))
4923 else if (ALTIVEC_VECTOR_MODE (mode
)
4924 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4925 && int_size_in_bytes (type
) >= 16))
4928 return PARM_BOUNDARY
;
4931 /* Compute the size (in words) of a function argument. */
4933 static unsigned long
4934 rs6000_arg_size (enum machine_mode mode
, tree type
)
4938 if (mode
!= BLKmode
)
4939 size
= GET_MODE_SIZE (mode
);
4941 size
= int_size_in_bytes (type
);
4944 return (size
+ 3) >> 2;
4946 return (size
+ 7) >> 3;
4949 /* The darwin64 ABI calls for us to recurse down through structs,
4950 applying the same rules to struct elements as if a reference to
4951 each were being passed directly. */
4954 darwin64_function_arg_advance (CUMULATIVE_ARGS
*cum
, tree type
,
4955 int named
, int depth
)
4960 switch (TREE_CODE (type
))
4963 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
4964 if (TREE_CODE (f
) == FIELD_DECL
)
4966 ftype
= TREE_TYPE (f
);
4967 function_arg_advance (cum
, TYPE_MODE (ftype
), ftype
,
4973 tot
= int_size_in_bytes (type
);
4976 ftype
= TREE_TYPE (type
);
4977 tot
/= int_size_in_bytes (ftype
);
4979 for (i
= 0; i
< tot
; ++i
)
4981 function_arg_advance (cum
, TYPE_MODE (ftype
), ftype
,
4991 /* Update the data in CUM to advance over an argument
4992 of mode MODE and data type TYPE.
4993 (TYPE is null for libcalls where that information may not be available.)
4995 Note that for args passed by reference, function_arg will be called
4996 with MODE and TYPE set to that of the pointer to the arg, not the arg
5000 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5001 tree type
, int named
, int depth
)
5003 /* Only tick off an argument if we're not recursing. */
5005 cum
->nargs_prototype
--;
5007 if (TARGET_ALTIVEC_ABI
5008 && (ALTIVEC_VECTOR_MODE (mode
)
5009 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5010 && int_size_in_bytes (type
) == 16)))
5014 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5017 if (!TARGET_ALTIVEC
)
5018 error ("Cannot pass argument in vector register because"
5019 " altivec instructions are disabled, use -maltivec"
5020 " to enable them.");
5022 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5023 even if it is going to be passed in a vector register.
5024 Darwin does the same for variable-argument functions. */
5025 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5026 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5036 /* Vector parameters must be 16-byte aligned. This places
5037 them at 2 mod 4 in terms of words in 32-bit mode, since
5038 the parameter save area starts at offset 24 from the
5039 stack. In 64-bit mode, they just have to start on an
5040 even word, since the parameter save area is 16-byte
5041 aligned. Space for GPRs is reserved even if the argument
5042 will be passed in memory. */
5044 align
= (2 - cum
->words
) & 3;
5046 align
= cum
->words
& 1;
5047 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5049 if (TARGET_DEBUG_ARG
)
5051 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5053 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5054 cum
->nargs_prototype
, cum
->prototype
,
5055 GET_MODE_NAME (mode
));
5059 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5061 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5064 else if (rs6000_darwin64_abi
5066 && (TREE_CODE (type
) == RECORD_TYPE
5067 || TREE_CODE (type
) == ARRAY_TYPE
))
5068 darwin64_function_arg_advance (cum
, type
, named
, depth
);
5070 else if (DEFAULT_ABI
== ABI_V4
)
5072 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5073 && (mode
== SFmode
|| mode
== DFmode
))
5075 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
5080 cum
->words
+= cum
->words
& 1;
5081 cum
->words
+= rs6000_arg_size (mode
, type
);
5086 int n_words
= rs6000_arg_size (mode
, type
);
5087 int gregno
= cum
->sysv_gregno
;
5089 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5090 (r7,r8) or (r9,r10). As does any other 2 word item such
5091 as complex int due to a historical mistake. */
5093 gregno
+= (1 - gregno
) & 1;
5095 /* Multi-reg args are not split between registers and stack. */
5096 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5098 /* Long long and SPE vectors are aligned on the stack.
5099 So are other 2 word items such as complex int due to
5100 a historical mistake. */
5102 cum
->words
+= cum
->words
& 1;
5103 cum
->words
+= n_words
;
5106 /* Note: continuing to accumulate gregno past when we've started
5107 spilling to the stack indicates the fact that we've started
5108 spilling to the stack to expand_builtin_saveregs. */
5109 cum
->sysv_gregno
= gregno
+ n_words
;
5112 if (TARGET_DEBUG_ARG
)
5114 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5115 cum
->words
, cum
->fregno
);
5116 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5117 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5118 fprintf (stderr
, "mode = %4s, named = %d\n",
5119 GET_MODE_NAME (mode
), named
);
5124 int n_words
= rs6000_arg_size (mode
, type
);
5125 int align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5127 /* The simple alignment calculation here works because
5128 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
5129 If we ever want to handle alignments larger than 8 bytes for
5130 32-bit or 16 bytes for 64-bit, then we'll need to take into
5131 account the offset to the start of the parm save area. */
5132 align
&= cum
->words
;
5133 cum
->words
+= align
+ n_words
;
5135 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5136 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5137 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5139 if (TARGET_DEBUG_ARG
)
5141 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5142 cum
->words
, cum
->fregno
);
5143 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5144 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5145 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5146 named
, align
, depth
);
5152 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5158 r1
= gen_rtx_REG (DImode
, gregno
);
5159 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5160 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5162 else if (mode
== DCmode
)
5164 r1
= gen_rtx_REG (DImode
, gregno
);
5165 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5166 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5167 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5168 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5174 /* Determine where to put a SIMD argument on the SPE. */
5176 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5179 int gregno
= cum
->sysv_gregno
;
5181 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5182 are passed and returned in a pair of GPRs for ABI compatibility. */
5183 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DCmode
))
5185 int n_words
= rs6000_arg_size (mode
, type
);
5187 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5189 gregno
+= (1 - gregno
) & 1;
5191 /* Multi-reg args are not split between registers and stack. */
5192 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5195 return spe_build_register_parallel (mode
, gregno
);
5199 int n_words
= rs6000_arg_size (mode
, type
);
5201 /* SPE vectors are put in odd registers. */
5202 if (n_words
== 2 && (gregno
& 1) == 0)
5205 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5208 enum machine_mode m
= SImode
;
5210 r1
= gen_rtx_REG (m
, gregno
);
5211 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5212 r2
= gen_rtx_REG (m
, gregno
+ 1);
5213 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5214 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5221 if (gregno
<= GP_ARG_MAX_REG
)
5222 return gen_rtx_REG (mode
, gregno
);
5228 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5229 the register(s) to be used for each field and subfield of a struct
5230 being passed by value, along with the offset of where the
5231 register's value may be found in the block. */
5234 rs6000_darwin64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5235 tree type
, int named
)
5237 tree f
, ftype
, offset
;
5238 rtx rvec
[FIRST_PSEUDO_REGISTER
], sub
, suboff
, roffset
;
5239 int k
= 0, i
, j
, bytepos
, subbytepos
, tot
;
5240 CUMULATIVE_ARGS saved_cum
= *cum
;
5241 enum machine_mode submode
;
5243 switch (TREE_CODE (type
))
5246 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5247 if (TREE_CODE (f
) == FIELD_DECL
)
5249 ftype
= TREE_TYPE (f
);
5250 offset
= DECL_FIELD_OFFSET (f
);
5251 bytepos
= int_bit_position (f
) / BITS_PER_UNIT
;
5252 /* Force substructs to be handled as BLKmode even if
5253 they're small enough to be recorded as DImode, so we
5254 drill through to non-record fields. */
5255 submode
= TYPE_MODE (ftype
);
5256 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5258 sub
= function_arg (cum
, submode
, ftype
, named
);
5259 if (sub
== NULL_RTX
)
5261 if (GET_CODE (sub
) == PARALLEL
)
5263 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
5265 rtx subsub
= XVECEXP (sub
, 0, i
);
5266 suboff
= XEXP (subsub
, 1);
5267 subbytepos
= INTVAL (suboff
);
5268 subbytepos
+= bytepos
;
5269 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
5270 subsub
= XEXP (subsub
, 0);
5271 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
5276 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
5277 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
5279 /* Now do an arg advance to get all the cumulative arg
5280 stuff set correctly for the next subfield. Note that it
5281 has no lasting effect, because it is being done on a
5282 temporary copy of the cumulative arg data. */
5283 function_arg_advance (cum
, submode
, ftype
, named
, 1);
5288 tot
= rs6000_arg_size (mode
, type
);
5293 for (j
= 0; j
< tot
; ++j
)
5295 sub
= gen_rtx_REG ((TARGET_64BIT
? DImode
: SImode
), GP_ARG_MIN_REG
+ cum
->words
++);
5296 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
5297 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
5298 if (cum
->words
>= GP_ARG_NUM_REG
)
5300 bytepos
+= (TARGET_64BIT
? 8 : 4);
5305 tot
= int_size_in_bytes (type
);
5308 ftype
= TREE_TYPE (type
);
5309 tot
/= int_size_in_bytes (ftype
);
5312 for (j
= 0; j
< tot
; ++j
)
5314 /* Force substructs to be handled as BLKmode even if
5315 they're small enough to be recorded as DImode, so we
5316 drill through to non-record fields. */
5317 submode
= TYPE_MODE (ftype
);
5318 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5320 sub
= function_arg (cum
, submode
, ftype
, named
);
5321 if (sub
== NULL_RTX
)
5323 if (GET_CODE (sub
) == PARALLEL
)
5325 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
5327 rtx subsub
= XVECEXP (sub
, 0, i
);
5329 suboff
= XEXP (subsub
, 1);
5330 subbytepos
= INTVAL (suboff
);
5331 subbytepos
+= bytepos
;
5332 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
5333 subsub
= XEXP (subsub
, 0);
5334 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
5339 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
5340 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
5342 /* Now do an arg advance to get all the cumulative arg
5343 stuff set correctly for the next subfield. Note that it
5344 has no lasting effect, because it is being done on a
5345 temporary copy of the cumulative arg data. */
5346 function_arg_advance (cum
, submode
, ftype
, named
, 1);
5347 bytepos
+= int_size_in_bytes (ftype
);
5357 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5362 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5365 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
5369 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5371 if (align_words
>= GP_ARG_NUM_REG
)
5374 n_units
= rs6000_arg_size (mode
, type
);
5376 /* Optimize the simple case where the arg fits in one gpr, except in
5377 the case of BLKmode due to assign_parms assuming that registers are
5378 BITS_PER_WORD wide. */
5380 || (n_units
== 1 && mode
!= BLKmode
))
5381 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5384 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
5385 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5386 using a magic NULL_RTX component.
5387 FIXME: This is not strictly correct. Only some of the arg
5388 belongs in memory, not all of it. However, there isn't any way
5389 to do this currently, apart from building rtx descriptions for
5390 the pieces of memory we want stored. Due to bugs in the generic
5391 code we can't use the normal function_arg_partial_nregs scheme
5392 with the PARALLEL arg description we emit here.
5393 In any case, the code to store the whole arg to memory is often
5394 more efficient than code to store pieces, and we know that space
5395 is available in the right place for the whole arg. */
5396 /* FIXME: This should be fixed since the conversion to
5397 TARGET_ARG_PARTIAL_BYTES. */
5398 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5403 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
5404 rtx off
= GEN_INT (i
++ * 4);
5405 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5407 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
5409 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5412 /* Determine where to put an argument to a function.
5413 Value is zero to push the argument on the stack,
5414 or a hard register in which to store the argument.
5416 MODE is the argument's machine mode.
5417 TYPE is the data type of the argument (as a tree).
5418 This is null for libcalls where that information may
5420 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5421 the preceding args and about the function being called.
5422 NAMED is nonzero if this argument is a named parameter
5423 (otherwise it is an extra parameter matching an ellipsis).
5425 On RS/6000 the first eight words of non-FP are normally in registers
5426 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5427 Under V.4, the first 8 FP args are in registers.
5429 If this is floating-point and no prototype is specified, we use
5430 both an FP and integer register (or possibly FP reg and stack). Library
5431 functions (when CALL_LIBCALL is set) always have the proper types for args,
5432 so we can pass the FP value just in one register. emit_library_function
5433 doesn't support PARALLEL anyway.
5435 Note that for args passed by reference, function_arg will be called
5436 with MODE and TYPE set to that of the pointer to the arg, not the arg
5440 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5441 tree type
, int named
)
5443 enum rs6000_abi abi
= DEFAULT_ABI
;
5445 /* Return a marker to indicate whether CR1 needs to set or clear the
5446 bit that V.4 uses to say fp args were passed in registers.
5447 Assume that we don't need the marker for software floating point,
5448 or compiler generated library calls. */
5449 if (mode
== VOIDmode
)
5452 && cum
->nargs_prototype
< 0
5453 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
5454 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))
5456 /* For the SPE, we need to crxor CR6 always. */
5458 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
5459 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5460 return GEN_INT (cum
->call_cookie
5461 | ((cum
->fregno
== FP_ARG_MIN_REG
)
5462 ? CALL_V4_SET_FP_ARGS
5463 : CALL_V4_CLEAR_FP_ARGS
));
5466 return GEN_INT (cum
->call_cookie
);
5470 && rs6000_darwin64_abi
5471 && (TREE_CODE (type
) == RECORD_TYPE
5472 || TREE_CODE (type
) == UNION_TYPE
5473 || TREE_CODE (type
) == ARRAY_TYPE
))
5475 rtx rslt
= rs6000_darwin64_function_arg (cum
, mode
, type
, named
);
5476 if (rslt
!= NULL_RTX
)
5478 /* Else fall through to usual handling. */
5481 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5482 if (TARGET_64BIT
&& ! cum
->prototype
)
5484 /* Vector parameters get passed in vector register
5485 and also in GPRs or memory, in absence of prototype. */
5488 align_words
= (cum
->words
+ 1) & ~1;
5490 if (align_words
>= GP_ARG_NUM_REG
)
5496 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5498 return gen_rtx_PARALLEL (mode
,
5500 gen_rtx_EXPR_LIST (VOIDmode
,
5502 gen_rtx_EXPR_LIST (VOIDmode
,
5503 gen_rtx_REG (mode
, cum
->vregno
),
5507 return gen_rtx_REG (mode
, cum
->vregno
);
5508 else if (TARGET_ALTIVEC_ABI
5509 && (ALTIVEC_VECTOR_MODE (mode
)
5510 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5511 && int_size_in_bytes (type
) == 16)))
5513 if (named
|| abi
== ABI_V4
)
5517 /* Vector parameters to varargs functions under AIX or Darwin
5518 get passed in memory and possibly also in GPRs. */
5519 int align
, align_words
, n_words
;
5520 enum machine_mode part_mode
;
5522 /* Vector parameters must be 16-byte aligned. This places them at
5523 2 mod 4 in terms of words in 32-bit mode, since the parameter
5524 save area starts at offset 24 from the stack. In 64-bit mode,
5525 they just have to start on an even word, since the parameter
5526 save area is 16-byte aligned. */
5528 align
= (2 - cum
->words
) & 3;
5530 align
= cum
->words
& 1;
5531 align_words
= cum
->words
+ align
;
5533 /* Out of registers? Memory, then. */
5534 if (align_words
>= GP_ARG_NUM_REG
)
5537 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5538 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5540 /* The vector value goes in GPRs. Only the part of the
5541 value in GPRs is reported here. */
5543 n_words
= rs6000_arg_size (mode
, type
);
5544 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
5545 /* Fortunately, there are only two possibilities, the value
5546 is either wholly in GPRs or half in GPRs and half not. */
5549 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
5552 else if (TARGET_SPE_ABI
&& TARGET_SPE
5553 && (SPE_VECTOR_MODE (mode
)
5554 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
5555 || mode
== DCmode
))))
5556 return rs6000_spe_function_arg (cum
, mode
, type
);
5558 else if (abi
== ABI_V4
)
5560 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5561 && (mode
== SFmode
|| mode
== DFmode
))
5563 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
5564 return gen_rtx_REG (mode
, cum
->fregno
);
5570 int n_words
= rs6000_arg_size (mode
, type
);
5571 int gregno
= cum
->sysv_gregno
;
5573 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5574 (r7,r8) or (r9,r10). As does any other 2 word item such
5575 as complex int due to a historical mistake. */
5577 gregno
+= (1 - gregno
) & 1;
5579 /* Multi-reg args are not split between registers and stack. */
5580 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5583 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5584 return rs6000_mixed_function_arg (mode
, type
,
5585 gregno
- GP_ARG_MIN_REG
);
5586 return gen_rtx_REG (mode
, gregno
);
5591 int align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5592 int align_words
= cum
->words
+ (cum
->words
& align
);
5594 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
5596 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5600 enum machine_mode fmode
= mode
;
5601 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
5603 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
5605 /* Currently, we only ever need one reg here because complex
5606 doubles are split. */
5607 if (cum
->fregno
!= FP_ARG_MAX_REG
|| fmode
!= TFmode
)
5610 /* Long double split over regs and memory. */
5614 /* Do we also need to pass this arg in the parameter save
5617 && (cum
->nargs_prototype
<= 0
5618 || (DEFAULT_ABI
== ABI_AIX
5620 && align_words
>= GP_ARG_NUM_REG
)));
5622 if (!needs_psave
&& mode
== fmode
)
5623 return gen_rtx_REG (fmode
, cum
->fregno
);
5628 /* Describe the part that goes in gprs or the stack.
5629 This piece must come first, before the fprs. */
5630 if (align_words
< GP_ARG_NUM_REG
)
5632 unsigned long n_words
= rs6000_arg_size (mode
, type
);
5634 if (align_words
+ n_words
> GP_ARG_NUM_REG
5635 || (TARGET_32BIT
&& TARGET_POWERPC64
))
5637 /* If this is partially on the stack, then we only
5638 include the portion actually in registers here. */
5639 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
5642 if (align_words
+ n_words
> GP_ARG_NUM_REG
5643 && (TARGET_32BIT
&& TARGET_POWERPC64
))
5644 /* Not all of the arg fits in gprs. Say that it
5645 goes in memory too, using a magic NULL_RTX
5646 component. Also see comment in
5647 rs6000_mixed_function_arg for why the normal
5648 function_arg_partial_nregs scheme doesn't work
5650 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
5654 r
= gen_rtx_REG (rmode
,
5655 GP_ARG_MIN_REG
+ align_words
);
5656 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
5657 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5659 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
5663 /* The whole arg fits in gprs. */
5664 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5665 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5669 /* It's entirely in memory. */
5670 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5673 /* Describe where this piece goes in the fprs. */
5674 r
= gen_rtx_REG (fmode
, cum
->fregno
);
5675 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5677 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5679 else if (align_words
< GP_ARG_NUM_REG
)
5681 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5682 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5684 if (mode
== BLKmode
)
5687 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5694 /* For an arg passed partly in registers and partly in memory, this is
5695 the number of registers used. For args passed entirely in registers
5696 or entirely in memory, zero. When an arg is described by a PARALLEL,
5697 perhaps using more than one register type, this function returns the
5698 number of bytes of registers used by the PARALLEL. */
5701 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5702 tree type
, bool named
)
5709 if (DEFAULT_ABI
== ABI_V4
)
5712 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
5713 && cum
->nargs_prototype
>= 0)
5716 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5717 parm_offset
= TARGET_32BIT
? 2 : 0;
5718 align_words
= cum
->words
+ ((parm_offset
- cum
->words
) & align
);
5720 if (USE_FP_FOR_ARG_P (cum
, mode
, type
)
5721 /* If we are passing this arg in gprs as well, then this function
5722 should return the number of gprs (or memory) partially passed,
5723 *not* the number of fprs. */
5725 && (cum
->nargs_prototype
<= 0
5726 || (DEFAULT_ABI
== ABI_AIX
5728 && align_words
>= GP_ARG_NUM_REG
))))
5730 if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3) > FP_ARG_MAX_REG
+ 1)
5731 ret
= FP_ARG_MAX_REG
+ 1 - cum
->fregno
;
5732 else if (cum
->nargs_prototype
>= 0)
5736 if (align_words
< GP_ARG_NUM_REG
5737 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
5738 ret
= GP_ARG_NUM_REG
- align_words
;
5740 ret
*= (TARGET_32BIT
? 4 : 8);
5742 if (ret
!= 0 && TARGET_DEBUG_ARG
)
5743 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
5748 /* A C expression that indicates when an argument must be passed by
5749 reference. If nonzero for an argument, a copy of that argument is
5750 made in memory and a pointer to the argument is passed instead of
5751 the argument itself. The pointer is passed in whatever way is
5752 appropriate for passing a pointer to that type.
5754 Under V.4, aggregates and long double are passed by reference.
5756 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5757 reference unless the AltiVec vector extension ABI is in force.
5759 As an extension to all ABIs, variable sized types are passed by
5763 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5764 enum machine_mode mode
, tree type
,
5765 bool named ATTRIBUTE_UNUSED
)
5767 if (DEFAULT_ABI
== ABI_V4
&& mode
== TFmode
)
5769 if (TARGET_DEBUG_ARG
)
5770 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
5777 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
5779 if (TARGET_DEBUG_ARG
)
5780 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
5784 if (int_size_in_bytes (type
) < 0)
5786 if (TARGET_DEBUG_ARG
)
5787 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
5791 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5792 modes only exist for GCC vector types if -maltivec. */
5793 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
5795 if (TARGET_DEBUG_ARG
)
5796 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
5800 /* Pass synthetic vectors in memory. */
5801 if (TREE_CODE (type
) == VECTOR_TYPE
5802 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5804 static bool warned_for_pass_big_vectors
= false;
5805 if (TARGET_DEBUG_ARG
)
5806 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
5807 if (!warned_for_pass_big_vectors
)
5809 warning ("GCC vector passed by reference: "
5810 "non-standard ABI extension with no compatibility guarantee");
5811 warned_for_pass_big_vectors
= true;
5820 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
5823 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
5828 for (i
= 0; i
< nregs
; i
++)
5830 rtx tem
= adjust_address_nv (x
, reg_mode
, i
*GET_MODE_SIZE(reg_mode
));
5831 if (reload_completed
)
5833 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
5836 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
5837 i
* GET_MODE_SIZE(reg_mode
));
5840 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
5842 if (tem
== NULL_RTX
)
5845 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
5849 /* Perform any needed actions needed for a function that is receiving a
5850 variable number of arguments.
5854 MODE and TYPE are the mode and type of the current parameter.
5856 PRETEND_SIZE is a variable that should be set to the amount of stack
5857 that must be pushed by the prolog to pretend that our caller pushed
5860 Normally, this macro will push all remaining incoming registers on the
5861 stack and set PRETEND_SIZE to the length of the registers pushed. */
5864 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5865 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5868 CUMULATIVE_ARGS next_cum
;
5869 int reg_size
= TARGET_32BIT
? 4 : 8;
5870 rtx save_area
= NULL_RTX
, mem
;
5871 int first_reg_offset
, set
;
5873 /* Skip the last named argument. */
5875 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
5877 if (DEFAULT_ABI
== ABI_V4
)
5880 save_area
= plus_constant (virtual_stack_vars_rtx
,
5881 - RS6000_VARARGS_SIZE
);
5883 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
5887 first_reg_offset
= next_cum
.words
;
5888 save_area
= virtual_incoming_args_rtx
;
5890 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5891 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
5894 set
= get_varargs_alias_set ();
5895 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
)
5897 mem
= gen_rtx_MEM (BLKmode
,
5898 plus_constant (save_area
,
5899 first_reg_offset
* reg_size
)),
5900 set_mem_alias_set (mem
, set
);
5901 set_mem_align (mem
, BITS_PER_WORD
);
5903 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
5904 GP_ARG_NUM_REG
- first_reg_offset
);
5907 /* Save FP registers if needed. */
5908 if (DEFAULT_ABI
== ABI_V4
5909 && TARGET_HARD_FLOAT
&& TARGET_FPRS
5911 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
)
5913 int fregno
= next_cum
.fregno
;
5914 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
5915 rtx lab
= gen_label_rtx ();
5916 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
) * 8);
5919 (gen_rtx_SET (VOIDmode
,
5921 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5922 gen_rtx_NE (VOIDmode
, cr1
,
5924 gen_rtx_LABEL_REF (VOIDmode
, lab
),
5927 while (fregno
<= FP_ARG_V4_MAX_REG
)
5929 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
5930 set_mem_alias_set (mem
, set
);
5931 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
5932 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
5941 /* Create the va_list data type. */
5944 rs6000_build_builtin_va_list (void)
5946 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
5948 /* For AIX, prefer 'char *' because that's what the system
5949 header files like. */
5950 if (DEFAULT_ABI
!= ABI_V4
)
5951 return build_pointer_type (char_type_node
);
5953 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5954 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5956 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
5957 unsigned_char_type_node
);
5958 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
5959 unsigned_char_type_node
);
5960 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5962 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
5963 short_unsigned_type_node
);
5964 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
5966 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
5969 DECL_FIELD_CONTEXT (f_gpr
) = record
;
5970 DECL_FIELD_CONTEXT (f_fpr
) = record
;
5971 DECL_FIELD_CONTEXT (f_res
) = record
;
5972 DECL_FIELD_CONTEXT (f_ovf
) = record
;
5973 DECL_FIELD_CONTEXT (f_sav
) = record
;
5975 TREE_CHAIN (record
) = type_decl
;
5976 TYPE_NAME (record
) = type_decl
;
5977 TYPE_FIELDS (record
) = f_gpr
;
5978 TREE_CHAIN (f_gpr
) = f_fpr
;
5979 TREE_CHAIN (f_fpr
) = f_res
;
5980 TREE_CHAIN (f_res
) = f_ovf
;
5981 TREE_CHAIN (f_ovf
) = f_sav
;
5983 layout_type (record
);
5985 /* The correct type is an array type of one element. */
5986 return build_array_type (record
, build_index_type (size_zero_node
));
5989 /* Implement va_start. */
5992 rs6000_va_start (tree valist
, rtx nextarg
)
5994 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
5995 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5996 tree gpr
, fpr
, ovf
, sav
, t
;
5998 /* Only SVR4 needs something special. */
5999 if (DEFAULT_ABI
!= ABI_V4
)
6001 std_expand_builtin_va_start (valist
, nextarg
);
6005 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6006 f_fpr
= TREE_CHAIN (f_gpr
);
6007 f_res
= TREE_CHAIN (f_fpr
);
6008 f_ovf
= TREE_CHAIN (f_res
);
6009 f_sav
= TREE_CHAIN (f_ovf
);
6011 valist
= build_va_arg_indirect_ref (valist
);
6012 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6013 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6014 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6015 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6017 /* Count number of gp and fp argument registers used. */
6018 words
= current_function_args_info
.words
;
6019 n_gpr
= MIN (current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
,
6021 n_fpr
= MIN (current_function_args_info
.fregno
- FP_ARG_MIN_REG
,
6024 if (TARGET_DEBUG_ARG
)
6025 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6026 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6027 words
, n_gpr
, n_fpr
);
6029 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
6030 build_int_cst (NULL_TREE
, n_gpr
));
6031 TREE_SIDE_EFFECTS (t
) = 1;
6032 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6034 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
6035 build_int_cst (NULL_TREE
, n_fpr
));
6036 TREE_SIDE_EFFECTS (t
) = 1;
6037 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6039 /* Find the overflow area. */
6040 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6042 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6043 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
6044 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6045 TREE_SIDE_EFFECTS (t
) = 1;
6046 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6048 /* Find the register save area. */
6049 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6050 t
= build (PLUS_EXPR
, TREE_TYPE (sav
), t
,
6051 build_int_cst (NULL_TREE
, -RS6000_VARARGS_SIZE
));
6052 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
6053 TREE_SIDE_EFFECTS (t
) = 1;
6054 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6057 /* Implement va_arg. */
6060 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6062 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6063 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6064 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6065 tree lab_false
, lab_over
, addr
;
6067 tree ptrtype
= build_pointer_type (type
);
6069 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6071 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6072 return build_va_arg_indirect_ref (t
);
6075 if (DEFAULT_ABI
!= ABI_V4
)
6077 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6079 tree elem_type
= TREE_TYPE (type
);
6080 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6081 int elem_size
= GET_MODE_SIZE (elem_mode
);
6083 if (elem_size
< UNITS_PER_WORD
)
6085 tree real_part
, imag_part
;
6086 tree post
= NULL_TREE
;
6088 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6090 /* Copy the value into a temporary, lest the formal temporary
6091 be reused out from under us. */
6092 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
6093 append_to_statement_list (post
, pre_p
);
6095 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6098 return build (COMPLEX_EXPR
, type
, real_part
, imag_part
);
6102 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6105 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6106 f_fpr
= TREE_CHAIN (f_gpr
);
6107 f_res
= TREE_CHAIN (f_fpr
);
6108 f_ovf
= TREE_CHAIN (f_res
);
6109 f_sav
= TREE_CHAIN (f_ovf
);
6111 valist
= build_va_arg_indirect_ref (valist
);
6112 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6113 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6114 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6115 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6117 size
= int_size_in_bytes (type
);
6118 rsize
= (size
+ 3) / 4;
6121 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6122 && (TYPE_MODE (type
) == SFmode
|| TYPE_MODE (type
) == DFmode
))
6124 /* FP args go in FP registers, if present. */
6129 if (TYPE_MODE (type
) == DFmode
)
6134 /* Otherwise into GP registers. */
6143 /* Pull the value out of the saved registers.... */
6146 addr
= create_tmp_var (ptr_type_node
, "addr");
6147 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
6149 /* AltiVec vectors never go in registers when -mabi=altivec. */
6150 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
6154 lab_false
= create_artificial_label ();
6155 lab_over
= create_artificial_label ();
6157 /* Long long and SPE vectors are aligned in the registers.
6158 As are any other 2 gpr item such as complex int due to a
6159 historical mistake. */
6163 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
6164 size_int (n_reg
- 1));
6165 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
6168 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
6169 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
6170 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
6171 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
6172 gimplify_and_add (t
, pre_p
);
6176 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
6178 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, size_int (n_reg
));
6179 u
= build1 (CONVERT_EXPR
, integer_type_node
, u
);
6180 u
= build2 (MULT_EXPR
, integer_type_node
, u
, size_int (sav_scale
));
6181 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
, u
);
6183 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
6184 gimplify_and_add (t
, pre_p
);
6186 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
6187 gimplify_and_add (t
, pre_p
);
6189 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
6190 append_to_statement_list (t
, pre_p
);
6194 /* Ensure that we don't find any more args in regs.
6195 Alignment has taken care of the n_reg == 2 case. */
6196 t
= build (MODIFY_EXPR
, TREE_TYPE (reg
), reg
, size_int (8));
6197 gimplify_and_add (t
, pre_p
);
6201 /* ... otherwise out of the overflow area. */
6203 /* Care for on-stack alignment if needed. */
6207 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
6208 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
6209 build_int_cst (NULL_TREE
, -align
));
6211 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
6213 u
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
6214 gimplify_and_add (u
, pre_p
);
6216 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6217 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6218 gimplify_and_add (t
, pre_p
);
6222 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
6223 append_to_statement_list (t
, pre_p
);
6226 addr
= fold_convert (ptrtype
, addr
);
6227 return build_va_arg_indirect_ref (addr
);
6232 #define def_builtin(MASK, NAME, TYPE, CODE) \
6234 if ((MASK) & target_flags) \
6235 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6239 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6241 static const struct builtin_description bdesc_3arg
[] =
6243 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
6244 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
6245 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
6246 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
6247 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
6248 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
6249 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
6250 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
6251 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
6252 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
6253 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
6254 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
6255 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
6256 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
6257 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
6258 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
6259 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
6260 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
6261 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
6262 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
6263 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
6264 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
6265 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
6268 /* DST operations: void foo (void *, const int, const char). */
6270 static const struct builtin_description bdesc_dst
[] =
6272 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
6273 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
6274 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
6275 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
}
6278 /* Simple binary operations: VECc = foo (VECa, VECb). */
6280 static struct builtin_description bdesc_2arg
[] =
6282 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
6283 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
6284 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
6285 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
6286 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
6287 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
6288 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
6289 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
6290 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
6291 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
6292 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
6293 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
6294 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
6295 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
6296 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
6297 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
6298 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
6299 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
6300 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
6301 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
6302 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
6303 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
6304 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
6305 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
6306 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
6307 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
6308 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
6309 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
6310 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
6311 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
6312 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
6313 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
6314 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
6315 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
6316 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
6317 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
6318 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
6319 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
6320 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
6321 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
6322 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
6323 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
6324 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
6325 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
6326 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
6327 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
6328 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
6329 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
6330 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
6331 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
6332 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
6333 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
6334 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
6335 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
6336 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
6337 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
6338 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
6339 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
6340 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
6341 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
6342 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
6343 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
6344 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
6345 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
6346 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
6347 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
6348 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
6349 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
6350 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
6351 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhss
, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS
},
6352 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
6353 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwss
, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS
},
6354 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
6355 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
6356 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
6357 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
6358 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
6359 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
6360 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
6361 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
6362 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
6363 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
6364 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
6365 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
6366 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
6367 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
6368 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
6369 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
6370 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrb
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
6371 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrh
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
6372 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrw
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
6373 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrab
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
6374 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrah
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
6375 { MASK_ALTIVEC
, CODE_FOR_altivec_vsraw
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
6376 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
6377 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
6378 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
6379 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
6380 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
6381 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
6382 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
6383 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
6384 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
6385 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
6386 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
6387 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
6388 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
6389 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
6390 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
6391 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
6392 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
6393 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
6394 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
6396 /* Place holder, leave as first spe builtin. */
6397 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
6398 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
6399 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
6400 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
6401 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
6402 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
6403 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
6404 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
6405 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
6406 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
6407 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
6408 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
6409 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
6410 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
6411 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
6412 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
6413 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
6414 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
6415 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
6416 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
6417 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
6418 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
6419 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
6420 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
6421 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
6422 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
6423 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
6424 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
6425 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
6426 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
6427 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
6428 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
6429 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
6430 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
6431 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
6432 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
6433 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
6434 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
6435 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
6436 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
6437 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
6438 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
6439 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
6440 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
6441 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
6442 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
6443 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
6444 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
6445 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
6446 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
6447 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
6448 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
6449 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
6450 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
6451 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
6452 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
6453 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
6454 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
6455 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
6456 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
6457 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
6458 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
6459 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
6460 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
6461 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
6462 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
6463 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
6464 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
6465 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
6466 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
6467 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
6468 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
6469 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
6470 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
6471 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
6472 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
6473 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
6474 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
6475 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
6476 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
6477 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
6478 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
6479 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
6480 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
6481 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
6482 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
6483 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
6484 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
6485 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
6486 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
6487 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
6488 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
6489 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
6490 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
6491 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
6492 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
6493 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
6494 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
6495 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
6496 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
6497 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
6498 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
6499 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
6500 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
6501 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
6502 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
6503 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
6504 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
6505 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
6507 /* SPE binary operations expecting a 5-bit unsigned literal. */
6508 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
6510 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
6511 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
6512 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
6513 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
6514 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
6515 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
6516 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
6517 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
6518 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
6519 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
6520 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
6521 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
6522 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
6523 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
6524 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
6525 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
6526 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
6527 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
6528 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
6529 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
6530 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
6531 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
6532 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
6533 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
6534 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
6535 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
6537 /* Place-holder. Leave as last binary SPE builtin. */
6538 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
},
6541 /* AltiVec predicates. */
6543 struct builtin_description_predicates
6545 const unsigned int mask
;
6546 const enum insn_code icode
;
6548 const char *const name
;
6549 const enum rs6000_builtins code
;
6552 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
6554 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
6555 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
6556 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
6557 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
6558 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
6559 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
6560 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
6561 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
6562 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
6563 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
6564 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
6565 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
6566 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
}
6569 /* SPE predicates. */
6570 static struct builtin_description bdesc_spe_predicates
[] =
6572 /* Place-holder. Leave as first. */
6573 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
6574 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
6575 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
6576 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
6577 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
6578 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
6579 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
6580 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
6581 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
6582 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
6583 /* Place-holder. Leave as last. */
6584 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
6587 /* SPE evsel predicates. */
6588 static struct builtin_description bdesc_spe_evsel
[] =
6590 /* Place-holder. Leave as first. */
6591 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
6592 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
6593 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
6594 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
6595 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
6596 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
6597 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
6598 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
6599 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
6600 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
6601 /* Place-holder. Leave as last. */
6602 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
6605 /* ABS* operations. */
6607 static const struct builtin_description bdesc_abs
[] =
6609 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
6610 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
6611 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
6612 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
6613 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
6614 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
6615 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
6618 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6621 static struct builtin_description bdesc_1arg
[] =
6623 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
6624 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
6625 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
6626 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
6627 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
6628 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
6629 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
6630 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
6631 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
6632 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
6633 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
6634 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
6635 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
6636 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
6637 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
6638 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
6639 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
6641 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6642 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6643 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
6644 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
6645 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
6646 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
6647 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
6648 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
6649 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
6650 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
6651 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
6652 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
6653 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
6654 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
6655 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
6656 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
6657 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
6658 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
6659 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
6660 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
6661 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
6662 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
6663 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
6664 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
6665 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
6666 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
6667 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
6668 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
6669 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
6670 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
6672 /* Place-holder. Leave as last unary SPE builtin. */
6673 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
6677 rs6000_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6680 tree arg0
= TREE_VALUE (arglist
);
6681 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6682 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6683 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6685 if (icode
== CODE_FOR_nothing
)
6686 /* Builtin not supported on this processor. */
6689 /* If we got invalid arguments bail out before generating bad rtl. */
6690 if (arg0
== error_mark_node
)
6693 if (icode
== CODE_FOR_altivec_vspltisb
6694 || icode
== CODE_FOR_altivec_vspltish
6695 || icode
== CODE_FOR_altivec_vspltisw
6696 || icode
== CODE_FOR_spe_evsplatfi
6697 || icode
== CODE_FOR_spe_evsplati
)
6699 /* Only allow 5-bit *signed* literals. */
6700 if (GET_CODE (op0
) != CONST_INT
6701 || INTVAL (op0
) > 0x1f
6702 || INTVAL (op0
) < -0x1f)
6704 error ("argument 1 must be a 5-bit signed literal");
6710 || GET_MODE (target
) != tmode
6711 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6712 target
= gen_reg_rtx (tmode
);
6714 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6715 op0
= copy_to_mode_reg (mode0
, op0
);
6717 pat
= GEN_FCN (icode
) (target
, op0
);
6726 altivec_expand_abs_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6728 rtx pat
, scratch1
, scratch2
;
6729 tree arg0
= TREE_VALUE (arglist
);
6730 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6731 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6732 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6734 /* If we have invalid arguments, bail out before generating bad rtl. */
6735 if (arg0
== error_mark_node
)
6739 || GET_MODE (target
) != tmode
6740 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6741 target
= gen_reg_rtx (tmode
);
6743 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6744 op0
= copy_to_mode_reg (mode0
, op0
);
6746 scratch1
= gen_reg_rtx (mode0
);
6747 scratch2
= gen_reg_rtx (mode0
);
6749 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
6758 rs6000_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6761 tree arg0
= TREE_VALUE (arglist
);
6762 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6763 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6764 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6765 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6766 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6767 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6769 if (icode
== CODE_FOR_nothing
)
6770 /* Builtin not supported on this processor. */
6773 /* If we got invalid arguments bail out before generating bad rtl. */
6774 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6777 if (icode
== CODE_FOR_altivec_vcfux
6778 || icode
== CODE_FOR_altivec_vcfsx
6779 || icode
== CODE_FOR_altivec_vctsxs
6780 || icode
== CODE_FOR_altivec_vctuxs
6781 || icode
== CODE_FOR_altivec_vspltb
6782 || icode
== CODE_FOR_altivec_vsplth
6783 || icode
== CODE_FOR_altivec_vspltw
6784 || icode
== CODE_FOR_spe_evaddiw
6785 || icode
== CODE_FOR_spe_evldd
6786 || icode
== CODE_FOR_spe_evldh
6787 || icode
== CODE_FOR_spe_evldw
6788 || icode
== CODE_FOR_spe_evlhhesplat
6789 || icode
== CODE_FOR_spe_evlhhossplat
6790 || icode
== CODE_FOR_spe_evlhhousplat
6791 || icode
== CODE_FOR_spe_evlwhe
6792 || icode
== CODE_FOR_spe_evlwhos
6793 || icode
== CODE_FOR_spe_evlwhou
6794 || icode
== CODE_FOR_spe_evlwhsplat
6795 || icode
== CODE_FOR_spe_evlwwsplat
6796 || icode
== CODE_FOR_spe_evrlwi
6797 || icode
== CODE_FOR_spe_evslwi
6798 || icode
== CODE_FOR_spe_evsrwis
6799 || icode
== CODE_FOR_spe_evsubifw
6800 || icode
== CODE_FOR_spe_evsrwiu
)
6802 /* Only allow 5-bit unsigned literals. */
6804 if (TREE_CODE (arg1
) != INTEGER_CST
6805 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6807 error ("argument 2 must be a 5-bit unsigned literal");
6813 || GET_MODE (target
) != tmode
6814 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6815 target
= gen_reg_rtx (tmode
);
6817 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6818 op0
= copy_to_mode_reg (mode0
, op0
);
6819 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6820 op1
= copy_to_mode_reg (mode1
, op1
);
6822 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6831 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
6832 tree arglist
, rtx target
)
6835 tree cr6_form
= TREE_VALUE (arglist
);
6836 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
6837 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6838 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6839 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6840 enum machine_mode tmode
= SImode
;
6841 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6842 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6845 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
6847 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6851 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
6856 /* If we have invalid arguments, bail out before generating bad rtl. */
6857 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6861 || GET_MODE (target
) != tmode
6862 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6863 target
= gen_reg_rtx (tmode
);
6865 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6866 op0
= copy_to_mode_reg (mode0
, op0
);
6867 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6868 op1
= copy_to_mode_reg (mode1
, op1
);
6870 scratch
= gen_reg_rtx (mode0
);
6872 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
6873 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
6878 /* The vec_any* and vec_all* predicates use the same opcodes for two
6879 different operations, but the bits in CR6 will be different
6880 depending on what information we want. So we have to play tricks
6881 with CR6 to get the right bits out.
6883 If you think this is disgusting, look at the specs for the
6884 AltiVec predicates. */
6886 switch (cr6_form_int
)
6889 emit_insn (gen_cr6_test_for_zero (target
));
6892 emit_insn (gen_cr6_test_for_zero_reverse (target
));
6895 emit_insn (gen_cr6_test_for_lt (target
));
6898 emit_insn (gen_cr6_test_for_lt_reverse (target
));
6901 error ("argument 1 of __builtin_altivec_predicate is out of range");
6909 altivec_expand_lv_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6912 tree arg0
= TREE_VALUE (arglist
);
6913 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6914 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6915 enum machine_mode mode0
= Pmode
;
6916 enum machine_mode mode1
= Pmode
;
6917 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6918 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6920 if (icode
== CODE_FOR_nothing
)
6921 /* Builtin not supported on this processor. */
6924 /* If we got invalid arguments bail out before generating bad rtl. */
6925 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6929 || GET_MODE (target
) != tmode
6930 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6931 target
= gen_reg_rtx (tmode
);
6933 op1
= copy_to_mode_reg (mode1
, op1
);
6935 if (op0
== const0_rtx
)
6937 addr
= gen_rtx_MEM (tmode
, op1
);
6941 op0
= copy_to_mode_reg (mode0
, op0
);
6942 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
6945 pat
= GEN_FCN (icode
) (target
, addr
);
6955 spe_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6957 tree arg0
= TREE_VALUE (arglist
);
6958 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6959 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6960 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6961 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6962 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6964 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
6965 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
6966 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
6968 /* Invalid arguments. Bail before doing anything stoopid! */
6969 if (arg0
== error_mark_node
6970 || arg1
== error_mark_node
6971 || arg2
== error_mark_node
)
6974 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
6975 op0
= copy_to_mode_reg (mode2
, op0
);
6976 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
6977 op1
= copy_to_mode_reg (mode0
, op1
);
6978 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
6979 op2
= copy_to_mode_reg (mode1
, op2
);
6981 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
6988 altivec_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6990 tree arg0
= TREE_VALUE (arglist
);
6991 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6992 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6993 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6994 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6995 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6997 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6998 enum machine_mode mode1
= Pmode
;
6999 enum machine_mode mode2
= Pmode
;
7001 /* Invalid arguments. Bail before doing anything stoopid! */
7002 if (arg0
== error_mark_node
7003 || arg1
== error_mark_node
7004 || arg2
== error_mark_node
)
7007 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
7008 op0
= copy_to_mode_reg (tmode
, op0
);
7010 op2
= copy_to_mode_reg (mode2
, op2
);
7012 if (op1
== const0_rtx
)
7014 addr
= gen_rtx_MEM (tmode
, op2
);
7018 op1
= copy_to_mode_reg (mode1
, op1
);
7019 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
7022 pat
= GEN_FCN (icode
) (addr
, op0
);
7029 rs6000_expand_ternop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7032 tree arg0
= TREE_VALUE (arglist
);
7033 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7034 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7035 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7036 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7037 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7038 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7039 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7040 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7041 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
7043 if (icode
== CODE_FOR_nothing
)
7044 /* Builtin not supported on this processor. */
7047 /* If we got invalid arguments bail out before generating bad rtl. */
7048 if (arg0
== error_mark_node
7049 || arg1
== error_mark_node
7050 || arg2
== error_mark_node
)
7053 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
7054 || icode
== CODE_FOR_altivec_vsldoi_v4si
7055 || icode
== CODE_FOR_altivec_vsldoi_v8hi
7056 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
7058 /* Only allow 4-bit unsigned literals. */
7060 if (TREE_CODE (arg2
) != INTEGER_CST
7061 || TREE_INT_CST_LOW (arg2
) & ~0xf)
7063 error ("argument 3 must be a 4-bit unsigned literal");
7069 || GET_MODE (target
) != tmode
7070 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7071 target
= gen_reg_rtx (tmode
);
7073 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7074 op0
= copy_to_mode_reg (mode0
, op0
);
7075 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7076 op1
= copy_to_mode_reg (mode1
, op1
);
7077 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
7078 op2
= copy_to_mode_reg (mode2
, op2
);
7080 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
7088 /* Expand the lvx builtins. */
7090 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
7092 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7093 tree arglist
= TREE_OPERAND (exp
, 1);
7094 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7096 enum machine_mode tmode
, mode0
;
7098 enum insn_code icode
;
7102 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
7103 icode
= CODE_FOR_altivec_lvx_v16qi
;
7105 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
7106 icode
= CODE_FOR_altivec_lvx_v8hi
;
7108 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
7109 icode
= CODE_FOR_altivec_lvx_v4si
;
7111 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
7112 icode
= CODE_FOR_altivec_lvx_v4sf
;
7121 arg0
= TREE_VALUE (arglist
);
7122 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7123 tmode
= insn_data
[icode
].operand
[0].mode
;
7124 mode0
= insn_data
[icode
].operand
[1].mode
;
7127 || GET_MODE (target
) != tmode
7128 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7129 target
= gen_reg_rtx (tmode
);
7131 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7132 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7134 pat
= GEN_FCN (icode
) (target
, op0
);
7141 /* Expand the stvx builtins. */
7143 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7146 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7147 tree arglist
= TREE_OPERAND (exp
, 1);
7148 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7150 enum machine_mode mode0
, mode1
;
7152 enum insn_code icode
;
7156 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
7157 icode
= CODE_FOR_altivec_stvx_v16qi
;
7159 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
7160 icode
= CODE_FOR_altivec_stvx_v8hi
;
7162 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
7163 icode
= CODE_FOR_altivec_stvx_v4si
;
7165 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
7166 icode
= CODE_FOR_altivec_stvx_v4sf
;
7173 arg0
= TREE_VALUE (arglist
);
7174 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7175 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7176 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7177 mode0
= insn_data
[icode
].operand
[0].mode
;
7178 mode1
= insn_data
[icode
].operand
[1].mode
;
7180 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7181 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7182 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7183 op1
= copy_to_mode_reg (mode1
, op1
);
7185 pat
= GEN_FCN (icode
) (op0
, op1
);
7193 /* Expand the dst builtins. */
7195 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7198 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7199 tree arglist
= TREE_OPERAND (exp
, 1);
7200 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7201 tree arg0
, arg1
, arg2
;
7202 enum machine_mode mode0
, mode1
, mode2
;
7203 rtx pat
, op0
, op1
, op2
;
7204 struct builtin_description
*d
;
7209 /* Handle DST variants. */
7210 d
= (struct builtin_description
*) bdesc_dst
;
7211 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
7212 if (d
->code
== fcode
)
7214 arg0
= TREE_VALUE (arglist
);
7215 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7216 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7217 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7218 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7219 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7220 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7221 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7222 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7224 /* Invalid arguments, bail out before generating bad rtl. */
7225 if (arg0
== error_mark_node
7226 || arg1
== error_mark_node
7227 || arg2
== error_mark_node
)
7232 if (TREE_CODE (arg2
) != INTEGER_CST
7233 || TREE_INT_CST_LOW (arg2
) & ~0x3)
7235 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
7239 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
7240 op0
= copy_to_mode_reg (Pmode
, op0
);
7241 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
7242 op1
= copy_to_mode_reg (mode1
, op1
);
7244 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
7254 /* Expand the builtin in EXP and store the result in TARGET. Store
7255 true in *EXPANDEDP if we found a builtin to expand. */
7257 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
7259 struct builtin_description
*d
;
7260 struct builtin_description_predicates
*dp
;
7262 enum insn_code icode
;
7263 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7264 tree arglist
= TREE_OPERAND (exp
, 1);
7267 enum machine_mode tmode
, mode0
;
7268 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7270 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
7274 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
7278 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
7286 case ALTIVEC_BUILTIN_STVX
:
7287 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, arglist
);
7288 case ALTIVEC_BUILTIN_STVEBX
:
7289 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, arglist
);
7290 case ALTIVEC_BUILTIN_STVEHX
:
7291 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, arglist
);
7292 case ALTIVEC_BUILTIN_STVEWX
:
7293 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, arglist
);
7294 case ALTIVEC_BUILTIN_STVXL
:
7295 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, arglist
);
7297 case ALTIVEC_BUILTIN_MFVSCR
:
7298 icode
= CODE_FOR_altivec_mfvscr
;
7299 tmode
= insn_data
[icode
].operand
[0].mode
;
7302 || GET_MODE (target
) != tmode
7303 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7304 target
= gen_reg_rtx (tmode
);
7306 pat
= GEN_FCN (icode
) (target
);
7312 case ALTIVEC_BUILTIN_MTVSCR
:
7313 icode
= CODE_FOR_altivec_mtvscr
;
7314 arg0
= TREE_VALUE (arglist
);
7315 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7316 mode0
= insn_data
[icode
].operand
[0].mode
;
7318 /* If we got invalid arguments bail out before generating bad rtl. */
7319 if (arg0
== error_mark_node
)
7322 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7323 op0
= copy_to_mode_reg (mode0
, op0
);
7325 pat
= GEN_FCN (icode
) (op0
);
7330 case ALTIVEC_BUILTIN_DSSALL
:
7331 emit_insn (gen_altivec_dssall ());
7334 case ALTIVEC_BUILTIN_DSS
:
7335 icode
= CODE_FOR_altivec_dss
;
7336 arg0
= TREE_VALUE (arglist
);
7338 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7339 mode0
= insn_data
[icode
].operand
[0].mode
;
7341 /* If we got invalid arguments bail out before generating bad rtl. */
7342 if (arg0
== error_mark_node
)
7345 if (TREE_CODE (arg0
) != INTEGER_CST
7346 || TREE_INT_CST_LOW (arg0
) & ~0x3)
7348 error ("argument to dss must be a 2-bit unsigned literal");
7352 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7353 op0
= copy_to_mode_reg (mode0
, op0
);
7355 emit_insn (gen_altivec_dss (op0
));
7358 case ALTIVEC_BUILTIN_COMPILETIME_ERROR
:
7359 arg0
= TREE_VALUE (arglist
);
7360 while (TREE_CODE (arg0
) == NOP_EXPR
|| TREE_CODE (arg0
) == ADDR_EXPR
7361 || TREE_CODE (arg0
) == ARRAY_REF
)
7362 arg0
= TREE_OPERAND (arg0
, 0);
7363 error ("invalid parameter combination for %qs AltiVec intrinsic",
7364 TREE_STRING_POINTER (arg0
));
7369 /* Expand abs* operations. */
7370 d
= (struct builtin_description
*) bdesc_abs
;
7371 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
7372 if (d
->code
== fcode
)
7373 return altivec_expand_abs_builtin (d
->icode
, arglist
, target
);
7375 /* Expand the AltiVec predicates. */
7376 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
7377 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
7378 if (dp
->code
== fcode
)
7379 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
7382 /* LV* are funky. We initialized them differently. */
7385 case ALTIVEC_BUILTIN_LVSL
:
7386 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
7388 case ALTIVEC_BUILTIN_LVSR
:
7389 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
7391 case ALTIVEC_BUILTIN_LVEBX
:
7392 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
7394 case ALTIVEC_BUILTIN_LVEHX
:
7395 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
7397 case ALTIVEC_BUILTIN_LVEWX
:
7398 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
7400 case ALTIVEC_BUILTIN_LVXL
:
7401 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
7403 case ALTIVEC_BUILTIN_LVX
:
7404 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
7415 /* Binops that need to be initialized manually, but can be expanded
7416 automagically by rs6000_expand_binop_builtin. */
7417 static struct builtin_description bdesc_2arg_spe
[] =
7419 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
7420 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
7421 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
7422 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
7423 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
7424 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
7425 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
7426 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
7427 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
7428 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
7429 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
7430 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
7431 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
7432 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
7433 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
7434 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
7435 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
7436 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
7437 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
7438 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
7439 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
7440 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
7443 /* Expand the builtin in EXP and store the result in TARGET. Store
7444 true in *EXPANDEDP if we found a builtin to expand.
7446 This expands the SPE builtins that are not simple unary and binary
7449 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
7451 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7452 tree arglist
= TREE_OPERAND (exp
, 1);
7454 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7455 enum insn_code icode
;
7456 enum machine_mode tmode
, mode0
;
7458 struct builtin_description
*d
;
7463 /* Syntax check for a 5-bit unsigned immediate. */
7466 case SPE_BUILTIN_EVSTDD
:
7467 case SPE_BUILTIN_EVSTDH
:
7468 case SPE_BUILTIN_EVSTDW
:
7469 case SPE_BUILTIN_EVSTWHE
:
7470 case SPE_BUILTIN_EVSTWHO
:
7471 case SPE_BUILTIN_EVSTWWE
:
7472 case SPE_BUILTIN_EVSTWWO
:
7473 arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7474 if (TREE_CODE (arg1
) != INTEGER_CST
7475 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7477 error ("argument 2 must be a 5-bit unsigned literal");
7485 /* The evsplat*i instructions are not quite generic. */
7488 case SPE_BUILTIN_EVSPLATFI
:
7489 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
7491 case SPE_BUILTIN_EVSPLATI
:
7492 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
7498 d
= (struct builtin_description
*) bdesc_2arg_spe
;
7499 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
7500 if (d
->code
== fcode
)
7501 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7503 d
= (struct builtin_description
*) bdesc_spe_predicates
;
7504 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
7505 if (d
->code
== fcode
)
7506 return spe_expand_predicate_builtin (d
->icode
, arglist
, target
);
7508 d
= (struct builtin_description
*) bdesc_spe_evsel
;
7509 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
7510 if (d
->code
== fcode
)
7511 return spe_expand_evsel_builtin (d
->icode
, arglist
, target
);
7515 case SPE_BUILTIN_EVSTDDX
:
7516 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, arglist
);
7517 case SPE_BUILTIN_EVSTDHX
:
7518 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, arglist
);
7519 case SPE_BUILTIN_EVSTDWX
:
7520 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, arglist
);
7521 case SPE_BUILTIN_EVSTWHEX
:
7522 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, arglist
);
7523 case SPE_BUILTIN_EVSTWHOX
:
7524 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, arglist
);
7525 case SPE_BUILTIN_EVSTWWEX
:
7526 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, arglist
);
7527 case SPE_BUILTIN_EVSTWWOX
:
7528 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, arglist
);
7529 case SPE_BUILTIN_EVSTDD
:
7530 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, arglist
);
7531 case SPE_BUILTIN_EVSTDH
:
7532 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, arglist
);
7533 case SPE_BUILTIN_EVSTDW
:
7534 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, arglist
);
7535 case SPE_BUILTIN_EVSTWHE
:
7536 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, arglist
);
7537 case SPE_BUILTIN_EVSTWHO
:
7538 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, arglist
);
7539 case SPE_BUILTIN_EVSTWWE
:
7540 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, arglist
);
7541 case SPE_BUILTIN_EVSTWWO
:
7542 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, arglist
);
7543 case SPE_BUILTIN_MFSPEFSCR
:
7544 icode
= CODE_FOR_spe_mfspefscr
;
7545 tmode
= insn_data
[icode
].operand
[0].mode
;
7548 || GET_MODE (target
) != tmode
7549 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7550 target
= gen_reg_rtx (tmode
);
7552 pat
= GEN_FCN (icode
) (target
);
7557 case SPE_BUILTIN_MTSPEFSCR
:
7558 icode
= CODE_FOR_spe_mtspefscr
;
7559 arg0
= TREE_VALUE (arglist
);
7560 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7561 mode0
= insn_data
[icode
].operand
[0].mode
;
7563 if (arg0
== error_mark_node
)
7566 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7567 op0
= copy_to_mode_reg (mode0
, op0
);
7569 pat
= GEN_FCN (icode
) (op0
);
7582 spe_expand_predicate_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7584 rtx pat
, scratch
, tmp
;
7585 tree form
= TREE_VALUE (arglist
);
7586 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
7587 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7588 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7589 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7590 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7591 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7595 if (TREE_CODE (form
) != INTEGER_CST
)
7597 error ("argument 1 of __builtin_spe_predicate must be a constant");
7601 form_int
= TREE_INT_CST_LOW (form
);
7606 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7610 || GET_MODE (target
) != SImode
7611 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
7612 target
= gen_reg_rtx (SImode
);
7614 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7615 op0
= copy_to_mode_reg (mode0
, op0
);
7616 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7617 op1
= copy_to_mode_reg (mode1
, op1
);
7619 scratch
= gen_reg_rtx (CCmode
);
7621 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7626 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7627 _lower_. We use one compare, but look in different bits of the
7628 CR for each variant.
7630 There are 2 elements in each SPE simd type (upper/lower). The CR
7631 bits are set as follows:
7633 BIT0 | BIT 1 | BIT 2 | BIT 3
7634 U | L | (U | L) | (U & L)
7636 So, for an "all" relationship, BIT 3 would be set.
7637 For an "any" relationship, BIT 2 would be set. Etc.
7639 Following traditional nomenclature, these bits map to:
7641 BIT0 | BIT 1 | BIT 2 | BIT 3
7644 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7649 /* All variant. OV bit. */
7651 /* We need to get to the OV bit, which is the ORDERED bit. We
7652 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7653 that's ugly and will trigger a validate_condition_mode abort.
7654 So let's just use another pattern. */
7655 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
7657 /* Any variant. EQ bit. */
7661 /* Upper variant. LT bit. */
7665 /* Lower variant. GT bit. */
7670 error ("argument 1 of __builtin_spe_predicate is out of range");
7674 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
7675 emit_move_insn (target
, tmp
);
7680 /* The evsel builtins look like this:
7682 e = __builtin_spe_evsel_OP (a, b, c, d);
7686 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7687 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7691 spe_expand_evsel_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7694 tree arg0
= TREE_VALUE (arglist
);
7695 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7696 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7697 tree arg3
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist
))));
7698 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7699 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7700 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7701 rtx op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
7702 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7703 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7708 if (arg0
== error_mark_node
|| arg1
== error_mark_node
7709 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
7713 || GET_MODE (target
) != mode0
7714 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
7715 target
= gen_reg_rtx (mode0
);
7717 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7718 op0
= copy_to_mode_reg (mode0
, op0
);
7719 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7720 op1
= copy_to_mode_reg (mode0
, op1
);
7721 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
7722 op2
= copy_to_mode_reg (mode0
, op2
);
7723 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
7724 op3
= copy_to_mode_reg (mode0
, op3
);
7726 /* Generate the compare. */
7727 scratch
= gen_reg_rtx (CCmode
);
7728 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7733 if (mode0
== V2SImode
)
7734 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
7736 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
7741 /* Expand an expression EXP that calls a built-in function,
7742 with result going to TARGET if that's convenient
7743 (and in mode MODE if that's convenient).
7744 SUBTARGET may be used as the target for computing one of EXP's operands.
7745 IGNORE is nonzero if the value is to be ignored. */
7748 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7749 enum machine_mode mode ATTRIBUTE_UNUSED
,
7750 int ignore ATTRIBUTE_UNUSED
)
7752 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7753 tree arglist
= TREE_OPERAND (exp
, 1);
7754 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7755 struct builtin_description
*d
;
7760 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
7761 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7763 int icode
= (int) CODE_FOR_altivec_lvsr
;
7764 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7765 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
7769 if (!TARGET_ALTIVEC
)
7772 arg
= TREE_VALUE (arglist
);
7773 if (TREE_CODE (TREE_TYPE (arg
)) != POINTER_TYPE
)
7775 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
7776 addr
= memory_address (mode
, op
);
7777 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7781 /* For the load case need to negate the address. */
7782 op
= gen_reg_rtx (GET_MODE (addr
));
7783 emit_insn (gen_rtx_SET (VOIDmode
, op
,
7784 gen_rtx_NEG (GET_MODE (addr
), addr
)));
7786 op
= gen_rtx_MEM (mode
, op
);
7789 || GET_MODE (target
) != tmode
7790 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7791 target
= gen_reg_rtx (tmode
);
7793 /*pat = gen_altivec_lvsr (target, op);*/
7794 pat
= GEN_FCN (icode
) (target
, op
);
7804 ret
= altivec_expand_builtin (exp
, target
, &success
);
7811 ret
= spe_expand_builtin (exp
, target
, &success
);
7817 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7819 /* Handle simple unary operations. */
7820 d
= (struct builtin_description
*) bdesc_1arg
;
7821 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
7822 if (d
->code
== fcode
)
7823 return rs6000_expand_unop_builtin (d
->icode
, arglist
, target
);
7825 /* Handle simple binary operations. */
7826 d
= (struct builtin_description
*) bdesc_2arg
;
7827 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
7828 if (d
->code
== fcode
)
7829 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7831 /* Handle simple ternary operations. */
7832 d
= (struct builtin_description
*) bdesc_3arg
;
7833 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7834 if (d
->code
== fcode
)
7835 return rs6000_expand_ternop_builtin (d
->icode
, arglist
, target
);
7843 build_opaque_vector_type (tree node
, int nunits
)
7845 node
= copy_node (node
);
7846 TYPE_MAIN_VARIANT (node
) = node
;
7847 return build_vector_type (node
, nunits
);
7851 rs6000_init_builtins (void)
7853 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
7854 V2SF_type_node
= build_vector_type (float_type_node
, 2);
7855 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
7856 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
7857 V4SF_type_node
= build_vector_type (float_type_node
, 4);
7858 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
7859 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
7861 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
7862 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
7863 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
7865 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
7866 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
7867 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
7869 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7870 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7871 'vector unsigned short'. */
7873 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
7874 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7875 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
7876 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7878 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7879 get_identifier ("__bool char"),
7880 bool_char_type_node
));
7881 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7882 get_identifier ("__bool short"),
7883 bool_short_type_node
));
7884 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7885 get_identifier ("__bool int"),
7886 bool_int_type_node
));
7887 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7888 get_identifier ("__pixel"),
7891 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
7892 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
7893 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
7894 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
7896 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7897 get_identifier ("__vector unsigned char"),
7898 unsigned_V16QI_type_node
));
7899 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7900 get_identifier ("__vector signed char"),
7902 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7903 get_identifier ("__vector __bool char"),
7904 bool_V16QI_type_node
));
7906 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7907 get_identifier ("__vector unsigned short"),
7908 unsigned_V8HI_type_node
));
7909 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7910 get_identifier ("__vector signed short"),
7912 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7913 get_identifier ("__vector __bool short"),
7914 bool_V8HI_type_node
));
7916 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7917 get_identifier ("__vector unsigned int"),
7918 unsigned_V4SI_type_node
));
7919 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7920 get_identifier ("__vector signed int"),
7922 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7923 get_identifier ("__vector __bool int"),
7924 bool_V4SI_type_node
));
7926 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7927 get_identifier ("__vector float"),
7929 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7930 get_identifier ("__vector __pixel"),
7931 pixel_V8HI_type_node
));
7934 spe_init_builtins ();
7936 altivec_init_builtins ();
7937 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7938 rs6000_common_init_builtins ();
7941 /* Search through a set of builtins and enable the mask bits.
7942 DESC is an array of builtins.
7943 SIZE is the total number of builtins.
7944 START is the builtin enum at which to start.
7945 END is the builtin enum at which to end. */
7947 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
7948 enum rs6000_builtins start
,
7949 enum rs6000_builtins end
)
7953 for (i
= 0; i
< size
; ++i
)
7954 if (desc
[i
].code
== start
)
7960 for (; i
< size
; ++i
)
7962 /* Flip all the bits on. */
7963 desc
[i
].mask
= target_flags
;
7964 if (desc
[i
].code
== end
)
7970 spe_init_builtins (void)
7972 tree endlink
= void_list_node
;
7973 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
7974 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
7975 struct builtin_description
*d
;
7978 tree v2si_ftype_4_v2si
7979 = build_function_type
7980 (opaque_V2SI_type_node
,
7981 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7982 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7983 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7984 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7987 tree v2sf_ftype_4_v2sf
7988 = build_function_type
7989 (opaque_V2SF_type_node
,
7990 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7991 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7992 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7993 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7996 tree int_ftype_int_v2si_v2si
7997 = build_function_type
7999 tree_cons (NULL_TREE
, integer_type_node
,
8000 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8001 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8004 tree int_ftype_int_v2sf_v2sf
8005 = build_function_type
8007 tree_cons (NULL_TREE
, integer_type_node
,
8008 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8009 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8012 tree void_ftype_v2si_puint_int
8013 = build_function_type (void_type_node
,
8014 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8015 tree_cons (NULL_TREE
, puint_type_node
,
8016 tree_cons (NULL_TREE
,
8020 tree void_ftype_v2si_puint_char
8021 = build_function_type (void_type_node
,
8022 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8023 tree_cons (NULL_TREE
, puint_type_node
,
8024 tree_cons (NULL_TREE
,
8028 tree void_ftype_v2si_pv2si_int
8029 = build_function_type (void_type_node
,
8030 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8031 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8032 tree_cons (NULL_TREE
,
8036 tree void_ftype_v2si_pv2si_char
8037 = build_function_type (void_type_node
,
8038 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8039 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8040 tree_cons (NULL_TREE
,
8045 = build_function_type (void_type_node
,
8046 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
8049 = build_function_type (integer_type_node
, endlink
);
8051 tree v2si_ftype_pv2si_int
8052 = build_function_type (opaque_V2SI_type_node
,
8053 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8054 tree_cons (NULL_TREE
, integer_type_node
,
8057 tree v2si_ftype_puint_int
8058 = build_function_type (opaque_V2SI_type_node
,
8059 tree_cons (NULL_TREE
, puint_type_node
,
8060 tree_cons (NULL_TREE
, integer_type_node
,
8063 tree v2si_ftype_pushort_int
8064 = build_function_type (opaque_V2SI_type_node
,
8065 tree_cons (NULL_TREE
, pushort_type_node
,
8066 tree_cons (NULL_TREE
, integer_type_node
,
8069 tree v2si_ftype_signed_char
8070 = build_function_type (opaque_V2SI_type_node
,
8071 tree_cons (NULL_TREE
, signed_char_type_node
,
8074 /* The initialization of the simple binary and unary builtins is
8075 done in rs6000_common_init_builtins, but we have to enable the
8076 mask bits here manually because we have run out of `target_flags'
8077 bits. We really need to redesign this mask business. */
8079 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
8080 ARRAY_SIZE (bdesc_2arg
),
8083 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
8084 ARRAY_SIZE (bdesc_1arg
),
8086 SPE_BUILTIN_EVSUBFUSIAAW
);
8087 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
8088 ARRAY_SIZE (bdesc_spe_predicates
),
8089 SPE_BUILTIN_EVCMPEQ
,
8090 SPE_BUILTIN_EVFSTSTLT
);
8091 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
8092 ARRAY_SIZE (bdesc_spe_evsel
),
8093 SPE_BUILTIN_EVSEL_CMPGTS
,
8094 SPE_BUILTIN_EVSEL_FSTSTEQ
);
8096 (*lang_hooks
.decls
.pushdecl
)
8097 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
8098 opaque_V2SI_type_node
));
8100 /* Initialize irregular SPE builtins. */
8102 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
8103 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
8104 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
8105 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
8106 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
8107 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
8108 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
8109 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
8110 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
8111 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
8112 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
8113 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
8114 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
8115 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
8116 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
8117 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
8118 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
8119 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
8122 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
8123 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
8124 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
8125 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
8126 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
8127 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
8128 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
8129 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
8130 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
8131 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
8132 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
8133 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
8134 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
8135 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
8136 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
8137 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
8138 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
8139 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
8140 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
8141 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
8142 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
8143 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
8146 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8147 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
8151 switch (insn_data
[d
->icode
].operand
[1].mode
)
8154 type
= int_ftype_int_v2si_v2si
;
8157 type
= int_ftype_int_v2sf_v2sf
;
8163 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8166 /* Evsel predicates. */
8167 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8168 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
8172 switch (insn_data
[d
->icode
].operand
[1].mode
)
8175 type
= v2si_ftype_4_v2si
;
8178 type
= v2sf_ftype_4_v2sf
;
8184 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8189 altivec_init_builtins (void)
8191 struct builtin_description
*d
;
8192 struct builtin_description_predicates
*dp
;
8194 tree pfloat_type_node
= build_pointer_type (float_type_node
);
8195 tree pint_type_node
= build_pointer_type (integer_type_node
);
8196 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
8197 tree pchar_type_node
= build_pointer_type (char_type_node
);
8199 tree pvoid_type_node
= build_pointer_type (void_type_node
);
8201 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
8202 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
8203 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
8204 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
8206 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
8208 tree int_ftype_int_v4si_v4si
8209 = build_function_type_list (integer_type_node
,
8210 integer_type_node
, V4SI_type_node
,
8211 V4SI_type_node
, NULL_TREE
);
8212 tree v4sf_ftype_pcfloat
8213 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
8214 tree void_ftype_pfloat_v4sf
8215 = build_function_type_list (void_type_node
,
8216 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
8217 tree v4si_ftype_pcint
8218 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
8219 tree void_ftype_pint_v4si
8220 = build_function_type_list (void_type_node
,
8221 pint_type_node
, V4SI_type_node
, NULL_TREE
);
8222 tree v8hi_ftype_pcshort
8223 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
8224 tree void_ftype_pshort_v8hi
8225 = build_function_type_list (void_type_node
,
8226 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
8227 tree v16qi_ftype_pcchar
8228 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
8229 tree void_ftype_pchar_v16qi
8230 = build_function_type_list (void_type_node
,
8231 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
8232 tree void_ftype_v4si
8233 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
8234 tree v8hi_ftype_void
8235 = build_function_type (V8HI_type_node
, void_list_node
);
8236 tree void_ftype_void
8237 = build_function_type (void_type_node
, void_list_node
);
8239 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
8241 tree v16qi_ftype_long_pcvoid
8242 = build_function_type_list (V16QI_type_node
,
8243 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8244 tree v8hi_ftype_long_pcvoid
8245 = build_function_type_list (V8HI_type_node
,
8246 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8247 tree v4si_ftype_long_pcvoid
8248 = build_function_type_list (V4SI_type_node
,
8249 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8251 tree void_ftype_v4si_long_pvoid
8252 = build_function_type_list (void_type_node
,
8253 V4SI_type_node
, long_integer_type_node
,
8254 pvoid_type_node
, NULL_TREE
);
8255 tree void_ftype_v16qi_long_pvoid
8256 = build_function_type_list (void_type_node
,
8257 V16QI_type_node
, long_integer_type_node
,
8258 pvoid_type_node
, NULL_TREE
);
8259 tree void_ftype_v8hi_long_pvoid
8260 = build_function_type_list (void_type_node
,
8261 V8HI_type_node
, long_integer_type_node
,
8262 pvoid_type_node
, NULL_TREE
);
8263 tree int_ftype_int_v8hi_v8hi
8264 = build_function_type_list (integer_type_node
,
8265 integer_type_node
, V8HI_type_node
,
8266 V8HI_type_node
, NULL_TREE
);
8267 tree int_ftype_int_v16qi_v16qi
8268 = build_function_type_list (integer_type_node
,
8269 integer_type_node
, V16QI_type_node
,
8270 V16QI_type_node
, NULL_TREE
);
8271 tree int_ftype_int_v4sf_v4sf
8272 = build_function_type_list (integer_type_node
,
8273 integer_type_node
, V4SF_type_node
,
8274 V4SF_type_node
, NULL_TREE
);
8275 tree v4si_ftype_v4si
8276 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8277 tree v8hi_ftype_v8hi
8278 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8279 tree v16qi_ftype_v16qi
8280 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8281 tree v4sf_ftype_v4sf
8282 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8283 tree void_ftype_pcvoid_int_int
8284 = build_function_type_list (void_type_node
,
8285 pcvoid_type_node
, integer_type_node
,
8286 integer_type_node
, NULL_TREE
);
8287 tree int_ftype_pcchar
8288 = build_function_type_list (integer_type_node
,
8289 pcchar_type_node
, NULL_TREE
);
8291 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
8292 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
8293 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
8294 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
8295 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
8296 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
8297 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
8298 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
8299 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
8300 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
8301 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
8302 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
8303 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
8304 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
8305 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
8306 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
8307 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
8308 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
8309 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
8310 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
8311 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
8312 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
8313 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
8314 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
8315 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
8316 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
8317 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
8318 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
8319 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
8320 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
8321 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
8322 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
8324 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
8325 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_compiletime_error", int_ftype_pcchar
,
8326 ALTIVEC_BUILTIN_COMPILETIME_ERROR
);
8328 /* Add the DST variants. */
8329 d
= (struct builtin_description
*) bdesc_dst
;
8330 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8331 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
8333 /* Initialize the predicates. */
8334 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
8335 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8337 enum machine_mode mode1
;
8340 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
8345 type
= int_ftype_int_v4si_v4si
;
8348 type
= int_ftype_int_v8hi_v8hi
;
8351 type
= int_ftype_int_v16qi_v16qi
;
8354 type
= int_ftype_int_v4sf_v4sf
;
8360 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
8363 /* Initialize the abs* operators. */
8364 d
= (struct builtin_description
*) bdesc_abs
;
8365 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8367 enum machine_mode mode0
;
8370 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8375 type
= v4si_ftype_v4si
;
8378 type
= v8hi_ftype_v8hi
;
8381 type
= v16qi_ftype_v16qi
;
8384 type
= v4sf_ftype_v4sf
;
8390 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8397 /* Initialize target builtin that implements
8398 targetm.vectorize.builtin_mask_for_load. */
8400 decl
= lang_hooks
.builtin_function ("__builtin_altivec_mask_for_load",
8401 v16qi_ftype_long_pcvoid
,
8402 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
8403 BUILT_IN_MD
, NULL
, NULL_TREE
);
8404 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8405 altivec_builtin_mask_for_load
= decl
;
8410 rs6000_common_init_builtins (void)
8412 struct builtin_description
*d
;
8415 tree v4sf_ftype_v4sf_v4sf_v16qi
8416 = build_function_type_list (V4SF_type_node
,
8417 V4SF_type_node
, V4SF_type_node
,
8418 V16QI_type_node
, NULL_TREE
);
8419 tree v4si_ftype_v4si_v4si_v16qi
8420 = build_function_type_list (V4SI_type_node
,
8421 V4SI_type_node
, V4SI_type_node
,
8422 V16QI_type_node
, NULL_TREE
);
8423 tree v8hi_ftype_v8hi_v8hi_v16qi
8424 = build_function_type_list (V8HI_type_node
,
8425 V8HI_type_node
, V8HI_type_node
,
8426 V16QI_type_node
, NULL_TREE
);
8427 tree v16qi_ftype_v16qi_v16qi_v16qi
8428 = build_function_type_list (V16QI_type_node
,
8429 V16QI_type_node
, V16QI_type_node
,
8430 V16QI_type_node
, NULL_TREE
);
8432 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
8434 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
8435 tree v16qi_ftype_int
8436 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
8437 tree v8hi_ftype_v16qi
8438 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
8439 tree v4sf_ftype_v4sf
8440 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8442 tree v2si_ftype_v2si_v2si
8443 = build_function_type_list (opaque_V2SI_type_node
,
8444 opaque_V2SI_type_node
,
8445 opaque_V2SI_type_node
, NULL_TREE
);
8447 tree v2sf_ftype_v2sf_v2sf
8448 = build_function_type_list (opaque_V2SF_type_node
,
8449 opaque_V2SF_type_node
,
8450 opaque_V2SF_type_node
, NULL_TREE
);
8452 tree v2si_ftype_int_int
8453 = build_function_type_list (opaque_V2SI_type_node
,
8454 integer_type_node
, integer_type_node
,
8457 tree v2si_ftype_v2si
8458 = build_function_type_list (opaque_V2SI_type_node
,
8459 opaque_V2SI_type_node
, NULL_TREE
);
8461 tree v2sf_ftype_v2sf
8462 = build_function_type_list (opaque_V2SF_type_node
,
8463 opaque_V2SF_type_node
, NULL_TREE
);
8465 tree v2sf_ftype_v2si
8466 = build_function_type_list (opaque_V2SF_type_node
,
8467 opaque_V2SI_type_node
, NULL_TREE
);
8469 tree v2si_ftype_v2sf
8470 = build_function_type_list (opaque_V2SI_type_node
,
8471 opaque_V2SF_type_node
, NULL_TREE
);
8473 tree v2si_ftype_v2si_char
8474 = build_function_type_list (opaque_V2SI_type_node
,
8475 opaque_V2SI_type_node
,
8476 char_type_node
, NULL_TREE
);
8478 tree v2si_ftype_int_char
8479 = build_function_type_list (opaque_V2SI_type_node
,
8480 integer_type_node
, char_type_node
, NULL_TREE
);
8482 tree v2si_ftype_char
8483 = build_function_type_list (opaque_V2SI_type_node
,
8484 char_type_node
, NULL_TREE
);
8486 tree int_ftype_int_int
8487 = build_function_type_list (integer_type_node
,
8488 integer_type_node
, integer_type_node
,
8491 tree v4si_ftype_v4si_v4si
8492 = build_function_type_list (V4SI_type_node
,
8493 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8494 tree v4sf_ftype_v4si_int
8495 = build_function_type_list (V4SF_type_node
,
8496 V4SI_type_node
, integer_type_node
, NULL_TREE
);
8497 tree v4si_ftype_v4sf_int
8498 = build_function_type_list (V4SI_type_node
,
8499 V4SF_type_node
, integer_type_node
, NULL_TREE
);
8500 tree v4si_ftype_v4si_int
8501 = build_function_type_list (V4SI_type_node
,
8502 V4SI_type_node
, integer_type_node
, NULL_TREE
);
8503 tree v8hi_ftype_v8hi_int
8504 = build_function_type_list (V8HI_type_node
,
8505 V8HI_type_node
, integer_type_node
, NULL_TREE
);
8506 tree v16qi_ftype_v16qi_int
8507 = build_function_type_list (V16QI_type_node
,
8508 V16QI_type_node
, integer_type_node
, NULL_TREE
);
8509 tree v16qi_ftype_v16qi_v16qi_int
8510 = build_function_type_list (V16QI_type_node
,
8511 V16QI_type_node
, V16QI_type_node
,
8512 integer_type_node
, NULL_TREE
);
8513 tree v8hi_ftype_v8hi_v8hi_int
8514 = build_function_type_list (V8HI_type_node
,
8515 V8HI_type_node
, V8HI_type_node
,
8516 integer_type_node
, NULL_TREE
);
8517 tree v4si_ftype_v4si_v4si_int
8518 = build_function_type_list (V4SI_type_node
,
8519 V4SI_type_node
, V4SI_type_node
,
8520 integer_type_node
, NULL_TREE
);
8521 tree v4sf_ftype_v4sf_v4sf_int
8522 = build_function_type_list (V4SF_type_node
,
8523 V4SF_type_node
, V4SF_type_node
,
8524 integer_type_node
, NULL_TREE
);
8525 tree v4sf_ftype_v4sf_v4sf
8526 = build_function_type_list (V4SF_type_node
,
8527 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8528 tree v4sf_ftype_v4sf_v4sf_v4si
8529 = build_function_type_list (V4SF_type_node
,
8530 V4SF_type_node
, V4SF_type_node
,
8531 V4SI_type_node
, NULL_TREE
);
8532 tree v4sf_ftype_v4sf_v4sf_v4sf
8533 = build_function_type_list (V4SF_type_node
,
8534 V4SF_type_node
, V4SF_type_node
,
8535 V4SF_type_node
, NULL_TREE
);
8536 tree v4si_ftype_v4si_v4si_v4si
8537 = build_function_type_list (V4SI_type_node
,
8538 V4SI_type_node
, V4SI_type_node
,
8539 V4SI_type_node
, NULL_TREE
);
8540 tree v8hi_ftype_v8hi_v8hi
8541 = build_function_type_list (V8HI_type_node
,
8542 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8543 tree v8hi_ftype_v8hi_v8hi_v8hi
8544 = build_function_type_list (V8HI_type_node
,
8545 V8HI_type_node
, V8HI_type_node
,
8546 V8HI_type_node
, NULL_TREE
);
8547 tree v4si_ftype_v8hi_v8hi_v4si
8548 = build_function_type_list (V4SI_type_node
,
8549 V8HI_type_node
, V8HI_type_node
,
8550 V4SI_type_node
, NULL_TREE
);
8551 tree v4si_ftype_v16qi_v16qi_v4si
8552 = build_function_type_list (V4SI_type_node
,
8553 V16QI_type_node
, V16QI_type_node
,
8554 V4SI_type_node
, NULL_TREE
);
8555 tree v16qi_ftype_v16qi_v16qi
8556 = build_function_type_list (V16QI_type_node
,
8557 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8558 tree v4si_ftype_v4sf_v4sf
8559 = build_function_type_list (V4SI_type_node
,
8560 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8561 tree v8hi_ftype_v16qi_v16qi
8562 = build_function_type_list (V8HI_type_node
,
8563 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8564 tree v4si_ftype_v8hi_v8hi
8565 = build_function_type_list (V4SI_type_node
,
8566 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8567 tree v8hi_ftype_v4si_v4si
8568 = build_function_type_list (V8HI_type_node
,
8569 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8570 tree v16qi_ftype_v8hi_v8hi
8571 = build_function_type_list (V16QI_type_node
,
8572 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8573 tree v4si_ftype_v16qi_v4si
8574 = build_function_type_list (V4SI_type_node
,
8575 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
8576 tree v4si_ftype_v16qi_v16qi
8577 = build_function_type_list (V4SI_type_node
,
8578 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8579 tree v4si_ftype_v8hi_v4si
8580 = build_function_type_list (V4SI_type_node
,
8581 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
8582 tree v4si_ftype_v8hi
8583 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
8584 tree int_ftype_v4si_v4si
8585 = build_function_type_list (integer_type_node
,
8586 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8587 tree int_ftype_v4sf_v4sf
8588 = build_function_type_list (integer_type_node
,
8589 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8590 tree int_ftype_v16qi_v16qi
8591 = build_function_type_list (integer_type_node
,
8592 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8593 tree int_ftype_v8hi_v8hi
8594 = build_function_type_list (integer_type_node
,
8595 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8597 /* Add the simple ternary operators. */
8598 d
= (struct builtin_description
*) bdesc_3arg
;
8599 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
8602 enum machine_mode mode0
, mode1
, mode2
, mode3
;
8605 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8608 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8609 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8610 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8611 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
8613 /* When all four are of the same mode. */
8614 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
8619 type
= v4si_ftype_v4si_v4si_v4si
;
8622 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
8625 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
8628 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8634 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
8639 type
= v4si_ftype_v4si_v4si_v16qi
;
8642 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
8645 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
8648 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8654 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
8655 && mode3
== V4SImode
)
8656 type
= v4si_ftype_v16qi_v16qi_v4si
;
8657 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
8658 && mode3
== V4SImode
)
8659 type
= v4si_ftype_v8hi_v8hi_v4si
;
8660 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
8661 && mode3
== V4SImode
)
8662 type
= v4sf_ftype_v4sf_v4sf_v4si
;
8664 /* vchar, vchar, vchar, 4 bit literal. */
8665 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
8667 type
= v16qi_ftype_v16qi_v16qi_int
;
8669 /* vshort, vshort, vshort, 4 bit literal. */
8670 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
8672 type
= v8hi_ftype_v8hi_v8hi_int
;
8674 /* vint, vint, vint, 4 bit literal. */
8675 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
8677 type
= v4si_ftype_v4si_v4si_int
;
8679 /* vfloat, vfloat, vfloat, 4 bit literal. */
8680 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
8682 type
= v4sf_ftype_v4sf_v4sf_int
;
8687 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8690 /* Add the simple binary operators. */
8691 d
= (struct builtin_description
*) bdesc_2arg
;
8692 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
8694 enum machine_mode mode0
, mode1
, mode2
;
8697 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8700 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8701 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8702 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8704 /* When all three operands are of the same mode. */
8705 if (mode0
== mode1
&& mode1
== mode2
)
8710 type
= v4sf_ftype_v4sf_v4sf
;
8713 type
= v4si_ftype_v4si_v4si
;
8716 type
= v16qi_ftype_v16qi_v16qi
;
8719 type
= v8hi_ftype_v8hi_v8hi
;
8722 type
= v2si_ftype_v2si_v2si
;
8725 type
= v2sf_ftype_v2sf_v2sf
;
8728 type
= int_ftype_int_int
;
8735 /* A few other combos we really don't want to do manually. */
8737 /* vint, vfloat, vfloat. */
8738 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
8739 type
= v4si_ftype_v4sf_v4sf
;
8741 /* vshort, vchar, vchar. */
8742 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8743 type
= v8hi_ftype_v16qi_v16qi
;
8745 /* vint, vshort, vshort. */
8746 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8747 type
= v4si_ftype_v8hi_v8hi
;
8749 /* vshort, vint, vint. */
8750 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
8751 type
= v8hi_ftype_v4si_v4si
;
8753 /* vchar, vshort, vshort. */
8754 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8755 type
= v16qi_ftype_v8hi_v8hi
;
8757 /* vint, vchar, vint. */
8758 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
8759 type
= v4si_ftype_v16qi_v4si
;
8761 /* vint, vchar, vchar. */
8762 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8763 type
= v4si_ftype_v16qi_v16qi
;
8765 /* vint, vshort, vint. */
8766 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
8767 type
= v4si_ftype_v8hi_v4si
;
8769 /* vint, vint, 5 bit literal. */
8770 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
8771 type
= v4si_ftype_v4si_int
;
8773 /* vshort, vshort, 5 bit literal. */
8774 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
8775 type
= v8hi_ftype_v8hi_int
;
8777 /* vchar, vchar, 5 bit literal. */
8778 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
8779 type
= v16qi_ftype_v16qi_int
;
8781 /* vfloat, vint, 5 bit literal. */
8782 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
8783 type
= v4sf_ftype_v4si_int
;
8785 /* vint, vfloat, 5 bit literal. */
8786 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
8787 type
= v4si_ftype_v4sf_int
;
8789 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
8790 type
= v2si_ftype_int_int
;
8792 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
8793 type
= v2si_ftype_v2si_char
;
8795 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
8796 type
= v2si_ftype_int_char
;
8799 else if (mode0
== SImode
)
8804 type
= int_ftype_v4si_v4si
;
8807 type
= int_ftype_v4sf_v4sf
;
8810 type
= int_ftype_v16qi_v16qi
;
8813 type
= int_ftype_v8hi_v8hi
;
8823 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8826 /* Add the simple unary operators. */
8827 d
= (struct builtin_description
*) bdesc_1arg
;
8828 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
8830 enum machine_mode mode0
, mode1
;
8833 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8836 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8837 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8839 if (mode0
== V4SImode
&& mode1
== QImode
)
8840 type
= v4si_ftype_int
;
8841 else if (mode0
== V8HImode
&& mode1
== QImode
)
8842 type
= v8hi_ftype_int
;
8843 else if (mode0
== V16QImode
&& mode1
== QImode
)
8844 type
= v16qi_ftype_int
;
8845 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
8846 type
= v4sf_ftype_v4sf
;
8847 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
8848 type
= v8hi_ftype_v16qi
;
8849 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
8850 type
= v4si_ftype_v8hi
;
8851 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
8852 type
= v2si_ftype_v2si
;
8853 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
8854 type
= v2sf_ftype_v2sf
;
8855 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
8856 type
= v2sf_ftype_v2si
;
8857 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
8858 type
= v2si_ftype_v2sf
;
8859 else if (mode0
== V2SImode
&& mode1
== QImode
)
8860 type
= v2si_ftype_char
;
8864 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8869 rs6000_init_libfuncs (void)
8871 if (!TARGET_HARD_FLOAT
)
8874 if (DEFAULT_ABI
!= ABI_V4
)
8876 if (TARGET_XCOFF
&& ! TARGET_POWER2
&& ! TARGET_POWERPC
)
8878 /* AIX library routines for float->int conversion. */
8879 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
8880 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
8881 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
8882 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
8885 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8886 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
8887 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
8888 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
8889 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
8893 /* 32-bit SVR4 quad floating point routines. */
8895 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
8896 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
8897 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
8898 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
8899 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
8900 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
8901 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
8903 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
8904 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
8905 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
8906 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
8907 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
8908 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
8910 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
8911 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
8912 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
8913 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
8914 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
8915 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
8916 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
8921 /* Expand a block clear operation, and return 1 if successful. Return 0
8922 if we should let the compiler generate normal code.
8924 operands[0] is the destination
8925 operands[1] is the length
8926 operands[2] is the alignment */
8929 expand_block_clear (rtx operands
[])
8931 rtx orig_dest
= operands
[0];
8932 rtx bytes_rtx
= operands
[1];
8933 rtx align_rtx
= operands
[2];
8934 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
8935 HOST_WIDE_INT align
;
8936 HOST_WIDE_INT bytes
;
8941 /* If this is not a fixed size move, just call memcpy */
8945 /* If this is not a fixed size alignment, abort */
8946 if (GET_CODE (align_rtx
) != CONST_INT
)
8948 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
8950 /* Anything to clear? */
8951 bytes
= INTVAL (bytes_rtx
);
8955 /* Use the builtin memset after a point, to avoid huge code bloat.
8956 When optimize_size, avoid any significant code bloat; calling
8957 memset is about 4 instructions, so allow for one instruction to
8958 load zero and three to do clearing. */
8959 if (TARGET_ALTIVEC
&& align
>= 128)
8961 else if (TARGET_POWERPC64
&& align
>= 32)
8966 if (optimize_size
&& bytes
> 3 * clear_step
)
8968 if (! optimize_size
&& bytes
> 8 * clear_step
)
8971 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
8973 enum machine_mode mode
= BLKmode
;
8976 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
8981 else if (bytes
>= 8 && TARGET_POWERPC64
8982 /* 64-bit loads and stores require word-aligned
8984 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
8989 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
8990 { /* move 4 bytes */
8994 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
8995 { /* move 2 bytes */
8999 else /* move 1 byte at a time */
9005 dest
= adjust_address (orig_dest
, mode
, offset
);
9007 emit_move_insn (dest
, CONST0_RTX (mode
));
9014 /* Expand a block move operation, and return 1 if successful. Return 0
9015 if we should let the compiler generate normal code.
9017 operands[0] is the destination
9018 operands[1] is the source
9019 operands[2] is the length
9020 operands[3] is the alignment */
9022 #define MAX_MOVE_REG 4
9025 expand_block_move (rtx operands
[])
9027 rtx orig_dest
= operands
[0];
9028 rtx orig_src
= operands
[1];
9029 rtx bytes_rtx
= operands
[2];
9030 rtx align_rtx
= operands
[3];
9031 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
9036 rtx stores
[MAX_MOVE_REG
];
9039 /* If this is not a fixed size move, just call memcpy */
9043 /* If this is not a fixed size alignment, abort */
9044 if (GET_CODE (align_rtx
) != CONST_INT
)
9046 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
9048 /* Anything to move? */
9049 bytes
= INTVAL (bytes_rtx
);
9053 /* store_one_arg depends on expand_block_move to handle at least the size of
9054 reg_parm_stack_space. */
9055 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
9058 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
9061 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
9062 rtx (*mov
) (rtx
, rtx
);
9064 enum machine_mode mode
= BLKmode
;
9067 /* Altivec first, since it will be faster than a string move
9068 when it applies, and usually not significantly larger. */
9069 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
9073 gen_func
.mov
= gen_movv4si
;
9075 else if (TARGET_STRING
9076 && bytes
> 24 /* move up to 32 bytes at a time */
9084 && ! fixed_regs
[12])
9086 move_bytes
= (bytes
> 32) ? 32 : bytes
;
9087 gen_func
.movmemsi
= gen_movmemsi_8reg
;
9089 else if (TARGET_STRING
9090 && bytes
> 16 /* move up to 24 bytes at a time */
9096 && ! fixed_regs
[10])
9098 move_bytes
= (bytes
> 24) ? 24 : bytes
;
9099 gen_func
.movmemsi
= gen_movmemsi_6reg
;
9101 else if (TARGET_STRING
9102 && bytes
> 8 /* move up to 16 bytes at a time */
9108 move_bytes
= (bytes
> 16) ? 16 : bytes
;
9109 gen_func
.movmemsi
= gen_movmemsi_4reg
;
9111 else if (bytes
>= 8 && TARGET_POWERPC64
9112 /* 64-bit loads and stores require word-aligned
9114 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
9118 gen_func
.mov
= gen_movdi
;
9120 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
9121 { /* move up to 8 bytes at a time */
9122 move_bytes
= (bytes
> 8) ? 8 : bytes
;
9123 gen_func
.movmemsi
= gen_movmemsi_2reg
;
9125 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
9126 { /* move 4 bytes */
9129 gen_func
.mov
= gen_movsi
;
9131 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
9132 { /* move 2 bytes */
9135 gen_func
.mov
= gen_movhi
;
9137 else if (TARGET_STRING
&& bytes
> 1)
9138 { /* move up to 4 bytes at a time */
9139 move_bytes
= (bytes
> 4) ? 4 : bytes
;
9140 gen_func
.movmemsi
= gen_movmemsi_1reg
;
9142 else /* move 1 byte at a time */
9146 gen_func
.mov
= gen_movqi
;
9149 src
= adjust_address (orig_src
, mode
, offset
);
9150 dest
= adjust_address (orig_dest
, mode
, offset
);
9152 if (mode
!= BLKmode
)
9154 rtx tmp_reg
= gen_reg_rtx (mode
);
9156 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
9157 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
9160 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
9163 for (i
= 0; i
< num_reg
; i
++)
9164 emit_insn (stores
[i
]);
9168 if (mode
== BLKmode
)
9170 /* Move the address into scratch registers. The movmemsi
9171 patterns require zero offset. */
9172 if (!REG_P (XEXP (src
, 0)))
9174 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
9175 src
= replace_equiv_address (src
, src_reg
);
9177 set_mem_size (src
, GEN_INT (move_bytes
));
9179 if (!REG_P (XEXP (dest
, 0)))
9181 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
9182 dest
= replace_equiv_address (dest
, dest_reg
);
9184 set_mem_size (dest
, GEN_INT (move_bytes
));
9186 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
9187 GEN_INT (move_bytes
& 31),
9196 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9197 known to be a PARALLEL. */
9199 save_world_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9204 int count
= XVECLEN (op
, 0);
9210 if (GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9211 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
)
9214 for (i
=1; i
<= 18; i
++)
9216 elt
= XVECEXP (op
, 0, index
++);
9217 if (GET_CODE (elt
) != SET
9218 || GET_CODE (SET_DEST (elt
)) != MEM
9219 || ! memory_operand (SET_DEST (elt
), DFmode
)
9220 || GET_CODE (SET_SRC (elt
)) != REG
9221 || GET_MODE (SET_SRC (elt
)) != DFmode
)
9225 for (i
=1; i
<= 12; i
++)
9227 elt
= XVECEXP (op
, 0, index
++);
9228 if (GET_CODE (elt
) != SET
9229 || GET_CODE (SET_DEST (elt
)) != MEM
9230 || GET_CODE (SET_SRC (elt
)) != REG
9231 || GET_MODE (SET_SRC (elt
)) != V4SImode
)
9235 for (i
=1; i
<= 19; i
++)
9237 elt
= XVECEXP (op
, 0, index
++);
9238 if (GET_CODE (elt
) != SET
9239 || GET_CODE (SET_DEST (elt
)) != MEM
9240 || ! memory_operand (SET_DEST (elt
), Pmode
)
9241 || GET_CODE (SET_SRC (elt
)) != REG
9242 || GET_MODE (SET_SRC (elt
)) != Pmode
)
9246 elt
= XVECEXP (op
, 0, index
++);
9247 if (GET_CODE (elt
) != SET
9248 || GET_CODE (SET_DEST (elt
)) != MEM
9249 || ! memory_operand (SET_DEST (elt
), Pmode
)
9250 || GET_CODE (SET_SRC (elt
)) != REG
9251 || REGNO (SET_SRC (elt
)) != CR2_REGNO
9252 || GET_MODE (SET_SRC (elt
)) != Pmode
)
9255 if (GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9256 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9257 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
)
9262 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9263 known to be a PARALLEL. */
9265 restore_world_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9270 int count
= XVECLEN (op
, 0);
9276 if (GET_CODE (XVECEXP (op
, 0, index
++)) != RETURN
9277 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9278 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9279 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
)
9282 elt
= XVECEXP (op
, 0, index
++);
9283 if (GET_CODE (elt
) != SET
9284 || GET_CODE (SET_SRC (elt
)) != MEM
9285 || ! memory_operand (SET_SRC (elt
), Pmode
)
9286 || GET_CODE (SET_DEST (elt
)) != REG
9287 || REGNO (SET_DEST (elt
)) != CR2_REGNO
9288 || GET_MODE (SET_DEST (elt
)) != Pmode
)
9291 for (i
=1; i
<= 19; i
++)
9293 elt
= XVECEXP (op
, 0, index
++);
9294 if (GET_CODE (elt
) != SET
9295 || GET_CODE (SET_SRC (elt
)) != MEM
9296 || ! memory_operand (SET_SRC (elt
), Pmode
)
9297 || GET_CODE (SET_DEST (elt
)) != REG
9298 || GET_MODE (SET_DEST (elt
)) != Pmode
)
9302 for (i
=1; i
<= 12; i
++)
9304 elt
= XVECEXP (op
, 0, index
++);
9305 if (GET_CODE (elt
) != SET
9306 || GET_CODE (SET_SRC (elt
)) != MEM
9307 || GET_CODE (SET_DEST (elt
)) != REG
9308 || GET_MODE (SET_DEST (elt
)) != V4SImode
)
9312 for (i
=1; i
<= 18; i
++)
9314 elt
= XVECEXP (op
, 0, index
++);
9315 if (GET_CODE (elt
) != SET
9316 || GET_CODE (SET_SRC (elt
)) != MEM
9317 || ! memory_operand (SET_SRC (elt
), DFmode
)
9318 || GET_CODE (SET_DEST (elt
)) != REG
9319 || GET_MODE (SET_DEST (elt
)) != DFmode
)
9323 if (GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9324 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9325 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9326 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9327 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
)
9333 /* Return 1 if OP is a load multiple operation. It is known to be a
9334 PARALLEL and the first section will be tested. */
9337 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9339 int count
= XVECLEN (op
, 0);
9340 unsigned int dest_regno
;
9344 /* Perform a quick check so we don't blow up below. */
9346 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9347 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9348 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
9351 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9352 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
9354 for (i
= 1; i
< count
; i
++)
9356 rtx elt
= XVECEXP (op
, 0, i
);
9358 if (GET_CODE (elt
) != SET
9359 || GET_CODE (SET_DEST (elt
)) != REG
9360 || GET_MODE (SET_DEST (elt
)) != SImode
9361 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
9362 || GET_CODE (SET_SRC (elt
)) != MEM
9363 || GET_MODE (SET_SRC (elt
)) != SImode
9364 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
9365 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
9366 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
9367 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
9374 /* Similar, but tests for store multiple. Here, the second vector element
9375 is a CLOBBER. It will be tested later. */
9378 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9380 int count
= XVECLEN (op
, 0) - 1;
9381 unsigned int src_regno
;
9385 /* Perform a quick check so we don't blow up below. */
9387 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9388 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
9389 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
9392 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9393 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
9395 for (i
= 1; i
< count
; i
++)
9397 rtx elt
= XVECEXP (op
, 0, i
+ 1);
9399 if (GET_CODE (elt
) != SET
9400 || GET_CODE (SET_SRC (elt
)) != REG
9401 || GET_MODE (SET_SRC (elt
)) != SImode
9402 || REGNO (SET_SRC (elt
)) != src_regno
+ i
9403 || GET_CODE (SET_DEST (elt
)) != MEM
9404 || GET_MODE (SET_DEST (elt
)) != SImode
9405 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
9406 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
9407 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
9408 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
9415 /* Return a string to perform a load_multiple operation.
9416 operands[0] is the vector.
9417 operands[1] is the source address.
9418 operands[2] is the first destination register. */
9421 rs6000_output_load_multiple (rtx operands
[3])
9423 /* We have to handle the case where the pseudo used to contain the address
9424 is assigned to one of the output registers. */
9426 int words
= XVECLEN (operands
[0], 0);
9429 if (XVECLEN (operands
[0], 0) == 1)
9430 return "{l|lwz} %2,0(%1)";
9432 for (i
= 0; i
< words
; i
++)
9433 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
9434 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
9438 xop
[0] = GEN_INT (4 * (words
-1));
9439 xop
[1] = operands
[1];
9440 xop
[2] = operands
[2];
9441 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
9446 xop
[0] = GEN_INT (4 * (words
-1));
9447 xop
[1] = operands
[1];
9448 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
9449 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
9454 for (j
= 0; j
< words
; j
++)
9457 xop
[0] = GEN_INT (j
* 4);
9458 xop
[1] = operands
[1];
9459 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
9460 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
9462 xop
[0] = GEN_INT (i
* 4);
9463 xop
[1] = operands
[1];
9464 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
9469 return "{lsi|lswi} %2,%1,%N0";
9472 /* Return 1 for a parallel vrsave operation. */
9475 vrsave_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9477 int count
= XVECLEN (op
, 0);
9478 unsigned int dest_regno
, src_regno
;
9482 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9483 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9484 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC_VOLATILE
)
9487 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9488 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9490 if (dest_regno
!= VRSAVE_REGNO
9491 && src_regno
!= VRSAVE_REGNO
)
9494 for (i
= 1; i
< count
; i
++)
9496 rtx elt
= XVECEXP (op
, 0, i
);
9498 if (GET_CODE (elt
) != CLOBBER
9499 && GET_CODE (elt
) != SET
)
9506 /* Return 1 for an PARALLEL suitable for mfcr. */
9509 mfcr_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9511 int count
= XVECLEN (op
, 0);
9514 /* Perform a quick check so we don't blow up below. */
9516 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9517 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
9518 || XVECLEN (SET_SRC (XVECEXP (op
, 0, 0)), 0) != 2)
9521 for (i
= 0; i
< count
; i
++)
9523 rtx exp
= XVECEXP (op
, 0, i
);
9528 src_reg
= XVECEXP (SET_SRC (exp
), 0, 0);
9530 if (GET_CODE (src_reg
) != REG
9531 || GET_MODE (src_reg
) != CCmode
9532 || ! CR_REGNO_P (REGNO (src_reg
)))
9535 if (GET_CODE (exp
) != SET
9536 || GET_CODE (SET_DEST (exp
)) != REG
9537 || GET_MODE (SET_DEST (exp
)) != SImode
9538 || ! INT_REGNO_P (REGNO (SET_DEST (exp
))))
9540 unspec
= SET_SRC (exp
);
9541 maskval
= 1 << (MAX_CR_REGNO
- REGNO (src_reg
));
9543 if (GET_CODE (unspec
) != UNSPEC
9544 || XINT (unspec
, 1) != UNSPEC_MOVESI_FROM_CR
9545 || XVECLEN (unspec
, 0) != 2
9546 || XVECEXP (unspec
, 0, 0) != src_reg
9547 || GET_CODE (XVECEXP (unspec
, 0, 1)) != CONST_INT
9548 || INTVAL (XVECEXP (unspec
, 0, 1)) != maskval
)
9554 /* Return 1 for an PARALLEL suitable for mtcrf. */
9557 mtcrf_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9559 int count
= XVECLEN (op
, 0);
9563 /* Perform a quick check so we don't blow up below. */
9565 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9566 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
9567 || XVECLEN (SET_SRC (XVECEXP (op
, 0, 0)), 0) != 2)
9569 src_reg
= XVECEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0, 0);
9571 if (GET_CODE (src_reg
) != REG
9572 || GET_MODE (src_reg
) != SImode
9573 || ! INT_REGNO_P (REGNO (src_reg
)))
9576 for (i
= 0; i
< count
; i
++)
9578 rtx exp
= XVECEXP (op
, 0, i
);
9582 if (GET_CODE (exp
) != SET
9583 || GET_CODE (SET_DEST (exp
)) != REG
9584 || GET_MODE (SET_DEST (exp
)) != CCmode
9585 || ! CR_REGNO_P (REGNO (SET_DEST (exp
))))
9587 unspec
= SET_SRC (exp
);
9588 maskval
= 1 << (MAX_CR_REGNO
- REGNO (SET_DEST (exp
)));
9590 if (GET_CODE (unspec
) != UNSPEC
9591 || XINT (unspec
, 1) != UNSPEC_MOVESI_TO_CR
9592 || XVECLEN (unspec
, 0) != 2
9593 || XVECEXP (unspec
, 0, 0) != src_reg
9594 || GET_CODE (XVECEXP (unspec
, 0, 1)) != CONST_INT
9595 || INTVAL (XVECEXP (unspec
, 0, 1)) != maskval
)
9601 /* Return 1 for an PARALLEL suitable for lmw. */
9604 lmw_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9606 int count
= XVECLEN (op
, 0);
9607 unsigned int dest_regno
;
9609 unsigned int base_regno
;
9610 HOST_WIDE_INT offset
;
9613 /* Perform a quick check so we don't blow up below. */
9615 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9616 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9617 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
9620 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9621 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
9624 || count
!= 32 - (int) dest_regno
)
9627 if (legitimate_indirect_address_p (src_addr
, 0))
9630 base_regno
= REGNO (src_addr
);
9631 if (base_regno
== 0)
9634 else if (rs6000_legitimate_offset_address_p (SImode
, src_addr
, 0))
9636 offset
= INTVAL (XEXP (src_addr
, 1));
9637 base_regno
= REGNO (XEXP (src_addr
, 0));
9642 for (i
= 0; i
< count
; i
++)
9644 rtx elt
= XVECEXP (op
, 0, i
);
9647 HOST_WIDE_INT newoffset
;
9649 if (GET_CODE (elt
) != SET
9650 || GET_CODE (SET_DEST (elt
)) != REG
9651 || GET_MODE (SET_DEST (elt
)) != SImode
9652 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
9653 || GET_CODE (SET_SRC (elt
)) != MEM
9654 || GET_MODE (SET_SRC (elt
)) != SImode
)
9656 newaddr
= XEXP (SET_SRC (elt
), 0);
9657 if (legitimate_indirect_address_p (newaddr
, 0))
9662 else if (rs6000_legitimate_offset_address_p (SImode
, newaddr
, 0))
9664 addr_reg
= XEXP (newaddr
, 0);
9665 newoffset
= INTVAL (XEXP (newaddr
, 1));
9669 if (REGNO (addr_reg
) != base_regno
9670 || newoffset
!= offset
+ 4 * i
)
9677 /* Return 1 for an PARALLEL suitable for stmw. */
9680 stmw_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9682 int count
= XVECLEN (op
, 0);
9683 unsigned int src_regno
;
9685 unsigned int base_regno
;
9686 HOST_WIDE_INT offset
;
9689 /* Perform a quick check so we don't blow up below. */
9691 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9692 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
9693 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
9696 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9697 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
9700 || count
!= 32 - (int) src_regno
)
9703 if (legitimate_indirect_address_p (dest_addr
, 0))
9706 base_regno
= REGNO (dest_addr
);
9707 if (base_regno
== 0)
9710 else if (rs6000_legitimate_offset_address_p (SImode
, dest_addr
, 0))
9712 offset
= INTVAL (XEXP (dest_addr
, 1));
9713 base_regno
= REGNO (XEXP (dest_addr
, 0));
9718 for (i
= 0; i
< count
; i
++)
9720 rtx elt
= XVECEXP (op
, 0, i
);
9723 HOST_WIDE_INT newoffset
;
9725 if (GET_CODE (elt
) != SET
9726 || GET_CODE (SET_SRC (elt
)) != REG
9727 || GET_MODE (SET_SRC (elt
)) != SImode
9728 || REGNO (SET_SRC (elt
)) != src_regno
+ i
9729 || GET_CODE (SET_DEST (elt
)) != MEM
9730 || GET_MODE (SET_DEST (elt
)) != SImode
)
9732 newaddr
= XEXP (SET_DEST (elt
), 0);
9733 if (legitimate_indirect_address_p (newaddr
, 0))
9738 else if (rs6000_legitimate_offset_address_p (SImode
, newaddr
, 0))
9740 addr_reg
= XEXP (newaddr
, 0);
9741 newoffset
= INTVAL (XEXP (newaddr
, 1));
9745 if (REGNO (addr_reg
) != base_regno
9746 || newoffset
!= offset
+ 4 * i
)
9753 /* A validation routine: say whether CODE, a condition code, and MODE
9754 match. The other alternatives either don't make sense or should
9755 never be generated. */
9758 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
9760 if ((GET_RTX_CLASS (code
) != RTX_COMPARE
9761 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
)
9762 || GET_MODE_CLASS (mode
) != MODE_CC
)
9765 /* These don't make sense. */
9766 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
9767 && mode
== CCUNSmode
)
9770 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
9771 && mode
!= CCUNSmode
)
9774 if (mode
!= CCFPmode
9775 && (code
== ORDERED
|| code
== UNORDERED
9776 || code
== UNEQ
|| code
== LTGT
9777 || code
== UNGT
|| code
== UNLT
9778 || code
== UNGE
|| code
== UNLE
))
9781 /* These should never be generated except for
9782 flag_finite_math_only. */
9783 if (mode
== CCFPmode
9784 && ! flag_finite_math_only
9785 && (code
== LE
|| code
== GE
9786 || code
== UNEQ
|| code
== LTGT
9787 || code
== UNGT
|| code
== UNLT
))
9790 /* These are invalid; the information is not there. */
9791 if (mode
== CCEQmode
9792 && code
!= EQ
&& code
!= NE
)
9796 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9797 We only check the opcode against the mode of the CC value here. */
9800 branch_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9802 enum rtx_code code
= GET_CODE (op
);
9803 enum machine_mode cc_mode
;
9805 if (!COMPARISON_P (op
))
9808 cc_mode
= GET_MODE (XEXP (op
, 0));
9809 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
9812 validate_condition_mode (code
, cc_mode
);
9817 /* Return 1 if OP is a comparison operation that is valid for a branch
9818 insn and which is true if the corresponding bit in the CC register
9822 branch_positive_comparison_operator (rtx op
, enum machine_mode mode
)
9826 if (! branch_comparison_operator (op
, mode
))
9829 code
= GET_CODE (op
);
9830 return (code
== EQ
|| code
== LT
|| code
== GT
9831 || code
== LTU
|| code
== GTU
9832 || code
== UNORDERED
);
9835 /* Return 1 if OP is a comparison operation that is valid for an scc
9836 insn: it must be a positive comparison. */
9839 scc_comparison_operator (rtx op
, enum machine_mode mode
)
9841 return branch_positive_comparison_operator (op
, mode
);
9845 trap_comparison_operator (rtx op
, enum machine_mode mode
)
9847 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
9849 return COMPARISON_P (op
);
9853 boolean_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9855 enum rtx_code code
= GET_CODE (op
);
9856 return (code
== AND
|| code
== IOR
|| code
== XOR
);
9860 boolean_or_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9862 enum rtx_code code
= GET_CODE (op
);
9863 return (code
== IOR
|| code
== XOR
);
9867 min_max_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9869 enum rtx_code code
= GET_CODE (op
);
9870 return (code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
);
9873 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9874 mask required to convert the result of a rotate insn into a shift
9875 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878 includes_lshift_p (rtx shiftop
, rtx andop
)
9880 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9882 shift_mask
<<= INTVAL (shiftop
);
9884 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9887 /* Similar, but for right shift. */
9890 includes_rshift_p (rtx shiftop
, rtx andop
)
9892 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9894 shift_mask
>>= INTVAL (shiftop
);
9896 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9899 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9900 to perform a left shift. It must have exactly SHIFTOP least
9901 significant 0's, then one or more 1's, then zero or more 0's. */
9904 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
9906 if (GET_CODE (andop
) == CONST_INT
)
9908 HOST_WIDE_INT c
, lsb
, shift_mask
;
9911 if (c
== 0 || c
== ~0)
9915 shift_mask
<<= INTVAL (shiftop
);
9917 /* Find the least significant one bit. */
9920 /* It must coincide with the LSB of the shift mask. */
9921 if (-lsb
!= shift_mask
)
9924 /* Invert to look for the next transition (if any). */
9927 /* Remove the low group of ones (originally low group of zeros). */
9930 /* Again find the lsb, and check we have all 1's above. */
9934 else if (GET_CODE (andop
) == CONST_DOUBLE
9935 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
9937 HOST_WIDE_INT low
, high
, lsb
;
9938 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
9940 low
= CONST_DOUBLE_LOW (andop
);
9941 if (HOST_BITS_PER_WIDE_INT
< 64)
9942 high
= CONST_DOUBLE_HIGH (andop
);
9944 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
9945 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
9948 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9950 shift_mask_high
= ~0;
9951 if (INTVAL (shiftop
) > 32)
9952 shift_mask_high
<<= INTVAL (shiftop
) - 32;
9956 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
9963 return high
== -lsb
;
9966 shift_mask_low
= ~0;
9967 shift_mask_low
<<= INTVAL (shiftop
);
9971 if (-lsb
!= shift_mask_low
)
9974 if (HOST_BITS_PER_WIDE_INT
< 64)
9979 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9982 return high
== -lsb
;
9986 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
9992 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9993 to perform a left shift. It must have SHIFTOP or more least
9994 significant 0's, with the remainder of the word 1's. */
9997 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
9999 if (GET_CODE (andop
) == CONST_INT
)
10001 HOST_WIDE_INT c
, lsb
, shift_mask
;
10004 shift_mask
<<= INTVAL (shiftop
);
10005 c
= INTVAL (andop
);
10007 /* Find the least significant one bit. */
10010 /* It must be covered by the shift mask.
10011 This test also rejects c == 0. */
10012 if ((lsb
& shift_mask
) == 0)
10015 /* Check we have all 1's above the transition, and reject all 1's. */
10016 return c
== -lsb
&& lsb
!= 1;
10018 else if (GET_CODE (andop
) == CONST_DOUBLE
10019 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
10021 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
10023 low
= CONST_DOUBLE_LOW (andop
);
10025 if (HOST_BITS_PER_WIDE_INT
< 64)
10027 HOST_WIDE_INT high
, shift_mask_high
;
10029 high
= CONST_DOUBLE_HIGH (andop
);
10033 shift_mask_high
= ~0;
10034 if (INTVAL (shiftop
) > 32)
10035 shift_mask_high
<<= INTVAL (shiftop
) - 32;
10037 lsb
= high
& -high
;
10039 if ((lsb
& shift_mask_high
) == 0)
10042 return high
== -lsb
;
10048 shift_mask_low
= ~0;
10049 shift_mask_low
<<= INTVAL (shiftop
);
10053 if ((lsb
& shift_mask_low
) == 0)
10056 return low
== -lsb
&& lsb
!= 1;
10062 /* Return 1 if operands will generate a valid arguments to rlwimi
10063 instruction for insert with right shift in 64-bit mode. The mask may
10064 not start on the first bit or stop on the last bit because wrap-around
10065 effects of instruction do not correspond to semantics of RTL insn. */
10068 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
10070 if (INTVAL (startop
) < 64
10071 && INTVAL (startop
) > 32
10072 && (INTVAL (sizeop
) + INTVAL (startop
) < 64)
10073 && (INTVAL (sizeop
) + INTVAL (startop
) > 33)
10074 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) < 96)
10075 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) >= 64)
10076 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
10082 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10083 for lfq and stfq insns iff the registers are hard registers. */
10086 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
10088 /* We might have been passed a SUBREG. */
10089 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
10092 /* We might have been passed non floating point registers. */
10093 if (!FP_REGNO_P (REGNO (reg1
))
10094 || !FP_REGNO_P (REGNO (reg2
)))
10097 return (REGNO (reg1
) == REGNO (reg2
) - 1);
10100 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10101 addr1 and addr2 must be in consecutive memory locations
10102 (addr2 == addr1 + 8). */
10105 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
10111 /* The mems cannot be volatile. */
10112 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
10115 addr1
= XEXP (mem1
, 0);
10116 addr2
= XEXP (mem2
, 0);
10118 /* Extract an offset (if used) from the first addr. */
10119 if (GET_CODE (addr1
) == PLUS
)
10121 /* If not a REG, return zero. */
10122 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
10126 reg1
= REGNO (XEXP (addr1
, 0));
10127 /* The offset must be constant! */
10128 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
10130 offset1
= INTVAL (XEXP (addr1
, 1));
10133 else if (GET_CODE (addr1
) != REG
)
10137 reg1
= REGNO (addr1
);
10138 /* This was a simple (mem (reg)) expression. Offset is 0. */
10142 /* Make sure the second address is a (mem (plus (reg) (const_int)))
10143 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
10144 register as addr1. */
10145 if (offset1
== -8 && GET_CODE (addr2
) == REG
&& reg1
== REGNO (addr2
))
10147 if (GET_CODE (addr2
) != PLUS
)
10150 if (GET_CODE (XEXP (addr2
, 0)) != REG
10151 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
10154 if (reg1
!= REGNO (XEXP (addr2
, 0)))
10157 /* The offset for the second addr must be 8 more than the first addr. */
10158 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 8)
10161 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10166 /* Return the register class of a scratch register needed to copy IN into
10167 or out of a register in CLASS in MODE. If it can be done directly,
10168 NO_REGS is returned. */
10171 secondary_reload_class (enum reg_class
class,
10172 enum machine_mode mode ATTRIBUTE_UNUSED
,
10177 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
10179 && MACHOPIC_INDIRECT
10183 /* We cannot copy a symbolic operand directly into anything
10184 other than BASE_REGS for TARGET_ELF. So indicate that a
10185 register from BASE_REGS is needed as an intermediate
10188 On Darwin, pic addresses require a load from memory, which
10189 needs a base register. */
10190 if (class != BASE_REGS
10191 && (GET_CODE (in
) == SYMBOL_REF
10192 || GET_CODE (in
) == HIGH
10193 || GET_CODE (in
) == LABEL_REF
10194 || GET_CODE (in
) == CONST
))
10198 if (GET_CODE (in
) == REG
)
10200 regno
= REGNO (in
);
10201 if (regno
>= FIRST_PSEUDO_REGISTER
)
10203 regno
= true_regnum (in
);
10204 if (regno
>= FIRST_PSEUDO_REGISTER
)
10208 else if (GET_CODE (in
) == SUBREG
)
10210 regno
= true_regnum (in
);
10211 if (regno
>= FIRST_PSEUDO_REGISTER
)
10217 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10219 if (class == GENERAL_REGS
|| class == BASE_REGS
10220 || (regno
>= 0 && INT_REGNO_P (regno
)))
10223 /* Constants, memory, and FP registers can go into FP registers. */
10224 if ((regno
== -1 || FP_REGNO_P (regno
))
10225 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
10228 /* Memory, and AltiVec registers can go into AltiVec registers. */
10229 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
10230 && class == ALTIVEC_REGS
)
10233 /* We can copy among the CR registers. */
10234 if ((class == CR_REGS
|| class == CR0_REGS
)
10235 && regno
>= 0 && CR_REGNO_P (regno
))
10238 /* Otherwise, we need GENERAL_REGS. */
10239 return GENERAL_REGS
;
10242 /* Given a comparison operation, return the bit number in CCR to test. We
10243 know this is a valid comparison.
10245 SCC_P is 1 if this is for an scc. That means that %D will have been
10246 used instead of %C, so the bits will be in different places.
10248 Return -1 if OP isn't a valid comparison for some reason. */
10251 ccr_bit (rtx op
, int scc_p
)
10253 enum rtx_code code
= GET_CODE (op
);
10254 enum machine_mode cc_mode
;
10259 if (!COMPARISON_P (op
))
10262 reg
= XEXP (op
, 0);
10264 if (GET_CODE (reg
) != REG
10265 || ! CR_REGNO_P (REGNO (reg
)))
10268 cc_mode
= GET_MODE (reg
);
10269 cc_regnum
= REGNO (reg
);
10270 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
10272 validate_condition_mode (code
, cc_mode
);
10274 /* When generating a sCOND operation, only positive conditions are
10276 if (scc_p
&& code
!= EQ
&& code
!= GT
&& code
!= LT
&& code
!= UNORDERED
10277 && code
!= GTU
&& code
!= LTU
)
10283 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
10285 return base_bit
+ 2;
10286 case GT
: case GTU
: case UNLE
:
10287 return base_bit
+ 1;
10288 case LT
: case LTU
: case UNGE
:
10290 case ORDERED
: case UNORDERED
:
10291 return base_bit
+ 3;
10294 /* If scc, we will have done a cror to put the bit in the
10295 unordered position. So test that bit. For integer, this is ! LT
10296 unless this is an scc insn. */
10297 return scc_p
? base_bit
+ 3 : base_bit
;
10300 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
10307 /* Return the GOT register. */
10310 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
10312 /* The second flow pass currently (June 1999) can't update
10313 regs_ever_live without disturbing other parts of the compiler, so
10314 update it here to make the prolog/epilogue code happy. */
10315 if (no_new_pseudos
&& ! regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
])
10316 regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
10318 current_function_uses_pic_offset_table
= 1;
10320 return pic_offset_table_rtx
;
10323 /* Function to init struct machine_function.
10324 This will be called, via a pointer variable,
10325 from push_function_context. */
10327 static struct machine_function
*
10328 rs6000_init_machine_status (void)
10330 return ggc_alloc_cleared (sizeof (machine_function
));
10333 /* These macros test for integers and extract the low-order bits. */
10335 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10336 && GET_MODE (X) == VOIDmode)
10338 #define INT_LOWPART(X) \
10339 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10342 extract_MB (rtx op
)
10345 unsigned long val
= INT_LOWPART (op
);
10347 /* If the high bit is zero, the value is the first 1 bit we find
10349 if ((val
& 0x80000000) == 0)
10351 if ((val
& 0xffffffff) == 0)
10355 while (((val
<<= 1) & 0x80000000) == 0)
10360 /* If the high bit is set and the low bit is not, or the mask is all
10361 1's, the value is zero. */
10362 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
10365 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10368 while (((val
>>= 1) & 1) != 0)
10375 extract_ME (rtx op
)
10378 unsigned long val
= INT_LOWPART (op
);
10380 /* If the low bit is zero, the value is the first 1 bit we find from
10382 if ((val
& 1) == 0)
10384 if ((val
& 0xffffffff) == 0)
10388 while (((val
>>= 1) & 1) == 0)
10394 /* If the low bit is set and the high bit is not, or the mask is all
10395 1's, the value is 31. */
10396 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
10399 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10402 while (((val
<<= 1) & 0x80000000) != 0)
10408 /* Locate some local-dynamic symbol still in use by this function
10409 so that we can print its name in some tls_ld pattern. */
10411 static const char *
10412 rs6000_get_some_local_dynamic_name (void)
10416 if (cfun
->machine
->some_ld_name
)
10417 return cfun
->machine
->some_ld_name
;
10419 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10421 && for_each_rtx (&PATTERN (insn
),
10422 rs6000_get_some_local_dynamic_name_1
, 0))
10423 return cfun
->machine
->some_ld_name
;
10428 /* Helper function for rs6000_get_some_local_dynamic_name. */
10431 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10435 if (GET_CODE (x
) == SYMBOL_REF
)
10437 const char *str
= XSTR (x
, 0);
10438 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10440 cfun
->machine
->some_ld_name
= str
;
10448 /* Write out a function code label. */
10451 rs6000_output_function_entry (FILE *file
, const char *fname
)
10453 if (fname
[0] != '.')
10455 switch (DEFAULT_ABI
)
10464 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
10473 RS6000_OUTPUT_BASENAME (file
, fname
);
10475 assemble_name (file
, fname
);
10478 /* Print an operand. Recognize special options, documented below. */
10481 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10482 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10484 #define SMALL_DATA_RELOC "sda21"
10485 #define SMALL_DATA_REG 0
10489 print_operand (FILE *file
, rtx x
, int code
)
10493 unsigned HOST_WIDE_INT uval
;
10498 /* Write out an instruction after the call which may be replaced
10499 with glue code by the loader. This depends on the AIX version. */
10500 asm_fprintf (file
, RS6000_CALL_GLUE
);
10503 /* %a is output_address. */
10506 /* If X is a constant integer whose low-order 5 bits are zero,
10507 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10508 in the AIX assembler where "sri" with a zero shift count
10509 writes a trash instruction. */
10510 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
10517 /* If constant, low-order 16 bits of constant, unsigned.
10518 Otherwise, write normally. */
10520 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
10522 print_operand (file
, x
, 0);
10526 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10527 for 64-bit mask direction. */
10528 putc (((INT_LOWPART(x
) & 1) == 0 ? 'r' : 'l'), file
);
10531 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10535 /* X is a CR register. Print the number of the GT bit of the CR. */
10536 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10537 output_operand_lossage ("invalid %%E value");
10539 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
10543 /* Like 'J' but get to the EQ bit. */
10544 if (GET_CODE (x
) != REG
)
10547 /* Bit 1 is EQ bit. */
10548 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 2;
10550 /* If we want bit 31, write a shift count of zero, not 32. */
10551 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10555 /* X is a CR register. Print the number of the EQ bit of the CR */
10556 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10557 output_operand_lossage ("invalid %%E value");
10559 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
10563 /* X is a CR register. Print the shift count needed to move it
10564 to the high-order four bits. */
10565 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10566 output_operand_lossage ("invalid %%f value");
10568 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
10572 /* Similar, but print the count for the rotate in the opposite
10574 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10575 output_operand_lossage ("invalid %%F value");
10577 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
10581 /* X is a constant integer. If it is negative, print "m",
10582 otherwise print "z". This is to make an aze or ame insn. */
10583 if (GET_CODE (x
) != CONST_INT
)
10584 output_operand_lossage ("invalid %%G value");
10585 else if (INTVAL (x
) >= 0)
10592 /* If constant, output low-order five bits. Otherwise, write
10595 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
10597 print_operand (file
, x
, 0);
10601 /* If constant, output low-order six bits. Otherwise, write
10604 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
10606 print_operand (file
, x
, 0);
10610 /* Print `i' if this is a constant, else nothing. */
10616 /* Write the bit number in CCR for jump. */
10617 i
= ccr_bit (x
, 0);
10619 output_operand_lossage ("invalid %%j code");
10621 fprintf (file
, "%d", i
);
10625 /* Similar, but add one for shift count in rlinm for scc and pass
10626 scc flag to `ccr_bit'. */
10627 i
= ccr_bit (x
, 1);
10629 output_operand_lossage ("invalid %%J code");
10631 /* If we want bit 31, write a shift count of zero, not 32. */
10632 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10636 /* X must be a constant. Write the 1's complement of the
10639 output_operand_lossage ("invalid %%k value");
10641 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
10645 /* X must be a symbolic constant on ELF. Write an
10646 expression suitable for an 'addi' that adds in the low 16
10647 bits of the MEM. */
10648 if (GET_CODE (x
) != CONST
)
10650 print_operand_address (file
, x
);
10651 fputs ("@l", file
);
10655 if (GET_CODE (XEXP (x
, 0)) != PLUS
10656 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
10657 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
10658 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
10659 output_operand_lossage ("invalid %%K value");
10660 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
10661 fputs ("@l", file
);
10662 /* For GNU as, there must be a non-alphanumeric character
10663 between 'l' and the number. The '-' is added by
10664 print_operand() already. */
10665 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
10667 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
10671 /* %l is output_asm_label. */
10674 /* Write second word of DImode or DFmode reference. Works on register
10675 or non-indexed memory only. */
10676 if (GET_CODE (x
) == REG
)
10677 fputs (reg_names
[REGNO (x
) + 1], file
);
10678 else if (GET_CODE (x
) == MEM
)
10680 /* Handle possible auto-increment. Since it is pre-increment and
10681 we have already done it, we can just use an offset of word. */
10682 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10683 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10684 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
10687 output_address (XEXP (adjust_address_nv (x
, SImode
,
10691 if (small_data_operand (x
, GET_MODE (x
)))
10692 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10693 reg_names
[SMALL_DATA_REG
]);
10698 /* MB value for a mask operand. */
10699 if (! mask_operand (x
, SImode
))
10700 output_operand_lossage ("invalid %%m value");
10702 fprintf (file
, "%d", extract_MB (x
));
10706 /* ME value for a mask operand. */
10707 if (! mask_operand (x
, SImode
))
10708 output_operand_lossage ("invalid %%M value");
10710 fprintf (file
, "%d", extract_ME (x
));
10713 /* %n outputs the negative of its operand. */
10716 /* Write the number of elements in the vector times 4. */
10717 if (GET_CODE (x
) != PARALLEL
)
10718 output_operand_lossage ("invalid %%N value");
10720 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
10724 /* Similar, but subtract 1 first. */
10725 if (GET_CODE (x
) != PARALLEL
)
10726 output_operand_lossage ("invalid %%O value");
10728 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
10732 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10734 || INT_LOWPART (x
) < 0
10735 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
10736 output_operand_lossage ("invalid %%p value");
10738 fprintf (file
, "%d", i
);
10742 /* The operand must be an indirect memory reference. The result
10743 is the register name. */
10744 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
10745 || REGNO (XEXP (x
, 0)) >= 32)
10746 output_operand_lossage ("invalid %%P value");
10748 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
10752 /* This outputs the logical code corresponding to a boolean
10753 expression. The expression may have one or both operands
10754 negated (if one, only the first one). For condition register
10755 logical operations, it will also treat the negated
10756 CR codes as NOTs, but not handle NOTs of them. */
10758 const char *const *t
= 0;
10760 enum rtx_code code
= GET_CODE (x
);
10761 static const char * const tbl
[3][3] = {
10762 { "and", "andc", "nor" },
10763 { "or", "orc", "nand" },
10764 { "xor", "eqv", "xor" } };
10768 else if (code
== IOR
)
10770 else if (code
== XOR
)
10773 output_operand_lossage ("invalid %%q value");
10775 if (GET_CODE (XEXP (x
, 0)) != NOT
)
10779 if (GET_CODE (XEXP (x
, 1)) == NOT
)
10797 /* X is a CR register. Print the mask for `mtcrf'. */
10798 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10799 output_operand_lossage ("invalid %%R value");
10801 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
10805 /* Low 5 bits of 32 - value */
10807 output_operand_lossage ("invalid %%s value");
10809 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
10813 /* PowerPC64 mask position. All 0's is excluded.
10814 CONST_INT 32-bit mask is considered sign-extended so any
10815 transition must occur within the CONST_INT, not on the boundary. */
10816 if (! mask64_operand (x
, DImode
))
10817 output_operand_lossage ("invalid %%S value");
10819 uval
= INT_LOWPART (x
);
10821 if (uval
& 1) /* Clear Left */
10823 #if HOST_BITS_PER_WIDE_INT > 64
10824 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10828 else /* Clear Right */
10831 #if HOST_BITS_PER_WIDE_INT > 64
10832 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10840 fprintf (file
, "%d", i
);
10844 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10845 if (GET_CODE (x
) != REG
|| GET_MODE (x
) != CCmode
)
10848 /* Bit 3 is OV bit. */
10849 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
10851 /* If we want bit 31, write a shift count of zero, not 32. */
10852 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10856 /* Print the symbolic name of a branch target register. */
10857 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LINK_REGISTER_REGNUM
10858 && REGNO (x
) != COUNT_REGISTER_REGNUM
))
10859 output_operand_lossage ("invalid %%T value");
10860 else if (REGNO (x
) == LINK_REGISTER_REGNUM
)
10861 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
10863 fputs ("ctr", file
);
10867 /* High-order 16 bits of constant for use in unsigned operand. */
10869 output_operand_lossage ("invalid %%u value");
10871 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10872 (INT_LOWPART (x
) >> 16) & 0xffff);
10876 /* High-order 16 bits of constant for use in signed operand. */
10878 output_operand_lossage ("invalid %%v value");
10880 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10881 (INT_LOWPART (x
) >> 16) & 0xffff);
10885 /* Print `u' if this has an auto-increment or auto-decrement. */
10886 if (GET_CODE (x
) == MEM
10887 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
10888 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
10893 /* Print the trap code for this operand. */
10894 switch (GET_CODE (x
))
10897 fputs ("eq", file
); /* 4 */
10900 fputs ("ne", file
); /* 24 */
10903 fputs ("lt", file
); /* 16 */
10906 fputs ("le", file
); /* 20 */
10909 fputs ("gt", file
); /* 8 */
10912 fputs ("ge", file
); /* 12 */
10915 fputs ("llt", file
); /* 2 */
10918 fputs ("lle", file
); /* 6 */
10921 fputs ("lgt", file
); /* 1 */
10924 fputs ("lge", file
); /* 5 */
10932 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10935 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
10936 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
10938 print_operand (file
, x
, 0);
10942 /* MB value for a PowerPC64 rldic operand. */
10943 val
= (GET_CODE (x
) == CONST_INT
10944 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
10949 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
10950 if ((val
<<= 1) < 0)
10953 #if HOST_BITS_PER_WIDE_INT == 32
10954 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
10955 i
+= 32; /* zero-extend high-part was all 0's */
10956 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
10958 val
= CONST_DOUBLE_LOW (x
);
10965 for ( ; i
< 64; i
++)
10966 if ((val
<<= 1) < 0)
10971 fprintf (file
, "%d", i
+ 1);
10975 if (GET_CODE (x
) == MEM
10976 && legitimate_indexed_address_p (XEXP (x
, 0), 0))
10981 /* Like 'L', for third word of TImode */
10982 if (GET_CODE (x
) == REG
)
10983 fputs (reg_names
[REGNO (x
) + 2], file
);
10984 else if (GET_CODE (x
) == MEM
)
10986 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10987 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10988 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
10990 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
10991 if (small_data_operand (x
, GET_MODE (x
)))
10992 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10993 reg_names
[SMALL_DATA_REG
]);
10998 /* X is a SYMBOL_REF. Write out the name preceded by a
10999 period and without any trailing data in brackets. Used for function
11000 names. If we are configured for System V (or the embedded ABI) on
11001 the PowerPC, do not emit the period, since those systems do not use
11002 TOCs and the like. */
11003 if (GET_CODE (x
) != SYMBOL_REF
)
11006 /* Mark the decl as referenced so that cgraph will output the
11008 if (SYMBOL_REF_DECL (x
))
11009 mark_decl_referenced (SYMBOL_REF_DECL (x
));
11011 /* For macho, check to see if we need a stub. */
11014 const char *name
= XSTR (x
, 0);
11016 if (MACHOPIC_INDIRECT
11017 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
11018 name
= machopic_indirection_name (x
, /*stub_p=*/true);
11020 assemble_name (file
, name
);
11022 else if (!DOT_SYMBOLS
)
11023 assemble_name (file
, XSTR (x
, 0));
11025 rs6000_output_function_entry (file
, XSTR (x
, 0));
11029 /* Like 'L', for last word of TImode. */
11030 if (GET_CODE (x
) == REG
)
11031 fputs (reg_names
[REGNO (x
) + 3], file
);
11032 else if (GET_CODE (x
) == MEM
)
11034 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11035 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11036 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
11038 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
11039 if (small_data_operand (x
, GET_MODE (x
)))
11040 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11041 reg_names
[SMALL_DATA_REG
]);
11045 /* Print AltiVec or SPE memory operand. */
11050 if (GET_CODE (x
) != MEM
)
11057 /* Handle [reg]. */
11058 if (GET_CODE (tmp
) == REG
)
11060 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
11063 /* Handle [reg+UIMM]. */
11064 else if (GET_CODE (tmp
) == PLUS
&&
11065 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
11069 if (GET_CODE (XEXP (tmp
, 0)) != REG
)
11072 x
= INTVAL (XEXP (tmp
, 1));
11073 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
11077 /* Fall through. Must be [reg+reg]. */
11080 && GET_CODE (tmp
) == AND
11081 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
11082 && INTVAL (XEXP (tmp
, 1)) == -16)
11083 tmp
= XEXP (tmp
, 0);
11084 if (GET_CODE (tmp
) == REG
)
11085 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
11086 else if (GET_CODE (tmp
) == PLUS
&& GET_CODE (XEXP (tmp
, 1)) == REG
)
11088 if (REGNO (XEXP (tmp
, 0)) == 0)
11089 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
11090 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
11092 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
11093 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
11101 if (GET_CODE (x
) == REG
)
11102 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
11103 else if (GET_CODE (x
) == MEM
)
11105 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11106 know the width from the mode. */
11107 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
11108 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
11109 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
11110 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11111 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
11112 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
11114 output_address (XEXP (x
, 0));
11117 output_addr_const (file
, x
);
11121 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
11125 output_operand_lossage ("invalid %%xn code");
11129 /* Print the address of an operand. */
11132 print_operand_address (FILE *file
, rtx x
)
11134 if (GET_CODE (x
) == REG
)
11135 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
11136 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
11137 || GET_CODE (x
) == LABEL_REF
)
11139 output_addr_const (file
, x
);
11140 if (small_data_operand (x
, GET_MODE (x
)))
11141 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11142 reg_names
[SMALL_DATA_REG
]);
11143 else if (TARGET_TOC
)
11146 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
11148 if (REGNO (XEXP (x
, 0)) == 0)
11149 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
11150 reg_names
[ REGNO (XEXP (x
, 0)) ]);
11152 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
11153 reg_names
[ REGNO (XEXP (x
, 1)) ]);
11155 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11156 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
11157 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
11159 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
11160 && CONSTANT_P (XEXP (x
, 1)))
11162 output_addr_const (file
, XEXP (x
, 1));
11163 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
11167 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
11168 && CONSTANT_P (XEXP (x
, 1)))
11170 fprintf (file
, "lo16(");
11171 output_addr_const (file
, XEXP (x
, 1));
11172 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
11175 else if (legitimate_constant_pool_address_p (x
))
11177 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
11179 rtx contains_minus
= XEXP (x
, 1);
11183 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11184 turn it into (sym) for output_addr_const. */
11185 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
11186 contains_minus
= XEXP (contains_minus
, 0);
11188 minus
= XEXP (contains_minus
, 0);
11189 symref
= XEXP (minus
, 0);
11190 XEXP (contains_minus
, 0) = symref
;
11195 name
= XSTR (symref
, 0);
11196 newname
= alloca (strlen (name
) + sizeof ("@toc"));
11197 strcpy (newname
, name
);
11198 strcat (newname
, "@toc");
11199 XSTR (symref
, 0) = newname
;
11201 output_addr_const (file
, XEXP (x
, 1));
11203 XSTR (symref
, 0) = name
;
11204 XEXP (contains_minus
, 0) = minus
;
11207 output_addr_const (file
, XEXP (x
, 1));
11209 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
11215 /* Target hook for assembling integer objects. The PowerPC version has
11216 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11217 is defined. It also needs to handle DI-mode objects on 64-bit
11221 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11223 #ifdef RELOCATABLE_NEEDS_FIXUP
11224 /* Special handling for SI values. */
11225 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
11227 extern int in_toc_section (void);
11228 static int recurse
= 0;
11230 /* For -mrelocatable, we mark all addresses that need to be fixed up
11231 in the .fixup section. */
11232 if (TARGET_RELOCATABLE
11233 && !in_toc_section ()
11234 && !in_text_section ()
11235 && !in_unlikely_text_section ()
11237 && GET_CODE (x
) != CONST_INT
11238 && GET_CODE (x
) != CONST_DOUBLE
11244 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
11246 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
11247 fprintf (asm_out_file
, "\t.long\t(");
11248 output_addr_const (asm_out_file
, x
);
11249 fprintf (asm_out_file
, ")@fixup\n");
11250 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
11251 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
11252 fprintf (asm_out_file
, "\t.long\t");
11253 assemble_name (asm_out_file
, buf
);
11254 fprintf (asm_out_file
, "\n\t.previous\n");
11258 /* Remove initial .'s to turn a -mcall-aixdesc function
11259 address into the address of the descriptor, not the function
11261 else if (GET_CODE (x
) == SYMBOL_REF
11262 && XSTR (x
, 0)[0] == '.'
11263 && DEFAULT_ABI
== ABI_AIX
)
11265 const char *name
= XSTR (x
, 0);
11266 while (*name
== '.')
11269 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
11273 #endif /* RELOCATABLE_NEEDS_FIXUP */
11274 return default_assemble_integer (x
, size
, aligned_p
);
11277 #ifdef HAVE_GAS_HIDDEN
11278 /* Emit an assembler directive to set symbol visibility for DECL to
11279 VISIBILITY_TYPE. */
11282 rs6000_assemble_visibility (tree decl
, int vis
)
11284 /* Functions need to have their entry point symbol visibility set as
11285 well as their descriptor symbol visibility. */
11286 if (DEFAULT_ABI
== ABI_AIX
11288 && TREE_CODE (decl
) == FUNCTION_DECL
)
11290 static const char * const visibility_types
[] = {
11291 NULL
, "internal", "hidden", "protected"
11294 const char *name
, *type
;
11296 name
= ((* targetm
.strip_name_encoding
)
11297 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
11298 type
= visibility_types
[vis
];
11300 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
11301 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
11304 default_assemble_visibility (decl
, vis
);
11309 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
11311 /* Reversal of FP compares takes care -- an ordered compare
11312 becomes an unordered compare and vice versa. */
11313 if (mode
== CCFPmode
11314 && (!flag_finite_math_only
11315 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
11316 || code
== UNEQ
|| code
== LTGT
))
11317 return reverse_condition_maybe_unordered (code
);
11319 return reverse_condition (code
);
11322 /* Generate a compare for CODE. Return a brand-new rtx that
11323 represents the result of the compare. */
11326 rs6000_generate_compare (enum rtx_code code
)
11328 enum machine_mode comp_mode
;
11329 rtx compare_result
;
11331 if (rs6000_compare_fp_p
)
11332 comp_mode
= CCFPmode
;
11333 else if (code
== GTU
|| code
== LTU
11334 || code
== GEU
|| code
== LEU
)
11335 comp_mode
= CCUNSmode
;
11336 else if ((code
== EQ
|| code
== NE
)
11337 && GET_CODE (rs6000_compare_op0
) == SUBREG
11338 && GET_CODE (rs6000_compare_op1
) == SUBREG
11339 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
11340 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
11341 /* These are unsigned values, perhaps there will be a later
11342 ordering compare that can be shared with this one.
11343 Unfortunately we cannot detect the signedness of the operands
11344 for non-subregs. */
11345 comp_mode
= CCUNSmode
;
11347 comp_mode
= CCmode
;
11349 /* First, the compare. */
11350 compare_result
= gen_reg_rtx (comp_mode
);
11352 /* SPE FP compare instructions on the GPRs. Yuck! */
11353 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
11354 && rs6000_compare_fp_p
)
11356 rtx cmp
, or1
, or2
, or_result
, compare_result2
;
11357 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
11359 if (op_mode
== VOIDmode
)
11360 op_mode
= GET_MODE (rs6000_compare_op1
);
11362 /* Note: The E500 comparison instructions set the GT bit (x +
11363 1), on success. This explains the mess. */
11367 case EQ
: case UNEQ
: case NE
: case LTGT
:
11368 if (op_mode
== SFmode
)
11369 cmp
= flag_unsafe_math_optimizations
11370 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
11371 rs6000_compare_op1
)
11372 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
11373 rs6000_compare_op1
);
11374 else if (op_mode
== DFmode
)
11375 cmp
= flag_unsafe_math_optimizations
11376 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
11377 rs6000_compare_op1
)
11378 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
11379 rs6000_compare_op1
);
11382 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
11383 if (op_mode
== SFmode
)
11384 cmp
= flag_unsafe_math_optimizations
11385 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
11386 rs6000_compare_op1
)
11387 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
11388 rs6000_compare_op1
);
11389 else if (op_mode
== DFmode
)
11390 cmp
= flag_unsafe_math_optimizations
11391 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
11392 rs6000_compare_op1
)
11393 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
11394 rs6000_compare_op1
);
11397 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
11398 if (op_mode
== SFmode
)
11399 cmp
= flag_unsafe_math_optimizations
11400 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
11401 rs6000_compare_op1
)
11402 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
11403 rs6000_compare_op1
);
11404 else if (op_mode
== DFmode
)
11405 cmp
= flag_unsafe_math_optimizations
11406 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
11407 rs6000_compare_op1
)
11408 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
11409 rs6000_compare_op1
);
11416 /* Synthesize LE and GE from LT/GT || EQ. */
11417 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
11423 case LE
: code
= LT
; break;
11424 case GE
: code
= GT
; break;
11425 case LEU
: code
= LT
; break;
11426 case GEU
: code
= GT
; break;
11430 or1
= gen_reg_rtx (SImode
);
11431 or2
= gen_reg_rtx (SImode
);
11432 or_result
= gen_reg_rtx (CCEQmode
);
11433 compare_result2
= gen_reg_rtx (CCFPmode
);
11436 if (op_mode
== SFmode
)
11437 cmp
= flag_unsafe_math_optimizations
11438 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
11439 rs6000_compare_op1
)
11440 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
11441 rs6000_compare_op1
);
11442 else if (op_mode
== DFmode
)
11443 cmp
= flag_unsafe_math_optimizations
11444 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
11445 rs6000_compare_op1
)
11446 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
11447 rs6000_compare_op1
);
11451 or1
= gen_rtx_GT (SImode
, compare_result
, const0_rtx
);
11452 or2
= gen_rtx_GT (SImode
, compare_result2
, const0_rtx
);
11454 /* OR them together. */
11455 cmp
= gen_rtx_SET (VOIDmode
, or_result
,
11456 gen_rtx_COMPARE (CCEQmode
,
11457 gen_rtx_IOR (SImode
, or1
, or2
),
11459 compare_result
= or_result
;
11464 if (code
== NE
|| code
== LTGT
)
11474 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11475 CLOBBERs to match cmptf_internal2 pattern. */
11476 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
11477 && GET_MODE (rs6000_compare_op0
) == TFmode
11478 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
11479 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
11480 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
11482 gen_rtx_SET (VOIDmode
,
11484 gen_rtx_COMPARE (comp_mode
,
11485 rs6000_compare_op0
,
11486 rs6000_compare_op1
)),
11487 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11488 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11489 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11490 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11491 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11492 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11493 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11494 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
11496 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
11497 gen_rtx_COMPARE (comp_mode
,
11498 rs6000_compare_op0
,
11499 rs6000_compare_op1
)));
11502 /* Some kinds of FP comparisons need an OR operation;
11503 under flag_unsafe_math_optimizations we don't bother. */
11504 if (rs6000_compare_fp_p
11505 && ! flag_unsafe_math_optimizations
11506 && ! (TARGET_HARD_FLOAT
&& TARGET_E500
&& !TARGET_FPRS
)
11507 && (code
== LE
|| code
== GE
11508 || code
== UNEQ
|| code
== LTGT
11509 || code
== UNGT
|| code
== UNLT
))
11511 enum rtx_code or1
, or2
;
11512 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
11513 rtx or_result
= gen_reg_rtx (CCEQmode
);
11517 case LE
: or1
= LT
; or2
= EQ
; break;
11518 case GE
: or1
= GT
; or2
= EQ
; break;
11519 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
11520 case LTGT
: or1
= LT
; or2
= GT
; break;
11521 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
11522 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
11525 validate_condition_mode (or1
, comp_mode
);
11526 validate_condition_mode (or2
, comp_mode
);
11527 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
11528 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
11529 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
11530 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
11532 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
11534 compare_result
= or_result
;
11538 validate_condition_mode (code
, GET_MODE (compare_result
));
11540 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
11544 /* Emit the RTL for an sCOND pattern. */
11547 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
11550 enum machine_mode op_mode
;
11551 enum rtx_code cond_code
;
11553 condition_rtx
= rs6000_generate_compare (code
);
11554 cond_code
= GET_CODE (condition_rtx
);
11556 if (TARGET_E500
&& rs6000_compare_fp_p
11557 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
11561 PUT_MODE (condition_rtx
, SImode
);
11562 t
= XEXP (condition_rtx
, 0);
11564 if (cond_code
!= NE
&& cond_code
!= EQ
)
11567 if (cond_code
== NE
)
11568 emit_insn (gen_e500_flip_eq_bit (t
, t
));
11570 emit_insn (gen_move_from_CR_eq_bit (result
, t
));
11574 if (cond_code
== NE
11575 || cond_code
== GE
|| cond_code
== LE
11576 || cond_code
== GEU
|| cond_code
== LEU
11577 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
11579 rtx not_result
= gen_reg_rtx (CCEQmode
);
11580 rtx not_op
, rev_cond_rtx
;
11581 enum machine_mode cc_mode
;
11583 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
11585 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
11586 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
11587 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
11588 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
11589 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
11592 op_mode
= GET_MODE (rs6000_compare_op0
);
11593 if (op_mode
== VOIDmode
)
11594 op_mode
= GET_MODE (rs6000_compare_op1
);
11596 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
11598 PUT_MODE (condition_rtx
, DImode
);
11599 convert_move (result
, condition_rtx
, 0);
11603 PUT_MODE (condition_rtx
, SImode
);
11604 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
11608 /* Emit a branch of kind CODE to location LOC. */
11611 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
11613 rtx condition_rtx
, loc_ref
;
11615 condition_rtx
= rs6000_generate_compare (code
);
11616 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
11617 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
11618 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
11619 loc_ref
, pc_rtx
)));
11622 /* Return the string to output a conditional branch to LABEL, which is
11623 the operand number of the label, or -1 if the branch is really a
11624 conditional return.
11626 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11627 condition code register and its mode specifies what kind of
11628 comparison we made.
11630 REVERSED is nonzero if we should reverse the sense of the comparison.
11632 INSN is the insn. */
11635 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
11637 static char string
[64];
11638 enum rtx_code code
= GET_CODE (op
);
11639 rtx cc_reg
= XEXP (op
, 0);
11640 enum machine_mode mode
= GET_MODE (cc_reg
);
11641 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
11642 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
11643 int really_reversed
= reversed
^ need_longbranch
;
11649 validate_condition_mode (code
, mode
);
11651 /* Work out which way this really branches. We could use
11652 reverse_condition_maybe_unordered here always but this
11653 makes the resulting assembler clearer. */
11654 if (really_reversed
)
11656 /* Reversal of FP compares takes care -- an ordered compare
11657 becomes an unordered compare and vice versa. */
11658 if (mode
== CCFPmode
)
11659 code
= reverse_condition_maybe_unordered (code
);
11661 code
= reverse_condition (code
);
11664 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
11666 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11669 /* Opposite of GT. */
11671 else if (code
== NE
)
11679 /* Not all of these are actually distinct opcodes, but
11680 we distinguish them for clarity of the resulting assembler. */
11681 case NE
: case LTGT
:
11682 ccode
= "ne"; break;
11683 case EQ
: case UNEQ
:
11684 ccode
= "eq"; break;
11686 ccode
= "ge"; break;
11687 case GT
: case GTU
: case UNGT
:
11688 ccode
= "gt"; break;
11690 ccode
= "le"; break;
11691 case LT
: case LTU
: case UNLT
:
11692 ccode
= "lt"; break;
11693 case UNORDERED
: ccode
= "un"; break;
11694 case ORDERED
: ccode
= "nu"; break;
11695 case UNGE
: ccode
= "nl"; break;
11696 case UNLE
: ccode
= "ng"; break;
11701 /* Maybe we have a guess as to how likely the branch is.
11702 The old mnemonics don't have a way to specify this information. */
11704 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
11705 if (note
!= NULL_RTX
)
11707 /* PROB is the difference from 50%. */
11708 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
11710 /* Only hint for highly probable/improbable branches on newer
11711 cpus as static prediction overrides processor dynamic
11712 prediction. For older cpus we may as well always hint, but
11713 assume not taken for branches that are very close to 50% as a
11714 mispredicted taken branch is more expensive than a
11715 mispredicted not-taken branch. */
11716 if (rs6000_always_hint
11717 || abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48)
11719 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
11720 && ((prob
> 0) ^ need_longbranch
))
11728 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
11730 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
11732 /* We need to escape any '%' characters in the reg_names string.
11733 Assume they'd only be the first character.... */
11734 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
11736 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
11740 /* If the branch distance was too far, we may have to use an
11741 unconditional branch to go the distance. */
11742 if (need_longbranch
)
11743 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
11745 s
+= sprintf (s
, ",%s", label
);
11751 /* Return the string to flip the EQ bit on a CR. */
11753 output_e500_flip_eq_bit (rtx dst
, rtx src
)
11755 static char string
[64];
11758 if (GET_CODE (dst
) != REG
|| ! CR_REGNO_P (REGNO (dst
))
11759 || GET_CODE (src
) != REG
|| ! CR_REGNO_P (REGNO (src
)))
11763 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 2;
11764 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 2;
11766 sprintf (string
, "crnot %d,%d", a
, b
);
11770 /* Return insn index for the vector compare instruction for given CODE,
11771 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11775 get_vec_cmp_insn (enum rtx_code code
,
11776 enum machine_mode dest_mode
,
11777 enum machine_mode op_mode
)
11779 if (!TARGET_ALTIVEC
)
11780 return INSN_NOT_AVAILABLE
;
11785 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11786 return UNSPEC_VCMPEQUB
;
11787 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11788 return UNSPEC_VCMPEQUH
;
11789 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11790 return UNSPEC_VCMPEQUW
;
11791 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11792 return UNSPEC_VCMPEQFP
;
11795 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11796 return UNSPEC_VCMPGEFP
;
11798 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11799 return UNSPEC_VCMPGTSB
;
11800 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11801 return UNSPEC_VCMPGTSH
;
11802 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11803 return UNSPEC_VCMPGTSW
;
11804 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11805 return UNSPEC_VCMPGTFP
;
11808 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11809 return UNSPEC_VCMPGTUB
;
11810 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11811 return UNSPEC_VCMPGTUH
;
11812 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11813 return UNSPEC_VCMPGTUW
;
11818 return INSN_NOT_AVAILABLE
;
11821 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11822 DMODE is expected destination mode. This is a recursive function. */
11825 rs6000_emit_vector_compare (enum rtx_code rcode
,
11827 enum machine_mode dmode
)
11831 enum machine_mode dest_mode
;
11832 enum machine_mode op_mode
= GET_MODE (op1
);
11834 #ifdef ENABLE_CHECKING
11835 if (!TARGET_ALTIVEC
)
11838 if (GET_MODE (op0
) != GET_MODE (op1
))
11842 /* Floating point vector compare instructions uses destination V4SImode.
11843 Move destination to appropriate mode later. */
11844 if (dmode
== V4SFmode
)
11845 dest_mode
= V4SImode
;
11849 mask
= gen_reg_rtx (dest_mode
);
11850 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
11852 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
11854 bool swap_operands
= false;
11855 bool try_again
= false;
11860 swap_operands
= true;
11865 swap_operands
= true;
11869 /* Treat A != B as ~(A==B). */
11871 enum insn_code nor_code
;
11872 rtx eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
11875 nor_code
= one_cmpl_optab
->handlers
[(int)dest_mode
].insn_code
;
11876 if (nor_code
== CODE_FOR_nothing
)
11878 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
11880 if (dmode
!= dest_mode
)
11882 rtx temp
= gen_reg_rtx (dest_mode
);
11883 convert_move (temp
, mask
, 0);
11893 /* Try GT/GTU/LT/LTU OR EQ */
11896 enum insn_code ior_code
;
11897 enum rtx_code new_code
;
11901 else if (rcode
== GEU
)
11903 else if (rcode
== LE
)
11905 else if (rcode
== LEU
)
11910 c_rtx
= rs6000_emit_vector_compare (new_code
,
11911 op0
, op1
, dest_mode
);
11912 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
11915 ior_code
= ior_optab
->handlers
[(int)dest_mode
].insn_code
;
11916 if (ior_code
== CODE_FOR_nothing
)
11918 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
11919 if (dmode
!= dest_mode
)
11921 rtx temp
= gen_reg_rtx (dest_mode
);
11922 convert_move (temp
, mask
, 0);
11934 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
11935 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
11936 /* You only get two chances. */
11949 emit_insn (gen_rtx_fmt_ee (SET
,
11952 gen_rtx_fmt_Ei (UNSPEC
, dest_mode
,
11953 gen_rtvec (2, op0
, op1
),
11955 if (dmode
!= dest_mode
)
11957 rtx temp
= gen_reg_rtx (dest_mode
);
11958 convert_move (temp
, mask
, 0);
11964 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11965 valid insn doesn exist for given mode. */
11968 get_vsel_insn (enum machine_mode mode
)
11973 return UNSPEC_VSEL4SI
;
11976 return UNSPEC_VSEL4SF
;
11979 return UNSPEC_VSEL8HI
;
11982 return UNSPEC_VSEL16QI
;
11985 return INSN_NOT_AVAILABLE
;
11988 return INSN_NOT_AVAILABLE
;
11991 /* Emit vector select insn where DEST is destination using
11992 operands OP1, OP2 and MASK. */
11995 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
11998 enum machine_mode dest_mode
= GET_MODE (dest
);
11999 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
12001 temp
= gen_reg_rtx (dest_mode
);
12003 t
= gen_rtx_fmt_ee (SET
, VOIDmode
, temp
,
12004 gen_rtx_fmt_Ei (UNSPEC
, dest_mode
,
12005 gen_rtvec (3, op1
, op2
, mask
),
12008 emit_move_insn (dest
, temp
);
12012 /* Emit vector conditional expression.
12013 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12014 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12017 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
12018 rtx cond
, rtx cc_op0
, rtx cc_op1
)
12020 enum machine_mode dest_mode
= GET_MODE (dest
);
12021 enum rtx_code rcode
= GET_CODE (cond
);
12024 if (!TARGET_ALTIVEC
)
12027 /* Get the vector mask for the given relational operations. */
12028 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
12030 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
12035 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12036 operands of the last comparison is nonzero/true, FALSE_COND if it
12037 is zero/false. Return 0 if the hardware has no such operation. */
12040 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
12042 enum rtx_code code
= GET_CODE (op
);
12043 rtx op0
= rs6000_compare_op0
;
12044 rtx op1
= rs6000_compare_op1
;
12045 REAL_VALUE_TYPE c1
;
12046 enum machine_mode compare_mode
= GET_MODE (op0
);
12047 enum machine_mode result_mode
= GET_MODE (dest
);
12049 bool is_against_zero
;
12051 /* These modes should always match. */
12052 if (GET_MODE (op1
) != compare_mode
12053 /* In the isel case however, we can use a compare immediate, so
12054 op1 may be a small constant. */
12055 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
12057 if (GET_MODE (true_cond
) != result_mode
)
12059 if (GET_MODE (false_cond
) != result_mode
)
12062 /* First, work out if the hardware can do this at all, or
12063 if it's too slow.... */
12064 if (! rs6000_compare_fp_p
)
12067 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
12070 else if (TARGET_E500
&& TARGET_HARD_FLOAT
&& !TARGET_FPRS
12071 && GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
)
12074 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
12076 /* A floating-point subtract might overflow, underflow, or produce
12077 an inexact result, thus changing the floating-point flags, so it
12078 can't be generated if we care about that. It's safe if one side
12079 of the construct is zero, since then no subtract will be
12081 if (GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
12082 && flag_trapping_math
&& ! is_against_zero
)
12085 /* Eliminate half of the comparisons by switching operands, this
12086 makes the remaining code simpler. */
12087 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
12088 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
12090 code
= reverse_condition_maybe_unordered (code
);
12092 true_cond
= false_cond
;
12096 /* UNEQ and LTGT take four instructions for a comparison with zero,
12097 it'll probably be faster to use a branch here too. */
12098 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
12101 if (GET_CODE (op1
) == CONST_DOUBLE
)
12102 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
12104 /* We're going to try to implement comparisons by performing
12105 a subtract, then comparing against zero. Unfortunately,
12106 Inf - Inf is NaN which is not zero, and so if we don't
12107 know that the operand is finite and the comparison
12108 would treat EQ different to UNORDERED, we can't do it. */
12109 if (HONOR_INFINITIES (compare_mode
)
12110 && code
!= GT
&& code
!= UNGE
12111 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
12112 /* Constructs of the form (a OP b ? a : b) are safe. */
12113 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
12114 || (! rtx_equal_p (op0
, true_cond
)
12115 && ! rtx_equal_p (op1
, true_cond
))))
12118 /* At this point we know we can use fsel. */
12120 /* Reduce the comparison to a comparison against zero. */
12121 if (! is_against_zero
)
12123 temp
= gen_reg_rtx (compare_mode
);
12124 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12125 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
12127 op1
= CONST0_RTX (compare_mode
);
12130 /* If we don't care about NaNs we can reduce some of the comparisons
12131 down to faster ones. */
12132 if (! HONOR_NANS (compare_mode
))
12138 true_cond
= false_cond
;
12151 /* Now, reduce everything down to a GE. */
12158 temp
= gen_reg_rtx (compare_mode
);
12159 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12164 temp
= gen_reg_rtx (compare_mode
);
12165 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
12170 temp
= gen_reg_rtx (compare_mode
);
12171 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12172 gen_rtx_NEG (compare_mode
,
12173 gen_rtx_ABS (compare_mode
, op0
))));
12178 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12179 temp
= gen_reg_rtx (result_mode
);
12180 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12181 gen_rtx_IF_THEN_ELSE (result_mode
,
12182 gen_rtx_GE (VOIDmode
,
12184 true_cond
, false_cond
)));
12185 false_cond
= true_cond
;
12188 temp
= gen_reg_rtx (compare_mode
);
12189 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12194 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12195 temp
= gen_reg_rtx (result_mode
);
12196 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12197 gen_rtx_IF_THEN_ELSE (result_mode
,
12198 gen_rtx_GE (VOIDmode
,
12200 true_cond
, false_cond
)));
12201 true_cond
= false_cond
;
12204 temp
= gen_reg_rtx (compare_mode
);
12205 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12213 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
12214 gen_rtx_IF_THEN_ELSE (result_mode
,
12215 gen_rtx_GE (VOIDmode
,
12217 true_cond
, false_cond
)));
12221 /* Same as above, but for ints (isel). */
12224 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
12226 rtx condition_rtx
, cr
;
12228 /* All isel implementations thus far are 32-bits. */
12229 if (GET_MODE (rs6000_compare_op0
) != SImode
)
12232 /* We still have to do the compare, because isel doesn't do a
12233 compare, it just looks at the CRx bits set by a previous compare
12235 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
12236 cr
= XEXP (condition_rtx
, 0);
12238 if (GET_MODE (cr
) == CCmode
)
12239 emit_insn (gen_isel_signed (dest
, condition_rtx
,
12240 true_cond
, false_cond
, cr
));
12242 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
12243 true_cond
, false_cond
, cr
));
12249 output_isel (rtx
*operands
)
12251 enum rtx_code code
;
12253 code
= GET_CODE (operands
[1]);
12254 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
12256 PUT_CODE (operands
[1], reverse_condition (code
));
12257 return "isel %0,%3,%2,%j1";
12260 return "isel %0,%2,%3,%j1";
12264 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
12266 enum machine_mode mode
= GET_MODE (op0
);
12270 if (code
== SMAX
|| code
== SMIN
)
12275 if (code
== SMAX
|| code
== UMAX
)
12276 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
12277 op0
, op1
, mode
, 0);
12279 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
12280 op1
, op0
, mode
, 0);
12281 if (target
== NULL_RTX
)
12283 if (target
!= dest
)
12284 emit_move_insn (dest
, target
);
12287 /* Emit instructions to move SRC to DST. Called by splitters for
12288 multi-register moves. It will emit at most one instruction for
12289 each register that is accessed; that is, it won't emit li/lis pairs
12290 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12294 rs6000_split_multireg_move (rtx dst
, rtx src
)
12296 /* The register number of the first register being moved. */
12298 /* The mode that is to be moved. */
12299 enum machine_mode mode
;
12300 /* The mode that the move is being done in, and its size. */
12301 enum machine_mode reg_mode
;
12303 /* The number of registers that will be moved. */
12306 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
12307 mode
= GET_MODE (dst
);
12308 nregs
= HARD_REGNO_NREGS (reg
, mode
);
12309 if (FP_REGNO_P (reg
))
12311 else if (ALTIVEC_REGNO_P (reg
))
12312 reg_mode
= V16QImode
;
12314 reg_mode
= word_mode
;
12315 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
12317 if (reg_mode_size
* nregs
!= GET_MODE_SIZE (mode
))
12320 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
12322 /* Move register range backwards, if we might have destructive
12325 for (i
= nregs
- 1; i
>= 0; i
--)
12326 emit_insn (gen_rtx_SET (VOIDmode
,
12327 simplify_gen_subreg (reg_mode
, dst
, mode
,
12328 i
* reg_mode_size
),
12329 simplify_gen_subreg (reg_mode
, src
, mode
,
12330 i
* reg_mode_size
)));
12336 bool used_update
= false;
12338 if (MEM_P (src
) && INT_REGNO_P (reg
))
12342 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
12343 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
12346 breg
= XEXP (XEXP (src
, 0), 0);
12347 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
12348 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
12349 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
12350 emit_insn (TARGET_32BIT
12351 ? gen_addsi3 (breg
, breg
, delta_rtx
)
12352 : gen_adddi3 (breg
, breg
, delta_rtx
));
12353 src
= gen_rtx_MEM (mode
, breg
);
12355 else if (! offsettable_memref_p (src
))
12357 rtx newsrc
, basereg
;
12358 basereg
= gen_rtx_REG (Pmode
, reg
);
12359 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
12360 newsrc
= gen_rtx_MEM (GET_MODE (src
), basereg
);
12361 MEM_COPY_ATTRIBUTES (newsrc
, src
);
12365 breg
= XEXP (src
, 0);
12366 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
12367 breg
= XEXP (breg
, 0);
12369 /* If the base register we are using to address memory is
12370 also a destination reg, then change that register last. */
12372 && REGNO (breg
) >= REGNO (dst
)
12373 && REGNO (breg
) < REGNO (dst
) + nregs
)
12374 j
= REGNO (breg
) - REGNO (dst
);
12377 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
12381 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
12382 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
12385 breg
= XEXP (XEXP (dst
, 0), 0);
12386 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
12387 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
12388 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
12390 /* We have to update the breg before doing the store.
12391 Use store with update, if available. */
12395 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
12396 emit_insn (TARGET_32BIT
12397 ? (TARGET_POWERPC64
12398 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
12399 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
12400 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
12401 used_update
= true;
12404 emit_insn (TARGET_32BIT
12405 ? gen_addsi3 (breg
, breg
, delta_rtx
)
12406 : gen_adddi3 (breg
, breg
, delta_rtx
));
12407 dst
= gen_rtx_MEM (mode
, breg
);
12409 else if (! offsettable_memref_p (dst
))
12413 for (i
= 0; i
< nregs
; i
++)
12415 /* Calculate index to next subword. */
12420 /* If compiler already emitted move of first word by
12421 store with update, no need to do anything. */
12422 if (j
== 0 && used_update
)
12425 emit_insn (gen_rtx_SET (VOIDmode
,
12426 simplify_gen_subreg (reg_mode
, dst
, mode
,
12427 j
* reg_mode_size
),
12428 simplify_gen_subreg (reg_mode
, src
, mode
,
12429 j
* reg_mode_size
)));
12435 /* This page contains routines that are used to determine what the
12436 function prologue and epilogue code will do and write them out. */
12438 /* Return the first fixed-point register that is required to be
12439 saved. 32 if none. */
12442 first_reg_to_save (void)
12446 /* Find lowest numbered live register. */
12447 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
12448 if (regs_ever_live
[first_reg
]
12449 && (! call_used_regs
[first_reg
]
12450 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
12451 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
12452 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
12453 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
12458 && current_function_uses_pic_offset_table
12459 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
12460 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
12466 /* Similar, for FP regs. */
12469 first_fp_reg_to_save (void)
12473 /* Find lowest numbered live register. */
12474 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
12475 if (regs_ever_live
[first_reg
])
12481 /* Similar, for AltiVec regs. */
12484 first_altivec_reg_to_save (void)
12488 /* Stack frame remains as is unless we are in AltiVec ABI. */
12489 if (! TARGET_ALTIVEC_ABI
)
12490 return LAST_ALTIVEC_REGNO
+ 1;
12492 /* Find lowest numbered live register. */
12493 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12494 if (regs_ever_live
[i
])
12500 /* Return a 32-bit mask of the AltiVec registers we need to set in
12501 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12502 the 32-bit word is 0. */
12504 static unsigned int
12505 compute_vrsave_mask (void)
12507 unsigned int i
, mask
= 0;
12509 /* First, find out if we use _any_ altivec registers. */
12510 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12511 if (regs_ever_live
[i
])
12512 mask
|= ALTIVEC_REG_BIT (i
);
12517 /* Next, remove the argument registers from the set. These must
12518 be in the VRSAVE mask set by the caller, so we don't need to add
12519 them in again. More importantly, the mask we compute here is
12520 used to generate CLOBBERs in the set_vrsave insn, and we do not
12521 wish the argument registers to die. */
12522 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
12523 mask
&= ~ALTIVEC_REG_BIT (i
);
12525 /* Similarly, remove the return value from the set. */
12528 diddle_return_value (is_altivec_return_reg
, &yes
);
12530 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
12536 /* For a very restricted set of circumstances, we can cut down the
12537 size of prologues/epilogues by calling our own save/restore-the-world
12541 compute_save_world_info (rs6000_stack_t
*info_ptr
)
12543 info_ptr
->world_save_p
= 1;
12544 info_ptr
->world_save_p
12545 = (WORLD_SAVE_P (info_ptr
)
12546 && DEFAULT_ABI
== ABI_DARWIN
12547 && ! (current_function_calls_setjmp
&& flag_exceptions
)
12548 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
12549 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
12550 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
12551 && info_ptr
->cr_save_p
);
12553 /* This will not work in conjunction with sibcalls. Make sure there
12554 are none. (This check is expensive, but seldom executed.) */
12555 if (WORLD_SAVE_P (info_ptr
))
12558 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
12559 if ( GET_CODE (insn
) == CALL_INSN
12560 && SIBLING_CALL_P (insn
))
12562 info_ptr
->world_save_p
= 0;
12567 if (WORLD_SAVE_P (info_ptr
))
12569 /* Even if we're not touching VRsave, make sure there's room on the
12570 stack for it, if it looks like we're calling SAVE_WORLD, which
12571 will attempt to save it. */
12572 info_ptr
->vrsave_size
= 4;
12574 /* "Save" the VRsave register too if we're saving the world. */
12575 if (info_ptr
->vrsave_mask
== 0)
12576 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
12578 /* Because the Darwin register save/restore routines only handle
12579 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12580 check and abort if there's something worng. */
12581 if (info_ptr
->first_fp_reg_save
< FIRST_SAVED_FP_REGNO
12582 || info_ptr
->first_altivec_reg_save
< FIRST_SAVED_ALTIVEC_REGNO
)
12590 is_altivec_return_reg (rtx reg
, void *xyes
)
12592 bool *yes
= (bool *) xyes
;
12593 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
12598 /* Calculate the stack information for the current function. This is
12599 complicated by having two separate calling sequences, the AIX calling
12600 sequence and the V.4 calling sequence.
12602 AIX (and Darwin/Mac OS X) stack frames look like:
12604 SP----> +---------------------------------------+
12605 | back chain to caller | 0 0
12606 +---------------------------------------+
12607 | saved CR | 4 8 (8-11)
12608 +---------------------------------------+
12610 +---------------------------------------+
12611 | reserved for compilers | 12 24
12612 +---------------------------------------+
12613 | reserved for binders | 16 32
12614 +---------------------------------------+
12615 | saved TOC pointer | 20 40
12616 +---------------------------------------+
12617 | Parameter save area (P) | 24 48
12618 +---------------------------------------+
12619 | Alloca space (A) | 24+P etc.
12620 +---------------------------------------+
12621 | Local variable space (L) | 24+P+A
12622 +---------------------------------------+
12623 | Float/int conversion temporary (X) | 24+P+A+L
12624 +---------------------------------------+
12625 | Save area for AltiVec registers (W) | 24+P+A+L+X
12626 +---------------------------------------+
12627 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12628 +---------------------------------------+
12629 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12630 +---------------------------------------+
12631 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12632 +---------------------------------------+
12633 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12634 +---------------------------------------+
12635 old SP->| back chain to caller's caller |
12636 +---------------------------------------+
12638 The required alignment for AIX configurations is two words (i.e., 8
12642 V.4 stack frames look like:
12644 SP----> +---------------------------------------+
12645 | back chain to caller | 0
12646 +---------------------------------------+
12647 | caller's saved LR | 4
12648 +---------------------------------------+
12649 | Parameter save area (P) | 8
12650 +---------------------------------------+
12651 | Alloca space (A) | 8+P
12652 +---------------------------------------+
12653 | Varargs save area (V) | 8+P+A
12654 +---------------------------------------+
12655 | Local variable space (L) | 8+P+A+V
12656 +---------------------------------------+
12657 | Float/int conversion temporary (X) | 8+P+A+V+L
12658 +---------------------------------------+
12659 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12660 +---------------------------------------+
12661 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12662 +---------------------------------------+
12663 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12664 +---------------------------------------+
12665 | SPE: area for 64-bit GP registers |
12666 +---------------------------------------+
12667 | SPE alignment padding |
12668 +---------------------------------------+
12669 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12670 +---------------------------------------+
12671 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12672 +---------------------------------------+
12673 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12674 +---------------------------------------+
12675 old SP->| back chain to caller's caller |
12676 +---------------------------------------+
12678 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12679 given. (But note below and in sysv4.h that we require only 8 and
12680 may round up the size of our stack frame anyways. The historical
12681 reason is early versions of powerpc-linux which didn't properly
12682 align the stack at program startup. A happy side-effect is that
12683 -mno-eabi libraries can be used with -meabi programs.)
12685 The EABI configuration defaults to the V.4 layout. However,
12686 the stack alignment requirements may differ. If -mno-eabi is not
12687 given, the required stack alignment is 8 bytes; if -mno-eabi is
12688 given, the required alignment is 16 bytes. (But see V.4 comment
12691 #ifndef ABI_STACK_BOUNDARY
12692 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12695 static rs6000_stack_t
*
12696 rs6000_stack_info (void)
12698 static rs6000_stack_t info
, zero_info
;
12699 rs6000_stack_t
*info_ptr
= &info
;
12700 int reg_size
= TARGET_32BIT
? 4 : 8;
12703 HOST_WIDE_INT non_fixed_size
;
12705 /* Zero all fields portably. */
12710 /* Cache value so we don't rescan instruction chain over and over. */
12711 if (cfun
->machine
->insn_chain_scanned_p
== 0)
12712 cfun
->machine
->insn_chain_scanned_p
12713 = spe_func_has_64bit_regs_p () + 1;
12714 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
12717 /* Select which calling sequence. */
12718 info_ptr
->abi
= DEFAULT_ABI
;
12720 /* Calculate which registers need to be saved & save area size. */
12721 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
12722 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12723 even if it currently looks like we won't. */
12724 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
12725 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
12726 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
12727 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
12728 info_ptr
->gp_size
= reg_size
* (32 - RS6000_PIC_OFFSET_TABLE_REGNUM
);
12730 info_ptr
->gp_size
= reg_size
* (32 - info_ptr
->first_gp_reg_save
);
12732 /* For the SPE, we have an additional upper 32-bits on each GPR.
12733 Ideally we should save the entire 64-bits only when the upper
12734 half is used in SIMD instructions. Since we only record
12735 registers live (not the size they are used in), this proves
12736 difficult because we'd have to traverse the instruction chain at
12737 the right time, taking reload into account. This is a real pain,
12738 so we opt to save the GPRs in 64-bits always if but one register
12739 gets used in 64-bits. Otherwise, all the registers in the frame
12740 get saved in 32-bits.
12742 So... since when we save all GPRs (except the SP) in 64-bits, the
12743 traditional GP save area will be empty. */
12744 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12745 info_ptr
->gp_size
= 0;
12747 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
12748 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
12750 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
12751 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
12752 - info_ptr
->first_altivec_reg_save
);
12754 /* Does this function call anything? */
12755 info_ptr
->calls_p
= (! current_function_is_leaf
12756 || cfun
->machine
->ra_needs_full_frame
);
12758 /* Determine if we need to save the link register. */
12759 if (rs6000_ra_ever_killed ()
12760 || (DEFAULT_ABI
== ABI_AIX
12761 && current_function_profile
12762 && !TARGET_PROFILE_KERNEL
)
12763 #ifdef TARGET_RELOCATABLE
12764 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
12766 || (info_ptr
->first_fp_reg_save
!= 64
12767 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
12768 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
12769 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
12770 || (DEFAULT_ABI
== ABI_DARWIN
12772 && current_function_uses_pic_offset_table
)
12773 || info_ptr
->calls_p
)
12775 info_ptr
->lr_save_p
= 1;
12776 regs_ever_live
[LINK_REGISTER_REGNUM
] = 1;
12779 /* Determine if we need to save the condition code registers. */
12780 if (regs_ever_live
[CR2_REGNO
]
12781 || regs_ever_live
[CR3_REGNO
]
12782 || regs_ever_live
[CR4_REGNO
])
12784 info_ptr
->cr_save_p
= 1;
12785 if (DEFAULT_ABI
== ABI_V4
)
12786 info_ptr
->cr_size
= reg_size
;
12789 /* If the current function calls __builtin_eh_return, then we need
12790 to allocate stack space for registers that will hold data for
12791 the exception handler. */
12792 if (current_function_calls_eh_return
)
12795 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
12798 /* SPE saves EH registers in 64-bits. */
12799 ehrd_size
= i
* (TARGET_SPE_ABI
12800 && info_ptr
->spe_64bit_regs_used
!= 0
12801 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
12806 /* Determine various sizes. */
12807 info_ptr
->reg_size
= reg_size
;
12808 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
12809 info_ptr
->varargs_size
= RS6000_VARARGS_AREA
;
12810 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
12811 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
12812 TARGET_ALTIVEC
? 16 : 8);
12814 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12815 info_ptr
->spe_gp_size
= 8 * (32 - info_ptr
->first_gp_reg_save
);
12817 info_ptr
->spe_gp_size
= 0;
12819 if (TARGET_ALTIVEC_ABI
)
12820 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
12822 info_ptr
->vrsave_mask
= 0;
12824 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
12825 info_ptr
->vrsave_size
= 4;
12827 info_ptr
->vrsave_size
= 0;
12829 compute_save_world_info (info_ptr
);
12831 /* Calculate the offsets. */
12832 switch (DEFAULT_ABI
)
12840 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
12841 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
12843 if (TARGET_ALTIVEC_ABI
)
12845 info_ptr
->vrsave_save_offset
12846 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
12848 /* Align stack so vector save area is on a quadword boundary. */
12849 if (info_ptr
->altivec_size
!= 0)
12850 info_ptr
->altivec_padding_size
12851 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
12853 info_ptr
->altivec_padding_size
= 0;
12855 info_ptr
->altivec_save_offset
12856 = info_ptr
->vrsave_save_offset
12857 - info_ptr
->altivec_padding_size
12858 - info_ptr
->altivec_size
;
12860 /* Adjust for AltiVec case. */
12861 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
12864 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
12865 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
12866 info_ptr
->lr_save_offset
= 2*reg_size
;
12870 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
12871 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
12872 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
12874 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12876 /* Align stack so SPE GPR save area is aligned on a
12877 double-word boundary. */
12878 if (info_ptr
->spe_gp_size
!= 0)
12879 info_ptr
->spe_padding_size
12880 = 8 - (-info_ptr
->cr_save_offset
% 8);
12882 info_ptr
->spe_padding_size
= 0;
12884 info_ptr
->spe_gp_save_offset
12885 = info_ptr
->cr_save_offset
12886 - info_ptr
->spe_padding_size
12887 - info_ptr
->spe_gp_size
;
12889 /* Adjust for SPE case. */
12890 info_ptr
->toc_save_offset
12891 = info_ptr
->spe_gp_save_offset
- info_ptr
->toc_size
;
12893 else if (TARGET_ALTIVEC_ABI
)
12895 info_ptr
->vrsave_save_offset
12896 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
12898 /* Align stack so vector save area is on a quadword boundary. */
12899 if (info_ptr
->altivec_size
!= 0)
12900 info_ptr
->altivec_padding_size
12901 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
12903 info_ptr
->altivec_padding_size
= 0;
12905 info_ptr
->altivec_save_offset
12906 = info_ptr
->vrsave_save_offset
12907 - info_ptr
->altivec_padding_size
12908 - info_ptr
->altivec_size
;
12910 /* Adjust for AltiVec case. */
12911 info_ptr
->toc_save_offset
12912 = info_ptr
->altivec_save_offset
- info_ptr
->toc_size
;
12915 info_ptr
->toc_save_offset
= info_ptr
->cr_save_offset
- info_ptr
->toc_size
;
12916 info_ptr
->ehrd_offset
= info_ptr
->toc_save_offset
- ehrd_size
;
12917 info_ptr
->lr_save_offset
= reg_size
;
12921 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
12922 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
12923 + info_ptr
->gp_size
12924 + info_ptr
->altivec_size
12925 + info_ptr
->altivec_padding_size
12926 + info_ptr
->spe_gp_size
12927 + info_ptr
->spe_padding_size
12929 + info_ptr
->cr_size
12930 + info_ptr
->lr_size
12931 + info_ptr
->vrsave_size
12932 + info_ptr
->toc_size
,
12935 non_fixed_size
= (info_ptr
->vars_size
12936 + info_ptr
->parm_size
12937 + info_ptr
->save_size
12938 + info_ptr
->varargs_size
);
12940 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
12941 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
12943 /* Determine if we need to allocate any stack frame:
12945 For AIX we need to push the stack if a frame pointer is needed
12946 (because the stack might be dynamically adjusted), if we are
12947 debugging, if we make calls, or if the sum of fp_save, gp_save,
12948 and local variables are more than the space needed to save all
12949 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12950 + 18*8 = 288 (GPR13 reserved).
12952 For V.4 we don't have the stack cushion that AIX uses, but assume
12953 that the debugger can handle stackless frames. */
12955 if (info_ptr
->calls_p
)
12956 info_ptr
->push_p
= 1;
12958 else if (DEFAULT_ABI
== ABI_V4
)
12959 info_ptr
->push_p
= non_fixed_size
!= 0;
12961 else if (frame_pointer_needed
)
12962 info_ptr
->push_p
= 1;
12964 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
12965 info_ptr
->push_p
= 1;
12968 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
12970 /* Zero offsets if we're not saving those registers. */
12971 if (info_ptr
->fp_size
== 0)
12972 info_ptr
->fp_save_offset
= 0;
12974 if (info_ptr
->gp_size
== 0)
12975 info_ptr
->gp_save_offset
= 0;
12977 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
12978 info_ptr
->altivec_save_offset
= 0;
12980 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
12981 info_ptr
->vrsave_save_offset
= 0;
12983 if (! TARGET_SPE_ABI
12984 || info_ptr
->spe_64bit_regs_used
== 0
12985 || info_ptr
->spe_gp_size
== 0)
12986 info_ptr
->spe_gp_save_offset
= 0;
12988 if (! info_ptr
->lr_save_p
)
12989 info_ptr
->lr_save_offset
= 0;
12991 if (! info_ptr
->cr_save_p
)
12992 info_ptr
->cr_save_offset
= 0;
12994 if (! info_ptr
->toc_save_p
)
12995 info_ptr
->toc_save_offset
= 0;
13000 /* Return true if the current function uses any GPRs in 64-bit SIMD
13004 spe_func_has_64bit_regs_p (void)
13008 /* Functions that save and restore all the call-saved registers will
13009 need to save/restore the registers in 64-bits. */
13010 if (current_function_calls_eh_return
13011 || current_function_calls_setjmp
13012 || current_function_has_nonlocal_goto
)
13015 insns
= get_insns ();
13017 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
13023 /* FIXME: This should be implemented with attributes...
13025 (set_attr "spe64" "true")....then,
13026 if (get_spe64(insn)) return true;
13028 It's the only reliable way to do the stuff below. */
13030 i
= PATTERN (insn
);
13031 if (GET_CODE (i
) == SET
)
13033 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
13035 if (SPE_VECTOR_MODE (mode
))
13037 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
13047 debug_stack_info (rs6000_stack_t
*info
)
13049 const char *abi_string
;
13052 info
= rs6000_stack_info ();
13054 fprintf (stderr
, "\nStack information for function %s:\n",
13055 ((current_function_decl
&& DECL_NAME (current_function_decl
))
13056 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
13061 default: abi_string
= "Unknown"; break;
13062 case ABI_NONE
: abi_string
= "NONE"; break;
13063 case ABI_AIX
: abi_string
= "AIX"; break;
13064 case ABI_DARWIN
: abi_string
= "Darwin"; break;
13065 case ABI_V4
: abi_string
= "V.4"; break;
13068 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
13070 if (TARGET_ALTIVEC_ABI
)
13071 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
13073 if (TARGET_SPE_ABI
)
13074 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
13076 if (info
->first_gp_reg_save
!= 32)
13077 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
13079 if (info
->first_fp_reg_save
!= 64)
13080 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
13082 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
13083 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
13084 info
->first_altivec_reg_save
);
13086 if (info
->lr_save_p
)
13087 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
13089 if (info
->cr_save_p
)
13090 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
13092 if (info
->toc_save_p
)
13093 fprintf (stderr
, "\ttoc_save_p = %5d\n", info
->toc_save_p
);
13095 if (info
->vrsave_mask
)
13096 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
13099 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
13102 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
13104 if (info
->gp_save_offset
)
13105 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
13107 if (info
->fp_save_offset
)
13108 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
13110 if (info
->altivec_save_offset
)
13111 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
13112 info
->altivec_save_offset
);
13114 if (info
->spe_gp_save_offset
)
13115 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
13116 info
->spe_gp_save_offset
);
13118 if (info
->vrsave_save_offset
)
13119 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
13120 info
->vrsave_save_offset
);
13122 if (info
->lr_save_offset
)
13123 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
13125 if (info
->cr_save_offset
)
13126 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
13128 if (info
->toc_save_offset
)
13129 fprintf (stderr
, "\ttoc_save_offset = %5d\n", info
->toc_save_offset
);
13131 if (info
->varargs_save_offset
)
13132 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
13134 if (info
->total_size
)
13135 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
13138 if (info
->varargs_size
)
13139 fprintf (stderr
, "\tvarargs_size = %5d\n", info
->varargs_size
);
13141 if (info
->vars_size
)
13142 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
13145 if (info
->parm_size
)
13146 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
13148 if (info
->fixed_size
)
13149 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
13152 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
13154 if (info
->spe_gp_size
)
13155 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
13158 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
13160 if (info
->altivec_size
)
13161 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
13163 if (info
->vrsave_size
)
13164 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
13166 if (info
->altivec_padding_size
)
13167 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
13168 info
->altivec_padding_size
);
13170 if (info
->spe_padding_size
)
13171 fprintf (stderr
, "\tspe_padding_size = %5d\n",
13172 info
->spe_padding_size
);
13175 fprintf (stderr
, "\tlr_size = %5d\n", info
->lr_size
);
13178 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
13180 if (info
->toc_size
)
13181 fprintf (stderr
, "\ttoc_size = %5d\n", info
->toc_size
);
13183 if (info
->save_size
)
13184 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
13186 if (info
->reg_size
!= 4)
13187 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
13189 fprintf (stderr
, "\n");
13193 rs6000_return_addr (int count
, rtx frame
)
13195 /* Currently we don't optimize very well between prolog and body
13196 code and for PIC code the code can be actually quite bad, so
13197 don't try to be too clever here. */
13198 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
13200 cfun
->machine
->ra_needs_full_frame
= 1;
13207 plus_constant (copy_to_reg
13208 (gen_rtx_MEM (Pmode
,
13209 memory_address (Pmode
, frame
))),
13210 RETURN_ADDRESS_OFFSET
)));
13213 cfun
->machine
->ra_need_lr
= 1;
13214 return get_hard_reg_initial_val (Pmode
, LINK_REGISTER_REGNUM
);
13217 /* Say whether a function is a candidate for sibcall handling or not.
13218 We do not allow indirect calls to be optimized into sibling calls.
13219 Also, we can't do it if there are any vector parameters; there's
13220 nowhere to put the VRsave code so it works; note that functions with
13221 vector parameters are required to have a prototype, so the argument
13222 type info must be available here. (The tail recursion case can work
13223 with vector parameters, but there's no way to distinguish here.) */
13225 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
13230 if (TARGET_ALTIVEC_VRSAVE
)
13232 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
13233 type
; type
= TREE_CHAIN (type
))
13235 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
13239 if (DEFAULT_ABI
== ABI_DARWIN
13240 || (*targetm
.binds_local_p
) (decl
))
13242 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
13244 if (!lookup_attribute ("longcall", attr_list
)
13245 || lookup_attribute ("shortcall", attr_list
))
13253 rs6000_ra_ever_killed (void)
13259 if (current_function_is_thunk
)
13262 /* regs_ever_live has LR marked as used if any sibcalls are present,
13263 but this should not force saving and restoring in the
13264 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13265 clobbers LR, so that is inappropriate. */
13267 /* Also, the prologue can generate a store into LR that
13268 doesn't really count, like this:
13271 bcl to set PIC register
13275 When we're called from the epilogue, we need to avoid counting
13276 this as a store. */
13278 push_topmost_sequence ();
13279 top
= get_insns ();
13280 pop_topmost_sequence ();
13281 reg
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13283 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
13287 if (FIND_REG_INC_NOTE (insn
, reg
))
13289 else if (GET_CODE (insn
) == CALL_INSN
13290 && !SIBLING_CALL_P (insn
))
13292 else if (set_of (reg
, insn
) != NULL_RTX
13293 && !prologue_epilogue_contains (insn
))
13300 /* Add a REG_MAYBE_DEAD note to the insn. */
13302 rs6000_maybe_dead (rtx insn
)
13304 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
13309 /* Emit instructions needed to load the TOC register.
13310 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13311 a constant pool; or for SVR4 -fpic. */
13314 rs6000_emit_load_toc_table (int fromprolog
)
13317 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
13319 if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
13321 rtx temp
= (fromprolog
13322 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13323 : gen_reg_rtx (Pmode
));
13324 insn
= emit_insn (gen_load_toc_v4_pic_si (temp
));
13326 rs6000_maybe_dead (insn
);
13327 insn
= emit_move_insn (dest
, temp
);
13329 rs6000_maybe_dead (insn
);
13331 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
13334 rtx tempLR
= (fromprolog
13335 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13336 : gen_reg_rtx (Pmode
));
13337 rtx temp0
= (fromprolog
13338 ? gen_rtx_REG (Pmode
, 0)
13339 : gen_reg_rtx (Pmode
));
13346 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
13347 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13349 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
13350 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13352 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR
,
13354 rs6000_maybe_dead (emit_move_insn (dest
, tempLR
));
13355 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
,
13362 static int reload_toc_labelno
= 0;
13364 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
13366 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCG", reload_toc_labelno
++);
13367 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13369 emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, symF
, tocsym
));
13370 emit_move_insn (dest
, tempLR
);
13371 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
13373 insn
= emit_insn (gen_addsi3 (dest
, temp0
, dest
));
13375 rs6000_maybe_dead (insn
);
13377 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
13379 /* This is for AIX code running in non-PIC ELF32. */
13382 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
13383 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13385 insn
= emit_insn (gen_elf_high (dest
, realsym
));
13387 rs6000_maybe_dead (insn
);
13388 insn
= emit_insn (gen_elf_low (dest
, dest
, realsym
));
13390 rs6000_maybe_dead (insn
);
13392 else if (DEFAULT_ABI
== ABI_AIX
)
13395 insn
= emit_insn (gen_load_toc_aix_si (dest
));
13397 insn
= emit_insn (gen_load_toc_aix_di (dest
));
13399 rs6000_maybe_dead (insn
);
13405 /* Emit instructions to restore the link register after determining where
13406 its value has been stored. */
13409 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
13411 rs6000_stack_t
*info
= rs6000_stack_info ();
13414 operands
[0] = source
;
13415 operands
[1] = scratch
;
13417 if (info
->lr_save_p
)
13419 rtx frame_rtx
= stack_pointer_rtx
;
13420 HOST_WIDE_INT sp_offset
= 0;
13423 if (frame_pointer_needed
13424 || current_function_calls_alloca
13425 || info
->total_size
> 32767)
13427 emit_move_insn (operands
[1], gen_rtx_MEM (Pmode
, frame_rtx
));
13428 frame_rtx
= operands
[1];
13430 else if (info
->push_p
)
13431 sp_offset
= info
->total_size
;
13433 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
13434 tmp
= gen_rtx_MEM (Pmode
, tmp
);
13435 emit_move_insn (tmp
, operands
[0]);
13438 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
), operands
[0]);
13441 static GTY(()) int set
= -1;
13444 get_TOC_alias_set (void)
13447 set
= new_alias_set ();
13451 /* This returns nonzero if the current function uses the TOC. This is
13452 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13453 is generated by the ABI_V4 load_toc_* patterns. */
13460 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13463 rtx pat
= PATTERN (insn
);
13466 if (GET_CODE (pat
) == PARALLEL
)
13467 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
13469 rtx sub
= XVECEXP (pat
, 0, i
);
13470 if (GET_CODE (sub
) == USE
)
13472 sub
= XEXP (sub
, 0);
13473 if (GET_CODE (sub
) == UNSPEC
13474 && XINT (sub
, 1) == UNSPEC_TOC
)
13484 create_TOC_reference (rtx symbol
)
13486 return gen_rtx_PLUS (Pmode
,
13487 gen_rtx_REG (Pmode
, TOC_REGISTER
),
13488 gen_rtx_CONST (Pmode
,
13489 gen_rtx_MINUS (Pmode
, symbol
,
13490 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
13493 /* If _Unwind_* has been called from within the same module,
13494 toc register is not guaranteed to be saved to 40(1) on function
13495 entry. Save it there in that case. */
13498 rs6000_aix_emit_builtin_unwind_init (void)
13501 rtx stack_top
= gen_reg_rtx (Pmode
);
13502 rtx opcode_addr
= gen_reg_rtx (Pmode
);
13503 rtx opcode
= gen_reg_rtx (SImode
);
13504 rtx tocompare
= gen_reg_rtx (SImode
);
13505 rtx no_toc_save_needed
= gen_label_rtx ();
13507 mem
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
13508 emit_move_insn (stack_top
, mem
);
13510 mem
= gen_rtx_MEM (Pmode
,
13511 gen_rtx_PLUS (Pmode
, stack_top
,
13512 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
13513 emit_move_insn (opcode_addr
, mem
);
13514 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
13515 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
13516 : 0xE8410028, SImode
));
13518 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
13519 SImode
, NULL_RTX
, NULL_RTX
,
13520 no_toc_save_needed
);
13522 mem
= gen_rtx_MEM (Pmode
,
13523 gen_rtx_PLUS (Pmode
, stack_top
,
13524 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
13525 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
13526 emit_label (no_toc_save_needed
);
13529 /* This ties together stack memory (MEM with an alias set of
13530 rs6000_sr_alias_set) and the change to the stack pointer. */
13533 rs6000_emit_stack_tie (void)
13535 rtx mem
= gen_rtx_MEM (BLKmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
13537 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13538 emit_insn (gen_stack_tie (mem
));
13541 /* Emit the correct code for allocating stack space, as insns.
13542 If COPY_R12, make sure a copy of the old frame is left in r12.
13543 The generated code may use hard register 0 as a temporary. */
13546 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
13549 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13550 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
13551 rtx todec
= gen_int_mode (-size
, Pmode
);
13553 if (INTVAL (todec
) != -size
)
13555 warning("stack frame too large");
13556 emit_insn (gen_trap ());
13560 if (current_function_limit_stack
)
13562 if (REG_P (stack_limit_rtx
)
13563 && REGNO (stack_limit_rtx
) > 1
13564 && REGNO (stack_limit_rtx
) <= 31)
13566 emit_insn (TARGET_32BIT
13567 ? gen_addsi3 (tmp_reg
,
13570 : gen_adddi3 (tmp_reg
,
13574 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
13577 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
13579 && DEFAULT_ABI
== ABI_V4
)
13581 rtx toload
= gen_rtx_CONST (VOIDmode
,
13582 gen_rtx_PLUS (Pmode
,
13586 emit_insn (gen_elf_high (tmp_reg
, toload
));
13587 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
13588 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
13592 warning ("stack limit expression is not supported");
13595 if (copy_r12
|| ! TARGET_UPDATE
)
13596 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
13602 /* Need a note here so that try_split doesn't get confused. */
13603 if (get_last_insn() == NULL_RTX
)
13604 emit_note (NOTE_INSN_DELETED
);
13605 insn
= emit_move_insn (tmp_reg
, todec
);
13606 try_split (PATTERN (insn
), insn
, 0);
13610 insn
= emit_insn (TARGET_32BIT
13611 ? gen_movsi_update (stack_reg
, stack_reg
,
13613 : gen_movdi_di_update (stack_reg
, stack_reg
,
13614 todec
, stack_reg
));
13618 insn
= emit_insn (TARGET_32BIT
13619 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
13620 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
13621 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
13622 gen_rtx_REG (Pmode
, 12));
13625 RTX_FRAME_RELATED_P (insn
) = 1;
13627 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13628 gen_rtx_SET (VOIDmode
, stack_reg
,
13629 gen_rtx_PLUS (Pmode
, stack_reg
,
13634 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13635 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13636 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13637 deduce these equivalences by itself so it wasn't necessary to hold
13638 its hand so much. */
13641 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
13642 rtx reg2
, rtx rreg
)
13646 /* copy_rtx will not make unique copies of registers, so we need to
13647 ensure we don't have unwanted sharing here. */
13649 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
13652 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
13654 real
= copy_rtx (PATTERN (insn
));
13656 if (reg2
!= NULL_RTX
)
13657 real
= replace_rtx (real
, reg2
, rreg
);
13659 real
= replace_rtx (real
, reg
,
13660 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
13661 STACK_POINTER_REGNUM
),
13664 /* We expect that 'real' is either a SET or a PARALLEL containing
13665 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13666 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13668 if (GET_CODE (real
) == SET
)
13672 temp
= simplify_rtx (SET_SRC (set
));
13674 SET_SRC (set
) = temp
;
13675 temp
= simplify_rtx (SET_DEST (set
));
13677 SET_DEST (set
) = temp
;
13678 if (GET_CODE (SET_DEST (set
)) == MEM
)
13680 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
13682 XEXP (SET_DEST (set
), 0) = temp
;
13685 else if (GET_CODE (real
) == PARALLEL
)
13688 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
13689 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
13691 rtx set
= XVECEXP (real
, 0, i
);
13693 temp
= simplify_rtx (SET_SRC (set
));
13695 SET_SRC (set
) = temp
;
13696 temp
= simplify_rtx (SET_DEST (set
));
13698 SET_DEST (set
) = temp
;
13699 if (GET_CODE (SET_DEST (set
)) == MEM
)
13701 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
13703 XEXP (SET_DEST (set
), 0) = temp
;
13705 RTX_FRAME_RELATED_P (set
) = 1;
13712 real
= spe_synthesize_frame_save (real
);
13714 RTX_FRAME_RELATED_P (insn
) = 1;
13715 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13720 /* Given an SPE frame note, return a PARALLEL of SETs with the
13721 original note, plus a synthetic register save. */
13724 spe_synthesize_frame_save (rtx real
)
13726 rtx synth
, offset
, reg
, real2
;
13728 if (GET_CODE (real
) != SET
13729 || GET_MODE (SET_SRC (real
)) != V2SImode
)
13732 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13733 frame related note. The parallel contains a set of the register
13734 being saved, and another set to a synthetic register (n+1200).
13735 This is so we can differentiate between 64-bit and 32-bit saves.
13736 Words cannot describe this nastiness. */
13738 if (GET_CODE (SET_DEST (real
)) != MEM
13739 || GET_CODE (XEXP (SET_DEST (real
), 0)) != PLUS
13740 || GET_CODE (SET_SRC (real
)) != REG
)
13744 (set (mem (plus (reg x) (const y)))
13747 (set (mem (plus (reg x) (const y+4)))
13751 real2
= copy_rtx (real
);
13752 PUT_MODE (SET_DEST (real2
), SImode
);
13753 reg
= SET_SRC (real2
);
13754 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
13755 synth
= copy_rtx (real2
);
13757 if (BYTES_BIG_ENDIAN
)
13759 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
13760 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
13763 reg
= SET_SRC (synth
);
13765 synth
= replace_rtx (synth
, reg
,
13766 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
13768 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
13769 synth
= replace_rtx (synth
, offset
,
13770 GEN_INT (INTVAL (offset
)
13771 + (BYTES_BIG_ENDIAN
? 0 : 4)));
13773 RTX_FRAME_RELATED_P (synth
) = 1;
13774 RTX_FRAME_RELATED_P (real2
) = 1;
13775 if (BYTES_BIG_ENDIAN
)
13776 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
13778 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
13783 /* Returns an insn that has a vrsave set operation with the
13784 appropriate CLOBBERs. */
13787 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
13790 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
13791 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
13794 = gen_rtx_SET (VOIDmode
,
13796 gen_rtx_UNSPEC_VOLATILE (SImode
,
13797 gen_rtvec (2, reg
, vrsave
),
13802 /* We need to clobber the registers in the mask so the scheduler
13803 does not move sets to VRSAVE before sets of AltiVec registers.
13805 However, if the function receives nonlocal gotos, reload will set
13806 all call saved registers live. We will end up with:
13808 (set (reg 999) (mem))
13809 (parallel [ (set (reg vrsave) (unspec blah))
13810 (clobber (reg 999))])
13812 The clobber will cause the store into reg 999 to be dead, and
13813 flow will attempt to delete an epilogue insn. In this case, we
13814 need an unspec use/set of the register. */
13816 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13817 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
13819 if (!epiloguep
|| call_used_regs
[i
])
13820 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
13821 gen_rtx_REG (V4SImode
, i
));
13824 rtx reg
= gen_rtx_REG (V4SImode
, i
);
13827 = gen_rtx_SET (VOIDmode
,
13829 gen_rtx_UNSPEC (V4SImode
,
13830 gen_rtvec (1, reg
), 27));
13834 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
13836 for (i
= 0; i
< nclobs
; ++i
)
13837 XVECEXP (insn
, 0, i
) = clobs
[i
];
13842 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13843 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13846 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
13847 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
13849 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
13850 rtx replacea
, replaceb
;
13852 int_rtx
= GEN_INT (offset
);
13854 /* Some cases that need register indexed addressing. */
13855 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
13856 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
13858 && SPE_VECTOR_MODE (mode
)
13859 && !SPE_CONST_OFFSET_OK (offset
)))
13861 /* Whomever calls us must make sure r11 is available in the
13862 flow path of instructions in the prologue. */
13863 offset_rtx
= gen_rtx_REG (Pmode
, 11);
13864 emit_move_insn (offset_rtx
, int_rtx
);
13866 replacea
= offset_rtx
;
13867 replaceb
= int_rtx
;
13871 offset_rtx
= int_rtx
;
13872 replacea
= NULL_RTX
;
13873 replaceb
= NULL_RTX
;
13876 reg
= gen_rtx_REG (mode
, regno
);
13877 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
13878 mem
= gen_rtx_MEM (mode
, addr
);
13879 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13881 insn
= emit_move_insn (mem
, reg
);
13883 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
13886 /* Emit an offset memory reference suitable for a frame store, while
13887 converting to a valid addressing mode. */
13890 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
13892 rtx int_rtx
, offset_rtx
;
13894 int_rtx
= GEN_INT (offset
);
13896 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
13897 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
13899 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13900 emit_move_insn (offset_rtx
, int_rtx
);
13903 offset_rtx
= int_rtx
;
13905 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
13908 #ifndef TARGET_FIX_AND_CONTINUE
13909 #define TARGET_FIX_AND_CONTINUE 0
13912 /* Emit function prologue as insns. */
13915 rs6000_emit_prologue (void)
13917 rs6000_stack_t
*info
= rs6000_stack_info ();
13918 enum machine_mode reg_mode
= Pmode
;
13919 int reg_size
= TARGET_32BIT
? 4 : 8;
13920 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13921 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
13922 rtx frame_reg_rtx
= sp_reg_rtx
;
13923 rtx cr_save_rtx
= NULL_RTX
;
13925 int saving_FPRs_inline
;
13926 int using_store_multiple
;
13927 HOST_WIDE_INT sp_offset
= 0;
13929 if (TARGET_FIX_AND_CONTINUE
)
13931 /* gdb on darwin arranges to forward a function from the old
13932 address by modifying the first 4 instructions of the function
13933 to branch to the overriding function. This is necessary to
13934 permit function pointers that point to the old function to
13935 actually forward to the new function. */
13936 emit_insn (gen_nop ());
13937 emit_insn (gen_nop ());
13938 emit_insn (gen_nop ());
13939 emit_insn (gen_nop ());
13942 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13944 reg_mode
= V2SImode
;
13948 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
13949 && (!TARGET_SPE_ABI
13950 || info
->spe_64bit_regs_used
== 0)
13951 && info
->first_gp_reg_save
< 31);
13952 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
13953 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
13954 || current_function_calls_eh_return
13955 || cfun
->machine
->ra_need_lr
);
13957 /* For V.4, update stack before we do any saving and set back pointer. */
13959 && (DEFAULT_ABI
== ABI_V4
13960 || current_function_calls_eh_return
))
13962 if (info
->total_size
< 32767)
13963 sp_offset
= info
->total_size
;
13965 frame_reg_rtx
= frame_ptr_rtx
;
13966 rs6000_emit_allocate_stack (info
->total_size
,
13967 (frame_reg_rtx
!= sp_reg_rtx
13968 && (info
->cr_save_p
13970 || info
->first_fp_reg_save
< 64
13971 || info
->first_gp_reg_save
< 32
13973 if (frame_reg_rtx
!= sp_reg_rtx
)
13974 rs6000_emit_stack_tie ();
13977 /* Handle world saves specially here. */
13978 if (WORLD_SAVE_P (info
))
13984 /* save_world expects lr in r0. */
13985 if (info
->lr_save_p
)
13987 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
13988 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
13989 RTX_FRAME_RELATED_P (insn
) = 1;
13992 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13993 assumptions about the offsets of various bits of the stack
13994 frame. Abort if things aren't what they should be. */
13995 if (info
->gp_save_offset
!= -220
13996 || info
->fp_save_offset
!= -144
13997 || info
->lr_save_offset
!= 8
13998 || info
->cr_save_offset
!= 4
14000 || !info
->lr_save_p
14001 || (current_function_calls_eh_return
&& info
->ehrd_offset
!= -432)
14002 || (info
->vrsave_save_offset
!= -224
14003 || info
->altivec_save_offset
!= (-224 -16 -192)))
14006 treg
= gen_rtx_REG (SImode
, 11);
14007 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
14009 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14010 in R11. It also clobbers R12, so beware! */
14012 /* Preserve CR2 for save_world prologues */
14014 sz
+= 32 - info
->first_gp_reg_save
;
14015 sz
+= 64 - info
->first_fp_reg_save
;
14016 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
14017 p
= rtvec_alloc (sz
);
14019 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
14020 gen_rtx_REG (Pmode
,
14021 LINK_REGISTER_REGNUM
));
14022 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
14023 gen_rtx_SYMBOL_REF (Pmode
,
14025 /* We do floats first so that the instruction pattern matches
14027 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14029 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14030 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14031 GEN_INT (info
->fp_save_offset
14032 + sp_offset
+ 8 * i
));
14033 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
14034 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14036 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14038 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
14040 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
14041 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14042 GEN_INT (info
->altivec_save_offset
14043 + sp_offset
+ 16 * i
));
14044 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
14045 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14047 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14049 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14051 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14052 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14053 GEN_INT (info
->gp_save_offset
14054 + sp_offset
+ reg_size
* i
));
14055 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14056 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14058 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14062 /* CR register traditionally saved as CR2. */
14063 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
14064 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14065 GEN_INT (info
->cr_save_offset
14067 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14068 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14070 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14072 /* Prevent any attempt to delete the setting of r0 and treg! */
14073 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
14074 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, treg
);
14075 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
, sp_reg_rtx
);
14077 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14078 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14079 NULL_RTX
, NULL_RTX
);
14081 if (current_function_calls_eh_return
)
14086 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
14087 if (regno
== INVALID_REGNUM
)
14089 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
14090 info
->ehrd_offset
+ sp_offset
14091 + reg_size
* (int) i
,
14097 /* Save AltiVec registers if needed. */
14098 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
14102 /* There should be a non inline version of this, for when we
14103 are saving lots of vector registers. */
14104 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14105 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
14107 rtx areg
, savereg
, mem
;
14110 offset
= info
->altivec_save_offset
+ sp_offset
14111 + 16 * (i
- info
->first_altivec_reg_save
);
14113 savereg
= gen_rtx_REG (V4SImode
, i
);
14115 areg
= gen_rtx_REG (Pmode
, 0);
14116 emit_move_insn (areg
, GEN_INT (offset
));
14118 /* AltiVec addressing mode is [reg+reg]. */
14119 mem
= gen_rtx_MEM (V4SImode
,
14120 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
14122 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14124 insn
= emit_move_insn (mem
, savereg
);
14126 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14127 areg
, GEN_INT (offset
));
14131 /* VRSAVE is a bit vector representing which AltiVec registers
14132 are used. The OS uses this to determine which vector
14133 registers to save on a context switch. We need to save
14134 VRSAVE on the stack frame, add whatever AltiVec registers we
14135 used in this function, and do the corresponding magic in the
14138 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
14139 && !WORLD_SAVE_P (info
) && info
->vrsave_mask
!= 0)
14141 rtx reg
, mem
, vrsave
;
14144 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14145 as frame_reg_rtx and r11 as the static chain pointer for
14146 nested functions. */
14147 reg
= gen_rtx_REG (SImode
, 0);
14148 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
14150 emit_insn (gen_get_vrsave_internal (reg
));
14152 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
14155 offset
= info
->vrsave_save_offset
+ sp_offset
;
14157 = gen_rtx_MEM (SImode
,
14158 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, GEN_INT (offset
)));
14159 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14160 insn
= emit_move_insn (mem
, reg
);
14162 /* Include the registers in the mask. */
14163 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
14165 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
14168 /* If we use the link register, get it into r0. */
14169 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
14171 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
14172 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
14173 RTX_FRAME_RELATED_P (insn
) = 1;
14176 /* If we need to save CR, put it into r12. */
14177 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
14181 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
14182 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
14183 RTX_FRAME_RELATED_P (insn
) = 1;
14184 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14185 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14186 But that's OK. All we have to do is specify that _one_ condition
14187 code register is saved in this stack slot. The thrower's epilogue
14188 will then restore all the call-saved registers.
14189 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14190 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
14191 gen_rtx_REG (SImode
, CR2_REGNO
));
14192 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14197 /* Do any required saving of fpr's. If only one or two to save, do
14198 it ourselves. Otherwise, call function. */
14199 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
14202 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14203 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
14204 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
14205 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
14206 info
->first_fp_reg_save
+ i
,
14207 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
14210 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
14214 const char *alloc_rname
;
14216 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
14218 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
14219 gen_rtx_REG (Pmode
,
14220 LINK_REGISTER_REGNUM
));
14221 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
14222 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
14223 alloc_rname
= ggc_strdup (rname
);
14224 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
14225 gen_rtx_SYMBOL_REF (Pmode
,
14227 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14229 rtx addr
, reg
, mem
;
14230 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14231 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14232 GEN_INT (info
->fp_save_offset
14233 + sp_offset
+ 8*i
));
14234 mem
= gen_rtx_MEM (DFmode
, addr
);
14235 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14237 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14239 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14240 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14241 NULL_RTX
, NULL_RTX
);
14244 /* Save GPRs. This is done as a PARALLEL if we are using
14245 the store-multiple instructions. */
14246 if (!WORLD_SAVE_P (info
) && using_store_multiple
)
14250 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
14251 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14253 rtx addr
, reg
, mem
;
14254 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14255 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14256 GEN_INT (info
->gp_save_offset
14259 mem
= gen_rtx_MEM (reg_mode
, addr
);
14260 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14262 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14264 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14265 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14266 NULL_RTX
, NULL_RTX
);
14268 else if (!WORLD_SAVE_P (info
))
14271 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14272 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
14273 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
14274 || (i
+info
->first_gp_reg_save
14275 == RS6000_PIC_OFFSET_TABLE_REGNUM
14276 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
14277 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14278 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14279 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
14281 rtx addr
, reg
, mem
;
14282 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14284 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14286 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
14289 if (!SPE_CONST_OFFSET_OK (offset
))
14291 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
14292 emit_move_insn (b
, GEN_INT (offset
));
14295 b
= GEN_INT (offset
);
14297 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
14298 mem
= gen_rtx_MEM (V2SImode
, addr
);
14299 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14300 insn
= emit_move_insn (mem
, reg
);
14302 if (GET_CODE (b
) == CONST_INT
)
14303 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14304 NULL_RTX
, NULL_RTX
);
14306 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14307 b
, GEN_INT (offset
));
14311 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14312 GEN_INT (info
->gp_save_offset
14315 mem
= gen_rtx_MEM (reg_mode
, addr
);
14316 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14318 insn
= emit_move_insn (mem
, reg
);
14319 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14320 NULL_RTX
, NULL_RTX
);
14325 /* ??? There's no need to emit actual instructions here, but it's the
14326 easiest way to get the frame unwind information emitted. */
14327 if (!WORLD_SAVE_P (info
) && current_function_calls_eh_return
)
14329 unsigned int i
, regno
;
14331 /* In AIX ABI we need to pretend we save r2 here. */
14334 rtx addr
, reg
, mem
;
14336 reg
= gen_rtx_REG (reg_mode
, 2);
14337 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14338 GEN_INT (sp_offset
+ 5 * reg_size
));
14339 mem
= gen_rtx_MEM (reg_mode
, addr
);
14340 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14342 insn
= emit_move_insn (mem
, reg
);
14343 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14344 NULL_RTX
, NULL_RTX
);
14345 PATTERN (insn
) = gen_blockage ();
14350 regno
= EH_RETURN_DATA_REGNO (i
);
14351 if (regno
== INVALID_REGNUM
)
14354 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
14355 info
->ehrd_offset
+ sp_offset
14356 + reg_size
* (int) i
,
14361 /* Save lr if we used it. */
14362 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
14364 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14365 GEN_INT (info
->lr_save_offset
+ sp_offset
));
14366 rtx reg
= gen_rtx_REG (Pmode
, 0);
14367 rtx mem
= gen_rtx_MEM (Pmode
, addr
);
14368 /* This should not be of rs6000_sr_alias_set, because of
14369 __builtin_return_address. */
14371 insn
= emit_move_insn (mem
, reg
);
14372 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14373 NULL_RTX
, NULL_RTX
);
14376 /* Save CR if we use any that must be preserved. */
14377 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
14379 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14380 GEN_INT (info
->cr_save_offset
+ sp_offset
));
14381 rtx mem
= gen_rtx_MEM (SImode
, addr
);
14382 /* See the large comment above about why CR2_REGNO is used. */
14383 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
14385 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14387 /* If r12 was used to hold the original sp, copy cr into r0 now
14389 if (REGNO (frame_reg_rtx
) == 12)
14393 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
14394 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
14395 RTX_FRAME_RELATED_P (insn
) = 1;
14396 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
14397 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14402 insn
= emit_move_insn (mem
, cr_save_rtx
);
14404 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14405 NULL_RTX
, NULL_RTX
);
14408 /* Update stack and set back pointer unless this is V.4,
14409 for which it was done previously. */
14410 if (!WORLD_SAVE_P (info
) && info
->push_p
14411 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
14412 rs6000_emit_allocate_stack (info
->total_size
, FALSE
);
14414 /* Set frame pointer, if needed. */
14415 if (frame_pointer_needed
)
14417 insn
= emit_move_insn (gen_rtx_REG (Pmode
, FRAME_POINTER_REGNUM
),
14419 RTX_FRAME_RELATED_P (insn
) = 1;
14422 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14423 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
14424 || (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1
14425 && regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
]))
14427 /* If emit_load_toc_table will use the link register, we need to save
14428 it. We use R12 for this purpose because emit_load_toc_table
14429 can use register 0. This allows us to use a plain 'blr' to return
14430 from the procedure more often. */
14431 int save_LR_around_toc_setup
= (TARGET_ELF
14432 && DEFAULT_ABI
!= ABI_AIX
14434 && ! info
->lr_save_p
14435 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
14436 if (save_LR_around_toc_setup
)
14438 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
14440 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
14441 rs6000_maybe_dead (insn
);
14442 RTX_FRAME_RELATED_P (insn
) = 1;
14444 rs6000_emit_load_toc_table (TRUE
);
14446 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
14447 rs6000_maybe_dead (insn
);
14448 RTX_FRAME_RELATED_P (insn
) = 1;
14451 rs6000_emit_load_toc_table (TRUE
);
14455 if (DEFAULT_ABI
== ABI_DARWIN
14456 && flag_pic
&& current_function_uses_pic_offset_table
)
14458 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
14459 rtx src
= machopic_function_base_sym ();
14461 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr
, src
)));
14463 insn
= emit_move_insn (gen_rtx_REG (Pmode
,
14464 RS6000_PIC_OFFSET_TABLE_REGNUM
),
14466 rs6000_maybe_dead (insn
);
14471 /* Write function prologue. */
14474 rs6000_output_function_prologue (FILE *file
,
14475 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
14477 rs6000_stack_t
*info
= rs6000_stack_info ();
14479 if (TARGET_DEBUG_STACK
)
14480 debug_stack_info (info
);
14482 /* Write .extern for any function we will call to save and restore
14484 if (info
->first_fp_reg_save
< 64
14485 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
14486 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14487 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
14488 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
14489 RESTORE_FP_SUFFIX
);
14491 /* Write .extern for AIX common mode routines, if needed. */
14492 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
14494 fputs ("\t.extern __mulh\n", file
);
14495 fputs ("\t.extern __mull\n", file
);
14496 fputs ("\t.extern __divss\n", file
);
14497 fputs ("\t.extern __divus\n", file
);
14498 fputs ("\t.extern __quoss\n", file
);
14499 fputs ("\t.extern __quous\n", file
);
14500 common_mode_defined
= 1;
14503 if (! HAVE_prologue
)
14507 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14508 the "toplevel" insn chain. */
14509 emit_note (NOTE_INSN_DELETED
);
14510 rs6000_emit_prologue ();
14511 emit_note (NOTE_INSN_DELETED
);
14513 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14517 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14519 INSN_ADDRESSES_NEW (insn
, addr
);
14524 if (TARGET_DEBUG_STACK
)
14525 debug_rtx_list (get_insns (), 100);
14526 final (get_insns (), file
, FALSE
, FALSE
);
14530 rs6000_pic_labelno
++;
14533 /* Emit function epilogue as insns.
14535 At present, dwarf2out_frame_debug_expr doesn't understand
14536 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14537 anywhere in the epilogue. Most of the insns below would in any case
14538 need special notes to explain where r11 is in relation to the stack. */
14541 rs6000_emit_epilogue (int sibcall
)
14543 rs6000_stack_t
*info
;
14544 int restoring_FPRs_inline
;
14545 int using_load_multiple
;
14546 int using_mfcr_multiple
;
14547 int use_backchain_to_restore_sp
;
14549 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
14550 rtx frame_reg_rtx
= sp_reg_rtx
;
14551 enum machine_mode reg_mode
= Pmode
;
14552 int reg_size
= TARGET_32BIT
? 4 : 8;
14555 info
= rs6000_stack_info ();
14557 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14559 reg_mode
= V2SImode
;
14563 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
14564 && (!TARGET_SPE_ABI
14565 || info
->spe_64bit_regs_used
== 0)
14566 && info
->first_gp_reg_save
< 31);
14567 restoring_FPRs_inline
= (sibcall
14568 || current_function_calls_eh_return
14569 || info
->first_fp_reg_save
== 64
14570 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
14571 use_backchain_to_restore_sp
= (frame_pointer_needed
14572 || current_function_calls_alloca
14573 || info
->total_size
> 32767);
14574 using_mfcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
14575 || rs6000_cpu
== PROCESSOR_PPC603
14576 || rs6000_cpu
== PROCESSOR_PPC750
14579 if (WORLD_SAVE_P (info
))
14583 const char *alloc_rname
;
14586 /* eh_rest_world_r10 will return to the location saved in the LR
14587 stack slot (which is not likely to be our caller.)
14588 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14589 rest_world is similar, except any R10 parameter is ignored.
14590 The exception-handling stuff that was here in 2.95 is no
14591 longer necessary. */
14595 + 32 - info
->first_gp_reg_save
14596 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
14597 + 63 + 1 - info
->first_fp_reg_save
);
14599 strcpy (rname
, ((current_function_calls_eh_return
) ?
14600 "*eh_rest_world_r10" : "*rest_world"));
14601 alloc_rname
= ggc_strdup (rname
);
14604 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
14605 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
14606 gen_rtx_REG (Pmode
,
14607 LINK_REGISTER_REGNUM
));
14609 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
14610 /* The instruction pattern requires a clobber here;
14611 it is shared with the restVEC helper. */
14613 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
14616 /* CR register traditionally saved as CR2. */
14617 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
14618 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14619 GEN_INT (info
->cr_save_offset
));
14620 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14621 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14623 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14626 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14628 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14629 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14630 GEN_INT (info
->gp_save_offset
14632 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14633 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14635 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14637 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
14639 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
14640 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14641 GEN_INT (info
->altivec_save_offset
14643 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
14644 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14646 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14648 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
14650 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14651 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14652 GEN_INT (info
->fp_save_offset
14654 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
14655 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14657 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14660 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
14662 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
14664 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
14666 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
14668 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
14669 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14674 /* If we have a frame pointer, a call to alloca, or a large stack
14675 frame, restore the old stack pointer using the backchain. Otherwise,
14676 we know what size to update it with. */
14677 if (use_backchain_to_restore_sp
)
14679 /* Under V.4, don't reset the stack pointer until after we're done
14680 loading the saved registers. */
14681 if (DEFAULT_ABI
== ABI_V4
)
14682 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
14684 emit_move_insn (frame_reg_rtx
,
14685 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
14688 else if (info
->push_p
)
14690 if (DEFAULT_ABI
== ABI_V4
14691 || current_function_calls_eh_return
)
14692 sp_offset
= info
->total_size
;
14695 emit_insn (TARGET_32BIT
14696 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
14697 GEN_INT (info
->total_size
))
14698 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
14699 GEN_INT (info
->total_size
)));
14703 /* Restore AltiVec registers if needed. */
14704 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
14708 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14709 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
14711 rtx addr
, areg
, mem
;
14713 areg
= gen_rtx_REG (Pmode
, 0);
14715 (areg
, GEN_INT (info
->altivec_save_offset
14717 + 16 * (i
- info
->first_altivec_reg_save
)));
14719 /* AltiVec addressing mode is [reg+reg]. */
14720 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
14721 mem
= gen_rtx_MEM (V4SImode
, addr
);
14722 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14724 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
14728 /* Restore VRSAVE if needed. */
14729 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
14730 && info
->vrsave_mask
!= 0)
14732 rtx addr
, mem
, reg
;
14734 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14735 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
14736 mem
= gen_rtx_MEM (SImode
, addr
);
14737 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14738 reg
= gen_rtx_REG (SImode
, 12);
14739 emit_move_insn (reg
, mem
);
14741 emit_insn (generate_set_vrsave (reg
, info
, 1));
14744 /* Get the old lr if we saved it. */
14745 if (info
->lr_save_p
)
14747 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
14748 info
->lr_save_offset
+ sp_offset
);
14750 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14752 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
14755 /* Get the old cr if we saved it. */
14756 if (info
->cr_save_p
)
14758 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14759 GEN_INT (info
->cr_save_offset
+ sp_offset
));
14760 rtx mem
= gen_rtx_MEM (SImode
, addr
);
14762 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14764 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
14767 /* Set LR here to try to overlap restores below. */
14768 if (info
->lr_save_p
)
14769 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
),
14770 gen_rtx_REG (Pmode
, 0));
14772 /* Load exception handler data registers, if needed. */
14773 if (current_function_calls_eh_return
)
14775 unsigned int i
, regno
;
14779 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14780 GEN_INT (sp_offset
+ 5 * reg_size
));
14781 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14783 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14785 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
14792 regno
= EH_RETURN_DATA_REGNO (i
);
14793 if (regno
== INVALID_REGNUM
)
14796 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
14797 info
->ehrd_offset
+ sp_offset
14798 + reg_size
* (int) i
);
14799 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14801 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
14805 /* Restore GPRs. This is done as a PARALLEL if we are using
14806 the load-multiple instructions. */
14807 if (using_load_multiple
)
14810 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
14811 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14813 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14814 GEN_INT (info
->gp_save_offset
14817 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14819 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14822 gen_rtx_SET (VOIDmode
,
14823 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
14826 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14829 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14830 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
14831 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
14832 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14833 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
14834 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14835 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14836 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
14838 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14839 GEN_INT (info
->gp_save_offset
14842 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14844 /* Restore 64-bit quantities for SPE. */
14845 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14847 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
14850 if (!SPE_CONST_OFFSET_OK (offset
))
14852 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
14853 emit_move_insn (b
, GEN_INT (offset
));
14856 b
= GEN_INT (offset
);
14858 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
14859 mem
= gen_rtx_MEM (V2SImode
, addr
);
14862 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14864 emit_move_insn (gen_rtx_REG (reg_mode
,
14865 info
->first_gp_reg_save
+ i
), mem
);
14868 /* Restore fpr's if we need to do it without calling a function. */
14869 if (restoring_FPRs_inline
)
14870 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14871 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
14872 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
14875 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14876 GEN_INT (info
->fp_save_offset
14879 mem
= gen_rtx_MEM (DFmode
, addr
);
14880 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14882 emit_move_insn (gen_rtx_REG (DFmode
,
14883 info
->first_fp_reg_save
+ i
),
14887 /* If we saved cr, restore it here. Just those that were used. */
14888 if (info
->cr_save_p
)
14890 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
14893 if (using_mfcr_multiple
)
14895 for (i
= 0; i
< 8; i
++)
14896 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14902 if (using_mfcr_multiple
&& count
> 1)
14907 p
= rtvec_alloc (count
);
14910 for (i
= 0; i
< 8; i
++)
14911 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14913 rtvec r
= rtvec_alloc (2);
14914 RTVEC_ELT (r
, 0) = r12_rtx
;
14915 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
14916 RTVEC_ELT (p
, ndx
) =
14917 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
14918 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
14921 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14926 for (i
= 0; i
< 8; i
++)
14927 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14929 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
14935 /* If this is V.4, unwind the stack pointer after all of the loads
14936 have been done. We need to emit a block here so that sched
14937 doesn't decide to move the sp change before the register restores
14938 (which may not have any obvious dependency on the stack). This
14939 doesn't hurt performance, because there is no scheduling that can
14940 be done after this point. */
14941 if (DEFAULT_ABI
== ABI_V4
14942 || current_function_calls_eh_return
)
14944 if (frame_reg_rtx
!= sp_reg_rtx
)
14945 rs6000_emit_stack_tie ();
14947 if (use_backchain_to_restore_sp
)
14949 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
14951 else if (sp_offset
!= 0)
14953 emit_insn (TARGET_32BIT
14954 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
14955 GEN_INT (sp_offset
))
14956 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
14957 GEN_INT (sp_offset
)));
14961 if (current_function_calls_eh_return
)
14963 rtx sa
= EH_RETURN_STACKADJ_RTX
;
14964 emit_insn (TARGET_32BIT
14965 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
14966 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
14972 if (! restoring_FPRs_inline
)
14973 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
14975 p
= rtvec_alloc (2);
14977 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
14978 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
14979 gen_rtx_REG (Pmode
,
14980 LINK_REGISTER_REGNUM
));
14982 /* If we have to restore more than two FP registers, branch to the
14983 restore function. It will return to our caller. */
14984 if (! restoring_FPRs_inline
)
14988 const char *alloc_rname
;
14990 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
14991 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
14992 alloc_rname
= ggc_strdup (rname
);
14993 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
14994 gen_rtx_SYMBOL_REF (Pmode
,
14997 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15000 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
15001 GEN_INT (info
->fp_save_offset
+ 8*i
));
15002 mem
= gen_rtx_MEM (DFmode
, addr
);
15003 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
15005 RTVEC_ELT (p
, i
+3) =
15006 gen_rtx_SET (VOIDmode
,
15007 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
15012 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15016 /* Write function epilogue. */
15019 rs6000_output_function_epilogue (FILE *file
,
15020 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
15022 rs6000_stack_t
*info
= rs6000_stack_info ();
15024 if (! HAVE_epilogue
)
15026 rtx insn
= get_last_insn ();
15027 /* If the last insn was a BARRIER, we don't have to write anything except
15028 the trace table. */
15029 if (GET_CODE (insn
) == NOTE
)
15030 insn
= prev_nonnote_insn (insn
);
15031 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
15033 /* This is slightly ugly, but at least we don't have two
15034 copies of the epilogue-emitting code. */
15037 /* A NOTE_INSN_DELETED is supposed to be at the start
15038 and end of the "toplevel" insn chain. */
15039 emit_note (NOTE_INSN_DELETED
);
15040 rs6000_emit_epilogue (FALSE
);
15041 emit_note (NOTE_INSN_DELETED
);
15043 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15047 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15049 INSN_ADDRESSES_NEW (insn
, addr
);
15054 if (TARGET_DEBUG_STACK
)
15055 debug_rtx_list (get_insns (), 100);
15056 final (get_insns (), file
, FALSE
, FALSE
);
15062 macho_branch_islands ();
15063 /* Mach-O doesn't support labels at the end of objects, so if
15064 it looks like we might want one, insert a NOP. */
15066 rtx insn
= get_last_insn ();
15069 && NOTE_LINE_NUMBER (insn
) != NOTE_INSN_DELETED_LABEL
)
15070 insn
= PREV_INSN (insn
);
15074 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED_LABEL
)))
15075 fputs ("\tnop\n", file
);
15079 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15082 We don't output a traceback table if -finhibit-size-directive was
15083 used. The documentation for -finhibit-size-directive reads
15084 ``don't output a @code{.size} assembler directive, or anything
15085 else that would cause trouble if the function is split in the
15086 middle, and the two halves are placed at locations far apart in
15087 memory.'' The traceback table has this property, since it
15088 includes the offset from the start of the function to the
15089 traceback table itself.
15091 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15092 different traceback table. */
15093 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
15094 && rs6000_traceback
!= traceback_none
)
15096 const char *fname
= NULL
;
15097 const char *language_string
= lang_hooks
.name
;
15098 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
15100 int optional_tbtab
;
15102 if (rs6000_traceback
== traceback_full
)
15103 optional_tbtab
= 1;
15104 else if (rs6000_traceback
== traceback_part
)
15105 optional_tbtab
= 0;
15107 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
15109 if (optional_tbtab
)
15111 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
15112 while (*fname
== '.') /* V.4 encodes . in the name */
15115 /* Need label immediately before tbtab, so we can compute
15116 its offset from the function start. */
15117 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
15118 ASM_OUTPUT_LABEL (file
, fname
);
15121 /* The .tbtab pseudo-op can only be used for the first eight
15122 expressions, since it can't handle the possibly variable
15123 length fields that follow. However, if you omit the optional
15124 fields, the assembler outputs zeros for all optional fields
15125 anyways, giving each variable length field is minimum length
15126 (as defined in sys/debug.h). Thus we can not use the .tbtab
15127 pseudo-op at all. */
15129 /* An all-zero word flags the start of the tbtab, for debuggers
15130 that have to find it by searching forward from the entry
15131 point or from the current pc. */
15132 fputs ("\t.long 0\n", file
);
15134 /* Tbtab format type. Use format type 0. */
15135 fputs ("\t.byte 0,", file
);
15137 /* Language type. Unfortunately, there does not seem to be any
15138 official way to discover the language being compiled, so we
15139 use language_string.
15140 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15141 Java is 13. Objective-C is 14. */
15142 if (! strcmp (language_string
, "GNU C"))
15144 else if (! strcmp (language_string
, "GNU F77")
15145 || ! strcmp (language_string
, "GNU F95"))
15147 else if (! strcmp (language_string
, "GNU Pascal"))
15149 else if (! strcmp (language_string
, "GNU Ada"))
15151 else if (! strcmp (language_string
, "GNU C++"))
15153 else if (! strcmp (language_string
, "GNU Java"))
15155 else if (! strcmp (language_string
, "GNU Objective-C"))
15159 fprintf (file
, "%d,", i
);
15161 /* 8 single bit fields: global linkage (not set for C extern linkage,
15162 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15163 from start of procedure stored in tbtab, internal function, function
15164 has controlled storage, function has no toc, function uses fp,
15165 function logs/aborts fp operations. */
15166 /* Assume that fp operations are used if any fp reg must be saved. */
15167 fprintf (file
, "%d,",
15168 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
15170 /* 6 bitfields: function is interrupt handler, name present in
15171 proc table, function calls alloca, on condition directives
15172 (controls stack walks, 3 bits), saves condition reg, saves
15174 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15175 set up as a frame pointer, even when there is no alloca call. */
15176 fprintf (file
, "%d,",
15177 ((optional_tbtab
<< 6)
15178 | ((optional_tbtab
& frame_pointer_needed
) << 5)
15179 | (info
->cr_save_p
<< 1)
15180 | (info
->lr_save_p
)));
15182 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15184 fprintf (file
, "%d,",
15185 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
15187 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15188 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
15190 if (optional_tbtab
)
15192 /* Compute the parameter info from the function decl argument
15195 int next_parm_info_bit
= 31;
15197 for (decl
= DECL_ARGUMENTS (current_function_decl
);
15198 decl
; decl
= TREE_CHAIN (decl
))
15200 rtx parameter
= DECL_INCOMING_RTL (decl
);
15201 enum machine_mode mode
= GET_MODE (parameter
);
15203 if (GET_CODE (parameter
) == REG
)
15205 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
15211 if (mode
== SFmode
)
15213 else if (mode
== DFmode
|| mode
== TFmode
)
15218 /* If only one bit will fit, don't or in this entry. */
15219 if (next_parm_info_bit
> 0)
15220 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
15221 next_parm_info_bit
-= 2;
15225 fixed_parms
+= ((GET_MODE_SIZE (mode
)
15226 + (UNITS_PER_WORD
- 1))
15228 next_parm_info_bit
-= 1;
15234 /* Number of fixed point parameters. */
15235 /* This is actually the number of words of fixed point parameters; thus
15236 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15237 fprintf (file
, "%d,", fixed_parms
);
15239 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15241 /* This is actually the number of fp registers that hold parameters;
15242 and thus the maximum value is 13. */
15243 /* Set parameters on stack bit if parameters are not in their original
15244 registers, regardless of whether they are on the stack? Xlc
15245 seems to set the bit when not optimizing. */
15246 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
15248 if (! optional_tbtab
)
15251 /* Optional fields follow. Some are variable length. */
15253 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15254 11 double float. */
15255 /* There is an entry for each parameter in a register, in the order that
15256 they occur in the parameter list. Any intervening arguments on the
15257 stack are ignored. If the list overflows a long (max possible length
15258 34 bits) then completely leave off all elements that don't fit. */
15259 /* Only emit this long if there was at least one parameter. */
15260 if (fixed_parms
|| float_parms
)
15261 fprintf (file
, "\t.long %d\n", parm_info
);
15263 /* Offset from start of code to tb table. */
15264 fputs ("\t.long ", file
);
15265 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
15267 RS6000_OUTPUT_BASENAME (file
, fname
);
15269 assemble_name (file
, fname
);
15271 rs6000_output_function_entry (file
, fname
);
15274 /* Interrupt handler mask. */
15275 /* Omit this long, since we never set the interrupt handler bit
15278 /* Number of CTL (controlled storage) anchors. */
15279 /* Omit this long, since the has_ctl bit is never set above. */
15281 /* Displacement into stack of each CTL anchor. */
15282 /* Omit this list of longs, because there are no CTL anchors. */
15284 /* Length of function name. */
15287 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
15289 /* Function name. */
15290 assemble_string (fname
, strlen (fname
));
15292 /* Register for alloca automatic storage; this is always reg 31.
15293 Only emit this if the alloca bit was set above. */
15294 if (frame_pointer_needed
)
15295 fputs ("\t.byte 31\n", file
);
15297 fputs ("\t.align 2\n", file
);
15301 /* A C compound statement that outputs the assembler code for a thunk
15302 function, used to implement C++ virtual function calls with
15303 multiple inheritance. The thunk acts as a wrapper around a virtual
15304 function, adjusting the implicit object parameter before handing
15305 control off to the real function.
15307 First, emit code to add the integer DELTA to the location that
15308 contains the incoming first argument. Assume that this argument
15309 contains a pointer, and is the one used to pass the `this' pointer
15310 in C++. This is the incoming argument *before* the function
15311 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15312 values of all other incoming arguments.
15314 After the addition, emit code to jump to FUNCTION, which is a
15315 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15316 not touch the return address. Hence returning from FUNCTION will
15317 return to whoever called the current `thunk'.
15319 The effect must be as if FUNCTION had been called directly with the
15320 adjusted first argument. This macro is responsible for emitting
15321 all of the code for a thunk function; output_function_prologue()
15322 and output_function_epilogue() are not invoked.
15324 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15325 been extracted from it.) It might possibly be useful on some
15326 targets, but probably not.
15328 If you do not define this macro, the target-independent code in the
15329 C++ frontend will generate a less efficient heavyweight thunk that
15330 calls FUNCTION instead of jumping to it. The generic approach does
15331 not support varargs. */
15334 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15335 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15338 rtx
this, insn
, funexp
;
15340 reload_completed
= 1;
15341 epilogue_completed
= 1;
15342 no_new_pseudos
= 1;
15343 reset_block_changes ();
15345 /* Mark the end of the (empty) prologue. */
15346 emit_note (NOTE_INSN_PROLOGUE_END
);
15348 /* Find the "this" pointer. If the function returns a structure,
15349 the structure return pointer is in r3. */
15350 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15351 this = gen_rtx_REG (Pmode
, 4);
15353 this = gen_rtx_REG (Pmode
, 3);
15355 /* Apply the constant offset, if required. */
15358 rtx delta_rtx
= GEN_INT (delta
);
15359 emit_insn (TARGET_32BIT
15360 ? gen_addsi3 (this, this, delta_rtx
)
15361 : gen_adddi3 (this, this, delta_rtx
));
15364 /* Apply the offset from the vtable, if required. */
15367 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
15368 rtx tmp
= gen_rtx_REG (Pmode
, 12);
15370 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
15371 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
15373 emit_insn (TARGET_32BIT
15374 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
15375 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
15376 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
15380 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
15382 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
15384 emit_insn (TARGET_32BIT
15385 ? gen_addsi3 (this, this, tmp
)
15386 : gen_adddi3 (this, this, tmp
));
15389 /* Generate a tail call to the target function. */
15390 if (!TREE_USED (function
))
15392 assemble_external (function
);
15393 TREE_USED (function
) = 1;
15395 funexp
= XEXP (DECL_RTL (function
), 0);
15396 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
15399 if (MACHOPIC_INDIRECT
)
15400 funexp
= machopic_indirect_call_target (funexp
);
15403 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15404 generate sibcall RTL explicitly to avoid constraint abort. */
15405 insn
= emit_call_insn (
15406 gen_rtx_PARALLEL (VOIDmode
,
15408 gen_rtx_CALL (VOIDmode
,
15409 funexp
, const0_rtx
),
15410 gen_rtx_USE (VOIDmode
, const0_rtx
),
15411 gen_rtx_USE (VOIDmode
,
15412 gen_rtx_REG (SImode
,
15413 LINK_REGISTER_REGNUM
)),
15414 gen_rtx_RETURN (VOIDmode
))));
15415 SIBLING_CALL_P (insn
) = 1;
15418 /* Run just enough of rest_of_compilation to get the insns emitted.
15419 There's not really enough bulk here to make other passes such as
15420 instruction scheduling worth while. Note that use_thunk calls
15421 assemble_start_function and assemble_end_function. */
15422 insn
= get_insns ();
15423 insn_locators_initialize ();
15424 shorten_branches (insn
);
15425 final_start_function (insn
, file
, 1);
15426 final (insn
, file
, 1, 0);
15427 final_end_function ();
15429 reload_completed
= 0;
15430 epilogue_completed
= 0;
15431 no_new_pseudos
= 0;
15434 /* A quick summary of the various types of 'constant-pool tables'
15437 Target Flags Name One table per
15438 AIX (none) AIX TOC object file
15439 AIX -mfull-toc AIX TOC object file
15440 AIX -mminimal-toc AIX minimal TOC translation unit
15441 SVR4/EABI (none) SVR4 SDATA object file
15442 SVR4/EABI -fpic SVR4 pic object file
15443 SVR4/EABI -fPIC SVR4 PIC translation unit
15444 SVR4/EABI -mrelocatable EABI TOC function
15445 SVR4/EABI -maix AIX TOC object file
15446 SVR4/EABI -maix -mminimal-toc
15447 AIX minimal TOC translation unit
15449 Name Reg. Set by entries contains:
15450 made by addrs? fp? sum?
15452 AIX TOC 2 crt0 as Y option option
15453 AIX minimal TOC 30 prolog gcc Y Y option
15454 SVR4 SDATA 13 crt0 gcc N Y N
15455 SVR4 pic 30 prolog ld Y not yet N
15456 SVR4 PIC 30 prolog gcc Y option option
15457 EABI TOC 30 prolog gcc Y option option
15461 /* Hash functions for the hash table. */
15464 rs6000_hash_constant (rtx k
)
15466 enum rtx_code code
= GET_CODE (k
);
15467 enum machine_mode mode
= GET_MODE (k
);
15468 unsigned result
= (code
<< 3) ^ mode
;
15469 const char *format
;
15472 format
= GET_RTX_FORMAT (code
);
15473 flen
= strlen (format
);
15479 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
15482 if (mode
!= VOIDmode
)
15483 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
15495 for (; fidx
< flen
; fidx
++)
15496 switch (format
[fidx
])
15501 const char *str
= XSTR (k
, fidx
);
15502 len
= strlen (str
);
15503 result
= result
* 613 + len
;
15504 for (i
= 0; i
< len
; i
++)
15505 result
= result
* 613 + (unsigned) str
[i
];
15510 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
15514 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
15517 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
15518 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
15522 for (i
= 0; i
< sizeof(HOST_WIDE_INT
)/sizeof(unsigned); i
++)
15523 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
15537 toc_hash_function (const void *hash_entry
)
15539 const struct toc_hash_struct
*thc
=
15540 (const struct toc_hash_struct
*) hash_entry
;
15541 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
15544 /* Compare H1 and H2 for equivalence. */
15547 toc_hash_eq (const void *h1
, const void *h2
)
15549 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
15550 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
15552 if (((const struct toc_hash_struct
*) h1
)->key_mode
15553 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
15556 return rtx_equal_p (r1
, r2
);
15559 /* These are the names given by the C++ front-end to vtables, and
15560 vtable-like objects. Ideally, this logic should not be here;
15561 instead, there should be some programmatic way of inquiring as
15562 to whether or not an object is a vtable. */
15564 #define VTABLE_NAME_P(NAME) \
15565 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15566 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15567 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15568 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15569 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15572 rs6000_output_symbol_ref (FILE *file
, rtx x
)
15574 /* Currently C++ toc references to vtables can be emitted before it
15575 is decided whether the vtable is public or private. If this is
15576 the case, then the linker will eventually complain that there is
15577 a reference to an unknown section. Thus, for vtables only,
15578 we emit the TOC reference to reference the symbol and not the
15580 const char *name
= XSTR (x
, 0);
15582 if (VTABLE_NAME_P (name
))
15584 RS6000_OUTPUT_BASENAME (file
, name
);
15587 assemble_name (file
, name
);
15590 /* Output a TOC entry. We derive the entry name from what is being
15594 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
15597 const char *name
= buf
;
15598 const char *real_name
;
15605 /* When the linker won't eliminate them, don't output duplicate
15606 TOC entries (this happens on AIX if there is any kind of TOC,
15607 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15609 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
15611 struct toc_hash_struct
*h
;
15614 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15615 time because GGC is not initialized at that point. */
15616 if (toc_hash_table
== NULL
)
15617 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
15618 toc_hash_eq
, NULL
);
15620 h
= ggc_alloc (sizeof (*h
));
15622 h
->key_mode
= mode
;
15623 h
->labelno
= labelno
;
15625 found
= htab_find_slot (toc_hash_table
, h
, 1);
15626 if (*found
== NULL
)
15628 else /* This is indeed a duplicate.
15629 Set this label equal to that label. */
15631 fputs ("\t.set ", file
);
15632 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
15633 fprintf (file
, "%d,", labelno
);
15634 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
15635 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
15641 /* If we're going to put a double constant in the TOC, make sure it's
15642 aligned properly when strict alignment is on. */
15643 if (GET_CODE (x
) == CONST_DOUBLE
15644 && STRICT_ALIGNMENT
15645 && GET_MODE_BITSIZE (mode
) >= 64
15646 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
15647 ASM_OUTPUT_ALIGN (file
, 3);
15650 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
15652 /* Handle FP constants specially. Note that if we have a minimal
15653 TOC, things we put here aren't actually in the TOC, so we can allow
15655 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == TFmode
)
15657 REAL_VALUE_TYPE rv
;
15660 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15661 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
15665 if (TARGET_MINIMAL_TOC
)
15666 fputs (DOUBLE_INT_ASM_OP
, file
);
15668 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15669 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15670 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15671 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
15672 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15673 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15678 if (TARGET_MINIMAL_TOC
)
15679 fputs ("\t.long ", file
);
15681 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15682 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15683 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15684 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15685 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15686 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15690 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
15692 REAL_VALUE_TYPE rv
;
15695 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15696 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
15700 if (TARGET_MINIMAL_TOC
)
15701 fputs (DOUBLE_INT_ASM_OP
, file
);
15703 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
15704 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15705 fprintf (file
, "0x%lx%08lx\n",
15706 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15711 if (TARGET_MINIMAL_TOC
)
15712 fputs ("\t.long ", file
);
15714 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
15715 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15716 fprintf (file
, "0x%lx,0x%lx\n",
15717 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15721 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
15723 REAL_VALUE_TYPE rv
;
15726 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15727 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
15731 if (TARGET_MINIMAL_TOC
)
15732 fputs (DOUBLE_INT_ASM_OP
, file
);
15734 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
15735 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
15740 if (TARGET_MINIMAL_TOC
)
15741 fputs ("\t.long ", file
);
15743 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
15744 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
15748 else if (GET_MODE (x
) == VOIDmode
15749 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
15751 unsigned HOST_WIDE_INT low
;
15752 HOST_WIDE_INT high
;
15754 if (GET_CODE (x
) == CONST_DOUBLE
)
15756 low
= CONST_DOUBLE_LOW (x
);
15757 high
= CONST_DOUBLE_HIGH (x
);
15760 #if HOST_BITS_PER_WIDE_INT == 32
15763 high
= (low
& 0x80000000) ? ~0 : 0;
15767 low
= INTVAL (x
) & 0xffffffff;
15768 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
15772 /* TOC entries are always Pmode-sized, but since this
15773 is a bigendian machine then if we're putting smaller
15774 integer constants in the TOC we have to pad them.
15775 (This is still a win over putting the constants in
15776 a separate constant pool, because then we'd have
15777 to have both a TOC entry _and_ the actual constant.)
15779 For a 32-bit target, CONST_INT values are loaded and shifted
15780 entirely within `low' and can be stored in one TOC entry. */
15782 if (TARGET_64BIT
&& POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
15783 abort ();/* It would be easy to make this work, but it doesn't now. */
15785 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
15787 #if HOST_BITS_PER_WIDE_INT == 32
15788 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
15789 POINTER_SIZE
, &low
, &high
, 0);
15792 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
15793 high
= (HOST_WIDE_INT
) low
>> 32;
15800 if (TARGET_MINIMAL_TOC
)
15801 fputs (DOUBLE_INT_ASM_OP
, file
);
15803 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
15804 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15805 fprintf (file
, "0x%lx%08lx\n",
15806 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15811 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
15813 if (TARGET_MINIMAL_TOC
)
15814 fputs ("\t.long ", file
);
15816 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
15817 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15818 fprintf (file
, "0x%lx,0x%lx\n",
15819 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15823 if (TARGET_MINIMAL_TOC
)
15824 fputs ("\t.long ", file
);
15826 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
15827 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
15833 if (GET_CODE (x
) == CONST
)
15835 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
15838 base
= XEXP (XEXP (x
, 0), 0);
15839 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
15842 if (GET_CODE (base
) == SYMBOL_REF
)
15843 name
= XSTR (base
, 0);
15844 else if (GET_CODE (base
) == LABEL_REF
)
15845 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (base
, 0)));
15846 else if (GET_CODE (base
) == CODE_LABEL
)
15847 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
15851 real_name
= (*targetm
.strip_name_encoding
) (name
);
15852 if (TARGET_MINIMAL_TOC
)
15853 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
15856 fprintf (file
, "\t.tc %s", real_name
);
15859 fprintf (file
, ".N%d", - offset
);
15861 fprintf (file
, ".P%d", offset
);
15863 fputs ("[TC],", file
);
15866 /* Currently C++ toc references to vtables can be emitted before it
15867 is decided whether the vtable is public or private. If this is
15868 the case, then the linker will eventually complain that there is
15869 a TOC reference to an unknown section. Thus, for vtables only,
15870 we emit the TOC reference to reference the symbol and not the
15872 if (VTABLE_NAME_P (name
))
15874 RS6000_OUTPUT_BASENAME (file
, name
);
15876 fprintf (file
, "%d", offset
);
15877 else if (offset
> 0)
15878 fprintf (file
, "+%d", offset
);
15881 output_addr_const (file
, x
);
15885 /* Output an assembler pseudo-op to write an ASCII string of N characters
15886 starting at P to FILE.
15888 On the RS/6000, we have to do this using the .byte operation and
15889 write out special characters outside the quoted string.
15890 Also, the assembler is broken; very long strings are truncated,
15891 so we must artificially break them up early. */
15894 output_ascii (FILE *file
, const char *p
, int n
)
15897 int i
, count_string
;
15898 const char *for_string
= "\t.byte \"";
15899 const char *for_decimal
= "\t.byte ";
15900 const char *to_close
= NULL
;
15903 for (i
= 0; i
< n
; i
++)
15906 if (c
>= ' ' && c
< 0177)
15909 fputs (for_string
, file
);
15912 /* Write two quotes to get one. */
15920 for_decimal
= "\"\n\t.byte ";
15924 if (count_string
>= 512)
15926 fputs (to_close
, file
);
15928 for_string
= "\t.byte \"";
15929 for_decimal
= "\t.byte ";
15937 fputs (for_decimal
, file
);
15938 fprintf (file
, "%d", c
);
15940 for_string
= "\n\t.byte \"";
15941 for_decimal
= ", ";
15947 /* Now close the string if we have written one. Then end the line. */
15949 fputs (to_close
, file
);
15952 /* Generate a unique section name for FILENAME for a section type
15953 represented by SECTION_DESC. Output goes into BUF.
15955 SECTION_DESC can be any string, as long as it is different for each
15956 possible section type.
15958 We name the section in the same manner as xlc. The name begins with an
15959 underscore followed by the filename (after stripping any leading directory
15960 names) with the last period replaced by the string SECTION_DESC. If
15961 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15965 rs6000_gen_section_name (char **buf
, const char *filename
,
15966 const char *section_desc
)
15968 const char *q
, *after_last_slash
, *last_period
= 0;
15972 after_last_slash
= filename
;
15973 for (q
= filename
; *q
; q
++)
15976 after_last_slash
= q
+ 1;
15977 else if (*q
== '.')
15981 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
15982 *buf
= (char *) xmalloc (len
);
15987 for (q
= after_last_slash
; *q
; q
++)
15989 if (q
== last_period
)
15991 strcpy (p
, section_desc
);
15992 p
+= strlen (section_desc
);
15996 else if (ISALNUM (*q
))
16000 if (last_period
== 0)
16001 strcpy (p
, section_desc
);
16006 /* Emit profile function. */
16009 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
16011 if (TARGET_PROFILE_KERNEL
)
16014 if (DEFAULT_ABI
== ABI_AIX
)
16016 #ifndef NO_PROFILE_COUNTERS
16017 # define NO_PROFILE_COUNTERS 0
16019 if (NO_PROFILE_COUNTERS
)
16020 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
16024 const char *label_name
;
16027 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
16028 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
16029 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
16031 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
16035 else if (DEFAULT_ABI
== ABI_DARWIN
)
16037 const char *mcount_name
= RS6000_MCOUNT
;
16038 int caller_addr_regno
= LINK_REGISTER_REGNUM
;
16040 /* Be conservative and always set this, at least for now. */
16041 current_function_uses_pic_offset_table
= 1;
16044 /* For PIC code, set up a stub and collect the caller's address
16045 from r0, which is where the prologue puts it. */
16046 if (MACHOPIC_INDIRECT
16047 && current_function_uses_pic_offset_table
)
16048 caller_addr_regno
= 0;
16050 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
16052 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
16056 /* Write function profiler code. */
16059 output_function_profiler (FILE *file
, int labelno
)
16064 switch (DEFAULT_ABI
)
16073 warning ("no profiling of 64-bit code for this ABI");
16076 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
16077 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
16080 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
16081 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
16082 reg_names
[0], save_lr
, reg_names
[1]);
16083 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
16084 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
16085 assemble_name (file
, buf
);
16086 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
16088 else if (flag_pic
> 1)
16090 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
16091 reg_names
[0], save_lr
, reg_names
[1]);
16092 /* Now, we need to get the address of the label. */
16093 fputs ("\tbl 1f\n\t.long ", file
);
16094 assemble_name (file
, buf
);
16095 fputs ("-.\n1:", file
);
16096 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
16097 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
16098 reg_names
[0], reg_names
[11]);
16099 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
16100 reg_names
[0], reg_names
[0], reg_names
[11]);
16104 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
16105 assemble_name (file
, buf
);
16106 fputs ("@ha\n", file
);
16107 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
16108 reg_names
[0], save_lr
, reg_names
[1]);
16109 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
16110 assemble_name (file
, buf
);
16111 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
16114 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16115 fprintf (file
, "\tbl %s%s\n",
16116 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
16121 if (!TARGET_PROFILE_KERNEL
)
16123 /* Don't do anything, done in output_profile_hook (). */
16130 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
16131 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
16133 if (cfun
->static_chain_decl
!= NULL
)
16135 asm_fprintf (file
, "\tstd %s,24(%s)\n",
16136 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
16137 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
16138 asm_fprintf (file
, "\tld %s,24(%s)\n",
16139 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
16142 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
16149 /* Power4 load update and store update instructions are cracked into a
16150 load or store and an integer insn which are executed in the same cycle.
16151 Branches have their own dispatch slot which does not count against the
16152 GCC issue rate, but it changes the program flow so there are no other
16153 instructions to issue in this cycle. */
16156 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
16157 int verbose ATTRIBUTE_UNUSED
,
16158 rtx insn
, int more
)
16160 if (GET_CODE (PATTERN (insn
)) == USE
16161 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16164 if (rs6000_sched_groups
)
16166 if (is_microcoded_insn (insn
))
16168 else if (is_cracked_insn (insn
))
16169 return more
> 2 ? more
- 2 : 0;
16175 /* Adjust the cost of a scheduling dependency. Return the new cost of
16176 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16179 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
16181 if (! recog_memoized (insn
))
16184 if (REG_NOTE_KIND (link
) != 0)
16187 if (REG_NOTE_KIND (link
) == 0)
16189 /* Data dependency; DEP_INSN writes a register that INSN reads
16190 some cycles later. */
16192 /* Separate a load from a narrower, dependent store. */
16193 if (rs6000_sched_groups
16194 && GET_CODE (PATTERN (insn
)) == SET
16195 && GET_CODE (PATTERN (dep_insn
)) == SET
16196 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
16197 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
16198 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
16199 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
16202 switch (get_attr_type (insn
))
16205 /* Tell the first scheduling pass about the latency between
16206 a mtctr and bctr (and mtlr and br/blr). The first
16207 scheduling pass will not know about this latency since
16208 the mtctr instruction, which has the latency associated
16209 to it, will be generated by reload. */
16210 return TARGET_POWER
? 5 : 4;
16212 /* Leave some extra cycles between a compare and its
16213 dependent branch, to inhibit expensive mispredicts. */
16214 if ((rs6000_cpu_attr
== CPU_PPC603
16215 || rs6000_cpu_attr
== CPU_PPC604
16216 || rs6000_cpu_attr
== CPU_PPC604E
16217 || rs6000_cpu_attr
== CPU_PPC620
16218 || rs6000_cpu_attr
== CPU_PPC630
16219 || rs6000_cpu_attr
== CPU_PPC750
16220 || rs6000_cpu_attr
== CPU_PPC7400
16221 || rs6000_cpu_attr
== CPU_PPC7450
16222 || rs6000_cpu_attr
== CPU_POWER4
16223 || rs6000_cpu_attr
== CPU_POWER5
)
16224 && recog_memoized (dep_insn
)
16225 && (INSN_CODE (dep_insn
) >= 0)
16226 && (get_attr_type (dep_insn
) == TYPE_CMP
16227 || get_attr_type (dep_insn
) == TYPE_COMPARE
16228 || get_attr_type (dep_insn
) == TYPE_DELAYED_COMPARE
16229 || get_attr_type (dep_insn
) == TYPE_IMUL_COMPARE
16230 || get_attr_type (dep_insn
) == TYPE_LMUL_COMPARE
16231 || get_attr_type (dep_insn
) == TYPE_FPCOMPARE
16232 || get_attr_type (dep_insn
) == TYPE_CR_LOGICAL
16233 || get_attr_type (dep_insn
) == TYPE_DELAYED_CR
))
16238 /* Fall out to return default cost. */
16244 /* The function returns a true if INSN is microcoded.
16245 Return false otherwise. */
16248 is_microcoded_insn (rtx insn
)
16250 if (!insn
|| !INSN_P (insn
)
16251 || GET_CODE (PATTERN (insn
)) == USE
16252 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16255 if (rs6000_sched_groups
)
16257 enum attr_type type
= get_attr_type (insn
);
16258 if (type
== TYPE_LOAD_EXT_U
16259 || type
== TYPE_LOAD_EXT_UX
16260 || type
== TYPE_LOAD_UX
16261 || type
== TYPE_STORE_UX
16262 || type
== TYPE_MFCR
)
16269 /* The function returns a nonzero value if INSN can be scheduled only
16270 as the first insn in a dispatch group ("dispatch-slot restricted").
16271 In this case, the returned value indicates how many dispatch slots
16272 the insn occupies (at the beginning of the group).
16273 Return 0 otherwise. */
16276 is_dispatch_slot_restricted (rtx insn
)
16278 enum attr_type type
;
16280 if (!rs6000_sched_groups
)
16284 || insn
== NULL_RTX
16285 || GET_CODE (insn
) == NOTE
16286 || GET_CODE (PATTERN (insn
)) == USE
16287 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16290 type
= get_attr_type (insn
);
16297 case TYPE_DELAYED_CR
:
16298 case TYPE_CR_LOGICAL
:
16306 if (rs6000_cpu
== PROCESSOR_POWER5
16307 && is_cracked_insn (insn
))
16313 /* The function returns true if INSN is cracked into 2 instructions
16314 by the processor (and therefore occupies 2 issue slots). */
16317 is_cracked_insn (rtx insn
)
16319 if (!insn
|| !INSN_P (insn
)
16320 || GET_CODE (PATTERN (insn
)) == USE
16321 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16324 if (rs6000_sched_groups
)
16326 enum attr_type type
= get_attr_type (insn
);
16327 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
16328 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
16329 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
16330 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
16331 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
16332 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
16333 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
16334 || type
== TYPE_INSERT_WORD
)
16341 /* The function returns true if INSN can be issued only from
16342 the branch slot. */
16345 is_branch_slot_insn (rtx insn
)
16347 if (!insn
|| !INSN_P (insn
)
16348 || GET_CODE (PATTERN (insn
)) == USE
16349 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16352 if (rs6000_sched_groups
)
16354 enum attr_type type
= get_attr_type (insn
);
16355 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
16363 /* A C statement (sans semicolon) to update the integer scheduling
16364 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16365 INSN earlier, reduce the priority to execute INSN later. Do not
16366 define this macro if you do not need to adjust the scheduling
16367 priorities of insns. */
16370 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
16372 /* On machines (like the 750) which have asymmetric integer units,
16373 where one integer unit can do multiply and divides and the other
16374 can't, reduce the priority of multiply/divide so it is scheduled
16375 before other integer operations. */
16378 if (! INSN_P (insn
))
16381 if (GET_CODE (PATTERN (insn
)) == USE
)
16384 switch (rs6000_cpu_attr
) {
16386 switch (get_attr_type (insn
))
16393 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
16394 priority
, priority
);
16395 if (priority
>= 0 && priority
< 0x01000000)
16402 if (is_dispatch_slot_restricted (insn
)
16403 && reload_completed
16404 && current_sched_info
->sched_max_insns_priority
16405 && rs6000_sched_restricted_insns_priority
)
16408 /* Prioritize insns that can be dispatched only in the first
16410 if (rs6000_sched_restricted_insns_priority
== 1)
16411 /* Attach highest priority to insn. This means that in
16412 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16413 precede 'priority' (critical path) considerations. */
16414 return current_sched_info
->sched_max_insns_priority
;
16415 else if (rs6000_sched_restricted_insns_priority
== 2)
16416 /* Increase priority of insn by a minimal amount. This means that in
16417 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16418 considerations precede dispatch-slot restriction considerations. */
16419 return (priority
+ 1);
16425 /* Return how many instructions the machine can issue per cycle. */
16428 rs6000_issue_rate (void)
16430 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16431 if (!reload_completed
)
16434 switch (rs6000_cpu_attr
) {
16435 case CPU_RIOS1
: /* ? */
16437 case CPU_PPC601
: /* ? */
16460 /* Return how many instructions to look ahead for better insn
16464 rs6000_use_sched_lookahead (void)
16466 if (rs6000_cpu_attr
== CPU_PPC8540
)
16471 /* Determine is PAT refers to memory. */
16474 is_mem_ref (rtx pat
)
16480 if (GET_CODE (pat
) == MEM
)
16483 /* Recursively process the pattern. */
16484 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
16486 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
16489 ret
|= is_mem_ref (XEXP (pat
, i
));
16490 else if (fmt
[i
] == 'E')
16491 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
16492 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
16498 /* Determine if PAT is a PATTERN of a load insn. */
16501 is_load_insn1 (rtx pat
)
16503 if (!pat
|| pat
== NULL_RTX
)
16506 if (GET_CODE (pat
) == SET
)
16507 return is_mem_ref (SET_SRC (pat
));
16509 if (GET_CODE (pat
) == PARALLEL
)
16513 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
16514 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
16521 /* Determine if INSN loads from memory. */
16524 is_load_insn (rtx insn
)
16526 if (!insn
|| !INSN_P (insn
))
16529 if (GET_CODE (insn
) == CALL_INSN
)
16532 return is_load_insn1 (PATTERN (insn
));
16535 /* Determine if PAT is a PATTERN of a store insn. */
16538 is_store_insn1 (rtx pat
)
16540 if (!pat
|| pat
== NULL_RTX
)
16543 if (GET_CODE (pat
) == SET
)
16544 return is_mem_ref (SET_DEST (pat
));
16546 if (GET_CODE (pat
) == PARALLEL
)
16550 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
16551 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
16558 /* Determine if INSN stores to memory. */
16561 is_store_insn (rtx insn
)
16563 if (!insn
|| !INSN_P (insn
))
16566 return is_store_insn1 (PATTERN (insn
));
16569 /* Returns whether the dependence between INSN and NEXT is considered
16570 costly by the given target. */
16573 rs6000_is_costly_dependence (rtx insn
, rtx next
, rtx link
, int cost
,
16576 /* If the flag is not enbled - no dependence is considered costly;
16577 allow all dependent insns in the same group.
16578 This is the most aggressive option. */
16579 if (rs6000_sched_costly_dep
== no_dep_costly
)
16582 /* If the flag is set to 1 - a dependence is always considered costly;
16583 do not allow dependent instructions in the same group.
16584 This is the most conservative option. */
16585 if (rs6000_sched_costly_dep
== all_deps_costly
)
16588 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
16589 && is_load_insn (next
)
16590 && is_store_insn (insn
))
16591 /* Prevent load after store in the same group. */
16594 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
16595 && is_load_insn (next
)
16596 && is_store_insn (insn
)
16597 && (!link
|| (int) REG_NOTE_KIND (link
) == 0))
16598 /* Prevent load after store in the same group if it is a true
16602 /* The flag is set to X; dependences with latency >= X are considered costly,
16603 and will not be scheduled in the same group. */
16604 if (rs6000_sched_costly_dep
<= max_dep_latency
16605 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
16611 /* Return the next insn after INSN that is found before TAIL is reached,
16612 skipping any "non-active" insns - insns that will not actually occupy
16613 an issue slot. Return NULL_RTX if such an insn is not found. */
16616 get_next_active_insn (rtx insn
, rtx tail
)
16620 if (!insn
|| insn
== tail
)
16623 next_insn
= NEXT_INSN (insn
);
16626 && next_insn
!= tail
16627 && (GET_CODE(next_insn
) == NOTE
16628 || GET_CODE (PATTERN (next_insn
)) == USE
16629 || GET_CODE (PATTERN (next_insn
)) == CLOBBER
))
16631 next_insn
= NEXT_INSN (next_insn
);
16634 if (!next_insn
|| next_insn
== tail
)
16640 /* Return whether the presence of INSN causes a dispatch group termination
16641 of group WHICH_GROUP.
16643 If WHICH_GROUP == current_group, this function will return true if INSN
16644 causes the termination of the current group (i.e, the dispatch group to
16645 which INSN belongs). This means that INSN will be the last insn in the
16646 group it belongs to.
16648 If WHICH_GROUP == previous_group, this function will return true if INSN
16649 causes the termination of the previous group (i.e, the dispatch group that
16650 precedes the group to which INSN belongs). This means that INSN will be
16651 the first insn in the group it belongs to). */
16654 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
16656 enum attr_type type
;
16661 type
= get_attr_type (insn
);
16663 if (is_microcoded_insn (insn
))
16666 if (which_group
== current_group
)
16668 if (is_branch_slot_insn (insn
))
16672 else if (which_group
== previous_group
)
16674 if (is_dispatch_slot_restricted (insn
))
16682 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16683 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16686 is_costly_group (rtx
*group_insns
, rtx next_insn
)
16691 int issue_rate
= rs6000_issue_rate ();
16693 for (i
= 0; i
< issue_rate
; i
++)
16695 rtx insn
= group_insns
[i
];
16698 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
16700 rtx next
= XEXP (link
, 0);
16701 if (next
== next_insn
)
16703 cost
= insn_cost (insn
, link
, next_insn
);
16704 if (rs6000_is_costly_dependence (insn
, next_insn
, link
, cost
, 0))
16713 /* Utility of the function redefine_groups.
16714 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16715 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16716 to keep it "far" (in a separate group) from GROUP_INSNS, following
16717 one of the following schemes, depending on the value of the flag
16718 -minsert_sched_nops = X:
16719 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16720 in order to force NEXT_INSN into a separate group.
16721 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16722 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16723 insertion (has a group just ended, how many vacant issue slots remain in the
16724 last group, and how many dispatch groups were encountered so far). */
16727 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
16728 rtx next_insn
, bool *group_end
, int can_issue_more
,
16733 int issue_rate
= rs6000_issue_rate ();
16734 bool end
= *group_end
;
16737 if (next_insn
== NULL_RTX
)
16738 return can_issue_more
;
16740 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
16741 return can_issue_more
;
16743 force
= is_costly_group (group_insns
, next_insn
);
16745 return can_issue_more
;
16747 if (sched_verbose
> 6)
16748 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
16749 *group_count
,can_issue_more
);
16751 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
16754 can_issue_more
= 0;
16756 /* Since only a branch can be issued in the last issue_slot, it is
16757 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16758 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16759 in this case the last nop will start a new group and the branch
16760 will be forced to the new group. */
16761 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
16764 while (can_issue_more
> 0)
16767 emit_insn_before (nop
, next_insn
);
16775 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
16777 int n_nops
= rs6000_sched_insert_nops
;
16779 /* Nops can't be issued from the branch slot, so the effective
16780 issue_rate for nops is 'issue_rate - 1'. */
16781 if (can_issue_more
== 0)
16782 can_issue_more
= issue_rate
;
16784 if (can_issue_more
== 0)
16786 can_issue_more
= issue_rate
- 1;
16789 for (i
= 0; i
< issue_rate
; i
++)
16791 group_insns
[i
] = 0;
16798 emit_insn_before (nop
, next_insn
);
16799 if (can_issue_more
== issue_rate
- 1) /* new group begins */
16802 if (can_issue_more
== 0)
16804 can_issue_more
= issue_rate
- 1;
16807 for (i
= 0; i
< issue_rate
; i
++)
16809 group_insns
[i
] = 0;
16815 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16818 /* Is next_insn going to start a new group? */
16821 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
16822 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
16823 || (can_issue_more
< issue_rate
&&
16824 insn_terminates_group_p (next_insn
, previous_group
)));
16825 if (*group_end
&& end
)
16828 if (sched_verbose
> 6)
16829 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
16830 *group_count
, can_issue_more
);
16831 return can_issue_more
;
16834 return can_issue_more
;
16837 /* This function tries to synch the dispatch groups that the compiler "sees"
16838 with the dispatch groups that the processor dispatcher is expected to
16839 form in practice. It tries to achieve this synchronization by forcing the
16840 estimated processor grouping on the compiler (as opposed to the function
16841 'pad_goups' which tries to force the scheduler's grouping on the processor).
16843 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16844 examines the (estimated) dispatch groups that will be formed by the processor
16845 dispatcher. It marks these group boundaries to reflect the estimated
16846 processor grouping, overriding the grouping that the scheduler had marked.
16847 Depending on the value of the flag '-minsert-sched-nops' this function can
16848 force certain insns into separate groups or force a certain distance between
16849 them by inserting nops, for example, if there exists a "costly dependence"
16852 The function estimates the group boundaries that the processor will form as
16853 folllows: It keeps track of how many vacant issue slots are available after
16854 each insn. A subsequent insn will start a new group if one of the following
16856 - no more vacant issue slots remain in the current dispatch group.
16857 - only the last issue slot, which is the branch slot, is vacant, but the next
16858 insn is not a branch.
16859 - only the last 2 or less issue slots, including the branch slot, are vacant,
16860 which means that a cracked insn (which occupies two issue slots) can't be
16861 issued in this group.
16862 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16863 start a new group. */
16866 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
16868 rtx insn
, next_insn
;
16870 int can_issue_more
;
16873 int group_count
= 0;
16877 issue_rate
= rs6000_issue_rate ();
16878 group_insns
= alloca (issue_rate
* sizeof (rtx
));
16879 for (i
= 0; i
< issue_rate
; i
++)
16881 group_insns
[i
] = 0;
16883 can_issue_more
= issue_rate
;
16885 insn
= get_next_active_insn (prev_head_insn
, tail
);
16888 while (insn
!= NULL_RTX
)
16890 slot
= (issue_rate
- can_issue_more
);
16891 group_insns
[slot
] = insn
;
16893 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
16894 if (insn_terminates_group_p (insn
, current_group
))
16895 can_issue_more
= 0;
16897 next_insn
= get_next_active_insn (insn
, tail
);
16898 if (next_insn
== NULL_RTX
)
16899 return group_count
+ 1;
16901 /* Is next_insn going to start a new group? */
16903 = (can_issue_more
== 0
16904 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
16905 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
16906 || (can_issue_more
< issue_rate
&&
16907 insn_terminates_group_p (next_insn
, previous_group
)));
16909 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
16910 next_insn
, &group_end
, can_issue_more
,
16916 can_issue_more
= 0;
16917 for (i
= 0; i
< issue_rate
; i
++)
16919 group_insns
[i
] = 0;
16923 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
16924 PUT_MODE(next_insn
, VOIDmode
);
16925 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
16926 PUT_MODE (next_insn
, TImode
);
16929 if (can_issue_more
== 0)
16930 can_issue_more
= issue_rate
;
16933 return group_count
;
16936 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16937 dispatch group boundaries that the scheduler had marked. Pad with nops
16938 any dispatch groups which have vacant issue slots, in order to force the
16939 scheduler's grouping on the processor dispatcher. The function
16940 returns the number of dispatch groups found. */
16943 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
16945 rtx insn
, next_insn
;
16948 int can_issue_more
;
16950 int group_count
= 0;
16952 /* Initialize issue_rate. */
16953 issue_rate
= rs6000_issue_rate ();
16954 can_issue_more
= issue_rate
;
16956 insn
= get_next_active_insn (prev_head_insn
, tail
);
16957 next_insn
= get_next_active_insn (insn
, tail
);
16959 while (insn
!= NULL_RTX
)
16962 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
16964 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
16966 if (next_insn
== NULL_RTX
)
16971 /* If the scheduler had marked group termination at this location
16972 (between insn and next_indn), and neither insn nor next_insn will
16973 force group termination, pad the group with nops to force group
16976 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
16977 && !insn_terminates_group_p (insn
, current_group
)
16978 && !insn_terminates_group_p (next_insn
, previous_group
))
16980 if (!is_branch_slot_insn(next_insn
))
16983 while (can_issue_more
)
16986 emit_insn_before (nop
, next_insn
);
16991 can_issue_more
= issue_rate
;
16996 next_insn
= get_next_active_insn (insn
, tail
);
16999 return group_count
;
17002 /* The following function is called at the end of scheduling BB.
17003 After reload, it inserts nops at insn group bundling. */
17006 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
17011 fprintf (dump
, "=== Finishing schedule.\n");
17013 if (reload_completed
&& rs6000_sched_groups
)
17015 if (rs6000_sched_insert_nops
== sched_finish_none
)
17018 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
17019 n_groups
= pad_groups (dump
, sched_verbose
,
17020 current_sched_info
->prev_head
,
17021 current_sched_info
->next_tail
);
17023 n_groups
= redefine_groups (dump
, sched_verbose
,
17024 current_sched_info
->prev_head
,
17025 current_sched_info
->next_tail
);
17027 if (sched_verbose
>= 6)
17029 fprintf (dump
, "ngroups = %d\n", n_groups
);
17030 print_rtl (dump
, current_sched_info
->prev_head
);
17031 fprintf (dump
, "Done finish_sched\n");
17036 /* Length in units of the trampoline for entering a nested function. */
17039 rs6000_trampoline_size (void)
17043 switch (DEFAULT_ABI
)
17049 ret
= (TARGET_32BIT
) ? 12 : 24;
17054 ret
= (TARGET_32BIT
) ? 40 : 48;
17061 /* Emit RTL insns to initialize the variable parts of a trampoline.
17062 FNADDR is an RTX for the address of the function's pure code.
17063 CXT is an RTX for the static chain value for the function. */
17066 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
17068 enum machine_mode pmode
= Pmode
;
17069 int regsize
= (TARGET_32BIT
) ? 4 : 8;
17070 rtx ctx_reg
= force_reg (pmode
, cxt
);
17072 switch (DEFAULT_ABI
)
17077 /* Macros to shorten the code expansions below. */
17078 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17079 #define MEM_PLUS(addr,offset) \
17080 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17082 /* Under AIX, just build the 3 word function descriptor */
17085 rtx fn_reg
= gen_reg_rtx (pmode
);
17086 rtx toc_reg
= gen_reg_rtx (pmode
);
17087 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
17088 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
17089 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
17090 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
17091 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
17095 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17098 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
17099 FALSE
, VOIDmode
, 4,
17101 GEN_INT (rs6000_trampoline_size ()), SImode
,
17111 /* Table of valid machine attributes. */
17113 const struct attribute_spec rs6000_attribute_table
[] =
17115 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17116 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
17117 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
17118 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
17119 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17120 SUBTARGET_ATTRIBUTE_TABLE
,
17122 { NULL
, 0, 0, false, false, false, NULL
}
17125 /* Handle the "altivec" attribute. The attribute may have
17126 arguments as follows:
17128 __attribute__((altivec(vector__)))
17129 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17130 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17132 and may appear more than once (e.g., 'vector bool char') in a
17133 given declaration. */
17136 rs6000_handle_altivec_attribute (tree
*node
,
17137 tree name ATTRIBUTE_UNUSED
,
17139 int flags ATTRIBUTE_UNUSED
,
17140 bool *no_add_attrs
)
17142 tree type
= *node
, result
= NULL_TREE
;
17143 enum machine_mode mode
;
17146 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
17147 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
17148 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
17151 while (POINTER_TYPE_P (type
)
17152 || TREE_CODE (type
) == FUNCTION_TYPE
17153 || TREE_CODE (type
) == METHOD_TYPE
17154 || TREE_CODE (type
) == ARRAY_TYPE
)
17155 type
= TREE_TYPE (type
);
17157 mode
= TYPE_MODE (type
);
17159 /* Check for invalid AltiVec type qualifiers. */
17160 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
17163 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17164 else if (rs6000_warn_altivec_long
)
17165 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
17167 else if (type
== long_long_unsigned_type_node
17168 || type
== long_long_integer_type_node
)
17169 error ("use of %<long long%> in AltiVec types is invalid");
17170 else if (type
== double_type_node
)
17171 error ("use of %<double%> in AltiVec types is invalid");
17172 else if (type
== long_double_type_node
)
17173 error ("use of %<long double%> in AltiVec types is invalid");
17174 else if (type
== boolean_type_node
)
17175 error ("use of boolean types in AltiVec types is invalid");
17176 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
17177 error ("use of %<complex%> in AltiVec types is invalid");
17179 switch (altivec_type
)
17182 unsigned_p
= TYPE_UNSIGNED (type
);
17186 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
17189 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
17192 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
17194 case SFmode
: result
= V4SF_type_node
; break;
17195 /* If the user says 'vector int bool', we may be handed the 'bool'
17196 attribute _before_ the 'vector' attribute, and so select the
17197 proper type in the 'b' case below. */
17198 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
17206 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
17207 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
17208 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
17215 case V8HImode
: result
= pixel_V8HI_type_node
;
17221 if (result
&& result
!= type
&& TYPE_READONLY (type
))
17222 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
17224 *no_add_attrs
= true; /* No need to hang on to the attribute. */
17227 *node
= reconstruct_complex_type (*node
, result
);
17232 /* AltiVec defines four built-in scalar types that serve as vector
17233 elements; we must teach the compiler how to mangle them. */
17235 static const char *
17236 rs6000_mangle_fundamental_type (tree type
)
17238 if (type
== bool_char_type_node
) return "U6__boolc";
17239 if (type
== bool_short_type_node
) return "U6__bools";
17240 if (type
== pixel_type_node
) return "u7__pixel";
17241 if (type
== bool_int_type_node
) return "U6__booli";
17243 /* For all other types, use normal C++ mangling. */
17247 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17248 struct attribute_spec.handler. */
17251 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
17252 tree args ATTRIBUTE_UNUSED
,
17253 int flags ATTRIBUTE_UNUSED
,
17254 bool *no_add_attrs
)
17256 if (TREE_CODE (*node
) != FUNCTION_TYPE
17257 && TREE_CODE (*node
) != FIELD_DECL
17258 && TREE_CODE (*node
) != TYPE_DECL
)
17260 warning ("%qs attribute only applies to functions",
17261 IDENTIFIER_POINTER (name
));
17262 *no_add_attrs
= true;
17268 /* Set longcall attributes on all functions declared when
17269 rs6000_default_long_calls is true. */
17271 rs6000_set_default_type_attributes (tree type
)
17273 if (rs6000_default_long_calls
17274 && (TREE_CODE (type
) == FUNCTION_TYPE
17275 || TREE_CODE (type
) == METHOD_TYPE
))
17276 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
17278 TYPE_ATTRIBUTES (type
));
17281 /* Return a reference suitable for calling a function with the
17282 longcall attribute. */
17285 rs6000_longcall_ref (rtx call_ref
)
17287 const char *call_name
;
17290 if (GET_CODE (call_ref
) != SYMBOL_REF
)
17293 /* System V adds '.' to the internal name, so skip them. */
17294 call_name
= XSTR (call_ref
, 0);
17295 if (*call_name
== '.')
17297 while (*call_name
== '.')
17300 node
= get_identifier (call_name
);
17301 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
17304 return force_reg (Pmode
, call_ref
);
17307 #ifdef USING_ELFOS_H
17309 /* A C statement or statements to switch to the appropriate section
17310 for output of RTX in mode MODE. You can assume that RTX is some
17311 kind of constant in RTL. The argument MODE is redundant except in
17312 the case of a `const_int' rtx. Select the section by calling
17313 `text_section' or one of the alternatives for other sections.
17315 Do not define this macro if you put all constants in the read-only
17319 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
17320 unsigned HOST_WIDE_INT align
)
17322 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
17325 default_elf_select_rtx_section (mode
, x
, align
);
17328 /* A C statement or statements to switch to the appropriate
17329 section for output of DECL. DECL is either a `VAR_DECL' node
17330 or a constant of some sort. RELOC indicates whether forming
17331 the initial value of DECL requires link-time relocations. */
17334 rs6000_elf_select_section (tree decl
, int reloc
,
17335 unsigned HOST_WIDE_INT align
)
17337 /* Pretend that we're always building for a shared library when
17338 ABI_AIX, because otherwise we end up with dynamic relocations
17339 in read-only sections. This happens for function pointers,
17340 references to vtables in typeinfo, and probably other cases. */
17341 default_elf_select_section_1 (decl
, reloc
, align
,
17342 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17345 /* A C statement to build up a unique section name, expressed as a
17346 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17347 RELOC indicates whether the initial value of EXP requires
17348 link-time relocations. If you do not define this macro, GCC will use
17349 the symbol name prefixed by `.' as the section name. Note - this
17350 macro can now be called for uninitialized data items as well as
17351 initialized data and functions. */
17354 rs6000_elf_unique_section (tree decl
, int reloc
)
17356 /* As above, pretend that we're always building for a shared library
17357 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17358 default_unique_section_1 (decl
, reloc
,
17359 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17362 /* For a SYMBOL_REF, set generic flags and then perform some
17363 target-specific processing.
17365 When the AIX ABI is requested on a non-AIX system, replace the
17366 function name with the real name (with a leading .) rather than the
17367 function descriptor name. This saves a lot of overriding code to
17368 read the prefixes. */
17371 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
17373 default_encode_section_info (decl
, rtl
, first
);
17376 && TREE_CODE (decl
) == FUNCTION_DECL
17378 && DEFAULT_ABI
== ABI_AIX
)
17380 rtx sym_ref
= XEXP (rtl
, 0);
17381 size_t len
= strlen (XSTR (sym_ref
, 0));
17382 char *str
= alloca (len
+ 2);
17384 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
17385 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
17390 rs6000_elf_in_small_data_p (tree decl
)
17392 if (rs6000_sdata
== SDATA_NONE
)
17395 /* We want to merge strings, so we never consider them small data. */
17396 if (TREE_CODE (decl
) == STRING_CST
)
17399 /* Functions are never in the small data area. */
17400 if (TREE_CODE (decl
) == FUNCTION_DECL
)
17403 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
17405 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
17406 if (strcmp (section
, ".sdata") == 0
17407 || strcmp (section
, ".sdata2") == 0
17408 || strcmp (section
, ".sbss") == 0
17409 || strcmp (section
, ".sbss2") == 0
17410 || strcmp (section
, ".PPC.EMB.sdata0") == 0
17411 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
17416 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
17419 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
17420 /* If it's not public, and we're not going to reference it there,
17421 there's no need to put it in the small data section. */
17422 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
17429 #endif /* USING_ELFOS_H */
17432 /* Return a REG that occurs in ADDR with coefficient 1.
17433 ADDR can be effectively incremented by incrementing REG.
17435 r0 is special and we must not select it as an address
17436 register by this routine since our caller will try to
17437 increment the returned register via an "la" instruction. */
17440 find_addr_reg (rtx addr
)
17442 while (GET_CODE (addr
) == PLUS
)
17444 if (GET_CODE (XEXP (addr
, 0)) == REG
17445 && REGNO (XEXP (addr
, 0)) != 0)
17446 addr
= XEXP (addr
, 0);
17447 else if (GET_CODE (XEXP (addr
, 1)) == REG
17448 && REGNO (XEXP (addr
, 1)) != 0)
17449 addr
= XEXP (addr
, 1);
17450 else if (CONSTANT_P (XEXP (addr
, 0)))
17451 addr
= XEXP (addr
, 1);
17452 else if (CONSTANT_P (XEXP (addr
, 1)))
17453 addr
= XEXP (addr
, 0);
17457 if (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0)
17463 rs6000_fatal_bad_address (rtx op
)
17465 fatal_insn ("bad address", op
);
17470 static tree branch_island_list
= 0;
17472 /* Remember to generate a branch island for far calls to the given
17476 add_compiler_branch_island (tree label_name
, tree function_name
,
17479 tree branch_island
= build_tree_list (function_name
, label_name
);
17480 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
17481 TREE_CHAIN (branch_island
) = branch_island_list
;
17482 branch_island_list
= branch_island
;
17485 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17486 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17487 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17488 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17490 /* Generate far-jump branch islands for everything on the
17491 branch_island_list. Invoked immediately after the last instruction
17492 of the epilogue has been emitted; the branch-islands must be
17493 appended to, and contiguous with, the function body. Mach-O stubs
17494 are generated in machopic_output_stub(). */
17497 macho_branch_islands (void)
17500 tree branch_island
;
17502 for (branch_island
= branch_island_list
;
17504 branch_island
= TREE_CHAIN (branch_island
))
17506 const char *label
=
17507 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
17509 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
17510 char name_buf
[512];
17511 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17512 if (name
[0] == '*' || name
[0] == '&')
17513 strcpy (name_buf
, name
+1);
17517 strcpy (name_buf
+1, name
);
17519 strcpy (tmp_buf
, "\n");
17520 strcat (tmp_buf
, label
);
17521 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17522 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
17523 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
17524 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17527 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
17528 strcat (tmp_buf
, label
);
17529 strcat (tmp_buf
, "_pic\n");
17530 strcat (tmp_buf
, label
);
17531 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
17533 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
17534 strcat (tmp_buf
, name_buf
);
17535 strcat (tmp_buf
, " - ");
17536 strcat (tmp_buf
, label
);
17537 strcat (tmp_buf
, "_pic)\n");
17539 strcat (tmp_buf
, "\tmtlr r0\n");
17541 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
17542 strcat (tmp_buf
, name_buf
);
17543 strcat (tmp_buf
, " - ");
17544 strcat (tmp_buf
, label
);
17545 strcat (tmp_buf
, "_pic)\n");
17547 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
17551 strcat (tmp_buf
, ":\nlis r12,hi16(");
17552 strcat (tmp_buf
, name_buf
);
17553 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
17554 strcat (tmp_buf
, name_buf
);
17555 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
17557 output_asm_insn (tmp_buf
, 0);
17558 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17559 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
17560 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
17561 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17564 branch_island_list
= 0;
17567 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17568 already there or not. */
17571 no_previous_def (tree function_name
)
17573 tree branch_island
;
17574 for (branch_island
= branch_island_list
;
17576 branch_island
= TREE_CHAIN (branch_island
))
17577 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
17582 /* GET_PREV_LABEL gets the label name from the previous definition of
17586 get_prev_label (tree function_name
)
17588 tree branch_island
;
17589 for (branch_island
= branch_island_list
;
17591 branch_island
= TREE_CHAIN (branch_island
))
17592 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
17593 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
17597 /* INSN is either a function call or a millicode call. It may have an
17598 unconditional jump in its delay slot.
17600 CALL_DEST is the routine we are calling. */
17603 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
17604 int cookie_operand_number
)
17606 static char buf
[256];
17607 if (GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
17608 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
17611 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
17613 if (no_previous_def (funname
))
17615 int line_number
= 0;
17616 rtx label_rtx
= gen_label_rtx ();
17617 char *label_buf
, temp_buf
[256];
17618 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
17619 CODE_LABEL_NUMBER (label_rtx
));
17620 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
17621 labelname
= get_identifier (label_buf
);
17622 for (; insn
&& GET_CODE (insn
) != NOTE
; insn
= PREV_INSN (insn
));
17624 line_number
= NOTE_LINE_NUMBER (insn
);
17625 add_compiler_branch_island (labelname
, funname
, line_number
);
17628 labelname
= get_prev_label (funname
);
17630 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17631 instruction will reach 'foo', otherwise link as 'bl L42'".
17632 "L42" should be a 'branch island', that will do a far jump to
17633 'foo'. Branch islands are generated in
17634 macho_branch_islands(). */
17635 sprintf (buf
, "jbsr %%z%d,%.246s",
17636 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
17639 sprintf (buf
, "bl %%z%d", dest_operand_number
);
17643 /* Generate PIC and indirect symbol stubs. */
17646 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
17648 unsigned int length
;
17649 char *symbol_name
, *lazy_ptr_name
;
17650 char *local_label_0
;
17651 static int label
= 0;
17653 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17654 symb
= (*targetm
.strip_name_encoding
) (symb
);
17657 length
= strlen (symb
);
17658 symbol_name
= alloca (length
+ 32);
17659 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
17661 lazy_ptr_name
= alloca (length
+ 32);
17662 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
17665 machopic_picsymbol_stub1_section ();
17667 machopic_symbol_stub1_section ();
17671 fprintf (file
, "\t.align 5\n");
17673 fprintf (file
, "%s:\n", stub
);
17674 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17677 local_label_0
= alloca (sizeof("\"L0000000000$spb\""));
17678 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
17680 fprintf (file
, "\tmflr r0\n");
17681 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
17682 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
17683 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
17684 lazy_ptr_name
, local_label_0
);
17685 fprintf (file
, "\tmtlr r0\n");
17686 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
17687 (TARGET_64BIT
? "ldu" : "lwzu"),
17688 lazy_ptr_name
, local_label_0
);
17689 fprintf (file
, "\tmtctr r12\n");
17690 fprintf (file
, "\tbctr\n");
17694 fprintf (file
, "\t.align 4\n");
17696 fprintf (file
, "%s:\n", stub
);
17697 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17699 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
17700 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
17701 (TARGET_64BIT
? "ldu" : "lwzu"),
17703 fprintf (file
, "\tmtctr r12\n");
17704 fprintf (file
, "\tbctr\n");
17707 machopic_lazy_symbol_ptr_section ();
17708 fprintf (file
, "%s:\n", lazy_ptr_name
);
17709 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17710 fprintf (file
, "%sdyld_stub_binding_helper\n",
17711 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
17714 /* Legitimize PIC addresses. If the address is already
17715 position-independent, we return ORIG. Newly generated
17716 position-independent addresses go into a reg. This is REG if non
17717 zero, otherwise we allocate register(s) as necessary. */
17719 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17722 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
17727 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
17728 reg
= gen_reg_rtx (Pmode
);
17730 if (GET_CODE (orig
) == CONST
)
17732 if (GET_CODE (XEXP (orig
, 0)) == PLUS
17733 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
17736 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
17738 /* Use a different reg for the intermediate value, as
17739 it will be marked UNCHANGING. */
17740 rtx reg_temp
= no_new_pseudos
? reg
: gen_reg_rtx (Pmode
);
17743 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
17746 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
17752 if (GET_CODE (offset
) == CONST_INT
)
17754 if (SMALL_INT (offset
))
17755 return plus_constant (base
, INTVAL (offset
));
17756 else if (! reload_in_progress
&& ! reload_completed
)
17757 offset
= force_reg (Pmode
, offset
);
17760 rtx mem
= force_const_mem (Pmode
, orig
);
17761 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
17764 return gen_rtx_PLUS (Pmode
, base
, offset
);
17767 /* Fall back on generic machopic code. */
17768 return machopic_legitimize_pic_address (orig
, mode
, reg
);
17771 /* This is just a placeholder to make linking work without having to
17772 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17773 ever needed for Darwin (not too likely!) this would have to get a
17774 real definition. */
17781 /* Output a .machine directive for the Darwin assembler, and call
17782 the generic start_file routine. */
17785 rs6000_darwin_file_start (void)
17787 static const struct
17793 { "ppc64", "ppc64", MASK_64BIT
},
17794 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
17795 { "power4", "ppc970", 0 },
17796 { "G5", "ppc970", 0 },
17797 { "7450", "ppc7450", 0 },
17798 { "7400", "ppc7400", MASK_ALTIVEC
},
17799 { "G4", "ppc7400", 0 },
17800 { "750", "ppc750", 0 },
17801 { "740", "ppc750", 0 },
17802 { "G3", "ppc750", 0 },
17803 { "604e", "ppc604e", 0 },
17804 { "604", "ppc604", 0 },
17805 { "603e", "ppc603", 0 },
17806 { "603", "ppc603", 0 },
17807 { "601", "ppc601", 0 },
17808 { NULL
, "ppc", 0 } };
17809 const char *cpu_id
= "";
17812 rs6000_file_start();
17814 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17815 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
17816 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
17817 && rs6000_select
[i
].string
[0] != '\0')
17818 cpu_id
= rs6000_select
[i
].string
;
17820 /* Look through the mapping array. Pick the first name that either
17821 matches the argument, has a bit set in IF_SET that is also set
17822 in the target flags, or has a NULL name. */
17825 while (mapping
[i
].arg
!= NULL
17826 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
17827 && (mapping
[i
].if_set
& target_flags
) == 0)
17830 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
17833 #endif /* TARGET_MACHO */
17836 static unsigned int
17837 rs6000_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
17839 return default_section_type_flags_1 (decl
, name
, reloc
,
17840 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17843 /* Record an element in the table of global constructors. SYMBOL is
17844 a SYMBOL_REF of the function to be called; PRIORITY is a number
17845 between 0 and MAX_INIT_PRIORITY.
17847 This differs from default_named_section_asm_out_constructor in
17848 that we have special handling for -mrelocatable. */
17851 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
17853 const char *section
= ".ctors";
17856 if (priority
!= DEFAULT_INIT_PRIORITY
)
17858 sprintf (buf
, ".ctors.%.5u",
17859 /* Invert the numbering so the linker puts us in the proper
17860 order; constructors are run from right to left, and the
17861 linker sorts in increasing order. */
17862 MAX_INIT_PRIORITY
- priority
);
17866 named_section_flags (section
, SECTION_WRITE
);
17867 assemble_align (POINTER_SIZE
);
17869 if (TARGET_RELOCATABLE
)
17871 fputs ("\t.long (", asm_out_file
);
17872 output_addr_const (asm_out_file
, symbol
);
17873 fputs (")@fixup\n", asm_out_file
);
17876 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
17880 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
17882 const char *section
= ".dtors";
17885 if (priority
!= DEFAULT_INIT_PRIORITY
)
17887 sprintf (buf
, ".dtors.%.5u",
17888 /* Invert the numbering so the linker puts us in the proper
17889 order; constructors are run from right to left, and the
17890 linker sorts in increasing order. */
17891 MAX_INIT_PRIORITY
- priority
);
17895 named_section_flags (section
, SECTION_WRITE
);
17896 assemble_align (POINTER_SIZE
);
17898 if (TARGET_RELOCATABLE
)
17900 fputs ("\t.long (", asm_out_file
);
17901 output_addr_const (asm_out_file
, symbol
);
17902 fputs (")@fixup\n", asm_out_file
);
17905 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
17909 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
17913 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
17914 ASM_OUTPUT_LABEL (file
, name
);
17915 fputs (DOUBLE_INT_ASM_OP
, file
);
17916 rs6000_output_function_entry (file
, name
);
17917 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
17920 fputs ("\t.size\t", file
);
17921 assemble_name (file
, name
);
17922 fputs (",24\n\t.type\t.", file
);
17923 assemble_name (file
, name
);
17924 fputs (",@function\n", file
);
17925 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
17927 fputs ("\t.globl\t.", file
);
17928 assemble_name (file
, name
);
17933 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
17934 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
17935 rs6000_output_function_entry (file
, name
);
17936 fputs (":\n", file
);
17940 if (TARGET_RELOCATABLE
17941 && (get_pool_size () != 0 || current_function_profile
)
17946 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
17948 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
17949 fprintf (file
, "\t.long ");
17950 assemble_name (file
, buf
);
17952 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
17953 assemble_name (file
, buf
);
17957 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
17958 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
17960 if (DEFAULT_ABI
== ABI_AIX
)
17962 const char *desc_name
, *orig_name
;
17964 orig_name
= (*targetm
.strip_name_encoding
) (name
);
17965 desc_name
= orig_name
;
17966 while (*desc_name
== '.')
17969 if (TREE_PUBLIC (decl
))
17970 fprintf (file
, "\t.globl %s\n", desc_name
);
17972 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
17973 fprintf (file
, "%s:\n", desc_name
);
17974 fprintf (file
, "\t.long %s\n", orig_name
);
17975 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
17976 if (DEFAULT_ABI
== ABI_AIX
)
17977 fputs ("\t.long 0\n", file
);
17978 fprintf (file
, "\t.previous\n");
17980 ASM_OUTPUT_LABEL (file
, name
);
17986 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
17988 fputs (GLOBAL_ASM_OP
, stream
);
17989 RS6000_OUTPUT_BASENAME (stream
, name
);
17990 putc ('\n', stream
);
17994 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
17995 tree decl ATTRIBUTE_UNUSED
)
17998 static const char * const suffix
[3] = { "PR", "RO", "RW" };
18000 if (flags
& SECTION_CODE
)
18002 else if (flags
& SECTION_WRITE
)
18007 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
18008 (flags
& SECTION_CODE
) ? "." : "",
18009 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
18013 rs6000_xcoff_select_section (tree decl
, int reloc
,
18014 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
18016 if (decl_readonly_section_1 (decl
, reloc
, 1))
18018 if (TREE_PUBLIC (decl
))
18019 read_only_data_section ();
18021 read_only_private_data_section ();
18025 if (TREE_PUBLIC (decl
))
18028 private_data_section ();
18033 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
18037 /* Use select_section for private and uninitialized data. */
18038 if (!TREE_PUBLIC (decl
)
18039 || DECL_COMMON (decl
)
18040 || DECL_INITIAL (decl
) == NULL_TREE
18041 || DECL_INITIAL (decl
) == error_mark_node
18042 || (flag_zero_initialized_in_bss
18043 && initializer_zerop (DECL_INITIAL (decl
))))
18046 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
18047 name
= (*targetm
.strip_name_encoding
) (name
);
18048 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
18051 /* Select section for constant in constant pool.
18053 On RS/6000, all constants are in the private read-only data area.
18054 However, if this is being placed in the TOC it must be output as a
18058 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
18059 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
18061 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
18064 read_only_private_data_section ();
18067 /* Remove any trailing [DS] or the like from the symbol name. */
18069 static const char *
18070 rs6000_xcoff_strip_name_encoding (const char *name
)
18075 len
= strlen (name
);
18076 if (name
[len
- 1] == ']')
18077 return ggc_alloc_string (name
, len
- 4);
18082 /* Section attributes. AIX is always PIC. */
18084 static unsigned int
18085 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
18087 unsigned int align
;
18088 unsigned int flags
= default_section_type_flags_1 (decl
, name
, reloc
, 1);
18090 /* Align to at least UNIT size. */
18091 if (flags
& SECTION_CODE
)
18092 align
= MIN_UNITS_PER_WORD
;
18094 /* Increase alignment of large objects if not already stricter. */
18095 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
18096 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
18097 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
18099 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
18102 /* Output at beginning of assembler file.
18104 Initialize the section names for the RS/6000 at this point.
18106 Specify filename, including full path, to assembler.
18108 We want to go into the TOC section so at least one .toc will be emitted.
18109 Also, in order to output proper .bs/.es pairs, we need at least one static
18110 [RW] section emitted.
18112 Finally, declare mcount when profiling to make the assembler happy. */
18115 rs6000_xcoff_file_start (void)
18117 rs6000_gen_section_name (&xcoff_bss_section_name
,
18118 main_input_filename
, ".bss_");
18119 rs6000_gen_section_name (&xcoff_private_data_section_name
,
18120 main_input_filename
, ".rw_");
18121 rs6000_gen_section_name (&xcoff_read_only_section_name
,
18122 main_input_filename
, ".ro_");
18124 fputs ("\t.file\t", asm_out_file
);
18125 output_quoted_string (asm_out_file
, main_input_filename
);
18126 fputc ('\n', asm_out_file
);
18127 if (write_symbols
!= NO_DEBUG
)
18128 private_data_section ();
18131 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
18132 rs6000_file_start ();
18135 /* Output at end of assembler file.
18136 On the RS/6000, referencing data should automatically pull in text. */
18139 rs6000_xcoff_file_end (void)
18142 fputs ("_section_.text:\n", asm_out_file
);
18144 fputs (TARGET_32BIT
18145 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18148 #endif /* TARGET_XCOFF */
18151 /* Cross-module name binding. Darwin does not support overriding
18152 functions at dynamic-link time. */
18155 rs6000_binds_local_p (tree decl
)
18157 return default_binds_local_p_1 (decl
, 0);
18161 /* Compute a (partial) cost for rtx X. Return true if the complete
18162 cost has been computed, and false if subexpressions should be
18163 scanned. In either case, *TOTAL contains the cost result. */
18166 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
18168 enum machine_mode mode
= GET_MODE (x
);
18172 /* On the RS/6000, if it is valid in the insn, it is free. */
18174 if (((outer_code
== SET
18175 || outer_code
== PLUS
18176 || outer_code
== MINUS
)
18177 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18178 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')))
18179 || (outer_code
== AND
18180 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18181 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18182 mode
== SImode
? 'L' : 'J'))
18183 || mask_operand (x
, VOIDmode
)))
18184 || ((outer_code
== IOR
|| outer_code
== XOR
)
18185 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18186 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18187 mode
== SImode
? 'L' : 'J'))))
18188 || outer_code
== ASHIFT
18189 || outer_code
== ASHIFTRT
18190 || outer_code
== LSHIFTRT
18191 || outer_code
== ROTATE
18192 || outer_code
== ROTATERT
18193 || outer_code
== ZERO_EXTRACT
18194 || (outer_code
== MULT
18195 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
18196 || ((outer_code
== DIV
|| outer_code
== UDIV
18197 || outer_code
== MOD
|| outer_code
== UMOD
)
18198 && exact_log2 (INTVAL (x
)) >= 0)
18199 || (outer_code
== COMPARE
18200 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18201 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')))
18202 || (outer_code
== EQ
18203 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18204 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18205 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18206 mode
== SImode
? 'L' : 'J'))))
18207 || (outer_code
== GTU
18208 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
18209 || (outer_code
== LTU
18210 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'P')))
18215 else if ((outer_code
== PLUS
18216 && reg_or_add_cint64_operand (x
, VOIDmode
))
18217 || (outer_code
== MINUS
18218 && reg_or_sub_cint64_operand (x
, VOIDmode
))
18219 || ((outer_code
== SET
18220 || outer_code
== IOR
18221 || outer_code
== XOR
)
18223 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
18225 *total
= COSTS_N_INSNS (1);
18232 && ((outer_code
== AND
18233 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18234 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')
18235 || mask64_operand (x
, DImode
)))
18236 || ((outer_code
== IOR
|| outer_code
== XOR
)
18237 && CONST_DOUBLE_HIGH (x
) == 0
18238 && (CONST_DOUBLE_LOW (x
)
18239 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)))
18244 else if (mode
== DImode
18245 && (outer_code
== SET
18246 || outer_code
== IOR
18247 || outer_code
== XOR
)
18248 && CONST_DOUBLE_HIGH (x
) == 0)
18250 *total
= COSTS_N_INSNS (1);
18259 /* When optimizing for size, MEM should be slightly more expensive
18260 than generating address, e.g., (plus (reg) (const)).
18261 L1 cache latency is about two instructions. */
18262 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18270 if (mode
== DFmode
)
18272 if (GET_CODE (XEXP (x
, 0)) == MULT
)
18274 /* FNMA accounted in outer NEG. */
18275 if (outer_code
== NEG
)
18276 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
18278 *total
= rs6000_cost
->dmul
;
18281 *total
= rs6000_cost
->fp
;
18283 else if (mode
== SFmode
)
18285 /* FNMA accounted in outer NEG. */
18286 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
18289 *total
= rs6000_cost
->fp
;
18291 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
18293 /* The rs6000 doesn't have shift-and-add instructions. */
18294 rs6000_rtx_costs (XEXP (x
, 0), MULT
, PLUS
, total
);
18295 *total
+= COSTS_N_INSNS (1);
18298 *total
= COSTS_N_INSNS (1);
18302 if (mode
== DFmode
)
18304 if (GET_CODE (XEXP (x
, 0)) == MULT
)
18306 /* FNMA accounted in outer NEG. */
18307 if (outer_code
== NEG
)
18310 *total
= rs6000_cost
->dmul
;
18313 *total
= rs6000_cost
->fp
;
18315 else if (mode
== SFmode
)
18317 /* FNMA accounted in outer NEG. */
18318 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
18321 *total
= rs6000_cost
->fp
;
18323 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
18325 /* The rs6000 doesn't have shift-and-sub instructions. */
18326 rs6000_rtx_costs (XEXP (x
, 0), MULT
, MINUS
, total
);
18327 *total
+= COSTS_N_INSNS (1);
18330 *total
= COSTS_N_INSNS (1);
18334 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
18335 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
18337 if (INTVAL (XEXP (x
, 1)) >= -256
18338 && INTVAL (XEXP (x
, 1)) <= 255)
18339 *total
= rs6000_cost
->mulsi_const9
;
18341 *total
= rs6000_cost
->mulsi_const
;
18343 /* FMA accounted in outer PLUS/MINUS. */
18344 else if ((mode
== DFmode
|| mode
== SFmode
)
18345 && (outer_code
== PLUS
|| outer_code
== MINUS
))
18347 else if (mode
== DFmode
)
18348 *total
= rs6000_cost
->dmul
;
18349 else if (mode
== SFmode
)
18350 *total
= rs6000_cost
->fp
;
18351 else if (mode
== DImode
)
18352 *total
= rs6000_cost
->muldi
;
18354 *total
= rs6000_cost
->mulsi
;
18359 if (FLOAT_MODE_P (mode
))
18361 *total
= mode
== DFmode
? rs6000_cost
->ddiv
18362 : rs6000_cost
->sdiv
;
18369 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
18370 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
18372 if (code
== DIV
|| code
== MOD
)
18374 *total
= COSTS_N_INSNS (2);
18377 *total
= COSTS_N_INSNS (1);
18381 if (GET_MODE (XEXP (x
, 1)) == DImode
)
18382 *total
= rs6000_cost
->divdi
;
18384 *total
= rs6000_cost
->divsi
;
18386 /* Add in shift and subtract for MOD. */
18387 if (code
== MOD
|| code
== UMOD
)
18388 *total
+= COSTS_N_INSNS (2);
18392 *total
= COSTS_N_INSNS (4);
18396 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
18407 *total
= COSTS_N_INSNS (1);
18415 /* Handle mul_highpart. */
18416 if (outer_code
== TRUNCATE
18417 && GET_CODE (XEXP (x
, 0)) == MULT
)
18419 if (mode
== DImode
)
18420 *total
= rs6000_cost
->muldi
;
18422 *total
= rs6000_cost
->mulsi
;
18425 else if (outer_code
== AND
)
18428 *total
= COSTS_N_INSNS (1);
18433 if (GET_CODE (XEXP (x
, 0)) == MEM
)
18436 *total
= COSTS_N_INSNS (1);
18442 if (!FLOAT_MODE_P (mode
))
18444 *total
= COSTS_N_INSNS (1);
18450 case UNSIGNED_FLOAT
:
18454 case FLOAT_TRUNCATE
:
18455 *total
= rs6000_cost
->fp
;
18459 switch (XINT (x
, 1))
18462 *total
= rs6000_cost
->fp
;
18474 *total
= COSTS_N_INSNS (1);
18477 else if (FLOAT_MODE_P (mode
)
18478 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18480 *total
= rs6000_cost
->fp
;
18488 /* Carry bit requires mode == Pmode.
18489 NEG or PLUS already counted so only add one. */
18491 && (outer_code
== NEG
|| outer_code
== PLUS
))
18493 *total
= COSTS_N_INSNS (1);
18496 if (outer_code
== SET
)
18498 if (XEXP (x
, 1) == const0_rtx
)
18500 *total
= COSTS_N_INSNS (2);
18503 else if (mode
== Pmode
)
18505 *total
= COSTS_N_INSNS (3);
18514 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
18516 *total
= COSTS_N_INSNS (2);
18520 if (outer_code
== COMPARE
)
18534 /* A C expression returning the cost of moving data from a register of class
18535 CLASS1 to one of CLASS2. */
18538 rs6000_register_move_cost (enum machine_mode mode
,
18539 enum reg_class from
, enum reg_class to
)
18541 /* Moves from/to GENERAL_REGS. */
18542 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
18543 || reg_classes_intersect_p (from
, GENERAL_REGS
))
18545 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
18548 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
18549 return (rs6000_memory_move_cost (mode
, from
, 0)
18550 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
18552 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18554 else if (from
== CR_REGS
)
18558 /* A move will cost one instruction per GPR moved. */
18559 return 2 * HARD_REGNO_NREGS (0, mode
);
18562 /* Moving between two similar registers is just one instruction. */
18563 else if (reg_classes_intersect_p (to
, from
))
18564 return mode
== TFmode
? 4 : 2;
18566 /* Everything else has to go through GENERAL_REGS. */
18568 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
18569 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
18572 /* A C expressions returning the cost of moving data of MODE from a register to
18576 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
18577 int in ATTRIBUTE_UNUSED
)
18579 if (reg_classes_intersect_p (class, GENERAL_REGS
))
18580 return 4 * HARD_REGNO_NREGS (0, mode
);
18581 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
18582 return 4 * HARD_REGNO_NREGS (32, mode
);
18583 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
18584 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO
, mode
);
18586 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
18589 /* Return an RTX representing where to find the function value of a
18590 function returning MODE. */
18592 rs6000_complex_function_value (enum machine_mode mode
)
18594 unsigned int regno
;
18596 enum machine_mode inner
= GET_MODE_INNER (mode
);
18597 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
18599 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18600 regno
= FP_ARG_RETURN
;
18603 regno
= GP_ARG_RETURN
;
18605 /* 32-bit is OK since it'll go in r3/r4. */
18606 if (TARGET_32BIT
&& inner_bytes
>= 4)
18607 return gen_rtx_REG (mode
, regno
);
18610 if (inner_bytes
>= 8)
18611 return gen_rtx_REG (mode
, regno
);
18613 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
18615 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
18616 GEN_INT (inner_bytes
));
18617 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
18620 /* Compose a PARALLEL for a darwin64 struct being returned by
18624 rs6000_darwin64_function_value (CUMULATIVE_ARGS
*cum
, tree valtype
)
18627 rtx rvec
[FIRST_PSEUDO_REGISTER
], sub
, roffset
, suboff
;
18628 int k
= 0, bytepos
, tot
, elt
, i
, subbytepos
;
18629 enum machine_mode fmode
;
18631 switch (TREE_CODE (valtype
))
18634 for (f
= TYPE_FIELDS (valtype
); f
; f
= TREE_CHAIN (f
))
18635 if (TREE_CODE (f
) == FIELD_DECL
)
18637 ftype
= TREE_TYPE (f
);
18638 fmode
= TYPE_MODE (ftype
);
18639 bytepos
= int_bit_position (f
) / BITS_PER_UNIT
;
18640 if (USE_FP_FOR_ARG_P (cum
, fmode
, ftype
))
18642 sub
= gen_rtx_REG (fmode
, cum
->fregno
++);
18643 cum
->sysv_gregno
++;
18645 else if (USE_ALTIVEC_FOR_ARG_P (cum
, fmode
, ftype
, 1))
18647 sub
= gen_rtx_REG (fmode
, cum
->vregno
++);
18648 cum
->sysv_gregno
++;
18650 else if (fmode
== BLKmode
18651 && (TREE_CODE (ftype
) == RECORD_TYPE
18652 || TREE_CODE (ftype
) == ARRAY_TYPE
))
18653 sub
= rs6000_darwin64_function_value (cum
, ftype
);
18655 sub
= gen_rtx_REG (fmode
, cum
->sysv_gregno
++);
18656 if (sub
== NULL_RTX
)
18658 else if (GET_CODE (sub
) == PARALLEL
)
18660 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
18662 rtx subsub
= XVECEXP (sub
, 0, i
);
18664 suboff
= XEXP (subsub
, 1);
18665 subbytepos
= INTVAL (suboff
);
18666 subbytepos
+= bytepos
;
18667 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
18668 subsub
= XEXP (subsub
, 0);
18669 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
18674 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
18675 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
18679 return gen_rtx_PARALLEL (TYPE_MODE (valtype
), gen_rtvec_v (k
, rvec
));
18684 /* If passing by value won't work, give up. */
18685 if (int_size_in_bytes (valtype
) <= 0)
18687 ftype
= TREE_TYPE (valtype
);
18688 fmode
= TYPE_MODE (ftype
);
18689 tot
= int_size_in_bytes (valtype
) / int_size_in_bytes (ftype
);
18691 for (elt
= 0; elt
< tot
; ++elt
)
18693 if (USE_FP_FOR_ARG_P (cum
, fmode
, ftype
))
18695 sub
= gen_rtx_REG (fmode
, cum
->fregno
++);
18696 cum
->sysv_gregno
++;
18698 else if (USE_ALTIVEC_FOR_ARG_P (cum
, fmode
, ftype
, 1))
18700 sub
= gen_rtx_REG (fmode
, cum
->vregno
++);
18701 cum
->sysv_gregno
++;
18703 else if (fmode
== BLKmode
18704 && (TREE_CODE (ftype
) == RECORD_TYPE
18705 || TREE_CODE (ftype
) == ARRAY_TYPE
))
18706 sub
= rs6000_darwin64_function_value (cum
, ftype
);
18708 sub
= gen_rtx_REG (fmode
, cum
->sysv_gregno
++);
18709 if (sub
== NULL_RTX
)
18711 else if (GET_CODE (sub
) == PARALLEL
)
18713 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
18715 rtx subsub
= XVECEXP (sub
, 0, i
);
18717 suboff
= XEXP (subsub
, 1);
18718 subbytepos
= INTVAL (suboff
);
18719 subbytepos
+= bytepos
;
18720 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
18721 subsub
= XEXP (subsub
, 0);
18722 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
18727 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
18728 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
18730 bytepos
+= int_size_in_bytes (ftype
);
18733 return gen_rtx_PARALLEL (TYPE_MODE (valtype
), gen_rtvec_v (k
, rvec
));
18742 /* Define how to find the value returned by a function.
18743 VALTYPE is the data type of the value (as a tree).
18744 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18745 otherwise, FUNC is 0.
18747 On the SPE, both FPs and vectors are returned in r3.
18749 On RS/6000 an integer value is in r3 and a floating-point value is in
18750 fp1, unless -msoft-float. */
18753 rs6000_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
18755 enum machine_mode mode
;
18756 unsigned int regno
;
18758 /* Special handling for structs in darwin64. */
18759 if (rs6000_darwin64_abi
18760 && TYPE_MODE (valtype
) == BLKmode
18761 && (TREE_CODE (valtype
) == RECORD_TYPE
18762 || TREE_CODE (valtype
) == ARRAY_TYPE
))
18764 CUMULATIVE_ARGS valcum
;
18767 valcum
.sysv_gregno
= GP_ARG_RETURN
;
18768 valcum
.fregno
= FP_ARG_MIN_REG
;
18769 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
18770 valret
= rs6000_darwin64_function_value (&valcum
, valtype
);
18773 /* Otherwise fall through to standard ABI rules. */
18776 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
18778 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18779 return gen_rtx_PARALLEL (DImode
,
18781 gen_rtx_EXPR_LIST (VOIDmode
,
18782 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18784 gen_rtx_EXPR_LIST (VOIDmode
,
18785 gen_rtx_REG (SImode
,
18786 GP_ARG_RETURN
+ 1),
18790 if ((INTEGRAL_TYPE_P (valtype
)
18791 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
18792 || POINTER_TYPE_P (valtype
))
18793 mode
= TARGET_32BIT
? SImode
: DImode
;
18795 mode
= TYPE_MODE (valtype
);
18797 if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18798 regno
= FP_ARG_RETURN
;
18799 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
18800 && targetm
.calls
.split_complex_arg
)
18801 return rs6000_complex_function_value (mode
);
18802 else if (TREE_CODE (valtype
) == VECTOR_TYPE
18803 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
18804 && ALTIVEC_VECTOR_MODE (mode
))
18805 regno
= ALTIVEC_ARG_RETURN
;
18806 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
18807 && (mode
== DFmode
|| mode
== DCmode
))
18808 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
18810 regno
= GP_ARG_RETURN
;
18812 return gen_rtx_REG (mode
, regno
);
18815 /* Define how to find the value returned by a library function
18816 assuming the value has mode MODE. */
18818 rs6000_libcall_value (enum machine_mode mode
)
18820 unsigned int regno
;
18822 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
18824 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18825 return gen_rtx_PARALLEL (DImode
,
18827 gen_rtx_EXPR_LIST (VOIDmode
,
18828 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18830 gen_rtx_EXPR_LIST (VOIDmode
,
18831 gen_rtx_REG (SImode
,
18832 GP_ARG_RETURN
+ 1),
18836 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
18837 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18838 regno
= FP_ARG_RETURN
;
18839 else if (ALTIVEC_VECTOR_MODE (mode
)
18840 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
18841 regno
= ALTIVEC_ARG_RETURN
;
18842 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
18843 return rs6000_complex_function_value (mode
);
18844 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
18845 && (mode
== DFmode
|| mode
== DCmode
))
18846 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
18848 regno
= GP_ARG_RETURN
;
18850 return gen_rtx_REG (mode
, regno
);
18853 /* Define the offset between two registers, FROM to be eliminated and its
18854 replacement TO, at the start of a routine. */
18856 rs6000_initial_elimination_offset (int from
, int to
)
18858 rs6000_stack_t
*info
= rs6000_stack_info ();
18859 HOST_WIDE_INT offset
;
18861 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
18862 offset
= info
->push_p
? 0 : -info
->total_size
;
18863 else if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
18864 offset
= info
->total_size
;
18865 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
18866 offset
= info
->push_p
? info
->total_size
: 0;
18867 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
18875 /* Return true if TYPE is of type __ev64_opaque__. */
18878 is_ev64_opaque_type (tree type
)
18881 && (type
== opaque_V2SI_type_node
18882 || type
== opaque_V2SF_type_node
18883 || type
== opaque_p_V2SI_type_node
));
18887 rs6000_dwarf_register_span (rtx reg
)
18892 && (SPE_VECTOR_MODE (GET_MODE (reg
))
18893 || (TARGET_E500_DOUBLE
&& GET_MODE (reg
) == DFmode
)))
18898 regno
= REGNO (reg
);
18900 /* The duality of the SPE register size wreaks all kinds of havoc.
18901 This is a way of distinguishing r0 in 32-bits from r0 in
18904 gen_rtx_PARALLEL (VOIDmode
,
18907 gen_rtx_REG (SImode
, regno
+ 1200),
18908 gen_rtx_REG (SImode
, regno
))
18910 gen_rtx_REG (SImode
, regno
),
18911 gen_rtx_REG (SImode
, regno
+ 1200)));
18914 /* Map internal gcc register numbers to DWARF2 register numbers. */
18917 rs6000_dbx_register_number (unsigned int regno
)
18919 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
18921 if (regno
== MQ_REGNO
)
18923 if (regno
== LINK_REGISTER_REGNUM
)
18925 if (regno
== COUNT_REGISTER_REGNUM
)
18927 if (CR_REGNO_P (regno
))
18928 return regno
- CR0_REGNO
+ 86;
18929 if (regno
== XER_REGNO
)
18931 if (ALTIVEC_REGNO_P (regno
))
18932 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
18933 if (regno
== VRSAVE_REGNO
)
18935 if (regno
== VSCR_REGNO
)
18937 if (regno
== SPE_ACC_REGNO
)
18939 if (regno
== SPEFSCR_REGNO
)
18941 /* SPE high reg number. We get these values of regno from
18942 rs6000_dwarf_register_span. */
18943 if (regno
>= 1200 && regno
< 1232)
18949 /* target hook eh_return_filter_mode */
18950 static enum machine_mode
18951 rs6000_eh_return_filter_mode (void)
18953 return TARGET_32BIT
? SImode
: word_mode
;
18956 /* Target hook for vector_mode_supported_p. */
18958 rs6000_vector_mode_supported_p (enum machine_mode mode
)
18961 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
18964 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
18971 #include "gt-rs6000.h"