gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VCMPBFP       50)
  24    (UNSPEC_VCMPEQUB      51)
  25    (UNSPEC_VCMPEQUH      52)
  26    (UNSPEC_VCMPEQUW      53)
  27    (UNSPEC_VCMPEQFP      54)
  28    (UNSPEC_VCMPGEFP      55)
  29    (UNSPEC_VCMPGTUB      56)
  30    (UNSPEC_VCMPGTSB      57)
  31    (UNSPEC_VCMPGTUH      58)
  32    (UNSPEC_VCMPGTSH      59)
  33    (UNSPEC_VCMPGTUW      60)
  34    (UNSPEC_VCMPGTSW      61)
  35    (UNSPEC_VCMPGTFP      62)
  36    (UNSPEC_VSEL4SI      159)
  37    (UNSPEC_VSEL4SF      160)
  38    (UNSPEC_VSEL8HI      161)
  39    (UNSPEC_VSEL16QI     162)
  40    (UNSPEC_VCOND_V4SI   301)
  41    (UNSPEC_VCOND_V4SF   302)
  42    (UNSPEC_VCOND_V8HI   303)
  43    (UNSPEC_VCOND_V16QI  304)
  44    (UNSPEC_VCONDU_V4SI  305)
  45    (UNSPEC_VCONDU_V8HI  306)
  46    (UNSPEC_VCONDU_V16QI 307)
  47    ])
  48
  49 ;; Vec int modes
  50 (define_mode_macro VI [V4SI V8HI V16QI])
  51 ;; Short vec in modes
  52 (define_mode_macro VIshort [V8HI V16QI])
  53 ;; Vec float modes
  54 (define_mode_macro VF [V4SF])
  55 ;; Vec modes, pity mode macros are not composable
  56 (define_mode_macro V [V4SI V8HI V16QI V4SF])
  57
  58 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
  59
  60 ;; Generic LVX load instruction.
  61 (define_insn "altivec_lvx_<mode>"
  62   [(set (match_operand:V 0 "altivec_register_operand" "=v")
  63         (match_operand:V 1 "memory_operand" "m"))]
  64   "TARGET_ALTIVEC"
  65   "lvx %0,%y1"
  66   [(set_attr "type" "vecload")])
  67
  68 ;; Generic STVX store instruction.
  69 (define_insn "altivec_stvx_<mode>"
  70   [(set (match_operand:V 0 "memory_operand" "=m")
  71         (match_operand:V 1 "altivec_register_operand" "v"))]
  72   "TARGET_ALTIVEC"
  73   "stvx %1,%y0"
  74   [(set_attr "type" "vecstore")])
  75
  76 ;; Vector move instructions.
  77 (define_expand "mov<mode>"
  78   [(set (match_operand:V 0 "nonimmediate_operand" "")
  79         (match_operand:V 1 "any_operand" ""))]
  80   "TARGET_ALTIVEC"
  81 {
  82   rs6000_emit_move (operands[0], operands[1], <MODE>mode);
  83   DONE;
  84 })
  85
  86 (define_insn "*mov<mode>_internal"
  87   [(set (match_operand:V 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  88         (match_operand:V 1 "input_operand" "v,m,v,r,o,r,W"))]
  89   "TARGET_ALTIVEC
  90    && (register_operand (operands[0], <MODE>mode)
  91        || register_operand (operands[1], <MODE>mode))"
  92 {
  93   switch (which_alternative)
  94     {
  95     case 0: return "stvx %1,%y0";
  96     case 1: return "lvx %0,%y1";
  97     case 2: return "vor %0,%1,%1";
  98     case 3: return "#";
  99     case 4: return "#";
 100     case 5: return "#";
 101     case 6: return output_vec_const_move (operands);
 102     default: abort();
 103     }
 104 }
 105   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 106
 107 (define_split
 108   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 109         (match_operand:V4SI 1 "input_operand" ""))]
 110   "TARGET_ALTIVEC && reload_completed
 111    && gpr_or_gpr_p (operands[0], operands[1])"
 112   [(pc)]
 113 {
 114   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 115 })
 116
 117 (define_split
 118   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 119         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 120   "TARGET_ALTIVEC && reload_completed"
 121   [(set (match_dup 0) (match_dup 3))
 122    (set (match_dup 0)
 123         (plus:V4SI (match_dup 0)
 124                    (match_dup 0)))]
 125 {
 126   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 127 })
 128
 129 (define_split
 130   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 131         (match_operand:V8HI 1 "input_operand" ""))]
 132   "TARGET_ALTIVEC && reload_completed
 133    && gpr_or_gpr_p (operands[0], operands[1])"
 134   [(pc)]
 135 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 136
 137 (define_split
 138   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 139         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 140   "TARGET_ALTIVEC && reload_completed"
 141   [(set (match_dup 0) (match_dup 3))
 142    (set (match_dup 0)
 143         (plus:V8HI (match_dup 0)
 144                    (match_dup 0)))]
 145 {
 146   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 147 })
 148
 149 (define_split
 150   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 151         (match_operand:V16QI 1 "input_operand" ""))]
 152   "TARGET_ALTIVEC && reload_completed
 153    && gpr_or_gpr_p (operands[0], operands[1])"
 154   [(pc)]
 155 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 156
 157 (define_split
 158   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 159         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 160   "TARGET_ALTIVEC && reload_completed"
 161   [(set (match_dup 0) (match_dup 3))
 162    (set (match_dup 0)
 163         (plus:V16QI (match_dup 0)
 164                    (match_dup 0)))]
 165 {
 166   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 167 })
 168
 169 (define_split
 170   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 171         (match_operand:V4SF 1 "input_operand" ""))]
 172   "TARGET_ALTIVEC && reload_completed
 173    && gpr_or_gpr_p (operands[0], operands[1])"
 174   [(pc)]
 175 {
 176   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 177 })
 178
 179 (define_insn "get_vrsave_internal"
 180   [(set (match_operand:SI 0 "register_operand" "=r")
 181         (unspec:SI [(reg:SI 109)] 214))]
 182   "TARGET_ALTIVEC"
 183 {
 184   if (TARGET_MACHO)
 185      return "mfspr %0,256";
 186   else
 187      return "mfvrsave %0";
 188 }
 189   [(set_attr "type" "*")])
 190
 191 (define_insn "*set_vrsave_internal"
 192   [(match_parallel 0 "vrsave_operation"
 193      [(set (reg:SI 109)
 194            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 195                                 (reg:SI 109)] 30))])]
 196   "TARGET_ALTIVEC"
 197 {
 198   if (TARGET_MACHO)
 199     return "mtspr 256,%1";
 200   else
 201     return "mtvrsave %1";
 202 }
 203   [(set_attr "type" "*")])
 204
 205 (define_insn "*save_world"
 206  [(match_parallel 0 "save_world_operation"
 207                   [(clobber (match_operand:SI 1 "register_operand" "=l"))
 208                    (use (match_operand:SI 2 "call_operand" "s"))])]
 209  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 210  "bl %z2"
 211   [(set_attr "type" "branch")
 212    (set_attr "length" "4")])
 213
 214 (define_insn "*restore_world"
 215  [(match_parallel 0 "restore_world_operation"
 216                   [(return)
 217                    (use (match_operand:SI 1 "register_operand" "l"))
 218                    (use (match_operand:SI 2 "call_operand" "s"))
 219                    (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
 220  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 221  "b %z2")
 222
 223 ;; Simple binary operations.
 224
 225 ;; add
 226 (define_insn "add<mode>3"
 227   [(set (match_operand:VI 0 "register_operand" "=v")
 228         (plus:VI (match_operand:VI 1 "register_operand" "v")
 229                  (match_operand:VI 2 "register_operand" "v")))]
 230   "TARGET_ALTIVEC"
 231   "vaddu<VI_char>m %0,%1,%2"
 232   [(set_attr "type" "vecsimple")])
 233
 234 (define_insn "addv4sf3"
 235   [(set (match_operand:V4SF 0 "register_operand" "=v")
 236         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 237                    (match_operand:V4SF 2 "register_operand" "v")))]
 238   "TARGET_ALTIVEC"
 239   "vaddfp %0,%1,%2"
 240   [(set_attr "type" "vecfloat")])
 241
 242 (define_insn "altivec_vaddcuw"
 243   [(set (match_operand:V4SI 0 "register_operand" "=v")
 244         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 245                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 246   "TARGET_ALTIVEC"
 247   "vaddcuw %0,%1,%2"
 248   [(set_attr "type" "vecsimple")])
 249
 250 (define_insn "altivec_vaddu<VI_char>s"
 251   [(set (match_operand:VI 0 "register_operand" "=v")
 252         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 253                     (match_operand:VI 2 "register_operand" "v")] 36))
 254    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 255   "TARGET_ALTIVEC"
 256   "vaddu<VI_char>s %0,%1,%2"
 257   [(set_attr "type" "vecsimple")])
 258
 259 (define_insn "altivec_vadds<VI_char>s"
 260   [(set (match_operand:VI 0 "register_operand" "=v")
 261         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 262                     (match_operand:VI 2 "register_operand" "v")] 37))
 263    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 264   "TARGET_ALTIVEC"
 265   "vadds<VI_char>s %0,%1,%2"
 266   [(set_attr "type" "vecsimple")])
 267
 268 ;; sub
 269 (define_insn "sub<mode>3"
 270   [(set (match_operand:VI 0 "register_operand" "=v")
 271         (minus:VI (match_operand:VI 1 "register_operand" "v")
 272                   (match_operand:VI 2 "register_operand" "v")))]
 273   "TARGET_ALTIVEC"
 274   "vsubu<VI_char>m %0,%1,%2"
 275   [(set_attr "type" "vecsimple")])
 276
 277 (define_insn "subv4sf3"
 278   [(set (match_operand:V4SF 0 "register_operand" "=v")
 279         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 280                     (match_operand:V4SF 2 "register_operand" "v")))]
 281   "TARGET_ALTIVEC"
 282   "vsubfp %0,%1,%2"
 283   [(set_attr "type" "vecfloat")])
 284
 285 (define_insn "altivec_vsubcuw"
 286   [(set (match_operand:V4SI 0 "register_operand" "=v")
 287         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 288                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
 289   "TARGET_ALTIVEC"
 290   "vsubcuw %0,%1,%2"
 291   [(set_attr "type" "vecsimple")])
 292
 293 (define_insn "altivec_vsubu<VI_char>s"
 294   [(set (match_operand:VI 0 "register_operand" "=v")
 295         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 296                     (match_operand:VI 2 "register_operand" "v")] 125))
 297    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 298   "TARGET_ALTIVEC"
 299   "vsubu<VI_char>s %0,%1,%2"
 300   [(set_attr "type" "vecsimple")])
 301
 302 (define_insn "altivec_vsubs<VI_char>s"
 303   [(set (match_operand:VI 0 "register_operand" "=v")
 304         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 305                     (match_operand:VI 2 "register_operand" "v")] 126))
 306    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 307   "TARGET_ALTIVEC"
 308   "vsubs<VI_char>s %0,%1,%2"
 309   [(set_attr "type" "vecsimple")])
 310
 311 ;;
 312 (define_insn "altivec_vavgu<VI_char>"
 313   [(set (match_operand:VI 0 "register_operand" "=v")
 314         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 315                     (match_operand:VI 2 "register_operand" "v")] 44))]
 316   "TARGET_ALTIVEC"
 317   "vavgu<VI_char> %0,%1,%2"
 318   [(set_attr "type" "vecsimple")])
 319
 320 (define_insn "altivec_vavgs<VI_char>"
 321   [(set (match_operand:VI 0 "register_operand" "=v")
 322         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 323                     (match_operand:VI 2 "register_operand" "v")] 45))]
 324   "TARGET_ALTIVEC"
 325   "vavgs<VI_char> %0,%1,%2"
 326   [(set_attr "type" "vecsimple")])
 327
 328 (define_insn "altivec_vcmpbfp"
 329   [(set (match_operand:V4SI 0 "register_operand" "=v")
 330         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 331                       (match_operand:V4SF 2 "register_operand" "v")]
 332                       UNSPEC_VCMPBFP))]
 333   "TARGET_ALTIVEC"
 334   "vcmpbfp %0,%1,%2"
 335   [(set_attr "type" "veccmp")])
 336
 337 (define_insn "altivec_vcmpequb"
 338   [(set (match_operand:V16QI 0 "register_operand" "=v")
 339         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 340                        (match_operand:V16QI 2 "register_operand" "v")]
 341                        UNSPEC_VCMPEQUB))]
 342   "TARGET_ALTIVEC"
 343   "vcmpequb %0,%1,%2"
 344   [(set_attr "type" "vecsimple")])
 345
 346 (define_insn "altivec_vcmpequh"
 347   [(set (match_operand:V8HI 0 "register_operand" "=v")
 348         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 349                       (match_operand:V8HI 2 "register_operand" "v")]
 350                       UNSPEC_VCMPEQUH))]
 351   "TARGET_ALTIVEC"
 352   "vcmpequh %0,%1,%2"
 353   [(set_attr "type" "vecsimple")])
 354
 355 (define_insn "altivec_vcmpequw"
 356   [(set (match_operand:V4SI 0 "register_operand" "=v")
 357         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 358                       (match_operand:V4SI 2 "register_operand" "v")]
 359                       UNSPEC_VCMPEQUW))]
 360   "TARGET_ALTIVEC"
 361   "vcmpequw %0,%1,%2"
 362   [(set_attr "type" "vecsimple")])
 363
 364 (define_insn "altivec_vcmpeqfp"
 365   [(set (match_operand:V4SI 0 "register_operand" "=v")
 366         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 367                       (match_operand:V4SF 2 "register_operand" "v")]
 368                       UNSPEC_VCMPEQFP))]
 369   "TARGET_ALTIVEC"
 370   "vcmpeqfp %0,%1,%2"
 371   [(set_attr "type" "veccmp")])
 372
 373 (define_insn "altivec_vcmpgefp"
 374   [(set (match_operand:V4SI 0 "register_operand" "=v")
 375         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 376                       (match_operand:V4SF 2 "register_operand" "v")]
 377                        UNSPEC_VCMPGEFP))]
 378   "TARGET_ALTIVEC"
 379   "vcmpgefp %0,%1,%2"
 380   [(set_attr "type" "veccmp")])
 381
 382 (define_insn "altivec_vcmpgtub"
 383   [(set (match_operand:V16QI 0 "register_operand" "=v")
 384         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 385                        (match_operand:V16QI 2 "register_operand" "v")]
 386                        UNSPEC_VCMPGTUB))]
 387   "TARGET_ALTIVEC"
 388   "vcmpgtub %0,%1,%2"
 389   [(set_attr "type" "vecsimple")])
 390
 391 (define_insn "altivec_vcmpgtsb"
 392   [(set (match_operand:V16QI 0 "register_operand" "=v")
 393         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 394                        (match_operand:V16QI 2 "register_operand" "v")]
 395                        UNSPEC_VCMPGTSB))]
 396   "TARGET_ALTIVEC"
 397   "vcmpgtsb %0,%1,%2"
 398   [(set_attr "type" "vecsimple")])
 399
 400 (define_insn "altivec_vcmpgtuh"
 401   [(set (match_operand:V8HI 0 "register_operand" "=v")
 402         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 403                       (match_operand:V8HI 2 "register_operand" "v")]
 404                       UNSPEC_VCMPGTUH))]
 405   "TARGET_ALTIVEC"
 406   "vcmpgtuh %0,%1,%2"
 407   [(set_attr "type" "vecsimple")])
 408
 409 (define_insn "altivec_vcmpgtsh"
 410   [(set (match_operand:V8HI 0 "register_operand" "=v")
 411         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 412                       (match_operand:V8HI 2 "register_operand" "v")]
 413                       UNSPEC_VCMPGTSH))]
 414   "TARGET_ALTIVEC"
 415   "vcmpgtsh %0,%1,%2"
 416   [(set_attr "type" "vecsimple")])
 417
 418 (define_insn "altivec_vcmpgtuw"
 419   [(set (match_operand:V4SI 0 "register_operand" "=v")
 420         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 421                       (match_operand:V4SI 2 "register_operand" "v")]
 422                       UNSPEC_VCMPGTUW))]
 423   "TARGET_ALTIVEC"
 424   "vcmpgtuw %0,%1,%2"
 425   [(set_attr "type" "vecsimple")])
 426
 427 (define_insn "altivec_vcmpgtsw"
 428   [(set (match_operand:V4SI 0 "register_operand" "=v")
 429         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 430                       (match_operand:V4SI 2 "register_operand" "v")]
 431                       UNSPEC_VCMPGTSW))]
 432   "TARGET_ALTIVEC"
 433   "vcmpgtsw %0,%1,%2"
 434   [(set_attr "type" "vecsimple")])
 435
 436 (define_insn "altivec_vcmpgtfp"
 437   [(set (match_operand:V4SI 0 "register_operand" "=v")
 438         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 439                       (match_operand:V4SF 2 "register_operand" "v")]
 440                       UNSPEC_VCMPGTFP))]
 441   "TARGET_ALTIVEC"
 442   "vcmpgtfp %0,%1,%2"
 443   [(set_attr "type" "veccmp")])
 444
 445 ;; Fused multiply add
 446 (define_insn "altivec_vmaddfp"
 447   [(set (match_operand:V4SF 0 "register_operand" "=v")
 448         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 449                               (match_operand:V4SF 2 "register_operand" "v"))
 450                    (match_operand:V4SF 3 "register_operand" "v")))]
 451   "TARGET_ALTIVEC"
 452   "vmaddfp %0,%1,%2,%3"
 453   [(set_attr "type" "vecfloat")])
 454
 455 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 456
 457 (define_expand "mulv4sf3"
 458   [(use (match_operand:V4SF 0 "register_operand" ""))
 459    (use (match_operand:V4SF 1 "register_operand" ""))
 460    (use (match_operand:V4SF 2 "register_operand" ""))]
 461   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 462   "
 463 {
 464   rtx neg0;
 465
 466   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 467   neg0 = gen_reg_rtx (V4SFmode);
 468   emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
 469   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 470
 471   /* Use the multiply-add.  */
 472   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 473                                   neg0));
 474   DONE;
 475 }")
 476
 477 ;; Fused multiply subtract
 478 (define_insn "altivec_vnmsubfp"
 479   [(set (match_operand:V4SF 0 "register_operand" "=v")
 480         (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 481                                (match_operand:V4SF 2 "register_operand" "v"))
 482                     (match_operand:V4SF 3 "register_operand" "v"))))]
 483   "TARGET_ALTIVEC"
 484   "vnmsubfp %0,%1,%2,%3"
 485   [(set_attr "type" "vecfloat")])
 486
 487 (define_insn "altivec_vmsumu<VI_char>m"
 488   [(set (match_operand:V4SI 0 "register_operand" "=v")
 489         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 490                       (match_operand:VIshort 2 "register_operand" "v")
 491                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 492   "TARGET_ALTIVEC"
 493   "vmsumu<VI_char>m %0,%1,%2,%3"
 494   [(set_attr "type" "veccomplex")])
 495
 496 (define_insn "altivec_vmsumm<VI_char>m"
 497   [(set (match_operand:V4SI 0 "register_operand" "=v")
 498         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 499                       (match_operand:VIshort 2 "register_operand" "v")
 500                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 501   "TARGET_ALTIVEC"
 502   "vmsumm<VI_char>m %0,%1,%2,%3"
 503   [(set_attr "type" "veccomplex")])
 504
 505 (define_insn "altivec_vmsumshm"
 506   [(set (match_operand:V4SI 0 "register_operand" "=v")
 507         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 508                       (match_operand:V8HI 2 "register_operand" "v")
 509                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 510   "TARGET_ALTIVEC"
 511   "vmsumshm %0,%1,%2,%3"
 512   [(set_attr "type" "veccomplex")])
 513
 514 (define_insn "altivec_vmsumuhs"
 515   [(set (match_operand:V4SI 0 "register_operand" "=v")
 516         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 517                       (match_operand:V8HI 2 "register_operand" "v")
 518                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 519    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 520   "TARGET_ALTIVEC"
 521   "vmsumuhs %0,%1,%2,%3"
 522   [(set_attr "type" "veccomplex")])
 523
 524 (define_insn "altivec_vmsumshs"
 525   [(set (match_operand:V4SI 0 "register_operand" "=v")
 526         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 527                       (match_operand:V8HI 2 "register_operand" "v")
 528                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 529    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 530   "TARGET_ALTIVEC"
 531   "vmsumshs %0,%1,%2,%3"
 532   [(set_attr "type" "veccomplex")])
 533
 534 ;; max
 535
 536 (define_insn "umax<mode>3"
 537   [(set (match_operand:VI 0 "register_operand" "=v")
 538         (umax:VI (match_operand:VI 1 "register_operand" "v")
 539                  (match_operand:VI 2 "register_operand" "v")))]
 540   "TARGET_ALTIVEC"
 541   "vmaxu<VI_char> %0,%1,%2"
 542   [(set_attr "type" "vecsimple")])
 543
 544 (define_insn "smax<mode>3"
 545   [(set (match_operand:VI 0 "register_operand" "=v")
 546         (smax:VI (match_operand:VI 1 "register_operand" "v")
 547                  (match_operand:VI 2 "register_operand" "v")))]
 548   "TARGET_ALTIVEC"
 549   "vmaxs<VI_char> %0,%1,%2"
 550   [(set_attr "type" "vecsimple")])
 551
 552 (define_insn "smaxv4sf3"
 553   [(set (match_operand:V4SF 0 "register_operand" "=v")
 554         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 555                    (match_operand:V4SF 2 "register_operand" "v")))]
 556   "TARGET_ALTIVEC"
 557   "vmaxfp %0,%1,%2"
 558   [(set_attr "type" "veccmp")])
 559
 560 (define_insn "umin<mode>3"
 561   [(set (match_operand:VI 0 "register_operand" "=v")
 562         (umin:VI (match_operand:VI 1 "register_operand" "v")
 563                  (match_operand:VI 2 "register_operand" "v")))]
 564   "TARGET_ALTIVEC"
 565   "vminu<VI_char> %0,%1,%2"
 566   [(set_attr "type" "vecsimple")])
 567
 568 (define_insn "smin<mode>3"
 569   [(set (match_operand:VI 0 "register_operand" "=v")
 570         (smin:VI (match_operand:VI 1 "register_operand" "v")
 571                  (match_operand:VI 2 "register_operand" "v")))]
 572   "TARGET_ALTIVEC"
 573   "vmins<VI_char> %0,%1,%2"
 574   [(set_attr "type" "vecsimple")])
 575
 576 (define_insn "sminv4sf3"
 577   [(set (match_operand:V4SF 0 "register_operand" "=v")
 578         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 579                    (match_operand:V4SF 2 "register_operand" "v")))]
 580   "TARGET_ALTIVEC"
 581   "vminfp %0,%1,%2"
 582   [(set_attr "type" "veccmp")])
 583
 584 (define_insn "altivec_vmhaddshs"
 585   [(set (match_operand:V8HI 0 "register_operand" "=v")
 586         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 587                       (match_operand:V8HI 2 "register_operand" "v")
 588                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 589    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 590   "TARGET_ALTIVEC"
 591   "vmhaddshs %0,%1,%2,%3"
 592   [(set_attr "type" "veccomplex")])
 593 (define_insn "altivec_vmhraddshs"
 594   [(set (match_operand:V8HI 0 "register_operand" "=v")
 595         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 596                       (match_operand:V8HI 2 "register_operand" "v")
 597                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 598    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 599   "TARGET_ALTIVEC"
 600   "vmhraddshs %0,%1,%2,%3"
 601   [(set_attr "type" "veccomplex")])
 602 (define_insn "altivec_vmladduhm"
 603   [(set (match_operand:V8HI 0 "register_operand" "=v")
 604         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 605                       (match_operand:V8HI 2 "register_operand" "v")
 606                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 607   "TARGET_ALTIVEC"
 608   "vmladduhm %0,%1,%2,%3"
 609   [(set_attr "type" "veccomplex")])
 610
 611 (define_insn "altivec_vmrghb"
 612   [(set (match_operand:V16QI 0 "register_operand" "=v")
 613         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 614                                            (parallel [(const_int 8)
 615                                                       (const_int 9)
 616                                                       (const_int 10)
 617                                                       (const_int 11)
 618                                                       (const_int 12)
 619                                                       (const_int 13)
 620                                                       (const_int 14)
 621                                                       (const_int 15)
 622                                                       (const_int 0)
 623                                                       (const_int 1)
 624                                                       (const_int 2)
 625                                                       (const_int 3)
 626                                                       (const_int 4)
 627                                                       (const_int 5)
 628                                                       (const_int 6)
 629                                                       (const_int 7)]))
 630                       (match_operand:V16QI 2 "register_operand" "v")
 631                       (const_int 255)))]
 632   "TARGET_ALTIVEC"
 633   "vmrghb %0,%1,%2"
 634   [(set_attr "type" "vecperm")])
 635
 636 (define_insn "altivec_vmrghh"
 637   [(set (match_operand:V8HI 0 "register_operand" "=v")
 638         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 639                                            (parallel [(const_int 4)
 640                                                       (const_int 5)
 641                                                       (const_int 6)
 642                                                       (const_int 7)
 643                                                       (const_int 0)
 644                                                       (const_int 1)
 645                                                       (const_int 2)
 646                                                       (const_int 3)]))
 647                       (match_operand:V8HI 2 "register_operand" "v")
 648                       (const_int 15)))]
 649   "TARGET_ALTIVEC"
 650   "vmrghh %0,%1,%2"
 651   [(set_attr "type" "vecperm")])
 652
 653 (define_insn "altivec_vmrghw"
 654   [(set (match_operand:V4SI 0 "register_operand" "=v")
 655         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 656                                          (parallel [(const_int 2)
 657                                                     (const_int 3)
 658                                                     (const_int 0)
 659                                                     (const_int 1)]))
 660                       (match_operand:V4SI 2 "register_operand" "v")
 661                       (const_int 12)))]
 662   "TARGET_ALTIVEC"
 663   "vmrghw %0,%1,%2"
 664   [(set_attr "type" "vecperm")])
 665
 666 (define_insn "altivec_vmrglb"
 667   [(set (match_operand:V16QI 0 "register_operand" "=v")
 668         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 669                                            (parallel [(const_int 0)
 670                                                       (const_int 1)
 671                                                       (const_int 2)
 672                                                       (const_int 3)
 673                                                       (const_int 4)
 674                                                       (const_int 5)
 675                                                       (const_int 6)
 676                                                       (const_int 7)
 677                                                       (const_int 8)
 678                                                       (const_int 9)
 679                                                       (const_int 10)
 680                                                       (const_int 11)
 681                                                       (const_int 12)
 682                                                       (const_int 13)
 683                                                       (const_int 14)
 684                                                       (const_int 15)]))
 685                       (match_operand:V16QI 1 "register_operand" "v")
 686                       (const_int 255)))]
 687   "TARGET_ALTIVEC"
 688   "vmrglb %0,%1,%2"
 689   [(set_attr "type" "vecperm")])
 690
 691 (define_insn "altivec_vmrglh"
 692   [(set (match_operand:V8HI 0 "register_operand" "=v")
 693         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 694                                            (parallel [(const_int 0)
 695                                                       (const_int 1)
 696                                                       (const_int 2)
 697                                                       (const_int 3)
 698                                                       (const_int 4)
 699                                                       (const_int 5)
 700                                                       (const_int 6)
 701                                                       (const_int 7)]))
 702                       (match_operand:V8HI 1 "register_operand" "v")
 703                       (const_int 15)))]
 704   "TARGET_ALTIVEC"
 705   "vmrglh %0,%1,%2"
 706   [(set_attr "type" "vecperm")])
 707
 708 (define_insn "altivec_vmrglw"
 709   [(set (match_operand:V4SI 0 "register_operand" "=v")
 710         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 711                                          (parallel [(const_int 0)
 712                                                     (const_int 1)
 713                                                     (const_int 2)
 714                                                     (const_int 3)]))
 715                       (match_operand:V4SI 1 "register_operand" "v")
 716                       (const_int 12)))]
 717   "TARGET_ALTIVEC"
 718   "vmrglw %0,%1,%2"
 719   [(set_attr "type" "vecperm")])
 720
 721 (define_insn "altivec_vmuleub"
 722   [(set (match_operand:V8HI 0 "register_operand" "=v")
 723         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 724                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 725   "TARGET_ALTIVEC"
 726   "vmuleub %0,%1,%2"
 727   [(set_attr "type" "veccomplex")])
 728
 729 (define_insn "altivec_vmulesb"
 730   [(set (match_operand:V8HI 0 "register_operand" "=v")
 731         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 732                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 733   "TARGET_ALTIVEC"
 734   "vmulesb %0,%1,%2"
 735   [(set_attr "type" "veccomplex")])
 736
 737 (define_insn "altivec_vmuleuh"
 738   [(set (match_operand:V4SI 0 "register_operand" "=v")
 739         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 740                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 741   "TARGET_ALTIVEC"
 742   "vmuleuh %0,%1,%2"
 743   [(set_attr "type" "veccomplex")])
 744
 745 (define_insn "altivec_vmulesh"
 746   [(set (match_operand:V4SI 0 "register_operand" "=v")
 747         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 748                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 749   "TARGET_ALTIVEC"
 750   "vmulesh %0,%1,%2"
 751   [(set_attr "type" "veccomplex")])
 752
 753 (define_insn "altivec_vmuloub"
 754   [(set (match_operand:V8HI 0 "register_operand" "=v")
 755         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 756                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 757   "TARGET_ALTIVEC"
 758   "vmuloub %0,%1,%2"
 759   [(set_attr "type" "veccomplex")])
 760
 761 (define_insn "altivec_vmulosb"
 762   [(set (match_operand:V8HI 0 "register_operand" "=v")
 763         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 764                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 765   "TARGET_ALTIVEC"
 766   "vmulosb %0,%1,%2"
 767   [(set_attr "type" "veccomplex")])
 768
 769 (define_insn "altivec_vmulouh"
 770   [(set (match_operand:V4SI 0 "register_operand" "=v")
 771         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 772                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 773   "TARGET_ALTIVEC"
 774   "vmulouh %0,%1,%2"
 775   [(set_attr "type" "veccomplex")])
 776
 777 (define_insn "altivec_vmulosh"
 778   [(set (match_operand:V4SI 0 "register_operand" "=v")
 779         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 780                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 781   "TARGET_ALTIVEC"
 782   "vmulosh %0,%1,%2"
 783   [(set_attr "type" "veccomplex")])
 784
 785
 786 ;; logical ops
 787
 788 (define_insn "and<mode>3"
 789   [(set (match_operand:VI 0 "register_operand" "=v")
 790         (and:VI (match_operand:VI 1 "register_operand" "v")
 791                 (match_operand:VI 2 "register_operand" "v")))]
 792   "TARGET_ALTIVEC"
 793   "vand %0,%1,%2"
 794   [(set_attr "type" "vecsimple")])
 795
 796 (define_insn "ior<mode>3"
 797   [(set (match_operand:VI 0 "register_operand" "=v")
 798         (ior:VI (match_operand:VI 1 "register_operand" "v")
 799                 (match_operand:VI 2 "register_operand" "v")))]
 800   "TARGET_ALTIVEC"
 801   "vor %0,%1,%2"
 802   [(set_attr "type" "vecsimple")])
 803
 804 (define_insn "xor<mode>3"
 805   [(set (match_operand:VI 0 "register_operand" "=v")
 806         (xor:VI (match_operand:VI 1 "register_operand" "v")
 807                 (match_operand:VI 2 "register_operand" "v")))]
 808   "TARGET_ALTIVEC"
 809   "vxor %0,%1,%2"
 810   [(set_attr "type" "vecsimple")])
 811
 812 (define_insn "one_cmpl<mode>2"
 813   [(set (match_operand:VI 0 "register_operand" "=v")
 814         (not:VI (match_operand:VI 1 "register_operand" "v")))]
 815   "TARGET_ALTIVEC"
 816   "vnor %0,%1,%1"
 817   [(set_attr "type" "vecsimple")])
 818
 819 (define_insn "altivec_nor<mode>3"
 820   [(set (match_operand:VI 0 "register_operand" "=v")
 821         (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
 822                         (match_operand:VI 2 "register_operand" "v"))))]
 823   "TARGET_ALTIVEC"
 824   "vnor %0,%1,%2"
 825   [(set_attr "type" "vecsimple")])
 826
 827 (define_insn "andc<mode>3"
 828   [(set (match_operand:VI 0 "register_operand" "=v")
 829         (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
 830                 (match_operand:VI 1 "register_operand" "v")))]
 831   "TARGET_ALTIVEC"
 832   "vandc %0,%1,%2"
 833   [(set_attr "type" "vecsimple")])
 834
 835 (define_insn "altivec_vpkuhum"
 836   [(set (match_operand:V16QI 0 "register_operand" "=v")
 837         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 838                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 839   "TARGET_ALTIVEC"
 840   "vpkuhum %0,%1,%2"
 841   [(set_attr "type" "vecperm")])
 842
 843 (define_insn "altivec_vpkuwum"
 844   [(set (match_operand:V8HI 0 "register_operand" "=v")
 845         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 846                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
 847   "TARGET_ALTIVEC"
 848   "vpkuwum %0,%1,%2"
 849   [(set_attr "type" "vecperm")])
 850
 851 (define_insn "altivec_vpkpx"
 852   [(set (match_operand:V8HI 0 "register_operand" "=v")
 853         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 854                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
 855   "TARGET_ALTIVEC"
 856   "vpkpx %0,%1,%2"
 857   [(set_attr "type" "vecperm")])
 858
 859 (define_insn "altivec_vpkuhss"
 860   [(set (match_operand:V16QI 0 "register_operand" "=v")
 861         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 862                        (match_operand:V8HI 2 "register_operand" "v")] 96))
 863    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 864   "TARGET_ALTIVEC"
 865   "vpkuhss %0,%1,%2"
 866   [(set_attr "type" "vecperm")])
 867
 868 (define_insn "altivec_vpkshss"
 869   [(set (match_operand:V16QI 0 "register_operand" "=v")
 870         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 871                        (match_operand:V8HI 2 "register_operand" "v")] 97))
 872    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 873   "TARGET_ALTIVEC"
 874   "vpkshss %0,%1,%2"
 875   [(set_attr "type" "vecperm")])
 876
 877 (define_insn "altivec_vpkuwss"
 878   [(set (match_operand:V8HI 0 "register_operand" "=v")
 879         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 880                       (match_operand:V4SI 2 "register_operand" "v")] 98))
 881    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 882   "TARGET_ALTIVEC"
 883   "vpkuwss %0,%1,%2"
 884   [(set_attr "type" "vecperm")])
 885
 886 (define_insn "altivec_vpkswss"
 887   [(set (match_operand:V8HI 0 "register_operand" "=v")
 888         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 889                       (match_operand:V4SI 2 "register_operand" "v")] 99))
 890    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 891   "TARGET_ALTIVEC"
 892   "vpkswss %0,%1,%2"
 893   [(set_attr "type" "vecperm")])
 894
 895 (define_insn "altivec_vpkuhus"
 896   [(set (match_operand:V16QI 0 "register_operand" "=v")
 897         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 898                        (match_operand:V8HI 2 "register_operand" "v")] 100))
 899    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 900   "TARGET_ALTIVEC"
 901   "vpkuhus %0,%1,%2"
 902   [(set_attr "type" "vecperm")])
 903
 904 (define_insn "altivec_vpkshus"
 905   [(set (match_operand:V16QI 0 "register_operand" "=v")
 906         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 907                        (match_operand:V8HI 2 "register_operand" "v")] 101))
 908    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 909   "TARGET_ALTIVEC"
 910   "vpkshus %0,%1,%2"
 911   [(set_attr "type" "vecperm")])
 912
 913 (define_insn "altivec_vpkuwus"
 914   [(set (match_operand:V8HI 0 "register_operand" "=v")
 915         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 916                       (match_operand:V4SI 2 "register_operand" "v")] 102))
 917    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 918   "TARGET_ALTIVEC"
 919   "vpkuwus %0,%1,%2"
 920   [(set_attr "type" "vecperm")])
 921
 922 (define_insn "altivec_vpkswus"
 923   [(set (match_operand:V8HI 0 "register_operand" "=v")
 924         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 925                       (match_operand:V4SI 2 "register_operand" "v")] 103))
 926    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 927   "TARGET_ALTIVEC"
 928   "vpkswus %0,%1,%2"
 929   [(set_attr "type" "vecperm")])
 930
 931 (define_insn "altivec_vrl<VI_char>"
 932   [(set (match_operand:VI 0 "register_operand" "=v")
 933         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 934                     (match_operand:VI 2 "register_operand" "v")] 104))]
 935   "TARGET_ALTIVEC"
 936   "vrl<VI_char> %0,%1,%2"
 937   [(set_attr "type" "vecsimple")])
 938
 939 (define_insn "altivec_vsl<VI_char>"
 940   [(set (match_operand:VI 0 "register_operand" "=v")
 941         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 942                     (match_operand:VI 2 "register_operand" "v")] 107))]
 943   "TARGET_ALTIVEC"
 944   "vsl<VI_char> %0,%1,%2"
 945   [(set_attr "type" "vecsimple")])
 946
 947 (define_insn "altivec_vslw_v4sf"
 948   [(set (match_operand:V4SF 0 "register_operand" "=v")
 949         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
 950                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
 951   "TARGET_ALTIVEC"
 952   "vslw %0,%1,%2"
 953   [(set_attr "type" "vecsimple")])
 954
 955 (define_insn "altivec_vsl"
 956   [(set (match_operand:V4SI 0 "register_operand" "=v")
 957         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 958                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
 959   "TARGET_ALTIVEC"
 960   "vsl %0,%1,%2"
 961   [(set_attr "type" "vecperm")])
 962
 963 (define_insn "altivec_vslo"
 964   [(set (match_operand:V4SI 0 "register_operand" "=v")
 965         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 966                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
 967   "TARGET_ALTIVEC"
 968   "vslo %0,%1,%2"
 969   [(set_attr "type" "vecperm")])
 970
 971 (define_insn "altivec_vsr<VI_char>"
 972   [(set (match_operand:VI 0 "register_operand" "=v")
 973         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 974                     (match_operand:VI 2 "register_operand" "v")] 112))]
 975   "TARGET_ALTIVEC"
 976   "vsr<VI_char> %0,%1,%2"
 977   [(set_attr "type" "vecsimple")])
 978
 979 (define_insn "altivec_vsra<VI_char>"
 980   [(set (match_operand:VI 0 "register_operand" "=v")
 981         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 982                     (match_operand:VI 2 "register_operand" "v")] 115))]
 983   "TARGET_ALTIVEC"
 984   "vsra<VI_char> %0,%1,%2"
 985   [(set_attr "type" "vecsimple")])
 986
 987 (define_insn "altivec_vsr"
 988   [(set (match_operand:V4SI 0 "register_operand" "=v")
 989         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 990                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
 991   "TARGET_ALTIVEC"
 992   "vsr %0,%1,%2"
 993   [(set_attr "type" "vecperm")])
 994
 995 (define_insn "altivec_vsro"
 996   [(set (match_operand:V4SI 0 "register_operand" "=v")
 997         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 998                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
 999   "TARGET_ALTIVEC"
1000   "vsro %0,%1,%2"
1001   [(set_attr "type" "vecperm")])
1002
1003 (define_insn "altivec_vsum4ubs"
1004   [(set (match_operand:V4SI 0 "register_operand" "=v")
1005         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1006                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1007    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1008   "TARGET_ALTIVEC"
1009   "vsum4ubs %0,%1,%2"
1010   [(set_attr "type" "veccomplex")])
1011
1012 (define_insn "altivec_vsum4s<VI_char>s"
1013   [(set (match_operand:V4SI 0 "register_operand" "=v")
1014         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1015                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1016    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1017   "TARGET_ALTIVEC"
1018   "vsum4s<VI_char>s %0,%1,%2"
1019   [(set_attr "type" "veccomplex")])
1020
1021 (define_insn "altivec_vsum2sws"
1022   [(set (match_operand:V4SI 0 "register_operand" "=v")
1023         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1024                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1025    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1026   "TARGET_ALTIVEC"
1027   "vsum2sws %0,%1,%2"
1028   [(set_attr "type" "veccomplex")])
1029
1030 (define_insn "altivec_vsumsws"
1031   [(set (match_operand:V4SI 0 "register_operand" "=v")
1032         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1033                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1034    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1035   "TARGET_ALTIVEC"
1036   "vsumsws %0,%1,%2"
1037   [(set_attr "type" "veccomplex")])
1038
1039 (define_insn "altivec_vspltb"
1040   [(set (match_operand:V16QI 0 "register_operand" "=v")
1041         (vec_duplicate:V16QI
1042          (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1043                         (parallel
1044                          [(match_operand:QI 2 "immediate_operand" "i")]))))]
1045   "TARGET_ALTIVEC"
1046   "vspltb %0,%1,%2"
1047   [(set_attr "type" "vecperm")])
1048
1049 (define_insn "altivec_vsplth"
1050   [(set (match_operand:V8HI 0 "register_operand" "=v")
1051         (vec_duplicate:V8HI
1052          (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1053                         (parallel
1054                          [(match_operand:QI 2 "immediate_operand" "i")]))))]
1055   "TARGET_ALTIVEC"
1056   "vsplth %0,%1,%2"
1057   [(set_attr "type" "vecperm")])
1058
1059 (define_insn "altivec_vspltw"
1060   [(set (match_operand:V4SI 0 "register_operand" "=v")
1061         (vec_duplicate:V4SI
1062          (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1063                         (parallel
1064                          [(match_operand:QI 2 "immediate_operand" "i")]))))]
1065   "TARGET_ALTIVEC"
1066   "vspltw %0,%1,%2"
1067   [(set_attr "type" "vecperm")])
1068
1069 (define_insn "altivec_vspltisb"
1070   [(set (match_operand:V16QI 0 "register_operand" "=v")
1071         (vec_duplicate:V16QI
1072          (match_operand:QI 1 "immediate_operand" "i")))]
1073   "TARGET_ALTIVEC"
1074   "vspltisb %0,%1"
1075   [(set_attr "type" "vecperm")])
1076
1077 (define_insn "altivec_vspltish"
1078   [(set (match_operand:V8HI 0 "register_operand" "=v")
1079         (vec_duplicate:V8HI
1080          (sign_extend:HI (match_operand:QI 1 "immediate_operand" "i"))))]
1081   "TARGET_ALTIVEC"
1082   "vspltish %0,%1"
1083   [(set_attr "type" "vecperm")])
1084
1085 (define_insn "altivec_vspltisw"
1086   [(set (match_operand:V4SI 0 "register_operand" "=v")
1087         (vec_duplicate:V4SI
1088          (sign_extend:SI (match_operand:QI 1 "immediate_operand" "i"))))]
1089   "TARGET_ALTIVEC"
1090   "vspltisw %0,%1"
1091   [(set_attr "type" "vecperm")])
1092
1093 (define_insn "altivec_vspltisw_v4sf"
1094   [(set (match_operand:V4SF 0 "register_operand" "=v")
1095         (vec_duplicate:V4SF
1096          (float:SF (sign_extend:SI
1097                     (match_operand:QI 1 "immediate_operand" "i")))))]
1098   "TARGET_ALTIVEC"
1099   "vspltisw %0,%1"
1100   [(set_attr "type" "vecperm")])
1101
1102 (define_insn "ftruncv4sf2"
1103   [(set (match_operand:V4SF 0 "register_operand" "=v")
1104         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1105   "TARGET_ALTIVEC"
1106   "vrfiz %0,%1"
1107   [(set_attr "type" "vecfloat")])
1108
1109 (define_insn "altivec_vperm_v4sf"
1110   [(set (match_operand:V4SF 0 "register_operand" "=v")
1111         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1112                       (match_operand:V4SF 2 "register_operand" "v")
1113                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1114   "TARGET_ALTIVEC"
1115   "vperm %0,%1,%2,%3"
1116   [(set_attr "type" "vecperm")])
1117
1118 (define_insn "altivec_vperm_<mode>"
1119   [(set (match_operand:VI 0 "register_operand" "=v")
1120         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1121                     (match_operand:VI 2 "register_operand" "v")
1122                     (match_operand:V16QI 3 "register_operand" "v")] 144))]
1123   "TARGET_ALTIVEC"
1124   "vperm %0,%1,%2,%3"
1125   [(set_attr "type" "vecperm")])
1126
1127 (define_insn "altivec_vrfip"
1128   [(set (match_operand:V4SF 0 "register_operand" "=v")
1129         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1130   "TARGET_ALTIVEC"
1131   "vrfip %0,%1"
1132   [(set_attr "type" "vecfloat")])
1133
1134 (define_insn "altivec_vrfin"
1135   [(set (match_operand:V4SF 0 "register_operand" "=v")
1136         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1137   "TARGET_ALTIVEC"
1138   "vrfin %0,%1"
1139   [(set_attr "type" "vecfloat")])
1140
1141 (define_insn "altivec_vrfim"
1142   [(set (match_operand:V4SF 0 "register_operand" "=v")
1143         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1144   "TARGET_ALTIVEC"
1145   "vrfim %0,%1"
1146   [(set_attr "type" "vecfloat")])
1147
1148 (define_insn "altivec_vcfux"
1149   [(set (match_operand:V4SF 0 "register_operand" "=v")
1150         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1151                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1152   "TARGET_ALTIVEC"
1153   "vcfux %0,%1,%2"
1154   [(set_attr "type" "vecfloat")])
1155
1156 (define_insn "altivec_vcfsx"
1157   [(set (match_operand:V4SF 0 "register_operand" "=v")
1158         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1159                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1160   "TARGET_ALTIVEC"
1161   "vcfsx %0,%1,%2"
1162   [(set_attr "type" "vecfloat")])
1163
1164 (define_insn "altivec_vctuxs"
1165   [(set (match_operand:V4SI 0 "register_operand" "=v")
1166         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1167                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1168    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1169   "TARGET_ALTIVEC"
1170   "vctuxs %0,%1,%2"
1171   [(set_attr "type" "vecfloat")])
1172
1173 (define_insn "altivec_vctsxs"
1174   [(set (match_operand:V4SI 0 "register_operand" "=v")
1175         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1176                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1177    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1178   "TARGET_ALTIVEC"
1179   "vctsxs %0,%1,%2"
1180   [(set_attr "type" "vecfloat")])
1181
1182 (define_insn "altivec_vlogefp"
1183   [(set (match_operand:V4SF 0 "register_operand" "=v")
1184         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1185   "TARGET_ALTIVEC"
1186   "vlogefp %0,%1"
1187   [(set_attr "type" "vecfloat")])
1188
1189 (define_insn "altivec_vexptefp"
1190   [(set (match_operand:V4SF 0 "register_operand" "=v")
1191         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1192   "TARGET_ALTIVEC"
1193   "vexptefp %0,%1"
1194   [(set_attr "type" "vecfloat")])
1195
1196 (define_insn "altivec_vrsqrtefp"
1197   [(set (match_operand:V4SF 0 "register_operand" "=v")
1198         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1199   "TARGET_ALTIVEC"
1200   "vrsqrtefp %0,%1"
1201   [(set_attr "type" "vecfloat")])
1202
1203 (define_insn "altivec_vrefp"
1204   [(set (match_operand:V4SF 0 "register_operand" "=v")
1205         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1206   "TARGET_ALTIVEC"
1207   "vrefp %0,%1"
1208   [(set_attr "type" "vecfloat")])
1209
1210 (define_expand "vcondv4si"
1211         [(set (match_operand:V4SI 0 "register_operand" "=v")
1212               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1213                (match_operand:V4SI 2 "register_operand" "v")
1214                (match_operand:V4SI 3 "comparison_operator" "")
1215                (match_operand:V4SI 4 "register_operand" "v")
1216                (match_operand:V4SI 5 "register_operand" "v")
1217                ] UNSPEC_VCOND_V4SI))]
1218         "TARGET_ALTIVEC"
1219         "
1220 {
1221         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1222                                           operands[3], operands[4], operands[5]))
1223         DONE;
1224         else
1225         FAIL;
1226 }
1227         ")
1228
1229 (define_expand "vconduv4si"
1230         [(set (match_operand:V4SI 0 "register_operand" "=v")
1231               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1232                (match_operand:V4SI 2 "register_operand" "v")
1233                (match_operand:V4SI 3 "comparison_operator" "")
1234                (match_operand:V4SI 4 "register_operand" "v")
1235                (match_operand:V4SI 5 "register_operand" "v")
1236                ] UNSPEC_VCONDU_V4SI))]
1237         "TARGET_ALTIVEC"
1238         "
1239 {
1240         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1241                                           operands[3], operands[4], operands[5]))
1242         DONE;
1243         else
1244         FAIL;
1245 }
1246         ")
1247
1248 (define_expand "vcondv4sf"
1249         [(set (match_operand:V4SF 0 "register_operand" "=v")
1250               (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1251                (match_operand:V4SF 2 "register_operand" "v")
1252                (match_operand:V4SF 3 "comparison_operator" "")
1253                (match_operand:V4SF 4 "register_operand" "v")
1254                (match_operand:V4SF 5 "register_operand" "v")
1255                ] UNSPEC_VCOND_V4SF))]
1256         "TARGET_ALTIVEC"
1257         "
1258 {
1259         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1260                                           operands[3], operands[4], operands[5]))
1261         DONE;
1262         else
1263         FAIL;
1264 }
1265         ")
1266
1267 (define_expand "vcondv8hi"
1268         [(set (match_operand:V4SF 0 "register_operand" "=v")
1269               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1270                (match_operand:V8HI 2 "register_operand" "v")
1271                (match_operand:V8HI 3 "comparison_operator" "")
1272                (match_operand:V8HI 4 "register_operand" "v")
1273                (match_operand:V8HI 5 "register_operand" "v")
1274                ] UNSPEC_VCOND_V8HI))]
1275         "TARGET_ALTIVEC"
1276         "
1277 {
1278         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1279                                           operands[3], operands[4], operands[5]))
1280         DONE;
1281         else
1282         FAIL;
1283 }
1284         ")
1285
1286 (define_expand "vconduv8hi"
1287         [(set (match_operand:V4SF 0 "register_operand" "=v")
1288               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1289                (match_operand:V8HI 2 "register_operand" "v")
1290                (match_operand:V8HI 3 "comparison_operator" "")
1291                (match_operand:V8HI 4 "register_operand" "v")
1292                (match_operand:V8HI 5 "register_operand" "v")
1293                ] UNSPEC_VCONDU_V8HI))]
1294         "TARGET_ALTIVEC"
1295         "
1296 {
1297         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1298                                           operands[3], operands[4], operands[5]))
1299         DONE;
1300         else
1301         FAIL;
1302 }
1303         ")
1304
1305 (define_expand "vcondv16qi"
1306         [(set (match_operand:V4SF 0 "register_operand" "=v")
1307               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1308                (match_operand:V16QI 2 "register_operand" "v")
1309                (match_operand:V16QI 3 "comparison_operator" "")
1310                (match_operand:V16QI 4 "register_operand" "v")
1311                (match_operand:V16QI 5 "register_operand" "v")
1312                ] UNSPEC_VCOND_V16QI))]
1313         "TARGET_ALTIVEC"
1314         "
1315 {
1316         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1317                                           operands[3], operands[4], operands[5]))
1318         DONE;
1319         else
1320         FAIL;
1321 }
1322         ")
1323
1324 (define_expand "vconduv16qi"
1325         [(set (match_operand:V4SF 0 "register_operand" "=v")
1326               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1327                (match_operand:V16QI 2 "register_operand" "v")
1328                (match_operand:V16QI 3 "comparison_operator" "")
1329                (match_operand:V16QI 4 "register_operand" "v")
1330                (match_operand:V16QI 5 "register_operand" "v")
1331                ] UNSPEC_VCONDU_V16QI))]
1332         "TARGET_ALTIVEC"
1333         "
1334 {
1335         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1336                                           operands[3], operands[4], operands[5]))
1337         DONE;
1338         else
1339         FAIL;
1340 }
1341         ")
1342
1343
1344 (define_insn "altivec_vsel_v4si"
1345   [(set (match_operand:V4SI 0 "register_operand" "=v")
1346         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1347                       (match_operand:V4SI 2 "register_operand" "v")
1348                       (match_operand:V4SI 3 "register_operand" "v")]
1349                       UNSPEC_VSEL4SI))]
1350   "TARGET_ALTIVEC"
1351   "vsel %0,%1,%2,%3"
1352   [(set_attr "type" "vecperm")])
1353
1354 (define_insn "altivec_vsel_v4sf"
1355   [(set (match_operand:V4SF 0 "register_operand" "=v")
1356         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1357                       (match_operand:V4SF 2 "register_operand" "v")
1358                       (match_operand:V4SI 3 "register_operand" "v")]
1359                       UNSPEC_VSEL4SF))]
1360   "TARGET_ALTIVEC"
1361   "vsel %0,%1,%2,%3"
1362   [(set_attr "type" "vecperm")])
1363
1364 (define_insn "altivec_vsel_v8hi"
1365   [(set (match_operand:V8HI 0 "register_operand" "=v")
1366         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1367                       (match_operand:V8HI 2 "register_operand" "v")
1368                       (match_operand:V8HI 3 "register_operand" "v")]
1369                       UNSPEC_VSEL8HI))]
1370   "TARGET_ALTIVEC"
1371   "vsel %0,%1,%2,%3"
1372   [(set_attr "type" "vecperm")])
1373
1374 (define_insn "altivec_vsel_v16qi"
1375   [(set (match_operand:V16QI 0 "register_operand" "=v")
1376         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1377                        (match_operand:V16QI 2 "register_operand" "v")
1378                        (match_operand:V16QI 3 "register_operand" "v")]
1379                        UNSPEC_VSEL16QI))]
1380   "TARGET_ALTIVEC"
1381   "vsel %0,%1,%2,%3"
1382   [(set_attr "type" "vecperm")])
1383
1384 (define_insn "altivec_vsldoi_v4si"
1385   [(set (match_operand:V4SI 0 "register_operand" "=v")
1386         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1387                       (match_operand:V4SI 2 "register_operand" "v")
1388                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1389   "TARGET_ALTIVEC"
1390   "vsldoi %0,%1,%2,%3"
1391   [(set_attr "type" "vecperm")])
1392
1393 (define_insn "altivec_vsldoi_v4sf"
1394   [(set (match_operand:V4SF 0 "register_operand" "=v")
1395         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1396                       (match_operand:V4SF 2 "register_operand" "v")
1397                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1398   "TARGET_ALTIVEC"
1399   "vsldoi %0,%1,%2,%3"
1400   [(set_attr "type" "vecperm")])
1401
1402 (define_insn "altivec_vsldoi_v8hi"
1403   [(set (match_operand:V8HI 0 "register_operand" "=v")
1404         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1405                       (match_operand:V8HI 2 "register_operand" "v")
1406                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1407   "TARGET_ALTIVEC"
1408   "vsldoi %0,%1,%2,%3"
1409   [(set_attr "type" "vecperm")])
1410
1411 (define_insn "altivec_vsldoi_v16qi"
1412   [(set (match_operand:V16QI 0 "register_operand" "=v")
1413         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1414                        (match_operand:V16QI 2 "register_operand" "v")
1415                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1416   "TARGET_ALTIVEC"
1417   "vsldoi %0,%1,%2,%3"
1418   [(set_attr "type" "vecperm")])
1419
1420 (define_insn "altivec_vupkhsb"
1421   [(set (match_operand:V8HI 0 "register_operand" "=v")
1422         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1423   "TARGET_ALTIVEC"
1424   "vupkhsb %0,%1"
1425   [(set_attr "type" "vecperm")])
1426
1427 (define_insn "altivec_vupkhpx"
1428   [(set (match_operand:V4SI 0 "register_operand" "=v")
1429         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1430   "TARGET_ALTIVEC"
1431   "vupkhpx %0,%1"
1432   [(set_attr "type" "vecperm")])
1433
1434 (define_insn "altivec_vupkhsh"
1435   [(set (match_operand:V4SI 0 "register_operand" "=v")
1436         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1437   "TARGET_ALTIVEC"
1438   "vupkhsh %0,%1"
1439   [(set_attr "type" "vecperm")])
1440
1441 (define_insn "altivec_vupklsb"
1442   [(set (match_operand:V8HI 0 "register_operand" "=v")
1443         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1444   "TARGET_ALTIVEC"
1445   "vupklsb %0,%1"
1446   [(set_attr "type" "vecperm")])
1447
1448 (define_insn "altivec_vupklpx"
1449   [(set (match_operand:V4SI 0 "register_operand" "=v")
1450         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1451   "TARGET_ALTIVEC"
1452   "vupklpx %0,%1"
1453   [(set_attr "type" "vecperm")])
1454
1455 (define_insn "altivec_vupklsh"
1456   [(set (match_operand:V4SI 0 "register_operand" "=v")
1457         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1458   "TARGET_ALTIVEC"
1459   "vupklsh %0,%1"
1460   [(set_attr "type" "vecperm")])
1461
1462 ;; AltiVec predicates.
1463
1464 (define_expand "cr6_test_for_zero"
1465   [(set (match_operand:SI 0 "register_operand" "=r")
1466         (eq:SI (reg:CC 74)
1467                (const_int 0)))]
1468   "TARGET_ALTIVEC"
1469   "")
1470
1471 (define_expand "cr6_test_for_zero_reverse"
1472   [(set (match_operand:SI 0 "register_operand" "=r")
1473         (eq:SI (reg:CC 74)
1474                (const_int 0)))
1475    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1476   "TARGET_ALTIVEC"
1477   "")
1478
1479 (define_expand "cr6_test_for_lt"
1480   [(set (match_operand:SI 0 "register_operand" "=r")
1481         (lt:SI (reg:CC 74)
1482                (const_int 0)))]
1483   "TARGET_ALTIVEC"
1484   "")
1485
1486 (define_expand "cr6_test_for_lt_reverse"
1487   [(set (match_operand:SI 0 "register_operand" "=r")
1488         (lt:SI (reg:CC 74)
1489                (const_int 0)))
1490    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1491   "TARGET_ALTIVEC"
1492   "")
1493
1494 ;; We can get away with generating the opcode on the fly (%3 below)
1495 ;; because all the predicates have the same scheduling parameters.
1496
1497 (define_insn "altivec_predicate_v4sf"
1498   [(set (reg:CC 74)
1499         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1500                     (match_operand:V4SF 2 "register_operand" "v")
1501                     (match_operand 3 "any_operand" "")] 174))
1502    (clobber (match_scratch:V4SF 0 "=v"))]
1503   "TARGET_ALTIVEC"
1504   "%3 %0,%1,%2"
1505 [(set_attr "type" "veccmp")])
1506
1507 (define_insn "altivec_predicate_<mode>"
1508   [(set (reg:CC 74)
1509         (unspec:CC [(match_operand:VI 1 "register_operand" "v")
1510                     (match_operand:VI 2 "register_operand" "v")
1511                     (match_operand 3 "any_operand" "")] 173))
1512    (clobber (match_scratch:VI 0 "=v"))]
1513   "TARGET_ALTIVEC"
1514   "%3 %0,%1,%2"
1515 [(set_attr "type" "veccmp")])
1516
1517 (define_insn "altivec_mtvscr"
1518   [(set (reg:SI 110)
1519         (unspec_volatile:SI
1520          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1521   "TARGET_ALTIVEC"
1522   "mtvscr %0"
1523   [(set_attr "type" "vecsimple")])
1524
1525 (define_insn "altivec_mfvscr"
1526   [(set (match_operand:V8HI 0 "register_operand" "=v")
1527         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1528   "TARGET_ALTIVEC"
1529   "mfvscr %0"
1530   [(set_attr "type" "vecsimple")])
1531
1532 (define_insn "altivec_dssall"
1533   [(unspec_volatile [(const_int 0)] 188)]
1534   "TARGET_ALTIVEC"
1535   "dssall"
1536   [(set_attr "type" "vecsimple")])
1537
1538 (define_insn "altivec_dss"
1539   [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1540   "TARGET_ALTIVEC"
1541   "dss %0"
1542   [(set_attr "type" "vecsimple")])
1543
1544 (define_insn "altivec_dst"
1545   [(unspec [(match_operand 0 "register_operand" "b")
1546             (match_operand:SI 1 "register_operand" "r")
1547             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1548   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1549   "dst %0,%1,%2"
1550   [(set_attr "type" "vecsimple")])
1551
1552 (define_insn "altivec_dstt"
1553   [(unspec [(match_operand 0 "register_operand" "b")
1554             (match_operand:SI 1 "register_operand" "r")
1555             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1556   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1557   "dstt %0,%1,%2"
1558   [(set_attr "type" "vecsimple")])
1559
1560 (define_insn "altivec_dstst"
1561   [(unspec [(match_operand 0 "register_operand" "b")
1562             (match_operand:SI 1 "register_operand" "r")
1563             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1564   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1565   "dstst %0,%1,%2"
1566   [(set_attr "type" "vecsimple")])
1567
1568 (define_insn "altivec_dststt"
1569   [(unspec [(match_operand 0 "register_operand" "b")
1570             (match_operand:SI 1 "register_operand" "r")
1571             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1572   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1573   "dststt %0,%1,%2"
1574   [(set_attr "type" "vecsimple")])
1575
1576 (define_insn "altivec_lvsl"
1577   [(set (match_operand:V16QI 0 "register_operand" "=v")
1578         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1579   "TARGET_ALTIVEC"
1580   "lvsl %0,%y1"
1581   [(set_attr "type" "vecload")])
1582
1583 (define_insn "altivec_lvsr"
1584   [(set (match_operand:V16QI 0 "register_operand" "=v")
1585         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1586   "TARGET_ALTIVEC"
1587   "lvsr %0,%y1"
1588   [(set_attr "type" "vecload")])
1589
1590 (define_expand "build_vector_mask_for_load"
1591   [(set (match_operand:V16QI 0 "register_operand" "=v")
1592         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1593   "TARGET_ALTIVEC"
1594   "
1595 {
1596   rtx addr;
1597   rtx temp;
1598
1599   if (GET_CODE (operands[1]) != MEM)
1600     abort ();
1601
1602   addr = XEXP (operands[1], 0);
1603   temp = gen_reg_rtx (GET_MODE (addr));
1604   emit_insn (gen_rtx_SET (VOIDmode, temp,
1605                           gen_rtx_NEG (GET_MODE (addr), addr)));
1606   emit_insn (gen_altivec_lvsr (operands[0],
1607                                gen_rtx_MEM (GET_MODE (operands[1]), temp)));
1608   DONE;
1609 }")
1610
1611 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1612 ;; identical rtl but different instructions-- and gcc gets confused.
1613
1614 (define_insn "altivec_lve<VI_char>x"
1615   [(parallel
1616     [(set (match_operand:VI 0 "register_operand" "=v")
1617           (match_operand:VI 1 "memory_operand" "m"))
1618      (unspec [(const_int 0)] 196)])]
1619   "TARGET_ALTIVEC"
1620   "lve<VI_char>x %0,%y1"
1621   [(set_attr "type" "vecload")])
1622
1623 (define_insn "altivec_lvxl"
1624   [(parallel
1625     [(set (match_operand:V4SI 0 "register_operand" "=v")
1626           (match_operand:V4SI 1 "memory_operand" "m"))
1627      (unspec [(const_int 0)] 213)])]
1628   "TARGET_ALTIVEC"
1629   "lvxl %0,%y1"
1630   [(set_attr "type" "vecload")])
1631
1632 (define_insn "altivec_lvx"
1633   [(set (match_operand:V4SI 0 "register_operand" "=v")
1634         (match_operand:V4SI 1 "memory_operand" "m"))]
1635   "TARGET_ALTIVEC"
1636   "lvx %0,%y1"
1637   [(set_attr "type" "vecload")])
1638
1639 (define_insn "altivec_stvx"
1640   [(parallel
1641     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1642           (match_operand:V4SI 1 "register_operand" "v"))
1643      (unspec [(const_int 0)] 201)])]
1644   "TARGET_ALTIVEC"
1645   "stvx %1,%y0"
1646   [(set_attr "type" "vecstore")])
1647
1648 (define_insn "altivec_stvxl"
1649   [(parallel
1650     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1651           (match_operand:V4SI 1 "register_operand" "v"))
1652      (unspec [(const_int 0)] 202)])]
1653   "TARGET_ALTIVEC"
1654   "stvxl %1,%y0"
1655   [(set_attr "type" "vecstore")])
1656
1657 (define_insn "altivec_stve<VI_char>x"
1658   [(parallel
1659     [(set (match_operand:VI 0 "memory_operand" "=m")
1660           (match_operand:VI 1 "register_operand" "v"))
1661      (unspec [(const_int 0)] 203)])]
1662   "TARGET_ALTIVEC"
1663   "stve<VI_char>x %1,%y0"
1664   [(set_attr "type" "vecstore")])
1665
1666 (define_insn "abs<mode>2"
1667   [(set (match_operand:VI 0 "register_operand" "=v")
1668         (abs:VI (match_operand:VI 1 "register_operand" "v")))
1669    (clobber (match_scratch:VI 2 "=&v"))
1670    (clobber (match_scratch:VI 3 "=&v"))]
1671   "TARGET_ALTIVEC"
1672   "vspltisb %2,0\;vsubu<VI_char>m %3,%2,%1\;vmaxs<VI_char> %0,%1,%3"
1673   [(set_attr "type" "vecsimple")
1674    (set_attr "length" "12")])
1675
1676 (define_insn "absv4sf2"
1677   [(set (match_operand:V4SF 0 "register_operand" "=v")
1678         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1679    (clobber (match_scratch:V4SF 2 "=&v"))
1680    (clobber (match_scratch:V4SF 3 "=&v"))]
1681   "TARGET_ALTIVEC"
1682   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1683   [(set_attr "type" "vecsimple")
1684    (set_attr "length" "12")])
1685
1686 (define_insn "altivec_abss_<mode>"
1687   [(set (match_operand:VI 0 "register_operand" "=v")
1688         (unspec:VI [(match_operand:VI 1 "register_operand" "v")] 210))
1689    (clobber (match_scratch:VI 2 "=&v"))
1690    (clobber (match_scratch:VI 3 "=&v"))]
1691   "TARGET_ALTIVEC"
1692   "vspltisb %2,0\;vsubs<VI_char>s %3,%2,%1\;vmaxs<VI_char> %0,%1,%3"
1693   [(set_attr "type" "vecsimple")
1694    (set_attr "length" "12")])
1695
1696 (define_insn "vec_realign_load_v4sf"
1697   [(set (match_operand:V4SF 0 "register_operand" "=v")
1698         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1699                       (match_operand:V4SF 2 "register_operand" "v")
1700                       (match_operand:V16QI 3 "register_operand" "v")] 216))]
1701   "TARGET_ALTIVEC"
1702   "vperm %0,%1,%2,%3"
1703   [(set_attr "type" "vecperm")])
1704
1705 (define_insn "vec_realign_load_<mode>"
1706   [(set (match_operand:VI 0 "register_operand" "=v")
1707         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1708                     (match_operand:VI 2 "register_operand" "v")
1709                     (match_operand:V16QI 3 "register_operand" "v")] 215))]
1710   "TARGET_ALTIVEC"
1711   "vperm %0,%1,%2,%3"
1712   [(set_attr "type" "vecperm")])