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Merge from mainline (gomp-merge-2005-02-26).
[official-gcc.git] / gcc / config / mips / mips.h
blob495b8190f4bf82cea62cdaf1dce8077294c53335
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* Which processor to schedule for. Since there is no difference between
34 a R2000 and R3000 in terms of the scheduler, we collapse them into
35 just an R3000. The elements of the enumeration must match exactly
36 the cpu attribute in the mips.md machine description. */
37
38 enum processor_type {
39 PROCESSOR_DEFAULT,
40 PROCESSOR_4KC,
41 PROCESSOR_5KC,
42 PROCESSOR_20KC,
43 PROCESSOR_M4K,
44 PROCESSOR_R3000,
45 PROCESSOR_R3900,
46 PROCESSOR_R6000,
47 PROCESSOR_R4000,
48 PROCESSOR_R4100,
49 PROCESSOR_R4111,
50 PROCESSOR_R4120,
51 PROCESSOR_R4130,
52 PROCESSOR_R4300,
53 PROCESSOR_R4600,
54 PROCESSOR_R4650,
55 PROCESSOR_R5000,
56 PROCESSOR_R5400,
57 PROCESSOR_R5500,
58 PROCESSOR_R7000,
59 PROCESSOR_R8000,
60 PROCESSOR_R9000,
61 PROCESSOR_SB1,
62 PROCESSOR_SR71000
63 };
64
65 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
66 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
67 to work on a 64 bit machine. */
68
69 #define ABI_32 0
70 #define ABI_N32 1
71 #define ABI_64 2
72 #define ABI_EABI 3
73 #define ABI_O64 4
74
75 /* Information about one recognized processor. Defined here for the
76 benefit of TARGET_CPU_CPP_BUILTINS. */
77 struct mips_cpu_info {
78 /* The 'canonical' name of the processor as far as GCC is concerned.
79 It's typically a manufacturer's prefix followed by a numerical
80 designation. It should be lower case. */
81 const char *name;
82
83 /* The internal processor number that most closely matches this
84 entry. Several processors can have the same value, if there's no
85 difference between them from GCC's point of view. */
86 enum processor_type cpu;
87
88 /* The ISA level that the processor implements. */
89 int isa;
90 };
91
92 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
93 extern const char *current_function_file; /* filename current function is in */
94 extern int num_source_filenames; /* current .file # */
95 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
96 extern int sym_lineno; /* sgi next label # for each stmt */
97 extern int set_noreorder; /* # of nested .set noreorder's */
98 extern int set_nomacro; /* # of nested .set nomacro's */
99 extern int set_noat; /* # of nested .set noat's */
100 extern int set_volatile; /* # of nested .set volatile's */
101 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
102 extern int mips_dbx_regno[]; /* Map register # to debug register # */
103 extern GTY(()) rtx cmp_operands[2];
104 extern enum processor_type mips_arch; /* which cpu to codegen for */
105 extern enum processor_type mips_tune; /* which cpu to schedule for */
106 extern int mips_isa; /* architectural level */
107 extern int mips_abi; /* which ABI to use */
108 extern int mips16_hard_float; /* mips16 without -msoft-float */
109 extern const char *mips_arch_string; /* for -march=<xxx> */
110 extern const char *mips_tune_string; /* for -mtune=<xxx> */
111 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
112 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
113 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
114 extern const struct mips_cpu_info mips_cpu_info_table[];
115 extern const struct mips_cpu_info *mips_arch_info;
116 extern const struct mips_cpu_info *mips_tune_info;
117
118 /* Macros to silence warnings about numbers being signed in traditional
119 C and unsigned in ISO C when compiled on 32-bit hosts. */
120
121 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
122 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
123 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
124
125 \f
126 /* Run-time compilation parameters selecting different hardware subsets. */
127
128 /* Macros used in the machine description to test the flags. */
129
130 /* Bits for real switches */
131 #define MASK_INT64 0x00000001 /* ints are 64 bits */
132 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
133 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
134 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
135 multiply-add operations. */
136 #define MASK_EXPLICIT_RELOCS 0x00000010 /* Use relocation operators. */
137 #define MASK_MEMCPY 0x00000020 /* call memcpy instead of inline code*/
138 #define MASK_SOFT_FLOAT 0x00000040 /* software floating point */
139 #define MASK_FLOAT64 0x00000080 /* fp registers are 64 bits */
140 #define MASK_ABICALLS 0x00000100 /* emit .abicalls/.cprestore/.cpload */
141 #define MASK_XGOT 0x00000200 /* emit big-got PIC */
142 #define MASK_LONG_CALLS 0x00000400 /* Always call through a register */
143 #define MASK_64BIT 0x00000800 /* Use 64 bit GP registers and insns */
144 #define MASK_EMBEDDED_DATA 0x00001000 /* Reduce RAM usage, not fast code */
145 #define MASK_BIG_ENDIAN 0x00002000 /* Generate big endian code */
146 #define MASK_SINGLE_FLOAT 0x00004000 /* Only single precision FPU. */
147 #define MASK_MAD 0x00008000 /* Generate mad/madu as on 4650. */
148 #define MASK_4300_MUL_FIX 0x00010000 /* Work-around early Vr4300 CPU bug */
149 #define MASK_MIPS16 0x00020000 /* Generate mips16 code */
150 #define MASK_NO_CHECK_ZERO_DIV \
151 0x00040000 /* divide by zero checking */
152 #define MASK_BRANCHLIKELY 0x00080000 /* Generate Branch Likely
153 instructions. */
154 #define MASK_UNINIT_CONST_IN_RODATA \
155 0x00100000 /* Store uninitialized
156 consts in rodata */
157 #define MASK_FIX_R4000 0x00200000 /* Work around R4000 errata. */
158 #define MASK_FIX_R4400 0x00400000 /* Work around R4400 errata. */
159 #define MASK_FIX_SB1 0x00800000 /* Work around SB-1 errata. */
160 #define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */
161 #define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
162 #define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
163 #define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses
164 break instead of trap. */
165 #define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
166 #define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
167
168 /* Debug switches, not documented */
169 #define MASK_DEBUG 0 /* unused */
170 #define MASK_DEBUG_D 0 /* don't do define_split's */
171
172 /* Dummy switches used only in specs */
173 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
174
175 /* r4000 64 bit sizes */
176 #define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
177 #define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
178 #define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
179 #define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
180
181 /* Mips vs. GNU linker */
182 #define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
183
184 /* Debug Modes */
185 #define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
186 #define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
187
188 /* call memcpy instead of inline code */
189 #define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
190
191 /* .abicalls, etc from Pyramid V.4 */
192 #define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
193 #define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
194
195 /* software floating point */
196 #define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
197 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
198
199 /* always call through a register */
200 #define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
201
202 /* for embedded systems, optimize for
203 reduced RAM space instead of for
204 fastest code. */
205 #define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
206
207 /* always store uninitialized const
208 variables in rodata, requires
209 TARGET_EMBEDDED_DATA. */
210 #define TARGET_UNINIT_CONST_IN_RODATA \
211 ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
212
213 /* generate big endian code. */
214 #define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
215
216 #define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
217 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
218
219 #define TARGET_MAD ((target_flags & MASK_MAD) != 0)
220
221 #define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
222
223 #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
224
225 #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
226 #define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
227
228 #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
229
230 #define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
231
232 /* Work around R4000 errata. */
233 #define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
234
235 /* Work around R4400 errata. */
236 #define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
237 #define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
238 #define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
239
240 #define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
241
242 #define TARGET_PAIRED_SINGLE_FLOAT \
243 ((target_flags & MASK_PAIRED_SINGLE) != 0)
244 #define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
245
246 /* True if we should use NewABI-style relocation operators for
247 symbolic addresses. This is never true for mips16 code,
248 which has its own conventions. */
249
250 #define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
251
252
253 /* True if the call patterns should be split into a jalr followed by
254 an instruction to restore $gp. This is only ever true for SVR4 PIC,
255 in which $gp is call-clobbered. It is only safe to split the load
256 from the call when every use of $gp is explicit. */
257
258 #define TARGET_SPLIT_CALLS \
259 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
260
261 /* True if we can optimize sibling calls. For simplicity, we only
262 handle cases in which call_insn_operand will reject invalid
263 sibcall addresses. There are two cases in which this isn't true:
264
265 - TARGET_MIPS16. call_insn_operand accepts constant addresses
266 but there is no direct jump instruction. It isn't worth
267 using sibling calls in this case anyway; they would usually
268 be longer than normal calls.
269
270 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
271 accepts global constants, but "jr $25" is the only allowed
272 sibcall. */
273
274 #define TARGET_SIBCALLS \
275 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
276
277 /* True if .gpword or .gpdword should be used for switch tables.
278
279 Although GAS does understand .gpdword, the SGI linker mishandles
280 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
281 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
282 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
283
284 /* Generate mips16 code */
285 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
286
287 /* Generic ISA defines. */
288 #define ISA_MIPS1 (mips_isa == 1)
289 #define ISA_MIPS2 (mips_isa == 2)
290 #define ISA_MIPS3 (mips_isa == 3)
291 #define ISA_MIPS4 (mips_isa == 4)
292 #define ISA_MIPS32 (mips_isa == 32)
293 #define ISA_MIPS32R2 (mips_isa == 33)
294 #define ISA_MIPS64 (mips_isa == 64)
295
296 /* Architecture target defines. */
297 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
298 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
299 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
300 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
301 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
302 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
303 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
304 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
305 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
306 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
307
308 /* Scheduling target defines. */
309 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
310 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
311 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
312 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
313 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
314 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
315 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
316 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
317 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
318 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
319 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
320 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
321
322 /* True if the pre-reload scheduler should try to create chains of
323 multiply-add or multiply-subtract instructions. For example,
324 suppose we have:
325
326 t1 = a * b
327 t2 = t1 + c * d
328 t3 = e * f
329 t4 = t3 - g * h
330
331 t1 will have a higher priority than t2 and t3 will have a higher
332 priority than t4. However, before reload, there is no dependence
333 between t1 and t3, and they can often have similar priorities.
334 The scheduler will then tend to prefer:
335
336 t1 = a * b
337 t3 = e * f
338 t2 = t1 + c * d
339 t4 = t3 - g * h
340
341 which stops us from making full use of macc/madd-style instructions.
342 This sort of situation occurs frequently in Fourier transforms and
343 in unrolled loops.
344
345 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
346 queue so that chained multiply-add and multiply-subtract instructions
347 appear ahead of any other instruction that is likely to clobber lo.
348 In the example above, if t2 and t3 become ready at the same time,
349 the code ensures that t2 is scheduled first.
350
351 Multiply-accumulate instructions are a bigger win for some targets
352 than others, so this macro is defined on an opt-in basis. */
353 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
354 || TUNE_MIPS4120 \
355 || TUNE_MIPS4130)
356
357 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
358 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
359
360 /* IRIX specific stuff. */
361 #define TARGET_IRIX 0
362 #define TARGET_IRIX6 0
363
364 /* Define preprocessor macros for the -march and -mtune options.
365 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
366 processor. If INFO's canonical name is "foo", define PREFIX to
367 be "foo", and define an additional macro PREFIX_FOO. */
368 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
369 do \
370 { \
371 char *macro, *p; \
372 \
373 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
374 for (p = macro; *p != 0; p++) \
375 *p = TOUPPER (*p); \
376 \
377 builtin_define (macro); \
378 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
379 free (macro); \
380 } \
381 while (0)
382
383 /* Target CPU builtins. */
384 #define TARGET_CPU_CPP_BUILTINS() \
385 do \
386 { \
387 /* Everyone but IRIX defines this to mips. */ \
388 if (!TARGET_IRIX) \
389 builtin_assert ("machine=mips"); \
390 \
391 builtin_assert ("cpu=mips"); \
392 builtin_define ("__mips__"); \
393 builtin_define ("_mips"); \
394 \
395 /* We do this here because __mips is defined below \
396 and so we can't use builtin_define_std. */ \
397 if (!flag_iso) \
398 builtin_define ("mips"); \
399 \
400 if (TARGET_64BIT) \
401 builtin_define ("__mips64"); \
402 \
403 if (!TARGET_IRIX) \
404 { \
405 /* Treat _R3000 and _R4000 like register-size \
406 defines, which is how they've historically \
407 been used. */ \
408 if (TARGET_64BIT) \
409 { \
410 builtin_define_std ("R4000"); \
411 builtin_define ("_R4000"); \
412 } \
413 else \
414 { \
415 builtin_define_std ("R3000"); \
416 builtin_define ("_R3000"); \
417 } \
418 } \
419 if (TARGET_FLOAT64) \
420 builtin_define ("__mips_fpr=64"); \
421 else \
422 builtin_define ("__mips_fpr=32"); \
423 \
424 if (TARGET_MIPS16) \
425 builtin_define ("__mips16"); \
426 \
427 if (TARGET_MIPS3D) \
428 builtin_define ("__mips3d"); \
429 \
430 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
431 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
432 \
433 if (ISA_MIPS1) \
434 { \
435 builtin_define ("__mips=1"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
437 } \
438 else if (ISA_MIPS2) \
439 { \
440 builtin_define ("__mips=2"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
442 } \
443 else if (ISA_MIPS3) \
444 { \
445 builtin_define ("__mips=3"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
447 } \
448 else if (ISA_MIPS4) \
449 { \
450 builtin_define ("__mips=4"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
452 } \
453 else if (ISA_MIPS32) \
454 { \
455 builtin_define ("__mips=32"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
458 } \
459 else if (ISA_MIPS32R2) \
460 { \
461 builtin_define ("__mips=32"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
464 } \
465 else if (ISA_MIPS64) \
466 { \
467 builtin_define ("__mips=64"); \
468 builtin_define ("__mips_isa_rev=1"); \
469 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
470 } \
471 \
472 if (TARGET_HARD_FLOAT) \
473 builtin_define ("__mips_hard_float"); \
474 else if (TARGET_SOFT_FLOAT) \
475 builtin_define ("__mips_soft_float"); \
476 \
477 if (TARGET_SINGLE_FLOAT) \
478 builtin_define ("__mips_single_float"); \
479 \
480 if (TARGET_PAIRED_SINGLE_FLOAT) \
481 builtin_define ("__mips_paired_single_float"); \
482 \
483 if (TARGET_BIG_ENDIAN) \
484 { \
485 builtin_define_std ("MIPSEB"); \
486 builtin_define ("_MIPSEB"); \
487 } \
488 else \
489 { \
490 builtin_define_std ("MIPSEL"); \
491 builtin_define ("_MIPSEL"); \
492 } \
493 \
494 /* Macros dependent on the C dialect. */ \
495 if (preprocessing_asm_p ()) \
496 { \
497 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
498 builtin_define ("_LANGUAGE_ASSEMBLY"); \
499 } \
500 else if (c_dialect_cxx ()) \
501 { \
502 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
503 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
504 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
505 } \
506 else \
507 { \
508 builtin_define_std ("LANGUAGE_C"); \
509 builtin_define ("_LANGUAGE_C"); \
510 } \
511 if (c_dialect_objc ()) \
512 { \
513 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
514 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
515 /* Bizarre, but needed at least for Irix. */ \
516 builtin_define_std ("LANGUAGE_C"); \
517 builtin_define ("_LANGUAGE_C"); \
518 } \
519 \
520 if (mips_abi == ABI_EABI) \
521 builtin_define ("__mips_eabi"); \
522 \
523 } while (0)
524
525
526
527 /* Macro to define tables used to set the flags.
528 This is a list in braces of pairs in braces,
529 each pair being { "NAME", VALUE }
530 where VALUE is the bits to set or minus the bits to clear.
531 An empty string NAME is used to identify the default VALUE. */
532
533 #define TARGET_SWITCHES \
534 { \
535 SUBTARGET_TARGET_SWITCHES \
536 {"int64", MASK_INT64 | MASK_LONG64, \
537 N_("Use 64-bit int type")}, \
538 {"long64", MASK_LONG64, \
539 N_("Use 64-bit long type")}, \
540 {"long32", -(MASK_LONG64 | MASK_INT64), \
541 N_("Use 32-bit long type")}, \
542 {"split-addresses", MASK_SPLIT_ADDR, \
543 N_("Optimize lui/addiu address loads")}, \
544 {"no-split-addresses", -MASK_SPLIT_ADDR, \
545 N_("Don't optimize lui/addiu address loads")}, \
546 {"gas", 0, \
547 N_("Use GNU as (now ignored)")}, \
548 {"gpOPT", 0, \
549 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
550 {"gpopt", 0, \
551 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
552 {"no-gpOPT", 0, \
553 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
554 {"no-gpopt", 0, \
555 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
556 {"stats", 0, \
557 N_("Output compiler statistics (now ignored)")}, \
558 {"no-stats", 0, \
559 N_("Don't output compiler statistics")}, \
560 {"memcpy", MASK_MEMCPY, \
561 N_("Don't optimize block moves")}, \
562 {"no-memcpy", -MASK_MEMCPY, \
563 N_("Optimize block moves")}, \
564 {"mips-tfile", MASK_MIPS_TFILE, \
565 N_("Use mips-tfile asm postpass")}, \
566 {"no-mips-tfile", -MASK_MIPS_TFILE, \
567 N_("Don't use mips-tfile asm postpass")}, \
568 {"soft-float", MASK_SOFT_FLOAT, \
569 N_("Use software floating point")}, \
570 {"hard-float", -MASK_SOFT_FLOAT, \
571 N_("Use hardware floating point")}, \
572 {"fp64", MASK_FLOAT64, \
573 N_("Use 64-bit FP registers")}, \
574 {"fp32", -MASK_FLOAT64, \
575 N_("Use 32-bit FP registers")}, \
576 {"gp64", MASK_64BIT, \
577 N_("Use 64-bit general registers")}, \
578 {"gp32", -MASK_64BIT, \
579 N_("Use 32-bit general registers")}, \
580 {"abicalls", MASK_ABICALLS, \
581 N_("Use Irix PIC")}, \
582 {"no-abicalls", -MASK_ABICALLS, \
583 N_("Don't use Irix PIC")}, \
584 {"long-calls", MASK_LONG_CALLS, \
585 N_("Use indirect calls")}, \
586 {"no-long-calls", -MASK_LONG_CALLS, \
587 N_("Don't use indirect calls")}, \
588 {"embedded-data", MASK_EMBEDDED_DATA, \
589 N_("Use ROM instead of RAM")}, \
590 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
591 N_("Don't use ROM instead of RAM")}, \
592 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
593 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
594 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
595 N_("Don't put uninitialized constants in ROM")}, \
596 {"eb", MASK_BIG_ENDIAN, \
597 N_("Use big-endian byte order")}, \
598 {"el", -MASK_BIG_ENDIAN, \
599 N_("Use little-endian byte order")}, \
600 {"single-float", MASK_SINGLE_FLOAT, \
601 N_("Use single (32-bit) FP only")}, \
602 {"double-float", -MASK_SINGLE_FLOAT, \
603 N_("Don't use single (32-bit) FP only")}, \
604 {"paired-single", MASK_PAIRED_SINGLE, \
605 N_("Use paired-single floating point instructions")}, \
606 {"no-paired-single", -MASK_PAIRED_SINGLE, \
607 N_("Use paired-single floating point instructions")}, \
608 {"ips3d", MASK_MIPS3D, \
609 N_("Use MIPS-3D instructions")}, \
610 {"no-mips3d", -MASK_MIPS3D, \
611 N_("Use MIPS-3D instructions")}, \
612 {"mad", MASK_MAD, \
613 N_("Use multiply accumulate")}, \
614 {"no-mad", -MASK_MAD, \
615 N_("Don't use multiply accumulate")}, \
616 {"no-fused-madd", MASK_NO_FUSED_MADD, \
617 N_("Don't generate fused multiply/add instructions")}, \
618 {"fused-madd", -MASK_NO_FUSED_MADD, \
619 N_("Generate fused multiply/add instructions")}, \
620 {"vr4130-align", MASK_VR4130_ALIGN, \
621 N_("Perform VR4130-specific alignment optimizations")}, \
622 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
623 N_("Don't perform VR4130-specific alignment optimizations")}, \
624 {"fix4300", MASK_4300_MUL_FIX, \
625 N_("Work around early 4300 hardware bug")}, \
626 {"no-fix4300", -MASK_4300_MUL_FIX, \
627 N_("Don't work around early 4300 hardware bug")}, \
628 {"fix-sb1", MASK_FIX_SB1, \
629 N_("Work around errata for early SB-1 revision 2 cores")}, \
630 {"no-fix-sb1", -MASK_FIX_SB1, \
631 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
632 {"fix-r4000", MASK_FIX_R4000, \
633 N_("Work around R4000 errata")}, \
634 {"no-fix-r4000", -MASK_FIX_R4000, \
635 N_("Don't work around R4000 errata")}, \
636 {"fix-r4400", MASK_FIX_R4400, \
637 N_("Work around R4400 errata")}, \
638 {"no-fix-r4400", -MASK_FIX_R4400, \
639 N_("Don't work around R4400 errata")}, \
640 {"fix-vr4120", MASK_FIX_VR4120, \
641 N_("Work around certain VR4120 errata")}, \
642 {"no-fix-vr4120", -MASK_FIX_VR4120, \
643 N_("Don't work around certain VR4120 errata")}, \
644 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
645 N_("Trap on integer divide by zero")}, \
646 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
647 N_("Don't trap on integer divide by zero")}, \
648 {"divide-traps", -MASK_DIVIDE_BREAKS, \
649 N_("Use trap to check for integer divide by zero")}, \
650 {"divide-breaks", MASK_DIVIDE_BREAKS, \
651 N_("Use break to check for integer divide by zero")}, \
652 { "branch-likely", MASK_BRANCHLIKELY, \
653 N_("Use Branch Likely instructions, overriding default for arch")}, \
654 { "no-branch-likely", -MASK_BRANCHLIKELY, \
655 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
656 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
657 N_("Use NewABI-style %reloc() assembly operators")}, \
658 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
659 N_("Use assembler macros instead of relocation operators")}, \
660 {"ips16", MASK_MIPS16, \
661 N_("Generate mips16 code") }, \
662 {"no-mips16", -MASK_MIPS16, \
663 N_("Generate normal-mode code") }, \
664 {"xgot", MASK_XGOT, \
665 N_("Lift restrictions on GOT size") }, \
666 {"no-xgot", -MASK_XGOT, \
667 N_("Do not lift restrictions on GOT size") }, \
668 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
669 N_("FP exceptions are enabled") }, \
670 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
671 N_("FP exceptions are not enabled") }, \
672 {"debug", MASK_DEBUG, \
673 NULL}, \
674 {"debugd", MASK_DEBUG_D, \
675 NULL}, \
676 {"", (TARGET_DEFAULT \
677 | TARGET_CPU_DEFAULT \
678 | TARGET_ENDIAN_DEFAULT \
679 | TARGET_FP_EXCEPTIONS_DEFAULT), \
680 NULL}, \
681 }
682
683 /* Default target_flags if no switches are specified */
684
685 #ifndef TARGET_DEFAULT
686 #define TARGET_DEFAULT 0
687 #endif
688
689 #ifndef TARGET_CPU_DEFAULT
690 #define TARGET_CPU_DEFAULT 0
691 #endif
692
693 #ifndef TARGET_ENDIAN_DEFAULT
694 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
695 #endif
696
697 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
698 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
699 #endif
700
701 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
702 #ifndef MIPS_ISA_DEFAULT
703 #ifndef MIPS_CPU_STRING_DEFAULT
704 #define MIPS_CPU_STRING_DEFAULT "from-abi"
705 #endif
706 #endif
707
708 #ifdef IN_LIBGCC2
709 #undef TARGET_64BIT
710 /* Make this compile time constant for libgcc2 */
711 #ifdef __mips64
712 #define TARGET_64BIT 1
713 #else
714 #define TARGET_64BIT 0
715 #endif
716 #endif /* IN_LIBGCC2 */
717
718 #ifndef MULTILIB_ENDIAN_DEFAULT
719 #if TARGET_ENDIAN_DEFAULT == 0
720 #define MULTILIB_ENDIAN_DEFAULT "EL"
721 #else
722 #define MULTILIB_ENDIAN_DEFAULT "EB"
723 #endif
724 #endif
725
726 #ifndef MULTILIB_ISA_DEFAULT
727 # if MIPS_ISA_DEFAULT == 1
728 # define MULTILIB_ISA_DEFAULT "mips1"
729 # else
730 # if MIPS_ISA_DEFAULT == 2
731 # define MULTILIB_ISA_DEFAULT "mips2"
732 # else
733 # if MIPS_ISA_DEFAULT == 3
734 # define MULTILIB_ISA_DEFAULT "mips3"
735 # else
736 # if MIPS_ISA_DEFAULT == 4
737 # define MULTILIB_ISA_DEFAULT "mips4"
738 # else
739 # if MIPS_ISA_DEFAULT == 32
740 # define MULTILIB_ISA_DEFAULT "mips32"
741 # else
742 # if MIPS_ISA_DEFAULT == 33
743 # define MULTILIB_ISA_DEFAULT "mips32r2"
744 # else
745 # if MIPS_ISA_DEFAULT == 64
746 # define MULTILIB_ISA_DEFAULT "mips64"
747 # else
748 # define MULTILIB_ISA_DEFAULT "mips1"
749 # endif
750 # endif
751 # endif
752 # endif
753 # endif
754 # endif
755 # endif
756 #endif
757
758 #ifndef MULTILIB_DEFAULTS
759 #define MULTILIB_DEFAULTS \
760 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
761 #endif
762
763 /* We must pass -EL to the linker by default for little endian embedded
764 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
765 linker will default to using big-endian output files. The OUTPUT_FORMAT
766 line must be in the linker script, otherwise -EB/-EL will not work. */
767
768 #ifndef ENDIAN_SPEC
769 #if TARGET_ENDIAN_DEFAULT == 0
770 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
771 #else
772 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
773 #endif
774 #endif
775
776 #define TARGET_OPTIONS \
777 { \
778 SUBTARGET_TARGET_OPTIONS \
779 { "tune=", &mips_tune_string, \
780 N_("Specify CPU for scheduling purposes"), 0}, \
781 { "arch=", &mips_arch_string, \
782 N_("Specify CPU for code generation purposes"), 0}, \
783 { "abi=", &mips_abi_string, \
784 N_("Specify an ABI"), 0}, \
785 { "ips", &mips_isa_string, \
786 N_("Specify a Standard MIPS ISA"), 0}, \
787 { "no-flush-func", &mips_cache_flush_func, \
788 N_("Don't call any cache flush functions"), 0}, \
789 { "flush-func=", &mips_cache_flush_func, \
790 N_("Specify cache flush function"), 0}, \
791 }
792
793 /* This is meant to be redefined in the host dependent files. */
794 #define SUBTARGET_TARGET_OPTIONS
795
796 /* Support for a compile-time default CPU, et cetera. The rules are:
797 --with-arch is ignored if -march is specified or a -mips is specified
798 (other than -mips16).
799 --with-tune is ignored if -mtune is specified.
800 --with-abi is ignored if -mabi is specified.
801 --with-float is ignored if -mhard-float or -msoft-float are
802 specified.
803 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
804 specified. */
805 #define OPTION_DEFAULT_SPECS \
806 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
807 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
808 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
809 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
810 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
811
812
813 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
814 && ISA_HAS_COND_TRAP)
815
816 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
817 && !TARGET_SR71K \
818 && !TARGET_MIPS16)
819
820 /* Generate three-operand multiply instructions for SImode. */
821 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
822 || TARGET_MIPS5400 \
823 || TARGET_MIPS5500 \
824 || TARGET_MIPS7000 \
825 || TARGET_MIPS9000 \
826 || TARGET_MAD \
827 || ISA_MIPS32 \
828 || ISA_MIPS32R2 \
829 || ISA_MIPS64) \
830 && !TARGET_MIPS16)
831
832 /* Generate three-operand multiply instructions for DImode. */
833 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
834 && !TARGET_MIPS16)
835
836 /* True if the ABI can only work with 64-bit integer registers. We
837 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
838 otherwise floating-point registers must also be 64-bit. */
839 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
840
841 /* Likewise for 32-bit regs. */
842 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
843
844 /* True if symbols are 64 bits wide. At present, n64 is the only
845 ABI for which this is true. */
846 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
847
848 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
849 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
850 || ISA_MIPS4 \
851 || ISA_MIPS64)
852
853 /* ISA has branch likely instructions (e.g. mips2). */
854 /* Disable branchlikely for tx39 until compare rewrite. They haven't
855 been generated up to this point. */
856 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
857
858 /* ISA has the conditional move instructions introduced in mips4. */
859 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
860 || ISA_MIPS32 \
861 || ISA_MIPS32R2 \
862 || ISA_MIPS64) \
863 && !TARGET_MIPS5500 \
864 && !TARGET_MIPS16)
865
866 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
867 branch on CC, and move (both FP and non-FP) on CC. */
868 #define ISA_HAS_8CC (ISA_MIPS4 \
869 || ISA_MIPS32 \
870 || ISA_MIPS32R2 \
871 || ISA_MIPS64)
872
873 /* This is a catch all for other mips4 instructions: indexed load, the
874 FP madd and msub instructions, and the FP recip and recip sqrt
875 instructions. */
876 #define ISA_HAS_FP4 ((ISA_MIPS4 \
877 || ISA_MIPS64) \
878 && !TARGET_MIPS16)
879
880 /* ISA has conditional trap instructions. */
881 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
882 && !TARGET_MIPS16)
883
884 /* ISA has integer multiply-accumulate instructions, madd and msub. */
885 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
886 || ISA_MIPS32R2 \
887 || ISA_MIPS64 \
888 ) && !TARGET_MIPS16)
889
890 /* ISA has floating-point nmadd and nmsub instructions. */
891 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
892 || ISA_MIPS64) \
893 && (!TARGET_MIPS5400 || TARGET_MAD) \
894 && ! TARGET_MIPS16)
895
896 /* ISA has count leading zeroes/ones instruction (not implemented). */
897 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
898 || ISA_MIPS32R2 \
899 || ISA_MIPS64 \
900 ) && !TARGET_MIPS16)
901
902 /* ISA has double-word count leading zeroes/ones instruction (not
903 implemented). */
904 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
905 && !TARGET_MIPS16)
906
907 /* ISA has three operand multiply instructions that put
908 the high part in an accumulator: mulhi or mulhiu. */
909 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
910 || TARGET_MIPS5500 \
911 || TARGET_SR71K \
912 )
913
914 /* ISA has three operand multiply instructions that
915 negates the result and puts the result in an accumulator. */
916 #define ISA_HAS_MULS (TARGET_MIPS5400 \
917 || TARGET_MIPS5500 \
918 || TARGET_SR71K \
919 )
920
921 /* ISA has three operand multiply instructions that subtracts the
922 result from a 4th operand and puts the result in an accumulator. */
923 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
924 || TARGET_MIPS5500 \
925 || TARGET_SR71K \
926 )
927 /* ISA has three operand multiply instructions that the result
928 from a 4th operand and puts the result in an accumulator. */
929 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
930 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
931 || TARGET_MIPS5400 \
932 || TARGET_MIPS5500 \
933 || TARGET_SR71K \
934 )
935
936 /* ISA has 32-bit rotate right instruction. */
937 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
938 && (ISA_MIPS32R2 \
939 || TARGET_MIPS5400 \
940 || TARGET_MIPS5500 \
941 || TARGET_SR71K \
942 ))
943
944 /* ISA has 64-bit rotate right instruction. */
945 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
946 && !TARGET_MIPS16 \
947 && (TARGET_MIPS5400 \
948 || TARGET_MIPS5500 \
949 || TARGET_SR71K \
950 ))
951
952 /* ISA has data prefetch instructions. This controls use of 'pref'. */
953 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
954 || ISA_MIPS32 \
955 || ISA_MIPS32R2 \
956 || ISA_MIPS64) \
957 && !TARGET_MIPS16)
958
959 /* ISA has data indexed prefetch instructions. This controls use of
960 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
961 (prefx is a cop1x instruction, so can only be used if FP is
962 enabled.) */
963 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
964 || ISA_MIPS64) \
965 && !TARGET_MIPS16)
966
967 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
968 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
969 also requires TARGET_DOUBLE_FLOAT. */
970 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
971
972 /* ISA includes the MIPS32r2 seb and seh instructions. */
973 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
974 && (ISA_MIPS32R2 \
975 ))
976
977 /* True if the result of a load is not available to the next instruction.
978 A nop will then be needed between instructions like "lw $4,..."
979 and "addiu $4,$4,1". */
980 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
981 && !TARGET_MIPS3900 \
982 && !TARGET_MIPS16)
983
984 /* Likewise mtc1 and mfc1. */
985 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
986
987 /* Likewise floating-point comparisons. */
988 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
989
990 /* True if mflo and mfhi can be immediately followed by instructions
991 which write to the HI and LO registers.
992
993 According to MIPS specifications, MIPS ISAs I, II, and III need
994 (at least) two instructions between the reads of HI/LO and
995 instructions which write them, and later ISAs do not. Contradicting
996 the MIPS specifications, some MIPS IV processor user manuals (e.g.
997 the UM for the NEC Vr5000) document needing the instructions between
998 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
999 MIPS64 and later ISAs to have the interlocks, plus any specific
1000 earlier-ISA CPUs for which CPU documentation declares that the
1001 instructions are really interlocked. */
1002 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1003 || ISA_MIPS32R2 \
1004 || ISA_MIPS64 \
1005 || TARGET_MIPS5500)
1006 \f
1007 /* Add -G xx support. */
1008
1009 #undef SWITCH_TAKES_ARG
1010 #define SWITCH_TAKES_ARG(CHAR) \
1011 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1012
1013 #define OVERRIDE_OPTIONS override_options ()
1014
1015 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1016
1017 /* Show we can debug even without a frame pointer. */
1018 #define CAN_DEBUG_WITHOUT_FP
1019 \f
1020 /* Tell collect what flags to pass to nm. */
1021 #ifndef NM_FLAGS
1022 #define NM_FLAGS "-Bn"
1023 #endif
1024
1025 \f
1026 #define SUBTARGET_TARGET_SWITCHES
1027
1028 #ifndef MIPS_ABI_DEFAULT
1029 #define MIPS_ABI_DEFAULT ABI_32
1030 #endif
1031
1032 /* Use the most portable ABI flag for the ASM specs. */
1033
1034 #if MIPS_ABI_DEFAULT == ABI_32
1035 #define MULTILIB_ABI_DEFAULT "mabi=32"
1036 #endif
1037
1038 #if MIPS_ABI_DEFAULT == ABI_O64
1039 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1040 #endif
1041
1042 #if MIPS_ABI_DEFAULT == ABI_N32
1043 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1044 #endif
1045
1046 #if MIPS_ABI_DEFAULT == ABI_64
1047 #define MULTILIB_ABI_DEFAULT "mabi=64"
1048 #endif
1049
1050 #if MIPS_ABI_DEFAULT == ABI_EABI
1051 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1052 #endif
1053
1054 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1055 to the assembler. It may be overridden by subtargets. */
1056 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1057 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1058 %{noasmopt:-O0} \
1059 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1060 #endif
1061
1062 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1063 the assembler. It may be overridden by subtargets.
1064
1065 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1066 COFF debugging info. */
1067
1068 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1069 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1070 %{g} %{g0} %{g1} %{g2} %{g3} \
1071 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1072 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1073 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1074 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1075 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1076 #endif
1077
1078 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1079 overridden by subtargets. */
1080
1081 #ifndef SUBTARGET_ASM_SPEC
1082 #define SUBTARGET_ASM_SPEC ""
1083 #endif
1084
1085 #undef ASM_SPEC
1086 #define ASM_SPEC "\
1087 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1088 %{mips32} %{mips32r2} %{mips64} \
1089 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1090 %{mips3d:-mips3d} \
1091 %{mfix-vr4120} \
1092 %(subtarget_asm_optimizing_spec) \
1093 %(subtarget_asm_debugging_spec) \
1094 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1095 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1096 %{mtune=*} %{v} \
1097 %(subtarget_asm_spec)"
1098
1099 /* Extra switches sometimes passed to the linker. */
1100 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1101 will interpret it as a -b option. */
1102
1103 #ifndef LINK_SPEC
1104 #define LINK_SPEC "\
1105 %(endian_spec) \
1106 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1107 %{bestGnum} %{shared} %{non_shared}"
1108 #endif /* LINK_SPEC defined */
1109
1110
1111 /* Specs for the compiler proper */
1112
1113 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1114 overridden by subtargets. */
1115 #ifndef SUBTARGET_CC1_SPEC
1116 #define SUBTARGET_CC1_SPEC ""
1117 #endif
1118
1119 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1120
1121 #ifndef CC1_SPEC
1122 #define CC1_SPEC "\
1123 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1124 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1125 %{save-temps: } \
1126 %(subtarget_cc1_spec)"
1127 #endif
1128
1129 /* Preprocessor specs. */
1130
1131 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1132 overridden by subtargets. */
1133 #ifndef SUBTARGET_CPP_SPEC
1134 #define SUBTARGET_CPP_SPEC ""
1135 #endif
1136
1137 #define CPP_SPEC "%(subtarget_cpp_spec)"
1138
1139 /* This macro defines names of additional specifications to put in the specs
1140 that can be used in various specifications like CC1_SPEC. Its definition
1141 is an initializer with a subgrouping for each command option.
1142
1143 Each subgrouping contains a string constant, that defines the
1144 specification name, and a string constant that used by the GCC driver
1145 program.
1146
1147 Do not define this macro if it does not need to do anything. */
1148
1149 #define EXTRA_SPECS \
1150 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1151 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1152 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1153 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1154 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1155 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1156 { "endian_spec", ENDIAN_SPEC }, \
1157 SUBTARGET_EXTRA_SPECS
1158
1159 #ifndef SUBTARGET_EXTRA_SPECS
1160 #define SUBTARGET_EXTRA_SPECS
1161 #endif
1162 \f
1163 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1164 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1165 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1166
1167 #ifndef PREFERRED_DEBUGGING_TYPE
1168 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1169 #endif
1170
1171 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1172
1173 /* By default, turn on GDB extensions. */
1174 #define DEFAULT_GDB_EXTENSIONS 1
1175
1176 /* Local compiler-generated symbols must have a prefix that the assembler
1177 understands. By default, this is $, although some targets (e.g.,
1178 NetBSD-ELF) need to override this. */
1179
1180 #ifndef LOCAL_LABEL_PREFIX
1181 #define LOCAL_LABEL_PREFIX "$"
1182 #endif
1183
1184 /* By default on the mips, external symbols do not have an underscore
1185 prepended, but some targets (e.g., NetBSD) require this. */
1186
1187 #ifndef USER_LABEL_PREFIX
1188 #define USER_LABEL_PREFIX ""
1189 #endif
1190
1191 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1192 since the length can run past this up to a continuation point. */
1193 #undef DBX_CONTIN_LENGTH
1194 #define DBX_CONTIN_LENGTH 1500
1195
1196 /* How to renumber registers for dbx and gdb. */
1197 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1198
1199 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1200 #define DWARF_FRAME_REGNUM(REG) (REG)
1201
1202 /* The DWARF 2 CFA column which tracks the return address. */
1203 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1204
1205 /* The DWARF 2 CFA column which tracks the return address from a
1206 signal handler context. */
1207 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1208
1209 /* Before the prologue, RA lives in r31. */
1210 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1211
1212 /* Describe how we implement __builtin_eh_return. */
1213 #define EH_RETURN_DATA_REGNO(N) \
1214 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1215
1216 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1217
1218 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1219 The default for this in 64-bit mode is 8, which causes problems with
1220 SFmode register saves. */
1221 #define DWARF_CIE_DATA_ALIGNMENT 4
1222
1223 /* Correct the offset of automatic variables and arguments. Note that
1224 the MIPS debug format wants all automatic variables and arguments
1225 to be in terms of the virtual frame pointer (stack pointer before
1226 any adjustment in the function), while the MIPS 3.0 linker wants
1227 the frame pointer to be the stack pointer after the initial
1228 adjustment. */
1229
1230 #define DEBUGGER_AUTO_OFFSET(X) \
1231 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1232 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1233 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1234 \f
1235 /* Target machine storage layout */
1236
1237 #define BITS_BIG_ENDIAN 0
1238 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1239 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1240
1241 /* Define this to set the endianness to use in libgcc2.c, which can
1242 not depend on target_flags. */
1243 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1244 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1245 #else
1246 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1247 #endif
1248
1249 #define MAX_BITS_PER_WORD 64
1250
1251 /* Width of a word, in units (bytes). */
1252 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1253 #define MIN_UNITS_PER_WORD 4
1254
1255 /* For MIPS, width of a floating point register. */
1256 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1257
1258 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1259 the next available register. */
1260 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1261
1262 /* The largest size of value that can be held in floating-point
1263 registers and moved with a single instruction. */
1264 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1265
1266 /* The largest size of value that can be held in floating-point
1267 registers. */
1268 #define UNITS_PER_FPVALUE \
1269 (TARGET_SOFT_FLOAT ? 0 \
1270 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1271 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1272
1273 /* The number of bytes in a double. */
1274 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1275
1276 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : 0)
1277
1278 /* Set the sizes of the core types. */
1279 #define SHORT_TYPE_SIZE 16
1280 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1281 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1282 #define LONG_LONG_TYPE_SIZE 64
1283
1284 #define FLOAT_TYPE_SIZE 32
1285 #define DOUBLE_TYPE_SIZE 64
1286 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1287
1288 /* long double is not a fixed mode, but the idea is that, if we
1289 support long double, we also want a 128-bit integer type. */
1290 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1291
1292 #ifdef IN_LIBGCC2
1293 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1294 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1295 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1296 # else
1297 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1298 # endif
1299 #endif
1300
1301 /* Width in bits of a pointer. */
1302 #ifndef POINTER_SIZE
1303 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1304 #endif
1305
1306 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1307 #define PARM_BOUNDARY BITS_PER_WORD
1308
1309 /* Allocation boundary (in *bits*) for the code of a function. */
1310 #define FUNCTION_BOUNDARY 32
1311
1312 /* Alignment of field after `int : 0' in a structure. */
1313 #define EMPTY_FIELD_BOUNDARY 32
1314
1315 /* Every structure's size must be a multiple of this. */
1316 /* 8 is observed right on a DECstation and on riscos 4.02. */
1317 #define STRUCTURE_SIZE_BOUNDARY 8
1318
1319 /* There is no point aligning anything to a rounder boundary than this. */
1320 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1321
1322 /* All accesses must be aligned. */
1323 #define STRICT_ALIGNMENT 1
1324
1325 /* Define this if you wish to imitate the way many other C compilers
1326 handle alignment of bitfields and the structures that contain
1327 them.
1328
1329 The behavior is that the type written for a bit-field (`int',
1330 `short', or other integer type) imposes an alignment for the
1331 entire structure, as if the structure really did contain an
1332 ordinary field of that type. In addition, the bit-field is placed
1333 within the structure so that it would fit within such a field,
1334 not crossing a boundary for it.
1335
1336 Thus, on most machines, a bit-field whose type is written as `int'
1337 would not cross a four-byte boundary, and would force four-byte
1338 alignment for the whole structure. (The alignment used may not
1339 be four bytes; it is controlled by the other alignment
1340 parameters.)
1341
1342 If the macro is defined, its definition should be a C expression;
1343 a nonzero value for the expression enables this behavior. */
1344
1345 #define PCC_BITFIELD_TYPE_MATTERS 1
1346
1347 /* If defined, a C expression to compute the alignment given to a
1348 constant that is being placed in memory. CONSTANT is the constant
1349 and ALIGN is the alignment that the object would ordinarily have.
1350 The value of this macro is used instead of that alignment to align
1351 the object.
1352
1353 If this macro is not defined, then ALIGN is used.
1354
1355 The typical use of this macro is to increase alignment for string
1356 constants to be word aligned so that `strcpy' calls that copy
1357 constants can be done inline. */
1358
1359 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1360 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1361 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1362
1363 /* If defined, a C expression to compute the alignment for a static
1364 variable. TYPE is the data type, and ALIGN is the alignment that
1365 the object would ordinarily have. The value of this macro is used
1366 instead of that alignment to align the object.
1367
1368 If this macro is not defined, then ALIGN is used.
1369
1370 One use of this macro is to increase alignment of medium-size
1371 data to make it all fit in fewer cache lines. Another is to
1372 cause character arrays to be word-aligned so that `strcpy' calls
1373 that copy constants to character arrays can be done inline. */
1374
1375 #undef DATA_ALIGNMENT
1376 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1377 ((((ALIGN) < BITS_PER_WORD) \
1378 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1379 || TREE_CODE (TYPE) == UNION_TYPE \
1380 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1381
1382
1383 #define PAD_VARARGS_DOWN \
1384 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1385
1386 /* Define if operations between registers always perform the operation
1387 on the full register even if a narrower mode is specified. */
1388 #define WORD_REGISTER_OPERATIONS
1389
1390 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1391 moves. All other references are zero extended. */
1392 #define LOAD_EXTEND_OP(MODE) \
1393 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1394 ? SIGN_EXTEND : ZERO_EXTEND)
1395
1396 /* Define this macro if it is advisable to hold scalars in registers
1397 in a wider mode than that declared by the program. In such cases,
1398 the value is constrained to be within the bounds of the declared
1399 type, but kept valid in the wider mode. The signedness of the
1400 extension may differ from that of the type. */
1401
1402 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1403 if (GET_MODE_CLASS (MODE) == MODE_INT \
1404 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1405 { \
1406 if ((MODE) == SImode) \
1407 (UNSIGNEDP) = 0; \
1408 (MODE) = Pmode; \
1409 }
1410
1411 /* Define if loading short immediate values into registers sign extends. */
1412 #define SHORT_IMMEDIATES_SIGN_EXTEND
1413 \f
1414 /* Standard register usage. */
1415
1416 /* Number of hardware registers. We have:
1417
1418 - 32 integer registers
1419 - 32 floating point registers
1420 - 8 condition code registers
1421 - 2 accumulator registers (hi and lo)
1422 - 32 registers each for coprocessors 0, 2 and 3
1423 - 3 fake registers:
1424 - ARG_POINTER_REGNUM
1425 - FRAME_POINTER_REGNUM
1426 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1427 - 3 dummy entries that were used at various times in the past. */
1428
1429 #define FIRST_PSEUDO_REGISTER 176
1430
1431 /* By default, fix the kernel registers ($26 and $27), the global
1432 pointer ($28) and the stack pointer ($29). This can change
1433 depending on the command-line options.
1434
1435 Regarding coprocessor registers: without evidence to the contrary,
1436 it's best to assume that each coprocessor register has a unique
1437 use. This can be overridden, in, e.g., override_options() or
1438 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1439 for a particular target. */
1440
1441 #define FIXED_REGISTERS \
1442 { \
1443 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1447 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1448 /* COP0 registers */ \
1449 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1450 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1451 /* COP2 registers */ \
1452 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1453 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1454 /* COP3 registers */ \
1455 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1456 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1457 }
1458
1459
1460 /* Set up this array for o32 by default.
1461
1462 Note that we don't mark $31 as a call-clobbered register. The idea is
1463 that it's really the call instructions themselves which clobber $31.
1464 We don't care what the called function does with it afterwards.
1465
1466 This approach makes it easier to implement sibcalls. Unlike normal
1467 calls, sibcalls don't clobber $31, so the register reaches the
1468 called function in tact. EPILOGUE_USES says that $31 is useful
1469 to the called function. */
1470
1471 #define CALL_USED_REGISTERS \
1472 { \
1473 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1474 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1475 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1476 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1477 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1478 /* COP0 registers */ \
1479 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1480 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1481 /* COP2 registers */ \
1482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1483 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1484 /* COP3 registers */ \
1485 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1487 }
1488
1489
1490 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1491
1492 #define CALL_REALLY_USED_REGISTERS \
1493 { /* General registers. */ \
1494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1495 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1496 /* Floating-point registers. */ \
1497 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1498 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1499 /* Others. */ \
1500 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1501 /* COP0 registers */ \
1502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1504 /* COP2 registers */ \
1505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1507 /* COP3 registers */ \
1508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1510 }
1511
1512 /* Internal macros to classify a register number as to whether it's a
1513 general purpose register, a floating point register, a
1514 multiply/divide register, or a status register. */
1515
1516 #define GP_REG_FIRST 0
1517 #define GP_REG_LAST 31
1518 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1519 #define GP_DBX_FIRST 0
1520
1521 #define FP_REG_FIRST 32
1522 #define FP_REG_LAST 63
1523 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1524 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1525
1526 #define MD_REG_FIRST 64
1527 #define MD_REG_LAST 65
1528 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1529 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1530
1531 #define ST_REG_FIRST 67
1532 #define ST_REG_LAST 74
1533 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1534
1535
1536 /* FIXME: renumber. */
1537 #define COP0_REG_FIRST 80
1538 #define COP0_REG_LAST 111
1539 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1540
1541 #define COP2_REG_FIRST 112
1542 #define COP2_REG_LAST 143
1543 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1544
1545 #define COP3_REG_FIRST 144
1546 #define COP3_REG_LAST 175
1547 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1548 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1549 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1550
1551 #define AT_REGNUM (GP_REG_FIRST + 1)
1552 #define HI_REGNUM (MD_REG_FIRST + 0)
1553 #define LO_REGNUM (MD_REG_FIRST + 1)
1554
1555 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1556 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1557 should be used instead. */
1558 #define FPSW_REGNUM ST_REG_FIRST
1559
1560 #define GP_REG_P(REGNO) \
1561 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1562 #define M16_REG_P(REGNO) \
1563 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1564 #define FP_REG_P(REGNO) \
1565 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1566 #define MD_REG_P(REGNO) \
1567 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1568 #define ST_REG_P(REGNO) \
1569 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1570 #define COP0_REG_P(REGNO) \
1571 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1572 #define COP2_REG_P(REGNO) \
1573 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1574 #define COP3_REG_P(REGNO) \
1575 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1576 #define ALL_COP_REG_P(REGNO) \
1577 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1578
1579 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1580
1581 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1582 to initialize the mips16 gp pseudo register. */
1583 #define CONST_GP_P(X) \
1584 (GET_CODE (X) == CONST \
1585 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1586 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1587
1588 /* Return coprocessor number from register number. */
1589
1590 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1591 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1592 : COP3_REG_P (REGNO) ? '3' : '?')
1593
1594
1595 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1596
1597 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1598 array built in override_options. Because machmodes.h is not yet
1599 included before this file is processed, the MODE bound can't be
1600 expressed here. */
1601
1602 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1603
1604 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1605 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1606
1607 /* Value is 1 if it is a good idea to tie two pseudo registers
1608 when one has mode MODE1 and one has mode MODE2.
1609 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1610 for any hard reg, then this must be 0 for correct output. */
1611 #define MODES_TIEABLE_P(MODE1, MODE2) \
1612 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1613 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1614 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1615 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1616
1617 /* Register to use for pushing function arguments. */
1618 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1619
1620 /* These two registers don't really exist: they get eliminated to either
1621 the stack or hard frame pointer. */
1622 #define ARG_POINTER_REGNUM 77
1623 #define FRAME_POINTER_REGNUM 78
1624
1625 /* $30 is not available on the mips16, so we use $17 as the frame
1626 pointer. */
1627 #define HARD_FRAME_POINTER_REGNUM \
1628 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1629
1630 /* Value should be nonzero if functions must have frame pointers.
1631 Zero means the frame pointer need not be set up (and parms
1632 may be accessed via the stack pointer) in functions that seem suitable.
1633 This is computed in `reload', in reload1.c. */
1634 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1635
1636 /* Register in which static-chain is passed to a function. */
1637 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1638
1639 /* Registers used as temporaries in prologue/epilogue code. If we're
1640 generating mips16 code, these registers must come from the core set
1641 of 8. The prologue register mustn't conflict with any incoming
1642 arguments, the static chain pointer, or the frame pointer. The
1643 epilogue temporary mustn't conflict with the return registers, the
1644 frame pointer, the EH stack adjustment, or the EH data registers. */
1645
1646 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1647 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1648
1649 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1650 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1651
1652 /* Define this macro if it is as good or better to call a constant
1653 function address than to call an address kept in a register. */
1654 #define NO_FUNCTION_CSE 1
1655
1656 /* The ABI-defined global pointer. Sometimes we use a different
1657 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1658 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1659
1660 /* We normally use $28 as the global pointer. However, when generating
1661 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1662 register instead. They can then avoid saving and restoring $28
1663 and perhaps avoid using a frame at all.
1664
1665 When a leaf function uses something other than $28, mips_expand_prologue
1666 will modify pic_offset_table_rtx in place. Take the register number
1667 from there after reload. */
1668 #define PIC_OFFSET_TABLE_REGNUM \
1669 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1670
1671 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1672 \f
1673 /* Define the classes of registers for register constraints in the
1674 machine description. Also define ranges of constants.
1675
1676 One of the classes must always be named ALL_REGS and include all hard regs.
1677 If there is more than one class, another class must be named NO_REGS
1678 and contain no registers.
1679
1680 The name GENERAL_REGS must be the name of a class (or an alias for
1681 another name such as ALL_REGS). This is the class of registers
1682 that is allowed by "g" or "r" in a register constraint.
1683 Also, registers outside this class are allocated only when
1684 instructions express preferences for them.
1685
1686 The classes must be numbered in nondecreasing order; that is,
1687 a larger-numbered class must never be contained completely
1688 in a smaller-numbered class.
1689
1690 For any two classes, it is very desirable that there be another
1691 class that represents their union. */
1692
1693 enum reg_class
1694 {
1695 NO_REGS, /* no registers in set */
1696 M16_NA_REGS, /* mips16 regs not used to pass args */
1697 M16_REGS, /* mips16 directly accessible registers */
1698 T_REG, /* mips16 T register ($24) */
1699 M16_T_REGS, /* mips16 registers plus T register */
1700 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1701 LEA_REGS, /* Every GPR except $25 */
1702 GR_REGS, /* integer registers */
1703 FP_REGS, /* floating point registers */
1704 HI_REG, /* hi register */
1705 LO_REG, /* lo register */
1706 MD_REGS, /* multiply/divide registers (hi/lo) */
1707 COP0_REGS, /* generic coprocessor classes */
1708 COP2_REGS,
1709 COP3_REGS,
1710 HI_AND_GR_REGS, /* union classes */
1711 LO_AND_GR_REGS,
1712 HI_AND_FP_REGS,
1713 COP0_AND_GR_REGS,
1714 COP2_AND_GR_REGS,
1715 COP3_AND_GR_REGS,
1716 ALL_COP_REGS,
1717 ALL_COP_AND_GR_REGS,
1718 ST_REGS, /* status registers (fp status) */
1719 ALL_REGS, /* all registers */
1720 LIM_REG_CLASSES /* max value + 1 */
1721 };
1722
1723 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1724
1725 #define GENERAL_REGS GR_REGS
1726
1727 /* An initializer containing the names of the register classes as C
1728 string constants. These names are used in writing some of the
1729 debugging dumps. */
1730
1731 #define REG_CLASS_NAMES \
1732 { \
1733 "NO_REGS", \
1734 "M16_NA_REGS", \
1735 "M16_REGS", \
1736 "T_REG", \
1737 "M16_T_REGS", \
1738 "PIC_FN_ADDR_REG", \
1739 "LEA_REGS", \
1740 "GR_REGS", \
1741 "FP_REGS", \
1742 "HI_REG", \
1743 "LO_REG", \
1744 "MD_REGS", \
1745 /* coprocessor registers */ \
1746 "COP0_REGS", \
1747 "COP2_REGS", \
1748 "COP3_REGS", \
1749 "HI_AND_GR_REGS", \
1750 "LO_AND_GR_REGS", \
1751 "HI_AND_FP_REGS", \
1752 "COP0_AND_GR_REGS", \
1753 "COP2_AND_GR_REGS", \
1754 "COP3_AND_GR_REGS", \
1755 "ALL_COP_REGS", \
1756 "ALL_COP_AND_GR_REGS", \
1757 "ST_REGS", \
1758 "ALL_REGS" \
1759 }
1760
1761 /* An initializer containing the contents of the register classes,
1762 as integers which are bit masks. The Nth integer specifies the
1763 contents of class N. The way the integer MASK is interpreted is
1764 that register R is in the class if `MASK & (1 << R)' is 1.
1765
1766 When the machine has more than 32 registers, an integer does not
1767 suffice. Then the integers are replaced by sub-initializers,
1768 braced groupings containing several integers. Each
1769 sub-initializer must be suitable as an initializer for the type
1770 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1771
1772 #define REG_CLASS_CONTENTS \
1773 { \
1774 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1775 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1776 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1777 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1778 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1779 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1780 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1781 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1782 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1783 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1784 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1785 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1786 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1787 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1788 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1789 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1790 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1791 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1792 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1793 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1794 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1795 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1796 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1797 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1798 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1799 }
1800
1801
1802 /* A C expression whose value is a register class containing hard
1803 register REGNO. In general there is more that one such class;
1804 choose a class which is "minimal", meaning that no smaller class
1805 also contains the register. */
1806
1807 extern const enum reg_class mips_regno_to_class[];
1808
1809 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1810
1811 /* A macro whose definition is the name of the class to which a
1812 valid base register must belong. A base register is one used in
1813 an address which is the register value plus a displacement. */
1814
1815 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1816
1817 /* A macro whose definition is the name of the class to which a
1818 valid index register must belong. An index register is one used
1819 in an address where its value is either multiplied by a scale
1820 factor or added to another register (as well as added to a
1821 displacement). */
1822
1823 #define INDEX_REG_CLASS NO_REGS
1824
1825 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1826 registers explicitly used in the rtl to be used as spill registers
1827 but prevents the compiler from extending the lifetime of these
1828 registers. */
1829
1830 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1831
1832 /* This macro is used later on in the file. */
1833 #define GR_REG_CLASS_P(CLASS) \
1834 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1835 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1836 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1837
1838 /* This macro is also used later on in the file. */
1839 #define COP_REG_CLASS_P(CLASS) \
1840 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1841
1842 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1843 is the default value (allocate the registers in numeric order). We
1844 define it just so that we can override it for the mips16 target in
1845 ORDER_REGS_FOR_LOCAL_ALLOC. */
1846
1847 #define REG_ALLOC_ORDER \
1848 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1849 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1850 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1851 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1852 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1853 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1854 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1855 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1856 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1857 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1858 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1859 }
1860
1861 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1862 to be rearranged based on a particular function. On the mips16, we
1863 want to allocate $24 (T_REG) before other registers for
1864 instructions for which it is possible. */
1865
1866 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1867
1868 /* REGISTER AND CONSTANT CLASSES */
1869
1870 /* Get reg_class from a letter such as appears in the machine
1871 description.
1872
1873 DEFINED REGISTER CLASSES:
1874
1875 'd' General (aka integer) registers
1876 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1877 'y' General registers (in both mips16 and non mips16 mode)
1878 'e' Effective address registers (general registers except $25)
1879 't' mips16 temporary register ($24)
1880 'f' Floating point registers
1881 'h' Hi register
1882 'l' Lo register
1883 'x' Multiply/divide registers
1884 'z' FP Status register
1885 'B' Cop0 register
1886 'C' Cop2 register
1887 'D' Cop3 register
1888 'b' All registers */
1889
1890 extern enum reg_class mips_char_to_class[256];
1891
1892 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1893
1894 /* True if VALUE is a signed 16-bit number. */
1895
1896 #define SMALL_OPERAND(VALUE) \
1897 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1898
1899 /* True if VALUE is an unsigned 16-bit number. */
1900
1901 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1902 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1903
1904 /* True if VALUE can be loaded into a register using LUI. */
1905
1906 #define LUI_OPERAND(VALUE) \
1907 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1908 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1909
1910 /* Return a value X with the low 16 bits clear, and such that
1911 VALUE - X is a signed 16-bit value. */
1912
1913 #define CONST_HIGH_PART(VALUE) \
1914 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1915
1916 #define CONST_LOW_PART(VALUE) \
1917 ((VALUE) - CONST_HIGH_PART (VALUE))
1918
1919 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1920 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1921 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1922
1923 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1924 string can be used to stand for particular ranges of immediate
1925 operands. This macro defines what the ranges are. C is the
1926 letter, and VALUE is a constant value. Return 1 if VALUE is
1927 in the range specified by C. */
1928
1929 /* For MIPS:
1930
1931 `I' is used for the range of constants an arithmetic insn can
1932 actually contain (16 bits signed integers).
1933
1934 `J' is used for the range which is just zero (i.e., $r0).
1935
1936 `K' is used for the range of constants a logical insn can actually
1937 contain (16 bit zero-extended integers).
1938
1939 `L' is used for the range of constants that be loaded with lui
1940 (i.e., the bottom 16 bits are zero).
1941
1942 `M' is used for the range of constants that take two words to load
1943 (i.e., not matched by `I', `K', and `L').
1944
1945 `N' is used for negative 16 bit constants other than -65536.
1946
1947 `O' is a 15 bit signed integer.
1948
1949 `P' is used for positive 16 bit constants. */
1950
1951 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1952 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1953 : (C) == 'J' ? ((VALUE) == 0) \
1954 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1955 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1956 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1957 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1958 && !LUI_OPERAND (VALUE)) \
1959 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1960 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1961 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1962 : 0)
1963
1964 /* Similar, but for floating constants, and defining letters G and H.
1965 Here VALUE is the CONST_DOUBLE rtx itself. */
1966
1967 /* For Mips
1968
1969 'G' : Floating point 0 */
1970
1971 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1972 ((C) == 'G' \
1973 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1974
1975 /* Letters in the range `Q' through `U' may be defined in a
1976 machine-dependent fashion to stand for arbitrary operand types.
1977 The machine description macro `EXTRA_CONSTRAINT' is passed the
1978 operand as its first argument and the constraint letter as its
1979 second operand.
1980
1981 `Q' is for signed 16-bit constants.
1982 `R' is for single-instruction memory references. Note that this
1983 constraint has often been used in linux and glibc code.
1984 `S' is for legitimate constant call addresses.
1985 `T' is for constant move_operands that cannot be safely loaded into $25.
1986 `U' is for constant move_operands that can be safely loaded into $25.
1987 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1988 This is true for all non-mips16 references (although it can sometimes
1989 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1990 stack and constant-pool references.
1991 `YG' is for 0 valued vector constants. */
1992
1993 #define EXTRA_CONSTRAINT_Y(OP,STR) \
1994 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
1995 && (OP) == CONST0_RTX (GET_MODE (OP))) \
1996 : FALSE)
1997
1998
1999 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
2000 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2001 : ((CODE) == 'R') ? (MEM_P (OP) \
2002 && mips_fetch_insns (OP) == 1) \
2003 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2004 && call_insn_operand (OP, VOIDmode)) \
2005 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2006 && move_operand (OP, VOIDmode) \
2007 && mips_dangerous_for_la25_p (OP)) \
2008 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2009 && move_operand (OP, VOIDmode) \
2010 && !mips_dangerous_for_la25_p (OP)) \
2011 : ((CODE) == 'W') ? (MEM_P (OP) \
2012 && memory_operand (OP, VOIDmode) \
2013 && (!TARGET_MIPS16 \
2014 || (!stack_operand (OP, VOIDmode) \
2015 && !CONSTANT_P (XEXP (OP, 0))))) \
2016 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
2017 : FALSE)
2018
2019 /* Y is the only multi-letter constraint, and has length 2. */
2020
2021 #define CONSTRAINT_LEN(C,STR) \
2022 (((C) == 'Y') ? 2 \
2023 : DEFAULT_CONSTRAINT_LEN (C, STR))
2024
2025 /* Say which of the above are memory constraints. */
2026 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2027
2028 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2029 mips_preferred_reload_class (X, CLASS)
2030
2031 /* Certain machines have the property that some registers cannot be
2032 copied to some other registers without using memory. Define this
2033 macro on those machines to be a C expression that is nonzero if
2034 objects of mode MODE in registers of CLASS1 can only be copied to
2035 registers of class CLASS2 by storing a register of CLASS1 into
2036 memory and loading that memory location into a register of CLASS2.
2037
2038 Do not define this macro if its value would always be zero. */
2039 #if 0
2040 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2041 ((!TARGET_DEBUG_H_MODE \
2042 && GET_MODE_CLASS (MODE) == MODE_INT \
2043 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2044 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2045 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2046 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2047 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2048 #endif
2049 /* The HI and LO registers can only be reloaded via the general
2050 registers. Condition code registers can only be loaded to the
2051 general registers, and from the floating point registers. */
2052
2053 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2054 mips_secondary_reload_class (CLASS, MODE, X, 1)
2055 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2056 mips_secondary_reload_class (CLASS, MODE, X, 0)
2057
2058 /* Return the maximum number of consecutive registers
2059 needed to represent mode MODE in a register of class CLASS. */
2060
2061 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2062
2063 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2064 mips_cannot_change_mode_class (FROM, TO, CLASS)
2065 \f
2066 /* Stack layout; function entry, exit and calling. */
2067
2068 #define STACK_GROWS_DOWNWARD
2069
2070 /* The offset of the first local variable from the beginning of the frame.
2071 See compute_frame_size for details about the frame layout.
2072
2073 ??? If flag_profile_values is true, and we are generating 32-bit code, then
2074 we assume that we will need 16 bytes of argument space. This is because
2075 the value profiling code may emit calls to cmpdi2 in leaf functions.
2076 Without this hack, the local variables will start at sp+8 and the gp save
2077 area will be at sp+16, and thus they will overlap. compute_frame_size is
2078 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
2079 will end up as 24 instead of 8. This won't be needed if profiling code is
2080 inserted before virtual register instantiation. */
2081
2082 #define STARTING_FRAME_OFFSET \
2083 ((flag_profile_values && ! TARGET_64BIT \
2084 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
2085 : current_function_outgoing_args_size) \
2086 + (TARGET_ABICALLS && !TARGET_NEWABI \
2087 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2088
2089 #define RETURN_ADDR_RTX mips_return_addr
2090
2091 /* Since the mips16 ISA mode is encoded in the least-significant bit
2092 of the address, mask it off return addresses for purposes of
2093 finding exception handling regions. */
2094
2095 #define MASK_RETURN_ADDR GEN_INT (-2)
2096
2097
2098 /* Similarly, don't use the least-significant bit to tell pointers to
2099 code from vtable index. */
2100
2101 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2102
2103 /* The eliminations to $17 are only used for mips16 code. See the
2104 definition of HARD_FRAME_POINTER_REGNUM. */
2105
2106 #define ELIMINABLE_REGS \
2107 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2108 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2109 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2110 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2111 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2112 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2113
2114 /* We can always eliminate to the hard frame pointer. We can eliminate
2115 to the stack pointer unless a frame pointer is needed.
2116
2117 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2118 reload may be unable to compute the address of a local variable,
2119 since there is no way to add a large constant to the stack pointer
2120 without using a temporary register. */
2121 #define CAN_ELIMINATE(FROM, TO) \
2122 ((TO) == HARD_FRAME_POINTER_REGNUM \
2123 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2124 && (!TARGET_MIPS16 \
2125 || compute_frame_size (get_frame_size ()) < 32768)))
2126
2127 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2128 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2129
2130 /* Allocate stack space for arguments at the beginning of each function. */
2131 #define ACCUMULATE_OUTGOING_ARGS 1
2132
2133 /* The argument pointer always points to the first argument. */
2134 #define FIRST_PARM_OFFSET(FNDECL) 0
2135
2136 /* o32 and o64 reserve stack space for all argument registers. */
2137 #define REG_PARM_STACK_SPACE(FNDECL) \
2138 (TARGET_OLDABI \
2139 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2140 : 0)
2141
2142 /* Define this if it is the responsibility of the caller to
2143 allocate the area reserved for arguments passed in registers.
2144 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2145 of this macro is to determine whether the space is included in
2146 `current_function_outgoing_args_size'. */
2147 #define OUTGOING_REG_PARM_STACK_SPACE
2148
2149 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2150 \f
2151 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2152
2153 /* Symbolic macros for the registers used to return integer and floating
2154 point values. */
2155
2156 #define GP_RETURN (GP_REG_FIRST + 2)
2157 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2158
2159 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2160
2161 /* Symbolic macros for the first/last argument registers. */
2162
2163 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2164 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2165 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2166 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2167
2168 #define LIBCALL_VALUE(MODE) \
2169 mips_function_value (NULL_TREE, NULL, (MODE))
2170
2171 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2172 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2173
2174 /* 1 if N is a possible register number for a function value.
2175 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2176 Currently, R2 and F0 are only implemented here (C has no complex type) */
2177
2178 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2179 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2180 && (N) == FP_RETURN + 2))
2181
2182 /* 1 if N is a possible register number for function argument passing.
2183 We have no FP argument registers when soft-float. When FP registers
2184 are 32 bits, we can't directly reference the odd numbered ones. */
2185
2186 #define FUNCTION_ARG_REGNO_P(N) \
2187 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2188 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2189 && !fixed_regs[N])
2190 \f
2191 /* This structure has to cope with two different argument allocation
2192 schemes. Most MIPS ABIs view the arguments as a structure, of which
2193 the first N words go in registers and the rest go on the stack. If I
2194 < N, the Ith word might go in Ith integer argument register or in a
2195 floating-point register. For these ABIs, we only need to remember
2196 the offset of the current argument into the structure.
2197
2198 The EABI instead allocates the integer and floating-point arguments
2199 separately. The first N words of FP arguments go in FP registers,
2200 the rest go on the stack. Likewise, the first N words of the other
2201 arguments go in integer registers, and the rest go on the stack. We
2202 need to maintain three counts: the number of integer registers used,
2203 the number of floating-point registers used, and the number of words
2204 passed on the stack.
2205
2206 We could keep separate information for the two ABIs (a word count for
2207 the standard ABIs, and three separate counts for the EABI). But it
2208 seems simpler to view the standard ABIs as forms of EABI that do not
2209 allocate floating-point registers.
2210
2211 So for the standard ABIs, the first N words are allocated to integer
2212 registers, and function_arg decides on an argument-by-argument basis
2213 whether that argument should really go in an integer register, or in
2214 a floating-point one. */
2215
2216 typedef struct mips_args {
2217 /* Always true for varargs functions. Otherwise true if at least
2218 one argument has been passed in an integer register. */
2219 int gp_reg_found;
2220
2221 /* The number of arguments seen so far. */
2222 unsigned int arg_number;
2223
2224 /* The number of integer registers used so far. For all ABIs except
2225 EABI, this is the number of words that have been added to the
2226 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2227 unsigned int num_gprs;
2228
2229 /* For EABI, the number of floating-point registers used so far. */
2230 unsigned int num_fprs;
2231
2232 /* The number of words passed on the stack. */
2233 unsigned int stack_words;
2234
2235 /* On the mips16, we need to keep track of which floating point
2236 arguments were passed in general registers, but would have been
2237 passed in the FP regs if this were a 32 bit function, so that we
2238 can move them to the FP regs if we wind up calling a 32 bit
2239 function. We record this information in fp_code, encoded in base
2240 four. A zero digit means no floating point argument, a one digit
2241 means an SFmode argument, and a two digit means a DFmode argument,
2242 and a three digit is not used. The low order digit is the first
2243 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2244 an SFmode argument. ??? A more sophisticated approach will be
2245 needed if MIPS_ABI != ABI_32. */
2246 int fp_code;
2247
2248 /* True if the function has a prototype. */
2249 int prototype;
2250 } CUMULATIVE_ARGS;
2251
2252 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2253 for a call to a function whose data type is FNTYPE.
2254 For a library call, FNTYPE is 0. */
2255
2256 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2257 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2258
2259 /* Update the data in CUM to advance over an argument
2260 of mode MODE and data type TYPE.
2261 (TYPE is null for libcalls where that information may not be available.) */
2262
2263 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2264 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2265
2266 /* Determine where to put an argument to a function.
2267 Value is zero to push the argument on the stack,
2268 or a hard register in which to store the argument.
2269
2270 MODE is the argument's machine mode.
2271 TYPE is the data type of the argument (as a tree).
2272 This is null for libcalls where that information may
2273 not be available.
2274 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2275 the preceding args and about the function being called.
2276 NAMED is nonzero if this argument is a named parameter
2277 (otherwise it is an extra parameter matching an ellipsis). */
2278
2279 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2280 function_arg( &CUM, MODE, TYPE, NAMED)
2281
2282 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2283
2284 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2285 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2286
2287 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2288 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2289
2290 /* True if using EABI and varargs can be passed in floating-point
2291 registers. Under these conditions, we need a more complex form
2292 of va_list, which tracks GPR, FPR and stack arguments separately. */
2293 #define EABI_FLOAT_VARARGS_P \
2294 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2295
2296 \f
2297 /* Say that the epilogue uses the return address register. Note that
2298 in the case of sibcalls, the values "used by the epilogue" are
2299 considered live at the start of the called function. */
2300 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2301
2302 /* Treat LOC as a byte offset from the stack pointer and round it up
2303 to the next fully-aligned offset. */
2304 #define MIPS_STACK_ALIGN(LOC) \
2305 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2306
2307 \f
2308 /* Implement `va_start' for varargs and stdarg. */
2309 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2310 mips_va_start (valist, nextarg)
2311 \f
2312 /* Output assembler code to FILE to increment profiler label # LABELNO
2313 for profiling a function entry. */
2314
2315 #define FUNCTION_PROFILER(FILE, LABELNO) \
2316 { \
2317 if (TARGET_MIPS16) \
2318 sorry ("mips16 function profiling"); \
2319 fprintf (FILE, "\t.set\tnoat\n"); \
2320 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2321 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2322 if (!TARGET_NEWABI) \
2323 { \
2324 fprintf (FILE, \
2325 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2326 TARGET_64BIT ? "dsubu" : "subu", \
2327 reg_names[STACK_POINTER_REGNUM], \
2328 reg_names[STACK_POINTER_REGNUM], \
2329 Pmode == DImode ? 16 : 8); \
2330 } \
2331 fprintf (FILE, "\tjal\t_mcount\n"); \
2332 fprintf (FILE, "\t.set\tat\n"); \
2333 }
2334
2335 /* Define this macro if the code for function profiling should come
2336 before the function prologue. Normally, the profiling code comes
2337 after. */
2338
2339 /* #define PROFILE_BEFORE_PROLOGUE */
2340
2341 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2342 the stack pointer does not matter. The value is tested only in
2343 functions that have frame pointers.
2344 No definition is equivalent to always zero. */
2345
2346 #define EXIT_IGNORE_STACK 1
2347
2348 \f
2349 /* A C statement to output, on the stream FILE, assembler code for a
2350 block of data that contains the constant parts of a trampoline.
2351 This code should not include a label--the label is taken care of
2352 automatically. */
2353
2354 #define TRAMPOLINE_TEMPLATE(STREAM) \
2355 { \
2356 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2357 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2358 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2359 if (ptr_mode == DImode) \
2360 { \
2361 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2362 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2363 } \
2364 else \
2365 { \
2366 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2367 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2368 } \
2369 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2370 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2371 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2372 if (ptr_mode == DImode) \
2373 { \
2374 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2375 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2376 } \
2377 else \
2378 { \
2379 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2380 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2381 } \
2382 }
2383
2384 /* A C expression for the size in bytes of the trampoline, as an
2385 integer. */
2386
2387 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2388
2389 /* Alignment required for trampolines, in bits. */
2390
2391 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2392
2393 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2394 program and data caches. */
2395
2396 #ifndef CACHE_FLUSH_FUNC
2397 #define CACHE_FLUSH_FUNC "_flush_cache"
2398 #endif
2399
2400 /* A C statement to initialize the variable parts of a trampoline.
2401 ADDR is an RTX for the address of the trampoline; FNADDR is an
2402 RTX for the address of the nested function; STATIC_CHAIN is an
2403 RTX for the static chain value that should be passed to the
2404 function when it is called. */
2405
2406 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2407 { \
2408 rtx func_addr, chain_addr; \
2409 \
2410 func_addr = plus_constant (ADDR, 32); \
2411 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2412 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2413 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2414 \
2415 /* Flush both caches. We need to flush the data cache in case \
2416 the system has a write-back cache. */ \
2417 /* ??? Should check the return value for errors. */ \
2418 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2419 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2420 0, VOIDmode, 3, ADDR, Pmode, \
2421 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2422 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2423 }
2424 \f
2425 /* Addressing modes, and classification of registers for them. */
2426
2427 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2428 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2429 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2430
2431 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2432 and check its validity for a certain class.
2433 We have two alternate definitions for each of them.
2434 The usual definition accepts all pseudo regs; the other rejects them all.
2435 The symbol REG_OK_STRICT causes the latter definition to be used.
2436
2437 Most source files want to accept pseudo regs in the hope that
2438 they will get allocated to the class that the insn wants them to be in.
2439 Some source files that are used after register allocation
2440 need to be strict. */
2441
2442 #ifndef REG_OK_STRICT
2443 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2444 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2445 #else
2446 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2447 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2448 #endif
2449
2450 #define REG_OK_FOR_INDEX_P(X) 0
2451
2452 \f
2453 /* Maximum number of registers that can appear in a valid memory address. */
2454
2455 #define MAX_REGS_PER_ADDRESS 1
2456
2457 #ifdef REG_OK_STRICT
2458 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2459 { \
2460 if (mips_legitimate_address_p (MODE, X, 1)) \
2461 goto ADDR; \
2462 }
2463 #else
2464 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2465 { \
2466 if (mips_legitimate_address_p (MODE, X, 0)) \
2467 goto ADDR; \
2468 }
2469 #endif
2470
2471 /* Check for constness inline but use mips_legitimate_address_p
2472 to check whether a constant really is an address. */
2473
2474 #define CONSTANT_ADDRESS_P(X) \
2475 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2476
2477 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2478
2479 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2480 do { \
2481 if (mips_legitimize_address (&(X), MODE)) \
2482 goto WIN; \
2483 } while (0)
2484
2485
2486 /* A C statement or compound statement with a conditional `goto
2487 LABEL;' executed if memory address X (an RTX) can have different
2488 meanings depending on the machine mode of the memory reference it
2489 is used for.
2490
2491 Autoincrement and autodecrement addresses typically have
2492 mode-dependent effects because the amount of the increment or
2493 decrement is the size of the operand being addressed. Some
2494 machines have other mode-dependent addresses. Many RISC machines
2495 have no mode-dependent addresses.
2496
2497 You may assume that ADDR is a valid address for the machine. */
2498
2499 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2500
2501 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2502 'the start of the function that this code is output in'. */
2503
2504 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2505 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2506 asm_fprintf ((FILE), "%U%s", \
2507 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2508 else \
2509 asm_fprintf ((FILE), "%U%s", (NAME))
2510 \f
2511 /* Specify the machine mode that this machine uses
2512 for the index in the tablejump instruction.
2513 ??? Using HImode in mips16 mode can cause overflow. */
2514 #define CASE_VECTOR_MODE \
2515 (TARGET_MIPS16 ? HImode : ptr_mode)
2516
2517 /* Define as C expression which evaluates to nonzero if the tablejump
2518 instruction expects the table to contain offsets from the address of the
2519 table.
2520 Do not define this if the table should contain absolute addresses. */
2521 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2522
2523 /* Define this as 1 if `char' should by default be signed; else as 0. */
2524 #ifndef DEFAULT_SIGNED_CHAR
2525 #define DEFAULT_SIGNED_CHAR 1
2526 #endif
2527
2528 /* Max number of bytes we can move from memory to memory
2529 in one reasonably fast instruction. */
2530 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2531 #define MAX_MOVE_MAX 8
2532
2533 /* Define this macro as a C expression which is nonzero if
2534 accessing less than a word of memory (i.e. a `char' or a
2535 `short') is no faster than accessing a word of memory, i.e., if
2536 such access require more than one instruction or if there is no
2537 difference in cost between byte and (aligned) word loads.
2538
2539 On RISC machines, it tends to generate better code to define
2540 this as 1, since it avoids making a QI or HI mode register. */
2541 #define SLOW_BYTE_ACCESS 1
2542
2543 /* Define this to be nonzero if shift instructions ignore all but the low-order
2544 few bits. */
2545 #define SHIFT_COUNT_TRUNCATED 1
2546
2547 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2548 is done just by pretending it is already truncated. */
2549 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2550 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2551
2552
2553 /* Specify the machine mode that pointers have.
2554 After generation of rtl, the compiler makes no further distinction
2555 between pointers and any other objects of this machine mode. */
2556
2557 #ifndef Pmode
2558 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2559 #endif
2560
2561 /* Give call MEMs SImode since it is the "most permissive" mode
2562 for both 32-bit and 64-bit targets. */
2563
2564 #define FUNCTION_MODE SImode
2565
2566 \f
2567 /* The cost of loading values from the constant pool. It should be
2568 larger than the cost of any constant we want to synthesize in-line. */
2569
2570 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2571
2572 /* A C expression for the cost of moving data from a register in
2573 class FROM to one in class TO. The classes are expressed using
2574 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2575 the default; other values are interpreted relative to that.
2576
2577 It is not required that the cost always equal 2 when FROM is the
2578 same as TO; on some machines it is expensive to move between
2579 registers if they are not general registers.
2580
2581 If reload sees an insn consisting of a single `set' between two
2582 hard registers, and if `REGISTER_MOVE_COST' applied to their
2583 classes returns a value of 2, reload does not check to ensure
2584 that the constraints of the insn are met. Setting a cost of
2585 other than 2 will allow reload to verify that the constraints are
2586 met. You should do this if the `movM' pattern's constraints do
2587 not allow such copying. */
2588
2589 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2590 mips_register_move_cost (MODE, FROM, TO)
2591
2592 /* ??? Fix this to be right for the R8000. */
2593 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2594 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2595 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2596
2597 /* Define if copies to/from condition code registers should be avoided.
2598
2599 This is needed for the MIPS because reload_outcc is not complete;
2600 it needs to handle cases where the source is a general or another
2601 condition code register. */
2602 #define AVOID_CCMODE_COPIES
2603
2604 /* A C expression for the cost of a branch instruction. A value of
2605 1 is the default; other values are interpreted relative to that. */
2606
2607 /* ??? Fix this to be right for the R8000. */
2608 #define BRANCH_COST \
2609 ((! TARGET_MIPS16 \
2610 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2611 ? 2 : 1)
2612
2613 /* If defined, modifies the length assigned to instruction INSN as a
2614 function of the context in which it is used. LENGTH is an lvalue
2615 that contains the initially computed length of the insn and should
2616 be updated with the correct length of the insn. */
2617 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2618 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2619 \f
2620 /* Control the assembler format that we output. */
2621
2622 /* Output to assembler file text saying following lines
2623 may contain character constants, extra white space, comments, etc. */
2624
2625 #ifndef ASM_APP_ON
2626 #define ASM_APP_ON " #APP\n"
2627 #endif
2628
2629 /* Output to assembler file text saying following lines
2630 no longer contain unusual constructs. */
2631
2632 #ifndef ASM_APP_OFF
2633 #define ASM_APP_OFF " #NO_APP\n"
2634 #endif
2635
2636 #define REGISTER_NAMES \
2637 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2638 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2639 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2640 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2641 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2642 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2643 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2644 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2645 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2646 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2647 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2648 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2649 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2650 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2651 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2652 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2653 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2654 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2655 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2656 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2657 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2658 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2659
2660 /* List the "software" names for each register. Also list the numerical
2661 names for $fp and $sp. */
2662
2663 #define ADDITIONAL_REGISTER_NAMES \
2664 { \
2665 { "$29", 29 + GP_REG_FIRST }, \
2666 { "$30", 30 + GP_REG_FIRST }, \
2667 { "at", 1 + GP_REG_FIRST }, \
2668 { "v0", 2 + GP_REG_FIRST }, \
2669 { "v1", 3 + GP_REG_FIRST }, \
2670 { "a0", 4 + GP_REG_FIRST }, \
2671 { "a1", 5 + GP_REG_FIRST }, \
2672 { "a2", 6 + GP_REG_FIRST }, \
2673 { "a3", 7 + GP_REG_FIRST }, \
2674 { "t0", 8 + GP_REG_FIRST }, \
2675 { "t1", 9 + GP_REG_FIRST }, \
2676 { "t2", 10 + GP_REG_FIRST }, \
2677 { "t3", 11 + GP_REG_FIRST }, \
2678 { "t4", 12 + GP_REG_FIRST }, \
2679 { "t5", 13 + GP_REG_FIRST }, \
2680 { "t6", 14 + GP_REG_FIRST }, \
2681 { "t7", 15 + GP_REG_FIRST }, \
2682 { "s0", 16 + GP_REG_FIRST }, \
2683 { "s1", 17 + GP_REG_FIRST }, \
2684 { "s2", 18 + GP_REG_FIRST }, \
2685 { "s3", 19 + GP_REG_FIRST }, \
2686 { "s4", 20 + GP_REG_FIRST }, \
2687 { "s5", 21 + GP_REG_FIRST }, \
2688 { "s6", 22 + GP_REG_FIRST }, \
2689 { "s7", 23 + GP_REG_FIRST }, \
2690 { "t8", 24 + GP_REG_FIRST }, \
2691 { "t9", 25 + GP_REG_FIRST }, \
2692 { "k0", 26 + GP_REG_FIRST }, \
2693 { "k1", 27 + GP_REG_FIRST }, \
2694 { "gp", 28 + GP_REG_FIRST }, \
2695 { "sp", 29 + GP_REG_FIRST }, \
2696 { "fp", 30 + GP_REG_FIRST }, \
2697 { "ra", 31 + GP_REG_FIRST }, \
2698 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2699 }
2700
2701 /* This is meant to be redefined in the host dependent files. It is a
2702 set of alternative names and regnums for mips coprocessors. */
2703
2704 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2705
2706 /* A C compound statement to output to stdio stream STREAM the
2707 assembler syntax for an instruction operand X. X is an RTL
2708 expression.
2709
2710 CODE is a value that can be used to specify one of several ways
2711 of printing the operand. It is used when identical operands
2712 must be printed differently depending on the context. CODE
2713 comes from the `%' specification that was used to request
2714 printing of the operand. If the specification was just `%DIGIT'
2715 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2716 is the ASCII code for LTR.
2717
2718 If X is a register, this macro should print the register's name.
2719 The names can be found in an array `reg_names' whose type is
2720 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2721
2722 When the machine description has a specification `%PUNCT' (a `%'
2723 followed by a punctuation character), this macro is called with
2724 a null pointer for X and the punctuation character for CODE.
2725
2726 See mips.c for the MIPS specific codes. */
2727
2728 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2729
2730 /* A C expression which evaluates to true if CODE is a valid
2731 punctuation character for use in the `PRINT_OPERAND' macro. If
2732 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2733 punctuation characters (except for the standard one, `%') are
2734 used in this way. */
2735
2736 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2737
2738 /* A C compound statement to output to stdio stream STREAM the
2739 assembler syntax for an instruction operand that is a memory
2740 reference whose address is ADDR. ADDR is an RTL expression. */
2741
2742 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2743
2744
2745 /* A C statement, to be executed after all slot-filler instructions
2746 have been output. If necessary, call `dbr_sequence_length' to
2747 determine the number of slots filled in a sequence (zero if not
2748 currently outputting a sequence), to decide how many no-ops to
2749 output, or whatever.
2750
2751 Don't define this macro if it has nothing to do, but it is
2752 helpful in reading assembly output if the extent of the delay
2753 sequence is made explicit (e.g. with white space).
2754
2755 Note that output routines for instructions with delay slots must
2756 be prepared to deal with not being output as part of a sequence
2757 (i.e. when the scheduling pass is not run, or when no slot
2758 fillers could be found.) The variable `final_sequence' is null
2759 when not processing a sequence, otherwise it contains the
2760 `sequence' rtx being output. */
2761
2762 #define DBR_OUTPUT_SEQEND(STREAM) \
2763 do \
2764 { \
2765 if (set_nomacro > 0 && --set_nomacro == 0) \
2766 fputs ("\t.set\tmacro\n", STREAM); \
2767 \
2768 if (set_noreorder > 0 && --set_noreorder == 0) \
2769 fputs ("\t.set\treorder\n", STREAM); \
2770 \
2771 fputs ("\n", STREAM); \
2772 } \
2773 while (0)
2774
2775
2776 /* How to tell the debugger about changes of source files. */
2777 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2778 mips_output_filename (STREAM, NAME)
2779
2780 /* mips-tfile does not understand .stabd directives. */
2781 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2782 dbxout_begin_stabn_sline (LINE); \
2783 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2784 } while (0)
2785
2786 /* Use .loc directives for SDB line numbers. */
2787 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2788 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2789
2790 /* The MIPS implementation uses some labels for its own purpose. The
2791 following lists what labels are created, and are all formed by the
2792 pattern $L[a-z].*. The machine independent portion of GCC creates
2793 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2794
2795 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2796 $Lb[0-9]+ Begin blocks for MIPS debug support
2797 $Lc[0-9]+ Label for use in s<xx> operation.
2798 $Le[0-9]+ End blocks for MIPS debug support */
2799
2800 #undef ASM_DECLARE_OBJECT_NAME
2801 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2802 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2803
2804 /* Globalizing directive for a label. */
2805 #define GLOBAL_ASM_OP "\t.globl\t"
2806
2807 /* This says how to define a global common symbol. */
2808
2809 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2810
2811 /* This says how to define a local common symbol (i.e., not visible to
2812 linker). */
2813
2814 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2815 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2816 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2817 #endif
2818
2819 /* This says how to output an external. It would be possible not to
2820 output anything and let undefined symbol become external. However
2821 the assembler uses length information on externals to allocate in
2822 data/sdata bss/sbss, thereby saving exec time. */
2823
2824 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2825 mips_output_external(STREAM,DECL,NAME)
2826
2827 /* This is how to declare a function name. The actual work of
2828 emitting the label is moved to function_prologue, so that we can
2829 get the line number correctly emitted before the .ent directive,
2830 and after any .file directives. Define as empty so that the function
2831 is not declared before the .ent directive elsewhere. */
2832
2833 #undef ASM_DECLARE_FUNCTION_NAME
2834 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2835
2836 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2837 #define FUNCTION_NAME_ALREADY_DECLARED 0
2838 #endif
2839
2840 /* This is how to store into the string LABEL
2841 the symbol_ref name of an internal numbered label where
2842 PREFIX is the class of label and NUM is the number within the class.
2843 This is suitable for output with `assemble_name'. */
2844
2845 #undef ASM_GENERATE_INTERNAL_LABEL
2846 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2847 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2848
2849 /* This is how to output an element of a case-vector that is absolute. */
2850
2851 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2852 fprintf (STREAM, "\t%s\t%sL%d\n", \
2853 ptr_mode == DImode ? ".dword" : ".word", \
2854 LOCAL_LABEL_PREFIX, \
2855 VALUE)
2856
2857 /* This is how to output an element of a case-vector. We can make the
2858 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2859 is supported. */
2860
2861 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2862 do { \
2863 if (TARGET_MIPS16) \
2864 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2865 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2866 else if (TARGET_GPWORD) \
2867 fprintf (STREAM, "\t%s\t%sL%d\n", \
2868 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2869 LOCAL_LABEL_PREFIX, VALUE); \
2870 else \
2871 fprintf (STREAM, "\t%s\t%sL%d\n", \
2872 ptr_mode == DImode ? ".dword" : ".word", \
2873 LOCAL_LABEL_PREFIX, VALUE); \
2874 } while (0)
2875
2876 /* When generating mips16 code we want to put the jump table in the .text
2877 section. In all other cases, we want to put the jump table in the .rdata
2878 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
2879 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
2880 to the .text section if appropriate. */
2881 #undef ASM_OUTPUT_CASE_LABEL
2882 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
2883 do { \
2884 if (TARGET_MIPS16) \
2885 function_section (current_function_decl); \
2886 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2887 } while (0)
2888
2889 /* This is how to output an assembler line
2890 that says to advance the location counter
2891 to a multiple of 2**LOG bytes. */
2892
2893 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2894 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2895
2896 /* This is how to output an assembler line to advance the location
2897 counter by SIZE bytes. */
2898
2899 #undef ASM_OUTPUT_SKIP
2900 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2901 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2902
2903 /* This is how to output a string. */
2904 #undef ASM_OUTPUT_ASCII
2905 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2906 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2907
2908 /* Output #ident as a in the read-only data section. */
2909 #undef ASM_OUTPUT_IDENT
2910 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2911 { \
2912 const char *p = STRING; \
2913 int size = strlen (p) + 1; \
2914 readonly_data_section (); \
2915 assemble_string (p, size); \
2916 }
2917 \f
2918 /* Default to -G 8 */
2919 #ifndef MIPS_DEFAULT_GVALUE
2920 #define MIPS_DEFAULT_GVALUE 8
2921 #endif
2922
2923 /* Define the strings to put out for each section in the object file. */
2924 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2925 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2926 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2927
2928 #undef READONLY_DATA_SECTION_ASM_OP
2929 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2930 \f
2931 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2932 do \
2933 { \
2934 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2935 TARGET_64BIT ? "dsubu" : "subu", \
2936 reg_names[STACK_POINTER_REGNUM], \
2937 reg_names[STACK_POINTER_REGNUM], \
2938 TARGET_64BIT ? "sd" : "sw", \
2939 reg_names[REGNO], \
2940 reg_names[STACK_POINTER_REGNUM]); \
2941 } \
2942 while (0)
2943
2944 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2945 do \
2946 { \
2947 if (! set_noreorder) \
2948 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2949 \
2950 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2951 TARGET_64BIT ? "ld" : "lw", \
2952 reg_names[REGNO], \
2953 reg_names[STACK_POINTER_REGNUM], \
2954 TARGET_64BIT ? "daddu" : "addu", \
2955 reg_names[STACK_POINTER_REGNUM], \
2956 reg_names[STACK_POINTER_REGNUM]); \
2957 \
2958 if (! set_noreorder) \
2959 fprintf (STREAM, "\t.set\treorder\n"); \
2960 } \
2961 while (0)
2962
2963 /* How to start an assembler comment.
2964 The leading space is important (the mips native assembler requires it). */
2965 #ifndef ASM_COMMENT_START
2966 #define ASM_COMMENT_START " #"
2967 #endif
2968 \f
2969 /* Default definitions for size_t and ptrdiff_t. We must override the
2970 definitions from ../svr4.h on mips-*-linux-gnu. */
2971
2972 #undef SIZE_TYPE
2973 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2974
2975 #undef PTRDIFF_TYPE
2976 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2977
2978 /* See mips_expand_prologue's use of loadgp for when this should be
2979 true. */
2980
2981 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
2982 \f
2983 #ifndef __mips16
2984 /* Since the bits of the _init and _fini function is spread across
2985 many object files, each potentially with its own GP, we must assume
2986 we need to load our GP. We don't preserve $gp or $ra, since each
2987 init/fini chunk is supposed to initialize $gp, and crti/crtn
2988 already take care of preserving $ra and, when appropriate, $gp. */
2989 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2990 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2991 asm (SECTION_OP "\n\
2992 .set noreorder\n\
2993 bal 1f\n\
2994 nop\n\
2995 1: .cpload $31\n\
2996 .set reorder\n\
2997 jal " USER_LABEL_PREFIX #FUNC "\n\
2998 " TEXT_SECTION_ASM_OP);
2999 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3000 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3001 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3002 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3003 asm (SECTION_OP "\n\
3004 .set noreorder\n\
3005 bal 1f\n\
3006 nop\n\
3007 1: .set reorder\n\
3008 .cpsetup $31, $2, 1b\n\
3009 jal " USER_LABEL_PREFIX #FUNC "\n\
3010 " TEXT_SECTION_ASM_OP);
3011 #endif
3012 #endif
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