gcc/config/m32r/m32r.c

   1 /* Subroutines used for code generation on the Renesas M32R cpu.
   2    Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 2, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #include "config.h"
  23 #include "system.h"
  24 #include "coretypes.h"
  25 #include "tm.h"
  26 #include "tree.h"
  27 #include "rtl.h"
  28 #include "regs.h"
  29 #include "hard-reg-set.h"
  30 #include "real.h"
  31 #include "insn-config.h"
  32 #include "conditions.h"
  33 #include "output.h"
  34 #include "insn-attr.h"
  35 #include "flags.h"
  36 #include "expr.h"
  37 #include "function.h"
  38 #include "recog.h"
  39 #include "toplev.h"
  40 #include "ggc.h"
  41 #include "integrate.h"
  42 #include "tm_p.h"
  43 #include "target.h"
  44 #include "target-def.h"
  45
  46 /* Save the operands last given to a compare for use when we
  47    generate a scc or bcc insn.  */
  48 rtx m32r_compare_op0, m32r_compare_op1;
  49
  50 /* Array of valid operand punctuation characters.  */
  51 char m32r_punct_chars[256];
  52
  53 /* Selected code model.  */
  54 const char * m32r_model_string = M32R_MODEL_DEFAULT;
  55 enum m32r_model m32r_model;
  56
  57 /* Selected SDA support.  */
  58 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
  59 enum m32r_sdata m32r_sdata;
  60
  61 /* Machine-specific symbol_ref flags.  */
  62 #define SYMBOL_FLAG_MODEL_SHIFT         SYMBOL_FLAG_MACH_DEP_SHIFT
  63 #define SYMBOL_REF_MODEL(X) \
  64   ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
  65
  66 /* For string literals, etc.  */
  67 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
  68
  69 /* Cache-flush support. Cache-flush is used at trampoline.
  70    Default cache-flush is "trap 12".
  71     default cache-flush function is "_flush_cache"  (CACHE_FLUSH_FUNC)
  72     default cache-flush trap-interrupt number is "12". (CACHE_FLUSH_TRAP)
  73    You can change how to generate code of cache-flush with following options.
  74    -flush-func=FLUSH-FUNC-NAME
  75    -no-flush-func
  76    -fluch-trap=TRAP-NUMBER
  77    -no-flush-trap.  */
  78 const char *m32r_cache_flush_func = CACHE_FLUSH_FUNC;
  79 const char *m32r_cache_flush_trap_string = CACHE_FLUSH_TRAP;
  80 int m32r_cache_flush_trap = 12;
  81
  82 /* Forward declaration.  */
  83 static void  init_reg_tables (void);
  84 static void  block_move_call (rtx, rtx, rtx);
  85 static int   m32r_is_insn (rtx);
  86 const struct attribute_spec m32r_attribute_table[];
  87 static tree  m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
  88 static void  m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
  89 static void  m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
  90
  91 static void  m32r_file_start (void);
  92
  93 static int    m32r_adjust_priority (rtx, int);
  94 static int    m32r_issue_rate (void);
  95
  96 static void m32r_encode_section_info (tree, rtx, int);
  97 static bool m32r_in_small_data_p (tree);
  98 static bool m32r_return_in_memory (tree, tree);
  99 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
 100                                          tree, int *, int);
 101 static void init_idents (void);
 102 static bool m32r_rtx_costs (rtx, int, int, int *);
 103 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
 104                                     tree, bool);
 105 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
 106                                    tree, bool);
 107 \f
 108 /* Initialize the GCC target structure.  */
 109 #undef  TARGET_ATTRIBUTE_TABLE
 110 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
 111
 112 #undef  TARGET_ASM_ALIGNED_HI_OP
 113 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
 114 #undef  TARGET_ASM_ALIGNED_SI_OP
 115 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
 116
 117 #undef  TARGET_ASM_FUNCTION_PROLOGUE
 118 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
 119 #undef  TARGET_ASM_FUNCTION_EPILOGUE
 120 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
 121
 122 #undef  TARGET_ASM_FILE_START
 123 #define TARGET_ASM_FILE_START m32r_file_start
 124
 125 #undef  TARGET_SCHED_ADJUST_PRIORITY
 126 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
 127 #undef  TARGET_SCHED_ISSUE_RATE
 128 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
 129
 130 #undef  TARGET_ENCODE_SECTION_INFO
 131 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
 132 #undef  TARGET_IN_SMALL_DATA_P
 133 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
 134
 135 #undef  TARGET_RTX_COSTS
 136 #define TARGET_RTX_COSTS m32r_rtx_costs
 137 #undef  TARGET_ADDRESS_COST
 138 #define TARGET_ADDRESS_COST hook_int_rtx_0
 139
 140 #undef  TARGET_PROMOTE_PROTOTYPES
 141 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
 142 #undef  TARGET_RETURN_IN_MEMORY
 143 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
 144 #undef  TARGET_SETUP_INCOMING_VARARGS
 145 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
 146 #undef  TARGET_MUST_PASS_IN_STACK
 147 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
 148 #undef  TARGET_PASS_BY_REFERENCE
 149 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
 150 #undef  TARGET_ARG_PARTIAL_BYTES
 151 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
 152
 153 struct gcc_target targetm = TARGET_INITIALIZER;
 154 \f
 155 /* Called by OVERRIDE_OPTIONS to initialize various things.  */
 156
 157 void
 158 m32r_init (void)
 159 {
 160   init_reg_tables ();
 161
 162   /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
 163   memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
 164   m32r_punct_chars['#'] = 1;
 165   m32r_punct_chars['@'] = 1; /* ??? no longer used */
 166
 167   /* Provide default value if not specified.  */
 168   if (!g_switch_set)
 169     g_switch_value = SDATA_DEFAULT_SIZE;
 170
 171   if (strcmp (m32r_model_string, "small") == 0)
 172     m32r_model = M32R_MODEL_SMALL;
 173   else if (strcmp (m32r_model_string, "medium") == 0)
 174     m32r_model = M32R_MODEL_MEDIUM;
 175   else if (strcmp (m32r_model_string, "large") == 0)
 176     m32r_model = M32R_MODEL_LARGE;
 177   else
 178     error ("bad value (%s) for -mmodel switch", m32r_model_string);
 179
 180   if (strcmp (m32r_sdata_string, "none") == 0)
 181     m32r_sdata = M32R_SDATA_NONE;
 182   else if (strcmp (m32r_sdata_string, "sdata") == 0)
 183     m32r_sdata = M32R_SDATA_SDATA;
 184   else if (strcmp (m32r_sdata_string, "use") == 0)
 185     m32r_sdata = M32R_SDATA_USE;
 186   else
 187     error ("bad value (%s) for -msdata switch", m32r_sdata_string);
 188
 189   if (m32r_cache_flush_trap_string)
 190     {
 191       /* Change trap-number (12) for cache-flush to the others (0 - 15).  */
 192       m32r_cache_flush_trap = atoi (m32r_cache_flush_trap_string);
 193       if (m32r_cache_flush_trap < 0 || m32r_cache_flush_trap > 15)
 194         error ("bad value (%s) for -flush-trap=n (0=<n<=15)",
 195                m32r_cache_flush_trap_string);
 196     }
 197 }
 198
 199 /* Vectors to keep interesting information about registers where it can easily
 200    be got.  We use to use the actual mode value as the bit number, but there
 201    is (or may be) more than 32 modes now.  Instead we use two tables: one
 202    indexed by hard register number, and one indexed by mode.  */
 203
 204 /* The purpose of m32r_mode_class is to shrink the range of modes so that
 205    they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
 206    mapped into one m32r_mode_class mode.  */
 207
 208 enum m32r_mode_class
 209 {
 210   C_MODE,
 211   S_MODE, D_MODE, T_MODE, O_MODE,
 212   SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
 213 };
 214
 215 /* Modes for condition codes.  */
 216 #define C_MODES (1 << (int) C_MODE)
 217
 218 /* Modes for single-word and smaller quantities.  */
 219 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
 220
 221 /* Modes for double-word and smaller quantities.  */
 222 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
 223
 224 /* Modes for quad-word and smaller quantities.  */
 225 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
 226
 227 /* Modes for accumulators.  */
 228 #define A_MODES (1 << (int) A_MODE)
 229
 230 /* Value is 1 if register/mode pair is acceptable on arc.  */
 231
 232 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
 233 {
 234   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
 235   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
 236   S_MODES, C_MODES, A_MODES, A_MODES
 237 };
 238
 239 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
 240
 241 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
 242
 243 static void
 244 init_reg_tables (void)
 245 {
 246   int i;
 247
 248   for (i = 0; i < NUM_MACHINE_MODES; i++)
 249     {
 250       switch (GET_MODE_CLASS (i))
 251         {
 252         case MODE_INT:
 253         case MODE_PARTIAL_INT:
 254         case MODE_COMPLEX_INT:
 255           if (GET_MODE_SIZE (i) <= 4)
 256             m32r_mode_class[i] = 1 << (int) S_MODE;
 257           else if (GET_MODE_SIZE (i) == 8)
 258             m32r_mode_class[i] = 1 << (int) D_MODE;
 259           else if (GET_MODE_SIZE (i) == 16)
 260             m32r_mode_class[i] = 1 << (int) T_MODE;
 261           else if (GET_MODE_SIZE (i) == 32)
 262             m32r_mode_class[i] = 1 << (int) O_MODE;
 263           else
 264             m32r_mode_class[i] = 0;
 265           break;
 266         case MODE_FLOAT:
 267         case MODE_COMPLEX_FLOAT:
 268           if (GET_MODE_SIZE (i) <= 4)
 269             m32r_mode_class[i] = 1 << (int) SF_MODE;
 270           else if (GET_MODE_SIZE (i) == 8)
 271             m32r_mode_class[i] = 1 << (int) DF_MODE;
 272           else if (GET_MODE_SIZE (i) == 16)
 273             m32r_mode_class[i] = 1 << (int) TF_MODE;
 274           else if (GET_MODE_SIZE (i) == 32)
 275             m32r_mode_class[i] = 1 << (int) OF_MODE;
 276           else
 277             m32r_mode_class[i] = 0;
 278           break;
 279         case MODE_CC:
 280           m32r_mode_class[i] = 1 << (int) C_MODE;
 281           break;
 282         default:
 283           m32r_mode_class[i] = 0;
 284           break;
 285         }
 286     }
 287
 288   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 289     {
 290       if (GPR_P (i))
 291         m32r_regno_reg_class[i] = GENERAL_REGS;
 292       else if (i == ARG_POINTER_REGNUM)
 293         m32r_regno_reg_class[i] = GENERAL_REGS;
 294       else
 295         m32r_regno_reg_class[i] = NO_REGS;
 296     }
 297 }
 298 \f
 299 /* M32R specific attribute support.
 300
 301    interrupt - for interrupt functions
 302
 303    model - select code model used to access object
 304
 305         small: addresses use 24 bits, use bl to make calls
 306         medium: addresses use 32 bits, use bl to make calls
 307         large: addresses use 32 bits, use seth/add3/jl to make calls
 308
 309         Grep for MODEL in m32r.h for more info.  */
 310
 311 static tree small_ident1;
 312 static tree small_ident2;
 313 static tree medium_ident1;
 314 static tree medium_ident2;
 315 static tree large_ident1;
 316 static tree large_ident2;
 317
 318 static void
 319 init_idents (void)
 320 {
 321   if (small_ident1 == 0)
 322     {
 323       small_ident1 = get_identifier ("small");
 324       small_ident2 = get_identifier ("__small__");
 325       medium_ident1 = get_identifier ("medium");
 326       medium_ident2 = get_identifier ("__medium__");
 327       large_ident1 = get_identifier ("large");
 328       large_ident2 = get_identifier ("__large__");
 329     }
 330 }
 331
 332 const struct attribute_spec m32r_attribute_table[] =
 333 {
 334   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
 335   { "interrupt", 0, 0, true,  false, false, NULL },
 336   { "model",     1, 1, true,  false, false, m32r_handle_model_attribute },
 337   { NULL,        0, 0, false, false, false, NULL }
 338 };
 339
 340
 341 /* Handle an "model" attribute; arguments as in
 342    struct attribute_spec.handler.  */
 343 static tree
 344 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
 345                              tree args, int flags ATTRIBUTE_UNUSED,
 346                              bool *no_add_attrs)
 347 {
 348   tree arg;
 349
 350   init_idents ();
 351   arg = TREE_VALUE (args);
 352
 353   if (arg != small_ident1
 354       && arg != small_ident2
 355       && arg != medium_ident1
 356       && arg != medium_ident2
 357       && arg != large_ident1
 358       && arg != large_ident2)
 359     {
 360       warning ("invalid argument of %qs attribute",
 361                IDENTIFIER_POINTER (name));
 362       *no_add_attrs = true;
 363     }
 364
 365   return NULL_TREE;
 366 }
 367 \f
 368 /* Encode section information of DECL, which is either a VAR_DECL,
 369    FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
 370
 371    For the M32R we want to record:
 372
 373    - whether the object lives in .sdata/.sbss.
 374    - what code model should be used to access the object
 375 */
 376
 377 static void
 378 m32r_encode_section_info (tree decl, rtx rtl, int first)
 379 {
 380   int extra_flags = 0;
 381   tree model_attr;
 382   enum m32r_model model;
 383
 384   default_encode_section_info (decl, rtl, first);
 385
 386   if (!DECL_P (decl))
 387     return;
 388
 389   model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
 390   if (model_attr)
 391     {
 392       tree id;
 393
 394       init_idents ();
 395
 396       id = TREE_VALUE (TREE_VALUE (model_attr));
 397
 398       if (id == small_ident1 || id == small_ident2)
 399         model = M32R_MODEL_SMALL;
 400       else if (id == medium_ident1 || id == medium_ident2)
 401         model = M32R_MODEL_MEDIUM;
 402       else if (id == large_ident1 || id == large_ident2)
 403         model = M32R_MODEL_LARGE;
 404       else
 405         abort (); /* shouldn't happen */
 406     }
 407   else
 408     {
 409       if (TARGET_MODEL_SMALL)
 410         model = M32R_MODEL_SMALL;
 411       else if (TARGET_MODEL_MEDIUM)
 412         model = M32R_MODEL_MEDIUM;
 413       else if (TARGET_MODEL_LARGE)
 414         model = M32R_MODEL_LARGE;
 415       else
 416         abort (); /* shouldn't happen */
 417     }
 418   extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
 419
 420   if (extra_flags)
 421     SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
 422 }
 423
 424 /* Only mark the object as being small data area addressable if
 425    it hasn't been explicitly marked with a code model.
 426
 427    The user can explicitly put an object in the small data area with the
 428    section attribute.  If the object is in sdata/sbss and marked with a
 429    code model do both [put the object in .sdata and mark it as being
 430    addressed with a specific code model - don't mark it as being addressed
 431    with an SDA reloc though].  This is ok and might be useful at times.  If
 432    the object doesn't fit the linker will give an error.  */
 433
 434 static bool
 435 m32r_in_small_data_p (tree decl)
 436 {
 437   tree section;
 438
 439   if (TREE_CODE (decl) != VAR_DECL)
 440     return false;
 441
 442   if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
 443     return false;
 444
 445   section = DECL_SECTION_NAME (decl);
 446   if (section)
 447     {
 448       char *name = (char *) TREE_STRING_POINTER (section);
 449       if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
 450         return true;
 451     }
 452   else
 453     {
 454       if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
 455         {
 456           int size = int_size_in_bytes (TREE_TYPE (decl));
 457
 458           if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
 459             return true;
 460         }
 461     }
 462
 463   return false;
 464 }
 465
 466 /* Do anything needed before RTL is emitted for each function.  */
 467
 468 void
 469 m32r_init_expanders (void)
 470 {
 471   /* ??? At one point there was code here.  The function is left in
 472      to make it easy to experiment.  */
 473 }
 474 \f
 475 /* Acceptable arguments to the call insn.  */
 476
 477 int
 478 call_address_operand (rtx op, enum machine_mode mode)
 479 {
 480   return symbolic_operand (op, mode);
 481
 482 /* Constants and values in registers are not OK, because
 483    the m32r BL instruction can only support PC relative branching.  */
 484 }
 485
 486 int
 487 call_operand (rtx op, enum machine_mode mode)
 488 {
 489   if (GET_CODE (op) != MEM)
 490     return 0;
 491   op = XEXP (op, 0);
 492   return call_address_operand (op, mode);
 493 }
 494
 495 /* Returns 1 if OP is a symbol reference.  */
 496
 497 int
 498 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 499 {
 500   switch (GET_CODE (op))
 501     {
 502     case SYMBOL_REF:
 503     case LABEL_REF:
 504     case CONST :
 505       return 1;
 506
 507     default:
 508       return 0;
 509     }
 510 }
 511
 512 /* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
 513
 514 int
 515 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 516 {
 517   if (! TARGET_SDATA_USE)
 518     return 0;
 519
 520   if (GET_CODE (op) == SYMBOL_REF)
 521     return SYMBOL_REF_SMALL_P (op);
 522
 523   if (GET_CODE (op) == CONST
 524       && GET_CODE (XEXP (op, 0)) == PLUS
 525       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 526       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 527       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 528     return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
 529
 530   return 0;
 531 }
 532
 533 /* Return 1 if OP is a symbol that can use 24 bit addressing.  */
 534
 535 int
 536 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 537 {
 538   rtx sym;
 539
 540   if (flag_pic)
 541     return 0;
 542
 543   if (GET_CODE (op) == LABEL_REF)
 544     return TARGET_ADDR24;
 545
 546   if (GET_CODE (op) == SYMBOL_REF)
 547     sym = op;
 548   else if (GET_CODE (op) == CONST
 549            && GET_CODE (XEXP (op, 0)) == PLUS
 550            && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 551            && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 552            && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 553     sym = XEXP (XEXP (op, 0), 0);
 554   else
 555     return 0;
 556
 557   if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
 558     return 1;
 559
 560   if (TARGET_ADDR24
 561       && (CONSTANT_POOL_ADDRESS_P (sym)
 562           || LIT_NAME_P (XSTR (sym, 0))))
 563     return 1;
 564
 565   return 0;
 566 }
 567
 568 /* Return 1 if OP is a symbol that needs 32 bit addressing.  */
 569
 570 int
 571 addr32_operand (rtx op, enum machine_mode mode)
 572 {
 573   rtx sym;
 574
 575   if (GET_CODE (op) == LABEL_REF)
 576     return TARGET_ADDR32;
 577
 578   if (GET_CODE (op) == SYMBOL_REF)
 579     sym = op;
 580   else if (GET_CODE (op) == CONST
 581            && GET_CODE (XEXP (op, 0)) == PLUS
 582            && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 583            && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 584            && ! flag_pic)
 585     sym = XEXP (XEXP (op, 0), 0);
 586   else
 587     return 0;
 588
 589   return (! addr24_operand (sym, mode)
 590           && ! small_data_operand (sym, mode));
 591 }
 592
 593 /* Return 1 if OP is a function that can be called with the `bl' insn.  */
 594
 595 int
 596 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 597 {
 598   if (flag_pic)
 599     return 1;
 600
 601   if (GET_CODE (op) == SYMBOL_REF)
 602     return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
 603
 604   return TARGET_CALL26;
 605 }
 606
 607 /* Returns 1 if OP is an acceptable operand for seth/add3.  */
 608
 609 int
 610 seth_add3_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 611 {
 612   if (flag_pic)
 613     return 0;
 614
 615   if (GET_CODE (op) == SYMBOL_REF
 616       || GET_CODE (op) == LABEL_REF)
 617     return 1;
 618
 619   if (GET_CODE (op) == CONST
 620       && GET_CODE (XEXP (op, 0)) == PLUS
 621       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 622       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 623       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 624     return 1;
 625
 626   return 0;
 627 }
 628
 629 /* Return true if OP is a signed 8 bit immediate value.  */
 630
 631 int
 632 int8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 633 {
 634   if (GET_CODE (op) != CONST_INT)
 635     return 0;
 636   return INT8_P (INTVAL (op));
 637 }
 638
 639 /* Return true if OP is a signed 16 bit immediate value
 640    useful in comparisons.  */
 641
 642 int
 643 cmp_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 644 {
 645   if (GET_CODE (op) != CONST_INT)
 646     return 0;
 647   return CMP_INT16_P (INTVAL (op));
 648 }
 649
 650 /* Return true if OP is an unsigned 16 bit immediate value.  */
 651
 652 int
 653 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 654 {
 655   if (GET_CODE (op) != CONST_INT)
 656     return 0;
 657   return UINT16_P (INTVAL (op));
 658 }
 659
 660 /* Return true if OP is a register or signed 16 bit value.  */
 661
 662 int
 663 reg_or_int16_operand (rtx op, enum machine_mode mode)
 664 {
 665   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 666     return register_operand (op, mode);
 667   if (GET_CODE (op) != CONST_INT)
 668     return 0;
 669   return INT16_P (INTVAL (op));
 670 }
 671
 672 /* Return true if OP is a register or an unsigned 16 bit value.  */
 673
 674 int
 675 reg_or_uint16_operand (rtx op, enum machine_mode mode)
 676 {
 677   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 678     return register_operand (op, mode);
 679   if (GET_CODE (op) != CONST_INT)
 680     return 0;
 681   return UINT16_P (INTVAL (op));
 682 }
 683
 684 /* Return true if OP is a register or an integer value that can be
 685    used is SEQ/SNE.  We can use either XOR of the value or ADD of
 686    the negative of the value for the constant.  Don't allow 0,
 687    because that is special cased.  */
 688
 689 int
 690 reg_or_eq_int16_operand (rtx op, enum machine_mode mode)
 691 {
 692   HOST_WIDE_INT value;
 693
 694   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 695     return register_operand (op, mode);
 696
 697   if (GET_CODE (op) != CONST_INT)
 698     return 0;
 699
 700   value = INTVAL (op);
 701   return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
 702 }
 703
 704 /* Return true if OP is a register or signed 16 bit value for compares.  */
 705
 706 int
 707 reg_or_cmp_int16_operand (rtx op, enum machine_mode mode)
 708 {
 709   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 710     return register_operand (op, mode);
 711   if (GET_CODE (op) != CONST_INT)
 712     return 0;
 713   return CMP_INT16_P (INTVAL (op));
 714 }
 715
 716 /* Return true if OP is a register or the constant 0.  */
 717
 718 int
 719 reg_or_zero_operand (rtx op, enum machine_mode mode)
 720 {
 721   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 722     return register_operand (op, mode);
 723
 724   if (GET_CODE (op) != CONST_INT)
 725     return 0;
 726
 727   return INTVAL (op) == 0;
 728 }
 729
 730 /* Return true if OP is a const_int requiring two instructions to load.  */
 731
 732 int
 733 two_insn_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 734 {
 735   if (GET_CODE (op) != CONST_INT)
 736     return 0;
 737   if (INT16_P (INTVAL (op))
 738       || UINT24_P (INTVAL (op))
 739       || UPPER16_P (INTVAL (op)))
 740     return 0;
 741   return 1;
 742 }
 743
 744 /* Return true if OP is an acceptable argument for a single word
 745    move source.  */
 746
 747 int
 748 move_src_operand (rtx op, enum machine_mode mode)
 749 {
 750   switch (GET_CODE (op))
 751     {
 752     case LABEL_REF :
 753     case SYMBOL_REF :
 754     case CONST :
 755       return addr24_operand (op, mode);
 756     case CONST_INT :
 757       /* ??? We allow more cse opportunities if we only allow constants
 758          loadable with one insn, and split the rest into two.  The instances
 759          where this would help should be rare and the current way is
 760          simpler.  */
 761       if (HOST_BITS_PER_WIDE_INT > 32)
 762         {
 763           HOST_WIDE_INT rest = INTVAL (op) >> 31;
 764           return (rest == 0 || rest == -1);
 765         }
 766       else
 767         return 1;
 768     case CONST_DOUBLE :
 769       if (mode == SFmode)
 770         return 1;
 771       else if (mode == SImode)
 772         {
 773           /* Large unsigned constants are represented as const_double's.  */
 774           unsigned HOST_WIDE_INT low, high;
 775
 776           low = CONST_DOUBLE_LOW (op);
 777           high = CONST_DOUBLE_HIGH (op);
 778           return high == 0 && low <= (unsigned) 0xffffffff;
 779         }
 780       else
 781         return 0;
 782     case REG :
 783       return register_operand (op, mode);
 784     case SUBREG :
 785       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 786          pseudo-reg and is now a stack slot.  */
 787       if (GET_CODE (SUBREG_REG (op)) == MEM)
 788         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 789       else
 790         return register_operand (op, mode);
 791     case MEM :
 792       if (GET_CODE (XEXP (op, 0)) == PRE_INC
 793           || GET_CODE (XEXP (op, 0)) == PRE_DEC)
 794         return 0;               /* loads can't do pre-{inc,dec} */
 795       return address_operand (XEXP (op, 0), mode);
 796     default :
 797       return 0;
 798     }
 799 }
 800
 801 /* Return true if OP is an acceptable argument for a double word
 802    move source.  */
 803
 804 int
 805 move_double_src_operand (rtx op, enum machine_mode mode)
 806 {
 807   switch (GET_CODE (op))
 808     {
 809     case CONST_INT :
 810     case CONST_DOUBLE :
 811       return 1;
 812     case REG :
 813       return register_operand (op, mode);
 814     case SUBREG :
 815       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 816          pseudo-reg and is now a stack slot.  */
 817       if (GET_CODE (SUBREG_REG (op)) == MEM)
 818         return move_double_src_operand (SUBREG_REG (op), mode);
 819       else
 820         return register_operand (op, mode);
 821     case MEM :
 822       /* Disallow auto inc/dec for now.  */
 823       if (GET_CODE (XEXP (op, 0)) == PRE_DEC
 824           || GET_CODE (XEXP (op, 0)) == PRE_INC)
 825         return 0;
 826       return address_operand (XEXP (op, 0), mode);
 827     default :
 828       return 0;
 829     }
 830 }
 831
 832 /* Return true if OP is an acceptable argument for a move destination.  */
 833
 834 int
 835 move_dest_operand (rtx op, enum machine_mode mode)
 836 {
 837   switch (GET_CODE (op))
 838     {
 839     case REG :
 840       return register_operand (op, mode);
 841     case SUBREG :
 842       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 843          pseudo-reg and is now a stack slot.  */
 844       if (GET_CODE (SUBREG_REG (op)) == MEM)
 845         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 846       else
 847         return register_operand (op, mode);
 848     case MEM :
 849       if (GET_CODE (XEXP (op, 0)) == POST_INC)
 850         return 0;               /* stores can't do post inc */
 851       return address_operand (XEXP (op, 0), mode);
 852     default :
 853       return 0;
 854     }
 855 }
 856
 857 /* Return 1 if OP is a DImode const we want to handle inline.
 858    This must match the code in the movdi pattern.
 859    It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */
 860
 861 int
 862 easy_di_const (rtx op)
 863 {
 864   rtx high_rtx, low_rtx;
 865   HOST_WIDE_INT high, low;
 866
 867   split_double (op, &high_rtx, &low_rtx);
 868   high = INTVAL (high_rtx);
 869   low = INTVAL (low_rtx);
 870   /* Pick constants loadable with 2 16 bit `ldi' insns.  */
 871   if (high >= -128 && high <= 127
 872       && low >= -128 && low <= 127)
 873     return 1;
 874   return 0;
 875 }
 876
 877 /* Return 1 if OP is a DFmode const we want to handle inline.
 878    This must match the code in the movdf pattern.
 879    It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */
 880
 881 int
 882 easy_df_const (rtx op)
 883 {
 884   REAL_VALUE_TYPE r;
 885   long l[2];
 886
 887   REAL_VALUE_FROM_CONST_DOUBLE (r, op);
 888   REAL_VALUE_TO_TARGET_DOUBLE (r, l);
 889   if (l[0] == 0 && l[1] == 0)
 890     return 1;
 891   if ((l[0] & 0xffff) == 0 && l[1] == 0)
 892     return 1;
 893   return 0;
 894 }
 895
 896 /* Return 1 if OP is an EQ or NE comparison operator.  */
 897
 898 int
 899 eqne_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 900 {
 901   enum rtx_code code = GET_CODE (op);
 902
 903   return (code == EQ || code == NE);
 904 }
 905
 906 /* Return 1 if OP is a signed comparison operator.  */
 907
 908 int
 909 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 910 {
 911   enum rtx_code code = GET_CODE (op);
 912
 913   return (COMPARISON_P (op)
 914           && (code == EQ || code == NE
 915               || code == LT || code == LE || code == GT || code == GE));
 916 }
 917
 918 /* Return 1 if OP is (mem (reg ...)).
 919    This is used in insn length calcs.  */
 920
 921 int
 922 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 923 {
 924   return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
 925 }
 926
 927 /* Return true if OP is an acceptable input argument for a zero/sign extend
 928    operation.  */
 929
 930 int
 931 extend_operand (rtx op, enum machine_mode mode)
 932 {
 933   rtx addr;
 934
 935   switch (GET_CODE (op))
 936     {
 937     case REG :
 938     case SUBREG :
 939       return register_operand (op, mode);
 940
 941     case MEM :
 942       addr = XEXP (op, 0);
 943       if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
 944         return 0;               /* loads can't do pre inc/pre dec */
 945
 946       return address_operand (addr, mode);
 947
 948     default :
 949       return 0;
 950     }
 951 }
 952
 953 /* Return nonzero if the operand is an insn that is a small insn.
 954    Allow const_int 0 as well, which is a placeholder for NOP slots.  */
 955
 956 int
 957 small_insn_p (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 958 {
 959   if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
 960     return 1;
 961
 962   if (! INSN_P (op))
 963     return 0;
 964
 965   return get_attr_length (op) == 2;
 966 }
 967
 968 /* Return nonzero if the operand is an insn that is a large insn.  */
 969
 970 int
 971 large_insn_p (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 972 {
 973   if (! INSN_P (op))
 974     return 0;
 975
 976   return get_attr_length (op) != 2;
 977 }
 978
 979 /* Return nonzero if TYPE must be passed by indirect reference.  */
 980
 981 static bool
 982 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
 983                         enum machine_mode mode, tree type,
 984                         bool named ATTRIBUTE_UNUSED)
 985 {
 986   int size;
 987
 988   if (type)
 989     size = int_size_in_bytes (type);
 990   else
 991     size = GET_MODE_SIZE (mode);
 992
 993   return (size < 0 || size > 8);
 994 }
 995 \f
 996 /* Comparisons.  */
 997
 998 /* X and Y are two things to compare using CODE.  Emit the compare insn and
 999    return the rtx for compare [arg0 of the if_then_else].
1000    If need_compare is true then the comparison insn must be generated, rather
1001    than being subsumed into the following branch instruction.  */
1002
1003 rtx
1004 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
1005 {
1006   enum rtx_code compare_code;
1007   enum rtx_code branch_code;
1008   rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1009   int must_swap = 0;
1010
1011   switch (code)
1012     {
1013     case EQ:  compare_code = EQ;  branch_code = NE; break;
1014     case NE:  compare_code = EQ;  branch_code = EQ; break;
1015     case LT:  compare_code = LT;  branch_code = NE; break;
1016     case LE:  compare_code = LT;  branch_code = EQ; must_swap = 1; break;
1017     case GT:  compare_code = LT;  branch_code = NE; must_swap = 1; break;
1018     case GE:  compare_code = LT;  branch_code = EQ; break;
1019     case LTU: compare_code = LTU; branch_code = NE; break;
1020     case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1021     case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1022     case GEU: compare_code = LTU; branch_code = EQ; break;
1023
1024     default:
1025       abort ();
1026     }
1027
1028   if (need_compare)
1029     {
1030       switch (compare_code)
1031         {
1032         case EQ:
1033           if (GET_CODE (y) == CONST_INT
1034               && CMP_INT16_P (INTVAL (y))               /* Reg equal to small const.  */
1035               && y != const0_rtx)
1036             {
1037               rtx tmp = gen_reg_rtx (SImode);
1038
1039               emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
1040               x = tmp;
1041               y = const0_rtx;
1042             }
1043           else if (CONSTANT_P (y))                      /* Reg equal to const.  */
1044             {
1045               rtx tmp = force_reg (GET_MODE (x), y);
1046               y = tmp;
1047             }
1048
1049           if (register_operand (y, SImode)              /* Reg equal to reg.  */
1050               || y == const0_rtx)                       /* Reg equal to zero.  */
1051             {
1052               emit_insn (gen_cmp_eqsi_insn (x, y));
1053
1054               return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1055             }
1056           break;
1057
1058         case LT:
1059           if (register_operand (y, SImode)
1060               || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1061             {
1062               rtx tmp = gen_reg_rtx (SImode);         /* Reg compared to reg.  */
1063
1064               switch (code)
1065                 {
1066                 case LT:
1067                   emit_insn (gen_cmp_ltsi_insn (x, y));
1068                   code = EQ;
1069                   break;
1070                 case LE:
1071                   if (y == const0_rtx)
1072                     tmp = const1_rtx;
1073                   else
1074                     emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1075                   emit_insn (gen_cmp_ltsi_insn (x, tmp));
1076                   code = EQ;
1077                   break;
1078                 case GT:
1079                   if (GET_CODE (y) == CONST_INT)
1080                     tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
1081                   else
1082                     emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1083                   emit_insn (gen_cmp_ltsi_insn (x, tmp));
1084                   code = NE;
1085                   break;
1086                 case GE:
1087                   emit_insn (gen_cmp_ltsi_insn (x, y));
1088                   code = NE;
1089                   break;
1090                 default:
1091                   abort ();
1092                 }
1093
1094               return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1095             }
1096           break;
1097
1098         case LTU:
1099           if (register_operand (y, SImode)
1100               || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1101             {
1102               rtx tmp = gen_reg_rtx (SImode);         /* Reg (unsigned) compared to reg.  */
1103
1104               switch (code)
1105                 {
1106                 case LTU:
1107                   emit_insn (gen_cmp_ltusi_insn (x, y));
1108                   code = EQ;
1109                   break;
1110                 case LEU:
1111                   if (y == const0_rtx)
1112                     tmp = const1_rtx;
1113                   else
1114                     emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1115                   emit_insn (gen_cmp_ltusi_insn (x, tmp));
1116                   code = EQ;
1117                   break;
1118                 case GTU:
1119                   if (GET_CODE (y) == CONST_INT)
1120                     tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
1121                   else
1122                     emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1123                   emit_insn (gen_cmp_ltusi_insn (x, tmp));
1124                   code = NE;
1125                   break;
1126                 case GEU:
1127                   emit_insn (gen_cmp_ltusi_insn (x, y));
1128                   code = NE;
1129                   break;
1130                 default:
1131                   abort();
1132                 }
1133
1134               return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1135             }
1136           break;
1137
1138         default:
1139           abort();
1140         }
1141     }
1142   else
1143     {
1144       /* Reg/reg equal comparison.  */
1145       if (compare_code == EQ
1146           && register_operand (y, SImode))
1147         return gen_rtx_fmt_ee (code, CCmode, x, y);
1148
1149       /* Reg/zero signed comparison.  */
1150       if ((compare_code == EQ || compare_code == LT)
1151           && y == const0_rtx)
1152         return gen_rtx_fmt_ee (code, CCmode, x, y);
1153
1154       /* Reg/smallconst equal comparison.  */
1155       if (compare_code == EQ
1156           && GET_CODE (y) == CONST_INT
1157           && CMP_INT16_P (INTVAL (y)))
1158         {
1159           rtx tmp = gen_reg_rtx (SImode);
1160
1161           emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
1162           return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
1163         }
1164
1165       /* Reg/const equal comparison.  */
1166       if (compare_code == EQ
1167           && CONSTANT_P (y))
1168         {
1169           rtx tmp = force_reg (GET_MODE (x), y);
1170
1171           return gen_rtx_fmt_ee (code, CCmode, x, tmp);
1172         }
1173     }
1174
1175   if (CONSTANT_P (y))
1176     {
1177       if (must_swap)
1178         y = force_reg (GET_MODE (x), y);
1179       else
1180         {
1181           int ok_const = reg_or_int16_operand (y, GET_MODE (y));
1182
1183           if (! ok_const)
1184             y = force_reg (GET_MODE (x), y);
1185         }
1186     }
1187
1188   switch (compare_code)
1189     {
1190     case EQ :
1191       emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1192       break;
1193     case LT :
1194       emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1195       break;
1196     case LTU :
1197       emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1198       break;
1199
1200     default:
1201       abort ();
1202     }
1203
1204   return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1205 }
1206 \f
1207 /* Split a 2 word move (DI or DF) into component parts.  */
1208
1209 rtx
1210 gen_split_move_double (rtx operands[])
1211 {
1212   enum machine_mode mode = GET_MODE (operands[0]);
1213   rtx dest = operands[0];
1214   rtx src  = operands[1];
1215   rtx val;
1216
1217   /* We might have (SUBREG (MEM)) here, so just get rid of the
1218      subregs to make this code simpler.  It is safe to call
1219      alter_subreg any time after reload.  */
1220   if (GET_CODE (dest) == SUBREG)
1221     alter_subreg (&dest);
1222   if (GET_CODE (src) == SUBREG)
1223     alter_subreg (&src);
1224
1225   start_sequence ();
1226   if (GET_CODE (dest) == REG)
1227     {
1228       int dregno = REGNO (dest);
1229
1230       /* Reg = reg.  */
1231       if (GET_CODE (src) == REG)
1232         {
1233           int sregno = REGNO (src);
1234
1235           int reverse = (dregno == sregno + 1);
1236
1237           /* We normally copy the low-numbered register first.  However, if
1238              the first register operand 0 is the same as the second register of
1239              operand 1, we must copy in the opposite order.  */
1240           emit_insn (gen_rtx_SET (VOIDmode,
1241                                   operand_subword (dest, reverse, TRUE, mode),
1242                                   operand_subword (src,  reverse, TRUE, mode)));
1243
1244           emit_insn (gen_rtx_SET (VOIDmode,
1245                                   operand_subword (dest, !reverse, TRUE, mode),
1246                                   operand_subword (src,  !reverse, TRUE, mode)));
1247         }
1248
1249       /* Reg = constant.  */
1250       else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1251         {
1252           rtx words[2];
1253           split_double (src, &words[0], &words[1]);
1254           emit_insn (gen_rtx_SET (VOIDmode,
1255                                   operand_subword (dest, 0, TRUE, mode),
1256                                   words[0]));
1257
1258           emit_insn (gen_rtx_SET (VOIDmode,
1259                                   operand_subword (dest, 1, TRUE, mode),
1260                                   words[1]));
1261         }
1262
1263       /* Reg = mem.  */
1264       else if (GET_CODE (src) == MEM)
1265         {
1266           /* If the high-address word is used in the address, we must load it
1267              last.  Otherwise, load it first.  */
1268           int reverse
1269             = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1270
1271           /* We used to optimize loads from single registers as
1272
1273                 ld r1,r3+; ld r2,r3
1274
1275              if r3 were not used subsequently.  However, the REG_NOTES aren't
1276              propagated correctly by the reload phase, and it can cause bad
1277              code to be generated.  We could still try:
1278
1279                 ld r1,r3+; ld r2,r3; addi r3,-4
1280
1281              which saves 2 bytes and doesn't force longword alignment.  */
1282           emit_insn (gen_rtx_SET (VOIDmode,
1283                                   operand_subword (dest, reverse, TRUE, mode),
1284                                   adjust_address (src, SImode,
1285                                                   reverse * UNITS_PER_WORD)));
1286
1287           emit_insn (gen_rtx_SET (VOIDmode,
1288                                   operand_subword (dest, !reverse, TRUE, mode),
1289                                   adjust_address (src, SImode,
1290                                                   !reverse * UNITS_PER_WORD)));
1291         }
1292       else
1293         abort ();
1294     }
1295
1296   /* Mem = reg.  */
1297   /* We used to optimize loads from single registers as
1298
1299         st r1,r3; st r2,+r3
1300
1301      if r3 were not used subsequently.  However, the REG_NOTES aren't
1302      propagated correctly by the reload phase, and it can cause bad
1303      code to be generated.  We could still try:
1304
1305         st r1,r3; st r2,+r3; addi r3,-4
1306
1307      which saves 2 bytes and doesn't force longword alignment.  */
1308   else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1309     {
1310       emit_insn (gen_rtx_SET (VOIDmode,
1311                               adjust_address (dest, SImode, 0),
1312                               operand_subword (src, 0, TRUE, mode)));
1313
1314       emit_insn (gen_rtx_SET (VOIDmode,
1315                               adjust_address (dest, SImode, UNITS_PER_WORD),
1316                               operand_subword (src, 1, TRUE, mode)));
1317     }
1318
1319   else
1320     abort ();
1321
1322   val = get_insns ();
1323   end_sequence ();
1324   return val;
1325 }
1326
1327 \f
1328 static int
1329 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1330                         tree type, bool named ATTRIBUTE_UNUSED)
1331 {
1332   int words;
1333   unsigned int size =
1334     (((mode == BLKmode && type)
1335       ? (unsigned int) int_size_in_bytes (type)
1336       : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1337     / UNITS_PER_WORD;
1338
1339   if (*cum >= M32R_MAX_PARM_REGS)
1340     words = 0;
1341   else if (*cum + size > M32R_MAX_PARM_REGS)
1342     words = (*cum + size) - M32R_MAX_PARM_REGS;
1343   else
1344     words = 0;
1345
1346   return words * UNITS_PER_WORD;
1347 }
1348
1349 /* Worker function for TARGET_RETURN_IN_MEMORY.  */
1350
1351 static bool
1352 m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1353 {
1354   return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1355 }
1356
1357 /* Do any needed setup for a variadic function.  For the M32R, we must
1358    create a register parameter block, and then copy any anonymous arguments
1359    in registers to memory.
1360
1361    CUM has not been updated for the last named argument which has type TYPE
1362    and mode MODE, and we rely on this fact.  */
1363
1364 static void
1365 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1366                              tree type, int *pretend_size, int no_rtl)
1367 {
1368   int first_anon_arg;
1369
1370   if (no_rtl)
1371     return;
1372
1373   /* All BLKmode values are passed by reference.  */
1374   if (mode == BLKmode)
1375     abort ();
1376
1377   first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1378                     + ROUND_ADVANCE_ARG (mode, type));
1379
1380   if (first_anon_arg < M32R_MAX_PARM_REGS)
1381     {
1382       /* Note that first_reg_offset < M32R_MAX_PARM_REGS.  */
1383       int first_reg_offset = first_anon_arg;
1384       /* Size in words to "pretend" allocate.  */
1385       int size = M32R_MAX_PARM_REGS - first_reg_offset;
1386       rtx regblock;
1387
1388       regblock = gen_rtx_MEM (BLKmode,
1389                               plus_constant (arg_pointer_rtx,
1390                                              FIRST_PARM_OFFSET (0)));
1391       set_mem_alias_set (regblock, get_varargs_alias_set ());
1392       move_block_from_reg (first_reg_offset, regblock, size);
1393
1394       *pretend_size = (size * UNITS_PER_WORD);
1395     }
1396 }
1397
1398 \f
1399 /* Return true if INSN is real instruction bearing insn.  */
1400
1401 static int
1402 m32r_is_insn (rtx insn)
1403 {
1404   return (INSN_P (insn)
1405           && GET_CODE (PATTERN (insn)) != USE
1406           && GET_CODE (PATTERN (insn)) != CLOBBER
1407           && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1408 }
1409
1410 /* Increase the priority of long instructions so that the
1411    short instructions are scheduled ahead of the long ones.  */
1412
1413 static int
1414 m32r_adjust_priority (rtx insn, int priority)
1415 {
1416   if (m32r_is_insn (insn)
1417       && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1418     priority <<= 3;
1419
1420   return priority;
1421 }
1422
1423 \f
1424 /* Indicate how many instructions can be issued at the same time.
1425    This is sort of a lie.  The m32r can issue only 1 long insn at
1426    once, but it can issue 2 short insns.  The default therefore is
1427    set at 2, but this can be overridden by the command line option
1428    -missue-rate=1.  */
1429
1430 static int
1431 m32r_issue_rate (void)
1432 {
1433   return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1434 }
1435 \f
1436 /* Cost functions.  */
1437
1438 static bool
1439 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1440 {
1441   switch (code)
1442     {
1443       /* Small integers are as cheap as registers.  4 byte values can be
1444          fetched as immediate constants - let's give that the cost of an
1445          extra insn.  */
1446     case CONST_INT:
1447       if (INT16_P (INTVAL (x)))
1448         {
1449           *total = 0;
1450           return true;
1451         }
1452       /* FALLTHRU */
1453
1454     case CONST:
1455     case LABEL_REF:
1456     case SYMBOL_REF:
1457       *total = COSTS_N_INSNS (1);
1458       return true;
1459
1460     case CONST_DOUBLE:
1461       {
1462         rtx high, low;
1463
1464         split_double (x, &high, &low);
1465         *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1466                                 + !INT16_P (INTVAL (low)));
1467         return true;
1468       }
1469
1470     case MULT:
1471       *total = COSTS_N_INSNS (3);
1472       return true;
1473
1474     case DIV:
1475     case UDIV:
1476     case MOD:
1477     case UMOD:
1478       *total = COSTS_N_INSNS (10);
1479       return true;
1480
1481     default:
1482       return false;
1483     }
1484 }
1485 \f
1486 /* Type of function DECL.
1487
1488    The result is cached.  To reset the cache at the end of a function,
1489    call with DECL = NULL_TREE.  */
1490
1491 enum m32r_function_type
1492 m32r_compute_function_type (tree decl)
1493 {
1494   /* Cached value.  */
1495   static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1496   /* Last function we were called for.  */
1497   static tree last_fn = NULL_TREE;
1498
1499   /* Resetting the cached value?  */
1500   if (decl == NULL_TREE)
1501     {
1502       fn_type = M32R_FUNCTION_UNKNOWN;
1503       last_fn = NULL_TREE;
1504       return fn_type;
1505     }
1506
1507   if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1508     return fn_type;
1509
1510   /* Compute function type.  */
1511   fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1512              ? M32R_FUNCTION_INTERRUPT
1513              : M32R_FUNCTION_NORMAL);
1514
1515   last_fn = decl;
1516   return fn_type;
1517 }
1518 \f/* Function prologue/epilogue handlers.  */
1519
1520 /* M32R stack frames look like:
1521
1522              Before call                       After call
1523         +-----------------------+       +-----------------------+
1524         |                       |       |                       |
1525    high |  local variables,     |       |  local variables,     |
1526    mem  |  reg save area, etc.  |       |  reg save area, etc.  |
1527         |                       |       |                       |
1528         +-----------------------+       +-----------------------+
1529         |                       |       |                       |
1530         |  arguments on stack.  |       |  arguments on stack.  |
1531         |                       |       |                       |
1532   SP+0->+-----------------------+       +-----------------------+
1533                                         |  reg parm save area,  |
1534                                         |  only created for     |
1535                                         |  variable argument    |
1536                                         |  functions            |
1537                                         +-----------------------+
1538                                         |   previous frame ptr  |
1539                                         +-----------------------+
1540                                         |                       |
1541                                         |  register save area   |
1542                                         |                       |
1543                                         +-----------------------+
1544                                         |    return address     |
1545                                         +-----------------------+
1546                                         |                       |
1547                                         |  local variables      |
1548                                         |                       |
1549                                         +-----------------------+
1550                                         |                       |
1551                                         |  alloca allocations   |
1552                                         |                       |
1553                                         +-----------------------+
1554                                         |                       |
1555    low                                  |  arguments on stack   |
1556    memory                               |                       |
1557                                   SP+0->+-----------------------+
1558
1559 Notes:
1560 1) The "reg parm save area" does not exist for non variable argument fns.
1561 2) The "reg parm save area" can be eliminated completely if we saved regs
1562    containing anonymous args separately but that complicates things too
1563    much (so it's not done).
1564 3) The return address is saved after the register save area so as to have as
1565    many insns as possible between the restoration of `lr' and the `jmp lr'.  */
1566
1567 /* Structure to be filled in by m32r_compute_frame_size with register
1568    save masks, and offsets for the current function.  */
1569 struct m32r_frame_info
1570 {
1571   unsigned int total_size;      /* # bytes that the entire frame takes up.  */
1572   unsigned int extra_size;      /* # bytes of extra stuff.  */
1573   unsigned int pretend_size;    /* # bytes we push and pretend caller did.  */
1574   unsigned int args_size;       /* # bytes that outgoing arguments take up.  */
1575   unsigned int reg_size;        /* # bytes needed to store regs.  */
1576   unsigned int var_size;        /* # bytes that variables take up.  */
1577   unsigned int gmask;           /* Mask of saved gp registers.  */
1578   unsigned int save_fp;         /* Nonzero if fp must be saved.  */
1579   unsigned int save_lr;         /* Nonzero if lr (return addr) must be saved.  */
1580   int          initialized;     /* Nonzero if frame size already calculated.  */
1581 };
1582
1583 /* Current frame information calculated by m32r_compute_frame_size.  */
1584 static struct m32r_frame_info current_frame_info;
1585
1586 /* Zero structure to initialize current_frame_info.  */
1587 static struct m32r_frame_info zero_frame_info;
1588
1589 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1590 #define RETURN_ADDR_MASK   (1 << (RETURN_ADDR_REGNUM))
1591
1592 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1593    The return address and frame pointer are treated separately.
1594    Don't consider them here.  */
1595 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1596   ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1597   && (regs_ever_live[regno] && (!call_really_used_regs[regno] || interrupt_p)))
1598
1599 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1600 #define MUST_SAVE_RETURN_ADDR   (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1601
1602 #define SHORT_INSN_SIZE 2       /* Size of small instructions.  */
1603 #define LONG_INSN_SIZE 4        /* Size of long instructions.  */
1604
1605 /* Return the bytes needed to compute the frame pointer from the current
1606    stack pointer.
1607
1608    SIZE is the size needed for local variables.  */
1609
1610 unsigned int
1611 m32r_compute_frame_size (int size)      /* # of var. bytes allocated.  */
1612 {
1613   int regno;
1614   unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1615   unsigned int reg_size, frame_size;
1616   unsigned int gmask;
1617   enum m32r_function_type fn_type;
1618   int interrupt_p;
1619   int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1620
1621   var_size      = M32R_STACK_ALIGN (size);
1622   args_size     = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1623   pretend_size  = current_function_pretend_args_size;
1624   extra_size    = FIRST_PARM_OFFSET (0);
1625   total_size    = extra_size + pretend_size + args_size + var_size;
1626   reg_size      = 0;
1627   gmask         = 0;
1628
1629   /* See if this is an interrupt handler.  Call used registers must be saved
1630      for them too.  */
1631   fn_type = m32r_compute_function_type (current_function_decl);
1632   interrupt_p = M32R_INTERRUPT_P (fn_type);
1633
1634   /* Calculate space needed for registers.  */
1635   for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1636     {
1637       if (MUST_SAVE_REGISTER (regno, interrupt_p)
1638           || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1639         {
1640           reg_size += UNITS_PER_WORD;
1641           gmask |= 1 << regno;
1642         }
1643     }
1644
1645   current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1646   current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1647
1648   reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1649                * UNITS_PER_WORD);
1650   total_size += reg_size;
1651
1652   /* ??? Not sure this is necessary, and I don't think the epilogue
1653      handler will do the right thing if this changes total_size.  */
1654   total_size = M32R_STACK_ALIGN (total_size);
1655
1656   frame_size = total_size - (pretend_size + reg_size);
1657
1658   /* Save computed information.  */
1659   current_frame_info.total_size   = total_size;
1660   current_frame_info.extra_size   = extra_size;
1661   current_frame_info.pretend_size = pretend_size;
1662   current_frame_info.var_size     = var_size;
1663   current_frame_info.args_size    = args_size;
1664   current_frame_info.reg_size     = reg_size;
1665   current_frame_info.gmask        = gmask;
1666   current_frame_info.initialized  = reload_completed;
1667
1668   /* Ok, we're done.  */
1669   return total_size;
1670 }
1671 \f
1672 /* The table we use to reference PIC data.  */
1673 static rtx global_offset_table;
1674
1675 static void
1676 m32r_reload_lr (rtx sp, int size)
1677 {
1678   rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1679
1680   if (size == 0)
1681     emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1682   else if (size <= 32768)
1683     emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1684                                            gen_rtx_PLUS (Pmode, sp,
1685                                                          GEN_INT (size)))));
1686   else
1687     {
1688       rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1689
1690       emit_insn (gen_movsi (tmp, GEN_INT (size)));
1691       emit_insn (gen_addsi3 (tmp, tmp, sp));
1692       emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1693     }
1694
1695   emit_insn (gen_rtx_USE (VOIDmode, lr));
1696 }
1697
1698 void
1699 m32r_load_pic_register (void)
1700 {
1701   global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1702   emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1703                          GEN_INT (TARGET_MODEL_SMALL)));
1704
1705   /* Need to emit this whether or not we obey regdecls,
1706      since setjmp/longjmp can cause life info to screw up.  */
1707   emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1708 }
1709
1710 /* Expand the m32r prologue as a series of insns.  */
1711
1712 void
1713 m32r_expand_prologue (void)
1714 {
1715   int regno;
1716   int frame_size;
1717   unsigned int gmask;
1718   int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1719
1720   if (! current_frame_info.initialized)
1721     m32r_compute_frame_size (get_frame_size ());
1722
1723   gmask = current_frame_info.gmask;
1724
1725   /* These cases shouldn't happen.  Catch them now.  */
1726   if (current_frame_info.total_size == 0 && gmask)
1727     abort ();
1728
1729   /* Allocate space for register arguments if this is a variadic function.  */
1730   if (current_frame_info.pretend_size != 0)
1731     {
1732       /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1733          the wrong result on a 64-bit host.  */
1734       HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1735       emit_insn (gen_addsi3 (stack_pointer_rtx,
1736                              stack_pointer_rtx,
1737                              GEN_INT (-pretend_size)));
1738     }
1739
1740   /* Save any registers we need to and set up fp.  */
1741   if (current_frame_info.save_fp)
1742     emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1743
1744   gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1745
1746   /* Save any needed call-saved regs (and call-used if this is an
1747      interrupt handler).  */
1748   for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1749     {
1750       if ((gmask & (1 << regno)) != 0)
1751         emit_insn (gen_movsi_push (stack_pointer_rtx,
1752                                    gen_rtx_REG (Pmode, regno)));
1753     }
1754
1755   if (current_frame_info.save_lr)
1756     emit_insn (gen_movsi_push (stack_pointer_rtx,
1757                                gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1758
1759   /* Allocate the stack frame.  */
1760   frame_size = (current_frame_info.total_size
1761                 - (current_frame_info.pretend_size
1762                    + current_frame_info.reg_size));
1763
1764   if (frame_size == 0)
1765     ; /* Nothing to do.  */
1766   else if (frame_size <= 32768)
1767     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1768                            GEN_INT (-frame_size)));
1769   else
1770     {
1771       rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1772
1773       emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1774       emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1775     }
1776
1777   if (frame_pointer_needed)
1778     emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1779
1780   if (current_function_profile)
1781     /* Push lr for mcount (form_pc, x).  */
1782     emit_insn (gen_movsi_push (stack_pointer_rtx,
1783                                gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1784
1785   if (pic_reg_used)
1786     {
1787       m32r_load_pic_register ();
1788       m32r_reload_lr (stack_pointer_rtx,
1789                       (current_function_profile ? 0 : frame_size));
1790     }
1791
1792   if (current_function_profile && !pic_reg_used)
1793     emit_insn (gen_blockage ());
1794 }
1795
1796 \f
1797 /* Set up the stack and frame pointer (if desired) for the function.
1798    Note, if this is changed, you need to mirror the changes in
1799    m32r_compute_frame_size which calculates the prolog size.  */
1800
1801 static void
1802 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1803 {
1804   enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1805
1806   /* If this is an interrupt handler, mark it as such.  */
1807   if (M32R_INTERRUPT_P (fn_type))
1808     fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1809
1810   if (! current_frame_info.initialized)
1811     m32r_compute_frame_size (size);
1812
1813   /* This is only for the human reader.  */
1814   fprintf (file,
1815            "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1816            ASM_COMMENT_START,
1817            current_frame_info.var_size,
1818            current_frame_info.reg_size / 4,
1819            current_frame_info.args_size,
1820            current_frame_info.extra_size);
1821 }
1822 \f
1823 /* Do any necessary cleanup after a function to restore stack, frame,
1824    and regs.  */
1825
1826 static void
1827 m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1828 {
1829   int regno;
1830   int noepilogue = FALSE;
1831   int total_size;
1832   enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1833
1834   /* This is only for the human reader.  */
1835   fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1836
1837   if (!current_frame_info.initialized)
1838     abort ();
1839   total_size = current_frame_info.total_size;
1840
1841   if (total_size == 0)
1842     {
1843       rtx insn = get_last_insn ();
1844
1845       /* If the last insn was a BARRIER, we don't have to write any code
1846          because a jump (aka return) was put there.  */
1847       if (GET_CODE (insn) == NOTE)
1848         insn = prev_nonnote_insn (insn);
1849       if (insn && GET_CODE (insn) == BARRIER)
1850         noepilogue = TRUE;
1851     }
1852
1853   if (!noepilogue)
1854     {
1855       unsigned int var_size = current_frame_info.var_size;
1856       unsigned int args_size = current_frame_info.args_size;
1857       unsigned int gmask = current_frame_info.gmask;
1858       int can_trust_sp_p = !current_function_calls_alloca;
1859       const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1860       const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1861
1862       /* The first thing to do is point the sp at the bottom of the register
1863          save area.  */
1864       if (can_trust_sp_p)
1865         {
1866           unsigned int reg_offset = var_size + args_size;
1867           if (reg_offset == 0)
1868             ; /* Nothing to do.  */
1869           else if (reg_offset < 128)
1870             fprintf (file, "\taddi %s,%s%d\n",
1871                      sp_str, IMMEDIATE_PREFIX, reg_offset);
1872           else if (reg_offset < 32768)
1873             fprintf (file, "\tadd3 %s,%s,%s%d\n",
1874                      sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1875           else
1876             fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1877                      reg_names[PROLOGUE_TMP_REGNUM],
1878                      IMMEDIATE_PREFIX, reg_offset,
1879                      sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1880         }
1881       else if (frame_pointer_needed)
1882         {
1883           unsigned int reg_offset = var_size + args_size;
1884
1885           if (reg_offset == 0)
1886             fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1887           else if (reg_offset < 32768)
1888             fprintf (file, "\tadd3 %s,%s,%s%d\n",
1889                      sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1890           else
1891             fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1892                      reg_names[PROLOGUE_TMP_REGNUM],
1893                      IMMEDIATE_PREFIX, reg_offset,
1894                      sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1895         }
1896       else
1897         abort ();
1898
1899       if (current_frame_info.save_lr)
1900         fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1901
1902       /* Restore any saved registers, in reverse order of course.  */
1903       gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1904       for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1905         {
1906           if ((gmask & (1L << regno)) != 0)
1907             fprintf (file, "\tpop %s\n", reg_names[regno]);
1908         }
1909
1910       if (current_frame_info.save_fp)
1911         fprintf (file, "\tpop %s\n", fp_str);
1912
1913       /* Remove varargs area if present.  */
1914       if (current_frame_info.pretend_size != 0)
1915         fprintf (file, "\taddi %s,%s%d\n",
1916                  sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1917
1918       /* Emit the return instruction.  */
1919       if (M32R_INTERRUPT_P (fn_type))
1920         fprintf (file, "\trte\n");
1921       else
1922         fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1923     }
1924
1925   /* Reset state info for each function.  */
1926   current_frame_info = zero_frame_info;
1927   m32r_compute_function_type (NULL_TREE);
1928 }
1929 \f
1930 /* Return nonzero if this function is known to have a null or 1 instruction
1931    epilogue.  */
1932
1933 int
1934 direct_return (void)
1935 {
1936   if (!reload_completed)
1937     return FALSE;
1938
1939   if (! current_frame_info.initialized)
1940     m32r_compute_frame_size (get_frame_size ());
1941
1942    return current_frame_info.total_size == 0;
1943 }
1944
1945 \f
1946 /* PIC.  */
1947
1948 int
1949 m32r_legitimate_pic_operand_p (rtx x)
1950 {
1951   if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1952     return 0;
1953
1954   if (GET_CODE (x) == CONST
1955       && GET_CODE (XEXP (x, 0)) == PLUS
1956       && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1957           || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1958       && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1959     return 0;
1960
1961   return 1;
1962 }
1963
1964 rtx
1965 m32r_legitimize_pic_address (rtx orig, rtx reg)
1966 {
1967 #ifdef DEBUG_PIC
1968   printf("m32r_legitimize_pic_address()\n");
1969 #endif
1970
1971   if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1972     {
1973       rtx pic_ref, address;
1974       rtx insn;
1975       int subregs = 0;
1976
1977       if (reg == 0)
1978         {
1979           if (reload_in_progress || reload_completed)
1980             abort ();
1981           else
1982             reg = gen_reg_rtx (Pmode);
1983
1984           subregs = 1;
1985         }
1986
1987       if (subregs)
1988         address = gen_reg_rtx (Pmode);
1989       else
1990         address = reg;
1991
1992       current_function_uses_pic_offset_table = 1;
1993
1994       if (GET_CODE (orig) == LABEL_REF
1995           || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1996         {
1997           emit_insn (gen_gotoff_load_addr (reg, orig));
1998           emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1999           return reg;
2000         }
2001
2002       emit_insn (gen_pic_load_addr (address, orig));
2003
2004       emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
2005       pic_ref = gen_const_mem (Pmode, address);
2006       insn = emit_move_insn (reg, pic_ref);
2007 #if 0
2008       /* Put a REG_EQUAL note on this insn, so that it can be optimized
2009          by loop.  */
2010       REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2011                   REG_NOTES (insn));
2012 #endif
2013       return reg;
2014     }
2015   else if (GET_CODE (orig) == CONST)
2016     {
2017       rtx base, offset;
2018
2019       if (GET_CODE (XEXP (orig, 0)) == PLUS
2020           && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
2021         return orig;
2022
2023       if (reg == 0)
2024         {
2025           if (reload_in_progress || reload_completed)
2026             abort ();
2027           else
2028             reg = gen_reg_rtx (Pmode);
2029         }
2030
2031       if (GET_CODE (XEXP (orig, 0)) == PLUS)
2032         {
2033           base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
2034           if (base == reg)
2035             offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
2036           else
2037             offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
2038         }
2039       else
2040         return orig;
2041
2042       if (GET_CODE (offset) == CONST_INT)
2043         {
2044           if (INT16_P (INTVAL (offset)))
2045             return plus_constant (base, INTVAL (offset));
2046           else if (! reload_in_progress && ! reload_completed)
2047             offset = force_reg (Pmode, offset);
2048           else
2049             /* If we reach here, then something is seriously wrong.  */
2050             abort ();
2051         }
2052
2053       return gen_rtx_PLUS (Pmode, base, offset);
2054     }
2055
2056   return orig;
2057 }
2058
2059 /* Emit special PIC prologues and epilogues.  */
2060
2061 void
2062 m32r_finalize_pic (void)
2063 {
2064   current_function_uses_pic_offset_table |= current_function_profile;
2065 }
2066 \f
2067 /* Nested function support.  */
2068
2069 /* Emit RTL insns to initialize the variable parts of a trampoline.
2070    FNADDR is an RTX for the address of the function's pure code.
2071    CXT is an RTX for the static chain value for the function.  */
2072
2073 void
2074 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
2075                             rtx fnaddr ATTRIBUTE_UNUSED,
2076                             rtx cxt ATTRIBUTE_UNUSED)
2077 {
2078 }
2079 \f
2080 static void
2081 m32r_file_start (void)
2082 {
2083   default_file_start ();
2084
2085   if (flag_verbose_asm)
2086     fprintf (asm_out_file,
2087              "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
2088              ASM_COMMENT_START, g_switch_value);
2089
2090   if (TARGET_LITTLE_ENDIAN)
2091     fprintf (asm_out_file, "\t.little\n");
2092 }
2093 \f
2094 /* Print operand X (an rtx) in assembler syntax to file FILE.
2095    CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2096    For `%' followed by punctuation, CODE is the punctuation and X is null.  */
2097
2098 void
2099 m32r_print_operand (FILE * file, rtx x, int code)
2100 {
2101   rtx addr;
2102
2103   switch (code)
2104     {
2105       /* The 's' and 'p' codes are used by output_block_move() to
2106          indicate post-increment 's'tores and 'p're-increment loads.  */
2107     case 's':
2108       if (GET_CODE (x) == REG)
2109         fprintf (file, "@+%s", reg_names [REGNO (x)]);
2110       else
2111         output_operand_lossage ("invalid operand to %%s code");
2112       return;
2113
2114     case 'p':
2115       if (GET_CODE (x) == REG)
2116         fprintf (file, "@%s+", reg_names [REGNO (x)]);
2117       else
2118         output_operand_lossage ("invalid operand to %%p code");
2119       return;
2120
2121     case 'R' :
2122       /* Write second word of DImode or DFmode reference,
2123          register or memory.  */
2124       if (GET_CODE (x) == REG)
2125         fputs (reg_names[REGNO (x)+1], file);
2126       else if (GET_CODE (x) == MEM)
2127         {
2128           fprintf (file, "@(");
2129           /* Handle possible auto-increment.  Since it is pre-increment and
2130              we have already done it, we can just use an offset of four.  */
2131           /* ??? This is taken from rs6000.c I think.  I don't think it is
2132              currently necessary, but keep it around.  */
2133           if (GET_CODE (XEXP (x, 0)) == PRE_INC
2134               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2135             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2136           else
2137             output_address (plus_constant (XEXP (x, 0), 4));
2138           fputc (')', file);
2139         }
2140       else
2141         output_operand_lossage ("invalid operand to %%R code");
2142       return;
2143
2144     case 'H' : /* High word.  */
2145     case 'L' : /* Low word.  */
2146       if (GET_CODE (x) == REG)
2147         {
2148           /* L = least significant word, H = most significant word.  */
2149           if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2150             fputs (reg_names[REGNO (x)], file);
2151           else
2152             fputs (reg_names[REGNO (x)+1], file);
2153         }
2154       else if (GET_CODE (x) == CONST_INT
2155                || GET_CODE (x) == CONST_DOUBLE)
2156         {
2157           rtx first, second;
2158
2159           split_double (x, &first, &second);
2160           fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2161                    code == 'L' ? INTVAL (first) : INTVAL (second));
2162         }
2163       else
2164         output_operand_lossage ("invalid operand to %%H/%%L code");
2165       return;
2166
2167     case 'A' :
2168       {
2169         char str[30];
2170
2171         if (GET_CODE (x) != CONST_DOUBLE
2172             || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2173           fatal_insn ("bad insn for 'A'", x);
2174
2175         real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2176         fprintf (file, "%s", str);
2177         return;
2178       }
2179
2180     case 'B' : /* Bottom half.  */
2181     case 'T' : /* Top half.  */
2182       /* Output the argument to a `seth' insn (sets the Top half-word).
2183          For constants output arguments to a seth/or3 pair to set Top and
2184          Bottom halves.  For symbols output arguments to a seth/add3 pair to
2185          set Top and Bottom halves.  The difference exists because for
2186          constants seth/or3 is more readable but for symbols we need to use
2187          the same scheme as `ld' and `st' insns (16 bit addend is signed).  */
2188       switch (GET_CODE (x))
2189         {
2190         case CONST_INT :
2191         case CONST_DOUBLE :
2192           {
2193             rtx first, second;
2194
2195             split_double (x, &first, &second);
2196             x = WORDS_BIG_ENDIAN ? second : first;
2197             fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2198                      (code == 'B'
2199                       ? INTVAL (x) & 0xffff
2200                       : (INTVAL (x) >> 16) & 0xffff));
2201           }
2202           return;
2203         case CONST :
2204         case SYMBOL_REF :
2205           if (code == 'B'
2206               && small_data_operand (x, VOIDmode))
2207             {
2208               fputs ("sda(", file);
2209               output_addr_const (file, x);
2210               fputc (')', file);
2211               return;
2212             }
2213           /* fall through */
2214         case LABEL_REF :
2215           fputs (code == 'T' ? "shigh(" : "low(", file);
2216           output_addr_const (file, x);
2217           fputc (')', file);
2218           return;
2219         default :
2220           output_operand_lossage ("invalid operand to %%T/%%B code");
2221           return;
2222         }
2223       break;
2224
2225     case 'U' :
2226       /* ??? wip */
2227       /* Output a load/store with update indicator if appropriate.  */
2228       if (GET_CODE (x) == MEM)
2229         {
2230           if (GET_CODE (XEXP (x, 0)) == PRE_INC
2231               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2232             fputs (".a", file);
2233         }
2234       else
2235         output_operand_lossage ("invalid operand to %%U code");
2236       return;
2237
2238     case 'N' :
2239       /* Print a constant value negated.  */
2240       if (GET_CODE (x) == CONST_INT)
2241         output_addr_const (file, GEN_INT (- INTVAL (x)));
2242       else
2243         output_operand_lossage ("invalid operand to %%N code");
2244       return;
2245
2246     case 'X' :
2247       /* Print a const_int in hex.  Used in comments.  */
2248       if (GET_CODE (x) == CONST_INT)
2249         fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2250       return;
2251
2252     case '#' :
2253       fputs (IMMEDIATE_PREFIX, file);
2254       return;
2255
2256     case 0 :
2257       /* Do nothing special.  */
2258       break;
2259
2260     default :
2261       /* Unknown flag.  */
2262       output_operand_lossage ("invalid operand output code");
2263     }
2264
2265   switch (GET_CODE (x))
2266     {
2267     case REG :
2268       fputs (reg_names[REGNO (x)], file);
2269       break;
2270
2271     case MEM :
2272       addr = XEXP (x, 0);
2273       if (GET_CODE (addr) == PRE_INC)
2274         {
2275           if (GET_CODE (XEXP (addr, 0)) != REG)
2276             fatal_insn ("pre-increment address is not a register", x);
2277
2278           fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2279         }
2280       else if (GET_CODE (addr) == PRE_DEC)
2281         {
2282           if (GET_CODE (XEXP (addr, 0)) != REG)
2283             fatal_insn ("pre-decrement address is not a register", x);
2284
2285           fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2286         }
2287       else if (GET_CODE (addr) == POST_INC)
2288         {
2289           if (GET_CODE (XEXP (addr, 0)) != REG)
2290             fatal_insn ("post-increment address is not a register", x);
2291
2292           fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2293         }
2294       else
2295         {
2296           fputs ("@(", file);
2297           output_address (XEXP (x, 0));
2298           fputc (')', file);
2299         }
2300       break;
2301
2302     case CONST_DOUBLE :
2303       /* We handle SFmode constants here as output_addr_const doesn't.  */
2304       if (GET_MODE (x) == SFmode)
2305         {
2306           REAL_VALUE_TYPE d;
2307           long l;
2308
2309           REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2310           REAL_VALUE_TO_TARGET_SINGLE (d, l);
2311           fprintf (file, "0x%08lx", l);
2312           break;
2313         }
2314
2315       /* Fall through.  Let output_addr_const deal with it.  */
2316
2317     default :
2318       output_addr_const (file, x);
2319       break;
2320     }
2321 }
2322
2323 /* Print a memory address as an operand to reference that memory location.  */
2324
2325 void
2326 m32r_print_operand_address (FILE * file, rtx addr)
2327 {
2328   rtx base;
2329   rtx index = 0;
2330   int offset = 0;
2331
2332   switch (GET_CODE (addr))
2333     {
2334     case REG :
2335       fputs (reg_names[REGNO (addr)], file);
2336       break;
2337
2338     case PLUS :
2339       if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2340         offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2341       else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2342         offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2343       else
2344         base = XEXP (addr, 0), index = XEXP (addr, 1);
2345       if (GET_CODE (base) == REG)
2346         {
2347           /* Print the offset first (if present) to conform to the manual.  */
2348           if (index == 0)
2349             {
2350               if (offset != 0)
2351                 fprintf (file, "%d,", offset);
2352               fputs (reg_names[REGNO (base)], file);
2353             }
2354           /* The chip doesn't support this, but left in for generality.  */
2355           else if (GET_CODE (index) == REG)
2356             fprintf (file, "%s,%s",
2357                      reg_names[REGNO (base)], reg_names[REGNO (index)]);
2358           /* Not sure this can happen, but leave in for now.  */
2359           else if (GET_CODE (index) == SYMBOL_REF)
2360             {
2361               output_addr_const (file, index);
2362               fputc (',', file);
2363               fputs (reg_names[REGNO (base)], file);
2364             }
2365           else
2366             fatal_insn ("bad address", addr);
2367         }
2368       else if (GET_CODE (base) == LO_SUM)
2369         {
2370           if (index != 0
2371               || GET_CODE (XEXP (base, 0)) != REG)
2372             abort ();
2373           if (small_data_operand (XEXP (base, 1), VOIDmode))
2374             fputs ("sda(", file);
2375           else
2376             fputs ("low(", file);
2377           output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2378           fputs ("),", file);
2379           fputs (reg_names[REGNO (XEXP (base, 0))], file);
2380         }
2381       else
2382         fatal_insn ("bad address", addr);
2383       break;
2384
2385     case LO_SUM :
2386       if (GET_CODE (XEXP (addr, 0)) != REG)
2387         fatal_insn ("lo_sum not of register", addr);
2388       if (small_data_operand (XEXP (addr, 1), VOIDmode))
2389         fputs ("sda(", file);
2390       else
2391         fputs ("low(", file);
2392       output_addr_const (file, XEXP (addr, 1));
2393       fputs ("),", file);
2394       fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2395       break;
2396
2397     case PRE_INC :      /* Assume SImode.  */
2398       fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2399       break;
2400
2401     case PRE_DEC :      /* Assume SImode.  */
2402       fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2403       break;
2404
2405     case POST_INC :     /* Assume SImode.  */
2406       fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2407       break;
2408
2409     default :
2410       output_addr_const (file, addr);
2411       break;
2412     }
2413 }
2414
2415 /* Return true if the operands are the constants 0 and 1.  */
2416
2417 int
2418 zero_and_one (rtx operand1, rtx operand2)
2419 {
2420   return
2421        GET_CODE (operand1) == CONST_INT
2422     && GET_CODE (operand2) == CONST_INT
2423     && (  ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2424         ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2425 }
2426
2427 /* Return nonzero if the operand is suitable for use in a conditional move sequence.  */
2428
2429 int
2430 conditional_move_operand (rtx operand, enum machine_mode mode)
2431 {
2432   /* Only defined for simple integers so far...  */
2433   if (mode != SImode && mode != HImode && mode != QImode)
2434     return FALSE;
2435
2436   /* At the moment we can handle moving registers and loading constants.  */
2437   /* To be added: Addition/subtraction/bitops/multiplication of registers.  */
2438
2439   switch (GET_CODE (operand))
2440     {
2441     case REG:
2442       return 1;
2443
2444     case CONST_INT:
2445       return INT8_P (INTVAL (operand));
2446
2447     default:
2448 #if 0
2449       fprintf (stderr, "Test for cond move op of type: %s\n",
2450                GET_RTX_NAME (GET_CODE (operand)));
2451 #endif
2452       return 0;
2453     }
2454 }
2455
2456 /* Return true if the code is a test of the carry bit.  */
2457
2458 int
2459 carry_compare_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2460 {
2461   rtx x;
2462
2463   if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2464     return FALSE;
2465
2466   if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2467     return FALSE;
2468
2469   x = XEXP (op, 0);
2470   if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2471     return FALSE;
2472
2473   x = XEXP (op, 1);
2474   if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2475     return FALSE;
2476
2477   return TRUE;
2478 }
2479
2480 /* Generate the correct assembler code to handle the conditional loading of a
2481    value into a register.  It is known that the operands satisfy the
2482    conditional_move_operand() function above.  The destination is operand[0].
2483    The condition is operand [1].  The 'true' value is operand [2] and the
2484    'false' value is operand [3].  */
2485
2486 char *
2487 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2488 {
2489   static char buffer [100];
2490   const char * dest = reg_names [REGNO (operands [0])];
2491
2492   buffer [0] = 0;
2493
2494   /* Destination must be a register.  */
2495   if (GET_CODE (operands [0]) != REG)
2496     abort();
2497   if (! conditional_move_operand (operands [2], SImode))
2498     abort();
2499   if (! conditional_move_operand (operands [3], SImode))
2500     abort();
2501
2502   /* Check to see if the test is reversed.  */
2503   if (GET_CODE (operands [1]) == NE)
2504     {
2505       rtx tmp = operands [2];
2506       operands [2] = operands [3];
2507       operands [3] = tmp;
2508     }
2509
2510   sprintf (buffer, "mvfc %s, cbr", dest);
2511
2512   /* If the true value was '0' then we need to invert the results of the move.  */
2513   if (INTVAL (operands [2]) == 0)
2514     sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2515              dest, dest);
2516
2517   return buffer;
2518 }
2519
2520 /* Returns true if the registers contained in the two
2521    rtl expressions are different.  */
2522
2523 int
2524 m32r_not_same_reg (rtx a, rtx b)
2525 {
2526   int reg_a = -1;
2527   int reg_b = -2;
2528
2529   while (GET_CODE (a) == SUBREG)
2530     a = SUBREG_REG (a);
2531
2532   if (GET_CODE (a) == REG)
2533     reg_a = REGNO (a);
2534
2535   while (GET_CODE (b) == SUBREG)
2536     b = SUBREG_REG (b);
2537
2538   if (GET_CODE (b) == REG)
2539     reg_b = REGNO (b);
2540
2541   return reg_a != reg_b;
2542 }
2543
2544 \f
2545 rtx
2546 m32r_function_symbol (const char *name)
2547 {
2548   int extra_flags = 0;
2549   enum m32r_model model;
2550   rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2551
2552   if (TARGET_MODEL_SMALL)
2553     model = M32R_MODEL_SMALL;
2554   else if (TARGET_MODEL_MEDIUM)
2555     model = M32R_MODEL_MEDIUM;
2556   else if (TARGET_MODEL_LARGE)
2557     model = M32R_MODEL_LARGE;
2558   else
2559     abort (); /* Shouldn't happen.  */
2560   extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2561
2562   if (extra_flags)
2563     SYMBOL_REF_FLAGS (sym) |= extra_flags;
2564
2565   return sym;
2566 }
2567
2568 /* Use a library function to move some bytes.  */
2569
2570 static void
2571 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2572 {
2573   /* We want to pass the size as Pmode, which will normally be SImode
2574      but will be DImode if we are using 64 bit longs and pointers.  */
2575   if (GET_MODE (bytes_rtx) != VOIDmode
2576       && GET_MODE (bytes_rtx) != Pmode)
2577     bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2578
2579   emit_library_call (m32r_function_symbol ("memcpy"), 0,
2580                      VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2581                      convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2582                                       TYPE_UNSIGNED (sizetype)),
2583                      TYPE_MODE (sizetype));
2584 }
2585
2586 /* The maximum number of bytes to copy using pairs of load/store instructions.
2587    If a block is larger than this then a loop will be generated to copy
2588    MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitrary choice.
2589    A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2590    string copy in it.  */
2591 #define MAX_MOVE_BYTES 32
2592
2593 /* Expand string/block move operations.
2594
2595    operands[0] is the pointer to the destination.
2596    operands[1] is the pointer to the source.
2597    operands[2] is the number of bytes to move.
2598    operands[3] is the alignment.  */
2599
2600 void
2601 m32r_expand_block_move (rtx operands[])
2602 {
2603   rtx           orig_dst  = operands[0];
2604   rtx           orig_src  = operands[1];
2605   rtx           bytes_rtx = operands[2];
2606   rtx           align_rtx = operands[3];
2607   int           constp    = GET_CODE (bytes_rtx) == CONST_INT;
2608   HOST_WIDE_INT bytes     = constp ? INTVAL (bytes_rtx) : 0;
2609   int           align     = INTVAL (align_rtx);
2610   int           leftover;
2611   rtx           src_reg;
2612   rtx           dst_reg;
2613
2614   if (constp && bytes <= 0)
2615     return;
2616
2617   /* Move the address into scratch registers.  */
2618   dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2619   src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2620
2621   if (align > UNITS_PER_WORD)
2622     align = UNITS_PER_WORD;
2623
2624   /* If we prefer size over speed, always use a function call.
2625      If we do not know the size, use a function call.
2626      If the blocks are not word aligned, use a function call.  */
2627   if (optimize_size || ! constp || align != UNITS_PER_WORD)
2628     {
2629       block_move_call (dst_reg, src_reg, bytes_rtx);
2630       return;
2631     }
2632
2633   leftover = bytes % MAX_MOVE_BYTES;
2634   bytes   -= leftover;
2635
2636   /* If necessary, generate a loop to handle the bulk of the copy.  */
2637   if (bytes)
2638     {
2639       rtx label = NULL_RTX;
2640       rtx final_src = NULL_RTX;
2641       rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2642       rtx rounded_total = GEN_INT (bytes);
2643       rtx new_dst_reg = gen_reg_rtx (SImode);
2644       rtx new_src_reg = gen_reg_rtx (SImode);
2645
2646       /* If we are going to have to perform this loop more than
2647          once, then generate a label and compute the address the
2648          source register will contain upon completion of the final
2649          iteration.  */
2650       if (bytes > MAX_MOVE_BYTES)
2651         {
2652           final_src = gen_reg_rtx (Pmode);
2653
2654           if (INT16_P(bytes))
2655             emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2656           else
2657             {
2658               emit_insn (gen_movsi (final_src, rounded_total));
2659               emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2660             }
2661
2662           label = gen_label_rtx ();
2663           emit_label (label);
2664         }
2665
2666       /* It is known that output_block_move() will update src_reg to point
2667          to the word after the end of the source block, and dst_reg to point
2668          to the last word of the destination block, provided that the block
2669          is MAX_MOVE_BYTES long.  */
2670       emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2671                                         new_dst_reg, new_src_reg));
2672       emit_move_insn (dst_reg, new_dst_reg);
2673       emit_move_insn (src_reg, new_src_reg);
2674       emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2675
2676       if (bytes > MAX_MOVE_BYTES)
2677         {
2678           emit_insn (gen_cmpsi (src_reg, final_src));
2679           emit_jump_insn (gen_bne (label));
2680         }
2681     }
2682
2683   if (leftover)
2684     emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2685                                       gen_reg_rtx (SImode),
2686                                       gen_reg_rtx (SImode)));
2687 }
2688
2689 \f
2690 /* Emit load/stores for a small constant word aligned block_move.
2691
2692    operands[0] is the memory address of the destination.
2693    operands[1] is the memory address of the source.
2694    operands[2] is the number of bytes to move.
2695    operands[3] is a temp register.
2696    operands[4] is a temp register.  */
2697
2698 void
2699 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2700 {
2701   HOST_WIDE_INT bytes = INTVAL (operands[2]);
2702   int           first_time;
2703   int           got_extra = 0;
2704
2705   if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2706     abort ();
2707
2708   /* We do not have a post-increment store available, so the first set of
2709      stores are done without any increment, then the remaining ones can use
2710      the pre-increment addressing mode.
2711
2712      Note: expand_block_move() also relies upon this behavior when building
2713      loops to copy large blocks.  */
2714   first_time = 1;
2715
2716   while (bytes > 0)
2717     {
2718       if (bytes >= 8)
2719         {
2720           if (first_time)
2721             {
2722               output_asm_insn ("ld\t%5, %p1", operands);
2723               output_asm_insn ("ld\t%6, %p1", operands);
2724               output_asm_insn ("st\t%5, @%0", operands);
2725               output_asm_insn ("st\t%6, %s0", operands);
2726             }
2727           else
2728             {
2729               output_asm_insn ("ld\t%5, %p1", operands);
2730               output_asm_insn ("ld\t%6, %p1", operands);
2731               output_asm_insn ("st\t%5, %s0", operands);
2732               output_asm_insn ("st\t%6, %s0", operands);
2733             }
2734
2735           bytes -= 8;
2736         }
2737       else if (bytes >= 4)
2738         {
2739           if (bytes > 4)
2740             got_extra = 1;
2741
2742           output_asm_insn ("ld\t%5, %p1", operands);
2743
2744           if (got_extra)
2745             output_asm_insn ("ld\t%6, %p1", operands);
2746
2747           if (first_time)
2748             output_asm_insn ("st\t%5, @%0", operands);
2749           else
2750             output_asm_insn ("st\t%5, %s0", operands);
2751
2752           bytes -= 4;
2753         }
2754       else
2755         {
2756           /* Get the entire next word, even though we do not want all of it.
2757              The saves us from doing several smaller loads, and we assume that
2758              we cannot cause a page fault when at least part of the word is in
2759              valid memory [since we don't get called if things aren't properly
2760              aligned].  */
2761           int dst_offset = first_time ? 0 : 4;
2762           /* The amount of increment we have to make to the
2763              destination pointer.  */
2764           int dst_inc_amount = dst_offset + bytes - 4;
2765           /* The same for the source pointer.  */
2766           int src_inc_amount = bytes;
2767           int last_shift;
2768           rtx my_operands[3];
2769
2770           /* If got_extra is true then we have already loaded
2771              the next word as part of loading and storing the previous word.  */
2772           if (! got_extra)
2773             output_asm_insn ("ld\t%6, @%1", operands);
2774
2775           if (bytes >= 2)
2776             {
2777               bytes -= 2;
2778
2779               output_asm_insn ("sra3\t%5, %6, #16", operands);
2780               my_operands[0] = operands[5];
2781               my_operands[1] = GEN_INT (dst_offset);
2782               my_operands[2] = operands[0];
2783               output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2784
2785               /* If there is a byte left to store then increment the
2786                  destination address and shift the contents of the source
2787                  register down by 8 bits.  We could not do the address
2788                  increment in the store half word instruction, because it does
2789                  not have an auto increment mode.  */
2790               if (bytes > 0)  /* assert (bytes == 1) */
2791                 {
2792                   dst_offset += 2;
2793                   last_shift = 8;
2794                 }
2795             }
2796           else
2797             last_shift = 24;
2798
2799           if (bytes > 0)
2800             {
2801               my_operands[0] = operands[6];
2802               my_operands[1] = GEN_INT (last_shift);
2803               output_asm_insn ("srai\t%0, #%1", my_operands);
2804               my_operands[0] = operands[6];
2805               my_operands[1] = GEN_INT (dst_offset);
2806               my_operands[2] = operands[0];
2807               output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2808             }
2809
2810           /* Update the destination pointer if needed.  We have to do
2811              this so that the patterns matches what we output in this
2812              function.  */
2813           if (dst_inc_amount
2814               && !find_reg_note (insn, REG_UNUSED, operands[0]))
2815             {
2816               my_operands[0] = operands[0];
2817               my_operands[1] = GEN_INT (dst_inc_amount);
2818               output_asm_insn ("addi\t%0, #%1", my_operands);
2819             }
2820
2821           /* Update the source pointer if needed.  We have to do this
2822              so that the patterns matches what we output in this
2823              function.  */
2824           if (src_inc_amount
2825               && !find_reg_note (insn, REG_UNUSED, operands[1]))
2826             {
2827               my_operands[0] = operands[1];
2828               my_operands[1] = GEN_INT (src_inc_amount);
2829               output_asm_insn ("addi\t%0, #%1", my_operands);
2830             }
2831
2832           bytes = 0;
2833         }
2834
2835       first_time = 0;
2836     }
2837 }
2838
2839 /* Return true if op is an integer constant, less than or equal to
2840    MAX_MOVE_BYTES.  */
2841
2842 int
2843 m32r_block_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2844 {
2845   if (GET_CODE (op) != CONST_INT
2846       || INTVAL (op) > MAX_MOVE_BYTES
2847       || INTVAL (op) <= 0)
2848     return 0;
2849
2850   return 1;
2851 }
2852
2853 /* Return true if using NEW_REG in place of OLD_REG is ok.  */
2854
2855 int
2856 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2857                            unsigned int new_reg)
2858 {
2859   /* Interrupt routines can't clobber any register that isn't already used.  */
2860   if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2861       && !regs_ever_live[new_reg])
2862     return 0;
2863
2864   /* We currently emit epilogues as text, not rtl, so the liveness
2865      of the return address register isn't visible.  */
2866   if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2867     return 0;
2868
2869   return 1;
2870 }
2871
2872 rtx
2873 m32r_return_addr (int count)
2874 {
2875   if (count != 0)
2876     return const0_rtx;
2877
2878   return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2879 }