gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 2, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 /* Driver configuration.  */
  23
  24 #undef  SWITCH_TAKES_ARG
  25 #define SWITCH_TAKES_ARG(CHAR)                                          \
  26   (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
  27
  28 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */
  29 #undef  LIB_SPEC
  30 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  31
  32 #undef STARTFILE_SPEC
  33 #undef ENDFILE_SPEC
  34
  35 \f
  36 /* Run-time target specifications.  */
  37
  38 #define TARGET_CPU_CPP_BUILTINS()               \
  39   do                                            \
  40     {                                           \
  41       builtin_define ("__iq2000__");            \
  42       builtin_assert ("cpu=iq2000");            \
  43       builtin_assert ("machine=iq2000");        \
  44     }                                           \
  45   while (0)
  46
  47 extern int      target_flags;
  48
  49 #define MASK_GPOPT         0x00000008   /* Optimize for global pointer.  */
  50 #define MASK_EMBEDDED_DATA 0x00008000   /* Reduce RAM usage, not fast code.  */
  51 #define MASK_UNINIT_CONST_IN_RODATA \
  52                            0x00800000   /* Store uninitialized
  53                                            consts in rodata.  */
  54
  55 /* Macros used in the machine description to test the flags.  */
  56
  57 #define TARGET_STATS            0
  58
  59 /* For embedded systems, optimize for reduced RAM space instead of for
  60    fastest code.  */
  61 #define TARGET_EMBEDDED_DATA    (target_flags & MASK_EMBEDDED_DATA)
  62
  63 #define TARGET_DEBUG_MODE       (target_flags & 0)
  64 #define TARGET_DEBUG_A_MODE     (target_flags & 0)
  65 #define TARGET_DEBUG_B_MODE     (target_flags & 0)
  66 #define TARGET_DEBUG_C_MODE     (target_flags & 0)
  67 #define TARGET_DEBUG_D_MODE     (target_flags & 0)
  68
  69 #define TARGET_SWITCHES                                                 \
  70 {                                                                       \
  71   {"no-crt0",          0,                                               \
  72      N_("No default crt0.o") },                                         \
  73   {"gpopt",               MASK_GPOPT,                                   \
  74      N_("Use GP relative sdata/sbss sections")},                        \
  75   {"no-gpopt",           -MASK_GPOPT,                                   \
  76      N_("Don't use GP relative sdata/sbss sections")},                  \
  77   {"embedded-data",       MASK_EMBEDDED_DATA,                           \
  78      N_("Use ROM instead of RAM")},                                     \
  79   {"no-embedded-data",   -MASK_EMBEDDED_DATA,                           \
  80      N_("Don't use ROM instead of RAM")},                               \
  81   {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA,               \
  82      N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
  83   {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA,           \
  84      N_("Don't put uninitialized constants in ROM")},                   \
  85   {"",                    (TARGET_DEFAULT                               \
  86                            | TARGET_CPU_DEFAULT),                       \
  87      NULL},                                                             \
  88 }
  89
  90 /* Default target_flags if no switches are specified.  */
  91
  92 #define TARGET_DEFAULT 0
  93
  94 #ifndef TARGET_CPU_DEFAULT
  95 #define TARGET_CPU_DEFAULT 0
  96 #endif
  97
  98 #ifndef IQ2000_ISA_DEFAULT
  99 #define IQ2000_ISA_DEFAULT 1
 100 #endif
 101
 102 #define TARGET_OPTIONS                                                  \
 103 {                                                                       \
 104   SUBTARGET_TARGET_OPTIONS                                              \
 105   { "cpu=",     & iq2000_cpu_string,                                    \
 106       N_("Specify CPU for scheduling purposes")},                       \
 107   { "arch=",    & iq2000_arch_string,                                   \
 108       N_("Specify CPU for code generation purposes")},                  \
 109 }
 110
 111 /* This is meant to be redefined in the host dependent files.  */
 112 #define SUBTARGET_TARGET_OPTIONS
 113
 114 #define IQ2000_VERSION "[1.0]"
 115
 116 #ifndef MACHINE_TYPE
 117 #define MACHINE_TYPE "IQ2000"
 118 #endif
 119
 120 #ifndef TARGET_VERSION_INTERNAL
 121 #define TARGET_VERSION_INTERNAL(STREAM)                                 \
 122   fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
 123 #endif
 124
 125 #ifndef TARGET_VERSION
 126 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
 127 #endif
 128
 129 #define OVERRIDE_OPTIONS override_options ()
 130
 131 #define CAN_DEBUG_WITHOUT_FP
 132 \f
 133 /* Storage Layout.  */
 134
 135 #define BITS_BIG_ENDIAN                 0
 136 #define BYTES_BIG_ENDIAN                1
 137 #define WORDS_BIG_ENDIAN                1
 138 #define LIBGCC2_WORDS_BIG_ENDIAN        1
 139 #define BITS_PER_WORD                   32
 140 #define MAX_BITS_PER_WORD               64
 141 #define UNITS_PER_WORD                  4
 142 #define MIN_UNITS_PER_WORD              4
 143 #define POINTER_SIZE                    32
 144
 145 /* Define this macro if it is advisable to hold scalars in registers
 146    in a wider mode than that declared by the program.  In such cases,
 147    the value is constrained to be within the bounds of the declared
 148    type, but kept valid in the wider mode.  The signedness of the
 149    extension may differ from that of the type.
 150
 151    We promote any value smaller than SImode up to SImode.  */
 152
 153 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 154   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 155       && GET_MODE_SIZE (MODE) < 4)              \
 156     (MODE) = SImode;
 157
 158 #define PARM_BOUNDARY 32
 159
 160 #define STACK_BOUNDARY 64
 161
 162 #define FUNCTION_BOUNDARY 32
 163
 164 #define BIGGEST_ALIGNMENT 64
 165
 166 #undef  DATA_ALIGNMENT
 167 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 168   ((((ALIGN) < BITS_PER_WORD)                                           \
 169     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 170         || TREE_CODE (TYPE) == UNION_TYPE                               \
 171         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 172
 173 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 174   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 175    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 176
 177 #define EMPTY_FIELD_BOUNDARY 32
 178
 179 #define STRUCTURE_SIZE_BOUNDARY 8
 180
 181 #define STRICT_ALIGNMENT 1
 182
 183 #define PCC_BITFIELD_TYPE_MATTERS 1
 184
 185 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 186
 187 \f
 188 /* Layout of Source Language Data Types.  */
 189
 190 #define INT_TYPE_SIZE           32
 191 #define SHORT_TYPE_SIZE         16
 192 #define LONG_TYPE_SIZE          32
 193 #define LONG_LONG_TYPE_SIZE     64
 194 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 195 #define FLOAT_TYPE_SIZE         32
 196 #define DOUBLE_TYPE_SIZE        64
 197 #define LONG_DOUBLE_TYPE_SIZE   64
 198 #define DEFAULT_SIGNED_CHAR     1
 199
 200 \f
 201 /* Register Basics.  */
 202
 203 /* On the IQ2000, we have 32 integer registers.  */
 204 #define FIRST_PSEUDO_REGISTER 33
 205
 206 #define FIXED_REGISTERS                                                 \
 207 {                                                                       \
 208   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 209   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 210 }
 211
 212 #define CALL_USED_REGISTERS                                             \
 213 {                                                                       \
 214   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 215   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 216 }
 217
 218 \f
 219 /* Order of allocation of registers.  */
 220
 221 #define REG_ALLOC_ORDER                                                 \
 222 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 223   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 224 }
 225
 226 \f
 227 /* How Values Fit in Registers.  */
 228
 229 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 230   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 231
 232 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 233  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 234   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 235   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 236
 237 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 238   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 239     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 240    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 241        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 242
 243 #define AVOID_CCMODE_COPIES
 244
 245 \f
 246 /* Register Classes.  */
 247
 248 enum reg_class
 249 {
 250   NO_REGS,                      /* No registers in set.  */
 251   GR_REGS,                      /* Integer registers.  */
 252   ALL_REGS,                     /* All registers.  */
 253   LIM_REG_CLASSES               /* Max value + 1.  */
 254 };
 255
 256 #define GENERAL_REGS GR_REGS
 257
 258 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 259
 260 #define REG_CLASS_NAMES                                         \
 261 {                                                               \
 262   "NO_REGS",                                                    \
 263   "GR_REGS",                                                    \
 264   "ALL_REGS"                                                    \
 265 }
 266
 267 #define REG_CLASS_CONTENTS                                      \
 268 {                                                               \
 269   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 270   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 271   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 272 }
 273
 274 #define REGNO_REG_CLASS(REGNO) \
 275 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 276
 277 #define BASE_REG_CLASS  (GR_REGS)
 278
 279 #define INDEX_REG_CLASS NO_REGS
 280
 281 #define REG_CLASS_FROM_LETTER(C) \
 282   ((C) == 'd' ? GR_REGS :        \
 283    (C) == 'b' ? ALL_REGS :       \
 284    (C) == 'y' ? GR_REGS :        \
 285    NO_REGS)
 286
 287 #define REGNO_OK_FOR_INDEX_P(regno)     0
 288
 289 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 290   ((CLASS) != ALL_REGS                                          \
 291    ? (CLASS)                                                    \
 292    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 293        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 294       ? (GR_REGS)                                               \
 295       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 296           || GET_MODE (X) == VOIDmode)                          \
 297          ? (GR_REGS)                                            \
 298          : (CLASS))))
 299
 300 #define SMALL_REGISTER_CLASSES 0
 301
 302 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 303   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 304
 305 /* For IQ2000:
 306
 307    `I'  is used for the range of constants an arithmetic insn can
 308         actually contain (16 bits signed integers).
 309
 310    `J'  is used for the range which is just zero (i.e., $r0).
 311
 312    `K'  is used for the range of constants a logical insn can actually
 313         contain (16 bit zero-extended integers).
 314
 315    `L'  is used for the range of constants that be loaded with lui
 316         (i.e., the bottom 16 bits are zero).
 317
 318    `M'  is used for the range of constants that take two words to load
 319         (i.e., not matched by `I', `K', and `L').
 320
 321    `N'  is used for constants 0xffffnnnn or 0xnnnnffff
 322
 323    `O'  is a 5 bit zero-extended integer.  */
 324
 325 #define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
 326   ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
 327    : (C) == 'J' ? ((VALUE) == 0)                                        \
 328    : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
 329    : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                          \
 330                    && (((VALUE) & ~2147483647) == 0                     \
 331                        || ((VALUE) & ~2147483647) == ~2147483647))      \
 332    : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                       \
 333                    && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
 334                    && (((VALUE) & 0x0000ffff) != 0                      \
 335                        || (((VALUE) & ~2147483647) != 0                 \
 336                            && ((VALUE) & ~2147483647) != ~2147483647))) \
 337    : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff)                       \
 338                    || (((VALUE) & 0xffff0000) == 0xffff0000))           \
 339    : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40)    \
 340    : 0)
 341
 342 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
 343   ((C) == 'G'                                                           \
 344    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
 345
 346 /* `R' is for memory references which take 1 word for the instruction.  */
 347
 348 #define EXTRA_CONSTRAINT(OP,CODE)                                       \
 349   (((CODE) == 'R')        ? simple_memory_operand (OP, GET_MODE (OP))   \
 350    : FALSE)
 351
 352 \f
 353 /* Basic Stack Layout.  */
 354
 355 #define STACK_GROWS_DOWNWARD
 356
 357 /* #define FRAME_GROWS_DOWNWARD */
 358
 359 #define STARTING_FRAME_OFFSET                                           \
 360   (current_function_outgoing_args_size)
 361
 362 /* Use the default value zero.  */
 363 /* #define STACK_POINTER_OFFSET 0 */
 364
 365 #define FIRST_PARM_OFFSET(FNDECL) 0
 366
 367 /* The return address for the current frame is in r31 if this is a leaf
 368    function.  Otherwise, it is on the stack.  It is at a variable offset
 369    from sp/fp/ap, so we define a fake hard register rap which is a
 370    pointer to the return address on the stack.  This always gets eliminated
 371    during reload to be either the frame pointer or the stack pointer plus
 372    an offset.  */
 373
 374 #define RETURN_ADDR_RTX(count, frame)                                   \
 375   (((count) == 0)                                                       \
 376    ? (leaf_function_p ()                                                \
 377       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 378       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 379                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 380     : (rtx) 0)
 381
 382 /* Before the prologue, RA lives in r31.  */
 383 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 384
 385 \f
 386 /* Register That Address the Stack Frame.  */
 387
 388 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 389 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 390 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 391 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 392 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 393 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 394
 395 \f
 396 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 397
 398 #define FRAME_POINTER_REQUIRED 0
 399
 400 #define ELIMINABLE_REGS                                                 \
 401 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 402  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 403  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 404  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 405  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 406  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 407  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 408
 409
 410 /* We can always eliminate to the frame pointer.  We can eliminate to the
 411    stack pointer unless a frame pointer is needed.  */
 412
 413 #define CAN_ELIMINATE(FROM, TO)                                         \
 414   (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p ()    \
 415    || (TO == GP_REG_FIRST + 31 && leaf_function_p)))                    \
 416   || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM                           \
 417    && ((TO) == HARD_FRAME_POINTER_REGNUM                                \
 418    || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
 419
 420 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 421         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 422 \f
 423 /* Passing Function Arguments on the Stack.  */
 424
 425 /* #define PUSH_ROUNDING(BYTES) 0 */
 426
 427 #define ACCUMULATE_OUTGOING_ARGS 1
 428
 429 #define REG_PARM_STACK_SPACE(FNDECL) 0
 430
 431 #define OUTGOING_REG_PARM_STACK_SPACE
 432
 433 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
 434
 435 \f
 436 /* Function Arguments in Registers.  */
 437
 438 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
 439   function_arg (& CUM, MODE, TYPE, NAMED)
 440
 441 #define MAX_ARGS_IN_REGISTERS 8
 442
 443 typedef struct iq2000_args
 444 {
 445   int gp_reg_found;             /* Whether a gp register was found yet.  */
 446   unsigned int arg_number;      /* Argument number.  */
 447   unsigned int arg_words;       /* # total words the arguments take.  */
 448   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 449   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 450   int fp_code;                  /* Mode of FP arguments.  */
 451   unsigned int num_adjusts;     /* Number of adjustments made.  */
 452                                 /* Adjustments made to args pass in regs.  */
 453   struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
 454 } CUMULATIVE_ARGS;
 455
 456 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 457    for a call to a function whose data type is FNTYPE.
 458    For a library call, FNTYPE is 0.  */
 459 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 460   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 461
 462 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
 463   function_arg_advance (& CUM, MODE, TYPE, NAMED)
 464
 465 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 466   (! BYTES_BIG_ENDIAN                                                   \
 467    ? upward                                                             \
 468    : (((MODE) == BLKmode                                                \
 469        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 470           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 471        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 472           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 473       ? downward : upward))
 474
 475 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE)                               \
 476   (((TYPE) != 0)                                                        \
 477         ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)                          \
 478                 ? PARM_BOUNDARY                                         \
 479                 : TYPE_ALIGN(TYPE))                                     \
 480         : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)                  \
 481                 ? PARM_BOUNDARY                                         \
 482                 : GET_MODE_ALIGNMENT(MODE)))
 483
 484 #define FUNCTION_ARG_REGNO_P(N)                                         \
 485   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 486
 487 \f
 488 /* How Scalar Function Values are Returned.  */
 489
 490 #define FUNCTION_VALUE(VALTYPE, FUNC)   iq2000_function_value (VALTYPE, FUNC)
 491
 492 #define LIBCALL_VALUE(MODE)                             \
 493   gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT      \
 494                  || GET_MODE_SIZE (MODE) >= 4)          \
 495                 ? (MODE)                                \
 496                 : SImode),                              \
 497                GP_RETURN)
 498
 499 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 500
 501 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
 502
 503 \f
 504 /* How Large Values are Returned.  */
 505
 506 #define DEFAULT_PCC_STRUCT_RETURN 0
 507 \f
 508 /* Function Entry and Exit.  */
 509
 510 #define EXIT_IGNORE_STACK 1
 511
 512 \f
 513 /* Generating Code for Profiling.  */
 514
 515 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 516 {                                                                       \
 517   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 518   fprintf (FILE, "\t.set\tnoat\n");                                     \
 519   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 520            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 521   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 522   fprintf (FILE,                                                        \
 523            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 524            "subu",                                                      \
 525            reg_names[STACK_POINTER_REGNUM],                             \
 526            reg_names[STACK_POINTER_REGNUM],                             \
 527            Pmode == DImode ? 16 : 8);                                   \
 528   fprintf (FILE, "\t.set\treorder\n");                                  \
 529   fprintf (FILE, "\t.set\tat\n");                                       \
 530 }
 531
 532 \f
 533 /* Implementing the Varargs Macros.  */
 534
 535 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
 536   iq2000_va_start (valist, nextarg)
 537
 538 \f
 539 /* Trampolines for Nested Functions.  */
 540
 541 /* A C statement to output, on the stream FILE, assembler code for a
 542    block of data that contains the constant parts of a trampoline.
 543    This code should not include a label--the label is taken care of
 544    automatically.  */
 545
 546 #define TRAMPOLINE_TEMPLATE(STREAM)                                      \
 547 {                                                                        \
 548   fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");         \
 549   fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");         \
 550   fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");                   \
 551   if (Pmode == DImode)                                                  \
 552     {                                                                   \
 553       fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n"); \
 554       fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n"); \
 555     }                                                                   \
 556   else                                                                  \
 557     {                                                                   \
 558       fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n"); \
 559       fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n"); \
 560     }                                                                   \
 561   fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
 562   fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");             \
 563   fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");         \
 564   fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
 565   fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
 566 }
 567
 568 #define TRAMPOLINE_SIZE (40)
 569
 570 #define TRAMPOLINE_ALIGNMENT 32
 571
 572 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)                            \
 573 {                                                                           \
 574   rtx addr = ADDR;                                                          \
 575     emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
 576     emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
 577 }
 578
 579 \f
 580 /* Addressing Modes.  */
 581
 582 #define CONSTANT_ADDRESS_P(X)                                           \
 583   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 584     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 585     || (GET_CODE (X) == CONST)))
 586
 587 #define MAX_REGS_PER_ADDRESS 1
 588
 589 #ifdef REG_OK_STRICT
 590 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
 591   {                                                     \
 592     if (iq2000_legitimate_address_p (MODE, X, 1))       \
 593       goto ADDR;                                        \
 594   }
 595 #else
 596 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
 597   {                                                     \
 598     if (iq2000_legitimate_address_p (MODE, X, 0))       \
 599       goto ADDR;                                        \
 600   }
 601 #endif
 602
 603 #define REG_OK_FOR_INDEX_P(X) 0
 604
 605
 606 /* For the IQ2000, transform:
 607
 608         memory(X + <large int>)
 609    into:
 610         Y = <large int> & ~0x7fff;
 611         Z = X + Y
 612         memory (Z + (<large int> & 0x7fff));
 613 */
 614
 615 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)                             \
 616 {                                                                       \
 617   rtx xinsn = (X);                                                      \
 618                                                                         \
 619   if (TARGET_DEBUG_B_MODE)                                              \
 620     {                                                                   \
 621       GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");                  \
 622       GO_DEBUG_RTX (xinsn);                                             \
 623     }                                                                   \
 624                                                                         \
 625   if (iq2000_check_split (X, MODE))             \
 626     {                                                                   \
 627       X = gen_rtx_LO_SUM (Pmode,                                        \
 628                           copy_to_mode_reg (Pmode,                      \
 629                                             gen_rtx_HIGH (Pmode, X)),   \
 630                           X);                                           \
 631       goto WIN;                                                         \
 632     }                                                                   \
 633                                                                         \
 634   if (GET_CODE (xinsn) == PLUS)                                         \
 635     {                                                                   \
 636       rtx xplus0 = XEXP (xinsn, 0);                                     \
 637       rtx xplus1 = XEXP (xinsn, 1);                                     \
 638       enum rtx_code code0 = GET_CODE (xplus0);                          \
 639       enum rtx_code code1 = GET_CODE (xplus1);                          \
 640                                                                         \
 641       if (code0 != REG && code1 == REG)                                 \
 642         {                                                               \
 643           xplus0 = XEXP (xinsn, 1);                                     \
 644           xplus1 = XEXP (xinsn, 0);                                     \
 645           code0 = GET_CODE (xplus0);                                    \
 646           code1 = GET_CODE (xplus1);                                    \
 647         }                                                               \
 648                                                                         \
 649       if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)         \
 650           && code1 == CONST_INT && !SMALL_INT (xplus1))                 \
 651         {                                                               \
 652           rtx int_reg = gen_reg_rtx (Pmode);                            \
 653           rtx ptr_reg = gen_reg_rtx (Pmode);                            \
 654                                                                         \
 655           emit_move_insn (int_reg,                                      \
 656                           GEN_INT (INTVAL (xplus1) & ~ 0x7fff));        \
 657                                                                         \
 658           emit_insn (gen_rtx_SET (VOIDmode,                             \
 659                                   ptr_reg,                              \
 660                                   gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
 661                                                                         \
 662           X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);        \
 663           goto WIN;                                                     \
 664         }                                                               \
 665     }                                                                   \
 666                                                                         \
 667   if (TARGET_DEBUG_B_MODE)                                              \
 668     GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");                  \
 669 }
 670
 671 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
 672
 673 #define LEGITIMATE_CONSTANT_P(X) (1)
 674
 675 \f
 676 /* Describing Relative Costs of Operations.  */
 677
 678 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 679
 680 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 681   (TO_P ? 2 : 16)
 682
 683 #define BRANCH_COST 2
 684
 685 #define SLOW_BYTE_ACCESS 1
 686
 687 #define NO_FUNCTION_CSE 1
 688
 689 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 690   if (REG_NOTE_KIND (LINK) != 0)                                        \
 691     (COST) = 0; /* Anti or output dependence.  */
 692
 693 \f
 694 /* Dividing the output into sections.  */
 695
 696 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 697
 698 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 699
 700 \f
 701 /* The Overall Framework of an Assembler File.  */
 702
 703 #define ASM_COMMENT_START " #"
 704
 705 #define ASM_APP_ON "#APP\n"
 706
 707 #define ASM_APP_OFF "#NO_APP\n"
 708
 709 \f
 710 /* Output and Generation of Labels.  */
 711
 712 #undef ASM_GENERATE_INTERNAL_LABEL
 713 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 714   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 715
 716 #define GLOBAL_ASM_OP "\t.globl\t"
 717
 718 \f
 719 /* Output of Assembler Instructions.  */
 720
 721 #define REGISTER_NAMES                                                  \
 722 {                                                                       \
 723  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 724  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 725  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 726  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 727 };
 728
 729 #define ADDITIONAL_REGISTER_NAMES                                       \
 730 {                                                                       \
 731   { "%0",        0 + GP_REG_FIRST },                                    \
 732   { "%1",        1 + GP_REG_FIRST },                                    \
 733   { "%2",        2 + GP_REG_FIRST },                                    \
 734   { "%3",        3 + GP_REG_FIRST },                                    \
 735   { "%4",        4 + GP_REG_FIRST },                                    \
 736   { "%5",        5 + GP_REG_FIRST },                                    \
 737   { "%6",        6 + GP_REG_FIRST },                                    \
 738   { "%7",        7 + GP_REG_FIRST },                                    \
 739   { "%8",        8 + GP_REG_FIRST },                                    \
 740   { "%9",        9 + GP_REG_FIRST },                                    \
 741   { "%10",      10 + GP_REG_FIRST },                                    \
 742   { "%11",      11 + GP_REG_FIRST },                                    \
 743   { "%12",      12 + GP_REG_FIRST },                                    \
 744   { "%13",      13 + GP_REG_FIRST },                                    \
 745   { "%14",      14 + GP_REG_FIRST },                                    \
 746   { "%15",      15 + GP_REG_FIRST },                                    \
 747   { "%16",      16 + GP_REG_FIRST },                                    \
 748   { "%17",      17 + GP_REG_FIRST },                                    \
 749   { "%18",      18 + GP_REG_FIRST },                                    \
 750   { "%19",      19 + GP_REG_FIRST },                                    \
 751   { "%20",      20 + GP_REG_FIRST },                                    \
 752   { "%21",      21 + GP_REG_FIRST },                                    \
 753   { "%22",      22 + GP_REG_FIRST },                                    \
 754   { "%23",      23 + GP_REG_FIRST },                                    \
 755   { "%24",      24 + GP_REG_FIRST },                                    \
 756   { "%25",      25 + GP_REG_FIRST },                                    \
 757   { "%26",      26 + GP_REG_FIRST },                                    \
 758   { "%27",      27 + GP_REG_FIRST },                                    \
 759   { "%28",      28 + GP_REG_FIRST },                                    \
 760   { "%29",      29 + GP_REG_FIRST },                                    \
 761   { "%30",      27 + GP_REG_FIRST },                                    \
 762   { "%31",      31 + GP_REG_FIRST },                                    \
 763   { "%rap",     32 + GP_REG_FIRST },                                    \
 764 }
 765
 766 /* Check if the current insn needs a nop in front of it
 767    because of load delays, and also update the delay slot statistics.  */
 768
 769 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 770   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 771
 772 /* See iq2000.c for the IQ2000 specific codes.  */
 773 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
 774
 775 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
 776
 777 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
 778
 779 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 780 do                                                                      \
 781   {                                                                     \
 782     fputs ("\n", STREAM);                                               \
 783   }                                                                     \
 784 while (0)
 785
 786 #define LOCAL_LABEL_PREFIX      "$"
 787
 788 #define USER_LABEL_PREFIX       ""
 789
 790 \f
 791 /* Output of dispatch tables.  */
 792
 793 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 794   do                                                                    \
 795     {                                                                   \
 796       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 797                Pmode == DImode ? ".dword" : ".word",                    \
 798                LOCAL_LABEL_PREFIX, VALUE);                              \
 799     }                                                                   \
 800   while (0)
 801
 802 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 803   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 804            Pmode == DImode ? ".dword" : ".word",                        \
 805            LOCAL_LABEL_PREFIX,                                          \
 806            VALUE)
 807
 808 \f
 809 /* Assembler Commands for Alignment.  */
 810
 811 #undef ASM_OUTPUT_SKIP
 812 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 813   fprintf (STREAM, "\t.space\t%u\n", (SIZE))
 814
 815 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 816   if ((LOG) != 0)                                                       \
 817     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 818
 819 \f
 820 /* Macros Affecting all Debug Formats.  */
 821
 822 #define DEBUGGER_AUTO_OFFSET(X)  \
 823   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 824
 825 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 826   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 827
 828 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 829
 830 #define DWARF2_DEBUGGING_INFO 1
 831
 832 \f
 833 /* Miscellaneous Parameters.  */
 834
 835 #define PREDICATE_CODES                                                 \
 836   {"uns_arith_operand",         { REG, CONST_INT, SUBREG }},            \
 837   {"arith_operand",             { REG, CONST_INT, SUBREG }},            \
 838   {"small_int",                 { CONST_INT }},                         \
 839   {"large_int",                 { CONST_INT }},                         \
 840   {"reg_or_0_operand",          { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
 841   {"simple_memory_operand",     { MEM, SUBREG }},                       \
 842   {"equality_op",               { EQ, NE }},                            \
 843   {"cmp_op",                    { EQ, NE, GT, GE, GTU, GEU, LT, LE,     \
 844                                   LTU, LEU }},                          \
 845   {"pc_or_label_operand",       { PC, LABEL_REF }},                     \
 846   {"call_insn_operand",         { CONST_INT, CONST, SYMBOL_REF, REG}},  \
 847   {"move_operand",              { CONST_INT, CONST_DOUBLE, CONST,       \
 848                                   SYMBOL_REF, LABEL_REF, SUBREG,        \
 849                                   REG, MEM}},                           \
 850   {"power_of_2_operand",        { CONST_INT }},
 851
 852 #define CASE_VECTOR_MODE SImode
 853
 854 #define WORD_REGISTER_OPERATIONS
 855
 856 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 857
 858 #define MOVE_MAX 4
 859
 860 #define MAX_MOVE_MAX 8
 861
 862 #define SHIFT_COUNT_TRUNCATED 1
 863
 864 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 865
 866 #define STORE_FLAG_VALUE 1
 867
 868 #define Pmode SImode
 869
 870 #define FUNCTION_MODE SImode
 871
 872 /* Standard GCC variables that we reference.  */
 873
 874 extern char     call_used_regs[];
 875
 876 /* IQ2000 external variables defined in iq2000.c.  */
 877
 878 /* Comparison type.  */
 879 enum cmp_type
 880 {
 881   CMP_SI,                               /* Compare four byte integers.  */
 882   CMP_DI,                               /* Compare eight byte integers.  */
 883   CMP_SF,                               /* Compare single precision floats.  */
 884   CMP_DF,                               /* Compare double precision floats.  */
 885   CMP_MAX                               /* Max comparison type.  */
 886 };
 887
 888 /* Types of delay slot.  */
 889 enum delay_type
 890 {
 891   DELAY_NONE,                           /* No delay slot.  */
 892   DELAY_LOAD,                           /* Load from memory delay.  */
 893   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 894 };
 895
 896 /* Which processor to schedule for.  */
 897
 898 enum processor_type
 899 {
 900   PROCESSOR_DEFAULT,
 901   PROCESSOR_IQ2000,
 902   PROCESSOR_IQ10
 903 };
 904
 905 /* Recast the cpu class to be the cpu attribute.  */
 906 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 907
 908 /* Functions to change what output section we are using.  */
 909 extern void             rdata_section (void);
 910 extern void             sdata_section (void);
 911 extern void             sbss_section  (void);
 912
 913 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 914 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 915
 916 \f
 917 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 918
 919 /* Macros to decide whether certain features are available or not,
 920    depending on the instruction set architecture level.  */
 921
 922 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 923
 924 /* ISA has branch likely instructions.  */
 925 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 926
 927 \f
 928 #undef ASM_SPEC
 929
 930 \f
 931 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 932 #define DWARF_FRAME_REGNUM(REG)        (REG)
 933
 934 /* The DWARF 2 CFA column which tracks the return address.  */
 935 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 936
 937 /* Describe how we implement __builtin_eh_return.  */
 938 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 939
 940 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 941    location used to store the amount to adjust the stack.  This is
 942    usually a register that is available from end of the function's body
 943    to the end of the epilogue. Thus, this cannot be a register used as a
 944    temporary by the epilogue.
 945
 946    This must be an integer register.  */
 947 #define EH_RETURN_STACKADJ_REGNO        3
 948 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 949
 950 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 951    location used to store the address the processor should jump to
 952    catch exception.  This is usually a registers that is available from
 953    end of the function's body to the end of the epilogue. Thus, this
 954    cannot be a register used as a temporary by the epilogue.
 955
 956    This must be an address register.  */
 957 #define EH_RETURN_HANDLER_REGNO         26
 958 #define EH_RETURN_HANDLER_RTX           \
 959         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 960
 961 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 962 #define DWARF_CIE_DATA_ALIGNMENT 4
 963
 964 /* For IQ2000, width of a floating point register.  */
 965 #define UNITS_PER_FPREG 4
 966
 967 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 968
 969 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 970
 971 /* Internal macros to classify a register number as to whether it's a
 972    general purpose register, a floating point register, a
 973    multiply/divide register, or a status register.  */
 974
 975 #define GP_REG_FIRST 0
 976 #define GP_REG_LAST  31
 977 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 978
 979 #define RAP_REG_NUM   32
 980 #define AT_REGNUM       (GP_REG_FIRST + 1)
 981
 982 #define GP_REG_P(REGNO) \
 983   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 984
 985 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 986    is larger than 32K bytes.  These registers must come from the
 987    scratch register set, and not used for passing and returning
 988    arguments and any other information used in the calling sequence.  */
 989
 990 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 991 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 992
 993 /* This macro is used later on in the file.  */
 994 #define GR_REG_CLASS_P(CLASS)                                           \
 995   ((CLASS) == GR_REGS)
 996
 997 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 998 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 999
1000 /* Certain machines have the property that some registers cannot be
1001    copied to some other registers without using memory.  Define this
1002    macro on those machines to be a C expression that is nonzero if
1003    objects of mode MODE in registers of CLASS1 can only be copied to
1004    registers of class CLASS2 by storing a register of CLASS1 into
1005    memory and loading that memory location into a register of CLASS2.
1006
1007    Do not define this macro if its value would always be zero.  */
1008
1009 /* Return the maximum number of consecutive registers
1010    needed to represent mode MODE in a register of class CLASS.  */
1011
1012 #define CLASS_UNITS(mode, size)                                         \
1013   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1014
1015 /* If defined, gives a class of registers that cannot be used as the
1016    operand of a SUBREG that changes the mode of the object illegally.  */
1017
1018 #define CLASS_CANNOT_CHANGE_MODE 0
1019
1020 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
1021
1022 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1023   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1024
1025 /* Make sure 4 words are always allocated on the stack.  */
1026
1027 #ifndef STACK_ARGS_ADJUST
1028 #define STACK_ARGS_ADJUST(SIZE)                                         \
1029   {                                                                     \
1030     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
1031       SIZE.constant = 4 * UNITS_PER_WORD;                               \
1032   }
1033 #endif
1034
1035 \f
1036 /* Symbolic macros for the registers used to return integer and floating
1037    point values.  */
1038
1039 #define GP_RETURN (GP_REG_FIRST + 2)
1040
1041 /* Symbolic macros for the first/last argument registers.  */
1042
1043 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1044 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
1045
1046 #define MAX_ARGS_IN_REGISTERS   8
1047
1048 \f
1049 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
1050
1051 #define MUST_SAVE_REGISTER(regno) \
1052  ((regs_ever_live[regno] && !call_used_regs[regno])                     \
1053   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
1054   || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
1055
1056 /* ALIGN FRAMES on double word boundaries */
1057 #ifndef IQ2000_STACK_ALIGN
1058 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
1059 #endif
1060
1061 \f
1062 /* These assume that REGNO is a hard or pseudo reg number.
1063    They give nonzero only if REGNO is a hard reg of the suitable class
1064    or a pseudo reg currently allocated to a suitable hard reg.
1065    These definitions are NOT overridden anywhere.  */
1066
1067 #define BASE_REG_P(regno, mode)                                 \
1068   (GP_REG_P (regno))
1069
1070 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
1071   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
1072              (mode))
1073
1074 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
1075   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
1076
1077 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
1078   GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
1079
1080 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1081    and check its validity for a certain class.
1082    We have two alternate definitions for each of them.
1083    The usual definition accepts all pseudo regs; the other rejects them all.
1084    The symbol REG_OK_STRICT causes the latter definition to be used.
1085
1086    Most source files want to accept pseudo regs in the hope that
1087    they will get allocated to the class that the insn wants them to be in.
1088    Some source files that are used after register allocation
1089    need to be strict.  */
1090
1091 #ifndef REG_OK_STRICT
1092 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1093   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
1094 #else
1095 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1096   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
1097 #endif
1098
1099 #if 1
1100 #define GO_PRINTF(x)    fprintf (stderr, (x))
1101 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
1102 #define GO_DEBUG_RTX(x) debug_rtx (x)
1103
1104 #else
1105 #define GO_PRINTF(x)
1106 #define GO_PRINTF2(x,y)
1107 #define GO_DEBUG_RTX(x)
1108 #endif
1109
1110 /* If defined, modifies the length assigned to instruction INSN as a
1111    function of the context in which it is used.  LENGTH is an lvalue
1112    that contains the initially computed length of the insn and should
1113    be updated with the correct length of the insn.  */
1114 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1115   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
1116
1117 \f
1118 /* A list of predicates that do special things with modes, and so
1119    should not elicit warnings for VOIDmode match_operand.  */
1120
1121 #define SPECIAL_MODE_PREDICATES \
1122   "pc_or_label_operand",
1123
1124 \f
1125
1126
1127 /* How to tell the debugger about changes of source files.  */
1128
1129 #ifndef SET_FILE_NUMBER
1130 #define SET_FILE_NUMBER() ++ num_source_filenames
1131 #endif
1132
1133 /* This is how to output a note the debugger telling it the line number
1134    to which the following sequence of instructions corresponds.  */
1135
1136 #ifndef LABEL_AFTER_LOC
1137 #define LABEL_AFTER_LOC(STREAM)
1138 #endif
1139
1140 \f
1141 /* Default to -G 8 */
1142 #ifndef IQ2000_DEFAULT_GVALUE
1143 #define IQ2000_DEFAULT_GVALUE 8
1144 #endif
1145
1146 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
1147
1148 \f
1149 /* See iq2000_expand_prologue's use of loadgp for when this should be
1150    true.  */
1151
1152 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE 0
1153 \f
1154 /* List of all IQ2000 punctuation characters used by print_operand.  */
1155 extern char iq2000_print_operand_punct[256];
1156
1157 /* The target cpu for optimization and scheduling.  */
1158 extern enum processor_type iq2000_tune;
1159
1160 /* Which instruction set architecture to use.  */
1161 extern int iq2000_isa;
1162
1163 /* Cached operands, and operator to compare for use in set/branch/trap
1164    on condition codes.  */
1165 extern rtx branch_cmp[2];
1166
1167 /* What type of branch to use.  */
1168 extern enum cmp_type branch_type;
1169
1170 /* Strings to hold which cpu and instruction set architecture to use.  */
1171 extern const char * iq2000_cpu_string;    /* For -mcpu=<xxx>.  */
1172 extern const char * iq2000_arch_string;   /* For -march=<xxx>.  */
1173
1174
1175
1176 enum iq2000_builtins
1177 {
1178   IQ2000_BUILTIN_ADO16,
1179   IQ2000_BUILTIN_CFC0,
1180   IQ2000_BUILTIN_CFC1,
1181   IQ2000_BUILTIN_CFC2,
1182   IQ2000_BUILTIN_CFC3,
1183   IQ2000_BUILTIN_CHKHDR,
1184   IQ2000_BUILTIN_CTC0,
1185   IQ2000_BUILTIN_CTC1,
1186   IQ2000_BUILTIN_CTC2,
1187   IQ2000_BUILTIN_CTC3,
1188   IQ2000_BUILTIN_LU,
1189   IQ2000_BUILTIN_LUC32L,
1190   IQ2000_BUILTIN_LUC64,
1191   IQ2000_BUILTIN_LUC64L,
1192   IQ2000_BUILTIN_LUK,
1193   IQ2000_BUILTIN_LULCK,
1194   IQ2000_BUILTIN_LUM32,
1195   IQ2000_BUILTIN_LUM32L,
1196   IQ2000_BUILTIN_LUM64,
1197   IQ2000_BUILTIN_LUM64L,
1198   IQ2000_BUILTIN_LUR,
1199   IQ2000_BUILTIN_LURL,
1200   IQ2000_BUILTIN_MFC0,
1201   IQ2000_BUILTIN_MFC1,
1202   IQ2000_BUILTIN_MFC2,
1203   IQ2000_BUILTIN_MFC3,
1204   IQ2000_BUILTIN_MRGB,
1205   IQ2000_BUILTIN_MTC0,
1206   IQ2000_BUILTIN_MTC1,
1207   IQ2000_BUILTIN_MTC2,
1208   IQ2000_BUILTIN_MTC3,
1209   IQ2000_BUILTIN_PKRL,
1210   IQ2000_BUILTIN_RAM,
1211   IQ2000_BUILTIN_RB,
1212   IQ2000_BUILTIN_RX,
1213   IQ2000_BUILTIN_SRRD,
1214   IQ2000_BUILTIN_SRRDL,
1215   IQ2000_BUILTIN_SRULC,
1216   IQ2000_BUILTIN_SRULCK,
1217   IQ2000_BUILTIN_SRWR,
1218   IQ2000_BUILTIN_SRWRU,
1219   IQ2000_BUILTIN_TRAPQF,
1220   IQ2000_BUILTIN_TRAPQFL,
1221   IQ2000_BUILTIN_TRAPQN,
1222   IQ2000_BUILTIN_TRAPQNE,
1223   IQ2000_BUILTIN_TRAPRE,
1224   IQ2000_BUILTIN_TRAPREL,
1225   IQ2000_BUILTIN_WB,
1226   IQ2000_BUILTIN_WBR,
1227   IQ2000_BUILTIN_WBU,
1228   IQ2000_BUILTIN_WX,
1229   IQ2000_BUILTIN_SYSCALL
1230 };