| blob | c643828acad54b0d853b5f3a8fe6b7a71932677f |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_CTTZ 1)
30 (UNSPEC_INSXH 2)
31 (UNSPEC_MSKXH 3)
32 (UNSPEC_CVTQL 4)
33 (UNSPEC_CVTLQ 5)
34 (UNSPEC_UMK_LAUM 6)
35 (UNSPEC_UMK_LALM 7)
36 (UNSPEC_UMK_LAL 8)
37 (UNSPEC_UMK_LOAD_CIW 9)
38 (UNSPEC_LDGP2 10)
39 (UNSPEC_LITERAL 11)
40 (UNSPEC_LITUSE 12)
41 (UNSPEC_SIBCALL 13)
42 (UNSPEC_SYMBOL 14)
44 ;; TLS Support
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
47 (UNSPEC_TLSGD 17)
48 (UNSPEC_TLSLDM 18)
49 (UNSPEC_DTPREL 19)
50 (UNSPEC_TPREL 20)
51 (UNSPEC_TP 21)
53 ;; Builtins
54 (UNSPEC_CMPBGE 22)
55 (UNSPEC_ZAP 23)
56 (UNSPEC_AMASK 24)
57 (UNSPEC_IMPLVER 25)
58 (UNSPEC_PERR 26)
59 (UNSPEC_CTLZ 27)
60 (UNSPEC_CTPOP 28)
61 (UNSPEC_COPYSIGN 29)
62 ])
64 ;; UNSPEC_VOLATILE:
66 (define_constants
67 [(UNSPECV_IMB 0)
68 (UNSPECV_BLOCKAGE 1)
69 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
70 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_TRAPB 4)
72 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_REALIGN 6)
74 (UNSPECV_EHR 7) ; exception_receiver
75 (UNSPECV_MCOUNT 8)
76 (UNSPECV_FORCE_MOV 9)
77 (UNSPECV_LDGP1 10)
78 (UNSPECV_PLDGP2 11) ; prologue ldgp
79 (UNSPECV_SET_TP 12)
80 (UNSPECV_RPCC 13)
81 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
82 ])
84 ;; Where necessary, the suffixes _le and _be are used to distinguish between
85 ;; little-endian and big-endian patterns.
86 ;;
87 ;; Note that the Unicos/Mk assembler does not support the following
88 ;; opcodes: mov, fmov, nop, fnop, unop.
89 \f
90 ;; Processor type -- this attribute must exactly match the processor_type
91 ;; enumeration in alpha.h.
93 (define_attr "cpu" "ev4,ev5,ev6"
94 (const (symbol_ref "alpha_cpu")))
96 ;; Define an insn type attribute. This is used in function unit delay
97 ;; computations, among other purposes. For the most part, we use the names
98 ;; defined in the EV4 documentation, but add a few that we have to know about
99 ;; separately.
101 (define_attr "type"
102 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
103 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
104 (const_string "iadd"))
106 ;; Describe a user's asm statement.
107 (define_asm_attributes
108 [(set_attr "type" "multi")])
110 ;; Define the operand size an insn operates on. Used primarily by mul
111 ;; and div operations that have size dependent timings.
113 (define_attr "opsize" "si,di,udi"
114 (const_string "di"))
116 ;; The TRAP attribute marks instructions that may generate traps
117 ;; (which are imprecise and may need a trapb if software completion
118 ;; is desired).
120 (define_attr "trap" "no,yes"
121 (const_string "no"))
123 ;; The ROUND_SUFFIX attribute marks which instructions require a
124 ;; rounding-mode suffix. The value NONE indicates no suffix,
125 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
127 (define_attr "round_suffix" "none,normal,c"
128 (const_string "none"))
130 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
131 ;; NONE no suffix
132 ;; SU accepts only /su (cmpt et al)
133 ;; SUI accepts only /sui (cvtqt and cvtqs)
134 ;; V_SV accepts /v and /sv (cvtql only)
135 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
136 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
137 ;;
138 ;; The actual suffix emitted is controlled by alpha_fptm.
140 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
141 (const_string "none"))
143 ;; The length of an instruction sequence in bytes.
145 (define_attr "length" ""
146 (const_int 4))
148 ;; The USEGP attribute marks instructions that have relocations that use
149 ;; the GP.
151 (define_attr "usegp" "no,yes"
152 (cond [(eq_attr "type" "ldsym,jsr")
153 (const_string "yes")
154 (eq_attr "type" "ild,fld,ist,fst")
155 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
156 ]
157 (const_string "no")))
159 ;; The CANNOT_COPY attribute marks instructions with relocations that
160 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
161 ;; since they have to stay in 1-1 correspondence with one another. This
162 ;; also includes jsr insns, since they must stay in correspondence with
163 ;; the immediately following gpdisp instructions.
165 (define_attr "cannot_copy" "false,true"
166 (const_string "false"))
167 \f
168 ;; Include scheduling descriptions.
170 (include "ev4.md")
171 (include "ev5.md")
172 (include "ev6.md")
174 \f
175 ;; Include predicate definitions
177 (include "predicates.md")
179 \f
180 ;; First define the arithmetic insns. Note that the 32-bit forms also
181 ;; sign-extend.
183 ;; Handle 32-64 bit extension from memory to a floating point register
184 ;; specially, since this occurs frequently in int->double conversions.
185 ;;
186 ;; Note that while we must retain the =f case in the insn for reload's
187 ;; benefit, it should be eliminated after reload, so we should never emit
188 ;; code for that case. But we don't reject the possibility.
190 (define_expand "extendsidi2"
191 [(set (match_operand:DI 0 "register_operand" "")
192 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
193 ""
194 "")
196 (define_insn "*cvtlq"
197 [(set (match_operand:DI 0 "register_operand" "=f")
198 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
199 UNSPEC_CVTLQ))]
200 ""
201 "cvtlq %1,%0"
202 [(set_attr "type" "fadd")])
204 (define_insn "*extendsidi2_1"
205 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
206 (sign_extend:DI
207 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
208 ""
209 "@
210 addl $31,%1,%0
211 ldl %0,%1
212 lds %0,%1\;cvtlq %0,%0"
213 [(set_attr "type" "iadd,ild,fld")
214 (set_attr "length" "*,*,8")])
216 (define_split
217 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
218 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
219 "reload_completed"
220 [(set (match_dup 2) (match_dup 1))
221 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
222 {
223 operands[1] = adjust_address (operands[1], SFmode, 0);
224 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
225 })
227 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
228 ;; reload when converting fp->int.
230 (define_peephole2
231 [(set (match_operand:SI 0 "hard_int_register_operand" "")
232 (match_operand:SI 1 "memory_operand" ""))
233 (set (match_operand:DI 2 "hard_int_register_operand" "")
234 (sign_extend:DI (match_dup 0)))]
235 "true_regnum (operands[0]) == true_regnum (operands[2])
236 || peep2_reg_dead_p (2, operands[0])"
237 [(set (match_dup 2)
238 (sign_extend:DI (match_dup 1)))]
239 "")
241 ;; Don't say we have addsi3 if optimizing. This generates better code. We
242 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
243 (define_expand "addsi3"
244 [(set (match_operand:SI 0 "register_operand" "")
245 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
246 (match_operand:SI 2 "add_operand" "")))]
247 "! optimize"
248 "")
250 (define_insn "*addsi_internal"
251 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
252 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
253 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
254 ""
255 "@
256 addl %r1,%2,%0
257 subl %r1,%n2,%0
258 lda %0,%2(%r1)
259 ldah %0,%h2(%r1)")
261 (define_split
262 [(set (match_operand:SI 0 "register_operand" "")
263 (plus:SI (match_operand:SI 1 "register_operand" "")
264 (match_operand:SI 2 "const_int_operand" "")))]
265 "! add_operand (operands[2], SImode)"
266 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
267 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
268 {
269 HOST_WIDE_INT val = INTVAL (operands[2]);
270 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
271 HOST_WIDE_INT rest = val - low;
273 operands[3] = GEN_INT (rest);
274 operands[4] = GEN_INT (low);
275 })
277 (define_insn "*addsi_se"
278 [(set (match_operand:DI 0 "register_operand" "=r,r")
279 (sign_extend:DI
280 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
281 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
282 ""
283 "@
284 addl %r1,%2,%0
285 subl %r1,%n2,%0")
287 (define_insn "*addsi_se2"
288 [(set (match_operand:DI 0 "register_operand" "=r,r")
289 (sign_extend:DI
290 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
291 (match_operand:DI 2 "sext_add_operand" "rI,O"))
292 0)))]
293 ""
294 "@
295 addl %r1,%2,%0
296 subl %r1,%n2,%0")
298 (define_split
299 [(set (match_operand:DI 0 "register_operand" "")
300 (sign_extend:DI
301 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
302 (match_operand:SI 2 "const_int_operand" ""))))
303 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
304 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
305 && INTVAL (operands[2]) % 4 == 0"
306 [(set (match_dup 3) (match_dup 4))
307 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
308 (match_dup 5))
309 (match_dup 1))))]
310 {
311 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
312 int mult = 4;
314 if (val % 2 == 0)
315 val /= 2, mult = 8;
317 operands[4] = GEN_INT (val);
318 operands[5] = GEN_INT (mult);
319 })
321 (define_split
322 [(set (match_operand:DI 0 "register_operand" "")
323 (sign_extend:DI
324 (plus:SI (match_operator:SI 1 "comparison_operator"
325 [(match_operand 2 "" "")
326 (match_operand 3 "" "")])
327 (match_operand:SI 4 "add_operand" ""))))
328 (clobber (match_operand:DI 5 "register_operand" ""))]
329 ""
330 [(set (match_dup 5) (match_dup 6))
331 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
332 {
333 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
334 operands[2], operands[3]);
335 operands[7] = gen_lowpart (SImode, operands[5]);
336 })
338 (define_insn "addvsi3"
339 [(set (match_operand:SI 0 "register_operand" "=r,r")
340 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
341 (match_operand:SI 2 "sext_add_operand" "rI,O")))
342 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
343 (sign_extend:DI (match_dup 2)))
344 (sign_extend:DI (plus:SI (match_dup 1)
345 (match_dup 2))))
346 (const_int 0))]
347 ""
348 "@
349 addlv %r1,%2,%0
350 sublv %r1,%n2,%0")
352 (define_expand "adddi3"
353 [(set (match_operand:DI 0 "register_operand" "")
354 (plus:DI (match_operand:DI 1 "register_operand" "")
355 (match_operand:DI 2 "add_operand" "")))]
356 ""
357 "")
359 (define_insn "*adddi_er_lo16_dtp"
360 [(set (match_operand:DI 0 "register_operand" "=r")
361 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
362 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
363 "HAVE_AS_TLS"
364 "lda %0,%2(%1)\t\t!dtprel")
366 (define_insn "*adddi_er_hi32_dtp"
367 [(set (match_operand:DI 0 "register_operand" "=r")
368 (plus:DI (match_operand:DI 1 "register_operand" "r")
369 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
370 "HAVE_AS_TLS"
371 "ldah %0,%2(%1)\t\t!dtprelhi")
373 (define_insn "*adddi_er_lo32_dtp"
374 [(set (match_operand:DI 0 "register_operand" "=r")
375 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
376 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
377 "HAVE_AS_TLS"
378 "lda %0,%2(%1)\t\t!dtprello")
380 (define_insn "*adddi_er_lo16_tp"
381 [(set (match_operand:DI 0 "register_operand" "=r")
382 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
383 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
384 "HAVE_AS_TLS"
385 "lda %0,%2(%1)\t\t!tprel")
387 (define_insn "*adddi_er_hi32_tp"
388 [(set (match_operand:DI 0 "register_operand" "=r")
389 (plus:DI (match_operand:DI 1 "register_operand" "r")
390 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
391 "HAVE_AS_TLS"
392 "ldah %0,%2(%1)\t\t!tprelhi")
394 (define_insn "*adddi_er_lo32_tp"
395 [(set (match_operand:DI 0 "register_operand" "=r")
396 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
397 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
398 "HAVE_AS_TLS"
399 "lda %0,%2(%1)\t\t!tprello")
401 (define_insn "*adddi_er_high_l"
402 [(set (match_operand:DI 0 "register_operand" "=r")
403 (plus:DI (match_operand:DI 1 "register_operand" "r")
404 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
405 "TARGET_EXPLICIT_RELOCS && reload_completed"
406 "ldah %0,%2(%1)\t\t!gprelhigh"
407 [(set_attr "usegp" "yes")])
409 (define_split
410 [(set (match_operand:DI 0 "register_operand" "")
411 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
412 "TARGET_EXPLICIT_RELOCS && reload_completed"
413 [(set (match_dup 0)
414 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
415 "operands[2] = pic_offset_table_rtx;")
417 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
418 ;; With complications like
419 ;;
420 ;; The NT stack unwind code can't handle a subq to adjust the stack
421 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
422 ;; the exception handling code will loop if a subq is used and an
423 ;; exception occurs.
424 ;;
425 ;; The 19980616 change to emit prologues as RTL also confused some
426 ;; versions of GDB, which also interprets prologues. This has been
427 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
428 ;; use lda here.
429 ;;
430 ;; and the fact that the three insns schedule exactly the same, it's
431 ;; just not worth the effort.
433 (define_insn "*adddi_internal"
434 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
435 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
436 (match_operand:DI 2 "add_operand" "r,K,L")))]
437 ""
438 "@
439 addq %1,%2,%0
440 lda %0,%2(%1)
441 ldah %0,%h2(%1)")
443 ;; ??? Allow large constants when basing off the frame pointer or some
444 ;; virtual register that may eliminate to the frame pointer. This is
445 ;; done because register elimination offsets will change the hi/lo split,
446 ;; and if we split before reload, we will require additional instructions.
448 (define_insn "*adddi_fp_hack"
449 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
450 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
451 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
452 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
453 && INTVAL (operands[2]) >= 0
454 /* This is the largest constant an lda+ldah pair can add, minus
455 an upper bound on the displacement between SP and AP during
456 register elimination. See INITIAL_ELIMINATION_OFFSET. */
457 && INTVAL (operands[2])
458 < (0x7fff8000
459 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
460 - ALPHA_ROUND(current_function_outgoing_args_size)
461 - (ALPHA_ROUND (get_frame_size ()
462 + max_reg_num () * UNITS_PER_WORD
463 + current_function_pretend_args_size)
464 - current_function_pretend_args_size))"
465 "@
466 lda %0,%2(%1)
467 ldah %0,%h2(%1)
468 #")
470 ;; Don't do this if we are adjusting SP since we don't want to do it
471 ;; in two steps. Don't split FP sources for the reason listed above.
472 (define_split
473 [(set (match_operand:DI 0 "register_operand" "")
474 (plus:DI (match_operand:DI 1 "register_operand" "")
475 (match_operand:DI 2 "const_int_operand" "")))]
476 "! add_operand (operands[2], DImode)
477 && operands[0] != stack_pointer_rtx
478 && operands[1] != frame_pointer_rtx
479 && operands[1] != arg_pointer_rtx"
480 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
481 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
482 {
483 HOST_WIDE_INT val = INTVAL (operands[2]);
484 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
485 HOST_WIDE_INT rest = val - low;
487 operands[4] = GEN_INT (low);
488 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
489 operands[3] = GEN_INT (rest);
490 else if (! no_new_pseudos)
491 {
492 operands[3] = gen_reg_rtx (DImode);
493 emit_move_insn (operands[3], operands[2]);
494 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
495 DONE;
496 }
497 else
498 FAIL;
499 })
501 (define_insn "*saddl"
502 [(set (match_operand:SI 0 "register_operand" "=r,r")
503 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
504 (match_operand:SI 2 "const48_operand" "I,I"))
505 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
506 ""
507 "@
508 s%2addl %1,%3,%0
509 s%2subl %1,%n3,%0")
511 (define_insn "*saddl_se"
512 [(set (match_operand:DI 0 "register_operand" "=r,r")
513 (sign_extend:DI
514 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
515 (match_operand:SI 2 "const48_operand" "I,I"))
516 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
517 ""
518 "@
519 s%2addl %1,%3,%0
520 s%2subl %1,%n3,%0")
522 (define_split
523 [(set (match_operand:DI 0 "register_operand" "")
524 (sign_extend:DI
525 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
526 [(match_operand 2 "" "")
527 (match_operand 3 "" "")])
528 (match_operand:SI 4 "const48_operand" ""))
529 (match_operand:SI 5 "sext_add_operand" ""))))
530 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
531 ""
532 [(set (match_dup 6) (match_dup 7))
533 (set (match_dup 0)
534 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
535 (match_dup 5))))]
536 {
537 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
538 operands[2], operands[3]);
539 operands[8] = gen_lowpart (SImode, operands[6]);
540 })
542 (define_insn "*saddq"
543 [(set (match_operand:DI 0 "register_operand" "=r,r")
544 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
545 (match_operand:DI 2 "const48_operand" "I,I"))
546 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
547 ""
548 "@
549 s%2addq %1,%3,%0
550 s%2subq %1,%n3,%0")
552 (define_insn "addvdi3"
553 [(set (match_operand:DI 0 "register_operand" "=r,r")
554 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
555 (match_operand:DI 2 "sext_add_operand" "rI,O")))
556 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
557 (sign_extend:TI (match_dup 2)))
558 (sign_extend:TI (plus:DI (match_dup 1)
559 (match_dup 2))))
560 (const_int 0))]
561 ""
562 "@
563 addqv %r1,%2,%0
564 subqv %r1,%n2,%0")
566 (define_insn "negsi2"
567 [(set (match_operand:SI 0 "register_operand" "=r")
568 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
569 ""
570 "subl $31,%1,%0")
572 (define_insn "*negsi_se"
573 [(set (match_operand:DI 0 "register_operand" "=r")
574 (sign_extend:DI (neg:SI
575 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
576 ""
577 "subl $31,%1,%0")
579 (define_insn "negvsi2"
580 [(set (match_operand:SI 0 "register_operand" "=r")
581 (neg:SI (match_operand:SI 1 "register_operand" "r")))
582 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
583 (sign_extend:DI (neg:SI (match_dup 1))))
584 (const_int 0))]
585 ""
586 "sublv $31,%1,%0")
588 (define_insn "negdi2"
589 [(set (match_operand:DI 0 "register_operand" "=r")
590 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
591 ""
592 "subq $31,%1,%0")
594 (define_insn "negvdi2"
595 [(set (match_operand:DI 0 "register_operand" "=r")
596 (neg:DI (match_operand:DI 1 "register_operand" "r")))
597 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
598 (sign_extend:TI (neg:DI (match_dup 1))))
599 (const_int 0))]
600 ""
601 "subqv $31,%1,%0")
603 (define_expand "subsi3"
604 [(set (match_operand:SI 0 "register_operand" "")
605 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
606 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
607 "! optimize"
608 "")
610 (define_insn "*subsi_internal"
611 [(set (match_operand:SI 0 "register_operand" "=r")
612 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
613 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
614 ""
615 "subl %r1,%2,%0")
617 (define_insn "*subsi_se"
618 [(set (match_operand:DI 0 "register_operand" "=r")
619 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
620 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
621 ""
622 "subl %r1,%2,%0")
624 (define_insn "*subsi_se2"
625 [(set (match_operand:DI 0 "register_operand" "=r")
626 (sign_extend:DI
627 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
628 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
629 0)))]
630 ""
631 "subl %r1,%2,%0")
633 (define_insn "subvsi3"
634 [(set (match_operand:SI 0 "register_operand" "=r")
635 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
636 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
637 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
638 (sign_extend:DI (match_dup 2)))
639 (sign_extend:DI (minus:SI (match_dup 1)
640 (match_dup 2))))
641 (const_int 0))]
642 ""
643 "sublv %r1,%2,%0")
645 (define_insn "subdi3"
646 [(set (match_operand:DI 0 "register_operand" "=r")
647 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
648 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
649 ""
650 "subq %r1,%2,%0")
652 (define_insn "*ssubl"
653 [(set (match_operand:SI 0 "register_operand" "=r")
654 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
655 (match_operand:SI 2 "const48_operand" "I"))
656 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
657 ""
658 "s%2subl %1,%3,%0")
660 (define_insn "*ssubl_se"
661 [(set (match_operand:DI 0 "register_operand" "=r")
662 (sign_extend:DI
663 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
664 (match_operand:SI 2 "const48_operand" "I"))
665 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
666 ""
667 "s%2subl %1,%3,%0")
669 (define_insn "*ssubq"
670 [(set (match_operand:DI 0 "register_operand" "=r")
671 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
672 (match_operand:DI 2 "const48_operand" "I"))
673 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
674 ""
675 "s%2subq %1,%3,%0")
677 (define_insn "subvdi3"
678 [(set (match_operand:DI 0 "register_operand" "=r")
679 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
680 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
681 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
682 (sign_extend:TI (match_dup 2)))
683 (sign_extend:TI (minus:DI (match_dup 1)
684 (match_dup 2))))
685 (const_int 0))]
686 ""
687 "subqv %r1,%2,%0")
689 ;; The Unicos/Mk assembler doesn't support mull.
691 (define_insn "mulsi3"
692 [(set (match_operand:SI 0 "register_operand" "=r")
693 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
694 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
695 "!TARGET_ABI_UNICOSMK"
696 "mull %r1,%2,%0"
697 [(set_attr "type" "imul")
698 (set_attr "opsize" "si")])
700 (define_insn "*mulsi_se"
701 [(set (match_operand:DI 0 "register_operand" "=r")
702 (sign_extend:DI
703 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
704 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
705 "!TARGET_ABI_UNICOSMK"
706 "mull %r1,%2,%0"
707 [(set_attr "type" "imul")
708 (set_attr "opsize" "si")])
710 (define_insn "mulvsi3"
711 [(set (match_operand:SI 0 "register_operand" "=r")
712 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
713 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
714 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
715 (sign_extend:DI (match_dup 2)))
716 (sign_extend:DI (mult:SI (match_dup 1)
717 (match_dup 2))))
718 (const_int 0))]
719 "!TARGET_ABI_UNICOSMK"
720 "mullv %r1,%2,%0"
721 [(set_attr "type" "imul")
722 (set_attr "opsize" "si")])
724 (define_insn "muldi3"
725 [(set (match_operand:DI 0 "register_operand" "=r")
726 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
727 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
728 ""
729 "mulq %r1,%2,%0"
730 [(set_attr "type" "imul")])
732 (define_insn "mulvdi3"
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
735 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
736 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
737 (sign_extend:TI (match_dup 2)))
738 (sign_extend:TI (mult:DI (match_dup 1)
739 (match_dup 2))))
740 (const_int 0))]
741 ""
742 "mulqv %r1,%2,%0"
743 [(set_attr "type" "imul")])
745 (define_expand "umuldi3_highpart"
746 [(set (match_operand:DI 0 "register_operand" "")
747 (truncate:DI
748 (lshiftrt:TI
749 (mult:TI (zero_extend:TI
750 (match_operand:DI 1 "register_operand" ""))
751 (match_operand:DI 2 "reg_or_8bit_operand" ""))
752 (const_int 64))))]
753 ""
754 {
755 if (REG_P (operands[2]))
756 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
757 })
759 (define_insn "*umuldi3_highpart_reg"
760 [(set (match_operand:DI 0 "register_operand" "=r")
761 (truncate:DI
762 (lshiftrt:TI
763 (mult:TI (zero_extend:TI
764 (match_operand:DI 1 "register_operand" "r"))
765 (zero_extend:TI
766 (match_operand:DI 2 "register_operand" "r")))
767 (const_int 64))))]
768 ""
769 "umulh %1,%2,%0"
770 [(set_attr "type" "imul")
771 (set_attr "opsize" "udi")])
773 (define_insn "*umuldi3_highpart_const"
774 [(set (match_operand:DI 0 "register_operand" "=r")
775 (truncate:DI
776 (lshiftrt:TI
777 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
778 (match_operand:TI 2 "cint8_operand" "I"))
779 (const_int 64))))]
780 ""
781 "umulh %1,%2,%0"
782 [(set_attr "type" "imul")
783 (set_attr "opsize" "udi")])
784 \f
785 ;; The divide and remainder operations take their inputs from r24 and
786 ;; r25, put their output in r27, and clobber r23 and r28 on all
787 ;; systems except Unicos/Mk. On Unicos, the standard library provides
788 ;; subroutines which use the standard calling convention and work on
789 ;; DImode operands.
791 ;; ??? Force sign-extension here because some versions of OSF/1 and
792 ;; Interix/NT don't do the right thing if the inputs are not properly
793 ;; sign-extended. But Linux, for instance, does not have this
794 ;; problem. Is it worth the complication here to eliminate the sign
795 ;; extension?
797 (define_expand "divsi3"
798 [(set (match_dup 3)
799 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
800 (set (match_dup 4)
801 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
802 (parallel [(set (match_dup 5)
803 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
804 (clobber (reg:DI 23))
805 (clobber (reg:DI 28))])
806 (set (match_operand:SI 0 "nonimmediate_operand" "")
807 (subreg:SI (match_dup 5) 0))]
808 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
809 {
810 operands[3] = gen_reg_rtx (DImode);
811 operands[4] = gen_reg_rtx (DImode);
812 operands[5] = gen_reg_rtx (DImode);
813 })
815 (define_expand "udivsi3"
816 [(set (match_dup 3)
817 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
818 (set (match_dup 4)
819 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
820 (parallel [(set (match_dup 5)
821 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
822 (clobber (reg:DI 23))
823 (clobber (reg:DI 28))])
824 (set (match_operand:SI 0 "nonimmediate_operand" "")
825 (subreg:SI (match_dup 5) 0))]
826 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
827 {
828 operands[3] = gen_reg_rtx (DImode);
829 operands[4] = gen_reg_rtx (DImode);
830 operands[5] = gen_reg_rtx (DImode);
831 })
833 (define_expand "modsi3"
834 [(set (match_dup 3)
835 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
836 (set (match_dup 4)
837 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
838 (parallel [(set (match_dup 5)
839 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
840 (clobber (reg:DI 23))
841 (clobber (reg:DI 28))])
842 (set (match_operand:SI 0 "nonimmediate_operand" "")
843 (subreg:SI (match_dup 5) 0))]
844 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
845 {
846 operands[3] = gen_reg_rtx (DImode);
847 operands[4] = gen_reg_rtx (DImode);
848 operands[5] = gen_reg_rtx (DImode);
849 })
851 (define_expand "umodsi3"
852 [(set (match_dup 3)
853 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
854 (set (match_dup 4)
855 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
856 (parallel [(set (match_dup 5)
857 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
858 (clobber (reg:DI 23))
859 (clobber (reg:DI 28))])
860 (set (match_operand:SI 0 "nonimmediate_operand" "")
861 (subreg:SI (match_dup 5) 0))]
862 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
863 {
864 operands[3] = gen_reg_rtx (DImode);
865 operands[4] = gen_reg_rtx (DImode);
866 operands[5] = gen_reg_rtx (DImode);
867 })
869 (define_expand "divdi3"
870 [(parallel [(set (match_operand:DI 0 "register_operand" "")
871 (div:DI (match_operand:DI 1 "register_operand" "")
872 (match_operand:DI 2 "register_operand" "")))
873 (clobber (reg:DI 23))
874 (clobber (reg:DI 28))])]
875 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
876 "")
878 (define_expand "udivdi3"
879 [(parallel [(set (match_operand:DI 0 "register_operand" "")
880 (udiv:DI (match_operand:DI 1 "register_operand" "")
881 (match_operand:DI 2 "register_operand" "")))
882 (clobber (reg:DI 23))
883 (clobber (reg:DI 28))])]
884 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
885 "")
887 (define_expand "moddi3"
888 [(use (match_operand:DI 0 "register_operand" ""))
889 (use (match_operand:DI 1 "register_operand" ""))
890 (use (match_operand:DI 2 "register_operand" ""))]
891 "!TARGET_ABI_OPEN_VMS"
892 {
893 if (TARGET_ABI_UNICOSMK)
894 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
895 else
896 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
897 DONE;
898 })
900 (define_expand "moddi3_dft"
901 [(parallel [(set (match_operand:DI 0 "register_operand" "")
902 (mod:DI (match_operand:DI 1 "register_operand" "")
903 (match_operand:DI 2 "register_operand" "")))
904 (clobber (reg:DI 23))
905 (clobber (reg:DI 28))])]
906 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
907 "")
909 ;; On Unicos/Mk, we do as the system's C compiler does:
910 ;; compute the quotient, multiply and subtract.
912 (define_expand "moddi3_umk"
913 [(use (match_operand:DI 0 "register_operand" ""))
914 (use (match_operand:DI 1 "register_operand" ""))
915 (use (match_operand:DI 2 "register_operand" ""))]
916 "TARGET_ABI_UNICOSMK"
917 {
918 rtx div, mul = gen_reg_rtx (DImode);
920 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
921 NULL_RTX, 0, OPTAB_LIB);
922 div = force_reg (DImode, div);
923 emit_insn (gen_muldi3 (mul, operands[2], div));
924 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
925 DONE;
926 })
928 (define_expand "umoddi3"
929 [(use (match_operand:DI 0 "register_operand" ""))
930 (use (match_operand:DI 1 "register_operand" ""))
931 (use (match_operand:DI 2 "register_operand" ""))]
932 "! TARGET_ABI_OPEN_VMS"
933 {
934 if (TARGET_ABI_UNICOSMK)
935 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
936 else
937 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
938 DONE;
939 })
941 (define_expand "umoddi3_dft"
942 [(parallel [(set (match_operand:DI 0 "register_operand" "")
943 (umod:DI (match_operand:DI 1 "register_operand" "")
944 (match_operand:DI 2 "register_operand" "")))
945 (clobber (reg:DI 23))
946 (clobber (reg:DI 28))])]
947 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
948 "")
950 (define_expand "umoddi3_umk"
951 [(use (match_operand:DI 0 "register_operand" ""))
952 (use (match_operand:DI 1 "register_operand" ""))
953 (use (match_operand:DI 2 "register_operand" ""))]
954 "TARGET_ABI_UNICOSMK"
955 {
956 rtx div, mul = gen_reg_rtx (DImode);
958 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
959 NULL_RTX, 1, OPTAB_LIB);
960 div = force_reg (DImode, div);
961 emit_insn (gen_muldi3 (mul, operands[2], div));
962 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
963 DONE;
964 })
966 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
967 ;; expanded by the assembler.
969 (define_insn_and_split "*divmodsi_internal_er"
970 [(set (match_operand:DI 0 "register_operand" "=c")
971 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
972 [(match_operand:DI 1 "register_operand" "a")
973 (match_operand:DI 2 "register_operand" "b")])))
974 (clobber (reg:DI 23))
975 (clobber (reg:DI 28))]
976 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
977 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
978 "&& reload_completed"
979 [(parallel [(set (match_dup 0)
980 (sign_extend:DI (match_dup 3)))
981 (use (match_dup 0))
982 (use (match_dup 4))
983 (clobber (reg:DI 23))
984 (clobber (reg:DI 28))])]
985 {
986 const char *str;
987 switch (GET_CODE (operands[3]))
988 {
989 case DIV:
990 str = "__divl";
991 break;
992 case UDIV:
993 str = "__divlu";
994 break;
995 case MOD:
996 str = "__reml";
997 break;
998 case UMOD:
999 str = "__remlu";
1000 break;
1001 default:
1002 abort ();
1003 }
1004 operands[4] = GEN_INT (alpha_next_sequence_number++);
1005 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1006 gen_rtx_SYMBOL_REF (DImode, str),
1007 operands[4]));
1008 }
1009 [(set_attr "type" "jsr")
1010 (set_attr "length" "8")])
1012 (define_insn "*divmodsi_internal_er_1"
1013 [(set (match_operand:DI 0 "register_operand" "=c")
1014 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1015 [(match_operand:DI 1 "register_operand" "a")
1016 (match_operand:DI 2 "register_operand" "b")])))
1017 (use (match_operand:DI 4 "register_operand" "c"))
1018 (use (match_operand 5 "const_int_operand" ""))
1019 (clobber (reg:DI 23))
1020 (clobber (reg:DI 28))]
1021 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1022 "jsr $23,($27),__%E3%J5"
1023 [(set_attr "type" "jsr")
1024 (set_attr "length" "4")])
1026 (define_insn "*divmodsi_internal"
1027 [(set (match_operand:DI 0 "register_operand" "=c")
1028 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1029 [(match_operand:DI 1 "register_operand" "a")
1030 (match_operand:DI 2 "register_operand" "b")])))
1031 (clobber (reg:DI 23))
1032 (clobber (reg:DI 28))]
1033 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1034 "%E3 %1,%2,%0"
1035 [(set_attr "type" "jsr")
1036 (set_attr "length" "8")])
1038 (define_insn_and_split "*divmoddi_internal_er"
1039 [(set (match_operand:DI 0 "register_operand" "=c")
1040 (match_operator:DI 3 "divmod_operator"
1041 [(match_operand:DI 1 "register_operand" "a")
1042 (match_operand:DI 2 "register_operand" "b")]))
1043 (clobber (reg:DI 23))
1044 (clobber (reg:DI 28))]
1045 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1046 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1047 "&& reload_completed"
1048 [(parallel [(set (match_dup 0) (match_dup 3))
1049 (use (match_dup 0))
1050 (use (match_dup 4))
1051 (clobber (reg:DI 23))
1052 (clobber (reg:DI 28))])]
1053 {
1054 const char *str;
1055 switch (GET_CODE (operands[3]))
1056 {
1057 case DIV:
1058 str = "__divq";
1059 break;
1060 case UDIV:
1061 str = "__divqu";
1062 break;
1063 case MOD:
1064 str = "__remq";
1065 break;
1066 case UMOD:
1067 str = "__remqu";
1068 break;
1069 default:
1070 abort ();
1071 }
1072 operands[4] = GEN_INT (alpha_next_sequence_number++);
1073 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1074 gen_rtx_SYMBOL_REF (DImode, str),
1075 operands[4]));
1076 }
1077 [(set_attr "type" "jsr")
1078 (set_attr "length" "8")])
1080 (define_insn "*divmoddi_internal_er_1"
1081 [(set (match_operand:DI 0 "register_operand" "=c")
1082 (match_operator:DI 3 "divmod_operator"
1083 [(match_operand:DI 1 "register_operand" "a")
1084 (match_operand:DI 2 "register_operand" "b")]))
1085 (use (match_operand:DI 4 "register_operand" "c"))
1086 (use (match_operand 5 "const_int_operand" ""))
1087 (clobber (reg:DI 23))
1088 (clobber (reg:DI 28))]
1089 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1090 "jsr $23,($27),__%E3%J5"
1091 [(set_attr "type" "jsr")
1092 (set_attr "length" "4")])
1094 (define_insn "*divmoddi_internal"
1095 [(set (match_operand:DI 0 "register_operand" "=c")
1096 (match_operator:DI 3 "divmod_operator"
1097 [(match_operand:DI 1 "register_operand" "a")
1098 (match_operand:DI 2 "register_operand" "b")]))
1099 (clobber (reg:DI 23))
1100 (clobber (reg:DI 28))]
1101 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1102 "%E3 %1,%2,%0"
1103 [(set_attr "type" "jsr")
1104 (set_attr "length" "8")])
1105 \f
1106 ;; Next are the basic logical operations. These only exist in DImode.
1108 (define_insn "anddi3"
1109 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1110 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1111 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1112 ""
1113 "@
1114 and %r1,%2,%0
1115 bic %r1,%N2,%0
1116 zapnot %r1,%m2,%0"
1117 [(set_attr "type" "ilog,ilog,shift")])
1119 ;; There are times when we can split an AND into two AND insns. This occurs
1120 ;; when we can first clear any bytes and then clear anything else. For
1121 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1122 ;; Only do this when running on 64-bit host since the computations are
1123 ;; too messy otherwise.
1125 (define_split
1126 [(set (match_operand:DI 0 "register_operand" "")
1127 (and:DI (match_operand:DI 1 "register_operand" "")
1128 (match_operand:DI 2 "const_int_operand" "")))]
1129 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1130 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1131 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1132 {
1133 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1134 unsigned HOST_WIDE_INT mask2 = mask1;
1135 int i;
1137 /* For each byte that isn't all zeros, make it all ones. */
1138 for (i = 0; i < 64; i += 8)
1139 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1140 mask1 |= (HOST_WIDE_INT) 0xff << i;
1142 /* Now turn on any bits we've just turned off. */
1143 mask2 |= ~ mask1;
1145 operands[3] = GEN_INT (mask1);
1146 operands[4] = GEN_INT (mask2);
1147 })
1149 (define_expand "zero_extendqihi2"
1150 [(set (match_operand:HI 0 "register_operand" "")
1151 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1152 ""
1153 {
1154 if (! TARGET_BWX)
1155 operands[1] = force_reg (QImode, operands[1]);
1156 })
1158 (define_insn "*zero_extendqihi2_bwx"
1159 [(set (match_operand:HI 0 "register_operand" "=r,r")
1160 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1161 "TARGET_BWX"
1162 "@
1163 and %1,0xff,%0
1164 ldbu %0,%1"
1165 [(set_attr "type" "ilog,ild")])
1167 (define_insn "*zero_extendqihi2_nobwx"
1168 [(set (match_operand:HI 0 "register_operand" "=r")
1169 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1170 "! TARGET_BWX"
1171 "and %1,0xff,%0"
1172 [(set_attr "type" "ilog")])
1174 (define_expand "zero_extendqisi2"
1175 [(set (match_operand:SI 0 "register_operand" "")
1176 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1177 ""
1178 {
1179 if (! TARGET_BWX)
1180 operands[1] = force_reg (QImode, operands[1]);
1181 })
1183 (define_insn "*zero_extendqisi2_bwx"
1184 [(set (match_operand:SI 0 "register_operand" "=r,r")
1185 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1186 "TARGET_BWX"
1187 "@
1188 and %1,0xff,%0
1189 ldbu %0,%1"
1190 [(set_attr "type" "ilog,ild")])
1192 (define_insn "*zero_extendqisi2_nobwx"
1193 [(set (match_operand:SI 0 "register_operand" "=r")
1194 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1195 "! TARGET_BWX"
1196 "and %1,0xff,%0"
1197 [(set_attr "type" "ilog")])
1199 (define_expand "zero_extendqidi2"
1200 [(set (match_operand:DI 0 "register_operand" "")
1201 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1202 ""
1203 {
1204 if (! TARGET_BWX)
1205 operands[1] = force_reg (QImode, operands[1]);
1206 })
1208 (define_insn "*zero_extendqidi2_bwx"
1209 [(set (match_operand:DI 0 "register_operand" "=r,r")
1210 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1211 "TARGET_BWX"
1212 "@
1213 and %1,0xff,%0
1214 ldbu %0,%1"
1215 [(set_attr "type" "ilog,ild")])
1217 (define_insn "*zero_extendqidi2_nobwx"
1218 [(set (match_operand:DI 0 "register_operand" "=r")
1219 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1220 "! TARGET_BWX"
1221 "and %1,0xff,%0"
1222 [(set_attr "type" "ilog")])
1224 (define_expand "zero_extendhisi2"
1225 [(set (match_operand:SI 0 "register_operand" "")
1226 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1227 ""
1228 {
1229 if (! TARGET_BWX)
1230 operands[1] = force_reg (HImode, operands[1]);
1231 })
1233 (define_insn "*zero_extendhisi2_bwx"
1234 [(set (match_operand:SI 0 "register_operand" "=r,r")
1235 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1236 "TARGET_BWX"
1237 "@
1238 zapnot %1,3,%0
1239 ldwu %0,%1"
1240 [(set_attr "type" "shift,ild")])
1242 (define_insn "*zero_extendhisi2_nobwx"
1243 [(set (match_operand:SI 0 "register_operand" "=r")
1244 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1245 "! TARGET_BWX"
1246 "zapnot %1,3,%0"
1247 [(set_attr "type" "shift")])
1249 (define_expand "zero_extendhidi2"
1250 [(set (match_operand:DI 0 "register_operand" "")
1251 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1252 ""
1253 {
1254 if (! TARGET_BWX)
1255 operands[1] = force_reg (HImode, operands[1]);
1256 })
1258 (define_insn "*zero_extendhidi2_bwx"
1259 [(set (match_operand:DI 0 "register_operand" "=r,r")
1260 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1261 "TARGET_BWX"
1262 "@
1263 zapnot %1,3,%0
1264 ldwu %0,%1"
1265 [(set_attr "type" "shift,ild")])
1267 (define_insn "*zero_extendhidi2_nobwx"
1268 [(set (match_operand:DI 0 "register_operand" "=r")
1269 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1270 ""
1271 "zapnot %1,3,%0"
1272 [(set_attr "type" "shift")])
1274 (define_insn "zero_extendsidi2"
1275 [(set (match_operand:DI 0 "register_operand" "=r")
1276 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1277 ""
1278 "zapnot %1,15,%0"
1279 [(set_attr "type" "shift")])
1281 (define_insn "andnotdi3"
1282 [(set (match_operand:DI 0 "register_operand" "=r")
1283 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1284 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1285 ""
1286 "bic %r2,%1,%0"
1287 [(set_attr "type" "ilog")])
1289 (define_insn "iordi3"
1290 [(set (match_operand:DI 0 "register_operand" "=r,r")
1291 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1292 (match_operand:DI 2 "or_operand" "rI,N")))]
1293 ""
1294 "@
1295 bis %r1,%2,%0
1296 ornot %r1,%N2,%0"
1297 [(set_attr "type" "ilog")])
1299 (define_insn "one_cmpldi2"
1300 [(set (match_operand:DI 0 "register_operand" "=r")
1301 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1302 ""
1303 "ornot $31,%1,%0"
1304 [(set_attr "type" "ilog")])
1306 (define_insn "*iornot"
1307 [(set (match_operand:DI 0 "register_operand" "=r")
1308 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1309 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1310 ""
1311 "ornot %r2,%1,%0"
1312 [(set_attr "type" "ilog")])
1314 (define_insn "xordi3"
1315 [(set (match_operand:DI 0 "register_operand" "=r,r")
1316 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1317 (match_operand:DI 2 "or_operand" "rI,N")))]
1318 ""
1319 "@
1320 xor %r1,%2,%0
1321 eqv %r1,%N2,%0"
1322 [(set_attr "type" "ilog")])
1324 (define_insn "*xornot"
1325 [(set (match_operand:DI 0 "register_operand" "=r")
1326 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1327 (match_operand:DI 2 "register_operand" "rI"))))]
1328 ""
1329 "eqv %r1,%2,%0"
1330 [(set_attr "type" "ilog")])
1331 \f
1332 ;; Handle FFS and related insns iff we support CIX.
1334 (define_expand "ffsdi2"
1335 [(set (match_dup 2)
1336 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1337 (set (match_dup 3)
1338 (plus:DI (match_dup 2) (const_int 1)))
1339 (set (match_operand:DI 0 "register_operand" "")
1340 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1341 (const_int 0) (match_dup 3)))]
1342 "TARGET_CIX"
1343 {
1344 operands[2] = gen_reg_rtx (DImode);
1345 operands[3] = gen_reg_rtx (DImode);
1346 })
1348 (define_insn "*cttz"
1349 [(set (match_operand:DI 0 "register_operand" "=r")
1350 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1351 "TARGET_CIX"
1352 "cttz %1,%0"
1353 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1354 ; reuse the existing type name.
1355 [(set_attr "type" "mvi")])
1357 (define_insn "clzdi2"
1358 [(set (match_operand:DI 0 "register_operand" "=r")
1359 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1360 "TARGET_CIX"
1361 "ctlz %1,%0"
1362 [(set_attr "type" "mvi")])
1364 (define_insn "ctzdi2"
1365 [(set (match_operand:DI 0 "register_operand" "=r")
1366 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1367 "TARGET_CIX"
1368 "cttz %1,%0"
1369 [(set_attr "type" "mvi")])
1371 (define_insn "popcountdi2"
1372 [(set (match_operand:DI 0 "register_operand" "=r")
1373 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1374 "TARGET_CIX"
1375 "ctpop %1,%0"
1376 [(set_attr "type" "mvi")])
1377 \f
1378 ;; Next come the shifts and the various extract and insert operations.
1380 (define_insn "ashldi3"
1381 [(set (match_operand:DI 0 "register_operand" "=r,r")
1382 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1383 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1384 ""
1385 {
1386 switch (which_alternative)
1387 {
1388 case 0:
1389 if (operands[2] == const1_rtx)
1390 return "addq %r1,%r1,%0";
1391 else
1392 return "s%P2addq %r1,0,%0";
1393 case 1:
1394 return "sll %r1,%2,%0";
1395 default:
1396 abort();
1397 }
1398 }
1399 [(set_attr "type" "iadd,shift")])
1401 (define_insn "*ashldi_se"
1402 [(set (match_operand:DI 0 "register_operand" "=r")
1403 (sign_extend:DI
1404 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1405 (match_operand:DI 2 "const_int_operand" "P"))
1406 0)))]
1407 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1408 {
1409 if (operands[2] == const1_rtx)
1410 return "addl %r1,%r1,%0";
1411 else
1412 return "s%P2addl %r1,0,%0";
1413 }
1414 [(set_attr "type" "iadd")])
1416 (define_insn "lshrdi3"
1417 [(set (match_operand:DI 0 "register_operand" "=r")
1418 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1419 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1420 ""
1421 "srl %r1,%2,%0"
1422 [(set_attr "type" "shift")])
1424 (define_insn "ashrdi3"
1425 [(set (match_operand:DI 0 "register_operand" "=r")
1426 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1427 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1428 ""
1429 "sra %r1,%2,%0"
1430 [(set_attr "type" "shift")])
1432 (define_expand "extendqihi2"
1433 [(set (match_dup 2)
1434 (ashift:DI (match_operand:QI 1 "some_operand" "")
1435 (const_int 56)))
1436 (set (match_operand:HI 0 "register_operand" "")
1437 (ashiftrt:DI (match_dup 2)
1438 (const_int 56)))]
1439 ""
1440 {
1441 if (TARGET_BWX)
1442 {
1443 emit_insn (gen_extendqihi2x (operands[0],
1444 force_reg (QImode, operands[1])));
1445 DONE;
1446 }
1448 /* If we have an unaligned MEM, extend to DImode (which we do
1449 specially) and then copy to the result. */
1450 if (unaligned_memory_operand (operands[1], HImode))
1451 {
1452 rtx temp = gen_reg_rtx (DImode);
1454 emit_insn (gen_extendqidi2 (temp, operands[1]));
1455 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1456 DONE;
1457 }
1459 operands[0] = gen_lowpart (DImode, operands[0]);
1460 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1461 operands[2] = gen_reg_rtx (DImode);
1462 })
1464 (define_insn "extendqidi2x"
1465 [(set (match_operand:DI 0 "register_operand" "=r")
1466 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1467 "TARGET_BWX"
1468 "sextb %1,%0"
1469 [(set_attr "type" "shift")])
1471 (define_insn "extendhidi2x"
1472 [(set (match_operand:DI 0 "register_operand" "=r")
1473 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1474 "TARGET_BWX"
1475 "sextw %1,%0"
1476 [(set_attr "type" "shift")])
1478 (define_insn "extendqisi2x"
1479 [(set (match_operand:SI 0 "register_operand" "=r")
1480 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1481 "TARGET_BWX"
1482 "sextb %1,%0"
1483 [(set_attr "type" "shift")])
1485 (define_insn "extendhisi2x"
1486 [(set (match_operand:SI 0 "register_operand" "=r")
1487 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1488 "TARGET_BWX"
1489 "sextw %1,%0"
1490 [(set_attr "type" "shift")])
1492 (define_insn "extendqihi2x"
1493 [(set (match_operand:HI 0 "register_operand" "=r")
1494 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1495 "TARGET_BWX"
1496 "sextb %1,%0"
1497 [(set_attr "type" "shift")])
1499 (define_expand "extendqisi2"
1500 [(set (match_dup 2)
1501 (ashift:DI (match_operand:QI 1 "some_operand" "")
1502 (const_int 56)))
1503 (set (match_operand:SI 0 "register_operand" "")
1504 (ashiftrt:DI (match_dup 2)
1505 (const_int 56)))]
1506 ""
1507 {
1508 if (TARGET_BWX)
1509 {
1510 emit_insn (gen_extendqisi2x (operands[0],
1511 force_reg (QImode, operands[1])));
1512 DONE;
1513 }
1515 /* If we have an unaligned MEM, extend to a DImode form of
1516 the result (which we do specially). */
1517 if (unaligned_memory_operand (operands[1], QImode))
1518 {
1519 rtx temp = gen_reg_rtx (DImode);
1521 emit_insn (gen_extendqidi2 (temp, operands[1]));
1522 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1523 DONE;
1524 }
1526 operands[0] = gen_lowpart (DImode, operands[0]);
1527 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1528 operands[2] = gen_reg_rtx (DImode);
1529 })
1531 (define_expand "extendqidi2"
1532 [(set (match_dup 2)
1533 (ashift:DI (match_operand:QI 1 "some_operand" "")
1534 (const_int 56)))
1535 (set (match_operand:DI 0 "register_operand" "")
1536 (ashiftrt:DI (match_dup 2)
1537 (const_int 56)))]
1538 ""
1539 {
1540 if (TARGET_BWX)
1541 {
1542 emit_insn (gen_extendqidi2x (operands[0],
1543 force_reg (QImode, operands[1])));
1544 DONE;
1545 }
1547 if (unaligned_memory_operand (operands[1], QImode))
1548 {
1549 rtx seq
1550 = gen_unaligned_extendqidi (operands[0],
1551 get_unaligned_address (operands[1], 1));
1553 alpha_set_memflags (seq, operands[1]);
1554 emit_insn (seq);
1555 DONE;
1556 }
1558 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1559 operands[2] = gen_reg_rtx (DImode);
1560 })
1562 (define_expand "extendhisi2"
1563 [(set (match_dup 2)
1564 (ashift:DI (match_operand:HI 1 "some_operand" "")
1565 (const_int 48)))
1566 (set (match_operand:SI 0 "register_operand" "")
1567 (ashiftrt:DI (match_dup 2)
1568 (const_int 48)))]
1569 ""
1570 {
1571 if (TARGET_BWX)
1572 {
1573 emit_insn (gen_extendhisi2x (operands[0],
1574 force_reg (HImode, operands[1])));
1575 DONE;
1576 }
1578 /* If we have an unaligned MEM, extend to a DImode form of
1579 the result (which we do specially). */
1580 if (unaligned_memory_operand (operands[1], HImode))
1581 {
1582 rtx temp = gen_reg_rtx (DImode);
1584 emit_insn (gen_extendhidi2 (temp, operands[1]));
1585 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1586 DONE;
1587 }
1589 operands[0] = gen_lowpart (DImode, operands[0]);
1590 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1591 operands[2] = gen_reg_rtx (DImode);
1592 })
1594 (define_expand "extendhidi2"
1595 [(set (match_dup 2)
1596 (ashift:DI (match_operand:HI 1 "some_operand" "")
1597 (const_int 48)))
1598 (set (match_operand:DI 0 "register_operand" "")
1599 (ashiftrt:DI (match_dup 2)
1600 (const_int 48)))]
1601 ""
1602 {
1603 if (TARGET_BWX)
1604 {
1605 emit_insn (gen_extendhidi2x (operands[0],
1606 force_reg (HImode, operands[1])));
1607 DONE;
1608 }
1610 if (unaligned_memory_operand (operands[1], HImode))
1611 {
1612 rtx seq
1613 = gen_unaligned_extendhidi (operands[0],
1614 get_unaligned_address (operands[1], 2));
1616 alpha_set_memflags (seq, operands[1]);
1617 emit_insn (seq);
1618 DONE;
1619 }
1621 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1622 operands[2] = gen_reg_rtx (DImode);
1623 })
1625 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1626 ;; as a pattern saves one instruction. The code is similar to that for
1627 ;; the unaligned loads (see below).
1628 ;;
1629 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1630 (define_expand "unaligned_extendqidi"
1631 [(use (match_operand:QI 0 "register_operand" ""))
1632 (use (match_operand:DI 1 "address_operand" ""))]
1633 ""
1634 {
1635 if (WORDS_BIG_ENDIAN)
1636 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1637 else
1638 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1639 DONE;
1640 })
1642 (define_expand "unaligned_extendqidi_le"
1643 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1644 (set (match_dup 3)
1645 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1646 (const_int -8))))
1647 (set (match_dup 4)
1648 (ashift:DI (match_dup 3)
1649 (minus:DI (const_int 64)
1650 (ashift:DI
1651 (and:DI (match_dup 2) (const_int 7))
1652 (const_int 3)))))
1653 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1654 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1655 "! WORDS_BIG_ENDIAN"
1656 {
1657 operands[2] = gen_reg_rtx (DImode);
1658 operands[3] = gen_reg_rtx (DImode);
1659 operands[4] = gen_reg_rtx (DImode);
1660 })
1662 (define_expand "unaligned_extendqidi_be"
1663 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1664 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1665 (set (match_dup 4)
1666 (mem:DI (and:DI (match_dup 3)
1667 (const_int -8))))
1668 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1669 (set (match_dup 6)
1670 (ashift:DI (match_dup 4)
1671 (ashift:DI
1672 (and:DI
1673 (plus:DI (match_dup 5) (const_int 1))
1674 (const_int 7))
1675 (const_int 3))))
1676 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1677 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1678 "WORDS_BIG_ENDIAN"
1679 {
1680 operands[2] = gen_reg_rtx (DImode);
1681 operands[3] = gen_reg_rtx (DImode);
1682 operands[4] = gen_reg_rtx (DImode);
1683 operands[5] = gen_reg_rtx (DImode);
1684 operands[6] = gen_reg_rtx (DImode);
1685 })
1687 (define_expand "unaligned_extendhidi"
1688 [(use (match_operand:QI 0 "register_operand" ""))
1689 (use (match_operand:DI 1 "address_operand" ""))]
1690 ""
1691 {
1692 operands[0] = gen_lowpart (DImode, operands[0]);
1693 emit_insn ((WORDS_BIG_ENDIAN
1694 ? gen_unaligned_extendhidi_be
1695 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1696 DONE;
1697 })
1699 (define_expand "unaligned_extendhidi_le"
1700 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1701 (set (match_dup 3)
1702 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1703 (const_int -8))))
1704 (set (match_dup 4)
1705 (ashift:DI (match_dup 3)
1706 (minus:DI (const_int 64)
1707 (ashift:DI
1708 (and:DI (match_dup 2) (const_int 7))
1709 (const_int 3)))))
1710 (set (match_operand:DI 0 "register_operand" "")
1711 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1712 "! WORDS_BIG_ENDIAN"
1713 {
1714 operands[2] = gen_reg_rtx (DImode);
1715 operands[3] = gen_reg_rtx (DImode);
1716 operands[4] = gen_reg_rtx (DImode);
1717 })
1719 (define_expand "unaligned_extendhidi_be"
1720 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1721 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1722 (set (match_dup 4)
1723 (mem:DI (and:DI (match_dup 3)
1724 (const_int -8))))
1725 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1726 (set (match_dup 6)
1727 (ashift:DI (match_dup 4)
1728 (ashift:DI
1729 (and:DI
1730 (plus:DI (match_dup 5) (const_int 1))
1731 (const_int 7))
1732 (const_int 3))))
1733 (set (match_operand:DI 0 "register_operand" "")
1734 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1735 "WORDS_BIG_ENDIAN"
1736 {
1737 operands[2] = gen_reg_rtx (DImode);
1738 operands[3] = gen_reg_rtx (DImode);
1739 operands[4] = gen_reg_rtx (DImode);
1740 operands[5] = gen_reg_rtx (DImode);
1741 operands[6] = gen_reg_rtx (DImode);
1742 })
1744 (define_insn "*extxl_const"
1745 [(set (match_operand:DI 0 "register_operand" "=r")
1746 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1747 (match_operand:DI 2 "mode_width_operand" "n")
1748 (match_operand:DI 3 "mul8_operand" "I")))]
1749 ""
1750 "ext%M2l %r1,%s3,%0"
1751 [(set_attr "type" "shift")])
1753 (define_insn "extxl_le"
1754 [(set (match_operand:DI 0 "register_operand" "=r")
1755 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1756 (match_operand:DI 2 "mode_width_operand" "n")
1757 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1758 (const_int 3))))]
1759 "! WORDS_BIG_ENDIAN"
1760 "ext%M2l %r1,%3,%0"
1761 [(set_attr "type" "shift")])
1763 (define_insn "extxl_be"
1764 [(set (match_operand:DI 0 "register_operand" "=r")
1765 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1766 (match_operand:DI 2 "mode_width_operand" "n")
1767 (minus:DI
1768 (const_int 56)
1769 (ashift:DI
1770 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1771 (const_int 3)))))]
1772 "WORDS_BIG_ENDIAN"
1773 "ext%M2l %r1,%3,%0"
1774 [(set_attr "type" "shift")])
1776 ;; Combine has some strange notion of preserving existing undefined behavior
1777 ;; in shifts larger than a word size. So capture these patterns that it
1778 ;; should have turned into zero_extracts.
1780 (define_insn "*extxl_1_le"
1781 [(set (match_operand:DI 0 "register_operand" "=r")
1782 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1783 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1784 (const_int 3)))
1785 (match_operand:DI 3 "mode_mask_operand" "n")))]
1786 "! WORDS_BIG_ENDIAN"
1787 "ext%U3l %1,%2,%0"
1788 [(set_attr "type" "shift")])
1790 (define_insn "*extxl_1_be"
1791 [(set (match_operand:DI 0 "register_operand" "=r")
1792 (and:DI (lshiftrt:DI
1793 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1794 (minus:DI (const_int 56)
1795 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1796 (const_int 3))))
1797 (match_operand:DI 3 "mode_mask_operand" "n")))]
1798 "WORDS_BIG_ENDIAN"
1799 "ext%U3l %1,%2,%0"
1800 [(set_attr "type" "shift")])
1802 (define_insn "*extql_2_le"
1803 [(set (match_operand:DI 0 "register_operand" "=r")
1804 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1805 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1806 (const_int 3))))]
1807 "! WORDS_BIG_ENDIAN"
1808 "extql %1,%2,%0"
1809 [(set_attr "type" "shift")])
1811 (define_insn "*extql_2_be"
1812 [(set (match_operand:DI 0 "register_operand" "=r")
1813 (lshiftrt:DI
1814 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1815 (minus:DI (const_int 56)
1816 (ashift:DI
1817 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1818 (const_int 3)))))]
1819 "WORDS_BIG_ENDIAN"
1820 "extql %1,%2,%0"
1821 [(set_attr "type" "shift")])
1823 (define_insn "extqh_le"
1824 [(set (match_operand:DI 0 "register_operand" "=r")
1825 (ashift:DI
1826 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1827 (minus:DI (const_int 64)
1828 (ashift:DI
1829 (and:DI
1830 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1831 (const_int 7))
1832 (const_int 3)))))]
1833 "! WORDS_BIG_ENDIAN"
1834 "extqh %r1,%2,%0"
1835 [(set_attr "type" "shift")])
1837 (define_insn "extqh_be"
1838 [(set (match_operand:DI 0 "register_operand" "=r")
1839 (ashift:DI
1840 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1841 (ashift:DI
1842 (and:DI
1843 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1844 (const_int 1))
1845 (const_int 7))
1846 (const_int 3))))]
1847 "WORDS_BIG_ENDIAN"
1848 "extqh %r1,%2,%0"
1849 [(set_attr "type" "shift")])
1851 (define_insn "extlh_le"
1852 [(set (match_operand:DI 0 "register_operand" "=r")
1853 (ashift:DI
1854 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1855 (const_int 2147483647))
1856 (minus:DI (const_int 64)
1857 (ashift:DI
1858 (and:DI
1859 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1860 (const_int 7))
1861 (const_int 3)))))]
1862 "! WORDS_BIG_ENDIAN"
1863 "extlh %r1,%2,%0"
1864 [(set_attr "type" "shift")])
1866 (define_insn "extlh_be"
1867 [(set (match_operand:DI 0 "register_operand" "=r")
1868 (and:DI
1869 (ashift:DI
1870 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1871 (ashift:DI
1872 (and:DI
1873 (plus:DI
1874 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1875 (const_int 1))
1876 (const_int 7))
1877 (const_int 3)))
1878 (const_int 2147483647)))]
1879 "WORDS_BIG_ENDIAN"
1880 "extlh %r1,%2,%0"
1881 [(set_attr "type" "shift")])
1883 (define_insn "extwh_le"
1884 [(set (match_operand:DI 0 "register_operand" "=r")
1885 (ashift:DI
1886 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1887 (const_int 65535))
1888 (minus:DI (const_int 64)
1889 (ashift:DI
1890 (and:DI
1891 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1892 (const_int 7))
1893 (const_int 3)))))]
1894 "! WORDS_BIG_ENDIAN"
1895 "extwh %r1,%2,%0"
1896 [(set_attr "type" "shift")])
1898 (define_insn "extwh_be"
1899 [(set (match_operand:DI 0 "register_operand" "=r")
1900 (and:DI
1901 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1902 (ashift:DI
1903 (and:DI
1904 (plus:DI
1905 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1906 (const_int 1))
1907 (const_int 7))
1908 (const_int 3)))
1909 (const_int 65535)))]
1910 "WORDS_BIG_ENDIAN"
1911 "extwh %r1,%2,%0"
1912 [(set_attr "type" "shift")])
1914 ;; This converts an extXl into an extXh with an appropriate adjustment
1915 ;; to the address calculation.
1917 ;;(define_split
1918 ;; [(set (match_operand:DI 0 "register_operand" "")
1919 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1920 ;; (match_operand:DI 2 "mode_width_operand" "")
1921 ;; (ashift:DI (match_operand:DI 3 "" "")
1922 ;; (const_int 3)))
1923 ;; (match_operand:DI 4 "const_int_operand" "")))
1924 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1925 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1926 ;; [(set (match_dup 5) (match_dup 6))
1927 ;; (set (match_dup 0)
1928 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1929 ;; (ashift:DI (plus:DI (match_dup 5)
1930 ;; (match_dup 7))
1931 ;; (const_int 3)))
1932 ;; (match_dup 4)))]
1933 ;; "
1934 ;;{
1935 ;; operands[6] = plus_constant (operands[3],
1936 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1937 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1938 ;;}")
1940 (define_insn "*insbl_const"
1941 [(set (match_operand:DI 0 "register_operand" "=r")
1942 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1943 (match_operand:DI 2 "mul8_operand" "I")))]
1944 ""
1945 "insbl %1,%s2,%0"
1946 [(set_attr "type" "shift")])
1948 (define_insn "*inswl_const"
1949 [(set (match_operand:DI 0 "register_operand" "=r")
1950 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1951 (match_operand:DI 2 "mul8_operand" "I")))]
1952 ""
1953 "inswl %1,%s2,%0"
1954 [(set_attr "type" "shift")])
1956 (define_insn "*insll_const"
1957 [(set (match_operand:DI 0 "register_operand" "=r")
1958 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1959 (match_operand:DI 2 "mul8_operand" "I")))]
1960 ""
1961 "insll %1,%s2,%0"
1962 [(set_attr "type" "shift")])
1964 (define_insn "insbl_le"
1965 [(set (match_operand:DI 0 "register_operand" "=r")
1966 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1967 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1968 (const_int 3))))]
1969 "! WORDS_BIG_ENDIAN"
1970 "insbl %1,%2,%0"
1971 [(set_attr "type" "shift")])
1973 (define_insn "insbl_be"
1974 [(set (match_operand:DI 0 "register_operand" "=r")
1975 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1976 (minus:DI (const_int 56)
1977 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1978 (const_int 3)))))]
1979 "WORDS_BIG_ENDIAN"
1980 "insbl %1,%2,%0"
1981 [(set_attr "type" "shift")])
1983 (define_insn "inswl_le"
1984 [(set (match_operand:DI 0 "register_operand" "=r")
1985 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1986 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1987 (const_int 3))))]
1988 "! WORDS_BIG_ENDIAN"
1989 "inswl %1,%2,%0"
1990 [(set_attr "type" "shift")])
1992 (define_insn "inswl_be"
1993 [(set (match_operand:DI 0 "register_operand" "=r")
1994 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1995 (minus:DI (const_int 56)
1996 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1997 (const_int 3)))))]
1998 "WORDS_BIG_ENDIAN"
1999 "inswl %1,%2,%0"
2000 [(set_attr "type" "shift")])
2002 (define_insn "insll_le"
2003 [(set (match_operand:DI 0 "register_operand" "=r")
2004 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2005 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2006 (const_int 3))))]
2007 "! WORDS_BIG_ENDIAN"
2008 "insll %1,%2,%0"
2009 [(set_attr "type" "shift")])
2011 (define_insn "insll_be"
2012 [(set (match_operand:DI 0 "register_operand" "=r")
2013 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2014 (minus:DI (const_int 56)
2015 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2016 (const_int 3)))))]
2017 "WORDS_BIG_ENDIAN"
2018 "insll %1,%2,%0"
2019 [(set_attr "type" "shift")])
2021 (define_insn "insql_le"
2022 [(set (match_operand:DI 0 "register_operand" "=r")
2023 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2024 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2025 (const_int 3))))]
2026 "! WORDS_BIG_ENDIAN"
2027 "insql %1,%2,%0"
2028 [(set_attr "type" "shift")])
2030 (define_insn "insql_be"
2031 [(set (match_operand:DI 0 "register_operand" "=r")
2032 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2033 (minus:DI (const_int 56)
2034 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2035 (const_int 3)))))]
2036 "WORDS_BIG_ENDIAN"
2037 "insql %1,%2,%0"
2038 [(set_attr "type" "shift")])
2040 ;; Combine has this sometimes habit of moving the and outside of the
2041 ;; shift, making life more interesting.
2043 (define_insn "*insxl"
2044 [(set (match_operand:DI 0 "register_operand" "=r")
2045 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2046 (match_operand:DI 2 "mul8_operand" "I"))
2047 (match_operand:DI 3 "immediate_operand" "i")))]
2048 "HOST_BITS_PER_WIDE_INT == 64
2049 && GET_CODE (operands[3]) == CONST_INT
2050 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2051 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2052 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2053 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2054 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2055 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2056 {
2057 #if HOST_BITS_PER_WIDE_INT == 64
2058 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2059 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2060 return "insbl %1,%s2,%0";
2061 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2062 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2063 return "inswl %1,%s2,%0";
2064 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2065 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2066 return "insll %1,%s2,%0";
2067 #endif
2068 abort();
2069 }
2070 [(set_attr "type" "shift")])
2072 ;; We do not include the insXh insns because they are complex to express
2073 ;; and it does not appear that we would ever want to generate them.
2074 ;;
2075 ;; Since we need them for block moves, though, cop out and use unspec.
2077 (define_insn "insxh"
2078 [(set (match_operand:DI 0 "register_operand" "=r")
2079 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2080 (match_operand:DI 2 "mode_width_operand" "n")
2081 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2082 UNSPEC_INSXH))]
2083 ""
2084 "ins%M2h %1,%3,%0"
2085 [(set_attr "type" "shift")])
2087 (define_insn "mskxl_le"
2088 [(set (match_operand:DI 0 "register_operand" "=r")
2089 (and:DI (not:DI (ashift:DI
2090 (match_operand:DI 2 "mode_mask_operand" "n")
2091 (ashift:DI
2092 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2093 (const_int 3))))
2094 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2095 "! WORDS_BIG_ENDIAN"
2096 "msk%U2l %r1,%3,%0"
2097 [(set_attr "type" "shift")])
2099 (define_insn "mskxl_be"
2100 [(set (match_operand:DI 0 "register_operand" "=r")
2101 (and:DI (not:DI (ashift:DI
2102 (match_operand:DI 2 "mode_mask_operand" "n")
2103 (minus:DI (const_int 56)
2104 (ashift:DI
2105 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2106 (const_int 3)))))
2107 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2108 "WORDS_BIG_ENDIAN"
2109 "msk%U2l %r1,%3,%0"
2110 [(set_attr "type" "shift")])
2112 ;; We do not include the mskXh insns because it does not appear we would
2113 ;; ever generate one.
2114 ;;
2115 ;; Again, we do for block moves and we use unspec again.
2117 (define_insn "mskxh"
2118 [(set (match_operand:DI 0 "register_operand" "=r")
2119 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2120 (match_operand:DI 2 "mode_width_operand" "n")
2121 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2122 UNSPEC_MSKXH))]
2123 ""
2124 "msk%M2h %1,%3,%0"
2125 [(set_attr "type" "shift")])
2127 ;; Prefer AND + NE over LSHIFTRT + AND.
2129 (define_insn_and_split "*ze_and_ne"
2130 [(set (match_operand:DI 0 "register_operand" "=r")
2131 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2132 (const_int 1)
2133 (match_operand 2 "const_int_operand" "I")))]
2134 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2135 "#"
2136 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2137 [(set (match_dup 0)
2138 (and:DI (match_dup 1) (match_dup 3)))
2139 (set (match_dup 0)
2140 (ne:DI (match_dup 0) (const_int 0)))]
2141 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2142 \f
2143 ;; Floating-point operations. All the double-precision insns can extend
2144 ;; from single, so indicate that. The exception are the ones that simply
2145 ;; play with the sign bits; it's not clear what to do there.
2147 (define_insn "abssf2"
2148 [(set (match_operand:SF 0 "register_operand" "=f")
2149 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2150 "TARGET_FP"
2151 "cpys $f31,%R1,%0"
2152 [(set_attr "type" "fcpys")])
2154 (define_insn "*nabssf2"
2155 [(set (match_operand:SF 0 "register_operand" "=f")
2156 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2157 "TARGET_FP"
2158 "cpysn $f31,%R1,%0"
2159 [(set_attr "type" "fadd")])
2161 (define_insn "absdf2"
2162 [(set (match_operand:DF 0 "register_operand" "=f")
2163 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2164 "TARGET_FP"
2165 "cpys $f31,%R1,%0"
2166 [(set_attr "type" "fcpys")])
2168 (define_insn "*nabsdf2"
2169 [(set (match_operand:DF 0 "register_operand" "=f")
2170 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2171 "TARGET_FP"
2172 "cpysn $f31,%R1,%0"
2173 [(set_attr "type" "fadd")])
2175 (define_expand "abstf2"
2176 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2177 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2178 (use (match_dup 2))])]
2179 "TARGET_HAS_XFLOATING_LIBS"
2180 {
2181 #if HOST_BITS_PER_WIDE_INT >= 64
2182 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2183 #else
2184 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2185 #endif
2186 })
2188 (define_insn_and_split "*abstf_internal"
2189 [(set (match_operand:TF 0 "register_operand" "=r")
2190 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2191 (use (match_operand:DI 2 "register_operand" "r"))]
2192 "TARGET_HAS_XFLOATING_LIBS"
2193 "#"
2194 "&& reload_completed"
2195 [(const_int 0)]
2196 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2198 (define_insn "negsf2"
2199 [(set (match_operand:SF 0 "register_operand" "=f")
2200 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2201 "TARGET_FP"
2202 "cpysn %R1,%R1,%0"
2203 [(set_attr "type" "fadd")])
2205 (define_insn "negdf2"
2206 [(set (match_operand:DF 0 "register_operand" "=f")
2207 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2208 "TARGET_FP"
2209 "cpysn %R1,%R1,%0"
2210 [(set_attr "type" "fadd")])
2212 (define_expand "negtf2"
2213 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2214 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2215 (use (match_dup 2))])]
2216 "TARGET_HAS_XFLOATING_LIBS"
2217 {
2218 #if HOST_BITS_PER_WIDE_INT >= 64
2219 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2220 #else
2221 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2222 #endif
2223 })
2225 (define_insn_and_split "*negtf_internal"
2226 [(set (match_operand:TF 0 "register_operand" "=r")
2227 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2228 (use (match_operand:DI 2 "register_operand" "r"))]
2229 "TARGET_HAS_XFLOATING_LIBS"
2230 "#"
2231 "&& reload_completed"
2232 [(const_int 0)]
2233 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2235 (define_insn "copysignsf3"
2236 [(set (match_operand:SF 0 "register_operand" "=f")
2237 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2238 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2239 UNSPEC_COPYSIGN))]
2240 "TARGET_FP"
2241 "cpys %R2,%R1,%0"
2242 [(set_attr "type" "fadd")])
2244 (define_insn "*ncopysignsf3"
2245 [(set (match_operand:SF 0 "register_operand" "=f")
2246 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2247 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2248 UNSPEC_COPYSIGN)))]
2249 "TARGET_FP"
2250 "cpysn %R2,%R1,%0"
2251 [(set_attr "type" "fadd")])
2253 (define_insn "copysigndf3"
2254 [(set (match_operand:DF 0 "register_operand" "=f")
2255 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2256 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2257 UNSPEC_COPYSIGN))]
2258 "TARGET_FP"
2259 "cpys %R2,%R1,%0"
2260 [(set_attr "type" "fadd")])
2262 (define_insn "*ncopysigndf3"
2263 [(set (match_operand:DF 0 "register_operand" "=f")
2264 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2265 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2266 UNSPEC_COPYSIGN)))]
2267 "TARGET_FP"
2268 "cpysn %R2,%R1,%0"
2269 [(set_attr "type" "fadd")])
2271 (define_insn "*addsf_ieee"
2272 [(set (match_operand:SF 0 "register_operand" "=&f")
2273 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2274 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2275 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2276 "add%,%/ %R1,%R2,%0"
2277 [(set_attr "type" "fadd")
2278 (set_attr "trap" "yes")
2279 (set_attr "round_suffix" "normal")
2280 (set_attr "trap_suffix" "u_su_sui")])
2282 (define_insn "addsf3"
2283 [(set (match_operand:SF 0 "register_operand" "=f")
2284 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2285 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2286 "TARGET_FP"
2287 "add%,%/ %R1,%R2,%0"
2288 [(set_attr "type" "fadd")
2289 (set_attr "trap" "yes")
2290 (set_attr "round_suffix" "normal")
2291 (set_attr "trap_suffix" "u_su_sui")])
2293 (define_insn "*adddf_ieee"
2294 [(set (match_operand:DF 0 "register_operand" "=&f")
2295 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2296 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2297 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2298 "add%-%/ %R1,%R2,%0"
2299 [(set_attr "type" "fadd")
2300 (set_attr "trap" "yes")
2301 (set_attr "round_suffix" "normal")
2302 (set_attr "trap_suffix" "u_su_sui")])
2304 (define_insn "adddf3"
2305 [(set (match_operand:DF 0 "register_operand" "=f")
2306 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2307 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2308 "TARGET_FP"
2309 "add%-%/ %R1,%R2,%0"
2310 [(set_attr "type" "fadd")
2311 (set_attr "trap" "yes")
2312 (set_attr "round_suffix" "normal")
2313 (set_attr "trap_suffix" "u_su_sui")])
2315 (define_insn "*adddf_ext1"
2316 [(set (match_operand:DF 0 "register_operand" "=f")
2317 (plus:DF (float_extend:DF
2318 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2319 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2320 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2321 "add%-%/ %R1,%R2,%0"
2322 [(set_attr "type" "fadd")
2323 (set_attr "trap" "yes")
2324 (set_attr "round_suffix" "normal")
2325 (set_attr "trap_suffix" "u_su_sui")])
2327 (define_insn "*adddf_ext2"
2328 [(set (match_operand:DF 0 "register_operand" "=f")
2329 (plus:DF (float_extend:DF
2330 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2331 (float_extend:DF
2332 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2333 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2334 "add%-%/ %R1,%R2,%0"
2335 [(set_attr "type" "fadd")
2336 (set_attr "trap" "yes")
2337 (set_attr "round_suffix" "normal")
2338 (set_attr "trap_suffix" "u_su_sui")])
2340 (define_expand "addtf3"
2341 [(use (match_operand 0 "register_operand" ""))
2342 (use (match_operand 1 "general_operand" ""))
2343 (use (match_operand 2 "general_operand" ""))]
2344 "TARGET_HAS_XFLOATING_LIBS"
2345 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2347 ;; Define conversion operators between DFmode and SImode, using the cvtql
2348 ;; instruction. To allow combine et al to do useful things, we keep the
2349 ;; operation as a unit until after reload, at which point we split the
2350 ;; instructions.
2351 ;;
2352 ;; Note that we (attempt to) only consider this optimization when the
2353 ;; ultimate destination is memory. If we will be doing further integer
2354 ;; processing, it is cheaper to do the truncation in the int regs.
2356 (define_insn "*cvtql"
2357 [(set (match_operand:SF 0 "register_operand" "=f")
2358 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2359 UNSPEC_CVTQL))]
2360 "TARGET_FP"
2361 "cvtql%/ %R1,%0"
2362 [(set_attr "type" "fadd")
2363 (set_attr "trap" "yes")
2364 (set_attr "trap_suffix" "v_sv")])
2366 (define_insn_and_split "*fix_truncdfsi_ieee"
2367 [(set (match_operand:SI 0 "memory_operand" "=m")
2368 (subreg:SI
2369 (match_operator:DI 4 "fix_operator"
2370 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2371 (clobber (match_scratch:DI 2 "=&f"))
2372 (clobber (match_scratch:SF 3 "=&f"))]
2373 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2374 "#"
2375 "&& reload_completed"
2376 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2377 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2378 (set (match_dup 5) (match_dup 3))]
2379 {
2380 operands[5] = adjust_address (operands[0], SFmode, 0);
2381 }
2382 [(set_attr "type" "fadd")
2383 (set_attr "trap" "yes")])
2385 (define_insn_and_split "*fix_truncdfsi_internal"
2386 [(set (match_operand:SI 0 "memory_operand" "=m")
2387 (subreg:SI
2388 (match_operator:DI 3 "fix_operator"
2389 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2390 (clobber (match_scratch:DI 2 "=f"))]
2391 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2392 "#"
2393 "&& reload_completed"
2394 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2395 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2396 (set (match_dup 5) (match_dup 4))]
2397 {
2398 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2399 operands[5] = adjust_address (operands[0], SFmode, 0);
2400 }
2401 [(set_attr "type" "fadd")
2402 (set_attr "trap" "yes")])
2404 (define_insn "*fix_truncdfdi_ieee"
2405 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2406 (match_operator:DI 2 "fix_operator"
2407 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2408 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2409 "cvt%-q%/ %R1,%0"
2410 [(set_attr "type" "fadd")
2411 (set_attr "trap" "yes")
2412 (set_attr "round_suffix" "c")
2413 (set_attr "trap_suffix" "v_sv_svi")])
2415 (define_insn "*fix_truncdfdi2"
2416 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2417 (match_operator:DI 2 "fix_operator"
2418 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2419 "TARGET_FP"
2420 "cvt%-q%/ %R1,%0"
2421 [(set_attr "type" "fadd")
2422 (set_attr "trap" "yes")
2423 (set_attr "round_suffix" "c")
2424 (set_attr "trap_suffix" "v_sv_svi")])
2426 (define_expand "fix_truncdfdi2"
2427 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2428 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2429 "TARGET_FP"
2430 "")
2432 (define_expand "fixuns_truncdfdi2"
2433 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2434 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2435 "TARGET_FP"
2436 "")
2438 ;; Likewise between SFmode and SImode.
2440 (define_insn_and_split "*fix_truncsfsi_ieee"
2441 [(set (match_operand:SI 0 "memory_operand" "=m")
2442 (subreg:SI
2443 (match_operator:DI 4 "fix_operator"
2444 [(float_extend:DF
2445 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2446 (clobber (match_scratch:DI 2 "=&f"))
2447 (clobber (match_scratch:SF 3 "=&f"))]
2448 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2449 "#"
2450 "&& reload_completed"
2451 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2452 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2453 (set (match_dup 5) (match_dup 3))]
2454 {
2455 operands[5] = adjust_address (operands[0], SFmode, 0);
2456 }
2457 [(set_attr "type" "fadd")
2458 (set_attr "trap" "yes")])
2460 (define_insn_and_split "*fix_truncsfsi_internal"
2461 [(set (match_operand:SI 0 "memory_operand" "=m")
2462 (subreg:SI
2463 (match_operator:DI 3 "fix_operator"
2464 [(float_extend:DF
2465 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2466 (clobber (match_scratch:DI 2 "=f"))]
2467 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2468 "#"
2469 "&& reload_completed"
2470 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2471 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2472 (set (match_dup 5) (match_dup 4))]
2473 {
2474 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2475 operands[5] = adjust_address (operands[0], SFmode, 0);
2476 }
2477 [(set_attr "type" "fadd")
2478 (set_attr "trap" "yes")])
2480 (define_insn "*fix_truncsfdi_ieee"
2481 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2482 (match_operator:DI 2 "fix_operator"
2483 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2484 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2485 "cvt%-q%/ %R1,%0"
2486 [(set_attr "type" "fadd")
2487 (set_attr "trap" "yes")
2488 (set_attr "round_suffix" "c")
2489 (set_attr "trap_suffix" "v_sv_svi")])
2491 (define_insn "*fix_truncsfdi2"
2492 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2493 (match_operator:DI 2 "fix_operator"
2494 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2495 "TARGET_FP"
2496 "cvt%-q%/ %R1,%0"
2497 [(set_attr "type" "fadd")
2498 (set_attr "trap" "yes")
2499 (set_attr "round_suffix" "c")
2500 (set_attr "trap_suffix" "v_sv_svi")])
2502 (define_expand "fix_truncsfdi2"
2503 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2504 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2505 "TARGET_FP"
2506 "")
2508 (define_expand "fixuns_truncsfdi2"
2509 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2510 (unsigned_fix:DI
2511 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2512 "TARGET_FP"
2513 "")
2515 (define_expand "fix_trunctfdi2"
2516 [(use (match_operand:DI 0 "register_operand" ""))
2517 (use (match_operand:TF 1 "general_operand" ""))]
2518 "TARGET_HAS_XFLOATING_LIBS"
2519 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2521 (define_expand "fixuns_trunctfdi2"
2522 [(use (match_operand:DI 0 "register_operand" ""))
2523 (use (match_operand:TF 1 "general_operand" ""))]
2524 "TARGET_HAS_XFLOATING_LIBS"
2525 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2527 (define_insn "*floatdisf_ieee"
2528 [(set (match_operand:SF 0 "register_operand" "=&f")
2529 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2530 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2531 "cvtq%,%/ %1,%0"
2532 [(set_attr "type" "fadd")
2533 (set_attr "trap" "yes")
2534 (set_attr "round_suffix" "normal")
2535 (set_attr "trap_suffix" "sui")])
2537 (define_insn "floatdisf2"
2538 [(set (match_operand:SF 0 "register_operand" "=f")
2539 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2540 "TARGET_FP"
2541 "cvtq%,%/ %1,%0"
2542 [(set_attr "type" "fadd")
2543 (set_attr "trap" "yes")
2544 (set_attr "round_suffix" "normal")
2545 (set_attr "trap_suffix" "sui")])
2547 (define_insn_and_split "*floatsisf2_ieee"
2548 [(set (match_operand:SF 0 "register_operand" "=&f")
2549 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2550 (clobber (match_scratch:DI 2 "=&f"))
2551 (clobber (match_scratch:SF 3 "=&f"))]
2552 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2553 "#"
2554 "&& reload_completed"
2555 [(set (match_dup 3) (match_dup 1))
2556 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2557 (set (match_dup 0) (float:SF (match_dup 2)))]
2558 {
2559 operands[1] = adjust_address (operands[1], SFmode, 0);
2560 })
2562 (define_insn_and_split "*floatsisf2"
2563 [(set (match_operand:SF 0 "register_operand" "=f")
2564 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2565 "TARGET_FP"
2566 "#"
2567 "&& reload_completed"
2568 [(set (match_dup 0) (match_dup 1))
2569 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2570 (set (match_dup 0) (float:SF (match_dup 2)))]
2571 {
2572 operands[1] = adjust_address (operands[1], SFmode, 0);
2573 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2574 })
2576 (define_insn "*floatdidf_ieee"
2577 [(set (match_operand:DF 0 "register_operand" "=&f")
2578 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2579 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2580 "cvtq%-%/ %1,%0"
2581 [(set_attr "type" "fadd")
2582 (set_attr "trap" "yes")
2583 (set_attr "round_suffix" "normal")
2584 (set_attr "trap_suffix" "sui")])
2586 (define_insn "floatdidf2"
2587 [(set (match_operand:DF 0 "register_operand" "=f")
2588 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2589 "TARGET_FP"
2590 "cvtq%-%/ %1,%0"
2591 [(set_attr "type" "fadd")
2592 (set_attr "trap" "yes")
2593 (set_attr "round_suffix" "normal")
2594 (set_attr "trap_suffix" "sui")])
2596 (define_insn_and_split "*floatsidf2_ieee"
2597 [(set (match_operand:DF 0 "register_operand" "=&f")
2598 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2599 (clobber (match_scratch:DI 2 "=&f"))
2600 (clobber (match_scratch:SF 3 "=&f"))]
2601 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2602 "#"
2603 "&& reload_completed"
2604 [(set (match_dup 3) (match_dup 1))
2605 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2606 (set (match_dup 0) (float:DF (match_dup 2)))]
2607 {
2608 operands[1] = adjust_address (operands[1], SFmode, 0);
2609 })
2611 (define_insn_and_split "*floatsidf2"
2612 [(set (match_operand:DF 0 "register_operand" "=f")
2613 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2614 "TARGET_FP"
2615 "#"
2616 "&& reload_completed"
2617 [(set (match_dup 3) (match_dup 1))
2618 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2619 (set (match_dup 0) (float:DF (match_dup 2)))]
2620 {
2621 operands[1] = adjust_address (operands[1], SFmode, 0);
2622 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2623 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2624 })
2626 (define_expand "floatditf2"
2627 [(use (match_operand:TF 0 "register_operand" ""))
2628 (use (match_operand:DI 1 "general_operand" ""))]
2629 "TARGET_HAS_XFLOATING_LIBS"
2630 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2632 (define_expand "floatunsdisf2"
2633 [(use (match_operand:SF 0 "register_operand" ""))
2634 (use (match_operand:DI 1 "register_operand" ""))]
2635 "TARGET_FP"
2636 "alpha_emit_floatuns (operands); DONE;")
2638 (define_expand "floatunsdidf2"
2639 [(use (match_operand:DF 0 "register_operand" ""))
2640 (use (match_operand:DI 1 "register_operand" ""))]
2641 "TARGET_FP"
2642 "alpha_emit_floatuns (operands); DONE;")
2644 (define_expand "floatunsditf2"
2645 [(use (match_operand:TF 0 "register_operand" ""))
2646 (use (match_operand:DI 1 "general_operand" ""))]
2647 "TARGET_HAS_XFLOATING_LIBS"
2648 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2650 (define_expand "extendsfdf2"
2651 [(set (match_operand:DF 0 "register_operand" "")
2652 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2653 "TARGET_FP"
2654 {
2655 if (alpha_fptm >= ALPHA_FPTM_SU)
2656 operands[1] = force_reg (SFmode, operands[1]);
2657 })
2659 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2660 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2662 (define_insn "*extendsfdf2_ieee"
2663 [(set (match_operand:DF 0 "register_operand" "=&f")
2664 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2665 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2666 "cvtsts %1,%0"
2667 [(set_attr "type" "fadd")
2668 (set_attr "trap" "yes")])
2670 (define_insn "*extendsfdf2_internal"
2671 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2672 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2673 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2674 "@
2675 cpys %1,%1,%0
2676 ld%, %0,%1
2677 st%- %1,%0"
2678 [(set_attr "type" "fcpys,fld,fst")])
2680 ;; Use register_operand for operand 1 to prevent compress_float_constant
2681 ;; from doing something silly. When optimizing we'll put things back
2682 ;; together anyway.
2683 (define_expand "extendsftf2"
2684 [(use (match_operand:TF 0 "register_operand" ""))
2685 (use (match_operand:SF 1 "register_operand" ""))]
2686 "TARGET_HAS_XFLOATING_LIBS"
2687 {
2688 rtx tmp = gen_reg_rtx (DFmode);
2689 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2690 emit_insn (gen_extenddftf2 (operands[0], tmp));
2691 DONE;
2692 })
2694 (define_expand "extenddftf2"
2695 [(use (match_operand:TF 0 "register_operand" ""))
2696 (use (match_operand:DF 1 "register_operand" ""))]
2697 "TARGET_HAS_XFLOATING_LIBS"
2698 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2700 (define_insn "*truncdfsf2_ieee"
2701 [(set (match_operand:SF 0 "register_operand" "=&f")
2702 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2703 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2704 "cvt%-%,%/ %R1,%0"
2705 [(set_attr "type" "fadd")
2706 (set_attr "trap" "yes")
2707 (set_attr "round_suffix" "normal")
2708 (set_attr "trap_suffix" "u_su_sui")])
2710 (define_insn "truncdfsf2"
2711 [(set (match_operand:SF 0 "register_operand" "=f")
2712 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2713 "TARGET_FP"
2714 "cvt%-%,%/ %R1,%0"
2715 [(set_attr "type" "fadd")
2716 (set_attr "trap" "yes")
2717 (set_attr "round_suffix" "normal")
2718 (set_attr "trap_suffix" "u_su_sui")])
2720 (define_expand "trunctfdf2"
2721 [(use (match_operand:DF 0 "register_operand" ""))
2722 (use (match_operand:TF 1 "general_operand" ""))]
2723 "TARGET_HAS_XFLOATING_LIBS"
2724 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2726 (define_expand "trunctfsf2"
2727 [(use (match_operand:SF 0 "register_operand" ""))
2728 (use (match_operand:TF 1 "general_operand" ""))]
2729 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2730 {
2731 rtx tmpf, sticky, arg, lo, hi;
2733 tmpf = gen_reg_rtx (DFmode);
2734 sticky = gen_reg_rtx (DImode);
2735 arg = copy_to_mode_reg (TFmode, operands[1]);
2736 lo = gen_lowpart (DImode, arg);
2737 hi = gen_highpart (DImode, arg);
2739 /* Convert the low word of the TFmode value into a sticky rounding bit,
2740 then or it into the low bit of the high word. This leaves the sticky
2741 bit at bit 48 of the fraction, which is representable in DFmode,
2742 which prevents rounding error in the final conversion to SFmode. */
2744 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2745 gen_rtx_NE (DImode, lo, const0_rtx)));
2746 emit_insn (gen_iordi3 (hi, hi, sticky));
2747 emit_insn (gen_trunctfdf2 (tmpf, arg));
2748 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2749 DONE;
2750 })
2752 (define_insn "*divsf3_ieee"
2753 [(set (match_operand:SF 0 "register_operand" "=&f")
2754 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2755 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2756 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2757 "div%,%/ %R1,%R2,%0"
2758 [(set_attr "type" "fdiv")
2759 (set_attr "opsize" "si")
2760 (set_attr "trap" "yes")
2761 (set_attr "round_suffix" "normal")
2762 (set_attr "trap_suffix" "u_su_sui")])
2764 (define_insn "divsf3"
2765 [(set (match_operand:SF 0 "register_operand" "=f")
2766 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2767 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2768 "TARGET_FP"
2769 "div%,%/ %R1,%R2,%0"
2770 [(set_attr "type" "fdiv")
2771 (set_attr "opsize" "si")
2772 (set_attr "trap" "yes")
2773 (set_attr "round_suffix" "normal")
2774 (set_attr "trap_suffix" "u_su_sui")])
2776 (define_insn "*divdf3_ieee"
2777 [(set (match_operand:DF 0 "register_operand" "=&f")
2778 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2779 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2780 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2781 "div%-%/ %R1,%R2,%0"
2782 [(set_attr "type" "fdiv")
2783 (set_attr "trap" "yes")
2784 (set_attr "round_suffix" "normal")
2785 (set_attr "trap_suffix" "u_su_sui")])
2787 (define_insn "divdf3"
2788 [(set (match_operand:DF 0 "register_operand" "=f")
2789 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2790 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2791 "TARGET_FP"
2792 "div%-%/ %R1,%R2,%0"
2793 [(set_attr "type" "fdiv")
2794 (set_attr "trap" "yes")
2795 (set_attr "round_suffix" "normal")
2796 (set_attr "trap_suffix" "u_su_sui")])
2798 (define_insn "*divdf_ext1"
2799 [(set (match_operand:DF 0 "register_operand" "=f")
2800 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2801 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2802 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2803 "div%-%/ %R1,%R2,%0"
2804 [(set_attr "type" "fdiv")
2805 (set_attr "trap" "yes")
2806 (set_attr "round_suffix" "normal")
2807 (set_attr "trap_suffix" "u_su_sui")])
2809 (define_insn "*divdf_ext2"
2810 [(set (match_operand:DF 0 "register_operand" "=f")
2811 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2812 (float_extend:DF
2813 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2814 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2815 "div%-%/ %R1,%R2,%0"
2816 [(set_attr "type" "fdiv")
2817 (set_attr "trap" "yes")
2818 (set_attr "round_suffix" "normal")
2819 (set_attr "trap_suffix" "u_su_sui")])
2821 (define_insn "*divdf_ext3"
2822 [(set (match_operand:DF 0 "register_operand" "=f")
2823 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2824 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2825 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2826 "div%-%/ %R1,%R2,%0"
2827 [(set_attr "type" "fdiv")
2828 (set_attr "trap" "yes")
2829 (set_attr "round_suffix" "normal")
2830 (set_attr "trap_suffix" "u_su_sui")])
2832 (define_expand "divtf3"
2833 [(use (match_operand 0 "register_operand" ""))
2834 (use (match_operand 1 "general_operand" ""))
2835 (use (match_operand 2 "general_operand" ""))]
2836 "TARGET_HAS_XFLOATING_LIBS"
2837 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2839 (define_insn "*mulsf3_ieee"
2840 [(set (match_operand:SF 0 "register_operand" "=&f")
2841 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2842 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2843 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2844 "mul%,%/ %R1,%R2,%0"
2845 [(set_attr "type" "fmul")
2846 (set_attr "trap" "yes")
2847 (set_attr "round_suffix" "normal")
2848 (set_attr "trap_suffix" "u_su_sui")])
2850 (define_insn "mulsf3"
2851 [(set (match_operand:SF 0 "register_operand" "=f")
2852 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2853 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2854 "TARGET_FP"
2855 "mul%,%/ %R1,%R2,%0"
2856 [(set_attr "type" "fmul")
2857 (set_attr "trap" "yes")
2858 (set_attr "round_suffix" "normal")
2859 (set_attr "trap_suffix" "u_su_sui")])
2861 (define_insn "*muldf3_ieee"
2862 [(set (match_operand:DF 0 "register_operand" "=&f")
2863 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2864 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2865 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2866 "mul%-%/ %R1,%R2,%0"
2867 [(set_attr "type" "fmul")
2868 (set_attr "trap" "yes")
2869 (set_attr "round_suffix" "normal")
2870 (set_attr "trap_suffix" "u_su_sui")])
2872 (define_insn "muldf3"
2873 [(set (match_operand:DF 0 "register_operand" "=f")
2874 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2875 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2876 "TARGET_FP"
2877 "mul%-%/ %R1,%R2,%0"
2878 [(set_attr "type" "fmul")
2879 (set_attr "trap" "yes")
2880 (set_attr "round_suffix" "normal")
2881 (set_attr "trap_suffix" "u_su_sui")])
2883 (define_insn "*muldf_ext1"
2884 [(set (match_operand:DF 0 "register_operand" "=f")
2885 (mult:DF (float_extend:DF
2886 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2887 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2888 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2889 "mul%-%/ %R1,%R2,%0"
2890 [(set_attr "type" "fmul")
2891 (set_attr "trap" "yes")
2892 (set_attr "round_suffix" "normal")
2893 (set_attr "trap_suffix" "u_su_sui")])
2895 (define_insn "*muldf_ext2"
2896 [(set (match_operand:DF 0 "register_operand" "=f")
2897 (mult:DF (float_extend:DF
2898 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2899 (float_extend:DF
2900 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2901 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2902 "mul%-%/ %R1,%R2,%0"
2903 [(set_attr "type" "fmul")
2904 (set_attr "trap" "yes")
2905 (set_attr "round_suffix" "normal")
2906 (set_attr "trap_suffix" "u_su_sui")])
2908 (define_expand "multf3"
2909 [(use (match_operand 0 "register_operand" ""))
2910 (use (match_operand 1 "general_operand" ""))
2911 (use (match_operand 2 "general_operand" ""))]
2912 "TARGET_HAS_XFLOATING_LIBS"
2913 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2915 (define_insn "*subsf3_ieee"
2916 [(set (match_operand:SF 0 "register_operand" "=&f")
2917 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2918 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2919 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2920 "sub%,%/ %R1,%R2,%0"
2921 [(set_attr "type" "fadd")
2922 (set_attr "trap" "yes")
2923 (set_attr "round_suffix" "normal")
2924 (set_attr "trap_suffix" "u_su_sui")])
2926 (define_insn "subsf3"
2927 [(set (match_operand:SF 0 "register_operand" "=f")
2928 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2929 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2930 "TARGET_FP"
2931 "sub%,%/ %R1,%R2,%0"
2932 [(set_attr "type" "fadd")
2933 (set_attr "trap" "yes")
2934 (set_attr "round_suffix" "normal")
2935 (set_attr "trap_suffix" "u_su_sui")])
2937 (define_insn "*subdf3_ieee"
2938 [(set (match_operand:DF 0 "register_operand" "=&f")
2939 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2940 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2941 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2942 "sub%-%/ %R1,%R2,%0"
2943 [(set_attr "type" "fadd")
2944 (set_attr "trap" "yes")
2945 (set_attr "round_suffix" "normal")
2946 (set_attr "trap_suffix" "u_su_sui")])
2948 (define_insn "subdf3"
2949 [(set (match_operand:DF 0 "register_operand" "=f")
2950 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2951 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2952 "TARGET_FP"
2953 "sub%-%/ %R1,%R2,%0"
2954 [(set_attr "type" "fadd")
2955 (set_attr "trap" "yes")
2956 (set_attr "round_suffix" "normal")
2957 (set_attr "trap_suffix" "u_su_sui")])
2959 (define_insn "*subdf_ext1"
2960 [(set (match_operand:DF 0 "register_operand" "=f")
2961 (minus:DF (float_extend:DF
2962 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2963 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2964 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2965 "sub%-%/ %R1,%R2,%0"
2966 [(set_attr "type" "fadd")
2967 (set_attr "trap" "yes")
2968 (set_attr "round_suffix" "normal")
2969 (set_attr "trap_suffix" "u_su_sui")])
2971 (define_insn "*subdf_ext2"
2972 [(set (match_operand:DF 0 "register_operand" "=f")
2973 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2974 (float_extend:DF
2975 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2976 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2977 "sub%-%/ %R1,%R2,%0"
2978 [(set_attr "type" "fadd")
2979 (set_attr "trap" "yes")
2980 (set_attr "round_suffix" "normal")
2981 (set_attr "trap_suffix" "u_su_sui")])
2983 (define_insn "*subdf_ext3"
2984 [(set (match_operand:DF 0 "register_operand" "=f")
2985 (minus:DF (float_extend:DF
2986 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2987 (float_extend:DF
2988 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2989 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2990 "sub%-%/ %R1,%R2,%0"
2991 [(set_attr "type" "fadd")
2992 (set_attr "trap" "yes")
2993 (set_attr "round_suffix" "normal")
2994 (set_attr "trap_suffix" "u_su_sui")])
2996 (define_expand "subtf3"
2997 [(use (match_operand 0 "register_operand" ""))
2998 (use (match_operand 1 "general_operand" ""))
2999 (use (match_operand 2 "general_operand" ""))]
3000 "TARGET_HAS_XFLOATING_LIBS"
3001 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3003 (define_insn "*sqrtsf2_ieee"
3004 [(set (match_operand:SF 0 "register_operand" "=&f")
3005 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3006 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3007 "sqrt%,%/ %R1,%0"
3008 [(set_attr "type" "fsqrt")
3009 (set_attr "opsize" "si")
3010 (set_attr "trap" "yes")
3011 (set_attr "round_suffix" "normal")
3012 (set_attr "trap_suffix" "u_su_sui")])
3014 (define_insn "sqrtsf2"
3015 [(set (match_operand:SF 0 "register_operand" "=f")
3016 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3017 "TARGET_FP && TARGET_FIX"
3018 "sqrt%,%/ %R1,%0"
3019 [(set_attr "type" "fsqrt")
3020 (set_attr "opsize" "si")
3021 (set_attr "trap" "yes")
3022 (set_attr "round_suffix" "normal")
3023 (set_attr "trap_suffix" "u_su_sui")])
3025 (define_insn "*sqrtdf2_ieee"
3026 [(set (match_operand:DF 0 "register_operand" "=&f")
3027 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3028 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3029 "sqrt%-%/ %R1,%0"
3030 [(set_attr "type" "fsqrt")
3031 (set_attr "trap" "yes")
3032 (set_attr "round_suffix" "normal")
3033 (set_attr "trap_suffix" "u_su_sui")])
3035 (define_insn "sqrtdf2"
3036 [(set (match_operand:DF 0 "register_operand" "=f")
3037 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3038 "TARGET_FP && TARGET_FIX"
3039 "sqrt%-%/ %R1,%0"
3040 [(set_attr "type" "fsqrt")
3041 (set_attr "trap" "yes")
3042 (set_attr "round_suffix" "normal")
3043 (set_attr "trap_suffix" "u_su_sui")])
3044 \f
3045 ;; Next are all the integer comparisons, and conditional moves and branches
3046 ;; and some of the related define_expand's and define_split's.
3048 (define_insn "*setcc_internal"
3049 [(set (match_operand 0 "register_operand" "=r")
3050 (match_operator 1 "alpha_comparison_operator"
3051 [(match_operand:DI 2 "register_operand" "r")
3052 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3053 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3054 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3055 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3056 "cmp%C1 %2,%3,%0"
3057 [(set_attr "type" "icmp")])
3059 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3060 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3061 ;; from cse on.
3062 (define_insn "*setcc_swapped_internal"
3063 [(set (match_operand 0 "register_operand" "=r")
3064 (match_operator 1 "alpha_swapped_comparison_operator"
3065 [(match_operand:DI 2 "register_operand" "r")
3066 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3067 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3068 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3069 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3070 "cmp%c1 %r3,%2,%0"
3071 [(set_attr "type" "icmp")])
3073 ;; Use match_operator rather than ne directly so that we can match
3074 ;; multiple integer modes.
3075 (define_insn "*setne_internal"
3076 [(set (match_operand 0 "register_operand" "=r")
3077 (match_operator 1 "signed_comparison_operator"
3078 [(match_operand:DI 2 "register_operand" "r")
3079 (const_int 0)]))]
3080 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3081 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3082 && GET_CODE (operands[1]) == NE
3083 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3084 "cmpult $31,%2,%0"
3085 [(set_attr "type" "icmp")])
3087 ;; The mode folding trick can't be used with const_int operands, since
3088 ;; reload needs to know the proper mode.
3089 ;;
3090 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3091 ;; in order to create more pairs of constants. As long as we're allowing
3092 ;; two constants at the same time, and will have to reload one of them...
3094 (define_insn "*movqicc_internal"
3095 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3096 (if_then_else:QI
3097 (match_operator 2 "signed_comparison_operator"
3098 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3099 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3100 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3101 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3102 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3103 "@
3104 cmov%C2 %r3,%1,%0
3105 cmov%D2 %r3,%5,%0
3106 cmov%c2 %r4,%1,%0
3107 cmov%d2 %r4,%5,%0"
3108 [(set_attr "type" "icmov")])
3110 (define_insn "*movhicc_internal"
3111 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3112 (if_then_else:HI
3113 (match_operator 2 "signed_comparison_operator"
3114 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3115 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3116 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3117 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3118 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3119 "@
3120 cmov%C2 %r3,%1,%0
3121 cmov%D2 %r3,%5,%0
3122 cmov%c2 %r4,%1,%0
3123 cmov%d2 %r4,%5,%0"
3124 [(set_attr "type" "icmov")])
3126 (define_insn "*movsicc_internal"
3127 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3128 (if_then_else:SI
3129 (match_operator 2 "signed_comparison_operator"
3130 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3131 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3132 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3133 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3134 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3135 "@
3136 cmov%C2 %r3,%1,%0
3137 cmov%D2 %r3,%5,%0
3138 cmov%c2 %r4,%1,%0
3139 cmov%d2 %r4,%5,%0"
3140 [(set_attr "type" "icmov")])
3142 (define_insn "*movdicc_internal"
3143 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3144 (if_then_else:DI
3145 (match_operator 2 "signed_comparison_operator"
3146 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3147 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3148 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3149 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3150 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3151 "@
3152 cmov%C2 %r3,%1,%0
3153 cmov%D2 %r3,%5,%0
3154 cmov%c2 %r4,%1,%0
3155 cmov%d2 %r4,%5,%0"
3156 [(set_attr "type" "icmov")])
3158 (define_insn "*movqicc_lbc"
3159 [(set (match_operand:QI 0 "register_operand" "=r,r")
3160 (if_then_else:QI
3161 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3162 (const_int 1)
3163 (const_int 0))
3164 (const_int 0))
3165 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3166 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3167 ""
3168 "@
3169 cmovlbc %r2,%1,%0
3170 cmovlbs %r2,%3,%0"
3171 [(set_attr "type" "icmov")])
3173 (define_insn "*movhicc_lbc"
3174 [(set (match_operand:HI 0 "register_operand" "=r,r")
3175 (if_then_else:HI
3176 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3177 (const_int 1)
3178 (const_int 0))
3179 (const_int 0))
3180 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3181 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3182 ""
3183 "@
3184 cmovlbc %r2,%1,%0
3185 cmovlbs %r2,%3,%0"
3186 [(set_attr "type" "icmov")])
3188 (define_insn "*movsicc_lbc"
3189 [(set (match_operand:SI 0 "register_operand" "=r,r")
3190 (if_then_else:SI
3191 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3192 (const_int 1)
3193 (const_int 0))
3194 (const_int 0))
3195 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3196 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3197 ""
3198 "@
3199 cmovlbc %r2,%1,%0
3200 cmovlbs %r2,%3,%0"
3201 [(set_attr "type" "icmov")])
3203 (define_insn "*movdicc_lbc"
3204 [(set (match_operand:DI 0 "register_operand" "=r,r")
3205 (if_then_else:DI
3206 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3207 (const_int 1)
3208 (const_int 0))
3209 (const_int 0))
3210 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3211 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3212 ""
3213 "@
3214 cmovlbc %r2,%1,%0
3215 cmovlbs %r2,%3,%0"
3216 [(set_attr "type" "icmov")])
3218 (define_insn "*movqicc_lbs"
3219 [(set (match_operand:QI 0 "register_operand" "=r,r")
3220 (if_then_else:QI
3221 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3222 (const_int 1)
3223 (const_int 0))
3224 (const_int 0))
3225 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3226 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3227 ""
3228 "@
3229 cmovlbs %r2,%1,%0
3230 cmovlbc %r2,%3,%0"
3231 [(set_attr "type" "icmov")])
3233 (define_insn "*movhicc_lbs"
3234 [(set (match_operand:HI 0 "register_operand" "=r,r")
3235 (if_then_else:HI
3236 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3237 (const_int 1)
3238 (const_int 0))
3239 (const_int 0))
3240 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3241 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3242 ""
3243 "@
3244 cmovlbs %r2,%1,%0
3245 cmovlbc %r2,%3,%0"
3246 [(set_attr "type" "icmov")])
3248 (define_insn "*movsicc_lbs"
3249 [(set (match_operand:SI 0 "register_operand" "=r,r")
3250 (if_then_else:SI
3251 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3252 (const_int 1)
3253 (const_int 0))
3254 (const_int 0))
3255 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3256 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3257 ""
3258 "@
3259 cmovlbs %r2,%1,%0
3260 cmovlbc %r2,%3,%0"
3261 [(set_attr "type" "icmov")])
3263 (define_insn "*movdicc_lbs"
3264 [(set (match_operand:DI 0 "register_operand" "=r,r")
3265 (if_then_else:DI
3266 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3267 (const_int 1)
3268 (const_int 0))
3269 (const_int 0))
3270 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3271 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3272 ""
3273 "@
3274 cmovlbs %r2,%1,%0
3275 cmovlbc %r2,%3,%0"
3276 [(set_attr "type" "icmov")])
3278 ;; For ABS, we have two choices, depending on whether the input and output
3279 ;; registers are the same or not.
3280 (define_expand "absdi2"
3281 [(set (match_operand:DI 0 "register_operand" "")
3282 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3283 ""
3284 {
3285 if (rtx_equal_p (operands[0], operands[1]))
3286 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3287 else
3288 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3289 DONE;
3290 })
3292 (define_expand "absdi2_same"
3293 [(set (match_operand:DI 1 "register_operand" "")
3294 (neg:DI (match_operand:DI 0 "register_operand" "")))
3295 (set (match_dup 0)
3296 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3297 (match_dup 0)
3298 (match_dup 1)))]
3299 ""
3300 "")
3302 (define_expand "absdi2_diff"
3303 [(set (match_operand:DI 0 "register_operand" "")
3304 (neg:DI (match_operand:DI 1 "register_operand" "")))
3305 (set (match_dup 0)
3306 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3307 (match_dup 0)
3308 (match_dup 1)))]
3309 ""
3310 "")
3312 (define_split
3313 [(set (match_operand:DI 0 "register_operand" "")
3314 (abs:DI (match_dup 0)))
3315 (clobber (match_operand:DI 1 "register_operand" ""))]
3316 ""
3317 [(set (match_dup 1) (neg:DI (match_dup 0)))
3318 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3319 (match_dup 0) (match_dup 1)))]
3320 "")
3322 (define_split
3323 [(set (match_operand:DI 0 "register_operand" "")
3324 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3325 "! rtx_equal_p (operands[0], operands[1])"
3326 [(set (match_dup 0) (neg:DI (match_dup 1)))
3327 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3328 (match_dup 0) (match_dup 1)))]
3329 "")
3331 (define_split
3332 [(set (match_operand:DI 0 "register_operand" "")
3333 (neg:DI (abs:DI (match_dup 0))))
3334 (clobber (match_operand:DI 1 "register_operand" ""))]
3335 ""
3336 [(set (match_dup 1) (neg:DI (match_dup 0)))
3337 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3338 (match_dup 0) (match_dup 1)))]
3339 "")
3341 (define_split
3342 [(set (match_operand:DI 0 "register_operand" "")
3343 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3344 "! rtx_equal_p (operands[0], operands[1])"
3345 [(set (match_dup 0) (neg:DI (match_dup 1)))
3346 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3347 (match_dup 0) (match_dup 1)))]
3348 "")
3350 (define_insn "sminqi3"
3351 [(set (match_operand:QI 0 "register_operand" "=r")
3352 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3353 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3354 "TARGET_MAX"
3355 "minsb8 %r1,%2,%0"
3356 [(set_attr "type" "mvi")])
3358 (define_insn "uminqi3"
3359 [(set (match_operand:QI 0 "register_operand" "=r")
3360 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3361 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3362 "TARGET_MAX"
3363 "minub8 %r1,%2,%0"
3364 [(set_attr "type" "mvi")])
3366 (define_insn "smaxqi3"
3367 [(set (match_operand:QI 0 "register_operand" "=r")
3368 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3369 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3370 "TARGET_MAX"
3371 "maxsb8 %r1,%2,%0"
3372 [(set_attr "type" "mvi")])
3374 (define_insn "umaxqi3"
3375 [(set (match_operand:QI 0 "register_operand" "=r")
3376 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3377 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3378 "TARGET_MAX"
3379 "maxub8 %r1,%2,%0"
3380 [(set_attr "type" "mvi")])
3382 (define_insn "sminhi3"
3383 [(set (match_operand:HI 0 "register_operand" "=r")
3384 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3385 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3386 "TARGET_MAX"
3387 "minsw4 %r1,%2,%0"
3388 [(set_attr "type" "mvi")])
3390 (define_insn "uminhi3"
3391 [(set (match_operand:HI 0 "register_operand" "=r")
3392 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3393 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3394 "TARGET_MAX"
3395 "minuw4 %r1,%2,%0"
3396 [(set_attr "type" "mvi")])
3398 (define_insn "smaxhi3"
3399 [(set (match_operand:HI 0 "register_operand" "=r")
3400 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3401 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3402 "TARGET_MAX"
3403 "maxsw4 %r1,%2,%0"
3404 [(set_attr "type" "mvi")])
3406 (define_insn "umaxhi3"
3407 [(set (match_operand:HI 0 "register_operand" "=r")
3408 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3409 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3410 "TARGET_MAX"
3411 "maxuw4 %r1,%2,%0"
3412 [(set_attr "type" "mvi")])
3414 (define_expand "smaxdi3"
3415 [(set (match_dup 3)
3416 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3417 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3418 (set (match_operand:DI 0 "register_operand" "")
3419 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3420 (match_dup 1) (match_dup 2)))]
3421 ""
3422 { operands[3] = gen_reg_rtx (DImode); })
3424 (define_split
3425 [(set (match_operand:DI 0 "register_operand" "")
3426 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3427 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3428 (clobber (match_operand:DI 3 "register_operand" ""))]
3429 "operands[2] != const0_rtx"
3430 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3431 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3432 (match_dup 1) (match_dup 2)))]
3433 "")
3435 (define_insn "*smax_const0"
3436 [(set (match_operand:DI 0 "register_operand" "=r")
3437 (smax:DI (match_operand:DI 1 "register_operand" "0")
3438 (const_int 0)))]
3439 ""
3440 "cmovlt %0,0,%0"
3441 [(set_attr "type" "icmov")])
3443 (define_expand "smindi3"
3444 [(set (match_dup 3)
3445 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3446 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3447 (set (match_operand:DI 0 "register_operand" "")
3448 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3449 (match_dup 1) (match_dup 2)))]
3450 ""
3451 { operands[3] = gen_reg_rtx (DImode); })
3453 (define_split
3454 [(set (match_operand:DI 0 "register_operand" "")
3455 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3456 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3457 (clobber (match_operand:DI 3 "register_operand" ""))]
3458 "operands[2] != const0_rtx"
3459 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3460 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3461 (match_dup 1) (match_dup 2)))]
3462 "")
3464 (define_insn "*smin_const0"
3465 [(set (match_operand:DI 0 "register_operand" "=r")
3466 (smin:DI (match_operand:DI 1 "register_operand" "0")
3467 (const_int 0)))]
3468 ""
3469 "cmovgt %0,0,%0"
3470 [(set_attr "type" "icmov")])
3472 (define_expand "umaxdi3"
3473 [(set (match_dup 3)
3474 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3475 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3476 (set (match_operand:DI 0 "register_operand" "")
3477 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3478 (match_dup 1) (match_dup 2)))]
3479 ""
3480 "operands[3] = gen_reg_rtx (DImode);")
3482 (define_split
3483 [(set (match_operand:DI 0 "register_operand" "")
3484 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3485 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3486 (clobber (match_operand:DI 3 "register_operand" ""))]
3487 "operands[2] != const0_rtx"
3488 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3489 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3490 (match_dup 1) (match_dup 2)))]
3491 "")
3493 (define_expand "umindi3"
3494 [(set (match_dup 3)
3495 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3496 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3497 (set (match_operand:DI 0 "register_operand" "")
3498 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3499 (match_dup 1) (match_dup 2)))]
3500 ""
3501 "operands[3] = gen_reg_rtx (DImode);")
3503 (define_split
3504 [(set (match_operand:DI 0 "register_operand" "")
3505 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3506 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3507 (clobber (match_operand:DI 3 "register_operand" ""))]
3508 "operands[2] != const0_rtx"
3509 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3510 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3511 (match_dup 1) (match_dup 2)))]
3512 "")
3514 (define_insn "*bcc_normal"
3515 [(set (pc)
3516 (if_then_else
3517 (match_operator 1 "signed_comparison_operator"
3518 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3519 (const_int 0)])
3520 (label_ref (match_operand 0 "" ""))
3521 (pc)))]
3522 ""
3523 "b%C1 %r2,%0"
3524 [(set_attr "type" "ibr")])
3526 (define_insn "*bcc_reverse"
3527 [(set (pc)
3528 (if_then_else
3529 (match_operator 1 "signed_comparison_operator"
3530 [(match_operand:DI 2 "register_operand" "r")
3531 (const_int 0)])
3533 (pc)
3534 (label_ref (match_operand 0 "" ""))))]
3535 ""
3536 "b%c1 %2,%0"
3537 [(set_attr "type" "ibr")])
3539 (define_insn "*blbs_normal"
3540 [(set (pc)
3541 (if_then_else
3542 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3543 (const_int 1)
3544 (const_int 0))
3545 (const_int 0))
3546 (label_ref (match_operand 0 "" ""))
3547 (pc)))]
3548 ""
3549 "blbs %r1,%0"
3550 [(set_attr "type" "ibr")])
3552 (define_insn "*blbc_normal"
3553 [(set (pc)
3554 (if_then_else
3555 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3556 (const_int 1)
3557 (const_int 0))
3558 (const_int 0))
3559 (label_ref (match_operand 0 "" ""))
3560 (pc)))]
3561 ""
3562 "blbc %r1,%0"
3563 [(set_attr "type" "ibr")])
3565 (define_split
3566 [(parallel
3567 [(set (pc)
3568 (if_then_else
3569 (match_operator 1 "comparison_operator"
3570 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3571 (const_int 1)
3572 (match_operand:DI 3 "const_int_operand" ""))
3573 (const_int 0)])
3574 (label_ref (match_operand 0 "" ""))
3575 (pc)))
3576 (clobber (match_operand:DI 4 "register_operand" ""))])]
3577 "INTVAL (operands[3]) != 0"
3578 [(set (match_dup 4)
3579 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3580 (set (pc)
3581 (if_then_else (match_op_dup 1
3582 [(zero_extract:DI (match_dup 4)
3583 (const_int 1)
3584 (const_int 0))
3585 (const_int 0)])
3586 (label_ref (match_dup 0))
3587 (pc)))]
3588 "")
3589 \f
3590 ;; The following are the corresponding floating-point insns. Recall
3591 ;; we need to have variants that expand the arguments from SFmode
3592 ;; to DFmode.
3594 (define_insn "*cmpdf_ieee"
3595 [(set (match_operand:DF 0 "register_operand" "=&f")
3596 (match_operator:DF 1 "alpha_fp_comparison_operator"
3597 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3598 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3599 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3600 "cmp%-%C1%/ %R2,%R3,%0"
3601 [(set_attr "type" "fadd")
3602 (set_attr "trap" "yes")
3603 (set_attr "trap_suffix" "su")])
3605 (define_insn "*cmpdf_internal"
3606 [(set (match_operand:DF 0 "register_operand" "=f")
3607 (match_operator:DF 1 "alpha_fp_comparison_operator"
3608 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3609 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3610 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3611 "cmp%-%C1%/ %R2,%R3,%0"
3612 [(set_attr "type" "fadd")
3613 (set_attr "trap" "yes")
3614 (set_attr "trap_suffix" "su")])
3616 (define_insn "*cmpdf_ieee_ext1"
3617 [(set (match_operand:DF 0 "register_operand" "=&f")
3618 (match_operator:DF 1 "alpha_fp_comparison_operator"
3619 [(float_extend:DF
3620 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3621 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3622 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3623 "cmp%-%C1%/ %R2,%R3,%0"
3624 [(set_attr "type" "fadd")
3625 (set_attr "trap" "yes")
3626 (set_attr "trap_suffix" "su")])
3628 (define_insn "*cmpdf_ext1"
3629 [(set (match_operand:DF 0 "register_operand" "=f")
3630 (match_operator:DF 1 "alpha_fp_comparison_operator"
3631 [(float_extend:DF
3632 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3633 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3634 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3635 "cmp%-%C1%/ %R2,%R3,%0"
3636 [(set_attr "type" "fadd")
3637 (set_attr "trap" "yes")
3638 (set_attr "trap_suffix" "su")])
3640 (define_insn "*cmpdf_ieee_ext2"
3641 [(set (match_operand:DF 0 "register_operand" "=&f")
3642 (match_operator:DF 1 "alpha_fp_comparison_operator"
3643 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3644 (float_extend:DF
3645 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3646 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3647 "cmp%-%C1%/ %R2,%R3,%0"
3648 [(set_attr "type" "fadd")
3649 (set_attr "trap" "yes")
3650 (set_attr "trap_suffix" "su")])
3652 (define_insn "*cmpdf_ext2"
3653 [(set (match_operand:DF 0 "register_operand" "=f")
3654 (match_operator:DF 1 "alpha_fp_comparison_operator"
3655 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3656 (float_extend:DF
3657 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3658 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3659 "cmp%-%C1%/ %R2,%R3,%0"
3660 [(set_attr "type" "fadd")
3661 (set_attr "trap" "yes")
3662 (set_attr "trap_suffix" "su")])
3664 (define_insn "*cmpdf_ieee_ext3"
3665 [(set (match_operand:DF 0 "register_operand" "=&f")
3666 (match_operator:DF 1 "alpha_fp_comparison_operator"
3667 [(float_extend:DF
3668 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3669 (float_extend:DF
3670 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3671 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3672 "cmp%-%C1%/ %R2,%R3,%0"
3673 [(set_attr "type" "fadd")
3674 (set_attr "trap" "yes")
3675 (set_attr "trap_suffix" "su")])
3677 (define_insn "*cmpdf_ext3"
3678 [(set (match_operand:DF 0 "register_operand" "=f")
3679 (match_operator:DF 1 "alpha_fp_comparison_operator"
3680 [(float_extend:DF
3681 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3682 (float_extend:DF
3683 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3684 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3685 "cmp%-%C1%/ %R2,%R3,%0"
3686 [(set_attr "type" "fadd")
3687 (set_attr "trap" "yes")
3688 (set_attr "trap_suffix" "su")])
3690 (define_insn "*movdfcc_internal"
3691 [(set (match_operand:DF 0 "register_operand" "=f,f")
3692 (if_then_else:DF
3693 (match_operator 3 "signed_comparison_operator"
3694 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3695 (match_operand:DF 2 "const0_operand" "G,G")])
3696 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3697 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3698 "TARGET_FP"
3699 "@
3700 fcmov%C3 %R4,%R1,%0
3701 fcmov%D3 %R4,%R5,%0"
3702 [(set_attr "type" "fcmov")])
3704 (define_insn "*movsfcc_internal"
3705 [(set (match_operand:SF 0 "register_operand" "=f,f")
3706 (if_then_else:SF
3707 (match_operator 3 "signed_comparison_operator"
3708 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3709 (match_operand:DF 2 "const0_operand" "G,G")])
3710 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3711 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3712 "TARGET_FP"
3713 "@
3714 fcmov%C3 %R4,%R1,%0
3715 fcmov%D3 %R4,%R5,%0"
3716 [(set_attr "type" "fcmov")])
3718 (define_insn "*movdfcc_ext1"
3719 [(set (match_operand:DF 0 "register_operand" "=f,f")
3720 (if_then_else:DF
3721 (match_operator 3 "signed_comparison_operator"
3722 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3723 (match_operand:DF 2 "const0_operand" "G,G")])
3724 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3725 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3726 "TARGET_FP"
3727 "@
3728 fcmov%C3 %R4,%R1,%0
3729 fcmov%D3 %R4,%R5,%0"
3730 [(set_attr "type" "fcmov")])
3732 (define_insn "*movdfcc_ext2"
3733 [(set (match_operand:DF 0 "register_operand" "=f,f")
3734 (if_then_else:DF
3735 (match_operator 3 "signed_comparison_operator"
3736 [(float_extend:DF
3737 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3738 (match_operand:DF 2 "const0_operand" "G,G")])
3739 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3740 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3741 "TARGET_FP"
3742 "@
3743 fcmov%C3 %R4,%R1,%0
3744 fcmov%D3 %R4,%R5,%0"
3745 [(set_attr "type" "fcmov")])
3747 (define_insn "*movdfcc_ext3"
3748 [(set (match_operand:SF 0 "register_operand" "=f,f")
3749 (if_then_else:SF
3750 (match_operator 3 "signed_comparison_operator"
3751 [(float_extend:DF
3752 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3753 (match_operand:DF 2 "const0_operand" "G,G")])
3754 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3755 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3756 "TARGET_FP"
3757 "@
3758 fcmov%C3 %R4,%R1,%0
3759 fcmov%D3 %R4,%R5,%0"
3760 [(set_attr "type" "fcmov")])
3762 (define_insn "*movdfcc_ext4"
3763 [(set (match_operand:DF 0 "register_operand" "=f,f")
3764 (if_then_else:DF
3765 (match_operator 3 "signed_comparison_operator"
3766 [(float_extend:DF
3767 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3768 (match_operand:DF 2 "const0_operand" "G,G")])
3769 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3770 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3771 "TARGET_FP"
3772 "@
3773 fcmov%C3 %R4,%R1,%0
3774 fcmov%D3 %R4,%R5,%0"
3775 [(set_attr "type" "fcmov")])
3777 (define_expand "smaxdf3"
3778 [(set (match_dup 3)
3779 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3780 (match_operand:DF 2 "reg_or_0_operand" "")))
3781 (set (match_operand:DF 0 "register_operand" "")
3782 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3783 (match_dup 1) (match_dup 2)))]
3784 "TARGET_FP"
3785 {
3786 operands[3] = gen_reg_rtx (DFmode);
3787 operands[4] = CONST0_RTX (DFmode);
3788 })
3790 (define_expand "smindf3"
3791 [(set (match_dup 3)
3792 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3793 (match_operand:DF 2 "reg_or_0_operand" "")))
3794 (set (match_operand:DF 0 "register_operand" "")
3795 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3796 (match_dup 1) (match_dup 2)))]
3797 "TARGET_FP"
3798 {
3799 operands[3] = gen_reg_rtx (DFmode);
3800 operands[4] = CONST0_RTX (DFmode);
3801 })
3803 (define_expand "smaxsf3"
3804 [(set (match_dup 3)
3805 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3806 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3807 (set (match_operand:SF 0 "register_operand" "")
3808 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3809 (match_dup 1) (match_dup 2)))]
3810 "TARGET_FP"
3811 {
3812 operands[3] = gen_reg_rtx (DFmode);
3813 operands[4] = CONST0_RTX (DFmode);
3814 })
3816 (define_expand "sminsf3"
3817 [(set (match_dup 3)
3818 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3819 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3820 (set (match_operand:SF 0 "register_operand" "")
3821 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3822 (match_dup 1) (match_dup 2)))]
3823 "TARGET_FP"
3824 {
3825 operands[3] = gen_reg_rtx (DFmode);
3826 operands[4] = CONST0_RTX (DFmode);
3827 })
3829 (define_insn "*fbcc_normal"
3830 [(set (pc)
3831 (if_then_else
3832 (match_operator 1 "signed_comparison_operator"
3833 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3834 (match_operand:DF 3 "const0_operand" "G")])
3835 (label_ref (match_operand 0 "" ""))
3836 (pc)))]
3837 "TARGET_FP"
3838 "fb%C1 %R2,%0"
3839 [(set_attr "type" "fbr")])
3841 (define_insn "*fbcc_ext_normal"
3842 [(set (pc)
3843 (if_then_else
3844 (match_operator 1 "signed_comparison_operator"
3845 [(float_extend:DF
3846 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3847 (match_operand:DF 3 "const0_operand" "G")])
3848 (label_ref (match_operand 0 "" ""))
3849 (pc)))]
3850 "TARGET_FP"
3851 "fb%C1 %R2,%0"
3852 [(set_attr "type" "fbr")])
3853 \f
3854 ;; These are the main define_expand's used to make conditional branches
3855 ;; and compares.
3857 (define_expand "cmpdf"
3858 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3859 (match_operand:DF 1 "reg_or_0_operand" "")))]
3860 "TARGET_FP"
3861 {
3862 alpha_compare.op0 = operands[0];
3863 alpha_compare.op1 = operands[1];
3864 alpha_compare.fp_p = 1;
3865 DONE;
3866 })
3868 (define_expand "cmptf"
3869 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3870 (match_operand:TF 1 "general_operand" "")))]
3871 "TARGET_HAS_XFLOATING_LIBS"
3872 {
3873 alpha_compare.op0 = operands[0];
3874 alpha_compare.op1 = operands[1];
3875 alpha_compare.fp_p = 1;
3876 DONE;
3877 })
3879 (define_expand "cmpdi"
3880 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3881 (match_operand:DI 1 "some_operand" "")))]
3882 ""
3883 {
3884 alpha_compare.op0 = operands[0];
3885 alpha_compare.op1 = operands[1];
3886 alpha_compare.fp_p = 0;
3887 DONE;
3888 })
3890 (define_expand "beq"
3891 [(set (pc)
3892 (if_then_else (match_dup 1)
3893 (label_ref (match_operand 0 "" ""))
3894 (pc)))]
3895 ""
3896 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3898 (define_expand "bne"
3899 [(set (pc)
3900 (if_then_else (match_dup 1)
3901 (label_ref (match_operand 0 "" ""))
3902 (pc)))]
3903 ""
3904 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3906 (define_expand "blt"
3907 [(set (pc)
3908 (if_then_else (match_dup 1)
3909 (label_ref (match_operand 0 "" ""))
3910 (pc)))]
3911 ""
3912 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3914 (define_expand "ble"
3915 [(set (pc)
3916 (if_then_else (match_dup 1)
3917 (label_ref (match_operand 0 "" ""))
3918 (pc)))]
3919 ""
3920 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3922 (define_expand "bgt"
3923 [(set (pc)
3924 (if_then_else (match_dup 1)
3925 (label_ref (match_operand 0 "" ""))
3926 (pc)))]
3927 ""
3928 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3930 (define_expand "bge"
3931 [(set (pc)
3932 (if_then_else (match_dup 1)
3933 (label_ref (match_operand 0 "" ""))
3934 (pc)))]
3935 ""
3936 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3938 (define_expand "bltu"
3939 [(set (pc)
3940 (if_then_else (match_dup 1)
3941 (label_ref (match_operand 0 "" ""))
3942 (pc)))]
3943 ""
3944 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3946 (define_expand "bleu"
3947 [(set (pc)
3948 (if_then_else (match_dup 1)
3949 (label_ref (match_operand 0 "" ""))
3950 (pc)))]
3951 ""
3952 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3954 (define_expand "bgtu"
3955 [(set (pc)
3956 (if_then_else (match_dup 1)
3957 (label_ref (match_operand 0 "" ""))
3958 (pc)))]
3959 ""
3960 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3962 (define_expand "bgeu"
3963 [(set (pc)
3964 (if_then_else (match_dup 1)
3965 (label_ref (match_operand 0 "" ""))
3966 (pc)))]
3967 ""
3968 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3970 (define_expand "bunordered"
3971 [(set (pc)
3972 (if_then_else (match_dup 1)
3973 (label_ref (match_operand 0 "" ""))
3974 (pc)))]
3975 ""
3976 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3978 (define_expand "bordered"
3979 [(set (pc)
3980 (if_then_else (match_dup 1)
3981 (label_ref (match_operand 0 "" ""))
3982 (pc)))]
3983 ""
3984 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3986 (define_expand "seq"
3987 [(set (match_operand:DI 0 "register_operand" "")
3988 (match_dup 1))]
3989 ""
3990 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3992 (define_expand "sne"
3993 [(set (match_operand:DI 0 "register_operand" "")
3994 (match_dup 1))]
3995 ""
3996 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3998 (define_expand "slt"
3999 [(set (match_operand:DI 0 "register_operand" "")
4000 (match_dup 1))]
4001 ""
4002 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4004 (define_expand "sle"
4005 [(set (match_operand:DI 0 "register_operand" "")
4006 (match_dup 1))]
4007 ""
4008 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4010 (define_expand "sgt"
4011 [(set (match_operand:DI 0 "register_operand" "")
4012 (match_dup 1))]
4013 ""
4014 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4016 (define_expand "sge"
4017 [(set (match_operand:DI 0 "register_operand" "")
4018 (match_dup 1))]
4019 ""
4020 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4022 (define_expand "sltu"
4023 [(set (match_operand:DI 0 "register_operand" "")
4024 (match_dup 1))]
4025 ""
4026 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4028 (define_expand "sleu"
4029 [(set (match_operand:DI 0 "register_operand" "")
4030 (match_dup 1))]
4031 ""
4032 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4034 (define_expand "sgtu"
4035 [(set (match_operand:DI 0 "register_operand" "")
4036 (match_dup 1))]
4037 ""
4038 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4040 (define_expand "sgeu"
4041 [(set (match_operand:DI 0 "register_operand" "")
4042 (match_dup 1))]
4043 ""
4044 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4046 (define_expand "sunordered"
4047 [(set (match_operand:DI 0 "register_operand" "")
4048 (match_dup 1))]
4049 ""
4050 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4052 (define_expand "sordered"
4053 [(set (match_operand:DI 0 "register_operand" "")
4054 (match_dup 1))]
4055 ""
4056 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4057 \f
4058 ;; These are the main define_expand's used to make conditional moves.
4060 (define_expand "movsicc"
4061 [(set (match_operand:SI 0 "register_operand" "")
4062 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4063 (match_operand:SI 2 "reg_or_8bit_operand" "")
4064 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4065 ""
4066 {
4067 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4068 FAIL;
4069 })
4071 (define_expand "movdicc"
4072 [(set (match_operand:DI 0 "register_operand" "")
4073 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4074 (match_operand:DI 2 "reg_or_8bit_operand" "")
4075 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4076 ""
4077 {
4078 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4079 FAIL;
4080 })
4082 (define_expand "movsfcc"
4083 [(set (match_operand:SF 0 "register_operand" "")
4084 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4085 (match_operand:SF 2 "reg_or_8bit_operand" "")
4086 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4087 ""
4088 {
4089 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4090 FAIL;
4091 })
4093 (define_expand "movdfcc"
4094 [(set (match_operand:DF 0 "register_operand" "")
4095 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4096 (match_operand:DF 2 "reg_or_8bit_operand" "")
4097 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4098 ""
4099 {
4100 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4101 FAIL;
4102 })
4103 \f
4104 ;; These define_split definitions are used in cases when comparisons have
4105 ;; not be stated in the correct way and we need to reverse the second
4106 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4107 ;; comparison that tests the result being reversed. We have one define_split
4108 ;; for each use of a comparison. They do not match valid insns and need
4109 ;; not generate valid insns.
4110 ;;
4111 ;; We can also handle equality comparisons (and inequality comparisons in
4112 ;; cases where the resulting add cannot overflow) by doing an add followed by
4113 ;; a comparison with zero. This is faster since the addition takes one
4114 ;; less cycle than a compare when feeding into a conditional move.
4115 ;; For this case, we also have an SImode pattern since we can merge the add
4116 ;; and sign extend and the order doesn't matter.
4117 ;;
4118 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4119 ;; operation could have been generated.
4121 (define_split
4122 [(set (match_operand:DI 0 "register_operand" "")
4123 (if_then_else:DI
4124 (match_operator 1 "comparison_operator"
4125 [(match_operand:DI 2 "reg_or_0_operand" "")
4126 (match_operand:DI 3 "reg_or_cint_operand" "")])
4127 (match_operand:DI 4 "reg_or_cint_operand" "")
4128 (match_operand:DI 5 "reg_or_cint_operand" "")))
4129 (clobber (match_operand:DI 6 "register_operand" ""))]
4130 "operands[3] != const0_rtx"
4131 [(set (match_dup 6) (match_dup 7))
4132 (set (match_dup 0)
4133 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4134 {
4135 enum rtx_code code = GET_CODE (operands[1]);
4136 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4138 /* If we are comparing for equality with a constant and that constant
4139 appears in the arm when the register equals the constant, use the
4140 register since that is more likely to match (and to produce better code
4141 if both would). */
4143 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4144 && rtx_equal_p (operands[4], operands[3]))
4145 operands[4] = operands[2];
4147 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4148 && rtx_equal_p (operands[5], operands[3]))
4149 operands[5] = operands[2];
4151 if (code == NE || code == EQ
4152 || (extended_count (operands[2], DImode, unsignedp) >= 1
4153 && extended_count (operands[3], DImode, unsignedp) >= 1))
4154 {
4155 if (GET_CODE (operands[3]) == CONST_INT)
4156 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4157 GEN_INT (- INTVAL (operands[3])));
4158 else
4159 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4161 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4162 }
4164 else if (code == EQ || code == LE || code == LT
4165 || code == LEU || code == LTU)
4166 {
4167 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4168 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4169 }
4170 else
4171 {
4172 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4173 operands[2], operands[3]);
4174 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4175 }
4176 })
4178 (define_split
4179 [(set (match_operand:DI 0 "register_operand" "")
4180 (if_then_else:DI
4181 (match_operator 1 "comparison_operator"
4182 [(match_operand:SI 2 "reg_or_0_operand" "")
4183 (match_operand:SI 3 "reg_or_cint_operand" "")])
4184 (match_operand:DI 4 "reg_or_8bit_operand" "")
4185 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4186 (clobber (match_operand:DI 6 "register_operand" ""))]
4187 "operands[3] != const0_rtx
4188 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4189 [(set (match_dup 6) (match_dup 7))
4190 (set (match_dup 0)
4191 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4192 {
4193 enum rtx_code code = GET_CODE (operands[1]);
4194 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4195 rtx tem;
4197 if ((code != NE && code != EQ
4198 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4199 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4200 FAIL;
4202 if (GET_CODE (operands[3]) == CONST_INT)
4203 tem = gen_rtx_PLUS (SImode, operands[2],
4204 GEN_INT (- INTVAL (operands[3])));
4205 else
4206 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4208 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4209 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4210 operands[6], const0_rtx);
4211 })
4213 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4215 (define_split
4216 [(set (match_operand 0 "register_operand" "")
4217 (if_then_else (match_operator 1 "signed_comparison_operator"
4218 [(match_operand:DI 2 "reg_or_0_operand" "")
4219 (const_int 0)])
4220 (match_operand 3 "const_int_operand" "")
4221 (match_operand 4 "const_int_operand" "")))]
4222 ""
4223 [(const_int 0)]
4224 {
4225 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4226 operands[2], operands[3], operands[4]))
4227 DONE;
4228 else
4229 FAIL;
4230 })
4232 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4233 ;; Oh well, we match it in movcc, so it must be partially our fault.
4234 (define_split
4235 [(set (match_operand 0 "register_operand" "")
4236 (if_then_else (match_operator 1 "signed_comparison_operator"
4237 [(const_int 0)
4238 (match_operand:DI 2 "reg_or_0_operand" "")])
4239 (match_operand 3 "const_int_operand" "")
4240 (match_operand 4 "const_int_operand" "")))]
4241 ""
4242 [(const_int 0)]
4243 {
4244 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4245 operands[0], operands[2], operands[3],
4246 operands[4]))
4247 DONE;
4248 else
4249 FAIL;
4250 })
4252 (define_insn_and_split "*cmp_sadd_di"
4253 [(set (match_operand:DI 0 "register_operand" "=r")
4254 (plus:DI (if_then_else:DI
4255 (match_operator 1 "alpha_zero_comparison_operator"
4256 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4257 (const_int 0)])
4258 (match_operand:DI 3 "const48_operand" "I")
4259 (const_int 0))
4260 (match_operand:DI 4 "sext_add_operand" "rIO")))
4261 (clobber (match_scratch:DI 5 "=r"))]
4262 ""
4263 "#"
4264 "! no_new_pseudos || reload_completed"
4265 [(set (match_dup 5)
4266 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4267 (set (match_dup 0)
4268 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4269 (match_dup 4)))]
4270 {
4271 if (! no_new_pseudos)
4272 operands[5] = gen_reg_rtx (DImode);
4273 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4274 operands[5] = operands[0];
4275 })
4277 (define_insn_and_split "*cmp_sadd_si"
4278 [(set (match_operand:SI 0 "register_operand" "=r")
4279 (plus:SI (if_then_else:SI
4280 (match_operator 1 "alpha_zero_comparison_operator"
4281 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4282 (const_int 0)])
4283 (match_operand:SI 3 "const48_operand" "I")
4284 (const_int 0))
4285 (match_operand:SI 4 "sext_add_operand" "rIO")))
4286 (clobber (match_scratch:SI 5 "=r"))]
4287 ""
4288 "#"
4289 "! no_new_pseudos || reload_completed"
4290 [(set (match_dup 5)
4291 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4292 (set (match_dup 0)
4293 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4294 (match_dup 4)))]
4295 {
4296 if (! no_new_pseudos)
4297 operands[5] = gen_reg_rtx (DImode);
4298 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4299 operands[5] = operands[0];
4300 })
4302 (define_insn_and_split "*cmp_sadd_sidi"
4303 [(set (match_operand:DI 0 "register_operand" "=r")
4304 (sign_extend:DI
4305 (plus:SI (if_then_else:SI
4306 (match_operator 1 "alpha_zero_comparison_operator"
4307 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4308 (const_int 0)])
4309 (match_operand:SI 3 "const48_operand" "I")
4310 (const_int 0))
4311 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4312 (clobber (match_scratch:SI 5 "=r"))]
4313 ""
4314 "#"
4315 "! no_new_pseudos || reload_completed"
4316 [(set (match_dup 5)
4317 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4318 (set (match_dup 0)
4319 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4320 (match_dup 4))))]
4321 {
4322 if (! no_new_pseudos)
4323 operands[5] = gen_reg_rtx (DImode);
4324 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4325 operands[5] = operands[0];
4326 })
4328 (define_insn_and_split "*cmp_ssub_di"
4329 [(set (match_operand:DI 0 "register_operand" "=r")
4330 (minus:DI (if_then_else:DI
4331 (match_operator 1 "alpha_zero_comparison_operator"
4332 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4333 (const_int 0)])
4334 (match_operand:DI 3 "const48_operand" "I")
4335 (const_int 0))
4336 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4337 (clobber (match_scratch:DI 5 "=r"))]
4338 ""
4339 "#"
4340 "! no_new_pseudos || reload_completed"
4341 [(set (match_dup 5)
4342 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4343 (set (match_dup 0)
4344 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4345 (match_dup 4)))]
4346 {
4347 if (! no_new_pseudos)
4348 operands[5] = gen_reg_rtx (DImode);
4349 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4350 operands[5] = operands[0];
4351 })
4353 (define_insn_and_split "*cmp_ssub_si"
4354 [(set (match_operand:SI 0 "register_operand" "=r")
4355 (minus:SI (if_then_else:SI
4356 (match_operator 1 "alpha_zero_comparison_operator"
4357 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4358 (const_int 0)])
4359 (match_operand:SI 3 "const48_operand" "I")
4360 (const_int 0))
4361 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4362 (clobber (match_scratch:SI 5 "=r"))]
4363 ""
4364 "#"
4365 "! no_new_pseudos || reload_completed"
4366 [(set (match_dup 5)
4367 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4368 (set (match_dup 0)
4369 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4370 (match_dup 4)))]
4371 {
4372 if (! no_new_pseudos)
4373 operands[5] = gen_reg_rtx (DImode);
4374 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4375 operands[5] = operands[0];
4376 })
4378 (define_insn_and_split "*cmp_ssub_sidi"
4379 [(set (match_operand:DI 0 "register_operand" "=r")
4380 (sign_extend:DI
4381 (minus:SI (if_then_else:SI
4382 (match_operator 1 "alpha_zero_comparison_operator"
4383 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4384 (const_int 0)])
4385 (match_operand:SI 3 "const48_operand" "I")
4386 (const_int 0))
4387 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4388 (clobber (match_scratch:SI 5 "=r"))]
4389 ""
4390 "#"
4391 "! no_new_pseudos || reload_completed"
4392 [(set (match_dup 5)
4393 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4394 (set (match_dup 0)
4395 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4396 (match_dup 4))))]
4397 {
4398 if (! no_new_pseudos)
4399 operands[5] = gen_reg_rtx (DImode);
4400 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4401 operands[5] = operands[0];
4402 })
4403 \f
4404 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4405 ;; work differently, so we have different patterns for each.
4407 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4408 ;; call. The CIW contains information about arguments passed in registers
4409 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4410 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4411 ;; in the presence of inlining since the CIWs for calls performed by the
4412 ;; inlined function must be stored in the SSIB of the function it is inlined
4413 ;; into as well. We encode the CIW in an unspec and append it to the list
4414 ;; of the CIWs for the current function only when the instruction for loading
4415 ;; $25 is generated.
4417 (define_expand "call"
4418 [(use (match_operand:DI 0 "" ""))
4419 (use (match_operand 1 "" ""))
4420 (use (match_operand 2 "" ""))
4421 (use (match_operand 3 "" ""))]
4422 ""
4423 {
4424 if (TARGET_ABI_WINDOWS_NT)
4425 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4426 else if (TARGET_ABI_OPEN_VMS)
4427 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4428 else if (TARGET_ABI_UNICOSMK)
4429 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4430 else
4431 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4432 DONE;
4433 })
4435 (define_expand "sibcall"
4436 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4437 (match_operand 1 "" ""))
4438 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4439 "TARGET_ABI_OSF"
4440 {
4441 if (GET_CODE (operands[0]) != MEM)
4442 abort ();
4443 operands[0] = XEXP (operands[0], 0);
4444 })
4446 (define_expand "call_osf"
4447 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4448 (match_operand 1 "" ""))
4449 (use (reg:DI 29))
4450 (clobber (reg:DI 26))])]
4451 ""
4452 {
4453 if (GET_CODE (operands[0]) != MEM)
4454 abort ();
4456 operands[0] = XEXP (operands[0], 0);
4457 if (! call_operand (operands[0], Pmode))
4458 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4459 })
4461 (define_expand "call_nt"
4462 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4463 (match_operand 1 "" ""))
4464 (clobber (reg:DI 26))])]
4465 ""
4466 {
4467 if (GET_CODE (operands[0]) != MEM)
4468 abort ();
4470 operands[0] = XEXP (operands[0], 0);
4471 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4472 operands[0] = force_reg (DImode, operands[0]);
4473 })
4475 ;; Calls on Unicos/Mk are always indirect.
4476 ;; op 0: symbol ref for called function
4477 ;; op 1: CIW for $25 represented by an unspec
4479 (define_expand "call_umk"
4480 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4481 (match_operand 1 "" ""))
4482 (use (reg:DI 25))
4483 (clobber (reg:DI 26))])]
4484 ""
4485 {
4486 if (GET_CODE (operands[0]) != MEM)
4487 abort ();
4489 /* Always load the address of the called function into a register;
4490 load the CIW in $25. */
4492 operands[0] = XEXP (operands[0], 0);
4493 if (GET_CODE (operands[0]) != REG)
4494 operands[0] = force_reg (DImode, operands[0]);
4496 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4497 })
4499 ;;
4500 ;; call openvms/alpha
4501 ;; op 0: symbol ref for called function
4502 ;; op 1: next_arg_reg (argument information value for R25)
4503 ;;
4504 (define_expand "call_vms"
4505 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4506 (match_operand 1 "" ""))
4507 (use (match_dup 2))
4508 (use (reg:DI 25))
4509 (use (reg:DI 26))
4510 (clobber (reg:DI 27))])]
4511 ""
4512 {
4513 if (GET_CODE (operands[0]) != MEM)
4514 abort ();
4516 operands[0] = XEXP (operands[0], 0);
4518 /* Always load AI with argument information, then handle symbolic and
4519 indirect call differently. Load RA and set operands[2] to PV in
4520 both cases. */
4522 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4523 if (GET_CODE (operands[0]) == SYMBOL_REF)
4524 {
4525 alpha_need_linkage (XSTR (operands[0], 0), 0);
4527 operands[2] = const0_rtx;
4528 }
4529 else
4530 {
4531 emit_move_insn (gen_rtx_REG (Pmode, 26),
4532 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4533 operands[2] = operands[0];
4534 }
4536 })
4538 (define_expand "call_value"
4539 [(use (match_operand 0 "" ""))
4540 (use (match_operand:DI 1 "" ""))
4541 (use (match_operand 2 "" ""))
4542 (use (match_operand 3 "" ""))
4543 (use (match_operand 4 "" ""))]
4544 ""
4545 {
4546 if (TARGET_ABI_WINDOWS_NT)
4547 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4548 else if (TARGET_ABI_OPEN_VMS)
4549 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4550 operands[3]));
4551 else if (TARGET_ABI_UNICOSMK)
4552 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4553 operands[3]));
4554 else
4555 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4556 operands[2]));
4557 DONE;
4558 })
4560 (define_expand "sibcall_value"
4561 [(parallel [(set (match_operand 0 "" "")
4562 (call (mem:DI (match_operand 1 "" ""))
4563 (match_operand 2 "" "")))
4564 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4565 "TARGET_ABI_OSF"
4566 {
4567 if (GET_CODE (operands[1]) != MEM)
4568 abort ();
4569 operands[1] = XEXP (operands[1], 0);
4570 })
4572 (define_expand "call_value_osf"
4573 [(parallel [(set (match_operand 0 "" "")
4574 (call (mem:DI (match_operand 1 "" ""))
4575 (match_operand 2 "" "")))
4576 (use (reg:DI 29))
4577 (clobber (reg:DI 26))])]
4578 ""
4579 {
4580 if (GET_CODE (operands[1]) != MEM)
4581 abort ();
4583 operands[1] = XEXP (operands[1], 0);
4584 if (! call_operand (operands[1], Pmode))
4585 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4586 })
4588 (define_expand "call_value_nt"
4589 [(parallel [(set (match_operand 0 "" "")
4590 (call (mem:DI (match_operand 1 "" ""))
4591 (match_operand 2 "" "")))
4592 (clobber (reg:DI 26))])]
4593 ""
4594 {
4595 if (GET_CODE (operands[1]) != MEM)
4596 abort ();
4598 operands[1] = XEXP (operands[1], 0);
4599 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4600 operands[1] = force_reg (DImode, operands[1]);
4601 })
4603 (define_expand "call_value_vms"
4604 [(parallel [(set (match_operand 0 "" "")
4605 (call (mem:DI (match_operand:DI 1 "" ""))
4606 (match_operand 2 "" "")))
4607 (use (match_dup 3))
4608 (use (reg:DI 25))
4609 (use (reg:DI 26))
4610 (clobber (reg:DI 27))])]
4611 ""
4612 {
4613 if (GET_CODE (operands[1]) != MEM)
4614 abort ();
4616 operands[1] = XEXP (operands[1], 0);
4618 /* Always load AI with argument information, then handle symbolic and
4619 indirect call differently. Load RA and set operands[3] to PV in
4620 both cases. */
4622 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4623 if (GET_CODE (operands[1]) == SYMBOL_REF)
4624 {
4625 alpha_need_linkage (XSTR (operands[1], 0), 0);
4627 operands[3] = const0_rtx;
4628 }
4629 else
4630 {
4631 emit_move_insn (gen_rtx_REG (Pmode, 26),
4632 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4633 operands[3] = operands[1];
4634 }
4635 })
4637 (define_expand "call_value_umk"
4638 [(parallel [(set (match_operand 0 "" "")
4639 (call (mem:DI (match_operand 1 "" ""))
4640 (match_operand 2 "" "")))
4641 (use (reg:DI 25))
4642 (clobber (reg:DI 26))])]
4643 ""
4644 {
4645 if (GET_CODE (operands[1]) != MEM)
4646 abort ();
4648 operands[1] = XEXP (operands[1], 0);
4649 if (GET_CODE (operands[1]) != REG)
4650 operands[1] = force_reg (DImode, operands[1]);
4652 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4653 })
4655 (define_insn "*call_osf_1_er"
4656 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4657 (match_operand 1 "" ""))
4658 (use (reg:DI 29))
4659 (clobber (reg:DI 26))]
4660 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4661 "@
4662 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4663 bsr $26,%0\t\t!samegp
4664 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4665 [(set_attr "type" "jsr")
4666 (set_attr "length" "12,*,16")])
4668 ;; We must use peep2 instead of a split because we need accurate life
4669 ;; information for $gp. Consider the case of { bar(); while (1); }.
4670 (define_peephole2
4671 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4672 (match_operand 1 "" ""))
4673 (use (reg:DI 29))
4674 (clobber (reg:DI 26))])]
4675 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4676 && ! samegp_function_operand (operands[0], Pmode)
4677 && (peep2_regno_dead_p (1, 29)
4678 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4679 [(parallel [(call (mem:DI (match_dup 2))
4680 (match_dup 1))
4681 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4682 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4683 (use (match_dup 0))
4684 (use (match_dup 3))])]
4685 {
4686 if (CONSTANT_P (operands[0]))
4687 {
4688 operands[2] = gen_rtx_REG (Pmode, 27);
4689 operands[3] = GEN_INT (alpha_next_sequence_number++);
4690 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4691 operands[0], operands[3]));
4692 }
4693 else
4694 {
4695 operands[2] = operands[0];
4696 operands[0] = const0_rtx;
4697 operands[3] = const0_rtx;
4698 }
4699 })
4701 (define_peephole2
4702 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4703 (match_operand 1 "" ""))
4704 (use (reg:DI 29))
4705 (clobber (reg:DI 26))])]
4706 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4707 && ! samegp_function_operand (operands[0], Pmode)
4708 && ! (peep2_regno_dead_p (1, 29)
4709 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4710 [(parallel [(call (mem:DI (match_dup 2))
4711 (match_dup 1))
4712 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4713 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4714 (use (match_dup 0))
4715 (use (match_dup 4))])
4716 (set (reg:DI 29)
4717 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4718 (set (reg:DI 29)
4719 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4720 {
4721 if (CONSTANT_P (operands[0]))
4722 {
4723 operands[2] = gen_rtx_REG (Pmode, 27);
4724 operands[4] = GEN_INT (alpha_next_sequence_number++);
4725 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4726 operands[0], operands[4]));
4727 }
4728 else
4729 {
4730 operands[2] = operands[0];
4731 operands[0] = const0_rtx;
4732 operands[4] = const0_rtx;
4733 }
4734 operands[3] = GEN_INT (alpha_next_sequence_number++);
4735 })
4737 ;; We add a blockage unspec_volatile to prevent insns from moving down
4738 ;; from above the call to in between the call and the ldah gpdisp.
4740 (define_insn "*call_osf_2_er"
4741 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4742 (match_operand 1 "" ""))
4743 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4744 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4745 (use (match_operand 2 "" ""))
4746 (use (match_operand 3 "const_int_operand" ""))]
4747 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4748 "jsr $26,(%0),%2%J3"
4749 [(set_attr "type" "jsr")
4750 (set_attr "cannot_copy" "true")])
4752 ;; We output a nop after noreturn calls at the very end of the function to
4753 ;; ensure that the return address always remains in the caller's code range,
4754 ;; as not doing so might confuse unwinding engines.
4755 ;;
4756 ;; The potential change in insn length is not reflected in the length
4757 ;; attributes at this stage. Since the extra space is only actually added at
4758 ;; the very end of the compilation process (via final/print_operand), it
4759 ;; really seems harmless and not worth the trouble of some extra computation
4760 ;; cost and complexity.
4762 (define_insn "*call_osf_1_noreturn"
4763 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4764 (match_operand 1 "" ""))
4765 (use (reg:DI 29))
4766 (clobber (reg:DI 26))]
4767 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4768 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4769 "@
4770 jsr $26,($27),0%+
4771 bsr $26,$%0..ng%+
4772 jsr $26,%0%+"
4773 [(set_attr "type" "jsr")
4774 (set_attr "length" "*,*,8")])
4776 (define_insn "*call_osf_1"
4777 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4778 (match_operand 1 "" ""))
4779 (use (reg:DI 29))
4780 (clobber (reg:DI 26))]
4781 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4782 "@
4783 jsr $26,($27),0\;ldgp $29,0($26)
4784 bsr $26,$%0..ng
4785 jsr $26,%0\;ldgp $29,0($26)"
4786 [(set_attr "type" "jsr")
4787 (set_attr "length" "12,*,16")])
4789 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4790 ;; doesn't do what we want.
4791 (define_insn "*sibcall_osf_1_er"
4792 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4793 (match_operand 1 "" ""))
4794 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4795 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4796 "@
4797 br $31,%0\t\t!samegp
4798 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4799 [(set_attr "type" "jsr")
4800 (set_attr "length" "*,8")])
4802 (define_insn "*sibcall_osf_1"
4803 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4804 (match_operand 1 "" ""))
4805 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4806 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4807 "@
4808 br $31,$%0..ng
4809 lda $27,%0\;jmp $31,($27),%0"
4810 [(set_attr "type" "jsr")
4811 (set_attr "length" "*,8")])
4813 (define_insn "*call_nt_1"
4814 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4815 (match_operand 1 "" ""))
4816 (clobber (reg:DI 26))]
4817 "TARGET_ABI_WINDOWS_NT"
4818 "@
4819 jsr $26,(%0)
4820 bsr $26,%0
4821 jsr $26,%0"
4822 [(set_attr "type" "jsr")
4823 (set_attr "length" "*,*,12")])
4825 ; GAS relies on the order and position of instructions output below in order
4826 ; to generate relocs for VMS link to potentially optimize the call.
4827 ; Please do not molest.
4828 (define_insn "*call_vms_1"
4829 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4830 (match_operand 1 "" ""))
4831 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4832 (use (reg:DI 25))
4833 (use (reg:DI 26))
4834 (clobber (reg:DI 27))]
4835 "TARGET_ABI_OPEN_VMS"
4836 {
4837 switch (which_alternative)
4838 {
4839 case 0:
4840 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4841 case 1:
4842 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4843 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4844 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4845 default:
4846 abort();
4847 }
4848 }
4849 [(set_attr "type" "jsr")
4850 (set_attr "length" "12,16")])
4852 (define_insn "*call_umk_1"
4853 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4854 (match_operand 1 "" ""))
4855 (use (reg:DI 25))
4856 (clobber (reg:DI 26))]
4857 "TARGET_ABI_UNICOSMK"
4858 "jsr $26,(%0)"
4859 [(set_attr "type" "jsr")])
4861 ;; Call subroutine returning any type.
4863 (define_expand "untyped_call"
4864 [(parallel [(call (match_operand 0 "" "")
4865 (const_int 0))
4866 (match_operand 1 "" "")
4867 (match_operand 2 "" "")])]
4868 ""
4869 {
4870 int i;
4872 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4874 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4875 {
4876 rtx set = XVECEXP (operands[2], 0, i);
4877 emit_move_insn (SET_DEST (set), SET_SRC (set));
4878 }
4880 /* The optimizer does not know that the call sets the function value
4881 registers we stored in the result block. We avoid problems by
4882 claiming that all hard registers are used and clobbered at this
4883 point. */
4884 emit_insn (gen_blockage ());
4886 DONE;
4887 })
4889 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4890 ;; all of memory. This blocks insns from being moved across this point.
4892 (define_insn "blockage"
4893 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4894 ""
4895 ""
4896 [(set_attr "length" "0")
4897 (set_attr "type" "none")])
4899 (define_insn "jump"
4900 [(set (pc)
4901 (label_ref (match_operand 0 "" "")))]
4902 ""
4903 "br $31,%l0"
4904 [(set_attr "type" "ibr")])
4906 (define_expand "return"
4907 [(return)]
4908 "direct_return ()"
4909 "")
4911 (define_insn "*return_internal"
4912 [(return)]
4913 "reload_completed"
4914 "ret $31,($26),1"
4915 [(set_attr "type" "ibr")])
4917 (define_insn "indirect_jump"
4918 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4919 ""
4920 "jmp $31,(%0),0"
4921 [(set_attr "type" "ibr")])
4923 (define_expand "tablejump"
4924 [(parallel [(set (pc)
4925 (match_operand 0 "register_operand" ""))
4926 (use (label_ref:DI (match_operand 1 "" "")))])]
4927 ""
4928 {
4929 if (TARGET_ABI_WINDOWS_NT)
4930 {
4931 rtx dest = gen_reg_rtx (DImode);
4932 emit_insn (gen_extendsidi2 (dest, operands[0]));
4933 operands[0] = dest;
4934 }
4935 else if (TARGET_ABI_OSF)
4936 {
4937 rtx dest = gen_reg_rtx (DImode);
4938 emit_insn (gen_extendsidi2 (dest, operands[0]));
4939 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4940 operands[0] = dest;
4941 }
4942 })
4944 (define_insn "*tablejump_osf_nt_internal"
4945 [(set (pc)
4946 (match_operand:DI 0 "register_operand" "r"))
4947 (use (label_ref:DI (match_operand 1 "" "")))]
4948 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4949 && alpha_tablejump_addr_vec (insn)"
4950 {
4951 operands[2] = alpha_tablejump_best_label (insn);
4952 return "jmp $31,(%0),%2";
4953 }
4954 [(set_attr "type" "ibr")])
4956 (define_insn "*tablejump_internal"
4957 [(set (pc)
4958 (match_operand:DI 0 "register_operand" "r"))
4959 (use (label_ref (match_operand 1 "" "")))]
4960 ""
4961 "jmp $31,(%0),0"
4962 [(set_attr "type" "ibr")])
4964 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4965 ;; want to have to include pal.h in our .s file.
4966 ;;
4967 ;; Technically the type for call_pal is jsr, but we use that for determining
4968 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4969 ;; characteristics.
4970 (define_insn "imb"
4971 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4972 ""
4973 "call_pal 0x86"
4974 [(set_attr "type" "callpal")])
4976 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4977 ;; NT does not document anything at 0x81 -- presumably it would generate
4978 ;; the equivalent of SIGILL, but this isn't that important.
4979 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4980 (define_insn "trap"
4981 [(trap_if (const_int 1) (const_int 0))]
4982 "!TARGET_ABI_WINDOWS_NT"
4983 "call_pal 0x81"
4984 [(set_attr "type" "callpal")])
4986 ;; For userland, we load the thread pointer from the TCB.
4987 ;; For the kernel, we load the per-cpu private value.
4989 (define_insn "load_tp"
4990 [(set (match_operand:DI 0 "register_operand" "=v")
4991 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4992 "TARGET_ABI_OSF"
4993 {
4994 if (TARGET_TLS_KERNEL)
4995 return "call_pal 0x32";
4996 else
4997 return "call_pal 0x9e";
4998 }
4999 [(set_attr "type" "callpal")])
5001 ;; For completeness, and possibly a __builtin function, here's how to
5002 ;; set the thread pointer. Since we don't describe enough of this
5003 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5004 ;; not much point in creating an R16_REG register class.
5006 (define_expand "set_tp"
5007 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5008 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5009 "TARGET_ABI_OSF"
5010 "")
5012 (define_insn "*set_tp"
5013 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5014 "TARGET_ABI_OSF"
5015 {
5016 if (TARGET_TLS_KERNEL)
5017 return "call_pal 0x31";
5018 else
5019 return "call_pal 0x9f";
5020 }
5021 [(set_attr "type" "callpal")])
5022 \f
5023 ;; Finally, we have the basic data motion insns. The byte and word insns
5024 ;; are done via define_expand. Start with the floating-point insns, since
5025 ;; they are simpler.
5027 (define_insn "*movsf_nofix"
5028 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5029 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5030 "TARGET_FPREGS && ! TARGET_FIX
5031 && (register_operand (operands[0], SFmode)
5032 || reg_or_0_operand (operands[1], SFmode))"
5033 "@
5034 cpys %R1,%R1,%0
5035 ld%, %0,%1
5036 bis $31,%r1,%0
5037 ldl %0,%1
5038 st%, %R1,%0
5039 stl %r1,%0"
5040 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5042 (define_insn "*movsf_fix"
5043 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5044 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5045 "TARGET_FPREGS && TARGET_FIX
5046 && (register_operand (operands[0], SFmode)
5047 || reg_or_0_operand (operands[1], SFmode))"
5048 "@
5049 cpys %R1,%R1,%0
5050 ld%, %0,%1
5051 bis $31,%r1,%0
5052 ldl %0,%1
5053 st%, %R1,%0
5054 stl %r1,%0
5055 itofs %1,%0
5056 ftois %1,%0"
5057 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5059 (define_insn "*movsf_nofp"
5060 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5061 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5062 "! TARGET_FPREGS
5063 && (register_operand (operands[0], SFmode)
5064 || reg_or_0_operand (operands[1], SFmode))"
5065 "@
5066 bis $31,%r1,%0
5067 ldl %0,%1
5068 stl %r1,%0"
5069 [(set_attr "type" "ilog,ild,ist")])
5071 (define_insn "*movdf_nofix"
5072 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5073 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5074 "TARGET_FPREGS && ! TARGET_FIX
5075 && (register_operand (operands[0], DFmode)
5076 || reg_or_0_operand (operands[1], DFmode))"
5077 "@
5078 cpys %R1,%R1,%0
5079 ld%- %0,%1
5080 bis $31,%r1,%0
5081 ldq %0,%1
5082 st%- %R1,%0
5083 stq %r1,%0"
5084 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5086 (define_insn "*movdf_fix"
5087 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5088 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5089 "TARGET_FPREGS && TARGET_FIX
5090 && (register_operand (operands[0], DFmode)
5091 || reg_or_0_operand (operands[1], DFmode))"
5092 "@
5093 cpys %R1,%R1,%0
5094 ld%- %0,%1
5095 bis $31,%r1,%0
5096 ldq %0,%1
5097 st%- %R1,%0
5098 stq %r1,%0
5099 itoft %1,%0
5100 ftoit %1,%0"
5101 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5103 (define_insn "*movdf_nofp"
5104 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5105 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5106 "! TARGET_FPREGS
5107 && (register_operand (operands[0], DFmode)
5108 || reg_or_0_operand (operands[1], DFmode))"
5109 "@
5110 bis $31,%r1,%0
5111 ldq %0,%1
5112 stq %r1,%0"
5113 [(set_attr "type" "ilog,ild,ist")])
5115 ;; Subregs suck for register allocation. Pretend we can move TFmode
5116 ;; data between general registers until after reload.
5118 (define_insn_and_split "*movtf_internal"
5119 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5120 (match_operand:TF 1 "input_operand" "roG,rG"))]
5121 "register_operand (operands[0], TFmode)
5122 || reg_or_0_operand (operands[1], TFmode)"
5123 "#"
5124 "reload_completed"
5125 [(set (match_dup 0) (match_dup 2))
5126 (set (match_dup 1) (match_dup 3))]
5127 {
5128 alpha_split_tfmode_pair (operands);
5129 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5130 {
5131 rtx tmp;
5132 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5133 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5134 }
5135 })
5137 (define_expand "movsf"
5138 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5139 (match_operand:SF 1 "general_operand" ""))]
5140 ""
5141 {
5142 if (GET_CODE (operands[0]) == MEM
5143 && ! reg_or_0_operand (operands[1], SFmode))
5144 operands[1] = force_reg (SFmode, operands[1]);
5145 })
5147 (define_expand "movdf"
5148 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5149 (match_operand:DF 1 "general_operand" ""))]
5150 ""
5151 {
5152 if (GET_CODE (operands[0]) == MEM
5153 && ! reg_or_0_operand (operands[1], DFmode))
5154 operands[1] = force_reg (DFmode, operands[1]);
5155 })
5157 (define_expand "movtf"
5158 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5159 (match_operand:TF 1 "general_operand" ""))]
5160 ""
5161 {
5162 if (GET_CODE (operands[0]) == MEM
5163 && ! reg_or_0_operand (operands[1], TFmode))
5164 operands[1] = force_reg (TFmode, operands[1]);
5165 })
5167 (define_insn "*movsi"
5168 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5169 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5170 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5171 && (register_operand (operands[0], SImode)
5172 || reg_or_0_operand (operands[1], SImode))"
5173 "@
5174 bis $31,%r1,%0
5175 lda %0,%1($31)
5176 ldah %0,%h1($31)
5177 #
5178 ldl %0,%1
5179 stl %r1,%0"
5180 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5182 (define_insn "*movsi_nt_vms"
5183 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5184 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5185 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5186 && (register_operand (operands[0], SImode)
5187 || reg_or_0_operand (operands[1], SImode))"
5188 "@
5189 bis $31,%1,%0
5190 lda %0,%1
5191 ldah %0,%h1
5192 lda %0,%1
5193 #
5194 ldl %0,%1
5195 stl %r1,%0"
5196 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5198 (define_insn "*movhi_nobwx"
5199 [(set (match_operand:HI 0 "register_operand" "=r,r")
5200 (match_operand:HI 1 "input_operand" "rJ,n"))]
5201 "! TARGET_BWX
5202 && (register_operand (operands[0], HImode)
5203 || register_operand (operands[1], HImode))"
5204 "@
5205 bis $31,%r1,%0
5206 lda %0,%L1($31)"
5207 [(set_attr "type" "ilog,iadd")])
5209 (define_insn "*movhi_bwx"
5210 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5211 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5212 "TARGET_BWX
5213 && (register_operand (operands[0], HImode)
5214 || reg_or_0_operand (operands[1], HImode))"
5215 "@
5216 bis $31,%r1,%0
5217 lda %0,%L1($31)
5218 ldwu %0,%1
5219 stw %r1,%0"
5220 [(set_attr "type" "ilog,iadd,ild,ist")])
5222 (define_insn "*movqi_nobwx"
5223 [(set (match_operand:QI 0 "register_operand" "=r,r")
5224 (match_operand:QI 1 "input_operand" "rJ,n"))]
5225 "! TARGET_BWX
5226 && (register_operand (operands[0], QImode)
5227 || register_operand (operands[1], QImode))"
5228 "@
5229 bis $31,%r1,%0
5230 lda %0,%L1($31)"
5231 [(set_attr "type" "ilog,iadd")])
5233 (define_insn "*movqi_bwx"
5234 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5235 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5236 "TARGET_BWX
5237 && (register_operand (operands[0], QImode)
5238 || reg_or_0_operand (operands[1], QImode))"
5239 "@
5240 bis $31,%r1,%0
5241 lda %0,%L1($31)
5242 ldbu %0,%1
5243 stb %r1,%0"
5244 [(set_attr "type" "ilog,iadd,ild,ist")])
5246 ;; We do two major things here: handle mem->mem and construct long
5247 ;; constants.
5249 (define_expand "movsi"
5250 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5251 (match_operand:SI 1 "general_operand" ""))]
5252 ""
5253 {
5254 if (alpha_expand_mov (SImode, operands))
5255 DONE;
5256 })
5258 ;; Split a load of a large constant into the appropriate two-insn
5259 ;; sequence.
5261 (define_split
5262 [(set (match_operand:SI 0 "register_operand" "")
5263 (match_operand:SI 1 "non_add_const_operand" ""))]
5264 ""
5265 [(const_int 0)]
5266 {
5267 if (alpha_split_const_mov (SImode, operands))
5268 DONE;
5269 else
5270 FAIL;
5271 })
5273 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5274 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5275 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5276 ;; notes and update LABEL_NUSES because this is not done automatically.
5277 ;; Labels may be incorrectly deleted if we don't do this.
5278 ;;
5279 ;; Describing what the individual instructions do correctly is too complicated
5280 ;; so use UNSPECs for each of the three parts of an address.
5282 (define_split
5283 [(set (match_operand:DI 0 "register_operand" "")
5284 (match_operand:DI 1 "symbolic_operand" ""))]
5285 "TARGET_ABI_UNICOSMK && reload_completed"
5286 [(const_int 0)]
5287 {
5288 rtx insn1, insn2, insn3;
5290 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5291 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5292 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5293 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5294 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5295 REG_NOTES (insn3));
5296 if (GET_CODE (operands[1]) == LABEL_REF)
5297 {
5298 rtx label;
5300 label = XEXP (operands[1], 0);
5301 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5302 REG_NOTES (insn1));
5303 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5304 REG_NOTES (insn2));
5305 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5306 REG_NOTES (insn3));
5307 LABEL_NUSES (label) += 3;
5308 }
5309 DONE;
5310 })
5312 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5314 (define_insn "umk_laum"
5315 [(set (match_operand:DI 0 "register_operand" "=r")
5316 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5317 UNSPEC_UMK_LAUM))]
5318 "TARGET_ABI_UNICOSMK"
5319 "laum %r0,%t1($31)"
5320 [(set_attr "type" "iadd")])
5322 (define_insn "umk_lalm"
5323 [(set (match_operand:DI 0 "register_operand" "=r")
5324 (plus:DI (match_operand:DI 1 "register_operand" "r")
5325 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5326 UNSPEC_UMK_LALM)))]
5327 "TARGET_ABI_UNICOSMK"
5328 "lalm %r0,%t2(%r1)"
5329 [(set_attr "type" "iadd")])
5331 (define_insn "umk_lal"
5332 [(set (match_operand:DI 0 "register_operand" "=r")
5333 (plus:DI (match_operand:DI 1 "register_operand" "r")
5334 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5335 UNSPEC_UMK_LAL)))]
5336 "TARGET_ABI_UNICOSMK"
5337 "lal %r0,%t2(%r1)"
5338 [(set_attr "type" "iadd")])
5340 ;; Add a new call information word to the current function's list of CIWs
5341 ;; and load its index into $25. Doing it here ensures that the CIW will be
5342 ;; associated with the correct function even in the presence of inlining.
5344 (define_insn "*umk_load_ciw"
5345 [(set (reg:DI 25)
5346 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5347 "TARGET_ABI_UNICOSMK"
5348 {
5349 operands[0] = unicosmk_add_call_info_word (operands[0]);
5350 return "lda $25,%0";
5351 }
5352 [(set_attr "type" "iadd")])
5354 (define_insn "*movdi_er_low_l"
5355 [(set (match_operand:DI 0 "register_operand" "=r")
5356 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5357 (match_operand:DI 2 "local_symbolic_operand" "")))]
5358 "TARGET_EXPLICIT_RELOCS"
5359 {
5360 if (true_regnum (operands[1]) == 29)
5361 return "lda %0,%2(%1)\t\t!gprel";
5362 else
5363 return "lda %0,%2(%1)\t\t!gprellow";
5364 }
5365 [(set_attr "usegp" "yes")])
5367 (define_split
5368 [(set (match_operand:DI 0 "register_operand" "")
5369 (match_operand:DI 1 "small_symbolic_operand" ""))]
5370 "TARGET_EXPLICIT_RELOCS && reload_completed"
5371 [(set (match_dup 0)
5372 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5373 "operands[2] = pic_offset_table_rtx;")
5375 (define_split
5376 [(set (match_operand:DI 0 "register_operand" "")
5377 (match_operand:DI 1 "local_symbolic_operand" ""))]
5378 "TARGET_EXPLICIT_RELOCS && reload_completed"
5379 [(set (match_dup 0)
5380 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5381 (set (match_dup 0)
5382 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5383 "operands[2] = pic_offset_table_rtx;")
5385 (define_split
5386 [(match_operand 0 "some_small_symbolic_operand" "")]
5387 ""
5388 [(match_dup 0)]
5389 "operands[0] = split_small_symbolic_operand (operands[0]);")
5391 ;; Accepts any symbolic, not just global, since function calls that
5392 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5393 (define_insn "movdi_er_high_g"
5394 [(set (match_operand:DI 0 "register_operand" "=r")
5395 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5396 (match_operand:DI 2 "symbolic_operand" "")
5397 (match_operand 3 "const_int_operand" "")]
5398 UNSPEC_LITERAL))]
5399 "TARGET_EXPLICIT_RELOCS"
5400 {
5401 if (INTVAL (operands[3]) == 0)
5402 return "ldq %0,%2(%1)\t\t!literal";
5403 else
5404 return "ldq %0,%2(%1)\t\t!literal!%3";
5405 }
5406 [(set_attr "type" "ldsym")])
5408 (define_split
5409 [(set (match_operand:DI 0 "register_operand" "")
5410 (match_operand:DI 1 "global_symbolic_operand" ""))]
5411 "TARGET_EXPLICIT_RELOCS && reload_completed"
5412 [(set (match_dup 0)
5413 (unspec:DI [(match_dup 2)
5414 (match_dup 1)
5415 (const_int 0)] UNSPEC_LITERAL))]
5416 "operands[2] = pic_offset_table_rtx;")
5418 (define_insn "movdi_er_tlsgd"
5419 [(set (match_operand:DI 0 "register_operand" "=r")
5420 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5421 (match_operand:DI 2 "symbolic_operand" "")
5422 (match_operand 3 "const_int_operand" "")]
5423 UNSPEC_TLSGD))]
5424 "HAVE_AS_TLS"
5425 {
5426 if (INTVAL (operands[3]) == 0)
5427 return "lda %0,%2(%1)\t\t!tlsgd";
5428 else
5429 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5430 })
5432 (define_insn "movdi_er_tlsldm"
5433 [(set (match_operand:DI 0 "register_operand" "=r")
5434 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5435 (match_operand 2 "const_int_operand" "")]
5436 UNSPEC_TLSLDM))]
5437 "HAVE_AS_TLS"
5438 {
5439 if (INTVAL (operands[2]) == 0)
5440 return "lda %0,%&(%1)\t\t!tlsldm";
5441 else
5442 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5443 })
5445 (define_insn "*movdi_er_gotdtp"
5446 [(set (match_operand:DI 0 "register_operand" "=r")
5447 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5448 (match_operand:DI 2 "symbolic_operand" "")]
5449 UNSPEC_DTPREL))]
5450 "HAVE_AS_TLS"
5451 "ldq %0,%2(%1)\t\t!gotdtprel"
5452 [(set_attr "type" "ild")
5453 (set_attr "usegp" "yes")])
5455 (define_split
5456 [(set (match_operand:DI 0 "register_operand" "")
5457 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5458 "HAVE_AS_TLS && reload_completed"
5459 [(set (match_dup 0)
5460 (unspec:DI [(match_dup 2)
5461 (match_dup 1)] UNSPEC_DTPREL))]
5462 {
5463 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5464 operands[2] = pic_offset_table_rtx;
5465 })
5467 (define_insn "*movdi_er_gottp"
5468 [(set (match_operand:DI 0 "register_operand" "=r")
5469 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5470 (match_operand:DI 2 "symbolic_operand" "")]
5471 UNSPEC_TPREL))]
5472 "HAVE_AS_TLS"
5473 "ldq %0,%2(%1)\t\t!gottprel"
5474 [(set_attr "type" "ild")
5475 (set_attr "usegp" "yes")])
5477 (define_split
5478 [(set (match_operand:DI 0 "register_operand" "")
5479 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5480 "HAVE_AS_TLS && reload_completed"
5481 [(set (match_dup 0)
5482 (unspec:DI [(match_dup 2)
5483 (match_dup 1)] UNSPEC_TPREL))]
5484 {
5485 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5486 operands[2] = pic_offset_table_rtx;
5487 })
5489 (define_insn "*movdi_er_nofix"
5490 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5491 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5492 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5493 && (register_operand (operands[0], DImode)
5494 || reg_or_0_operand (operands[1], DImode))"
5495 "@
5496 mov %r1,%0
5497 lda %0,%1($31)
5498 ldah %0,%h1($31)
5499 #
5500 #
5501 #
5502 ldq%A1 %0,%1
5503 stq%A0 %r1,%0
5504 fmov %R1,%0
5505 ldt %0,%1
5506 stt %R1,%0"
5507 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5508 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5510 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5511 ;; have been split up by the rules above but we shouldn't reject the
5512 ;; possibility of them getting through.
5514 (define_insn "*movdi_nofix"
5515 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5516 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5517 "! TARGET_FIX
5518 && (register_operand (operands[0], DImode)
5519 || reg_or_0_operand (operands[1], DImode))"
5520 "@
5521 bis $31,%r1,%0
5522 lda %0,%1($31)
5523 ldah %0,%h1($31)
5524 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5525 lda %0,%1
5526 #
5527 ldq%A1 %0,%1
5528 stq%A0 %r1,%0
5529 cpys %R1,%R1,%0
5530 ldt %0,%1
5531 stt %R1,%0"
5532 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5533 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5535 (define_insn "*movdi_er_fix"
5536 [(set (match_operand:DI 0 "nonimmediate_operand"
5537 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5538 (match_operand:DI 1 "input_operand"
5539 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5540 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5541 && (register_operand (operands[0], DImode)
5542 || reg_or_0_operand (operands[1], DImode))"
5543 "@
5544 mov %r1,%0
5545 lda %0,%1($31)
5546 ldah %0,%h1($31)
5547 #
5548 #
5549 #
5550 ldq%A1 %0,%1
5551 stq%A0 %r1,%0
5552 fmov %R1,%0
5553 ldt %0,%1
5554 stt %R1,%0
5555 ftoit %1,%0
5556 itoft %1,%0"
5557 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5558 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5560 (define_insn "*movdi_fix"
5561 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5562 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5563 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5564 && (register_operand (operands[0], DImode)
5565 || reg_or_0_operand (operands[1], DImode))"
5566 "@
5567 bis $31,%r1,%0
5568 lda %0,%1($31)
5569 ldah %0,%h1($31)
5570 lda %0,%1
5571 #
5572 ldq%A1 %0,%1
5573 stq%A0 %r1,%0
5574 cpys %R1,%R1,%0
5575 ldt %0,%1
5576 stt %R1,%0
5577 ftoit %1,%0
5578 itoft %1,%0"
5579 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5581 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5582 ;; often appears dead to the life analysis code, at which point we
5583 ;; abort for emitting dead prologue instructions. Force this live.
5585 (define_insn "force_movdi"
5586 [(set (match_operand:DI 0 "register_operand" "=r")
5587 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5588 UNSPECV_FORCE_MOV))]
5589 ""
5590 "mov %1,%0"
5591 [(set_attr "type" "ilog")])
5593 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5594 ;; memory, and construct long 32-bit constants.
5596 (define_expand "movdi"
5597 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5598 (match_operand:DI 1 "general_operand" ""))]
5599 ""
5600 {
5601 if (alpha_expand_mov (DImode, operands))
5602 DONE;
5603 })
5605 ;; Split a load of a large constant into the appropriate two-insn
5606 ;; sequence.
5608 (define_split
5609 [(set (match_operand:DI 0 "register_operand" "")
5610 (match_operand:DI 1 "non_add_const_operand" ""))]
5611 ""
5612 [(const_int 0)]
5613 {
5614 if (alpha_split_const_mov (DImode, operands))
5615 DONE;
5616 else
5617 FAIL;
5618 })
5620 ;; These are the partial-word cases.
5621 ;;
5622 ;; First we have the code to load an aligned word. Operand 0 is the register
5623 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5624 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5625 ;; number of bits within the word that the value is. Operand 3 is an SImode
5626 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5627 ;; same register. It is allowed to conflict with operand 1 as well.
5629 (define_expand "aligned_loadqi"
5630 [(set (match_operand:SI 3 "register_operand" "")
5631 (match_operand:SI 1 "memory_operand" ""))
5632 (set (match_operand:DI 0 "register_operand" "")
5633 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5634 (const_int 8)
5635 (match_operand:DI 2 "const_int_operand" "")))]
5637 ""
5638 "")
5640 (define_expand "aligned_loadhi"
5641 [(set (match_operand:SI 3 "register_operand" "")
5642 (match_operand:SI 1 "memory_operand" ""))
5643 (set (match_operand:DI 0 "register_operand" "")
5644 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5645 (const_int 16)
5646 (match_operand:DI 2 "const_int_operand" "")))]
5648 ""
5649 "")
5651 ;; Similar for unaligned loads, where we use the sequence from the
5652 ;; Alpha Architecture manual. We have to distinguish between little-endian
5653 ;; and big-endian systems as the sequences are different.
5654 ;;
5655 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5656 ;; operand 3 can overlap the input and output registers.
5658 (define_expand "unaligned_loadqi"
5659 [(use (match_operand:DI 0 "register_operand" ""))
5660 (use (match_operand:DI 1 "address_operand" ""))
5661 (use (match_operand:DI 2 "register_operand" ""))
5662 (use (match_operand:DI 3 "register_operand" ""))]
5663 ""
5664 {
5665 if (WORDS_BIG_ENDIAN)
5666 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5667 operands[2], operands[3]));
5668 else
5669 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5670 operands[2], operands[3]));
5671 DONE;
5672 })
5674 (define_expand "unaligned_loadqi_le"
5675 [(set (match_operand:DI 2 "register_operand" "")
5676 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5677 (const_int -8))))
5678 (set (match_operand:DI 3 "register_operand" "")
5679 (match_dup 1))
5680 (set (match_operand:DI 0 "register_operand" "")
5681 (zero_extract:DI (match_dup 2)
5682 (const_int 8)
5683 (ashift:DI (match_dup 3) (const_int 3))))]
5684 "! WORDS_BIG_ENDIAN"
5685 "")
5687 (define_expand "unaligned_loadqi_be"
5688 [(set (match_operand:DI 2 "register_operand" "")
5689 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5690 (const_int -8))))
5691 (set (match_operand:DI 3 "register_operand" "")
5692 (match_dup 1))
5693 (set (match_operand:DI 0 "register_operand" "")
5694 (zero_extract:DI (match_dup 2)
5695 (const_int 8)
5696 (minus:DI
5697 (const_int 56)
5698 (ashift:DI (match_dup 3) (const_int 3)))))]
5699 "WORDS_BIG_ENDIAN"
5700 "")
5702 (define_expand "unaligned_loadhi"
5703 [(use (match_operand:DI 0 "register_operand" ""))
5704 (use (match_operand:DI 1 "address_operand" ""))
5705 (use (match_operand:DI 2 "register_operand" ""))
5706 (use (match_operand:DI 3 "register_operand" ""))]
5707 ""
5708 {
5709 if (WORDS_BIG_ENDIAN)
5710 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5711 operands[2], operands[3]));
5712 else
5713 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5714 operands[2], operands[3]));
5715 DONE;
5716 })
5718 (define_expand "unaligned_loadhi_le"
5719 [(set (match_operand:DI 2 "register_operand" "")
5720 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5721 (const_int -8))))
5722 (set (match_operand:DI 3 "register_operand" "")
5723 (match_dup 1))
5724 (set (match_operand:DI 0 "register_operand" "")
5725 (zero_extract:DI (match_dup 2)
5726 (const_int 16)
5727 (ashift:DI (match_dup 3) (const_int 3))))]
5728 "! WORDS_BIG_ENDIAN"
5729 "")
5731 (define_expand "unaligned_loadhi_be"
5732 [(set (match_operand:DI 2 "register_operand" "")
5733 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5734 (const_int -8))))
5735 (set (match_operand:DI 3 "register_operand" "")
5736 (plus:DI (match_dup 1) (const_int 1)))
5737 (set (match_operand:DI 0 "register_operand" "")
5738 (zero_extract:DI (match_dup 2)
5739 (const_int 16)
5740 (minus:DI
5741 (const_int 56)
5742 (ashift:DI (match_dup 3) (const_int 3)))))]
5743 "WORDS_BIG_ENDIAN"
5744 "")
5746 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5747 ;; aligned SImode MEM. Operand 1 is the register containing the
5748 ;; byte or word to store. Operand 2 is the number of bits within the word that
5749 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5751 (define_expand "aligned_store"
5752 [(set (match_operand:SI 3 "register_operand" "")
5753 (match_operand:SI 0 "memory_operand" ""))
5754 (set (subreg:DI (match_dup 3) 0)
5755 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5756 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5757 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5758 (match_operand:DI 2 "const_int_operand" "")))
5759 (set (subreg:DI (match_dup 4) 0)
5760 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5761 (set (match_dup 0) (match_dup 4))]
5762 ""
5763 {
5764 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5765 << INTVAL (operands[2])));
5766 })
5768 ;; For the unaligned byte and halfword cases, we use code similar to that
5769 ;; in the ;; Architecture book, but reordered to lower the number of registers
5770 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5771 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5772 ;; be the same temporary, if desired. If the address is in a register,
5773 ;; operand 2 can be that register.
5775 (define_expand "unaligned_storeqi"
5776 [(use (match_operand:DI 0 "address_operand" ""))
5777 (use (match_operand:QI 1 "register_operand" ""))
5778 (use (match_operand:DI 2 "register_operand" ""))
5779 (use (match_operand:DI 3 "register_operand" ""))
5780 (use (match_operand:DI 4 "register_operand" ""))]
5781 ""
5782 {
5783 if (WORDS_BIG_ENDIAN)
5784 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5785 operands[2], operands[3],
5786 operands[4]));
5787 else
5788 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5789 operands[2], operands[3],
5790 operands[4]));
5791 DONE;
5792 })
5794 (define_expand "unaligned_storeqi_le"
5795 [(set (match_operand:DI 3 "register_operand" "")
5796 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5797 (const_int -8))))
5798 (set (match_operand:DI 2 "register_operand" "")
5799 (match_dup 0))
5800 (set (match_dup 3)
5801 (and:DI (not:DI (ashift:DI (const_int 255)
5802 (ashift:DI (match_dup 2) (const_int 3))))
5803 (match_dup 3)))
5804 (set (match_operand:DI 4 "register_operand" "")
5805 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5806 (ashift:DI (match_dup 2) (const_int 3))))
5807 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5808 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5809 (match_dup 4))]
5810 "! WORDS_BIG_ENDIAN"
5811 "")
5813 (define_expand "unaligned_storeqi_be"
5814 [(set (match_operand:DI 3 "register_operand" "")
5815 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5816 (const_int -8))))
5817 (set (match_operand:DI 2 "register_operand" "")
5818 (match_dup 0))
5819 (set (match_dup 3)
5820 (and:DI (not:DI (ashift:DI (const_int 255)
5821 (minus:DI (const_int 56)
5822 (ashift:DI (match_dup 2) (const_int 3)))))
5823 (match_dup 3)))
5824 (set (match_operand:DI 4 "register_operand" "")
5825 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5826 (minus:DI (const_int 56)
5827 (ashift:DI (match_dup 2) (const_int 3)))))
5828 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5829 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5830 (match_dup 4))]
5831 "WORDS_BIG_ENDIAN"
5832 "")
5834 (define_expand "unaligned_storehi"
5835 [(use (match_operand:DI 0 "address_operand" ""))
5836 (use (match_operand:HI 1 "register_operand" ""))
5837 (use (match_operand:DI 2 "register_operand" ""))
5838 (use (match_operand:DI 3 "register_operand" ""))
5839 (use (match_operand:DI 4 "register_operand" ""))]
5840 ""
5841 {
5842 if (WORDS_BIG_ENDIAN)
5843 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5844 operands[2], operands[3],
5845 operands[4]));
5846 else
5847 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5848 operands[2], operands[3],
5849 operands[4]));
5850 DONE;
5851 })
5853 (define_expand "unaligned_storehi_le"
5854 [(set (match_operand:DI 3 "register_operand" "")
5855 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5856 (const_int -8))))
5857 (set (match_operand:DI 2 "register_operand" "")
5858 (match_dup 0))
5859 (set (match_dup 3)
5860 (and:DI (not:DI (ashift:DI (const_int 65535)
5861 (ashift:DI (match_dup 2) (const_int 3))))
5862 (match_dup 3)))
5863 (set (match_operand:DI 4 "register_operand" "")
5864 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5865 (ashift:DI (match_dup 2) (const_int 3))))
5866 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5867 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5868 (match_dup 4))]
5869 "! WORDS_BIG_ENDIAN"
5870 "")
5872 (define_expand "unaligned_storehi_be"
5873 [(set (match_operand:DI 3 "register_operand" "")
5874 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5875 (const_int -8))))
5876 (set (match_operand:DI 2 "register_operand" "")
5877 (plus:DI (match_dup 0) (const_int 1)))
5878 (set (match_dup 3)
5879 (and:DI (not:DI (ashift:DI
5880 (const_int 65535)
5881 (minus:DI (const_int 56)
5882 (ashift:DI (match_dup 2) (const_int 3)))))
5883 (match_dup 3)))
5884 (set (match_operand:DI 4 "register_operand" "")
5885 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5886 (minus:DI (const_int 56)
5887 (ashift:DI (match_dup 2) (const_int 3)))))
5888 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5889 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5890 (match_dup 4))]
5891 "WORDS_BIG_ENDIAN"
5892 "")
5893 \f
5894 ;; Here are the define_expand's for QI and HI moves that use the above
5895 ;; patterns. We have the normal sets, plus the ones that need scratch
5896 ;; registers for reload.
5898 (define_expand "movqi"
5899 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5900 (match_operand:QI 1 "general_operand" ""))]
5901 ""
5902 {
5903 if (TARGET_BWX
5904 ? alpha_expand_mov (QImode, operands)
5905 : alpha_expand_mov_nobwx (QImode, operands))
5906 DONE;
5907 })
5909 (define_expand "movhi"
5910 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5911 (match_operand:HI 1 "general_operand" ""))]
5912 ""
5913 {
5914 if (TARGET_BWX
5915 ? alpha_expand_mov (HImode, operands)
5916 : alpha_expand_mov_nobwx (HImode, operands))
5917 DONE;
5918 })
5920 ;; Here are the versions for reload. Note that in the unaligned cases
5921 ;; we know that the operand must not be a pseudo-register because stack
5922 ;; slots are always aligned references.
5924 (define_expand "reload_inqi"
5925 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5926 (match_operand:QI 1 "any_memory_operand" "m")
5927 (match_operand:TI 2 "register_operand" "=&r")])]
5928 "! TARGET_BWX"
5929 {
5930 rtx scratch, seq;
5932 if (aligned_memory_operand (operands[1], QImode))
5933 {
5934 seq = gen_reload_inqi_help (operands[0], operands[1],
5935 gen_rtx_REG (SImode, REGNO (operands[2])));
5936 }
5937 else
5938 {
5939 rtx addr;
5941 /* It is possible that one of the registers we got for operands[2]
5942 might coincide with that of operands[0] (which is why we made
5943 it TImode). Pick the other one to use as our scratch. */
5944 if (REGNO (operands[0]) == REGNO (operands[2]))
5945 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5946 else
5947 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5949 addr = get_unaligned_address (operands[1], 0);
5950 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5951 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
5952 alpha_set_memflags (seq, operands[1]);
5953 }
5954 emit_insn (seq);
5955 DONE;
5956 })
5958 (define_expand "reload_inhi"
5959 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5960 (match_operand:HI 1 "any_memory_operand" "m")
5961 (match_operand:TI 2 "register_operand" "=&r")])]
5962 "! TARGET_BWX"
5963 {
5964 rtx scratch, seq;
5966 if (aligned_memory_operand (operands[1], HImode))
5967 {
5968 seq = gen_reload_inhi_help (operands[0], operands[1],
5969 gen_rtx_REG (SImode, REGNO (operands[2])));
5970 }
5971 else
5972 {
5973 rtx addr;
5975 /* It is possible that one of the registers we got for operands[2]
5976 might coincide with that of operands[0] (which is why we made
5977 it TImode). Pick the other one to use as our scratch. */
5978 if (REGNO (operands[0]) == REGNO (operands[2]))
5979 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5980 else
5981 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5983 addr = get_unaligned_address (operands[1], 0);
5984 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5985 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
5986 alpha_set_memflags (seq, operands[1]);
5987 }
5988 emit_insn (seq);
5989 DONE;
5990 })
5992 (define_expand "reload_outqi"
5993 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5994 (match_operand:QI 1 "register_operand" "r")
5995 (match_operand:TI 2 "register_operand" "=&r")])]
5996 "! TARGET_BWX"
5997 {
5998 if (aligned_memory_operand (operands[0], QImode))
5999 {
6000 emit_insn (gen_reload_outqi_help
6001 (operands[0], operands[1],
6002 gen_rtx_REG (SImode, REGNO (operands[2])),
6003 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6004 }
6005 else
6006 {
6007 rtx addr = get_unaligned_address (operands[0], 0);
6008 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6009 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6010 rtx scratch3 = scratch1;
6011 rtx seq;
6013 if (GET_CODE (addr) == REG)
6014 scratch1 = addr;
6016 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6017 scratch2, scratch3);
6018 alpha_set_memflags (seq, operands[0]);
6019 emit_insn (seq);
6020 }
6021 DONE;
6022 })
6024 (define_expand "reload_outhi"
6025 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6026 (match_operand:HI 1 "register_operand" "r")
6027 (match_operand:TI 2 "register_operand" "=&r")])]
6028 "! TARGET_BWX"
6029 {
6030 if (aligned_memory_operand (operands[0], HImode))
6031 {
6032 emit_insn (gen_reload_outhi_help
6033 (operands[0], operands[1],
6034 gen_rtx_REG (SImode, REGNO (operands[2])),
6035 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6036 }
6037 else
6038 {
6039 rtx addr = get_unaligned_address (operands[0], 0);
6040 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6041 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6042 rtx scratch3 = scratch1;
6043 rtx seq;
6045 if (GET_CODE (addr) == REG)
6046 scratch1 = addr;
6048 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6049 scratch2, scratch3);
6050 alpha_set_memflags (seq, operands[0]);
6051 emit_insn (seq);
6052 }
6053 DONE;
6054 })
6056 ;; Helpers for the above. The way reload is structured, we can't
6057 ;; always get a proper address for a stack slot during reload_foo
6058 ;; expansion, so we must delay our address manipulations until after.
6060 (define_insn_and_split "reload_inqi_help"
6061 [(set (match_operand:QI 0 "register_operand" "=r")
6062 (match_operand:QI 1 "memory_operand" "m"))
6063 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6064 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6065 "#"
6066 "! TARGET_BWX && reload_completed"
6067 [(const_int 0)]
6068 {
6069 rtx aligned_mem, bitnum;
6070 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6071 operands[0] = gen_lowpart (DImode, operands[0]);
6072 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6073 operands[2]));
6074 DONE;
6075 })
6077 (define_insn_and_split "reload_inhi_help"
6078 [(set (match_operand:HI 0 "register_operand" "=r")
6079 (match_operand:HI 1 "memory_operand" "m"))
6080 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6081 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6082 "#"
6083 "! TARGET_BWX && reload_completed"
6084 [(const_int 0)]
6085 {
6086 rtx aligned_mem, bitnum;
6087 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6088 operands[0] = gen_lowpart (DImode, operands[0]);
6089 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6090 operands[2]));
6091 DONE;
6092 })
6094 (define_insn_and_split "reload_outqi_help"
6095 [(set (match_operand:QI 0 "memory_operand" "=m")
6096 (match_operand:QI 1 "register_operand" "r"))
6097 (clobber (match_operand:SI 2 "register_operand" "=r"))
6098 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6099 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6100 "#"
6101 "! TARGET_BWX && reload_completed"
6102 [(const_int 0)]
6103 {
6104 rtx aligned_mem, bitnum;
6105 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6106 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6107 operands[2], operands[3]));
6108 DONE;
6109 })
6111 (define_insn_and_split "reload_outhi_help"
6112 [(set (match_operand:HI 0 "memory_operand" "=m")
6113 (match_operand:HI 1 "register_operand" "r"))
6114 (clobber (match_operand:SI 2 "register_operand" "=r"))
6115 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6116 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6117 "#"
6118 "! TARGET_BWX && reload_completed"
6119 [(const_int 0)]
6120 {
6121 rtx aligned_mem, bitnum;
6122 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6123 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6124 operands[2], operands[3]));
6125 DONE;
6126 })
6127 \f
6128 ;; Vector operations
6130 (define_mode_macro VEC [V8QI V4HI V2SI])
6132 (define_expand "mov<mode>"
6133 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6134 (match_operand:VEC 1 "general_operand" ""))]
6135 ""
6136 {
6137 if (alpha_expand_mov (<MODE>mode, operands))
6138 DONE;
6139 })
6141 (define_split
6142 [(set (match_operand:VEC 0 "register_operand" "")
6143 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6144 ""
6145 [(const_int 0)]
6146 {
6147 if (alpha_split_const_mov (<MODE>mode, operands))
6148 DONE;
6149 else
6150 FAIL;
6151 })
6154 (define_expand "movmisalign<mode>"
6155 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6156 (match_operand:VEC 1 "general_operand" ""))]
6157 ""
6158 {
6159 alpha_expand_movmisalign (<MODE>mode, operands);
6160 DONE;
6161 })
6163 (define_insn "*mov<mode>_fix"
6164 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6165 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6166 "TARGET_FIX
6167 && (register_operand (operands[0], <MODE>mode)
6168 || reg_or_0_operand (operands[1], <MODE>mode))"
6169 "@
6170 bis $31,%r1,%0
6171 #
6172 ldq %0,%1
6173 stq %r1,%0
6174 cpys %R1,%R1,%0
6175 ldt %0,%1
6176 stt %R1,%0
6177 ftoit %1,%0
6178 itoft %1,%0"
6179 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6181 (define_insn "*mov<mode>_nofix"
6182 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6183 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6184 "! TARGET_FIX
6185 && (register_operand (operands[0], <MODE>mode)
6186 || reg_or_0_operand (operands[1], <MODE>mode))"
6187 "@
6188 bis $31,%r1,%0
6189 #
6190 ldq %0,%1
6191 stq %r1,%0
6192 cpys %R1,%R1,%0
6193 ldt %0,%1
6194 stt %R1,%0"
6195 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6197 (define_insn "uminv8qi3"
6198 [(set (match_operand:V8QI 0 "register_operand" "=r")
6199 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6200 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6201 "TARGET_MAX"
6202 "minub8 %r1,%r2,%0"
6203 [(set_attr "type" "mvi")])
6205 (define_insn "sminv8qi3"
6206 [(set (match_operand:V8QI 0 "register_operand" "=r")
6207 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6208 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6209 "TARGET_MAX"
6210 "minsb8 %r1,%r2,%0"
6211 [(set_attr "type" "mvi")])
6213 (define_insn "uminv4hi3"
6214 [(set (match_operand:V4HI 0 "register_operand" "=r")
6215 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6216 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6217 "TARGET_MAX"
6218 "minuw4 %r1,%r2,%0"
6219 [(set_attr "type" "mvi")])
6221 (define_insn "sminv4hi3"
6222 [(set (match_operand:V4HI 0 "register_operand" "=r")
6223 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6224 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6225 "TARGET_MAX"
6226 "minsw4 %r1,%r2,%0"
6227 [(set_attr "type" "mvi")])
6229 (define_insn "umaxv8qi3"
6230 [(set (match_operand:V8QI 0 "register_operand" "=r")
6231 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6232 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6233 "TARGET_MAX"
6234 "maxub8 %r1,%r2,%0"
6235 [(set_attr "type" "mvi")])
6237 (define_insn "smaxv8qi3"
6238 [(set (match_operand:V8QI 0 "register_operand" "=r")
6239 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6240 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6241 "TARGET_MAX"
6242 "maxsb8 %r1,%r2,%0"
6243 [(set_attr "type" "mvi")])
6245 (define_insn "umaxv4hi3"
6246 [(set (match_operand:V4HI 0 "register_operand" "=r")
6247 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6248 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6249 "TARGET_MAX"
6250 "maxuw4 %r1,%r2,%0"
6251 [(set_attr "type" "mvi")])
6253 (define_insn "smaxv4hi3"
6254 [(set (match_operand:V4HI 0 "register_operand" "=r")
6255 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6256 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6257 "TARGET_MAX"
6258 "maxsw4 %r1,%r2,%0"
6259 [(set_attr "type" "mvi")])
6261 (define_insn "one_cmpl<mode>2"
6262 [(set (match_operand:VEC 0 "register_operand" "=r")
6263 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6264 ""
6265 "ornot $31,%1,%0"
6266 [(set_attr "type" "ilog")])
6268 (define_insn "and<mode>3"
6269 [(set (match_operand:VEC 0 "register_operand" "=r")
6270 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6271 (match_operand:VEC 2 "register_operand" "r")))]
6272 ""
6273 "and %1,%2,%0"
6274 [(set_attr "type" "ilog")])
6276 (define_insn "*andnot<mode>3"
6277 [(set (match_operand:VEC 0 "register_operand" "=r")
6278 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6279 (match_operand:VEC 2 "register_operand" "r")))]
6280 ""
6281 "bic %2,%1,%0"
6282 [(set_attr "type" "ilog")])
6284 (define_insn "ior<mode>3"
6285 [(set (match_operand:VEC 0 "register_operand" "=r")
6286 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6287 (match_operand:VEC 2 "register_operand" "r")))]
6288 ""
6289 "bis %1,%2,%0"
6290 [(set_attr "type" "ilog")])
6292 (define_insn "*iornot<mode>3"
6293 [(set (match_operand:VEC 0 "register_operand" "=r")
6294 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6295 (match_operand:VEC 2 "register_operand" "r")))]
6296 ""
6297 "ornot %2,%1,%0"
6298 [(set_attr "type" "ilog")])
6300 (define_insn "xor<mode>3"
6301 [(set (match_operand:VEC 0 "register_operand" "=r")
6302 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6303 (match_operand:VEC 2 "register_operand" "r")))]
6304 ""
6305 "xor %1,%2,%0"
6306 [(set_attr "type" "ilog")])
6308 (define_insn "*xornot<mode>3"
6309 [(set (match_operand:VEC 0 "register_operand" "=r")
6310 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6311 (match_operand:VEC 2 "register_operand" "r"))))]
6312 ""
6313 "eqv %1,%2,%0"
6314 [(set_attr "type" "ilog")])
6315 \f
6316 ;; Bit field extract patterns which use ext[wlq][lh]
6318 (define_expand "extv"
6319 [(set (match_operand:DI 0 "register_operand" "")
6320 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6321 (match_operand:DI 2 "immediate_operand" "")
6322 (match_operand:DI 3 "immediate_operand" "")))]
6323 ""
6324 {
6325 int ofs;
6327 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6328 if (INTVAL (operands[3]) % 8 != 0
6329 || (INTVAL (operands[2]) != 16
6330 && INTVAL (operands[2]) != 32
6331 && INTVAL (operands[2]) != 64))
6332 FAIL;
6334 /* From mips.md: extract_bit_field doesn't verify that our source
6335 matches the predicate, so we force it to be a MEM here. */
6336 if (GET_CODE (operands[1]) != MEM)
6337 FAIL;
6339 /* The bit number is relative to the mode of operand 1 which is
6340 usually QImode (this might actually be a bug in expmed.c). Note
6341 that the bit number is negative in big-endian mode in this case.
6342 We have to convert that to the offset. */
6343 if (WORDS_BIG_ENDIAN)
6344 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6345 - INTVAL (operands[2]) - INTVAL (operands[3]);
6346 else
6347 ofs = INTVAL (operands[3]);
6349 ofs = ofs / 8;
6351 alpha_expand_unaligned_load (operands[0], operands[1],
6352 INTVAL (operands[2]) / 8,
6353 ofs, 1);
6354 DONE;
6355 })
6357 (define_expand "extzv"
6358 [(set (match_operand:DI 0 "register_operand" "")
6359 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6360 (match_operand:DI 2 "immediate_operand" "")
6361 (match_operand:DI 3 "immediate_operand" "")))]
6362 ""
6363 {
6364 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6365 if (INTVAL (operands[3]) % 8 != 0
6366 || (INTVAL (operands[2]) != 8
6367 && INTVAL (operands[2]) != 16
6368 && INTVAL (operands[2]) != 32
6369 && INTVAL (operands[2]) != 64))
6370 FAIL;
6372 if (GET_CODE (operands[1]) == MEM)
6373 {
6374 int ofs;
6376 /* Fail 8 bit fields, falling back on a simple byte load. */
6377 if (INTVAL (operands[2]) == 8)
6378 FAIL;
6380 /* The bit number is relative to the mode of operand 1 which is
6381 usually QImode (this might actually be a bug in expmed.c). Note
6382 that the bit number is negative in big-endian mode in this case.
6383 We have to convert that to the offset. */
6384 if (WORDS_BIG_ENDIAN)
6385 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6386 - INTVAL (operands[2]) - INTVAL (operands[3]);
6387 else
6388 ofs = INTVAL (operands[3]);
6390 ofs = ofs / 8;
6392 alpha_expand_unaligned_load (operands[0], operands[1],
6393 INTVAL (operands[2]) / 8,
6394 ofs, 0);
6395 DONE;
6396 }
6397 })
6399 (define_expand "insv"
6400 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6401 (match_operand:DI 1 "immediate_operand" "")
6402 (match_operand:DI 2 "immediate_operand" ""))
6403 (match_operand:DI 3 "register_operand" ""))]
6404 ""
6405 {
6406 int ofs;
6408 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6409 if (INTVAL (operands[2]) % 8 != 0
6410 || (INTVAL (operands[1]) != 16
6411 && INTVAL (operands[1]) != 32
6412 && INTVAL (operands[1]) != 64))
6413 FAIL;
6415 /* From mips.md: store_bit_field doesn't verify that our source
6416 matches the predicate, so we force it to be a MEM here. */
6417 if (GET_CODE (operands[0]) != MEM)
6418 FAIL;
6420 /* The bit number is relative to the mode of operand 1 which is
6421 usually QImode (this might actually be a bug in expmed.c). Note
6422 that the bit number is negative in big-endian mode in this case.
6423 We have to convert that to the offset. */
6424 if (WORDS_BIG_ENDIAN)
6425 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6426 - INTVAL (operands[1]) - INTVAL (operands[2]);
6427 else
6428 ofs = INTVAL (operands[2]);
6430 ofs = ofs / 8;
6432 alpha_expand_unaligned_store (operands[0], operands[3],
6433 INTVAL (operands[1]) / 8, ofs);
6434 DONE;
6435 })
6437 ;; Block move/clear, see alpha.c for more details.
6438 ;; Argument 0 is the destination
6439 ;; Argument 1 is the source
6440 ;; Argument 2 is the length
6441 ;; Argument 3 is the alignment
6443 (define_expand "movmemqi"
6444 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6445 (match_operand:BLK 1 "memory_operand" ""))
6446 (use (match_operand:DI 2 "immediate_operand" ""))
6447 (use (match_operand:DI 3 "immediate_operand" ""))])]
6448 ""
6449 {
6450 if (alpha_expand_block_move (operands))
6451 DONE;
6452 else
6453 FAIL;
6454 })
6456 (define_expand "movmemdi"
6457 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6458 (match_operand:BLK 1 "memory_operand" ""))
6459 (use (match_operand:DI 2 "immediate_operand" ""))
6460 (use (match_operand:DI 3 "immediate_operand" ""))
6461 (use (match_dup 4))
6462 (clobber (reg:DI 25))
6463 (clobber (reg:DI 16))
6464 (clobber (reg:DI 17))
6465 (clobber (reg:DI 18))
6466 (clobber (reg:DI 19))
6467 (clobber (reg:DI 20))
6468 (clobber (reg:DI 26))
6469 (clobber (reg:DI 27))])]
6470 "TARGET_ABI_OPEN_VMS"
6471 {
6472 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6473 alpha_need_linkage (XSTR (operands[4], 0), 0);
6474 })
6476 (define_insn "*movmemdi_1"
6477 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6478 (match_operand:BLK 1 "memory_operand" "m,m"))
6479 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6480 (use (match_operand:DI 3 "immediate_operand" ""))
6481 (use (match_operand:DI 4 "call_operand" "i,i"))
6482 (clobber (reg:DI 25))
6483 (clobber (reg:DI 16))
6484 (clobber (reg:DI 17))
6485 (clobber (reg:DI 18))
6486 (clobber (reg:DI 19))
6487 (clobber (reg:DI 20))
6488 (clobber (reg:DI 26))
6489 (clobber (reg:DI 27))]
6490 "TARGET_ABI_OPEN_VMS"
6491 {
6492 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6493 switch (which_alternative)
6494 {
6495 case 0:
6496 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6497 case 1:
6498 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6499 default:
6500 abort();
6501 }
6502 }
6503 [(set_attr "type" "multi")
6504 (set_attr "length" "28")])
6506 (define_expand "clrmemqi"
6507 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6508 (const_int 0))
6509 (use (match_operand:DI 1 "immediate_operand" ""))
6510 (use (match_operand:DI 2 "immediate_operand" ""))])]
6511 ""
6512 {
6513 if (alpha_expand_block_clear (operands))
6514 DONE;
6515 else
6516 FAIL;
6517 })
6519 (define_expand "clrmemdi"
6520 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6521 (const_int 0))
6522 (use (match_operand:DI 1 "immediate_operand" ""))
6523 (use (match_operand:DI 2 "immediate_operand" ""))
6524 (use (match_dup 3))
6525 (clobber (reg:DI 25))
6526 (clobber (reg:DI 16))
6527 (clobber (reg:DI 17))
6528 (clobber (reg:DI 26))
6529 (clobber (reg:DI 27))])]
6530 "TARGET_ABI_OPEN_VMS"
6531 {
6532 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6533 alpha_need_linkage (XSTR (operands[3], 0), 0);
6534 })
6536 (define_insn "*clrmemdi_1"
6537 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6538 (const_int 0))
6539 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6540 (use (match_operand:DI 2 "immediate_operand" ""))
6541 (use (match_operand:DI 3 "call_operand" "i,i"))
6542 (clobber (reg:DI 25))
6543 (clobber (reg:DI 16))
6544 (clobber (reg:DI 17))
6545 (clobber (reg:DI 26))
6546 (clobber (reg:DI 27))]
6547 "TARGET_ABI_OPEN_VMS"
6548 {
6549 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6550 switch (which_alternative)
6551 {
6552 case 0:
6553 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6554 case 1:
6555 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6556 default:
6557 abort();
6558 }
6559 }
6560 [(set_attr "type" "multi")
6561 (set_attr "length" "24")])
6563 \f
6564 ;; Subroutine of stack space allocation. Perform a stack probe.
6565 (define_expand "probe_stack"
6566 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6567 ""
6568 {
6569 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6570 INTVAL (operands[0])));
6571 MEM_VOLATILE_P (operands[1]) = 1;
6573 operands[0] = const0_rtx;
6574 })
6576 ;; This is how we allocate stack space. If we are allocating a
6577 ;; constant amount of space and we know it is less than 4096
6578 ;; bytes, we need do nothing.
6579 ;;
6580 ;; If it is more than 4096 bytes, we need to probe the stack
6581 ;; periodically.
6582 (define_expand "allocate_stack"
6583 [(set (reg:DI 30)
6584 (plus:DI (reg:DI 30)
6585 (match_operand:DI 1 "reg_or_cint_operand" "")))
6586 (set (match_operand:DI 0 "register_operand" "=r")
6587 (match_dup 2))]
6588 ""
6589 {
6590 if (GET_CODE (operands[1]) == CONST_INT
6591 && INTVAL (operands[1]) < 32768)
6592 {
6593 if (INTVAL (operands[1]) >= 4096)
6594 {
6595 /* We do this the same way as in the prologue and generate explicit
6596 probes. Then we update the stack by the constant. */
6598 int probed = 4096;
6600 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6601 while (probed + 8192 < INTVAL (operands[1]))
6602 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6604 if (probed + 4096 < INTVAL (operands[1]))
6605 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6606 }
6608 operands[1] = GEN_INT (- INTVAL (operands[1]));
6609 operands[2] = virtual_stack_dynamic_rtx;
6610 }
6611 else
6612 {
6613 rtx out_label = 0;
6614 rtx loop_label = gen_label_rtx ();
6615 rtx want = gen_reg_rtx (Pmode);
6616 rtx tmp = gen_reg_rtx (Pmode);
6617 rtx memref;
6619 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6620 force_reg (Pmode, operands[1])));
6621 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6623 if (GET_CODE (operands[1]) != CONST_INT)
6624 {
6625 out_label = gen_label_rtx ();
6626 emit_insn (gen_cmpdi (want, tmp));
6627 emit_jump_insn (gen_bgeu (out_label));
6628 }
6630 emit_label (loop_label);
6631 memref = gen_rtx_MEM (DImode, tmp);
6632 MEM_VOLATILE_P (memref) = 1;
6633 emit_move_insn (memref, const0_rtx);
6634 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6635 emit_insn (gen_cmpdi (tmp, want));
6636 emit_jump_insn (gen_bgtu (loop_label));
6638 memref = gen_rtx_MEM (DImode, want);
6639 MEM_VOLATILE_P (memref) = 1;
6640 emit_move_insn (memref, const0_rtx);
6642 if (out_label)
6643 emit_label (out_label);
6645 emit_move_insn (stack_pointer_rtx, want);
6646 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6647 DONE;
6648 }
6649 })
6651 ;; This is used by alpha_expand_prolog to do the same thing as above,
6652 ;; except we cannot at that time generate new basic blocks, so we hide
6653 ;; the loop in this one insn.
6655 (define_insn "prologue_stack_probe_loop"
6656 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6657 (match_operand:DI 1 "register_operand" "r")]
6658 UNSPECV_PSPL)]
6659 ""
6660 {
6661 operands[2] = gen_label_rtx ();
6662 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6663 CODE_LABEL_NUMBER (operands[2]));
6665 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6666 }
6667 [(set_attr "length" "16")
6668 (set_attr "type" "multi")])
6670 (define_expand "prologue"
6671 [(clobber (const_int 0))]
6672 ""
6673 {
6674 alpha_expand_prologue ();
6675 DONE;
6676 })
6678 ;; These take care of emitting the ldgp insn in the prologue. This will be
6679 ;; an lda/ldah pair and we want to align them properly. So we have two
6680 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6681 ;; and the second of which emits nothing. However, both are marked as type
6682 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6683 ;; with them.
6685 (define_expand "prologue_ldgp"
6686 [(set (match_dup 0)
6687 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6688 (set (match_dup 0)
6689 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6690 ""
6691 {
6692 operands[0] = pic_offset_table_rtx;
6693 operands[1] = gen_rtx_REG (Pmode, 27);
6694 operands[2] = (TARGET_EXPLICIT_RELOCS
6695 ? GEN_INT (alpha_next_sequence_number++)
6696 : const0_rtx);
6697 })
6699 (define_insn "*ldgp_er_1"
6700 [(set (match_operand:DI 0 "register_operand" "=r")
6701 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6702 (match_operand 2 "const_int_operand" "")]
6703 UNSPECV_LDGP1))]
6704 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6705 "ldah %0,0(%1)\t\t!gpdisp!%2"
6706 [(set_attr "cannot_copy" "true")])
6708 (define_insn "*ldgp_er_2"
6709 [(set (match_operand:DI 0 "register_operand" "=r")
6710 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6711 (match_operand 2 "const_int_operand" "")]
6712 UNSPEC_LDGP2))]
6713 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6714 "lda %0,0(%1)\t\t!gpdisp!%2"
6715 [(set_attr "cannot_copy" "true")])
6717 (define_insn "*prologue_ldgp_er_2"
6718 [(set (match_operand:DI 0 "register_operand" "=r")
6719 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6720 (match_operand 2 "const_int_operand" "")]
6721 UNSPECV_PLDGP2))]
6722 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6723 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6724 [(set_attr "cannot_copy" "true")])
6726 (define_insn "*prologue_ldgp_1"
6727 [(set (match_operand:DI 0 "register_operand" "=r")
6728 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6729 (match_operand 2 "const_int_operand" "")]
6730 UNSPECV_LDGP1))]
6731 ""
6732 "ldgp %0,0(%1)\n$%~..ng:"
6733 [(set_attr "cannot_copy" "true")])
6735 (define_insn "*prologue_ldgp_2"
6736 [(set (match_operand:DI 0 "register_operand" "=r")
6737 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6738 (match_operand 2 "const_int_operand" "")]
6739 UNSPECV_PLDGP2))]
6740 ""
6741 "")
6743 ;; The _mcount profiling hook has special calling conventions, and
6744 ;; does not clobber all the registers that a normal call would. So
6745 ;; hide the fact this is a call at all.
6747 (define_insn "prologue_mcount"
6748 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6749 ""
6750 {
6751 if (TARGET_EXPLICIT_RELOCS)
6752 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6753 cannot be called via the PLT. */
6754 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6755 else
6756 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6757 }
6758 [(set_attr "type" "multi")
6759 (set_attr "length" "8")])
6761 (define_insn "init_fp"
6762 [(set (match_operand:DI 0 "register_operand" "=r")
6763 (match_operand:DI 1 "register_operand" "r"))
6764 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6765 ""
6766 "bis $31,%1,%0")
6768 (define_expand "epilogue"
6769 [(return)]
6770 ""
6771 {
6772 alpha_expand_epilogue ();
6773 })
6775 (define_expand "sibcall_epilogue"
6776 [(return)]
6777 "TARGET_ABI_OSF"
6778 {
6779 alpha_expand_epilogue ();
6780 DONE;
6781 })
6783 (define_expand "builtin_longjmp"
6784 [(use (match_operand:DI 0 "register_operand" "r"))]
6785 "TARGET_ABI_OSF"
6786 {
6787 /* The elements of the buffer are, in order: */
6788 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6789 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6790 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6791 rtx pv = gen_rtx_REG (Pmode, 27);
6793 /* This bit is the same as expand_builtin_longjmp. */
6794 emit_move_insn (hard_frame_pointer_rtx, fp);
6795 emit_move_insn (pv, lab);
6796 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6797 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6798 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6800 /* Load the label we are jumping through into $27 so that we know
6801 where to look for it when we get back to setjmp's function for
6802 restoring the gp. */
6803 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6804 emit_barrier ();
6805 DONE;
6806 })
6808 ;; This is effectively a copy of indirect_jump, but constrained such
6809 ;; that register renaming cannot foil our cunning plan with $27.
6810 (define_insn "builtin_longjmp_internal"
6811 [(set (pc)
6812 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6813 UNSPECV_LONGJMP))]
6814 ""
6815 "jmp $31,(%0),0"
6816 [(set_attr "type" "ibr")])
6818 (define_expand "builtin_setjmp_receiver"
6819 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6820 "TARGET_ABI_OSF"
6821 "")
6823 (define_insn_and_split "*builtin_setjmp_receiver_1"
6824 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6825 "TARGET_ABI_OSF"
6826 {
6827 if (TARGET_EXPLICIT_RELOCS)
6828 return "#";
6829 else
6830 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6831 }
6832 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6833 [(set (match_dup 1)
6834 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6835 (set (match_dup 1)
6836 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6837 {
6838 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6839 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6840 UNSPECV_SETJMPR_ER));
6841 operands[1] = pic_offset_table_rtx;
6842 operands[2] = gen_rtx_REG (Pmode, 27);
6843 operands[3] = GEN_INT (alpha_next_sequence_number++);
6844 }
6845 [(set_attr "length" "12")
6846 (set_attr "type" "multi")])
6848 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6849 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6850 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6851 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6853 (define_insn "*builtin_setjmp_receiver_er_1"
6854 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6855 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
6856 "br $27,$LSJ%=\n$LSJ%=:"
6857 [(set_attr "type" "ibr")])
6859 (define_expand "exception_receiver"
6860 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6861 "TARGET_ABI_OSF"
6862 {
6863 if (TARGET_LD_BUGGY_LDGP)
6864 operands[0] = alpha_gp_save_rtx ();
6865 else
6866 operands[0] = const0_rtx;
6867 })
6869 (define_insn "*exception_receiver_2"
6870 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6871 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
6872 "ldq $29,%0"
6873 [(set_attr "type" "ild")])
6875 (define_insn_and_split "*exception_receiver_1"
6876 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6877 "TARGET_ABI_OSF"
6878 {
6879 if (TARGET_EXPLICIT_RELOCS)
6880 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
6881 else
6882 return "ldgp $29,0($26)";
6883 }
6884 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6885 [(set (match_dup 0)
6886 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6887 (set (match_dup 0)
6888 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6889 {
6890 operands[0] = pic_offset_table_rtx;
6891 operands[1] = gen_rtx_REG (Pmode, 26);
6892 operands[2] = GEN_INT (alpha_next_sequence_number++);
6893 }
6894 [(set_attr "length" "8")
6895 (set_attr "type" "multi")])
6897 (define_expand "nonlocal_goto_receiver"
6898 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6899 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6900 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6901 (use (reg:DI 27))]
6902 "TARGET_ABI_OPEN_VMS"
6903 "")
6905 (define_insn "arg_home"
6906 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6907 (use (reg:DI 1))
6908 (use (reg:DI 25))
6909 (use (reg:DI 16))
6910 (use (reg:DI 17))
6911 (use (reg:DI 18))
6912 (use (reg:DI 19))
6913 (use (reg:DI 20))
6914 (use (reg:DI 21))
6915 (use (reg:DI 48))
6916 (use (reg:DI 49))
6917 (use (reg:DI 50))
6918 (use (reg:DI 51))
6919 (use (reg:DI 52))
6920 (use (reg:DI 53))
6921 (clobber (mem:BLK (const_int 0)))
6922 (clobber (reg:DI 24))
6923 (clobber (reg:DI 25))
6924 (clobber (reg:DI 0))]
6925 "TARGET_ABI_OPEN_VMS"
6926 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6927 [(set_attr "length" "16")
6928 (set_attr "type" "multi")])
6930 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6932 (define_expand "umk_mismatch_args"
6933 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6934 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6935 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6936 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6937 (const_int 8))
6938 (match_dup 2)))
6939 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6940 "TARGET_ABI_UNICOSMK"
6941 {
6942 operands[1] = gen_reg_rtx (DImode);
6943 operands[2] = gen_reg_rtx (DImode);
6944 operands[3] = gen_reg_rtx (DImode);
6945 })
6947 (define_insn "arg_home_umk"
6948 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6949 (use (reg:DI 1))
6950 (use (reg:DI 2))
6951 (use (reg:DI 16))
6952 (use (reg:DI 17))
6953 (use (reg:DI 18))
6954 (use (reg:DI 19))
6955 (use (reg:DI 20))
6956 (use (reg:DI 21))
6957 (use (reg:DI 48))
6958 (use (reg:DI 49))
6959 (use (reg:DI 50))
6960 (use (reg:DI 51))
6961 (use (reg:DI 52))
6962 (use (reg:DI 53))
6963 (clobber (mem:BLK (const_int 0)))
6964 (parallel [
6965 (clobber (reg:DI 22))
6966 (clobber (reg:DI 23))
6967 (clobber (reg:DI 24))
6968 (clobber (reg:DI 0))
6969 (clobber (reg:DI 1))
6970 (clobber (reg:DI 2))
6971 (clobber (reg:DI 3))
6972 (clobber (reg:DI 4))
6973 (clobber (reg:DI 5))
6974 (clobber (reg:DI 6))
6975 (clobber (reg:DI 7))
6976 (clobber (reg:DI 8))])]
6977 "TARGET_ABI_UNICOSMK"
6978 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6979 [(set_attr "length" "16")
6980 (set_attr "type" "multi")])
6982 ;; Prefetch data.
6983 ;;
6984 ;; On EV4, these instructions are nops -- no load occurs.
6985 ;;
6986 ;; On EV5, these instructions act as a normal load, and thus can trap
6987 ;; if the address is invalid. The OS may (or may not) handle this in
6988 ;; the entMM fault handler and suppress the fault. If so, then this
6989 ;; has the effect of a read prefetch instruction.
6990 ;;
6991 ;; On EV6, these become official prefetch instructions.
6993 (define_insn "prefetch"
6994 [(prefetch (match_operand:DI 0 "address_operand" "p")
6995 (match_operand:DI 1 "const_int_operand" "n")
6996 (match_operand:DI 2 "const_int_operand" "n"))]
6997 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6998 {
6999 /* Interpret "no temporal locality" as this data should be evicted once
7000 it is used. The "evict next" alternatives load the data into the cache
7001 and leave the LRU eviction counter pointing to that block. */
7002 static const char * const alt[2][2] = {
7003 {
7004 "ldq $31,%a0", /* read, evict next */
7005 "ldl $31,%a0", /* read, evict last */
7006 },
7007 {
7008 "ldt $f31,%a0", /* write, evict next */
7009 "lds $f31,%a0", /* write, evict last */
7010 }
7011 };
7013 bool write = INTVAL (operands[1]) != 0;
7014 bool lru = INTVAL (operands[2]) != 0;
7016 return alt[write][lru];
7017 }
7018 [(set_attr "type" "ild")])
7020 ;; Close the trap shadow of preceding instructions. This is generated
7021 ;; by alpha_reorg.
7023 (define_insn "trapb"
7024 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7025 ""
7026 "trapb"
7027 [(set_attr "type" "misc")])
7029 ;; No-op instructions used by machine-dependent reorg to preserve
7030 ;; alignment for instruction issue.
7031 ;; The Unicos/Mk assembler does not support these opcodes.
7033 (define_insn "nop"
7034 [(const_int 0)]
7035 ""
7036 "bis $31,$31,$31"
7037 [(set_attr "type" "ilog")])
7039 (define_insn "fnop"
7040 [(const_int 1)]
7041 "TARGET_FP"
7042 "cpys $f31,$f31,$f31"
7043 [(set_attr "type" "fcpys")])
7045 (define_insn "unop"
7046 [(const_int 2)]
7047 ""
7048 "ldq_u $31,0($30)")
7050 ;; On Unicos/Mk we use a macro for aligning code.
7052 (define_insn "realign"
7053 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7054 UNSPECV_REALIGN)]
7055 ""
7056 {
7057 if (TARGET_ABI_UNICOSMK)
7058 return "gcc@code@align %0";
7059 else
7060 return ".align %0 #realign";
7061 })
7062 \f
7063 ;; Instructions to be emitted from __builtins.
7065 (define_insn "builtin_cmpbge"
7066 [(set (match_operand:DI 0 "register_operand" "=r")
7067 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7068 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7069 UNSPEC_CMPBGE))]
7070 ""
7071 "cmpbge %r1,%2,%0"
7072 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7073 ;; actually differentiate between ILOG and ICMP in the schedule.
7074 [(set_attr "type" "icmp")])
7076 (define_expand "builtin_extbl"
7077 [(match_operand:DI 0 "register_operand" "")
7078 (match_operand:DI 1 "reg_or_0_operand" "")
7079 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7080 ""
7081 {
7082 rtx (*gen) (rtx, rtx, rtx, rtx);
7083 if (WORDS_BIG_ENDIAN)
7084 gen = gen_extxl_be;
7085 else
7086 gen = gen_extxl_le;
7087 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7088 DONE;
7089 })
7091 (define_expand "builtin_extwl"
7092 [(match_operand:DI 0 "register_operand" "")
7093 (match_operand:DI 1 "reg_or_0_operand" "")
7094 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7095 ""
7096 {
7097 rtx (*gen) (rtx, rtx, rtx, rtx);
7098 if (WORDS_BIG_ENDIAN)
7099 gen = gen_extxl_be;
7100 else
7101 gen = gen_extxl_le;
7102 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7103 DONE;
7104 })
7106 (define_expand "builtin_extll"
7107 [(match_operand:DI 0 "register_operand" "")
7108 (match_operand:DI 1 "reg_or_0_operand" "")
7109 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7110 ""
7111 {
7112 rtx (*gen) (rtx, rtx, rtx, rtx);
7113 if (WORDS_BIG_ENDIAN)
7114 gen = gen_extxl_be;
7115 else
7116 gen = gen_extxl_le;
7117 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7118 DONE;
7119 })
7121 (define_expand "builtin_extql"
7122 [(match_operand:DI 0 "register_operand" "")
7123 (match_operand:DI 1 "reg_or_0_operand" "")
7124 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7125 ""
7126 {
7127 rtx (*gen) (rtx, rtx, rtx, rtx);
7128 if (WORDS_BIG_ENDIAN)
7129 gen = gen_extxl_be;
7130 else
7131 gen = gen_extxl_le;
7132 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7133 DONE;
7134 })
7136 (define_expand "builtin_extwh"
7137 [(match_operand:DI 0 "register_operand" "")
7138 (match_operand:DI 1 "reg_or_0_operand" "")
7139 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7140 ""
7141 {
7142 rtx (*gen) (rtx, rtx, rtx);
7143 if (WORDS_BIG_ENDIAN)
7144 gen = gen_extwh_be;
7145 else
7146 gen = gen_extwh_le;
7147 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7148 DONE;
7149 })
7151 (define_expand "builtin_extlh"
7152 [(match_operand:DI 0 "register_operand" "")
7153 (match_operand:DI 1 "reg_or_0_operand" "")
7154 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7155 ""
7156 {
7157 rtx (*gen) (rtx, rtx, rtx);
7158 if (WORDS_BIG_ENDIAN)
7159 gen = gen_extlh_be;
7160 else
7161 gen = gen_extlh_le;
7162 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7163 DONE;
7164 })
7166 (define_expand "builtin_extqh"
7167 [(match_operand:DI 0 "register_operand" "")
7168 (match_operand:DI 1 "reg_or_0_operand" "")
7169 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7170 ""
7171 {
7172 rtx (*gen) (rtx, rtx, rtx);
7173 if (WORDS_BIG_ENDIAN)
7174 gen = gen_extqh_be;
7175 else
7176 gen = gen_extqh_le;
7177 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7178 DONE;
7179 })
7181 (define_expand "builtin_insbl"
7182 [(match_operand:DI 0 "register_operand" "")
7183 (match_operand:DI 1 "register_operand" "")
7184 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7185 ""
7186 {
7187 rtx (*gen) (rtx, rtx, rtx);
7188 if (WORDS_BIG_ENDIAN)
7189 gen = gen_insbl_be;
7190 else
7191 gen = gen_insbl_le;
7192 operands[1] = gen_lowpart (QImode, operands[1]);
7193 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7194 DONE;
7195 })
7197 (define_expand "builtin_inswl"
7198 [(match_operand:DI 0 "register_operand" "")
7199 (match_operand:DI 1 "register_operand" "")
7200 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7201 ""
7202 {
7203 rtx (*gen) (rtx, rtx, rtx);
7204 if (WORDS_BIG_ENDIAN)
7205 gen = gen_inswl_be;
7206 else
7207 gen = gen_inswl_le;
7208 operands[1] = gen_lowpart (HImode, operands[1]);
7209 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7210 DONE;
7211 })
7213 (define_expand "builtin_insll"
7214 [(match_operand:DI 0 "register_operand" "")
7215 (match_operand:DI 1 "register_operand" "")
7216 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7217 ""
7218 {
7219 rtx (*gen) (rtx, rtx, rtx);
7220 if (WORDS_BIG_ENDIAN)
7221 gen = gen_insll_be;
7222 else
7223 gen = gen_insll_le;
7224 operands[1] = gen_lowpart (SImode, operands[1]);
7225 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7226 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7227 DONE;
7228 })
7230 (define_expand "builtin_insql"
7231 [(match_operand:DI 0 "register_operand" "")
7232 (match_operand:DI 1 "reg_or_0_operand" "")
7233 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7234 ""
7235 {
7236 rtx (*gen) (rtx, rtx, rtx);
7237 if (WORDS_BIG_ENDIAN)
7238 gen = gen_insql_be;
7239 else
7240 gen = gen_insql_le;
7241 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7242 DONE;
7243 })
7245 (define_expand "builtin_inswh"
7246 [(match_operand:DI 0 "register_operand" "")
7247 (match_operand:DI 1 "register_operand" "")
7248 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7249 ""
7250 {
7251 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7252 DONE;
7253 })
7255 (define_expand "builtin_inslh"
7256 [(match_operand:DI 0 "register_operand" "")
7257 (match_operand:DI 1 "register_operand" "")
7258 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7259 ""
7260 {
7261 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7262 DONE;
7263 })
7265 (define_expand "builtin_insqh"
7266 [(match_operand:DI 0 "register_operand" "")
7267 (match_operand:DI 1 "register_operand" "")
7268 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7269 ""
7270 {
7271 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7272 DONE;
7273 })
7275 (define_expand "builtin_mskbl"
7276 [(match_operand:DI 0 "register_operand" "")
7277 (match_operand:DI 1 "reg_or_0_operand" "")
7278 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7279 ""
7280 {
7281 rtx (*gen) (rtx, rtx, rtx, rtx);
7282 rtx mask;
7283 if (WORDS_BIG_ENDIAN)
7284 gen = gen_mskxl_be;
7285 else
7286 gen = gen_mskxl_le;
7287 mask = GEN_INT (0xff);
7288 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7289 DONE;
7290 })
7292 (define_expand "builtin_mskwl"
7293 [(match_operand:DI 0 "register_operand" "")
7294 (match_operand:DI 1 "reg_or_0_operand" "")
7295 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7296 ""
7297 {
7298 rtx (*gen) (rtx, rtx, rtx, rtx);
7299 rtx mask;
7300 if (WORDS_BIG_ENDIAN)
7301 gen = gen_mskxl_be;
7302 else
7303 gen = gen_mskxl_le;
7304 mask = GEN_INT (0xffff);
7305 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7306 DONE;
7307 })
7309 (define_expand "builtin_mskll"
7310 [(match_operand:DI 0 "register_operand" "")
7311 (match_operand:DI 1 "reg_or_0_operand" "")
7312 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7313 ""
7314 {
7315 rtx (*gen) (rtx, rtx, rtx, rtx);
7316 rtx mask;
7317 if (WORDS_BIG_ENDIAN)
7318 gen = gen_mskxl_be;
7319 else
7320 gen = gen_mskxl_le;
7321 mask = immed_double_const (0xffffffff, 0, DImode);
7322 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7323 DONE;
7324 })
7326 (define_expand "builtin_mskql"
7327 [(match_operand:DI 0 "register_operand" "")
7328 (match_operand:DI 1 "reg_or_0_operand" "")
7329 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7330 ""
7331 {
7332 rtx (*gen) (rtx, rtx, rtx, rtx);
7333 rtx mask;
7334 if (WORDS_BIG_ENDIAN)
7335 gen = gen_mskxl_be;
7336 else
7337 gen = gen_mskxl_le;
7338 mask = constm1_rtx;
7339 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7340 DONE;
7341 })
7343 (define_expand "builtin_mskwh"
7344 [(match_operand:DI 0 "register_operand" "")
7345 (match_operand:DI 1 "register_operand" "")
7346 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7347 ""
7348 {
7349 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7350 DONE;
7351 })
7353 (define_expand "builtin_msklh"
7354 [(match_operand:DI 0 "register_operand" "")
7355 (match_operand:DI 1 "register_operand" "")
7356 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7357 ""
7358 {
7359 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7360 DONE;
7361 })
7363 (define_expand "builtin_mskqh"
7364 [(match_operand:DI 0 "register_operand" "")
7365 (match_operand:DI 1 "register_operand" "")
7366 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7367 ""
7368 {
7369 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7370 DONE;
7371 })
7373 (define_expand "builtin_zap"
7374 [(set (match_operand:DI 0 "register_operand" "")
7375 (and:DI (unspec:DI
7376 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7377 UNSPEC_ZAP)
7378 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7379 ""
7380 {
7381 if (GET_CODE (operands[2]) == CONST_INT)
7382 {
7383 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7385 if (mask == const0_rtx)
7386 {
7387 emit_move_insn (operands[0], const0_rtx);
7388 DONE;
7389 }
7390 if (mask == constm1_rtx)
7391 {
7392 emit_move_insn (operands[0], operands[1]);
7393 DONE;
7394 }
7396 operands[1] = force_reg (DImode, operands[1]);
7397 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7398 DONE;
7399 }
7401 operands[1] = force_reg (DImode, operands[1]);
7402 operands[2] = gen_lowpart (QImode, operands[2]);
7403 })
7405 (define_insn "*builtin_zap_1"
7406 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7407 (and:DI (unspec:DI
7408 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7409 UNSPEC_ZAP)
7410 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7411 ""
7412 "@
7413 #
7414 #
7415 bis $31,$31,%0
7416 zap %r1,%2,%0"
7417 [(set_attr "type" "shift,shift,ilog,shift")])
7419 (define_split
7420 [(set (match_operand:DI 0 "register_operand" "")
7421 (and:DI (unspec:DI
7422 [(match_operand:QI 2 "const_int_operand" "")]
7423 UNSPEC_ZAP)
7424 (match_operand:DI 1 "const_int_operand" "")))]
7425 ""
7426 [(const_int 0)]
7427 {
7428 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7429 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7430 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7431 else
7432 {
7433 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7434 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7435 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7436 c_hi & CONST_DOUBLE_HIGH (mask),
7437 DImode);
7438 }
7439 emit_move_insn (operands[0], operands[1]);
7440 DONE;
7441 })
7443 (define_split
7444 [(set (match_operand:DI 0 "register_operand" "")
7445 (and:DI (unspec:DI
7446 [(match_operand:QI 2 "const_int_operand" "")]
7447 UNSPEC_ZAP)
7448 (match_operand:DI 1 "register_operand" "")))]
7449 ""
7450 [(set (match_dup 0)
7451 (and:DI (match_dup 1) (match_dup 2)))]
7452 {
7453 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7454 if (operands[2] == const0_rtx)
7455 {
7456 emit_move_insn (operands[0], const0_rtx);
7457 DONE;
7458 }
7459 if (operands[2] == constm1_rtx)
7460 {
7461 emit_move_insn (operands[0], operands[1]);
7462 DONE;
7463 }
7464 })
7466 (define_expand "builtin_zapnot"
7467 [(set (match_operand:DI 0 "register_operand" "")
7468 (and:DI (unspec:DI
7469 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7470 UNSPEC_ZAP)
7471 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7472 ""
7473 {
7474 if (GET_CODE (operands[2]) == CONST_INT)
7475 {
7476 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7478 if (mask == const0_rtx)
7479 {
7480 emit_move_insn (operands[0], const0_rtx);
7481 DONE;
7482 }
7483 if (mask == constm1_rtx)
7484 {
7485 emit_move_insn (operands[0], operands[1]);
7486 DONE;
7487 }
7489 operands[1] = force_reg (DImode, operands[1]);
7490 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7491 DONE;
7492 }
7494 operands[1] = force_reg (DImode, operands[1]);
7495 operands[2] = gen_lowpart (QImode, operands[2]);
7496 })
7498 (define_insn "*builtin_zapnot_1"
7499 [(set (match_operand:DI 0 "register_operand" "=r")
7500 (and:DI (unspec:DI
7501 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7502 UNSPEC_ZAP)
7503 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7504 ""
7505 "zapnot %r1,%2,%0"
7506 [(set_attr "type" "shift")])
7508 (define_insn "builtin_amask"
7509 [(set (match_operand:DI 0 "register_operand" "=r")
7510 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7511 UNSPEC_AMASK))]
7512 ""
7513 "amask %1,%0"
7514 [(set_attr "type" "ilog")])
7516 (define_insn "builtin_implver"
7517 [(set (match_operand:DI 0 "register_operand" "=r")
7518 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7519 ""
7520 "implver %0"
7521 [(set_attr "type" "ilog")])
7523 (define_insn "builtin_rpcc"
7524 [(set (match_operand:DI 0 "register_operand" "=r")
7525 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7526 ""
7527 "rpcc %0"
7528 [(set_attr "type" "ilog")])
7530 (define_expand "builtin_minub8"
7531 [(match_operand:DI 0 "register_operand" "")
7532 (match_operand:DI 1 "reg_or_0_operand" "")
7533 (match_operand:DI 2 "reg_or_0_operand" "")]
7534 "TARGET_MAX"
7535 {
7536 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7537 operands[1], operands[2]);
7538 DONE;
7539 })
7541 (define_expand "builtin_minsb8"
7542 [(match_operand:DI 0 "register_operand" "")
7543 (match_operand:DI 1 "reg_or_0_operand" "")
7544 (match_operand:DI 2 "reg_or_0_operand" "")]
7545 "TARGET_MAX"
7546 {
7547 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7548 operands[1], operands[2]);
7549 DONE;
7550 })
7552 (define_expand "builtin_minuw4"
7553 [(match_operand:DI 0 "register_operand" "")
7554 (match_operand:DI 1 "reg_or_0_operand" "")
7555 (match_operand:DI 2 "reg_or_0_operand" "")]
7556 "TARGET_MAX"
7557 {
7558 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7559 operands[1], operands[2]);
7560 DONE;
7561 })
7563 (define_expand "builtin_minsw4"
7564 [(match_operand:DI 0 "register_operand" "")
7565 (match_operand:DI 1 "reg_or_0_operand" "")
7566 (match_operand:DI 2 "reg_or_0_operand" "")]
7567 "TARGET_MAX"
7568 {
7569 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7570 operands[1], operands[2]);
7571 DONE;
7572 })
7574 (define_expand "builtin_maxub8"
7575 [(match_operand:DI 0 "register_operand" "")
7576 (match_operand:DI 1 "reg_or_0_operand" "")
7577 (match_operand:DI 2 "reg_or_0_operand" "")]
7578 "TARGET_MAX"
7579 {
7580 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7581 operands[1], operands[2]);
7582 DONE;
7583 })
7585 (define_expand "builtin_maxsb8"
7586 [(match_operand:DI 0 "register_operand" "")
7587 (match_operand:DI 1 "reg_or_0_operand" "")
7588 (match_operand:DI 2 "reg_or_0_operand" "")]
7589 "TARGET_MAX"
7590 {
7591 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7592 operands[1], operands[2]);
7593 DONE;
7594 })
7596 (define_expand "builtin_maxuw4"
7597 [(match_operand:DI 0 "register_operand" "")
7598 (match_operand:DI 1 "reg_or_0_operand" "")
7599 (match_operand:DI 2 "reg_or_0_operand" "")]
7600 "TARGET_MAX"
7601 {
7602 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7603 operands[1], operands[2]);
7604 DONE;
7605 })
7607 (define_expand "builtin_maxsw4"
7608 [(match_operand:DI 0 "register_operand" "")
7609 (match_operand:DI 1 "reg_or_0_operand" "")
7610 (match_operand:DI 2 "reg_or_0_operand" "")]
7611 "TARGET_MAX"
7612 {
7613 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7614 operands[1], operands[2]);
7615 DONE;
7616 })
7618 (define_insn "builtin_perr"
7619 [(set (match_operand:DI 0 "register_operand" "=r")
7620 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7621 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7622 UNSPEC_PERR))]
7623 "TARGET_MAX"
7624 "perr %r1,%r2,%0"
7625 [(set_attr "type" "mvi")])
7627 (define_expand "builtin_pklb"
7628 [(set (match_operand:DI 0 "register_operand" "")
7629 (vec_concat:V8QI
7630 (vec_concat:V4QI
7631 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7632 (match_dup 2))
7633 (match_dup 3)))]
7634 "TARGET_MAX"
7635 {
7636 operands[0] = gen_lowpart (V8QImode, operands[0]);
7637 operands[1] = gen_lowpart (V2SImode, operands[1]);
7638 operands[2] = CONST0_RTX (V2QImode);
7639 operands[3] = CONST0_RTX (V4QImode);
7640 })
7642 (define_insn "*pklb"
7643 [(set (match_operand:V8QI 0 "register_operand" "=r")
7644 (vec_concat:V8QI
7645 (vec_concat:V4QI
7646 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7647 (match_operand:V2QI 2 "const0_operand" ""))
7648 (match_operand:V4QI 3 "const0_operand" "")))]
7649 "TARGET_MAX"
7650 "pklb %r1,%0"
7651 [(set_attr "type" "mvi")])
7653 (define_expand "builtin_pkwb"
7654 [(set (match_operand:DI 0 "register_operand" "")
7655 (vec_concat:V8QI
7656 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7657 (match_dup 2)))]
7658 "TARGET_MAX"
7659 {
7660 operands[0] = gen_lowpart (V8QImode, operands[0]);
7661 operands[1] = gen_lowpart (V4HImode, operands[1]);
7662 operands[2] = CONST0_RTX (V4QImode);
7663 })
7665 (define_insn "*pkwb"
7666 [(set (match_operand:V8QI 0 "register_operand" "=r")
7667 (vec_concat:V8QI
7668 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7669 (match_operand:V4QI 2 "const0_operand" "")))]
7670 "TARGET_MAX"
7671 "pkwb %r1,%0"
7672 [(set_attr "type" "mvi")])
7674 (define_expand "builtin_unpkbl"
7675 [(set (match_operand:DI 0 "register_operand" "")
7676 (zero_extend:V2SI
7677 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7678 (parallel [(const_int 0) (const_int 1)]))))]
7679 "TARGET_MAX"
7680 {
7681 operands[0] = gen_lowpart (V2SImode, operands[0]);
7682 operands[1] = gen_lowpart (V8QImode, operands[1]);
7683 })
7685 (define_insn "*unpkbl"
7686 [(set (match_operand:V2SI 0 "register_operand" "=r")
7687 (zero_extend:V2SI
7688 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7689 (parallel [(const_int 0) (const_int 1)]))))]
7690 "TARGET_MAX"
7691 "unpkbl %r1,%0"
7692 [(set_attr "type" "mvi")])
7694 (define_expand "builtin_unpkbw"
7695 [(set (match_operand:DI 0 "register_operand" "")
7696 (zero_extend:V4HI
7697 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7698 (parallel [(const_int 0)
7699 (const_int 1)
7700 (const_int 2)
7701 (const_int 3)]))))]
7702 "TARGET_MAX"
7703 {
7704 operands[0] = gen_lowpart (V4HImode, operands[0]);
7705 operands[1] = gen_lowpart (V8QImode, operands[1]);
7706 })
7708 (define_insn "*unpkbw"
7709 [(set (match_operand:V4HI 0 "register_operand" "=r")
7710 (zero_extend:V4HI
7711 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7712 (parallel [(const_int 0)
7713 (const_int 1)
7714 (const_int 2)
7715 (const_int 3)]))))]
7716 "TARGET_MAX"
7717 "unpkbw %r1,%0"
7718 [(set_attr "type" "mvi")])
7720 (define_expand "builtin_cttz"
7721 [(set (match_operand:DI 0 "register_operand" "")
7722 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7723 UNSPEC_CTTZ))]
7724 "TARGET_CIX"
7725 "")
7727 (define_insn "builtin_ctlz"
7728 [(set (match_operand:DI 0 "register_operand" "=r")
7729 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7730 UNSPEC_CTLZ))]
7731 "TARGET_CIX"
7732 "ctlz %1,%0"
7733 [(set_attr "type" "mvi")])
7735 (define_insn "builtin_ctpop"
7736 [(set (match_operand:DI 0 "register_operand" "=r")
7737 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7738 UNSPEC_CTPOP))]
7739 "TARGET_CIX"
7740 "ctpop %1,%0"
7741 [(set_attr "type" "mvi")])
7742 \f
7743 ;; The call patterns are at the end of the file because their
7744 ;; wildcard operand0 interferes with nice recognition.
7746 (define_insn "*call_value_osf_1_er"
7747 [(set (match_operand 0 "" "")
7748 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7749 (match_operand 2 "" "")))
7750 (use (reg:DI 29))
7751 (clobber (reg:DI 26))]
7752 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7753 "@
7754 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7755 bsr $26,%1\t\t!samegp
7756 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7757 [(set_attr "type" "jsr")
7758 (set_attr "length" "12,*,16")])
7760 ;; We must use peep2 instead of a split because we need accurate life
7761 ;; information for $gp. Consider the case of { bar(); while (1); }.
7762 (define_peephole2
7763 [(parallel [(set (match_operand 0 "" "")
7764 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7765 (match_operand 2 "" "")))
7766 (use (reg:DI 29))
7767 (clobber (reg:DI 26))])]
7768 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7769 && ! samegp_function_operand (operands[1], Pmode)
7770 && (peep2_regno_dead_p (1, 29)
7771 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7772 [(parallel [(set (match_dup 0)
7773 (call (mem:DI (match_dup 3))
7774 (match_dup 2)))
7775 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7776 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7777 (use (match_dup 1))
7778 (use (match_dup 4))])]
7779 {
7780 if (CONSTANT_P (operands[1]))
7781 {
7782 operands[3] = gen_rtx_REG (Pmode, 27);
7783 operands[4] = GEN_INT (alpha_next_sequence_number++);
7784 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7785 operands[1], operands[4]));
7786 }
7787 else
7788 {
7789 operands[3] = operands[1];
7790 operands[1] = const0_rtx;
7791 operands[4] = const0_rtx;
7792 }
7793 })
7795 (define_peephole2
7796 [(parallel [(set (match_operand 0 "" "")
7797 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7798 (match_operand 2 "" "")))
7799 (use (reg:DI 29))
7800 (clobber (reg:DI 26))])]
7801 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7802 && ! samegp_function_operand (operands[1], Pmode)
7803 && ! (peep2_regno_dead_p (1, 29)
7804 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7805 [(parallel [(set (match_dup 0)
7806 (call (mem:DI (match_dup 3))
7807 (match_dup 2)))
7808 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7809 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7810 (use (match_dup 1))
7811 (use (match_dup 5))])
7812 (set (reg:DI 29)
7813 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7814 (set (reg:DI 29)
7815 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7816 {
7817 if (CONSTANT_P (operands[1]))
7818 {
7819 operands[3] = gen_rtx_REG (Pmode, 27);
7820 operands[5] = GEN_INT (alpha_next_sequence_number++);
7821 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7822 operands[1], operands[5]));
7823 }
7824 else
7825 {
7826 operands[3] = operands[1];
7827 operands[1] = const0_rtx;
7828 operands[5] = const0_rtx;
7829 }
7830 operands[4] = GEN_INT (alpha_next_sequence_number++);
7831 })
7833 ;; We add a blockage unspec_volatile to prevent insns from moving down
7834 ;; from above the call to in between the call and the ldah gpdisp.
7835 (define_insn "*call_value_osf_2_er"
7836 [(set (match_operand 0 "" "")
7837 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7838 (match_operand 2 "" "")))
7839 (set (reg:DI 26)
7840 (plus:DI (pc) (const_int 4)))
7841 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7842 (use (match_operand 3 "" ""))
7843 (use (match_operand 4 "" ""))]
7844 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7845 "jsr $26,(%1),%3%J4"
7846 [(set_attr "type" "jsr")
7847 (set_attr "cannot_copy" "true")])
7849 (define_insn "*call_value_osf_1_noreturn"
7850 [(set (match_operand 0 "" "")
7851 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7852 (match_operand 2 "" "")))
7853 (use (reg:DI 29))
7854 (clobber (reg:DI 26))]
7855 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7856 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7857 "@
7858 jsr $26,($27),0%+
7859 bsr $26,$%1..ng%+
7860 jsr $26,%1%+"
7861 [(set_attr "type" "jsr")
7862 (set_attr "length" "*,*,8")])
7864 (define_insn_and_split "call_value_osf_tlsgd"
7865 [(set (match_operand 0 "" "")
7866 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7867 (const_int 0)))
7868 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7869 (use (reg:DI 29))
7870 (clobber (reg:DI 26))]
7871 "HAVE_AS_TLS"
7872 "#"
7873 "&& reload_completed"
7874 [(set (match_dup 3)
7875 (unspec:DI [(match_dup 5)
7876 (match_dup 1)
7877 (match_dup 2)] UNSPEC_LITERAL))
7878 (parallel [(set (match_dup 0)
7879 (call (mem:DI (match_dup 3))
7880 (const_int 0)))
7881 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7882 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7883 (use (match_dup 1))
7884 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7885 (set (match_dup 5)
7886 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7887 (set (match_dup 5)
7888 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7889 {
7890 operands[3] = gen_rtx_REG (Pmode, 27);
7891 operands[4] = GEN_INT (alpha_next_sequence_number++);
7892 operands[5] = pic_offset_table_rtx;
7893 }
7894 [(set_attr "type" "multi")])
7896 (define_insn_and_split "call_value_osf_tlsldm"
7897 [(set (match_operand 0 "" "")
7898 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7899 (const_int 0)))
7900 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7901 (use (reg:DI 29))
7902 (clobber (reg:DI 26))]
7903 "HAVE_AS_TLS"
7904 "#"
7905 "&& reload_completed"
7906 [(set (match_dup 3)
7907 (unspec:DI [(match_dup 5)
7908 (match_dup 1)
7909 (match_dup 2)] UNSPEC_LITERAL))
7910 (parallel [(set (match_dup 0)
7911 (call (mem:DI (match_dup 3))
7912 (const_int 0)))
7913 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7914 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7915 (use (match_dup 1))
7916 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7917 (set (reg:DI 29)
7918 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7919 (set (reg:DI 29)
7920 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7921 {
7922 operands[3] = gen_rtx_REG (Pmode, 27);
7923 operands[4] = GEN_INT (alpha_next_sequence_number++);
7924 operands[5] = pic_offset_table_rtx;
7925 }
7926 [(set_attr "type" "multi")])
7928 (define_insn "*call_value_osf_1"
7929 [(set (match_operand 0 "" "")
7930 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7931 (match_operand 2 "" "")))
7932 (use (reg:DI 29))
7933 (clobber (reg:DI 26))]
7934 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7935 "@
7936 jsr $26,($27),0\;ldgp $29,0($26)
7937 bsr $26,$%1..ng
7938 jsr $26,%1\;ldgp $29,0($26)"
7939 [(set_attr "type" "jsr")
7940 (set_attr "length" "12,*,16")])
7942 (define_insn "*sibcall_value_osf_1_er"
7943 [(set (match_operand 0 "" "")
7944 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7945 (match_operand 2 "" "")))
7946 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7947 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7948 "@
7949 br $31,%1\t\t!samegp
7950 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7951 [(set_attr "type" "jsr")
7952 (set_attr "length" "*,8")])
7954 (define_insn "*sibcall_value_osf_1"
7955 [(set (match_operand 0 "" "")
7956 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7957 (match_operand 2 "" "")))
7958 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7959 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7960 "@
7961 br $31,$%1..ng
7962 lda $27,%1\;jmp $31,($27),%1"
7963 [(set_attr "type" "jsr")
7964 (set_attr "length" "*,8")])
7966 (define_insn "*call_value_nt_1"
7967 [(set (match_operand 0 "" "")
7968 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7969 (match_operand 2 "" "")))
7970 (clobber (reg:DI 26))]
7971 "TARGET_ABI_WINDOWS_NT"
7972 "@
7973 jsr $26,(%1)
7974 bsr $26,%1
7975 jsr $26,%1"
7976 [(set_attr "type" "jsr")
7977 (set_attr "length" "*,*,12")])
7979 ; GAS relies on the order and position of instructions output below in order
7980 ; to generate relocs for VMS link to potentially optimize the call.
7981 ; Please do not molest.
7982 (define_insn "*call_value_vms_1"
7983 [(set (match_operand 0 "" "")
7984 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7985 (match_operand 2 "" "")))
7986 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
7987 (use (reg:DI 25))
7988 (use (reg:DI 26))
7989 (clobber (reg:DI 27))]
7990 "TARGET_ABI_OPEN_VMS"
7991 {
7992 switch (which_alternative)
7993 {
7994 case 0:
7995 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
7996 case 1:
7997 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
7998 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
7999 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8000 default:
8001 abort();
8002 }
8003 }
8004 [(set_attr "type" "jsr")
8005 (set_attr "length" "12,16")])
8007 (define_insn "*call_value_umk"
8008 [(set (match_operand 0 "" "")
8009 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8010 (match_operand 2 "" "")))
8011 (use (reg:DI 25))
8012 (clobber (reg:DI 26))]
8013 "TARGET_ABI_UNICOSMK"
8014 "jsr $26,(%1)"
8015 [(set_attr "type" "jsr")])