1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
49 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Cached operands, and operator to compare for use in set/branch on
78 /* what type of branch to use */
79 enum cmp_type branch_type
;
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size
;
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function
GTY(())
94 int accesses_prev_frame
;
98 rtx set_frame_ptr_insn
;
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
105 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
] =
116 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
117 RL_REGS
, RL_REGS
, RL_REGS
, GR_REGS
,
118 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
119 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
120 AR_REGS
, AR_REGS
, BR_REGS
,
121 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
122 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
123 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
124 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
128 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
129 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
130 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
131 static rtx
gen_conditional_move (rtx
);
132 static rtx
fixup_subreg_mem (rtx
);
133 static struct machine_function
* xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (const_tree
);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT
);
137 static rtx
xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
139 int) ATTRIBUTE_UNUSED
;
140 static section
*xtensa_select_rtx_section (enum machine_mode
, rtx
,
141 unsigned HOST_WIDE_INT
);
142 static bool xtensa_rtx_costs (rtx
, int, int, int *);
143 static tree
xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree
, const_tree
);
145 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, tree
*, tree
*);
146 static void xtensa_init_builtins (void);
147 static tree
xtensa_fold_builtin (tree
, tree
, bool);
148 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
149 static void xtensa_va_start (tree
, rtx
);
151 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
155 /* This macro generates the assembly code for function exit,
156 on machines that need it. If FUNCTION_EPILOGUE is not defined
157 then individual return instructions are generated for each
158 return statement. Args are same as for FUNCTION_PROLOGUE. */
160 #undef TARGET_ASM_FUNCTION_EPILOGUE
161 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
163 /* These hooks specify assembly directives for creating certain kinds
164 of integer object. */
166 #undef TARGET_ASM_ALIGNED_SI_OP
167 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
169 #undef TARGET_ASM_SELECT_RTX_SECTION
170 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
172 #undef TARGET_DEFAULT_TARGET_FLAGS
173 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
175 #undef TARGET_RTX_COSTS
176 #define TARGET_RTX_COSTS xtensa_rtx_costs
177 #undef TARGET_ADDRESS_COST
178 #define TARGET_ADDRESS_COST hook_int_rtx_0
180 #undef TARGET_BUILD_BUILTIN_VA_LIST
181 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
183 #undef TARGET_EXPAND_BUILTIN_VA_START
184 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
186 #undef TARGET_PROMOTE_FUNCTION_ARGS
187 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
188 #undef TARGET_PROMOTE_FUNCTION_RETURN
189 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
190 #undef TARGET_PROMOTE_PROTOTYPES
191 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
193 #undef TARGET_RETURN_IN_MEMORY
194 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
195 #undef TARGET_SPLIT_COMPLEX_ARG
196 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
197 #undef TARGET_MUST_PASS_IN_STACK
198 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
200 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
201 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
202 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
203 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
205 #undef TARGET_RETURN_IN_MSB
206 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
208 #undef TARGET_INIT_BUILTINS
209 #define TARGET_INIT_BUILTINS xtensa_init_builtins
210 #undef TARGET_FOLD_BUILTIN
211 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
212 #undef TARGET_EXPAND_BUILTIN
213 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
215 struct gcc_target targetm
= TARGET_INITIALIZER
;
218 /* Functions to test Xtensa immediate operand validity. */
221 xtensa_simm8 (HOST_WIDE_INT v
)
223 return v
>= -128 && v
<= 127;
228 xtensa_simm8x256 (HOST_WIDE_INT v
)
230 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
235 xtensa_simm12b (HOST_WIDE_INT v
)
237 return v
>= -2048 && v
<= 2047;
242 xtensa_uimm8 (HOST_WIDE_INT v
)
244 return v
>= 0 && v
<= 255;
249 xtensa_uimm8x2 (HOST_WIDE_INT v
)
251 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
256 xtensa_uimm8x4 (HOST_WIDE_INT v
)
258 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
263 xtensa_b4const (HOST_WIDE_INT v
)
290 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
294 return xtensa_b4const (v
);
299 xtensa_b4constu (HOST_WIDE_INT v
)
326 xtensa_mask_immediate (HOST_WIDE_INT v
)
328 #define MAX_MASK_SIZE 16
331 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
344 /* This is just like the standard true_regnum() function except that it
345 works even when reg_renumber is not initialized. */
348 xt_true_regnum (rtx x
)
350 if (GET_CODE (x
) == REG
)
353 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
354 && reg_renumber
[REGNO (x
)] >= 0)
355 return reg_renumber
[REGNO (x
)];
358 if (GET_CODE (x
) == SUBREG
)
360 int base
= xt_true_regnum (SUBREG_REG (x
));
361 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
362 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
363 GET_MODE (SUBREG_REG (x
)),
364 SUBREG_BYTE (x
), GET_MODE (x
));
371 xtensa_valid_move (enum machine_mode mode
, rtx
*operands
)
373 /* Either the destination or source must be a register, and the
374 MAC16 accumulator doesn't count. */
376 if (register_operand (operands
[0], mode
))
378 int dst_regnum
= xt_true_regnum (operands
[0]);
380 /* The stack pointer can only be assigned with a MOVSP opcode. */
381 if (dst_regnum
== STACK_POINTER_REGNUM
)
382 return (mode
== SImode
383 && register_operand (operands
[1], mode
)
384 && !ACC_REG_P (xt_true_regnum (operands
[1])));
386 if (!ACC_REG_P (dst_regnum
))
389 if (register_operand (operands
[1], mode
))
391 int src_regnum
= xt_true_regnum (operands
[1]);
392 if (!ACC_REG_P (src_regnum
))
400 smalloffset_mem_p (rtx op
)
402 if (GET_CODE (op
) == MEM
)
404 rtx addr
= XEXP (op
, 0);
405 if (GET_CODE (addr
) == REG
)
406 return BASE_REG_P (addr
, 0);
407 if (GET_CODE (addr
) == PLUS
)
409 rtx offset
= XEXP (addr
, 0);
411 if (GET_CODE (offset
) != CONST_INT
)
412 offset
= XEXP (addr
, 1);
413 if (GET_CODE (offset
) != CONST_INT
)
416 val
= INTVAL (offset
);
417 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
425 constantpool_address_p (rtx addr
)
429 if (GET_CODE (addr
) == CONST
)
433 /* Only handle (PLUS (SYM, OFFSET)) form. */
434 addr
= XEXP (addr
, 0);
435 if (GET_CODE (addr
) != PLUS
)
438 /* Make sure the address is word aligned. */
439 offset
= XEXP (addr
, 1);
440 if ((GET_CODE (offset
) != CONST_INT
)
441 || ((INTVAL (offset
) & 3) != 0))
444 sym
= XEXP (addr
, 0);
447 if ((GET_CODE (sym
) == SYMBOL_REF
)
448 && CONSTANT_POOL_ADDRESS_P (sym
))
455 constantpool_mem_p (rtx op
)
457 if (GET_CODE (op
) == SUBREG
)
458 op
= SUBREG_REG (op
);
459 if (GET_CODE (op
) == MEM
)
460 return constantpool_address_p (XEXP (op
, 0));
466 xtensa_extend_reg (rtx dst
, rtx src
)
468 rtx temp
= gen_reg_rtx (SImode
);
469 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
471 /* Generate paradoxical subregs as needed so that the modes match. */
472 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
473 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
475 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
476 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
481 xtensa_mem_offset (unsigned v
, enum machine_mode mode
)
486 /* Handle the worst case for block moves. See xtensa_expand_block_move
487 where we emit an optimized block move operation if the block can be
488 moved in < "move_ratio" pieces. The worst case is when the block is
489 aligned but has a size of (3 mod 4) (does this happen?) so that the
490 last piece requires a byte load/store. */
491 return (xtensa_uimm8 (v
)
492 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
495 return xtensa_uimm8 (v
);
498 return xtensa_uimm8x2 (v
);
501 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
507 return xtensa_uimm8x4 (v
);
511 /* Make normal rtx_code into something we can index from an array. */
513 static enum internal_test
514 map_test_to_internal_test (enum rtx_code test_code
)
516 enum internal_test test
= ITEST_MAX
;
521 case EQ
: test
= ITEST_EQ
; break;
522 case NE
: test
= ITEST_NE
; break;
523 case GT
: test
= ITEST_GT
; break;
524 case GE
: test
= ITEST_GE
; break;
525 case LT
: test
= ITEST_LT
; break;
526 case LE
: test
= ITEST_LE
; break;
527 case GTU
: test
= ITEST_GTU
; break;
528 case GEU
: test
= ITEST_GEU
; break;
529 case LTU
: test
= ITEST_LTU
; break;
530 case LEU
: test
= ITEST_LEU
; break;
537 /* Generate the code to compare two integer values. The return value is
538 the comparison expression. */
541 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
542 rtx cmp0
, /* first operand to compare */
543 rtx cmp1
, /* second operand to compare */
544 int *p_invert
/* whether branch needs to reverse test */)
548 enum rtx_code test_code
; /* test code to use in insn */
549 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
550 int const_add
; /* constant to add (convert LE -> LT) */
551 int reverse_regs
; /* reverse registers in test */
552 int invert_const
; /* != 0 if invert value if cmp1 is constant */
553 int invert_reg
; /* != 0 if invert value if cmp1 is register */
554 int unsignedp
; /* != 0 for unsigned comparisons. */
557 static struct cmp_info info
[ (int)ITEST_MAX
] = {
559 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
560 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
562 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
563 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
564 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
565 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
567 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
568 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
569 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
570 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
573 enum internal_test test
;
574 enum machine_mode mode
;
575 struct cmp_info
*p_info
;
577 test
= map_test_to_internal_test (test_code
);
578 gcc_assert (test
!= ITEST_MAX
);
580 p_info
= &info
[ (int)test
];
582 mode
= GET_MODE (cmp0
);
583 if (mode
== VOIDmode
)
584 mode
= GET_MODE (cmp1
);
586 /* Make sure we can handle any constants given to us. */
587 if (GET_CODE (cmp1
) == CONST_INT
)
589 HOST_WIDE_INT value
= INTVAL (cmp1
);
590 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
592 /* if the immediate overflows or does not fit in the immediate field,
593 spill it to a register */
595 if ((p_info
->unsignedp
?
596 (uvalue
+ p_info
->const_add
> uvalue
) :
597 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
599 cmp1
= force_reg (mode
, cmp1
);
601 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
603 cmp1
= force_reg (mode
, cmp1
);
606 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
608 cmp1
= force_reg (mode
, cmp1
);
611 /* See if we need to invert the result. */
612 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
613 ? p_info
->invert_const
614 : p_info
->invert_reg
);
616 /* Comparison to constants, may involve adding 1 to change a LT into LE.
617 Comparison between two registers, may involve switching operands. */
618 if (GET_CODE (cmp1
) == CONST_INT
)
620 if (p_info
->const_add
!= 0)
621 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
624 else if (p_info
->reverse_regs
)
631 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
635 /* Generate the code to compare two float values. The return value is
636 the comparison expression. */
639 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
640 rtx cmp0
, /* first operand to compare */
641 rtx cmp1
/* second operand to compare */)
643 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
645 int reverse_regs
, invert
;
649 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
650 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
651 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
652 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
653 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
654 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
655 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
656 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
657 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
658 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
659 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
660 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
662 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
664 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
666 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
667 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
677 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
678 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
680 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
685 xtensa_expand_conditional_branch (rtx
*operands
, enum rtx_code test_code
)
687 enum cmp_type type
= branch_type
;
688 rtx cmp0
= branch_cmp
[0];
689 rtx cmp1
= branch_cmp
[1];
698 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
702 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
706 if (!TARGET_HARD_FLOAT
)
707 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
710 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
714 /* Generate the branch. */
716 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
725 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
726 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
733 gen_conditional_move (rtx cmp
)
735 enum rtx_code code
= GET_CODE (cmp
);
736 rtx op0
= branch_cmp
[0];
737 rtx op1
= branch_cmp
[1];
739 if (branch_type
== CMP_SI
)
741 /* Jump optimization calls get_condition() which canonicalizes
742 comparisons like (GE x <const>) to (GT x <const-1>).
743 Transform those comparisons back to GE, since that is the
744 comparison supported in Xtensa. We shouldn't have to
745 transform <LE x const> comparisons, because neither
746 xtensa_expand_conditional_branch() nor get_condition() will
749 if ((code
== GT
) && (op1
== constm1_rtx
))
754 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
756 if (boolean_operator (cmp
, VOIDmode
))
758 /* Swap the operands to make const0 second. */
759 if (op0
== const0_rtx
)
765 /* If not comparing against zero, emit a comparison (subtract). */
766 if (op1
!= const0_rtx
)
768 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
769 0, 0, OPTAB_LIB_WIDEN
);
773 else if (branch_operator (cmp
, VOIDmode
))
775 /* Swap the operands to make const0 second. */
776 if (op0
== const0_rtx
)
783 case LT
: code
= GE
; break;
784 case GE
: code
= LT
; break;
785 default: gcc_unreachable ();
789 if (op1
!= const0_rtx
)
795 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
798 if (TARGET_HARD_FLOAT
&& (branch_type
== CMP_SF
))
799 return gen_float_relational (code
, op0
, op1
);
806 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
809 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
811 if (!(cmp
= gen_conditional_move (operands
[1])))
815 gen_fn
= (branch_type
== CMP_SI
816 ? gen_movsfcc_internal0
817 : gen_movsfcc_internal1
);
819 gen_fn
= (branch_type
== CMP_SI
820 ? gen_movsicc_internal0
821 : gen_movsicc_internal1
);
823 emit_insn (gen_fn (operands
[0], XEXP (cmp
, 0),
824 operands
[2], operands
[3], cmp
));
830 xtensa_expand_scc (rtx
*operands
)
832 rtx dest
= operands
[0];
833 rtx cmp
= operands
[1];
834 rtx one_tmp
, zero_tmp
;
835 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
837 if (!(cmp
= gen_conditional_move (cmp
)))
840 one_tmp
= gen_reg_rtx (SImode
);
841 zero_tmp
= gen_reg_rtx (SImode
);
842 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
843 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
845 gen_fn
= (branch_type
== CMP_SI
846 ? gen_movsicc_internal0
847 : gen_movsicc_internal1
);
848 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
853 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
854 for the output, i.e., the input operands are twice as big as MODE. */
857 xtensa_split_operand_pair (rtx operands
[4], enum machine_mode mode
)
859 switch (GET_CODE (operands
[1]))
862 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
863 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
867 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
868 operands
[2] = adjust_address (operands
[1], mode
, 0);
873 split_double (operands
[1], &operands
[2], &operands
[3]);
880 switch (GET_CODE (operands
[0]))
883 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
884 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
888 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
889 operands
[0] = adjust_address (operands
[0], mode
, 0);
898 /* Emit insns to move operands[1] into operands[0].
899 Return 1 if we have written out everything that needs to be done to
900 do the move. Otherwise, return 0 and the caller will emit the move
904 xtensa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
906 if (CONSTANT_P (operands
[1])
907 && (GET_CODE (operands
[1]) != CONST_INT
908 || !xtensa_simm12b (INTVAL (operands
[1]))))
911 operands
[1] = force_const_mem (SImode
, operands
[1]);
913 /* PC-relative loads are always SImode, and CONST16 is only
914 supported in the movsi pattern, so add a SUBREG for any other
919 if (register_operand (operands
[0], mode
))
921 operands
[0] = simplify_gen_subreg (SImode
, operands
[0], mode
, 0);
922 emit_move_insn (operands
[0], operands
[1]);
927 operands
[1] = force_reg (SImode
, operands
[1]);
928 operands
[1] = gen_lowpart_SUBREG (mode
, operands
[1]);
933 if (!(reload_in_progress
| reload_completed
)
934 && !xtensa_valid_move (mode
, operands
))
935 operands
[1] = force_reg (mode
, operands
[1]);
937 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
939 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
940 instruction won't be recognized after reload, so we remove the
941 subreg and adjust mem accordingly. */
942 if (reload_in_progress
)
944 operands
[0] = fixup_subreg_mem (operands
[0]);
945 operands
[1] = fixup_subreg_mem (operands
[1]);
952 fixup_subreg_mem (rtx x
)
954 if (GET_CODE (x
) == SUBREG
955 && GET_CODE (SUBREG_REG (x
)) == REG
956 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
959 gen_rtx_SUBREG (GET_MODE (x
),
960 reg_equiv_mem
[REGNO (SUBREG_REG (x
))],
962 x
= alter_subreg (&temp
);
968 /* Check if an incoming argument in a7 is expected to be used soon and
969 if OPND is a register or register pair that includes a7. If so,
970 create a new pseudo and copy a7 into that pseudo at the very
971 beginning of the function, followed by the special "set_frame_ptr"
972 unspec_volatile insn. The return value is either the original
973 operand, if it is not a7, or the new pseudo containing a copy of
974 the incoming argument. This is necessary because the register
975 allocator will ignore conflicts with a7 and may either assign some
976 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
977 the incoming argument in a7. By copying the argument out of a7 as
978 the very first thing, and then immediately following that with an
979 unspec_volatile to keep the scheduler away, we should avoid any
980 problems. Putting the set_frame_ptr insn at the beginning, with
981 only the a7 copy before it, also makes it easier for the prologue
982 expander to initialize the frame pointer after the a7 copy and to
983 fix up the a7 copy to use the stack pointer instead of the frame
987 xtensa_copy_incoming_a7 (rtx opnd
)
991 enum machine_mode mode
;
993 if (!cfun
->machine
->need_a7_copy
)
996 /* This function should never be called again once a7 has been copied. */
997 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
999 mode
= GET_MODE (opnd
);
1001 /* The operand using a7 may come in a later instruction, so just return
1002 the original operand if it doesn't use a7. */
1004 if (GET_CODE (reg
) == SUBREG
)
1006 gcc_assert (SUBREG_BYTE (reg
) == 0);
1007 reg
= SUBREG_REG (reg
);
1009 if (GET_CODE (reg
) != REG
1010 || REGNO (reg
) > A7_REG
1011 || REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) <= A7_REG
)
1014 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1015 gcc_assert (REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) - 1 == A7_REG
);
1017 cfun
->machine
->need_a7_copy
= false;
1019 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1020 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1023 tmp
= gen_reg_rtx (mode
);
1029 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1030 gen_rtx_REG (SImode
, A7_REG
- 1)));
1031 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1032 gen_raw_REG (SImode
, A7_REG
)));
1035 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1038 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1041 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1044 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1050 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1051 entry_insns
= get_insns ();
1054 if (cfun
->machine
->vararg_a7
)
1056 /* This is called from within builtin_saveregs, which will insert the
1057 saveregs code at the function entry, ahead of anything placed at
1058 the function entry now. Instead, save the sequence to be inserted
1059 at the beginning of the saveregs code. */
1060 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1064 /* Put entry_insns after the NOTE that starts the function. If
1065 this is inside a start_sequence, make the outer-level insn
1066 chain current, so the code is placed at the start of the
1068 push_topmost_sequence ();
1069 /* Do not use entry_of_function() here. This is called from within
1070 expand_function_start, when the CFG still holds GIMPLE. */
1071 emit_insn_after (entry_insns
, get_insns ());
1072 pop_topmost_sequence ();
1079 /* Try to expand a block move operation to a sequence of RTL move
1080 instructions. If not optimizing, or if the block size is not a
1081 constant, or if the block is too large, the expansion fails and GCC
1082 falls back to calling memcpy().
1084 operands[0] is the destination
1085 operands[1] is the source
1086 operands[2] is the length
1087 operands[3] is the alignment */
1090 xtensa_expand_block_move (rtx
*operands
)
1092 static const enum machine_mode mode_from_align
[] =
1094 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1097 rtx dst_mem
= operands
[0];
1098 rtx src_mem
= operands
[1];
1099 HOST_WIDE_INT bytes
, align
;
1100 int num_pieces
, move_ratio
;
1102 enum machine_mode mode
[2];
1111 /* If this is not a fixed size move, just call memcpy. */
1112 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1115 bytes
= INTVAL (operands
[2]);
1116 align
= INTVAL (operands
[3]);
1118 /* Anything to move? */
1122 if (align
> MOVE_MAX
)
1125 /* Decide whether to expand inline based on the optimization level. */
1128 move_ratio
= LARGEST_MOVE_RATIO
;
1129 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1130 if (num_pieces
> move_ratio
)
1133 x
= XEXP (dst_mem
, 0);
1136 x
= force_reg (Pmode
, x
);
1137 dst_mem
= replace_equiv_address (dst_mem
, x
);
1140 x
= XEXP (src_mem
, 0);
1143 x
= force_reg (Pmode
, x
);
1144 src_mem
= replace_equiv_address (src_mem
, x
);
1147 active
[0] = active
[1] = false;
1158 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1159 next_amount
= MIN (next_amount
, align
);
1161 amount
[next
] = next_amount
;
1162 mode
[next
] = mode_from_align
[next_amount
];
1163 temp
[next
] = gen_reg_rtx (mode
[next
]);
1165 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1166 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1168 offset_ld
+= next_amount
;
1169 bytes
-= next_amount
;
1170 active
[next
] = true;
1175 active
[phase
] = false;
1177 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1178 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1180 offset_st
+= amount
[phase
];
1183 while (active
[next
]);
1190 xtensa_expand_nonlocal_goto (rtx
*operands
)
1192 rtx goto_handler
= operands
[1];
1193 rtx containing_fp
= operands
[3];
1195 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1196 is too big to generate in-line. */
1198 if (GET_CODE (containing_fp
) != REG
)
1199 containing_fp
= force_reg (Pmode
, containing_fp
);
1201 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1203 containing_fp
, Pmode
,
1204 goto_handler
, Pmode
);
1208 static struct machine_function
*
1209 xtensa_init_machine_status (void)
1211 return ggc_alloc_cleared (sizeof (struct machine_function
));
1215 /* Shift VAL of mode MODE left by COUNT bits. */
1218 xtensa_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
1220 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1221 NULL_RTX
, 1, OPTAB_DIRECT
);
1222 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1223 NULL_RTX
, 1, OPTAB_DIRECT
);
1227 /* Structure to hold the initial parameters for a compare_and_swap operation
1228 in HImode and QImode. */
1230 struct alignment_context
1232 rtx memsi
; /* SI aligned memory location. */
1233 rtx shift
; /* Bit offset with regard to lsb. */
1234 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1235 rtx modemaski
; /* ~modemask */
1239 /* Initialize structure AC for word access to HI and QI mode memory. */
1242 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1244 enum machine_mode mode
= GET_MODE (mem
);
1245 rtx byteoffset
= NULL_RTX
;
1246 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1249 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1252 /* Alignment is unknown. */
1255 /* Force the address into a register. */
1256 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1258 /* Align it to SImode. */
1259 align
= expand_simple_binop (Pmode
, AND
, addr
,
1260 GEN_INT (-GET_MODE_SIZE (SImode
)),
1261 NULL_RTX
, 1, OPTAB_DIRECT
);
1263 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1264 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1265 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1266 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1268 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1269 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1270 NULL_RTX
, 1, OPTAB_DIRECT
);
1273 /* Calculate shiftcount. */
1274 if (TARGET_BIG_ENDIAN
)
1276 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1278 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1279 NULL_RTX
, 1, OPTAB_DIRECT
);
1284 ac
->shift
= NULL_RTX
;
1286 ac
->shift
= byteoffset
;
1289 if (ac
->shift
!= NULL_RTX
)
1291 /* Shift is the byte count, but we need the bitcount. */
1292 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
,
1293 GEN_INT (BITS_PER_UNIT
),
1294 NULL_RTX
, 1, OPTAB_DIRECT
);
1295 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1296 GEN_INT (GET_MODE_MASK (mode
)),
1298 NULL_RTX
, 1, OPTAB_DIRECT
);
1301 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1303 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1307 /* Expand an atomic compare and swap operation for HImode and QImode.
1308 MEM is the memory location, CMP the old value to compare MEM with
1309 and NEW the value to set if CMP == MEM. */
1312 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx
new)
1314 enum machine_mode mode
= GET_MODE (mem
);
1315 struct alignment_context ac
;
1316 rtx tmp
, cmpv
, newv
, val
;
1317 rtx oldval
= gen_reg_rtx (SImode
);
1318 rtx res
= gen_reg_rtx (SImode
);
1319 rtx csloop
= gen_label_rtx ();
1320 rtx csend
= gen_label_rtx ();
1322 init_alignment_context (&ac
, mem
);
1324 if (ac
.shift
!= NULL_RTX
)
1326 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1327 new = xtensa_expand_mask_and_shift (new, mode
, ac
.shift
);
1330 /* Load the surrounding word into VAL with the MEM value masked out. */
1331 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1332 ac
.modemaski
, NULL_RTX
, 1,
1334 emit_label (csloop
);
1336 /* Patch CMP and NEW into VAL at correct position. */
1337 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1338 NULL_RTX
, 1, OPTAB_DIRECT
));
1339 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new, val
,
1340 NULL_RTX
, 1, OPTAB_DIRECT
));
1342 /* Jump to end if we're done. */
1343 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1344 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1346 /* Check for changes outside mode. */
1347 emit_move_insn (oldval
, val
);
1348 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1349 val
, 1, OPTAB_DIRECT
);
1351 emit_move_insn (val
, tmp
);
1353 /* Loop internal if so. */
1354 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1358 /* Return the correct part of the bitfield. */
1359 convert_move (target
,
1360 (ac
.shift
== NULL_RTX
? res
1361 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1362 NULL_RTX
, 1, OPTAB_DIRECT
)),
1367 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1368 the default expansion works fine for SImode). MEM is the memory location
1369 and VAL the value to play with. If AFTER is true then store the value
1370 MEM holds after the operation, if AFTER is false then store the value MEM
1371 holds before the operation. If TARGET is zero then discard that value, else
1372 store it to TARGET. */
1375 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1378 enum machine_mode mode
= GET_MODE (mem
);
1379 struct alignment_context ac
;
1380 rtx csloop
= gen_label_rtx ();
1382 rtx old
= gen_reg_rtx (SImode
);
1383 rtx
new = gen_reg_rtx (SImode
);
1384 rtx orig
= NULL_RTX
;
1386 init_alignment_context (&ac
, mem
);
1388 /* Prepare values before the compare-and-swap loop. */
1389 if (ac
.shift
!= NULL_RTX
)
1390 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1395 orig
= gen_reg_rtx (SImode
);
1396 convert_move (orig
, val
, 1);
1404 case MULT
: /* NAND */
1406 /* val = "11..1<val>11..1" */
1407 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1408 NULL_RTX
, 1, OPTAB_DIRECT
);
1415 /* Load full word. Subsequent loads are performed by S32C1I. */
1416 cmp
= force_reg (SImode
, ac
.memsi
);
1418 emit_label (csloop
);
1419 emit_move_insn (old
, cmp
);
1425 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1426 NULL_RTX
, 1, OPTAB_DIRECT
);
1427 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1428 NULL_RTX
, 1, OPTAB_DIRECT
);
1431 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1432 NULL_RTX
, 1, OPTAB_DIRECT
);
1433 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1434 new, 1, OPTAB_DIRECT
);
1440 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1441 new, 1, OPTAB_DIRECT
);
1444 case MULT
: /* NAND */
1445 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1446 NULL_RTX
, 1, OPTAB_DIRECT
);
1447 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1448 new, 1, OPTAB_DIRECT
);
1456 emit_move_insn (new, tmp
);
1457 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new));
1458 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1462 tmp
= (after
? new : cmp
);
1463 convert_move (target
,
1464 (ac
.shift
== NULL_RTX
? tmp
1465 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1466 NULL_RTX
, 1, OPTAB_DIRECT
)),
1473 xtensa_setup_frame_addresses (void)
1475 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1476 cfun
->machine
->accesses_prev_frame
= 1;
1479 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1484 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1485 a comment showing where the end of the loop is. However, if there is a
1486 label or a branch at the end of the loop then we need to place a nop
1487 there. If the loop ends with a label we need the nop so that branches
1488 targeting that label will target the nop (and thus remain in the loop),
1489 instead of targeting the instruction after the loop (and thus exiting
1490 the loop). If the loop ends with a branch, we need the nop in case the
1491 branch is targeting a location inside the loop. When the branch
1492 executes it will cause the loop count to be decremented even if it is
1493 taken (because it is the last instruction in the loop), so we need to
1494 nop after the branch to prevent the loop count from being decremented
1495 when the branch is taken. */
1498 xtensa_emit_loop_end (rtx insn
, rtx
*operands
)
1502 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1504 switch (GET_CODE (insn
))
1511 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1517 rtx body
= PATTERN (insn
);
1519 if (GET_CODE (body
) == JUMP_INSN
)
1521 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1524 else if ((GET_CODE (body
) != USE
)
1525 && (GET_CODE (body
) != CLOBBER
))
1532 output_asm_insn ("# loop end for %0", operands
);
1537 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1539 static char result
[64];
1543 code
= GET_CODE (operands
[3]);
1546 case EQ
: op
= inverted
? "ne" : "eq"; break;
1547 case NE
: op
= inverted
? "eq" : "ne"; break;
1548 case LT
: op
= inverted
? "ge" : "lt"; break;
1549 case GE
: op
= inverted
? "lt" : "ge"; break;
1550 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1551 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1552 default: gcc_unreachable ();
1557 if (INTVAL (operands
[1]) == 0)
1558 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1559 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1561 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1564 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1571 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1573 static char result
[64];
1576 switch (GET_CODE (operands
[3]))
1578 case EQ
: op
= inverted
? "bs" : "bc"; break;
1579 case NE
: op
= inverted
? "bc" : "bs"; break;
1580 default: gcc_unreachable ();
1585 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1586 operands
[1] = GEN_INT (bitnum
);
1587 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1590 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1597 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1599 static char result
[64];
1603 code
= GET_CODE (operands
[4]);
1608 case EQ
: op
= inverted
? "t" : "f"; break;
1609 case NE
: op
= inverted
? "f" : "t"; break;
1610 default: gcc_unreachable ();
1617 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1618 case NE
: op
= inverted
? "eqz" : "nez"; break;
1619 case LT
: op
= inverted
? "gez" : "ltz"; break;
1620 case GE
: op
= inverted
? "ltz" : "gez"; break;
1621 default: gcc_unreachable ();
1625 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1626 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1632 xtensa_emit_call (int callop
, rtx
*operands
)
1634 static char result
[64];
1635 rtx tgt
= operands
[callop
];
1637 if (GET_CODE (tgt
) == CONST_INT
)
1638 sprintf (result
, "call8\t0x%lx", INTVAL (tgt
));
1639 else if (register_operand (tgt
, VOIDmode
))
1640 sprintf (result
, "callx8\t%%%d", callop
);
1642 sprintf (result
, "call8\t%%%d", callop
);
1649 xtensa_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
1651 /* Allow constant pool addresses. */
1652 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1653 && ! TARGET_CONST16
&& constantpool_address_p (addr
))
1656 while (GET_CODE (addr
) == SUBREG
)
1657 addr
= SUBREG_REG (addr
);
1659 /* Allow base registers. */
1660 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1663 /* Check for "register + offset" addressing. */
1664 if (GET_CODE (addr
) == PLUS
)
1666 rtx xplus0
= XEXP (addr
, 0);
1667 rtx xplus1
= XEXP (addr
, 1);
1668 enum rtx_code code0
;
1669 enum rtx_code code1
;
1671 while (GET_CODE (xplus0
) == SUBREG
)
1672 xplus0
= SUBREG_REG (xplus0
);
1673 code0
= GET_CODE (xplus0
);
1675 while (GET_CODE (xplus1
) == SUBREG
)
1676 xplus1
= SUBREG_REG (xplus1
);
1677 code1
= GET_CODE (xplus1
);
1679 /* Swap operands if necessary so the register is first. */
1680 if (code0
!= REG
&& code1
== REG
)
1682 xplus0
= XEXP (addr
, 1);
1683 xplus1
= XEXP (addr
, 0);
1684 code0
= GET_CODE (xplus0
);
1685 code1
= GET_CODE (xplus1
);
1688 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1689 && code1
== CONST_INT
1690 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1699 xtensa_legitimize_address (rtx x
,
1700 rtx oldx ATTRIBUTE_UNUSED
,
1701 enum machine_mode mode
)
1703 if (GET_CODE (x
) == PLUS
)
1705 rtx plus0
= XEXP (x
, 0);
1706 rtx plus1
= XEXP (x
, 1);
1708 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1710 plus0
= XEXP (x
, 1);
1711 plus1
= XEXP (x
, 0);
1714 /* Try to split up the offset to use an ADDMI instruction. */
1715 if (GET_CODE (plus0
) == REG
1716 && GET_CODE (plus1
) == CONST_INT
1717 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1718 && !xtensa_simm8 (INTVAL (plus1
))
1719 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1720 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1722 rtx temp
= gen_reg_rtx (Pmode
);
1723 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1724 emit_insn (gen_rtx_SET (Pmode
, temp
,
1725 gen_rtx_PLUS (Pmode
, plus0
, addmi_offset
)));
1726 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1734 /* Return the debugger register number to use for 'regno'. */
1737 xtensa_dbx_register_number (int regno
)
1741 if (GP_REG_P (regno
))
1743 regno
-= GP_REG_FIRST
;
1746 else if (BR_REG_P (regno
))
1748 regno
-= BR_REG_FIRST
;
1751 else if (FP_REG_P (regno
))
1753 regno
-= FP_REG_FIRST
;
1756 else if (ACC_REG_P (regno
))
1758 first
= 0x200; /* Start of Xtensa special registers. */
1759 regno
= 16; /* ACCLO is special register 16. */
1762 /* When optimizing, we sometimes get asked about pseudo-registers
1763 that don't represent hard registers. Return 0 for these. */
1767 return first
+ regno
;
1771 /* Argument support functions. */
1773 /* Initialize CUMULATIVE_ARGS for a function. */
1776 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
1779 cum
->incoming
= incoming
;
1783 /* Advance the argument to the next argument position. */
1786 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
)
1791 arg_words
= &cum
->arg_words
;
1792 max
= MAX_ARGS_IN_REGISTERS
;
1794 words
= (((mode
!= BLKmode
)
1795 ? (int) GET_MODE_SIZE (mode
)
1796 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1798 if (*arg_words
< max
1799 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
1800 || *arg_words
+ words
> max
))
1803 *arg_words
+= words
;
1807 /* Return an RTL expression containing the register for the given mode,
1808 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1809 if this is an incoming argument to the current function. */
1812 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1815 int regbase
, words
, max
;
1819 arg_words
= &cum
->arg_words
;
1820 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
1821 max
= MAX_ARGS_IN_REGISTERS
;
1823 words
= (((mode
!= BLKmode
)
1824 ? (int) GET_MODE_SIZE (mode
)
1825 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1827 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
1829 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
1830 *arg_words
= (*arg_words
+ align
- 1) & -align
;
1833 if (*arg_words
+ words
> max
)
1836 regno
= regbase
+ *arg_words
;
1838 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
1839 cfun
->machine
->need_a7_copy
= true;
1841 return gen_rtx_REG (mode
, regno
);
1846 function_arg_boundary (enum machine_mode mode
, tree type
)
1848 unsigned int alignment
;
1850 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
1851 if (alignment
< PARM_BOUNDARY
)
1852 alignment
= PARM_BOUNDARY
;
1853 if (alignment
> STACK_BOUNDARY
)
1854 alignment
= STACK_BOUNDARY
;
1860 xtensa_return_in_msb (const_tree valtype
)
1862 return (TARGET_BIG_ENDIAN
1863 && AGGREGATE_TYPE_P (valtype
)
1864 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
1869 override_options (void)
1872 enum machine_mode mode
;
1874 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
1875 error ("boolean registers required for the floating-point option");
1877 /* Set up array giving whether a given register can hold a given mode. */
1878 for (mode
= VOIDmode
;
1879 mode
!= MAX_MACHINE_MODE
;
1880 mode
= (enum machine_mode
) ((int) mode
+ 1))
1882 int size
= GET_MODE_SIZE (mode
);
1883 enum mode_class
class = GET_MODE_CLASS (mode
);
1885 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1889 if (ACC_REG_P (regno
))
1890 temp
= (TARGET_MAC16
1891 && (class == MODE_INT
) && (size
<= UNITS_PER_WORD
));
1892 else if (GP_REG_P (regno
))
1893 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
1894 else if (FP_REG_P (regno
))
1895 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
1896 else if (BR_REG_P (regno
))
1897 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
1901 xtensa_hard_regno_mode_ok
[(int) mode
][regno
] = temp
;
1905 init_machine_status
= xtensa_init_machine_status
;
1907 /* Check PIC settings. PIC is only supported when using L32R
1908 instructions, and some targets need to always use PIC. */
1909 if (flag_pic
&& TARGET_CONST16
)
1910 error ("-f%s is not supported with CONST16 instructions",
1911 (flag_pic
> 1 ? "PIC" : "pic"));
1912 else if (XTENSA_ALWAYS_PIC
)
1915 error ("PIC is required but not supported with CONST16 instructions");
1918 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1921 if (flag_pic
&& !flag_pie
)
1924 /* Hot/cold partitioning does not work on this architecture, because of
1925 constant pools (the load instruction cannot necessarily reach that far).
1926 Therefore disable it on this architecture. */
1927 if (flag_reorder_blocks_and_partition
)
1929 flag_reorder_blocks_and_partition
= 0;
1930 flag_reorder_blocks
= 1;
1935 /* A C compound statement to output to stdio stream STREAM the
1936 assembler syntax for an instruction operand X. X is an RTL
1939 CODE is a value that can be used to specify one of several ways
1940 of printing the operand. It is used when identical operands
1941 must be printed differently depending on the context. CODE
1942 comes from the '%' specification that was used to request
1943 printing of the operand. If the specification was just '%DIGIT'
1944 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1945 is the ASCII code for LTR.
1947 If X is a register, this macro should print the register's name.
1948 The names can be found in an array 'reg_names' whose type is
1949 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1951 When the machine description has a specification '%PUNCT' (a '%'
1952 followed by a punctuation character), this macro is called with
1953 a null pointer for X and the punctuation character for CODE.
1955 'a', 'c', 'l', and 'n' are reserved.
1957 The Xtensa specific codes are:
1959 'd' CONST_INT, print as signed decimal
1960 'x' CONST_INT, print as signed hexadecimal
1961 'K' CONST_INT, print number of bits in mask for EXTUI
1962 'R' CONST_INT, print (X & 0x1f)
1963 'L' CONST_INT, print ((32 - X) & 0x1f)
1964 'D' REG, print second register of double-word register operand
1965 'N' MEM, print address of next word following a memory operand
1966 'v' MEM, if memory reference is volatile, output a MEMW before it
1967 't' any constant, add "@h" suffix for top 16 bits
1968 'b' any constant, add "@l" suffix for bottom 16 bits
1972 printx (FILE *file
, signed int val
)
1974 /* Print a hexadecimal value in a nice way. */
1975 if ((val
> -0xa) && (val
< 0xa))
1976 fprintf (file
, "%d", val
);
1978 fprintf (file
, "-0x%x", -val
);
1980 fprintf (file
, "0x%x", val
);
1985 print_operand (FILE *file
, rtx x
, int letter
)
1988 error ("PRINT_OPERAND null pointer");
1993 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
1994 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
1996 output_operand_lossage ("invalid %%D value");
2000 if (GET_CODE (x
) == MEM
)
2002 /* For a volatile memory reference, emit a MEMW before the
2004 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2005 fprintf (file
, "memw\n\t");
2008 output_operand_lossage ("invalid %%v value");
2012 if (GET_CODE (x
) == MEM
2013 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2015 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? SFmode
: SImode
, 4);
2016 output_address (XEXP (x
, 0));
2019 output_operand_lossage ("invalid %%N value");
2023 if (GET_CODE (x
) == CONST_INT
)
2026 unsigned val
= INTVAL (x
);
2032 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2033 fatal_insn ("invalid mask", x
);
2035 fprintf (file
, "%d", num_bits
);
2038 output_operand_lossage ("invalid %%K value");
2042 if (GET_CODE (x
) == CONST_INT
)
2043 fprintf (file
, "%ld", (32 - INTVAL (x
)) & 0x1f);
2045 output_operand_lossage ("invalid %%L value");
2049 if (GET_CODE (x
) == CONST_INT
)
2050 fprintf (file
, "%ld", INTVAL (x
) & 0x1f);
2052 output_operand_lossage ("invalid %%R value");
2056 if (GET_CODE (x
) == CONST_INT
)
2057 printx (file
, INTVAL (x
));
2059 output_operand_lossage ("invalid %%x value");
2063 if (GET_CODE (x
) == CONST_INT
)
2064 fprintf (file
, "%ld", INTVAL (x
));
2066 output_operand_lossage ("invalid %%d value");
2071 if (GET_CODE (x
) == CONST_INT
)
2073 printx (file
, INTVAL (x
));
2074 fputs (letter
== 't' ? "@h" : "@l", file
);
2076 else if (GET_CODE (x
) == CONST_DOUBLE
)
2079 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2080 if (GET_MODE (x
) == SFmode
)
2083 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2084 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2087 output_operand_lossage ("invalid %%t/%%b value");
2089 else if (GET_CODE (x
) == CONST
)
2091 /* X must be a symbolic constant on ELF. Write an expression
2092 suitable for 'const16' that sets the high or low 16 bits. */
2093 if (GET_CODE (XEXP (x
, 0)) != PLUS
2094 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2095 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2096 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2097 output_operand_lossage ("invalid %%t/%%b value");
2098 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2099 fputs (letter
== 't' ? "@h" : "@l", file
);
2100 /* There must be a non-alphanumeric character between 'h' or 'l'
2101 and the number. The '-' is added by print_operand() already. */
2102 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2104 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2108 output_addr_const (file
, x
);
2109 fputs (letter
== 't' ? "@h" : "@l", file
);
2114 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2115 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2116 else if (GET_CODE (x
) == MEM
)
2117 output_address (XEXP (x
, 0));
2118 else if (GET_CODE (x
) == CONST_INT
)
2119 fprintf (file
, "%ld", INTVAL (x
));
2121 output_addr_const (file
, x
);
2126 /* A C compound statement to output to stdio stream STREAM the
2127 assembler syntax for an instruction operand that is a memory
2128 reference whose address is ADDR. ADDR is an RTL expression. */
2131 print_operand_address (FILE *file
, rtx addr
)
2134 error ("PRINT_OPERAND_ADDRESS, null pointer");
2136 switch (GET_CODE (addr
))
2139 fatal_insn ("invalid address", addr
);
2143 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2149 rtx offset
= (rtx
)0;
2150 rtx arg0
= XEXP (addr
, 0);
2151 rtx arg1
= XEXP (addr
, 1);
2153 if (GET_CODE (arg0
) == REG
)
2158 else if (GET_CODE (arg1
) == REG
)
2164 fatal_insn ("no register in address", addr
);
2166 if (CONSTANT_P (offset
))
2168 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2169 output_addr_const (file
, offset
);
2172 fatal_insn ("address offset not a constant", addr
);
2180 output_addr_const (file
, addr
);
2187 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2189 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2191 switch (XINT (x
, 1))
2196 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2210 xtensa_output_literal (FILE *file
, rtx x
, enum machine_mode mode
, int labelno
)
2217 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2219 switch (GET_MODE_CLASS (mode
))
2222 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2224 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2228 REAL_VALUE_TO_TARGET_SINGLE (r
, value_long
[0]);
2229 if (HOST_BITS_PER_LONG
> 32)
2230 value_long
[0] &= 0xffffffff;
2231 fprintf (file
, "0x%08lx\n", value_long
[0]);
2235 REAL_VALUE_TO_TARGET_DOUBLE (r
, value_long
);
2236 if (HOST_BITS_PER_LONG
> 32)
2238 value_long
[0] &= 0xffffffff;
2239 value_long
[1] &= 0xffffffff;
2241 fprintf (file
, "0x%08lx, 0x%08lx\n",
2242 value_long
[0], value_long
[1]);
2252 case MODE_PARTIAL_INT
:
2253 size
= GET_MODE_SIZE (mode
);
2257 output_addr_const (file
, x
);
2262 split_double (x
, &first
, &second
);
2263 output_addr_const (file
, first
);
2265 output_addr_const (file
, second
);
2280 /* Return the bytes needed to compute the frame pointer from the current
2283 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2284 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2287 compute_frame_size (int size
)
2289 /* Add space for the incoming static chain value. */
2290 if (cfun
->static_chain_decl
!= NULL
)
2291 size
+= (1 * UNITS_PER_WORD
);
2293 xtensa_current_frame_size
=
2294 XTENSA_STACK_ALIGN (size
2295 + crtl
->outgoing_args_size
2296 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2297 return xtensa_current_frame_size
;
2302 xtensa_frame_pointer_required (void)
2304 /* The code to expand builtin_frame_addr and builtin_return_addr
2305 currently uses the hard_frame_pointer instead of frame_pointer.
2306 This seems wrong but maybe it's necessary for other architectures.
2307 This function is derived from the i386 code. */
2309 if (cfun
->machine
->accesses_prev_frame
)
2316 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2317 and the total number of words must be a multiple of 128 bits. */
2318 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2321 xtensa_expand_prologue (void)
2323 HOST_WIDE_INT total_size
;
2327 total_size
= compute_frame_size (get_frame_size ());
2328 size_rtx
= GEN_INT (total_size
);
2330 if (total_size
< (1 << (12+3)))
2331 insn
= emit_insn (gen_entry (size_rtx
));
2334 /* Use a8 as a temporary since a0-a7 may be live. */
2335 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2336 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2337 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2338 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2339 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2342 if (frame_pointer_needed
)
2344 if (cfun
->machine
->set_frame_ptr_insn
)
2348 push_topmost_sequence ();
2349 first
= get_insns ();
2350 pop_topmost_sequence ();
2352 /* For all instructions prior to set_frame_ptr_insn, replace
2353 hard_frame_pointer references with stack_pointer. */
2355 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2356 insn
= NEXT_INSN (insn
))
2360 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2361 hard_frame_pointer_rtx
,
2363 df_insn_rescan (insn
);
2368 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2369 stack_pointer_rtx
));
2372 /* Create a note to describe the CFA. Because this is only used to set
2373 DW_AT_frame_base for debug info, don't bother tracking changes through
2374 each instruction in the prologue. It just takes up space. */
2375 note_rtx
= gen_rtx_SET (VOIDmode
, (frame_pointer_needed
2376 ? hard_frame_pointer_rtx
2377 : stack_pointer_rtx
),
2378 plus_constant (stack_pointer_rtx
, -total_size
));
2379 RTX_FRAME_RELATED_P (insn
) = 1;
2380 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2381 note_rtx
, REG_NOTES (insn
));
2385 /* Clear variables at function end. */
2388 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
2389 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
2391 xtensa_current_frame_size
= 0;
2396 xtensa_return_addr (int count
, rtx frame
)
2398 rtx result
, retaddr
, curaddr
, label
;
2401 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
2404 rtx addr
= plus_constant (frame
, -4 * UNITS_PER_WORD
);
2405 addr
= memory_address (Pmode
, addr
);
2406 retaddr
= gen_reg_rtx (Pmode
);
2407 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
2410 /* The 2 most-significant bits of the return address on Xtensa hold
2411 the register window size. To get the real return address, these
2412 bits must be replaced with the high bits from some address in the
2415 /* Get the 2 high bits of a local label in the code. */
2416 curaddr
= gen_reg_rtx (Pmode
);
2417 label
= gen_label_rtx ();
2419 LABEL_PRESERVE_P (label
) = 1;
2420 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
2421 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
2422 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
2424 /* Clear the 2 high bits of the return address. */
2425 result
= gen_reg_rtx (Pmode
);
2426 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
2427 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
2429 /* Combine them to get the result. */
2430 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
2435 /* Create the va_list data type.
2437 This structure is set up by __builtin_saveregs. The __va_reg field
2438 points to a stack-allocated region holding the contents of the
2439 incoming argument registers. The __va_ndx field is an index
2440 initialized to the position of the first unnamed (variable)
2441 argument. This same index is also used to address the arguments
2442 passed in memory. Thus, the __va_stk field is initialized to point
2443 to the position of the first argument in memory offset to account
2444 for the arguments passed in registers and to account for the size
2445 of the argument registers not being 16-byte aligned. E.G., there
2446 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2447 for the first stack argument to have the maximal alignment of 16
2448 bytes, so we offset the __va_stk address by 32 bytes so that
2449 __va_stk[32] references the first argument on the stack. */
2452 xtensa_build_builtin_va_list (void)
2454 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
2456 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2457 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2459 f_stk
= build_decl (FIELD_DECL
, get_identifier ("__va_stk"),
2461 f_reg
= build_decl (FIELD_DECL
, get_identifier ("__va_reg"),
2463 f_ndx
= build_decl (FIELD_DECL
, get_identifier ("__va_ndx"),
2466 DECL_FIELD_CONTEXT (f_stk
) = record
;
2467 DECL_FIELD_CONTEXT (f_reg
) = record
;
2468 DECL_FIELD_CONTEXT (f_ndx
) = record
;
2470 TREE_CHAIN (record
) = type_decl
;
2471 TYPE_NAME (record
) = type_decl
;
2472 TYPE_FIELDS (record
) = f_stk
;
2473 TREE_CHAIN (f_stk
) = f_reg
;
2474 TREE_CHAIN (f_reg
) = f_ndx
;
2476 layout_type (record
);
2481 /* Save the incoming argument registers on the stack. Returns the
2482 address of the saved registers. */
2485 xtensa_builtin_saveregs (void)
2488 int arg_words
= crtl
->args
.info
.arg_words
;
2489 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
2494 /* Allocate the general-purpose register space. */
2495 gp_regs
= assign_stack_local
2496 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
2497 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
2499 /* Now store the incoming registers. */
2500 cfun
->machine
->need_a7_copy
= true;
2501 cfun
->machine
->vararg_a7
= true;
2502 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
2503 adjust_address (gp_regs
, BLKmode
,
2504 arg_words
* UNITS_PER_WORD
),
2506 gcc_assert (cfun
->machine
->vararg_a7_copy
!= 0);
2507 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
2509 return XEXP (gp_regs
, 0);
2513 /* Implement `va_start' for varargs and stdarg. We look at the
2514 current function to fill in an initial va_list. */
2517 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
2525 arg_words
= crtl
->args
.info
.arg_words
;
2527 f_stk
= TYPE_FIELDS (va_list_type_node
);
2528 f_reg
= TREE_CHAIN (f_stk
);
2529 f_ndx
= TREE_CHAIN (f_reg
);
2531 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2532 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), valist
, f_reg
, NULL_TREE
);
2533 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), valist
, f_ndx
, NULL_TREE
);
2535 /* Call __builtin_saveregs; save the result in __va_reg */
2536 u
= make_tree (sizetype
, expand_builtin_saveregs ());
2537 u
= fold_convert (ptr_type_node
, u
);
2538 t
= build2 (GIMPLE_MODIFY_STMT
, ptr_type_node
, reg
, u
);
2539 TREE_SIDE_EFFECTS (t
) = 1;
2540 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2542 /* Set the __va_stk member to ($arg_ptr - 32). */
2543 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
2544 u
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, u
, size_int (-32));
2545 t
= build2 (GIMPLE_MODIFY_STMT
, ptr_type_node
, stk
, u
);
2546 TREE_SIDE_EFFECTS (t
) = 1;
2547 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2549 /* Set the __va_ndx member. If the first variable argument is on
2550 the stack, adjust __va_ndx by 2 words to account for the extra
2551 alignment offset for __va_stk. */
2552 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
2554 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, ndx
,
2555 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
2556 TREE_SIDE_EFFECTS (t
) = 1;
2557 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2561 /* Implement `va_arg'. */
2564 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
,
2565 tree
*post_p ATTRIBUTE_UNUSED
)
2570 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
2571 tree lab_false
, lab_over
, lab_false2
;
2574 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
2576 type
= build_pointer_type (type
);
2578 /* Handle complex values as separate real and imaginary parts. */
2579 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2581 tree real_part
, imag_part
;
2583 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2585 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
2587 imag_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2589 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
2591 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
2594 f_stk
= TYPE_FIELDS (va_list_type_node
);
2595 f_reg
= TREE_CHAIN (f_stk
);
2596 f_ndx
= TREE_CHAIN (f_reg
);
2598 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2599 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), valist
, f_reg
, NULL_TREE
);
2600 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), valist
, f_ndx
, NULL_TREE
);
2602 type_size
= size_in_bytes (type
);
2603 va_size
= round_up (type_size
, UNITS_PER_WORD
);
2604 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
2607 /* First align __va_ndx if necessary for this arg:
2609 orig_ndx = (AP).__va_ndx;
2610 if (__alignof__ (TYPE) > 4 )
2611 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2612 & -__alignof__ (TYPE)); */
2614 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
2616 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2618 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
2620 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
,
2621 build_int_cst (integer_type_node
, align
- 1));
2622 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
2623 build_int_cst (integer_type_node
, -align
));
2624 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, orig_ndx
, t
);
2625 gimplify_and_add (t
, pre_p
);
2629 /* Increment __va_ndx to point past the argument:
2631 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2633 t
= fold_convert (integer_type_node
, va_size
);
2634 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
2635 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, ndx
, t
);
2636 gimplify_and_add (t
, pre_p
);
2639 /* Check if the argument is in registers:
2641 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2642 && !must_pass_in_stack (type))
2643 __array = (AP).__va_reg; */
2645 array
= create_tmp_var (ptr_type_node
, NULL
);
2648 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
2650 lab_false
= create_artificial_label ();
2651 lab_over
= create_artificial_label ();
2653 t
= build2 (GT_EXPR
, boolean_type_node
, ndx
,
2654 build_int_cst (integer_type_node
,
2655 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2656 t
= build3 (COND_EXPR
, void_type_node
, t
,
2657 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
2659 gimplify_and_add (t
, pre_p
);
2661 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, array
, reg
);
2662 gimplify_and_add (t
, pre_p
);
2664 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
2665 gimplify_and_add (t
, pre_p
);
2667 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
2668 gimplify_and_add (t
, pre_p
);
2672 /* ...otherwise, the argument is on the stack (never split between
2673 registers and the stack -- change __va_ndx if necessary):
2677 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2678 (AP).__va_ndx = 32 + __va_size (TYPE);
2679 __array = (AP).__va_stk;
2682 lab_false2
= create_artificial_label ();
2684 t
= build2 (GT_EXPR
, boolean_type_node
, orig_ndx
,
2685 build_int_cst (integer_type_node
,
2686 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2687 t
= build3 (COND_EXPR
, void_type_node
, t
,
2688 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
2690 gimplify_and_add (t
, pre_p
);
2692 t
= size_binop (PLUS_EXPR
, va_size
, size_int (32));
2693 t
= fold_convert (integer_type_node
, t
);
2694 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, ndx
, t
);
2695 gimplify_and_add (t
, pre_p
);
2697 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
2698 gimplify_and_add (t
, pre_p
);
2700 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, array
, stk
);
2701 gimplify_and_add (t
, pre_p
);
2705 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
2706 gimplify_and_add (t
, pre_p
);
2710 /* Given the base array pointer (__array) and index to the subsequent
2711 argument (__va_ndx), find the address:
2713 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2717 The results are endian-dependent because values smaller than one word
2718 are aligned differently. */
2721 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
2723 t
= fold_build2 (GE_EXPR
, boolean_type_node
, type_size
,
2724 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
2725 t
= fold_build3 (COND_EXPR
, sizetype
, t
, va_size
, type_size
);
2731 t
= fold_convert (sizetype
, ndx
);
2732 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
2733 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, array
, t
);
2735 addr
= fold_convert (build_pointer_type (type
), addr
);
2737 addr
= build_va_arg_indirect_ref (addr
);
2738 return build_va_arg_indirect_ref (addr
);
2746 XTENSA_BUILTIN_UMULSIDI3
,
2752 xtensa_init_builtins (void)
2756 ftype
= build_function_type_list (unsigned_intDI_type_node
,
2757 unsigned_intSI_type_node
,
2758 unsigned_intSI_type_node
, NULL_TREE
);
2760 add_builtin_function ("__builtin_umulsidi3", ftype
,
2761 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
2762 "__umulsidi3", NULL_TREE
);
2767 xtensa_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
2769 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2772 if (fcode
== XTENSA_BUILTIN_UMULSIDI3
)
2774 arg0
= TREE_VALUE (arglist
);
2775 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
2776 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
2777 || TARGET_MUL32_HIGH
)
2778 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
2779 fold_convert (unsigned_intDI_type_node
, arg0
),
2780 fold_convert (unsigned_intDI_type_node
, arg1
));
2785 internal_error ("bad builtin code");
2791 xtensa_expand_builtin (tree exp
, rtx target
,
2792 rtx subtarget ATTRIBUTE_UNUSED
,
2793 enum machine_mode mode ATTRIBUTE_UNUSED
,
2796 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
2797 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2799 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2800 __umulsidi3 function when the Xtensa configuration can directly
2801 implement it. If not, just call the function. */
2802 if (fcode
== XTENSA_BUILTIN_UMULSIDI3
)
2803 return expand_call (exp
, target
, ignore
);
2805 internal_error ("bad builtin code");
2811 xtensa_preferred_reload_class (rtx x
, enum reg_class
class, int isoutput
)
2813 if (!isoutput
&& CONSTANT_P (x
) && GET_CODE (x
) == CONST_DOUBLE
)
2816 /* Don't use the stack pointer or hard frame pointer for reloads!
2817 The hard frame pointer would normally be OK except that it may
2818 briefly hold an incoming argument in the prologue, and reload
2819 won't know that it is live because the hard frame pointer is
2820 treated specially. */
2822 if (class == AR_REGS
|| class == GR_REGS
)
2830 xtensa_secondary_reload_class (enum reg_class
class,
2831 enum machine_mode mode ATTRIBUTE_UNUSED
,
2832 rtx x
, int isoutput
)
2836 if (GET_CODE (x
) == SIGN_EXTEND
)
2838 regno
= xt_true_regnum (x
);
2842 if ((class == FP_REGS
|| GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
2843 && constantpool_mem_p (x
))
2847 if (ACC_REG_P (regno
))
2848 return ((class == GR_REGS
|| class == RL_REGS
) ? NO_REGS
: RL_REGS
);
2849 if (class == ACC_REG
)
2850 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
2857 order_regs_for_local_alloc (void)
2859 if (!leaf_function_p ())
2861 memcpy (reg_alloc_order
, reg_nonleaf_alloc_order
,
2862 FIRST_PSEUDO_REGISTER
* sizeof (int));
2866 int i
, num_arg_regs
;
2869 /* Use the AR registers in increasing order (skipping a0 and a1)
2870 but save the incoming argument registers for a last resort. */
2871 num_arg_regs
= crtl
->args
.info
.arg_words
;
2872 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
2873 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
2874 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
2875 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
2876 for (i
= 0; i
< num_arg_regs
; i
++)
2877 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
2879 /* List the coprocessor registers in order. */
2880 for (i
= 0; i
< BR_REG_NUM
; i
++)
2881 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
2883 /* List the FP registers in order for now. */
2884 for (i
= 0; i
< 16; i
++)
2885 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
2887 /* GCC requires that we list *all* the registers.... */
2888 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
2889 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
2890 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
2891 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
2893 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
2898 /* Some Xtensa targets support multiple bss sections. If the section
2899 name ends with ".bss", add SECTION_BSS to the flags. */
2902 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
2904 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
2907 suffix
= strrchr (name
, '.');
2908 if (suffix
&& strcmp (suffix
, ".bss") == 0)
2910 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
2911 && DECL_INITIAL (decl
) == NULL_TREE
))
2912 flags
|= SECTION_BSS
; /* @nobits */
2914 warning (0, "only uninitialized variables can be placed in a "
2922 /* The literal pool stays with the function. */
2925 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED
,
2926 rtx x ATTRIBUTE_UNUSED
,
2927 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
2929 return function_section (current_function_decl
);
2933 /* Compute a (partial) cost for rtx X. Return true if the complete
2934 cost has been computed, and false if subexpressions should be
2935 scanned. In either case, *TOTAL contains the cost result. */
2938 xtensa_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2946 if (xtensa_simm12b (INTVAL (x
)))
2953 if (xtensa_simm8 (INTVAL (x
))
2954 || xtensa_simm8x256 (INTVAL (x
)))
2961 if (xtensa_mask_immediate (INTVAL (x
)))
2968 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
2979 /* No way to tell if X is the 2nd operand so be conservative. */
2982 if (xtensa_simm12b (INTVAL (x
)))
2984 else if (TARGET_CONST16
)
2985 *total
= COSTS_N_INSNS (2);
2994 *total
= COSTS_N_INSNS (2);
3001 *total
= COSTS_N_INSNS (4);
3009 (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
) ? 2 : 1;
3011 if (memory_address_p (GET_MODE (x
), XEXP ((x
), 0)))
3012 *total
= COSTS_N_INSNS (num_words
);
3014 *total
= COSTS_N_INSNS (2*num_words
);
3020 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3024 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3028 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 3 : 2);
3034 if (GET_MODE (x
) == DImode
)
3035 *total
= COSTS_N_INSNS (2);
3037 *total
= COSTS_N_INSNS (1);
3043 if (GET_MODE (x
) == DImode
)
3044 *total
= COSTS_N_INSNS (50);
3046 *total
= COSTS_N_INSNS (1);
3051 enum machine_mode xmode
= GET_MODE (x
);
3052 if (xmode
== SFmode
)
3053 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3054 else if (xmode
== DFmode
)
3055 *total
= COSTS_N_INSNS (50);
3057 *total
= COSTS_N_INSNS (4);
3064 enum machine_mode xmode
= GET_MODE (x
);
3065 if (xmode
== SFmode
)
3066 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3067 else if (xmode
== DFmode
|| xmode
== DImode
)
3068 *total
= COSTS_N_INSNS (50);
3070 *total
= COSTS_N_INSNS (1);
3075 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 4 : 2);
3080 enum machine_mode xmode
= GET_MODE (x
);
3081 if (xmode
== SFmode
)
3082 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3083 else if (xmode
== DFmode
)
3084 *total
= COSTS_N_INSNS (50);
3085 else if (xmode
== DImode
)
3086 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3087 else if (TARGET_MUL32
)
3088 *total
= COSTS_N_INSNS (4);
3089 else if (TARGET_MAC16
)
3090 *total
= COSTS_N_INSNS (16);
3091 else if (TARGET_MUL16
)
3092 *total
= COSTS_N_INSNS (12);
3094 *total
= COSTS_N_INSNS (50);
3101 enum machine_mode xmode
= GET_MODE (x
);
3102 if (xmode
== SFmode
)
3104 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3107 else if (xmode
== DFmode
)
3109 *total
= COSTS_N_INSNS (50);
3118 enum machine_mode xmode
= GET_MODE (x
);
3119 if (xmode
== DImode
)
3120 *total
= COSTS_N_INSNS (50);
3121 else if (TARGET_DIV32
)
3122 *total
= COSTS_N_INSNS (32);
3124 *total
= COSTS_N_INSNS (50);
3129 if (GET_MODE (x
) == SFmode
)
3130 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3132 *total
= COSTS_N_INSNS (50);
3139 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3144 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3149 *total
= COSTS_N_INSNS (1);
3157 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3160 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3162 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3163 > 4 * UNITS_PER_WORD
);
3167 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3168 instruction with a minimal stack frame in order to get some free
3169 registers. Once the actual call target is known, the proper stack frame
3170 size is extracted from the ENTRY instruction at the target and the
3171 current frame is adjusted to match. The trampoline then transfers
3172 control to the instruction following the ENTRY at the target. Note:
3173 this assumes that the target begins with an ENTRY instruction. */
3176 xtensa_trampoline_template (FILE *stream
)
3178 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3180 fprintf (stream
, "\t.begin no-transform\n");
3181 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3185 /* Save the return address. */
3186 fprintf (stream
, "\tmov\ta10, a0\n");
3188 /* Use a CALL0 instruction to skip past the constants and in the
3189 process get the PC into A0. This allows PC-relative access to
3190 the constants without relying on L32R. */
3191 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3194 fprintf (stream
, "\tj\t.Lskipconsts\n");
3196 fprintf (stream
, "\t.align\t4\n");
3197 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3198 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3199 fprintf (stream
, ".Lskipconsts:\n");
3201 /* Load the static chain and function address from the trampoline. */
3204 fprintf (stream
, "\taddi\ta0, a0, 3\n");
3205 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
3206 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
3210 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
3211 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
3214 /* Store the static chain. */
3215 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
3217 /* Set the proper stack pointer value. */
3218 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
3219 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
3220 TARGET_BIG_ENDIAN
? 8 : 12);
3221 fprintf (stream
, "\tslli\ta9, a9, 3\n");
3222 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
3223 fprintf (stream
, "\tsub\ta9, sp, a9\n");
3224 fprintf (stream
, "\tmovsp\tsp, a9\n");
3227 /* Restore the return address. */
3228 fprintf (stream
, "\tmov\ta0, a10\n");
3230 /* Jump to the instruction following the ENTRY. */
3231 fprintf (stream
, "\taddi\ta8, a8, 3\n");
3232 fprintf (stream
, "\tjx\ta8\n");
3234 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3236 fprintf (stream
, "\t.byte\t0\n");
3238 fprintf (stream
, "\tnop\n");
3240 fprintf (stream
, "\t.end no-transform\n");
3245 xtensa_initialize_trampoline (rtx addr
, rtx func
, rtx chain
)
3247 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3248 int chain_off
= use_call0
? 12 : 8;
3249 int func_off
= use_call0
? 16 : 12;
3250 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (addr
, chain_off
)), chain
);
3251 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (addr
, func_off
)), func
);
3252 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
3253 0, VOIDmode
, 1, addr
, Pmode
);
3257 #include "gt-xtensa.h"