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2008-05-30 Vladimir Makarov <vmakarov@redhat.com>
[official-gcc.git] / gcc / config / mips / mips.h
blob402cd579c5cfe755dd3edaa29ca62ddc49491b94
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_R3900,
54 PROCESSOR_R6000,
55 PROCESSOR_R4000,
56 PROCESSOR_R4100,
57 PROCESSOR_R4111,
58 PROCESSOR_R4120,
59 PROCESSOR_R4130,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SB1A,
71 PROCESSOR_SR71000,
72 PROCESSOR_MAX
73 };
74
75 /* Costs of various operations on the different architectures. */
76
77 struct mips_rtx_cost_data
78 {
79 unsigned short fp_add;
80 unsigned short fp_mult_sf;
81 unsigned short fp_mult_df;
82 unsigned short fp_div_sf;
83 unsigned short fp_div_df;
84 unsigned short int_mult_si;
85 unsigned short int_mult_di;
86 unsigned short int_div_si;
87 unsigned short int_div_di;
88 unsigned short branch_cost;
89 unsigned short memory_latency;
90 };
91
92 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
93 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
94 to work on a 64-bit machine. */
95
96 #define ABI_32 0
97 #define ABI_N32 1
98 #define ABI_64 2
99 #define ABI_EABI 3
100 #define ABI_O64 4
101
102 /* Masks that affect tuning.
103
104 PTF_AVOID_BRANCHLIKELY
105 Set if it is usually not profitable to use branch-likely instructions
106 for this target, typically because the branches are always predicted
107 taken and so incur a large overhead when not taken. */
108 #define PTF_AVOID_BRANCHLIKELY 0x1
109
110 /* Information about one recognized processor. Defined here for the
111 benefit of TARGET_CPU_CPP_BUILTINS. */
112 struct mips_cpu_info {
113 /* The 'canonical' name of the processor as far as GCC is concerned.
114 It's typically a manufacturer's prefix followed by a numerical
115 designation. It should be lowercase. */
116 const char *name;
117
118 /* The internal processor number that most closely matches this
119 entry. Several processors can have the same value, if there's no
120 difference between them from GCC's point of view. */
121 enum processor_type cpu;
122
123 /* The ISA level that the processor implements. */
124 int isa;
125
126 /* A mask of PTF_* values. */
127 unsigned int tune_flags;
128 };
129
130 /* Enumerates the setting of the -mcode-readable option. */
131 enum mips_code_readable_setting {
132 CODE_READABLE_NO,
133 CODE_READABLE_PCREL,
134 CODE_READABLE_YES
135 };
136
137 /* Macros to silence warnings about numbers being signed in traditional
138 C and unsigned in ISO C when compiled on 32-bit hosts. */
139
140 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
141 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
142 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
143
144 \f
145 /* Run-time compilation parameters selecting different hardware subsets. */
146
147 /* True if we are generating position-independent VxWorks RTP code. */
148 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
149
150 /* True if the call patterns should be split into a jalr followed by
151 an instruction to restore $gp. It is only safe to split the load
152 from the call when every use of $gp is explicit. */
153
154 #define TARGET_SPLIT_CALLS \
155 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
156
157 /* True if we're generating a form of -mabicalls in which we can use
158 operators like %hi and %lo to refer to locally-binding symbols.
159 We can only do this for -mno-shared, and only then if we can use
160 relocation operations instead of assembly macros. It isn't really
161 worth using absolute sequences for 64-bit symbols because GOT
162 accesses are so much shorter. */
163
164 #define TARGET_ABSOLUTE_ABICALLS \
165 (TARGET_ABICALLS \
166 && !TARGET_SHARED \
167 && TARGET_EXPLICIT_RELOCS \
168 && !ABI_HAS_64BIT_SYMBOLS)
169
170 /* True if we can optimize sibling calls. For simplicity, we only
171 handle cases in which call_insn_operand will reject invalid
172 sibcall addresses. There are two cases in which this isn't true:
173
174 - TARGET_MIPS16. call_insn_operand accepts constant addresses
175 but there is no direct jump instruction. It isn't worth
176 using sibling calls in this case anyway; they would usually
177 be longer than normal calls.
178
179 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
180 accepts global constants, but all sibcalls must be indirect. */
181 #define TARGET_SIBCALLS \
182 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
183
184 /* True if we need to use a global offset table to access some symbols. */
185 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
186
187 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
188 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
189
190 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
191 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
192
193 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
194 This is true for both the PIC and non-PIC VxWorks RTP modes. */
195 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
196
197 /* True if .gpword or .gpdword should be used for switch tables.
198
199 Although GAS does understand .gpdword, the SGI linker mishandles
200 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
201 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
202 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
203
204 /* Generate mips16 code */
205 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
206 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
207 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
208 /* Generate mips16e register save/restore sequences. */
209 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
210
211 /* True if we're generating a form of MIPS16 code in which general
212 text loads are allowed. */
213 #define TARGET_MIPS16_TEXT_LOADS \
214 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
215
216 /* True if we're generating a form of MIPS16 code in which PC-relative
217 loads are allowed. */
218 #define TARGET_MIPS16_PCREL_LOADS \
219 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
220
221 /* Generic ISA defines. */
222 #define ISA_MIPS1 (mips_isa == 1)
223 #define ISA_MIPS2 (mips_isa == 2)
224 #define ISA_MIPS3 (mips_isa == 3)
225 #define ISA_MIPS4 (mips_isa == 4)
226 #define ISA_MIPS32 (mips_isa == 32)
227 #define ISA_MIPS32R2 (mips_isa == 33)
228 #define ISA_MIPS64 (mips_isa == 64)
229
230 /* Architecture target defines. */
231 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
232 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
233 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
234 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
235 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
236 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
237 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
238 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
239 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
240 || mips_arch == PROCESSOR_SB1A)
241 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
242 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
243 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
244 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
245
246 /* Scheduling target defines. */
247 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
248 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
249 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
250 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
251 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
252 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
253 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
254 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
255 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
256 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
257 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
258 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
259 || mips_tune == PROCESSOR_SB1A)
260 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
261 || mips_tune == PROCESSOR_24KF2_1 \
262 || mips_tune == PROCESSOR_24KF1_1)
263 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
264 || mips_tune == PROCESSOR_74KF2_1 \
265 || mips_tune == PROCESSOR_74KF1_1 \
266 || mips_tune == PROCESSOR_74KF3_2)
267 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
268
269 /* True if the pre-reload scheduler should try to create chains of
270 multiply-add or multiply-subtract instructions. For example,
271 suppose we have:
272
273 t1 = a * b
274 t2 = t1 + c * d
275 t3 = e * f
276 t4 = t3 - g * h
277
278 t1 will have a higher priority than t2 and t3 will have a higher
279 priority than t4. However, before reload, there is no dependence
280 between t1 and t3, and they can often have similar priorities.
281 The scheduler will then tend to prefer:
282
283 t1 = a * b
284 t3 = e * f
285 t2 = t1 + c * d
286 t4 = t3 - g * h
287
288 which stops us from making full use of macc/madd-style instructions.
289 This sort of situation occurs frequently in Fourier transforms and
290 in unrolled loops.
291
292 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
293 queue so that chained multiply-add and multiply-subtract instructions
294 appear ahead of any other instruction that is likely to clobber lo.
295 In the example above, if t2 and t3 become ready at the same time,
296 the code ensures that t2 is scheduled first.
297
298 Multiply-accumulate instructions are a bigger win for some targets
299 than others, so this macro is defined on an opt-in basis. */
300 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
301 || TUNE_MIPS4120 \
302 || TUNE_MIPS4130 \
303 || TUNE_24K)
304
305 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
306 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
307
308 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
309 directly accessible, while the command-line options select
310 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
311 in use. */
312 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
313 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
314
315 /* IRIX specific stuff. */
316 #define TARGET_IRIX 0
317 #define TARGET_IRIX6 0
318
319 /* Define preprocessor macros for the -march and -mtune options.
320 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
321 processor. If INFO's canonical name is "foo", define PREFIX to
322 be "foo", and define an additional macro PREFIX_FOO. */
323 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
324 do \
325 { \
326 char *macro, *p; \
327 \
328 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
329 for (p = macro; *p != 0; p++) \
330 *p = TOUPPER (*p); \
331 \
332 builtin_define (macro); \
333 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
334 free (macro); \
335 } \
336 while (0)
337
338 /* Target CPU builtins. */
339 #define TARGET_CPU_CPP_BUILTINS() \
340 do \
341 { \
342 /* Everyone but IRIX defines this to mips. */ \
343 if (!TARGET_IRIX) \
344 builtin_assert ("machine=mips"); \
345 \
346 builtin_assert ("cpu=mips"); \
347 builtin_define ("__mips__"); \
348 builtin_define ("_mips"); \
349 \
350 /* We do this here because __mips is defined below and so we \
351 can't use builtin_define_std. We don't ever want to define \
352 "mips" for VxWorks because some of the VxWorks headers \
353 construct include filenames from a root directory macro, \
354 an architecture macro and a filename, where the architecture \
355 macro expands to 'mips'. If we define 'mips' to 1, the \
356 architecture macro expands to 1 as well. */ \
357 if (!flag_iso && !TARGET_VXWORKS) \
358 builtin_define ("mips"); \
359 \
360 if (TARGET_64BIT) \
361 builtin_define ("__mips64"); \
362 \
363 if (!TARGET_IRIX) \
364 { \
365 /* Treat _R3000 and _R4000 like register-size \
366 defines, which is how they've historically \
367 been used. */ \
368 if (TARGET_64BIT) \
369 { \
370 builtin_define_std ("R4000"); \
371 builtin_define ("_R4000"); \
372 } \
373 else \
374 { \
375 builtin_define_std ("R3000"); \
376 builtin_define ("_R3000"); \
377 } \
378 } \
379 if (TARGET_FLOAT64) \
380 builtin_define ("__mips_fpr=64"); \
381 else \
382 builtin_define ("__mips_fpr=32"); \
383 \
384 if (TARGET_MIPS16) \
385 builtin_define ("__mips16"); \
386 \
387 if (TARGET_MIPS3D) \
388 builtin_define ("__mips3d"); \
389 \
390 if (TARGET_SMARTMIPS) \
391 builtin_define ("__mips_smartmips"); \
392 \
393 if (TARGET_DSP) \
394 { \
395 builtin_define ("__mips_dsp"); \
396 if (TARGET_DSPR2) \
397 { \
398 builtin_define ("__mips_dspr2"); \
399 builtin_define ("__mips_dsp_rev=2"); \
400 } \
401 else \
402 builtin_define ("__mips_dsp_rev=1"); \
403 } \
404 \
405 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
406 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
407 \
408 if (ISA_MIPS1) \
409 { \
410 builtin_define ("__mips=1"); \
411 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
412 } \
413 else if (ISA_MIPS2) \
414 { \
415 builtin_define ("__mips=2"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
417 } \
418 else if (ISA_MIPS3) \
419 { \
420 builtin_define ("__mips=3"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
422 } \
423 else if (ISA_MIPS4) \
424 { \
425 builtin_define ("__mips=4"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
427 } \
428 else if (ISA_MIPS32) \
429 { \
430 builtin_define ("__mips=32"); \
431 builtin_define ("__mips_isa_rev=1"); \
432 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
433 } \
434 else if (ISA_MIPS32R2) \
435 { \
436 builtin_define ("__mips=32"); \
437 builtin_define ("__mips_isa_rev=2"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
439 } \
440 else if (ISA_MIPS64) \
441 { \
442 builtin_define ("__mips=64"); \
443 builtin_define ("__mips_isa_rev=1"); \
444 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
445 } \
446 \
447 switch (mips_abi) \
448 { \
449 case ABI_32: \
450 builtin_define ("_ABIO32=1"); \
451 builtin_define ("_MIPS_SIM=_ABIO32"); \
452 break; \
453 \
454 case ABI_N32: \
455 builtin_define ("_ABIN32=2"); \
456 builtin_define ("_MIPS_SIM=_ABIN32"); \
457 break; \
458 \
459 case ABI_64: \
460 builtin_define ("_ABI64=3"); \
461 builtin_define ("_MIPS_SIM=_ABI64"); \
462 break; \
463 \
464 case ABI_O64: \
465 builtin_define ("_ABIO64=4"); \
466 builtin_define ("_MIPS_SIM=_ABIO64"); \
467 break; \
468 } \
469 \
470 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
471 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
472 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
473 builtin_define_with_int_value ("_MIPS_FPSET", \
474 32 / MAX_FPRS_PER_FMT); \
475 \
476 /* These defines reflect the ABI in use, not whether the \
477 FPU is directly accessible. */ \
478 if (TARGET_HARD_FLOAT_ABI) \
479 builtin_define ("__mips_hard_float"); \
480 else \
481 builtin_define ("__mips_soft_float"); \
482 \
483 if (TARGET_SINGLE_FLOAT) \
484 builtin_define ("__mips_single_float"); \
485 \
486 if (TARGET_PAIRED_SINGLE_FLOAT) \
487 builtin_define ("__mips_paired_single_float"); \
488 \
489 if (TARGET_BIG_ENDIAN) \
490 { \
491 builtin_define_std ("MIPSEB"); \
492 builtin_define ("_MIPSEB"); \
493 } \
494 else \
495 { \
496 builtin_define_std ("MIPSEL"); \
497 builtin_define ("_MIPSEL"); \
498 } \
499 \
500 /* Macros dependent on the C dialect. */ \
501 if (preprocessing_asm_p ()) \
502 { \
503 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
504 builtin_define ("_LANGUAGE_ASSEMBLY"); \
505 } \
506 else if (c_dialect_cxx ()) \
507 { \
508 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
509 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
510 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
511 } \
512 else \
513 { \
514 builtin_define_std ("LANGUAGE_C"); \
515 builtin_define ("_LANGUAGE_C"); \
516 } \
517 if (c_dialect_objc ()) \
518 { \
519 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
520 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
521 /* Bizarre, but needed at least for Irix. */ \
522 builtin_define_std ("LANGUAGE_C"); \
523 builtin_define ("_LANGUAGE_C"); \
524 } \
525 \
526 if (mips_abi == ABI_EABI) \
527 builtin_define ("__mips_eabi"); \
528 } \
529 while (0)
530
531 /* Default target_flags if no switches are specified */
532
533 #ifndef TARGET_DEFAULT
534 #define TARGET_DEFAULT 0
535 #endif
536
537 #ifndef TARGET_CPU_DEFAULT
538 #define TARGET_CPU_DEFAULT 0
539 #endif
540
541 #ifndef TARGET_ENDIAN_DEFAULT
542 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
543 #endif
544
545 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
546 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
547 #endif
548
549 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
550 #ifndef MIPS_ISA_DEFAULT
551 #ifndef MIPS_CPU_STRING_DEFAULT
552 #define MIPS_CPU_STRING_DEFAULT "from-abi"
553 #endif
554 #endif
555
556 #ifdef IN_LIBGCC2
557 #undef TARGET_64BIT
558 /* Make this compile time constant for libgcc2 */
559 #ifdef __mips64
560 #define TARGET_64BIT 1
561 #else
562 #define TARGET_64BIT 0
563 #endif
564 #endif /* IN_LIBGCC2 */
565
566 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
567 when compiled with hardware floating point. This is because MIPS16
568 code cannot save and restore the floating-point registers, which is
569 important if in a mixed MIPS16/non-MIPS16 environment. */
570
571 #ifdef IN_LIBGCC2
572 #if __mips_hard_float
573 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
574 #endif
575 #endif /* IN_LIBGCC2 */
576
577 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
578
579 #ifndef MULTILIB_ENDIAN_DEFAULT
580 #if TARGET_ENDIAN_DEFAULT == 0
581 #define MULTILIB_ENDIAN_DEFAULT "EL"
582 #else
583 #define MULTILIB_ENDIAN_DEFAULT "EB"
584 #endif
585 #endif
586
587 #ifndef MULTILIB_ISA_DEFAULT
588 # if MIPS_ISA_DEFAULT == 1
589 # define MULTILIB_ISA_DEFAULT "mips1"
590 # else
591 # if MIPS_ISA_DEFAULT == 2
592 # define MULTILIB_ISA_DEFAULT "mips2"
593 # else
594 # if MIPS_ISA_DEFAULT == 3
595 # define MULTILIB_ISA_DEFAULT "mips3"
596 # else
597 # if MIPS_ISA_DEFAULT == 4
598 # define MULTILIB_ISA_DEFAULT "mips4"
599 # else
600 # if MIPS_ISA_DEFAULT == 32
601 # define MULTILIB_ISA_DEFAULT "mips32"
602 # else
603 # if MIPS_ISA_DEFAULT == 33
604 # define MULTILIB_ISA_DEFAULT "mips32r2"
605 # else
606 # if MIPS_ISA_DEFAULT == 64
607 # define MULTILIB_ISA_DEFAULT "mips64"
608 # else
609 # define MULTILIB_ISA_DEFAULT "mips1"
610 # endif
611 # endif
612 # endif
613 # endif
614 # endif
615 # endif
616 # endif
617 #endif
618
619 #ifndef MULTILIB_DEFAULTS
620 #define MULTILIB_DEFAULTS \
621 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
622 #endif
623
624 /* We must pass -EL to the linker by default for little endian embedded
625 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
626 linker will default to using big-endian output files. The OUTPUT_FORMAT
627 line must be in the linker script, otherwise -EB/-EL will not work. */
628
629 #ifndef ENDIAN_SPEC
630 #if TARGET_ENDIAN_DEFAULT == 0
631 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
632 #else
633 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
634 #endif
635 #endif
636
637 /* A spec condition that matches all non-mips16 -mips arguments. */
638
639 #define MIPS_ISA_LEVEL_OPTION_SPEC \
640 "mips1|mips2|mips3|mips4|mips32*|mips64*"
641
642 /* A spec condition that matches all non-mips16 architecture arguments. */
643
644 #define MIPS_ARCH_OPTION_SPEC \
645 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
646
647 /* A spec that infers a -mips argument from an -march argument,
648 or injects the default if no architecture is specified. */
649
650 #define MIPS_ISA_LEVEL_SPEC \
651 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
652 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
653 %{march=mips2|march=r6000:-mips2} \
654 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
655 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
656 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
657 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
658 |march=34k*|march=74k*: -mips32r2} \
659 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
660 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
661
662 /* A spec that infers a -mhard-float or -msoft-float setting from an
663 -march argument. Note that soft-float and hard-float code are not
664 link-compatible. */
665
666 #define MIPS_ARCH_FLOAT_SPEC \
667 "%{mhard-float|msoft-float|march=mips*:; \
668 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
669 |march=34kc|march=74kc|march=5kc: -msoft-float; \
670 march=*: -mhard-float}"
671
672 /* A spec condition that matches 32-bit options. It only works if
673 MIPS_ISA_LEVEL_SPEC has been applied. */
674
675 #define MIPS_32BIT_OPTION_SPEC \
676 "mips1|mips2|mips32*|mgp32"
677
678 /* Support for a compile-time default CPU, et cetera. The rules are:
679 --with-arch is ignored if -march is specified or a -mips is specified
680 (other than -mips16).
681 --with-tune is ignored if -mtune is specified.
682 --with-abi is ignored if -mabi is specified.
683 --with-float is ignored if -mhard-float or -msoft-float are
684 specified.
685 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
686 specified. */
687 #define OPTION_DEFAULT_SPECS \
688 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
689 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
690 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
691 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
692 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
693 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }
694
695
696 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
697 && ISA_HAS_COND_TRAP)
698
699 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
700
701 /* True if the ABI can only work with 64-bit integer registers. We
702 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
703 otherwise floating-point registers must also be 64-bit. */
704 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
705
706 /* Likewise for 32-bit regs. */
707 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
708
709 /* True if symbols are 64 bits wide. At present, n64 is the only
710 ABI for which this is true. */
711 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
712
713 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
714 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
715 || ISA_MIPS4 \
716 || ISA_MIPS64)
717
718 /* ISA has branch likely instructions (e.g. mips2). */
719 /* Disable branchlikely for tx39 until compare rewrite. They haven't
720 been generated up to this point. */
721 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
722
723 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
724 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
725 || TARGET_MIPS5400 \
726 || TARGET_MIPS5500 \
727 || TARGET_MIPS7000 \
728 || TARGET_MIPS9000 \
729 || TARGET_MAD \
730 || ISA_MIPS32 \
731 || ISA_MIPS32R2 \
732 || ISA_MIPS64) \
733 && !TARGET_MIPS16)
734
735 /* ISA has the conditional move instructions introduced in mips4. */
736 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
737 || ISA_MIPS32 \
738 || ISA_MIPS32R2 \
739 || ISA_MIPS64) \
740 && !TARGET_MIPS5500 \
741 && !TARGET_MIPS16)
742
743 /* ISA has LDC1 and SDC1. */
744 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
745
746 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
747 branch on CC, and move (both FP and non-FP) on CC. */
748 #define ISA_HAS_8CC (ISA_MIPS4 \
749 || ISA_MIPS32 \
750 || ISA_MIPS32R2 \
751 || ISA_MIPS64)
752
753 /* This is a catch all for other mips4 instructions: indexed load, the
754 FP madd and msub instructions, and the FP recip and recip sqrt
755 instructions. */
756 #define ISA_HAS_FP4 ((ISA_MIPS4 \
757 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
758 || ISA_MIPS64) \
759 && !TARGET_MIPS16)
760
761 /* ISA has paired-single instructions. */
762 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64)
763
764 /* ISA has conditional trap instructions. */
765 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
766 && !TARGET_MIPS16)
767
768 /* ISA has integer multiply-accumulate instructions, madd and msub. */
769 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
770 || ISA_MIPS32R2 \
771 || ISA_MIPS64) \
772 && !TARGET_MIPS16)
773
774 /* Integer multiply-accumulate instructions should be generated. */
775 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
776
777 /* ISA has floating-point nmadd and nmsub instructions for mode MODE. */
778 #define ISA_HAS_NMADD_NMSUB(MODE) \
779 ((ISA_MIPS4 \
780 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
781 || ISA_MIPS64) \
782 && (!TARGET_MIPS5400 || TARGET_MAD) \
783 && !TARGET_MIPS16)
784
785 /* ISA has count leading zeroes/ones instruction (not implemented). */
786 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
787 || ISA_MIPS32R2 \
788 || ISA_MIPS64) \
789 && !TARGET_MIPS16)
790
791 /* ISA has three operand multiply instructions that put
792 the high part in an accumulator: mulhi or mulhiu. */
793 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
794 || TARGET_MIPS5500 \
795 || TARGET_SR71K) \
796 && !TARGET_MIPS16)
797
798 /* ISA has three operand multiply instructions that
799 negates the result and puts the result in an accumulator. */
800 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
801 || TARGET_MIPS5500 \
802 || TARGET_SR71K) \
803 && !TARGET_MIPS16)
804
805 /* ISA has three operand multiply instructions that subtracts the
806 result from a 4th operand and puts the result in an accumulator. */
807 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
808 || TARGET_MIPS5500 \
809 || TARGET_SR71K) \
810 && !TARGET_MIPS16)
811
812 /* ISA has three operand multiply instructions that the result
813 from a 4th operand and puts the result in an accumulator. */
814 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
815 || TARGET_MIPS4130 \
816 || TARGET_MIPS5400 \
817 || TARGET_MIPS5500 \
818 || TARGET_SR71K) \
819 && !TARGET_MIPS16)
820
821 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
822 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
823 || TARGET_MIPS4130) \
824 && !TARGET_MIPS16)
825
826 /* ISA has the "ror" (rotate right) instructions. */
827 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
828 || TARGET_MIPS5400 \
829 || TARGET_MIPS5500 \
830 || TARGET_SR71K \
831 || TARGET_SMARTMIPS) \
832 && !TARGET_MIPS16)
833
834 /* ISA has data prefetch instructions. This controls use of 'pref'. */
835 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
836 || ISA_MIPS32 \
837 || ISA_MIPS32R2 \
838 || ISA_MIPS64) \
839 && !TARGET_MIPS16)
840
841 /* ISA has data indexed prefetch instructions. This controls use of
842 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
843 (prefx is a cop1x instruction, so can only be used if FP is
844 enabled.) */
845 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
846 || ISA_MIPS32R2 \
847 || ISA_MIPS64) \
848 && !TARGET_MIPS16)
849
850 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
851 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
852 also requires TARGET_DOUBLE_FLOAT. */
853 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
854
855 /* ISA includes the MIPS32r2 seb and seh instructions. */
856 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
857 && !TARGET_MIPS16)
858
859 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
860 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
861 && !TARGET_MIPS16)
862
863 /* ISA has instructions for accessing top part of 64-bit fp regs. */
864 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
865
866 /* ISA has lwxs instruction (load w/scaled index address. */
867 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
868
869 /* The DSP ASE is available. */
870 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
871
872 /* Revision 2 of the DSP ASE is available. */
873 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
874
875 /* True if the result of a load is not available to the next instruction.
876 A nop will then be needed between instructions like "lw $4,..."
877 and "addiu $4,$4,1". */
878 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
879 && !TARGET_MIPS3900 \
880 && !TARGET_MIPS16)
881
882 /* Likewise mtc1 and mfc1. */
883 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
884
885 /* Likewise floating-point comparisons. */
886 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
887
888 /* True if mflo and mfhi can be immediately followed by instructions
889 which write to the HI and LO registers.
890
891 According to MIPS specifications, MIPS ISAs I, II, and III need
892 (at least) two instructions between the reads of HI/LO and
893 instructions which write them, and later ISAs do not. Contradicting
894 the MIPS specifications, some MIPS IV processor user manuals (e.g.
895 the UM for the NEC Vr5000) document needing the instructions between
896 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
897 MIPS64 and later ISAs to have the interlocks, plus any specific
898 earlier-ISA CPUs for which CPU documentation declares that the
899 instructions are really interlocked. */
900 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
901 || ISA_MIPS32R2 \
902 || ISA_MIPS64 \
903 || TARGET_MIPS5500)
904
905 /* ISA includes synci, jr.hb and jalr.hb. */
906 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
907
908 /* ISA includes sync. */
909 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
910 #define GENERATE_SYNC \
911 (target_flags_explicit & MASK_LLSC \
912 ? TARGET_LLSC && !TARGET_MIPS16 \
913 : ISA_HAS_SYNC)
914
915 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
916 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
917 instructions. */
918 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
919 #define GENERATE_LL_SC \
920 (target_flags_explicit & MASK_LLSC \
921 ? TARGET_LLSC && !TARGET_MIPS16 \
922 : ISA_HAS_LL_SC)
923 \f
924 /* Add -G xx support. */
925
926 #undef SWITCH_TAKES_ARG
927 #define SWITCH_TAKES_ARG(CHAR) \
928 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
929
930 #define OVERRIDE_OPTIONS mips_override_options ()
931
932 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
933
934 /* Show we can debug even without a frame pointer. */
935 #define CAN_DEBUG_WITHOUT_FP
936 \f
937 /* Tell collect what flags to pass to nm. */
938 #ifndef NM_FLAGS
939 #define NM_FLAGS "-Bn"
940 #endif
941
942 \f
943 #ifndef MIPS_ABI_DEFAULT
944 #define MIPS_ABI_DEFAULT ABI_32
945 #endif
946
947 /* Use the most portable ABI flag for the ASM specs. */
948
949 #if MIPS_ABI_DEFAULT == ABI_32
950 #define MULTILIB_ABI_DEFAULT "mabi=32"
951 #endif
952
953 #if MIPS_ABI_DEFAULT == ABI_O64
954 #define MULTILIB_ABI_DEFAULT "mabi=o64"
955 #endif
956
957 #if MIPS_ABI_DEFAULT == ABI_N32
958 #define MULTILIB_ABI_DEFAULT "mabi=n32"
959 #endif
960
961 #if MIPS_ABI_DEFAULT == ABI_64
962 #define MULTILIB_ABI_DEFAULT "mabi=64"
963 #endif
964
965 #if MIPS_ABI_DEFAULT == ABI_EABI
966 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
967 #endif
968
969 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
970 to the assembler. It may be overridden by subtargets. */
971 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
972 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
973 %{noasmopt:-O0} \
974 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
975 #endif
976
977 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
978 the assembler. It may be overridden by subtargets.
979
980 Beginning with gas 2.13, -mdebug must be passed to correctly handle
981 COFF debugging info. */
982
983 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
984 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
985 %{g} %{g0} %{g1} %{g2} %{g3} \
986 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
987 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
988 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
989 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
990 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
991 #endif
992
993 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
994 overridden by subtargets. */
995
996 #ifndef SUBTARGET_ASM_SPEC
997 #define SUBTARGET_ASM_SPEC ""
998 #endif
999
1000 #undef ASM_SPEC
1001 #define ASM_SPEC "\
1002 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1003 %{mips32} %{mips32r2} %{mips64} \
1004 %{mips16} %{mno-mips16:-no-mips16} \
1005 %{mips3d} %{mno-mips3d:-no-mips3d} \
1006 %{mdmx} %{mno-mdmx:-no-mdmx} \
1007 %{mdsp} %{mno-dsp} \
1008 %{mdspr2} %{mno-dspr2} \
1009 %{msmartmips} %{mno-smartmips} \
1010 %{mmt} %{mno-mt} \
1011 %{mfix-vr4120} %{mfix-vr4130} \
1012 %(subtarget_asm_optimizing_spec) \
1013 %(subtarget_asm_debugging_spec) \
1014 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1015 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1016 %{mfp32} %{mfp64} \
1017 %{mshared} %{mno-shared} \
1018 %{msym32} %{mno-sym32} \
1019 %{mtune=*} %{v} \
1020 %(subtarget_asm_spec)"
1021
1022 /* Extra switches sometimes passed to the linker. */
1023 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1024 will interpret it as a -b option. */
1025
1026 #ifndef LINK_SPEC
1027 #define LINK_SPEC "\
1028 %(endian_spec) \
1029 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1030 %{bestGnum} %{shared} %{non_shared}"
1031 #endif /* LINK_SPEC defined */
1032
1033
1034 /* Specs for the compiler proper */
1035
1036 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1037 overridden by subtargets. */
1038 #ifndef SUBTARGET_CC1_SPEC
1039 #define SUBTARGET_CC1_SPEC ""
1040 #endif
1041
1042 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1043
1044 #undef CC1_SPEC
1045 #define CC1_SPEC "\
1046 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1047 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1048 %{save-temps: } \
1049 %(subtarget_cc1_spec)"
1050
1051 /* Preprocessor specs. */
1052
1053 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1054 overridden by subtargets. */
1055 #ifndef SUBTARGET_CPP_SPEC
1056 #define SUBTARGET_CPP_SPEC ""
1057 #endif
1058
1059 #define CPP_SPEC "%(subtarget_cpp_spec)"
1060
1061 /* This macro defines names of additional specifications to put in the specs
1062 that can be used in various specifications like CC1_SPEC. Its definition
1063 is an initializer with a subgrouping for each command option.
1064
1065 Each subgrouping contains a string constant, that defines the
1066 specification name, and a string constant that used by the GCC driver
1067 program.
1068
1069 Do not define this macro if it does not need to do anything. */
1070
1071 #define EXTRA_SPECS \
1072 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1073 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1074 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1075 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1076 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1077 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1078 { "endian_spec", ENDIAN_SPEC }, \
1079 SUBTARGET_EXTRA_SPECS
1080
1081 #ifndef SUBTARGET_EXTRA_SPECS
1082 #define SUBTARGET_EXTRA_SPECS
1083 #endif
1084 \f
1085 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1086 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1087
1088 #ifndef PREFERRED_DEBUGGING_TYPE
1089 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1090 #endif
1091
1092 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1093
1094 /* By default, turn on GDB extensions. */
1095 #define DEFAULT_GDB_EXTENSIONS 1
1096
1097 /* Local compiler-generated symbols must have a prefix that the assembler
1098 understands. By default, this is $, although some targets (e.g.,
1099 NetBSD-ELF) need to override this. */
1100
1101 #ifndef LOCAL_LABEL_PREFIX
1102 #define LOCAL_LABEL_PREFIX "$"
1103 #endif
1104
1105 /* By default on the mips, external symbols do not have an underscore
1106 prepended, but some targets (e.g., NetBSD) require this. */
1107
1108 #ifndef USER_LABEL_PREFIX
1109 #define USER_LABEL_PREFIX ""
1110 #endif
1111
1112 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1113 since the length can run past this up to a continuation point. */
1114 #undef DBX_CONTIN_LENGTH
1115 #define DBX_CONTIN_LENGTH 1500
1116
1117 /* How to renumber registers for dbx and gdb. */
1118 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1119
1120 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1121 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1122
1123 /* The DWARF 2 CFA column which tracks the return address. */
1124 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1125
1126 /* Before the prologue, RA lives in r31. */
1127 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1128
1129 /* Describe how we implement __builtin_eh_return. */
1130 #define EH_RETURN_DATA_REGNO(N) \
1131 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1132
1133 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1134
1135 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1136 The default for this in 64-bit mode is 8, which causes problems with
1137 SFmode register saves. */
1138 #define DWARF_CIE_DATA_ALIGNMENT -4
1139
1140 /* Correct the offset of automatic variables and arguments. Note that
1141 the MIPS debug format wants all automatic variables and arguments
1142 to be in terms of the virtual frame pointer (stack pointer before
1143 any adjustment in the function), while the MIPS 3.0 linker wants
1144 the frame pointer to be the stack pointer after the initial
1145 adjustment. */
1146
1147 #define DEBUGGER_AUTO_OFFSET(X) \
1148 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1149 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1150 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1151 \f
1152 /* Target machine storage layout */
1153
1154 #define BITS_BIG_ENDIAN 0
1155 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1156 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1157
1158 /* Define this to set the endianness to use in libgcc2.c, which can
1159 not depend on target_flags. */
1160 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1161 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1162 #else
1163 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1164 #endif
1165
1166 #define MAX_BITS_PER_WORD 64
1167
1168 /* Width of a word, in units (bytes). */
1169 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1170 #ifndef IN_LIBGCC2
1171 #define MIN_UNITS_PER_WORD 4
1172 #endif
1173
1174 /* For MIPS, width of a floating point register. */
1175 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1176
1177 /* The number of consecutive floating-point registers needed to store the
1178 largest format supported by the FPU. */
1179 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1180
1181 /* The number of consecutive floating-point registers needed to store the
1182 smallest format supported by the FPU. */
1183 #define MIN_FPRS_PER_FMT \
1184 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1185
1186 /* The largest size of value that can be held in floating-point
1187 registers and moved with a single instruction. */
1188 #define UNITS_PER_HWFPVALUE \
1189 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1190
1191 /* The largest size of value that can be held in floating-point
1192 registers. */
1193 #define UNITS_PER_FPVALUE \
1194 (TARGET_SOFT_FLOAT_ABI ? 0 \
1195 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1196 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1197
1198 /* The number of bytes in a double. */
1199 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1200
1201 #define UNITS_PER_SIMD_WORD(MODE) \
1202 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1203
1204 /* Set the sizes of the core types. */
1205 #define SHORT_TYPE_SIZE 16
1206 #define INT_TYPE_SIZE 32
1207 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1208 #define LONG_LONG_TYPE_SIZE 64
1209
1210 #define FLOAT_TYPE_SIZE 32
1211 #define DOUBLE_TYPE_SIZE 64
1212 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1213
1214 /* Define the sizes of fixed-point types. */
1215 #define SHORT_FRACT_TYPE_SIZE 8
1216 #define FRACT_TYPE_SIZE 16
1217 #define LONG_FRACT_TYPE_SIZE 32
1218 #define LONG_LONG_FRACT_TYPE_SIZE 64
1219
1220 #define SHORT_ACCUM_TYPE_SIZE 16
1221 #define ACCUM_TYPE_SIZE 32
1222 #define LONG_ACCUM_TYPE_SIZE 64
1223 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1224 doesn't support 128-bit integers for MIPS32 currently. */
1225 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1226
1227 /* long double is not a fixed mode, but the idea is that, if we
1228 support long double, we also want a 128-bit integer type. */
1229 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1230
1231 #ifdef IN_LIBGCC2
1232 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1233 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1234 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1235 # else
1236 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1237 # endif
1238 #endif
1239
1240 /* Width in bits of a pointer. */
1241 #ifndef POINTER_SIZE
1242 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1243 #endif
1244
1245 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1246 #define PARM_BOUNDARY BITS_PER_WORD
1247
1248 /* Allocation boundary (in *bits*) for the code of a function. */
1249 #define FUNCTION_BOUNDARY 32
1250
1251 /* Alignment of field after `int : 0' in a structure. */
1252 #define EMPTY_FIELD_BOUNDARY 32
1253
1254 /* Every structure's size must be a multiple of this. */
1255 /* 8 is observed right on a DECstation and on riscos 4.02. */
1256 #define STRUCTURE_SIZE_BOUNDARY 8
1257
1258 /* There is no point aligning anything to a rounder boundary than this. */
1259 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1260
1261 /* All accesses must be aligned. */
1262 #define STRICT_ALIGNMENT 1
1263
1264 /* Define this if you wish to imitate the way many other C compilers
1265 handle alignment of bitfields and the structures that contain
1266 them.
1267
1268 The behavior is that the type written for a bit-field (`int',
1269 `short', or other integer type) imposes an alignment for the
1270 entire structure, as if the structure really did contain an
1271 ordinary field of that type. In addition, the bit-field is placed
1272 within the structure so that it would fit within such a field,
1273 not crossing a boundary for it.
1274
1275 Thus, on most machines, a bit-field whose type is written as `int'
1276 would not cross a four-byte boundary, and would force four-byte
1277 alignment for the whole structure. (The alignment used may not
1278 be four bytes; it is controlled by the other alignment
1279 parameters.)
1280
1281 If the macro is defined, its definition should be a C expression;
1282 a nonzero value for the expression enables this behavior. */
1283
1284 #define PCC_BITFIELD_TYPE_MATTERS 1
1285
1286 /* If defined, a C expression to compute the alignment given to a
1287 constant that is being placed in memory. CONSTANT is the constant
1288 and ALIGN is the alignment that the object would ordinarily have.
1289 The value of this macro is used instead of that alignment to align
1290 the object.
1291
1292 If this macro is not defined, then ALIGN is used.
1293
1294 The typical use of this macro is to increase alignment for string
1295 constants to be word aligned so that `strcpy' calls that copy
1296 constants can be done inline. */
1297
1298 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1299 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1300 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1301
1302 /* If defined, a C expression to compute the alignment for a static
1303 variable. TYPE is the data type, and ALIGN is the alignment that
1304 the object would ordinarily have. The value of this macro is used
1305 instead of that alignment to align the object.
1306
1307 If this macro is not defined, then ALIGN is used.
1308
1309 One use of this macro is to increase alignment of medium-size
1310 data to make it all fit in fewer cache lines. Another is to
1311 cause character arrays to be word-aligned so that `strcpy' calls
1312 that copy constants to character arrays can be done inline. */
1313
1314 #undef DATA_ALIGNMENT
1315 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1316 ((((ALIGN) < BITS_PER_WORD) \
1317 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1318 || TREE_CODE (TYPE) == UNION_TYPE \
1319 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1320
1321 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1322 character arrays to be word-aligned so that `strcpy' calls that copy
1323 constants to character arrays can be done inline, and 'strcmp' can be
1324 optimised to use word loads. */
1325 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1326 DATA_ALIGNMENT (TYPE, ALIGN)
1327
1328 #define PAD_VARARGS_DOWN \
1329 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1330
1331 /* Define if operations between registers always perform the operation
1332 on the full register even if a narrower mode is specified. */
1333 #define WORD_REGISTER_OPERATIONS
1334
1335 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1336 moves. All other references are zero extended. */
1337 #define LOAD_EXTEND_OP(MODE) \
1338 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1339 ? SIGN_EXTEND : ZERO_EXTEND)
1340
1341 /* Define this macro if it is advisable to hold scalars in registers
1342 in a wider mode than that declared by the program. In such cases,
1343 the value is constrained to be within the bounds of the declared
1344 type, but kept valid in the wider mode. The signedness of the
1345 extension may differ from that of the type. */
1346
1347 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1348 if (GET_MODE_CLASS (MODE) == MODE_INT \
1349 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1350 { \
1351 if ((MODE) == SImode) \
1352 (UNSIGNEDP) = 0; \
1353 (MODE) = Pmode; \
1354 }
1355
1356 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1357 Extensions of pointers to word_mode must be signed. */
1358 #define POINTERS_EXTEND_UNSIGNED false
1359
1360 /* Define if loading short immediate values into registers sign extends. */
1361 #define SHORT_IMMEDIATES_SIGN_EXTEND
1362
1363 /* The [d]clz instructions have the natural values at 0. */
1364
1365 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1366 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1367 \f
1368 /* Standard register usage. */
1369
1370 /* Number of hardware registers. We have:
1371
1372 - 32 integer registers
1373 - 32 floating point registers
1374 - 8 condition code registers
1375 - 2 accumulator registers (hi and lo)
1376 - 32 registers each for coprocessors 0, 2 and 3
1377 - 3 fake registers:
1378 - ARG_POINTER_REGNUM
1379 - FRAME_POINTER_REGNUM
1380 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1381 - 3 dummy entries that were used at various times in the past.
1382 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1383 - 6 DSP control registers */
1384
1385 #define FIRST_PSEUDO_REGISTER 188
1386
1387 /* By default, fix the kernel registers ($26 and $27), the global
1388 pointer ($28) and the stack pointer ($29). This can change
1389 depending on the command-line options.
1390
1391 Regarding coprocessor registers: without evidence to the contrary,
1392 it's best to assume that each coprocessor register has a unique
1393 use. This can be overridden, in, e.g., mips_override_options or
1394 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1395 for a particular target. */
1396
1397 #define FIXED_REGISTERS \
1398 { \
1399 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1401 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1402 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1403 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1404 /* COP0 registers */ \
1405 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1407 /* COP2 registers */ \
1408 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1410 /* COP3 registers */ \
1411 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1412 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1413 /* 6 DSP accumulator registers & 6 control registers */ \
1414 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1415 }
1416
1417
1418 /* Set up this array for o32 by default.
1419
1420 Note that we don't mark $31 as a call-clobbered register. The idea is
1421 that it's really the call instructions themselves which clobber $31.
1422 We don't care what the called function does with it afterwards.
1423
1424 This approach makes it easier to implement sibcalls. Unlike normal
1425 calls, sibcalls don't clobber $31, so the register reaches the
1426 called function in tact. EPILOGUE_USES says that $31 is useful
1427 to the called function. */
1428
1429 #define CALL_USED_REGISTERS \
1430 { \
1431 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1432 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1434 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1436 /* COP0 registers */ \
1437 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1439 /* COP2 registers */ \
1440 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1442 /* COP3 registers */ \
1443 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1445 /* 6 DSP accumulator registers & 6 control registers */ \
1446 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1447 }
1448
1449
1450 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1451
1452 #define CALL_REALLY_USED_REGISTERS \
1453 { /* General registers. */ \
1454 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1455 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1456 /* Floating-point registers. */ \
1457 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1458 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1459 /* Others. */ \
1460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1461 /* COP0 registers */ \
1462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1464 /* COP2 registers */ \
1465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1467 /* COP3 registers */ \
1468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1470 /* 6 DSP accumulator registers & 6 control registers */ \
1471 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1472 }
1473
1474 /* Internal macros to classify a register number as to whether it's a
1475 general purpose register, a floating point register, a
1476 multiply/divide register, or a status register. */
1477
1478 #define GP_REG_FIRST 0
1479 #define GP_REG_LAST 31
1480 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1481 #define GP_DBX_FIRST 0
1482
1483 #define FP_REG_FIRST 32
1484 #define FP_REG_LAST 63
1485 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1486 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1487
1488 #define MD_REG_FIRST 64
1489 #define MD_REG_LAST 65
1490 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1491 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1492
1493 /* The DWARF 2 CFA column which tracks the return address from a
1494 signal handler context. This means that to maintain backwards
1495 compatibility, no hard register can be assigned this column if it
1496 would need to be handled by the DWARF unwinder. */
1497 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1498
1499 #define ST_REG_FIRST 67
1500 #define ST_REG_LAST 74
1501 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1502
1503
1504 /* FIXME: renumber. */
1505 #define COP0_REG_FIRST 80
1506 #define COP0_REG_LAST 111
1507 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1508
1509 #define COP2_REG_FIRST 112
1510 #define COP2_REG_LAST 143
1511 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1512
1513 #define COP3_REG_FIRST 144
1514 #define COP3_REG_LAST 175
1515 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1516 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1517 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1518
1519 #define DSP_ACC_REG_FIRST 176
1520 #define DSP_ACC_REG_LAST 181
1521 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1522
1523 #define AT_REGNUM (GP_REG_FIRST + 1)
1524 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1525 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1526
1527 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1528 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1529 should be used instead. */
1530 #define FPSW_REGNUM ST_REG_FIRST
1531
1532 #define GP_REG_P(REGNO) \
1533 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1534 #define M16_REG_P(REGNO) \
1535 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1536 #define FP_REG_P(REGNO) \
1537 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1538 #define MD_REG_P(REGNO) \
1539 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1540 #define ST_REG_P(REGNO) \
1541 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1542 #define COP0_REG_P(REGNO) \
1543 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1544 #define COP2_REG_P(REGNO) \
1545 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1546 #define COP3_REG_P(REGNO) \
1547 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1548 #define ALL_COP_REG_P(REGNO) \
1549 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1550 /* Test if REGNO is one of the 6 new DSP accumulators. */
1551 #define DSP_ACC_REG_P(REGNO) \
1552 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1553 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1554 #define ACC_REG_P(REGNO) \
1555 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1556
1557 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1558
1559 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1560 to initialize the mips16 gp pseudo register. */
1561 #define CONST_GP_P(X) \
1562 (GET_CODE (X) == CONST \
1563 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1564 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1565
1566 /* Return coprocessor number from register number. */
1567
1568 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1569 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1570 : COP3_REG_P (REGNO) ? '3' : '?')
1571
1572
1573 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1574
1575 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1576 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1577
1578 #define MODES_TIEABLE_P mips_modes_tieable_p
1579
1580 /* Register to use for pushing function arguments. */
1581 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1582
1583 /* These two registers don't really exist: they get eliminated to either
1584 the stack or hard frame pointer. */
1585 #define ARG_POINTER_REGNUM 77
1586 #define FRAME_POINTER_REGNUM 78
1587
1588 /* $30 is not available on the mips16, so we use $17 as the frame
1589 pointer. */
1590 #define HARD_FRAME_POINTER_REGNUM \
1591 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1592
1593 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1594
1595 /* Register in which static-chain is passed to a function. */
1596 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1597
1598 /* Registers used as temporaries in prologue/epilogue code. If we're
1599 generating mips16 code, these registers must come from the core set
1600 of 8. The prologue register mustn't conflict with any incoming
1601 arguments, the static chain pointer, or the frame pointer. The
1602 epilogue temporary mustn't conflict with the return registers, the
1603 frame pointer, the EH stack adjustment, or the EH data registers. */
1604
1605 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1606 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1607
1608 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1609 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1610
1611 /* Define this macro if it is as good or better to call a constant
1612 function address than to call an address kept in a register. */
1613 #define NO_FUNCTION_CSE 1
1614
1615 /* The ABI-defined global pointer. Sometimes we use a different
1616 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1617 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1618
1619 /* We normally use $28 as the global pointer. However, when generating
1620 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1621 register instead. They can then avoid saving and restoring $28
1622 and perhaps avoid using a frame at all.
1623
1624 When a leaf function uses something other than $28, mips_expand_prologue
1625 will modify pic_offset_table_rtx in place. Take the register number
1626 from there after reload. */
1627 #define PIC_OFFSET_TABLE_REGNUM \
1628 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1629
1630 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1631 \f
1632 /* Define the classes of registers for register constraints in the
1633 machine description. Also define ranges of constants.
1634
1635 One of the classes must always be named ALL_REGS and include all hard regs.
1636 If there is more than one class, another class must be named NO_REGS
1637 and contain no registers.
1638
1639 The name GENERAL_REGS must be the name of a class (or an alias for
1640 another name such as ALL_REGS). This is the class of registers
1641 that is allowed by "g" or "r" in a register constraint.
1642 Also, registers outside this class are allocated only when
1643 instructions express preferences for them.
1644
1645 The classes must be numbered in nondecreasing order; that is,
1646 a larger-numbered class must never be contained completely
1647 in a smaller-numbered class.
1648
1649 For any two classes, it is very desirable that there be another
1650 class that represents their union. */
1651
1652 enum reg_class
1653 {
1654 NO_REGS, /* no registers in set */
1655 M16_NA_REGS, /* mips16 regs not used to pass args */
1656 M16_REGS, /* mips16 directly accessible registers */
1657 T_REG, /* mips16 T register ($24) */
1658 M16_T_REGS, /* mips16 registers plus T register */
1659 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1660 V1_REG, /* Register $v1 ($3) used for TLS access. */
1661 LEA_REGS, /* Every GPR except $25 */
1662 GR_REGS, /* integer registers */
1663 FP_REGS, /* floating point registers */
1664 MD0_REG, /* first multiply/divide register */
1665 MD1_REG, /* second multiply/divide register */
1666 MD_REGS, /* multiply/divide registers (hi/lo) */
1667 COP0_REGS, /* generic coprocessor classes */
1668 COP2_REGS,
1669 COP3_REGS,
1670 HI_AND_GR_REGS, /* union classes */
1671 LO_AND_GR_REGS,
1672 HI_AND_FP_REGS,
1673 COP0_AND_GR_REGS,
1674 COP2_AND_GR_REGS,
1675 COP3_AND_GR_REGS,
1676 ALL_COP_REGS,
1677 ALL_COP_AND_GR_REGS,
1678 ST_REGS, /* status registers (fp status) */
1679 DSP_ACC_REGS, /* DSP accumulator registers */
1680 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1681 ALL_REGS, /* all registers */
1682 LIM_REG_CLASSES /* max value + 1 */
1683 };
1684
1685 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1686
1687 #define GENERAL_REGS GR_REGS
1688
1689 /* An initializer containing the names of the register classes as C
1690 string constants. These names are used in writing some of the
1691 debugging dumps. */
1692
1693 #define REG_CLASS_NAMES \
1694 { \
1695 "NO_REGS", \
1696 "M16_NA_REGS", \
1697 "M16_REGS", \
1698 "T_REG", \
1699 "M16_T_REGS", \
1700 "PIC_FN_ADDR_REG", \
1701 "V1_REG", \
1702 "LEA_REGS", \
1703 "GR_REGS", \
1704 "FP_REGS", \
1705 "MD0_REG", \
1706 "MD1_REG", \
1707 "MD_REGS", \
1708 /* coprocessor registers */ \
1709 "COP0_REGS", \
1710 "COP2_REGS", \
1711 "COP3_REGS", \
1712 "HI_AND_GR_REGS", \
1713 "LO_AND_GR_REGS", \
1714 "HI_AND_FP_REGS", \
1715 "COP0_AND_GR_REGS", \
1716 "COP2_AND_GR_REGS", \
1717 "COP3_AND_GR_REGS", \
1718 "ALL_COP_REGS", \
1719 "ALL_COP_AND_GR_REGS", \
1720 "ST_REGS", \
1721 "DSP_ACC_REGS", \
1722 "ACC_REGS", \
1723 "ALL_REGS" \
1724 }
1725
1726 /* An initializer containing the contents of the register classes,
1727 as integers which are bit masks. The Nth integer specifies the
1728 contents of class N. The way the integer MASK is interpreted is
1729 that register R is in the class if `MASK & (1 << R)' is 1.
1730
1731 When the machine has more than 32 registers, an integer does not
1732 suffice. Then the integers are replaced by sub-initializers,
1733 braced groupings containing several integers. Each
1734 sub-initializer must be suitable as an initializer for the type
1735 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1736
1737 #define REG_CLASS_CONTENTS \
1738 { \
1739 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1740 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1741 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1742 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1743 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1744 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1745 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1746 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1747 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1748 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1749 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1750 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1751 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1752 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1753 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1754 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1755 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1756 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1757 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1758 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1759 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1760 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1761 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1762 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1763 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1764 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1765 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1766 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1767 }
1768
1769
1770 /* A C expression whose value is a register class containing hard
1771 register REGNO. In general there is more that one such class;
1772 choose a class which is "minimal", meaning that no smaller class
1773 also contains the register. */
1774
1775 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1776
1777 /* A macro whose definition is the name of the class to which a
1778 valid base register must belong. A base register is one used in
1779 an address which is the register value plus a displacement. */
1780
1781 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1782
1783 /* A macro whose definition is the name of the class to which a
1784 valid index register must belong. An index register is one used
1785 in an address where its value is either multiplied by a scale
1786 factor or added to another register (as well as added to a
1787 displacement). */
1788
1789 #define INDEX_REG_CLASS NO_REGS
1790
1791 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1792 registers explicitly used in the rtl to be used as spill registers
1793 but prevents the compiler from extending the lifetime of these
1794 registers. */
1795
1796 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1797
1798 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1799 is the default value (allocate the registers in numeric order). We
1800 define it just so that we can override it for the mips16 target in
1801 ORDER_REGS_FOR_LOCAL_ALLOC. */
1802
1803 #define REG_ALLOC_ORDER \
1804 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1805 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1806 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1807 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1808 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1809 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1810 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1811 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1812 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1813 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1814 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1815 176,177,178,179,180,181,182,183,184,185,186,187 \
1816 }
1817
1818 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1819 to be rearranged based on a particular function. On the mips16, we
1820 want to allocate $24 (T_REG) before other registers for
1821 instructions for which it is possible. */
1822
1823 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1824
1825 /* True if VALUE is an unsigned 6-bit number. */
1826
1827 #define UIMM6_OPERAND(VALUE) \
1828 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1829
1830 /* True if VALUE is a signed 10-bit number. */
1831
1832 #define IMM10_OPERAND(VALUE) \
1833 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1834
1835 /* True if VALUE is a signed 16-bit number. */
1836
1837 #define SMALL_OPERAND(VALUE) \
1838 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1839
1840 /* True if VALUE is an unsigned 16-bit number. */
1841
1842 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1843 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1844
1845 /* True if VALUE can be loaded into a register using LUI. */
1846
1847 #define LUI_OPERAND(VALUE) \
1848 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1849 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1850
1851 /* Return a value X with the low 16 bits clear, and such that
1852 VALUE - X is a signed 16-bit value. */
1853
1854 #define CONST_HIGH_PART(VALUE) \
1855 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1856
1857 #define CONST_LOW_PART(VALUE) \
1858 ((VALUE) - CONST_HIGH_PART (VALUE))
1859
1860 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1861 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1862 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1863
1864 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1865 mips_preferred_reload_class (X, CLASS)
1866
1867 /* The HI and LO registers can only be reloaded via the general
1868 registers. Condition code registers can only be loaded to the
1869 general registers, and from the floating point registers. */
1870
1871 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1872 mips_secondary_reload_class (CLASS, MODE, X, true)
1873 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1874 mips_secondary_reload_class (CLASS, MODE, X, false)
1875
1876 /* Return the maximum number of consecutive registers
1877 needed to represent mode MODE in a register of class CLASS. */
1878
1879 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1880
1881 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1882 mips_cannot_change_mode_class (FROM, TO, CLASS)
1883 \f
1884 /* Stack layout; function entry, exit and calling. */
1885
1886 #define STACK_GROWS_DOWNWARD
1887
1888 /* The offset of the first local variable from the beginning of the frame.
1889 See mips_compute_frame_info for details about the frame layout. */
1890
1891 #define STARTING_FRAME_OFFSET \
1892 (crtl->outgoing_args_size \
1893 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1894
1895 #define RETURN_ADDR_RTX mips_return_addr
1896
1897 /* Since the mips16 ISA mode is encoded in the least-significant bit
1898 of the address, mask it off return addresses for purposes of
1899 finding exception handling regions. */
1900
1901 #define MASK_RETURN_ADDR GEN_INT (-2)
1902
1903
1904 /* Similarly, don't use the least-significant bit to tell pointers to
1905 code from vtable index. */
1906
1907 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1908
1909 /* The eliminations to $17 are only used for mips16 code. See the
1910 definition of HARD_FRAME_POINTER_REGNUM. */
1911
1912 #define ELIMINABLE_REGS \
1913 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1914 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1915 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1916 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1917 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1918 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1919
1920 /* Make sure that we're not trying to eliminate to the wrong hard frame
1921 pointer. */
1922 #define CAN_ELIMINATE(FROM, TO) \
1923 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
1924
1925 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1926 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1927
1928 /* Allocate stack space for arguments at the beginning of each function. */
1929 #define ACCUMULATE_OUTGOING_ARGS 1
1930
1931 /* The argument pointer always points to the first argument. */
1932 #define FIRST_PARM_OFFSET(FNDECL) 0
1933
1934 /* o32 and o64 reserve stack space for all argument registers. */
1935 #define REG_PARM_STACK_SPACE(FNDECL) \
1936 (TARGET_OLDABI \
1937 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1938 : 0)
1939
1940 /* Define this if it is the responsibility of the caller to
1941 allocate the area reserved for arguments passed in registers.
1942 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1943 of this macro is to determine whether the space is included in
1944 `crtl->outgoing_args_size'. */
1945 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1946
1947 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1948 \f
1949 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1950
1951 /* Symbolic macros for the registers used to return integer and floating
1952 point values. */
1953
1954 #define GP_RETURN (GP_REG_FIRST + 2)
1955 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1956
1957 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1958
1959 /* Symbolic macros for the first/last argument registers. */
1960
1961 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1962 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1963 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1964 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1965
1966 #define LIBCALL_VALUE(MODE) \
1967 mips_function_value (NULL_TREE, MODE)
1968
1969 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1970 mips_function_value (VALTYPE, VOIDmode)
1971
1972 /* 1 if N is a possible register number for a function value.
1973 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1974 Currently, R2 and F0 are only implemented here (C has no complex type) */
1975
1976 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1977 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1978 && (N) == FP_RETURN + 2))
1979
1980 /* 1 if N is a possible register number for function argument passing.
1981 We have no FP argument registers when soft-float. When FP registers
1982 are 32 bits, we can't directly reference the odd numbered ones. */
1983
1984 #define FUNCTION_ARG_REGNO_P(N) \
1985 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1986 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1987 && !fixed_regs[N])
1988 \f
1989 /* This structure has to cope with two different argument allocation
1990 schemes. Most MIPS ABIs view the arguments as a structure, of which
1991 the first N words go in registers and the rest go on the stack. If I
1992 < N, the Ith word might go in Ith integer argument register or in a
1993 floating-point register. For these ABIs, we only need to remember
1994 the offset of the current argument into the structure.
1995
1996 The EABI instead allocates the integer and floating-point arguments
1997 separately. The first N words of FP arguments go in FP registers,
1998 the rest go on the stack. Likewise, the first N words of the other
1999 arguments go in integer registers, and the rest go on the stack. We
2000 need to maintain three counts: the number of integer registers used,
2001 the number of floating-point registers used, and the number of words
2002 passed on the stack.
2003
2004 We could keep separate information for the two ABIs (a word count for
2005 the standard ABIs, and three separate counts for the EABI). But it
2006 seems simpler to view the standard ABIs as forms of EABI that do not
2007 allocate floating-point registers.
2008
2009 So for the standard ABIs, the first N words are allocated to integer
2010 registers, and mips_function_arg decides on an argument-by-argument
2011 basis whether that argument should really go in an integer register,
2012 or in a floating-point one. */
2013
2014 typedef struct mips_args {
2015 /* Always true for varargs functions. Otherwise true if at least
2016 one argument has been passed in an integer register. */
2017 int gp_reg_found;
2018
2019 /* The number of arguments seen so far. */
2020 unsigned int arg_number;
2021
2022 /* The number of integer registers used so far. For all ABIs except
2023 EABI, this is the number of words that have been added to the
2024 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2025 unsigned int num_gprs;
2026
2027 /* For EABI, the number of floating-point registers used so far. */
2028 unsigned int num_fprs;
2029
2030 /* The number of words passed on the stack. */
2031 unsigned int stack_words;
2032
2033 /* On the mips16, we need to keep track of which floating point
2034 arguments were passed in general registers, but would have been
2035 passed in the FP regs if this were a 32-bit function, so that we
2036 can move them to the FP regs if we wind up calling a 32-bit
2037 function. We record this information in fp_code, encoded in base
2038 four. A zero digit means no floating point argument, a one digit
2039 means an SFmode argument, and a two digit means a DFmode argument,
2040 and a three digit is not used. The low order digit is the first
2041 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2042 an SFmode argument. ??? A more sophisticated approach will be
2043 needed if MIPS_ABI != ABI_32. */
2044 int fp_code;
2045
2046 /* True if the function has a prototype. */
2047 int prototype;
2048 } CUMULATIVE_ARGS;
2049
2050 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2051 for a call to a function whose data type is FNTYPE.
2052 For a library call, FNTYPE is 0. */
2053
2054 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2055 mips_init_cumulative_args (&CUM, FNTYPE)
2056
2057 /* Update the data in CUM to advance over an argument
2058 of mode MODE and data type TYPE.
2059 (TYPE is null for libcalls where that information may not be available.) */
2060
2061 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2062 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2063
2064 /* Determine where to put an argument to a function.
2065 Value is zero to push the argument on the stack,
2066 or a hard register in which to store the argument.
2067
2068 MODE is the argument's machine mode.
2069 TYPE is the data type of the argument (as a tree).
2070 This is null for libcalls where that information may
2071 not be available.
2072 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2073 the preceding args and about the function being called.
2074 NAMED is nonzero if this argument is a named parameter
2075 (otherwise it is an extra parameter matching an ellipsis). */
2076
2077 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2078 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2079
2080 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2081
2082 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2083 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2084
2085 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2086 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2087
2088 /* True if using EABI and varargs can be passed in floating-point
2089 registers. Under these conditions, we need a more complex form
2090 of va_list, which tracks GPR, FPR and stack arguments separately. */
2091 #define EABI_FLOAT_VARARGS_P \
2092 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2093
2094 \f
2095 /* Say that the epilogue uses the return address register. Note that
2096 in the case of sibcalls, the values "used by the epilogue" are
2097 considered live at the start of the called function.
2098
2099 If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
2100 See the comment above load_call<mode> for details. */
2101 #define EPILOGUE_USES(REGNO) \
2102 ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
2103
2104 /* Treat LOC as a byte offset from the stack pointer and round it up
2105 to the next fully-aligned offset. */
2106 #define MIPS_STACK_ALIGN(LOC) \
2107 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2108
2109 \f
2110 /* Output assembler code to FILE to increment profiler label # LABELNO
2111 for profiling a function entry. */
2112
2113 #define FUNCTION_PROFILER(FILE, LABELNO) \
2114 { \
2115 if (TARGET_MIPS16) \
2116 sorry ("mips16 function profiling"); \
2117 fprintf (FILE, "\t.set\tnoat\n"); \
2118 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2119 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2120 if (!TARGET_NEWABI) \
2121 { \
2122 fprintf (FILE, \
2123 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2124 TARGET_64BIT ? "dsubu" : "subu", \
2125 reg_names[STACK_POINTER_REGNUM], \
2126 reg_names[STACK_POINTER_REGNUM], \
2127 Pmode == DImode ? 16 : 8); \
2128 } \
2129 fprintf (FILE, "\tjal\t_mcount\n"); \
2130 fprintf (FILE, "\t.set\tat\n"); \
2131 }
2132
2133 /* The profiler preserves all interesting registers, including $31. */
2134 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2135
2136 /* No mips port has ever used the profiler counter word, so don't emit it
2137 or the label for it. */
2138
2139 #define NO_PROFILE_COUNTERS 1
2140
2141 /* Define this macro if the code for function profiling should come
2142 before the function prologue. Normally, the profiling code comes
2143 after. */
2144
2145 /* #define PROFILE_BEFORE_PROLOGUE */
2146
2147 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2148 the stack pointer does not matter. The value is tested only in
2149 functions that have frame pointers.
2150 No definition is equivalent to always zero. */
2151
2152 #define EXIT_IGNORE_STACK 1
2153
2154 \f
2155 /* A C statement to output, on the stream FILE, assembler code for a
2156 block of data that contains the constant parts of a trampoline.
2157 This code should not include a label--the label is taken care of
2158 automatically. */
2159
2160 #define TRAMPOLINE_TEMPLATE(STREAM) \
2161 { \
2162 if (ptr_mode == DImode) \
2163 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2164 else \
2165 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2166 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2167 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2168 if (ptr_mode == DImode) \
2169 { \
2170 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2171 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2172 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2173 } \
2174 else \
2175 { \
2176 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2177 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2178 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2179 } \
2180 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2181 if (ptr_mode == DImode) \
2182 { \
2183 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2184 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2185 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2186 } \
2187 else \
2188 { \
2189 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2190 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2191 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2192 } \
2193 }
2194
2195 /* A C expression for the size in bytes of the trampoline, as an
2196 integer. */
2197
2198 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2199
2200 /* Alignment required for trampolines, in bits. */
2201
2202 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2203
2204 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2205 program and data caches. */
2206
2207 #ifndef CACHE_FLUSH_FUNC
2208 #define CACHE_FLUSH_FUNC "_flush_cache"
2209 #endif
2210
2211 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2212 /* Flush both caches. We need to flush the data cache in case \
2213 the system has a write-back cache. */ \
2214 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2215 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2216 GEN_INT (3), TYPE_MODE (integer_type_node))
2217
2218 /* A C statement to initialize the variable parts of a trampoline.
2219 ADDR is an RTX for the address of the trampoline; FNADDR is an
2220 RTX for the address of the nested function; STATIC_CHAIN is an
2221 RTX for the static chain value that should be passed to the
2222 function when it is called. */
2223
2224 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2225 { \
2226 rtx func_addr, chain_addr, end_addr; \
2227 \
2228 func_addr = plus_constant (ADDR, 32); \
2229 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2230 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2231 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2232 end_addr = gen_reg_rtx (Pmode); \
2233 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2234 GEN_INT (TRAMPOLINE_SIZE))); \
2235 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2236 }
2237 \f
2238 /* Addressing modes, and classification of registers for them. */
2239
2240 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2241 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2242 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2243
2244 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2245 and check its validity for a certain class.
2246 We have two alternate definitions for each of them.
2247 The usual definition accepts all pseudo regs; the other rejects them all.
2248 The symbol REG_OK_STRICT causes the latter definition to be used.
2249
2250 Most source files want to accept pseudo regs in the hope that
2251 they will get allocated to the class that the insn wants them to be in.
2252 Some source files that are used after register allocation
2253 need to be strict. */
2254
2255 #ifndef REG_OK_STRICT
2256 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2257 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2258 #else
2259 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2260 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2261 #endif
2262
2263 #define REG_OK_FOR_INDEX_P(X) 0
2264
2265 \f
2266 /* Maximum number of registers that can appear in a valid memory address. */
2267
2268 #define MAX_REGS_PER_ADDRESS 1
2269
2270 #ifdef REG_OK_STRICT
2271 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2272 { \
2273 if (mips_legitimate_address_p (MODE, X, 1)) \
2274 goto ADDR; \
2275 }
2276 #else
2277 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2278 { \
2279 if (mips_legitimate_address_p (MODE, X, 0)) \
2280 goto ADDR; \
2281 }
2282 #endif
2283
2284 /* Check for constness inline but use mips_legitimate_address_p
2285 to check whether a constant really is an address. */
2286
2287 #define CONSTANT_ADDRESS_P(X) \
2288 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2289
2290 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2291
2292 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2293 do { \
2294 if (mips_legitimize_address (&(X), MODE)) \
2295 goto WIN; \
2296 } while (0)
2297
2298
2299 /* A C statement or compound statement with a conditional `goto
2300 LABEL;' executed if memory address X (an RTX) can have different
2301 meanings depending on the machine mode of the memory reference it
2302 is used for.
2303
2304 Autoincrement and autodecrement addresses typically have
2305 mode-dependent effects because the amount of the increment or
2306 decrement is the size of the operand being addressed. Some
2307 machines have other mode-dependent addresses. Many RISC machines
2308 have no mode-dependent addresses.
2309
2310 You may assume that ADDR is a valid address for the machine. */
2311
2312 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2313
2314 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2315 'the start of the function that this code is output in'. */
2316
2317 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2318 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2319 asm_fprintf ((FILE), "%U%s", \
2320 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2321 else \
2322 asm_fprintf ((FILE), "%U%s", (NAME))
2323 \f
2324 /* Flag to mark a function decl symbol that requires a long call. */
2325 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2326 #define SYMBOL_REF_LONG_CALL_P(X) \
2327 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2328
2329 /* True if we're generating a form of MIPS16 code in which jump tables
2330 are stored in the text section and encoded as 16-bit PC-relative
2331 offsets. This is only possible when general text loads are allowed,
2332 since the table access itself will be an "lh" instruction. */
2333 /* ??? 16-bit offsets can overflow in large functions. */
2334 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2335
2336 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2337
2338 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2339
2340 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2341
2342 /* Define this as 1 if `char' should by default be signed; else as 0. */
2343 #ifndef DEFAULT_SIGNED_CHAR
2344 #define DEFAULT_SIGNED_CHAR 1
2345 #endif
2346
2347 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2348 we generally don't want to use them for copying arbitrary data.
2349 A single N-word move is usually the same cost as N single-word moves. */
2350 #define MOVE_MAX UNITS_PER_WORD
2351 #define MAX_MOVE_MAX 8
2352
2353 /* Define this macro as a C expression which is nonzero if
2354 accessing less than a word of memory (i.e. a `char' or a
2355 `short') is no faster than accessing a word of memory, i.e., if
2356 such access require more than one instruction or if there is no
2357 difference in cost between byte and (aligned) word loads.
2358
2359 On RISC machines, it tends to generate better code to define
2360 this as 1, since it avoids making a QI or HI mode register.
2361
2362 But, generating word accesses for -mips16 is generally bad as shifts
2363 (often extended) would be needed for byte accesses. */
2364 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2365
2366 /* Define this to be nonzero if shift instructions ignore all but the low-order
2367 few bits. */
2368 #define SHIFT_COUNT_TRUNCATED 1
2369
2370 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2371 is done just by pretending it is already truncated. */
2372 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2373 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2374
2375
2376 /* Specify the machine mode that pointers have.
2377 After generation of rtl, the compiler makes no further distinction
2378 between pointers and any other objects of this machine mode. */
2379
2380 #ifndef Pmode
2381 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2382 #endif
2383
2384 /* Give call MEMs SImode since it is the "most permissive" mode
2385 for both 32-bit and 64-bit targets. */
2386
2387 #define FUNCTION_MODE SImode
2388
2389 \f
2390 /* A C expression for the cost of moving data from a register in
2391 class FROM to one in class TO. The classes are expressed using
2392 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2393 the default; other values are interpreted relative to that.
2394
2395 It is not required that the cost always equal 2 when FROM is the
2396 same as TO; on some machines it is expensive to move between
2397 registers if they are not general registers.
2398
2399 If reload sees an insn consisting of a single `set' between two
2400 hard registers, and if `REGISTER_MOVE_COST' applied to their
2401 classes returns a value of 2, reload does not check to ensure
2402 that the constraints of the insn are met. Setting a cost of
2403 other than 2 will allow reload to verify that the constraints are
2404 met. You should do this if the `movM' pattern's constraints do
2405 not allow such copying. */
2406
2407 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2408 mips_register_move_cost (MODE, FROM, TO)
2409
2410 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2411 (mips_cost->memory_latency \
2412 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2413
2414 /* Define if copies to/from condition code registers should be avoided.
2415
2416 This is needed for the MIPS because reload_outcc is not complete;
2417 it needs to handle cases where the source is a general or another
2418 condition code register. */
2419 #define AVOID_CCMODE_COPIES
2420
2421 /* A C expression for the cost of a branch instruction. A value of
2422 1 is the default; other values are interpreted relative to that. */
2423
2424 #define BRANCH_COST mips_branch_cost
2425 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2426
2427 /* If defined, modifies the length assigned to instruction INSN as a
2428 function of the context in which it is used. LENGTH is an lvalue
2429 that contains the initially computed length of the insn and should
2430 be updated with the correct length of the insn. */
2431 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2432 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2433
2434 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2435 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2436 its operands. */
2437 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2438 "%*" OPCODE "%?\t" OPERANDS "%/"
2439
2440 /* Return the asm template for a call. INSN is the instruction's mnemonic
2441 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2442 of the target.
2443
2444 When generating GOT code without explicit relocation operators,
2445 all calls should use assembly macros. Otherwise, all indirect
2446 calls should use "jr" or "jalr"; we will arrange to restore $gp
2447 afterwards if necessary. Finally, we can only generate direct
2448 calls for -mabicalls by temporarily switching to non-PIC mode. */
2449 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2450 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2451 ? "%*" INSN "\t%" #OPNO "%/" \
2452 : REG_P (OPERANDS[OPNO]) \
2453 ? "%*" INSN "r\t%" #OPNO "%/" \
2454 : TARGET_ABICALLS \
2455 ? (".option\tpic0\n\t" \
2456 "%*" INSN "\t%" #OPNO "%/\n\t" \
2457 ".option\tpic2") \
2458 : "%*" INSN "\t%" #OPNO "%/")
2459 \f
2460 /* Control the assembler format that we output. */
2461
2462 /* Output to assembler file text saying following lines
2463 may contain character constants, extra white space, comments, etc. */
2464
2465 #ifndef ASM_APP_ON
2466 #define ASM_APP_ON " #APP\n"
2467 #endif
2468
2469 /* Output to assembler file text saying following lines
2470 no longer contain unusual constructs. */
2471
2472 #ifndef ASM_APP_OFF
2473 #define ASM_APP_OFF " #NO_APP\n"
2474 #endif
2475
2476 #define REGISTER_NAMES \
2477 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2478 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2479 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2480 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2481 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2482 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2483 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2484 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2485 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2486 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2487 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2488 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2489 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2490 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2491 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2492 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2493 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2494 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2495 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2496 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2497 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2498 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2499 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2500 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2501
2502 /* List the "software" names for each register. Also list the numerical
2503 names for $fp and $sp. */
2504
2505 #define ADDITIONAL_REGISTER_NAMES \
2506 { \
2507 { "$29", 29 + GP_REG_FIRST }, \
2508 { "$30", 30 + GP_REG_FIRST }, \
2509 { "at", 1 + GP_REG_FIRST }, \
2510 { "v0", 2 + GP_REG_FIRST }, \
2511 { "v1", 3 + GP_REG_FIRST }, \
2512 { "a0", 4 + GP_REG_FIRST }, \
2513 { "a1", 5 + GP_REG_FIRST }, \
2514 { "a2", 6 + GP_REG_FIRST }, \
2515 { "a3", 7 + GP_REG_FIRST }, \
2516 { "t0", 8 + GP_REG_FIRST }, \
2517 { "t1", 9 + GP_REG_FIRST }, \
2518 { "t2", 10 + GP_REG_FIRST }, \
2519 { "t3", 11 + GP_REG_FIRST }, \
2520 { "t4", 12 + GP_REG_FIRST }, \
2521 { "t5", 13 + GP_REG_FIRST }, \
2522 { "t6", 14 + GP_REG_FIRST }, \
2523 { "t7", 15 + GP_REG_FIRST }, \
2524 { "s0", 16 + GP_REG_FIRST }, \
2525 { "s1", 17 + GP_REG_FIRST }, \
2526 { "s2", 18 + GP_REG_FIRST }, \
2527 { "s3", 19 + GP_REG_FIRST }, \
2528 { "s4", 20 + GP_REG_FIRST }, \
2529 { "s5", 21 + GP_REG_FIRST }, \
2530 { "s6", 22 + GP_REG_FIRST }, \
2531 { "s7", 23 + GP_REG_FIRST }, \
2532 { "t8", 24 + GP_REG_FIRST }, \
2533 { "t9", 25 + GP_REG_FIRST }, \
2534 { "k0", 26 + GP_REG_FIRST }, \
2535 { "k1", 27 + GP_REG_FIRST }, \
2536 { "gp", 28 + GP_REG_FIRST }, \
2537 { "sp", 29 + GP_REG_FIRST }, \
2538 { "fp", 30 + GP_REG_FIRST }, \
2539 { "ra", 31 + GP_REG_FIRST }, \
2540 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2541 }
2542
2543 /* This is meant to be redefined in the host dependent files. It is a
2544 set of alternative names and regnums for mips coprocessors. */
2545
2546 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2547
2548 #define PRINT_OPERAND mips_print_operand
2549 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2550 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2551
2552 /* A C statement, to be executed after all slot-filler instructions
2553 have been output. If necessary, call `dbr_sequence_length' to
2554 determine the number of slots filled in a sequence (zero if not
2555 currently outputting a sequence), to decide how many no-ops to
2556 output, or whatever.
2557
2558 Don't define this macro if it has nothing to do, but it is
2559 helpful in reading assembly output if the extent of the delay
2560 sequence is made explicit (e.g. with white space).
2561
2562 Note that output routines for instructions with delay slots must
2563 be prepared to deal with not being output as part of a sequence
2564 (i.e. when the scheduling pass is not run, or when no slot
2565 fillers could be found.) The variable `final_sequence' is null
2566 when not processing a sequence, otherwise it contains the
2567 `sequence' rtx being output. */
2568
2569 #define DBR_OUTPUT_SEQEND(STREAM) \
2570 do \
2571 { \
2572 if (set_nomacro > 0 && --set_nomacro == 0) \
2573 fputs ("\t.set\tmacro\n", STREAM); \
2574 \
2575 if (set_noreorder > 0 && --set_noreorder == 0) \
2576 fputs ("\t.set\treorder\n", STREAM); \
2577 \
2578 fputs ("\n", STREAM); \
2579 } \
2580 while (0)
2581
2582 /* How to tell the debugger about changes of source files. */
2583 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2584
2585 /* mips-tfile does not understand .stabd directives. */
2586 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2587 dbxout_begin_stabn_sline (LINE); \
2588 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2589 } while (0)
2590
2591 /* Use .loc directives for SDB line numbers. */
2592 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2593 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2594
2595 /* The MIPS implementation uses some labels for its own purpose. The
2596 following lists what labels are created, and are all formed by the
2597 pattern $L[a-z].*. The machine independent portion of GCC creates
2598 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2599
2600 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2601 $Lb[0-9]+ Begin blocks for MIPS debug support
2602 $Lc[0-9]+ Label for use in s<xx> operation.
2603 $Le[0-9]+ End blocks for MIPS debug support */
2604
2605 #undef ASM_DECLARE_OBJECT_NAME
2606 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2607 mips_declare_object (STREAM, NAME, "", ":\n")
2608
2609 /* Globalizing directive for a label. */
2610 #define GLOBAL_ASM_OP "\t.globl\t"
2611
2612 /* This says how to define a global common symbol. */
2613
2614 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2615
2616 /* This says how to define a local common symbol (i.e., not visible to
2617 linker). */
2618
2619 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2620 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2621 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2622 #endif
2623
2624 /* This says how to output an external. It would be possible not to
2625 output anything and let undefined symbol become external. However
2626 the assembler uses length information on externals to allocate in
2627 data/sdata bss/sbss, thereby saving exec time. */
2628
2629 #undef ASM_OUTPUT_EXTERNAL
2630 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2631 mips_output_external(STREAM,DECL,NAME)
2632
2633 /* This is how to declare a function name. The actual work of
2634 emitting the label is moved to function_prologue, so that we can
2635 get the line number correctly emitted before the .ent directive,
2636 and after any .file directives. Define as empty so that the function
2637 is not declared before the .ent directive elsewhere. */
2638
2639 #undef ASM_DECLARE_FUNCTION_NAME
2640 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2641
2642 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2643 #define FUNCTION_NAME_ALREADY_DECLARED 0
2644 #endif
2645
2646 /* This is how to store into the string LABEL
2647 the symbol_ref name of an internal numbered label where
2648 PREFIX is the class of label and NUM is the number within the class.
2649 This is suitable for output with `assemble_name'. */
2650
2651 #undef ASM_GENERATE_INTERNAL_LABEL
2652 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2653 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2654
2655 /* This is how to output an element of a case-vector that is absolute. */
2656
2657 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2658 fprintf (STREAM, "\t%s\t%sL%d\n", \
2659 ptr_mode == DImode ? ".dword" : ".word", \
2660 LOCAL_LABEL_PREFIX, \
2661 VALUE)
2662
2663 /* This is how to output an element of a case-vector. We can make the
2664 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2665 is supported. */
2666
2667 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2668 do { \
2669 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2670 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2671 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2672 else if (TARGET_GPWORD) \
2673 fprintf (STREAM, "\t%s\t%sL%d\n", \
2674 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2675 LOCAL_LABEL_PREFIX, VALUE); \
2676 else if (TARGET_RTP_PIC) \
2677 { \
2678 /* Make the entry relative to the start of the function. */ \
2679 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2680 fprintf (STREAM, "\t%s\t%sL%d-", \
2681 Pmode == DImode ? ".dword" : ".word", \
2682 LOCAL_LABEL_PREFIX, VALUE); \
2683 assemble_name (STREAM, XSTR (fnsym, 0)); \
2684 fprintf (STREAM, "\n"); \
2685 } \
2686 else \
2687 fprintf (STREAM, "\t%s\t%sL%d\n", \
2688 ptr_mode == DImode ? ".dword" : ".word", \
2689 LOCAL_LABEL_PREFIX, VALUE); \
2690 } while (0)
2691
2692 /* This is how to output an assembler line
2693 that says to advance the location counter
2694 to a multiple of 2**LOG bytes. */
2695
2696 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2697 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2698
2699 /* This is how to output an assembler line to advance the location
2700 counter by SIZE bytes. */
2701
2702 #undef ASM_OUTPUT_SKIP
2703 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2704 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2705
2706 /* This is how to output a string. */
2707 #undef ASM_OUTPUT_ASCII
2708 #define ASM_OUTPUT_ASCII mips_output_ascii
2709
2710 /* Output #ident as a in the read-only data section. */
2711 #undef ASM_OUTPUT_IDENT
2712 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2713 { \
2714 const char *p = STRING; \
2715 int size = strlen (p) + 1; \
2716 switch_to_section (readonly_data_section); \
2717 assemble_string (p, size); \
2718 }
2719 \f
2720 /* Default to -G 8 */
2721 #ifndef MIPS_DEFAULT_GVALUE
2722 #define MIPS_DEFAULT_GVALUE 8
2723 #endif
2724
2725 /* Define the strings to put out for each section in the object file. */
2726 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2727 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2728
2729 #undef READONLY_DATA_SECTION_ASM_OP
2730 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2731 \f
2732 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2733 do \
2734 { \
2735 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2736 TARGET_64BIT ? "daddiu" : "addiu", \
2737 reg_names[STACK_POINTER_REGNUM], \
2738 reg_names[STACK_POINTER_REGNUM], \
2739 TARGET_64BIT ? "sd" : "sw", \
2740 reg_names[REGNO], \
2741 reg_names[STACK_POINTER_REGNUM]); \
2742 } \
2743 while (0)
2744
2745 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2746 do \
2747 { \
2748 if (! set_noreorder) \
2749 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2750 \
2751 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2752 TARGET_64BIT ? "ld" : "lw", \
2753 reg_names[REGNO], \
2754 reg_names[STACK_POINTER_REGNUM], \
2755 TARGET_64BIT ? "daddu" : "addu", \
2756 reg_names[STACK_POINTER_REGNUM], \
2757 reg_names[STACK_POINTER_REGNUM]); \
2758 \
2759 if (! set_noreorder) \
2760 fprintf (STREAM, "\t.set\treorder\n"); \
2761 } \
2762 while (0)
2763
2764 /* How to start an assembler comment.
2765 The leading space is important (the mips native assembler requires it). */
2766 #ifndef ASM_COMMENT_START
2767 #define ASM_COMMENT_START " #"
2768 #endif
2769 \f
2770 /* Default definitions for size_t and ptrdiff_t. We must override the
2771 definitions from ../svr4.h on mips-*-linux-gnu. */
2772
2773 #undef SIZE_TYPE
2774 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2775
2776 #undef PTRDIFF_TYPE
2777 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2778
2779 /* The maximum number of bytes that can be copied by one iteration of
2780 a movmemsi loop; see mips_block_move_loop. */
2781 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2782 (UNITS_PER_WORD * 4)
2783
2784 /* The maximum number of bytes that can be copied by a straight-line
2785 implementation of movmemsi; see mips_block_move_straight. We want
2786 to make sure that any loop-based implementation will iterate at
2787 least twice. */
2788 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2789 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2790
2791 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2792 values were determined experimentally by benchmarking with CSiBE.
2793 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2794 for o32 where we have to restore $gp afterwards as well as make an
2795 indirect call), but in practice, bumping this up higher for
2796 TARGET_ABICALLS doesn't make much difference to code size. */
2797
2798 #define MIPS_CALL_RATIO 8
2799
2800 /* Any loop-based implementation of movmemsi will have at least
2801 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2802 moves, so allow individual copies of fewer elements.
2803
2804 When movmemsi is not available, use a value approximating
2805 the length of a memcpy call sequence, so that move_by_pieces
2806 will generate inline code if it is shorter than a function call.
2807 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2808 we'll have to generate a load/store pair for each, halve the
2809 value of MIPS_CALL_RATIO to take that into account. */
2810
2811 #define MOVE_RATIO \
2812 (HAVE_movmemsi \
2813 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2814 : MIPS_CALL_RATIO / 2)
2815
2816 /* movmemsi is meant to generate code that is at least as good as
2817 move_by_pieces. However, movmemsi effectively uses a by-pieces
2818 implementation both for moves smaller than a word and for word-aligned
2819 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2820 allow the tree-level optimisers to do such moves by pieces, as it
2821 often exposes other optimization opportunities. We might as well
2822 continue to use movmemsi at the rtl level though, as it produces
2823 better code when scheduling is disabled (such as at -O). */
2824
2825 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2826 (HAVE_movmemsi \
2827 ? (!currently_expanding_to_rtl \
2828 && ((ALIGN) < BITS_PER_WORD \
2829 ? (SIZE) < UNITS_PER_WORD \
2830 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2831 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2832 < (unsigned int) MOVE_RATIO))
2833
2834 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2835 of the length of a memset call, but use the default otherwise. */
2836
2837 #define CLEAR_RATIO \
2838 (optimize_size ? MIPS_CALL_RATIO : 15)
2839
2840 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2841 optimizing for size adjust the ratio to account for the overhead of
2842 loading the constant and replicating it across the word. */
2843
2844 #define SET_RATIO \
2845 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2846
2847 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2848 in that case each word takes 3 insns (lui, ori, sw), or more in
2849 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2850 and let the move_by_pieces code copy the string from read-only
2851 memory. In the future, this could be tuned further for multi-issue
2852 CPUs that can issue stores down one pipe and arithmetic instructions
2853 down another; in that case, the lui/ori/sw combination would be a
2854 win for long enough strings. */
2855
2856 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2857 \f
2858 #ifndef __mips16
2859 /* Since the bits of the _init and _fini function is spread across
2860 many object files, each potentially with its own GP, we must assume
2861 we need to load our GP. We don't preserve $gp or $ra, since each
2862 init/fini chunk is supposed to initialize $gp, and crti/crtn
2863 already take care of preserving $ra and, when appropriate, $gp. */
2864 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2865 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2866 asm (SECTION_OP "\n\
2867 .set noreorder\n\
2868 bal 1f\n\
2869 nop\n\
2870 1: .cpload $31\n\
2871 .set reorder\n\
2872 jal " USER_LABEL_PREFIX #FUNC "\n\
2873 " TEXT_SECTION_ASM_OP);
2874 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2875 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2876 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2877 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2878 asm (SECTION_OP "\n\
2879 .set noreorder\n\
2880 bal 1f\n\
2881 nop\n\
2882 1: .set reorder\n\
2883 .cpsetup $31, $2, 1b\n\
2884 jal " USER_LABEL_PREFIX #FUNC "\n\
2885 " TEXT_SECTION_ASM_OP);
2886 #endif
2887 #endif
2888
2889 #ifndef HAVE_AS_TLS
2890 #define HAVE_AS_TLS 0
2891 #endif
2892
2893 /* Return an asm string that atomically:
2894
2895 - Compares memory reference %1 to register %2 and, if they are
2896 equal, changes %1 to %3.
2897
2898 - Sets register %0 to the old value of memory reference %1.
2899
2900 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2901 and OP is the instruction that should be used to load %3 into a
2902 register. */
2903 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2904 "%(%<%[%|sync\n" \
2905 "1:\tll" SUFFIX "\t%0,%1\n" \
2906 "\tbne\t%0,%z2,2f\n" \
2907 "\t" OP "\t%@,%3\n" \
2908 "\tsc" SUFFIX "\t%@,%1\n" \
2909 "\tbeq\t%@,%.,1b\n" \
2910 "\tnop\n" \
2911 "\tsync%-%]%>%)\n" \
2912 "2:\n"
2913
2914 /* Return an asm string that atomically:
2915
2916 - Given that %2 contains a bit mask and %3 the inverted mask and
2917 that %4 and %5 have already been ANDed with %2.
2918
2919 - Compares the bits in memory reference %1 selected by mask %2 to
2920 register %4 and, if they are equal, changes the selected bits
2921 in memory to %5.
2922
2923 - Sets register %0 to the old value of memory reference %1.
2924
2925 OPS are the instructions needed to OR %5 with %@. */
2926 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
2927 "%(%<%[%|sync\n" \
2928 "1:\tll\t%0,%1\n" \
2929 "\tand\t%@,%0,%2\n" \
2930 "\tbne\t%@,%z4,2f\n" \
2931 "\tand\t%@,%0,%3\n" \
2932 OPS \
2933 "\tsc\t%@,%1\n" \
2934 "\tbeq\t%@,%.,1b\n" \
2935 "\tnop\n" \
2936 "\tsync%-%]%>%)\n" \
2937 "2:\n"
2938
2939 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
2940 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
2941
2942
2943 /* Return an asm string that atomically:
2944
2945 - Sets memory reference %0 to %0 INSN %1.
2946
2947 SUFFIX is the suffix that should be added to "ll" and "sc"
2948 instructions. */
2949 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2950 "%(%<%[%|sync\n" \
2951 "1:\tll" SUFFIX "\t%@,%0\n" \
2952 "\t" INSN "\t%@,%@,%1\n" \
2953 "\tsc" SUFFIX "\t%@,%0\n" \
2954 "\tbeq\t%@,%.,1b\n" \
2955 "\tnop\n" \
2956 "\tsync%-%]%>%)"
2957
2958 /* Return an asm string that atomically:
2959
2960 - Given that %1 contains a bit mask and %2 the inverted mask and
2961 that %3 has already been ANDed with %1.
2962
2963 - Sets the selected bits of memory reference %0 to %0 INSN %3.
2964
2965 - Uses scratch register %4.
2966
2967 NOT_OP are the optional instructions to do a bit-wise not
2968 operation in conjunction with an AND INSN to generate a sync_nand
2969 operation. */
2970 #define MIPS_SYNC_OP_12(INSN, NOT_OP) \
2971 "%(%<%[%|sync\n" \
2972 "1:\tll\t%4,%0\n" \
2973 "\tand\t%@,%4,%2\n" \
2974 NOT_OP \
2975 "\t" INSN "\t%4,%4,%z3\n" \
2976 "\tand\t%4,%4,%1\n" \
2977 "\tor\t%@,%@,%4\n" \
2978 "\tsc\t%@,%0\n" \
2979 "\tbeq\t%@,%.,1b\n" \
2980 "\tnop\n" \
2981 "\tsync%-%]%>%)"
2982
2983 #define MIPS_SYNC_OP_12_NOT_NOP ""
2984 #define MIPS_SYNC_OP_12_NOT_NOT "\tnor\t%4,%4,%.\n"
2985
2986 /* Return an asm string that atomically:
2987
2988 - Given that %2 contains a bit mask and %3 the inverted mask and
2989 that %4 has already been ANDed with %2.
2990
2991 - Sets the selected bits of memory reference %1 to %1 INSN %4.
2992
2993 - Sets %0 to the original value of %1.
2994
2995 - Uses scratch register %5.
2996
2997 NOT_OP are the optional instructions to do a bit-wise not
2998 operation in conjunction with an AND INSN to generate a sync_nand
2999 operation.
3000
3001 REG is used in conjunction with NOT_OP and is used to select the
3002 register operated on by the INSN. */
3003 #define MIPS_SYNC_OLD_OP_12(INSN, NOT_OP, REG) \
3004 "%(%<%[%|sync\n" \
3005 "1:\tll\t%0,%1\n" \
3006 "\tand\t%@,%0,%3\n" \
3007 NOT_OP \
3008 "\t" INSN "\t%5," REG ",%z4\n" \
3009 "\tand\t%5,%5,%2\n" \
3010 "\tor\t%@,%@,%5\n" \
3011 "\tsc\t%@,%1\n" \
3012 "\tbeq\t%@,%.,1b\n" \
3013 "\tnop\n" \
3014 "\tsync%-%]%>%)"
3015
3016 #define MIPS_SYNC_OLD_OP_12_NOT_NOP ""
3017 #define MIPS_SYNC_OLD_OP_12_NOT_NOP_REG "%0"
3018 #define MIPS_SYNC_OLD_OP_12_NOT_NOT "\tnor\t%5,%0,%.\n"
3019 #define MIPS_SYNC_OLD_OP_12_NOT_NOT_REG "%5"
3020
3021 /* Return an asm string that atomically:
3022
3023 - Given that %2 contains a bit mask and %3 the inverted mask and
3024 that %4 has already been ANDed with %2.
3025
3026 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3027
3028 - Sets %0 to the new value of %1.
3029
3030 NOT_OP are the optional instructions to do a bit-wise not
3031 operation in conjunction with an AND INSN to generate a sync_nand
3032 operation. */
3033 #define MIPS_SYNC_NEW_OP_12(INSN, NOT_OP) \
3034 "%(%<%[%|sync\n" \
3035 "1:\tll\t%0,%1\n" \
3036 "\tand\t%@,%0,%3\n" \
3037 NOT_OP \
3038 "\t" INSN "\t%0,%0,%z4\n" \
3039 "\tand\t%0,%0,%2\n" \
3040 "\tor\t%@,%@,%0\n" \
3041 "\tsc\t%@,%1\n" \
3042 "\tbeq\t%@,%.,1b\n" \
3043 "\tnop\n" \
3044 "\tsync%-%]%>%)"
3045
3046 #define MIPS_SYNC_NEW_OP_12_NOT_NOP ""
3047 #define MIPS_SYNC_NEW_OP_12_NOT_NOT "\tnor\t%0,%0,%.\n"
3048
3049 /* Return an asm string that atomically:
3050
3051 - Sets memory reference %1 to %1 INSN %2.
3052
3053 - Sets register %0 to the old value of memory reference %1.
3054
3055 SUFFIX is the suffix that should be added to "ll" and "sc"
3056 instructions. */
3057 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3058 "%(%<%[%|sync\n" \
3059 "1:\tll" SUFFIX "\t%0,%1\n" \
3060 "\t" INSN "\t%@,%0,%2\n" \
3061 "\tsc" SUFFIX "\t%@,%1\n" \
3062 "\tbeq\t%@,%.,1b\n" \
3063 "\tnop\n" \
3064 "\tsync%-%]%>%)"
3065
3066 /* Return an asm string that atomically:
3067
3068 - Sets memory reference %1 to %1 INSN %2.
3069
3070 - Sets register %0 to the new value of memory reference %1.
3071
3072 SUFFIX is the suffix that should be added to "ll" and "sc"
3073 instructions. */
3074 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3075 "%(%<%[%|sync\n" \
3076 "1:\tll" SUFFIX "\t%0,%1\n" \
3077 "\t" INSN "\t%@,%0,%2\n" \
3078 "\tsc" SUFFIX "\t%@,%1\n" \
3079 "\tbeq\t%@,%.,1b\n" \
3080 "\t" INSN "\t%0,%0,%2\n" \
3081 "\tsync%-%]%>%)"
3082
3083 /* Return an asm string that atomically:
3084
3085 - Sets memory reference %0 to ~%0 AND %1.
3086
3087 SUFFIX is the suffix that should be added to "ll" and "sc"
3088 instructions. INSN is the and instruction needed to and a register
3089 with %2. */
3090 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3091 "%(%<%[%|sync\n" \
3092 "1:\tll" SUFFIX "\t%@,%0\n" \
3093 "\tnor\t%@,%@,%.\n" \
3094 "\t" INSN "\t%@,%@,%1\n" \
3095 "\tsc" SUFFIX "\t%@,%0\n" \
3096 "\tbeq\t%@,%.,1b\n" \
3097 "\tnop\n" \
3098 "\tsync%-%]%>%)"
3099
3100 /* Return an asm string that atomically:
3101
3102 - Sets memory reference %1 to ~%1 AND %2.
3103
3104 - Sets register %0 to the old value of memory reference %1.
3105
3106 SUFFIX is the suffix that should be added to "ll" and "sc"
3107 instructions. INSN is the and instruction needed to and a register
3108 with %2. */
3109 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3110 "%(%<%[%|sync\n" \
3111 "1:\tll" SUFFIX "\t%0,%1\n" \
3112 "\tnor\t%@,%0,%.\n" \
3113 "\t" INSN "\t%@,%@,%2\n" \
3114 "\tsc" SUFFIX "\t%@,%1\n" \
3115 "\tbeq\t%@,%.,1b\n" \
3116 "\tnop\n" \
3117 "\tsync%-%]%>%)"
3118
3119 /* Return an asm string that atomically:
3120
3121 - Sets memory reference %1 to ~%1 AND %2.
3122
3123 - Sets register %0 to the new value of memory reference %1.
3124
3125 SUFFIX is the suffix that should be added to "ll" and "sc"
3126 instructions. INSN is the and instruction needed to and a register
3127 with %2. */
3128 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3129 "%(%<%[%|sync\n" \
3130 "1:\tll" SUFFIX "\t%0,%1\n" \
3131 "\tnor\t%0,%0,%.\n" \
3132 "\t" INSN "\t%@,%0,%2\n" \
3133 "\tsc" SUFFIX "\t%@,%1\n" \
3134 "\tbeq\t%@,%.,1b\n" \
3135 "\t" INSN "\t%0,%0,%2\n" \
3136 "\tsync%-%]%>%)"
3137
3138 /* Return an asm string that atomically:
3139
3140 - Sets memory reference %1 to %2.
3141
3142 - Sets register %0 to the old value of memory reference %1.
3143
3144 SUFFIX is the suffix that should be added to "ll" and "sc"
3145 instructions. OP is the and instruction that should be used to
3146 load %2 into a register. */
3147 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3148 "%(%<%[%|\n" \
3149 "1:\tll" SUFFIX "\t%0,%1\n" \
3150 "\t" OP "\t%@,%2\n" \
3151 "\tsc" SUFFIX "\t%@,%1\n" \
3152 "\tbeq\t%@,%.,1b\n" \
3153 "\tnop\n" \
3154 "\tsync%-%]%>%)"
3155
3156 /* Return an asm string that atomically:
3157
3158 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3159 and %4 has already been ANDed with the inclusive mask.
3160
3161 - Sets bits selected by the inclusive mask of memory reference %1
3162 to %4.
3163
3164 - Sets register %0 to the old value of memory reference %1.
3165
3166 OPS are the instructions needed to OR %4 with %@.
3167
3168 Operand %2 is unused, but needed as to give the test_and_set_12
3169 insn the five operands expected by the expander. */
3170 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3171 "%(%<%[%|\n" \
3172 "1:\tll\t%0,%1\n" \
3173 "\tand\t%@,%0,%3\n" \
3174 OPS \
3175 "\tsc\t%@,%1\n" \
3176 "\tbeq\t%@,%.,1b\n" \
3177 "\tnop\n" \
3178 "\tsync%-%]%>%)"
3179
3180 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3181 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3182
3183 #ifndef USED_FOR_TARGET
3184 extern const enum reg_class mips_regno_to_class[];
3185 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3186 extern bool mips_print_operand_punct[256];
3187 extern const char *current_function_file; /* filename current function is in */
3188 extern int num_source_filenames; /* current .file # */
3189 extern int set_noreorder; /* # of nested .set noreorder's */
3190 extern int set_nomacro; /* # of nested .set nomacro's */
3191 extern int mips_dbx_regno[];
3192 extern int mips_dwarf_regno[];
3193 extern bool mips_split_p[];
3194 extern GTY(()) rtx cmp_operands[2];
3195 extern enum processor_type mips_arch; /* which cpu to codegen for */
3196 extern enum processor_type mips_tune; /* which cpu to schedule for */
3197 extern int mips_isa; /* architectural level */
3198 extern int mips_abi; /* which ABI to use */
3199 extern const struct mips_cpu_info *mips_arch_info;
3200 extern const struct mips_cpu_info *mips_tune_info;
3201 extern const struct mips_rtx_cost_data *mips_cost;
3202 extern enum mips_code_readable_setting mips_code_readable;
3203 #endif
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