1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
50 enum reg_class regno_reg_class
[] =
52 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
62 /* The minimum number of integer registers that we want to save with the
63 movem instruction. Using two movel instructions instead of a single
64 moveml is about 15% faster for the 68020 and 68030 at no expense in
66 #define MIN_MOVEM_REGS 3
68 /* The minimum number of floating point registers that we want to save
69 with the fmovem instruction. */
70 #define MIN_FMOVEM_REGS 1
72 /* Structure describing stack frame layout. */
75 /* Stack pointer to frame pointer offset. */
78 /* Offset of FPU registers. */
79 HOST_WIDE_INT foffset
;
81 /* Frame size in bytes (rounded up). */
84 /* Data and address register. */
86 unsigned int reg_mask
;
90 unsigned int fpu_mask
;
92 /* Offsets relative to ARG_POINTER. */
93 HOST_WIDE_INT frame_pointer_offset
;
94 HOST_WIDE_INT stack_pointer_offset
;
96 /* Function which the above information refers to. */
100 /* Current frame information calculated by m68k_compute_frame_layout(). */
101 static struct m68k_frame current_frame
;
103 /* Structure describing an m68k address.
105 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
106 with null fields evaluating to 0. Here:
108 - BASE satisfies m68k_legitimate_base_reg_p
109 - INDEX satisfies m68k_legitimate_index_reg_p
110 - OFFSET satisfies m68k_legitimate_constant_address_p
112 INDEX is either HImode or SImode. The other fields are SImode.
114 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
115 the address is (BASE)+. */
116 struct m68k_address
{
124 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
125 static int m68k_sched_issue_rate (void);
126 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
127 static void m68k_sched_md_init_global (FILE *, int, int);
128 static void m68k_sched_md_finish_global (FILE *, int);
129 static void m68k_sched_md_init (FILE *, int, int);
130 static void m68k_sched_dfa_pre_advance_cycle (void);
131 static void m68k_sched_dfa_post_advance_cycle (void);
132 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
134 static bool m68k_handle_option (size_t, const char *, int);
135 static rtx
find_addr_reg (rtx
);
136 static const char *singlemove_string (rtx
*);
137 #ifdef M68K_TARGET_COFF
138 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
139 #endif /* M68K_TARGET_COFF */
140 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
141 HOST_WIDE_INT
, tree
);
142 static rtx
m68k_struct_value_rtx (tree
, int);
143 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
144 tree args
, int flags
,
146 static void m68k_compute_frame_layout (void);
147 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
148 static bool m68k_ok_for_sibcall_p (tree
, tree
);
149 static bool m68k_rtx_costs (rtx
, int, int, int *);
150 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
151 static bool m68k_return_in_memory (tree
, tree
);
155 /* Specify the identification number of the library being built */
156 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
158 /* Nonzero if the last compare/test insn had FP operands. The
159 sCC expanders peek at this to determine what to do for the
160 68060, which has no fsCC instructions. */
161 int m68k_last_compare_had_fp_operands
;
163 /* Initialize the GCC target structure. */
165 #if INT_OP_GROUP == INT_OP_DOT_WORD
166 #undef TARGET_ASM_ALIGNED_HI_OP
167 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
170 #if INT_OP_GROUP == INT_OP_NO_DOT
171 #undef TARGET_ASM_BYTE_OP
172 #define TARGET_ASM_BYTE_OP "\tbyte\t"
173 #undef TARGET_ASM_ALIGNED_HI_OP
174 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
175 #undef TARGET_ASM_ALIGNED_SI_OP
176 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
179 #if INT_OP_GROUP == INT_OP_DC
180 #undef TARGET_ASM_BYTE_OP
181 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
182 #undef TARGET_ASM_ALIGNED_HI_OP
183 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
184 #undef TARGET_ASM_ALIGNED_SI_OP
185 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
188 #undef TARGET_ASM_UNALIGNED_HI_OP
189 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
190 #undef TARGET_ASM_UNALIGNED_SI_OP
191 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
193 #undef TARGET_ASM_OUTPUT_MI_THUNK
194 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
195 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
196 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
198 #undef TARGET_ASM_FILE_START_APP_OFF
199 #define TARGET_ASM_FILE_START_APP_OFF true
201 #undef TARGET_SCHED_ADJUST_COST
202 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
204 #undef TARGET_SCHED_ISSUE_RATE
205 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
207 #undef TARGET_SCHED_VARIABLE_ISSUE
208 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
210 #undef TARGET_SCHED_INIT_GLOBAL
211 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
213 #undef TARGET_SCHED_FINISH_GLOBAL
214 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
216 #undef TARGET_SCHED_INIT
217 #define TARGET_SCHED_INIT m68k_sched_md_init
219 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
220 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
222 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
223 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
225 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
226 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
227 m68k_sched_first_cycle_multipass_dfa_lookahead
229 #undef TARGET_HANDLE_OPTION
230 #define TARGET_HANDLE_OPTION m68k_handle_option
232 #undef TARGET_RTX_COSTS
233 #define TARGET_RTX_COSTS m68k_rtx_costs
235 #undef TARGET_ATTRIBUTE_TABLE
236 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
238 #undef TARGET_PROMOTE_PROTOTYPES
239 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
241 #undef TARGET_STRUCT_VALUE_RTX
242 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
244 #undef TARGET_CANNOT_FORCE_CONST_MEM
245 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
247 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
248 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
250 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
251 #undef TARGET_RETURN_IN_MEMORY
252 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
255 static const struct attribute_spec m68k_attribute_table
[] =
257 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
258 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
259 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
260 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
261 { NULL
, 0, 0, false, false, false, NULL
}
264 struct gcc_target targetm
= TARGET_INITIALIZER
;
266 /* Base flags for 68k ISAs. */
267 #define FL_FOR_isa_00 FL_ISA_68000
268 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
269 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
270 generated 68881 code for 68020 and 68030 targets unless explicitly told
272 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
273 | FL_BITFIELD | FL_68881)
274 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
275 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
277 /* Base flags for ColdFire ISAs. */
278 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
279 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
280 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
281 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
282 /* ISA_C is not upwardly compatible with ISA_B. */
283 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
287 /* Traditional 68000 instruction sets. */
293 /* ColdFire instruction set variants. */
301 /* Information about one of the -march, -mcpu or -mtune arguments. */
302 struct m68k_target_selection
304 /* The argument being described. */
307 /* For -mcpu, this is the device selected by the option.
308 For -mtune and -march, it is a representative device
309 for the microarchitecture or ISA respectively. */
310 enum target_device device
;
312 /* The M68K_DEVICE fields associated with DEVICE. See the comment
313 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
315 enum uarch_type microarch
;
320 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
321 static const struct m68k_target_selection all_devices
[] =
323 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
324 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
325 #include "m68k-devices.def"
327 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
330 /* A list of all ISAs, mapping each one to a representative device.
331 Used for -march selection. */
332 static const struct m68k_target_selection all_isas
[] =
334 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
335 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
336 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
337 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
338 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
339 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
340 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
341 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
343 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
345 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
346 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
348 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
351 /* A list of all microarchitectures, mapping each one to a representative
352 device. Used for -mtune selection. */
353 static const struct m68k_target_selection all_microarchs
[] =
355 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
356 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
357 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
358 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
359 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
360 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
361 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
362 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
363 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
364 { "cfv1", mcf51qe
, NULL
, ucfv1
, isa_c
, FL_FOR_isa_c
},
365 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
366 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
368 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
369 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
373 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
376 /* The entries associated with the -mcpu, -march and -mtune settings,
377 or null for options that have not been used. */
378 const struct m68k_target_selection
*m68k_cpu_entry
;
379 const struct m68k_target_selection
*m68k_arch_entry
;
380 const struct m68k_target_selection
*m68k_tune_entry
;
382 /* Which CPU we are generating code for. */
383 enum target_device m68k_cpu
;
385 /* Which microarchitecture to tune for. */
386 enum uarch_type m68k_tune
;
388 /* Which FPU to use. */
389 enum fpu_type m68k_fpu
;
391 /* The set of FL_* flags that apply to the target processor. */
392 unsigned int m68k_cpu_flags
;
394 /* Asm templates for calling or jumping to an arbitrary symbolic address,
395 or NULL if such calls or jumps are not supported. The address is held
397 const char *m68k_symbolic_call
;
398 const char *m68k_symbolic_jump
;
400 /* Enum variable that corresponds to m68k_symbolic_call values. */
401 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
404 /* See whether TABLE has an entry with name NAME. Return true and
405 store the entry in *ENTRY if so, otherwise return false and
406 leave *ENTRY alone. */
409 m68k_find_selection (const struct m68k_target_selection
**entry
,
410 const struct m68k_target_selection
*table
,
415 for (i
= 0; table
[i
].name
; i
++)
416 if (strcmp (table
[i
].name
, name
) == 0)
424 /* Implement TARGET_HANDLE_OPTION. */
427 m68k_handle_option (size_t code
, const char *arg
, int value
)
432 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
435 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
438 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
441 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
444 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
447 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
450 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
453 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
456 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
460 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
463 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
467 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
470 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
472 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
475 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
477 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
480 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
483 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
486 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
489 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
493 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
495 case OPT_mshared_library_id_
:
496 if (value
> MAX_LIBRARY_ID
)
497 error ("-mshared-library-id=%s is not between 0 and %d",
498 arg
, MAX_LIBRARY_ID
);
500 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
508 /* Sometimes certain combinations of command options do not make
509 sense on a particular target machine. You can define a macro
510 `OVERRIDE_OPTIONS' to take account of this. This macro, if
511 defined, is executed once just after all the command options have
514 Don't use this macro to turn on various extra optimizations for
515 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
518 override_options (void)
520 const struct m68k_target_selection
*entry
;
521 unsigned long target_mask
;
529 -march=ARCH should generate code that runs any processor
530 implementing architecture ARCH. -mcpu=CPU should override -march
531 and should generate code that runs on processor CPU, making free
532 use of any instructions that CPU understands. -mtune=UARCH applies
533 on top of -mcpu or -march and optimizes the code for UARCH. It does
534 not change the target architecture. */
537 /* Complain if the -march setting is for a different microarchitecture,
538 or includes flags that the -mcpu setting doesn't. */
540 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
541 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
542 warning (0, "-mcpu=%s conflicts with -march=%s",
543 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
545 entry
= m68k_cpu_entry
;
548 entry
= m68k_arch_entry
;
551 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
553 m68k_cpu_flags
= entry
->flags
;
555 /* Use the architecture setting to derive default values for
559 /* ColdFire is lenient about alignment. */
560 if (!TARGET_COLDFIRE
)
561 target_mask
|= MASK_STRICT_ALIGNMENT
;
563 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
564 target_mask
|= MASK_BITFIELD
;
565 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
566 target_mask
|= MASK_CF_HWDIV
;
567 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
568 target_mask
|= MASK_HARD_FLOAT
;
569 target_flags
|= target_mask
& ~target_flags_explicit
;
571 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
572 m68k_cpu
= entry
->device
;
574 m68k_tune
= m68k_tune_entry
->microarch
;
575 #ifdef M68K_DEFAULT_TUNE
576 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
577 m68k_tune
= M68K_DEFAULT_TUNE
;
580 m68k_tune
= entry
->microarch
;
582 /* Set the type of FPU. */
583 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
584 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
587 /* Sanity check to ensure that msep-data and mid-sahred-library are not
588 * both specified together. Doing so simply doesn't make sense.
590 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
591 error ("cannot specify both -msep-data and -mid-shared-library");
593 /* If we're generating code for a separate A5 relative data segment,
594 * we've got to enable -fPIC as well. This might be relaxable to
595 * -fpic but it hasn't been tested properly.
597 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
600 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
601 error if the target does not support them. */
602 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
603 error ("-mpcrel -fPIC is not currently supported on selected cpu");
605 /* ??? A historic way of turning on pic, or is this intended to
606 be an embedded thing that doesn't have the same name binding
607 significance that it does on hosted ELF systems? */
608 if (TARGET_PCREL
&& flag_pic
== 0)
613 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
615 m68k_symbolic_jump
= "jra %a0";
617 else if (TARGET_ID_SHARED_LIBRARY
)
618 /* All addresses must be loaded from the GOT. */
620 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
623 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
625 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
628 /* No unconditional long branch */;
629 else if (TARGET_PCREL
)
630 m68k_symbolic_jump
= "bra%.l %c0";
632 m68k_symbolic_jump
= "bra%.l %p0";
633 /* Turn off function cse if we are doing PIC. We always want
634 function call to be done as `bsr foo@PLTPC'. */
635 /* ??? It's traditional to do this for -mpcrel too, but it isn't
636 clear how intentional that is. */
637 flag_no_function_cse
= 1;
640 switch (m68k_symbolic_call_var
)
642 case M68K_SYMBOLIC_CALL_JSR
:
643 m68k_symbolic_call
= "jsr %a0";
646 case M68K_SYMBOLIC_CALL_BSR_C
:
647 m68k_symbolic_call
= "bsr%.l %c0";
650 case M68K_SYMBOLIC_CALL_BSR_P
:
651 m68k_symbolic_call
= "bsr%.l %p0";
654 case M68K_SYMBOLIC_CALL_NONE
:
655 gcc_assert (m68k_symbolic_call
== NULL
);
662 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
663 if (align_labels
> 2)
665 warning (0, "-falign-labels=%d is not supported", align_labels
);
670 warning (0, "-falign-loops=%d is not supported", align_loops
);
675 SUBTARGET_OVERRIDE_OPTIONS
;
677 /* Setup scheduling options. */
679 m68k_sched_cpu
= CPU_CFV1
;
681 m68k_sched_cpu
= CPU_CFV2
;
683 m68k_sched_cpu
= CPU_CFV3
;
685 m68k_sched_cpu
= CPU_CFV4
;
688 m68k_sched_cpu
= CPU_UNKNOWN
;
689 flag_schedule_insns
= 0;
690 flag_schedule_insns_after_reload
= 0;
691 flag_modulo_sched
= 0;
694 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
696 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
697 m68k_sched_mac
= MAC_CF_EMAC
;
698 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
699 m68k_sched_mac
= MAC_CF_MAC
;
701 m68k_sched_mac
= MAC_NO
;
705 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
706 given argument and NAME is the argument passed to -mcpu. Return NULL
707 if -mcpu was not passed. */
710 m68k_cpp_cpu_ident (const char *prefix
)
714 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
717 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
718 given argument and NAME is the name of the representative device for
719 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
722 m68k_cpp_cpu_family (const char *prefix
)
726 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
729 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
730 "interrupt_handler" attribute and interrupt_thread if FUNC has an
731 "interrupt_thread" attribute. Otherwise, return
732 m68k_fk_normal_function. */
734 enum m68k_function_kind
735 m68k_get_function_kind (tree func
)
739 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
741 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
743 return m68k_fk_interrupt_handler
;
745 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
747 return m68k_fk_interrupt_handler
;
749 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
751 return m68k_fk_interrupt_thread
;
753 return m68k_fk_normal_function
;
756 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
757 struct attribute_spec.handler. */
759 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
760 tree args ATTRIBUTE_UNUSED
,
761 int flags ATTRIBUTE_UNUSED
,
764 if (TREE_CODE (*node
) != FUNCTION_DECL
)
766 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
767 IDENTIFIER_POINTER (name
));
768 *no_add_attrs
= true;
771 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
773 error ("multiple interrupt attributes not allowed");
774 *no_add_attrs
= true;
778 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
780 error ("interrupt_thread is available only on fido");
781 *no_add_attrs
= true;
788 m68k_compute_frame_layout (void)
792 enum m68k_function_kind func_kind
=
793 m68k_get_function_kind (current_function_decl
);
794 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
795 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
797 /* Only compute the frame once per function.
798 Don't cache information until reload has been completed. */
799 if (current_frame
.funcdef_no
== current_function_funcdef_no
803 current_frame
.size
= (get_frame_size () + 3) & -4;
807 /* Interrupt thread does not need to save any register. */
808 if (!interrupt_thread
)
809 for (regno
= 0; regno
< 16; regno
++)
810 if (m68k_save_reg (regno
, interrupt_handler
))
812 mask
|= 1 << (regno
- D0_REG
);
815 current_frame
.offset
= saved
* 4;
816 current_frame
.reg_no
= saved
;
817 current_frame
.reg_mask
= mask
;
819 current_frame
.foffset
= 0;
821 if (TARGET_HARD_FLOAT
)
823 /* Interrupt thread does not need to save any register. */
824 if (!interrupt_thread
)
825 for (regno
= 16; regno
< 24; regno
++)
826 if (m68k_save_reg (regno
, interrupt_handler
))
828 mask
|= 1 << (regno
- FP0_REG
);
831 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
832 current_frame
.offset
+= current_frame
.foffset
;
834 current_frame
.fpu_no
= saved
;
835 current_frame
.fpu_mask
= mask
;
837 /* Remember what function this frame refers to. */
838 current_frame
.funcdef_no
= current_function_funcdef_no
;
842 m68k_initial_elimination_offset (int from
, int to
)
845 /* The arg pointer points 8 bytes before the start of the arguments,
846 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
847 frame pointer in most frames. */
848 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
849 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
850 return argptr_offset
;
852 m68k_compute_frame_layout ();
854 gcc_assert (to
== STACK_POINTER_REGNUM
);
857 case ARG_POINTER_REGNUM
:
858 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
859 case FRAME_POINTER_REGNUM
:
860 return current_frame
.offset
+ current_frame
.size
;
866 /* Refer to the array `regs_ever_live' to determine which registers
867 to save; `regs_ever_live[I]' is nonzero if register number I
868 is ever used in the function. This function is responsible for
869 knowing which registers should not be saved even if used.
870 Return true if we need to save REGNO. */
873 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
875 if (flag_pic
&& regno
== PIC_REG
)
877 if (crtl
->saves_all_registers
)
879 if (crtl
->uses_pic_offset_table
)
881 /* Reload may introduce constant pool references into a function
882 that thitherto didn't need a PIC register. Note that the test
883 above will not catch that case because we will only set
884 crtl->uses_pic_offset_table when emitting
885 the address reloads. */
886 if (crtl
->uses_const_pool
)
890 if (crtl
->calls_eh_return
)
895 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
896 if (test
== INVALID_REGNUM
)
903 /* Fixed regs we never touch. */
904 if (fixed_regs
[regno
])
907 /* The frame pointer (if it is such) is handled specially. */
908 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
911 /* Interrupt handlers must also save call_used_regs
912 if they are live or when calling nested functions. */
913 if (interrupt_handler
)
915 if (df_regs_ever_live_p (regno
))
918 if (!current_function_is_leaf
&& call_used_regs
[regno
])
922 /* Never need to save registers that aren't touched. */
923 if (!df_regs_ever_live_p (regno
))
926 /* Otherwise save everything that isn't call-clobbered. */
927 return !call_used_regs
[regno
];
930 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
931 the lowest memory address. COUNT is the number of registers to be
932 moved, with register REGNO + I being moved if bit I of MASK is set.
933 STORE_P specifies the direction of the move and ADJUST_STACK_P says
934 whether or not this is pre-decrement (if STORE_P) or post-increment
935 (if !STORE_P) operation. */
938 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
939 unsigned int count
, unsigned int regno
,
940 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
943 rtx body
, addr
, src
, operands
[2];
944 enum machine_mode mode
;
946 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
947 mode
= reg_raw_mode
[regno
];
952 src
= plus_constant (base
, (count
953 * GET_MODE_SIZE (mode
)
954 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
955 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
958 for (; mask
!= 0; mask
>>= 1, regno
++)
961 addr
= plus_constant (base
, offset
);
962 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
963 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
964 XVECEXP (body
, 0, i
++)
965 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
966 offset
+= GET_MODE_SIZE (mode
);
968 gcc_assert (i
== XVECLEN (body
, 0));
970 return emit_insn (body
);
973 /* Make INSN a frame-related instruction. */
976 m68k_set_frame_related (rtx insn
)
981 RTX_FRAME_RELATED_P (insn
) = 1;
982 body
= PATTERN (insn
);
983 if (GET_CODE (body
) == PARALLEL
)
984 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
985 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
988 /* Emit RTL for the "prologue" define_expand. */
991 m68k_expand_prologue (void)
993 HOST_WIDE_INT fsize_with_regs
;
994 rtx limit
, src
, dest
, insn
;
996 m68k_compute_frame_layout ();
998 /* If the stack limit is a symbol, we can check it here,
999 before actually allocating the space. */
1000 if (crtl
->limit_stack
1001 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1003 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
1004 if (!LEGITIMATE_CONSTANT_P (limit
))
1006 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1007 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1009 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
1010 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
1011 cc0_rtx
, const0_rtx
),
1015 fsize_with_regs
= current_frame
.size
;
1016 if (TARGET_COLDFIRE
)
1018 /* ColdFire's move multiple instructions do not allow pre-decrement
1019 addressing. Add the size of movem saves to the initial stack
1020 allocation instead. */
1021 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1022 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1023 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1024 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1027 if (frame_pointer_needed
)
1029 if (fsize_with_regs
== 0 && TUNE_68040
)
1031 /* On the 68040, two separate moves are faster than link.w 0. */
1032 dest
= gen_frame_mem (Pmode
,
1033 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1034 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1035 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1036 stack_pointer_rtx
));
1038 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1039 m68k_set_frame_related
1040 (emit_insn (gen_link (frame_pointer_rtx
,
1041 GEN_INT (-4 - fsize_with_regs
))));
1044 m68k_set_frame_related
1045 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1046 m68k_set_frame_related
1047 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1049 GEN_INT (-fsize_with_regs
))));
1052 /* If the frame pointer is needed, emit a special barrier that
1053 will prevent the scheduler from moving stores to the frame
1054 before the stack adjustment. */
1055 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1057 else if (fsize_with_regs
!= 0)
1058 m68k_set_frame_related
1059 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1061 GEN_INT (-fsize_with_regs
))));
1063 if (current_frame
.fpu_mask
)
1065 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1067 m68k_set_frame_related
1068 (m68k_emit_movem (stack_pointer_rtx
,
1069 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1070 current_frame
.fpu_no
, FP0_REG
,
1071 current_frame
.fpu_mask
, true, true));
1076 /* If we're using moveml to save the integer registers,
1077 the stack pointer will point to the bottom of the moveml
1078 save area. Find the stack offset of the first FP register. */
1079 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1082 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1083 m68k_set_frame_related
1084 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1085 current_frame
.fpu_no
, FP0_REG
,
1086 current_frame
.fpu_mask
, true, false));
1090 /* If the stack limit is not a symbol, check it here.
1091 This has the disadvantage that it may be too late... */
1092 if (crtl
->limit_stack
)
1094 if (REG_P (stack_limit_rtx
))
1096 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
1097 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
1098 cc0_rtx
, const0_rtx
),
1101 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1102 warning (0, "stack limit expression is not supported");
1105 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1107 /* Store each register separately in the same order moveml does. */
1110 for (i
= 16; i
-- > 0; )
1111 if (current_frame
.reg_mask
& (1 << i
))
1113 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1114 dest
= gen_frame_mem (SImode
,
1115 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1116 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1121 if (TARGET_COLDFIRE
)
1122 /* The required register save space has already been allocated.
1123 The first register should be stored at (%sp). */
1124 m68k_set_frame_related
1125 (m68k_emit_movem (stack_pointer_rtx
, 0,
1126 current_frame
.reg_no
, D0_REG
,
1127 current_frame
.reg_mask
, true, false));
1129 m68k_set_frame_related
1130 (m68k_emit_movem (stack_pointer_rtx
,
1131 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1132 current_frame
.reg_no
, D0_REG
,
1133 current_frame
.reg_mask
, true, true));
1138 && crtl
->uses_pic_offset_table
)
1139 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
1142 /* Return true if a simple (return) instruction is sufficient for this
1143 instruction (i.e. if no epilogue is needed). */
1146 m68k_use_return_insn (void)
1148 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1151 m68k_compute_frame_layout ();
1152 return current_frame
.offset
== 0;
1155 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1156 SIBCALL_P says which.
1158 The function epilogue should not depend on the current stack pointer!
1159 It should use the frame pointer only, if there is a frame pointer.
1160 This is mandatory because of alloca; we also take advantage of it to
1161 omit stack adjustments before returning. */
1164 m68k_expand_epilogue (bool sibcall_p
)
1166 HOST_WIDE_INT fsize
, fsize_with_regs
;
1167 bool big
, restore_from_sp
;
1169 m68k_compute_frame_layout ();
1171 fsize
= current_frame
.size
;
1173 restore_from_sp
= false;
1175 /* FIXME : current_function_is_leaf below is too strong.
1176 What we really need to know there is if there could be pending
1177 stack adjustment needed at that point. */
1178 restore_from_sp
= (!frame_pointer_needed
1179 || (!cfun
->calls_alloca
1180 && current_function_is_leaf
));
1182 /* fsize_with_regs is the size we need to adjust the sp when
1183 popping the frame. */
1184 fsize_with_regs
= fsize
;
1185 if (TARGET_COLDFIRE
&& restore_from_sp
)
1187 /* ColdFire's move multiple instructions do not allow post-increment
1188 addressing. Add the size of movem loads to the final deallocation
1190 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1191 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1192 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1193 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1196 if (current_frame
.offset
+ fsize
>= 0x8000
1198 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1201 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1202 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1204 /* ColdFire's move multiple instructions do not support the
1205 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1206 stack-based restore. */
1207 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1208 GEN_INT (-(current_frame
.offset
+ fsize
)));
1209 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1210 gen_rtx_REG (Pmode
, A1_REG
),
1211 frame_pointer_rtx
));
1212 restore_from_sp
= true;
1216 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1222 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1224 /* Restore each register separately in the same order moveml does. */
1226 HOST_WIDE_INT offset
;
1228 offset
= current_frame
.offset
+ fsize
;
1229 for (i
= 0; i
< 16; i
++)
1230 if (current_frame
.reg_mask
& (1 << i
))
1236 /* Generate the address -OFFSET(%fp,%a1.l). */
1237 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1238 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1239 addr
= plus_constant (addr
, -offset
);
1241 else if (restore_from_sp
)
1242 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1244 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1245 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1246 gen_frame_mem (SImode
, addr
));
1247 offset
-= GET_MODE_SIZE (SImode
);
1250 else if (current_frame
.reg_mask
)
1253 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1254 gen_rtx_REG (Pmode
, A1_REG
),
1256 -(current_frame
.offset
+ fsize
),
1257 current_frame
.reg_no
, D0_REG
,
1258 current_frame
.reg_mask
, false, false);
1259 else if (restore_from_sp
)
1260 m68k_emit_movem (stack_pointer_rtx
, 0,
1261 current_frame
.reg_no
, D0_REG
,
1262 current_frame
.reg_mask
, false,
1265 m68k_emit_movem (frame_pointer_rtx
,
1266 -(current_frame
.offset
+ fsize
),
1267 current_frame
.reg_no
, D0_REG
,
1268 current_frame
.reg_mask
, false, false);
1271 if (current_frame
.fpu_no
> 0)
1274 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1275 gen_rtx_REG (Pmode
, A1_REG
),
1277 -(current_frame
.foffset
+ fsize
),
1278 current_frame
.fpu_no
, FP0_REG
,
1279 current_frame
.fpu_mask
, false, false);
1280 else if (restore_from_sp
)
1282 if (TARGET_COLDFIRE
)
1286 /* If we used moveml to restore the integer registers, the
1287 stack pointer will still point to the bottom of the moveml
1288 save area. Find the stack offset of the first FP
1290 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1293 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1294 m68k_emit_movem (stack_pointer_rtx
, offset
,
1295 current_frame
.fpu_no
, FP0_REG
,
1296 current_frame
.fpu_mask
, false, false);
1299 m68k_emit_movem (stack_pointer_rtx
, 0,
1300 current_frame
.fpu_no
, FP0_REG
,
1301 current_frame
.fpu_mask
, false, true);
1304 m68k_emit_movem (frame_pointer_rtx
,
1305 -(current_frame
.foffset
+ fsize
),
1306 current_frame
.fpu_no
, FP0_REG
,
1307 current_frame
.fpu_mask
, false, false);
1310 if (frame_pointer_needed
)
1311 emit_insn (gen_unlink (frame_pointer_rtx
));
1312 else if (fsize_with_regs
)
1313 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1315 GEN_INT (fsize_with_regs
)));
1317 if (crtl
->calls_eh_return
)
1318 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1320 EH_RETURN_STACKADJ_RTX
));
1323 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1326 /* Return true if X is a valid comparison operator for the dbcc
1329 Note it rejects floating point comparison operators.
1330 (In the future we could use Fdbcc).
1332 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1335 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1337 switch (GET_CODE (x
))
1339 case EQ
: case NE
: case GTU
: case LTU
:
1343 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1345 case GT
: case LT
: case GE
: case LE
:
1346 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1352 /* Return nonzero if flags are currently in the 68881 flag register. */
1354 flags_in_68881 (void)
1356 /* We could add support for these in the future */
1357 return cc_status
.flags
& CC_IN_68881
;
1360 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1363 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1365 enum m68k_function_kind kind
;
1367 /* We cannot use sibcalls for nested functions because we use the
1368 static chain register for indirect calls. */
1369 if (CALL_EXPR_STATIC_CHAIN (exp
))
1372 kind
= m68k_get_function_kind (current_function_decl
);
1373 if (kind
== m68k_fk_normal_function
)
1374 /* We can always sibcall from a normal function, because it's
1375 undefined if it is calling an interrupt function. */
1378 /* Otherwise we can only sibcall if the function kind is known to be
1380 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1386 /* Convert X to a legitimate function call memory reference and return the
1390 m68k_legitimize_call_address (rtx x
)
1392 gcc_assert (MEM_P (x
));
1393 if (call_operand (XEXP (x
, 0), VOIDmode
))
1395 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1398 /* Likewise for sibling calls. */
1401 m68k_legitimize_sibcall_address (rtx x
)
1403 gcc_assert (MEM_P (x
));
1404 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1407 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1408 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1411 /* Output a dbCC; jCC sequence. Note we do not handle the
1412 floating point version of this sequence (Fdbcc). We also
1413 do not handle alternative conditions when CC_NO_OVERFLOW is
1414 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1415 kick those out before we get here. */
1418 output_dbcc_and_branch (rtx
*operands
)
1420 switch (GET_CODE (operands
[3]))
1423 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1427 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1431 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1435 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1439 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1443 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1447 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1451 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1455 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1459 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1466 /* If the decrement is to be done in SImode, then we have
1467 to compensate for the fact that dbcc decrements in HImode. */
1468 switch (GET_MODE (operands
[0]))
1471 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1483 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1486 enum rtx_code op_code
= GET_CODE (op
);
1488 /* This does not produce a useful cc. */
1491 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1492 below. Swap the operands and change the op if these requirements
1493 are not fulfilled. */
1494 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1498 operand1
= operand2
;
1500 op_code
= swap_condition (op_code
);
1502 loperands
[0] = operand1
;
1503 if (GET_CODE (operand1
) == REG
)
1504 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1506 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1507 if (operand2
!= const0_rtx
)
1509 loperands
[2] = operand2
;
1510 if (GET_CODE (operand2
) == REG
)
1511 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1513 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1515 loperands
[4] = gen_label_rtx ();
1516 if (operand2
!= const0_rtx
)
1517 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1520 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1521 output_asm_insn ("tst%.l %0", loperands
);
1523 output_asm_insn ("cmp%.w #0,%0", loperands
);
1525 output_asm_insn ("jne %l4", loperands
);
1527 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1528 output_asm_insn ("tst%.l %1", loperands
);
1530 output_asm_insn ("cmp%.w #0,%1", loperands
);
1533 loperands
[5] = dest
;
1538 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1539 CODE_LABEL_NUMBER (loperands
[4]));
1540 output_asm_insn ("seq %5", loperands
);
1544 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1545 CODE_LABEL_NUMBER (loperands
[4]));
1546 output_asm_insn ("sne %5", loperands
);
1550 loperands
[6] = gen_label_rtx ();
1551 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1552 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1553 CODE_LABEL_NUMBER (loperands
[4]));
1554 output_asm_insn ("sgt %5", loperands
);
1555 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1556 CODE_LABEL_NUMBER (loperands
[6]));
1560 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1561 CODE_LABEL_NUMBER (loperands
[4]));
1562 output_asm_insn ("shi %5", loperands
);
1566 loperands
[6] = gen_label_rtx ();
1567 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1568 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1569 CODE_LABEL_NUMBER (loperands
[4]));
1570 output_asm_insn ("slt %5", loperands
);
1571 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1572 CODE_LABEL_NUMBER (loperands
[6]));
1576 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1577 CODE_LABEL_NUMBER (loperands
[4]));
1578 output_asm_insn ("scs %5", loperands
);
1582 loperands
[6] = gen_label_rtx ();
1583 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1584 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1585 CODE_LABEL_NUMBER (loperands
[4]));
1586 output_asm_insn ("sge %5", loperands
);
1587 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1588 CODE_LABEL_NUMBER (loperands
[6]));
1592 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1593 CODE_LABEL_NUMBER (loperands
[4]));
1594 output_asm_insn ("scc %5", loperands
);
1598 loperands
[6] = gen_label_rtx ();
1599 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1600 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1601 CODE_LABEL_NUMBER (loperands
[4]));
1602 output_asm_insn ("sle %5", loperands
);
1603 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1604 CODE_LABEL_NUMBER (loperands
[6]));
1608 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1609 CODE_LABEL_NUMBER (loperands
[4]));
1610 output_asm_insn ("sls %5", loperands
);
1620 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1622 operands
[0] = countop
;
1623 operands
[1] = dataop
;
1625 if (GET_CODE (countop
) == CONST_INT
)
1627 register int count
= INTVAL (countop
);
1628 /* If COUNT is bigger than size of storage unit in use,
1629 advance to the containing unit of same size. */
1630 if (count
> signpos
)
1632 int offset
= (count
& ~signpos
) / 8;
1633 count
= count
& signpos
;
1634 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1636 if (count
== signpos
)
1637 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1639 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1641 /* These three statements used to use next_insns_test_no...
1642 but it appears that this should do the same job. */
1644 && next_insn_tests_no_inequality (insn
))
1647 && next_insn_tests_no_inequality (insn
))
1650 && next_insn_tests_no_inequality (insn
))
1652 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1653 On some m68k variants unfortunately that's slower than btst.
1654 On 68000 and higher, that should also work for all HImode operands. */
1655 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1657 if (count
== 3 && DATA_REG_P (operands
[1])
1658 && next_insn_tests_no_inequality (insn
))
1660 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1661 return "move%.w %1,%%ccr";
1663 if (count
== 2 && DATA_REG_P (operands
[1])
1664 && next_insn_tests_no_inequality (insn
))
1666 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1667 return "move%.w %1,%%ccr";
1669 /* count == 1 followed by bvc/bvs and
1670 count == 0 followed by bcc/bcs are also possible, but need
1671 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1674 cc_status
.flags
= CC_NOT_NEGATIVE
;
1676 return "btst %0,%1";
1679 /* Return true if X is a legitimate base register. STRICT_P says
1680 whether we need strict checking. */
1683 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1685 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1686 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1691 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1692 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1695 /* Return true if X is a legitimate index register. STRICT_P says
1696 whether we need strict checking. */
1699 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1701 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1706 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1707 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1710 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1711 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1712 ADDRESS if so. STRICT_P says whether we need strict checking. */
1715 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1719 /* Check for a scale factor. */
1721 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1722 && GET_CODE (x
) == MULT
1723 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1724 && (INTVAL (XEXP (x
, 1)) == 2
1725 || INTVAL (XEXP (x
, 1)) == 4
1726 || (INTVAL (XEXP (x
, 1)) == 8
1727 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1729 scale
= INTVAL (XEXP (x
, 1));
1733 /* Check for a word extension. */
1734 if (!TARGET_COLDFIRE
1735 && GET_CODE (x
) == SIGN_EXTEND
1736 && GET_MODE (XEXP (x
, 0)) == HImode
)
1739 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1741 address
->scale
= scale
;
1749 /* Return true if X is an illegitimate symbolic constant. */
1752 m68k_illegitimate_symbolic_constant_p (rtx x
)
1756 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1758 split_const (x
, &base
, &offset
);
1759 if (GET_CODE (base
) == SYMBOL_REF
1760 && !offset_within_block_p (base
, INTVAL (offset
)))
1766 /* Return true if X is a legitimate constant address that can reach
1767 bytes in the range [X, X + REACH). STRICT_P says whether we need
1771 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1775 if (!CONSTANT_ADDRESS_P (x
))
1779 && !(strict_p
&& TARGET_PCREL
)
1780 && symbolic_operand (x
, VOIDmode
))
1783 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1785 split_const (x
, &base
, &offset
);
1786 if (GET_CODE (base
) == SYMBOL_REF
1787 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1794 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1795 labels will become jump tables. */
1798 m68k_jump_table_ref_p (rtx x
)
1800 if (GET_CODE (x
) != LABEL_REF
)
1804 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1807 x
= next_nonnote_insn (x
);
1808 return x
&& JUMP_TABLE_DATA_P (x
);
1811 /* Return true if X is a legitimate address for values of mode MODE.
1812 STRICT_P says whether strict checking is needed. If the address
1813 is valid, describe its components in *ADDRESS. */
1816 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1817 bool strict_p
, struct m68k_address
*address
)
1821 memset (address
, 0, sizeof (*address
));
1823 if (mode
== BLKmode
)
1826 reach
= GET_MODE_SIZE (mode
);
1828 /* Check for (An) (mode 2). */
1829 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1835 /* Check for -(An) and (An)+ (modes 3 and 4). */
1836 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1837 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1839 address
->code
= GET_CODE (x
);
1840 address
->base
= XEXP (x
, 0);
1844 /* Check for (d16,An) (mode 5). */
1845 if (GET_CODE (x
) == PLUS
1846 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1847 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1848 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1850 address
->base
= XEXP (x
, 0);
1851 address
->offset
= XEXP (x
, 1);
1855 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1856 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1859 && GET_CODE (x
) == PLUS
1860 && XEXP (x
, 0) == pic_offset_table_rtx
1861 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1862 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1864 address
->base
= XEXP (x
, 0);
1865 address
->offset
= XEXP (x
, 1);
1869 /* The ColdFire FPU only accepts addressing modes 2-5. */
1870 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1873 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1874 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1875 All these modes are variations of mode 7. */
1876 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1878 address
->offset
= x
;
1882 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1885 ??? do_tablejump creates these addresses before placing the target
1886 label, so we have to assume that unplaced labels are jump table
1887 references. It seems unlikely that we would ever generate indexed
1888 accesses to unplaced labels in other cases. */
1889 if (GET_CODE (x
) == PLUS
1890 && m68k_jump_table_ref_p (XEXP (x
, 1))
1891 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1893 address
->offset
= XEXP (x
, 1);
1897 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1898 (bd,An,Xn.SIZE*SCALE) addresses. */
1902 /* Check for a nonzero base displacement. */
1903 if (GET_CODE (x
) == PLUS
1904 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1906 address
->offset
= XEXP (x
, 1);
1910 /* Check for a suppressed index register. */
1911 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1917 /* Check for a suppressed base register. Do not allow this case
1918 for non-symbolic offsets as it effectively gives gcc freedom
1919 to treat data registers as base registers, which can generate
1922 && symbolic_operand (address
->offset
, VOIDmode
)
1923 && m68k_decompose_index (x
, strict_p
, address
))
1928 /* Check for a nonzero base displacement. */
1929 if (GET_CODE (x
) == PLUS
1930 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1931 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1933 address
->offset
= XEXP (x
, 1);
1938 /* We now expect the sum of a base and an index. */
1939 if (GET_CODE (x
) == PLUS
)
1941 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1942 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1944 address
->base
= XEXP (x
, 0);
1948 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1949 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1951 address
->base
= XEXP (x
, 1);
1958 /* Return true if X is a legitimate address for values of mode MODE.
1959 STRICT_P says whether strict checking is needed. */
1962 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1964 struct m68k_address address
;
1966 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1969 /* Return true if X is a memory, describing its address in ADDRESS if so.
1970 Apply strict checking if called during or after reload. */
1973 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1976 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1977 reload_in_progress
|| reload_completed
,
1981 /* Return true if X matches the 'Q' constraint. It must be a memory
1982 with a base address and no constant offset or index. */
1985 m68k_matches_q_p (rtx x
)
1987 struct m68k_address address
;
1989 return (m68k_legitimate_mem_p (x
, &address
)
1990 && address
.code
== UNKNOWN
1996 /* Return true if X matches the 'U' constraint. It must be a base address
1997 with a constant offset and no index. */
2000 m68k_matches_u_p (rtx x
)
2002 struct m68k_address address
;
2004 return (m68k_legitimate_mem_p (x
, &address
)
2005 && address
.code
== UNKNOWN
2011 /* Legitimize PIC addresses. If the address is already
2012 position-independent, we return ORIG. Newly generated
2013 position-independent addresses go to REG. If we need more
2014 than one register, we lose.
2016 An address is legitimized by making an indirect reference
2017 through the Global Offset Table with the name of the symbol
2020 The assembler and linker are responsible for placing the
2021 address of the symbol in the GOT. The function prologue
2022 is responsible for initializing a5 to the starting address
2025 The assembler is also responsible for translating a symbol name
2026 into a constant displacement from the start of the GOT.
2028 A quick example may make things a little clearer:
2030 When not generating PIC code to store the value 12345 into _foo
2031 we would generate the following code:
2035 When generating PIC two transformations are made. First, the compiler
2036 loads the address of foo into a register. So the first transformation makes:
2041 The code in movsi will intercept the lea instruction and call this
2042 routine which will transform the instructions into:
2044 movel a5@(_foo:w), a0
2048 That (in a nutshell) is how *all* symbol and label references are
2052 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2057 /* First handle a simple SYMBOL_REF or LABEL_REF */
2058 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2062 pic_ref
= gen_rtx_MEM (Pmode
,
2063 gen_rtx_PLUS (Pmode
,
2064 pic_offset_table_rtx
, orig
));
2065 crtl
->uses_pic_offset_table
= 1;
2066 MEM_READONLY_P (pic_ref
) = 1;
2067 emit_move_insn (reg
, pic_ref
);
2070 else if (GET_CODE (orig
) == CONST
)
2074 /* Make sure this has not already been legitimized. */
2075 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2076 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2081 /* legitimize both operands of the PLUS */
2082 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2084 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2085 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2086 base
== reg
? 0 : reg
);
2088 if (GET_CODE (orig
) == CONST_INT
)
2089 return plus_constant (base
, INTVAL (orig
));
2090 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2091 /* Likewise, should we set special REG_NOTEs here? */
2098 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2100 /* Return the type of move that should be used for integer I. */
2103 m68k_const_method (HOST_WIDE_INT i
)
2110 /* The ColdFire doesn't have byte or word operations. */
2111 /* FIXME: This may not be useful for the m68060 either. */
2112 if (!TARGET_COLDFIRE
)
2114 /* if -256 < N < 256 but N is not in range for a moveq
2115 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2116 if (USE_MOVQ (i
^ 0xff))
2118 /* Likewise, try with not.w */
2119 if (USE_MOVQ (i
^ 0xffff))
2121 /* This is the only value where neg.w is useful */
2126 /* Try also with swap. */
2128 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2133 /* Try using MVZ/MVS with an immediate value to load constants. */
2134 if (i
>= 0 && i
<= 65535)
2136 if (i
>= -32768 && i
<= 32767)
2140 /* Otherwise, use move.l */
2144 /* Return the cost of moving constant I into a data register. */
2147 const_int_cost (HOST_WIDE_INT i
)
2149 switch (m68k_const_method (i
))
2152 /* Constants between -128 and 127 are cheap due to moveq. */
2160 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2170 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2175 /* Constant zero is super cheap due to clr instruction. */
2176 if (x
== const0_rtx
)
2179 *total
= const_int_cost (INTVAL (x
));
2189 /* Make 0.0 cheaper than other floating constants to
2190 encourage creating tstsf and tstdf insns. */
2191 if (outer_code
== COMPARE
2192 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2198 /* These are vaguely right for a 68020. */
2199 /* The costs for long multiply have been adjusted to work properly
2200 in synth_mult on the 68020, relative to an average of the time
2201 for add and the time for shift, taking away a little more because
2202 sometimes move insns are needed. */
2203 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2209 : TARGET_COLDFIRE ? 3 : 13)
2214 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2215 : TARGET_COLDFIRE ? 2 : 8)
2218 (TARGET_CF_HWDIV ? 11 \
2219 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2222 /* An lea costs about three times as much as a simple add. */
2223 if (GET_MODE (x
) == SImode
2224 && GET_CODE (XEXP (x
, 1)) == REG
2225 && GET_CODE (XEXP (x
, 0)) == MULT
2226 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2227 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2228 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2229 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2230 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2232 /* lea an@(dx:l:i),am */
2233 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2243 *total
= COSTS_N_INSNS(1);
2248 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2250 if (INTVAL (XEXP (x
, 1)) < 16)
2251 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2253 /* We're using clrw + swap for these cases. */
2254 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2257 *total
= COSTS_N_INSNS (10); /* Worst case. */
2260 /* A shift by a big integer takes an extra instruction. */
2261 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2262 && (INTVAL (XEXP (x
, 1)) == 16))
2264 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2267 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2268 && !(INTVAL (XEXP (x
, 1)) > 0
2269 && INTVAL (XEXP (x
, 1)) <= 8))
2271 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2277 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2278 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2279 && GET_MODE (x
) == SImode
)
2280 *total
= COSTS_N_INSNS (MULW_COST
);
2281 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2282 *total
= COSTS_N_INSNS (MULW_COST
);
2284 *total
= COSTS_N_INSNS (MULL_COST
);
2291 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2292 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2293 else if (TARGET_CF_HWDIV
)
2294 *total
= COSTS_N_INSNS (18);
2296 *total
= COSTS_N_INSNS (43); /* div.l */
2304 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2308 output_move_const_into_data_reg (rtx
*operands
)
2312 i
= INTVAL (operands
[1]);
2313 switch (m68k_const_method (i
))
2316 return "mvzw %1,%0";
2318 return "mvsw %1,%0";
2320 return "moveq %1,%0";
2323 operands
[1] = GEN_INT (i
^ 0xff);
2324 return "moveq %1,%0\n\tnot%.b %0";
2327 operands
[1] = GEN_INT (i
^ 0xffff);
2328 return "moveq %1,%0\n\tnot%.w %0";
2331 return "moveq #-128,%0\n\tneg%.w %0";
2336 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2337 return "moveq %1,%0\n\tswap %0";
2340 return "move%.l %1,%0";
2346 /* Return true if I can be handled by ISA B's mov3q instruction. */
2349 valid_mov3q_const (HOST_WIDE_INT i
)
2351 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2354 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2355 I is the value of OPERANDS[1]. */
2358 output_move_simode_const (rtx
*operands
)
2364 src
= INTVAL (operands
[1]);
2366 && (DATA_REG_P (dest
) || MEM_P (dest
))
2367 /* clr insns on 68000 read before writing. */
2368 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2369 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2371 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2372 return "mov3q%.l %1,%0";
2373 else if (src
== 0 && ADDRESS_REG_P (dest
))
2374 return "sub%.l %0,%0";
2375 else if (DATA_REG_P (dest
))
2376 return output_move_const_into_data_reg (operands
);
2377 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2379 if (valid_mov3q_const (src
))
2380 return "mov3q%.l %1,%0";
2381 return "move%.w %1,%0";
2383 else if (MEM_P (dest
)
2384 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2385 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2386 && IN_RANGE (src
, -0x8000, 0x7fff))
2388 if (valid_mov3q_const (src
))
2389 return "mov3q%.l %1,%-";
2392 return "move%.l %1,%0";
2396 output_move_simode (rtx
*operands
)
2398 if (GET_CODE (operands
[1]) == CONST_INT
)
2399 return output_move_simode_const (operands
);
2400 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2401 || GET_CODE (operands
[1]) == CONST
)
2402 && push_operand (operands
[0], SImode
))
2404 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2405 || GET_CODE (operands
[1]) == CONST
)
2406 && ADDRESS_REG_P (operands
[0]))
2407 return "lea %a1,%0";
2408 return "move%.l %1,%0";
2412 output_move_himode (rtx
*operands
)
2414 if (GET_CODE (operands
[1]) == CONST_INT
)
2416 if (operands
[1] == const0_rtx
2417 && (DATA_REG_P (operands
[0])
2418 || GET_CODE (operands
[0]) == MEM
)
2419 /* clr insns on 68000 read before writing. */
2420 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2421 || !(GET_CODE (operands
[0]) == MEM
2422 && MEM_VOLATILE_P (operands
[0]))))
2424 else if (operands
[1] == const0_rtx
2425 && ADDRESS_REG_P (operands
[0]))
2426 return "sub%.l %0,%0";
2427 else if (DATA_REG_P (operands
[0])
2428 && INTVAL (operands
[1]) < 128
2429 && INTVAL (operands
[1]) >= -128)
2430 return "moveq %1,%0";
2431 else if (INTVAL (operands
[1]) < 0x8000
2432 && INTVAL (operands
[1]) >= -0x8000)
2433 return "move%.w %1,%0";
2435 else if (CONSTANT_P (operands
[1]))
2436 return "move%.l %1,%0";
2437 return "move%.w %1,%0";
2441 output_move_qimode (rtx
*operands
)
2443 /* 68k family always modifies the stack pointer by at least 2, even for
2444 byte pushes. The 5200 (ColdFire) does not do this. */
2446 /* This case is generated by pushqi1 pattern now. */
2447 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2448 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2449 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2450 && ! ADDRESS_REG_P (operands
[1])
2451 && ! TARGET_COLDFIRE
));
2453 /* clr and st insns on 68000 read before writing. */
2454 if (!ADDRESS_REG_P (operands
[0])
2455 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2456 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2458 if (operands
[1] == const0_rtx
)
2460 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2461 && GET_CODE (operands
[1]) == CONST_INT
2462 && (INTVAL (operands
[1]) & 255) == 255)
2468 if (GET_CODE (operands
[1]) == CONST_INT
2469 && DATA_REG_P (operands
[0])
2470 && INTVAL (operands
[1]) < 128
2471 && INTVAL (operands
[1]) >= -128)
2472 return "moveq %1,%0";
2473 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2474 return "sub%.l %0,%0";
2475 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2476 return "move%.l %1,%0";
2477 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2478 from address registers. */
2479 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2480 return "move%.w %1,%0";
2481 return "move%.b %1,%0";
2485 output_move_stricthi (rtx
*operands
)
2487 if (operands
[1] == const0_rtx
2488 /* clr insns on 68000 read before writing. */
2489 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2490 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2492 return "move%.w %1,%0";
2496 output_move_strictqi (rtx
*operands
)
2498 if (operands
[1] == const0_rtx
2499 /* clr insns on 68000 read before writing. */
2500 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2501 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2503 return "move%.b %1,%0";
2506 /* Return the best assembler insn template
2507 for moving operands[1] into operands[0] as a fullword. */
2510 singlemove_string (rtx
*operands
)
2512 if (GET_CODE (operands
[1]) == CONST_INT
)
2513 return output_move_simode_const (operands
);
2514 return "move%.l %1,%0";
2518 /* Output assembler or rtl code to perform a doubleword move insn
2519 with operands OPERANDS.
2520 Pointers to 3 helper functions should be specified:
2521 HANDLE_REG_ADJUST to adjust a register by a small value,
2522 HANDLE_COMPADR to compute an address and
2523 HANDLE_MOVSI to move 4 bytes. */
2526 handle_move_double (rtx operands
[2],
2527 void (*handle_reg_adjust
) (rtx
, int),
2528 void (*handle_compadr
) (rtx
[2]),
2529 void (*handle_movsi
) (rtx
[2]))
2533 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2538 rtx addreg0
= 0, addreg1
= 0;
2539 int dest_overlapped_low
= 0;
2540 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2545 /* First classify both operands. */
2547 if (REG_P (operands
[0]))
2549 else if (offsettable_memref_p (operands
[0]))
2551 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2553 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2555 else if (GET_CODE (operands
[0]) == MEM
)
2560 if (REG_P (operands
[1]))
2562 else if (CONSTANT_P (operands
[1]))
2564 else if (offsettable_memref_p (operands
[1]))
2566 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2568 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2570 else if (GET_CODE (operands
[1]) == MEM
)
2575 /* Check for the cases that the operand constraints are not supposed
2576 to allow to happen. Generating code for these cases is
2578 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2580 /* If one operand is decrementing and one is incrementing
2581 decrement the former register explicitly
2582 and change that operand into ordinary indexing. */
2584 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2586 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2588 handle_reg_adjust (operands
[0], -size
);
2590 if (GET_MODE (operands
[1]) == XFmode
)
2591 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2592 else if (GET_MODE (operands
[0]) == DFmode
)
2593 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2595 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2598 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2600 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2602 handle_reg_adjust (operands
[1], -size
);
2604 if (GET_MODE (operands
[1]) == XFmode
)
2605 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2606 else if (GET_MODE (operands
[1]) == DFmode
)
2607 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2609 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2613 /* If an operand is an unoffsettable memory ref, find a register
2614 we can increment temporarily to make it refer to the second word. */
2616 if (optype0
== MEMOP
)
2617 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2619 if (optype1
== MEMOP
)
2620 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2622 /* Ok, we can do one word at a time.
2623 Normally we do the low-numbered word first,
2624 but if either operand is autodecrementing then we
2625 do the high-numbered word first.
2627 In either case, set up in LATEHALF the operands to use
2628 for the high-numbered word and in some cases alter the
2629 operands in OPERANDS to be suitable for the low-numbered word. */
2633 if (optype0
== REGOP
)
2635 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2636 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2638 else if (optype0
== OFFSOP
)
2640 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2641 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2645 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
2646 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
2649 if (optype1
== REGOP
)
2651 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2652 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2654 else if (optype1
== OFFSOP
)
2656 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2657 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2659 else if (optype1
== CNSTOP
)
2661 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2666 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2667 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2668 operands
[1] = GEN_INT (l
[0]);
2669 middlehalf
[1] = GEN_INT (l
[1]);
2670 latehalf
[1] = GEN_INT (l
[2]);
2674 /* No non-CONST_DOUBLE constant should ever appear
2676 gcc_assert (!CONSTANT_P (operands
[1]));
2681 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
2682 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
2686 /* size is not 12: */
2688 if (optype0
== REGOP
)
2689 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2690 else if (optype0
== OFFSOP
)
2691 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2693 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
2695 if (optype1
== REGOP
)
2696 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2697 else if (optype1
== OFFSOP
)
2698 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2699 else if (optype1
== CNSTOP
)
2700 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2702 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
2705 /* If insn is effectively movd N(sp),-(sp) then we will do the
2706 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2707 for the low word as well, to compensate for the first decrement of sp. */
2708 if (optype0
== PUSHOP
2709 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2710 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2711 operands
[1] = middlehalf
[1] = latehalf
[1];
2713 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2714 if the upper part of reg N does not appear in the MEM, arrange to
2715 emit the move late-half first. Otherwise, compute the MEM address
2716 into the upper part of N and use that as a pointer to the memory
2718 if (optype0
== REGOP
2719 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2721 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2723 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2724 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2726 /* If both halves of dest are used in the src memory address,
2727 compute the address into latehalf of dest.
2728 Note that this can't happen if the dest is two data regs. */
2730 xops
[0] = latehalf
[0];
2731 xops
[1] = XEXP (operands
[1], 0);
2733 handle_compadr (xops
);
2734 if (GET_MODE (operands
[1]) == XFmode
)
2736 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2737 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2738 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2742 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2743 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2747 && reg_overlap_mentioned_p (middlehalf
[0],
2748 XEXP (operands
[1], 0)))
2750 /* Check for two regs used by both source and dest.
2751 Note that this can't happen if the dest is all data regs.
2752 It can happen if the dest is d6, d7, a0.
2753 But in that case, latehalf is an addr reg, so
2754 the code at compadr does ok. */
2756 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2757 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2760 /* JRV says this can't happen: */
2761 gcc_assert (!addreg0
&& !addreg1
);
2763 /* Only the middle reg conflicts; simply put it last. */
2764 handle_movsi (operands
);
2765 handle_movsi (latehalf
);
2766 handle_movsi (middlehalf
);
2770 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2771 /* If the low half of dest is mentioned in the source memory
2772 address, the arrange to emit the move late half first. */
2773 dest_overlapped_low
= 1;
2776 /* If one or both operands autodecrementing,
2777 do the two words, high-numbered first. */
2779 /* Likewise, the first move would clobber the source of the second one,
2780 do them in the other order. This happens only for registers;
2781 such overlap can't happen in memory unless the user explicitly
2782 sets it up, and that is an undefined circumstance. */
2784 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2785 || (optype0
== REGOP
&& optype1
== REGOP
2786 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2787 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2788 || dest_overlapped_low
)
2790 /* Make any unoffsettable addresses point at high-numbered word. */
2792 handle_reg_adjust (addreg0
, size
- 4);
2794 handle_reg_adjust (addreg1
, size
- 4);
2797 handle_movsi (latehalf
);
2799 /* Undo the adds we just did. */
2801 handle_reg_adjust (addreg0
, -4);
2803 handle_reg_adjust (addreg1
, -4);
2807 handle_movsi (middlehalf
);
2810 handle_reg_adjust (addreg0
, -4);
2812 handle_reg_adjust (addreg1
, -4);
2815 /* Do low-numbered word. */
2817 handle_movsi (operands
);
2821 /* Normal case: do the two words, low-numbered first. */
2823 handle_movsi (operands
);
2825 /* Do the middle one of the three words for long double */
2829 handle_reg_adjust (addreg0
, 4);
2831 handle_reg_adjust (addreg1
, 4);
2833 handle_movsi (middlehalf
);
2836 /* Make any unoffsettable addresses point at high-numbered word. */
2838 handle_reg_adjust (addreg0
, 4);
2840 handle_reg_adjust (addreg1
, 4);
2843 handle_movsi (latehalf
);
2845 /* Undo the adds we just did. */
2847 handle_reg_adjust (addreg0
, -(size
- 4));
2849 handle_reg_adjust (addreg1
, -(size
- 4));
2854 /* Output assembler code to adjust REG by N. */
2856 output_reg_adjust (rtx reg
, int n
)
2860 gcc_assert (GET_MODE (reg
) == SImode
2861 && -12 <= n
&& n
!= 0 && n
<= 12);
2866 s
= "add%.l #12,%0";
2870 s
= "addq%.l #8,%0";
2874 s
= "addq%.l #4,%0";
2878 s
= "sub%.l #12,%0";
2882 s
= "subq%.l #8,%0";
2886 s
= "subq%.l #4,%0";
2894 output_asm_insn (s
, ®
);
2897 /* Emit rtl code to adjust REG by N. */
2899 emit_reg_adjust (rtx reg1
, int n
)
2903 gcc_assert (GET_MODE (reg1
) == SImode
2904 && -12 <= n
&& n
!= 0 && n
<= 12);
2906 reg1
= copy_rtx (reg1
);
2907 reg2
= copy_rtx (reg1
);
2910 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
2912 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
2917 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
2919 output_compadr (rtx operands
[2])
2921 output_asm_insn ("lea %a1,%0", operands
);
2924 /* Output the best assembler insn for moving operands[1] into operands[0]
2927 output_movsi (rtx operands
[2])
2929 output_asm_insn (singlemove_string (operands
), operands
);
2932 /* Copy OP and change its mode to MODE. */
2934 copy_operand (rtx op
, enum machine_mode mode
)
2936 /* ??? This looks really ugly. There must be a better way
2937 to change a mode on the operand. */
2938 if (GET_MODE (op
) != VOIDmode
)
2941 op
= gen_rtx_REG (mode
, REGNO (op
));
2945 PUT_MODE (op
, mode
);
2952 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
2954 emit_movsi (rtx operands
[2])
2956 operands
[0] = copy_operand (operands
[0], SImode
);
2957 operands
[1] = copy_operand (operands
[1], SImode
);
2959 emit_insn (gen_movsi (operands
[0], operands
[1]));
2962 /* Output assembler code to perform a doubleword move insn
2963 with operands OPERANDS. */
2965 output_move_double (rtx
*operands
)
2967 handle_move_double (operands
,
2968 output_reg_adjust
, output_compadr
, output_movsi
);
2973 /* Output rtl code to perform a doubleword move insn
2974 with operands OPERANDS. */
2976 m68k_emit_move_double (rtx operands
[2])
2978 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
2981 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2982 new rtx with the correct mode. */
2985 force_mode (enum machine_mode mode
, rtx orig
)
2987 if (mode
== GET_MODE (orig
))
2990 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2993 return gen_rtx_REG (mode
, REGNO (orig
));
2997 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2999 return reg_renumber
&& FP_REG_P (op
);
3002 /* Emit insns to move operands[1] into operands[0].
3004 Return 1 if we have written out everything that needs to be done to
3005 do the move. Otherwise, return 0 and the caller will emit the move
3008 Note SCRATCH_REG may not be in the proper mode depending on how it
3009 will be used. This routine is responsible for creating a new copy
3010 of SCRATCH_REG in the proper mode. */
3013 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3015 register rtx operand0
= operands
[0];
3016 register rtx operand1
= operands
[1];
3020 && reload_in_progress
&& GET_CODE (operand0
) == REG
3021 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3022 operand0
= reg_equiv_mem
[REGNO (operand0
)];
3023 else if (scratch_reg
3024 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3025 && GET_CODE (SUBREG_REG (operand0
)) == REG
3026 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3028 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3029 the code which tracks sets/uses for delete_output_reload. */
3030 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3031 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
3032 SUBREG_BYTE (operand0
));
3033 operand0
= alter_subreg (&temp
);
3037 && reload_in_progress
&& GET_CODE (operand1
) == REG
3038 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3039 operand1
= reg_equiv_mem
[REGNO (operand1
)];
3040 else if (scratch_reg
3041 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3042 && GET_CODE (SUBREG_REG (operand1
)) == REG
3043 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3045 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3046 the code which tracks sets/uses for delete_output_reload. */
3047 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3048 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
3049 SUBREG_BYTE (operand1
));
3050 operand1
= alter_subreg (&temp
);
3053 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3054 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3055 != XEXP (operand0
, 0)))
3056 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3057 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3058 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3059 != XEXP (operand1
, 0)))
3060 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3062 /* Handle secondary reloads for loads/stores of FP registers where
3063 the address is symbolic by using the scratch register */
3064 if (fp_reg_operand (operand0
, mode
)
3065 && ((GET_CODE (operand1
) == MEM
3066 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3067 || ((GET_CODE (operand1
) == SUBREG
3068 && GET_CODE (XEXP (operand1
, 0)) == MEM
3069 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3072 if (GET_CODE (operand1
) == SUBREG
)
3073 operand1
= XEXP (operand1
, 0);
3075 /* SCRATCH_REG will hold an address. We want
3076 it in SImode regardless of what mode it was originally given
3078 scratch_reg
= force_mode (SImode
, scratch_reg
);
3080 /* D might not fit in 14 bits either; for such cases load D into
3082 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3084 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3085 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3087 XEXP (XEXP (operand1
, 0), 0),
3091 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3092 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3093 gen_rtx_MEM (mode
, scratch_reg
)));
3096 else if (fp_reg_operand (operand1
, mode
)
3097 && ((GET_CODE (operand0
) == MEM
3098 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3099 || ((GET_CODE (operand0
) == SUBREG
)
3100 && GET_CODE (XEXP (operand0
, 0)) == MEM
3101 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3104 if (GET_CODE (operand0
) == SUBREG
)
3105 operand0
= XEXP (operand0
, 0);
3107 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3108 it in SIMODE regardless of what mode it was originally given
3110 scratch_reg
= force_mode (SImode
, scratch_reg
);
3112 /* D might not fit in 14 bits either; for such cases load D into
3114 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3116 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3117 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3120 XEXP (XEXP (operand0
, 0),
3125 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3126 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3130 /* Handle secondary reloads for loads of FP registers from constant
3131 expressions by forcing the constant into memory.
3133 use scratch_reg to hold the address of the memory location.
3135 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3136 NO_REGS when presented with a const_int and an register class
3137 containing only FP registers. Doing so unfortunately creates
3138 more problems than it solves. Fix this for 2.5. */
3139 else if (fp_reg_operand (operand0
, mode
)
3140 && CONSTANT_P (operand1
)
3145 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3146 it in SIMODE regardless of what mode it was originally given
3148 scratch_reg
= force_mode (SImode
, scratch_reg
);
3150 /* Force the constant into memory and put the address of the
3151 memory location into scratch_reg. */
3152 xoperands
[0] = scratch_reg
;
3153 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3154 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3156 /* Now load the destination register. */
3157 emit_insn (gen_rtx_SET (mode
, operand0
,
3158 gen_rtx_MEM (mode
, scratch_reg
)));
3162 /* Now have insn-emit do whatever it normally does. */
3166 /* Split one or more DImode RTL references into pairs of SImode
3167 references. The RTL can be REG, offsettable MEM, integer constant, or
3168 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3169 split and "num" is its length. lo_half and hi_half are output arrays
3170 that parallel "operands". */
3173 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3177 rtx op
= operands
[num
];
3179 /* simplify_subreg refuses to split volatile memory addresses,
3180 but we still have to handle it. */
3181 if (GET_CODE (op
) == MEM
)
3183 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3184 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3188 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3189 GET_MODE (op
) == VOIDmode
3190 ? DImode
: GET_MODE (op
), 4);
3191 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3192 GET_MODE (op
) == VOIDmode
3193 ? DImode
: GET_MODE (op
), 0);
3198 /* Split X into a base and a constant offset, storing them in *BASE
3199 and *OFFSET respectively. */
3202 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3205 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3207 *offset
+= INTVAL (XEXP (x
, 1));
3213 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3214 instruction. STORE_P says whether the move is a load or store.
3216 If the instruction uses post-increment or pre-decrement addressing,
3217 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3218 adjustment. This adjustment will be made by the first element of
3219 PARALLEL, with the loads or stores starting at element 1. If the
3220 instruction does not use post-increment or pre-decrement addressing,
3221 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3222 start at element 0. */
3225 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3226 HOST_WIDE_INT automod_offset
, bool store_p
)
3228 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3229 HOST_WIDE_INT offset
, mem_offset
;
3231 enum reg_class rclass
;
3233 len
= XVECLEN (pattern
, 0);
3234 first
= (automod_base
!= NULL
);
3238 /* Stores must be pre-decrement and loads must be post-increment. */
3239 if (store_p
!= (automod_offset
< 0))
3242 /* Work out the base and offset for lowest memory location. */
3243 base
= automod_base
;
3244 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3248 /* Allow any valid base and offset in the first access. */
3255 for (i
= first
; i
< len
; i
++)
3257 /* We need a plain SET. */
3258 set
= XVECEXP (pattern
, 0, i
);
3259 if (GET_CODE (set
) != SET
)
3262 /* Check that we have a memory location... */
3263 mem
= XEXP (set
, !store_p
);
3264 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3267 /* ...with the right address. */
3270 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3271 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3272 There are no mode restrictions for 680x0 besides the
3273 automodification rules enforced above. */
3275 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3280 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3281 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3285 /* Check that we have a register of the required mode and class. */
3286 reg
= XEXP (set
, store_p
);
3288 || !HARD_REGISTER_P (reg
)
3289 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3294 /* The register must belong to RCLASS and have a higher number
3295 than the register in the previous SET. */
3296 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3297 || REGNO (last_reg
) >= REGNO (reg
))
3302 /* Work out which register class we need. */
3303 if (INT_REGNO_P (REGNO (reg
)))
3304 rclass
= GENERAL_REGS
;
3305 else if (FP_REGNO_P (REGNO (reg
)))
3312 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3315 /* If we have an automodification, check whether the final offset is OK. */
3316 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3319 /* Reject unprofitable cases. */
3320 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3326 /* Return the assembly code template for a movem or fmovem instruction
3327 whose pattern is given by PATTERN. Store the template's operands
3330 If the instruction uses post-increment or pre-decrement addressing,
3331 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3332 is true if this is a store instruction. */
3335 m68k_output_movem (rtx
*operands
, rtx pattern
,
3336 HOST_WIDE_INT automod_offset
, bool store_p
)
3341 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3343 first
= (automod_offset
!= 0);
3344 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3346 /* When using movem with pre-decrement addressing, register X + D0_REG
3347 is controlled by bit 15 - X. For all other addressing modes,
3348 register X + D0_REG is controlled by bit X. Confusingly, the
3349 register mask for fmovem is in the opposite order to that for
3353 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3354 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3355 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3356 if (automod_offset
< 0)
3358 if (FP_REGNO_P (regno
))
3359 mask
|= 1 << (regno
- FP0_REG
);
3361 mask
|= 1 << (15 - (regno
- D0_REG
));
3365 if (FP_REGNO_P (regno
))
3366 mask
|= 1 << (7 - (regno
- FP0_REG
));
3368 mask
|= 1 << (regno
- D0_REG
);
3373 if (automod_offset
== 0)
3374 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3375 else if (automod_offset
< 0)
3376 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3378 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3379 operands
[1] = GEN_INT (mask
);
3380 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3383 return "fmovem %1,%a0";
3385 return "fmovem %a0,%1";
3390 return "movem%.l %1,%a0";
3392 return "movem%.l %a0,%1";
3396 /* Return a REG that occurs in ADDR with coefficient 1.
3397 ADDR can be effectively incremented by incrementing REG. */
3400 find_addr_reg (rtx addr
)
3402 while (GET_CODE (addr
) == PLUS
)
3404 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3405 addr
= XEXP (addr
, 0);
3406 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3407 addr
= XEXP (addr
, 1);
3408 else if (CONSTANT_P (XEXP (addr
, 0)))
3409 addr
= XEXP (addr
, 1);
3410 else if (CONSTANT_P (XEXP (addr
, 1)))
3411 addr
= XEXP (addr
, 0);
3415 gcc_assert (GET_CODE (addr
) == REG
);
3419 /* Output assembler code to perform a 32-bit 3-operand add. */
3422 output_addsi3 (rtx
*operands
)
3424 if (! operands_match_p (operands
[0], operands
[1]))
3426 if (!ADDRESS_REG_P (operands
[1]))
3428 rtx tmp
= operands
[1];
3430 operands
[1] = operands
[2];
3434 /* These insns can result from reloads to access
3435 stack slots over 64k from the frame pointer. */
3436 if (GET_CODE (operands
[2]) == CONST_INT
3437 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3438 return "move%.l %2,%0\n\tadd%.l %1,%0";
3439 if (GET_CODE (operands
[2]) == REG
)
3440 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3441 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3443 if (GET_CODE (operands
[2]) == CONST_INT
)
3445 if (INTVAL (operands
[2]) > 0
3446 && INTVAL (operands
[2]) <= 8)
3447 return "addq%.l %2,%0";
3448 if (INTVAL (operands
[2]) < 0
3449 && INTVAL (operands
[2]) >= -8)
3451 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3452 return "subq%.l %2,%0";
3454 /* On the CPU32 it is faster to use two addql instructions to
3455 add a small integer (8 < N <= 16) to a register.
3456 Likewise for subql. */
3457 if (TUNE_CPU32
&& REG_P (operands
[0]))
3459 if (INTVAL (operands
[2]) > 8
3460 && INTVAL (operands
[2]) <= 16)
3462 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3463 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3465 if (INTVAL (operands
[2]) < -8
3466 && INTVAL (operands
[2]) >= -16)
3468 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3469 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3472 if (ADDRESS_REG_P (operands
[0])
3473 && INTVAL (operands
[2]) >= -0x8000
3474 && INTVAL (operands
[2]) < 0x8000)
3477 return "add%.w %2,%0";
3479 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3482 return "add%.l %2,%0";
3485 /* Store in cc_status the expressions that the condition codes will
3486 describe after execution of an instruction whose pattern is EXP.
3487 Do not alter them if the instruction would not alter the cc's. */
3489 /* On the 68000, all the insns to store in an address register fail to
3490 set the cc's. However, in some cases these instructions can make it
3491 possibly invalid to use the saved cc's. In those cases we clear out
3492 some or all of the saved cc's so they won't be used. */
3495 notice_update_cc (rtx exp
, rtx insn
)
3497 if (GET_CODE (exp
) == SET
)
3499 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3501 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3503 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3504 cc_status
.value1
= 0;
3505 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3506 cc_status
.value2
= 0;
3508 /* fmoves to memory or data registers do not set the condition
3509 codes. Normal moves _do_ set the condition codes, but not in
3510 a way that is appropriate for comparison with 0, because -0.0
3511 would be treated as a negative nonzero number. Note that it
3512 isn't appropriate to conditionalize this restriction on
3513 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3514 we care about the difference between -0.0 and +0.0. */
3515 else if (!FP_REG_P (SET_DEST (exp
))
3516 && SET_DEST (exp
) != cc0_rtx
3517 && (FP_REG_P (SET_SRC (exp
))
3518 || GET_CODE (SET_SRC (exp
)) == FIX
3519 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3521 /* A pair of move insns doesn't produce a useful overall cc. */
3522 else if (!FP_REG_P (SET_DEST (exp
))
3523 && !FP_REG_P (SET_SRC (exp
))
3524 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3525 && (GET_CODE (SET_SRC (exp
)) == REG
3526 || GET_CODE (SET_SRC (exp
)) == MEM
3527 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3529 else if (SET_DEST (exp
) != pc_rtx
)
3531 cc_status
.flags
= 0;
3532 cc_status
.value1
= SET_DEST (exp
);
3533 cc_status
.value2
= SET_SRC (exp
);
3536 else if (GET_CODE (exp
) == PARALLEL
3537 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3539 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3540 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3542 if (ADDRESS_REG_P (dest
))
3544 else if (dest
!= pc_rtx
)
3546 cc_status
.flags
= 0;
3547 cc_status
.value1
= dest
;
3548 cc_status
.value2
= src
;
3553 if (cc_status
.value2
!= 0
3554 && ADDRESS_REG_P (cc_status
.value2
)
3555 && GET_MODE (cc_status
.value2
) == QImode
)
3557 if (cc_status
.value2
!= 0)
3558 switch (GET_CODE (cc_status
.value2
))
3560 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3561 case ROTATE
: case ROTATERT
:
3562 /* These instructions always clear the overflow bit, and set
3563 the carry to the bit shifted out. */
3564 /* ??? We don't currently have a way to signal carry not valid,
3565 nor do we check for it in the branch insns. */
3569 case PLUS
: case MINUS
: case MULT
:
3570 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3571 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3572 cc_status
.flags
|= CC_NO_OVERFLOW
;
3575 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3576 ends with a move insn moving r2 in r2's mode.
3577 Thus, the cc's are set for r2.
3578 This can set N bit spuriously. */
3579 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3584 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3586 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3587 cc_status
.value2
= 0;
3588 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3589 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3590 cc_status
.flags
= CC_IN_68881
;
3591 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
3592 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
3594 cc_status
.flags
= CC_IN_68881
;
3595 if (!FP_REG_P (XEXP (cc_status
.value2
, 0)))
3596 cc_status
.flags
|= CC_REVERSED
;
3601 output_move_const_double (rtx
*operands
)
3603 int code
= standard_68881_constant_p (operands
[1]);
3607 static char buf
[40];
3609 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3612 return "fmove%.d %1,%0";
3616 output_move_const_single (rtx
*operands
)
3618 int code
= standard_68881_constant_p (operands
[1]);
3622 static char buf
[40];
3624 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3627 return "fmove%.s %f1,%0";
3630 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3631 from the "fmovecr" instruction.
3632 The value, anded with 0xff, gives the code to use in fmovecr
3633 to get the desired constant. */
3635 /* This code has been fixed for cross-compilation. */
3637 static int inited_68881_table
= 0;
3639 static const char *const strings_68881
[7] = {
3649 static const int codes_68881
[7] = {
3659 REAL_VALUE_TYPE values_68881
[7];
3661 /* Set up values_68881 array by converting the decimal values
3662 strings_68881 to binary. */
3665 init_68881_table (void)
3669 enum machine_mode mode
;
3672 for (i
= 0; i
< 7; i
++)
3676 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3677 values_68881
[i
] = r
;
3679 inited_68881_table
= 1;
3683 standard_68881_constant_p (rtx x
)
3688 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3689 used at all on those chips. */
3693 if (! inited_68881_table
)
3694 init_68881_table ();
3696 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3698 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3700 for (i
= 0; i
< 6; i
++)
3702 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3703 return (codes_68881
[i
]);
3706 if (GET_MODE (x
) == SFmode
)
3709 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3710 return (codes_68881
[6]);
3712 /* larger powers of ten in the constants ram are not used
3713 because they are not equal to a `double' C constant. */
3717 /* If X is a floating-point constant, return the logarithm of X base 2,
3718 or 0 if X is not a power of 2. */
3721 floating_exact_log2 (rtx x
)
3723 REAL_VALUE_TYPE r
, r1
;
3726 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3728 if (REAL_VALUES_LESS (r
, dconst1
))
3731 exp
= real_exponent (&r
);
3732 real_2expN (&r1
, exp
, DFmode
);
3733 if (REAL_VALUES_EQUAL (r1
, r
))
3739 /* A C compound statement to output to stdio stream STREAM the
3740 assembler syntax for an instruction operand X. X is an RTL
3743 CODE is a value that can be used to specify one of several ways
3744 of printing the operand. It is used when identical operands
3745 must be printed differently depending on the context. CODE
3746 comes from the `%' specification that was used to request
3747 printing of the operand. If the specification was just `%DIGIT'
3748 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3749 is the ASCII code for LTR.
3751 If X is a register, this macro should print the register's name.
3752 The names can be found in an array `reg_names' whose type is
3753 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3755 When the machine description has a specification `%PUNCT' (a `%'
3756 followed by a punctuation character), this macro is called with
3757 a null pointer for X and the punctuation character for CODE.
3759 The m68k specific codes are:
3761 '.' for dot needed in Motorola-style opcode names.
3762 '-' for an operand pushing on the stack:
3763 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3764 '+' for an operand pushing on the stack:
3765 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3766 '@' for a reference to the top word on the stack:
3767 sp@, (sp) or (%sp) depending on the style of syntax.
3768 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3769 but & in SGS syntax).
3770 '!' for the cc register (used in an `and to cc' insn).
3771 '$' for the letter `s' in an op code, but only on the 68040.
3772 '&' for the letter `d' in an op code, but only on the 68040.
3773 '/' for register prefix needed by longlong.h.
3774 '?' for m68k_library_id_string
3776 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3777 'd' to force memory addressing to be absolute, not relative.
3778 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3779 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3780 or print pair of registers as rx:ry.
3781 'p' print an address with @PLTPC attached, but only if the operand
3782 is not locally-bound. */
3785 print_operand (FILE *file
, rtx op
, int letter
)
3790 fprintf (file
, ".");
3792 else if (letter
== '#')
3793 asm_fprintf (file
, "%I");
3794 else if (letter
== '-')
3795 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3796 else if (letter
== '+')
3797 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3798 else if (letter
== '@')
3799 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3800 else if (letter
== '!')
3801 asm_fprintf (file
, "%Rfpcr");
3802 else if (letter
== '$')
3805 fprintf (file
, "s");
3807 else if (letter
== '&')
3810 fprintf (file
, "d");
3812 else if (letter
== '/')
3813 asm_fprintf (file
, "%R");
3814 else if (letter
== '?')
3815 asm_fprintf (file
, m68k_library_id_string
);
3816 else if (letter
== 'p')
3818 output_addr_const (file
, op
);
3819 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3820 fprintf (file
, "@PLTPC");
3822 else if (GET_CODE (op
) == REG
)
3825 /* Print out the second register name of a register pair.
3826 I.e., R (6) => 7. */
3827 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3829 fputs (M68K_REGNAME(REGNO (op
)), file
);
3831 else if (GET_CODE (op
) == MEM
)
3833 output_address (XEXP (op
, 0));
3834 if (letter
== 'd' && ! TARGET_68020
3835 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3836 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3837 && INTVAL (XEXP (op
, 0)) < 0x8000
3838 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3839 fprintf (file
, MOTOROLA
? ".l" : ":l");
3841 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3844 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3845 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3847 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3850 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3851 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3853 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3856 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3857 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3861 /* Use `print_operand_address' instead of `output_addr_const'
3862 to ensure that we print relevant PIC stuff. */
3863 asm_fprintf (file
, "%I");
3865 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3866 print_operand_address (file
, op
);
3868 output_addr_const (file
, op
);
3873 /* A C compound statement to output to stdio stream STREAM the
3874 assembler syntax for an instruction operand that is a memory
3875 reference whose address is ADDR. ADDR is an RTL expression.
3877 Note that this contains a kludge that knows that the only reason
3878 we have an address (plus (label_ref...) (reg...)) when not generating
3879 PIC code is in the insn before a tablejump, and we know that m68k.md
3880 generates a label LInnn: on such an insn.
3882 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3883 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3885 This routine is responsible for distinguishing between -fpic and -fPIC
3886 style relocations in an address. When generating -fpic code the
3887 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3888 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3891 print_operand_address (FILE *file
, rtx addr
)
3893 struct m68k_address address
;
3895 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3898 if (address
.code
== PRE_DEC
)
3899 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3900 M68K_REGNAME (REGNO (address
.base
)));
3901 else if (address
.code
== POST_INC
)
3902 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3903 M68K_REGNAME (REGNO (address
.base
)));
3904 else if (!address
.base
&& !address
.index
)
3906 /* A constant address. */
3907 gcc_assert (address
.offset
== addr
);
3908 if (GET_CODE (addr
) == CONST_INT
)
3910 /* (xxx).w or (xxx).l. */
3911 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3912 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3914 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3916 else if (TARGET_PCREL
)
3918 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3920 output_addr_const (file
, addr
);
3921 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3925 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3926 name ends in `.<letter>', as the last 2 characters can be
3927 mistaken as a size suffix. Put the name in parentheses. */
3928 if (GET_CODE (addr
) == SYMBOL_REF
3929 && strlen (XSTR (addr
, 0)) > 2
3930 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3933 output_addr_const (file
, addr
);
3937 output_addr_const (file
, addr
);
3944 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3945 label being accessed, otherwise it is -1. */
3946 labelno
= (address
.offset
3948 && GET_CODE (address
.offset
) == LABEL_REF
3949 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3953 /* Print the "offset(base" component. */
3955 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
3960 output_addr_const (file
, address
.offset
);
3961 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3963 fprintf (file
, "@GOT");
3964 if (flag_pic
== 1 && TARGET_68020
)
3965 fprintf (file
, ".w");
3970 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3972 /* Print the ",index" component, if any. */
3977 fprintf (file
, "%s.%c",
3978 M68K_REGNAME (REGNO (address
.index
)),
3979 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3980 if (address
.scale
!= 1)
3981 fprintf (file
, "*%d", address
.scale
);
3985 else /* !MOTOROLA */
3987 if (!address
.offset
&& !address
.index
)
3988 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3991 /* Print the "base@(offset" component. */
3993 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
3997 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3998 fprintf (file
, "@(");
4001 output_addr_const (file
, address
.offset
);
4002 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
4006 fprintf (file
, ":w"); break;
4008 fprintf (file
, ":l"); break;
4014 /* Print the ",index" component, if any. */
4017 fprintf (file
, ",%s:%c",
4018 M68K_REGNAME (REGNO (address
.index
)),
4019 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4020 if (address
.scale
!= 1)
4021 fprintf (file
, ":%d", address
.scale
);
4029 /* Check for cases where a clr insns can be omitted from code using
4030 strict_low_part sets. For example, the second clrl here is not needed:
4031 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4033 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4034 insn we are checking for redundancy. TARGET is the register set by the
4038 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4043 while ((p
= PREV_INSN (p
)))
4045 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4051 /* If it isn't an insn, then give up. */
4055 if (reg_set_p (target
, p
))
4057 rtx set
= single_set (p
);
4060 /* If it isn't an easy to recognize insn, then give up. */
4064 dest
= SET_DEST (set
);
4066 /* If this sets the entire target register to zero, then our
4067 first_insn is redundant. */
4068 if (rtx_equal_p (dest
, target
)
4069 && SET_SRC (set
) == const0_rtx
)
4071 else if (GET_CODE (dest
) == STRICT_LOW_PART
4072 && GET_CODE (XEXP (dest
, 0)) == REG
4073 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4074 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4075 <= GET_MODE_SIZE (mode
)))
4076 /* This is a strict low part set which modifies less than
4077 we are using, so it is safe. */
4087 /* Operand predicates for implementing asymmetric pc-relative addressing
4088 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4089 when used as a source operand, but not as a destination operand.
4091 We model this by restricting the meaning of the basic predicates
4092 (general_operand, memory_operand, etc) to forbid the use of this
4093 addressing mode, and then define the following predicates that permit
4094 this addressing mode. These predicates can then be used for the
4095 source operands of the appropriate instructions.
4097 n.b. While it is theoretically possible to change all machine patterns
4098 to use this addressing more where permitted by the architecture,
4099 it has only been implemented for "common" cases: SImode, HImode, and
4100 QImode operands, and only for the principle operations that would
4101 require this addressing mode: data movement and simple integer operations.
4103 In parallel with these new predicates, two new constraint letters
4104 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4105 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4106 In the pcrel case 's' is only valid in combination with 'a' registers.
4107 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4108 of how these constraints are used.
4110 The use of these predicates is strictly optional, though patterns that
4111 don't will cause an extra reload register to be allocated where one
4114 lea (abc:w,%pc),%a0 ; need to reload address
4115 moveq &1,%d1 ; since write to pc-relative space
4116 movel %d1,%a0@ ; is not allowed
4118 lea (abc:w,%pc),%a1 ; no need to reload address here
4119 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4121 For more info, consult tiemann@cygnus.com.
4124 All of the ugliness with predicates and constraints is due to the
4125 simple fact that the m68k does not allow a pc-relative addressing
4126 mode as a destination. gcc does not distinguish between source and
4127 destination addresses. Hence, if we claim that pc-relative address
4128 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4129 end up with invalid code. To get around this problem, we left
4130 pc-relative modes as invalid addresses, and then added special
4131 predicates and constraints to accept them.
4133 A cleaner way to handle this is to modify gcc to distinguish
4134 between source and destination addresses. We can then say that
4135 pc-relative is a valid source address but not a valid destination
4136 address, and hopefully avoid a lot of the predicate and constraint
4137 hackery. Unfortunately, this would be a pretty big change. It would
4138 be a useful change for a number of ports, but there aren't any current
4139 plans to undertake this.
4141 ***************************************************************************/
4145 output_andsi3 (rtx
*operands
)
4148 if (GET_CODE (operands
[2]) == CONST_INT
4149 && (INTVAL (operands
[2]) | 0xffff) == -1
4150 && (DATA_REG_P (operands
[0])
4151 || offsettable_memref_p (operands
[0]))
4152 && !TARGET_COLDFIRE
)
4154 if (GET_CODE (operands
[0]) != REG
)
4155 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4156 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4157 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4159 if (operands
[2] == const0_rtx
)
4161 return "and%.w %2,%0";
4163 if (GET_CODE (operands
[2]) == CONST_INT
4164 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
4165 && (DATA_REG_P (operands
[0])
4166 || offsettable_memref_p (operands
[0])))
4168 if (DATA_REG_P (operands
[0]))
4169 operands
[1] = GEN_INT (logval
);
4172 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4173 operands
[1] = GEN_INT (logval
% 8);
4175 /* This does not set condition codes in a standard way. */
4177 return "bclr %1,%0";
4179 return "and%.l %2,%0";
4183 output_iorsi3 (rtx
*operands
)
4185 register int logval
;
4186 if (GET_CODE (operands
[2]) == CONST_INT
4187 && INTVAL (operands
[2]) >> 16 == 0
4188 && (DATA_REG_P (operands
[0])
4189 || offsettable_memref_p (operands
[0]))
4190 && !TARGET_COLDFIRE
)
4192 if (GET_CODE (operands
[0]) != REG
)
4193 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4194 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4196 if (INTVAL (operands
[2]) == 0xffff)
4197 return "mov%.w %2,%0";
4198 return "or%.w %2,%0";
4200 if (GET_CODE (operands
[2]) == CONST_INT
4201 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4202 && (DATA_REG_P (operands
[0])
4203 || offsettable_memref_p (operands
[0])))
4205 if (DATA_REG_P (operands
[0]))
4206 operands
[1] = GEN_INT (logval
);
4209 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4210 operands
[1] = GEN_INT (logval
% 8);
4213 return "bset %1,%0";
4215 return "or%.l %2,%0";
4219 output_xorsi3 (rtx
*operands
)
4221 register int logval
;
4222 if (GET_CODE (operands
[2]) == CONST_INT
4223 && INTVAL (operands
[2]) >> 16 == 0
4224 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4225 && !TARGET_COLDFIRE
)
4227 if (! DATA_REG_P (operands
[0]))
4228 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4229 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4231 if (INTVAL (operands
[2]) == 0xffff)
4233 return "eor%.w %2,%0";
4235 if (GET_CODE (operands
[2]) == CONST_INT
4236 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4237 && (DATA_REG_P (operands
[0])
4238 || offsettable_memref_p (operands
[0])))
4240 if (DATA_REG_P (operands
[0]))
4241 operands
[1] = GEN_INT (logval
);
4244 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4245 operands
[1] = GEN_INT (logval
% 8);
4248 return "bchg %1,%0";
4250 return "eor%.l %2,%0";
4253 /* Return the instruction that should be used for a call to address X,
4254 which is known to be in operand 0. */
4259 if (symbolic_operand (x
, VOIDmode
))
4260 return m68k_symbolic_call
;
4265 /* Likewise sibling calls. */
4268 output_sibcall (rtx x
)
4270 if (symbolic_operand (x
, VOIDmode
))
4271 return m68k_symbolic_jump
;
4276 #ifdef M68K_TARGET_COFF
4278 /* Output assembly to switch to section NAME with attribute FLAGS. */
4281 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
4282 tree decl ATTRIBUTE_UNUSED
)
4286 if (flags
& SECTION_WRITE
)
4291 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4294 #endif /* M68K_TARGET_COFF */
4297 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4298 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4301 rtx this_slot
, offset
, addr
, mem
, insn
;
4303 /* Pretend to be a post-reload pass while generating rtl. */
4304 reload_completed
= 1;
4306 /* The "this" pointer is stored at 4(%sp). */
4307 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
4309 /* Add DELTA to THIS. */
4312 /* Make the offset a legitimate operand for memory addition. */
4313 offset
= GEN_INT (delta
);
4314 if ((delta
< -8 || delta
> 8)
4315 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
4317 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
4318 offset
= gen_rtx_REG (Pmode
, D0_REG
);
4320 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
4321 copy_rtx (this_slot
), offset
));
4324 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4325 if (vcall_offset
!= 0)
4327 /* Set the static chain register to *THIS. */
4328 emit_move_insn (static_chain_rtx
, this_slot
);
4329 emit_move_insn (static_chain_rtx
, gen_rtx_MEM (Pmode
, static_chain_rtx
));
4331 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4332 addr
= plus_constant (static_chain_rtx
, vcall_offset
);
4333 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
4335 emit_insn (gen_rtx_SET (VOIDmode
, static_chain_rtx
, addr
));
4336 addr
= static_chain_rtx
;
4339 /* Load the offset into %d0 and add it to THIS. */
4340 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
4341 gen_rtx_MEM (Pmode
, addr
));
4342 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
4343 copy_rtx (this_slot
),
4344 gen_rtx_REG (Pmode
, D0_REG
)));
4347 /* Jump to the target function. Use a sibcall if direct jumps are
4348 allowed, otherwise load the address into a register first. */
4349 mem
= DECL_RTL (function
);
4350 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
4352 gcc_assert (flag_pic
);
4354 if (!TARGET_SEP_DATA
)
4356 /* Use the static chain register as a temporary (call-clobbered)
4357 GOT pointer for this function. We can use the static chain
4358 register because it isn't live on entry to the thunk. */
4359 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
4360 emit_insn (gen_load_got (pic_offset_table_rtx
));
4362 legitimize_pic_address (XEXP (mem
, 0), Pmode
, static_chain_rtx
);
4363 mem
= replace_equiv_address (mem
, static_chain_rtx
);
4365 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
4366 SIBLING_CALL_P (insn
) = 1;
4368 /* Run just enough of rest_of_compilation. */
4369 insn
= get_insns ();
4370 split_all_insns_noflow ();
4371 final_start_function (insn
, file
, 1);
4372 final (insn
, file
, 1);
4373 final_end_function ();
4375 /* Clean up the vars set above. */
4376 reload_completed
= 0;
4378 /* Restore the original PIC register. */
4380 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
4381 free_after_compilation (cfun
);
4384 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4387 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4388 int incoming ATTRIBUTE_UNUSED
)
4390 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4393 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4395 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4396 unsigned int new_reg
)
4399 /* Interrupt functions can only use registers that have already been
4400 saved by the prologue, even if they would normally be
4403 if ((m68k_get_function_kind (current_function_decl
)
4404 == m68k_fk_interrupt_handler
)
4405 && !df_regs_ever_live_p (new_reg
))
4411 /* Value is true if hard register REGNO can hold a value of machine-mode
4412 MODE. On the 68000, we let the cpu registers can hold any mode, but
4413 restrict the 68881 registers to floating-point modes. */
4416 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4418 if (DATA_REGNO_P (regno
))
4420 /* Data Registers, can hold aggregate if fits in. */
4421 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4424 else if (ADDRESS_REGNO_P (regno
))
4426 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4429 else if (FP_REGNO_P (regno
))
4431 /* FPU registers, hold float or complex float of long double or
4433 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4434 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4435 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4441 /* Implement SECONDARY_RELOAD_CLASS. */
4444 m68k_secondary_reload_class (enum reg_class rclass
,
4445 enum machine_mode mode
, rtx x
)
4449 regno
= true_regnum (x
);
4451 /* If one operand of a movqi is an address register, the other
4452 operand must be a general register or constant. Other types
4453 of operand must be reloaded through a data register. */
4454 if (GET_MODE_SIZE (mode
) == 1
4455 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
4456 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
4459 /* PC-relative addresses must be loaded into an address register first. */
4461 && !reg_class_subset_p (rclass
, ADDR_REGS
)
4462 && symbolic_operand (x
, VOIDmode
))
4468 /* Implement PREFERRED_RELOAD_CLASS. */
4471 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
4473 enum reg_class secondary_class
;
4475 /* If RCLASS might need a secondary reload, try restricting it to
4476 a class that doesn't. */
4477 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
4478 if (secondary_class
!= NO_REGS
4479 && reg_class_subset_p (secondary_class
, rclass
))
4480 return secondary_class
;
4482 /* Prefer to use moveq for in-range constants. */
4483 if (GET_CODE (x
) == CONST_INT
4484 && reg_class_subset_p (DATA_REGS
, rclass
)
4485 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
4488 /* ??? Do we really need this now? */
4489 if (GET_CODE (x
) == CONST_DOUBLE
4490 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4492 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
4501 /* Return floating point values in a 68881 register. This makes 68881 code
4502 a little bit faster. It also makes -msoft-float code incompatible with
4503 hard-float code, so people have to be careful not to mix the two.
4504 For ColdFire it was decided the ABI incompatibility is undesirable.
4505 If there is need for a hard-float ABI it is probably worth doing it
4506 properly and also passing function arguments in FP registers. */
4508 m68k_libcall_value (enum machine_mode mode
)
4515 return gen_rtx_REG (mode
, FP0_REG
);
4520 return gen_rtx_REG (mode
, D0_REG
);
4524 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
4526 enum machine_mode mode
;
4528 mode
= TYPE_MODE (valtype
);
4534 return gen_rtx_REG (mode
, FP0_REG
);
4540 /* If the function returns a pointer, push that into %a0. */
4541 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4542 /* For compatibility with the large body of existing code which
4543 does not always properly declare external functions returning
4544 pointer types, the m68k/SVR4 convention is to copy the value
4545 returned for pointer functions from a0 to d0 in the function
4546 epilogue, so that callers that have neglected to properly
4547 declare the callee can still find the correct return value in
4549 return gen_rtx_PARALLEL
4552 gen_rtx_EXPR_LIST (VOIDmode
,
4553 gen_rtx_REG (mode
, A0_REG
),
4555 gen_rtx_EXPR_LIST (VOIDmode
,
4556 gen_rtx_REG (mode
, D0_REG
),
4558 else if (POINTER_TYPE_P (valtype
))
4559 return gen_rtx_REG (mode
, A0_REG
);
4561 return gen_rtx_REG (mode
, D0_REG
);
4564 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4565 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
4567 m68k_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
4569 enum machine_mode mode
= TYPE_MODE (type
);
4571 if (mode
== BLKmode
)
4574 /* If TYPE's known alignment is less than the alignment of MODE that
4575 would contain the structure, then return in memory. We need to
4576 do so to maintain the compatibility between code compiled with
4577 -mstrict-align and that compiled with -mno-strict-align. */
4578 if (AGGREGATE_TYPE_P (type
)
4579 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
4586 /* CPU to schedule the program for. */
4587 enum attr_cpu m68k_sched_cpu
;
4589 /* MAC to schedule the program for. */
4590 enum attr_mac m68k_sched_mac
;
4598 /* Integer register. */
4604 /* Implicit mem reference (e.g. stack). */
4607 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
4610 /* Memory with offset but without indexing. EA mode 5. */
4613 /* Memory with indexing. EA mode 6. */
4616 /* Memory referenced by absolute address. EA mode 7. */
4619 /* Immediate operand that doesn't require extension word. */
4622 /* Immediate 16 bit operand. */
4625 /* Immediate 32 bit operand. */
4629 /* Return type of memory ADDR_RTX refers to. */
4630 static enum attr_op_type
4631 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
4633 struct m68k_address address
;
4635 if (symbolic_operand (addr_rtx
, VOIDmode
))
4636 return OP_TYPE_MEM7
;
4638 if (!m68k_decompose_address (mode
, addr_rtx
,
4639 reload_completed
, &address
))
4641 gcc_assert (!reload_completed
);
4642 /* Reload will likely fix the address to be in the register. */
4643 return OP_TYPE_MEM234
;
4646 if (address
.scale
!= 0)
4647 return OP_TYPE_MEM6
;
4649 if (address
.base
!= NULL_RTX
)
4651 if (address
.offset
== NULL_RTX
)
4652 return OP_TYPE_MEM234
;
4654 return OP_TYPE_MEM5
;
4657 gcc_assert (address
.offset
!= NULL_RTX
);
4659 return OP_TYPE_MEM7
;
4662 /* Return X or Y (depending on OPX_P) operand of INSN. */
4664 sched_get_operand (rtx insn
, bool opx_p
)
4668 if (recog_memoized (insn
) < 0)
4671 extract_constrain_insn_cached (insn
);
4674 i
= get_attr_opx (insn
);
4676 i
= get_attr_opy (insn
);
4678 if (i
>= recog_data
.n_operands
)
4681 return recog_data
.operand
[i
];
4684 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
4685 If ADDRESS_P is true, return type of memory location operand refers to. */
4686 static enum attr_op_type
4687 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
4691 op
= sched_get_operand (insn
, opx_p
);
4695 gcc_assert (!reload_completed
);
4700 return sched_address_type (QImode
, op
);
4702 if (memory_operand (op
, VOIDmode
))
4703 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
4705 if (register_operand (op
, VOIDmode
))
4707 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
4708 || (reload_completed
&& FP_REG_P (op
)))
4714 if (GET_CODE (op
) == CONST_INT
)
4720 /* Check for quick constants. */
4721 switch (get_attr_type (insn
))
4724 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
4725 return OP_TYPE_IMM_Q
;
4727 gcc_assert (!reload_completed
);
4731 if (USE_MOVQ (ival
))
4732 return OP_TYPE_IMM_Q
;
4734 gcc_assert (!reload_completed
);
4738 if (valid_mov3q_const (ival
))
4739 return OP_TYPE_IMM_Q
;
4741 gcc_assert (!reload_completed
);
4748 if (IN_RANGE (ival
, -0x8000, 0x7fff))
4749 return OP_TYPE_IMM_W
;
4751 return OP_TYPE_IMM_L
;
4754 if (GET_CODE (op
) == CONST_DOUBLE
)
4756 switch (GET_MODE (op
))
4759 return OP_TYPE_IMM_W
;
4763 return OP_TYPE_IMM_L
;
4770 if (symbolic_operand (op
, VOIDmode
)
4773 switch (GET_MODE (op
))
4776 return OP_TYPE_IMM_Q
;
4779 return OP_TYPE_IMM_W
;
4782 return OP_TYPE_IMM_L
;
4785 if (GET_CODE (op
) == SYMBOL_REF
)
4786 /* ??? Just a guess. Probably we can guess better using length
4787 attribute of the instructions. */
4788 return OP_TYPE_IMM_W
;
4790 return OP_TYPE_IMM_L
;
4794 gcc_assert (!reload_completed
);
4796 if (FLOAT_MODE_P (GET_MODE (op
)))
4802 /* Implement opx_type attribute.
4803 Return type of INSN's operand X.
4804 If ADDRESS_P is true, return type of memory location operand refers to. */
4806 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
4808 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
4814 return OPX_TYPE_FPN
;
4817 return OPX_TYPE_MEM1
;
4819 case OP_TYPE_MEM234
:
4820 return OPX_TYPE_MEM234
;
4823 return OPX_TYPE_MEM5
;
4826 return OPX_TYPE_MEM6
;
4829 return OPX_TYPE_MEM7
;
4832 return OPX_TYPE_IMM_Q
;
4835 return OPX_TYPE_IMM_W
;
4838 return OPX_TYPE_IMM_L
;
4846 /* Implement opy_type attribute.
4847 Return type of INSN's operand Y.
4848 If ADDRESS_P is true, return type of memory location operand refers to. */
4850 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
4852 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
4858 return OPY_TYPE_FPN
;
4861 return OPY_TYPE_MEM1
;
4863 case OP_TYPE_MEM234
:
4864 return OPY_TYPE_MEM234
;
4867 return OPY_TYPE_MEM5
;
4870 return OPY_TYPE_MEM6
;
4873 return OPY_TYPE_MEM7
;
4876 return OPY_TYPE_IMM_Q
;
4879 return OPY_TYPE_IMM_W
;
4882 return OPY_TYPE_IMM_L
;
4890 /* Return size of INSN as int. */
4892 sched_get_attr_size_int (rtx insn
)
4896 switch (get_attr_type (insn
))
4899 /* There should be no references to m68k_sched_attr_size for 'ignore'
4913 switch (get_attr_opx_type (insn
))
4919 case OPX_TYPE_MEM234
:
4920 case OPY_TYPE_IMM_Q
:
4925 /* Here we assume that most absolute references are short. */
4927 case OPY_TYPE_IMM_W
:
4931 case OPY_TYPE_IMM_L
:
4939 switch (get_attr_opy_type (insn
))
4945 case OPY_TYPE_MEM234
:
4946 case OPY_TYPE_IMM_Q
:
4951 /* Here we assume that most absolute references are short. */
4953 case OPY_TYPE_IMM_W
:
4957 case OPY_TYPE_IMM_L
:
4967 gcc_assert (!reload_completed
);
4975 /* Return size of INSN as attribute enum value. */
4977 m68k_sched_attr_size (rtx insn
)
4979 switch (sched_get_attr_size_int (insn
))
4996 /* Return operand X or Y (depending on OPX_P) of INSN,
4997 if it is a MEM, or NULL overwise. */
4998 static enum attr_op_type
4999 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5003 switch (get_attr_opx_type (insn
))
5008 case OPX_TYPE_IMM_Q
:
5009 case OPX_TYPE_IMM_W
:
5010 case OPX_TYPE_IMM_L
:
5014 case OPX_TYPE_MEM234
:
5017 return OP_TYPE_MEM1
;
5020 return OP_TYPE_MEM6
;
5029 switch (get_attr_opy_type (insn
))
5034 case OPY_TYPE_IMM_Q
:
5035 case OPY_TYPE_IMM_W
:
5036 case OPY_TYPE_IMM_L
:
5040 case OPY_TYPE_MEM234
:
5043 return OP_TYPE_MEM1
;
5046 return OP_TYPE_MEM6
;
5055 /* Implement op_mem attribute. */
5057 m68k_sched_attr_op_mem (rtx insn
)
5059 enum attr_op_type opx
;
5060 enum attr_op_type opy
;
5062 opx
= sched_get_opxy_mem_type (insn
, true);
5063 opy
= sched_get_opxy_mem_type (insn
, false);
5065 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5068 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5070 switch (get_attr_opx_access (insn
))
5087 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5089 switch (get_attr_opx_access (insn
))
5106 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5109 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5111 switch (get_attr_opx_access (insn
))
5117 gcc_assert (!reload_completed
);
5122 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5124 switch (get_attr_opx_access (insn
))
5130 gcc_assert (!reload_completed
);
5135 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5138 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5140 switch (get_attr_opx_access (insn
))
5146 gcc_assert (!reload_completed
);
5151 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5152 gcc_assert (!reload_completed
);
5156 /* Jump instructions types. Indexed by INSN_UID.
5157 The same rtl insn can be expanded into different asm instructions
5158 depending on the cc0_status. To properly determine type of jump
5159 instructions we scan instruction stream and map jumps types to this
5161 static enum attr_type
*sched_branch_type
;
5163 /* Return the type of the jump insn. */
5165 m68k_sched_branch_type (rtx insn
)
5167 enum attr_type type
;
5169 type
= sched_branch_type
[INSN_UID (insn
)];
5171 gcc_assert (type
!= 0);
5176 /* Data for ColdFire V4 index bypass.
5177 Producer modifies register that is used as index in consumer with
5181 /* Producer instruction. */
5184 /* Consumer instruction. */
5187 /* Scale of indexed memory access within consumer.
5188 Or zero if bypass should not be effective at the moment. */
5190 } sched_cfv4_bypass_data
;
5192 /* An empty state that is used in m68k_sched_adjust_cost. */
5193 static state_t sched_adjust_cost_state
;
5195 /* Implement adjust_cost scheduler hook.
5196 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5198 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5203 if (recog_memoized (def_insn
) < 0
5204 || recog_memoized (insn
) < 0)
5207 if (sched_cfv4_bypass_data
.scale
== 1)
5208 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5210 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5211 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5212 that the data in sched_cfv4_bypass_data is up to date. */
5213 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5214 && sched_cfv4_bypass_data
.con
== insn
);
5219 sched_cfv4_bypass_data
.pro
= NULL
;
5220 sched_cfv4_bypass_data
.con
= NULL
;
5221 sched_cfv4_bypass_data
.scale
= 0;
5224 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5225 && sched_cfv4_bypass_data
.con
== NULL
5226 && sched_cfv4_bypass_data
.scale
== 0);
5228 /* Don't try to issue INSN earlier than DFA permits.
5229 This is especially useful for instructions that write to memory,
5230 as their true dependence (default) latency is better to be set to 0
5231 to workaround alias analysis limitations.
5232 This is, in fact, a machine independent tweak, so, probably,
5233 it should be moved to haifa-sched.c: insn_cost (). */
5234 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5241 /* Return maximal number of insns that can be scheduled on a single cycle. */
5243 m68k_sched_issue_rate (void)
5245 switch (m68k_sched_cpu
)
5261 /* Maximal length of instruction for current CPU.
5262 E.g. it is 3 for any ColdFire core. */
5263 static int max_insn_size
;
5265 /* Data to model instruction buffer of CPU. */
5268 /* True if instruction buffer model is modeled for current CPU. */
5271 /* Size of the instruction buffer in words. */
5274 /* Number of filled words in the instruction buffer. */
5277 /* Additional information about instruction buffer for CPUs that have
5278 a buffer of instruction records, rather then a plain buffer
5279 of instruction words. */
5280 struct _sched_ib_records
5282 /* Size of buffer in records. */
5285 /* Array to hold data on adjustements made to the size of the buffer. */
5288 /* Index of the above array. */
5292 /* An insn that reserves (marks empty) one word in the instruction buffer. */
5296 static struct _sched_ib sched_ib
;
5298 /* ID of memory unit. */
5299 static int sched_mem_unit_code
;
5301 /* Implementation of the targetm.sched.variable_issue () hook.
5302 It is called after INSN was issued. It returns the number of insns
5303 that can possibly get scheduled on the current cycle.
5304 It is used here to determine the effect of INSN on the instruction
5307 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
5308 int sched_verbose ATTRIBUTE_UNUSED
,
5309 rtx insn
, int can_issue_more
)
5313 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
5315 switch (m68k_sched_cpu
)
5319 insn_size
= sched_get_attr_size_int (insn
);
5323 insn_size
= sched_get_attr_size_int (insn
);
5325 /* ColdFire V3 and V4 cores have instruction buffers that can
5326 accumulate up to 8 instructions regardless of instructions'
5327 sizes. So we should take care not to "prefetch" 24 one-word
5328 or 12 two-words instructions.
5329 To model this behavior we temporarily decrease size of the
5330 buffer by (max_insn_size - insn_size) for next 7 instructions. */
5334 adjust
= max_insn_size
- insn_size
;
5335 sched_ib
.size
-= adjust
;
5337 if (sched_ib
.filled
> sched_ib
.size
)
5338 sched_ib
.filled
= sched_ib
.size
;
5340 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
5343 ++sched_ib
.records
.adjust_index
;
5344 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
5345 sched_ib
.records
.adjust_index
= 0;
5347 /* Undo adjustement we did 7 instructions ago. */
5349 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
5354 gcc_assert (!sched_ib
.enabled_p
);
5362 gcc_assert (insn_size
<= sched_ib
.filled
);
5365 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
5366 || asm_noperands (PATTERN (insn
)) >= 0)
5367 insn_size
= sched_ib
.filled
;
5371 sched_ib
.filled
-= insn_size
;
5373 return can_issue_more
;
5376 /* Return how many instructions should scheduler lookahead to choose the
5379 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
5381 return m68k_sched_issue_rate () - 1;
5384 /* Implementation of targetm.sched.md_init_global () hook.
5385 It is invoked once per scheduling pass and is used here
5386 to initialize scheduler constants. */
5388 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
5389 int sched_verbose ATTRIBUTE_UNUSED
,
5390 int n_insns ATTRIBUTE_UNUSED
)
5392 /* Init branch types. */
5396 sched_branch_type
= xcalloc (get_max_uid () + 1,
5397 sizeof (*sched_branch_type
));
5399 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
5402 /* !!! FIXME: Implement real scan here. */
5403 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
5407 #ifdef ENABLE_CHECKING
5408 /* Check that all instructions have DFA reservations and
5409 that all instructions can be issued from a clean state. */
5414 state
= alloca (state_size ());
5416 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
5418 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
5420 gcc_assert (insn_has_dfa_reservation_p (insn
));
5422 state_reset (state
);
5423 if (state_transition (state
, insn
) >= 0)
5430 /* Setup target cpu. */
5432 /* ColdFire V4 has a set of features to keep its instruction buffer full
5433 (e.g., a separate memory bus for instructions) and, hence, we do not model
5434 buffer for this CPU. */
5435 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
5437 switch (m68k_sched_cpu
)
5440 sched_ib
.filled
= 0;
5447 sched_ib
.records
.n_insns
= 0;
5448 sched_ib
.records
.adjust
= NULL
;
5453 sched_ib
.records
.n_insns
= 8;
5454 sched_ib
.records
.adjust
= xmalloc (sched_ib
.records
.n_insns
5455 * sizeof (*sched_ib
.records
.adjust
));
5462 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
5464 sched_adjust_cost_state
= xmalloc (state_size ());
5465 state_reset (sched_adjust_cost_state
);
5468 emit_insn (gen_ib ());
5469 sched_ib
.insn
= get_insns ();
5473 /* Scheduling pass is now finished. Free/reset static variables. */
5475 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
5476 int verbose ATTRIBUTE_UNUSED
)
5478 sched_ib
.insn
= NULL
;
5480 free (sched_adjust_cost_state
);
5481 sched_adjust_cost_state
= NULL
;
5483 sched_mem_unit_code
= 0;
5485 free (sched_ib
.records
.adjust
);
5486 sched_ib
.records
.adjust
= NULL
;
5487 sched_ib
.records
.n_insns
= 0;
5490 free (sched_branch_type
);
5491 sched_branch_type
= NULL
;
5494 /* Implementation of targetm.sched.md_init () hook.
5495 It is invoked each time scheduler starts on the new block (basic block or
5496 extended basic block). */
5498 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
5499 int sched_verbose ATTRIBUTE_UNUSED
,
5500 int n_insns ATTRIBUTE_UNUSED
)
5502 switch (m68k_sched_cpu
)
5510 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
5512 memset (sched_ib
.records
.adjust
, 0,
5513 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
5514 sched_ib
.records
.adjust_index
= 0;
5518 gcc_assert (!sched_ib
.enabled_p
);
5526 if (sched_ib
.enabled_p
)
5527 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
5528 the first cycle. Workaround that. */
5529 sched_ib
.filled
= -2;
5532 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
5533 It is invoked just before current cycle finishes and is used here
5534 to track if instruction buffer got its two words this cycle. */
5536 m68k_sched_dfa_pre_advance_cycle (void)
5538 if (!sched_ib
.enabled_p
)
5541 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
5543 sched_ib
.filled
+= 2;
5545 if (sched_ib
.filled
> sched_ib
.size
)
5546 sched_ib
.filled
= sched_ib
.size
;
5550 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
5551 It is invoked just after new cycle begins and is used here
5552 to setup number of filled words in the instruction buffer so that
5553 instructions which won't have all their words prefetched would be
5554 stalled for a cycle. */
5556 m68k_sched_dfa_post_advance_cycle (void)
5560 if (!sched_ib
.enabled_p
)
5563 /* Setup number of prefetched instruction words in the instruction
5565 i
= max_insn_size
- sched_ib
.filled
;
5569 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
5574 /* Return X or Y (depending on OPX_P) operand of INSN,
5575 if it is an integer register, or NULL overwise. */
5577 sched_get_reg_operand (rtx insn
, bool opx_p
)
5583 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
5585 op
= sched_get_operand (insn
, true);
5586 gcc_assert (op
!= NULL
);
5588 if (!reload_completed
&& !REG_P (op
))
5594 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
5596 op
= sched_get_operand (insn
, false);
5597 gcc_assert (op
!= NULL
);
5599 if (!reload_completed
&& !REG_P (op
))
5607 /* Return true, if X or Y (depending on OPX_P) operand of INSN
5610 sched_mem_operand_p (rtx insn
, bool opx_p
)
5612 switch (sched_get_opxy_mem_type (insn
, opx_p
))
5623 /* Return X or Y (depending on OPX_P) operand of INSN,
5624 if it is a MEM, or NULL overwise. */
5626 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
5646 if (opy_p
&& sched_mem_operand_p (insn
, false))
5647 return sched_get_operand (insn
, false);
5649 if (opx_p
&& sched_mem_operand_p (insn
, true))
5650 return sched_get_operand (insn
, true);
5656 /* Return non-zero if PRO modifies register used as part of
5659 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
5664 pro_x
= sched_get_reg_operand (pro
, true);
5668 con_mem_read
= sched_get_mem_operand (con
, true, false);
5669 gcc_assert (con_mem_read
!= NULL
);
5671 if (reg_mentioned_p (pro_x
, con_mem_read
))
5677 /* Helper function for m68k_sched_indexed_address_bypass_p.
5678 if PRO modifies register used as index in CON,
5679 return scale of indexed memory access in CON. Return zero overwise. */
5681 sched_get_indexed_address_scale (rtx pro
, rtx con
)
5685 struct m68k_address address
;
5687 reg
= sched_get_reg_operand (pro
, true);
5691 mem
= sched_get_mem_operand (con
, true, false);
5692 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
5694 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
5698 if (REGNO (reg
) == REGNO (address
.index
))
5700 gcc_assert (address
.scale
!= 0);
5701 return address
.scale
;
5707 /* Return non-zero if PRO modifies register used
5708 as index with scale 2 or 4 in CON. */
5710 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
5712 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5713 && sched_cfv4_bypass_data
.con
== NULL
5714 && sched_cfv4_bypass_data
.scale
== 0);
5716 switch (sched_get_indexed_address_scale (pro
, con
))
5719 /* We can't have a variable latency bypass, so
5720 remember to adjust the insn cost in adjust_cost hook. */
5721 sched_cfv4_bypass_data
.pro
= pro
;
5722 sched_cfv4_bypass_data
.con
= con
;
5723 sched_cfv4_bypass_data
.scale
= 1;