gcc/config/m68k/cf.md

   1 ;; ColdFire V1, V2, V3 and V4/V4e DFA description.
   2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
   3 ;; Contributed by CodeSourcery Inc., www.codesourcery.com
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  20 ;; Boston, MA 02110-1301, USA.
  21
  22 ;; Instruction Buffer
  23 (define_automaton "cfv123_ib")
  24
  25 ;; These pseudo units are used to model instruction buffer of ColdFire cores.
  26 ;; Instruction of size N can be issued only when cf_ib_wN is available.
  27 (define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cfv123_ib")
  28
  29 ;; Instruction occupies 1 word in the instruction buffer.
  30 (define_reservation "cf_ib1" "cf_ib_w1")
  31 ;; Instruction occupies 2 words in the instruction buffer.
  32 (define_reservation "cf_ib2" "cf_ib_w1+cf_ib_w2")
  33 ;; Instruction occupies 3 words in the instruction buffer.
  34 (define_reservation "cf_ib3" "cf_ib_w1+cf_ib_w2+cf_ib_w3")
  35
  36 ;; This reservation is used at the start of each cycle to setup the maximal
  37 ;; length of instruction that can be issued on current cycle.
  38 ;; E.g., when this reservation is applied for the first time, cf_ib_w3
  39 ;; resource is marked busy, thus filtering out all 3-word insns.
  40 ;;
  41 ;; This reservation requires deterministic automaton.
  42 ;;
  43 ;; At each cycle, given that memory bus is available (i.e., there is no
  44 ;; pending memory operation), instruction fetch pipeline (IFP) prefetches
  45 ;; two instruction words into instruction buffer (IB).
  46 (define_insn_reservation "cf_ib1" 0
  47   (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
  48        (eq_attr "type" "ib"))
  49   "cf_ib_w3|cf_ib_w2|cf_ib_w1")
  50
  51 ;; Operand Execution Pipeline
  52 (define_automaton "cfv123_oep")
  53
  54 (define_cpu_unit "cf_dsoc,cf_agex" "cfv123_oep")
  55
  56 ;; A memory unit that is reffered to as 'certain hardware resources' in
  57 ;; ColdFire reference manuals.  This unit remains occupied for two cycles
  58 ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
  59 ;; two consecutive stores.
  60 (define_automaton "cfv123_chr")
  61
  62 (define_cpu_unit "cf_chr" "cfv123_chr")
  63
  64 ;; Memory bus
  65 (define_automaton "cfv123_mem")
  66
  67 ;; When memory bus is subscribed, that implies that instruction buffer won't
  68 ;; get its portion this cycle.  To model that we query if cf_mem unit is
  69 ;; subscribed and adjust number of prefetched instruction words accordingly.
  70 ;;
  71 (define_query_cpu_unit "cf_mem1, cf_mem2" "cfv123_mem")
  72
  73 (define_reservation "cf_mem" "cf_mem1+cf_mem2")
  74
  75 (define_automaton "cf_mac")
  76
  77 (define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4"
  78   "cf_mac")
  79
  80 (define_automaton "cfv123_guess")
  81
  82 (define_query_cpu_unit "cfv123_guess" "cfv123_guess")
  83
  84 ;; Register to register move.
  85 ;; Takes 1 cycle.
  86 (define_reservation "cfv123_alu_00"
  87   "cf_dsoc,cf_agex")
  88
  89 ;; Load from a memory location.
  90 ;; Takes 3 cycles.
  91 (define_reservation "cfv12_alu_10"
  92   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex")
  93 ;; Takes 2 cycles.
  94 (define_reservation "cfv12_omove_10"
  95   "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex")
  96 ;; Takes 4 cycles.
  97 (define_reservation "cfv3_alu_10"
  98   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
  99 ;; Takes 3 cycles.
 100 (define_reservation "cfv3_omove_10"
 101   "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
 102
 103 ;; Load from an indexed location.
 104 ;; Takes 4 cycles.
 105 (define_reservation "cfv12_alu_i0"
 106   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex")
 107 ;; Takes 3 cycles.
 108 (define_reservation "cfv12_omove_i0"
 109   "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex")
 110 ;; Takes 5 cycles.
 111 (define_reservation "cfv3_alu_i0"
 112   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
 113 ;; Takes 4 cycles.
 114 (define_reservation "cfv3_omove_i0"
 115   "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
 116
 117 ;; Store to a memory location.
 118 ;; Takes 1 cycle.
 119 (define_reservation "cfv12_alu_01"
 120   "cf_dsoc+cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 121 ;; Takes 1 cycle.
 122 (define_reservation "cfv3_alu_01"
 123   "cf_dsoc+cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 124
 125 ;; Store to an indexed location.
 126 ;; Takes 2 cycles.
 127 (define_reservation "cfv12_alu_0i"
 128   "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 129 ;; Takes 2 cycles.
 130 (define_reservation "cfv3_alu_0i"
 131   "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 132
 133 ;; Load from a memory location and store to a memory location.
 134 ;; Takes 3 cycles
 135 (define_reservation "cfv12_alu_11"
 136   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 137 ;; Takes 2 cycles.
 138 (define_reservation "cfv12_omove_11"
 139   "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 140 ;; Takes 4 cycles
 141 (define_reservation "cfv3_alu_11"
 142   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 143 ;; Takes 3 cycles.
 144 (define_reservation "cfv3_omove_11"
 145   "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 146
 147 ;; Load from an indexed location and store to a memory location.
 148 ;; Takes 4 cycles.
 149 (define_reservation "cfv12_alu_i1"
 150   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 151 ;; Takes 3 cycles.
 152 (define_reservation "cfv12_omove_i1"
 153   "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 154 ;; Takes 5 cycles.
 155 (define_reservation "cfv3_alu_i1"
 156   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 157 ;; Takes 4 cycles.
 158 (define_reservation "cfv3_omove_i1"
 159   "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 160
 161 ;; Load from a memory location and store to an indexed location.
 162 ;; Takes 4 cycles.
 163 (define_reservation "cfv12_alu_1i"
 164   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 165 ;; Takes 3 cycles.
 166 (define_reservation "cfv12_omove_1i"
 167   "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 168 ;; Takes 5 cycles.
 169 (define_reservation "cfv3_alu_1i"
 170   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 171 ;; Takes 4 cycles.
 172 (define_reservation "cfv3_omove_1i"
 173   "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 174
 175 ;; Lea operation for a memory location.
 176 ;; Takes 1 cycle.
 177 (define_reservation "cfv123_lea_10"
 178   "cf_dsoc,cf_agex")
 179
 180 ;; Lea operation for an indexed location.
 181 ;; Takes 2 cycles.
 182 (define_reservation "cfv123_lea_i0"
 183   "cf_dsoc,cf_agex,cf_agex")
 184
 185 ;; Pea operation for a memory location.
 186 ;; Takes 2 cycles.
 187 (define_reservation "cfv12_pea_11"
 188   "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 189 ;; Takes 2 cycles.
 190 (define_reservation "cfv3_pea_11"
 191   "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 192
 193 ;; Pea operation for an indexed location.
 194 ;; Takes 3 cycles.
 195 (define_reservation "cfv12_pea_i1"
 196   "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 197 ;; Takes 3 cycles.
 198 (define_reservation "cfv3_pea_i1"
 199   "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 200
 201 ;; Long multiplication with no mac.
 202 ;; Takes 9-18 cycles.
 203 (define_reservation "cfv123_mul_l_00"
 204   "cf_dsoc,(cf_agex+cf_dsoc)*17,cf_agex")
 205
 206 ;; Word multiplication with no mac.
 207 ;; Takes 9 cycles.
 208 (define_reservation "cfv123_mul_w_00"
 209   "cf_dsoc,(cf_agex+cf_dsoc)*8,cf_agex")
 210
 211 ;; Long multiplication with no mac.
 212 ;; Takes 11-20 cycles.
 213 (define_reservation "cfv12_mul_l_10"
 214   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*17,cf_agex")
 215 ;; Takes 12-21 cycles.
 216 (define_reservation "cfv3_mul_l_10"
 217   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*17,cf_agex")
 218
 219 ;; Word multiplication with no mac.
 220 ;; Takes 11 cycles.
 221 (define_reservation "cfv12_mul_w_10"
 222   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex")
 223 ;; Takes 12 cycles.
 224 (define_reservation "cfv3_mul_w_10"
 225   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
 226
 227 ;; Word multiplication with no mac.
 228 ;; Takes 12 cycles.
 229 (define_reservation "cfv12_mul_w_i0"
 230   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex")
 231 ;; Takes 13 cycles.
 232 (define_reservation "cfv3_mul_w_i0"
 233   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
 234
 235 ;; Long multiplication with mac.
 236 ;; Takes 5 cycles.
 237 (define_reservation "cfv123_mac_l_00"
 238   "cf_dsoc,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 239
 240 ;; Word multiplication with mac.
 241 ;; Takes 3 cycles.
 242 (define_reservation "cfv123_mac_w_00"
 243   "cf_dsoc,cf_agex,cf_mac1,cf_mac2")
 244
 245 ;; Long multiplication with mac.
 246 ;; Takes 7 cycles.
 247 (define_reservation "cfv12_mac_l_10"
 248   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 249 ;; Takes 8 cycles.
 250 (define_reservation "cfv3_mac_l_10"
 251   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 252
 253 ;; Word multiplication with mac.
 254 ;; Takes 5 cycles.
 255 (define_reservation "cfv12_mac_w_10"
 256   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2")
 257 ;; Takes 6 cycles.
 258 (define_reservation "cfv3_mac_w_10"
 259   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2")
 260
 261 ;; Word multiplication with mac.
 262 ;; Takes 6 cycles.
 263 (define_reservation "cfv12_mac_w_i0"
 264   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2")
 265 ;; Takes 7 cycles.
 266 (define_reservation "cfv3_mac_w_i0"
 267   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2")
 268
 269 ;; Multiplication with emac.
 270 ;; Takes 4 cycles.
 271 (define_reservation "cfv123_emac_00"
 272   "cf_dsoc,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 273
 274 ;; Multiplication with emac.
 275 ;; Takes 6 cycles.
 276 (define_reservation "cfv12_emac_10"
 277   "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 278 ;; Takes 7 cycles.
 279 (define_reservation "cfv3_emac_10"
 280   "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 281
 282 ;; Word multiplication with emac.
 283 ;; Takes 7 cycles.
 284 (define_reservation "cfv12_emac_w_i0"
 285   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 286 ;; Takes 8 cycles.
 287 (define_reservation "cfv3_emac_w_i0"
 288   "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 289
 290 ;; Return instruction.
 291 ;; ??? As return reads target address from stack, use a mem-read reservation
 292 ;; ??? for it.
 293 ;; ??? It's not clear what the core does during these 5 cycles.
 294 ;; ??? Luckily, we don't care that much about an insn that won't be moved.
 295 ;; Takes 5 cycles.
 296 (define_reservation "cfv12_rts" "cfv12_alu_10")
 297 ;; Takes 8 cycles.
 298 (define_reservation "cfv3_rts" "cfv3_alu_10")
 299
 300 ;; Call instruction.
 301 ;; ??? It's not clear what reservation is best to use for calls.
 302 ;; ??? For now we use mem-write + return reservations to reflect the fact of
 303 ;; ??? pushing and poping return address to and from the stack.
 304 ;; Takes 3 cycles.
 305 (define_reservation "cfv12_call" "cfv12_alu_01,cfv12_rts")
 306 ;; Takes 1/5 cycles.
 307 (define_reservation "cfv3_call" "cfv3_alu_01,cfv3_rts")
 308
 309 ;; Conditional branch instruction.
 310 ;; ??? Branch reservations are unclear to me so far.  Luckily, we don't care
 311 ;; ??? that much about branches.
 312 ;; Takes 2 cycles.
 313 (define_reservation "cfv12_bcc" "cfv123_alu_00")
 314 ;; Takes 1 cycles.
 315 (define_reservation "cfv3_bcc" "cfv123_alu_00")
 316
 317 ;; Unconditional branch instruciton.
 318 ;; Takes 2 cycles.
 319 (define_reservation "cfv12_bra" "cfv12_alu_01")
 320 ;; Takes 1 cycles.
 321 (define_reservation "cfv3_bra" "cfv3_alu_01")
 322
 323 ;; Computed jump instruction.
 324 ;; Takes 3 cycles.
 325 (define_reservation "cfv12_jmp"
 326   "(cf_dsoc+cf_agex)*3")
 327 ;; Takes 5 cycles.
 328 (define_reservation "cfv3_jmp"
 329   "(cf_dsoc+cf_agex)*5")
 330
 331 ;; Instruction reservations.
 332
 333 ;; Below reservations are simple derivation from the above reservations.
 334 ;; Each reservation from the above expands into 3 reservations below - one
 335 ;; for each instruction size.
 336 ;; A number in the end of reservation's name is the size of the instruction.
 337
 338 (define_insn_reservation "cfv123_alu_00_1" 1
 339   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 340                  (eq_attr "type" "
 341 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 342 clr,clr_l,mov3q_l,move,moveq_l,tst,
 343 move_l,tst_l"))
 344             (eq_attr "op_mem" "00"))
 345        (eq_attr "size" "1"))
 346   "cf_ib1+cfv123_alu_00")
 347
 348 (define_insn_reservation "cfv123_alu_00_2" 1
 349   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 350                  (eq_attr "type" "
 351 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 352 clr,clr_l,mov3q_l,move,moveq_l,tst,
 353 move_l,tst_l"))
 354             (eq_attr "op_mem" "00"))
 355        (eq_attr "size" "2"))
 356   "cf_ib2+cfv123_alu_00")
 357
 358 (define_insn_reservation "cfv123_alu_00_3" 1
 359   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 360                  (eq_attr "type" "
 361 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 362 clr,clr_l,mov3q_l,move,moveq_l,tst,
 363 move_l,tst_l"))
 364             (eq_attr "op_mem" "00"))
 365        (eq_attr "size" "3"))
 366   "cf_ib3+cfv123_alu_00")
 367
 368 (define_insn_reservation "cfv1_alu_10_1" 3
 369   (and (and (and (eq_attr "cpu" "cfv1")
 370                  (eq_attr "type" "
 371 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 372             (eq_attr "op_mem" "10"))
 373        (eq_attr "size" "1"))
 374   "cf_ib1+cfv12_alu_10")
 375
 376 (define_insn_reservation "cfv1_alu_10_2" 3
 377   (and (and (and (eq_attr "cpu" "cfv1")
 378                  (eq_attr "type" "
 379 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 380             (eq_attr "op_mem" "10"))
 381        (eq_attr "size" "2"))
 382   "cf_ib2+cfv12_alu_10")
 383
 384 (define_insn_reservation "cfv1_alu_10_3" 3
 385   (and (and (and (eq_attr "cpu" "cfv1")
 386                  (eq_attr "type" "
 387 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 388             (eq_attr "op_mem" "10"))
 389        (eq_attr "size" "3"))
 390   "cf_ib3+cfv12_alu_10")
 391
 392 (define_insn_reservation "cfv1_omove_10_1" 2
 393   (and (and (and (eq_attr "cpu" "cfv1")
 394                  (eq_attr "type" "
 395 clr,clr_l,mov3q_l,move,moveq_l,tst,
 396 move_l,tst_l"))
 397             (eq_attr "op_mem" "10"))
 398        (eq_attr "size" "1"))
 399   "cf_ib1+cfv12_omove_10")
 400
 401 (define_insn_reservation "cfv1_omove_10_2" 2
 402   (and (and (and (eq_attr "cpu" "cfv1")
 403                  (eq_attr "type" "
 404 clr,clr_l,mov3q_l,move,moveq_l,tst,
 405 move_l,tst_l"))
 406             (eq_attr "op_mem" "10"))
 407        (eq_attr "size" "2"))
 408   "cf_ib2+cfv12_omove_10")
 409
 410 (define_insn_reservation "cfv1_omove_10_3" 2
 411   (and (and (and (eq_attr "cpu" "cfv1")
 412                  (eq_attr "type" "
 413 clr,clr_l,mov3q_l,move,moveq_l,tst,
 414 move_l,tst_l"))
 415             (eq_attr "op_mem" "10"))
 416        (eq_attr "size" "3"))
 417   "cf_ib3+cfv12_omove_10")
 418
 419 (define_insn_reservation "cfv2_alu_10_1" 3
 420   (and (and (and (eq_attr "cpu" "cfv2")
 421                  (eq_attr "type" "
 422 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 423 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 424             (eq_attr "op_mem" "10"))
 425        (eq_attr "size" "1"))
 426   "cf_ib1+cfv12_alu_10")
 427
 428 (define_insn_reservation "cfv2_alu_10_2" 3
 429   (and (and (and (eq_attr "cpu" "cfv2")
 430                  (eq_attr "type" "
 431 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 432 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 433             (eq_attr "op_mem" "10"))
 434        (eq_attr "size" "2"))
 435   "cf_ib2+cfv12_alu_10")
 436
 437 (define_insn_reservation "cfv2_alu_10_3" 3
 438   (and (and (and (eq_attr "cpu" "cfv2")
 439                  (eq_attr "type" "
 440 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 441 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 442             (eq_attr "op_mem" "10"))
 443        (eq_attr "size" "3"))
 444   "cf_ib3+cfv12_alu_10")
 445
 446 (define_insn_reservation "cfv2_omove_10_1" 2
 447   (and (and (and (eq_attr "cpu" "cfv2")
 448                  (eq_attr "type" "
 449 move_l,tst_l"))
 450             (eq_attr "op_mem" "10"))
 451        (eq_attr "size" "1"))
 452   "cf_ib1+cfv12_omove_10")
 453
 454 (define_insn_reservation "cfv2_omove_10_2" 2
 455   (and (and (and (eq_attr "cpu" "cfv2")
 456                  (eq_attr "type" "
 457 move_l,tst_l"))
 458             (eq_attr "op_mem" "10"))
 459        (eq_attr "size" "2"))
 460   "cf_ib2+cfv12_omove_10")
 461
 462 (define_insn_reservation "cfv2_omove_10_3" 2
 463   (and (and (and (eq_attr "cpu" "cfv2")
 464                  (eq_attr "type" "
 465 move_l,tst_l"))
 466             (eq_attr "op_mem" "10"))
 467        (eq_attr "size" "3"))
 468   "cf_ib3+cfv12_omove_10")
 469
 470 (define_insn_reservation "cfv3_alu_10_1" 4
 471   (and (and (and (eq_attr "cpu" "cfv3")
 472                  (eq_attr "type" "
 473 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 474 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 475             (eq_attr "op_mem" "10"))
 476        (eq_attr "size" "1"))
 477   "cf_ib1+cfv3_alu_10")
 478
 479 (define_insn_reservation "cfv3_alu_10_2" 4
 480   (and (and (and (eq_attr "cpu" "cfv3")
 481                  (eq_attr "type" "
 482 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 483 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 484             (eq_attr "op_mem" "10"))
 485        (eq_attr "size" "2"))
 486   "cf_ib2+cfv3_alu_10")
 487
 488 (define_insn_reservation "cfv3_alu_10_3" 4
 489   (and (and (and (eq_attr "cpu" "cfv3")
 490                  (eq_attr "type" "
 491 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 492 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 493             (eq_attr "op_mem" "10"))
 494        (eq_attr "size" "3"))
 495   "cf_ib3+cfv3_alu_10")
 496
 497 (define_insn_reservation "cfv3_omove_10_1" 3
 498   (and (and (and (eq_attr "cpu" "cfv3")
 499                  (eq_attr "type" "
 500 move_l,tst_l"))
 501             (eq_attr "op_mem" "10"))
 502        (eq_attr "size" "1"))
 503   "cf_ib1+cfv3_omove_10")
 504
 505 (define_insn_reservation "cfv3_omove_10_2" 3
 506   (and (and (and (eq_attr "cpu" "cfv3")
 507                  (eq_attr "type" "
 508 move_l,tst_l"))
 509             (eq_attr "op_mem" "10"))
 510        (eq_attr "size" "2"))
 511   "cf_ib2+cfv3_omove_10")
 512
 513 (define_insn_reservation "cfv3_omove_10_3" 3
 514   (and (and (and (eq_attr "cpu" "cfv3")
 515                  (eq_attr "type" "
 516 move_l,tst_l"))
 517             (eq_attr "op_mem" "10"))
 518        (eq_attr "size" "3"))
 519   "cf_ib3+cfv3_omove_10")
 520
 521 (define_insn_reservation "cfv1_alu_i0_2" 4
 522   (and (and (and (eq_attr "cpu" "cfv1")
 523                  (eq_attr "type" "
 524 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 525             (eq_attr "op_mem" "i0"))
 526        (eq_attr "size" "1,2"))
 527   "cf_ib2+cfv12_alu_i0")
 528
 529 (define_insn_reservation "cfv1_alu_i0_3" 4
 530   (and (and (and (eq_attr "cpu" "cfv1")
 531                  (eq_attr "type" "
 532 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 533             (eq_attr "op_mem" "i0"))
 534        (eq_attr "size" "3"))
 535   "cf_ib3+cfv12_alu_i0")
 536
 537 (define_insn_reservation "cfv1_omove_i0_2" 3
 538   (and (and (and (eq_attr "cpu" "cfv1")
 539                  (eq_attr "type" "
 540 clr,clr_l,mov3q_l,move,moveq_l,tst,
 541 move_l,tst_l"))
 542             (eq_attr "op_mem" "i0"))
 543        (eq_attr "size" "1,2"))
 544   "cf_ib2+cfv12_omove_i0")
 545
 546 (define_insn_reservation "cfv1_omove_i0_3" 3
 547   (and (and (and (eq_attr "cpu" "cfv1")
 548                  (eq_attr "type" "
 549 clr,clr_l,mov3q_l,move,moveq_l,tst,
 550 move_l,tst_l"))
 551             (eq_attr "op_mem" "i0"))
 552        (eq_attr "size" "3"))
 553   "cf_ib3+cfv12_omove_i0")
 554
 555 (define_insn_reservation "cfv2_alu_i0_2" 4
 556   (and (and (and (eq_attr "cpu" "cfv2")
 557                  (eq_attr "type" "
 558 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 559 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 560             (eq_attr "op_mem" "i0"))
 561        (eq_attr "size" "1,2"))
 562   "cf_ib2+cfv12_alu_i0")
 563
 564 (define_insn_reservation "cfv2_alu_i0_3" 4
 565   (and (and (and (eq_attr "cpu" "cfv2")
 566                  (eq_attr "type" "
 567 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 568 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 569             (eq_attr "op_mem" "i0"))
 570        (eq_attr "size" "3"))
 571   "cf_ib3+cfv12_alu_i0")
 572
 573 (define_insn_reservation "cfv2_omove_i0_2" 3
 574   (and (and (and (eq_attr "cpu" "cfv2")
 575                  (eq_attr "type" "
 576 move_l,tst_l"))
 577             (eq_attr "op_mem" "i0"))
 578        (eq_attr "size" "1,2"))
 579   "cf_ib2+cfv12_omove_i0")
 580
 581 (define_insn_reservation "cfv2_omove_i0_3" 3
 582   (and (and (and (eq_attr "cpu" "cfv2")
 583                  (eq_attr "type" "
 584 move_l,tst_l"))
 585             (eq_attr "op_mem" "i0"))
 586        (eq_attr "size" "3"))
 587   "cf_ib3+cfv12_omove_i0")
 588
 589 (define_insn_reservation "cfv3_alu_i0_2" 5
 590   (and (and (and (eq_attr "cpu" "cfv3")
 591                  (eq_attr "type" "
 592 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 593 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 594             (eq_attr "op_mem" "i0"))
 595        (eq_attr "size" "1,2"))
 596   "cf_ib2+cfv3_alu_i0")
 597
 598 (define_insn_reservation "cfv3_alu_i0_3" 5
 599   (and (and (and (eq_attr "cpu" "cfv3")
 600                  (eq_attr "type" "
 601 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 602 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 603             (eq_attr "op_mem" "i0"))
 604        (eq_attr "size" "3"))
 605   "cf_ib3+cfv3_alu_i0")
 606
 607 (define_insn_reservation "cfv3_omove_i0_2" 4
 608   (and (and (and (eq_attr "cpu" "cfv3")
 609                  (eq_attr "type" "
 610 move_l,tst_l"))
 611             (eq_attr "op_mem" "i0"))
 612        (eq_attr "size" "1,2"))
 613   "cf_ib2+cfv3_omove_i0")
 614
 615 (define_insn_reservation "cfv3_omove_i0_3" 4
 616   (and (and (and (eq_attr "cpu" "cfv3")
 617                  (eq_attr "type" "
 618 move_l,tst_l"))
 619             (eq_attr "op_mem" "i0"))
 620        (eq_attr "size" "3"))
 621   "cf_ib3+cfv3_omove_i0")
 622
 623 (define_insn_reservation "cfv12_alu_01_1" 1
 624   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 625                  (eq_attr "type" "
 626 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 627 clr,clr_l,mov3q_l,move,moveq_l,tst,
 628 move_l,tst_l"))
 629             (eq_attr "op_mem" "01"))
 630        (eq_attr "size" "1"))
 631   "cf_ib1+cfv12_alu_01")
 632
 633 (define_insn_reservation "cfv12_alu_01_2" 1
 634   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 635                  (eq_attr "type" "
 636 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 637 clr,clr_l,mov3q_l,move,moveq_l,tst,
 638 move_l,tst_l"))
 639             (eq_attr "op_mem" "01"))
 640        (eq_attr "size" "2"))
 641   "cf_ib2+cfv12_alu_01")
 642
 643 (define_insn_reservation "cfv12_alu_01_3" 1
 644   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 645                  (eq_attr "type" "
 646 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 647 clr,clr_l,mov3q_l,move,moveq_l,tst,
 648 move_l,tst_l"))
 649             (eq_attr "op_mem" "01"))
 650        (eq_attr "size" "3"))
 651   "cf_ib3+cfv12_alu_01")
 652
 653 (define_insn_reservation "cfv3_alu_01_1" 1
 654   (and (and (and (eq_attr "cpu" "cfv3")
 655                  (eq_attr "type" "
 656 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 657 clr,clr_l,mov3q_l,move,moveq_l,tst,
 658 move_l,tst_l"))
 659             (eq_attr "op_mem" "01"))
 660        (eq_attr "size" "1"))
 661   "cf_ib1+cfv3_alu_01")
 662
 663 (define_insn_reservation "cfv3_alu_01_2" 1
 664   (and (and (and (eq_attr "cpu" "cfv3")
 665                  (eq_attr "type" "
 666 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 667 clr,clr_l,mov3q_l,move,moveq_l,tst,
 668 move_l,tst_l"))
 669             (eq_attr "op_mem" "01"))
 670        (eq_attr "size" "2"))
 671   "cf_ib2+cfv3_alu_01")
 672
 673 (define_insn_reservation "cfv3_alu_01_3" 1
 674   (and (and (and (eq_attr "cpu" "cfv3")
 675                  (eq_attr "type" "
 676 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 677 clr,clr_l,mov3q_l,move,moveq_l,tst,
 678 move_l,tst_l"))
 679             (eq_attr "op_mem" "01"))
 680        (eq_attr "size" "3"))
 681   "cf_ib3+cfv3_alu_01")
 682
 683 (define_insn_reservation "cfv12_alu_0i_2" 2
 684   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 685                  (eq_attr "type" "
 686 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 687 clr,clr_l,mov3q_l,move,moveq_l,tst,
 688 move_l,tst_l"))
 689             (eq_attr "op_mem" "0i"))
 690        (eq_attr "size" "1,2"))
 691   "cf_ib2+cfv12_alu_0i")
 692
 693 (define_insn_reservation "cfv12_alu_0i_3" 2
 694   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 695                  (eq_attr "type" "
 696 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 697 clr,clr_l,mov3q_l,move,moveq_l,tst,
 698 move_l,tst_l"))
 699             (eq_attr "op_mem" "0i"))
 700        (eq_attr "size" "3"))
 701   "cf_ib3+cfv12_alu_0i")
 702
 703 (define_insn_reservation "cfv3_alu_0i_2" 2
 704   (and (and (and (eq_attr "cpu" "cfv3")
 705                  (eq_attr "type" "
 706 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 707 clr,clr_l,mov3q_l,move,moveq_l,tst,
 708 move_l,tst_l"))
 709             (eq_attr "op_mem" "0i"))
 710        (eq_attr "size" "1,2"))
 711   "cf_ib2+cfv3_alu_0i")
 712
 713 (define_insn_reservation "cfv3_alu_0i_3" 2
 714   (and (and (and (eq_attr "cpu" "cfv3")
 715                  (eq_attr "type" "
 716 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 717 clr,clr_l,mov3q_l,move,moveq_l,tst,
 718 move_l,tst_l"))
 719             (eq_attr "op_mem" "0i"))
 720        (eq_attr "size" "3"))
 721   "cf_ib3+cfv3_alu_0i")
 722
 723 (define_insn_reservation "cfv1_alu_11_1" 1
 724   (and (and (and (eq_attr "cpu" "cfv1")
 725                  (eq_attr "type" "
 726 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 727             (eq_attr "op_mem" "11"))
 728        (eq_attr "size" "1"))
 729   "cf_ib1+cfv12_alu_11")
 730
 731 (define_insn_reservation "cfv1_alu_11_2" 1
 732   (and (and (and (eq_attr "cpu" "cfv1")
 733                  (eq_attr "type" "
 734 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 735             (eq_attr "op_mem" "11"))
 736        (eq_attr "size" "2"))
 737   "cf_ib2+cfv12_alu_11")
 738
 739 (define_insn_reservation "cfv1_alu_11_3" 1
 740   (and (and (and (eq_attr "cpu" "cfv1")
 741                  (eq_attr "type" "
 742 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 743             (eq_attr "op_mem" "11"))
 744        (eq_attr "size" "3"))
 745   "cf_ib3+cfv12_alu_11")
 746
 747 (define_insn_reservation "cfv1_omove_11_1" 1
 748   (and (and (and (eq_attr "cpu" "cfv1")
 749                  (eq_attr "type" "
 750 clr,clr_l,mov3q_l,move,moveq_l,tst,
 751 move_l,tst_l"))
 752             (eq_attr "op_mem" "11"))
 753        (eq_attr "size" "1"))
 754   "cf_ib1+cfv12_omove_11")
 755
 756 (define_insn_reservation "cfv1_omove_11_2" 1
 757   (and (and (and (eq_attr "cpu" "cfv1")
 758                  (eq_attr "type" "
 759 clr,clr_l,mov3q_l,move,moveq_l,tst,
 760 move_l,tst_l"))
 761             (eq_attr "op_mem" "11"))
 762        (eq_attr "size" "2"))
 763   "cf_ib2+cfv12_omove_11")
 764
 765 (define_insn_reservation "cfv1_omove_11_3" 1
 766   (and (and (and (eq_attr "cpu" "cfv1")
 767                  (eq_attr "type" "
 768 clr,clr_l,mov3q_l,move,moveq_l,tst,
 769 move_l,tst_l"))
 770             (eq_attr "op_mem" "11"))
 771        (eq_attr "size" "3"))
 772   "cf_ib3+cfv12_omove_11")
 773
 774 (define_insn_reservation "cfv2_alu_11_1" 1
 775   (and (and (and (eq_attr "cpu" "cfv2")
 776                  (eq_attr "type" "
 777 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 778 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 779             (eq_attr "op_mem" "11"))
 780        (eq_attr "size" "1"))
 781   "cf_ib1+cfv12_alu_11")
 782
 783 (define_insn_reservation "cfv2_alu_11_2" 1
 784   (and (and (and (eq_attr "cpu" "cfv2")
 785                  (eq_attr "type" "
 786 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 787 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 788             (eq_attr "op_mem" "11"))
 789        (eq_attr "size" "2"))
 790   "cf_ib2+cfv12_alu_11")
 791
 792 (define_insn_reservation "cfv2_alu_11_3" 1
 793   (and (and (and (eq_attr "cpu" "cfv2")
 794                  (eq_attr "type" "
 795 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 796 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 797             (eq_attr "op_mem" "11"))
 798        (eq_attr "size" "3"))
 799   "cf_ib3+cfv12_alu_11")
 800
 801 (define_insn_reservation "cfv2_omove_11_1" 1
 802   (and (and (and (eq_attr "cpu" "cfv2")
 803                  (eq_attr "type" "
 804 move_l,tst_l"))
 805             (eq_attr "op_mem" "11"))
 806        (eq_attr "size" "1"))
 807   "cf_ib1+cfv12_omove_11")
 808
 809 (define_insn_reservation "cfv2_omove_11_2" 1
 810   (and (and (and (eq_attr "cpu" "cfv2")
 811                  (eq_attr "type" "
 812 move_l,tst_l"))
 813             (eq_attr "op_mem" "11"))
 814        (eq_attr "size" "2"))
 815   "cf_ib2+cfv12_omove_11")
 816
 817 (define_insn_reservation "cfv2_omove_11_3" 1
 818   (and (and (and (eq_attr "cpu" "cfv2")
 819                  (eq_attr "type" "
 820 move_l,tst_l"))
 821             (eq_attr "op_mem" "11"))
 822        (eq_attr "size" "3"))
 823   "cf_ib3+cfv12_omove_11")
 824
 825 (define_insn_reservation "cfv3_alu_11_1" 1
 826   (and (and (and (eq_attr "cpu" "cfv3")
 827                  (eq_attr "type" "
 828 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 829 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 830             (eq_attr "op_mem" "11"))
 831        (eq_attr "size" "1"))
 832   "cf_ib1+cfv3_alu_11")
 833
 834 (define_insn_reservation "cfv3_alu_11_2" 1
 835   (and (and (and (eq_attr "cpu" "cfv3")
 836                  (eq_attr "type" "
 837 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 838 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 839             (eq_attr "size" "2"))
 840        (eq_attr "op_mem" "11"))
 841   "cf_ib2+cfv3_alu_11")
 842
 843 (define_insn_reservation "cfv3_alu_11_3" 1
 844   (and (and (and (eq_attr "cpu" "cfv3")
 845                  (eq_attr "type" "
 846 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 847 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 848             (eq_attr "op_mem" "11"))
 849        (eq_attr "size" "3"))
 850   "cf_ib3+cfv3_alu_11")
 851
 852 (define_insn_reservation "cfv3_omove_11_1" 1
 853   (and (and (and (eq_attr "cpu" "cfv3")
 854                  (eq_attr "type" "
 855 move_l,tst_l"))
 856             (eq_attr "op_mem" "11"))
 857        (eq_attr "size" "1"))
 858   "cf_ib1+cfv3_omove_11")
 859
 860 (define_insn_reservation "cfv3_omove_11_2" 1
 861   (and (and (and (eq_attr "cpu" "cfv3")
 862                  (eq_attr "type" "
 863 move_l,tst_l"))
 864             (eq_attr "size" "2"))
 865        (eq_attr "op_mem" "11"))
 866   "cf_ib2+cfv3_omove_11")
 867
 868 (define_insn_reservation "cfv3_omove_11_3" 1
 869   (and (and (and (eq_attr "cpu" "cfv3")
 870                  (eq_attr "type" "
 871 move_l,tst_l"))
 872             (eq_attr "op_mem" "11"))
 873        (eq_attr "size" "3"))
 874   "cf_ib3+cfv3_omove_11")
 875
 876 (define_insn_reservation "cfv1_alu_i1_2" 2
 877   (and (and (and (eq_attr "cpu" "cfv1")
 878                  (eq_attr "type" "
 879 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 880             (eq_attr "op_mem" "i1"))
 881        (eq_attr "size" "1,2"))
 882   "cf_ib2+cfv12_alu_i1")
 883
 884 (define_insn_reservation "cfv1_alu_i1_3" 2
 885   (and (and (and (eq_attr "cpu" "cfv1")
 886                  (eq_attr "type" "
 887 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 888             (eq_attr "op_mem" "i1"))
 889        (eq_attr "size" "3"))
 890   "cf_ib3+cfv12_alu_i1")
 891
 892 (define_insn_reservation "cfv1_omove_i1_2" 2
 893   (and (and (and (eq_attr "cpu" "cfv1")
 894                  (eq_attr "type" "
 895 clr,clr_l,mov3q_l,move,moveq_l,tst,
 896 move_l,tst_l"))
 897             (eq_attr "op_mem" "i1"))
 898        (eq_attr "size" "1,2"))
 899   "cf_ib2+cfv12_omove_i1")
 900
 901 (define_insn_reservation "cfv1_omove_i1_3" 2
 902   (and (and (and (eq_attr "cpu" "cfv1")
 903                  (eq_attr "type" "
 904 clr,clr_l,mov3q_l,move,moveq_l,tst,
 905 move_l,tst_l"))
 906             (eq_attr "op_mem" "i1"))
 907        (eq_attr "size" "3"))
 908   "cf_ib3+cfv12_omove_i1")
 909
 910 (define_insn_reservation "cfv2_alu_i1_2" 2
 911   (and (and (and (eq_attr "cpu" "cfv2")
 912                  (eq_attr "type" "
 913 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 914 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 915             (eq_attr "op_mem" "i1"))
 916        (eq_attr "size" "1,2"))
 917   "cf_ib2+cfv12_alu_i1")
 918
 919 (define_insn_reservation "cfv2_alu_i1_3" 2
 920   (and (and (and (eq_attr "cpu" "cfv2")
 921                  (eq_attr "type" "
 922 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 923 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 924             (eq_attr "op_mem" "i1"))
 925        (eq_attr "size" "3"))
 926   "cf_ib3+cfv12_alu_i1")
 927
 928 (define_insn_reservation "cfv2_omove_i1_2" 2
 929   (and (and (and (eq_attr "cpu" "cfv2")
 930                  (eq_attr "type" "
 931 move_l,tst_l"))
 932             (eq_attr "op_mem" "i1"))
 933        (eq_attr "size" "1,2"))
 934   "cf_ib2+cfv12_omove_i1")
 935
 936 (define_insn_reservation "cfv2_omove_i1_3" 2
 937   (and (and (and (eq_attr "cpu" "cfv2")
 938                  (eq_attr "type" "
 939 move_l,tst_l"))
 940             (eq_attr "op_mem" "i1"))
 941        (eq_attr "size" "3"))
 942   "cf_ib3+cfv12_omove_i1")
 943
 944 (define_insn_reservation "cfv3_alu_i1_2" 2
 945   (and (and (and (eq_attr "cpu" "cfv3")
 946                  (eq_attr "type" "
 947 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 948 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 949             (eq_attr "op_mem" "i1"))
 950        (eq_attr "size" "1,2"))
 951   "cf_ib2+cfv3_alu_i1")
 952
 953 (define_insn_reservation "cfv3_alu_i1_3" 2
 954   (and (and (and (eq_attr "cpu" "cfv3")
 955                  (eq_attr "type" "
 956 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
 957 clr,clr_l,mov3q_l,move,moveq_l,tst"))
 958             (eq_attr "op_mem" "i1"))
 959        (eq_attr "size" "3"))
 960   "cf_ib3+cfv3_alu_i1")
 961
 962 (define_insn_reservation "cfv3_omove_i1_2" 2
 963   (and (and (and (eq_attr "cpu" "cfv3")
 964                  (eq_attr "type" "
 965 move_l,tst_l"))
 966             (eq_attr "op_mem" "i1"))
 967        (eq_attr "size" "1,2"))
 968   "cf_ib2+cfv3_omove_i1")
 969
 970 (define_insn_reservation "cfv3_omove_i1_3" 2
 971   (and (and (and (eq_attr "cpu" "cfv3")
 972                  (eq_attr "type" "
 973 move_l,tst_l"))
 974             (eq_attr "op_mem" "i1"))
 975        (eq_attr "size" "3"))
 976   "cf_ib3+cfv3_omove_i1")
 977
 978 (define_insn_reservation "cfv1_alu_1i_2" 2
 979   (and (and (and (eq_attr "cpu" "cfv1")
 980                  (eq_attr "type" "
 981 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 982             (eq_attr "op_mem" "1i"))
 983        (eq_attr "size" "1,2"))
 984   "cf_ib2+cfv12_alu_1i")
 985
 986 (define_insn_reservation "cfv1_alu_1i_3" 2
 987   (and (and (and (eq_attr "cpu" "cfv1")
 988                  (eq_attr "type" "
 989 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
 990             (eq_attr "op_mem" "1i"))
 991        (eq_attr "size" "3"))
 992   "cf_ib3+cfv12_alu_1i")
 993
 994 (define_insn_reservation "cfv1_omove_1i_2" 2
 995   (and (and (and (eq_attr "cpu" "cfv1")
 996                  (eq_attr "type" "
 997 clr,clr_l,mov3q_l,move,moveq_l,tst,
 998 move_l,tst_l"))
 999             (eq_attr "op_mem" "1i"))
1000        (eq_attr "size" "1,2"))
1001   "cf_ib2+cfv12_omove_1i")
1002
1003 (define_insn_reservation "cfv1_omove_1i_3" 2
1004   (and (and (and (eq_attr "cpu" "cfv1")
1005                  (eq_attr "type" "
1006 clr,clr_l,mov3q_l,move,moveq_l,tst,
1007 move_l,tst_l"))
1008             (eq_attr "op_mem" "1i"))
1009        (eq_attr "size" "3"))
1010   "cf_ib3+cfv12_omove_1i")
1011
1012 (define_insn_reservation "cfv2_alu_1i_2" 2
1013   (and (and (and (eq_attr "cpu" "cfv2")
1014                  (eq_attr "type" "
1015 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
1016 clr,clr_l,mov3q_l,move,moveq_l,tst"))
1017             (eq_attr "op_mem" "1i"))
1018        (eq_attr "size" "1,2"))
1019   "cf_ib2+cfv12_alu_1i")
1020
1021 (define_insn_reservation "cfv2_alu_1i_3" 2
1022   (and (and (and (eq_attr "cpu" "cfv2")
1023                  (eq_attr "type" "
1024 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
1025 clr,clr_l,mov3q_l,move,moveq_l,tst"))
1026             (eq_attr "op_mem" "1i"))
1027        (eq_attr "size" "3"))
1028   "cf_ib3+cfv12_alu_1i")
1029
1030 (define_insn_reservation "cfv2_omove_1i_2" 2
1031   (and (and (and (eq_attr "cpu" "cfv2")
1032                  (eq_attr "type" "
1033 move_l,tst_l"))
1034             (eq_attr "op_mem" "1i"))
1035        (eq_attr "size" "1,2"))
1036   "cf_ib2+cfv12_omove_1i")
1037
1038 (define_insn_reservation "cfv2_omove_1i_3" 2
1039   (and (and (and (eq_attr "cpu" "cfv2")
1040                  (eq_attr "type" "
1041 move_l,tst_l"))
1042             (eq_attr "op_mem" "1i"))
1043        (eq_attr "size" "3"))
1044   "cf_ib3+cfv12_omove_1i")
1045
1046 (define_insn_reservation "cfv3_alu_1i_2" 2
1047   (and (and (and (eq_attr "cpu" "cfv3")
1048                  (eq_attr "type" "
1049 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
1050 clr,clr_l,mov3q_l,move,moveq_l,tst"))
1051             (eq_attr "op_mem" "1i"))
1052        (eq_attr "size" "1,2"))
1053   "cf_ib2+cfv3_alu_1i")
1054
1055 (define_insn_reservation "cfv3_alu_1i_3" 2
1056   (and (and (and (eq_attr "cpu" "cfv3")
1057                  (eq_attr "type" "
1058 alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
1059 clr,clr_l,mov3q_l,move,moveq_l,tst"))
1060             (eq_attr "op_mem" "1i"))
1061        (eq_attr "size" "3"))
1062   "cf_ib3+cfv3_alu_1i")
1063
1064 (define_insn_reservation "cfv3_omove_1i_2" 2
1065   (and (and (and (eq_attr "cpu" "cfv3")
1066                  (eq_attr "type" "
1067 move_l,tst_l"))
1068             (eq_attr "op_mem" "1i"))
1069        (eq_attr "size" "1,2"))
1070   "cf_ib2+cfv3_omove_1i")
1071
1072 (define_insn_reservation "cfv3_omove_1i_3" 2
1073   (and (and (and (eq_attr "cpu" "cfv3")
1074                  (eq_attr "type" "
1075 move_l,tst_l"))
1076             (eq_attr "op_mem" "1i"))
1077        (eq_attr "size" "3"))
1078   "cf_ib3+cfv3_omove_1i")
1079
1080 (define_insn_reservation "cfv123_lea_10_1" 1
1081   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1082                  (eq_attr "type" "lea"))
1083             (eq_attr "op_mem" "10,11,1i"))
1084        (eq_attr "size" "1"))
1085   "cf_ib1+cfv123_lea_10")
1086
1087 (define_insn_reservation "cfv123_lea_10_2" 1
1088   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1089                  (eq_attr "type" "lea"))
1090             (eq_attr "op_mem" "10,11,1i"))
1091        (eq_attr "size" "2"))
1092   "cf_ib2+cfv123_lea_10")
1093
1094 (define_insn_reservation "cfv123_lea_10_3" 1
1095   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1096                  (eq_attr "type" "lea"))
1097             (eq_attr "op_mem" "10,11,1i"))
1098        (eq_attr "size" "3"))
1099   "cf_ib3+cfv123_lea_10")
1100
1101 (define_insn_reservation "cfv123_lea_i0_2" 2
1102   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1103                  (eq_attr "type" "lea"))
1104             (eq_attr "op_mem" "i0,i1"))
1105        (eq_attr "size" "1,2"))
1106   "cf_ib2+cfv123_lea_i0")
1107
1108 (define_insn_reservation "cfv123_lea_i0_3" 2
1109   (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1110                  (eq_attr "type" "lea"))
1111             (eq_attr "op_mem" "i0,i1"))
1112        (eq_attr "size" "3"))
1113   "cf_ib3+cfv123_lea_i0")
1114
1115 (define_insn_reservation "cfv12_pea_11_1" 1
1116   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1117                  (eq_attr "type" "pea"))
1118             (eq_attr "op_mem" "11"))
1119        (eq_attr "size" "1"))
1120   "cf_ib1+cfv12_pea_11")
1121
1122 (define_insn_reservation "cfv12_pea_11_2" 1
1123   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1124                  (eq_attr "type" "pea"))
1125             (eq_attr "op_mem" "11"))
1126        (eq_attr "size" "2"))
1127   "cf_ib2+cfv12_pea_11")
1128
1129 (define_insn_reservation "cfv12_pea_11_3" 1
1130   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1131                  (eq_attr "type" "pea"))
1132             (eq_attr "op_mem" "11"))
1133        (eq_attr "size" "3"))
1134   "cf_ib3+cfv12_pea_11")
1135
1136 (define_insn_reservation "cfv3_pea_11_1" 1
1137   (and (and (and (eq_attr "cpu" "cfv3")
1138                  (eq_attr "type" "pea"))
1139             (eq_attr "op_mem" "11"))
1140        (eq_attr "size" "1"))
1141   "cf_ib1+cfv3_pea_11")
1142
1143 (define_insn_reservation "cfv3_pea_11_2" 1
1144   (and (and (and (eq_attr "cpu" "cfv3")
1145                  (eq_attr "type" "pea"))
1146             (eq_attr "op_mem" "11"))
1147        (eq_attr "size" "2"))
1148   "cf_ib2+cfv3_pea_11")
1149
1150 (define_insn_reservation "cfv3_pea_11_3" 1
1151   (and (and (and (eq_attr "cpu" "cfv3")
1152                  (eq_attr "type" "pea"))
1153             (eq_attr "op_mem" "11"))
1154        (eq_attr "size" "3"))
1155   "cf_ib3+cfv3_pea_11")
1156
1157 (define_insn_reservation "cfv12_pea_i1_2" 2
1158   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1159                  (eq_attr "type" "pea"))
1160             (eq_attr "op_mem" "i1"))
1161        (eq_attr "size" "1,2"))
1162   "cf_ib2+cfv12_pea_i1")
1163
1164 (define_insn_reservation "cfv12_pea_i1_3" 2
1165   (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1166                  (eq_attr "type" "pea"))
1167             (eq_attr "op_mem" "i1"))
1168        (eq_attr "size" "3"))
1169   "cf_ib3+cfv12_pea_i1")
1170
1171 (define_insn_reservation "cfv3_pea_i1_2" 2
1172   (and (and (and (eq_attr "cpu" "cfv3")
1173                  (eq_attr "type" "pea"))
1174             (eq_attr "op_mem" "i1"))
1175        (eq_attr "size" "1,2"))
1176   "cf_ib2+cfv3_pea_i1")
1177
1178 (define_insn_reservation "cfv3_pea_i1_3" 2
1179   (and (and (and (eq_attr "cpu" "cfv3")
1180                  (eq_attr "type" "pea"))
1181             (eq_attr "op_mem" "i1"))
1182        (eq_attr "size" "3"))
1183   "cf_ib3+cfv3_pea_i1")
1184
1185 (define_insn_reservation "cfv123_mul_l_00_1" 18
1186   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1187                       (eq_attr "mac" "no"))
1188                  (eq_attr "type" "mul_l"))
1189             (eq_attr "op_mem" "00,01,0i"))
1190        (eq_attr "size" "1"))
1191   "cf_ib1+cfv123_mul_l_00")
1192
1193 (define_insn_reservation "cfv123_mul_l_00_2" 18
1194   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1195                       (eq_attr "mac" "no"))
1196                  (eq_attr "type" "mul_l"))
1197             (eq_attr "op_mem" "00,01,0i"))
1198        (eq_attr "size" "2"))
1199   "cf_ib2+cfv123_mul_l_00")
1200
1201 (define_insn_reservation "cfv123_mul_l_00_3" 18
1202   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1203                       (eq_attr "mac" "no"))
1204                  (eq_attr "type" "mul_l"))
1205             (eq_attr "op_mem" "00,01,0i"))
1206        (eq_attr "size" "3"))
1207   "cf_ib3+cfv123_mul_l_00")
1208
1209 (define_insn_reservation "cfv123_mul_w_00_1" 9
1210   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1211                       (eq_attr "mac" "no"))
1212                  (eq_attr "type" "mul_w"))
1213             (eq_attr "op_mem" "00,01,0i"))
1214        (eq_attr "size" "1"))
1215   "cf_ib1+cfv123_mul_w_00")
1216
1217 (define_insn_reservation "cfv123_mul_w_00_2" 9
1218   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1219                       (eq_attr "mac" "no"))
1220                  (eq_attr "type" "mul_w"))
1221             (eq_attr "op_mem" "00,01,0i"))
1222        (eq_attr "size" "2"))
1223   "cf_ib2+cfv123_mul_w_00")
1224
1225 (define_insn_reservation "cfv123_mul_w_00_3" 9
1226   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1227                       (eq_attr "mac" "no"))
1228                  (eq_attr "type" "mul_w"))
1229             (eq_attr "op_mem" "00,01,0i"))
1230        (eq_attr "size" "3"))
1231   "cf_ib3+cfv123_mul_w_00")
1232
1233 (define_insn_reservation "cfv12_mul_l_10_1" 20
1234   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1235                       (eq_attr "mac" "no"))
1236                  (eq_attr "type" "mul_l"))
1237             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1238        (eq_attr "size" "1"))
1239   "cf_ib1+cfv12_mul_l_10")
1240
1241 (define_insn_reservation "cfv12_mul_l_10_2" 20
1242   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1243                       (eq_attr "mac" "no"))
1244                  (eq_attr "type" "mul_l"))
1245             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1246        (eq_attr "size" "2"))
1247   "cf_ib2+cfv12_mul_l_10")
1248
1249 (define_insn_reservation "cfv12_mul_l_10_3" 20
1250   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1251                       (eq_attr "mac" "no"))
1252                  (eq_attr "type" "mul_l"))
1253             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1254        (eq_attr "size" "3"))
1255   "cf_ib3+cfv12_mul_l_10")
1256
1257 (define_insn_reservation "cfv3_mul_l_10_1" 21
1258   (and (and (and (and (eq_attr "cpu" "cfv3")
1259                       (eq_attr "mac" "no"))
1260                  (eq_attr "type" "mul_l"))
1261             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1262        (eq_attr "size" "1"))
1263   "cf_ib1+cfv3_mul_l_10")
1264
1265 (define_insn_reservation "cfv3_mul_l_10_2" 21
1266   (and (and (and (and (eq_attr "cpu" "cfv3")
1267                       (eq_attr "mac" "no"))
1268                  (eq_attr "type" "mul_l"))
1269             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1270        (eq_attr "size" "2"))
1271   "cf_ib2+cfv3_mul_l_10")
1272
1273 (define_insn_reservation "cfv3_mul_l_10_3" 21
1274   (and (and (and (and (eq_attr "cpu" "cfv3")
1275                       (eq_attr "mac" "no"))
1276                  (eq_attr "type" "mul_l"))
1277             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1278        (eq_attr "size" "3"))
1279   "cf_ib3+cfv3_mul_l_10")
1280
1281 (define_insn_reservation "cfv12_mul_w_10_1" 11
1282   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1283                       (eq_attr "mac" "no"))
1284                  (eq_attr "type" "mul_w"))
1285             (eq_attr "op_mem" "10,11,1i"))
1286        (eq_attr "size" "1"))
1287   "cf_ib1+cfv12_mul_w_10")
1288
1289 (define_insn_reservation "cfv12_mul_w_10_2" 11
1290   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1291                       (eq_attr "mac" "no"))
1292                  (eq_attr "type" "mul_w"))
1293             (eq_attr "op_mem" "10,11,1i"))
1294        (eq_attr "size" "2"))
1295   "cf_ib2+cfv12_mul_w_10")
1296
1297 (define_insn_reservation "cfv12_mul_w_10_3" 11
1298   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1299                       (eq_attr "mac" "no"))
1300                  (eq_attr "type" "mul_w"))
1301             (eq_attr "op_mem" "10,11,1i"))
1302        (eq_attr "size" "3"))
1303   "cf_ib3+cfv12_mul_w_10")
1304
1305 (define_insn_reservation "cfv3_mul_w_10_1" 12
1306   (and (and (and (and (eq_attr "cpu" "cfv3")
1307                       (eq_attr "mac" "no"))
1308                  (eq_attr "type" "mul_w"))
1309             (eq_attr "op_mem" "10,11,1i"))
1310        (eq_attr "size" "1"))
1311   "cf_ib1+cfv3_mul_w_10")
1312
1313 (define_insn_reservation "cfv3_mul_w_10_2" 12
1314   (and (and (and (and (eq_attr "cpu" "cfv3")
1315                       (eq_attr "mac" "no"))
1316                  (eq_attr "type" "mul_w"))
1317             (eq_attr "op_mem" "10,11,1i"))
1318        (eq_attr "size" "2"))
1319   "cf_ib2+cfv3_mul_w_10")
1320
1321 (define_insn_reservation "cfv3_mul_w_10_3" 12
1322   (and (and (and (and (eq_attr "cpu" "cfv3")
1323                       (eq_attr "mac" "no"))
1324                  (eq_attr "type" "mul_w"))
1325             (eq_attr "op_mem" "10,11,1i"))
1326        (eq_attr "size" "3"))
1327   "cf_ib3+cfv3_mul_w_10")
1328
1329 (define_insn_reservation "cfv12_mul_w_i0_2" 12
1330   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1331                       (eq_attr "mac" "no"))
1332                  (eq_attr "type" "mul_w"))
1333             (eq_attr "op_mem" "i0,i1"))
1334        (eq_attr "size" "1,2"))
1335   "cf_ib2+cfv12_mul_w_i0")
1336
1337 (define_insn_reservation "cfv12_mul_w_i0_3" 12
1338   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1339                       (eq_attr "mac" "no"))
1340                  (eq_attr "type" "mul_w"))
1341             (eq_attr "op_mem" "i0,i1"))
1342        (eq_attr "size" "3"))
1343   "cf_ib3+cfv12_mul_w_i0")
1344
1345 (define_insn_reservation "cfv3_mul_w_i0_2" 13
1346   (and (and (and (and (eq_attr "cpu" "cfv3")
1347                       (eq_attr "mac" "no"))
1348                  (eq_attr "type" "mul_w"))
1349             (eq_attr "op_mem" "i0,i1"))
1350        (eq_attr "size" "1,2"))
1351   "cf_ib2+cfv3_mul_w_i0")
1352
1353 (define_insn_reservation "cfv3_mul_w_i0_3" 13
1354   (and (and (and (and (eq_attr "cpu" "cfv3")
1355                       (eq_attr "mac" "no"))
1356                  (eq_attr "type" "mul_w"))
1357             (eq_attr "op_mem" "i0,i1"))
1358        (eq_attr "size" "3"))
1359   "cf_ib3+cfv3_mul_w_i0")
1360
1361 (define_insn_reservation "cfv123_mac_l_00_1" 5
1362   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1363                       (eq_attr "mac" "cf_mac"))
1364                  (eq_attr "type" "mul_l"))
1365             (eq_attr "op_mem" "00,01,0i"))
1366        (eq_attr "size" "1"))
1367   "cf_ib1+cfv123_mac_l_00")
1368
1369 (define_insn_reservation "cfv123_mac_l_00_2" 5
1370   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1371                       (eq_attr "mac" "cf_mac"))
1372                  (eq_attr "type" "mul_l"))
1373             (eq_attr "op_mem" "00,01,0i"))
1374        (eq_attr "size" "2"))
1375   "cf_ib2+cfv123_mac_l_00")
1376
1377 (define_insn_reservation "cfv123_mac_l_00_3" 5
1378   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1379                       (eq_attr "mac" "cf_mac"))
1380                  (eq_attr "type" "mul_l"))
1381             (eq_attr "op_mem" "00,01,0i"))
1382        (eq_attr "size" "3"))
1383   "cf_ib3+cfv123_mac_l_00")
1384
1385 (define_insn_reservation "cfv123_mac_w_00_1" 3
1386   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1387                       (eq_attr "mac" "cf_mac"))
1388                  (eq_attr "type" "mul_w"))
1389             (eq_attr "op_mem" "00,01,0i"))
1390        (eq_attr "size" "1"))
1391   "cf_ib1+cfv123_mac_w_00")
1392
1393 (define_insn_reservation "cfv123_mac_w_00_2" 3
1394   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1395                       (eq_attr "mac" "cf_mac"))
1396                  (eq_attr "type" "mul_w"))
1397             (eq_attr "op_mem" "00,01,0i"))
1398        (eq_attr "size" "2"))
1399   "cf_ib2+cfv123_mac_w_00")
1400
1401 (define_insn_reservation "cfv123_mac_w_00_3" 3
1402   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1403                       (eq_attr "mac" "cf_mac"))
1404                  (eq_attr "type" "mul_w"))
1405             (eq_attr "op_mem" "00,01,0i"))
1406        (eq_attr "size" "3"))
1407   "cf_ib3+cfv123_mac_w_00")
1408
1409 (define_insn_reservation "cfv12_mac_l_10_1" 7
1410   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1411                       (eq_attr "mac" "cf_mac"))
1412                  (eq_attr "type" "mul_l"))
1413             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1414        (eq_attr "size" "1"))
1415   "cf_ib1+cfv12_mac_l_10")
1416
1417 (define_insn_reservation "cfv12_mac_l_10_2" 7
1418   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1419                       (eq_attr "mac" "cf_mac"))
1420                  (eq_attr "type" "mul_l"))
1421             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1422        (eq_attr "size" "2"))
1423   "cf_ib2+cfv12_mac_l_10")
1424
1425 (define_insn_reservation "cfv12_mac_l_10_3" 7
1426   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1427                       (eq_attr "mac" "cf_mac"))
1428                  (eq_attr "type" "mul_l"))
1429             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1430        (eq_attr "size" "3"))
1431   "cf_ib3+cfv12_mac_l_10")
1432
1433 (define_insn_reservation "cfv3_mac_l_10_1" 8
1434   (and (and (and (and (eq_attr "cpu" "cfv3")
1435                       (eq_attr "mac" "cf_mac"))
1436                  (eq_attr "type" "mul_l"))
1437             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1438        (eq_attr "size" "1"))
1439   "cf_ib1+cfv3_mac_l_10")
1440
1441 (define_insn_reservation "cfv3_mac_l_10_2" 8
1442   (and (and (and (and (eq_attr "cpu" "cfv3")
1443                       (eq_attr "mac" "cf_mac"))
1444                  (eq_attr "type" "mul_l"))
1445             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1446        (eq_attr "size" "2"))
1447   "cf_ib2+cfv3_mac_l_10")
1448
1449 (define_insn_reservation "cfv3_mac_l_10_3" 8
1450   (and (and (and (and (eq_attr "cpu" "cfv3")
1451                       (eq_attr "mac" "cf_mac"))
1452                  (eq_attr "type" "mul_l"))
1453             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1454        (eq_attr "size" "3"))
1455   "cf_ib3+cfv3_mac_l_10")
1456
1457 (define_insn_reservation "cfv12_mac_w_10_1" 5
1458   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1459                       (eq_attr "mac" "cf_mac"))
1460                  (eq_attr "type" "mul_w"))
1461             (eq_attr "op_mem" "10,11,1i"))
1462        (eq_attr "size" "1"))
1463   "cf_ib1+cfv12_mac_w_10")
1464
1465 (define_insn_reservation "cfv12_mac_w_10_2" 5
1466   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1467                       (eq_attr "mac" "cf_mac"))
1468                  (eq_attr "type" "mul_w"))
1469             (eq_attr "op_mem" "10,11,1i"))
1470        (eq_attr "size" "2"))
1471   "cf_ib2+cfv12_mac_w_10")
1472
1473 (define_insn_reservation "cfv12_mac_w_10_3" 5
1474   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1475                       (eq_attr "mac" "cf_mac"))
1476                  (eq_attr "type" "mul_w"))
1477             (eq_attr "op_mem" "10,11,1i"))
1478        (eq_attr "size" "3"))
1479   "cf_ib3+cfv12_mac_w_10")
1480
1481 (define_insn_reservation "cfv3_mac_w_10_1" 6
1482   (and (and (and (and (eq_attr "cpu" "cfv3")
1483                       (eq_attr "mac" "cf_mac"))
1484                  (eq_attr "type" "mul_w"))
1485             (eq_attr "op_mem" "10,11,1i"))
1486        (eq_attr "size" "1"))
1487   "cf_ib1+cfv3_mac_w_10")
1488
1489 (define_insn_reservation "cfv3_mac_w_10_2" 6
1490   (and (and (and (and (eq_attr "cpu" "cfv3")
1491                       (eq_attr "mac" "cf_mac"))
1492                  (eq_attr "type" "mul_w"))
1493             (eq_attr "op_mem" "10,11,1i"))
1494        (eq_attr "size" "2"))
1495   "cf_ib2+cfv3_mac_w_10")
1496
1497 (define_insn_reservation "cfv3_mac_w_10_3" 6
1498   (and (and (and (and (eq_attr "cpu" "cfv3")
1499                       (eq_attr "mac" "cf_mac"))
1500                  (eq_attr "type" "mul_w"))
1501             (eq_attr "op_mem" "10,11,1i"))
1502        (eq_attr "size" "3"))
1503   "cf_ib3+cfv3_mac_w_10")
1504
1505 (define_insn_reservation "cfv12_mac_w_i0_2" 6
1506   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1507                       (eq_attr "mac" "cf_mac"))
1508                  (eq_attr "type" "mul_w"))
1509             (eq_attr "op_mem" "i0,i1"))
1510        (eq_attr "size" "1,2"))
1511   "cf_ib2+cfv12_mac_w_i0")
1512
1513 (define_insn_reservation "cfv12_mac_w_i0_3" 6
1514   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1515                       (eq_attr "mac" "cf_mac"))
1516                  (eq_attr "type" "mul_w"))
1517             (eq_attr "op_mem" "i0,i1"))
1518        (eq_attr "size" "3"))
1519   "cf_ib3+cfv12_mac_w_i0")
1520
1521 (define_insn_reservation "cfv3_mac_w_i0_2" 7
1522   (and (and (and (and (eq_attr "cpu" "cfv3")
1523                       (eq_attr "mac" "cf_mac"))
1524                  (eq_attr "type" "mul_w"))
1525             (eq_attr "op_mem" "i0,i1"))
1526        (eq_attr "size" "1,2"))
1527   "cf_ib2+cfv3_mac_w_i0")
1528
1529 (define_insn_reservation "cfv3_mac_w_i0_3" 7
1530   (and (and (and (and (eq_attr "cpu" "cfv3")
1531                       (eq_attr "mac" "cf_mac"))
1532                  (eq_attr "type" "mul_w"))
1533             (eq_attr "op_mem" "i0,i1"))
1534        (eq_attr "size" "3"))
1535   "cf_ib3+cfv3_mac_w_i0")
1536
1537 (define_insn_reservation "cfv123_emac_00_1" 4
1538   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1539                       (eq_attr "mac" "cf_emac"))
1540                  (eq_attr "type" "mul_l,mul_w"))
1541             (eq_attr "op_mem" "00,01,0i"))
1542        (eq_attr "size" "1"))
1543   "cf_ib1+cfv123_emac_00")
1544
1545 (define_insn_reservation "cfv123_emac_00_2" 4
1546   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1547                       (eq_attr "mac" "cf_emac"))
1548                  (eq_attr "type" "mul_l,mul_w"))
1549             (eq_attr "op_mem" "00,01,0i"))
1550        (eq_attr "size" "2"))
1551   "cf_ib2+cfv123_emac_00")
1552
1553 (define_insn_reservation "cfv123_emac_00_3" 4
1554   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1555                       (eq_attr "mac" "cf_emac"))
1556                  (eq_attr "type" "mul_l,mul_w"))
1557             (eq_attr "op_mem" "00,01,0i"))
1558        (eq_attr "size" "3"))
1559   "cf_ib3+cfv123_emac_00")
1560
1561 (define_insn_reservation "cfv12_emac_l_10_1" 6
1562   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1563                       (eq_attr "mac" "cf_emac"))
1564                  (eq_attr "type" "mul_l"))
1565             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1566        (eq_attr "size" "1"))
1567   "cf_ib1+cfv12_emac_10")
1568
1569 (define_insn_reservation "cfv12_emac_l_10_2" 6
1570   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1571                       (eq_attr "mac" "cf_emac"))
1572                  (eq_attr "type" "mul_l"))
1573             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1574        (eq_attr "size" "2"))
1575   "cf_ib2+cfv12_emac_10")
1576
1577 (define_insn_reservation "cfv12_emac_l_10_3" 6
1578   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1579                       (eq_attr "mac" "cf_emac"))
1580                  (eq_attr "type" "mul_l"))
1581             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1582        (eq_attr "size" "3"))
1583   "cf_ib3+cfv12_emac_10")
1584
1585 (define_insn_reservation "cfv3_emac_l_10_1" 7
1586   (and (and (and (and (eq_attr "cpu" "cfv3")
1587                       (eq_attr "mac" "cf_emac"))
1588                  (eq_attr "type" "mul_l"))
1589             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1590        (eq_attr "size" "1"))
1591   "cf_ib1+cfv3_emac_10")
1592
1593 (define_insn_reservation "cfv3_emac_l_10_2" 7
1594   (and (and (and (and (eq_attr "cpu" "cfv3")
1595                       (eq_attr "mac" "cf_emac"))
1596                  (eq_attr "type" "mul_l"))
1597             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1598        (eq_attr "size" "2"))
1599   "cf_ib2+cfv3_emac_10")
1600
1601 (define_insn_reservation "cfv3_emac_l_10_3" 7
1602   (and (and (and (and (eq_attr "cpu" "cfv3")
1603                       (eq_attr "mac" "cf_emac"))
1604                  (eq_attr "type" "mul_l"))
1605             (eq_attr "op_mem" "10,i0,i1,11,1i"))
1606        (eq_attr "size" "3"))
1607   "cf_ib3+cfv3_emac_10")
1608
1609 (define_insn_reservation "cfv12_emac_w_10_1" 6
1610   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1611                       (eq_attr "mac" "cf_emac"))
1612                  (eq_attr "type" "mul_w"))
1613             (eq_attr "op_mem" "10,11,1i"))
1614        (eq_attr "size" "1"))
1615   "cf_ib1+cfv12_emac_10")
1616
1617 (define_insn_reservation "cfv12_emac_w_10_2" 6
1618   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1619                       (eq_attr "mac" "cf_emac"))
1620                  (eq_attr "type" "mul_w"))
1621             (eq_attr "op_mem" "10,11,1i"))
1622        (eq_attr "size" "2"))
1623   "cf_ib2+cfv12_emac_10")
1624
1625 (define_insn_reservation "cfv12_emac_w_10_3" 6
1626   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1627                       (eq_attr "mac" "cf_emac"))
1628                  (eq_attr "type" "mul_w"))
1629             (eq_attr "op_mem" "10,11,1i"))
1630        (eq_attr "size" "3"))
1631   "cf_ib3+cfv12_emac_10")
1632
1633 (define_insn_reservation "cfv3_emac_w_10_1" 7
1634   (and (and (and (and (eq_attr "cpu" "cfv3")
1635                       (eq_attr "mac" "cf_emac"))
1636                  (eq_attr "type" "mul_w"))
1637             (eq_attr "op_mem" "10,11,1i"))
1638        (eq_attr "size" "1"))
1639   "cf_ib1+cfv3_emac_10")
1640
1641 (define_insn_reservation "cfv3_emac_w_10_2" 7
1642   (and (and (and (and (eq_attr "cpu" "cfv3")
1643                       (eq_attr "mac" "cf_emac"))
1644                  (eq_attr "type" "mul_w"))
1645             (eq_attr "op_mem" "10,11,1i"))
1646        (eq_attr "size" "2"))
1647   "cf_ib2+cfv3_emac_10")
1648
1649 (define_insn_reservation "cfv3_emac_w_10_3" 7
1650   (and (and (and (and (eq_attr "cpu" "cfv3")
1651                       (eq_attr "mac" "cf_emac"))
1652                  (eq_attr "type" "mul_w"))
1653             (eq_attr "op_mem" "10,11,1i"))
1654        (eq_attr "size" "3"))
1655   "cf_ib3+cfv3_emac_10")
1656
1657 (define_insn_reservation "cfv12_emac_w_i0_2" 7
1658   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1659                       (eq_attr "mac" "cf_emac"))
1660                  (eq_attr "type" "mul_w"))
1661             (eq_attr "op_mem" "i0,i1"))
1662        (eq_attr "size" "1,2"))
1663   "cf_ib2+cfv12_emac_w_i0")
1664
1665 (define_insn_reservation "cfv12_emac_w_i0_3" 7
1666   (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1667                       (eq_attr "mac" "cf_emac"))
1668                  (eq_attr "type" "mul_w"))
1669             (eq_attr "op_mem" "i0,i1"))
1670        (eq_attr "size" "3"))
1671   "cf_ib3+cfv12_emac_w_i0")
1672
1673 (define_insn_reservation "cfv3_emac_w_i0_2" 8
1674   (and (and (and (and (eq_attr "cpu" "cfv3")
1675                       (eq_attr "mac" "cf_emac"))
1676                  (eq_attr "type" "mul_w"))
1677             (eq_attr "op_mem" "i0,i1"))
1678        (eq_attr "size" "1,2"))
1679   "cf_ib2+cfv3_emac_w_i0")
1680
1681 (define_insn_reservation "cfv3_emac_w_i0_3" 8
1682   (and (and (and (and (eq_attr "cpu" "cfv3")
1683                       (eq_attr "mac" "cf_emac"))
1684                  (eq_attr "type" "mul_w"))
1685             (eq_attr "op_mem" "i0,i1"))
1686        (eq_attr "size" "3"))
1687   "cf_ib3+cfv3_emac_w_i0")
1688
1689 (define_insn_reservation "cfv12_rts" 5
1690   (and (eq_attr "cpu" "cfv1,cfv2")
1691        (eq_attr "type" "rts"))
1692   "cf_ib1+cfv12_rts")
1693
1694 (define_insn_reservation "cfv3_rts" 8
1695   (and (eq_attr "cpu" "cfv3")
1696        (eq_attr "type" "rts"))
1697   "cf_ib1+cfv3_rts")
1698
1699 (define_insn_reservation "cfv12_call_1" 3
1700   (and (and (eq_attr "cpu" "cfv1,cfv2")
1701             (eq_attr "type" "bsr,jsr"))
1702        (eq_attr "size" "1"))
1703   "cf_ib1+cfv12_call")
1704
1705 (define_insn_reservation "cfv12_call_2" 3
1706   (and (and (eq_attr "cpu" "cfv1,cfv2")
1707             (eq_attr "type" "bsr,jsr"))
1708        (eq_attr "size" "2"))
1709   "cf_ib2+cfv12_call")
1710
1711 (define_insn_reservation "cfv12_call_3" 3
1712   (and (and (eq_attr "cpu" "cfv1,cfv2")
1713             (eq_attr "type" "bsr,jsr"))
1714        (eq_attr "size" "3"))
1715   "cf_ib3+cfv12_call")
1716
1717 (define_insn_reservation "cfv3_call_1" 1
1718   (and (and (eq_attr "cpu" "cfv3")
1719             (eq_attr "type" "bsr,jsr"))
1720        (eq_attr "size" "1"))
1721   "cf_ib1+cfv3_call")
1722
1723 (define_insn_reservation "cfv3_call_2" 1
1724   (and (and (eq_attr "cpu" "cfv3")
1725             (eq_attr "type" "bsr,jsr"))
1726        (eq_attr "size" "2"))
1727   "cf_ib2+cfv3_call")
1728
1729 (define_insn_reservation "cfv3_call_3" 1
1730   (and (and (eq_attr "cpu" "cfv3")
1731             (eq_attr "type" "bsr,jsr"))
1732        (eq_attr "size" "3"))
1733   "cf_ib3+cfv3_call")
1734
1735 (define_insn_reservation "cfv12_bcc_1" 2
1736   (and (and (eq_attr "cpu" "cfv1,cfv2")
1737             (eq_attr "type" "bcc"))
1738        (eq_attr "size" "1"))
1739   "cf_ib1+cfv12_bcc")
1740
1741 (define_insn_reservation "cfv12_bcc_2" 2
1742   (and (and (eq_attr "cpu" "cfv1,cfv2")
1743             (eq_attr "type" "bcc"))
1744        (eq_attr "size" "2"))
1745   "cf_ib2+cfv12_bcc")
1746
1747 (define_insn_reservation "cfv12_bcc_3" 2
1748   (and (and (eq_attr "cpu" "cfv1,cfv2")
1749             (eq_attr "type" "bcc"))
1750        (eq_attr "size" "3"))
1751   "cf_ib3+cfv12_bcc")
1752
1753 (define_insn_reservation "cfv3_bcc_1" 1
1754   (and (and (eq_attr "cpu" "cfv3")
1755             (eq_attr "type" "bcc"))
1756        (eq_attr "size" "1"))
1757   "cf_ib1+cfv3_bcc")
1758
1759 (define_insn_reservation "cfv3_bcc_2" 1
1760   (and (and (eq_attr "cpu" "cfv3")
1761             (eq_attr "type" "bcc"))
1762        (eq_attr "size" "2"))
1763   "cf_ib2+cfv3_bcc")
1764
1765 (define_insn_reservation "cfv3_bcc_3" 1
1766   (and (and (eq_attr "cpu" "cfv3")
1767             (eq_attr "type" "bcc"))
1768        (eq_attr "size" "3"))
1769   "cf_ib3+cfv3_bcc")
1770
1771 (define_insn_reservation "cfv12_bra_1" 2
1772   (and (and (eq_attr "cpu" "cfv1,cfv2")
1773             (eq_attr "type" "bra"))
1774        (eq_attr "size" "1"))
1775   "cf_ib1+cfv12_bra")
1776
1777 (define_insn_reservation "cfv12_bra_2" 2
1778   (and (and (eq_attr "cpu" "cfv1,cfv2")
1779             (eq_attr "type" "bra"))
1780        (eq_attr "size" "2"))
1781   "cf_ib2+cfv12_bra")
1782
1783 (define_insn_reservation "cfv12_bra_3" 2
1784   (and (and (eq_attr "cpu" "cfv1,cfv2")
1785             (eq_attr "type" "bra"))
1786        (eq_attr "size" "3"))
1787   "cf_ib3+cfv12_bra")
1788
1789 (define_insn_reservation "cfv3_bra_1" 1
1790   (and (and (eq_attr "cpu" "cfv3")
1791             (eq_attr "type" "bra"))
1792        (eq_attr "size" "1"))
1793   "cf_ib1+cfv3_bra")
1794
1795 (define_insn_reservation "cfv3_bra_2" 1
1796   (and (and (eq_attr "cpu" "cfv3")
1797             (eq_attr "type" "bra"))
1798        (eq_attr "size" "2"))
1799   "cf_ib2+cfv3_bra")
1800
1801 (define_insn_reservation "cfv3_bra_3" 1
1802   (and (and (eq_attr "cpu" "cfv3")
1803             (eq_attr "type" "bra"))
1804        (eq_attr "size" "3"))
1805   "cf_ib3+cfv3_bra")
1806
1807 (define_insn_reservation "cfv12_jmp_1" 3
1808   (and (and (eq_attr "cpu" "cfv1,cfv2")
1809             (eq_attr "type" "jmp"))
1810        (eq_attr "size" "1"))
1811   "cf_ib1+cfv12_jmp")
1812
1813 (define_insn_reservation "cfv12_jmp_2" 3
1814   (and (and (eq_attr "cpu" "cfv1,cfv2")
1815             (eq_attr "type" "jmp"))
1816        (eq_attr "size" "2"))
1817   "cf_ib2+cfv12_jmp")
1818
1819 (define_insn_reservation "cfv12_jmp_3" 3
1820   (and (and (eq_attr "cpu" "cfv1,cfv2")
1821             (eq_attr "type" "jmp"))
1822        (eq_attr "size" "3"))
1823   "cf_ib3+cfv12_jmp")
1824
1825 (define_insn_reservation "cfv3_jmp_1" 5
1826   (and (and (eq_attr "cpu" "cfv3")
1827             (eq_attr "type" "jmp"))
1828        (eq_attr "size" "1"))
1829   "cf_ib1+cfv3_jmp")
1830
1831 (define_insn_reservation "cfv3_jmp_2" 5
1832   (and (and (eq_attr "cpu" "cfv3")
1833             (eq_attr "type" "jmp"))
1834        (eq_attr "size" "2"))
1835   "cf_ib2+cfv3_jmp")
1836
1837 (define_insn_reservation "cfv3_jmp_3" 5
1838   (and (and (eq_attr "cpu" "cfv3")
1839             (eq_attr "type" "jmp"))
1840        (eq_attr "size" "3"))
1841   "cf_ib3+cfv3_jmp")
1842
1843 (define_insn_reservation "cfv12_unlk" 2
1844   (and (eq_attr "cpu" "cfv1,cfv2")
1845        (eq_attr "type" "unlk"))
1846   "cf_ib1+cfv12_alu_10")
1847
1848 (define_insn_reservation "cfv3_unlk" 3
1849   (and (eq_attr "cpu" "cfv3")
1850        (eq_attr "type" "unlk"))
1851   "cf_ib1+cfv3_alu_10")
1852
1853 ;; Dummy reservation for instructions that are not handled.
1854 (define_insn_reservation "cfv123_guess" 3
1855   (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1856        (eq_attr "type" "falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
1857                         div_w,div_l,link,mvsz,nop,trap,unknown"))
1858   "cf_ib3+cfv123_guess+cf_dsoc+cf_agex+cf_mem")
1859
1860 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1861 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1862 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1863
1864 ;; Below is pipeline description of ColdFire V4 core.
1865 ;; It is substantially different from the description of V1, V2 or V3 cores,
1866 ;; primarily due to no need to model the instruction buffer.
1867 ;;
1868 ;; V4 pipeline model uses a completely separate set of cpu units.
1869
1870 ;; Operand Execution Pipeline.
1871 (define_automaton "cfv4_oep")
1872
1873 (define_cpu_unit "cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da"
1874   "cfv4_oep")
1875
1876 ;; This automaton is used to support CFv4 dual-issue.
1877 (define_automaton "cfv4_ds")
1878
1879 ;; V4 has 3 cases of dual-issue.
1880 ;; After issuing a cfv4_pOEPx instruction, it'll be possible to issue
1881 ;; a cfv4_sOEPx instruction on the same cycle (see final_presence_sets below).
1882 (define_cpu_unit "cfv4_pOEP1,cfv4_sOEP1,
1883                   cfv4_pOEP2,cfv4_sOEP2,
1884                   cfv4_pOEP3,cfv4_sOEP3" "cfv4_ds")
1885
1886 (final_presence_set "cfv4_sOEP1" "cfv4_pOEP1")
1887 (final_presence_set "cfv4_sOEP2" "cfv4_pOEP2")
1888 (final_presence_set "cfv4_sOEP3" "cfv4_pOEP3")
1889
1890 ;; Reservation for instructions that don't allow dual-issue.
1891 (define_reservation "cfv4_ds" "cfv4_pOEP1+cfv4_sOEP1+
1892                                cfv4_pOEP2+cfv4_sOEP2+
1893                                cfv4_pOEP3+cfv4_sOEP3")
1894
1895 ;; Memory access resource.
1896 (define_automaton "cfv4_mem")
1897
1898 (define_cpu_unit "cfv4_mem" "cfv4_mem")
1899
1900 ;; EMAC.
1901 (define_automaton "cfv4_emac")
1902
1903 (define_cpu_unit "cfv4_emac" "cfv4_emac")
1904
1905 ;; FPU.
1906 (define_automaton "cfv4_fp")
1907
1908 (define_cpu_unit "cfv4_fp" "cfv4_fp")
1909
1910 ;; Automaton for unknown instruction.
1911 (define_automaton "cfv4_guess")
1912
1913 (define_query_cpu_unit "cfv4_guess" "cfv4_guess")
1914
1915 ;; This bypass allows 1st case of dual-issue.
1916 (define_bypass 0 "cfv4_00_oag_pOEP1,cfv4_10_pOEP1,cfv4_i0_pOEP1"
1917   "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_pOEP1,
1918    cfv4_00_oag_moveql,cfv4_00_ex_sOEP13")
1919
1920 ;; The following bypasses decrease the latency of producers if it modifies
1921 ;; a target register in the EX stage and the consumer also uses
1922 ;; that register in the EX stage.
1923 (define_bypass 1 "cfv4_00_ex" "cfv4_00_ex,cfv4_00_ex_sOEP13")
1924 (define_bypass 1 "cfv4_00_ex" "cfv4_10,cfv4_10_pOEP1,cfv4_i0,cfv4_i0_pOEP1"
1925   "!m68k_sched_address_bypass_p")
1926
1927 ;; Indexed loads with scale factors 2 and 4 require an update of the index
1928 ;; register in the register file.  Considering that the index register is
1929 ;; only needed at the second cycle of address generation, we get
1930 ;; a latency of 4.
1931 ;; Producers for indexed loads with scale factor 1 should have
1932 ;; a latency of 3.  Since we're only allowed one bypass, we handle it
1933 ;; in the adjust_cost hook.
1934 (define_bypass 4
1935   "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_lea,cfv4_00_oag_pOEP1,
1936    cfv4_00_oag_moveql"
1937   "cfv4_i0,cfv4_i0_pOEP1"
1938   "m68k_sched_indexed_address_bypass_p")
1939
1940 ;; First part of cfv4_00.
1941 ;; If issued in pairs with cfv4_movel_?0, the cost should be increased.
1942 ;; ??? Is it possible that combined cfv4_movel_00 and cfv4_oag_00 instructions
1943 ;; have longer latency than the two instructions emitted sequentially?
1944 ;; Due to register renaming, the result of the sequence would be available
1945 ;; after 3 cycles, instead of 4 for combined instruction?
1946 (define_insn_reservation "cfv4_00_oag" 1
1947   (and (and (eq_attr "cpu" "cfv4")
1948             (eq_attr "type" "alu_l,aluq_l,clr_l,cmp_l,mov3q_l,neg_l"))
1949        (eq_attr "op_mem" "00"))
1950   "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
1951
1952 (define_insn_reservation "cfv4_00_oag_pOEP3_sOEP12" 1
1953   (and (and (eq_attr "cpu" "cfv4")
1954             (eq_attr "type" "move_l,mov3q_l,clr_l"))
1955        (and (eq_attr "op_mem" "00")
1956             (and (eq_attr "opx_type" "Rn")
1957                  (eq_attr "opy_type" "none,imm_q,imm_w,imm_l"))))
1958   "cfv4_sOEP1|cfv4_sOEP2|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
1959
1960 (define_insn_reservation "cfv4_00_oag_lea" 1
1961   (and (eq_attr "cpu" "cfv4")
1962        (eq_attr "type" "lea"))
1963   "cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
1964
1965 (define_insn_reservation "cfv4_00_oag_pOEP1" 1
1966   (and (and (eq_attr "cpu" "cfv4")
1967             (eq_attr "type" "move_l,mov3q_l,clr_l"))
1968        (and (eq_attr "op_mem" "00")
1969             (ior (eq_attr "opx_type" "!Rn")
1970                  (eq_attr "opy_type" "!none,imm_q,imm_w,imm_l"))))
1971   "cfv4_sOEP1|(cfv4_pOEP1,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
1972
1973 (define_insn_reservation "cfv4_00_oag_moveql" 1
1974   (and (and (eq_attr "cpu" "cfv4")
1975             (eq_attr "type" "moveq_l"))
1976        (eq_attr "op_mem" "00"))
1977   "cfv4_sOEP1|cfv4_sOEP2|cfv4_sOEP3|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
1978
1979 ;; Second part of cfv4_00.
1980 ;; Latency is either 1 or 4 depending on which stage the consumer
1981 ;; will need the data.
1982
1983 (define_insn_reservation "cfv4_00_ex" 4
1984   (and (and (eq_attr "cpu" "cfv4")
1985             (eq_attr "type" "bitr,bitrw,clr,cmp,move,mvsz,scc,tst"))
1986        (eq_attr "op_mem" "00"))
1987   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
1988
1989 (define_insn_reservation "cfv4_00_ex_sOEP13" 4
1990   (and (and (eq_attr "cpu" "cfv4")
1991             (eq_attr "type" "alux_l,ext,shift,tst_l"))
1992        (eq_attr "op_mem" "00"))
1993   "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
1994
1995 ;; Several types mentioned in this reservation (e.g., ext and shift) don't
1996 ;; support implicit load.  But we handle them anyway due to first scheduling
1997 ;; pass, which handles non-strict rtl.
1998 ;;
1999 ;; Latency is either 1 or 4 depending in which stage the consumer
2000 ;; will need the data.
2001 (define_insn_reservation "cfv4_10" 4
2002   (and (and (eq_attr "cpu" "cfv4")
2003             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2004                              clr,clr_l,cmp,cmp_l,ext,
2005                              mov3q_l,move,moveq_l,mvsz,neg_l,
2006                              shift,tst,tst_l"))
2007        (eq_attr "op_mem" "10"))
2008   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
2009
2010 ;; Specialization of cfv4_10.
2011 ;; move.l has OC2-to-DS forwarding path, that saves one cycle of latency.
2012 (define_insn_reservation "cfv4_10_pOEP1" 3
2013   (and (and (eq_attr "cpu" "cfv4")
2014             (eq_attr "type" "move_l"))
2015        (eq_attr "op_mem" "10"))
2016   "cfv4_pOEP1,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
2017
2018 ;; Same here.  But +1 to latency due to longer OAG.
2019 (define_insn_reservation "cfv4_i0" 5
2020   (and (and (eq_attr "cpu" "cfv4")
2021             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2022                              clr,clr_l,cmp,cmp_l,ext,
2023                              mov3q_l,move,moveq_l,mvsz,neg_l,
2024                              shift,tst,tst_l"))
2025        (eq_attr "op_mem" "i0"))
2026   "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
2027
2028 ;; ??? Does indexed load trigger dual-issue?
2029 ;; ??? Does OC2-to-DS forwarding path saves a cycle?
2030 (define_insn_reservation "cfv4_i0_pOEP1" 4
2031   (and (and (eq_attr "cpu" "cfv4")
2032             (eq_attr "type" "move_l"))
2033        (eq_attr "op_mem" "i0"))
2034   "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
2035
2036 ;; This reservation is for moves and clr.  Arithmetic instructions
2037 ;; don't write to memory unless they also read from it.
2038 ;; But, before reload we can have all sorts of things.
2039 ;; With cfv4_pOEP2 allow dual-issue for type 2 cases.
2040 (define_insn_reservation "cfv4_01" 1
2041   (and (and (eq_attr "cpu" "cfv4")
2042             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2043                              clr,clr_l,cmp,cmp_l,ext,
2044                              mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
2045                              shift"))
2046        (eq_attr "op_mem" "01"))
2047   "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2048
2049 ;; ??? Does indexed store trigger dual-issue?
2050 (define_insn_reservation "cfv4_0i" 2
2051   (and (and (eq_attr "cpu" "cfv4")
2052             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2053                              clr,clr_l,cmp,cmp_l,ext,
2054                              mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
2055                              shift"))
2056        (eq_attr "op_mem" "0i"))
2057   "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2058
2059 (define_insn_reservation "cfv4_11" 1
2060   (and (and (eq_attr "cpu" "cfv4")
2061             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2062                              clr,clr_l,cmp,cmp_l,ext,
2063                              mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
2064                              shift"))
2065        (eq_attr "op_mem" "11"))
2066   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2067
2068 ;; Latency is 2 due to long OAG stage.
2069 (define_insn_reservation "cfv4_i1" 2
2070   (and (and (eq_attr "cpu" "cfv4")
2071             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2072                              clr,clr_l,cmp,cmp_l,ext,
2073                              mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
2074                              shift"))
2075        (eq_attr "op_mem" "i1"))
2076   "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2077
2078 ;; This one is the same as cfv4_i1.
2079 ;; ??? Should it be different?
2080 (define_insn_reservation "cfv4_1i" 2
2081   (and (and (eq_attr "cpu" "cfv4")
2082             (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
2083                              clr,clr_l,cmp,cmp_l,ext,
2084                              mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
2085                              shift"))
2086        (eq_attr "op_mem" "1i"))
2087   "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2088
2089 ;; ??? Does pea indeed support case 2 of dual-issue?
2090 (define_insn_reservation "cfv4_11_pea" 1
2091   (and (and (eq_attr "cpu" "cfv4")
2092             (eq_attr "type" "pea"))
2093        (eq_attr "op_mem" "11,00,01,0i,10"))
2094   "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2095
2096 ;; ??? Does pea indeed support case 2 of dual-issue?
2097 ;; ??? Does indexed store trigger dual-issue?
2098 (define_insn_reservation "cfv4_i1_pea" 1
2099   (and (and (eq_attr "cpu" "cfv4")
2100             (eq_attr "type" "pea"))
2101        (eq_attr "op_mem" "i1,1i"))
2102   "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
2103
2104 (define_insn_reservation "cfv4_link" 2
2105   (and (eq_attr "cpu" "cfv4")
2106        (eq_attr "type" "link"))
2107   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_ex,cfv4_da,cfv4_mem")
2108
2109 (define_insn_reservation "cfv4_unlink" 2
2110   (and (eq_attr "cpu" "cfv4")
2111        (eq_attr "type" "unlk"))
2112   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
2113
2114 (define_insn_reservation "cfv4_divw_00" 20
2115   (and (and (eq_attr "cpu" "cfv4")
2116             (eq_attr "type" "div_w"))
2117        (eq_attr "op_mem" "00,01,0i"))
2118   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*15")
2119
2120 (define_insn_reservation "cfv4_divw_10" 20
2121   (and (and (eq_attr "cpu" "cfv4")
2122             (eq_attr "type" "div_w"))
2123        (eq_attr "op_mem" "10,11,1i"))
2124   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15")
2125
2126 (define_insn_reservation "cfv4_divw_i0" 21
2127   (and (and (eq_attr "cpu" "cfv4")
2128             (eq_attr "type" "div_w"))
2129        (eq_attr "op_mem" "i0,i1"))
2130   "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15")
2131
2132 (define_insn_reservation "cfv4_divl_00" 35
2133   (and (and (eq_attr "cpu" "cfv4")
2134             (eq_attr "type" "div_l"))
2135        (eq_attr "op_mem" "00,01,0i"))
2136   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*30")
2137
2138 (define_insn_reservation "cfv4_divl_10" 35
2139   (and (and (eq_attr "cpu" "cfv4")
2140             (eq_attr "type" "div_l"))
2141        (eq_attr "op_mem" "10,11,1i,i0,i1"))
2142   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*30")
2143
2144 (define_insn_reservation "cfv4_emac_mul_00" 7
2145   (and (and (eq_attr "cpu" "cfv4")
2146             (eq_attr "type" "mul_w,mul_l"))
2147        (eq_attr "op_mem" "00,01,0i"))
2148   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_emac")
2149
2150 (define_insn_reservation "cfv4_emac_mul_10" 7
2151   (and (and (eq_attr "cpu" "cfv4")
2152             (eq_attr "type" "mul_w,mul_l"))
2153        (eq_attr "op_mem" "10,11,1i"))
2154   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac")
2155
2156 (define_insn_reservation "cfv4_emac_mul_i0" 8
2157   (and (and (eq_attr "cpu" "cfv4")
2158             (eq_attr "type" "mul_w,mul_l"))
2159        (eq_attr "op_mem" "i0,i1"))
2160   "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac")
2161
2162 (define_insn_reservation "cfv4_falu_00" 7
2163   (and (and (eq_attr "cpu" "cfv4")
2164             (eq_attr "type" "falu,fcmp,fmul"))
2165        (eq_attr "op_mem" "00,01,0i"))
2166   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp")
2167
2168 (define_insn_reservation "cfv4_falu_10" 7
2169   (and (and (eq_attr "cpu" "cfv4")
2170             (eq_attr "type" "falu,fcmp,fmul"))
2171        (eq_attr "op_mem" "10,i0,11,1i,i1"))
2172   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp")
2173
2174 (define_insn_reservation "cfv4_fneg_00" 4
2175   (and (and (eq_attr "cpu" "cfv4")
2176             (eq_attr "type" "fmove,fneg,ftst"))
2177        (eq_attr "op_mem" "00"))
2178   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp")
2179
2180 (define_insn_reservation "cfv4_fmove_fneg_10" 4
2181   (and (and (eq_attr "cpu" "cfv4")
2182             (eq_attr "type" "fmove,fneg,ftst"))
2183        (eq_attr "op_mem" "10,i0,11,1i,i1"))
2184   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp")
2185
2186 (define_insn_reservation "cfv4_fmove_01" 1
2187   (and (and (eq_attr "cpu" "cfv4")
2188             (eq_attr "type" "fmove,fneg,ftst"))
2189        (eq_attr "op_mem" "01,0i"))
2190   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp,cfv4_da,cfv4_mem")
2191
2192 (define_insn_reservation "cfv4_fdiv_00" 23
2193   (and (and (eq_attr "cpu" "cfv4")
2194             (eq_attr "type" "fdiv"))
2195        (eq_attr "op_mem" "00,01,0i"))
2196   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*17")
2197
2198 (define_insn_reservation "cfv4_fdiv_10" 23
2199   (and (and (eq_attr "cpu" "cfv4")
2200             (eq_attr "type" "fdiv"))
2201        (eq_attr "op_mem" "10,i0,11,1i,i1"))
2202   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*17")
2203
2204 (define_insn_reservation "cfv4_fsqrt_00" 56
2205   (and (and (eq_attr "cpu" "cfv4")
2206             (eq_attr "type" "fsqrt"))
2207        (eq_attr "op_mem" "00,01,0i"))
2208   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*50")
2209
2210 (define_insn_reservation "cfv4_fsqrt_10" 56
2211   (and (and (eq_attr "cpu" "cfv4")
2212             (eq_attr "type" "fsqrt"))
2213        (eq_attr "op_mem" "10,i0,11,1i,i1"))
2214   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*50")
2215
2216 (define_insn_reservation "cfv4_bcc" 0
2217   (and (eq_attr "cpu" "cfv4")
2218        (eq_attr "type" "bcc"))
2219   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
2220
2221 (define_insn_reservation "cfv4_fbcc" 2
2222   (and (eq_attr "cpu" "cfv4")
2223        (eq_attr "type" "fbcc"))
2224   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp")
2225
2226 ;; ??? Why is bra said to write to memory: 1(0/1) ?
2227 (define_insn_reservation "cfv4_bra_bsr" 1
2228   (and (eq_attr "cpu" "cfv4")
2229        (eq_attr "type" "bra,bsr"))
2230   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
2231
2232 (define_insn_reservation "cfv4_jmp_jsr" 5
2233   (and (eq_attr "cpu" "cfv4")
2234        (eq_attr "type" "jmp,jsr"))
2235   "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
2236
2237 (define_insn_reservation "cfv4_rts" 2
2238   (and (eq_attr "cpu" "cfv4")
2239        (eq_attr "type" "rts"))
2240   "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
2241
2242 (define_insn_reservation "cfv4_nop" 1
2243   (and (eq_attr "cpu" "cfv4")
2244        (eq_attr "type" "nop"))
2245   "cfv4_ds+cfv4_oag+cfv4_oc1+cfv4_mem+cfv4_oc2+cfv4_ex")
2246
2247 (define_insn_reservation "cfv4_guess" 10
2248   (and (eq_attr "cpu" "cfv4")
2249        (eq_attr "type" "trap,unknown"))
2250   "cfv4_guess+cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac+cfv4_fp")
2251
2252 (define_insn_reservation "ignore" 0
2253   (eq_attr "type" "ignore")
2254   "nothing")