1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx
, int);
152 static void arm_encode_section_info (tree
, rtx
, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx
arm_struct_value_rtx (tree
, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
168 enum machine_mode
, tree
, bool);
169 static bool arm_promote_prototypes (tree
);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree
);
173 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx
);
176 static bool arm_output_ttype (rtx
);
179 static tree
arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree
arm_get_cookie_size (tree
);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree
);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
191 static bool arm_cannot_copy_insn_p (rtx
);
192 static bool arm_tls_symbol_p (rtx x
);
195 /* Initialize the GCC target structure. */
196 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
197 #undef TARGET_MERGE_DECL_ATTRIBUTES
198 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
201 #undef TARGET_ATTRIBUTE_TABLE
202 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
204 #undef TARGET_ASM_FILE_END
205 #define TARGET_ASM_FILE_END arm_file_end
208 #undef TARGET_ASM_BYTE_OP
209 #define TARGET_ASM_BYTE_OP "\tDCB\t"
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
214 #undef TARGET_ASM_GLOBALIZE_LABEL
215 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
216 #undef TARGET_ASM_FILE_START
217 #define TARGET_ASM_FILE_START aof_file_start
218 #undef TARGET_ASM_FILE_END
219 #define TARGET_ASM_FILE_END aof_file_end
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP NULL
223 #undef TARGET_ASM_INTEGER
224 #define TARGET_ASM_INTEGER arm_assemble_integer
227 #undef TARGET_ASM_FUNCTION_PROLOGUE
228 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
230 #undef TARGET_ASM_FUNCTION_EPILOGUE
231 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
233 #undef TARGET_DEFAULT_TARGET_FLAGS
234 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
235 #undef TARGET_HANDLE_OPTION
236 #define TARGET_HANDLE_OPTION arm_handle_option
238 #undef TARGET_COMP_TYPE_ATTRIBUTES
239 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
241 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
242 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
244 #undef TARGET_SCHED_ADJUST_COST
245 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
247 #undef TARGET_ENCODE_SECTION_INFO
249 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
251 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
254 #undef TARGET_STRIP_NAME_ENCODING
255 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
257 #undef TARGET_ASM_INTERNAL_LABEL
258 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
261 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
263 #undef TARGET_ASM_OUTPUT_MI_THUNK
264 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
265 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
266 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
268 /* This will be overridden in arm_override_options. */
269 #undef TARGET_RTX_COSTS
270 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
271 #undef TARGET_ADDRESS_COST
272 #define TARGET_ADDRESS_COST arm_address_cost
274 #undef TARGET_SHIFT_TRUNCATION_MASK
275 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
276 #undef TARGET_VECTOR_MODE_SUPPORTED_P
277 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
279 #undef TARGET_MACHINE_DEPENDENT_REORG
280 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
282 #undef TARGET_INIT_BUILTINS
283 #define TARGET_INIT_BUILTINS arm_init_builtins
284 #undef TARGET_EXPAND_BUILTIN
285 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
287 #undef TARGET_INIT_LIBFUNCS
288 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
290 #undef TARGET_PROMOTE_FUNCTION_ARGS
291 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
292 #undef TARGET_PROMOTE_FUNCTION_RETURN
293 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
294 #undef TARGET_PROMOTE_PROTOTYPES
295 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
296 #undef TARGET_PASS_BY_REFERENCE
297 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
298 #undef TARGET_ARG_PARTIAL_BYTES
299 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
301 #undef TARGET_STRUCT_VALUE_RTX
302 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
304 #undef TARGET_SETUP_INCOMING_VARARGS
305 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
307 #undef TARGET_DEFAULT_SHORT_ENUMS
308 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
310 #undef TARGET_ALIGN_ANON_BITFIELD
311 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
313 #undef TARGET_CXX_GUARD_TYPE
314 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
316 #undef TARGET_CXX_GUARD_MASK_BIT
317 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
319 #undef TARGET_CXX_GET_COOKIE_SIZE
320 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
322 #undef TARGET_CXX_COOKIE_HAS_SIZE
323 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
325 #undef TARGET_CXX_CDTOR_RETURNS_THIS
326 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
328 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
329 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
331 #undef TARGET_CXX_USE_AEABI_ATEXIT
332 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
334 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
335 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
336 arm_cxx_determine_class_data_visibility
338 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
339 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
341 #undef TARGET_RETURN_IN_MSB
342 #define TARGET_RETURN_IN_MSB arm_return_in_msb
344 #undef TARGET_MUST_PASS_IN_STACK
345 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
347 #ifdef TARGET_UNWIND_INFO
348 #undef TARGET_UNWIND_EMIT
349 #define TARGET_UNWIND_EMIT arm_unwind_emit
351 /* EABI unwinding tables use a different format for the typeinfo tables. */
352 #undef TARGET_ASM_TTYPE
353 #define TARGET_ASM_TTYPE arm_output_ttype
355 #undef TARGET_ARM_EABI_UNWINDER
356 #define TARGET_ARM_EABI_UNWINDER true
357 #endif /* TARGET_UNWIND_INFO */
359 #undef TARGET_CANNOT_COPY_INSN_P
360 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
363 #undef TARGET_HAVE_TLS
364 #define TARGET_HAVE_TLS true
367 #undef TARGET_CANNOT_FORCE_CONST_MEM
368 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
370 struct gcc_target targetm
= TARGET_INITIALIZER
;
372 /* Obstack for minipool constant handling. */
373 static struct obstack minipool_obstack
;
374 static char * minipool_startobj
;
376 /* The maximum number of insns skipped which
377 will be conditionalised if possible. */
378 static int max_insns_skipped
= 5;
380 extern FILE * asm_out_file
;
382 /* True if we are currently building a constant table. */
383 int making_const_table
;
385 /* Define the information needed to generate branch insns. This is
386 stored from the compare operation. */
387 rtx arm_compare_op0
, arm_compare_op1
;
389 /* The processor for which instructions should be scheduled. */
390 enum processor_type arm_tune
= arm_none
;
392 /* Which floating point model to use. */
393 enum arm_fp_model arm_fp_model
;
395 /* Which floating point hardware is available. */
396 enum fputype arm_fpu_arch
;
398 /* Which floating point hardware to schedule for. */
399 enum fputype arm_fpu_tune
;
401 /* Whether to use floating point hardware. */
402 enum float_abi_type arm_float_abi
;
404 /* Which ABI to use. */
405 enum arm_abi_type arm_abi
;
407 /* Which thread pointer model to use. */
408 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
410 /* Used to parse -mstructure_size_boundary command line option. */
411 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
413 /* Used for Thumb call_via trampolines. */
414 rtx thumb_call_via_label
[14];
415 static int thumb_call_reg_needed
;
417 /* Bit values used to identify processor capabilities. */
418 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
419 #define FL_ARCH3M (1 << 1) /* Extended multiply */
420 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
421 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
422 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
423 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
424 #define FL_THUMB (1 << 6) /* Thumb aware */
425 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
426 #define FL_STRONG (1 << 8) /* StrongARM */
427 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
428 #define FL_XSCALE (1 << 10) /* XScale */
429 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
430 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
431 media instructions. */
432 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
433 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
434 Note: ARM6 & 7 derivatives only. */
435 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
437 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
439 #define FL_FOR_ARCH2 0
440 #define FL_FOR_ARCH3 FL_MODE32
441 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
442 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
443 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
444 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
445 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
446 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
447 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
448 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
449 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
450 #define FL_FOR_ARCH6J FL_FOR_ARCH6
451 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
452 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
453 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
455 /* The bits in this mask specify which
456 instructions we are allowed to generate. */
457 static unsigned long insn_flags
= 0;
459 /* The bits in this mask specify which instruction scheduling options should
461 static unsigned long tune_flags
= 0;
463 /* The following are used in the arm.md file as equivalents to bits
464 in the above two flag variables. */
466 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
469 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
472 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
475 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
478 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
481 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
484 /* Nonzero if this chip supports the ARM 6K extensions. */
487 /* Nonzero if this chip can benefit from load scheduling. */
488 int arm_ld_sched
= 0;
490 /* Nonzero if this chip is a StrongARM. */
491 int arm_tune_strongarm
= 0;
493 /* Nonzero if this chip is a Cirrus variant. */
494 int arm_arch_cirrus
= 0;
496 /* Nonzero if this chip supports Intel Wireless MMX technology. */
497 int arm_arch_iwmmxt
= 0;
499 /* Nonzero if this chip is an XScale. */
500 int arm_arch_xscale
= 0;
502 /* Nonzero if tuning for XScale */
503 int arm_tune_xscale
= 0;
505 /* Nonzero if we want to tune for stores that access the write-buffer.
506 This typically means an ARM6 or ARM7 with MMU or MPU. */
507 int arm_tune_wbuf
= 0;
509 /* Nonzero if generating Thumb instructions. */
512 /* Nonzero if we should define __THUMB_INTERWORK__ in the
514 XXX This is a bit of a hack, it's intended to help work around
515 problems in GLD which doesn't understand that armv5t code is
516 interworking clean. */
517 int arm_cpp_interwork
= 0;
519 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
520 must report the mode of the memory reference from PRINT_OPERAND to
521 PRINT_OPERAND_ADDRESS. */
522 enum machine_mode output_memory_reference_mode
;
524 /* The register number to be used for the PIC offset register. */
525 int arm_pic_register
= INVALID_REGNUM
;
527 /* Set to 1 when a return insn is output, this means that the epilogue
529 int return_used_this_function
;
531 /* Set to 1 after arm_reorg has started. Reset to start at the start of
532 the next function. */
533 static int after_arm_reorg
= 0;
535 /* The maximum number of insns to be used when loading a constant. */
536 static int arm_constant_limit
= 3;
538 /* For an explanation of these variables, see final_prescan_insn below. */
540 enum arm_cond_code arm_current_cc
;
542 int arm_target_label
;
544 /* The condition codes of the ARM, and the inverse function. */
545 static const char * const arm_condition_codes
[] =
547 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
548 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
551 #define streq(string1, string2) (strcmp (string1, string2) == 0)
553 /* Initialization code. */
557 const char *const name
;
558 enum processor_type core
;
560 const unsigned long flags
;
561 bool (* rtx_costs
) (rtx
, int, int, int *);
564 /* Not all of these give usefully different compilation alternatives,
565 but there is no simple way of generalizing them. */
566 static const struct processors all_cores
[] =
569 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
570 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
571 #include "arm-cores.def"
573 {NULL
, arm_none
, NULL
, 0, NULL
}
576 static const struct processors all_architectures
[] =
578 /* ARM Architectures */
579 /* We don't specify rtx_costs here as it will be figured out
582 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
583 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
584 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
585 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
586 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
587 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
588 implementations that support it, so we will leave it out for now. */
589 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
590 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
591 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
592 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
593 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
594 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
595 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
596 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
597 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
598 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
599 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
600 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
601 {NULL
, arm_none
, NULL
, 0 , NULL
}
604 struct arm_cpu_select
608 const struct processors
* processors
;
611 /* This is a magic structure. The 'string' field is magically filled in
612 with a pointer to the value specified by the user on the command line
613 assuming that the user has specified such a value. */
615 static struct arm_cpu_select arm_select
[] =
617 /* string name processors */
618 { NULL
, "-mcpu=", all_cores
},
619 { NULL
, "-march=", all_architectures
},
620 { NULL
, "-mtune=", all_cores
}
623 /* Defines representing the indexes into the above table. */
624 #define ARM_OPT_SET_CPU 0
625 #define ARM_OPT_SET_ARCH 1
626 #define ARM_OPT_SET_TUNE 2
628 /* The name of the proprocessor macro to define for this architecture. */
630 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
639 /* Available values for for -mfpu=. */
641 static const struct fpu_desc all_fpus
[] =
643 {"fpa", FPUTYPE_FPA
},
644 {"fpe2", FPUTYPE_FPA_EMU2
},
645 {"fpe3", FPUTYPE_FPA_EMU2
},
646 {"maverick", FPUTYPE_MAVERICK
},
651 /* Floating point models used by the different hardware.
652 See fputype in arm.h. */
654 static const enum fputype fp_model_for_fpu
[] =
656 /* No FP hardware. */
657 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
658 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
659 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
660 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
661 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
662 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
669 enum float_abi_type abi_type
;
673 /* Available values for -mfloat-abi=. */
675 static const struct float_abi all_float_abis
[] =
677 {"soft", ARM_FLOAT_ABI_SOFT
},
678 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
679 {"hard", ARM_FLOAT_ABI_HARD
}
686 enum arm_abi_type abi_type
;
690 /* Available values for -mabi=. */
692 static const struct abi_name arm_all_abis
[] =
694 {"apcs-gnu", ARM_ABI_APCS
},
695 {"atpcs", ARM_ABI_ATPCS
},
696 {"aapcs", ARM_ABI_AAPCS
},
697 {"iwmmxt", ARM_ABI_IWMMXT
},
698 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
701 /* Supported TLS relocations. */
711 /* Return the number of bits set in VALUE. */
713 bit_count (unsigned long value
)
715 unsigned long count
= 0;
720 value
&= value
- 1; /* Clear the least-significant set bit. */
726 /* Set up library functions unique to ARM. */
729 arm_init_libfuncs (void)
731 /* There are no special library functions unless we are using the
736 /* The functions below are described in Section 4 of the "Run-Time
737 ABI for the ARM architecture", Version 1.0. */
739 /* Double-precision floating-point arithmetic. Table 2. */
740 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
741 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
742 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
743 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
744 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
746 /* Double-precision comparisons. Table 3. */
747 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
748 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
749 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
750 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
751 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
752 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
753 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
755 /* Single-precision floating-point arithmetic. Table 4. */
756 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
757 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
758 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
759 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
760 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
762 /* Single-precision comparisons. Table 5. */
763 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
764 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
765 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
766 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
767 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
768 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
769 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
771 /* Floating-point to integer conversions. Table 6. */
772 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
773 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
774 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
775 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
776 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
777 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
778 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
779 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
781 /* Conversions between floating types. Table 7. */
782 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
783 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
785 /* Integer to floating-point conversions. Table 8. */
786 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
787 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
788 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
789 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
790 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
791 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
792 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
793 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
795 /* Long long. Table 9. */
796 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
797 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
798 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
799 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
800 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
801 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
802 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
803 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
805 /* Integer (32/32->32) division. \S 4.3.1. */
806 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
807 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
809 /* The divmod functions are designed so that they can be used for
810 plain division, even though they return both the quotient and the
811 remainder. The quotient is returned in the usual location (i.e.,
812 r0 for SImode, {r0, r1} for DImode), just as would be expected
813 for an ordinary division routine. Because the AAPCS calling
814 conventions specify that all of { r0, r1, r2, r3 } are
815 callee-saved registers, there is no need to tell the compiler
816 explicitly that those registers are clobbered by these
818 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
819 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
821 /* For SImode division the ABI provides div-without-mod routines,
823 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
824 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
826 /* We don't have mod libcalls. Fortunately gcc knows how to use the
827 divmod libcalls instead. */
828 set_optab_libfunc (smod_optab
, DImode
, NULL
);
829 set_optab_libfunc (umod_optab
, DImode
, NULL
);
830 set_optab_libfunc (smod_optab
, SImode
, NULL
);
831 set_optab_libfunc (umod_optab
, SImode
, NULL
);
834 /* Implement TARGET_HANDLE_OPTION. */
837 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
842 arm_select
[1].string
= arg
;
846 arm_select
[0].string
= arg
;
849 case OPT_mhard_float
:
850 target_float_abi_name
= "hard";
853 case OPT_msoft_float
:
854 target_float_abi_name
= "soft";
858 arm_select
[2].string
= arg
;
866 /* Fix up any incompatible options that the user has specified.
867 This has now turned into a maze. */
869 arm_override_options (void)
872 enum processor_type target_arch_cpu
= arm_none
;
874 /* Set up the flags based on the cpu/architecture selected by the user. */
875 for (i
= ARRAY_SIZE (arm_select
); i
--;)
877 struct arm_cpu_select
* ptr
= arm_select
+ i
;
879 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
881 const struct processors
* sel
;
883 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
884 if (streq (ptr
->string
, sel
->name
))
886 /* Set the architecture define. */
887 if (i
!= ARM_OPT_SET_TUNE
)
888 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
890 /* Determine the processor core for which we should
891 tune code-generation. */
892 if (/* -mcpu= is a sensible default. */
894 /* -mtune= overrides -mcpu= and -march=. */
895 || i
== ARM_OPT_SET_TUNE
)
896 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
898 /* Remember the CPU associated with this architecture.
899 If no other option is used to set the CPU type,
900 we'll use this to guess the most suitable tuning
902 if (i
== ARM_OPT_SET_ARCH
)
903 target_arch_cpu
= sel
->core
;
905 if (i
!= ARM_OPT_SET_TUNE
)
907 /* If we have been given an architecture and a processor
908 make sure that they are compatible. We only generate
909 a warning though, and we prefer the CPU over the
911 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
912 warning (0, "switch -mcpu=%s conflicts with -march= switch",
915 insn_flags
= sel
->flags
;
921 if (sel
->name
== NULL
)
922 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
926 /* Guess the tuning options from the architecture if necessary. */
927 if (arm_tune
== arm_none
)
928 arm_tune
= target_arch_cpu
;
930 /* If the user did not specify a processor, choose one for them. */
933 const struct processors
* sel
;
935 enum processor_type cpu
;
937 cpu
= TARGET_CPU_DEFAULT
;
940 #ifdef SUBTARGET_CPU_DEFAULT
941 /* Use the subtarget default CPU if none was specified by
943 cpu
= SUBTARGET_CPU_DEFAULT
;
945 /* Default to ARM6. */
949 sel
= &all_cores
[cpu
];
951 insn_flags
= sel
->flags
;
953 /* Now check to see if the user has specified some command line
954 switch that require certain abilities from the cpu. */
957 if (TARGET_INTERWORK
|| TARGET_THUMB
)
959 sought
|= (FL_THUMB
| FL_MODE32
);
961 /* There are no ARM processors that support both APCS-26 and
962 interworking. Therefore we force FL_MODE26 to be removed
963 from insn_flags here (if it was set), so that the search
964 below will always be able to find a compatible processor. */
965 insn_flags
&= ~FL_MODE26
;
968 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
970 /* Try to locate a CPU type that supports all of the abilities
971 of the default CPU, plus the extra abilities requested by
973 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
974 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
977 if (sel
->name
== NULL
)
979 unsigned current_bit_count
= 0;
980 const struct processors
* best_fit
= NULL
;
982 /* Ideally we would like to issue an error message here
983 saying that it was not possible to find a CPU compatible
984 with the default CPU, but which also supports the command
985 line options specified by the programmer, and so they
986 ought to use the -mcpu=<name> command line option to
987 override the default CPU type.
989 If we cannot find a cpu that has both the
990 characteristics of the default cpu and the given
991 command line options we scan the array again looking
993 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
994 if ((sel
->flags
& sought
) == sought
)
998 count
= bit_count (sel
->flags
& insn_flags
);
1000 if (count
>= current_bit_count
)
1003 current_bit_count
= count
;
1007 gcc_assert (best_fit
);
1011 insn_flags
= sel
->flags
;
1013 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1014 if (arm_tune
== arm_none
)
1015 arm_tune
= (enum processor_type
) (sel
- all_cores
);
1018 /* The processor for which we should tune should now have been
1020 gcc_assert (arm_tune
!= arm_none
);
1022 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1024 targetm
.rtx_costs
= arm_size_rtx_costs
;
1026 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1028 /* Make sure that the processor choice does not conflict with any of the
1029 other command line choices. */
1030 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1032 warning (0, "target CPU does not support interworking" );
1033 target_flags
&= ~MASK_INTERWORK
;
1036 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1038 warning (0, "target CPU does not support THUMB instructions");
1039 target_flags
&= ~MASK_THUMB
;
1042 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1044 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1045 target_flags
&= ~MASK_APCS_FRAME
;
1048 /* Callee super interworking implies thumb interworking. Adding
1049 this to the flags here simplifies the logic elsewhere. */
1050 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1051 target_flags
|= MASK_INTERWORK
;
1053 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1054 from here where no function is being compiled currently. */
1055 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1056 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1058 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1059 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1061 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1062 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1064 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1066 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1067 target_flags
|= MASK_APCS_FRAME
;
1070 if (TARGET_POKE_FUNCTION_NAME
)
1071 target_flags
|= MASK_APCS_FRAME
;
1073 if (TARGET_APCS_REENT
&& flag_pic
)
1074 error ("-fpic and -mapcs-reent are incompatible");
1076 if (TARGET_APCS_REENT
)
1077 warning (0, "APCS reentrant code not supported. Ignored");
1079 /* If this target is normally configured to use APCS frames, warn if they
1080 are turned off and debugging is turned on. */
1082 && write_symbols
!= NO_DEBUG
1083 && !TARGET_APCS_FRAME
1084 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1085 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1087 /* If stack checking is disabled, we can use r10 as the PIC register,
1088 which keeps r9 available. */
1090 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1092 if (TARGET_APCS_FLOAT
)
1093 warning (0, "passing floating point arguments in fp regs not yet supported");
1095 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1096 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1097 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1098 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1099 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1100 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1101 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1102 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1103 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1104 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1106 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1107 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1108 thumb_code
= (TARGET_ARM
== 0);
1109 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1110 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1111 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1113 /* V5 code we generate is completely interworking capable, so we turn off
1114 TARGET_INTERWORK here to avoid many tests later on. */
1116 /* XXX However, we must pass the right pre-processor defines to CPP
1117 or GLD can get confused. This is a hack. */
1118 if (TARGET_INTERWORK
)
1119 arm_cpp_interwork
= 1;
1122 target_flags
&= ~MASK_INTERWORK
;
1124 if (target_abi_name
)
1126 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1128 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1130 arm_abi
= arm_all_abis
[i
].abi_type
;
1134 if (i
== ARRAY_SIZE (arm_all_abis
))
1135 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1138 arm_abi
= ARM_DEFAULT_ABI
;
1140 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1141 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1143 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1144 error ("iwmmxt abi requires an iwmmxt capable cpu");
1146 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1147 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1149 if (streq (target_fpe_name
, "2"))
1150 target_fpu_name
= "fpe2";
1151 else if (streq (target_fpe_name
, "3"))
1152 target_fpu_name
= "fpe3";
1154 error ("invalid floating point emulation option: -mfpe=%s",
1157 if (target_fpu_name
!= NULL
)
1159 /* The user specified a FPU. */
1160 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1162 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1164 arm_fpu_arch
= all_fpus
[i
].fpu
;
1165 arm_fpu_tune
= arm_fpu_arch
;
1166 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1170 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1171 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1175 #ifdef FPUTYPE_DEFAULT
1176 /* Use the default if it is specified for this platform. */
1177 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1178 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1180 /* Pick one based on CPU type. */
1181 /* ??? Some targets assume FPA is the default.
1182 if ((insn_flags & FL_VFP) != 0)
1183 arm_fpu_arch = FPUTYPE_VFP;
1186 if (arm_arch_cirrus
)
1187 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1189 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1191 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1192 arm_fpu_tune
= FPUTYPE_FPA
;
1194 arm_fpu_tune
= arm_fpu_arch
;
1195 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1196 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1199 if (target_float_abi_name
!= NULL
)
1201 /* The user specified a FP ABI. */
1202 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1204 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1206 arm_float_abi
= all_float_abis
[i
].abi_type
;
1210 if (i
== ARRAY_SIZE (all_float_abis
))
1211 error ("invalid floating point abi: -mfloat-abi=%s",
1212 target_float_abi_name
);
1215 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1217 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1218 sorry ("-mfloat-abi=hard and VFP");
1220 /* If soft-float is specified then don't use FPU. */
1221 if (TARGET_SOFT_FLOAT
)
1222 arm_fpu_arch
= FPUTYPE_NONE
;
1224 /* For arm2/3 there is no need to do any scheduling if there is only
1225 a floating point emulator, or we are doing software floating-point. */
1226 if ((TARGET_SOFT_FLOAT
1227 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1228 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1229 && (tune_flags
& FL_MODE32
) == 0)
1230 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1232 if (target_thread_switch
)
1234 if (strcmp (target_thread_switch
, "soft") == 0)
1235 target_thread_pointer
= TP_SOFT
;
1236 else if (strcmp (target_thread_switch
, "auto") == 0)
1237 target_thread_pointer
= TP_AUTO
;
1238 else if (strcmp (target_thread_switch
, "cp15") == 0)
1239 target_thread_pointer
= TP_CP15
;
1241 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1244 /* Use the cp15 method if it is available. */
1245 if (target_thread_pointer
== TP_AUTO
)
1247 if (arm_arch6k
&& !TARGET_THUMB
)
1248 target_thread_pointer
= TP_CP15
;
1250 target_thread_pointer
= TP_SOFT
;
1253 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1254 error ("can not use -mtp=cp15 with -mthumb");
1256 /* Override the default structure alignment for AAPCS ABI. */
1257 if (TARGET_AAPCS_BASED
)
1258 arm_structure_size_boundary
= 8;
1260 if (structure_size_string
!= NULL
)
1262 int size
= strtol (structure_size_string
, NULL
, 0);
1264 if (size
== 8 || size
== 32
1265 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1266 arm_structure_size_boundary
= size
;
1268 warning (0, "structure size boundary can only be set to %s",
1269 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1272 if (arm_pic_register_string
!= NULL
)
1274 int pic_register
= decode_reg_name (arm_pic_register_string
);
1277 warning (0, "-mpic-register= is useless without -fpic");
1279 /* Prevent the user from choosing an obviously stupid PIC register. */
1280 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1281 || pic_register
== HARD_FRAME_POINTER_REGNUM
1282 || pic_register
== STACK_POINTER_REGNUM
1283 || pic_register
>= PC_REGNUM
)
1284 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1286 arm_pic_register
= pic_register
;
1289 if (TARGET_THUMB
&& flag_schedule_insns
)
1291 /* Don't warn since it's on by default in -O2. */
1292 flag_schedule_insns
= 0;
1297 arm_constant_limit
= 1;
1299 /* If optimizing for size, bump the number of instructions that we
1300 are prepared to conditionally execute (even on a StrongARM). */
1301 max_insns_skipped
= 6;
1305 /* For processors with load scheduling, it never costs more than
1306 2 cycles to load a constant, and the load scheduler may well
1307 reduce that to 1. */
1309 arm_constant_limit
= 1;
1311 /* On XScale the longer latency of a load makes it more difficult
1312 to achieve a good schedule, so it's faster to synthesize
1313 constants that can be done in two insns. */
1314 if (arm_tune_xscale
)
1315 arm_constant_limit
= 2;
1317 /* StrongARM has early execution of branches, so a sequence
1318 that is worth skipping is shorter. */
1319 if (arm_tune_strongarm
)
1320 max_insns_skipped
= 3;
1323 /* Register global variables with the garbage collector. */
1324 arm_add_gc_roots ();
1328 arm_add_gc_roots (void)
1330 gcc_obstack_init(&minipool_obstack
);
1331 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1334 /* A table of known ARM exception types.
1335 For use with the interrupt function attribute. */
1339 const char *const arg
;
1340 const unsigned long return_value
;
1344 static const isr_attribute_arg isr_attribute_args
[] =
1346 { "IRQ", ARM_FT_ISR
},
1347 { "irq", ARM_FT_ISR
},
1348 { "FIQ", ARM_FT_FIQ
},
1349 { "fiq", ARM_FT_FIQ
},
1350 { "ABORT", ARM_FT_ISR
},
1351 { "abort", ARM_FT_ISR
},
1352 { "ABORT", ARM_FT_ISR
},
1353 { "abort", ARM_FT_ISR
},
1354 { "UNDEF", ARM_FT_EXCEPTION
},
1355 { "undef", ARM_FT_EXCEPTION
},
1356 { "SWI", ARM_FT_EXCEPTION
},
1357 { "swi", ARM_FT_EXCEPTION
},
1358 { NULL
, ARM_FT_NORMAL
}
1361 /* Returns the (interrupt) function type of the current
1362 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1364 static unsigned long
1365 arm_isr_value (tree argument
)
1367 const isr_attribute_arg
* ptr
;
1370 /* No argument - default to IRQ. */
1371 if (argument
== NULL_TREE
)
1374 /* Get the value of the argument. */
1375 if (TREE_VALUE (argument
) == NULL_TREE
1376 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1377 return ARM_FT_UNKNOWN
;
1379 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1381 /* Check it against the list of known arguments. */
1382 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1383 if (streq (arg
, ptr
->arg
))
1384 return ptr
->return_value
;
1386 /* An unrecognized interrupt type. */
1387 return ARM_FT_UNKNOWN
;
1390 /* Computes the type of the current function. */
1392 static unsigned long
1393 arm_compute_func_type (void)
1395 unsigned long type
= ARM_FT_UNKNOWN
;
1399 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1401 /* Decide if the current function is volatile. Such functions
1402 never return, and many memory cycles can be saved by not storing
1403 register values that will never be needed again. This optimization
1404 was added to speed up context switching in a kernel application. */
1406 && TREE_NOTHROW (current_function_decl
)
1407 && TREE_THIS_VOLATILE (current_function_decl
))
1408 type
|= ARM_FT_VOLATILE
;
1410 if (cfun
->static_chain_decl
!= NULL
)
1411 type
|= ARM_FT_NESTED
;
1413 attr
= DECL_ATTRIBUTES (current_function_decl
);
1415 a
= lookup_attribute ("naked", attr
);
1417 type
|= ARM_FT_NAKED
;
1419 a
= lookup_attribute ("isr", attr
);
1421 a
= lookup_attribute ("interrupt", attr
);
1424 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1426 type
|= arm_isr_value (TREE_VALUE (a
));
1431 /* Returns the type of the current function. */
1434 arm_current_func_type (void)
1436 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1437 cfun
->machine
->func_type
= arm_compute_func_type ();
1439 return cfun
->machine
->func_type
;
1442 /* Return 1 if it is possible to return using a single instruction.
1443 If SIBLING is non-null, this is a test for a return before a sibling
1444 call. SIBLING is the call insn, so we can examine its register usage. */
1447 use_return_insn (int iscond
, rtx sibling
)
1450 unsigned int func_type
;
1451 unsigned long saved_int_regs
;
1452 unsigned HOST_WIDE_INT stack_adjust
;
1453 arm_stack_offsets
*offsets
;
1455 /* Never use a return instruction before reload has run. */
1456 if (!reload_completed
)
1459 func_type
= arm_current_func_type ();
1461 /* Naked functions and volatile functions need special
1463 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1466 /* So do interrupt functions that use the frame pointer. */
1467 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1470 offsets
= arm_get_frame_offsets ();
1471 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1473 /* As do variadic functions. */
1474 if (current_function_pretend_args_size
1475 || cfun
->machine
->uses_anonymous_args
1476 /* Or if the function calls __builtin_eh_return () */
1477 || current_function_calls_eh_return
1478 /* Or if the function calls alloca */
1479 || current_function_calls_alloca
1480 /* Or if there is a stack adjustment. However, if the stack pointer
1481 is saved on the stack, we can use a pre-incrementing stack load. */
1482 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1485 saved_int_regs
= arm_compute_save_reg_mask ();
1487 /* Unfortunately, the insn
1489 ldmib sp, {..., sp, ...}
1491 triggers a bug on most SA-110 based devices, such that the stack
1492 pointer won't be correctly restored if the instruction takes a
1493 page fault. We work around this problem by popping r3 along with
1494 the other registers, since that is never slower than executing
1495 another instruction.
1497 We test for !arm_arch5 here, because code for any architecture
1498 less than this could potentially be run on one of the buggy
1500 if (stack_adjust
== 4 && !arm_arch5
)
1502 /* Validate that r3 is a call-clobbered register (always true in
1503 the default abi) ... */
1504 if (!call_used_regs
[3])
1507 /* ... that it isn't being used for a return value ... */
1508 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1511 /* ... or for a tail-call argument ... */
1514 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1516 if (find_regno_fusage (sibling
, USE
, 3))
1520 /* ... and that there are no call-saved registers in r0-r2
1521 (always true in the default ABI). */
1522 if (saved_int_regs
& 0x7)
1526 /* Can't be done if interworking with Thumb, and any registers have been
1528 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1531 /* On StrongARM, conditional returns are expensive if they aren't
1532 taken and multiple registers have been stacked. */
1533 if (iscond
&& arm_tune_strongarm
)
1535 /* Conditional return when just the LR is stored is a simple
1536 conditional-load instruction, that's not expensive. */
1537 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1540 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1544 /* If there are saved registers but the LR isn't saved, then we need
1545 two instructions for the return. */
1546 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1549 /* Can't be done if any of the FPA regs are pushed,
1550 since this also requires an insn. */
1551 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1552 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1553 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1556 /* Likewise VFP regs. */
1557 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1558 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1559 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1562 if (TARGET_REALLY_IWMMXT
)
1563 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1564 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1570 /* Return TRUE if int I is a valid immediate ARM constant. */
1573 const_ok_for_arm (HOST_WIDE_INT i
)
1577 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1578 be all zero, or all one. */
1579 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1580 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1581 != ((~(unsigned HOST_WIDE_INT
) 0)
1582 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1585 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1587 /* Fast return for 0 and small values. We must do this for zero, since
1588 the code below can't handle that one case. */
1589 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1592 /* Get the number of trailing zeros, rounded down to the nearest even
1594 lowbit
= (ffs ((int) i
) - 1) & ~1;
1596 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1598 else if (lowbit
<= 4
1599 && ((i
& ~0xc000003f) == 0
1600 || (i
& ~0xf000000f) == 0
1601 || (i
& ~0xfc000003) == 0))
1607 /* Return true if I is a valid constant for the operation CODE. */
1609 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1611 if (const_ok_for_arm (i
))
1617 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1619 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1625 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1632 /* Emit a sequence of insns to handle a large constant.
1633 CODE is the code of the operation required, it can be any of SET, PLUS,
1634 IOR, AND, XOR, MINUS;
1635 MODE is the mode in which the operation is being performed;
1636 VAL is the integer to operate on;
1637 SOURCE is the other operand (a register, or a null-pointer for SET);
1638 SUBTARGETS means it is safe to create scratch registers if that will
1639 either produce a simpler sequence, or we will want to cse the values.
1640 Return value is the number of insns emitted. */
1643 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1644 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1648 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1649 cond
= COND_EXEC_TEST (PATTERN (insn
));
1653 if (subtargets
|| code
== SET
1654 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1655 && REGNO (target
) != REGNO (source
)))
1657 /* After arm_reorg has been called, we can't fix up expensive
1658 constants by pushing them into memory so we must synthesize
1659 them in-line, regardless of the cost. This is only likely to
1660 be more costly on chips that have load delay slots and we are
1661 compiling without running the scheduler (so no splitting
1662 occurred before the final instruction emission).
1664 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1666 if (!after_arm_reorg
1668 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1670 > arm_constant_limit
+ (code
!= SET
)))
1674 /* Currently SET is the only monadic value for CODE, all
1675 the rest are diadic. */
1676 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1681 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1683 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1684 /* For MINUS, the value is subtracted from, since we never
1685 have subtraction of a constant. */
1687 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1688 gen_rtx_MINUS (mode
, temp
, source
)));
1690 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1691 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1697 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1702 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1704 HOST_WIDE_INT temp1
;
1712 if (remainder
& (3 << (i
- 2)))
1717 temp1
= remainder
& ((0x0ff << end
)
1718 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1719 remainder
&= ~temp1
;
1724 } while (remainder
);
1728 /* Emit an instruction with the indicated PATTERN. If COND is
1729 non-NULL, conditionalize the execution of the instruction on COND
1733 emit_constant_insn (rtx cond
, rtx pattern
)
1736 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1737 emit_insn (pattern
);
1740 /* As above, but extra parameter GENERATE which, if clear, suppresses
1744 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1745 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1750 int can_negate_initial
= 0;
1753 int num_bits_set
= 0;
1754 int set_sign_bit_copies
= 0;
1755 int clear_sign_bit_copies
= 0;
1756 int clear_zero_bit_copies
= 0;
1757 int set_zero_bit_copies
= 0;
1759 unsigned HOST_WIDE_INT temp1
, temp2
;
1760 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1762 /* Find out which operations are safe for a given CODE. Also do a quick
1763 check for degenerate cases; these can occur when DImode operations
1775 can_negate_initial
= 1;
1779 if (remainder
== 0xffffffff)
1782 emit_constant_insn (cond
,
1783 gen_rtx_SET (VOIDmode
, target
,
1784 GEN_INT (ARM_SIGN_EXTEND (val
))));
1789 if (reload_completed
&& rtx_equal_p (target
, source
))
1792 emit_constant_insn (cond
,
1793 gen_rtx_SET (VOIDmode
, target
, source
));
1802 emit_constant_insn (cond
,
1803 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1806 if (remainder
== 0xffffffff)
1808 if (reload_completed
&& rtx_equal_p (target
, source
))
1811 emit_constant_insn (cond
,
1812 gen_rtx_SET (VOIDmode
, target
, source
));
1821 if (reload_completed
&& rtx_equal_p (target
, source
))
1824 emit_constant_insn (cond
,
1825 gen_rtx_SET (VOIDmode
, target
, source
));
1829 /* We don't know how to handle other cases yet. */
1830 gcc_assert (remainder
== 0xffffffff);
1833 emit_constant_insn (cond
,
1834 gen_rtx_SET (VOIDmode
, target
,
1835 gen_rtx_NOT (mode
, source
)));
1839 /* We treat MINUS as (val - source), since (source - val) is always
1840 passed as (source + (-val)). */
1844 emit_constant_insn (cond
,
1845 gen_rtx_SET (VOIDmode
, target
,
1846 gen_rtx_NEG (mode
, source
)));
1849 if (const_ok_for_arm (val
))
1852 emit_constant_insn (cond
,
1853 gen_rtx_SET (VOIDmode
, target
,
1854 gen_rtx_MINUS (mode
, GEN_INT (val
),
1866 /* If we can do it in one insn get out quickly. */
1867 if (const_ok_for_arm (val
)
1868 || (can_negate_initial
&& const_ok_for_arm (-val
))
1869 || (can_invert
&& const_ok_for_arm (~val
)))
1872 emit_constant_insn (cond
,
1873 gen_rtx_SET (VOIDmode
, target
,
1875 ? gen_rtx_fmt_ee (code
, mode
, source
,
1881 /* Calculate a few attributes that may be useful for specific
1883 for (i
= 31; i
>= 0; i
--)
1885 if ((remainder
& (1 << i
)) == 0)
1886 clear_sign_bit_copies
++;
1891 for (i
= 31; i
>= 0; i
--)
1893 if ((remainder
& (1 << i
)) != 0)
1894 set_sign_bit_copies
++;
1899 for (i
= 0; i
<= 31; i
++)
1901 if ((remainder
& (1 << i
)) == 0)
1902 clear_zero_bit_copies
++;
1907 for (i
= 0; i
<= 31; i
++)
1909 if ((remainder
& (1 << i
)) != 0)
1910 set_zero_bit_copies
++;
1918 /* See if we can do this by sign_extending a constant that is known
1919 to be negative. This is a good, way of doing it, since the shift
1920 may well merge into a subsequent insn. */
1921 if (set_sign_bit_copies
> 1)
1923 if (const_ok_for_arm
1924 (temp1
= ARM_SIGN_EXTEND (remainder
1925 << (set_sign_bit_copies
- 1))))
1929 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1930 emit_constant_insn (cond
,
1931 gen_rtx_SET (VOIDmode
, new_src
,
1933 emit_constant_insn (cond
,
1934 gen_ashrsi3 (target
, new_src
,
1935 GEN_INT (set_sign_bit_copies
- 1)));
1939 /* For an inverted constant, we will need to set the low bits,
1940 these will be shifted out of harm's way. */
1941 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1942 if (const_ok_for_arm (~temp1
))
1946 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1947 emit_constant_insn (cond
,
1948 gen_rtx_SET (VOIDmode
, new_src
,
1950 emit_constant_insn (cond
,
1951 gen_ashrsi3 (target
, new_src
,
1952 GEN_INT (set_sign_bit_copies
- 1)));
1958 /* See if we can calculate the value as the difference between two
1959 valid immediates. */
1960 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1962 int topshift
= clear_sign_bit_copies
& ~1;
1964 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1965 & (0xff000000 >> topshift
));
1967 /* If temp1 is zero, then that means the 9 most significant
1968 bits of remainder were 1 and we've caused it to overflow.
1969 When topshift is 0 we don't need to do anything since we
1970 can borrow from 'bit 32'. */
1971 if (temp1
== 0 && topshift
!= 0)
1972 temp1
= 0x80000000 >> (topshift
- 1);
1974 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1976 if (const_ok_for_arm (temp2
))
1980 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1981 emit_constant_insn (cond
,
1982 gen_rtx_SET (VOIDmode
, new_src
,
1984 emit_constant_insn (cond
,
1985 gen_addsi3 (target
, new_src
,
1993 /* See if we can generate this by setting the bottom (or the top)
1994 16 bits, and then shifting these into the other half of the
1995 word. We only look for the simplest cases, to do more would cost
1996 too much. Be careful, however, not to generate this when the
1997 alternative would take fewer insns. */
1998 if (val
& 0xffff0000)
2000 temp1
= remainder
& 0xffff0000;
2001 temp2
= remainder
& 0x0000ffff;
2003 /* Overlaps outside this range are best done using other methods. */
2004 for (i
= 9; i
< 24; i
++)
2006 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2007 && !const_ok_for_arm (temp2
))
2009 rtx new_src
= (subtargets
2010 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2012 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2013 source
, subtargets
, generate
);
2021 gen_rtx_ASHIFT (mode
, source
,
2028 /* Don't duplicate cases already considered. */
2029 for (i
= 17; i
< 24; i
++)
2031 if (((temp1
| (temp1
>> i
)) == remainder
)
2032 && !const_ok_for_arm (temp1
))
2034 rtx new_src
= (subtargets
2035 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2037 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2038 source
, subtargets
, generate
);
2043 gen_rtx_SET (VOIDmode
, target
,
2046 gen_rtx_LSHIFTRT (mode
, source
,
2057 /* If we have IOR or XOR, and the constant can be loaded in a
2058 single instruction, and we can find a temporary to put it in,
2059 then this can be done in two instructions instead of 3-4. */
2061 /* TARGET can't be NULL if SUBTARGETS is 0 */
2062 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2064 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2068 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2070 emit_constant_insn (cond
,
2071 gen_rtx_SET (VOIDmode
, sub
,
2073 emit_constant_insn (cond
,
2074 gen_rtx_SET (VOIDmode
, target
,
2075 gen_rtx_fmt_ee (code
, mode
,
2085 if (set_sign_bit_copies
> 8
2086 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2090 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2091 rtx shift
= GEN_INT (set_sign_bit_copies
);
2095 gen_rtx_SET (VOIDmode
, sub
,
2097 gen_rtx_ASHIFT (mode
,
2102 gen_rtx_SET (VOIDmode
, target
,
2104 gen_rtx_LSHIFTRT (mode
, sub
,
2110 if (set_zero_bit_copies
> 8
2111 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2115 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2116 rtx shift
= GEN_INT (set_zero_bit_copies
);
2120 gen_rtx_SET (VOIDmode
, sub
,
2122 gen_rtx_LSHIFTRT (mode
,
2127 gen_rtx_SET (VOIDmode
, target
,
2129 gen_rtx_ASHIFT (mode
, sub
,
2135 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2139 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2140 emit_constant_insn (cond
,
2141 gen_rtx_SET (VOIDmode
, sub
,
2142 gen_rtx_NOT (mode
, source
)));
2145 sub
= gen_reg_rtx (mode
);
2146 emit_constant_insn (cond
,
2147 gen_rtx_SET (VOIDmode
, sub
,
2148 gen_rtx_AND (mode
, source
,
2150 emit_constant_insn (cond
,
2151 gen_rtx_SET (VOIDmode
, target
,
2152 gen_rtx_NOT (mode
, sub
)));
2159 /* See if two shifts will do 2 or more insn's worth of work. */
2160 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2162 HOST_WIDE_INT shift_mask
= ((0xffffffff
2163 << (32 - clear_sign_bit_copies
))
2166 if ((remainder
| shift_mask
) != 0xffffffff)
2170 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2171 insns
= arm_gen_constant (AND
, mode
, cond
,
2172 remainder
| shift_mask
,
2173 new_src
, source
, subtargets
, 1);
2178 rtx targ
= subtargets
? NULL_RTX
: target
;
2179 insns
= arm_gen_constant (AND
, mode
, cond
,
2180 remainder
| shift_mask
,
2181 targ
, source
, subtargets
, 0);
2187 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2188 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2190 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2191 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2197 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2199 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2201 if ((remainder
| shift_mask
) != 0xffffffff)
2205 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2207 insns
= arm_gen_constant (AND
, mode
, cond
,
2208 remainder
| shift_mask
,
2209 new_src
, source
, subtargets
, 1);
2214 rtx targ
= subtargets
? NULL_RTX
: target
;
2216 insns
= arm_gen_constant (AND
, mode
, cond
,
2217 remainder
| shift_mask
,
2218 targ
, source
, subtargets
, 0);
2224 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2225 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2227 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2228 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2240 for (i
= 0; i
< 32; i
++)
2241 if (remainder
& (1 << i
))
2244 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2245 remainder
= (~remainder
) & 0xffffffff;
2246 else if (code
== PLUS
&& num_bits_set
> 16)
2247 remainder
= (-remainder
) & 0xffffffff;
2254 /* Now try and find a way of doing the job in either two or three
2256 We start by looking for the largest block of zeros that are aligned on
2257 a 2-bit boundary, we then fill up the temps, wrapping around to the
2258 top of the word when we drop off the bottom.
2259 In the worst case this code should produce no more than four insns. */
2262 int best_consecutive_zeros
= 0;
2264 for (i
= 0; i
< 32; i
+= 2)
2266 int consecutive_zeros
= 0;
2268 if (!(remainder
& (3 << i
)))
2270 while ((i
< 32) && !(remainder
& (3 << i
)))
2272 consecutive_zeros
+= 2;
2275 if (consecutive_zeros
> best_consecutive_zeros
)
2277 best_consecutive_zeros
= consecutive_zeros
;
2278 best_start
= i
- consecutive_zeros
;
2284 /* So long as it won't require any more insns to do so, it's
2285 desirable to emit a small constant (in bits 0...9) in the last
2286 insn. This way there is more chance that it can be combined with
2287 a later addressing insn to form a pre-indexed load or store
2288 operation. Consider:
2290 *((volatile int *)0xe0000100) = 1;
2291 *((volatile int *)0xe0000110) = 2;
2293 We want this to wind up as:
2297 str rB, [rA, #0x100]
2299 str rB, [rA, #0x110]
2301 rather than having to synthesize both large constants from scratch.
2303 Therefore, we calculate how many insns would be required to emit
2304 the constant starting from `best_start', and also starting from
2305 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2306 yield a shorter sequence, we may as well use zero. */
2308 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2309 && (count_insns_for_constant (remainder
, 0) <=
2310 count_insns_for_constant (remainder
, best_start
)))
2313 /* Now start emitting the insns. */
2321 if (remainder
& (3 << (i
- 2)))
2326 temp1
= remainder
& ((0x0ff << end
)
2327 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2328 remainder
&= ~temp1
;
2332 rtx new_src
, temp1_rtx
;
2334 if (code
== SET
|| code
== MINUS
)
2336 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2337 if (can_invert
&& code
!= MINUS
)
2342 if (remainder
&& subtargets
)
2343 new_src
= gen_reg_rtx (mode
);
2348 else if (can_negate
)
2352 temp1
= trunc_int_for_mode (temp1
, mode
);
2353 temp1_rtx
= GEN_INT (temp1
);
2357 else if (code
== MINUS
)
2358 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2360 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2362 emit_constant_insn (cond
,
2363 gen_rtx_SET (VOIDmode
, new_src
,
2373 else if (code
== MINUS
)
2387 /* Canonicalize a comparison so that we are more likely to recognize it.
2388 This can be done for a few constant compares, where we can make the
2389 immediate value easier to load. */
2392 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2395 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2396 unsigned HOST_WIDE_INT maxval
;
2397 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2408 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2410 *op1
= GEN_INT (i
+ 1);
2411 return code
== GT
? GE
: LT
;
2418 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2420 *op1
= GEN_INT (i
- 1);
2421 return code
== GE
? GT
: LE
;
2427 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2428 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2430 *op1
= GEN_INT (i
+ 1);
2431 return code
== GTU
? GEU
: LTU
;
2438 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2440 *op1
= GEN_INT (i
- 1);
2441 return code
== GEU
? GTU
: LEU
;
2453 /* Define how to find the value returned by a function. */
2456 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2458 enum machine_mode mode
;
2459 int unsignedp ATTRIBUTE_UNUSED
;
2460 rtx r ATTRIBUTE_UNUSED
;
2462 mode
= TYPE_MODE (type
);
2463 /* Promote integer types. */
2464 if (INTEGRAL_TYPE_P (type
))
2465 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2467 /* Promotes small structs returned in a register to full-word size
2468 for big-endian AAPCS. */
2469 if (arm_return_in_msb (type
))
2471 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2472 if (size
% UNITS_PER_WORD
!= 0)
2474 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2475 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2479 return LIBCALL_VALUE(mode
);
2482 /* Determine the amount of memory needed to store the possible return
2483 registers of an untyped call. */
2485 arm_apply_result_size (void)
2491 if (TARGET_HARD_FLOAT_ABI
)
2495 if (TARGET_MAVERICK
)
2498 if (TARGET_IWMMXT_ABI
)
2505 /* Decide whether a type should be returned in memory (true)
2506 or in a register (false). This is called by the macro
2507 RETURN_IN_MEMORY. */
2509 arm_return_in_memory (tree type
)
2513 if (!AGGREGATE_TYPE_P (type
) &&
2514 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2515 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2516 /* All simple types are returned in registers.
2517 For AAPCS, complex types are treated the same as aggregates. */
2520 size
= int_size_in_bytes (type
);
2522 if (arm_abi
!= ARM_ABI_APCS
)
2524 /* ATPCS and later return aggregate types in memory only if they are
2525 larger than a word (or are variable size). */
2526 return (size
< 0 || size
> UNITS_PER_WORD
);
2529 /* To maximize backwards compatibility with previous versions of gcc,
2530 return vectors up to 4 words in registers. */
2531 if (TREE_CODE (type
) == VECTOR_TYPE
)
2532 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2534 /* For the arm-wince targets we choose to be compatible with Microsoft's
2535 ARM and Thumb compilers, which always return aggregates in memory. */
2537 /* All structures/unions bigger than one word are returned in memory.
2538 Also catch the case where int_size_in_bytes returns -1. In this case
2539 the aggregate is either huge or of variable size, and in either case
2540 we will want to return it via memory and not in a register. */
2541 if (size
< 0 || size
> UNITS_PER_WORD
)
2544 if (TREE_CODE (type
) == RECORD_TYPE
)
2548 /* For a struct the APCS says that we only return in a register
2549 if the type is 'integer like' and every addressable element
2550 has an offset of zero. For practical purposes this means
2551 that the structure can have at most one non bit-field element
2552 and that this element must be the first one in the structure. */
2554 /* Find the first field, ignoring non FIELD_DECL things which will
2555 have been created by C++. */
2556 for (field
= TYPE_FIELDS (type
);
2557 field
&& TREE_CODE (field
) != FIELD_DECL
;
2558 field
= TREE_CHAIN (field
))
2562 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2564 /* Check that the first field is valid for returning in a register. */
2566 /* ... Floats are not allowed */
2567 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2570 /* ... Aggregates that are not themselves valid for returning in
2571 a register are not allowed. */
2572 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2575 /* Now check the remaining fields, if any. Only bitfields are allowed,
2576 since they are not addressable. */
2577 for (field
= TREE_CHAIN (field
);
2579 field
= TREE_CHAIN (field
))
2581 if (TREE_CODE (field
) != FIELD_DECL
)
2584 if (!DECL_BIT_FIELD_TYPE (field
))
2591 if (TREE_CODE (type
) == UNION_TYPE
)
2595 /* Unions can be returned in registers if every element is
2596 integral, or can be returned in an integer register. */
2597 for (field
= TYPE_FIELDS (type
);
2599 field
= TREE_CHAIN (field
))
2601 if (TREE_CODE (field
) != FIELD_DECL
)
2604 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2607 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2613 #endif /* not ARM_WINCE */
2615 /* Return all other types in memory. */
2619 /* Indicate whether or not words of a double are in big-endian order. */
2622 arm_float_words_big_endian (void)
2624 if (TARGET_MAVERICK
)
2627 /* For FPA, float words are always big-endian. For VFP, floats words
2628 follow the memory system mode. */
2636 return (TARGET_BIG_END
? 1 : 0);
2641 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2642 for a call to a function whose data type is FNTYPE.
2643 For a library call, FNTYPE is NULL. */
2645 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2646 rtx libname ATTRIBUTE_UNUSED
,
2647 tree fndecl ATTRIBUTE_UNUSED
)
2649 /* On the ARM, the offset starts at 0. */
2650 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2651 pcum
->iwmmxt_nregs
= 0;
2652 pcum
->can_split
= true;
2654 pcum
->call_cookie
= CALL_NORMAL
;
2656 if (TARGET_LONG_CALLS
)
2657 pcum
->call_cookie
= CALL_LONG
;
2659 /* Check for long call/short call attributes. The attributes
2660 override any command line option. */
2663 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2664 pcum
->call_cookie
= CALL_SHORT
;
2665 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2666 pcum
->call_cookie
= CALL_LONG
;
2669 /* Varargs vectors are treated the same as long long.
2670 named_count avoids having to change the way arm handles 'named' */
2671 pcum
->named_count
= 0;
2674 if (TARGET_REALLY_IWMMXT
&& fntype
)
2678 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2680 fn_arg
= TREE_CHAIN (fn_arg
))
2681 pcum
->named_count
+= 1;
2683 if (! pcum
->named_count
)
2684 pcum
->named_count
= INT_MAX
;
2689 /* Return true if mode/type need doubleword alignment. */
2691 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2693 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2694 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2698 /* Determine where to put an argument to a function.
2699 Value is zero to push the argument on the stack,
2700 or a hard register in which to store the argument.
2702 MODE is the argument's machine mode.
2703 TYPE is the data type of the argument (as a tree).
2704 This is null for libcalls where that information may
2706 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2707 the preceding args and about the function being called.
2708 NAMED is nonzero if this argument is a named parameter
2709 (otherwise it is an extra parameter matching an ellipsis). */
2712 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2713 tree type
, int named
)
2717 /* Varargs vectors are treated the same as long long.
2718 named_count avoids having to change the way arm handles 'named' */
2719 if (TARGET_IWMMXT_ABI
2720 && arm_vector_mode_supported_p (mode
)
2721 && pcum
->named_count
> pcum
->nargs
+ 1)
2723 if (pcum
->iwmmxt_nregs
<= 9)
2724 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2727 pcum
->can_split
= false;
2732 /* Put doubleword aligned quantities in even register pairs. */
2734 && ARM_DOUBLEWORD_ALIGN
2735 && arm_needs_doubleword_align (mode
, type
))
2738 if (mode
== VOIDmode
)
2739 /* Compute operand 2 of the call insn. */
2740 return GEN_INT (pcum
->call_cookie
);
2742 /* Only allow splitting an arg between regs and memory if all preceding
2743 args were allocated to regs. For args passed by reference we only count
2744 the reference pointer. */
2745 if (pcum
->can_split
)
2748 nregs
= ARM_NUM_REGS2 (mode
, type
);
2750 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2753 return gen_rtx_REG (mode
, pcum
->nregs
);
2757 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2758 tree type
, bool named ATTRIBUTE_UNUSED
)
2760 int nregs
= pcum
->nregs
;
2762 if (arm_vector_mode_supported_p (mode
))
2765 if (NUM_ARG_REGS
> nregs
2766 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2768 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2773 /* Variable sized types are passed by reference. This is a GCC
2774 extension to the ARM ABI. */
2777 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2778 enum machine_mode mode ATTRIBUTE_UNUSED
,
2779 tree type
, bool named ATTRIBUTE_UNUSED
)
2781 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2784 /* Encode the current state of the #pragma [no_]long_calls. */
2787 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2788 LONG
, /* #pragma long_calls is in effect. */
2789 SHORT
/* #pragma no_long_calls is in effect. */
2792 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2795 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2797 arm_pragma_long_calls
= LONG
;
2801 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2803 arm_pragma_long_calls
= SHORT
;
2807 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2809 arm_pragma_long_calls
= OFF
;
2812 /* Table of machine attributes. */
2813 const struct attribute_spec arm_attribute_table
[] =
2815 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2816 /* Function calls made to this symbol must be done indirectly, because
2817 it may lie outside of the 26 bit addressing range of a normal function
2819 { "long_call", 0, 0, false, true, true, NULL
},
2820 /* Whereas these functions are always known to reside within the 26 bit
2821 addressing range. */
2822 { "short_call", 0, 0, false, true, true, NULL
},
2823 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2824 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2825 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2826 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2828 /* ARM/PE has three new attributes:
2830 dllexport - for exporting a function/variable that will live in a dll
2831 dllimport - for importing a function/variable from a dll
2833 Microsoft allows multiple declspecs in one __declspec, separating
2834 them with spaces. We do NOT support this. Instead, use __declspec
2837 { "dllimport", 0, 0, true, false, false, NULL
},
2838 { "dllexport", 0, 0, true, false, false, NULL
},
2839 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2840 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2841 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2842 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2843 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2845 { NULL
, 0, 0, false, false, false, NULL
}
2848 /* Handle an attribute requiring a FUNCTION_DECL;
2849 arguments as in struct attribute_spec.handler. */
2851 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2852 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2854 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2856 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2857 IDENTIFIER_POINTER (name
));
2858 *no_add_attrs
= true;
2864 /* Handle an "interrupt" or "isr" attribute;
2865 arguments as in struct attribute_spec.handler. */
2867 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2872 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2874 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2875 IDENTIFIER_POINTER (name
));
2876 *no_add_attrs
= true;
2878 /* FIXME: the argument if any is checked for type attributes;
2879 should it be checked for decl ones? */
2883 if (TREE_CODE (*node
) == FUNCTION_TYPE
2884 || TREE_CODE (*node
) == METHOD_TYPE
)
2886 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2888 warning (OPT_Wattributes
, "%qs attribute ignored",
2889 IDENTIFIER_POINTER (name
));
2890 *no_add_attrs
= true;
2893 else if (TREE_CODE (*node
) == POINTER_TYPE
2894 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2895 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2896 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2898 *node
= build_variant_type_copy (*node
);
2899 TREE_TYPE (*node
) = build_type_attribute_variant
2901 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2902 *no_add_attrs
= true;
2906 /* Possibly pass this attribute on from the type to a decl. */
2907 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2908 | (int) ATTR_FLAG_FUNCTION_NEXT
2909 | (int) ATTR_FLAG_ARRAY_NEXT
))
2911 *no_add_attrs
= true;
2912 return tree_cons (name
, args
, NULL_TREE
);
2916 warning (OPT_Wattributes
, "%qs attribute ignored",
2917 IDENTIFIER_POINTER (name
));
2925 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2926 /* Handle the "notshared" attribute. This attribute is another way of
2927 requesting hidden visibility. ARM's compiler supports
2928 "__declspec(notshared)"; we support the same thing via an
2932 arm_handle_notshared_attribute (tree
*node
,
2933 tree name ATTRIBUTE_UNUSED
,
2934 tree args ATTRIBUTE_UNUSED
,
2935 int flags ATTRIBUTE_UNUSED
,
2938 tree decl
= TYPE_NAME (*node
);
2942 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2943 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2944 *no_add_attrs
= false;
2950 /* Return 0 if the attributes for two types are incompatible, 1 if they
2951 are compatible, and 2 if they are nearly compatible (which causes a
2952 warning to be generated). */
2954 arm_comp_type_attributes (tree type1
, tree type2
)
2958 /* Check for mismatch of non-default calling convention. */
2959 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2962 /* Check for mismatched call attributes. */
2963 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2964 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2965 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2966 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2968 /* Only bother to check if an attribute is defined. */
2969 if (l1
| l2
| s1
| s2
)
2971 /* If one type has an attribute, the other must have the same attribute. */
2972 if ((l1
!= l2
) || (s1
!= s2
))
2975 /* Disallow mixed attributes. */
2976 if ((l1
& s2
) || (l2
& s1
))
2980 /* Check for mismatched ISR attribute. */
2981 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2983 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2984 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2986 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2993 /* Encode long_call or short_call attribute by prefixing
2994 symbol name in DECL with a special character FLAG. */
2996 arm_encode_call_attribute (tree decl
, int flag
)
2998 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2999 int len
= strlen (str
);
3002 /* Do not allow weak functions to be treated as short call. */
3003 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3006 newstr
= alloca (len
+ 2);
3008 strcpy (newstr
+ 1, str
);
3010 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3011 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3014 /* Assigns default attributes to newly defined type. This is used to
3015 set short_call/long_call attributes for function types of
3016 functions defined inside corresponding #pragma scopes. */
3018 arm_set_default_type_attributes (tree type
)
3020 /* Add __attribute__ ((long_call)) to all functions, when
3021 inside #pragma long_calls or __attribute__ ((short_call)),
3022 when inside #pragma no_long_calls. */
3023 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3025 tree type_attr_list
, attr_name
;
3026 type_attr_list
= TYPE_ATTRIBUTES (type
);
3028 if (arm_pragma_long_calls
== LONG
)
3029 attr_name
= get_identifier ("long_call");
3030 else if (arm_pragma_long_calls
== SHORT
)
3031 attr_name
= get_identifier ("short_call");
3035 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3036 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3040 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3041 defined within the current compilation unit. If this cannot be
3042 determined, then 0 is returned. */
3044 current_file_function_operand (rtx sym_ref
)
3046 /* This is a bit of a fib. A function will have a short call flag
3047 applied to its name if it has the short call attribute, or it has
3048 already been defined within the current compilation unit. */
3049 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3052 /* The current function is always defined within the current compilation
3053 unit. If it s a weak definition however, then this may not be the real
3054 definition of the function, and so we have to say no. */
3055 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3056 && !DECL_WEAK (current_function_decl
))
3059 /* We cannot make the determination - default to returning 0. */
3063 /* Return nonzero if a 32 bit "long_call" should be generated for
3064 this call. We generate a long_call if the function:
3066 a. has an __attribute__((long call))
3067 or b. is within the scope of a #pragma long_calls
3068 or c. the -mlong-calls command line switch has been specified
3070 1. -ffunction-sections is in effect
3071 or 2. the current function has __attribute__ ((section))
3072 or 3. the target function has __attribute__ ((section))
3074 However we do not generate a long call if the function:
3076 d. has an __attribute__ ((short_call))
3077 or e. is inside the scope of a #pragma no_long_calls
3078 or f. is defined within the current compilation unit.
3080 This function will be called by C fragments contained in the machine
3081 description file. SYM_REF and CALL_COOKIE correspond to the matched
3082 rtl operands. CALL_SYMBOL is used to distinguish between
3083 two different callers of the function. It is set to 1 in the
3084 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3085 and "call_value" patterns. This is because of the difference in the
3086 SYM_REFs passed by these patterns. */
3088 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3092 if (GET_CODE (sym_ref
) != MEM
)
3095 sym_ref
= XEXP (sym_ref
, 0);
3098 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3101 if (call_cookie
& CALL_SHORT
)
3104 if (TARGET_LONG_CALLS
)
3106 if (flag_function_sections
3107 || DECL_SECTION_NAME (current_function_decl
))
3108 /* c.3 is handled by the definition of the
3109 ARM_DECLARE_FUNCTION_SIZE macro. */
3113 if (current_file_function_operand (sym_ref
))
3116 return (call_cookie
& CALL_LONG
)
3117 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3118 || TARGET_LONG_CALLS
;
3121 /* Return nonzero if it is ok to make a tail-call to DECL. */
3123 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3125 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3127 if (cfun
->machine
->sibcall_blocked
)
3130 /* Never tailcall something for which we have no decl, or if we
3131 are in Thumb mode. */
3132 if (decl
== NULL
|| TARGET_THUMB
)
3135 /* Get the calling method. */
3136 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3137 call_type
= CALL_SHORT
;
3138 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3139 call_type
= CALL_LONG
;
3141 /* Cannot tail-call to long calls, since these are out of range of
3142 a branch instruction. However, if not compiling PIC, we know
3143 we can reach the symbol if it is in this compilation unit. */
3144 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3147 /* If we are interworking and the function is not declared static
3148 then we can't tail-call it unless we know that it exists in this
3149 compilation unit (since it might be a Thumb routine). */
3150 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3153 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3154 if (IS_INTERRUPT (arm_current_func_type ()))
3157 /* Everything else is ok. */
3162 /* Addressing mode support functions. */
3164 /* Return nonzero if X is a legitimate immediate operand when compiling
3167 legitimate_pic_operand_p (rtx x
)
3171 && (GET_CODE (x
) == SYMBOL_REF
3172 || (GET_CODE (x
) == CONST
3173 && GET_CODE (XEXP (x
, 0)) == PLUS
3174 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
3181 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3183 if (GET_CODE (orig
) == SYMBOL_REF
3184 || GET_CODE (orig
) == LABEL_REF
)
3186 #ifndef AOF_ASSEMBLER
3187 rtx pic_ref
, address
;
3194 gcc_assert (!no_new_pseudos
);
3195 reg
= gen_reg_rtx (Pmode
);
3200 #ifdef AOF_ASSEMBLER
3201 /* The AOF assembler can generate relocations for these directly, and
3202 understands that the PIC register has to be added into the offset. */
3203 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3206 address
= gen_reg_rtx (Pmode
);
3211 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3213 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3215 if ((GET_CODE (orig
) == LABEL_REF
3216 || (GET_CODE (orig
) == SYMBOL_REF
&&
3217 SYMBOL_REF_LOCAL_P (orig
)))
3219 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3222 pic_ref
= gen_const_mem (Pmode
,
3223 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3227 insn
= emit_move_insn (reg
, pic_ref
);
3229 current_function_uses_pic_offset_table
= 1;
3230 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3232 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3236 else if (GET_CODE (orig
) == CONST
)
3240 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3241 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3244 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3245 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3250 gcc_assert (!no_new_pseudos
);
3251 reg
= gen_reg_rtx (Pmode
);
3254 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3256 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3257 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3258 base
== reg
? 0 : reg
);
3260 if (GET_CODE (offset
) == CONST_INT
)
3262 /* The base register doesn't really matter, we only want to
3263 test the index for the appropriate mode. */
3264 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3266 gcc_assert (!no_new_pseudos
);
3267 offset
= force_reg (Pmode
, offset
);
3270 if (GET_CODE (offset
) == CONST_INT
)
3271 return plus_constant (base
, INTVAL (offset
));
3274 if (GET_MODE_SIZE (mode
) > 4
3275 && (GET_MODE_CLASS (mode
) == MODE_INT
3276 || TARGET_SOFT_FLOAT
))
3278 emit_insn (gen_addsi3 (reg
, base
, offset
));
3282 return gen_rtx_PLUS (Pmode
, base
, offset
);
3289 /* Find a spare low register to use during the prolog of a function. */
3292 thumb_find_work_register (unsigned long pushed_regs_mask
)
3296 /* Check the argument registers first as these are call-used. The
3297 register allocation order means that sometimes r3 might be used
3298 but earlier argument registers might not, so check them all. */
3299 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3300 if (!regs_ever_live
[reg
])
3303 /* Before going on to check the call-saved registers we can try a couple
3304 more ways of deducing that r3 is available. The first is when we are
3305 pushing anonymous arguments onto the stack and we have less than 4
3306 registers worth of fixed arguments(*). In this case r3 will be part of
3307 the variable argument list and so we can be sure that it will be
3308 pushed right at the start of the function. Hence it will be available
3309 for the rest of the prologue.
3310 (*): ie current_function_pretend_args_size is greater than 0. */
3311 if (cfun
->machine
->uses_anonymous_args
3312 && current_function_pretend_args_size
> 0)
3313 return LAST_ARG_REGNUM
;
3315 /* The other case is when we have fixed arguments but less than 4 registers
3316 worth. In this case r3 might be used in the body of the function, but
3317 it is not being used to convey an argument into the function. In theory
3318 we could just check current_function_args_size to see how many bytes are
3319 being passed in argument registers, but it seems that it is unreliable.
3320 Sometimes it will have the value 0 when in fact arguments are being
3321 passed. (See testcase execute/20021111-1.c for an example). So we also
3322 check the args_info.nregs field as well. The problem with this field is
3323 that it makes no allowances for arguments that are passed to the
3324 function but which are not used. Hence we could miss an opportunity
3325 when a function has an unused argument in r3. But it is better to be
3326 safe than to be sorry. */
3327 if (! cfun
->machine
->uses_anonymous_args
3328 && current_function_args_size
>= 0
3329 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3330 && cfun
->args_info
.nregs
< 4)
3331 return LAST_ARG_REGNUM
;
3333 /* Otherwise look for a call-saved register that is going to be pushed. */
3334 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3335 if (pushed_regs_mask
& (1 << reg
))
3338 /* Something went wrong - thumb_compute_save_reg_mask()
3339 should have arranged for a suitable register to be pushed. */
3344 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3348 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3350 #ifndef AOF_ASSEMBLER
3351 rtx l1
, pic_tmp
, pic_tmp2
, pic_rtx
;
3352 rtx global_offset_table
;
3354 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3357 gcc_assert (flag_pic
);
3359 l1
= gen_label_rtx ();
3361 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3362 /* On the ARM the PC register contains 'dot + 8' at the time of the
3363 addition, on the Thumb it is 'dot + 4'. */
3364 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3366 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3367 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3369 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3371 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3375 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3376 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
,
3377 pic_offset_table_rtx
, l1
));
3381 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3383 /* We will have pushed the pic register, so we should always be
3384 able to find a work register. */
3385 pic_tmp
= gen_rtx_REG (SImode
,
3386 thumb_find_work_register (saved_regs
));
3387 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3388 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3391 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3392 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
,
3393 pic_offset_table_rtx
, l1
));
3396 /* Need to emit this whether or not we obey regdecls,
3397 since setjmp/longjmp can cause life info to screw up. */
3398 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3399 #endif /* AOF_ASSEMBLER */
3403 /* Return nonzero if X is valid as an ARM state addressing register. */
3405 arm_address_register_rtx_p (rtx x
, int strict_p
)
3409 if (GET_CODE (x
) != REG
)
3415 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3417 return (regno
<= LAST_ARM_REGNUM
3418 || regno
>= FIRST_PSEUDO_REGISTER
3419 || regno
== FRAME_POINTER_REGNUM
3420 || regno
== ARG_POINTER_REGNUM
);
3423 /* Return TRUE if this rtx is the difference of a symbol and a label,
3424 and will reduce to a PC-relative relocation in the object file.
3425 Expressions like this can be left alone when generating PIC, rather
3426 than forced through the GOT. */
3428 pcrel_constant_p (rtx x
)
3430 if (GET_CODE (x
) == MINUS
)
3431 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3436 /* Return nonzero if X is a valid ARM state address operand. */
3438 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3442 enum rtx_code code
= GET_CODE (x
);
3444 if (arm_address_register_rtx_p (x
, strict_p
))
3447 use_ldrd
= (TARGET_LDRD
3449 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3451 if (code
== POST_INC
|| code
== PRE_DEC
3452 || ((code
== PRE_INC
|| code
== POST_DEC
)
3453 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3454 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3456 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3457 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3458 && GET_CODE (XEXP (x
, 1)) == PLUS
3459 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3461 rtx addend
= XEXP (XEXP (x
, 1), 1);
3463 /* Don't allow ldrd post increment by register because it's hard
3464 to fixup invalid register choices. */
3466 && GET_CODE (x
) == POST_MODIFY
3467 && GET_CODE (addend
) == REG
)
3470 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3471 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3474 /* After reload constants split into minipools will have addresses
3475 from a LABEL_REF. */
3476 else if (reload_completed
3477 && (code
== LABEL_REF
3479 && GET_CODE (XEXP (x
, 0)) == PLUS
3480 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3481 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3484 else if (mode
== TImode
)
3487 else if (code
== PLUS
)
3489 rtx xop0
= XEXP (x
, 0);
3490 rtx xop1
= XEXP (x
, 1);
3492 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3493 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3494 || (arm_address_register_rtx_p (xop1
, strict_p
)
3495 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3499 /* Reload currently can't handle MINUS, so disable this for now */
3500 else if (GET_CODE (x
) == MINUS
)
3502 rtx xop0
= XEXP (x
, 0);
3503 rtx xop1
= XEXP (x
, 1);
3505 return (arm_address_register_rtx_p (xop0
, strict_p
)
3506 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3510 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3511 && code
== SYMBOL_REF
3512 && CONSTANT_POOL_ADDRESS_P (x
)
3514 && symbol_mentioned_p (get_pool_constant (x
))
3515 && ! pcrel_constant_p (get_pool_constant (x
))))
3521 /* Return nonzero if INDEX is valid for an address index operand in
3524 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3527 HOST_WIDE_INT range
;
3528 enum rtx_code code
= GET_CODE (index
);
3530 /* Standard coprocessor addressing modes. */
3531 if (TARGET_HARD_FLOAT
3532 && (TARGET_FPA
|| TARGET_MAVERICK
)
3533 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3534 || (TARGET_MAVERICK
&& mode
== DImode
)))
3535 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3536 && INTVAL (index
) > -1024
3537 && (INTVAL (index
) & 3) == 0);
3539 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3540 return (code
== CONST_INT
3541 && INTVAL (index
) < 1024
3542 && INTVAL (index
) > -1024
3543 && (INTVAL (index
) & 3) == 0);
3545 if (arm_address_register_rtx_p (index
, strict_p
)
3546 && (GET_MODE_SIZE (mode
) <= 4))
3549 if (mode
== DImode
|| mode
== DFmode
)
3551 if (code
== CONST_INT
)
3553 HOST_WIDE_INT val
= INTVAL (index
);
3556 return val
> -256 && val
< 256;
3558 return val
> -4096 && val
< 4092;
3561 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3564 if (GET_MODE_SIZE (mode
) <= 4
3567 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3571 rtx xiop0
= XEXP (index
, 0);
3572 rtx xiop1
= XEXP (index
, 1);
3574 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3575 && power_of_two_operand (xiop1
, SImode
))
3576 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3577 && power_of_two_operand (xiop0
, SImode
)));
3579 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3580 || code
== ASHIFT
|| code
== ROTATERT
)
3582 rtx op
= XEXP (index
, 1);
3584 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3585 && GET_CODE (op
) == CONST_INT
3587 && INTVAL (op
) <= 31);
3591 /* For ARM v4 we may be doing a sign-extend operation during the
3595 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3601 range
= (mode
== HImode
) ? 4095 : 4096;
3603 return (code
== CONST_INT
3604 && INTVAL (index
) < range
3605 && INTVAL (index
) > -range
);
3608 /* Return nonzero if X is valid as a Thumb state base register. */
3610 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3614 if (GET_CODE (x
) != REG
)
3620 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3622 return (regno
<= LAST_LO_REGNUM
3623 || regno
> LAST_VIRTUAL_REGISTER
3624 || regno
== FRAME_POINTER_REGNUM
3625 || (GET_MODE_SIZE (mode
) >= 4
3626 && (regno
== STACK_POINTER_REGNUM
3627 || regno
>= FIRST_PSEUDO_REGISTER
3628 || x
== hard_frame_pointer_rtx
3629 || x
== arg_pointer_rtx
)));
3632 /* Return nonzero if x is a legitimate index register. This is the case
3633 for any base register that can access a QImode object. */
3635 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3637 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3640 /* Return nonzero if x is a legitimate Thumb-state address.
3642 The AP may be eliminated to either the SP or the FP, so we use the
3643 least common denominator, e.g. SImode, and offsets from 0 to 64.
3645 ??? Verify whether the above is the right approach.
3647 ??? Also, the FP may be eliminated to the SP, so perhaps that
3648 needs special handling also.
3650 ??? Look at how the mips16 port solves this problem. It probably uses
3651 better ways to solve some of these problems.
3653 Although it is not incorrect, we don't accept QImode and HImode
3654 addresses based on the frame pointer or arg pointer until the
3655 reload pass starts. This is so that eliminating such addresses
3656 into stack based ones won't produce impossible code. */
3658 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3660 /* ??? Not clear if this is right. Experiment. */
3661 if (GET_MODE_SIZE (mode
) < 4
3662 && !(reload_in_progress
|| reload_completed
)
3663 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3664 || reg_mentioned_p (arg_pointer_rtx
, x
)
3665 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3666 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3667 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3668 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3671 /* Accept any base register. SP only in SImode or larger. */
3672 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3675 /* This is PC relative data before arm_reorg runs. */
3676 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3677 && GET_CODE (x
) == SYMBOL_REF
3678 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3681 /* This is PC relative data after arm_reorg runs. */
3682 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3683 && (GET_CODE (x
) == LABEL_REF
3684 || (GET_CODE (x
) == CONST
3685 && GET_CODE (XEXP (x
, 0)) == PLUS
3686 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3687 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3690 /* Post-inc indexing only supported for SImode and larger. */
3691 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3692 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3695 else if (GET_CODE (x
) == PLUS
)
3697 /* REG+REG address can be any two index registers. */
3698 /* We disallow FRAME+REG addressing since we know that FRAME
3699 will be replaced with STACK, and SP relative addressing only
3700 permits SP+OFFSET. */
3701 if (GET_MODE_SIZE (mode
) <= 4
3702 && XEXP (x
, 0) != frame_pointer_rtx
3703 && XEXP (x
, 1) != frame_pointer_rtx
3704 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3705 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3708 /* REG+const has 5-7 bit offset for non-SP registers. */
3709 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3710 || XEXP (x
, 0) == arg_pointer_rtx
)
3711 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3712 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3715 /* REG+const has 10 bit offset for SP, but only SImode and
3716 larger is supported. */
3717 /* ??? Should probably check for DI/DFmode overflow here
3718 just like GO_IF_LEGITIMATE_OFFSET does. */
3719 else if (GET_CODE (XEXP (x
, 0)) == REG
3720 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3721 && GET_MODE_SIZE (mode
) >= 4
3722 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3723 && INTVAL (XEXP (x
, 1)) >= 0
3724 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3725 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3728 else if (GET_CODE (XEXP (x
, 0)) == REG
3729 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3730 && GET_MODE_SIZE (mode
) >= 4
3731 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3732 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3736 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3737 && GET_MODE_SIZE (mode
) == 4
3738 && GET_CODE (x
) == SYMBOL_REF
3739 && CONSTANT_POOL_ADDRESS_P (x
)
3741 && symbol_mentioned_p (get_pool_constant (x
))
3742 && ! pcrel_constant_p (get_pool_constant (x
))))
3748 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3749 instruction of mode MODE. */
3751 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3753 switch (GET_MODE_SIZE (mode
))
3756 return val
>= 0 && val
< 32;
3759 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3763 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3768 /* Build the SYMBOL_REF for __tls_get_addr. */
3770 static GTY(()) rtx tls_get_addr_libfunc
;
3773 get_tls_get_addr (void)
3775 if (!tls_get_addr_libfunc
)
3776 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3777 return tls_get_addr_libfunc
;
3781 arm_load_tp (rtx target
)
3784 target
= gen_reg_rtx (SImode
);
3788 /* Can return in any reg. */
3789 emit_insn (gen_load_tp_hard (target
));
3793 /* Always returned in r0. Immediately copy the result into a pseudo,
3794 otherwise other uses of r0 (e.g. setting up function arguments) may
3795 clobber the value. */
3799 emit_insn (gen_load_tp_soft ());
3801 tmp
= gen_rtx_REG (SImode
, 0);
3802 emit_move_insn (target
, tmp
);
3808 load_tls_operand (rtx x
, rtx reg
)
3812 if (reg
== NULL_RTX
)
3813 reg
= gen_reg_rtx (SImode
);
3815 tmp
= gen_rtx_CONST (SImode
, x
);
3817 emit_move_insn (reg
, tmp
);
3823 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3825 rtx insns
, label
, sum
;
3829 label
= gen_label_rtx ();
3830 sum
= gen_rtx_UNSPEC (Pmode
,
3831 gen_rtvec (4, x
, GEN_INT (reloc
),
3832 gen_rtx_LABEL_REF (Pmode
, label
),
3833 GEN_INT (TARGET_ARM
? 8 : 4)),
3835 reg
= load_tls_operand (sum
, reg
);
3838 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, label
));
3840 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, label
));
3842 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3843 Pmode
, 1, reg
, Pmode
);
3845 insns
= get_insns ();
3852 legitimize_tls_address (rtx x
, rtx reg
)
3854 rtx dest
, tp
, label
, sum
, insns
, ret
, eqv
, addend
;
3855 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3859 case TLS_MODEL_GLOBAL_DYNAMIC
:
3860 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3861 dest
= gen_reg_rtx (Pmode
);
3862 emit_libcall_block (insns
, dest
, ret
, x
);
3865 case TLS_MODEL_LOCAL_DYNAMIC
:
3866 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3868 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3869 share the LDM result with other LD model accesses. */
3870 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3872 dest
= gen_reg_rtx (Pmode
);
3873 emit_libcall_block (insns
, dest
, ret
, x
);
3875 /* Load the addend. */
3876 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3878 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3879 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3881 case TLS_MODEL_INITIAL_EXEC
:
3882 label
= gen_label_rtx ();
3883 sum
= gen_rtx_UNSPEC (Pmode
,
3884 gen_rtvec (4, x
, GEN_INT (TLS_IE32
),
3885 gen_rtx_LABEL_REF (Pmode
, label
),
3886 GEN_INT (TARGET_ARM
? 8 : 4)),
3888 reg
= load_tls_operand (sum
, reg
);
3891 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, label
));
3894 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, label
));
3895 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3898 tp
= arm_load_tp (NULL_RTX
);
3900 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3902 case TLS_MODEL_LOCAL_EXEC
:
3903 tp
= arm_load_tp (NULL_RTX
);
3905 reg
= gen_rtx_UNSPEC (Pmode
,
3906 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3908 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3910 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3917 /* Try machine-dependent ways of modifying an illegitimate address
3918 to be legitimate. If we find one, return the new, valid address. */
3920 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3922 if (arm_tls_symbol_p (x
))
3923 return legitimize_tls_address (x
, NULL_RTX
);
3925 if (GET_CODE (x
) == PLUS
)
3927 rtx xop0
= XEXP (x
, 0);
3928 rtx xop1
= XEXP (x
, 1);
3930 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3931 xop0
= force_reg (SImode
, xop0
);
3933 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3934 xop1
= force_reg (SImode
, xop1
);
3936 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3937 && GET_CODE (xop1
) == CONST_INT
)
3939 HOST_WIDE_INT n
, low_n
;
3943 /* VFP addressing modes actually allow greater offsets, but for
3944 now we just stick with the lowest common denominator. */
3946 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3958 low_n
= ((mode
) == TImode
? 0
3959 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3963 base_reg
= gen_reg_rtx (SImode
);
3964 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3965 GEN_INT (n
)), NULL_RTX
);
3966 emit_move_insn (base_reg
, val
);
3967 x
= (low_n
== 0 ? base_reg
3968 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3970 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3971 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3974 /* XXX We don't allow MINUS any more -- see comment in
3975 arm_legitimate_address_p (). */
3976 else if (GET_CODE (x
) == MINUS
)
3978 rtx xop0
= XEXP (x
, 0);
3979 rtx xop1
= XEXP (x
, 1);
3981 if (CONSTANT_P (xop0
))
3982 xop0
= force_reg (SImode
, xop0
);
3984 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3985 xop1
= force_reg (SImode
, xop1
);
3987 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3988 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3991 /* Make sure to take full advantage of the pre-indexed addressing mode
3992 with absolute addresses which often allows for the base register to
3993 be factorized for multiple adjacent memory references, and it might
3994 even allows for the mini pool to be avoided entirely. */
3995 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
3998 HOST_WIDE_INT mask
, base
, index
;
4001 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4002 use a 8 bit index. So let's use a 12 bit index for SImode only and
4003 hope that arm_gen_constant will enable ldrb to use more bits. */
4004 bits
= (mode
== SImode
) ? 12 : 8;
4005 mask
= (1 << bits
) - 1;
4006 base
= INTVAL (x
) & ~mask
;
4007 index
= INTVAL (x
) & mask
;
4008 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4010 /* It'll most probably be more efficient to generate the base
4011 with more bits set and use a negative index instead. */
4015 base_reg
= force_reg (SImode
, GEN_INT (base
));
4016 x
= gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (index
));
4021 /* We need to find and carefully transform any SYMBOL and LABEL
4022 references; so go back to the original address expression. */
4023 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4025 if (new_x
!= orig_x
)
4033 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4034 to be legitimate. If we find one, return the new, valid address. */
4036 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4038 if (arm_tls_symbol_p (x
))
4039 return legitimize_tls_address (x
, NULL_RTX
);
4041 if (GET_CODE (x
) == PLUS
4042 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4043 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4044 || INTVAL (XEXP (x
, 1)) < 0))
4046 rtx xop0
= XEXP (x
, 0);
4047 rtx xop1
= XEXP (x
, 1);
4048 HOST_WIDE_INT offset
= INTVAL (xop1
);
4050 /* Try and fold the offset into a biasing of the base register and
4051 then offsetting that. Don't do this when optimizing for space
4052 since it can cause too many CSEs. */
4053 if (optimize_size
&& offset
>= 0
4054 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4056 HOST_WIDE_INT delta
;
4059 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4060 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4061 delta
= 31 * GET_MODE_SIZE (mode
);
4063 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4065 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4067 x
= plus_constant (xop0
, delta
);
4069 else if (offset
< 0 && offset
> -256)
4070 /* Small negative offsets are best done with a subtract before the
4071 dereference, forcing these into a register normally takes two
4073 x
= force_operand (x
, NULL_RTX
);
4076 /* For the remaining cases, force the constant into a register. */
4077 xop1
= force_reg (SImode
, xop1
);
4078 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4081 else if (GET_CODE (x
) == PLUS
4082 && s_register_operand (XEXP (x
, 1), SImode
)
4083 && !s_register_operand (XEXP (x
, 0), SImode
))
4085 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4087 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4092 /* We need to find and carefully transform any SYMBOL and LABEL
4093 references; so go back to the original address expression. */
4094 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4096 if (new_x
!= orig_x
)
4104 thumb_legitimize_reload_address (rtx
*x_p
,
4105 enum machine_mode mode
,
4106 int opnum
, int type
,
4107 int ind_levels ATTRIBUTE_UNUSED
)
4111 if (GET_CODE (x
) == PLUS
4112 && GET_MODE_SIZE (mode
) < 4
4113 && REG_P (XEXP (x
, 0))
4114 && XEXP (x
, 0) == stack_pointer_rtx
4115 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4116 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4121 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4122 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4126 /* If both registers are hi-regs, then it's better to reload the
4127 entire expression rather than each register individually. That
4128 only requires one reload register rather than two. */
4129 if (GET_CODE (x
) == PLUS
4130 && REG_P (XEXP (x
, 0))
4131 && REG_P (XEXP (x
, 1))
4132 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4133 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4138 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4139 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4146 /* Test for various thread-local symbols. */
4148 /* Return TRUE if X is a thread-local symbol. */
4151 arm_tls_symbol_p (rtx x
)
4153 if (! TARGET_HAVE_TLS
)
4156 if (GET_CODE (x
) != SYMBOL_REF
)
4159 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4162 /* Helper for arm_tls_referenced_p. */
4165 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4167 if (GET_CODE (*x
) == SYMBOL_REF
)
4168 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4170 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4171 TLS offsets, not real symbol references. */
4172 if (GET_CODE (*x
) == UNSPEC
4173 && XINT (*x
, 1) == UNSPEC_TLS
)
4179 /* Return TRUE if X contains any TLS symbol references. */
4182 arm_tls_referenced_p (rtx x
)
4184 if (! TARGET_HAVE_TLS
)
4187 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4190 #define REG_OR_SUBREG_REG(X) \
4191 (GET_CODE (X) == REG \
4192 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4194 #define REG_OR_SUBREG_RTX(X) \
4195 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4197 #ifndef COSTS_N_INSNS
4198 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4201 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4203 enum machine_mode mode
= GET_MODE (x
);
4216 return COSTS_N_INSNS (1);
4219 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4222 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4229 return COSTS_N_INSNS (2) + cycles
;
4231 return COSTS_N_INSNS (1) + 16;
4234 return (COSTS_N_INSNS (1)
4235 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4236 + GET_CODE (SET_DEST (x
)) == MEM
));
4241 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4243 if (thumb_shiftable_const (INTVAL (x
)))
4244 return COSTS_N_INSNS (2);
4245 return COSTS_N_INSNS (3);
4247 else if ((outer
== PLUS
|| outer
== COMPARE
)
4248 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4250 else if (outer
== AND
4251 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4252 return COSTS_N_INSNS (1);
4253 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4254 || outer
== LSHIFTRT
)
4256 return COSTS_N_INSNS (2);
4262 return COSTS_N_INSNS (3);
4280 /* XXX another guess. */
4281 /* Memory costs quite a lot for the first word, but subsequent words
4282 load at the equivalent of a single insn each. */
4283 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4284 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4289 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4294 /* XXX still guessing. */
4295 switch (GET_MODE (XEXP (x
, 0)))
4298 return (1 + (mode
== DImode
? 4 : 0)
4299 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4302 return (4 + (mode
== DImode
? 4 : 0)
4303 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4306 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4318 /* Worker routine for arm_rtx_costs. */
4320 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4322 enum machine_mode mode
= GET_MODE (x
);
4323 enum rtx_code subcode
;
4329 /* Memory costs quite a lot for the first word, but subsequent words
4330 load at the equivalent of a single insn each. */
4331 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4332 + (GET_CODE (x
) == SYMBOL_REF
4333 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4339 return optimize_size
? COSTS_N_INSNS (2) : 100;
4342 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4349 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4351 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4352 + ((GET_CODE (XEXP (x
, 0)) == REG
4353 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4354 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4356 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4357 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4358 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4360 + ((GET_CODE (XEXP (x
, 1)) == REG
4361 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4362 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4363 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4368 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4369 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4370 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4371 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4374 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4375 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4376 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4377 && arm_const_double_rtx (XEXP (x
, 1))))
4379 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4380 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4381 && arm_const_double_rtx (XEXP (x
, 0))))
4384 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4385 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4386 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4387 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4388 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4389 || subcode
== ROTATE
|| subcode
== ROTATERT
4391 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4392 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4393 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4394 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4395 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4396 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4397 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4402 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4403 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4404 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4405 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4406 && arm_const_double_rtx (XEXP (x
, 1))))
4410 case AND
: case XOR
: case IOR
:
4413 /* Normally the frame registers will be spilt into reg+const during
4414 reload, so it is a bad idea to combine them with other instructions,
4415 since then they might not be moved outside of loops. As a compromise
4416 we allow integration with ops that have a constant as their second
4418 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4419 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4420 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4421 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4422 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4426 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4427 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4428 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4429 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4432 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4433 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4434 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4435 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4436 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4439 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4440 return (1 + extra_cost
4441 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4442 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4443 || subcode
== ROTATE
|| subcode
== ROTATERT
4445 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4446 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4447 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4448 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4449 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4450 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4456 /* This should have been handled by the CPU specific routines. */
4460 if (arm_arch3m
&& mode
== SImode
4461 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4462 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4463 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4464 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4465 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4466 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4471 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4472 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4476 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4478 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4481 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4489 return 4 + (mode
== DImode
? 4 : 0);
4492 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4493 return (4 + (mode
== DImode
? 4 : 0)
4494 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4497 switch (GET_MODE (XEXP (x
, 0)))
4500 return (1 + (mode
== DImode
? 4 : 0)
4501 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4504 return (4 + (mode
== DImode
? 4 : 0)
4505 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4508 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4523 if (const_ok_for_arm (INTVAL (x
)))
4524 return outer
== SET
? 2 : -1;
4525 else if (outer
== AND
4526 && const_ok_for_arm (~INTVAL (x
)))
4528 else if ((outer
== COMPARE
4529 || outer
== PLUS
|| outer
== MINUS
)
4530 && const_ok_for_arm (-INTVAL (x
)))
4541 if (arm_const_double_rtx (x
))
4542 return outer
== SET
? 2 : -1;
4543 else if ((outer
== COMPARE
|| outer
== PLUS
)
4544 && neg_const_double_rtx_ok_for_fpa (x
))
4553 /* RTX costs when optimizing for size. */
4555 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4557 enum machine_mode mode
= GET_MODE (x
);
4561 /* XXX TBD. For now, use the standard costs. */
4562 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4569 /* A memory access costs 1 insn if the mode is small, or the address is
4570 a single register, otherwise it costs one insn per word. */
4571 if (REG_P (XEXP (x
, 0)))
4572 *total
= COSTS_N_INSNS (1);
4574 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4581 /* Needs a libcall, so it costs about this. */
4582 *total
= COSTS_N_INSNS (2);
4586 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4588 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4596 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4598 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4601 else if (mode
== SImode
)
4603 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4604 /* Slightly disparage register shifts, but not by much. */
4605 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4606 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4610 /* Needs a libcall. */
4611 *total
= COSTS_N_INSNS (2);
4615 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4617 *total
= COSTS_N_INSNS (1);
4623 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4624 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4626 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4627 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4628 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4629 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4630 || subcode1
== ASHIFTRT
)
4632 /* It's just the cost of the two operands. */
4637 *total
= COSTS_N_INSNS (1);
4641 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4645 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4647 *total
= COSTS_N_INSNS (1);
4652 case AND
: case XOR
: case IOR
:
4655 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4657 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4658 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4659 || (code
== AND
&& subcode
== NOT
))
4661 /* It's just the cost of the two operands. */
4667 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4671 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4675 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4676 *total
= COSTS_N_INSNS (1);
4679 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4688 if (cc_register (XEXP (x
, 0), VOIDmode
))
4691 *total
= COSTS_N_INSNS (1);
4695 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4696 *total
= COSTS_N_INSNS (1);
4698 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4703 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4705 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4706 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4709 *total
+= COSTS_N_INSNS (1);
4714 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4716 switch (GET_MODE (XEXP (x
, 0)))
4719 *total
+= COSTS_N_INSNS (1);
4723 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4729 *total
+= COSTS_N_INSNS (2);
4734 *total
+= COSTS_N_INSNS (1);
4739 if (const_ok_for_arm (INTVAL (x
)))
4740 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4741 else if (const_ok_for_arm (~INTVAL (x
)))
4742 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4743 else if (const_ok_for_arm (-INTVAL (x
)))
4745 if (outer_code
== COMPARE
|| outer_code
== PLUS
4746 || outer_code
== MINUS
)
4749 *total
= COSTS_N_INSNS (1);
4752 *total
= COSTS_N_INSNS (2);
4758 *total
= COSTS_N_INSNS (2);
4762 *total
= COSTS_N_INSNS (4);
4766 if (mode
!= VOIDmode
)
4767 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4769 *total
= COSTS_N_INSNS (4); /* How knows? */
4774 /* RTX costs for cores with a slow MUL implementation. */
4777 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4779 enum machine_mode mode
= GET_MODE (x
);
4783 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4790 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4797 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4799 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4800 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4801 int cost
, const_ok
= const_ok_for_arm (i
);
4802 int j
, booth_unit_size
;
4804 /* Tune as appropriate. */
4805 cost
= const_ok
? 4 : 8;
4806 booth_unit_size
= 2;
4807 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4809 i
>>= booth_unit_size
;
4817 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4818 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4822 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4828 /* RTX cost for cores with a fast multiply unit (M variants). */
4831 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4833 enum machine_mode mode
= GET_MODE (x
);
4837 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4844 /* There is no point basing this on the tuning, since it is always the
4845 fast variant if it exists at all. */
4847 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4848 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4849 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4856 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4863 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4865 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4866 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4867 int cost
, const_ok
= const_ok_for_arm (i
);
4868 int j
, booth_unit_size
;
4870 /* Tune as appropriate. */
4871 cost
= const_ok
? 4 : 8;
4872 booth_unit_size
= 8;
4873 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4875 i
>>= booth_unit_size
;
4883 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4884 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4888 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4894 /* RTX cost for XScale CPUs. */
4897 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4899 enum machine_mode mode
= GET_MODE (x
);
4903 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4910 /* There is no point basing this on the tuning, since it is always the
4911 fast variant if it exists at all. */
4913 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4914 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4915 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4922 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4929 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4931 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4932 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4933 int cost
, const_ok
= const_ok_for_arm (i
);
4934 unsigned HOST_WIDE_INT masked_const
;
4936 /* The cost will be related to two insns.
4937 First a load of the constant (MOV or LDR), then a multiply. */
4940 cost
+= 1; /* LDR is probably more expensive because
4941 of longer result latency. */
4942 masked_const
= i
& 0xffff8000;
4943 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4945 masked_const
= i
& 0xf8000000;
4946 if (masked_const
== 0 || masked_const
== 0xf8000000)
4955 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4956 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4960 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4961 will stall until the multiplication is complete. */
4962 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4963 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4965 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4969 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4975 /* RTX costs for 9e (and later) cores. */
4978 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4980 enum machine_mode mode
= GET_MODE (x
);
4989 *total
= COSTS_N_INSNS (3);
4993 *total
= thumb_rtx_costs (x
, code
, outer_code
);
5001 /* There is no point basing this on the tuning, since it is always the
5002 fast variant if it exists at all. */
5004 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5005 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5006 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5013 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5030 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5031 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5035 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5039 /* All address computations that can be done are free, but rtx cost returns
5040 the same for practically all of them. So we weight the different types
5041 of address here in the order (most pref first):
5042 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5044 arm_arm_address_cost (rtx x
)
5046 enum rtx_code c
= GET_CODE (x
);
5048 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5050 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5053 if (c
== PLUS
|| c
== MINUS
)
5055 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5058 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5068 arm_thumb_address_cost (rtx x
)
5070 enum rtx_code c
= GET_CODE (x
);
5075 && GET_CODE (XEXP (x
, 0)) == REG
5076 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5083 arm_address_cost (rtx x
)
5085 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5089 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5093 /* Some true dependencies can have a higher cost depending
5094 on precisely how certain input operands are used. */
5096 && REG_NOTE_KIND (link
) == 0
5097 && recog_memoized (insn
) >= 0
5098 && recog_memoized (dep
) >= 0)
5100 int shift_opnum
= get_attr_shift (insn
);
5101 enum attr_type attr_type
= get_attr_type (dep
);
5103 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5104 operand for INSN. If we have a shifted input operand and the
5105 instruction we depend on is another ALU instruction, then we may
5106 have to account for an additional stall. */
5107 if (shift_opnum
!= 0
5108 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5110 rtx shifted_operand
;
5113 /* Get the shifted operand. */
5114 extract_insn (insn
);
5115 shifted_operand
= recog_data
.operand
[shift_opnum
];
5117 /* Iterate over all the operands in DEP. If we write an operand
5118 that overlaps with SHIFTED_OPERAND, then we have increase the
5119 cost of this dependency. */
5121 preprocess_constraints ();
5122 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5124 /* We can ignore strict inputs. */
5125 if (recog_data
.operand_type
[opno
] == OP_IN
)
5128 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5135 /* XXX This is not strictly true for the FPA. */
5136 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5137 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5140 /* Call insns don't incur a stall, even if they follow a load. */
5141 if (REG_NOTE_KIND (link
) == 0
5142 && GET_CODE (insn
) == CALL_INSN
)
5145 if ((i_pat
= single_set (insn
)) != NULL
5146 && GET_CODE (SET_SRC (i_pat
)) == MEM
5147 && (d_pat
= single_set (dep
)) != NULL
5148 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5150 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5151 /* This is a load after a store, there is no conflict if the load reads
5152 from a cached area. Assume that loads from the stack, and from the
5153 constant pool are cached, and that others will miss. This is a
5156 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5157 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5158 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5159 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5166 static int fp_consts_inited
= 0;
5168 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5169 static const char * const strings_fp
[8] =
5172 "4", "5", "0.5", "10"
5175 static REAL_VALUE_TYPE values_fp
[8];
5178 init_fp_table (void)
5184 fp_consts_inited
= 1;
5186 fp_consts_inited
= 8;
5188 for (i
= 0; i
< fp_consts_inited
; i
++)
5190 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5195 /* Return TRUE if rtx X is a valid immediate FP constant. */
5197 arm_const_double_rtx (rtx x
)
5202 if (!fp_consts_inited
)
5205 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5206 if (REAL_VALUE_MINUS_ZERO (r
))
5209 for (i
= 0; i
< fp_consts_inited
; i
++)
5210 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5216 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5218 neg_const_double_rtx_ok_for_fpa (rtx x
)
5223 if (!fp_consts_inited
)
5226 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5227 r
= REAL_VALUE_NEGATE (r
);
5228 if (REAL_VALUE_MINUS_ZERO (r
))
5231 for (i
= 0; i
< 8; i
++)
5232 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5238 /* Predicates for `match_operand' and `match_operator'. */
5240 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5242 cirrus_memory_offset (rtx op
)
5244 /* Reject eliminable registers. */
5245 if (! (reload_in_progress
|| reload_completed
)
5246 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5247 || reg_mentioned_p (arg_pointer_rtx
, op
)
5248 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5249 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5250 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5251 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5254 if (GET_CODE (op
) == MEM
)
5260 /* Match: (mem (reg)). */
5261 if (GET_CODE (ind
) == REG
)
5267 if (GET_CODE (ind
) == PLUS
5268 && GET_CODE (XEXP (ind
, 0)) == REG
5269 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5270 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5277 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5278 WB if true if writeback address modes are allowed. */
5281 arm_coproc_mem_operand (rtx op
, bool wb
)
5285 /* Reject eliminable registers. */
5286 if (! (reload_in_progress
|| reload_completed
)
5287 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5288 || reg_mentioned_p (arg_pointer_rtx
, op
)
5289 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5290 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5291 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5292 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5295 /* Constants are converted into offsets from labels. */
5296 if (GET_CODE (op
) != MEM
)
5301 if (reload_completed
5302 && (GET_CODE (ind
) == LABEL_REF
5303 || (GET_CODE (ind
) == CONST
5304 && GET_CODE (XEXP (ind
, 0)) == PLUS
5305 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5306 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5309 /* Match: (mem (reg)). */
5310 if (GET_CODE (ind
) == REG
)
5311 return arm_address_register_rtx_p (ind
, 0);
5313 /* Autoincremment addressing modes. */
5315 && (GET_CODE (ind
) == PRE_INC
5316 || GET_CODE (ind
) == POST_INC
5317 || GET_CODE (ind
) == PRE_DEC
5318 || GET_CODE (ind
) == POST_DEC
))
5319 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5322 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5323 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5324 && GET_CODE (XEXP (ind
, 1)) == PLUS
5325 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5326 ind
= XEXP (ind
, 1);
5331 if (GET_CODE (ind
) == PLUS
5332 && GET_CODE (XEXP (ind
, 0)) == REG
5333 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5334 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5335 && INTVAL (XEXP (ind
, 1)) > -1024
5336 && INTVAL (XEXP (ind
, 1)) < 1024
5337 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5343 /* Return true if X is a register that will be eliminated later on. */
5345 arm_eliminable_register (rtx x
)
5347 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5348 || REGNO (x
) == ARG_POINTER_REGNUM
5349 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5350 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5353 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5354 VFP registers. Otherwise return NO_REGS. */
5357 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5359 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5362 return GENERAL_REGS
;
5365 /* Values which must be returned in the most-significant end of the return
5369 arm_return_in_msb (tree valtype
)
5371 return (TARGET_AAPCS_BASED
5373 && (AGGREGATE_TYPE_P (valtype
)
5374 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5377 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5378 Use by the Cirrus Maverick code which has to workaround
5379 a hardware bug triggered by such instructions. */
5381 arm_memory_load_p (rtx insn
)
5383 rtx body
, lhs
, rhs
;;
5385 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5388 body
= PATTERN (insn
);
5390 if (GET_CODE (body
) != SET
)
5393 lhs
= XEXP (body
, 0);
5394 rhs
= XEXP (body
, 1);
5396 lhs
= REG_OR_SUBREG_RTX (lhs
);
5398 /* If the destination is not a general purpose
5399 register we do not have to worry. */
5400 if (GET_CODE (lhs
) != REG
5401 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5404 /* As well as loads from memory we also have to react
5405 to loads of invalid constants which will be turned
5406 into loads from the minipool. */
5407 return (GET_CODE (rhs
) == MEM
5408 || GET_CODE (rhs
) == SYMBOL_REF
5409 || note_invalid_constants (insn
, -1, false));
5412 /* Return TRUE if INSN is a Cirrus instruction. */
5414 arm_cirrus_insn_p (rtx insn
)
5416 enum attr_cirrus attr
;
5418 /* get_attr cannot accept USE or CLOBBER. */
5420 || GET_CODE (insn
) != INSN
5421 || GET_CODE (PATTERN (insn
)) == USE
5422 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5425 attr
= get_attr_cirrus (insn
);
5427 return attr
!= CIRRUS_NOT
;
5430 /* Cirrus reorg for invalid instruction combinations. */
5432 cirrus_reorg (rtx first
)
5434 enum attr_cirrus attr
;
5435 rtx body
= PATTERN (first
);
5439 /* Any branch must be followed by 2 non Cirrus instructions. */
5440 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5443 t
= next_nonnote_insn (first
);
5445 if (arm_cirrus_insn_p (t
))
5448 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5452 emit_insn_after (gen_nop (), first
);
5457 /* (float (blah)) is in parallel with a clobber. */
5458 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5459 body
= XVECEXP (body
, 0, 0);
5461 if (GET_CODE (body
) == SET
)
5463 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5465 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5466 be followed by a non Cirrus insn. */
5467 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5469 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5470 emit_insn_after (gen_nop (), first
);
5474 else if (arm_memory_load_p (first
))
5476 unsigned int arm_regno
;
5478 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5479 ldr/cfmv64hr combination where the Rd field is the same
5480 in both instructions must be split with a non Cirrus
5487 /* Get Arm register number for ldr insn. */
5488 if (GET_CODE (lhs
) == REG
)
5489 arm_regno
= REGNO (lhs
);
5492 gcc_assert (GET_CODE (rhs
) == REG
);
5493 arm_regno
= REGNO (rhs
);
5497 first
= next_nonnote_insn (first
);
5499 if (! arm_cirrus_insn_p (first
))
5502 body
= PATTERN (first
);
5504 /* (float (blah)) is in parallel with a clobber. */
5505 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5506 body
= XVECEXP (body
, 0, 0);
5508 if (GET_CODE (body
) == FLOAT
)
5509 body
= XEXP (body
, 0);
5511 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5512 && GET_CODE (XEXP (body
, 1)) == REG
5513 && arm_regno
== REGNO (XEXP (body
, 1)))
5514 emit_insn_after (gen_nop (), first
);
5520 /* get_attr cannot accept USE or CLOBBER. */
5522 || GET_CODE (first
) != INSN
5523 || GET_CODE (PATTERN (first
)) == USE
5524 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5527 attr
= get_attr_cirrus (first
);
5529 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5530 must be followed by a non-coprocessor instruction. */
5531 if (attr
== CIRRUS_COMPARE
)
5535 t
= next_nonnote_insn (first
);
5537 if (arm_cirrus_insn_p (t
))
5540 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5544 emit_insn_after (gen_nop (), first
);
5550 /* Return TRUE if X references a SYMBOL_REF. */
5552 symbol_mentioned_p (rtx x
)
5557 if (GET_CODE (x
) == SYMBOL_REF
)
5560 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5561 are constant offsets, not symbols. */
5562 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5565 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5567 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5573 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5574 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5577 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5584 /* Return TRUE if X references a LABEL_REF. */
5586 label_mentioned_p (rtx x
)
5591 if (GET_CODE (x
) == LABEL_REF
)
5594 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5595 instruction, but they are constant offsets, not symbols. */
5596 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5599 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5600 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5606 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5607 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5610 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5618 tls_mentioned_p (rtx x
)
5620 switch (GET_CODE (x
))
5623 return tls_mentioned_p (XEXP (x
, 0));
5626 if (XINT (x
, 1) == UNSPEC_TLS
)
5634 /* Must not copy a SET whose source operand is PC-relative. */
5637 arm_cannot_copy_insn_p (rtx insn
)
5639 rtx pat
= PATTERN (insn
);
5641 if (GET_CODE (pat
) == PARALLEL
5642 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5644 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5646 if (GET_CODE (rhs
) == UNSPEC
5647 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5650 if (GET_CODE (rhs
) == MEM
5651 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5652 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5662 enum rtx_code code
= GET_CODE (x
);
5679 /* Return 1 if memory locations are adjacent. */
5681 adjacent_mem_locations (rtx a
, rtx b
)
5683 /* We don't guarantee to preserve the order of these memory refs. */
5684 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5687 if ((GET_CODE (XEXP (a
, 0)) == REG
5688 || (GET_CODE (XEXP (a
, 0)) == PLUS
5689 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5690 && (GET_CODE (XEXP (b
, 0)) == REG
5691 || (GET_CODE (XEXP (b
, 0)) == PLUS
5692 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5694 HOST_WIDE_INT val0
= 0, val1
= 0;
5698 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5700 reg0
= XEXP (XEXP (a
, 0), 0);
5701 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5706 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5708 reg1
= XEXP (XEXP (b
, 0), 0);
5709 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5714 /* Don't accept any offset that will require multiple
5715 instructions to handle, since this would cause the
5716 arith_adjacentmem pattern to output an overlong sequence. */
5717 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5720 /* Don't allow an eliminable register: register elimination can make
5721 the offset too large. */
5722 if (arm_eliminable_register (reg0
))
5725 val_diff
= val1
- val0
;
5729 /* If the target has load delay slots, then there's no benefit
5730 to using an ldm instruction unless the offset is zero and
5731 we are optimizing for size. */
5732 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5733 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5734 && (val_diff
== 4 || val_diff
== -4));
5737 return ((REGNO (reg0
) == REGNO (reg1
))
5738 && (val_diff
== 4 || val_diff
== -4));
5745 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5746 HOST_WIDE_INT
*load_offset
)
5748 int unsorted_regs
[4];
5749 HOST_WIDE_INT unsorted_offsets
[4];
5754 /* Can only handle 2, 3, or 4 insns at present,
5755 though could be easily extended if required. */
5756 gcc_assert (nops
>= 2 && nops
<= 4);
5758 /* Loop over the operands and check that the memory references are
5759 suitable (i.e. immediate offsets from the same base register). At
5760 the same time, extract the target register, and the memory
5762 for (i
= 0; i
< nops
; i
++)
5767 /* Convert a subreg of a mem into the mem itself. */
5768 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5769 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5771 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5773 /* Don't reorder volatile memory references; it doesn't seem worth
5774 looking for the case where the order is ok anyway. */
5775 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5778 offset
= const0_rtx
;
5780 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5781 || (GET_CODE (reg
) == SUBREG
5782 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5783 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5784 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5786 || (GET_CODE (reg
) == SUBREG
5787 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5788 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5793 base_reg
= REGNO (reg
);
5794 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5795 ? REGNO (operands
[i
])
5796 : REGNO (SUBREG_REG (operands
[i
])));
5801 if (base_reg
!= (int) REGNO (reg
))
5802 /* Not addressed from the same base register. */
5805 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5806 ? REGNO (operands
[i
])
5807 : REGNO (SUBREG_REG (operands
[i
])));
5808 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5812 /* If it isn't an integer register, or if it overwrites the
5813 base register but isn't the last insn in the list, then
5814 we can't do this. */
5815 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5816 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5819 unsorted_offsets
[i
] = INTVAL (offset
);
5822 /* Not a suitable memory address. */
5826 /* All the useful information has now been extracted from the
5827 operands into unsorted_regs and unsorted_offsets; additionally,
5828 order[0] has been set to the lowest numbered register in the
5829 list. Sort the registers into order, and check that the memory
5830 offsets are ascending and adjacent. */
5832 for (i
= 1; i
< nops
; i
++)
5836 order
[i
] = order
[i
- 1];
5837 for (j
= 0; j
< nops
; j
++)
5838 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5839 && (order
[i
] == order
[i
- 1]
5840 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5843 /* Have we found a suitable register? if not, one must be used more
5845 if (order
[i
] == order
[i
- 1])
5848 /* Is the memory address adjacent and ascending? */
5849 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5857 for (i
= 0; i
< nops
; i
++)
5858 regs
[i
] = unsorted_regs
[order
[i
]];
5860 *load_offset
= unsorted_offsets
[order
[0]];
5863 if (unsorted_offsets
[order
[0]] == 0)
5864 return 1; /* ldmia */
5866 if (unsorted_offsets
[order
[0]] == 4)
5867 return 2; /* ldmib */
5869 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5870 return 3; /* ldmda */
5872 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5873 return 4; /* ldmdb */
5875 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5876 if the offset isn't small enough. The reason 2 ldrs are faster
5877 is because these ARMs are able to do more than one cache access
5878 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5879 whilst the ARM8 has a double bandwidth cache. This means that
5880 these cores can do both an instruction fetch and a data fetch in
5881 a single cycle, so the trick of calculating the address into a
5882 scratch register (one of the result regs) and then doing a load
5883 multiple actually becomes slower (and no smaller in code size).
5884 That is the transformation
5886 ldr rd1, [rbase + offset]
5887 ldr rd2, [rbase + offset + 4]
5891 add rd1, rbase, offset
5892 ldmia rd1, {rd1, rd2}
5894 produces worse code -- '3 cycles + any stalls on rd2' instead of
5895 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5896 access per cycle, the first sequence could never complete in less
5897 than 6 cycles, whereas the ldm sequence would only take 5 and
5898 would make better use of sequential accesses if not hitting the
5901 We cheat here and test 'arm_ld_sched' which we currently know to
5902 only be true for the ARM8, ARM9 and StrongARM. If this ever
5903 changes, then the test below needs to be reworked. */
5904 if (nops
== 2 && arm_ld_sched
)
5907 /* Can't do it without setting up the offset, only do this if it takes
5908 no more than one insn. */
5909 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5910 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5914 emit_ldm_seq (rtx
*operands
, int nops
)
5918 HOST_WIDE_INT offset
;
5922 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5925 strcpy (buf
, "ldm%?ia\t");
5929 strcpy (buf
, "ldm%?ib\t");
5933 strcpy (buf
, "ldm%?da\t");
5937 strcpy (buf
, "ldm%?db\t");
5942 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5943 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5946 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5947 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5949 output_asm_insn (buf
, operands
);
5951 strcpy (buf
, "ldm%?ia\t");
5958 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5959 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5961 for (i
= 1; i
< nops
; i
++)
5962 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5963 reg_names
[regs
[i
]]);
5965 strcat (buf
, "}\t%@ phole ldm");
5967 output_asm_insn (buf
, operands
);
5972 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5973 HOST_WIDE_INT
* load_offset
)
5975 int unsorted_regs
[4];
5976 HOST_WIDE_INT unsorted_offsets
[4];
5981 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5982 extended if required. */
5983 gcc_assert (nops
>= 2 && nops
<= 4);
5985 /* Loop over the operands and check that the memory references are
5986 suitable (i.e. immediate offsets from the same base register). At
5987 the same time, extract the target register, and the memory
5989 for (i
= 0; i
< nops
; i
++)
5994 /* Convert a subreg of a mem into the mem itself. */
5995 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5996 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5998 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6000 /* Don't reorder volatile memory references; it doesn't seem worth
6001 looking for the case where the order is ok anyway. */
6002 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6005 offset
= const0_rtx
;
6007 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6008 || (GET_CODE (reg
) == SUBREG
6009 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6010 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6011 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6013 || (GET_CODE (reg
) == SUBREG
6014 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6015 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6020 base_reg
= REGNO (reg
);
6021 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6022 ? REGNO (operands
[i
])
6023 : REGNO (SUBREG_REG (operands
[i
])));
6028 if (base_reg
!= (int) REGNO (reg
))
6029 /* Not addressed from the same base register. */
6032 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6033 ? REGNO (operands
[i
])
6034 : REGNO (SUBREG_REG (operands
[i
])));
6035 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6039 /* If it isn't an integer register, then we can't do this. */
6040 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6043 unsorted_offsets
[i
] = INTVAL (offset
);
6046 /* Not a suitable memory address. */
6050 /* All the useful information has now been extracted from the
6051 operands into unsorted_regs and unsorted_offsets; additionally,
6052 order[0] has been set to the lowest numbered register in the
6053 list. Sort the registers into order, and check that the memory
6054 offsets are ascending and adjacent. */
6056 for (i
= 1; i
< nops
; i
++)
6060 order
[i
] = order
[i
- 1];
6061 for (j
= 0; j
< nops
; j
++)
6062 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6063 && (order
[i
] == order
[i
- 1]
6064 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6067 /* Have we found a suitable register? if not, one must be used more
6069 if (order
[i
] == order
[i
- 1])
6072 /* Is the memory address adjacent and ascending? */
6073 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6081 for (i
= 0; i
< nops
; i
++)
6082 regs
[i
] = unsorted_regs
[order
[i
]];
6084 *load_offset
= unsorted_offsets
[order
[0]];
6087 if (unsorted_offsets
[order
[0]] == 0)
6088 return 1; /* stmia */
6090 if (unsorted_offsets
[order
[0]] == 4)
6091 return 2; /* stmib */
6093 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6094 return 3; /* stmda */
6096 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6097 return 4; /* stmdb */
6103 emit_stm_seq (rtx
*operands
, int nops
)
6107 HOST_WIDE_INT offset
;
6111 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6114 strcpy (buf
, "stm%?ia\t");
6118 strcpy (buf
, "stm%?ib\t");
6122 strcpy (buf
, "stm%?da\t");
6126 strcpy (buf
, "stm%?db\t");
6133 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6134 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6136 for (i
= 1; i
< nops
; i
++)
6137 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6138 reg_names
[regs
[i
]]);
6140 strcat (buf
, "}\t%@ phole stm");
6142 output_asm_insn (buf
, operands
);
6146 /* Routines for use in generating RTL. */
6149 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6150 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6152 HOST_WIDE_INT offset
= *offsetp
;
6155 int sign
= up
? 1 : -1;
6158 /* XScale has load-store double instructions, but they have stricter
6159 alignment requirements than load-store multiple, so we cannot
6162 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6163 the pipeline until completion.
6171 An ldr instruction takes 1-3 cycles, but does not block the
6180 Best case ldr will always win. However, the more ldr instructions
6181 we issue, the less likely we are to be able to schedule them well.
6182 Using ldr instructions also increases code size.
6184 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6185 for counts of 3 or 4 regs. */
6186 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6192 for (i
= 0; i
< count
; i
++)
6194 addr
= plus_constant (from
, i
* 4 * sign
);
6195 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6196 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6202 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6212 result
= gen_rtx_PARALLEL (VOIDmode
,
6213 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6216 XVECEXP (result
, 0, 0)
6217 = gen_rtx_SET (GET_MODE (from
), from
,
6218 plus_constant (from
, count
* 4 * sign
));
6223 for (j
= 0; i
< count
; i
++, j
++)
6225 addr
= plus_constant (from
, j
* 4 * sign
);
6226 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6227 XVECEXP (result
, 0, i
)
6228 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6239 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6240 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6242 HOST_WIDE_INT offset
= *offsetp
;
6245 int sign
= up
? 1 : -1;
6248 /* See arm_gen_load_multiple for discussion of
6249 the pros/cons of ldm/stm usage for XScale. */
6250 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6256 for (i
= 0; i
< count
; i
++)
6258 addr
= plus_constant (to
, i
* 4 * sign
);
6259 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6260 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6266 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6276 result
= gen_rtx_PARALLEL (VOIDmode
,
6277 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6280 XVECEXP (result
, 0, 0)
6281 = gen_rtx_SET (GET_MODE (to
), to
,
6282 plus_constant (to
, count
* 4 * sign
));
6287 for (j
= 0; i
< count
; i
++, j
++)
6289 addr
= plus_constant (to
, j
* 4 * sign
);
6290 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6291 XVECEXP (result
, 0, i
)
6292 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6303 arm_gen_movmemqi (rtx
*operands
)
6305 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6306 HOST_WIDE_INT srcoffset
, dstoffset
;
6308 rtx src
, dst
, srcbase
, dstbase
;
6309 rtx part_bytes_reg
= NULL
;
6312 if (GET_CODE (operands
[2]) != CONST_INT
6313 || GET_CODE (operands
[3]) != CONST_INT
6314 || INTVAL (operands
[2]) > 64
6315 || INTVAL (operands
[3]) & 3)
6318 dstbase
= operands
[0];
6319 srcbase
= operands
[1];
6321 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6322 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6324 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6325 out_words_to_go
= INTVAL (operands
[2]) / 4;
6326 last_bytes
= INTVAL (operands
[2]) & 3;
6327 dstoffset
= srcoffset
= 0;
6329 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6330 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6332 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6334 if (in_words_to_go
> 4)
6335 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6336 srcbase
, &srcoffset
));
6338 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6339 FALSE
, srcbase
, &srcoffset
));
6341 if (out_words_to_go
)
6343 if (out_words_to_go
> 4)
6344 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6345 dstbase
, &dstoffset
));
6346 else if (out_words_to_go
!= 1)
6347 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6351 dstbase
, &dstoffset
));
6354 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6355 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6356 if (last_bytes
!= 0)
6358 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6364 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6365 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6368 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6369 if (out_words_to_go
)
6373 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6374 sreg
= copy_to_reg (mem
);
6376 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6377 emit_move_insn (mem
, sreg
);
6380 gcc_assert (!in_words_to_go
); /* Sanity check */
6385 gcc_assert (in_words_to_go
> 0);
6387 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6388 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6391 gcc_assert (!last_bytes
|| part_bytes_reg
);
6393 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6395 rtx tmp
= gen_reg_rtx (SImode
);
6397 /* The bytes we want are in the top end of the word. */
6398 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6399 GEN_INT (8 * (4 - last_bytes
))));
6400 part_bytes_reg
= tmp
;
6404 mem
= adjust_automodify_address (dstbase
, QImode
,
6405 plus_constant (dst
, last_bytes
- 1),
6406 dstoffset
+ last_bytes
- 1);
6407 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6411 tmp
= gen_reg_rtx (SImode
);
6412 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6413 part_bytes_reg
= tmp
;
6422 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6423 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6427 rtx tmp
= gen_reg_rtx (SImode
);
6428 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6429 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6430 part_bytes_reg
= tmp
;
6437 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6438 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6445 /* Select a dominance comparison mode if possible for a test of the general
6446 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6447 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6448 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6449 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6450 In all cases OP will be either EQ or NE, but we don't need to know which
6451 here. If we are unable to support a dominance comparison we return
6452 CC mode. This will then fail to match for the RTL expressions that
6453 generate this call. */
6455 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6457 enum rtx_code cond1
, cond2
;
6460 /* Currently we will probably get the wrong result if the individual
6461 comparisons are not simple. This also ensures that it is safe to
6462 reverse a comparison if necessary. */
6463 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6465 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6469 /* The if_then_else variant of this tests the second condition if the
6470 first passes, but is true if the first fails. Reverse the first
6471 condition to get a true "inclusive-or" expression. */
6472 if (cond_or
== DOM_CC_NX_OR_Y
)
6473 cond1
= reverse_condition (cond1
);
6475 /* If the comparisons are not equal, and one doesn't dominate the other,
6476 then we can't do this. */
6478 && !comparison_dominates_p (cond1
, cond2
)
6479 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6484 enum rtx_code temp
= cond1
;
6492 if (cond_or
== DOM_CC_X_AND_Y
)
6497 case EQ
: return CC_DEQmode
;
6498 case LE
: return CC_DLEmode
;
6499 case LEU
: return CC_DLEUmode
;
6500 case GE
: return CC_DGEmode
;
6501 case GEU
: return CC_DGEUmode
;
6502 default: gcc_unreachable ();
6506 if (cond_or
== DOM_CC_X_AND_Y
)
6522 if (cond_or
== DOM_CC_X_AND_Y
)
6538 if (cond_or
== DOM_CC_X_AND_Y
)
6554 if (cond_or
== DOM_CC_X_AND_Y
)
6569 /* The remaining cases only occur when both comparisons are the
6572 gcc_assert (cond1
== cond2
);
6576 gcc_assert (cond1
== cond2
);
6580 gcc_assert (cond1
== cond2
);
6584 gcc_assert (cond1
== cond2
);
6588 gcc_assert (cond1
== cond2
);
6597 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6599 /* All floating point compares return CCFP if it is an equality
6600 comparison, and CCFPE otherwise. */
6601 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6621 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6630 /* A compare with a shifted operand. Because of canonicalization, the
6631 comparison will have to be swapped when we emit the assembler. */
6632 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6633 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6634 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6635 || GET_CODE (x
) == ROTATERT
))
6638 /* This operation is performed swapped, but since we only rely on the Z
6639 flag we don't need an additional mode. */
6640 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6641 && GET_CODE (x
) == NEG
6642 && (op
== EQ
|| op
== NE
))
6645 /* This is a special case that is used by combine to allow a
6646 comparison of a shifted byte load to be split into a zero-extend
6647 followed by a comparison of the shifted integer (only valid for
6648 equalities and unsigned inequalities). */
6649 if (GET_MODE (x
) == SImode
6650 && GET_CODE (x
) == ASHIFT
6651 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6652 && GET_CODE (XEXP (x
, 0)) == SUBREG
6653 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6654 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6655 && (op
== EQ
|| op
== NE
6656 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6657 && GET_CODE (y
) == CONST_INT
)
6660 /* A construct for a conditional compare, if the false arm contains
6661 0, then both conditions must be true, otherwise either condition
6662 must be true. Not all conditions are possible, so CCmode is
6663 returned if it can't be done. */
6664 if (GET_CODE (x
) == IF_THEN_ELSE
6665 && (XEXP (x
, 2) == const0_rtx
6666 || XEXP (x
, 2) == const1_rtx
)
6667 && COMPARISON_P (XEXP (x
, 0))
6668 && COMPARISON_P (XEXP (x
, 1)))
6669 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6670 INTVAL (XEXP (x
, 2)));
6672 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6673 if (GET_CODE (x
) == AND
6674 && COMPARISON_P (XEXP (x
, 0))
6675 && COMPARISON_P (XEXP (x
, 1)))
6676 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6679 if (GET_CODE (x
) == IOR
6680 && COMPARISON_P (XEXP (x
, 0))
6681 && COMPARISON_P (XEXP (x
, 1)))
6682 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6685 /* An operation (on Thumb) where we want to test for a single bit.
6686 This is done by shifting that bit up into the top bit of a
6687 scratch register; we can then branch on the sign bit. */
6689 && GET_MODE (x
) == SImode
6690 && (op
== EQ
|| op
== NE
)
6691 && (GET_CODE (x
) == ZERO_EXTRACT
))
6694 /* An operation that sets the condition codes as a side-effect, the
6695 V flag is not set correctly, so we can only use comparisons where
6696 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6698 if (GET_MODE (x
) == SImode
6700 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6701 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6702 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6703 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6704 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6705 || GET_CODE (x
) == LSHIFTRT
6706 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6707 || GET_CODE (x
) == ROTATERT
6708 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6711 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6714 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6715 && GET_CODE (x
) == PLUS
6716 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6722 /* X and Y are two things to compare using CODE. Emit the compare insn and
6723 return the rtx for register 0 in the proper mode. FP means this is a
6724 floating point compare: I don't think that it is needed on the arm. */
6726 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6728 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6729 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6731 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6732 gen_rtx_COMPARE (mode
, x
, y
)));
6737 /* Generate a sequence of insns that will generate the correct return
6738 address mask depending on the physical architecture that the program
6741 arm_gen_return_addr_mask (void)
6743 rtx reg
= gen_reg_rtx (Pmode
);
6745 emit_insn (gen_return_addr_mask (reg
));
6750 arm_reload_in_hi (rtx
*operands
)
6752 rtx ref
= operands
[1];
6754 HOST_WIDE_INT offset
= 0;
6756 if (GET_CODE (ref
) == SUBREG
)
6758 offset
= SUBREG_BYTE (ref
);
6759 ref
= SUBREG_REG (ref
);
6762 if (GET_CODE (ref
) == REG
)
6764 /* We have a pseudo which has been spilt onto the stack; there
6765 are two cases here: the first where there is a simple
6766 stack-slot replacement and a second where the stack-slot is
6767 out of range, or is used as a subreg. */
6768 if (reg_equiv_mem
[REGNO (ref
)])
6770 ref
= reg_equiv_mem
[REGNO (ref
)];
6771 base
= find_replacement (&XEXP (ref
, 0));
6774 /* The slot is out of range, or was dressed up in a SUBREG. */
6775 base
= reg_equiv_address
[REGNO (ref
)];
6778 base
= find_replacement (&XEXP (ref
, 0));
6780 /* Handle the case where the address is too complex to be offset by 1. */
6781 if (GET_CODE (base
) == MINUS
6782 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6784 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6786 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6789 else if (GET_CODE (base
) == PLUS
)
6791 /* The addend must be CONST_INT, or we would have dealt with it above. */
6792 HOST_WIDE_INT hi
, lo
;
6794 offset
+= INTVAL (XEXP (base
, 1));
6795 base
= XEXP (base
, 0);
6797 /* Rework the address into a legal sequence of insns. */
6798 /* Valid range for lo is -4095 -> 4095 */
6801 : -((-offset
) & 0xfff));
6803 /* Corner case, if lo is the max offset then we would be out of range
6804 once we have added the additional 1 below, so bump the msb into the
6805 pre-loading insn(s). */
6809 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6810 ^ (HOST_WIDE_INT
) 0x80000000)
6811 - (HOST_WIDE_INT
) 0x80000000);
6813 gcc_assert (hi
+ lo
== offset
);
6817 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6819 /* Get the base address; addsi3 knows how to handle constants
6820 that require more than one insn. */
6821 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6827 /* Operands[2] may overlap operands[0] (though it won't overlap
6828 operands[1]), that's why we asked for a DImode reg -- so we can
6829 use the bit that does not overlap. */
6830 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6831 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6833 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6835 emit_insn (gen_zero_extendqisi2 (scratch
,
6836 gen_rtx_MEM (QImode
,
6837 plus_constant (base
,
6839 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6840 gen_rtx_MEM (QImode
,
6841 plus_constant (base
,
6843 if (!BYTES_BIG_ENDIAN
)
6844 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6845 gen_rtx_IOR (SImode
,
6848 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6852 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6853 gen_rtx_IOR (SImode
,
6854 gen_rtx_ASHIFT (SImode
, scratch
,
6856 gen_rtx_SUBREG (SImode
, operands
[0],
6860 /* Handle storing a half-word to memory during reload by synthesizing as two
6861 byte stores. Take care not to clobber the input values until after we
6862 have moved them somewhere safe. This code assumes that if the DImode
6863 scratch in operands[2] overlaps either the input value or output address
6864 in some way, then that value must die in this insn (we absolutely need
6865 two scratch registers for some corner cases). */
6867 arm_reload_out_hi (rtx
*operands
)
6869 rtx ref
= operands
[0];
6870 rtx outval
= operands
[1];
6872 HOST_WIDE_INT offset
= 0;
6874 if (GET_CODE (ref
) == SUBREG
)
6876 offset
= SUBREG_BYTE (ref
);
6877 ref
= SUBREG_REG (ref
);
6880 if (GET_CODE (ref
) == REG
)
6882 /* We have a pseudo which has been spilt onto the stack; there
6883 are two cases here: the first where there is a simple
6884 stack-slot replacement and a second where the stack-slot is
6885 out of range, or is used as a subreg. */
6886 if (reg_equiv_mem
[REGNO (ref
)])
6888 ref
= reg_equiv_mem
[REGNO (ref
)];
6889 base
= find_replacement (&XEXP (ref
, 0));
6892 /* The slot is out of range, or was dressed up in a SUBREG. */
6893 base
= reg_equiv_address
[REGNO (ref
)];
6896 base
= find_replacement (&XEXP (ref
, 0));
6898 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6900 /* Handle the case where the address is too complex to be offset by 1. */
6901 if (GET_CODE (base
) == MINUS
6902 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6904 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6906 /* Be careful not to destroy OUTVAL. */
6907 if (reg_overlap_mentioned_p (base_plus
, outval
))
6909 /* Updating base_plus might destroy outval, see if we can
6910 swap the scratch and base_plus. */
6911 if (!reg_overlap_mentioned_p (scratch
, outval
))
6914 scratch
= base_plus
;
6919 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6921 /* Be conservative and copy OUTVAL into the scratch now,
6922 this should only be necessary if outval is a subreg
6923 of something larger than a word. */
6924 /* XXX Might this clobber base? I can't see how it can,
6925 since scratch is known to overlap with OUTVAL, and
6926 must be wider than a word. */
6927 emit_insn (gen_movhi (scratch_hi
, outval
));
6928 outval
= scratch_hi
;
6932 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6935 else if (GET_CODE (base
) == PLUS
)
6937 /* The addend must be CONST_INT, or we would have dealt with it above. */
6938 HOST_WIDE_INT hi
, lo
;
6940 offset
+= INTVAL (XEXP (base
, 1));
6941 base
= XEXP (base
, 0);
6943 /* Rework the address into a legal sequence of insns. */
6944 /* Valid range for lo is -4095 -> 4095 */
6947 : -((-offset
) & 0xfff));
6949 /* Corner case, if lo is the max offset then we would be out of range
6950 once we have added the additional 1 below, so bump the msb into the
6951 pre-loading insn(s). */
6955 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6956 ^ (HOST_WIDE_INT
) 0x80000000)
6957 - (HOST_WIDE_INT
) 0x80000000);
6959 gcc_assert (hi
+ lo
== offset
);
6963 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6965 /* Be careful not to destroy OUTVAL. */
6966 if (reg_overlap_mentioned_p (base_plus
, outval
))
6968 /* Updating base_plus might destroy outval, see if we
6969 can swap the scratch and base_plus. */
6970 if (!reg_overlap_mentioned_p (scratch
, outval
))
6973 scratch
= base_plus
;
6978 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6980 /* Be conservative and copy outval into scratch now,
6981 this should only be necessary if outval is a
6982 subreg of something larger than a word. */
6983 /* XXX Might this clobber base? I can't see how it
6984 can, since scratch is known to overlap with
6986 emit_insn (gen_movhi (scratch_hi
, outval
));
6987 outval
= scratch_hi
;
6991 /* Get the base address; addsi3 knows how to handle constants
6992 that require more than one insn. */
6993 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6999 if (BYTES_BIG_ENDIAN
)
7001 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7002 plus_constant (base
, offset
+ 1)),
7003 gen_lowpart (QImode
, outval
)));
7004 emit_insn (gen_lshrsi3 (scratch
,
7005 gen_rtx_SUBREG (SImode
, outval
, 0),
7007 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7008 gen_lowpart (QImode
, scratch
)));
7012 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7013 gen_lowpart (QImode
, outval
)));
7014 emit_insn (gen_lshrsi3 (scratch
,
7015 gen_rtx_SUBREG (SImode
, outval
, 0),
7017 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7018 plus_constant (base
, offset
+ 1)),
7019 gen_lowpart (QImode
, scratch
)));
7023 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7024 (padded to the size of a word) should be passed in a register. */
7027 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7029 if (TARGET_AAPCS_BASED
)
7030 return must_pass_in_stack_var_size (mode
, type
);
7032 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7036 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7037 Return true if an argument passed on the stack should be padded upwards,
7038 i.e. if the least-significant byte has useful data.
7039 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7040 aggregate types are placed in the lowest memory address. */
7043 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7045 if (!TARGET_AAPCS_BASED
)
7046 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7048 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7055 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7056 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7057 byte of the register has useful data, and return the opposite if the
7058 most significant byte does.
7059 For AAPCS, small aggregates and small complex types are always padded
7063 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7064 tree type
, int first ATTRIBUTE_UNUSED
)
7066 if (TARGET_AAPCS_BASED
7068 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7069 && int_size_in_bytes (type
) <= 4)
7072 /* Otherwise, use default padding. */
7073 return !BYTES_BIG_ENDIAN
;
7077 /* Print a symbolic form of X to the debug file, F. */
7079 arm_print_value (FILE *f
, rtx x
)
7081 switch (GET_CODE (x
))
7084 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7088 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7096 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7098 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7099 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7107 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7111 fprintf (f
, "`%s'", XSTR (x
, 0));
7115 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7119 arm_print_value (f
, XEXP (x
, 0));
7123 arm_print_value (f
, XEXP (x
, 0));
7125 arm_print_value (f
, XEXP (x
, 1));
7133 fprintf (f
, "????");
7138 /* Routines for manipulation of the constant pool. */
7140 /* Arm instructions cannot load a large constant directly into a
7141 register; they have to come from a pc relative load. The constant
7142 must therefore be placed in the addressable range of the pc
7143 relative load. Depending on the precise pc relative load
7144 instruction the range is somewhere between 256 bytes and 4k. This
7145 means that we often have to dump a constant inside a function, and
7146 generate code to branch around it.
7148 It is important to minimize this, since the branches will slow
7149 things down and make the code larger.
7151 Normally we can hide the table after an existing unconditional
7152 branch so that there is no interruption of the flow, but in the
7153 worst case the code looks like this:
7171 We fix this by performing a scan after scheduling, which notices
7172 which instructions need to have their operands fetched from the
7173 constant table and builds the table.
7175 The algorithm starts by building a table of all the constants that
7176 need fixing up and all the natural barriers in the function (places
7177 where a constant table can be dropped without breaking the flow).
7178 For each fixup we note how far the pc-relative replacement will be
7179 able to reach and the offset of the instruction into the function.
7181 Having built the table we then group the fixes together to form
7182 tables that are as large as possible (subject to addressing
7183 constraints) and emit each table of constants after the last
7184 barrier that is within range of all the instructions in the group.
7185 If a group does not contain a barrier, then we forcibly create one
7186 by inserting a jump instruction into the flow. Once the table has
7187 been inserted, the insns are then modified to reference the
7188 relevant entry in the pool.
7190 Possible enhancements to the algorithm (not implemented) are:
7192 1) For some processors and object formats, there may be benefit in
7193 aligning the pools to the start of cache lines; this alignment
7194 would need to be taken into account when calculating addressability
7197 /* These typedefs are located at the start of this file, so that
7198 they can be used in the prototypes there. This comment is to
7199 remind readers of that fact so that the following structures
7200 can be understood more easily.
7202 typedef struct minipool_node Mnode;
7203 typedef struct minipool_fixup Mfix; */
7205 struct minipool_node
7207 /* Doubly linked chain of entries. */
7210 /* The maximum offset into the code that this entry can be placed. While
7211 pushing fixes for forward references, all entries are sorted in order
7212 of increasing max_address. */
7213 HOST_WIDE_INT max_address
;
7214 /* Similarly for an entry inserted for a backwards ref. */
7215 HOST_WIDE_INT min_address
;
7216 /* The number of fixes referencing this entry. This can become zero
7217 if we "unpush" an entry. In this case we ignore the entry when we
7218 come to emit the code. */
7220 /* The offset from the start of the minipool. */
7221 HOST_WIDE_INT offset
;
7222 /* The value in table. */
7224 /* The mode of value. */
7225 enum machine_mode mode
;
7226 /* The size of the value. With iWMMXt enabled
7227 sizes > 4 also imply an alignment of 8-bytes. */
7231 struct minipool_fixup
7235 HOST_WIDE_INT address
;
7237 enum machine_mode mode
;
7241 HOST_WIDE_INT forwards
;
7242 HOST_WIDE_INT backwards
;
7245 /* Fixes less than a word need padding out to a word boundary. */
7246 #define MINIPOOL_FIX_SIZE(mode) \
7247 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7249 static Mnode
* minipool_vector_head
;
7250 static Mnode
* minipool_vector_tail
;
7251 static rtx minipool_vector_label
;
7253 /* The linked list of all minipool fixes required for this function. */
7254 Mfix
* minipool_fix_head
;
7255 Mfix
* minipool_fix_tail
;
7256 /* The fix entry for the current minipool, once it has been placed. */
7257 Mfix
* minipool_barrier
;
7259 /* Determines if INSN is the start of a jump table. Returns the end
7260 of the TABLE or NULL_RTX. */
7262 is_jump_table (rtx insn
)
7266 if (GET_CODE (insn
) == JUMP_INSN
7267 && JUMP_LABEL (insn
) != NULL
7268 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7269 == next_real_insn (insn
))
7271 && GET_CODE (table
) == JUMP_INSN
7272 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7273 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7279 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7280 #define JUMP_TABLES_IN_TEXT_SECTION 0
7283 static HOST_WIDE_INT
7284 get_jump_table_size (rtx insn
)
7286 /* ADDR_VECs only take room if read-only data does into the text
7288 if (JUMP_TABLES_IN_TEXT_SECTION
7289 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7294 rtx body
= PATTERN (insn
);
7295 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7297 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7303 /* Move a minipool fix MP from its current location to before MAX_MP.
7304 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7305 constraints may need updating. */
7307 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7308 HOST_WIDE_INT max_address
)
7310 /* The code below assumes these are different. */
7311 gcc_assert (mp
!= max_mp
);
7315 if (max_address
< mp
->max_address
)
7316 mp
->max_address
= max_address
;
7320 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7321 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7323 mp
->max_address
= max_address
;
7325 /* Unlink MP from its current position. Since max_mp is non-null,
7326 mp->prev must be non-null. */
7327 mp
->prev
->next
= mp
->next
;
7328 if (mp
->next
!= NULL
)
7329 mp
->next
->prev
= mp
->prev
;
7331 minipool_vector_tail
= mp
->prev
;
7333 /* Re-insert it before MAX_MP. */
7335 mp
->prev
= max_mp
->prev
;
7338 if (mp
->prev
!= NULL
)
7339 mp
->prev
->next
= mp
;
7341 minipool_vector_head
= mp
;
7344 /* Save the new entry. */
7347 /* Scan over the preceding entries and adjust their addresses as
7349 while (mp
->prev
!= NULL
7350 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7352 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7359 /* Add a constant to the minipool for a forward reference. Returns the
7360 node added or NULL if the constant will not fit in this pool. */
7362 add_minipool_forward_ref (Mfix
*fix
)
7364 /* If set, max_mp is the first pool_entry that has a lower
7365 constraint than the one we are trying to add. */
7366 Mnode
* max_mp
= NULL
;
7367 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7370 /* If this fix's address is greater than the address of the first
7371 entry, then we can't put the fix in this pool. We subtract the
7372 size of the current fix to ensure that if the table is fully
7373 packed we still have enough room to insert this value by shuffling
7374 the other fixes forwards. */
7375 if (minipool_vector_head
&&
7376 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7379 /* Scan the pool to see if a constant with the same value has
7380 already been added. While we are doing this, also note the
7381 location where we must insert the constant if it doesn't already
7383 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7385 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7386 && fix
->mode
== mp
->mode
7387 && (GET_CODE (fix
->value
) != CODE_LABEL
7388 || (CODE_LABEL_NUMBER (fix
->value
)
7389 == CODE_LABEL_NUMBER (mp
->value
)))
7390 && rtx_equal_p (fix
->value
, mp
->value
))
7392 /* More than one fix references this entry. */
7394 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7397 /* Note the insertion point if necessary. */
7399 && mp
->max_address
> max_address
)
7402 /* If we are inserting an 8-bytes aligned quantity and
7403 we have not already found an insertion point, then
7404 make sure that all such 8-byte aligned quantities are
7405 placed at the start of the pool. */
7406 if (ARM_DOUBLEWORD_ALIGN
7408 && fix
->fix_size
== 8
7409 && mp
->fix_size
!= 8)
7412 max_address
= mp
->max_address
;
7416 /* The value is not currently in the minipool, so we need to create
7417 a new entry for it. If MAX_MP is NULL, the entry will be put on
7418 the end of the list since the placement is less constrained than
7419 any existing entry. Otherwise, we insert the new fix before
7420 MAX_MP and, if necessary, adjust the constraints on the other
7422 mp
= xmalloc (sizeof (* mp
));
7423 mp
->fix_size
= fix
->fix_size
;
7424 mp
->mode
= fix
->mode
;
7425 mp
->value
= fix
->value
;
7427 /* Not yet required for a backwards ref. */
7428 mp
->min_address
= -65536;
7432 mp
->max_address
= max_address
;
7434 mp
->prev
= minipool_vector_tail
;
7436 if (mp
->prev
== NULL
)
7438 minipool_vector_head
= mp
;
7439 minipool_vector_label
= gen_label_rtx ();
7442 mp
->prev
->next
= mp
;
7444 minipool_vector_tail
= mp
;
7448 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7449 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7451 mp
->max_address
= max_address
;
7454 mp
->prev
= max_mp
->prev
;
7456 if (mp
->prev
!= NULL
)
7457 mp
->prev
->next
= mp
;
7459 minipool_vector_head
= mp
;
7462 /* Save the new entry. */
7465 /* Scan over the preceding entries and adjust their addresses as
7467 while (mp
->prev
!= NULL
7468 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7470 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7478 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7479 HOST_WIDE_INT min_address
)
7481 HOST_WIDE_INT offset
;
7483 /* The code below assumes these are different. */
7484 gcc_assert (mp
!= min_mp
);
7488 if (min_address
> mp
->min_address
)
7489 mp
->min_address
= min_address
;
7493 /* We will adjust this below if it is too loose. */
7494 mp
->min_address
= min_address
;
7496 /* Unlink MP from its current position. Since min_mp is non-null,
7497 mp->next must be non-null. */
7498 mp
->next
->prev
= mp
->prev
;
7499 if (mp
->prev
!= NULL
)
7500 mp
->prev
->next
= mp
->next
;
7502 minipool_vector_head
= mp
->next
;
7504 /* Reinsert it after MIN_MP. */
7506 mp
->next
= min_mp
->next
;
7508 if (mp
->next
!= NULL
)
7509 mp
->next
->prev
= mp
;
7511 minipool_vector_tail
= mp
;
7517 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7519 mp
->offset
= offset
;
7520 if (mp
->refcount
> 0)
7521 offset
+= mp
->fix_size
;
7523 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7524 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7530 /* Add a constant to the minipool for a backward reference. Returns the
7531 node added or NULL if the constant will not fit in this pool.
7533 Note that the code for insertion for a backwards reference can be
7534 somewhat confusing because the calculated offsets for each fix do
7535 not take into account the size of the pool (which is still under
7538 add_minipool_backward_ref (Mfix
*fix
)
7540 /* If set, min_mp is the last pool_entry that has a lower constraint
7541 than the one we are trying to add. */
7542 Mnode
*min_mp
= NULL
;
7543 /* This can be negative, since it is only a constraint. */
7544 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7547 /* If we can't reach the current pool from this insn, or if we can't
7548 insert this entry at the end of the pool without pushing other
7549 fixes out of range, then we don't try. This ensures that we
7550 can't fail later on. */
7551 if (min_address
>= minipool_barrier
->address
7552 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7553 >= minipool_barrier
->address
))
7556 /* Scan the pool to see if a constant with the same value has
7557 already been added. While we are doing this, also note the
7558 location where we must insert the constant if it doesn't already
7560 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7562 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7563 && fix
->mode
== mp
->mode
7564 && (GET_CODE (fix
->value
) != CODE_LABEL
7565 || (CODE_LABEL_NUMBER (fix
->value
)
7566 == CODE_LABEL_NUMBER (mp
->value
)))
7567 && rtx_equal_p (fix
->value
, mp
->value
)
7568 /* Check that there is enough slack to move this entry to the
7569 end of the table (this is conservative). */
7571 > (minipool_barrier
->address
7572 + minipool_vector_tail
->offset
7573 + minipool_vector_tail
->fix_size
)))
7576 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7580 mp
->min_address
+= fix
->fix_size
;
7583 /* Note the insertion point if necessary. */
7584 if (mp
->min_address
< min_address
)
7586 /* For now, we do not allow the insertion of 8-byte alignment
7587 requiring nodes anywhere but at the start of the pool. */
7588 if (ARM_DOUBLEWORD_ALIGN
7589 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7594 else if (mp
->max_address
7595 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7597 /* Inserting before this entry would push the fix beyond
7598 its maximum address (which can happen if we have
7599 re-located a forwards fix); force the new fix to come
7602 min_address
= mp
->min_address
+ fix
->fix_size
;
7604 /* If we are inserting an 8-bytes aligned quantity and
7605 we have not already found an insertion point, then
7606 make sure that all such 8-byte aligned quantities are
7607 placed at the start of the pool. */
7608 else if (ARM_DOUBLEWORD_ALIGN
7610 && fix
->fix_size
== 8
7611 && mp
->fix_size
< 8)
7614 min_address
= mp
->min_address
+ fix
->fix_size
;
7619 /* We need to create a new entry. */
7620 mp
= xmalloc (sizeof (* mp
));
7621 mp
->fix_size
= fix
->fix_size
;
7622 mp
->mode
= fix
->mode
;
7623 mp
->value
= fix
->value
;
7625 mp
->max_address
= minipool_barrier
->address
+ 65536;
7627 mp
->min_address
= min_address
;
7632 mp
->next
= minipool_vector_head
;
7634 if (mp
->next
== NULL
)
7636 minipool_vector_tail
= mp
;
7637 minipool_vector_label
= gen_label_rtx ();
7640 mp
->next
->prev
= mp
;
7642 minipool_vector_head
= mp
;
7646 mp
->next
= min_mp
->next
;
7650 if (mp
->next
!= NULL
)
7651 mp
->next
->prev
= mp
;
7653 minipool_vector_tail
= mp
;
7656 /* Save the new entry. */
7664 /* Scan over the following entries and adjust their offsets. */
7665 while (mp
->next
!= NULL
)
7667 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7668 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7671 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7673 mp
->next
->offset
= mp
->offset
;
7682 assign_minipool_offsets (Mfix
*barrier
)
7684 HOST_WIDE_INT offset
= 0;
7687 minipool_barrier
= barrier
;
7689 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7691 mp
->offset
= offset
;
7693 if (mp
->refcount
> 0)
7694 offset
+= mp
->fix_size
;
7698 /* Output the literal table */
7700 dump_minipool (rtx scan
)
7706 if (ARM_DOUBLEWORD_ALIGN
)
7707 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7708 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7716 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7717 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7719 scan
= emit_label_after (gen_label_rtx (), scan
);
7720 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7721 scan
= emit_label_after (minipool_vector_label
, scan
);
7723 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7725 if (mp
->refcount
> 0)
7730 ";; Offset %u, min %ld, max %ld ",
7731 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7732 (unsigned long) mp
->max_address
);
7733 arm_print_value (dump_file
, mp
->value
);
7734 fputc ('\n', dump_file
);
7737 switch (mp
->fix_size
)
7739 #ifdef HAVE_consttable_1
7741 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7745 #ifdef HAVE_consttable_2
7747 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7751 #ifdef HAVE_consttable_4
7753 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7757 #ifdef HAVE_consttable_8
7759 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7772 minipool_vector_head
= minipool_vector_tail
= NULL
;
7773 scan
= emit_insn_after (gen_consttable_end (), scan
);
7774 scan
= emit_barrier_after (scan
);
7777 /* Return the cost of forcibly inserting a barrier after INSN. */
7779 arm_barrier_cost (rtx insn
)
7781 /* Basing the location of the pool on the loop depth is preferable,
7782 but at the moment, the basic block information seems to be
7783 corrupt by this stage of the compilation. */
7785 rtx next
= next_nonnote_insn (insn
);
7787 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7790 switch (GET_CODE (insn
))
7793 /* It will always be better to place the table before the label, rather
7802 return base_cost
- 10;
7805 return base_cost
+ 10;
7809 /* Find the best place in the insn stream in the range
7810 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7811 Create the barrier by inserting a jump and add a new fix entry for
7814 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7816 HOST_WIDE_INT count
= 0;
7818 rtx from
= fix
->insn
;
7819 rtx selected
= from
;
7821 HOST_WIDE_INT selected_address
;
7823 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7824 rtx label
= gen_label_rtx ();
7826 selected_cost
= arm_barrier_cost (from
);
7827 selected_address
= fix
->address
;
7829 while (from
&& count
< max_count
)
7834 /* This code shouldn't have been called if there was a natural barrier
7836 gcc_assert (GET_CODE (from
) != BARRIER
);
7838 /* Count the length of this insn. */
7839 count
+= get_attr_length (from
);
7841 /* If there is a jump table, add its length. */
7842 tmp
= is_jump_table (from
);
7845 count
+= get_jump_table_size (tmp
);
7847 /* Jump tables aren't in a basic block, so base the cost on
7848 the dispatch insn. If we select this location, we will
7849 still put the pool after the table. */
7850 new_cost
= arm_barrier_cost (from
);
7852 if (count
< max_count
&& new_cost
<= selected_cost
)
7855 selected_cost
= new_cost
;
7856 selected_address
= fix
->address
+ count
;
7859 /* Continue after the dispatch table. */
7860 from
= NEXT_INSN (tmp
);
7864 new_cost
= arm_barrier_cost (from
);
7866 if (count
< max_count
&& new_cost
<= selected_cost
)
7869 selected_cost
= new_cost
;
7870 selected_address
= fix
->address
+ count
;
7873 from
= NEXT_INSN (from
);
7876 /* Create a new JUMP_INSN that branches around a barrier. */
7877 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7878 JUMP_LABEL (from
) = label
;
7879 barrier
= emit_barrier_after (from
);
7880 emit_label_after (label
, barrier
);
7882 /* Create a minipool barrier entry for the new barrier. */
7883 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7884 new_fix
->insn
= barrier
;
7885 new_fix
->address
= selected_address
;
7886 new_fix
->next
= fix
->next
;
7887 fix
->next
= new_fix
;
7892 /* Record that there is a natural barrier in the insn stream at
7895 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7897 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7900 fix
->address
= address
;
7903 if (minipool_fix_head
!= NULL
)
7904 minipool_fix_tail
->next
= fix
;
7906 minipool_fix_head
= fix
;
7908 minipool_fix_tail
= fix
;
7911 /* Record INSN, which will need fixing up to load a value from the
7912 minipool. ADDRESS is the offset of the insn since the start of the
7913 function; LOC is a pointer to the part of the insn which requires
7914 fixing; VALUE is the constant that must be loaded, which is of type
7917 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7918 enum machine_mode mode
, rtx value
)
7920 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7922 #ifdef AOF_ASSEMBLER
7923 /* PIC symbol references need to be converted into offsets into the
7925 /* XXX This shouldn't be done here. */
7926 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7927 value
= aof_pic_entry (value
);
7928 #endif /* AOF_ASSEMBLER */
7931 fix
->address
= address
;
7934 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7936 fix
->forwards
= get_attr_pool_range (insn
);
7937 fix
->backwards
= get_attr_neg_pool_range (insn
);
7938 fix
->minipool
= NULL
;
7940 /* If an insn doesn't have a range defined for it, then it isn't
7941 expecting to be reworked by this code. Better to stop now than
7942 to generate duff assembly code. */
7943 gcc_assert (fix
->forwards
|| fix
->backwards
);
7945 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7946 So there might be an empty word before the start of the pool.
7947 Hence we reduce the forward range by 4 to allow for this
7949 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7955 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7956 GET_MODE_NAME (mode
),
7957 INSN_UID (insn
), (unsigned long) address
,
7958 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7959 arm_print_value (dump_file
, fix
->value
);
7960 fprintf (dump_file
, "\n");
7963 /* Add it to the chain of fixes. */
7966 if (minipool_fix_head
!= NULL
)
7967 minipool_fix_tail
->next
= fix
;
7969 minipool_fix_head
= fix
;
7971 minipool_fix_tail
= fix
;
7974 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7975 Returns the number of insns needed, or 99 if we don't know how to
7978 arm_const_double_inline_cost (rtx val
)
7980 rtx lowpart
, highpart
;
7981 enum machine_mode mode
;
7983 mode
= GET_MODE (val
);
7985 if (mode
== VOIDmode
)
7988 gcc_assert (GET_MODE_SIZE (mode
) == 8);
7990 lowpart
= gen_lowpart (SImode
, val
);
7991 highpart
= gen_highpart_mode (SImode
, mode
, val
);
7993 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
7994 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
7996 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
7997 NULL_RTX
, NULL_RTX
, 0, 0)
7998 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
7999 NULL_RTX
, NULL_RTX
, 0, 0));
8002 /* Return true if it is worthwhile to split a 64-bit constant into two
8003 32-bit operations. This is the case if optimizing for size, or
8004 if we have load delay slots, or if one 32-bit part can be done with
8005 a single data operation. */
8007 arm_const_double_by_parts (rtx val
)
8009 enum machine_mode mode
= GET_MODE (val
);
8012 if (optimize_size
|| arm_ld_sched
)
8015 if (mode
== VOIDmode
)
8018 part
= gen_highpart_mode (SImode
, mode
, val
);
8020 gcc_assert (GET_CODE (part
) == CONST_INT
);
8022 if (const_ok_for_arm (INTVAL (part
))
8023 || const_ok_for_arm (~INTVAL (part
)))
8026 part
= gen_lowpart (SImode
, val
);
8028 gcc_assert (GET_CODE (part
) == CONST_INT
);
8030 if (const_ok_for_arm (INTVAL (part
))
8031 || const_ok_for_arm (~INTVAL (part
)))
8037 /* Scan INSN and note any of its operands that need fixing.
8038 If DO_PUSHES is false we do not actually push any of the fixups
8039 needed. The function returns TRUE if any fixups were needed/pushed.
8040 This is used by arm_memory_load_p() which needs to know about loads
8041 of constants that will be converted into minipool loads. */
8043 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8045 bool result
= false;
8048 extract_insn (insn
);
8050 if (!constrain_operands (1))
8051 fatal_insn_not_found (insn
);
8053 if (recog_data
.n_alternatives
== 0)
8056 /* Fill in recog_op_alt with information about the constraints of
8058 preprocess_constraints ();
8060 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8062 /* Things we need to fix can only occur in inputs. */
8063 if (recog_data
.operand_type
[opno
] != OP_IN
)
8066 /* If this alternative is a memory reference, then any mention
8067 of constants in this alternative is really to fool reload
8068 into allowing us to accept one there. We need to fix them up
8069 now so that we output the right code. */
8070 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8072 rtx op
= recog_data
.operand
[opno
];
8074 if (CONSTANT_P (op
))
8077 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8078 recog_data
.operand_mode
[opno
], op
);
8081 else if (GET_CODE (op
) == MEM
8082 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8083 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8087 rtx cop
= avoid_constant_pool_reference (op
);
8089 /* Casting the address of something to a mode narrower
8090 than a word can cause avoid_constant_pool_reference()
8091 to return the pool reference itself. That's no good to
8092 us here. Lets just hope that we can use the
8093 constant pool value directly. */
8095 cop
= get_pool_constant (XEXP (op
, 0));
8097 push_minipool_fix (insn
, address
,
8098 recog_data
.operand_loc
[opno
],
8099 recog_data
.operand_mode
[opno
], cop
);
8110 /* Gcc puts the pool in the wrong place for ARM, since we can only
8111 load addresses a limited distance around the pc. We do some
8112 special munging to move the constant pool values to the correct
8113 point in the code. */
8118 HOST_WIDE_INT address
= 0;
8121 minipool_fix_head
= minipool_fix_tail
= NULL
;
8123 /* The first insn must always be a note, or the code below won't
8124 scan it properly. */
8125 insn
= get_insns ();
8126 gcc_assert (GET_CODE (insn
) == NOTE
);
8128 /* Scan all the insns and record the operands that will need fixing. */
8129 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8131 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8132 && (arm_cirrus_insn_p (insn
)
8133 || GET_CODE (insn
) == JUMP_INSN
8134 || arm_memory_load_p (insn
)))
8135 cirrus_reorg (insn
);
8137 if (GET_CODE (insn
) == BARRIER
)
8138 push_minipool_barrier (insn
, address
);
8139 else if (INSN_P (insn
))
8143 note_invalid_constants (insn
, address
, true);
8144 address
+= get_attr_length (insn
);
8146 /* If the insn is a vector jump, add the size of the table
8147 and skip the table. */
8148 if ((table
= is_jump_table (insn
)) != NULL
)
8150 address
+= get_jump_table_size (table
);
8156 fix
= minipool_fix_head
;
8158 /* Now scan the fixups and perform the required changes. */
8163 Mfix
* last_added_fix
;
8164 Mfix
* last_barrier
= NULL
;
8167 /* Skip any further barriers before the next fix. */
8168 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8171 /* No more fixes. */
8175 last_added_fix
= NULL
;
8177 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8179 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8181 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8184 last_barrier
= ftmp
;
8186 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8189 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8192 /* If we found a barrier, drop back to that; any fixes that we
8193 could have reached but come after the barrier will now go in
8194 the next mini-pool. */
8195 if (last_barrier
!= NULL
)
8197 /* Reduce the refcount for those fixes that won't go into this
8199 for (fdel
= last_barrier
->next
;
8200 fdel
&& fdel
!= ftmp
;
8203 fdel
->minipool
->refcount
--;
8204 fdel
->minipool
= NULL
;
8207 ftmp
= last_barrier
;
8211 /* ftmp is first fix that we can't fit into this pool and
8212 there no natural barriers that we could use. Insert a
8213 new barrier in the code somewhere between the previous
8214 fix and this one, and arrange to jump around it. */
8215 HOST_WIDE_INT max_address
;
8217 /* The last item on the list of fixes must be a barrier, so
8218 we can never run off the end of the list of fixes without
8219 last_barrier being set. */
8222 max_address
= minipool_vector_head
->max_address
;
8223 /* Check that there isn't another fix that is in range that
8224 we couldn't fit into this pool because the pool was
8225 already too large: we need to put the pool before such an
8227 if (ftmp
->address
< max_address
)
8228 max_address
= ftmp
->address
;
8230 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8233 assign_minipool_offsets (last_barrier
);
8237 if (GET_CODE (ftmp
->insn
) != BARRIER
8238 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8245 /* Scan over the fixes we have identified for this pool, fixing them
8246 up and adding the constants to the pool itself. */
8247 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8248 this_fix
= this_fix
->next
)
8249 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8252 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8253 minipool_vector_label
),
8254 this_fix
->minipool
->offset
);
8255 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8258 dump_minipool (last_barrier
->insn
);
8262 /* From now on we must synthesize any constants that we can't handle
8263 directly. This can happen if the RTL gets split during final
8264 instruction generation. */
8265 after_arm_reorg
= 1;
8267 /* Free the minipool memory. */
8268 obstack_free (&minipool_obstack
, minipool_startobj
);
8271 /* Routines to output assembly language. */
8273 /* If the rtx is the correct value then return the string of the number.
8274 In this way we can ensure that valid double constants are generated even
8275 when cross compiling. */
8277 fp_immediate_constant (rtx x
)
8282 if (!fp_consts_inited
)
8285 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8286 for (i
= 0; i
< 8; i
++)
8287 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8288 return strings_fp
[i
];
8293 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8295 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8299 if (!fp_consts_inited
)
8302 for (i
= 0; i
< 8; i
++)
8303 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8304 return strings_fp
[i
];
8309 /* Output the operands of a LDM/STM instruction to STREAM.
8310 MASK is the ARM register set mask of which only bits 0-15 are important.
8311 REG is the base register, either the frame pointer or the stack pointer,
8312 INSTR is the possibly suffixed load or store instruction. */
8315 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8319 bool not_first
= FALSE
;
8321 fputc ('\t', stream
);
8322 asm_fprintf (stream
, instr
, reg
);
8323 fputs (", {", stream
);
8325 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8326 if (mask
& (1 << i
))
8329 fprintf (stream
, ", ");
8331 asm_fprintf (stream
, "%r", i
);
8335 fprintf (stream
, "}\n");
8339 /* Output a FLDMX instruction to STREAM.
8340 BASE if the register containing the address.
8341 REG and COUNT specify the register range.
8342 Extra registers may be added to avoid hardware bugs. */
8345 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8349 /* Workaround ARM10 VFPr1 bug. */
8350 if (count
== 2 && !arm_arch6
)
8357 fputc ('\t', stream
);
8358 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8360 for (i
= reg
; i
< reg
+ count
; i
++)
8363 fputs (", ", stream
);
8364 asm_fprintf (stream
, "d%d", i
);
8366 fputs ("}\n", stream
);
8371 /* Output the assembly for a store multiple. */
8374 vfp_output_fstmx (rtx
* operands
)
8381 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8382 p
= strlen (pattern
);
8384 gcc_assert (GET_CODE (operands
[1]) == REG
);
8386 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8387 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8389 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8391 strcpy (&pattern
[p
], "}");
8393 output_asm_insn (pattern
, operands
);
8398 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8399 number of bytes pushed. */
8402 vfp_emit_fstmx (int base_reg
, int count
)
8409 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8410 register pairs are stored by a store multiple insn. We avoid this
8411 by pushing an extra pair. */
8412 if (count
== 2 && !arm_arch6
)
8414 if (base_reg
== LAST_VFP_REGNUM
- 3)
8419 /* ??? The frame layout is implementation defined. We describe
8420 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8421 We really need some way of representing the whole block so that the
8422 unwinder can figure it out at runtime. */
8423 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8424 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8426 reg
= gen_rtx_REG (DFmode
, base_reg
);
8430 = gen_rtx_SET (VOIDmode
,
8431 gen_frame_mem (BLKmode
,
8432 gen_rtx_PRE_DEC (BLKmode
,
8433 stack_pointer_rtx
)),
8434 gen_rtx_UNSPEC (BLKmode
,
8438 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8439 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8440 GEN_INT (-(count
* 8 + 4))));
8441 RTX_FRAME_RELATED_P (tmp
) = 1;
8442 XVECEXP (dwarf
, 0, 0) = tmp
;
8444 tmp
= gen_rtx_SET (VOIDmode
,
8445 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8447 RTX_FRAME_RELATED_P (tmp
) = 1;
8448 XVECEXP (dwarf
, 0, 1) = tmp
;
8450 for (i
= 1; i
< count
; i
++)
8452 reg
= gen_rtx_REG (DFmode
, base_reg
);
8454 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8456 tmp
= gen_rtx_SET (VOIDmode
,
8457 gen_frame_mem (DFmode
,
8458 gen_rtx_PLUS (SImode
,
8462 RTX_FRAME_RELATED_P (tmp
) = 1;
8463 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8466 par
= emit_insn (par
);
8467 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8469 RTX_FRAME_RELATED_P (par
) = 1;
8471 return count
* 8 + 4;
8475 /* Output a 'call' insn. */
8477 output_call (rtx
*operands
)
8479 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8481 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8482 if (REGNO (operands
[0]) == LR_REGNUM
)
8484 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8485 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8488 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8490 if (TARGET_INTERWORK
|| arm_arch4t
)
8491 output_asm_insn ("bx%?\t%0", operands
);
8493 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8498 /* Output a 'call' insn that is a reference in memory. */
8500 output_call_mem (rtx
*operands
)
8502 if (TARGET_INTERWORK
&& !arm_arch5
)
8504 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8505 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8506 output_asm_insn ("bx%?\t%|ip", operands
);
8508 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8510 /* LR is used in the memory address. We load the address in the
8511 first instruction. It's safe to use IP as the target of the
8512 load since the call will kill it anyway. */
8513 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8515 output_asm_insn ("blx%?\t%|ip", operands
);
8518 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8520 output_asm_insn ("bx%?\t%|ip", operands
);
8522 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8527 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8528 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8535 /* Output a move from arm registers to an fpa registers.
8536 OPERANDS[0] is an fpa register.
8537 OPERANDS[1] is the first registers of an arm register pair. */
8539 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8541 int arm_reg0
= REGNO (operands
[1]);
8544 gcc_assert (arm_reg0
!= IP_REGNUM
);
8546 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8547 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8548 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8550 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8551 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8556 /* Output a move from an fpa register to arm registers.
8557 OPERANDS[0] is the first registers of an arm register pair.
8558 OPERANDS[1] is an fpa register. */
8560 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8562 int arm_reg0
= REGNO (operands
[0]);
8565 gcc_assert (arm_reg0
!= IP_REGNUM
);
8567 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8568 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8569 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8571 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8572 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8576 /* Output a move from arm registers to arm registers of a long double
8577 OPERANDS[0] is the destination.
8578 OPERANDS[1] is the source. */
8580 output_mov_long_double_arm_from_arm (rtx
*operands
)
8582 /* We have to be careful here because the two might overlap. */
8583 int dest_start
= REGNO (operands
[0]);
8584 int src_start
= REGNO (operands
[1]);
8588 if (dest_start
< src_start
)
8590 for (i
= 0; i
< 3; i
++)
8592 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8593 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8594 output_asm_insn ("mov%?\t%0, %1", ops
);
8599 for (i
= 2; i
>= 0; i
--)
8601 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8602 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8603 output_asm_insn ("mov%?\t%0, %1", ops
);
8611 /* Output a move from arm registers to an fpa registers.
8612 OPERANDS[0] is an fpa register.
8613 OPERANDS[1] is the first registers of an arm register pair. */
8615 output_mov_double_fpa_from_arm (rtx
*operands
)
8617 int arm_reg0
= REGNO (operands
[1]);
8620 gcc_assert (arm_reg0
!= IP_REGNUM
);
8622 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8623 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8624 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8625 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8629 /* Output a move from an fpa register to arm registers.
8630 OPERANDS[0] is the first registers of an arm register pair.
8631 OPERANDS[1] is an fpa register. */
8633 output_mov_double_arm_from_fpa (rtx
*operands
)
8635 int arm_reg0
= REGNO (operands
[0]);
8638 gcc_assert (arm_reg0
!= IP_REGNUM
);
8640 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8641 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8642 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8643 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8647 /* Output a move between double words.
8648 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8649 or MEM<-REG and all MEMs must be offsettable addresses. */
8651 output_move_double (rtx
*operands
)
8653 enum rtx_code code0
= GET_CODE (operands
[0]);
8654 enum rtx_code code1
= GET_CODE (operands
[1]);
8659 int reg0
= REGNO (operands
[0]);
8661 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8663 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8665 switch (GET_CODE (XEXP (operands
[1], 0)))
8668 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8672 gcc_assert (TARGET_LDRD
);
8673 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8677 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8681 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8685 gcc_assert (TARGET_LDRD
);
8686 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8691 otherops
[0] = operands
[0];
8692 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8693 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8695 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8697 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8699 /* Registers overlap so split out the increment. */
8700 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8701 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8704 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8708 /* We only allow constant increments, so this is safe. */
8709 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8715 output_asm_insn ("adr%?\t%0, %1", operands
);
8716 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8720 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8721 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8723 otherops
[0] = operands
[0];
8724 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8725 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8727 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8729 if (GET_CODE (otherops
[2]) == CONST_INT
)
8731 switch ((int) INTVAL (otherops
[2]))
8734 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8737 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8740 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8745 && (GET_CODE (otherops
[2]) == REG
8746 || (GET_CODE (otherops
[2]) == CONST_INT
8747 && INTVAL (otherops
[2]) > -256
8748 && INTVAL (otherops
[2]) < 256)))
8750 if (reg_overlap_mentioned_p (otherops
[0],
8753 /* Swap base and index registers over to
8754 avoid a conflict. */
8755 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8756 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8758 /* If both registers conflict, it will usually
8759 have been fixed by a splitter. */
8760 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8762 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8763 output_asm_insn ("ldr%?d\t%0, [%1]",
8767 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8771 if (GET_CODE (otherops
[2]) == CONST_INT
)
8773 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8774 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8776 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8779 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8782 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8784 return "ldm%?ia\t%0, %M0";
8788 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8789 /* Take care of overlapping base/data reg. */
8790 if (reg_mentioned_p (operands
[0], operands
[1]))
8792 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8793 output_asm_insn ("ldr%?\t%0, %1", operands
);
8797 output_asm_insn ("ldr%?\t%0, %1", operands
);
8798 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8805 /* Constraints should ensure this. */
8806 gcc_assert (code0
== MEM
&& code1
== REG
);
8807 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8809 switch (GET_CODE (XEXP (operands
[0], 0)))
8812 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8816 gcc_assert (TARGET_LDRD
);
8817 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8821 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8825 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8829 gcc_assert (TARGET_LDRD
);
8830 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8835 otherops
[0] = operands
[1];
8836 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8837 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8839 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8840 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8842 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8846 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8847 if (GET_CODE (otherops
[2]) == CONST_INT
)
8849 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8852 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8856 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8860 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8865 && (GET_CODE (otherops
[2]) == REG
8866 || (GET_CODE (otherops
[2]) == CONST_INT
8867 && INTVAL (otherops
[2]) > -256
8868 && INTVAL (otherops
[2]) < 256)))
8870 otherops
[0] = operands
[1];
8871 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8872 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8878 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8879 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8880 output_asm_insn ("str%?\t%1, %0", operands
);
8881 output_asm_insn ("str%?\t%1, %0", otherops
);
8888 /* Output an ADD r, s, #n where n may be too big for one instruction.
8889 If adding zero to one register, output nothing. */
8891 output_add_immediate (rtx
*operands
)
8893 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8895 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8898 output_multi_immediate (operands
,
8899 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8902 output_multi_immediate (operands
,
8903 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8910 /* Output a multiple immediate operation.
8911 OPERANDS is the vector of operands referred to in the output patterns.
8912 INSTR1 is the output pattern to use for the first constant.
8913 INSTR2 is the output pattern to use for subsequent constants.
8914 IMMED_OP is the index of the constant slot in OPERANDS.
8915 N is the constant value. */
8917 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8918 int immed_op
, HOST_WIDE_INT n
)
8920 #if HOST_BITS_PER_WIDE_INT > 32
8926 /* Quick and easy output. */
8927 operands
[immed_op
] = const0_rtx
;
8928 output_asm_insn (instr1
, operands
);
8933 const char * instr
= instr1
;
8935 /* Note that n is never zero here (which would give no output). */
8936 for (i
= 0; i
< 32; i
+= 2)
8940 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8941 output_asm_insn (instr
, operands
);
8951 /* Return the appropriate ARM instruction for the operation code.
8952 The returned result should not be overwritten. OP is the rtx of the
8953 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8956 arithmetic_instr (rtx op
, int shift_first_arg
)
8958 switch (GET_CODE (op
))
8964 return shift_first_arg
? "rsb" : "sub";
8980 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8981 for the operation code. The returned result should not be overwritten.
8982 OP is the rtx code of the shift.
8983 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8986 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8989 enum rtx_code code
= GET_CODE (op
);
8991 switch (GET_CODE (XEXP (op
, 1)))
8999 *amountp
= INTVAL (XEXP (op
, 1));
9021 gcc_assert (*amountp
!= -1);
9022 *amountp
= 32 - *amountp
;
9031 /* We never have to worry about the amount being other than a
9032 power of 2, since this case can never be reloaded from a reg. */
9033 gcc_assert (*amountp
!= -1);
9034 *amountp
= int_log2 (*amountp
);
9043 /* This is not 100% correct, but follows from the desire to merge
9044 multiplication by a power of 2 with the recognizer for a
9045 shift. >=32 is not a valid shift for "asl", so we must try and
9046 output a shift that produces the correct arithmetical result.
9047 Using lsr #32 is identical except for the fact that the carry bit
9048 is not set correctly if we set the flags; but we never use the
9049 carry bit from such an operation, so we can ignore that. */
9050 if (code
== ROTATERT
)
9051 /* Rotate is just modulo 32. */
9053 else if (*amountp
!= (*amountp
& 31))
9060 /* Shifts of 0 are no-ops. */
9068 /* Obtain the shift from the POWER of two. */
9070 static HOST_WIDE_INT
9071 int_log2 (HOST_WIDE_INT power
)
9073 HOST_WIDE_INT shift
= 0;
9075 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9077 gcc_assert (shift
<= 31);
9084 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9085 because /bin/as is horribly restrictive. The judgement about
9086 whether or not each character is 'printable' (and can be output as
9087 is) or not (and must be printed with an octal escape) must be made
9088 with reference to the *host* character set -- the situation is
9089 similar to that discussed in the comments above pp_c_char in
9090 c-pretty-print.c. */
9092 #define MAX_ASCII_LEN 51
9095 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9100 fputs ("\t.ascii\t\"", stream
);
9102 for (i
= 0; i
< len
; i
++)
9106 if (len_so_far
>= MAX_ASCII_LEN
)
9108 fputs ("\"\n\t.ascii\t\"", stream
);
9114 if (c
== '\\' || c
== '\"')
9116 putc ('\\', stream
);
9124 fprintf (stream
, "\\%03o", c
);
9129 fputs ("\"\n", stream
);
9132 /* Compute the register save mask for registers 0 through 12
9133 inclusive. This code is used by arm_compute_save_reg_mask. */
9135 static unsigned long
9136 arm_compute_save_reg0_reg12_mask (void)
9138 unsigned long func_type
= arm_current_func_type ();
9139 unsigned long save_reg_mask
= 0;
9142 if (IS_INTERRUPT (func_type
))
9144 unsigned int max_reg
;
9145 /* Interrupt functions must not corrupt any registers,
9146 even call clobbered ones. If this is a leaf function
9147 we can just examine the registers used by the RTL, but
9148 otherwise we have to assume that whatever function is
9149 called might clobber anything, and so we have to save
9150 all the call-clobbered registers as well. */
9151 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9152 /* FIQ handlers have registers r8 - r12 banked, so
9153 we only need to check r0 - r7, Normal ISRs only
9154 bank r14 and r15, so we must check up to r12.
9155 r13 is the stack pointer which is always preserved,
9156 so we do not need to consider it here. */
9161 for (reg
= 0; reg
<= max_reg
; reg
++)
9162 if (regs_ever_live
[reg
]
9163 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9164 save_reg_mask
|= (1 << reg
);
9166 /* Also save the pic base register if necessary. */
9168 && !TARGET_SINGLE_PIC_BASE
9169 && current_function_uses_pic_offset_table
)
9170 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9174 /* In the normal case we only need to save those registers
9175 which are call saved and which are used by this function. */
9176 for (reg
= 0; reg
<= 10; reg
++)
9177 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9178 save_reg_mask
|= (1 << reg
);
9180 /* Handle the frame pointer as a special case. */
9181 if (! TARGET_APCS_FRAME
9182 && ! frame_pointer_needed
9183 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9184 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9185 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9187 /* If we aren't loading the PIC register,
9188 don't stack it even though it may be live. */
9190 && !TARGET_SINGLE_PIC_BASE
9191 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9192 || current_function_uses_pic_offset_table
))
9193 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9196 /* Save registers so the exception handler can modify them. */
9197 if (current_function_calls_eh_return
)
9203 reg
= EH_RETURN_DATA_REGNO (i
);
9204 if (reg
== INVALID_REGNUM
)
9206 save_reg_mask
|= 1 << reg
;
9210 return save_reg_mask
;
9213 /* Compute a bit mask of which registers need to be
9214 saved on the stack for the current function. */
9216 static unsigned long
9217 arm_compute_save_reg_mask (void)
9219 unsigned int save_reg_mask
= 0;
9220 unsigned long func_type
= arm_current_func_type ();
9222 if (IS_NAKED (func_type
))
9223 /* This should never really happen. */
9226 /* If we are creating a stack frame, then we must save the frame pointer,
9227 IP (which will hold the old stack pointer), LR and the PC. */
9228 if (frame_pointer_needed
)
9230 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9235 /* Volatile functions do not return, so there
9236 is no need to save any other registers. */
9237 if (IS_VOLATILE (func_type
))
9238 return save_reg_mask
;
9240 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9242 /* Decide if we need to save the link register.
9243 Interrupt routines have their own banked link register,
9244 so they never need to save it.
9245 Otherwise if we do not use the link register we do not need to save
9246 it. If we are pushing other registers onto the stack however, we
9247 can save an instruction in the epilogue by pushing the link register
9248 now and then popping it back into the PC. This incurs extra memory
9249 accesses though, so we only do it when optimizing for size, and only
9250 if we know that we will not need a fancy return sequence. */
9251 if (regs_ever_live
[LR_REGNUM
]
9254 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9255 && !current_function_calls_eh_return
))
9256 save_reg_mask
|= 1 << LR_REGNUM
;
9258 if (cfun
->machine
->lr_save_eliminated
)
9259 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9261 if (TARGET_REALLY_IWMMXT
9262 && ((bit_count (save_reg_mask
)
9263 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9267 /* The total number of registers that are going to be pushed
9268 onto the stack is odd. We need to ensure that the stack
9269 is 64-bit aligned before we start to save iWMMXt registers,
9270 and also before we start to create locals. (A local variable
9271 might be a double or long long which we will load/store using
9272 an iWMMXt instruction). Therefore we need to push another
9273 ARM register, so that the stack will be 64-bit aligned. We
9274 try to avoid using the arg registers (r0 -r3) as they might be
9275 used to pass values in a tail call. */
9276 for (reg
= 4; reg
<= 12; reg
++)
9277 if ((save_reg_mask
& (1 << reg
)) == 0)
9281 save_reg_mask
|= (1 << reg
);
9284 cfun
->machine
->sibcall_blocked
= 1;
9285 save_reg_mask
|= (1 << 3);
9289 return save_reg_mask
;
9293 /* Compute a bit mask of which registers need to be
9294 saved on the stack for the current function. */
9295 static unsigned long
9296 thumb_compute_save_reg_mask (void)
9302 for (reg
= 0; reg
< 12; reg
++)
9303 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9307 && !TARGET_SINGLE_PIC_BASE
9308 && current_function_uses_pic_offset_table
)
9309 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9311 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9312 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9313 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9315 /* LR will also be pushed if any lo regs are pushed. */
9316 if (mask
& 0xff || thumb_force_lr_save ())
9317 mask
|= (1 << LR_REGNUM
);
9319 /* Make sure we have a low work register if we need one.
9320 We will need one if we are going to push a high register,
9321 but we are not currently intending to push a low register. */
9322 if ((mask
& 0xff) == 0
9323 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9325 /* Use thumb_find_work_register to choose which register
9326 we will use. If the register is live then we will
9327 have to push it. Use LAST_LO_REGNUM as our fallback
9328 choice for the register to select. */
9329 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9331 if (! call_used_regs
[reg
])
9339 /* Return the number of bytes required to save VFP registers. */
9341 arm_get_vfp_saved_size (void)
9348 /* Space for saved VFP registers. */
9349 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9352 for (regno
= FIRST_VFP_REGNUM
;
9353 regno
< LAST_VFP_REGNUM
;
9356 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9357 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9361 /* Workaround ARM10 VFPr1 bug. */
9362 if (count
== 2 && !arm_arch6
)
9364 saved
+= count
* 8 + 4;
9373 if (count
== 2 && !arm_arch6
)
9375 saved
+= count
* 8 + 4;
9382 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9383 everything bar the final return instruction. */
9385 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9387 char conditional
[10];
9390 unsigned long live_regs_mask
;
9391 unsigned long func_type
;
9392 arm_stack_offsets
*offsets
;
9394 func_type
= arm_current_func_type ();
9396 if (IS_NAKED (func_type
))
9399 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9401 /* If this function was declared non-returning, and we have
9402 found a tail call, then we have to trust that the called
9403 function won't return. */
9408 /* Otherwise, trap an attempted return by aborting. */
9410 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9412 assemble_external_libcall (ops
[1]);
9413 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9419 gcc_assert (!current_function_calls_alloca
|| really_return
);
9421 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9423 return_used_this_function
= 1;
9425 live_regs_mask
= arm_compute_save_reg_mask ();
9429 const char * return_reg
;
9431 /* If we do not have any special requirements for function exit
9432 (e.g. interworking, or ISR) then we can load the return address
9433 directly into the PC. Otherwise we must load it into LR. */
9435 && ! TARGET_INTERWORK
)
9436 return_reg
= reg_names
[PC_REGNUM
];
9438 return_reg
= reg_names
[LR_REGNUM
];
9440 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9442 /* There are three possible reasons for the IP register
9443 being saved. 1) a stack frame was created, in which case
9444 IP contains the old stack pointer, or 2) an ISR routine
9445 corrupted it, or 3) it was saved to align the stack on
9446 iWMMXt. In case 1, restore IP into SP, otherwise just
9448 if (frame_pointer_needed
)
9450 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9451 live_regs_mask
|= (1 << SP_REGNUM
);
9454 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9457 /* On some ARM architectures it is faster to use LDR rather than
9458 LDM to load a single register. On other architectures, the
9459 cost is the same. In 26 bit mode, or for exception handlers,
9460 we have to use LDM to load the PC so that the CPSR is also
9462 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9463 if (live_regs_mask
== (1U << reg
))
9466 if (reg
<= LAST_ARM_REGNUM
9467 && (reg
!= LR_REGNUM
9469 || ! IS_INTERRUPT (func_type
)))
9471 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9472 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9479 /* Generate the load multiple instruction to restore the
9480 registers. Note we can get here, even if
9481 frame_pointer_needed is true, but only if sp already
9482 points to the base of the saved core registers. */
9483 if (live_regs_mask
& (1 << SP_REGNUM
))
9485 unsigned HOST_WIDE_INT stack_adjust
;
9487 offsets
= arm_get_frame_offsets ();
9488 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9489 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9491 if (stack_adjust
&& arm_arch5
)
9492 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9495 /* If we can't use ldmib (SA110 bug),
9496 then try to pop r3 instead. */
9498 live_regs_mask
|= 1 << 3;
9499 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9503 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9505 p
= instr
+ strlen (instr
);
9507 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9508 if (live_regs_mask
& (1 << reg
))
9510 int l
= strlen (reg_names
[reg
]);
9516 memcpy (p
, ", ", 2);
9520 memcpy (p
, "%|", 2);
9521 memcpy (p
+ 2, reg_names
[reg
], l
);
9525 if (live_regs_mask
& (1 << LR_REGNUM
))
9527 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9528 /* If returning from an interrupt, restore the CPSR. */
9529 if (IS_INTERRUPT (func_type
))
9536 output_asm_insn (instr
, & operand
);
9538 /* See if we need to generate an extra instruction to
9539 perform the actual function return. */
9541 && func_type
!= ARM_FT_INTERWORKED
9542 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9544 /* The return has already been handled
9545 by loading the LR into the PC. */
9552 switch ((int) ARM_FUNC_TYPE (func_type
))
9556 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9559 case ARM_FT_INTERWORKED
:
9560 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9563 case ARM_FT_EXCEPTION
:
9564 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9568 /* Use bx if it's available. */
9569 if (arm_arch5
|| arm_arch4t
)
9570 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9572 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9576 output_asm_insn (instr
, & operand
);
9582 /* Write the function name into the code section, directly preceding
9583 the function prologue.
9585 Code will be output similar to this:
9587 .ascii "arm_poke_function_name", 0
9590 .word 0xff000000 + (t1 - t0)
9591 arm_poke_function_name
9593 stmfd sp!, {fp, ip, lr, pc}
9596 When performing a stack backtrace, code can inspect the value
9597 of 'pc' stored at 'fp' + 0. If the trace function then looks
9598 at location pc - 12 and the top 8 bits are set, then we know
9599 that there is a function name embedded immediately preceding this
9600 location and has length ((pc[-3]) & 0xff000000).
9602 We assume that pc is declared as a pointer to an unsigned long.
9604 It is of no benefit to output the function name if we are assembling
9605 a leaf function. These function types will not contain a stack
9606 backtrace structure, therefore it is not possible to determine the
9609 arm_poke_function_name (FILE *stream
, const char *name
)
9611 unsigned long alignlength
;
9612 unsigned long length
;
9615 length
= strlen (name
) + 1;
9616 alignlength
= ROUND_UP_WORD (length
);
9618 ASM_OUTPUT_ASCII (stream
, name
, length
);
9619 ASM_OUTPUT_ALIGN (stream
, 2);
9620 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9621 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9624 /* Place some comments into the assembler stream
9625 describing the current function. */
9627 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9629 unsigned long func_type
;
9633 thumb_output_function_prologue (f
, frame_size
);
9638 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9640 func_type
= arm_current_func_type ();
9642 switch ((int) ARM_FUNC_TYPE (func_type
))
9647 case ARM_FT_INTERWORKED
:
9648 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9651 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9654 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9656 case ARM_FT_EXCEPTION
:
9657 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9661 if (IS_NAKED (func_type
))
9662 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9664 if (IS_VOLATILE (func_type
))
9665 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9667 if (IS_NESTED (func_type
))
9668 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9670 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9671 current_function_args_size
,
9672 current_function_pretend_args_size
, frame_size
);
9674 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9675 frame_pointer_needed
,
9676 cfun
->machine
->uses_anonymous_args
);
9678 if (cfun
->machine
->lr_save_eliminated
)
9679 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9681 if (current_function_calls_eh_return
)
9682 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9684 #ifdef AOF_ASSEMBLER
9686 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9689 return_used_this_function
= 0;
9693 arm_output_epilogue (rtx sibling
)
9696 unsigned long saved_regs_mask
;
9697 unsigned long func_type
;
9698 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9699 frame that is $fp + 4 for a non-variadic function. */
9700 int floats_offset
= 0;
9702 FILE * f
= asm_out_file
;
9703 unsigned int lrm_count
= 0;
9704 int really_return
= (sibling
== NULL
);
9706 arm_stack_offsets
*offsets
;
9708 /* If we have already generated the return instruction
9709 then it is futile to generate anything else. */
9710 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9713 func_type
= arm_current_func_type ();
9715 if (IS_NAKED (func_type
))
9716 /* Naked functions don't have epilogues. */
9719 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9723 /* A volatile function should never return. Call abort. */
9724 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9725 assemble_external_libcall (op
);
9726 output_asm_insn ("bl\t%a0", &op
);
9731 /* If we are throwing an exception, then we really must be doing a
9732 return, so we can't tail-call. */
9733 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9735 offsets
= arm_get_frame_offsets ();
9736 saved_regs_mask
= arm_compute_save_reg_mask ();
9739 lrm_count
= bit_count (saved_regs_mask
);
9741 floats_offset
= offsets
->saved_args
;
9742 /* Compute how far away the floats will be. */
9743 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9744 if (saved_regs_mask
& (1 << reg
))
9747 if (frame_pointer_needed
)
9749 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9750 int vfp_offset
= offsets
->frame
;
9752 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9754 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9755 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9757 floats_offset
+= 12;
9758 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9759 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9764 start_reg
= LAST_FPA_REGNUM
;
9766 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9768 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9770 floats_offset
+= 12;
9772 /* We can't unstack more than four registers at once. */
9773 if (start_reg
- reg
== 3)
9775 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9776 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9777 start_reg
= reg
- 1;
9782 if (reg
!= start_reg
)
9783 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9784 reg
+ 1, start_reg
- reg
,
9785 FP_REGNUM
, floats_offset
- vfp_offset
);
9786 start_reg
= reg
- 1;
9790 /* Just in case the last register checked also needs unstacking. */
9791 if (reg
!= start_reg
)
9792 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9793 reg
+ 1, start_reg
- reg
,
9794 FP_REGNUM
, floats_offset
- vfp_offset
);
9797 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9801 /* The fldmx insn does not have base+offset addressing modes,
9802 so we use IP to hold the address. */
9803 saved_size
= arm_get_vfp_saved_size ();
9807 floats_offset
+= saved_size
;
9808 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9809 FP_REGNUM
, floats_offset
- vfp_offset
);
9811 start_reg
= FIRST_VFP_REGNUM
;
9812 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9814 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9815 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9817 if (start_reg
!= reg
)
9818 arm_output_fldmx (f
, IP_REGNUM
,
9819 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9820 (reg
- start_reg
) / 2);
9821 start_reg
= reg
+ 2;
9824 if (start_reg
!= reg
)
9825 arm_output_fldmx (f
, IP_REGNUM
,
9826 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9827 (reg
- start_reg
) / 2);
9832 /* The frame pointer is guaranteed to be non-double-word aligned.
9833 This is because it is set to (old_stack_pointer - 4) and the
9834 old_stack_pointer was double word aligned. Thus the offset to
9835 the iWMMXt registers to be loaded must also be non-double-word
9836 sized, so that the resultant address *is* double-word aligned.
9837 We can ignore floats_offset since that was already included in
9838 the live_regs_mask. */
9839 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9841 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9842 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9844 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9845 reg
, FP_REGNUM
, lrm_count
* 4);
9850 /* saved_regs_mask should contain the IP, which at the time of stack
9851 frame generation actually contains the old stack pointer. So a
9852 quick way to unwind the stack is just pop the IP register directly
9853 into the stack pointer. */
9854 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9855 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9856 saved_regs_mask
|= (1 << SP_REGNUM
);
9858 /* There are two registers left in saved_regs_mask - LR and PC. We
9859 only need to restore the LR register (the return address), but to
9860 save time we can load it directly into the PC, unless we need a
9861 special function exit sequence, or we are not really returning. */
9863 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9864 && !current_function_calls_eh_return
)
9865 /* Delete the LR from the register mask, so that the LR on
9866 the stack is loaded into the PC in the register mask. */
9867 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9869 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9871 /* We must use SP as the base register, because SP is one of the
9872 registers being restored. If an interrupt or page fault
9873 happens in the ldm instruction, the SP might or might not
9874 have been restored. That would be bad, as then SP will no
9875 longer indicate the safe area of stack, and we can get stack
9876 corruption. Using SP as the base register means that it will
9877 be reset correctly to the original value, should an interrupt
9878 occur. If the stack pointer already points at the right
9879 place, then omit the subtraction. */
9880 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9881 || current_function_calls_alloca
)
9882 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9883 4 * bit_count (saved_regs_mask
));
9884 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9886 if (IS_INTERRUPT (func_type
))
9887 /* Interrupt handlers will have pushed the
9888 IP onto the stack, so restore it now. */
9889 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9893 /* Restore stack pointer if necessary. */
9894 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9896 operands
[0] = operands
[1] = stack_pointer_rtx
;
9897 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9898 output_add_immediate (operands
);
9901 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9903 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9904 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9905 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9910 start_reg
= FIRST_FPA_REGNUM
;
9912 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9914 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9916 if (reg
- start_reg
== 3)
9918 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9919 start_reg
, SP_REGNUM
);
9920 start_reg
= reg
+ 1;
9925 if (reg
!= start_reg
)
9926 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9927 start_reg
, reg
- start_reg
,
9930 start_reg
= reg
+ 1;
9934 /* Just in case the last register checked also needs unstacking. */
9935 if (reg
!= start_reg
)
9936 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9937 start_reg
, reg
- start_reg
, SP_REGNUM
);
9940 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9942 start_reg
= FIRST_VFP_REGNUM
;
9943 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9945 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9946 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9948 if (start_reg
!= reg
)
9949 arm_output_fldmx (f
, SP_REGNUM
,
9950 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9951 (reg
- start_reg
) / 2);
9952 start_reg
= reg
+ 2;
9955 if (start_reg
!= reg
)
9956 arm_output_fldmx (f
, SP_REGNUM
,
9957 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9958 (reg
- start_reg
) / 2);
9961 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9962 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9963 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9965 /* If we can, restore the LR into the PC. */
9966 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9968 && current_function_pretend_args_size
== 0
9969 && saved_regs_mask
& (1 << LR_REGNUM
)
9970 && !current_function_calls_eh_return
)
9972 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9973 saved_regs_mask
|= (1 << PC_REGNUM
);
9976 /* Load the registers off the stack. If we only have one register
9977 to load use the LDR instruction - it is faster. */
9978 if (saved_regs_mask
== (1 << LR_REGNUM
))
9980 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9982 else if (saved_regs_mask
)
9984 if (saved_regs_mask
& (1 << SP_REGNUM
))
9985 /* Note - write back to the stack register is not enabled
9986 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9987 in the list of registers and if we add writeback the
9988 instruction becomes UNPREDICTABLE. */
9989 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9991 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9994 if (current_function_pretend_args_size
)
9996 /* Unwind the pre-pushed regs. */
9997 operands
[0] = operands
[1] = stack_pointer_rtx
;
9998 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9999 output_add_immediate (operands
);
10003 /* We may have already restored PC directly from the stack. */
10004 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10007 /* Stack adjustment for exception handler. */
10008 if (current_function_calls_eh_return
)
10009 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10010 ARM_EH_STACKADJ_REGNUM
);
10012 /* Generate the return instruction. */
10013 switch ((int) ARM_FUNC_TYPE (func_type
))
10017 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10020 case ARM_FT_EXCEPTION
:
10021 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10024 case ARM_FT_INTERWORKED
:
10025 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10029 if (arm_arch5
|| arm_arch4t
)
10030 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10032 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10040 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10041 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10043 arm_stack_offsets
*offsets
;
10049 /* Emit any call-via-reg trampolines that are needed for v4t support
10050 of call_reg and call_value_reg type insns. */
10051 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10053 rtx label
= cfun
->machine
->call_via
[regno
];
10057 function_section (current_function_decl
);
10058 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10059 CODE_LABEL_NUMBER (label
));
10060 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10064 /* ??? Probably not safe to set this here, since it assumes that a
10065 function will be emitted as assembly immediately after we generate
10066 RTL for it. This does not happen for inline functions. */
10067 return_used_this_function
= 0;
10071 /* We need to take into account any stack-frame rounding. */
10072 offsets
= arm_get_frame_offsets ();
10074 gcc_assert (!use_return_insn (FALSE
, NULL
)
10075 || !return_used_this_function
10076 || offsets
->saved_regs
== offsets
->outgoing_args
10077 || frame_pointer_needed
);
10079 /* Reset the ARM-specific per-function variables. */
10080 after_arm_reorg
= 0;
10084 /* Generate and emit an insn that we will recognize as a push_multi.
10085 Unfortunately, since this insn does not reflect very well the actual
10086 semantics of the operation, we need to annotate the insn for the benefit
10087 of DWARF2 frame unwind information. */
10089 emit_multi_reg_push (unsigned long mask
)
10092 int num_dwarf_regs
;
10096 int dwarf_par_index
;
10099 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10100 if (mask
& (1 << i
))
10103 gcc_assert (num_regs
&& num_regs
<= 16);
10105 /* We don't record the PC in the dwarf frame information. */
10106 num_dwarf_regs
= num_regs
;
10107 if (mask
& (1 << PC_REGNUM
))
10110 /* For the body of the insn we are going to generate an UNSPEC in
10111 parallel with several USEs. This allows the insn to be recognized
10112 by the push_multi pattern in the arm.md file. The insn looks
10113 something like this:
10116 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10117 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10118 (use (reg:SI 11 fp))
10119 (use (reg:SI 12 ip))
10120 (use (reg:SI 14 lr))
10121 (use (reg:SI 15 pc))
10124 For the frame note however, we try to be more explicit and actually
10125 show each register being stored into the stack frame, plus a (single)
10126 decrement of the stack pointer. We do it this way in order to be
10127 friendly to the stack unwinding code, which only wants to see a single
10128 stack decrement per instruction. The RTL we generate for the note looks
10129 something like this:
10132 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10133 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10134 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10135 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10136 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10139 This sequence is used both by the code to support stack unwinding for
10140 exceptions handlers and the code to generate dwarf2 frame debugging. */
10142 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10143 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10144 dwarf_par_index
= 1;
10146 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10148 if (mask
& (1 << i
))
10150 reg
= gen_rtx_REG (SImode
, i
);
10152 XVECEXP (par
, 0, 0)
10153 = gen_rtx_SET (VOIDmode
,
10154 gen_frame_mem (BLKmode
,
10155 gen_rtx_PRE_DEC (BLKmode
,
10156 stack_pointer_rtx
)),
10157 gen_rtx_UNSPEC (BLKmode
,
10158 gen_rtvec (1, reg
),
10159 UNSPEC_PUSH_MULT
));
10161 if (i
!= PC_REGNUM
)
10163 tmp
= gen_rtx_SET (VOIDmode
,
10164 gen_frame_mem (SImode
, stack_pointer_rtx
),
10166 RTX_FRAME_RELATED_P (tmp
) = 1;
10167 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10175 for (j
= 1, i
++; j
< num_regs
; i
++)
10177 if (mask
& (1 << i
))
10179 reg
= gen_rtx_REG (SImode
, i
);
10181 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10183 if (i
!= PC_REGNUM
)
10186 = gen_rtx_SET (VOIDmode
,
10187 gen_frame_mem (SImode
,
10188 plus_constant (stack_pointer_rtx
,
10191 RTX_FRAME_RELATED_P (tmp
) = 1;
10192 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10199 par
= emit_insn (par
);
10201 tmp
= gen_rtx_SET (SImode
,
10203 gen_rtx_PLUS (SImode
,
10205 GEN_INT (-4 * num_regs
)));
10206 RTX_FRAME_RELATED_P (tmp
) = 1;
10207 XVECEXP (dwarf
, 0, 0) = tmp
;
10209 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10214 /* Calculate the size of the return value that is passed in registers. */
10216 arm_size_return_regs (void)
10218 enum machine_mode mode
;
10220 if (current_function_return_rtx
!= 0)
10221 mode
= GET_MODE (current_function_return_rtx
);
10223 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10225 return GET_MODE_SIZE (mode
);
10229 emit_sfm (int base_reg
, int count
)
10236 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10237 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10239 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10241 XVECEXP (par
, 0, 0)
10242 = gen_rtx_SET (VOIDmode
,
10243 gen_frame_mem (BLKmode
,
10244 gen_rtx_PRE_DEC (BLKmode
,
10245 stack_pointer_rtx
)),
10246 gen_rtx_UNSPEC (BLKmode
,
10247 gen_rtvec (1, reg
),
10248 UNSPEC_PUSH_MULT
));
10249 tmp
= gen_rtx_SET (VOIDmode
,
10250 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10251 RTX_FRAME_RELATED_P (tmp
) = 1;
10252 XVECEXP (dwarf
, 0, 1) = tmp
;
10254 for (i
= 1; i
< count
; i
++)
10256 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10257 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10259 tmp
= gen_rtx_SET (VOIDmode
,
10260 gen_frame_mem (XFmode
,
10261 plus_constant (stack_pointer_rtx
,
10264 RTX_FRAME_RELATED_P (tmp
) = 1;
10265 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10268 tmp
= gen_rtx_SET (VOIDmode
,
10270 gen_rtx_PLUS (SImode
,
10272 GEN_INT (-12 * count
)));
10273 RTX_FRAME_RELATED_P (tmp
) = 1;
10274 XVECEXP (dwarf
, 0, 0) = tmp
;
10276 par
= emit_insn (par
);
10277 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10283 /* Return true if the current function needs to save/restore LR. */
10286 thumb_force_lr_save (void)
10288 return !cfun
->machine
->lr_save_eliminated
10289 && (!leaf_function_p ()
10290 || thumb_far_jump_used_p ()
10291 || regs_ever_live
[LR_REGNUM
]);
10295 /* Compute the distance from register FROM to register TO.
10296 These can be the arg pointer (26), the soft frame pointer (25),
10297 the stack pointer (13) or the hard frame pointer (11).
10298 In thumb mode r7 is used as the soft frame pointer, if needed.
10299 Typical stack layout looks like this:
10301 old stack pointer -> | |
10304 | | saved arguments for
10305 | | vararg functions
10308 hard FP & arg pointer -> | | \
10316 soft frame pointer -> | | /
10321 locals base pointer -> | | /
10326 current stack pointer -> | | /
10329 For a given function some or all of these stack components
10330 may not be needed, giving rise to the possibility of
10331 eliminating some of the registers.
10333 The values returned by this function must reflect the behavior
10334 of arm_expand_prologue() and arm_compute_save_reg_mask().
10336 The sign of the number returned reflects the direction of stack
10337 growth, so the values are positive for all eliminations except
10338 from the soft frame pointer to the hard frame pointer.
10340 SFP may point just inside the local variables block to ensure correct
10344 /* Calculate stack offsets. These are used to calculate register elimination
10345 offsets and in prologue/epilogue code. */
10347 static arm_stack_offsets
*
10348 arm_get_frame_offsets (void)
10350 struct arm_stack_offsets
*offsets
;
10351 unsigned long func_type
;
10354 HOST_WIDE_INT frame_size
;
10356 offsets
= &cfun
->machine
->stack_offsets
;
10358 /* We need to know if we are a leaf function. Unfortunately, it
10359 is possible to be called after start_sequence has been called,
10360 which causes get_insns to return the insns for the sequence,
10361 not the function, which will cause leaf_function_p to return
10362 the incorrect result.
10364 to know about leaf functions once reload has completed, and the
10365 frame size cannot be changed after that time, so we can safely
10366 use the cached value. */
10368 if (reload_completed
)
10371 /* Initially this is the size of the local variables. It will translated
10372 into an offset once we have determined the size of preceding data. */
10373 frame_size
= ROUND_UP_WORD (get_frame_size ());
10375 leaf
= leaf_function_p ();
10377 /* Space for variadic functions. */
10378 offsets
->saved_args
= current_function_pretend_args_size
;
10380 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10384 unsigned int regno
;
10386 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10388 /* We know that SP will be doubleword aligned on entry, and we must
10389 preserve that condition at any subroutine call. We also require the
10390 soft frame pointer to be doubleword aligned. */
10392 if (TARGET_REALLY_IWMMXT
)
10394 /* Check for the call-saved iWMMXt registers. */
10395 for (regno
= FIRST_IWMMXT_REGNUM
;
10396 regno
<= LAST_IWMMXT_REGNUM
;
10398 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10402 func_type
= arm_current_func_type ();
10403 if (! IS_VOLATILE (func_type
))
10405 /* Space for saved FPA registers. */
10406 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10407 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10410 /* Space for saved VFP registers. */
10411 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10412 saved
+= arm_get_vfp_saved_size ();
10415 else /* TARGET_THUMB */
10417 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10418 if (TARGET_BACKTRACE
)
10422 /* Saved registers include the stack frame. */
10423 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10424 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10425 /* A leaf function does not need any stack alignment if it has nothing
10427 if (leaf
&& frame_size
== 0)
10429 offsets
->outgoing_args
= offsets
->soft_frame
;
10433 /* Ensure SFP has the correct alignment. */
10434 if (ARM_DOUBLEWORD_ALIGN
10435 && (offsets
->soft_frame
& 7))
10436 offsets
->soft_frame
+= 4;
10438 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10439 offsets
->outgoing_args
= (offsets
->locals_base
10440 + current_function_outgoing_args_size
);
10442 if (ARM_DOUBLEWORD_ALIGN
)
10444 /* Ensure SP remains doubleword aligned. */
10445 if (offsets
->outgoing_args
& 7)
10446 offsets
->outgoing_args
+= 4;
10447 gcc_assert (!(offsets
->outgoing_args
& 7));
10454 /* Calculate the relative offsets for the different stack pointers. Positive
10455 offsets are in the direction of stack growth. */
10458 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10460 arm_stack_offsets
*offsets
;
10462 offsets
= arm_get_frame_offsets ();
10464 /* OK, now we have enough information to compute the distances.
10465 There must be an entry in these switch tables for each pair
10466 of registers in ELIMINABLE_REGS, even if some of the entries
10467 seem to be redundant or useless. */
10470 case ARG_POINTER_REGNUM
:
10473 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10476 case FRAME_POINTER_REGNUM
:
10477 /* This is the reverse of the soft frame pointer
10478 to hard frame pointer elimination below. */
10479 return offsets
->soft_frame
- offsets
->saved_args
;
10481 case ARM_HARD_FRAME_POINTER_REGNUM
:
10482 /* If there is no stack frame then the hard
10483 frame pointer and the arg pointer coincide. */
10484 if (offsets
->frame
== offsets
->saved_regs
)
10486 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10487 return (frame_pointer_needed
10488 && cfun
->static_chain_decl
!= NULL
10489 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10491 case STACK_POINTER_REGNUM
:
10492 /* If nothing has been pushed on the stack at all
10493 then this will return -4. This *is* correct! */
10494 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10497 gcc_unreachable ();
10499 gcc_unreachable ();
10501 case FRAME_POINTER_REGNUM
:
10504 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10507 case ARM_HARD_FRAME_POINTER_REGNUM
:
10508 /* The hard frame pointer points to the top entry in the
10509 stack frame. The soft frame pointer to the bottom entry
10510 in the stack frame. If there is no stack frame at all,
10511 then they are identical. */
10513 return offsets
->frame
- offsets
->soft_frame
;
10515 case STACK_POINTER_REGNUM
:
10516 return offsets
->outgoing_args
- offsets
->soft_frame
;
10519 gcc_unreachable ();
10521 gcc_unreachable ();
10524 /* You cannot eliminate from the stack pointer.
10525 In theory you could eliminate from the hard frame
10526 pointer to the stack pointer, but this will never
10527 happen, since if a stack frame is not needed the
10528 hard frame pointer will never be used. */
10529 gcc_unreachable ();
10534 /* Generate the prologue instructions for entry into an ARM function. */
10536 arm_expand_prologue (void)
10542 unsigned long live_regs_mask
;
10543 unsigned long func_type
;
10545 int saved_pretend_args
= 0;
10546 int saved_regs
= 0;
10547 unsigned HOST_WIDE_INT args_to_push
;
10548 arm_stack_offsets
*offsets
;
10550 func_type
= arm_current_func_type ();
10552 /* Naked functions don't have prologues. */
10553 if (IS_NAKED (func_type
))
10556 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10557 args_to_push
= current_function_pretend_args_size
;
10559 /* Compute which register we will have to save onto the stack. */
10560 live_regs_mask
= arm_compute_save_reg_mask ();
10562 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10564 if (frame_pointer_needed
)
10566 if (IS_INTERRUPT (func_type
))
10568 /* Interrupt functions must not corrupt any registers.
10569 Creating a frame pointer however, corrupts the IP
10570 register, so we must push it first. */
10571 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10573 /* Do not set RTX_FRAME_RELATED_P on this insn.
10574 The dwarf stack unwinding code only wants to see one
10575 stack decrement per function, and this is not it. If
10576 this instruction is labeled as being part of the frame
10577 creation sequence then dwarf2out_frame_debug_expr will
10578 die when it encounters the assignment of IP to FP
10579 later on, since the use of SP here establishes SP as
10580 the CFA register and not IP.
10582 Anyway this instruction is not really part of the stack
10583 frame creation although it is part of the prologue. */
10585 else if (IS_NESTED (func_type
))
10587 /* The Static chain register is the same as the IP register
10588 used as a scratch register during stack frame creation.
10589 To get around this need to find somewhere to store IP
10590 whilst the frame is being created. We try the following
10593 1. The last argument register.
10594 2. A slot on the stack above the frame. (This only
10595 works if the function is not a varargs function).
10596 3. Register r3, after pushing the argument registers
10599 Note - we only need to tell the dwarf2 backend about the SP
10600 adjustment in the second variant; the static chain register
10601 doesn't need to be unwound, as it doesn't contain a value
10602 inherited from the caller. */
10604 if (regs_ever_live
[3] == 0)
10606 insn
= gen_rtx_REG (SImode
, 3);
10607 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10608 insn
= emit_insn (insn
);
10610 else if (args_to_push
== 0)
10613 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10614 insn
= gen_frame_mem (SImode
, insn
);
10615 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10616 insn
= emit_insn (insn
);
10620 /* Just tell the dwarf backend that we adjusted SP. */
10621 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10622 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10623 GEN_INT (-fp_offset
)));
10624 RTX_FRAME_RELATED_P (insn
) = 1;
10625 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10626 dwarf
, REG_NOTES (insn
));
10630 /* Store the args on the stack. */
10631 if (cfun
->machine
->uses_anonymous_args
)
10632 insn
= emit_multi_reg_push
10633 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10636 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10637 GEN_INT (- args_to_push
)));
10639 RTX_FRAME_RELATED_P (insn
) = 1;
10641 saved_pretend_args
= 1;
10642 fp_offset
= args_to_push
;
10645 /* Now reuse r3 to preserve IP. */
10646 insn
= gen_rtx_REG (SImode
, 3);
10647 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10648 (void) emit_insn (insn
);
10654 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10655 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10658 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10660 insn
= emit_insn (insn
);
10661 RTX_FRAME_RELATED_P (insn
) = 1;
10666 /* Push the argument registers, or reserve space for them. */
10667 if (cfun
->machine
->uses_anonymous_args
)
10668 insn
= emit_multi_reg_push
10669 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10672 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10673 GEN_INT (- args_to_push
)));
10674 RTX_FRAME_RELATED_P (insn
) = 1;
10677 /* If this is an interrupt service routine, and the link register
10678 is going to be pushed, and we are not creating a stack frame,
10679 (which would involve an extra push of IP and a pop in the epilogue)
10680 subtracting four from LR now will mean that the function return
10681 can be done with a single instruction. */
10682 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10683 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10684 && ! frame_pointer_needed
)
10685 emit_insn (gen_rtx_SET (SImode
,
10686 gen_rtx_REG (SImode
, LR_REGNUM
),
10687 gen_rtx_PLUS (SImode
,
10688 gen_rtx_REG (SImode
, LR_REGNUM
),
10691 if (live_regs_mask
)
10693 insn
= emit_multi_reg_push (live_regs_mask
);
10694 saved_regs
+= bit_count (live_regs_mask
) * 4;
10695 RTX_FRAME_RELATED_P (insn
) = 1;
10699 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10700 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10702 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10703 insn
= gen_frame_mem (V2SImode
, insn
);
10704 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10705 gen_rtx_REG (V2SImode
, reg
)));
10706 RTX_FRAME_RELATED_P (insn
) = 1;
10710 if (! IS_VOLATILE (func_type
))
10714 /* Save any floating point call-saved registers used by this
10716 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10718 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10719 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10721 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10722 insn
= gen_frame_mem (XFmode
, insn
);
10723 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10724 gen_rtx_REG (XFmode
, reg
)));
10725 RTX_FRAME_RELATED_P (insn
) = 1;
10731 start_reg
= LAST_FPA_REGNUM
;
10733 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10735 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10737 if (start_reg
- reg
== 3)
10739 insn
= emit_sfm (reg
, 4);
10740 RTX_FRAME_RELATED_P (insn
) = 1;
10742 start_reg
= reg
- 1;
10747 if (start_reg
!= reg
)
10749 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10750 RTX_FRAME_RELATED_P (insn
) = 1;
10751 saved_regs
+= (start_reg
- reg
) * 12;
10753 start_reg
= reg
- 1;
10757 if (start_reg
!= reg
)
10759 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10760 saved_regs
+= (start_reg
- reg
) * 12;
10761 RTX_FRAME_RELATED_P (insn
) = 1;
10764 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10766 start_reg
= FIRST_VFP_REGNUM
;
10768 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10770 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10771 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10773 if (start_reg
!= reg
)
10774 saved_regs
+= vfp_emit_fstmx (start_reg
,
10775 (reg
- start_reg
) / 2);
10776 start_reg
= reg
+ 2;
10779 if (start_reg
!= reg
)
10780 saved_regs
+= vfp_emit_fstmx (start_reg
,
10781 (reg
- start_reg
) / 2);
10785 if (frame_pointer_needed
)
10787 /* Create the new frame pointer. */
10788 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10789 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10790 RTX_FRAME_RELATED_P (insn
) = 1;
10792 if (IS_NESTED (func_type
))
10794 /* Recover the static chain register. */
10795 if (regs_ever_live
[3] == 0
10796 || saved_pretend_args
)
10797 insn
= gen_rtx_REG (SImode
, 3);
10798 else /* if (current_function_pretend_args_size == 0) */
10800 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10802 insn
= gen_frame_mem (SImode
, insn
);
10805 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10806 /* Add a USE to stop propagate_one_insn() from barfing. */
10807 emit_insn (gen_prologue_use (ip_rtx
));
10811 offsets
= arm_get_frame_offsets ();
10812 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10814 /* This add can produce multiple insns for a large constant, so we
10815 need to get tricky. */
10816 rtx last
= get_last_insn ();
10818 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10819 - offsets
->outgoing_args
);
10821 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10825 last
= last
? NEXT_INSN (last
) : get_insns ();
10826 RTX_FRAME_RELATED_P (last
) = 1;
10828 while (last
!= insn
);
10830 /* If the frame pointer is needed, emit a special barrier that
10831 will prevent the scheduler from moving stores to the frame
10832 before the stack adjustment. */
10833 if (frame_pointer_needed
)
10834 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10835 hard_frame_pointer_rtx
));
10840 arm_load_pic_register (0UL);
10842 /* If we are profiling, make sure no instructions are scheduled before
10843 the call to mcount. Similarly if the user has requested no
10844 scheduling in the prolog. */
10845 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
10846 emit_insn (gen_blockage ());
10848 /* If the link register is being kept alive, with the return address in it,
10849 then make sure that it does not get reused by the ce2 pass. */
10850 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10852 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10853 cfun
->machine
->lr_save_eliminated
= 1;
10857 /* If CODE is 'd', then the X is a condition operand and the instruction
10858 should only be executed if the condition is true.
10859 if CODE is 'D', then the X is a condition operand and the instruction
10860 should only be executed if the condition is false: however, if the mode
10861 of the comparison is CCFPEmode, then always execute the instruction -- we
10862 do this because in these circumstances !GE does not necessarily imply LT;
10863 in these cases the instruction pattern will take care to make sure that
10864 an instruction containing %d will follow, thereby undoing the effects of
10865 doing this instruction unconditionally.
10866 If CODE is 'N' then X is a floating point operand that must be negated
10868 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10869 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10871 arm_print_operand (FILE *stream
, rtx x
, int code
)
10876 fputs (ASM_COMMENT_START
, stream
);
10880 fputs (user_label_prefix
, stream
);
10884 fputs (REGISTER_PREFIX
, stream
);
10888 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10892 output_operand_lossage ("predicated Thumb instruction");
10895 if (current_insn_predicate
!= NULL
)
10897 output_operand_lossage
10898 ("predicated instruction in conditional sequence");
10902 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10904 else if (current_insn_predicate
)
10906 enum arm_cond_code code
;
10910 output_operand_lossage ("predicated Thumb instruction");
10914 code
= get_arm_condition_code (current_insn_predicate
);
10915 fputs (arm_condition_codes
[code
], stream
);
10922 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10923 r
= REAL_VALUE_NEGATE (r
);
10924 fprintf (stream
, "%s", fp_const_from_val (&r
));
10929 if (GET_CODE (x
) == CONST_INT
)
10932 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10933 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10937 putc ('~', stream
);
10938 output_addr_const (stream
, x
);
10943 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10946 /* Truncate Cirrus shift counts. */
10948 if (GET_CODE (x
) == CONST_INT
)
10950 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10953 arm_print_operand (stream
, x
, 0);
10957 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10963 const char * shift
= shift_op (x
, &val
);
10967 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10969 arm_print_operand (stream
, XEXP (x
, 1), 0);
10971 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10976 /* An explanation of the 'Q', 'R' and 'H' register operands:
10978 In a pair of registers containing a DI or DF value the 'Q'
10979 operand returns the register number of the register containing
10980 the least significant part of the value. The 'R' operand returns
10981 the register number of the register containing the most
10982 significant part of the value.
10984 The 'H' operand returns the higher of the two register numbers.
10985 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10986 same as the 'Q' operand, since the most significant part of the
10987 value is held in the lower number register. The reverse is true
10988 on systems where WORDS_BIG_ENDIAN is false.
10990 The purpose of these operands is to distinguish between cases
10991 where the endian-ness of the values is important (for example
10992 when they are added together), and cases where the endian-ness
10993 is irrelevant, but the order of register operations is important.
10994 For example when loading a value from memory into a register
10995 pair, the endian-ness does not matter. Provided that the value
10996 from the lower memory address is put into the lower numbered
10997 register, and the value from the higher address is put into the
10998 higher numbered register, the load will work regardless of whether
10999 the value being loaded is big-wordian or little-wordian. The
11000 order of the two register loads can matter however, if the address
11001 of the memory location is actually held in one of the registers
11002 being overwritten by the load. */
11004 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11006 output_operand_lossage ("invalid operand for code '%c'", code
);
11010 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11014 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11016 output_operand_lossage ("invalid operand for code '%c'", code
);
11020 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11024 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11026 output_operand_lossage ("invalid operand for code '%c'", code
);
11030 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11034 asm_fprintf (stream
, "%r",
11035 GET_CODE (XEXP (x
, 0)) == REG
11036 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11040 asm_fprintf (stream
, "{%r-%r}",
11042 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11046 /* CONST_TRUE_RTX means always -- that's the default. */
11047 if (x
== const_true_rtx
)
11050 if (!COMPARISON_P (x
))
11052 output_operand_lossage ("invalid operand for code '%c'", code
);
11056 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11061 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11062 want to do that. */
11063 if (x
== const_true_rtx
)
11065 output_operand_lossage ("instruction never exectued");
11068 if (!COMPARISON_P (x
))
11070 output_operand_lossage ("invalid operand for code '%c'", code
);
11074 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11075 (get_arm_condition_code (x
))],
11079 /* Cirrus registers can be accessed in a variety of ways:
11080 single floating point (f)
11081 double floating point (d)
11083 64bit integer (dx). */
11084 case 'W': /* Cirrus register in F mode. */
11085 case 'X': /* Cirrus register in D mode. */
11086 case 'Y': /* Cirrus register in FX mode. */
11087 case 'Z': /* Cirrus register in DX mode. */
11088 gcc_assert (GET_CODE (x
) == REG
11089 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11091 fprintf (stream
, "mv%s%s",
11093 : code
== 'X' ? "d"
11094 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11098 /* Print cirrus register in the mode specified by the register's mode. */
11101 int mode
= GET_MODE (x
);
11103 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11105 output_operand_lossage ("invalid operand for code '%c'", code
);
11109 fprintf (stream
, "mv%s%s",
11110 mode
== DFmode
? "d"
11111 : mode
== SImode
? "fx"
11112 : mode
== DImode
? "dx"
11113 : "f", reg_names
[REGNO (x
)] + 2);
11119 if (GET_CODE (x
) != REG
11120 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11121 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11122 /* Bad value for wCG register number. */
11124 output_operand_lossage ("invalid operand for code '%c'", code
);
11129 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11132 /* Print an iWMMXt control register name. */
11134 if (GET_CODE (x
) != CONST_INT
11136 || INTVAL (x
) >= 16)
11137 /* Bad value for wC register number. */
11139 output_operand_lossage ("invalid operand for code '%c'", code
);
11145 static const char * wc_reg_names
[16] =
11147 "wCID", "wCon", "wCSSF", "wCASF",
11148 "wC4", "wC5", "wC6", "wC7",
11149 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11150 "wC12", "wC13", "wC14", "wC15"
11153 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11157 /* Print a VFP double precision register name. */
11160 int mode
= GET_MODE (x
);
11163 if (mode
!= DImode
&& mode
!= DFmode
)
11165 output_operand_lossage ("invalid operand for code '%c'", code
);
11169 if (GET_CODE (x
) != REG
11170 || !IS_VFP_REGNUM (REGNO (x
)))
11172 output_operand_lossage ("invalid operand for code '%c'", code
);
11176 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11179 output_operand_lossage ("invalid operand for code '%c'", code
);
11183 fprintf (stream
, "d%d", num
>> 1);
11190 output_operand_lossage ("missing operand");
11194 switch (GET_CODE (x
))
11197 asm_fprintf (stream
, "%r", REGNO (x
));
11201 output_memory_reference_mode
= GET_MODE (x
);
11202 output_address (XEXP (x
, 0));
11206 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11210 gcc_assert (GET_CODE (x
) != NEG
);
11211 fputc ('#', stream
);
11212 output_addr_const (stream
, x
);
11218 #ifndef AOF_ASSEMBLER
11219 /* Target hook for assembling integer objects. The ARM version needs to
11220 handle word-sized values specially. */
11222 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11224 if (size
== UNITS_PER_WORD
&& aligned_p
)
11226 fputs ("\t.word\t", asm_out_file
);
11227 output_addr_const (asm_out_file
, x
);
11229 /* Mark symbols as position independent. We only do this in the
11230 .text segment, not in the .data segment. */
11231 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11232 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11234 if (GET_CODE (x
) == SYMBOL_REF
11235 && (CONSTANT_POOL_ADDRESS_P (x
)
11236 || SYMBOL_REF_LOCAL_P (x
)))
11237 fputs ("(GOTOFF)", asm_out_file
);
11238 else if (GET_CODE (x
) == LABEL_REF
)
11239 fputs ("(GOTOFF)", asm_out_file
);
11241 fputs ("(GOT)", asm_out_file
);
11243 fputc ('\n', asm_out_file
);
11247 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11251 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11253 units
= CONST_VECTOR_NUNITS (x
);
11255 switch (GET_MODE (x
))
11257 case V2SImode
: size
= 4; break;
11258 case V4HImode
: size
= 2; break;
11259 case V8QImode
: size
= 1; break;
11261 gcc_unreachable ();
11264 for (i
= 0; i
< units
; i
++)
11268 elt
= CONST_VECTOR_ELT (x
, i
);
11270 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11276 return default_assemble_integer (x
, size
, aligned_p
);
11280 /* Add a function to the list of static constructors. */
11283 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
11285 if (!TARGET_AAPCS_BASED
)
11287 default_named_section_asm_out_constructor (symbol
, priority
);
11291 /* Put these in the .init_array section, using a special relocation. */
11293 assemble_align (POINTER_SIZE
);
11294 fputs ("\t.word\t", asm_out_file
);
11295 output_addr_const (asm_out_file
, symbol
);
11296 fputs ("(target1)\n", asm_out_file
);
11300 /* A finite state machine takes care of noticing whether or not instructions
11301 can be conditionally executed, and thus decrease execution time and code
11302 size by deleting branch instructions. The fsm is controlled by
11303 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11305 /* The state of the fsm controlling condition codes are:
11306 0: normal, do nothing special
11307 1: make ASM_OUTPUT_OPCODE not output this instruction
11308 2: make ASM_OUTPUT_OPCODE not output this instruction
11309 3: make instructions conditional
11310 4: make instructions conditional
11312 State transitions (state->state by whom under condition):
11313 0 -> 1 final_prescan_insn if the `target' is a label
11314 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11315 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11316 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11317 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11318 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11319 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11320 (the target insn is arm_target_insn).
11322 If the jump clobbers the conditions then we use states 2 and 4.
11324 A similar thing can be done with conditional return insns.
11326 XXX In case the `target' is an unconditional branch, this conditionalising
11327 of the instructions always reduces code size, but not always execution
11328 time. But then, I want to reduce the code size to somewhere near what
11329 /bin/cc produces. */
11331 /* Returns the index of the ARM condition code string in
11332 `arm_condition_codes'. COMPARISON should be an rtx like
11333 `(eq (...) (...))'. */
11334 static enum arm_cond_code
11335 get_arm_condition_code (rtx comparison
)
11337 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11339 enum rtx_code comp_code
= GET_CODE (comparison
);
11341 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11342 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11343 XEXP (comparison
, 1));
11347 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11348 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11349 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11350 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11351 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11352 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11353 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11354 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11355 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11356 case CC_DLTUmode
: code
= ARM_CC
;
11359 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11361 if (comp_code
== EQ
)
11362 return ARM_INVERSE_CONDITION_CODE (code
);
11368 case NE
: return ARM_NE
;
11369 case EQ
: return ARM_EQ
;
11370 case GE
: return ARM_PL
;
11371 case LT
: return ARM_MI
;
11372 default: gcc_unreachable ();
11378 case NE
: return ARM_NE
;
11379 case EQ
: return ARM_EQ
;
11380 default: gcc_unreachable ();
11386 case NE
: return ARM_MI
;
11387 case EQ
: return ARM_PL
;
11388 default: gcc_unreachable ();
11393 /* These encodings assume that AC=1 in the FPA system control
11394 byte. This allows us to handle all cases except UNEQ and
11398 case GE
: return ARM_GE
;
11399 case GT
: return ARM_GT
;
11400 case LE
: return ARM_LS
;
11401 case LT
: return ARM_MI
;
11402 case NE
: return ARM_NE
;
11403 case EQ
: return ARM_EQ
;
11404 case ORDERED
: return ARM_VC
;
11405 case UNORDERED
: return ARM_VS
;
11406 case UNLT
: return ARM_LT
;
11407 case UNLE
: return ARM_LE
;
11408 case UNGT
: return ARM_HI
;
11409 case UNGE
: return ARM_PL
;
11410 /* UNEQ and LTGT do not have a representation. */
11411 case UNEQ
: /* Fall through. */
11412 case LTGT
: /* Fall through. */
11413 default: gcc_unreachable ();
11419 case NE
: return ARM_NE
;
11420 case EQ
: return ARM_EQ
;
11421 case GE
: return ARM_LE
;
11422 case GT
: return ARM_LT
;
11423 case LE
: return ARM_GE
;
11424 case LT
: return ARM_GT
;
11425 case GEU
: return ARM_LS
;
11426 case GTU
: return ARM_CC
;
11427 case LEU
: return ARM_CS
;
11428 case LTU
: return ARM_HI
;
11429 default: gcc_unreachable ();
11435 case LTU
: return ARM_CS
;
11436 case GEU
: return ARM_CC
;
11437 default: gcc_unreachable ();
11443 case NE
: return ARM_NE
;
11444 case EQ
: return ARM_EQ
;
11445 case GE
: return ARM_GE
;
11446 case GT
: return ARM_GT
;
11447 case LE
: return ARM_LE
;
11448 case LT
: return ARM_LT
;
11449 case GEU
: return ARM_CS
;
11450 case GTU
: return ARM_HI
;
11451 case LEU
: return ARM_LS
;
11452 case LTU
: return ARM_CC
;
11453 default: gcc_unreachable ();
11456 default: gcc_unreachable ();
11461 arm_final_prescan_insn (rtx insn
)
11463 /* BODY will hold the body of INSN. */
11464 rtx body
= PATTERN (insn
);
11466 /* This will be 1 if trying to repeat the trick, and things need to be
11467 reversed if it appears to fail. */
11470 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11471 taken are clobbered, even if the rtl suggests otherwise. It also
11472 means that we have to grub around within the jump expression to find
11473 out what the conditions are when the jump isn't taken. */
11474 int jump_clobbers
= 0;
11476 /* If we start with a return insn, we only succeed if we find another one. */
11477 int seeking_return
= 0;
11479 /* START_INSN will hold the insn from where we start looking. This is the
11480 first insn after the following code_label if REVERSE is true. */
11481 rtx start_insn
= insn
;
11483 /* If in state 4, check if the target branch is reached, in order to
11484 change back to state 0. */
11485 if (arm_ccfsm_state
== 4)
11487 if (insn
== arm_target_insn
)
11489 arm_target_insn
= NULL
;
11490 arm_ccfsm_state
= 0;
11495 /* If in state 3, it is possible to repeat the trick, if this insn is an
11496 unconditional branch to a label, and immediately following this branch
11497 is the previous target label which is only used once, and the label this
11498 branch jumps to is not too far off. */
11499 if (arm_ccfsm_state
== 3)
11501 if (simplejump_p (insn
))
11503 start_insn
= next_nonnote_insn (start_insn
);
11504 if (GET_CODE (start_insn
) == BARRIER
)
11506 /* XXX Isn't this always a barrier? */
11507 start_insn
= next_nonnote_insn (start_insn
);
11509 if (GET_CODE (start_insn
) == CODE_LABEL
11510 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11511 && LABEL_NUSES (start_insn
) == 1)
11516 else if (GET_CODE (body
) == RETURN
)
11518 start_insn
= next_nonnote_insn (start_insn
);
11519 if (GET_CODE (start_insn
) == BARRIER
)
11520 start_insn
= next_nonnote_insn (start_insn
);
11521 if (GET_CODE (start_insn
) == CODE_LABEL
11522 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11523 && LABEL_NUSES (start_insn
) == 1)
11526 seeking_return
= 1;
11535 gcc_assert (!arm_ccfsm_state
|| reverse
);
11536 if (GET_CODE (insn
) != JUMP_INSN
)
11539 /* This jump might be paralleled with a clobber of the condition codes
11540 the jump should always come first */
11541 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11542 body
= XVECEXP (body
, 0, 0);
11545 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11546 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11549 int fail
= FALSE
, succeed
= FALSE
;
11550 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11551 int then_not_else
= TRUE
;
11552 rtx this_insn
= start_insn
, label
= 0;
11554 /* If the jump cannot be done with one instruction, we cannot
11555 conditionally execute the instruction in the inverse case. */
11556 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11562 /* Register the insn jumped to. */
11565 if (!seeking_return
)
11566 label
= XEXP (SET_SRC (body
), 0);
11568 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11569 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11570 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11572 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11573 then_not_else
= FALSE
;
11575 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11576 seeking_return
= 1;
11577 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11579 seeking_return
= 1;
11580 then_not_else
= FALSE
;
11583 gcc_unreachable ();
11585 /* See how many insns this branch skips, and what kind of insns. If all
11586 insns are okay, and the label or unconditional branch to the same
11587 label is not too far away, succeed. */
11588 for (insns_skipped
= 0;
11589 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11593 this_insn
= next_nonnote_insn (this_insn
);
11597 switch (GET_CODE (this_insn
))
11600 /* Succeed if it is the target label, otherwise fail since
11601 control falls in from somewhere else. */
11602 if (this_insn
== label
)
11606 arm_ccfsm_state
= 2;
11607 this_insn
= next_nonnote_insn (this_insn
);
11610 arm_ccfsm_state
= 1;
11618 /* Succeed if the following insn is the target label.
11620 If return insns are used then the last insn in a function
11621 will be a barrier. */
11622 this_insn
= next_nonnote_insn (this_insn
);
11623 if (this_insn
&& this_insn
== label
)
11627 arm_ccfsm_state
= 2;
11628 this_insn
= next_nonnote_insn (this_insn
);
11631 arm_ccfsm_state
= 1;
11639 /* The AAPCS says that conditional calls should not be
11640 used since they make interworking inefficient (the
11641 linker can't transform BL<cond> into BLX). That's
11642 only a problem if the machine has BLX. */
11649 /* Succeed if the following insn is the target label, or
11650 if the following two insns are a barrier and the
11652 this_insn
= next_nonnote_insn (this_insn
);
11653 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11654 this_insn
= next_nonnote_insn (this_insn
);
11656 if (this_insn
&& this_insn
== label
11657 && insns_skipped
< max_insns_skipped
)
11661 arm_ccfsm_state
= 2;
11662 this_insn
= next_nonnote_insn (this_insn
);
11665 arm_ccfsm_state
= 1;
11673 /* If this is an unconditional branch to the same label, succeed.
11674 If it is to another label, do nothing. If it is conditional,
11676 /* XXX Probably, the tests for SET and the PC are
11679 scanbody
= PATTERN (this_insn
);
11680 if (GET_CODE (scanbody
) == SET
11681 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11683 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11684 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11686 arm_ccfsm_state
= 2;
11689 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11692 /* Fail if a conditional return is undesirable (e.g. on a
11693 StrongARM), but still allow this if optimizing for size. */
11694 else if (GET_CODE (scanbody
) == RETURN
11695 && !use_return_insn (TRUE
, NULL
)
11698 else if (GET_CODE (scanbody
) == RETURN
11701 arm_ccfsm_state
= 2;
11704 else if (GET_CODE (scanbody
) == PARALLEL
)
11706 switch (get_attr_conds (this_insn
))
11716 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11721 /* Instructions using or affecting the condition codes make it
11723 scanbody
= PATTERN (this_insn
);
11724 if (!(GET_CODE (scanbody
) == SET
11725 || GET_CODE (scanbody
) == PARALLEL
)
11726 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11729 /* A conditional cirrus instruction must be followed by
11730 a non Cirrus instruction. However, since we
11731 conditionalize instructions in this function and by
11732 the time we get here we can't add instructions
11733 (nops), because shorten_branches() has already been
11734 called, we will disable conditionalizing Cirrus
11735 instructions to be safe. */
11736 if (GET_CODE (scanbody
) != USE
11737 && GET_CODE (scanbody
) != CLOBBER
11738 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11748 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11749 arm_target_label
= CODE_LABEL_NUMBER (label
);
11752 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11754 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11756 this_insn
= next_nonnote_insn (this_insn
);
11757 gcc_assert (!this_insn
11758 || (GET_CODE (this_insn
) != BARRIER
11759 && GET_CODE (this_insn
) != CODE_LABEL
));
11763 /* Oh, dear! we ran off the end.. give up. */
11764 recog (PATTERN (insn
), insn
, NULL
);
11765 arm_ccfsm_state
= 0;
11766 arm_target_insn
= NULL
;
11769 arm_target_insn
= this_insn
;
11773 gcc_assert (!reverse
);
11775 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11777 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11778 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11779 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11780 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11784 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11787 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11791 if (reverse
|| then_not_else
)
11792 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11795 /* Restore recog_data (getting the attributes of other insns can
11796 destroy this array, but final.c assumes that it remains intact
11797 across this call; since the insn has been recognized already we
11798 call recog direct). */
11799 recog (PATTERN (insn
), insn
, NULL
);
11803 /* Returns true if REGNO is a valid register
11804 for holding a quantity of type MODE. */
11806 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11808 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11809 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11812 /* For the Thumb we only allow values bigger than SImode in
11813 registers 0 - 6, so that there is always a second low
11814 register available to hold the upper part of the value.
11815 We probably we ought to ensure that the register is the
11816 start of an even numbered register pair. */
11817 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11819 if (IS_CIRRUS_REGNUM (regno
))
11820 /* We have outlawed SI values in Cirrus registers because they
11821 reside in the lower 32 bits, but SF values reside in the
11822 upper 32 bits. This causes gcc all sorts of grief. We can't
11823 even split the registers into pairs because Cirrus SI values
11824 get sign extended to 64bits-- aldyh. */
11825 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11827 if (IS_VFP_REGNUM (regno
))
11829 if (mode
== SFmode
|| mode
== SImode
)
11832 /* DFmode values are only valid in even register pairs. */
11833 if (mode
== DFmode
)
11834 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11838 if (IS_IWMMXT_GR_REGNUM (regno
))
11839 return mode
== SImode
;
11841 if (IS_IWMMXT_REGNUM (regno
))
11842 return VALID_IWMMXT_REG_MODE (mode
);
11844 /* We allow any value to be stored in the general registers.
11845 Restrict doubleword quantities to even register pairs so that we can
11847 if (regno
<= LAST_ARM_REGNUM
)
11848 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11850 if ( regno
== FRAME_POINTER_REGNUM
11851 || regno
== ARG_POINTER_REGNUM
)
11852 /* We only allow integers in the fake hard registers. */
11853 return GET_MODE_CLASS (mode
) == MODE_INT
;
11855 /* The only registers left are the FPA registers
11856 which we only allow to hold FP values. */
11857 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11858 && regno
>= FIRST_FPA_REGNUM
11859 && regno
<= LAST_FPA_REGNUM
;
11863 arm_regno_class (int regno
)
11867 if (regno
== STACK_POINTER_REGNUM
)
11869 if (regno
== CC_REGNUM
)
11876 if ( regno
<= LAST_ARM_REGNUM
11877 || regno
== FRAME_POINTER_REGNUM
11878 || regno
== ARG_POINTER_REGNUM
)
11879 return GENERAL_REGS
;
11881 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11884 if (IS_CIRRUS_REGNUM (regno
))
11885 return CIRRUS_REGS
;
11887 if (IS_VFP_REGNUM (regno
))
11890 if (IS_IWMMXT_REGNUM (regno
))
11891 return IWMMXT_REGS
;
11893 if (IS_IWMMXT_GR_REGNUM (regno
))
11894 return IWMMXT_GR_REGS
;
11899 /* Handle a special case when computing the offset
11900 of an argument from the frame pointer. */
11902 arm_debugger_arg_offset (int value
, rtx addr
)
11906 /* We are only interested if dbxout_parms() failed to compute the offset. */
11910 /* We can only cope with the case where the address is held in a register. */
11911 if (GET_CODE (addr
) != REG
)
11914 /* If we are using the frame pointer to point at the argument, then
11915 an offset of 0 is correct. */
11916 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11919 /* If we are using the stack pointer to point at the
11920 argument, then an offset of 0 is correct. */
11921 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11922 && REGNO (addr
) == SP_REGNUM
)
11925 /* Oh dear. The argument is pointed to by a register rather
11926 than being held in a register, or being stored at a known
11927 offset from the frame pointer. Since GDB only understands
11928 those two kinds of argument we must translate the address
11929 held in the register into an offset from the frame pointer.
11930 We do this by searching through the insns for the function
11931 looking to see where this register gets its value. If the
11932 register is initialized from the frame pointer plus an offset
11933 then we are in luck and we can continue, otherwise we give up.
11935 This code is exercised by producing debugging information
11936 for a function with arguments like this:
11938 double func (double a, double b, int c, double d) {return d;}
11940 Without this code the stab for parameter 'd' will be set to
11941 an offset of 0 from the frame pointer, rather than 8. */
11943 /* The if() statement says:
11945 If the insn is a normal instruction
11946 and if the insn is setting the value in a register
11947 and if the register being set is the register holding the address of the argument
11948 and if the address is computing by an addition
11949 that involves adding to a register
11950 which is the frame pointer
11955 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11957 if ( GET_CODE (insn
) == INSN
11958 && GET_CODE (PATTERN (insn
)) == SET
11959 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11960 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11961 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11962 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11963 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11966 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11975 warning (0, "unable to compute real location of stacked parameter");
11976 value
= 8; /* XXX magic hack */
11982 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11985 if ((MASK) & insn_flags) \
11986 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11987 BUILT_IN_MD, NULL, NULL_TREE); \
11991 struct builtin_description
11993 const unsigned int mask
;
11994 const enum insn_code icode
;
11995 const char * const name
;
11996 const enum arm_builtins code
;
11997 const enum rtx_code comparison
;
11998 const unsigned int flag
;
12001 static const struct builtin_description bdesc_2arg
[] =
12003 #define IWMMXT_BUILTIN(code, string, builtin) \
12004 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12005 ARM_BUILTIN_##builtin, 0, 0 },
12007 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12008 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12009 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12010 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12011 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12012 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12013 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12014 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12015 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12016 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12017 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12018 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12019 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12020 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12021 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12022 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12023 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12024 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12025 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12026 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12027 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12028 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12029 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12030 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12031 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12032 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12033 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12034 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12035 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12036 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12037 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12038 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12039 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12040 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12041 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12042 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12043 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12044 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12045 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12046 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12047 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12048 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12049 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12050 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12051 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12052 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12053 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12054 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12055 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12056 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12057 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12058 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12059 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12060 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12061 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12062 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12063 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12064 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12066 #define IWMMXT_BUILTIN2(code, builtin) \
12067 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12069 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12070 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12071 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12072 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12073 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12074 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12075 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12076 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12077 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12078 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12079 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12080 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12081 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12082 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12083 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12084 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12085 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12086 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12087 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12088 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12089 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12090 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12091 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12092 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12093 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12094 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12095 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12096 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12097 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12098 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12099 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12100 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12103 static const struct builtin_description bdesc_1arg
[] =
12105 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12106 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12107 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12108 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12109 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12110 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12111 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12112 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12113 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12114 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12115 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12116 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12117 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12118 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12119 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12120 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12121 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12122 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12125 /* Set up all the iWMMXt builtins. This is
12126 not called if TARGET_IWMMXT is zero. */
12129 arm_init_iwmmxt_builtins (void)
12131 const struct builtin_description
* d
;
12133 tree endlink
= void_list_node
;
12135 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12136 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12137 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12140 = build_function_type (integer_type_node
,
12141 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12142 tree v8qi_ftype_v8qi_v8qi_int
12143 = build_function_type (V8QI_type_node
,
12144 tree_cons (NULL_TREE
, V8QI_type_node
,
12145 tree_cons (NULL_TREE
, V8QI_type_node
,
12146 tree_cons (NULL_TREE
,
12149 tree v4hi_ftype_v4hi_int
12150 = build_function_type (V4HI_type_node
,
12151 tree_cons (NULL_TREE
, V4HI_type_node
,
12152 tree_cons (NULL_TREE
, integer_type_node
,
12154 tree v2si_ftype_v2si_int
12155 = build_function_type (V2SI_type_node
,
12156 tree_cons (NULL_TREE
, V2SI_type_node
,
12157 tree_cons (NULL_TREE
, integer_type_node
,
12159 tree v2si_ftype_di_di
12160 = build_function_type (V2SI_type_node
,
12161 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12162 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12164 tree di_ftype_di_int
12165 = build_function_type (long_long_integer_type_node
,
12166 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12167 tree_cons (NULL_TREE
, integer_type_node
,
12169 tree di_ftype_di_int_int
12170 = build_function_type (long_long_integer_type_node
,
12171 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12172 tree_cons (NULL_TREE
, integer_type_node
,
12173 tree_cons (NULL_TREE
,
12176 tree int_ftype_v8qi
12177 = build_function_type (integer_type_node
,
12178 tree_cons (NULL_TREE
, V8QI_type_node
,
12180 tree int_ftype_v4hi
12181 = build_function_type (integer_type_node
,
12182 tree_cons (NULL_TREE
, V4HI_type_node
,
12184 tree int_ftype_v2si
12185 = build_function_type (integer_type_node
,
12186 tree_cons (NULL_TREE
, V2SI_type_node
,
12188 tree int_ftype_v8qi_int
12189 = build_function_type (integer_type_node
,
12190 tree_cons (NULL_TREE
, V8QI_type_node
,
12191 tree_cons (NULL_TREE
, integer_type_node
,
12193 tree int_ftype_v4hi_int
12194 = build_function_type (integer_type_node
,
12195 tree_cons (NULL_TREE
, V4HI_type_node
,
12196 tree_cons (NULL_TREE
, integer_type_node
,
12198 tree int_ftype_v2si_int
12199 = build_function_type (integer_type_node
,
12200 tree_cons (NULL_TREE
, V2SI_type_node
,
12201 tree_cons (NULL_TREE
, integer_type_node
,
12203 tree v8qi_ftype_v8qi_int_int
12204 = build_function_type (V8QI_type_node
,
12205 tree_cons (NULL_TREE
, V8QI_type_node
,
12206 tree_cons (NULL_TREE
, integer_type_node
,
12207 tree_cons (NULL_TREE
,
12210 tree v4hi_ftype_v4hi_int_int
12211 = build_function_type (V4HI_type_node
,
12212 tree_cons (NULL_TREE
, V4HI_type_node
,
12213 tree_cons (NULL_TREE
, integer_type_node
,
12214 tree_cons (NULL_TREE
,
12217 tree v2si_ftype_v2si_int_int
12218 = build_function_type (V2SI_type_node
,
12219 tree_cons (NULL_TREE
, V2SI_type_node
,
12220 tree_cons (NULL_TREE
, integer_type_node
,
12221 tree_cons (NULL_TREE
,
12224 /* Miscellaneous. */
12225 tree v8qi_ftype_v4hi_v4hi
12226 = build_function_type (V8QI_type_node
,
12227 tree_cons (NULL_TREE
, V4HI_type_node
,
12228 tree_cons (NULL_TREE
, V4HI_type_node
,
12230 tree v4hi_ftype_v2si_v2si
12231 = build_function_type (V4HI_type_node
,
12232 tree_cons (NULL_TREE
, V2SI_type_node
,
12233 tree_cons (NULL_TREE
, V2SI_type_node
,
12235 tree v2si_ftype_v4hi_v4hi
12236 = build_function_type (V2SI_type_node
,
12237 tree_cons (NULL_TREE
, V4HI_type_node
,
12238 tree_cons (NULL_TREE
, V4HI_type_node
,
12240 tree v2si_ftype_v8qi_v8qi
12241 = build_function_type (V2SI_type_node
,
12242 tree_cons (NULL_TREE
, V8QI_type_node
,
12243 tree_cons (NULL_TREE
, V8QI_type_node
,
12245 tree v4hi_ftype_v4hi_di
12246 = build_function_type (V4HI_type_node
,
12247 tree_cons (NULL_TREE
, V4HI_type_node
,
12248 tree_cons (NULL_TREE
,
12249 long_long_integer_type_node
,
12251 tree v2si_ftype_v2si_di
12252 = build_function_type (V2SI_type_node
,
12253 tree_cons (NULL_TREE
, V2SI_type_node
,
12254 tree_cons (NULL_TREE
,
12255 long_long_integer_type_node
,
12257 tree void_ftype_int_int
12258 = build_function_type (void_type_node
,
12259 tree_cons (NULL_TREE
, integer_type_node
,
12260 tree_cons (NULL_TREE
, integer_type_node
,
12263 = build_function_type (long_long_unsigned_type_node
, endlink
);
12265 = build_function_type (long_long_integer_type_node
,
12266 tree_cons (NULL_TREE
, V8QI_type_node
,
12269 = build_function_type (long_long_integer_type_node
,
12270 tree_cons (NULL_TREE
, V4HI_type_node
,
12273 = build_function_type (long_long_integer_type_node
,
12274 tree_cons (NULL_TREE
, V2SI_type_node
,
12276 tree v2si_ftype_v4hi
12277 = build_function_type (V2SI_type_node
,
12278 tree_cons (NULL_TREE
, V4HI_type_node
,
12280 tree v4hi_ftype_v8qi
12281 = build_function_type (V4HI_type_node
,
12282 tree_cons (NULL_TREE
, V8QI_type_node
,
12285 tree di_ftype_di_v4hi_v4hi
12286 = build_function_type (long_long_unsigned_type_node
,
12287 tree_cons (NULL_TREE
,
12288 long_long_unsigned_type_node
,
12289 tree_cons (NULL_TREE
, V4HI_type_node
,
12290 tree_cons (NULL_TREE
,
12294 tree di_ftype_v4hi_v4hi
12295 = build_function_type (long_long_unsigned_type_node
,
12296 tree_cons (NULL_TREE
, V4HI_type_node
,
12297 tree_cons (NULL_TREE
, V4HI_type_node
,
12300 /* Normal vector binops. */
12301 tree v8qi_ftype_v8qi_v8qi
12302 = build_function_type (V8QI_type_node
,
12303 tree_cons (NULL_TREE
, V8QI_type_node
,
12304 tree_cons (NULL_TREE
, V8QI_type_node
,
12306 tree v4hi_ftype_v4hi_v4hi
12307 = build_function_type (V4HI_type_node
,
12308 tree_cons (NULL_TREE
, V4HI_type_node
,
12309 tree_cons (NULL_TREE
, V4HI_type_node
,
12311 tree v2si_ftype_v2si_v2si
12312 = build_function_type (V2SI_type_node
,
12313 tree_cons (NULL_TREE
, V2SI_type_node
,
12314 tree_cons (NULL_TREE
, V2SI_type_node
,
12316 tree di_ftype_di_di
12317 = build_function_type (long_long_unsigned_type_node
,
12318 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12319 tree_cons (NULL_TREE
,
12320 long_long_unsigned_type_node
,
12323 /* Add all builtins that are more or less simple operations on two
12325 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12327 /* Use one of the operands; the target can have a different mode for
12328 mask-generating compares. */
12329 enum machine_mode mode
;
12335 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12340 type
= v8qi_ftype_v8qi_v8qi
;
12343 type
= v4hi_ftype_v4hi_v4hi
;
12346 type
= v2si_ftype_v2si_v2si
;
12349 type
= di_ftype_di_di
;
12353 gcc_unreachable ();
12356 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12359 /* Add the remaining MMX insns with somewhat more complicated types. */
12360 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12361 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12362 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12364 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12365 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12366 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12367 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12368 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12369 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12371 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12372 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12373 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12374 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12375 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12376 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12378 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12379 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12380 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12381 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12382 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12383 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12385 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12386 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12387 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12388 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12389 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12390 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12392 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12394 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12395 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12396 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12397 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12399 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12400 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12401 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12402 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12403 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12404 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12405 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12406 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12407 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12409 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12410 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12411 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12413 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12414 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12415 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12417 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12418 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12419 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12420 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12421 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12422 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12424 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12425 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12426 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12427 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12428 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12429 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12430 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12431 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12432 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12433 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12434 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12435 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12437 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12438 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12439 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12440 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12442 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12443 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12444 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12445 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12446 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12447 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12448 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12452 arm_init_tls_builtins (void)
12455 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12456 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12458 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12459 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
12460 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12461 NULL
, const_nothrow
);
12465 arm_init_builtins (void)
12467 arm_init_tls_builtins ();
12469 if (TARGET_REALLY_IWMMXT
)
12470 arm_init_iwmmxt_builtins ();
12473 /* Errors in the source file can cause expand_expr to return const0_rtx
12474 where we expect a vector. To avoid crashing, use one of the vector
12475 clear instructions. */
12478 safe_vector_operand (rtx x
, enum machine_mode mode
)
12480 if (x
!= const0_rtx
)
12482 x
= gen_reg_rtx (mode
);
12484 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12485 : gen_rtx_SUBREG (DImode
, x
, 0)));
12489 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12492 arm_expand_binop_builtin (enum insn_code icode
,
12493 tree arglist
, rtx target
)
12496 tree arg0
= TREE_VALUE (arglist
);
12497 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12498 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12499 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12500 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12501 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12502 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12504 if (VECTOR_MODE_P (mode0
))
12505 op0
= safe_vector_operand (op0
, mode0
);
12506 if (VECTOR_MODE_P (mode1
))
12507 op1
= safe_vector_operand (op1
, mode1
);
12510 || GET_MODE (target
) != tmode
12511 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12512 target
= gen_reg_rtx (tmode
);
12514 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12516 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12517 op0
= copy_to_mode_reg (mode0
, op0
);
12518 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12519 op1
= copy_to_mode_reg (mode1
, op1
);
12521 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12528 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12531 arm_expand_unop_builtin (enum insn_code icode
,
12532 tree arglist
, rtx target
, int do_load
)
12535 tree arg0
= TREE_VALUE (arglist
);
12536 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12537 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12538 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12541 || GET_MODE (target
) != tmode
12542 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12543 target
= gen_reg_rtx (tmode
);
12545 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12548 if (VECTOR_MODE_P (mode0
))
12549 op0
= safe_vector_operand (op0
, mode0
);
12551 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12552 op0
= copy_to_mode_reg (mode0
, op0
);
12555 pat
= GEN_FCN (icode
) (target
, op0
);
12562 /* Expand an expression EXP that calls a built-in function,
12563 with result going to TARGET if that's convenient
12564 (and in mode MODE if that's convenient).
12565 SUBTARGET may be used as the target for computing one of EXP's operands.
12566 IGNORE is nonzero if the value is to be ignored. */
12569 arm_expand_builtin (tree exp
,
12571 rtx subtarget ATTRIBUTE_UNUSED
,
12572 enum machine_mode mode ATTRIBUTE_UNUSED
,
12573 int ignore ATTRIBUTE_UNUSED
)
12575 const struct builtin_description
* d
;
12576 enum insn_code icode
;
12577 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12578 tree arglist
= TREE_OPERAND (exp
, 1);
12586 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12588 enum machine_mode tmode
;
12589 enum machine_mode mode0
;
12590 enum machine_mode mode1
;
12591 enum machine_mode mode2
;
12595 case ARM_BUILTIN_TEXTRMSB
:
12596 case ARM_BUILTIN_TEXTRMUB
:
12597 case ARM_BUILTIN_TEXTRMSH
:
12598 case ARM_BUILTIN_TEXTRMUH
:
12599 case ARM_BUILTIN_TEXTRMSW
:
12600 case ARM_BUILTIN_TEXTRMUW
:
12601 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12602 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12603 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12604 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12605 : CODE_FOR_iwmmxt_textrmw
);
12607 arg0
= TREE_VALUE (arglist
);
12608 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12609 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12610 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12611 tmode
= insn_data
[icode
].operand
[0].mode
;
12612 mode0
= insn_data
[icode
].operand
[1].mode
;
12613 mode1
= insn_data
[icode
].operand
[2].mode
;
12615 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12616 op0
= copy_to_mode_reg (mode0
, op0
);
12617 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12619 /* @@@ better error message */
12620 error ("selector must be an immediate");
12621 return gen_reg_rtx (tmode
);
12624 || GET_MODE (target
) != tmode
12625 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12626 target
= gen_reg_rtx (tmode
);
12627 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12633 case ARM_BUILTIN_TINSRB
:
12634 case ARM_BUILTIN_TINSRH
:
12635 case ARM_BUILTIN_TINSRW
:
12636 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12637 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12638 : CODE_FOR_iwmmxt_tinsrw
);
12639 arg0
= TREE_VALUE (arglist
);
12640 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12641 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12642 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12643 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12644 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12645 tmode
= insn_data
[icode
].operand
[0].mode
;
12646 mode0
= insn_data
[icode
].operand
[1].mode
;
12647 mode1
= insn_data
[icode
].operand
[2].mode
;
12648 mode2
= insn_data
[icode
].operand
[3].mode
;
12650 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12651 op0
= copy_to_mode_reg (mode0
, op0
);
12652 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12653 op1
= copy_to_mode_reg (mode1
, op1
);
12654 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12656 /* @@@ better error message */
12657 error ("selector must be an immediate");
12661 || GET_MODE (target
) != tmode
12662 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12663 target
= gen_reg_rtx (tmode
);
12664 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12670 case ARM_BUILTIN_SETWCX
:
12671 arg0
= TREE_VALUE (arglist
);
12672 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12673 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12674 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12675 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12678 case ARM_BUILTIN_GETWCX
:
12679 arg0
= TREE_VALUE (arglist
);
12680 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12681 target
= gen_reg_rtx (SImode
);
12682 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12685 case ARM_BUILTIN_WSHUFH
:
12686 icode
= CODE_FOR_iwmmxt_wshufh
;
12687 arg0
= TREE_VALUE (arglist
);
12688 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12689 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12690 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12691 tmode
= insn_data
[icode
].operand
[0].mode
;
12692 mode1
= insn_data
[icode
].operand
[1].mode
;
12693 mode2
= insn_data
[icode
].operand
[2].mode
;
12695 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12696 op0
= copy_to_mode_reg (mode1
, op0
);
12697 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12699 /* @@@ better error message */
12700 error ("mask must be an immediate");
12704 || GET_MODE (target
) != tmode
12705 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12706 target
= gen_reg_rtx (tmode
);
12707 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12713 case ARM_BUILTIN_WSADB
:
12714 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12715 case ARM_BUILTIN_WSADH
:
12716 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12717 case ARM_BUILTIN_WSADBZ
:
12718 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12719 case ARM_BUILTIN_WSADHZ
:
12720 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12722 /* Several three-argument builtins. */
12723 case ARM_BUILTIN_WMACS
:
12724 case ARM_BUILTIN_WMACU
:
12725 case ARM_BUILTIN_WALIGN
:
12726 case ARM_BUILTIN_TMIA
:
12727 case ARM_BUILTIN_TMIAPH
:
12728 case ARM_BUILTIN_TMIATT
:
12729 case ARM_BUILTIN_TMIATB
:
12730 case ARM_BUILTIN_TMIABT
:
12731 case ARM_BUILTIN_TMIABB
:
12732 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12733 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12734 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12735 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12736 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12737 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12738 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12739 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12740 : CODE_FOR_iwmmxt_walign
);
12741 arg0
= TREE_VALUE (arglist
);
12742 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12743 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12744 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12745 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12746 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12747 tmode
= insn_data
[icode
].operand
[0].mode
;
12748 mode0
= insn_data
[icode
].operand
[1].mode
;
12749 mode1
= insn_data
[icode
].operand
[2].mode
;
12750 mode2
= insn_data
[icode
].operand
[3].mode
;
12752 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12753 op0
= copy_to_mode_reg (mode0
, op0
);
12754 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12755 op1
= copy_to_mode_reg (mode1
, op1
);
12756 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12757 op2
= copy_to_mode_reg (mode2
, op2
);
12759 || GET_MODE (target
) != tmode
12760 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12761 target
= gen_reg_rtx (tmode
);
12762 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12768 case ARM_BUILTIN_WZERO
:
12769 target
= gen_reg_rtx (DImode
);
12770 emit_insn (gen_iwmmxt_clrdi (target
));
12773 case ARM_BUILTIN_THREAD_POINTER
:
12774 return arm_load_tp (target
);
12780 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12781 if (d
->code
== (const enum arm_builtins
) fcode
)
12782 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12784 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12785 if (d
->code
== (const enum arm_builtins
) fcode
)
12786 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12788 /* @@@ Should really do something sensible here. */
12792 /* Return the number (counting from 0) of
12793 the least significant set bit in MASK. */
12796 number_of_first_bit_set (unsigned mask
)
12801 (mask
& (1 << bit
)) == 0;
12808 /* Emit code to push or pop registers to or from the stack. F is the
12809 assembly file. MASK is the registers to push or pop. PUSH is
12810 nonzero if we should push, and zero if we should pop. For debugging
12811 output, if pushing, adjust CFA_OFFSET by the amount of space added
12812 to the stack. REAL_REGS should have the same number of bits set as
12813 MASK, and will be used instead (in the same order) to describe which
12814 registers were saved - this is used to mark the save slots when we
12815 push high registers after moving them to low registers. */
12817 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12818 unsigned long real_regs
)
12821 int lo_mask
= mask
& 0xFF;
12822 int pushed_words
= 0;
12826 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12828 /* Special case. Do not generate a POP PC statement here, do it in
12830 thumb_exit (f
, -1);
12834 if (ARM_EABI_UNWIND_TABLES
&& push
)
12836 fprintf (f
, "\t.save\t{");
12837 for (regno
= 0; regno
< 15; regno
++)
12839 if (real_regs
& (1 << regno
))
12841 if (real_regs
& ((1 << regno
) -1))
12843 asm_fprintf (f
, "%r", regno
);
12846 fprintf (f
, "}\n");
12849 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12851 /* Look at the low registers first. */
12852 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12856 asm_fprintf (f
, "%r", regno
);
12858 if ((lo_mask
& ~1) != 0)
12865 if (push
&& (mask
& (1 << LR_REGNUM
)))
12867 /* Catch pushing the LR. */
12871 asm_fprintf (f
, "%r", LR_REGNUM
);
12875 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12877 /* Catch popping the PC. */
12878 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12879 || current_function_calls_eh_return
)
12881 /* The PC is never poped directly, instead
12882 it is popped into r3 and then BX is used. */
12883 fprintf (f
, "}\n");
12885 thumb_exit (f
, -1);
12894 asm_fprintf (f
, "%r", PC_REGNUM
);
12898 fprintf (f
, "}\n");
12900 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12902 char *l
= dwarf2out_cfi_label ();
12903 int pushed_mask
= real_regs
;
12905 *cfa_offset
+= pushed_words
* 4;
12906 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12909 pushed_mask
= real_regs
;
12910 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12912 if (pushed_mask
& 1)
12913 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12918 /* Generate code to return from a thumb function.
12919 If 'reg_containing_return_addr' is -1, then the return address is
12920 actually on the stack, at the stack pointer. */
12922 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12924 unsigned regs_available_for_popping
;
12925 unsigned regs_to_pop
;
12927 unsigned available
;
12931 int restore_a4
= FALSE
;
12933 /* Compute the registers we need to pop. */
12937 if (reg_containing_return_addr
== -1)
12939 regs_to_pop
|= 1 << LR_REGNUM
;
12943 if (TARGET_BACKTRACE
)
12945 /* Restore the (ARM) frame pointer and stack pointer. */
12946 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12950 /* If there is nothing to pop then just emit the BX instruction and
12952 if (pops_needed
== 0)
12954 if (current_function_calls_eh_return
)
12955 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12957 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12960 /* Otherwise if we are not supporting interworking and we have not created
12961 a backtrace structure and the function was not entered in ARM mode then
12962 just pop the return address straight into the PC. */
12963 else if (!TARGET_INTERWORK
12964 && !TARGET_BACKTRACE
12965 && !is_called_in_ARM_mode (current_function_decl
)
12966 && !current_function_calls_eh_return
)
12968 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12972 /* Find out how many of the (return) argument registers we can corrupt. */
12973 regs_available_for_popping
= 0;
12975 /* If returning via __builtin_eh_return, the bottom three registers
12976 all contain information needed for the return. */
12977 if (current_function_calls_eh_return
)
12981 /* If we can deduce the registers used from the function's
12982 return value. This is more reliable that examining
12983 regs_ever_live[] because that will be set if the register is
12984 ever used in the function, not just if the register is used
12985 to hold a return value. */
12987 if (current_function_return_rtx
!= 0)
12988 mode
= GET_MODE (current_function_return_rtx
);
12990 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12992 size
= GET_MODE_SIZE (mode
);
12996 /* In a void function we can use any argument register.
12997 In a function that returns a structure on the stack
12998 we can use the second and third argument registers. */
12999 if (mode
== VOIDmode
)
13000 regs_available_for_popping
=
13001 (1 << ARG_REGISTER (1))
13002 | (1 << ARG_REGISTER (2))
13003 | (1 << ARG_REGISTER (3));
13005 regs_available_for_popping
=
13006 (1 << ARG_REGISTER (2))
13007 | (1 << ARG_REGISTER (3));
13009 else if (size
<= 4)
13010 regs_available_for_popping
=
13011 (1 << ARG_REGISTER (2))
13012 | (1 << ARG_REGISTER (3));
13013 else if (size
<= 8)
13014 regs_available_for_popping
=
13015 (1 << ARG_REGISTER (3));
13018 /* Match registers to be popped with registers into which we pop them. */
13019 for (available
= regs_available_for_popping
,
13020 required
= regs_to_pop
;
13021 required
!= 0 && available
!= 0;
13022 available
&= ~(available
& - available
),
13023 required
&= ~(required
& - required
))
13026 /* If we have any popping registers left over, remove them. */
13028 regs_available_for_popping
&= ~available
;
13030 /* Otherwise if we need another popping register we can use
13031 the fourth argument register. */
13032 else if (pops_needed
)
13034 /* If we have not found any free argument registers and
13035 reg a4 contains the return address, we must move it. */
13036 if (regs_available_for_popping
== 0
13037 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13039 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13040 reg_containing_return_addr
= LR_REGNUM
;
13042 else if (size
> 12)
13044 /* Register a4 is being used to hold part of the return value,
13045 but we have dire need of a free, low register. */
13048 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13051 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13053 /* The fourth argument register is available. */
13054 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13060 /* Pop as many registers as we can. */
13061 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13062 regs_available_for_popping
);
13064 /* Process the registers we popped. */
13065 if (reg_containing_return_addr
== -1)
13067 /* The return address was popped into the lowest numbered register. */
13068 regs_to_pop
&= ~(1 << LR_REGNUM
);
13070 reg_containing_return_addr
=
13071 number_of_first_bit_set (regs_available_for_popping
);
13073 /* Remove this register for the mask of available registers, so that
13074 the return address will not be corrupted by further pops. */
13075 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13078 /* If we popped other registers then handle them here. */
13079 if (regs_available_for_popping
)
13083 /* Work out which register currently contains the frame pointer. */
13084 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13086 /* Move it into the correct place. */
13087 asm_fprintf (f
, "\tmov\t%r, %r\n",
13088 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13090 /* (Temporarily) remove it from the mask of popped registers. */
13091 regs_available_for_popping
&= ~(1 << frame_pointer
);
13092 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13094 if (regs_available_for_popping
)
13098 /* We popped the stack pointer as well,
13099 find the register that contains it. */
13100 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13102 /* Move it into the stack register. */
13103 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13105 /* At this point we have popped all necessary registers, so
13106 do not worry about restoring regs_available_for_popping
13107 to its correct value:
13109 assert (pops_needed == 0)
13110 assert (regs_available_for_popping == (1 << frame_pointer))
13111 assert (regs_to_pop == (1 << STACK_POINTER)) */
13115 /* Since we have just move the popped value into the frame
13116 pointer, the popping register is available for reuse, and
13117 we know that we still have the stack pointer left to pop. */
13118 regs_available_for_popping
|= (1 << frame_pointer
);
13122 /* If we still have registers left on the stack, but we no longer have
13123 any registers into which we can pop them, then we must move the return
13124 address into the link register and make available the register that
13126 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13128 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13130 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13131 reg_containing_return_addr
);
13133 reg_containing_return_addr
= LR_REGNUM
;
13136 /* If we have registers left on the stack then pop some more.
13137 We know that at most we will want to pop FP and SP. */
13138 if (pops_needed
> 0)
13143 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13144 regs_available_for_popping
);
13146 /* We have popped either FP or SP.
13147 Move whichever one it is into the correct register. */
13148 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13149 move_to
= number_of_first_bit_set (regs_to_pop
);
13151 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13153 regs_to_pop
&= ~(1 << move_to
);
13158 /* If we still have not popped everything then we must have only
13159 had one register available to us and we are now popping the SP. */
13160 if (pops_needed
> 0)
13164 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13165 regs_available_for_popping
);
13167 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13169 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13171 assert (regs_to_pop == (1 << STACK_POINTER))
13172 assert (pops_needed == 1)
13176 /* If necessary restore the a4 register. */
13179 if (reg_containing_return_addr
!= LR_REGNUM
)
13181 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13182 reg_containing_return_addr
= LR_REGNUM
;
13185 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13188 if (current_function_calls_eh_return
)
13189 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13191 /* Return to caller. */
13192 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13197 thumb_final_prescan_insn (rtx insn
)
13199 if (flag_print_asm_name
)
13200 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13201 INSN_ADDRESSES (INSN_UID (insn
)));
13205 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13207 unsigned HOST_WIDE_INT mask
= 0xff;
13210 if (val
== 0) /* XXX */
13213 for (i
= 0; i
< 25; i
++)
13214 if ((val
& (mask
<< i
)) == val
)
13220 /* Returns nonzero if the current function contains,
13221 or might contain a far jump. */
13223 thumb_far_jump_used_p (void)
13227 /* This test is only important for leaf functions. */
13228 /* assert (!leaf_function_p ()); */
13230 /* If we have already decided that far jumps may be used,
13231 do not bother checking again, and always return true even if
13232 it turns out that they are not being used. Once we have made
13233 the decision that far jumps are present (and that hence the link
13234 register will be pushed onto the stack) we cannot go back on it. */
13235 if (cfun
->machine
->far_jump_used
)
13238 /* If this function is not being called from the prologue/epilogue
13239 generation code then it must be being called from the
13240 INITIAL_ELIMINATION_OFFSET macro. */
13241 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13243 /* In this case we know that we are being asked about the elimination
13244 of the arg pointer register. If that register is not being used,
13245 then there are no arguments on the stack, and we do not have to
13246 worry that a far jump might force the prologue to push the link
13247 register, changing the stack offsets. In this case we can just
13248 return false, since the presence of far jumps in the function will
13249 not affect stack offsets.
13251 If the arg pointer is live (or if it was live, but has now been
13252 eliminated and so set to dead) then we do have to test to see if
13253 the function might contain a far jump. This test can lead to some
13254 false negatives, since before reload is completed, then length of
13255 branch instructions is not known, so gcc defaults to returning their
13256 longest length, which in turn sets the far jump attribute to true.
13258 A false negative will not result in bad code being generated, but it
13259 will result in a needless push and pop of the link register. We
13260 hope that this does not occur too often.
13262 If we need doubleword stack alignment this could affect the other
13263 elimination offsets so we can't risk getting it wrong. */
13264 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13265 cfun
->machine
->arg_pointer_live
= 1;
13266 else if (!cfun
->machine
->arg_pointer_live
)
13270 /* Check to see if the function contains a branch
13271 insn with the far jump attribute set. */
13272 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13274 if (GET_CODE (insn
) == JUMP_INSN
13275 /* Ignore tablejump patterns. */
13276 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13277 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13278 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13281 /* Record the fact that we have decided that
13282 the function does use far jumps. */
13283 cfun
->machine
->far_jump_used
= 1;
13291 /* Return nonzero if FUNC must be entered in ARM mode. */
13293 is_called_in_ARM_mode (tree func
)
13295 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13297 /* Ignore the problem about functions whose address is taken. */
13298 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13302 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13308 /* The bits which aren't usefully expanded as rtl. */
13310 thumb_unexpanded_epilogue (void)
13313 unsigned long live_regs_mask
= 0;
13314 int high_regs_pushed
= 0;
13315 int had_to_push_lr
;
13318 if (return_used_this_function
)
13321 if (IS_NAKED (arm_current_func_type ()))
13324 live_regs_mask
= thumb_compute_save_reg_mask ();
13325 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13327 /* If we can deduce the registers used from the function's return value.
13328 This is more reliable that examining regs_ever_live[] because that
13329 will be set if the register is ever used in the function, not just if
13330 the register is used to hold a return value. */
13331 size
= arm_size_return_regs ();
13333 /* The prolog may have pushed some high registers to use as
13334 work registers. e.g. the testsuite file:
13335 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13336 compiles to produce:
13337 push {r4, r5, r6, r7, lr}
13341 as part of the prolog. We have to undo that pushing here. */
13343 if (high_regs_pushed
)
13345 unsigned long mask
= live_regs_mask
& 0xff;
13348 /* The available low registers depend on the size of the value we are
13356 /* Oh dear! We have no low registers into which we can pop
13359 ("no low registers available for popping high registers");
13361 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13362 if (live_regs_mask
& (1 << next_hi_reg
))
13365 while (high_regs_pushed
)
13367 /* Find lo register(s) into which the high register(s) can
13369 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13371 if (mask
& (1 << regno
))
13372 high_regs_pushed
--;
13373 if (high_regs_pushed
== 0)
13377 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13379 /* Pop the values into the low register(s). */
13380 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13382 /* Move the value(s) into the high registers. */
13383 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13385 if (mask
& (1 << regno
))
13387 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13390 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13391 if (live_regs_mask
& (1 << next_hi_reg
))
13396 live_regs_mask
&= ~0x0f00;
13399 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13400 live_regs_mask
&= 0xff;
13402 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13404 /* Pop the return address into the PC. */
13405 if (had_to_push_lr
)
13406 live_regs_mask
|= 1 << PC_REGNUM
;
13408 /* Either no argument registers were pushed or a backtrace
13409 structure was created which includes an adjusted stack
13410 pointer, so just pop everything. */
13411 if (live_regs_mask
)
13412 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13415 /* We have either just popped the return address into the
13416 PC or it is was kept in LR for the entire function. */
13417 if (!had_to_push_lr
)
13418 thumb_exit (asm_out_file
, LR_REGNUM
);
13422 /* Pop everything but the return address. */
13423 if (live_regs_mask
)
13424 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13427 if (had_to_push_lr
)
13431 /* We have no free low regs, so save one. */
13432 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13436 /* Get the return address into a temporary register. */
13437 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13438 1 << LAST_ARG_REGNUM
);
13442 /* Move the return address to lr. */
13443 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13445 /* Restore the low register. */
13446 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13451 regno
= LAST_ARG_REGNUM
;
13456 /* Remove the argument registers that were pushed onto the stack. */
13457 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13458 SP_REGNUM
, SP_REGNUM
,
13459 current_function_pretend_args_size
);
13461 thumb_exit (asm_out_file
, regno
);
13467 /* Functions to save and restore machine-specific function data. */
13468 static struct machine_function
*
13469 arm_init_machine_status (void)
13471 struct machine_function
*machine
;
13472 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13474 #if ARM_FT_UNKNOWN != 0
13475 machine
->func_type
= ARM_FT_UNKNOWN
;
13480 /* Return an RTX indicating where the return address to the
13481 calling function can be found. */
13483 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13488 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13491 /* Do anything needed before RTL is emitted for each function. */
13493 arm_init_expanders (void)
13495 /* Arrange to initialize and mark the machine per-function status. */
13496 init_machine_status
= arm_init_machine_status
;
13498 /* This is to stop the combine pass optimizing away the alignment
13499 adjustment of va_arg. */
13500 /* ??? It is claimed that this should not be necessary. */
13502 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13506 /* Like arm_compute_initial_elimination offset. Simpler because there
13507 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13508 to point at the base of the local variables after static stack
13509 space for a function has been allocated. */
13512 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13514 arm_stack_offsets
*offsets
;
13516 offsets
= arm_get_frame_offsets ();
13520 case ARG_POINTER_REGNUM
:
13523 case STACK_POINTER_REGNUM
:
13524 return offsets
->outgoing_args
- offsets
->saved_args
;
13526 case FRAME_POINTER_REGNUM
:
13527 return offsets
->soft_frame
- offsets
->saved_args
;
13529 case ARM_HARD_FRAME_POINTER_REGNUM
:
13530 return offsets
->saved_regs
- offsets
->saved_args
;
13532 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13533 return offsets
->locals_base
- offsets
->saved_args
;
13536 gcc_unreachable ();
13540 case FRAME_POINTER_REGNUM
:
13543 case STACK_POINTER_REGNUM
:
13544 return offsets
->outgoing_args
- offsets
->soft_frame
;
13546 case ARM_HARD_FRAME_POINTER_REGNUM
:
13547 return offsets
->saved_regs
- offsets
->soft_frame
;
13549 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13550 return offsets
->locals_base
- offsets
->soft_frame
;
13553 gcc_unreachable ();
13558 gcc_unreachable ();
13563 /* Generate the rest of a function's prologue. */
13565 thumb_expand_prologue (void)
13569 HOST_WIDE_INT amount
;
13570 arm_stack_offsets
*offsets
;
13571 unsigned long func_type
;
13573 unsigned long live_regs_mask
;
13575 func_type
= arm_current_func_type ();
13577 /* Naked functions don't have prologues. */
13578 if (IS_NAKED (func_type
))
13581 if (IS_INTERRUPT (func_type
))
13583 error ("interrupt Service Routines cannot be coded in Thumb mode");
13587 live_regs_mask
= thumb_compute_save_reg_mask ();
13588 /* Load the pic register before setting the frame pointer,
13589 so we can use r7 as a temporary work register. */
13591 arm_load_pic_register (live_regs_mask
);
13593 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13594 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13595 stack_pointer_rtx
);
13597 offsets
= arm_get_frame_offsets ();
13598 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13603 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13604 GEN_INT (- amount
)));
13605 RTX_FRAME_RELATED_P (insn
) = 1;
13611 /* The stack decrement is too big for an immediate value in a single
13612 insn. In theory we could issue multiple subtracts, but after
13613 three of them it becomes more space efficient to place the full
13614 value in the constant pool and load into a register. (Also the
13615 ARM debugger really likes to see only one stack decrement per
13616 function). So instead we look for a scratch register into which
13617 we can load the decrement, and then we subtract this from the
13618 stack pointer. Unfortunately on the thumb the only available
13619 scratch registers are the argument registers, and we cannot use
13620 these as they may hold arguments to the function. Instead we
13621 attempt to locate a call preserved register which is used by this
13622 function. If we can find one, then we know that it will have
13623 been pushed at the start of the prologue and so we can corrupt
13625 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13626 if (live_regs_mask
& (1 << regno
)
13627 && !(frame_pointer_needed
13628 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13631 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13633 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13635 /* Choose an arbitrary, non-argument low register. */
13636 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13638 /* Save it by copying it into a high, scratch register. */
13639 emit_insn (gen_movsi (spare
, reg
));
13640 /* Add a USE to stop propagate_one_insn() from barfing. */
13641 emit_insn (gen_prologue_use (spare
));
13643 /* Decrement the stack. */
13644 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13645 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13646 stack_pointer_rtx
, reg
));
13647 RTX_FRAME_RELATED_P (insn
) = 1;
13648 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13649 plus_constant (stack_pointer_rtx
,
13651 RTX_FRAME_RELATED_P (dwarf
) = 1;
13653 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13656 /* Restore the low register's original value. */
13657 emit_insn (gen_movsi (reg
, spare
));
13659 /* Emit a USE of the restored scratch register, so that flow
13660 analysis will not consider the restore redundant. The
13661 register won't be used again in this function and isn't
13662 restored by the epilogue. */
13663 emit_insn (gen_prologue_use (reg
));
13667 reg
= gen_rtx_REG (SImode
, regno
);
13669 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13671 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13672 stack_pointer_rtx
, reg
));
13673 RTX_FRAME_RELATED_P (insn
) = 1;
13674 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13675 plus_constant (stack_pointer_rtx
,
13677 RTX_FRAME_RELATED_P (dwarf
) = 1;
13679 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13685 if (frame_pointer_needed
)
13687 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13690 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13691 stack_pointer_rtx
, GEN_INT (amount
)));
13694 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13695 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13696 hard_frame_pointer_rtx
,
13697 stack_pointer_rtx
));
13698 dwarf
= gen_rtx_SET (SImode
, hard_frame_pointer_rtx
,
13699 plus_constant (stack_pointer_rtx
, amount
));
13700 RTX_FRAME_RELATED_P (dwarf
) = 1;
13701 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13705 RTX_FRAME_RELATED_P (insn
) = 1;
13708 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13709 emit_insn (gen_blockage ());
13711 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13712 if (live_regs_mask
& 0xff)
13713 cfun
->machine
->lr_save_eliminated
= 0;
13715 /* If the link register is being kept alive, with the return address in it,
13716 then make sure that it does not get reused by the ce2 pass. */
13717 if (cfun
->machine
->lr_save_eliminated
)
13718 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13723 thumb_expand_epilogue (void)
13725 HOST_WIDE_INT amount
;
13726 arm_stack_offsets
*offsets
;
13729 /* Naked functions don't have prologues. */
13730 if (IS_NAKED (arm_current_func_type ()))
13733 offsets
= arm_get_frame_offsets ();
13734 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13736 if (frame_pointer_needed
)
13738 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13739 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13745 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13746 GEN_INT (amount
)));
13749 /* r3 is always free in the epilogue. */
13750 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13752 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13753 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13757 /* Emit a USE (stack_pointer_rtx), so that
13758 the stack adjustment will not be deleted. */
13759 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13761 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13762 emit_insn (gen_blockage ());
13764 /* Emit a clobber for each insn that will be restored in the epilogue,
13765 so that flow2 will get register lifetimes correct. */
13766 for (regno
= 0; regno
< 13; regno
++)
13767 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13768 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13770 if (! regs_ever_live
[LR_REGNUM
])
13771 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13775 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13777 unsigned long live_regs_mask
= 0;
13778 unsigned long l_mask
;
13779 unsigned high_regs_pushed
= 0;
13780 int cfa_offset
= 0;
13783 if (IS_NAKED (arm_current_func_type ()))
13786 if (is_called_in_ARM_mode (current_function_decl
))
13790 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13791 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13793 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13795 /* Generate code sequence to switch us into Thumb mode. */
13796 /* The .code 32 directive has already been emitted by
13797 ASM_DECLARE_FUNCTION_NAME. */
13798 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13799 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13801 /* Generate a label, so that the debugger will notice the
13802 change in instruction sets. This label is also used by
13803 the assembler to bypass the ARM code when this function
13804 is called from a Thumb encoded function elsewhere in the
13805 same file. Hence the definition of STUB_NAME here must
13806 agree with the definition in gas/config/tc-arm.c. */
13808 #define STUB_NAME ".real_start_of"
13810 fprintf (f
, "\t.code\t16\n");
13812 if (arm_dllexport_name_p (name
))
13813 name
= arm_strip_name_encoding (name
);
13815 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13816 fprintf (f
, "\t.thumb_func\n");
13817 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13820 if (current_function_pretend_args_size
)
13822 /* Output unwind directive for the stack adjustment. */
13823 if (ARM_EABI_UNWIND_TABLES
)
13824 fprintf (f
, "\t.pad #%d\n",
13825 current_function_pretend_args_size
);
13827 if (cfun
->machine
->uses_anonymous_args
)
13831 fprintf (f
, "\tpush\t{");
13833 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13835 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13836 regno
<= LAST_ARG_REGNUM
;
13838 asm_fprintf (f
, "%r%s", regno
,
13839 regno
== LAST_ARG_REGNUM
? "" : ", ");
13841 fprintf (f
, "}\n");
13844 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13845 SP_REGNUM
, SP_REGNUM
,
13846 current_function_pretend_args_size
);
13848 /* We don't need to record the stores for unwinding (would it
13849 help the debugger any if we did?), but record the change in
13850 the stack pointer. */
13851 if (dwarf2out_do_frame ())
13853 char *l
= dwarf2out_cfi_label ();
13855 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13856 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13860 /* Get the registers we are going to push. */
13861 live_regs_mask
= thumb_compute_save_reg_mask ();
13862 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13863 l_mask
= live_regs_mask
& 0x40ff;
13864 /* Then count how many other high registers will need to be pushed. */
13865 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13867 if (TARGET_BACKTRACE
)
13870 unsigned work_register
;
13872 /* We have been asked to create a stack backtrace structure.
13873 The code looks like this:
13877 0 sub SP, #16 Reserve space for 4 registers.
13878 2 push {R7} Push low registers.
13879 4 add R7, SP, #20 Get the stack pointer before the push.
13880 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13881 8 mov R7, PC Get hold of the start of this code plus 12.
13882 10 str R7, [SP, #16] Store it.
13883 12 mov R7, FP Get hold of the current frame pointer.
13884 14 str R7, [SP, #4] Store it.
13885 16 mov R7, LR Get hold of the current return address.
13886 18 str R7, [SP, #12] Store it.
13887 20 add R7, SP, #16 Point at the start of the backtrace structure.
13888 22 mov FP, R7 Put this value into the frame pointer. */
13890 work_register
= thumb_find_work_register (live_regs_mask
);
13892 if (ARM_EABI_UNWIND_TABLES
)
13893 asm_fprintf (f
, "\t.pad #16\n");
13896 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13897 SP_REGNUM
, SP_REGNUM
);
13899 if (dwarf2out_do_frame ())
13901 char *l
= dwarf2out_cfi_label ();
13903 cfa_offset
= cfa_offset
+ 16;
13904 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13909 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13910 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13915 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13916 offset
+ 16 + current_function_pretend_args_size
);
13918 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13921 /* Make sure that the instruction fetching the PC is in the right place
13922 to calculate "start of backtrace creation code + 12". */
13925 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13926 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13928 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13929 ARM_HARD_FRAME_POINTER_REGNUM
);
13930 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13935 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13936 ARM_HARD_FRAME_POINTER_REGNUM
);
13937 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13939 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13940 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13944 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13945 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13947 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13949 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13950 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13952 /* Optimization: If we are not pushing any low registers but we are going
13953 to push some high registers then delay our first push. This will just
13954 be a push of LR and we can combine it with the push of the first high
13956 else if ((l_mask
& 0xff) != 0
13957 || (high_regs_pushed
== 0 && l_mask
))
13958 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13960 if (high_regs_pushed
)
13962 unsigned pushable_regs
;
13963 unsigned next_hi_reg
;
13965 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13966 if (live_regs_mask
& (1 << next_hi_reg
))
13969 pushable_regs
= l_mask
& 0xff;
13971 if (pushable_regs
== 0)
13972 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13974 while (high_regs_pushed
> 0)
13976 unsigned long real_regs_mask
= 0;
13978 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13980 if (pushable_regs
& (1 << regno
))
13982 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13984 high_regs_pushed
--;
13985 real_regs_mask
|= (1 << next_hi_reg
);
13987 if (high_regs_pushed
)
13989 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13991 if (live_regs_mask
& (1 << next_hi_reg
))
13996 pushable_regs
&= ~((1 << regno
) - 1);
14002 /* If we had to find a work register and we have not yet
14003 saved the LR then add it to the list of regs to push. */
14004 if (l_mask
== (1 << LR_REGNUM
))
14006 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14008 real_regs_mask
| (1 << LR_REGNUM
));
14012 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14017 /* Handle the case of a double word load into a low register from
14018 a computed memory address. The computed address may involve a
14019 register which is overwritten by the load. */
14021 thumb_load_double_from_address (rtx
*operands
)
14029 gcc_assert (GET_CODE (operands
[0]) == REG
);
14030 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14032 /* Get the memory address. */
14033 addr
= XEXP (operands
[1], 0);
14035 /* Work out how the memory address is computed. */
14036 switch (GET_CODE (addr
))
14039 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14041 if (REGNO (operands
[0]) == REGNO (addr
))
14043 output_asm_insn ("ldr\t%H0, %2", operands
);
14044 output_asm_insn ("ldr\t%0, %1", operands
);
14048 output_asm_insn ("ldr\t%0, %1", operands
);
14049 output_asm_insn ("ldr\t%H0, %2", operands
);
14054 /* Compute <address> + 4 for the high order load. */
14055 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14057 output_asm_insn ("ldr\t%0, %1", operands
);
14058 output_asm_insn ("ldr\t%H0, %2", operands
);
14062 arg1
= XEXP (addr
, 0);
14063 arg2
= XEXP (addr
, 1);
14065 if (CONSTANT_P (arg1
))
14066 base
= arg2
, offset
= arg1
;
14068 base
= arg1
, offset
= arg2
;
14070 gcc_assert (GET_CODE (base
) == REG
);
14072 /* Catch the case of <address> = <reg> + <reg> */
14073 if (GET_CODE (offset
) == REG
)
14075 int reg_offset
= REGNO (offset
);
14076 int reg_base
= REGNO (base
);
14077 int reg_dest
= REGNO (operands
[0]);
14079 /* Add the base and offset registers together into the
14080 higher destination register. */
14081 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14082 reg_dest
+ 1, reg_base
, reg_offset
);
14084 /* Load the lower destination register from the address in
14085 the higher destination register. */
14086 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14087 reg_dest
, reg_dest
+ 1);
14089 /* Load the higher destination register from its own address
14091 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14092 reg_dest
+ 1, reg_dest
+ 1);
14096 /* Compute <address> + 4 for the high order load. */
14097 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14099 /* If the computed address is held in the low order register
14100 then load the high order register first, otherwise always
14101 load the low order register first. */
14102 if (REGNO (operands
[0]) == REGNO (base
))
14104 output_asm_insn ("ldr\t%H0, %2", operands
);
14105 output_asm_insn ("ldr\t%0, %1", operands
);
14109 output_asm_insn ("ldr\t%0, %1", operands
);
14110 output_asm_insn ("ldr\t%H0, %2", operands
);
14116 /* With no registers to worry about we can just load the value
14118 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14120 output_asm_insn ("ldr\t%H0, %2", operands
);
14121 output_asm_insn ("ldr\t%0, %1", operands
);
14125 gcc_unreachable ();
14132 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14139 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14142 operands
[4] = operands
[5];
14145 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14146 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14150 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14153 operands
[4] = operands
[5];
14156 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14159 operands
[5] = operands
[6];
14162 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14165 operands
[4] = operands
[5];
14169 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14170 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14174 gcc_unreachable ();
14180 /* Output a call-via instruction for thumb state. */
14182 thumb_call_via_reg (rtx reg
)
14184 int regno
= REGNO (reg
);
14187 gcc_assert (regno
< LR_REGNUM
);
14189 /* If we are in the normal text section we can use a single instance
14190 per compilation unit. If we are doing function sections, then we need
14191 an entry per section, since we can't rely on reachability. */
14192 if (in_text_section ())
14194 thumb_call_reg_needed
= 1;
14196 if (thumb_call_via_label
[regno
] == NULL
)
14197 thumb_call_via_label
[regno
] = gen_label_rtx ();
14198 labelp
= thumb_call_via_label
+ regno
;
14202 if (cfun
->machine
->call_via
[regno
] == NULL
)
14203 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14204 labelp
= cfun
->machine
->call_via
+ regno
;
14207 output_asm_insn ("bl\t%a0", labelp
);
14211 /* Routines for generating rtl. */
14213 thumb_expand_movmemqi (rtx
*operands
)
14215 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14216 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14217 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14218 HOST_WIDE_INT offset
= 0;
14222 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14228 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14234 rtx reg
= gen_reg_rtx (SImode
);
14235 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14236 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14243 rtx reg
= gen_reg_rtx (HImode
);
14244 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14245 plus_constant (in
, offset
))));
14246 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14254 rtx reg
= gen_reg_rtx (QImode
);
14255 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14256 plus_constant (in
, offset
))));
14257 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14263 thumb_reload_out_hi (rtx
*operands
)
14265 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14268 /* Handle reading a half-word from memory during reload. */
14270 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14272 gcc_unreachable ();
14275 /* Return the length of a function name prefix
14276 that starts with the character 'c'. */
14278 arm_get_strip_length (int c
)
14282 ARM_NAME_ENCODING_LENGTHS
14287 /* Return a pointer to a function's name with any
14288 and all prefix encodings stripped from it. */
14290 arm_strip_name_encoding (const char *name
)
14294 while ((skip
= arm_get_strip_length (* name
)))
14300 /* If there is a '*' anywhere in the name's prefix, then
14301 emit the stripped name verbatim, otherwise prepend an
14302 underscore if leading underscores are being used. */
14304 arm_asm_output_labelref (FILE *stream
, const char *name
)
14309 while ((skip
= arm_get_strip_length (* name
)))
14311 verbatim
|= (*name
== '*');
14316 fputs (name
, stream
);
14318 asm_fprintf (stream
, "%U%s", name
);
14322 arm_file_end (void)
14326 if (! thumb_call_reg_needed
)
14330 asm_fprintf (asm_out_file
, "\t.code 16\n");
14331 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14333 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14335 rtx label
= thumb_call_via_label
[regno
];
14339 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14340 CODE_LABEL_NUMBER (label
));
14341 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14348 #ifdef AOF_ASSEMBLER
14349 /* Special functions only needed when producing AOF syntax assembler. */
14353 struct pic_chain
* next
;
14354 const char * symname
;
14357 static struct pic_chain
* aof_pic_chain
= NULL
;
14360 aof_pic_entry (rtx x
)
14362 struct pic_chain
** chainp
;
14365 if (aof_pic_label
== NULL_RTX
)
14367 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14370 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14371 offset
+= 4, chainp
= &(*chainp
)->next
)
14372 if ((*chainp
)->symname
== XSTR (x
, 0))
14373 return plus_constant (aof_pic_label
, offset
);
14375 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14376 (*chainp
)->next
= NULL
;
14377 (*chainp
)->symname
= XSTR (x
, 0);
14378 return plus_constant (aof_pic_label
, offset
);
14382 aof_dump_pic_table (FILE *f
)
14384 struct pic_chain
* chain
;
14386 if (aof_pic_chain
== NULL
)
14389 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14390 PIC_OFFSET_TABLE_REGNUM
,
14391 PIC_OFFSET_TABLE_REGNUM
);
14392 fputs ("|x$adcons|\n", f
);
14394 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14396 fputs ("\tDCD\t", f
);
14397 assemble_name (f
, chain
->symname
);
14402 int arm_text_section_count
= 1;
14405 aof_text_section (void )
14407 static char buf
[100];
14408 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14409 arm_text_section_count
++);
14411 strcat (buf
, ", PIC, REENTRANT");
14415 static int arm_data_section_count
= 1;
14418 aof_data_section (void)
14420 static char buf
[100];
14421 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14425 /* The AOF assembler is religiously strict about declarations of
14426 imported and exported symbols, so that it is impossible to declare
14427 a function as imported near the beginning of the file, and then to
14428 export it later on. It is, however, possible to delay the decision
14429 until all the functions in the file have been compiled. To get
14430 around this, we maintain a list of the imports and exports, and
14431 delete from it any that are subsequently defined. At the end of
14432 compilation we spit the remainder of the list out before the END
14437 struct import
* next
;
14441 static struct import
* imports_list
= NULL
;
14444 aof_add_import (const char *name
)
14446 struct import
* new;
14448 for (new = imports_list
; new; new = new->next
)
14449 if (new->name
== name
)
14452 new = (struct import
*) xmalloc (sizeof (struct import
));
14453 new->next
= imports_list
;
14454 imports_list
= new;
14459 aof_delete_import (const char *name
)
14461 struct import
** old
;
14463 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14465 if ((*old
)->name
== name
)
14467 *old
= (*old
)->next
;
14473 int arm_main_function
= 0;
14476 aof_dump_imports (FILE *f
)
14478 /* The AOF assembler needs this to cause the startup code to be extracted
14479 from the library. Brining in __main causes the whole thing to work
14481 if (arm_main_function
)
14484 fputs ("\tIMPORT __main\n", f
);
14485 fputs ("\tDCD __main\n", f
);
14488 /* Now dump the remaining imports. */
14489 while (imports_list
)
14491 fprintf (f
, "\tIMPORT\t");
14492 assemble_name (f
, imports_list
->name
);
14494 imports_list
= imports_list
->next
;
14499 aof_globalize_label (FILE *stream
, const char *name
)
14501 default_globalize_label (stream
, name
);
14502 if (! strcmp (name
, "main"))
14503 arm_main_function
= 1;
14507 aof_file_start (void)
14509 fputs ("__r0\tRN\t0\n", asm_out_file
);
14510 fputs ("__a1\tRN\t0\n", asm_out_file
);
14511 fputs ("__a2\tRN\t1\n", asm_out_file
);
14512 fputs ("__a3\tRN\t2\n", asm_out_file
);
14513 fputs ("__a4\tRN\t3\n", asm_out_file
);
14514 fputs ("__v1\tRN\t4\n", asm_out_file
);
14515 fputs ("__v2\tRN\t5\n", asm_out_file
);
14516 fputs ("__v3\tRN\t6\n", asm_out_file
);
14517 fputs ("__v4\tRN\t7\n", asm_out_file
);
14518 fputs ("__v5\tRN\t8\n", asm_out_file
);
14519 fputs ("__v6\tRN\t9\n", asm_out_file
);
14520 fputs ("__sl\tRN\t10\n", asm_out_file
);
14521 fputs ("__fp\tRN\t11\n", asm_out_file
);
14522 fputs ("__ip\tRN\t12\n", asm_out_file
);
14523 fputs ("__sp\tRN\t13\n", asm_out_file
);
14524 fputs ("__lr\tRN\t14\n", asm_out_file
);
14525 fputs ("__pc\tRN\t15\n", asm_out_file
);
14526 fputs ("__f0\tFN\t0\n", asm_out_file
);
14527 fputs ("__f1\tFN\t1\n", asm_out_file
);
14528 fputs ("__f2\tFN\t2\n", asm_out_file
);
14529 fputs ("__f3\tFN\t3\n", asm_out_file
);
14530 fputs ("__f4\tFN\t4\n", asm_out_file
);
14531 fputs ("__f5\tFN\t5\n", asm_out_file
);
14532 fputs ("__f6\tFN\t6\n", asm_out_file
);
14533 fputs ("__f7\tFN\t7\n", asm_out_file
);
14538 aof_file_end (void)
14541 aof_dump_pic_table (asm_out_file
);
14543 aof_dump_imports (asm_out_file
);
14544 fputs ("\tEND\n", asm_out_file
);
14546 #endif /* AOF_ASSEMBLER */
14549 /* Symbols in the text segment can be accessed without indirecting via the
14550 constant pool; it may take an extra binary operation, but this is still
14551 faster than indirecting via memory. Don't do this when not optimizing,
14552 since we won't be calculating al of the offsets necessary to do this
14556 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14558 /* This doesn't work with AOF syntax, since the string table may be in
14559 a different AREA. */
14560 #ifndef AOF_ASSEMBLER
14561 if (optimize
> 0 && TREE_CONSTANT (decl
))
14562 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14565 /* If we are referencing a function that is weak then encode a long call
14566 flag in the function name, otherwise if the function is static or
14567 or known to be defined in this file then encode a short call flag. */
14568 if (first
&& DECL_P (decl
))
14570 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14571 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14572 else if (! TREE_PUBLIC (decl
))
14573 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14576 default_encode_section_info (decl
, rtl
, first
);
14578 #endif /* !ARM_PE */
14581 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14583 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14584 && !strcmp (prefix
, "L"))
14586 arm_ccfsm_state
= 0;
14587 arm_target_insn
= NULL
;
14589 default_internal_label (stream
, prefix
, labelno
);
14592 /* Output code to add DELTA to the first argument, and then jump
14593 to FUNCTION. Used for C++ multiple inheritance. */
14595 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14596 HOST_WIDE_INT delta
,
14597 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14600 static int thunk_label
= 0;
14602 int mi_delta
= delta
;
14603 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14605 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14608 mi_delta
= - mi_delta
;
14611 int labelno
= thunk_label
++;
14612 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14613 fputs ("\tldr\tr12, ", file
);
14614 assemble_name (file
, label
);
14615 fputc ('\n', file
);
14617 while (mi_delta
!= 0)
14619 if ((mi_delta
& (3 << shift
)) == 0)
14623 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14624 mi_op
, this_regno
, this_regno
,
14625 mi_delta
& (0xff << shift
));
14626 mi_delta
&= ~(0xff << shift
);
14632 fprintf (file
, "\tbx\tr12\n");
14633 ASM_OUTPUT_ALIGN (file
, 2);
14634 assemble_name (file
, label
);
14635 fputs (":\n", file
);
14636 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14640 fputs ("\tb\t", file
);
14641 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14642 if (NEED_PLT_RELOC
)
14643 fputs ("(PLT)", file
);
14644 fputc ('\n', file
);
14649 arm_emit_vector_const (FILE *file
, rtx x
)
14652 const char * pattern
;
14654 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14656 switch (GET_MODE (x
))
14658 case V2SImode
: pattern
= "%08x"; break;
14659 case V4HImode
: pattern
= "%04x"; break;
14660 case V8QImode
: pattern
= "%02x"; break;
14661 default: gcc_unreachable ();
14664 fprintf (file
, "0x");
14665 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14669 element
= CONST_VECTOR_ELT (x
, i
);
14670 fprintf (file
, pattern
, INTVAL (element
));
14677 arm_output_load_gr (rtx
*operands
)
14684 if (GET_CODE (operands
[1]) != MEM
14685 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14686 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14687 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14688 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14689 return "wldrw%?\t%0, %1";
14691 /* Fix up an out-of-range load of a GR register. */
14692 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14693 wcgr
= operands
[0];
14695 output_asm_insn ("ldr%?\t%0, %1", operands
);
14697 operands
[0] = wcgr
;
14699 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14700 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14706 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14707 int incoming ATTRIBUTE_UNUSED
)
14710 /* FIXME: The ARM backend has special code to handle structure
14711 returns, and will reserve its own hidden first argument. So
14712 if this macro is enabled a *second* hidden argument will be
14713 reserved, which will break binary compatibility with old
14714 toolchains and also thunk handling. One day this should be
14718 /* Register in which address to store a structure value
14719 is passed to a function. */
14720 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14724 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14726 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14727 named arg and all anonymous args onto the stack.
14728 XXX I know the prologue shouldn't be pushing registers, but it is faster
14732 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14733 enum machine_mode mode ATTRIBUTE_UNUSED
,
14734 tree type ATTRIBUTE_UNUSED
,
14736 int second_time ATTRIBUTE_UNUSED
)
14738 cfun
->machine
->uses_anonymous_args
= 1;
14739 if (cum
->nregs
< NUM_ARG_REGS
)
14740 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14743 /* Return nonzero if the CONSUMER instruction (a store) does not need
14744 PRODUCER's value to calculate the address. */
14747 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14749 rtx value
= PATTERN (producer
);
14750 rtx addr
= PATTERN (consumer
);
14752 if (GET_CODE (value
) == COND_EXEC
)
14753 value
= COND_EXEC_CODE (value
);
14754 if (GET_CODE (value
) == PARALLEL
)
14755 value
= XVECEXP (value
, 0, 0);
14756 value
= XEXP (value
, 0);
14757 if (GET_CODE (addr
) == COND_EXEC
)
14758 addr
= COND_EXEC_CODE (addr
);
14759 if (GET_CODE (addr
) == PARALLEL
)
14760 addr
= XVECEXP (addr
, 0, 0);
14761 addr
= XEXP (addr
, 0);
14763 return !reg_overlap_mentioned_p (value
, addr
);
14766 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14767 have an early register shift value or amount dependency on the
14768 result of PRODUCER. */
14771 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14773 rtx value
= PATTERN (producer
);
14774 rtx op
= PATTERN (consumer
);
14777 if (GET_CODE (value
) == COND_EXEC
)
14778 value
= COND_EXEC_CODE (value
);
14779 if (GET_CODE (value
) == PARALLEL
)
14780 value
= XVECEXP (value
, 0, 0);
14781 value
= XEXP (value
, 0);
14782 if (GET_CODE (op
) == COND_EXEC
)
14783 op
= COND_EXEC_CODE (op
);
14784 if (GET_CODE (op
) == PARALLEL
)
14785 op
= XVECEXP (op
, 0, 0);
14788 early_op
= XEXP (op
, 0);
14789 /* This is either an actual independent shift, or a shift applied to
14790 the first operand of another operation. We want the whole shift
14792 if (GET_CODE (early_op
) == REG
)
14795 return !reg_overlap_mentioned_p (value
, early_op
);
14798 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14799 have an early register shift value dependency on the result of
14803 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14805 rtx value
= PATTERN (producer
);
14806 rtx op
= PATTERN (consumer
);
14809 if (GET_CODE (value
) == COND_EXEC
)
14810 value
= COND_EXEC_CODE (value
);
14811 if (GET_CODE (value
) == PARALLEL
)
14812 value
= XVECEXP (value
, 0, 0);
14813 value
= XEXP (value
, 0);
14814 if (GET_CODE (op
) == COND_EXEC
)
14815 op
= COND_EXEC_CODE (op
);
14816 if (GET_CODE (op
) == PARALLEL
)
14817 op
= XVECEXP (op
, 0, 0);
14820 early_op
= XEXP (op
, 0);
14822 /* This is either an actual independent shift, or a shift applied to
14823 the first operand of another operation. We want the value being
14824 shifted, in either case. */
14825 if (GET_CODE (early_op
) != REG
)
14826 early_op
= XEXP (early_op
, 0);
14828 return !reg_overlap_mentioned_p (value
, early_op
);
14831 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14832 have an early register mult dependency on the result of
14836 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14838 rtx value
= PATTERN (producer
);
14839 rtx op
= PATTERN (consumer
);
14841 if (GET_CODE (value
) == COND_EXEC
)
14842 value
= COND_EXEC_CODE (value
);
14843 if (GET_CODE (value
) == PARALLEL
)
14844 value
= XVECEXP (value
, 0, 0);
14845 value
= XEXP (value
, 0);
14846 if (GET_CODE (op
) == COND_EXEC
)
14847 op
= COND_EXEC_CODE (op
);
14848 if (GET_CODE (op
) == PARALLEL
)
14849 op
= XVECEXP (op
, 0, 0);
14852 return (GET_CODE (op
) == PLUS
14853 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14857 /* We can't rely on the caller doing the proper promotion when
14858 using APCS or ATPCS. */
14861 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14863 return !TARGET_AAPCS_BASED
;
14867 /* AAPCS based ABIs use short enums by default. */
14870 arm_default_short_enums (void)
14872 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
14876 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14879 arm_align_anon_bitfield (void)
14881 return TARGET_AAPCS_BASED
;
14885 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14888 arm_cxx_guard_type (void)
14890 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14894 /* The EABI says test the least significant bit of a guard variable. */
14897 arm_cxx_guard_mask_bit (void)
14899 return TARGET_AAPCS_BASED
;
14903 /* The EABI specifies that all array cookies are 8 bytes long. */
14906 arm_get_cookie_size (tree type
)
14910 if (!TARGET_AAPCS_BASED
)
14911 return default_cxx_get_cookie_size (type
);
14913 size
= build_int_cst (sizetype
, 8);
14918 /* The EABI says that array cookies should also contain the element size. */
14921 arm_cookie_has_size (void)
14923 return TARGET_AAPCS_BASED
;
14927 /* The EABI says constructors and destructors should return a pointer to
14928 the object constructed/destroyed. */
14931 arm_cxx_cdtor_returns_this (void)
14933 return TARGET_AAPCS_BASED
;
14936 /* The EABI says that an inline function may never be the key
14940 arm_cxx_key_method_may_be_inline (void)
14942 return !TARGET_AAPCS_BASED
;
14946 arm_cxx_determine_class_data_visibility (tree decl
)
14948 if (!TARGET_AAPCS_BASED
)
14951 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14952 is exported. However, on systems without dynamic vague linkage,
14953 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14954 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
14955 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
14957 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
14958 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
14962 arm_cxx_class_data_always_comdat (void)
14964 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14965 vague linkage if the class has no key function. */
14966 return !TARGET_AAPCS_BASED
;
14970 /* The EABI says __aeabi_atexit should be used to register static
14974 arm_cxx_use_aeabi_atexit (void)
14976 return TARGET_AAPCS_BASED
;
14981 arm_set_return_address (rtx source
, rtx scratch
)
14983 arm_stack_offsets
*offsets
;
14984 HOST_WIDE_INT delta
;
14986 unsigned long saved_regs
;
14988 saved_regs
= arm_compute_save_reg_mask ();
14990 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14991 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14994 if (frame_pointer_needed
)
14995 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14998 /* LR will be the first saved register. */
14999 offsets
= arm_get_frame_offsets ();
15000 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15005 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15006 GEN_INT (delta
& ~4095)));
15011 addr
= stack_pointer_rtx
;
15013 addr
= plus_constant (addr
, delta
);
15015 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15021 thumb_set_return_address (rtx source
, rtx scratch
)
15023 arm_stack_offsets
*offsets
;
15024 HOST_WIDE_INT delta
;
15027 unsigned long mask
;
15029 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15031 mask
= thumb_compute_save_reg_mask ();
15032 if (mask
& (1 << LR_REGNUM
))
15034 offsets
= arm_get_frame_offsets ();
15036 /* Find the saved regs. */
15037 if (frame_pointer_needed
)
15039 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15040 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15044 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15047 /* Allow for the stack frame. */
15048 if (TARGET_BACKTRACE
)
15050 /* The link register is always the first saved register. */
15053 /* Construct the address. */
15054 addr
= gen_rtx_REG (SImode
, reg
);
15055 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15058 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15059 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15063 addr
= plus_constant (addr
, delta
);
15065 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15068 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15071 /* Implements target hook vector_mode_supported_p. */
15073 arm_vector_mode_supported_p (enum machine_mode mode
)
15075 if ((mode
== V2SImode
)
15076 || (mode
== V4HImode
)
15077 || (mode
== V8QImode
))
15083 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15084 ARM insns and therefore guarantee that the shift count is modulo 256.
15085 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15086 guarantee no particular behavior for out-of-range counts. */
15088 static unsigned HOST_WIDE_INT
15089 arm_shift_truncation_mask (enum machine_mode mode
)
15091 return mode
== SImode
? 255 : 0;
15095 /* Map internal gcc register numbers to DWARF2 register numbers. */
15098 arm_dbx_register_number (unsigned int regno
)
15103 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15104 compatibility. The EABI defines them as registers 96-103. */
15105 if (IS_FPA_REGNUM (regno
))
15106 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15108 if (IS_VFP_REGNUM (regno
))
15109 return 64 + regno
- FIRST_VFP_REGNUM
;
15111 if (IS_IWMMXT_GR_REGNUM (regno
))
15112 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15114 if (IS_IWMMXT_REGNUM (regno
))
15115 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15117 gcc_unreachable ();
15121 #ifdef TARGET_UNWIND_INFO
15122 /* Emit unwind directives for a store-multiple instruction. This should
15123 only ever be generated by the function prologue code, so we expect it
15124 to have a particular form. */
15127 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15130 HOST_WIDE_INT offset
;
15131 HOST_WIDE_INT nregs
;
15137 /* First insn will adjust the stack pointer. */
15138 e
= XVECEXP (p
, 0, 0);
15139 if (GET_CODE (e
) != SET
15140 || GET_CODE (XEXP (e
, 0)) != REG
15141 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15142 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15145 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15146 nregs
= XVECLEN (p
, 0) - 1;
15148 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15151 /* The function prologue may also push pc, but not annotate it as it is
15152 never restored. We turn this into a stack pointer adjustment. */
15153 if (nregs
* 4 == offset
- 4)
15155 fprintf (asm_out_file
, "\t.pad #4\n");
15160 else if (IS_VFP_REGNUM (reg
))
15162 /* FPA register saves use an additional word. */
15166 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15168 /* FPA registers are done differently. */
15169 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15173 /* Unknown register type. */
15176 /* If the stack increment doesn't match the size of the saved registers,
15177 something has gone horribly wrong. */
15178 if (offset
!= nregs
* reg_size
)
15181 fprintf (asm_out_file
, "\t.save {");
15185 /* The remaining insns will describe the stores. */
15186 for (i
= 1; i
<= nregs
; i
++)
15188 /* Expect (set (mem <addr>) (reg)).
15189 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15190 e
= XVECEXP (p
, 0, i
);
15191 if (GET_CODE (e
) != SET
15192 || GET_CODE (XEXP (e
, 0)) != MEM
15193 || GET_CODE (XEXP (e
, 1)) != REG
)
15196 reg
= REGNO (XEXP (e
, 1));
15201 fprintf (asm_out_file
, ", ");
15202 /* We can't use %r for vfp because we need to use the
15203 double precision register names. */
15204 if (IS_VFP_REGNUM (reg
))
15205 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15207 asm_fprintf (asm_out_file
, "%r", reg
);
15209 #ifdef ENABLE_CHECKING
15210 /* Check that the addresses are consecutive. */
15211 e
= XEXP (XEXP (e
, 0), 0);
15212 if (GET_CODE (e
) == PLUS
)
15214 offset
+= reg_size
;
15215 if (GET_CODE (XEXP (e
, 0)) != REG
15216 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15217 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15218 || offset
!= INTVAL (XEXP (e
, 1)))
15222 || GET_CODE (e
) != REG
15223 || REGNO (e
) != SP_REGNUM
)
15227 fprintf (asm_out_file
, "}\n");
15230 /* Emit unwind directives for a SET. */
15233 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15240 switch (GET_CODE (e0
))
15243 /* Pushing a single register. */
15244 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15245 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15246 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15249 asm_fprintf (asm_out_file
, "\t.save ");
15250 if (IS_VFP_REGNUM (REGNO (e1
)))
15251 asm_fprintf(asm_out_file
, "{d%d}\n",
15252 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15254 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15258 if (REGNO (e0
) == SP_REGNUM
)
15260 /* A stack increment. */
15261 if (GET_CODE (e1
) != PLUS
15262 || GET_CODE (XEXP (e1
, 0)) != REG
15263 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15264 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15267 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15268 -INTVAL (XEXP (e1
, 1)));
15270 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15272 HOST_WIDE_INT offset
;
15275 if (GET_CODE (e1
) == PLUS
)
15277 if (GET_CODE (XEXP (e1
, 0)) != REG
15278 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15280 reg
= REGNO (XEXP (e1
, 0));
15281 offset
= INTVAL (XEXP (e1
, 1));
15282 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15283 HARD_FRAME_POINTER_REGNUM
, reg
,
15284 INTVAL (XEXP (e1
, 1)));
15286 else if (GET_CODE (e1
) == REG
)
15289 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15290 HARD_FRAME_POINTER_REGNUM
, reg
);
15295 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15297 /* Move from sp to reg. */
15298 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15310 /* Emit unwind directives for the given insn. */
15313 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15317 if (!ARM_EABI_UNWIND_TABLES
)
15320 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15323 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15325 pat
= XEXP (pat
, 0);
15327 pat
= PATTERN (insn
);
15329 switch (GET_CODE (pat
))
15332 arm_unwind_emit_set (asm_out_file
, pat
);
15336 /* Store multiple. */
15337 arm_unwind_emit_stm (asm_out_file
, pat
);
15346 /* Output a reference from a function exception table to the type_info
15347 object X. The EABI specifies that the symbol should be relocated by
15348 an R_ARM_TARGET2 relocation. */
15351 arm_output_ttype (rtx x
)
15353 fputs ("\t.word\t", asm_out_file
);
15354 output_addr_const (asm_out_file
, x
);
15355 /* Use special relocations for symbol references. */
15356 if (GET_CODE (x
) != CONST_INT
)
15357 fputs ("(TARGET2)", asm_out_file
);
15358 fputc ('\n', asm_out_file
);
15362 #endif /* TARGET_UNWIND_INFO */
15365 /* Output unwind directives for the start/end of a function. */
15368 arm_output_fn_unwind (FILE * f
, bool prologue
)
15370 if (!ARM_EABI_UNWIND_TABLES
)
15374 fputs ("\t.fnstart\n", f
);
15376 fputs ("\t.fnend\n", f
);
15380 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15382 enum tls_reloc reloc
;
15385 val
= XVECEXP (x
, 0, 0);
15386 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15388 output_addr_const (fp
, val
);
15393 fputs ("(tlsgd)", fp
);
15396 fputs ("(tlsldm)", fp
);
15399 fputs ("(tlsldo)", fp
);
15402 fputs ("(gottpoff)", fp
);
15405 fputs ("(tpoff)", fp
);
15408 gcc_unreachable ();
15416 fputs (" + (. - ", fp
);
15417 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15419 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15430 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15432 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15433 return arm_emit_tls_decoration (fp
, x
);
15434 else if (GET_CODE (x
) == CONST_VECTOR
)
15435 return arm_emit_vector_const (fp
, x
);
15440 #include "gt-arm.h"