gcc/ChangeLog

   1 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
   2
   3         PR c/102998
   4         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
   5         (Warning Options): Correct/edit discussion of -Warray-parameter
   6         to make the first example less confusing, and fill in missing info.
   7
   8 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
   9
  10         PR tree-optimization/113462
  11         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
  12         Handle rhs1 INTEGER_CST like SSA_NAME.
  13
  14 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
  15
  16         PR tree-optimization/113491
  17         * tree-switch-conversion.cc (switch_conversion::build_constructors):
  18         If elt.index has precision higher than sizetype, fold_convert it to
  19         sizetype.
  20         (switch_conversion::array_value_type): Return type if type is
  21         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
  22         (switch_conversion::build_arrays): Use unsigned_type_for rather than
  23         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
  24         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
  25         higher than sizetype, use sizetype as tidx type and fold_convert the
  26         subtraction to sizetype.
  27
  28 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
  29
  30         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
  31         (riscv_vector_mode_supported_any_target_p): Ditto.
  32
  33 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
  34
  35         PR target/110934
  36         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
  37         (TARGET_ZERO_CALL_USED_REGS): Define.
  38
  39 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
  40
  41         PR target/108640
  42         * config/m68k/m68k.cc (output_andsi3): Use QImode for
  43         address adjusted for 1-byte RMW access.
  44         (output_iorsi3): Likewise.
  45         (output_xorsi3): Likewise.
  46
  47 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
  48
  49         * doc/invoke.texi (RISC-V Options): Add list of supported
  50         extensions.
  51
  52 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
  53
  54         PR target/113495
  55         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
  56         (RVV_VUNDEF): Ditto.
  57         * config/riscv/riscv-vsetvl.cc: Add timevar.
  58
  59 2024-01-19  Richard Biener  <rguenther@suse.de>
  60
  61         PR debug/113488
  62         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
  63         an early DIE but there should be, do not pretend there is.
  64
  65 2024-01-19  Richard Biener  <rguenther@suse.de>
  66
  67         PR tree-optimization/113494
  68         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
  69         Handle endless loop on exit.  Handle re-allocated PHI.
  70
  71 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
  72
  73         PR tree-optimization/113464
  74         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
  75         optimize loads into GIMPLE_ASM stmts.
  76
  77 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
  78
  79         PR tree-optimization/113463
  80         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
  81         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
  82         lhs.
  83
  84 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
  85
  86         PR tree-optimization/113459
  87         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
  88         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
  89         of SCALAR_INT_TYPE_MODE if type has BLKmode.
  90         (vn_reference_lookup_3): Likewise.  Formatting fix.
  91
  92 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
  93             Richard Biener  <rguenther@suse.de>
  94
  95         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
  96         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
  97         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
  98         but adjust_address also for BLKmode mode and MEM op0.
  99
 100 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
 101
 102         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
 103         extensions.
 104
 105 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 106
 107         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
 108
 109 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 110
 111         * common/config/riscv/riscv-common.cc
 112         (riscv_subset_list::parse_std_ext): Remove.
 113         (riscv_subset_list::parse_multiletter_ext): Remove.
 114         * config/riscv/riscv-subset.h
 115         (riscv_subset_list::parse_std_ext): Remove.
 116         (riscv_subset_list::parse_multiletter_ext): Remove.
 117
 118 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 119
 120         * common/config/riscv/riscv-common.cc
 121         (riscv_subset_list::parse_single_std_ext): New parameter.
 122         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
 123         (riscv_subset_list::parse_single_ext): Ditto.
 124         (riscv_subset_list::parse): Relax the order for the input of ISA
 125         string.
 126         * config/riscv/riscv-subset.h
 127         (riscv_subset_list::parse_single_std_ext): New parameter.
 128         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
 129         (riscv_subset_list::parse_single_ext): Ditto.
 130
 131 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 132
 133         * common/config/riscv/riscv-common.cc
 134         (riscv_subset_list::parse_base_ext): New.
 135         (riscv_subset_list::parse): Extract part of logic into
 136         riscv_subset_list::parse_base_ext.
 137         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
 138         New.
 139
 140 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 141
 142         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
 143         sorry message.
 144
 145 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
 146
 147         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
 148         UNSPEC_CLMUL_VC.
 149
 150 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
 151
 152         PR c/110029
 153         * doc/extend.texi (Common Variable Attributes): Explain what
 154         happens when multiple variables with cleanups are in the same scope.
 155
 156 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 157
 158         PR ipa/108470
 159         * doc/extend.texi (Common Function Attributes): Document that
 160         noinline also disables some interprocedural optimizations and
 161         improve flow to the part about using inline asm instead to
 162         disable calls from being optimized away completely.  Remove the
 163         sentence that says noipa is mainly for internal compiler testing.
 164
 165 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
 166
 167         PR tree-optimization/69807
 168         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
 169
 170 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
 171
 172         PR target/108521
 173         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
 174         from x86 Windows Options.
 175
 176 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 177
 178         PR c/107942
 179         * doc/extend.texi (C Extensions): Add new section to menu.
 180         (Function Attributes):  Move dangling index entries to....
 181         (Const and Volatile Functions): New section.
 182
 183 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
 184
 185         PR middle-end/112684
 186         * toplev.cc (toplev::main): Don't ICE in
 187         -fdiagnostics-generate-patch when exiting after options,
 188         since no edit context will have been created.
 189
 190 2024-01-18  Richard Biener  <rguenther@suse.de>
 191
 192         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
 193         operands vector.
 194
 195 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 196
 197         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
 198         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
 199
 200 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 201             Jin Ma  <jinma@linux.alibaba.com>
 202             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 203             Christoph Müllner  <christoph.muellner@vrull.eu>
 204
 205         * config/riscv/thead.cc
 206         (th_asm_output_opcode): Rewrite some instructions.
 207
 208 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 209             Jin Ma  <jinma@linux.alibaba.com>
 210             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 211             Christoph Müllner  <christoph.muellner@vrull.eu>
 212
 213         * config/riscv/riscv.md (none,thv,rvv): New attribute.
 214         (no,yes): Add an attribute to disable alternative
 215         for xtheadvector or RVV1.0.
 216         * config/riscv/vector.md:
 217         Disable alternatives that destination register overlaps
 218         source register group for xtheadvector.
 219
 220 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 221             Jin Ma  <jinma@linux.alibaba.com>
 222             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 223             Christoph Müllner  <christoph.muellner@vrull.eu>
 224
 225         * config/riscv/riscv-vector-builtins-bases.cc
 226         (class th_loadstore_width): Define new builtin bases.
 227         (class th_extract): Define new builtin bases.
 228         (BASE): Define new builtin bases.
 229         * config/riscv/riscv-vector-builtins-bases.h:
 230         Define new builtin class.
 231         * config/riscv/riscv-vector-builtins-shapes.cc
 232         (struct th_loadstore_width_def): Define new builtin shapes.
 233         (struct th_indexed_loadstore_width_def):
 234         Define new builtin shapes.
 235         (struct th_extract_def): Define new builtin shapes.
 236         (SHAPE): Define new builtin shapes.
 237         * config/riscv/riscv-vector-builtins-shapes.h:
 238         Define new builtin shapes.
 239         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
 240         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
 241         * config/riscv/riscv-vector-builtins.h
 242         (enum required_ext): Add new XTheadVector member.
 243         (struct function_group_info): Likewise.
 244         * config/riscv/t-riscv:
 245         Add thead-vector-builtins-functions.def
 246         * config/riscv/thead-vector.md
 247         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
 248         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
 249         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
 250         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
 251         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
 252         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
 253         (@pred_th_extract<mode>): Likewise.
 254         (*pred_th_extract<mode>): Likewise.
 255         * config/riscv/thead-vector-builtins-functions.def: New file.
 256
 257 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 258             Jin Ma  <jinma@linux.alibaba.com>
 259             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 260             Christoph Müllner  <christoph.muellner@vrull.eu>
 261
 262         * config.gcc:  Add files for XTheadVector intrinsics.
 263         * config/riscv/autovec.md: Guard XTheadVector.
 264         * config/riscv/predicates.md: Disable immediate vl
 265         for XTheadVector.
 266         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
 267         Add pragma for XTheadVector.
 268         * config/riscv/riscv-string.cc (riscv_expand_block_move):
 269         Guard XTheadVector.
 270         * config/riscv/riscv-v.cc (vls_mode_valid_p):
 271         Avoid autovec.
 272         * config/riscv/riscv-vector-builtins-bases.cc:
 273         Do not normalize vsetvl instructions for XTheadVector.
 274         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
 275         New check type function.
 276         (build_one): Adjust for XTheadVector.
 277         * config/riscv/riscv-vector-switch.def (ENTRY):
 278         Disable fractional mode for the XTheadVector extension.
 279         (TUPLE_ENTRY): Likewise.
 280         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
 281         Guard XTheadVector.
 282         (riscv_preferred_simd_mode): Likewsie.
 283         (riscv_autovectorize_vector_modes): Likewise.
 284         (riscv_vector_mode_supported_any_target_p): Likewise.
 285         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
 286         * config/riscv/thead.cc (th_asm_output_opcode):
 287         Rewrite vsetvl instructions.
 288         * config/riscv/vector.md:
 289         Include thead-vector.md and change fractional LMUL
 290         into 1 for vbool.
 291         * config/riscv/riscv_th_vector.h: New file.
 292         * config/riscv/thead-vector.md: New file.
 293
 294 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 295             Jin Ma  <jinma@linux.alibaba.com>
 296             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 297             Christoph Müllner  <christoph.muellner@vrull.eu>
 298
 299         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
 300         Add new function to add assembler insn code prefix/suffix.
 301         (th_asm_output_opcode):
 302         Add Thead function to add assembler insn code prefix/suffix.
 303         * config/riscv/riscv.cc (riscv_asm_output_opcode):
 304         Implement function to add assembler insn code prefix/suffix.
 305         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
 306         Add new function to add assembler insn code prefix/suffix.
 307         * config/riscv/thead.cc (th_asm_output_opcode):
 308         Implement Thead function to add assembler insn code
 309         prefix/suffix.
 310
 311 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 312             Jin Ma  <jinma@linux.alibaba.com>
 313             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 314             Christoph Müllner  <christoph.muellner@vrull.eu>
 315
 316         * common/config/riscv/riscv-common.cc
 317         (riscv_subset_list::parse): Add new vendor extension.
 318         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
 319         Add test marco.
 320         * config/riscv/riscv.opt:  Add new mask.
 321
 322 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 323
 324         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
 325         to be conditional on macosx-version-min.
 326
 327 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 328
 329         * config/darwin.cc (darwin_objc1_section): Use the correct
 330         meta-data version for constant strings.
 331         (machopic_select_section): Assert if we fail to handle CFString
 332         sections as Obejctive-C meta-data or drectly.
 333
 334 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 335
 336         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
 337         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
 338         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
 339         versions when the object format is Mach-O.
 340
 341 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 342
 343         PR target/105522
 344         * config/darwin.cc (machopic_select_section): Handle C and C++
 345         CFStrings.
 346         (darwin_rename_builtins): Move this out of the CFString code.
 347         (darwin_libc_has_function): Likewise.
 348         (darwin_build_constant_cfstring): Create an anonymous var to
 349         hold each CFString.
 350         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
 351         CFstrings.
 352
 353 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
 354
 355         PR bootstrap/113445
 356         * haifa-sched.cc (dep_list_size): Make global.
 357         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
 358         * sched-int.h (dep_list_size): Declare.
 359
 360 2024-01-18  Martin Jambor  <mjambor@suse.cz>
 361
 362         PR tree-optimization/110422
 363         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
 364         gotos.
 365
 366 2024-01-18  Richard Biener  <rguenther@suse.de>
 367
 368         PR tree-optimization/113475
 369         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
 370         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
 371         (phi_analyzer::~phi_analyzer): Deallocate and free collected
 372         phi_grous.
 373         (phi_analyzer::process_phi): Record allocated phi_groups.
 374
 375 2024-01-18  Richard Biener  <rguenther@suse.de>
 376
 377         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
 378         storage for gvec_oprnds elements.
 379
 380 2024-01-18  Richard Biener  <rguenther@suse.de>
 381
 382         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
 383         prefer all later exits we can handle.
 384         (vect_analyze_loop_form): Free the allocated loop body.
 385         Adjust comments.
 386
 387 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 388
 389         * config/avr/avr-log.cc: Tabify.
 390
 391 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 392
 393         * config/riscv/autovec.md: Support vi variant.
 394
 395 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 396
 397         * config/avr/avr-devices.cc: Tabify.
 398
 399 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 400
 401         * config/avr/avr-c.cc: Tabify.
 402
 403 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 404
 405         * config/avr/driver-avr.cc: Tabify.
 406
 407 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 408
 409         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
 410
 411 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 412
 413         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
 414
 415 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 416
 417         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
 418         minline-strcmp, minline-strncmp, minline-strlen,
 419         -param=riscv-vector-abi): Remove Bool keywords.
 420
 421 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 422
 423         PR target/113122
 424         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
 425         support.  Add missing space after , in emitted assembly in some
 426         cases.  Formatting fixes.
 427
 428 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
 429
 430         * config/loongarch/loongarch.md (movsi_internal): Remove
 431         constraint z.
 432
 433 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 434
 435         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
 436         in the diagnostic, and capitalize the device name.
 437         (print_mcu): Generate specs such that:
 438         <*check_rodata_in_ram>: New.
 439         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
 440         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
 441         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
 442
 443 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 444
 445         PR other/113399
 446         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
 447         Common and Optimization.
 448
 449 2024-01-18  Richard Biener  <rguenther@suse.de>
 450
 451         PR tree-optimization/113431
 452         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
 453         When there is an invariant load we might not preserve
 454         scalar order.
 455
 456 2024-01-18  Richard Biener  <rguenther@suse.de>
 457
 458         PR tree-optimization/113374
 459         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
 460         * tree-vect-loop.cc (move_early_exit_stmts): Update
 461         virtual LC PHIs.
 462         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 463         Refactor.  Preserve virtual LC PHIs on all exits.
 464
 465 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
 466
 467         * config/loongarch/loongarch.cc (loongarch_split_symbol):
 468         Assign the '/u' attribute to the mem.
 469
 470 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 471
 472         PR middle-end/110847
 473         * doc/invoke.texi (Option Summary): Document negative forms of
 474         -Wtsan and -Wxor-used-as-pow.
 475         (Warning Options): Likewise.
 476
 477 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 478
 479         PR target/113429
 480         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
 481
 482 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 483
 484         * doc/extend.texi (Common Function Attributes): Re-alphabetize
 485         the table.
 486         (Common Variable Attributes): Likewise.
 487         (Common Type Attributes): Likewise.
 488
 489 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 490
 491         PR middle-end/111659
 492         * doc/extend.texi (Common Variable Attributes): Fix long lines
 493         in documentation of strict_flex_array + other minor copy-editing.
 494         Add a cross-reference to -Wstrict-flex-arrays.
 495         * doc/invoke.texi (Option Summary): Fix whitespace in tables
 496         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
 497         (C Dialect Options): Combine the docs for the two
 498         -fstrict-flex-arrays forms into a single entry.  Note this option
 499         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
 500         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
 501         Minor copy-editing.  Add cross references to the strict_flex_array
 502         attribute and -fstrict-flex-arrays option.  Add note that this
 503         option depends on -ftree-vrp.
 504
 505 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
 506
 507         PR target/113221
 508         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
 509         only allow REG operands instead of allowing all.
 510
 511 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
 512
 513         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
 514         Remove redundant checks in else condition for readablity.
 515         (earliest_fuse_vsetvl_info) Print iteration count in debug
 516         prints.
 517         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
 518         dump details in certain cases.
 519
 520 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
 521
 522         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
 523         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
 524         * config/riscv/riscv-vsetvl.cc
 525         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
 526         (pass_vsetvl::execute): Use vsetvl_strategy.
 527
 528 2024-01-17  Jan Hubicka  <jh@suse.cz>
 529
 530         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
 531         accidental hack reseting offset.
 532
 533 2024-01-17  Jan Hubicka  <jh@suse.cz>
 534
 535         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
 536         handling of X86_TUNE_AVOID_512FMA_CHAINS.
 537
 538 2024-01-17  Jan Hubicka  <jh@suse.cz>
 539             Jakub Jelinek  <jakub@redhat.com>
 540
 541         PR tree-optimization/110852
 542         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
 543         binary operations
 544         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
 545         PRED_COMBINED_VALUE_PREDICTIONS_PHI
 546         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
 547         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
 548
 549 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 550
 551         PR tree-optimization/113421
 552         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
 553         comment.
 554         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
 555         formatting.  Start at vop rather than cvop even if stmt is a store
 556         and needs_operand_addr.
 557
 558 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 559
 560         PR middle-end/113410
 561         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
 562         If access_nelts is integral with larger precision than sizetype,
 563         fold_convert it to sizetype.
 564
 565 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 566
 567         PR tree-optimization/113408
 568         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
 569         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
 570         to handle_cast.
 571
 572 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 573
 574         PR middle-end/113406
 575         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
 576         regardless of whether is_gimple_reg_type (restype) or not.
 577
 578 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 579
 580         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
 581         funcions -> functions, and use were instead of was.
 582         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
 583         and guaranteee -> guarantee.
 584         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
 585
 586 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 587
 588         PR middle-end/113409
 589         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
 590         INTEGER_TYPE.
 591         (omp_extract_for_data): Use build_bitint_type rather than
 592         build_nonstandard_integer_type if either iter_type or loop->v type
 593         is BITINT_TYPE.
 594         * omp-expand.cc (expand_omp_for_generic,
 595         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
 596         BITINT_TYPE like INTEGER_TYPE.
 597
 598 2024-01-17  Richard Biener  <rguenther@suse.de>
 599
 600         PR tree-optimization/113371
 601         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
 602         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
 603         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
 604         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
 605
 606 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
 607
 608         PR rtl-optimization/96388
 609         PR rtl-optimization/111554
 610         * sched-deps.cc (find_inc): Avoid exponential behavior.
 611
 612 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 613
 614         PR c/111693
 615         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
 616         from C++ Language Options to Warning Options.  Add entry for
 617         -Wuse-after-free.
 618         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
 619         from here....
 620         (Warning Options): ...to here.  Minor copy-editing to fix typo
 621         and grammar.
 622
 623 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
 624
 625         * config/mips/mips.cc (mips_compute_frame_info): If another
 626         register is used as global_pointer, mark $GP live false.
 627
 628 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 629
 630         PR target/112973
 631         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
 632         give the section a light copy-editing pass.
 633
 634 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 635
 636         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
 637         * config/aarch64/aarch64-tune.md: Regenerated.
 638         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
 639
 640 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 641
 642         PR target/112573
 643         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
 644         badly formed CONST expressions.
 645
 646 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
 647
 648         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
 649
 650 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
 651
 652         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
 653         * config/sparc/sync.md (membar_storeload): Turn into named insn
 654         and add GR712RC errata workaround.
 655         (membar_v8): Add GR712RC errata workaround.
 656
 657 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
 658
 659         * config/sparc/sync.md (*membar_storeload_leon3): Remove
 660         (*membar_storeload): Enable for LEON
 661
 662 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
 663
 664         PR tree-optimization/113372
 665         PR middle-end/90348
 666         PR middle-end/110115
 667         PR middle-end/111422
 668         * cfgexpand.cc (add_scope_conflicts_2): New function.
 669         (add_scope_conflicts_1): Use it.
 670
 671 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
 672
 673         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
 674         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
 675         * doc/avr-mmcu.texi: Regenerate.
 676
 677 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
 678
 679         PR tree-optimization/113091
 680         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
 681         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
 682         scalar use with new function.
 683         (vect_bb_slp_mark_live_stmts): New function as entry to existing
 684         overriden functions with same name.
 685         (vect_slp_analyze_operations): Call new entry function to mark
 686         live statements.
 687
 688 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 689
 690         PR target/113404
 691         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
 692         for RVV in big-endian mode.
 693
 694 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
 695
 696         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
 697         (riscv_pass_in_vector_p): Delete.
 698         (riscv_init_cumulative_args): Delete the checking.
 699         (riscv_get_arg_info): Delete the checking.
 700         (riscv_function_value): Delete the checking.
 701         * config/riscv/riscv.h: Delete the member for checking.
 702
 703 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
 704
 705         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
 706
 707 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
 708
 709         * config.gcc: Include riscv_bitmanip.h.
 710         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
 711         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
 712         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
 713         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
 714         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
 715         * config/riscv/riscv-ftypes.def (2): New ftypes.
 716         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
 717         (RISCV_BUILTIN_NO_PREFIX): Likewise.
 718         * config/riscv/riscv_bitmanip.h: New file.
 719
 720 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
 721
 722         * config.gcc: Include riscv_crypto.h.
 723         * config/riscv/riscv_crypto.h: New file.
 724
 725 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
 726
 727         PR middle-end/113354
 728         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
 729         in the insn if the corresponding operand does not require hard
 730         register anymore.
 731
 732 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
 733
 734         PR target/107201
 735         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
 736         * config/avr/driver-avr.cc (avr_no_devlib): New function.
 737         (avr_devicespecs_file): Use it to remove -nodevicelib from the
 738         options for cores only.
 739         * config/avr/avr-arch.h (avr_get_parch): New prototype.
 740         * config/avr/avr-devices.cc (avr_get_parch): New function.
 741
 742 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 743
 744         PR target/113247
 745         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
 746         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
 747         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
 748
 749 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 750
 751         PR target/113281
 752         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
 753         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
 754         * config/riscv/riscv-vector-costs.h: New function.
 755
 756 2024-01-15  Richard Biener  <rguenther@suse.de>
 757
 758         PR tree-optimization/113385
 759         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 760         First redirect, then split the exit edge.
 761
 762 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 763
 764         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
 765         Remove m_num_vector_iterations.
 766         * config/riscv/riscv-vector-costs.h: Ditto.
 767
 768 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
 769
 770         PR target/113156
 771         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
 772         (-mbranch-cost): Set "Optimization" flag.
 773
 774 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
 775
 776         PR tree-optimization/113370
 777         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
 778         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
 779         set it to just prec % limb_prec.
 780
 781 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 782
 783         PR target/113393
 784         * config/riscv/vector.md: Fix ternary attributes.
 785
 786 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
 787
 788         PR target/112944
 789         * configure.ac [target=avr]: Check availability of emulations
 790         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
 791         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
 792         * configure: Regenerate.
 793         * config.in: Regenerate.
 794         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
 795         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
 796         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
 797         * config/avr/avr-arch.h (enum avr_device_specific_features):
 798         Add AVR_ISA_FLMAP.
 799         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
 800         AVR_ISA_FLMAP.
 801         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
 802         (avr_set_core_architecture): Set avr_arch_index.
 803         (have_avrxmega2_flmap, have_avrxmega4_flmap)
 804         (have_avrxmega3_rodata_in_flash): Set new static const bool according
 805         to configure results.
 806         (avr_rodata_in_flash_p): New function using them.
 807         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
 808         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
 809         (avr_asm_named_section): Track avr_has_rodata_p.
 810         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
 811         and not avr_rodata_in_flash_p ().
 812         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
 813         (LINK_SPEC): Add %(link_rodata_in_ram).
 814         (LINK_ARCH_SPEC): Remove.
 815         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
 816         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
 817         const bool according to configure results.
 818         (diagnose_mrodata_in_ram): New function.
 819         (print_mcu): Generate specs with the following changes:
 820         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
 821         need to extend avr/specs.h each time we add a new bell or whistle.
 822         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
 823         -m[no-]rodata-in-ram.
 824         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
 825         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
 826         <*cpp>: Add %(cpp_rodata_in_ram).
 827         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
 828         requested.
 829         <*self_spec>: Add -mflmap or %<mflmap as needed.
 830
 831 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
 832
 833         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
 834         not the GPR iterator.  Adjust pattern name and mode attribute
 835         accordingly.
 836
 837 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
 838
 839         PR tree-optimization/113361
 840         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
 841         Fix up determination of the type for > limb_prec constants.
 842
 843 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 844
 845         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
 846         Add web-link to the avr-gcc wiki.
 847
 848 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 849
 850         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
 851         documentation for a version without argument, which is not supported.
 852
 853 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 854
 855         * config/arm/arm_neon.h
 856         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
 857         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
 858         (vld1_f16_x4, vld1_f32_x4): New.
 859         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
 860         (vld1_bf16_x4): New.
 861         (vld1q_types_x4): Updated to use vld1q_x4
 862         from arm_neon_builtins.def
 863         * config/arm/arm_neon_builtins.def
 864         (vld1_x4): Updated entries.
 865         (vld1q_x4): New entries, but comes from the old vld1_x4
 866         * config/arm/neon.md
 867         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
 868
 869 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 870
 871         * config/arm/arm_neon.h
 872         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
 873         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
 874         (vld1_f16_x3, vld1_f32_x3): New.
 875         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
 876         (vld1_bf16_x3): New.
 877         (vld1q_types_x3): Updated to use vld1q_x3 from
 878         arm_neon_builtins.def
 879         * config/arm/arm_neon_builtins.def
 880         (vld1_x3): Updated entries.
 881         (vld1q_x3): New entries, but comes from the old vld1_x2
 882         * config/arm/neon.md
 883         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
 884
 885 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 886
 887         * config/arm/arm_neon.h
 888         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
 889         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
 890         (vld1_f16_x2, vld1_f32_x2): New.
 891         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
 892         (vld1_bf16_x2): New.
 893         (vld1q_types_x2): Updated to use vld1q_x2 from
 894         arm_neon_builtins.def
 895         * config/arm/arm_neon_builtins.def
 896         (vld1_x2): Updated entries.
 897         (vld1q_x2): New entries, but comes from the old vld1_x2
 898         * config/arm/neon.md
 899         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 900         neon_vld1_x2<mode>.
 901
 902 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 903
 904         * config/arm/arm_neon.h
 905         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
 906         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
 907         (vst1q_f16_x4, vst1q_f32_x4): New.
 908         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
 909         (vst1q_bf16_x4): New.
 910         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
 911         * config/arm/neon.md
 912         (neon_vst1q_x4<mode>): New.
 913         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
 914         * config/arm/unspecs.md
 915         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
 916
 917 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 918
 919         * config/arm/arm_neon.h
 920         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
 921         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
 922         (vst1q_f16_x3, vst1q_f32_x3): New.
 923         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
 924         (vst1q_bf16_x3): New.
 925         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
 926         * config/arm/neon.md
 927         (neon_vst1q_x3<mode>): New.
 928         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
 929         * config/arm/unspecs.md
 930         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
 931
 932 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 933
 934         * config/arm/arm_neon.h
 935         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
 936         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
 937         (vst1q_f16_x2, vst1q_f32_x2): New.
 938         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
 939         (vst1q_bf16_x2): New.
 940         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
 941         * config/arm/neon.md
 942         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 943         neon_vst1_x2<mode>.
 944         * config/arm/iterators.md
 945         (VMEMX2): New mode iterator.
 946         (VMEMX2_q): New mode attribute.
 947
 948 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 949
 950         * config/arm/arm_neon.h
 951         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
 952         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
 953         (vst1_f16_x4, vst1_f32_x4): New.
 954         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
 955         (vst1_bf16_x4): New.
 956         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
 957         * config/arm/neon.md (vst1_x4<mode>): New.
 958
 959 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 960
 961         * config/arm/arm_neon.h
 962         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
 963         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
 964         (vst1_f16_x3, vst1_f32_x3): New.
 965         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
 966         (vst1_bf16_x3): New.
 967         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
 968         * config/arm/neon.md (vst1_x3<mode>): New.
 969
 970 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 971
 972         * config/arm/arm_neon.h
 973         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
 974         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
 975         (vst1_f16_x2, vst1_f32_x2): New.
 976         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
 977         (vst1_bf16_x2): New.
 978         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
 979         * config/arm/neon.md (vst1_x2<mode>): New.
 980
 981 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 982
 983         * config/arm/arm_neon.h
 984         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
 985         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
 986         (vld1q_f16_x4, vld1q_f32_x4): New.
 987         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
 988         (vld1q_bf16_x4): New.
 989         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
 990         * config/arm/neon.md
 991         (neon_vld1_x4<mode>): New.
 992         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
 993         * config/arm/unspecs.md
 994         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
 995
 996 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 997
 998         * config/arm/arm_neon.h
 999         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
1000         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
1001         (vld1q_f16_x3, vld1q_f32_x3): New.
1002         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
1003         (vld1q_bf16_x3): New.
1004         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
1005         * config/arm/neon.md
1006         (neon_vld1_x3<mode>): New.
1007         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
1008         * config/arm/unspecs.md
1009         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
1010
1011 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
1012
1013         * config/arm/arm_neon.h
1014         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
1015         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
1016         (vld1q_f16_x2, vld1q_f32_x2): New.
1017         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
1018         (vld1q_bf16_x2): New.
1019         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
1020         * config/arm/neon.md (vld1_x2<mode>): New.
1021
1022 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1023
1024         PR tree-optimization/113287
1025         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
1026
1027 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1028
1029         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
1030         * tree-vect-loop.cc (vect_transform_loop): Likewise.
1031
1032 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1033
1034         PR tree-optimization/113178
1035         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
1036         alternate exits.
1037
1038 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1039
1040         PR tree-optimization/113237
1041         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
1042         existing LCSSA variable for exit when all exits are early break.
1043
1044 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1045
1046         PR tree-optimization/113137
1047         PR tree-optimization/113136
1048         PR tree-optimization/113172
1049         PR tree-optimization/113178
1050         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1051         Maintain PHIs on inverted loops.
1052         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
1053         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
1054         latch.
1055         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
1056
1057 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1058
1059         PR tree-optimization/113135
1060         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
1061         dependency analysis.
1062
1063 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
1064
1065         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
1066         diagnostics class member name for abort of error.
1067
1068 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
1069
1070         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
1071         format string to %s argument.
1072
1073 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
1074             Jakub Jelinek  <jakub@redhat.com>
1075
1076         PR middle-end/113182
1077         * varasm.cc (process_pending_assemble_externals,
1078         assemble_external_libcall): Use targetm.strip_name_encoding
1079         before calling get_identifier.
1080
1081 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1082
1083         PR target/113196
1084         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
1085         New member variable.
1086         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
1087         Declare.
1088         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
1089         * config/aarch64/aarch64-simd.md
1090         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
1091         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
1092         zip2 for zero-extends to...
1093         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
1094         instruction.  Fix big-endian handling.
1095         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
1096         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
1097         zip1 for zero-extends to...
1098         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
1099         Fix big-endian handling.
1100         (*aarch64_zip1_uxtl): New pattern.
1101         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
1102         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
1103         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
1104         (aarch64_gen_shareable_zero): Use it.
1105         (aarch64_split_simd_shift_p): New function.
1106
1107 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1108
1109         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
1110         (function_beg_insn): New macro.
1111         * function.cc (expand_function_start): Initialize function_beg_insn.
1112
1113 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1114
1115         PR target/112989
1116         * config/aarch64/aarch64-sve-builtins.h
1117         (function_builder::m_overload_names): Replace with...
1118         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
1119         new global.
1120         (add_overloaded_function): Update accordingly, using get_identifier
1121         to get a GGC-friendly record of the name.
1122
1123 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1124
1125         PR target/112989
1126         * config/aarch64/aarch64-sve-builtins.def: Don't include
1127         aarch64-sve-builtins-sme.def.
1128         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
1129         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
1130         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
1131         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
1132         requires AARCH64_FL_SME2.
1133         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
1134         AARCH64_FL_SME adjustment here.
1135         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
1136         include SME intrinsics.
1137         (sme_function_groups): New array.
1138         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
1139         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
1140
1141 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1142
1143         PR target/113281
1144         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
1145         (struct cpu_vector_cost): Add regmove struct.
1146         (get_vector_costs): Export as global.
1147         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
1148         (costs::add_stmt_cost): Ditto.
1149         * config/riscv/riscv.cc (get_common_costs): Export global function.
1150
1151 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1152
1153         PR tree-optimization/113334
1154         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
1155         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
1156         to determine if number should be extended by all ones rather than zero
1157         extended.
1158
1159 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1160
1161         PR tree-optimization/113330
1162         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
1163         too large size.
1164
1165 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1166
1167         PR tree-optimization/113323
1168         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
1169         check for lhs being large/huge _BitInt not in m_names.
1170
1171 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1172
1173         PR tree-optimization/113316
1174         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
1175         uninitialized large/huge _BitInt arguments to calls.
1176
1177 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1178
1179         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
1180         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
1181         CEIL (TYPE_PRECISION (t), limb_prec).
1182         (bitint_large_huge::handle_cast): Likewise.
1183
1184 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
1185
1186         PR sanitizer/113284
1187         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1188         Use assemble_function_label_final () for Power ELF V1 ABI.
1189         * output.h (assemble_function_label_final): New function.
1190         * varasm.cc (assemble_function_label_raw): Use
1191         assemble_function_label_final ().
1192         (assemble_function_label_final): New function.
1193
1194 2024-01-12  Richard Biener  <rguenther@suse.de>
1195
1196         PR middle-end/113344
1197         * match.pd ((double)float CMP (double)float -> float CMP float):
1198         Perform result type check only for vectors.
1199         * fold-const.cc (fold_binary_loc): Likewise.
1200
1201 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
1202
1203         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
1204         (usdot_prod<mode>): Ditto.
1205         (sdot_prod<mode>): Ditto.
1206         (udot_prod<mode>): Ditto.
1207
1208 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
1209
1210         PR target/113288
1211         * config/i386/i386-c.cc (ix86_target_macros_internal):
1212         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
1213
1214 2024-01-12  Richard Biener  <rguenther@suse.de>
1215
1216         PR target/112280
1217         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
1218         Do not generate code when d.testing_p.
1219
1220 2024-01-12  liuhongt  <hongtao.liu@intel.com>
1221
1222         PR target/113039
1223         * doc/invoke.texi (fcf-protection=): Update documents.
1224
1225 2024-01-12  Pan Li  <pan2.li@intel.com>
1226
1227         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
1228         comments of predicate func riscv_v_ext_mode_p.
1229
1230 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
1231
1232         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
1233                         Modify ABI-name length of vfloat16m8_t
1234
1235 2024-01-12  Li Wei  <liwei@loongson.cn>
1236
1237         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
1238         Adjust.
1239
1240 2024-01-12  Li Wei  <liwei@loongson.cn>
1241
1242         * config/loongarch/loongarch.md (add<mode>3): Removed.
1243         (*addsi3): New.
1244         (addsi3): Ditto.
1245         (adddi3): Ditto.
1246         (*addsi3_extended): Removed.
1247         (addsi3_extended): New.
1248
1249 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
1250
1251         * config/riscv/thead.md: Add limits for splits.
1252
1253 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
1254
1255         PR middle-end/113322
1256         * expr.cc (do_store_flag): Don't try single bit tests with
1257         comparison on vector types.
1258
1259 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
1260
1261         PR tree-optimization/113301
1262         * match.pd (`1/x`): Delay signed case until late.
1263
1264 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
1265
1266         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
1267         and -msp8 to...
1268         (AVR Internal Options): ...this new @subsubsection.
1269
1270 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
1271
1272         PR rtl-optimization/112918
1273         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
1274         (in_class_p): Restrict condition for narrowing class in case of
1275         allow_all_reload_class_changes_p.
1276         (process_alt_operands): Try to match operand without and with
1277         narrowing reg class.  Discourage narrowing the class.  Finish insn
1278         matching only if there is no class narrowing.
1279         (curr_insn_transform): Pass true to in_class_p for reg operand win.
1280
1281 2024-01-11  Richard Biener  <rguenther@suse.de>
1282
1283         PR tree-optimization/112505
1284         * tree-vect-loop.cc (vectorizable_induction): Reject
1285         bit-precision induction.
1286
1287 2024-01-11  Richard Biener  <rguenther@suse.de>
1288
1289         PR tree-optimization/113126
1290         * match.pd ((double)float CMP (double)float -> float CMP float):
1291         Make sure the boolean type is the same.
1292         * fold-const.cc (fold_binary_loc): Likewise.
1293
1294 2024-01-11  Richard Biener  <rguenther@suse.de>
1295
1296         PR tree-optimization/112636
1297         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
1298         estimate_numbers_of_iterations before querying
1299         get_max_loop_iterations_int.
1300         (pass_ch::execute): Initialize SCEV and loops appropriately.
1301
1302 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
1303
1304         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
1305         Reduced Tiny.
1306         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
1307         * doc/extend.texi (AVR Variable Attributes): Improve documentation
1308         of io, io_low and address attributes.
1309         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
1310         * doc/avr-mmcu.texi: Rebuild.
1311
1312 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
1313
1314         PR target/113233
1315         * config/loongarch/genopts/loongarch.opt.in: Mark options with
1316         the "Save" property.
1317         * config/loongarch/loongarch.opt: Same.
1318         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
1319         according to la_target.
1320         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
1321         RESTORE} for the la_target structure; Rename option conditions
1322         to have the same "la_" prefix.
1323         * config/loongarch/loongarch.h: Same.
1324
1325 2024-01-11  Pan Li  <pan2.li@intel.com>
1326
1327         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
1328         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
1329
1330 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
1331
1332         PR target/113077
1333         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
1334         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
1335         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
1336         synthesize these if needed.  Update caller ...
1337         (ldp_bb_info::fuse_pair): ... here.
1338         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
1339         and either insn is frame-related.
1340         (find_trailing_add): Punt on frame-related insns.
1341         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
1342         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
1343
1344 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
1345
1346         * config/mips/mips.cc (mips_start_function_definition):
1347         Add ATTRIBUTE_UNUSED.
1348
1349 2024-01-11  Richard Biener  <rguenther@suse.de>
1350
1351         PR middle-end/112740
1352         * expr.cc (store_constructor): Check the integer vector
1353         mask has a single bit per element before using sign-extension
1354         to expand an uniform vector.
1355
1356 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1357
1358         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
1359         preempt VLS on unknown NITERS loop.
1360
1361 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
1362
1363         * doc/invoke.texi: Add -mevex512.
1364
1365 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
1366
1367         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
1368         (*nor<mode>3): Likewise.
1369         (nor<mode>3): Likewise.
1370         (*negsi2_extended): New template.
1371         (*<optab>si3_internal): Likewise.
1372         (*one_cmplsi2_internal): Likewise.
1373         (*norsi3_internal): Likewise.
1374         (*<optab>nsi_internal): Likewise.
1375         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
1376         modified bit operation to make the optimization work.
1377
1378 2024-01-11  liuhongt  <hongtao.liu@intel.com>
1379
1380         PR target/104401
1381         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
1382
1383 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1384
1385         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
1386         (get_vector_costs): Ditto.
1387         (riscv_builtin_vectorization_cost): Ditto.
1388
1389 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1390
1391         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
1392
1393 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
1394
1395         PR jit/111396
1396         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
1397         ipa_free_size_summary.
1398         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
1399         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
1400         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
1401         * ipa-prop.h (ipa_prop_cc_finalize): New function.
1402         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
1403         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
1404         ipa_sra_cc_finalize): New functions.
1405         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
1406         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
1407         ipa_sra_cc_finalize
1408         Include ipa-utils.h.
1409
1410 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
1411
1412         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
1413         (th_int_get_save_adjustment): Likewise.
1414         (th_int_adjust_cfi_prologue): Likewise.
1415         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
1416         (TH_INT_INTERRUPT): New macro.
1417         (riscv_expand_prologue): Add the processing of XTheadInt.
1418         (riscv_expand_epilogue): Likewise.
1419         * config/riscv/riscv.h (BITSET_P): Moved to here.
1420         * config/riscv/riscv.md: New unspec.
1421         * config/riscv/thead.cc (th_int_get_mask): New function.
1422         (th_int_get_save_adjustment): Likewise.
1423         (th_int_adjust_cfi_prologue): Likewise.
1424         * config/riscv/thead.md (th_int_push): New pattern.
1425         (th_int_pop): new pattern.
1426
1427 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1428
1429         PR tree-optimization/112468
1430         * doc/sourcebuild.texi: Document ifn_copysign.
1431         * match.pd: Only apply transformation if target supports the IFN.
1432
1433 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
1434
1435         PR tree-optimization/112581
1436         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
1437         mark_ssa_maybe_undefs.
1438         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
1439         variables can not be reassociated.
1440         (init_range_entry): Check for uninitialized variables too.
1441         (init_reassoc): Call mark_ssa_maybe_undefs.
1442
1443 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
1444
1445         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
1446         Also handle sign extension.
1447
1448 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
1449
1450         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
1451         to 0.
1452         (-mlate-ldp-fusion): Likewise.
1453
1454 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1455
1456         PR tree-optimization/113287
1457         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
1458         instead of using BRANCH_EDGE to determine true edge.
1459
1460 2024-01-10  Richard Biener  <rguenther@suse.de>
1461
1462         PR tree-optimization/113078
1463         * tree-vect-loop.cc (check_reduction_path): Canonicalize
1464         .COND_SUB to .COND_ADD.
1465
1466 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1467
1468         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
1469         Handle prefix mappings before calling find_opt.
1470         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
1471         "-fno-"-prefixed command-line option.
1472         * opts-common.cc (get_option_prefix_remapping): New.
1473         * opts.h (get_option_prefix_remapping): New decl.
1474
1475 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1476
1477         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
1478         m_urlifier to pp_output_formatted_text.
1479         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
1480         (obstack_append_string): New overload, taking a length.
1481         (urlify_quoted_string): Pass in an obstack ptr, rather than using
1482         that of the pp's buffer.  Generalize to handle trailing text in
1483         the buffer beyond the run of quoted text.
1484         (class quoting_info): New.
1485         (on_begin_quote): New.
1486         (on_end_quote): New.
1487         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
1488         it to calls to on_begin_quote and on_end_quote.
1489         (struct auto_obstack): New.
1490         (quoting_info::handle_phase_3): New.
1491         (pp_output_formatted_text): Add urlifier param.  Use it if there
1492         is deferred urlification.  Delete m_quotes.
1493         (selftest::pp_printf_with_urlifier): Pass urlifier to
1494         pp_output_formatted_text.
1495         (selftest::test_urlification): Update results for the existing
1496         case of quoted text stradding chunks; add more such test cases.
1497         * pretty-print.h (class quoting_info): New forward decl.
1498         (chunk_info::m_quotes): New field.
1499         (pp_output_formatted_text): Add optional urlifier param.
1500
1501 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1502
1503         * pretty-print.cc (selftest::test_pp_format): Add selftest
1504         coverage for numbered args.
1505
1506 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1507
1508         PR tree-optimization/113144
1509         PR tree-optimization/113145
1510         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1511         Update all BB that the original exits dominated.
1512
1513 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
1514
1515         * dwarf2out.cc (modified_type_die): Extend the support of reverse
1516         storage order to enumeration types if -gstrict-dwarf is not passed.
1517         (gen_enumeration_type_die): Add REVERSE parameter and generate the
1518         DIE immediately after the existing one if it is true.
1519         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
1520         call to gen_enumeration_type_die.
1521         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
1522         first recursive call as well as the call to gen_tagged_type_die.
1523         (gen_type_die): Add REVERSE parameter and pass it in the call to
1524         gen_type_die_with_usage.
1525
1526 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
1527
1528         PR tree-optimization/113120
1529         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
1530         with root->size TYPE_PRECISION don't build anything new.
1531         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
1532         rather than build_nonstandard_integer_type.
1533
1534 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
1535
1536         * config/i386/i386.opt: Adjust document.
1537         * doc/invoke.texi: Add description for
1538         -mapx-inline-asm-use-gpr32.
1539
1540 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1541
1542         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
1543         (avg<v_double_trunc>3_floor): New pattern.
1544         (<u>avg<v_double_trunc>3_ceil): Remove.
1545         (avg<v_double_trunc>3_ceil): New pattern.
1546         (uavg<mode>3_floor): Ditto.
1547         (uavg<mode>3_ceil): Ditto.
1548         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
1549         (enum insn_type): Ditto.
1550         * config/riscv/riscv-v.cc: Ditto.
1551         * config/riscv/vector-iterators.md (ashiftrt): Remove.
1552         (ASHIFTRT): Ditto.
1553         * config/riscv/vector.md: Add VLS modes.
1554
1555 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1556
1557         PR target/111480
1558         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
1559         (vczlsbb_char): New int attribute.
1560         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
1561         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
1562         (*vctzlsbb_zext_<mode>): Rename to ...
1563         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
1564         cover vclzlsbb.
1565
1566 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1567
1568         PR target/112606
1569         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
1570         of the last argument from altivec_register_operand to any_operand.  If
1571         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
1572         otherwise if it doesn't satisfy altivec_register_operand, force it to
1573         REG using copy_to_mode_reg.
1574
1575 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1576
1577         PR middle-end/113100
1578         * builtins.cc (expand_builtin_stack_address): Guard stack point
1579         adjustment with SPARC_STACK_BOUNDARY_HACK.
1580
1581 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1582
1583         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
1584         argument string definitions.
1585         * config/loongarch/loongarch-str.h: Same.
1586         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
1587         as aliases to -mexplicit-relocs={always,none}
1588         * config/loongarch/loongarch.opt: Regenerate.
1589         * config/loongarch/loongarch.cc: Same.
1590
1591 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1592
1593         * config/loongarch/loongarch-def.h: Define constants with
1594         enums instead of Macros.
1595
1596 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1597
1598         * config/loongarch/genopts/loongarch-strings: Rename.
1599         * config/loongarch/genopts/loongarch.opt.in: Same.
1600         * config/loongarch/loongarch-cpu.cc: Same.
1601         * config/loongarch/loongarch-def.cc: Same.
1602         * config/loongarch/loongarch-def.h: Same.
1603         * config/loongarch/loongarch-opts.cc: Same.
1604         * config/loongarch/loongarch-opts.h: Same.
1605         * config/loongarch/loongarch-str.h: Same.
1606         * config/loongarch/loongarch.opt: Same.
1607
1608 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1609
1610         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
1611         variable with the common la_ prefix.
1612         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
1613         flags as saved using TargetVariable.
1614         * config/loongarch/loongarch.opt: Same.
1615         * config/loongarch/loongarch-def.h: Define evolution_set to
1616         mark changes to the -march default.
1617         * config/loongarch/loongarch-driver.cc: Same.
1618         * config/loongarch/loongarch-opts.cc: Same.
1619         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
1620         conditions around the la_target structure.
1621         * config/loongarch/loongarch.cc: Same.
1622         * config/loongarch/loongarch.md: Same.
1623         * config/loongarch/loongarch-builtins.cc: Same.
1624         * config/loongarch/loongarch-c.cc: Same.
1625         * config/loongarch/lasx.md: Same.
1626         * config/loongarch/lsx.md: Same.
1627         * config/loongarch/sync.md: Same.
1628
1629 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
1630
1631         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
1632         no less.
1633
1634 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
1635
1636         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
1637
1638 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1639
1640         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
1641         restart_loop.
1642         (vectorizable_live_operation): Likewise.
1643
1644 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1645
1646         PR tree-optimization/113199
1647         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
1648         BIT_FIELD_REF.
1649
1650 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
1651
1652         PR target/113270
1653         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
1654         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
1655         GTY(()) declaration before the definition, drop GTY(()) drom the
1656         definition.
1657
1658 2024-01-09  Richard Biener  <rguenther@suse.de>
1659
1660         PR tree-optimization/113026
1661         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
1662         redundant and wrong niter bound setting.  Move niter
1663         bound adjustment down.
1664
1665 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1666
1667         PR middle-end/113163
1668         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
1669         Reject non-linear inductions that aren't supported.
1670
1671 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
1672
1673         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
1674         left shift implementation strategies.
1675         (arc_shift_info): Type for each entry of the shift strategy table.
1676         (arc_shift_context_idx): Return a integer value for each code
1677         generation context, used as an index
1678         (arc_ashl_alg): Table indexed by context and shifted bit count.
1679         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
1680         left shift implementation.
1681         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
1682         provide accurate costs, when optimizing for speed or size.
1683
1684 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1685
1686         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
1687
1688 2024-01-09  Julian Brown  <julian@codesourcery.com>
1689
1690         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
1691         processed out before gimplification.
1692         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
1693         * tree.def (OMP_ARRAY_SECTION): New tree code.
1694
1695 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
1696
1697         PR tree-optimization/113210
1698         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
1699         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
1700         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
1701         minus 1.
1702
1703 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
1704
1705         PR rtl-optimization/113140
1706         * reorg.cc (fill_slots_from_thread): If we are to branch after the
1707         last instruction of the function, create an end label.
1708
1709 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
1710             Hongtao Liu  <hongtao.liu@intel.com>
1711
1712         PR target/112992
1713         * config/i386/i386-expand.cc
1714         (ix86_convert_const_wide_int_to_broadcast): Allow call to
1715         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
1716         (ix86_broadcast_from_constant): Revert recent change; Return a
1717         suitable MEMREF independently of mode/target combinations.
1718         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
1719         to decide whether expansion is possible/preferrable.  Only try
1720         forcing DImode constants to memory (and trying again) if calling
1721         ix86_expand_vector_init_duplicate fails with an DImode immediate
1722         constant.
1723         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
1724         V4SImode for suitable immediate constants.
1725         <case E_V4DImode>: Try using V8SImode for suitable constants.
1726         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
1727         <case E_V2HImode>: Likewise.
1728         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
1729         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
1730         <label widen>: Handle CONT_INTs via simplify_binary_operation.
1731         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
1732         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
1733         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
1734         (ix86_expand_vector_init): Move try using a broadcast for all_same
1735         with ix86_expand_vector_init_duplicate before using constant pool.
1736
1737 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
1738
1739         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
1740
1741 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
1742
1743         * config/arm/arm-cpus.in (cortex-m52): New cpu.
1744         * config/arm/arm-tables.opt: Regenerate.
1745         * config/arm/arm-tune.md: Regenerate.
1746
1747 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
1748
1749         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
1750         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
1751         (@vec_concatz<mode>): New insn pattern.
1752         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
1753         Handle VALS containing two vectors.
1754
1755 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1756
1757         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
1758         (vundefined): Ditto.
1759
1760 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
1761
1762         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1763                                 Add new function_base for crypto vector.
1764         (class bitmanip): Ditto.
1765         (class b_reverse):Ditto.
1766         (class vwsll):   Ditto.
1767         (class clmul):   Ditto.
1768         (class vg_nhab):  Ditto.
1769         (class crypto_vv):Ditto.
1770         (class crypto_vi):Ditto.
1771         (class vaeskf2_vsm3c):Ditto.
1772         (class vsm3me): Ditto.
1773         (BASE): Add BASE declaration for crypto vector.
1774         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1775         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1776                                 Add crypto vector intrinsic definition.
1777         (vbrev): Ditto.
1778         (vclz): Ditto.
1779         (vctz): Ditto.
1780         (vwsll): Ditto.
1781         (vandn): Ditto.
1782         (vbrev8): Ditto.
1783         (vrev8): Ditto.
1784         (vrol): Ditto.
1785         (vror): Ditto.
1786         (vclmul): Ditto.
1787         (vclmulh): Ditto.
1788         (vghsh): Ditto.
1789         (vgmul): Ditto.
1790         (vaesef): Ditto.
1791         (vaesem): Ditto.
1792         (vaesdf): Ditto.
1793         (vaesdm): Ditto.
1794         (vaesz): Ditto.
1795         (vaeskf1): Ditto.
1796         (vaeskf2): Ditto.
1797         (vsha2ms): Ditto.
1798         (vsha2ch): Ditto.
1799         (vsha2cl): Ditto.
1800         (vsm4k): Ditto.
1801         (vsm4r): Ditto.
1802         (vsm3me): Ditto.
1803         (vsm3c): Ditto.
1804         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1805                                 Add new function_shape for crypto vector.
1806         (struct crypto_vi_def): Ditto.
1807         (struct crypto_vv_no_op_type_def): Ditto.
1808         (SHAPE): Add SHAPE declaration of crypto vector.
1809         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1810         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1811                                 Add new data type for crypto vector.
1812         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1813         (vuint32mf2_t): Ditto.
1814         (vuint32m1_t): Ditto.
1815         (vuint32m2_t): Ditto.
1816         (vuint32m4_t): Ditto.
1817         (vuint32m8_t): Ditto.
1818         (vuint64m1_t): Ditto.
1819         (vuint64m2_t): Ditto.
1820         (vuint64m4_t): Ditto.
1821         (vuint64m8_t): Ditto.
1822         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1823                                 Add new data struct for crypto vector.
1824         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1825         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1826         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1827
1828 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
1829
1830         PR sanitizer/113251
1831         * varasm.cc (assemble_function_label_raw): Do not call
1832         asan_function_start () without the current function.
1833
1834 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1835
1836         PR target/113225
1837         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
1838         extern and kernel_helper attributed function decls.
1839
1840 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1841
1842         * btfout.cc (output_btf_strs): Changed.
1843
1844 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1845
1846         * config/gcn/mkoffload.cc (main): Handle gfx1100
1847         when setting the default XNACK.
1848
1849 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1850
1851         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
1852         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
1853         (ASM_SPEC): Handle gfx1100.
1854         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
1855         (enum gcn_isa): Add ISA_RDNA3.
1856         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
1857         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1858         * config/gcn/gcn.cc (gcn_option_override,
1859         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
1860         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
1861         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1862         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
1863         with gfx1100.
1864         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
1865         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
1866         __gfx1100__.
1867         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1868         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
1869         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
1870         (isa_has_combined_avgprs, main): Handle gfx1100.
1871         * config/gcn/t-omp-device (isa): Add gfx1100.
1872
1873 2024-01-08  Richard Biener  <rguenther@suse.de>
1874
1875         * doc/invoke.texi (-mmovbe): Clarify.
1876
1877 2024-01-08  Richard Biener  <rguenther@suse.de>
1878
1879         PR tree-optimization/113026
1880         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
1881         Avoid an epilog in more cases.
1882         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
1883         epilogues niter upper bounds and estimates.
1884
1885 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1886
1887         PR tree-optimization/113228
1888         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
1889
1890 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1891
1892         PR tree-optimization/113120
1893         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
1894         large _BitInt zero INTEGER_CST PHI argument.
1895
1896 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1897
1898         PR tree-optimization/113119
1899         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
1900         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
1901         is before REALPART_EXPR.
1902
1903 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
1904
1905         PR target/112952
1906         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
1907         range when diagnosing attribute "io" and "io_low" are out of range.
1908         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
1909         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
1910         in contexts other than static storage.
1911         (avr_asm_output_aligned_decl_common): Move output of decls with
1912         attribute "address", "io", and "io_low" to...
1913         (avr_output_addr_attrib): ...this new function.
1914         (avr_asm_asm_output_aligned_bss): Remove output for decls with
1915         attribute "address", "io", and "io_low".
1916         (avr_encode_section_info): Rectify handling of decls with attribute
1917         "address", "io", and "io_low".
1918
1919 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1920
1921         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
1922         (elf_flags): Remove XNACK from the default value.
1923         (main): Set a default XNACK according to the arch.
1924
1925 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1926
1927         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
1928         (process_asm): Don't count avgprs.
1929
1930 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
1931
1932         * config/i386/i386.opt: Add supported sub-features.
1933         * doc/extend.texi: Add description for target attribute.
1934
1935 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
1936
1937         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
1938
1939 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
1940             Uros Bizjak  <ubizjak@gmail.com>
1941
1942         PR target/113231
1943         * config/i386/i386-features.cc (compute_convert_gain): Include
1944         the overhead of explicit load and store (movd) instructions when
1945         converting non-store scalar operations with memory destinations.
1946         Various indentation whitespace fixes.
1947
1948 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
1949
1950         * config/arm/neon.md (cbranch<mode>4): New.
1951
1952 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1953
1954         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
1955
1956 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
1957
1958         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
1959
1960 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1961
1962         PR target/113248
1963         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
1964         Update the MAX_SEW.
1965
1966 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1967
1968         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
1969         (variable_vectorized_p): Teach loop invariant.
1970         (has_unexpected_spills_p): Ditto.
1971
1972 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1973
1974         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
1975         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
1976         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
1977
1978 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
1979
1980         PR target/113104
1981         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
1982         (aarch64-vect-compare-costs): ...this.
1983         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
1984         Replace with...
1985         (-param=aarch64-vect-compare-costs=): ...this new param.
1986         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
1987         Don't disable it when vectorizing for Advanced SIMD only.
1988         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
1989         whenever aarch64_vect_compare_costs is true.
1990
1991 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
1992
1993         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
1994         Modify the method of determining the memory offset of [x]vld/[x]vst.
1995         (lasx_mxst_<lasxfmt_f>): Likewise.
1996         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
1997         (loongarch_address_insns): Likewise.
1998         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
1999         (lsx_st_<lsxfmt_f>): Likewise.
2000         * config/loongarch/predicates.md (aq10b_operand): Likewise.
2001         (aq10h_operand): Likewise.
2002         (aq10w_operand): Likewise.
2003         (aq10d_operand): Likewise.
2004
2005 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
2006
2007         PR target/113217
2008         * config/aarch64/aarch64-ldp-fusion.cc
2009         (ldp_bb_info::try_fuse_pair): If the second access can throw,
2010         narrow the move range to exactly that insn.
2011
2012 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
2013
2014         * asan.cc (asan_function_start): Drop switch_to_section ().
2015         (asan_emit_stack_protection): Set .LASANPC alignment.
2016         * config/i386/i386.cc: Use assemble_function_label_raw ()
2017         instead of ASM_OUTPUT_LABEL ().
2018         * config/s390/s390.cc (s390_asm_output_function_label):
2019         Likewise.
2020         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
2021         * final.cc (final_start_function_1): Drop
2022         asan_function_start ().
2023         * output.h (assemble_function_label_raw): New function.
2024         * varasm.cc (assemble_function_label_raw): Likewise.
2025
2026 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
2027
2028         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
2029         Use ASM_OUTPUT_FUNCTION_LABEL ().
2030         * config/alpha/alpha.cc (alpha_start_function): Likewise.
2031         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2032         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
2033         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2034         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2035         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
2036         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2037         * config/ia64/ia64.cc (ia64_start_function): Likewise.
2038         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
2039         Likewise.
2040         * config/microblaze/microblaze.cc (microblaze_function_prologue):
2041         Likewise.
2042         * config/mips/mips.cc (mips_start_unique_function): Return the
2043         tree.
2044         (mips_start_function_definition): Use
2045         ASM_OUTPUT_FUNCTION_LABEL ().
2046         (mips_finish_stub): Pass the tree to
2047         mips_start_function_definition ().
2048         (mips16_build_function_stub): Likewise.
2049         (mips16_build_call_stub): Likewise.
2050         (mips_output_function_prologue): Likewise.
2051         * config/pa/pa.cc (pa_output_function_label): Use
2052         ASM_OUTPUT_FUNCTION_LABEL ().
2053         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
2054         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
2055         Likewise.
2056         (rs6000_xcoff_declare_function_name): Likewise.
2057
2058 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
2059
2060         PR tree-optimization/113201
2061         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
2062         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
2063
2064 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
2065
2066         PR tree-optimization/90693
2067         * tree-ssa-math-opts.cc (match_single_bit_test): If
2068         tree_expr_nonzero_p (arg), remember it in the second argument to
2069         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
2070         arg ^ (arg - 1) > arg - 1.
2071         * internal-fn.cc (expand_POPCOUNT): If second argument to
2072         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
2073         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
2074
2075 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
2076
2077         * config/riscv/riscv-v.cc (expand_load_store):
2078         Remove `value`.
2079         (expand_cond_len_op): Ditto.
2080         (expand_gather_scatter): Ditto.
2081         (expand_lanes_load_store): Ditto.
2082         (expand_fold_extract_last): Ditto.
2083
2084 2024-01-05  Pan Li  <pan2.li@intel.com>
2085
2086         Revert:
2087         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
2088
2089         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2090                                 Add new function_base for crypto vector.
2091         (class bitmanip): Ditto.
2092         (class b_reverse):Ditto.
2093         (class vwsll):   Ditto.
2094         (class clmul):   Ditto.
2095         (class vg_nhab):  Ditto.
2096         (class crypto_vv):Ditto.
2097         (class crypto_vi):Ditto.
2098         (class vaeskf2_vsm3c):Ditto.
2099         (class vsm3me): Ditto.
2100         (BASE): Add BASE declaration for crypto vector.
2101         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2102         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2103                                 Add crypto vector intrinsic definition.
2104         (vbrev): Ditto.
2105         (vclz): Ditto.
2106         (vctz): Ditto.
2107         (vwsll): Ditto.
2108         (vandn): Ditto.
2109         (vbrev8): Ditto.
2110         (vrev8): Ditto.
2111         (vrol): Ditto.
2112         (vror): Ditto.
2113         (vclmul): Ditto.
2114         (vclmulh): Ditto.
2115         (vghsh): Ditto.
2116         (vgmul): Ditto.
2117         (vaesef): Ditto.
2118         (vaesem): Ditto.
2119         (vaesdf): Ditto.
2120         (vaesdm): Ditto.
2121         (vaesz): Ditto.
2122         (vaeskf1): Ditto.
2123         (vaeskf2): Ditto.
2124         (vsha2ms): Ditto.
2125         (vsha2ch): Ditto.
2126         (vsha2cl): Ditto.
2127         (vsm4k): Ditto.
2128         (vsm4r): Ditto.
2129         (vsm3me): Ditto.
2130         (vsm3c): Ditto.
2131         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2132                                 Add new function_shape for crypto vector.
2133         (struct crypto_vi_def): Ditto.
2134         (struct crypto_vv_no_op_type_def): Ditto.
2135         (SHAPE): Add SHAPE declaration of crypto vector.
2136         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2137         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2138                                 Add new data type for crypto vector.
2139         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2140         (vuint32mf2_t): Ditto.
2141         (vuint32m1_t): Ditto.
2142         (vuint32m2_t): Ditto.
2143         (vuint32m4_t): Ditto.
2144         (vuint32m8_t): Ditto.
2145         (vuint64m1_t): Ditto.
2146         (vuint64m2_t): Ditto.
2147         (vuint64m4_t): Ditto.
2148         (vuint64m8_t): Ditto.
2149         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2150                                 Add new data struct for crypto vector.
2151         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2152         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2153         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2154
2155 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
2156
2157         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2158                                 Add new function_base for crypto vector.
2159         (class bitmanip): Ditto.
2160         (class b_reverse):Ditto.
2161         (class vwsll):   Ditto.
2162         (class clmul):   Ditto.
2163         (class vg_nhab):  Ditto.
2164         (class crypto_vv):Ditto.
2165         (class crypto_vi):Ditto.
2166         (class vaeskf2_vsm3c):Ditto.
2167         (class vsm3me): Ditto.
2168         (BASE): Add BASE declaration for crypto vector.
2169         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2170         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2171                                 Add crypto vector intrinsic definition.
2172         (vbrev): Ditto.
2173         (vclz): Ditto.
2174         (vctz): Ditto.
2175         (vwsll): Ditto.
2176         (vandn): Ditto.
2177         (vbrev8): Ditto.
2178         (vrev8): Ditto.
2179         (vrol): Ditto.
2180         (vror): Ditto.
2181         (vclmul): Ditto.
2182         (vclmulh): Ditto.
2183         (vghsh): Ditto.
2184         (vgmul): Ditto.
2185         (vaesef): Ditto.
2186         (vaesem): Ditto.
2187         (vaesdf): Ditto.
2188         (vaesdm): Ditto.
2189         (vaesz): Ditto.
2190         (vaeskf1): Ditto.
2191         (vaeskf2): Ditto.
2192         (vsha2ms): Ditto.
2193         (vsha2ch): Ditto.
2194         (vsha2cl): Ditto.
2195         (vsm4k): Ditto.
2196         (vsm4r): Ditto.
2197         (vsm3me): Ditto.
2198         (vsm3c): Ditto.
2199         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2200                                 Add new function_shape for crypto vector.
2201         (struct crypto_vi_def): Ditto.
2202         (struct crypto_vv_no_op_type_def): Ditto.
2203         (SHAPE): Add SHAPE declaration of crypto vector.
2204         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2205         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2206                                 Add new data type for crypto vector.
2207         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2208         (vuint32mf2_t): Ditto.
2209         (vuint32m1_t): Ditto.
2210         (vuint32m2_t): Ditto.
2211         (vuint32m4_t): Ditto.
2212         (vuint32m8_t): Ditto.
2213         (vuint64m1_t): Ditto.
2214         (vuint64m2_t): Ditto.
2215         (vuint64m4_t): Ditto.
2216         (vuint64m8_t): Ditto.
2217         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2218                                 Add new data struct for crypto vector.
2219         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2220         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2221         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2222
2223 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2224
2225         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2226
2227 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
2228
2229         PR tree-optimization/113186
2230         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
2231         Match `^` with the `==` for 1bit integral types.
2232         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
2233         integral types.
2234
2235 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2236
2237         * toplev.cc (general_init): Pass lang_mask to urlifier.
2238
2239 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2240
2241         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
2242         param.
2243         (diagnostic_context::make_option_url): Update for lang_mask param.
2244         * gcc-urlifier.cc: Include "opts.h" and "options.h".
2245         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
2246         (gcc_urlifier::m_lang_mask): New field.
2247         (doc_urls): Make static.
2248         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
2249         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2250         Look for an option by name before trying a binary search in
2251         doc_urls.
2252         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2253         (gcc_urlifier::get_url_suffix_for_option): New.
2254         (make_gcc_urlifier): Add lang_mask param.
2255         (selftest::gcc_urlifier_cc_tests): Update for above changes.
2256         Verify that a URL is found for "-fpack-struct".
2257         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
2258         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
2259         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
2260         to make_gcc_urlifier.
2261         * opts-diagnostic.h (get_option_url): Add lang_mask param.
2262         * opts.cc (get_option_html_page): Remove special-casing for
2263         analyzer and LTO.
2264         (get_option_url_suffix): New.
2265         (get_option_url): Reimplement.
2266         (selftest::test_get_option_html_page): Rename to...
2267         (selftest::test_get_option_url_suffix): ...this and update for
2268         above changes.
2269         (selftest::opts_cc_tests): Update for renaming.
2270         * opts.h: Include "rich-location.h".
2271         (get_option_url_suffix): New decl.
2272
2273 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2274
2275         * Makefile.in (ALL_OPT_URL_FILES): New.
2276         (GCC_OBJS): Add options-urls.o.
2277         (OBJS): Likewise.
2278         (OBJS-libcommon): Likewise.
2279         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
2280         inputs to opt-gather.awk.
2281         (options-urls.cc): New Makefile target.
2282         * opt-functions.awk (url_suffix): New function.
2283         (lang_url_suffix): New function.
2284         * options-urls-cc-gen.awk: New file.
2285         * opts.h (get_opt_url_suffix): New decl.
2286
2287 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2288
2289         * params.opt.urls: New file, autogenerated by
2290         regenerate-opt-urls.py.
2291
2292 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2293
2294         * common.opt.urls: New file, autogenerated by
2295         regenerate-opt-urls.py.
2296         * config/aarch64/aarch64.opt.urls: Likewise.
2297         * config/alpha/alpha.opt.urls: Likewise.
2298         * config/alpha/elf.opt.urls: Likewise.
2299         * config/arc/arc-tables.opt.urls: Likewise.
2300         * config/arc/arc.opt.urls: Likewise.
2301         * config/arm/arm-tables.opt.urls: Likewise.
2302         * config/arm/arm.opt.urls: Likewise.
2303         * config/arm/vxworks.opt.urls: Likewise.
2304         * config/avr/avr.opt.urls: Likewise.
2305         * config/bpf/bpf.opt.urls: Likewise.
2306         * config/c6x/c6x-tables.opt.urls: Likewise.
2307         * config/c6x/c6x.opt.urls: Likewise.
2308         * config/cris/cris.opt.urls: Likewise.
2309         * config/cris/elf.opt.urls: Likewise.
2310         * config/csky/csky.opt.urls: Likewise.
2311         * config/csky/csky_tables.opt.urls: Likewise.
2312         * config/darwin.opt.urls: Likewise.
2313         * config/dragonfly.opt.urls: Likewise.
2314         * config/epiphany/epiphany.opt.urls: Likewise.
2315         * config/fr30/fr30.opt.urls: Likewise.
2316         * config/freebsd.opt.urls: Likewise.
2317         * config/frv/frv.opt.urls: Likewise.
2318         * config/ft32/ft32.opt.urls: Likewise.
2319         * config/fused-madd.opt.urls: Likewise.
2320         * config/g.opt.urls: Likewise.
2321         * config/gcn/gcn.opt.urls: Likewise.
2322         * config/gnu-user.opt.urls: Likewise.
2323         * config/h8300/h8300.opt.urls: Likewise.
2324         * config/hpux11.opt.urls: Likewise.
2325         * config/i386/cygming.opt.urls: Likewise.
2326         * config/i386/cygwin.opt.urls: Likewise.
2327         * config/i386/djgpp.opt.urls: Likewise.
2328         * config/i386/i386.opt.urls: Likewise.
2329         * config/i386/mingw-w64.opt.urls: Likewise.
2330         * config/i386/mingw.opt.urls: Likewise.
2331         * config/i386/nto.opt.urls: Likewise.
2332         * config/ia64/ia64.opt.urls: Likewise.
2333         * config/ia64/ilp32.opt.urls: Likewise.
2334         * config/ia64/vms.opt.urls: Likewise.
2335         * config/iq2000/iq2000.opt.urls: Likewise.
2336         * config/linux-android.opt.urls: Likewise.
2337         * config/linux.opt.urls: Likewise.
2338         * config/lm32/lm32.opt.urls: Likewise.
2339         * config/loongarch/loongarch.opt.urls: Likewise.
2340         * config/lynx.opt.urls: Likewise.
2341         * config/m32c/m32c.opt.urls: Likewise.
2342         * config/m32r/m32r.opt.urls: Likewise.
2343         * config/m68k/ieee.opt.urls: Likewise.
2344         * config/m68k/m68k-tables.opt.urls: Likewise.
2345         * config/m68k/m68k.opt.urls: Likewise.
2346         * config/m68k/uclinux.opt.urls: Likewise.
2347         * config/mcore/mcore.opt.urls: Likewise.
2348         * config/microblaze/microblaze.opt.urls: Likewise.
2349         * config/mips/mips-tables.opt.urls: Likewise.
2350         * config/mips/mips.opt.urls: Likewise.
2351         * config/mips/sde.opt.urls: Likewise.
2352         * config/mmix/mmix.opt.urls: Likewise.
2353         * config/mn10300/mn10300.opt.urls: Likewise.
2354         * config/moxie/moxie.opt.urls: Likewise.
2355         * config/msp430/msp430.opt.urls: Likewise.
2356         * config/nds32/nds32-elf.opt.urls: Likewise.
2357         * config/nds32/nds32-linux.opt.urls: Likewise.
2358         * config/nds32/nds32.opt.urls: Likewise.
2359         * config/netbsd-elf.opt.urls: Likewise.
2360         * config/netbsd.opt.urls: Likewise.
2361         * config/nios2/elf.opt.urls: Likewise.
2362         * config/nios2/nios2.opt.urls: Likewise.
2363         * config/nvptx/nvptx-gen.opt.urls: Likewise.
2364         * config/nvptx/nvptx.opt.urls: Likewise.
2365         * config/openbsd.opt.urls: Likewise.
2366         * config/or1k/elf.opt.urls: Likewise.
2367         * config/or1k/or1k.opt.urls: Likewise.
2368         * config/pa/pa-hpux.opt.urls: Likewise.
2369         * config/pa/pa-hpux1010.opt.urls: Likewise.
2370         * config/pa/pa-hpux1111.opt.urls: Likewise.
2371         * config/pa/pa-hpux1131.opt.urls: Likewise.
2372         * config/pa/pa.opt.urls: Likewise.
2373         * config/pa/pa64-hpux.opt.urls: Likewise.
2374         * config/pdp11/pdp11.opt.urls: Likewise.
2375         * config/pru/pru.opt.urls: Likewise.
2376         * config/riscv/riscv.opt.urls: Likewise.
2377         * config/rl78/rl78.opt.urls: Likewise.
2378         * config/rpath.opt.urls: Likewise.
2379         * config/rs6000/476.opt.urls: Likewise.
2380         * config/rs6000/aix64.opt.urls: Likewise.
2381         * config/rs6000/darwin.opt.urls: Likewise.
2382         * config/rs6000/linux64.opt.urls: Likewise.
2383         * config/rs6000/rs6000-tables.opt.urls: Likewise.
2384         * config/rs6000/rs6000.opt.urls: Likewise.
2385         * config/rs6000/sysv4.opt.urls: Likewise.
2386         * config/rtems.opt.urls: Likewise.
2387         * config/rx/elf.opt.urls: Likewise.
2388         * config/rx/rx.opt.urls: Likewise.
2389         * config/s390/s390.opt.urls: Likewise.
2390         * config/s390/tpf.opt.urls: Likewise.
2391         * config/sh/sh.opt.urls: Likewise.
2392         * config/sh/superh.opt.urls: Likewise.
2393         * config/sol2.opt.urls: Likewise.
2394         * config/sparc/long-double-switch.opt.urls: Likewise.
2395         * config/sparc/sparc.opt.urls: Likewise.
2396         * config/stormy16/stormy16.opt.urls: Likewise.
2397         * config/v850/v850.opt.urls: Likewise.
2398         * config/vax/elf.opt.urls: Likewise.
2399         * config/vax/vax.opt.urls: Likewise.
2400         * config/visium/visium.opt.urls: Likewise.
2401         * config/vms/vms.opt.urls: Likewise.
2402         * config/vxworks-smp.opt.urls: Likewise.
2403         * config/vxworks.opt.urls: Likewise.
2404         * config/xtensa/elf.opt.urls: Likewise.
2405         * config/xtensa/uclinux.opt.urls: Likewise.
2406         * config/xtensa/xtensa.opt.urls: Likewise.
2407         * config/bfin/bfin.opt.urls: New file.
2408
2409 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2410
2411         * Makefile.in (OPT_URLS_HTML_DEPS): New.
2412         (regenerate-opt-urls): New target.
2413         (regenerate-opt-urls-unit-test): New target.
2414         * doc/options.texi (Option properties): Add UrlSuffix and
2415         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
2416         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
2417         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
2418         and Makefile.in's OPT_URLS_HTML_DEPS.
2419         (Anatomy of a Target Back End): Add
2420         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
2421         * regenerate-opt-urls.py: New file.
2422
2423 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2424
2425         * diagnostic-format-sarif.cc
2426         (sarif_builder::make_logical_location_object): Convert to...
2427         (make_sarif_logical_location_object): ...this.
2428         (sarif_builder::set_any_logical_locs_arr): Update for above
2429         change.
2430         (sarif_builder::make_thread_flow_location_object): Call
2431         maybe_add_sarif_properties on each diagnostic_event.
2432         * diagnostic-format-sarif.h (class logical_location): New forward
2433         decl.
2434         (make_sarif_logical_location_object): New decl.
2435         * diagnostic-path.h (class sarif_object): New forward decl.
2436         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
2437
2438 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
2439             Patrick Lin  <patrick@andestech.com>
2440             Rufus Chen  <rufus@andestech.com>
2441             Monk Chiang  <monk.chiang@sifive.com>
2442
2443         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
2444         with Nan-boxing value.
2445         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
2446
2447 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
2448             Jeff Law  <jlaw@ventanamicro.com>
2449
2450         PR rtl-optimization/104914
2451         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
2452         a sign or zero extension is only required if the modified field
2453         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
2454         targets, don't refer to the temporarily incorrectly extended value
2455         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
2456
2457 2024-01-04  Pan Li  <pan2.li@intel.com>
2458
2459         Revert:
2460         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2461
2462         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2463
2464 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2465
2466         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2467
2468 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
2469
2470         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
2471         offset of fcsr.
2472
2473 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2474
2475         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
2476         (compute_nregs_for_mode): Refine LMUL.
2477         (max_number_of_live_regs): Ditto.
2478         (compute_estimated_lmul): Ditto.
2479         (has_unexpected_spills_p): Ditto.
2480
2481 2024-01-04  Li Wei  <liwei@loongson.cn>
2482
2483         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
2484         Remove useless forward declaration.
2485         (loongarch_is_even_extraction): Remove useless forward declaration.
2486         (loongarch_try_expand_lsx_vshuf_const): Removed.
2487         (loongarch_expand_vec_perm_const_1): Merged.
2488         (loongarch_is_double_duplicate): Removed.
2489         (loongarch_is_center_extraction): Ditto.
2490         (loongarch_is_reversing_permutation): Ditto.
2491         (loongarch_is_di_misalign_extract): Ditto.
2492         (loongarch_is_si_misalign_extract): Ditto.
2493         (loongarch_is_lasx_lowpart_extract): Ditto.
2494         (loongarch_is_op_reverse_perm): Ditto.
2495         (loongarch_is_single_op_perm): Ditto.
2496         (loongarch_is_divisible_perm): Ditto.
2497         (loongarch_is_triple_stride_extract): Ditto.
2498         (loongarch_expand_vec_perm_const_2): Merged.
2499         (loongarch_expand_vec_perm_const): New.
2500         (loongarch_vectorize_vec_perm_const): Adjust.
2501
2502 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
2503
2504         * omp-general.cc: Fix comment typos and misplaced/confusing
2505         comments.  Delete redundant include of omp-general.h.
2506
2507 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2508
2509         PR rtl-optimization/104914
2510         * config/mips/mips.md (insqisi_extended): New patterns.
2511         (inshisi_extended): Ditto.
2512
2513 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2514
2515         * config/mips/mips.cc (mips_insn_cost): New function.
2516
2517 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2518
2519         * config/mips/mips.md (perf_ratio): New attribute.
2520
2521 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2522
2523         PR target/113206
2524         PR target/113209
2525         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
2526         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
2527         blocks belong to infinite loop.
2528         (pre_vsetvl::emit_vsetvl): Remove fake edges.
2529         * config/riscv/t-riscv: Add a new include file.
2530
2531 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2532
2533         * config/riscv/vector.md: Fix indent.
2534
2535 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
2536
2537         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
2538         OMP_CLAUSE__SIMDUID_.
2539         * tree.cc (omp_clause_num_ops): Update position of entry for
2540         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
2541         (omp_clause_code_name): Likewise.
2542
2543 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
2544
2545         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
2546         printing of FUNC_MAP/IND_FUNC_MAP labels.
2547
2548 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
2549
2550         * gcc.cc (process_command): Update copyright notice dates.
2551         * gcov-dump.cc (print_version): Ditto.
2552         * gcov.cc (print_version): Ditto.
2553         * gcov-tool.cc (print_version): Ditto.
2554         * gengtype.cc (create_file): Ditto.
2555         * doc/cpp.texi: Bump @copying's copyright year.
2556         * doc/cppinternals.texi: Ditto.
2557         * doc/gcc.texi: Ditto.
2558         * doc/gccint.texi: Ditto.
2559         * doc/gcov.texi: Ditto.
2560         * doc/install.texi: Ditto.
2561         * doc/invoke.texi: Ditto.
2562
2563 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
2564
2565         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
2566         (fmin<mode>3): Likewise.
2567         (reduc_fmax_scal_<mode>3): New define_expand.
2568         (reduc_fmin_scal_<mode>3): Likewise.
2569
2570 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2571
2572         PR target/113112
2573         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
2574         (max_number_of_live_regs): Ditto.
2575         (has_unexpected_spills_p): Ditto.
2576
2577 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2578             Jin Ma  <jinma@linux.alibaba.com>
2579             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2580             Christoph Müllner  <christoph.muellner@vrull.eu>
2581
2582         * config/riscv/vector.md:
2583         Use vector_length_operand for vsetvl patterns.
2584
2585 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2586
2587         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
2588         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
2589
2590 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
2591
2592         * config/aarch64/aarch64-tuning-flags.def
2593         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
2594         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
2595         * config/aarch64/aarch64.cc
2596         (aarch64_override_options_internal): Set
2597         param_fully_pipelined_fma according to tuning option.
2598         * config/aarch64/tuning_models/ampere1.h: Add
2599         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
2600         * config/aarch64/tuning_models/ampere1a.h: Likewise.
2601         * config/aarch64/tuning_models/ampere1b.h: Likewise.
2602
2603 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
2604
2605         * config/riscv/vector-crypto.md: Modify copyright year.
2606
2607 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2608
2609         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
2610
2611 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
2612
2613         * config.in: Regenerate.
2614         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
2615         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
2616         Added TLS Le Relax support.
2617         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
2618         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
2619         * configure: Regenerate.
2620         * configure.ac: Check if binutils supports TLS le relax.
2621
2622 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
2623
2624         * config/riscv/iterators.md: Add rotate insn name.
2625         * config/riscv/riscv.md: Add new insns name for crypto vector.
2626         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
2627         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
2628         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
2629
2630 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2631
2632         PR target/113112
2633         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
2634         pointer type liveness count.
2635 \f
2636 Copyright (C) 2024 Free Software Foundation, Inc.
2637
2638 Copying and distribution of this file, with or without modification,
2639 are permitted in any medium without royalty provided the copyright
2640 notice and this notice are preserved.