gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  28   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  29
  30 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  31    It is used in nds32_encode_section_info() to store flag in symbol_ref
  32    in case the symbol should be placed in .rodata section.
  33    So that we can check it in nds32_legitimate_address_p().  */
  34 #define NDS32_SYMBOL_FLAG_RODATA \
  35   (SYMBOL_FLAG_MACH_DEP << 0)
  36 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  37   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  38
  39 /* Classifies expand result for expand helper function.  */
  40 enum nds32_expand_result_type
  41 {
  42   EXPAND_DONE,
  43   EXPAND_FAIL,
  44   EXPAND_CREATE_TEMPLATE
  45 };
  46
  47 /* Classifies address type to distinguish 16-bit/32-bit format.  */
  48 enum nds32_16bit_address_type
  49 {
  50   /* [reg]: 45 format address.  */
  51   ADDRESS_REG,
  52   /* [lo_reg + imm3u]: 333 format address.  */
  53   ADDRESS_LO_REG_IMM3U,
  54   /* post_inc [lo_reg + imm3u]: 333 format address.  */
  55   ADDRESS_POST_INC_LO_REG_IMM3U,
  56   /* post_modify [lo_reg + imm3u]: 333 format address.  */
  57   ADDRESS_POST_MODIFY_LO_REG_IMM3U,
  58   /* [$r8 + imm7u]: r8 imply address.  */
  59   ADDRESS_R8_IMM7U,
  60   /* [$fp + imm7u]: fp imply address.  */
  61   ADDRESS_FP_IMM7U,
  62   /* [$sp + imm7u]: sp imply address.  */
  63   ADDRESS_SP_IMM7U,
  64   /* Other address format.  */
  65   ADDRESS_NOT_16BIT_FORMAT
  66 };
  67
  68
  69 /* ------------------------------------------------------------------------ */
  70
  71 /* Define maximum numbers of registers for passing arguments.  */
  72 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
  73 #define NDS32_MAX_FPR_REGS_FOR_ARGS 6
  74
  75 /* Define the register number for first argument.  */
  76 #define NDS32_GPR_ARG_FIRST_REGNUM 0
  77 #define NDS32_FPR_ARG_FIRST_REGNUM 34
  78
  79 /* Define the register number for return value.  */
  80 #define NDS32_GPR_RET_FIRST_REGNUM 0
  81 #define NDS32_FPR_RET_FIRST_REGNUM 34
  82
  83 /* Define the first integer register number.  */
  84 #define NDS32_FIRST_GPR_REGNUM 0
  85 /* Define the last integer register number.  */
  86 #define NDS32_LAST_GPR_REGNUM 31
  87
  88 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
  89 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
  90   (TARGET_REDUCED_REGS ? 10 : 14)
  91
  92 /* Define the floating-point number of registers.  */
  93 #define NDS32_FLOAT_REGISTER_NUMBER                           \
  94  (((nds32_fp_regnum == NDS32_CONFIG_FPU_0)              \
  95    || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8      \
  96   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1)            \
  97     || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16    \
  98   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2)            \
  99     || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32    \
 100   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3)            \
 101     || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64    \
 102   : 32)
 103
 104 #define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
 105
 106 /* Define the first floating-point register number.  */
 107 #define NDS32_FIRST_FPR_REGNUM 34
 108 /* Define the last floating-point register number.  */
 109 #define NDS32_LAST_FPR_REGNUM \
 110   (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
 111
 112
 113 #define NDS32_IS_EXT_FPR_REGNUM(regno) \
 114   (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
 115    && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
 116
 117 #define NDS32_IS_FPR_REGNUM(regno) \
 118   (((regno) >= NDS32_FIRST_FPR_REGNUM) \
 119    && ((regno) <= NDS32_LAST_FPR_REGNUM))
 120
 121 #define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
 122   ((regno) <= NDS32_LAST_FPR_REGNUM)
 123
 124 #define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
 125   ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
 126
 127 #define NDS32_IS_GPR_REGNUM(regno) \
 128   (((regno) <= NDS32_LAST_GPR_REGNUM))
 129
 130 /* Define double word alignment bits.  */
 131 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 132
 133 /* Define alignment checking macros for convenience.  */
 134 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 135 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 136 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 137
 138 /* Determine whether we would like to have code generation strictly aligned.
 139    We set it strictly aligned when -malways-align is enabled.
 140    Check gcc/common/config/nds32/nds32-common.c for the optimizations that
 141    apply -malways-align.  */
 142 #define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
 143 /* Get alignment according to mode or type information.
 144    When 'type' is nonnull, there is no need to look at 'mode'.  */
 145 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 146   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 147
 148 /* Round X up to the nearest double word.  */
 149 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 150
 151
 152 /* This macro is used to calculate the numbers of registers for
 153    containing 'size' bytes of the argument.
 154    The size of a register is a word in nds32 target.
 155    So we use UNITS_PER_WORD to do the calculation.  */
 156 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 157   ((mode == BLKmode)                                                     \
 158    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 159    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 160
 161 /* This macro is used to return the register number for passing argument.
 162    We need to obey the following rules:
 163      1. If it is required MORE THAN one register,
 164         we need to further check if it really needs to be
 165         aligned on double words.
 166           a) If double word alignment is necessary,
 167              the register number must be even value.
 168           b) Otherwise, the register number can be odd or even value.
 169      2. If it is required ONLY one register,
 170         the register number can be odd or even value.  */
 171 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 172   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 173    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 174       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 175       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 176    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 177
 178 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
 179   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 180    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 181       ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 182       : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))               \
 183    : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
 184
 185 /* These two macros are to check if there are still available registers
 186    for passing argument, which must be entirely in registers.  */
 187 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 188   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 189     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 190    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 191        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 192
 193 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type)   \
 194   ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 195     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 196    <= (NDS32_FPR_ARG_FIRST_REGNUM                               \
 197        + NDS32_MAX_FPR_REGS_FOR_ARGS))
 198
 199 /* These two macros are to check if there are still available registers
 200    for passing argument, either entirely in registers or partially
 201    in registers.  */
 202 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 203   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 204    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 205
 206 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
 207   (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 208    < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
 209
 210 /* This macro is to check if the register is required to be saved on stack.
 211    If call_used_regs[regno] == 0, regno is the callee-saved register.
 212    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 213    As long as the register satisfies both criteria above,
 214    it is required to be saved.  */
 215 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 216   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 217
 218 /* This macro is to check if the push25/pop25 are available to be used
 219    for code generation.  Because pop25 also performs return behavior,
 220    the instructions may not be available for some cases.
 221    If we want to use push25/pop25, all the following conditions must
 222    be satisfied:
 223      1. TARGET_V3PUSH is set.
 224      2. Current function is not an ISR function.
 225      3. Current function is not a variadic function.*/
 226 #define NDS32_V3PUSH_AVAILABLE_P  \
 227   (TARGET_V3PUSH \
 228    && !nds32_isr_function_p (current_function_decl) \
 229    && (cfun->machine->va_args_size == 0))
 230
 231 /* ------------------------------------------------------------------------ */
 232
 233 /* A C structure for machine-specific, per-function data.
 234    This is added to the cfun structure.  */
 235 struct GTY(()) machine_function
 236 {
 237   /* Number of bytes allocated on the stack for variadic args
 238      if we want to push them into stack as pretend arguments by ourself.  */
 239   int va_args_size;
 240   /* Number of bytes reserved on the stack for
 241      local and temporary variables.  */
 242   int local_size;
 243   /* Number of bytes allocated on the stack for outgoing arguments.  */
 244   int out_args_size;
 245
 246   /* Number of bytes on the stack for saving $fp.  */
 247   int fp_size;
 248   /* Number of bytes on the stack for saving $gp.  */
 249   int gp_size;
 250   /* Number of bytes on the stack for saving $lp.  */
 251   int lp_size;
 252
 253   /* Number of bytes on the stack for saving general purpose
 254      callee-saved registers.  */
 255   int callee_saved_gpr_regs_size;
 256
 257   /* Number of bytes on the stack for saving floating-point
 258      callee-saved registers.  */
 259   int callee_saved_fpr_regs_size;
 260
 261   /* The padding bytes in callee-saved area may be required.  */
 262   int callee_saved_area_gpr_padding_bytes;
 263
 264   /* The first required general purpose callee-saved register.  */
 265   int callee_saved_first_gpr_regno;
 266   /* The last required general purpose callee-saved register.  */
 267   int callee_saved_last_gpr_regno;
 268
 269   /* The first required floating-point callee-saved register.  */
 270   int callee_saved_first_fpr_regno;
 271   /* The last required floating-point callee-saved register.  */
 272   int callee_saved_last_fpr_regno;
 273
 274   /* The padding bytes in varargs area may be required.  */
 275   int va_args_area_padding_bytes;
 276
 277   /* The first required register that should be saved on stack for va_args.  */
 278   int va_args_first_regno;
 279   /* The last required register that should be saved on stack for va_args.  */
 280   int va_args_last_regno;
 281
 282   /* Number of bytes on the stack for saving exception handling registers.  */
 283   int eh_return_data_regs_size;
 284   /* The first register of passing exception handling information.  */
 285   int eh_return_data_first_regno;
 286   /* The last register of passing exception handling information.  */
 287   int eh_return_data_last_regno;
 288
 289   /* Indicate that whether this function
 290      calls __builtin_eh_return.  */
 291   int use_eh_return_p;
 292
 293   /* Indicate that whether this function needs
 294      prologue/epilogue code generation.  */
 295   int naked_p;
 296   /* Indicate that whether this function
 297      uses fp_as_gp optimization.  */
 298   int fp_as_gp_p;
 299   /* Indicate that whether this function is under strictly aligned
 300      situation for legitimate address checking.  This flag informs
 301      nds32_legitimate_address_p() how to treat offset alignment:
 302        1. The IVOPT phase needs to detect available range for memory access,
 303           such as checking [base + 32767] ~ [base + (-32768)].
 304           For this case we do not want address to be strictly aligned.
 305        2. The rtl lowering and optimization are close to target code.
 306           For this case we need address to be strictly aligned.  */
 307   int strict_aligned_p;
 308 };
 309
 310 /* A C structure that contains the arguments information.  */
 311 typedef struct
 312 {
 313   unsigned int gpr_offset;
 314   unsigned int fpr_offset;
 315 } nds32_cumulative_args;
 316
 317 /* ------------------------------------------------------------------------ */
 318
 319 /* The following we define C-ISR related stuff.
 320    In nds32 architecture, we have 73 vectors for interrupt/exception.
 321    For each vector (except for vector 0, which is used for reset behavior),
 322    we allow users to set its register saving scheme and interrupt level.  */
 323
 324 /* There are 73 vectors in nds32 architecture.
 325    0 for reset handler,
 326    1-8 for exception handler,
 327    and 9-72 for interrupt handler.
 328    We use an array, which is defined in nds32.c, to record
 329    essential information for each vector.  */
 330 #define NDS32_N_ISR_VECTORS 73
 331
 332 /* Define possible isr category.  */
 333 enum nds32_isr_category
 334 {
 335   NDS32_ISR_NONE,
 336   NDS32_ISR_INTERRUPT,
 337   NDS32_ISR_EXCEPTION,
 338   NDS32_ISR_RESET
 339 };
 340
 341 /* Define isr register saving scheme.  */
 342 enum nds32_isr_save_reg
 343 {
 344   NDS32_SAVE_ALL,
 345   NDS32_PARTIAL_SAVE
 346 };
 347
 348 /* Define isr nested type.  */
 349 enum nds32_isr_nested_type
 350 {
 351   NDS32_NESTED,
 352   NDS32_NOT_NESTED,
 353   NDS32_NESTED_READY
 354 };
 355
 356 /* Define structure to record isr information.
 357    The isr vector array 'isr_vectors[]' with this structure
 358    is defined in nds32.c.  */
 359 struct nds32_isr_info
 360 {
 361   /* The field to identify isr category.
 362      It should be set to NDS32_ISR_NONE by default.
 363      If user specifies a function as isr by using attribute,
 364      this field will be set accordingly.  */
 365   enum nds32_isr_category category;
 366
 367   /* A string for the applied function name.
 368      It should be set to empty string by default.  */
 369   char func_name[100];
 370
 371   /* The register saving scheme.
 372      It should be set to NDS32_PARTIAL_SAVE by default
 373      unless user specifies attribute to change it.  */
 374   enum nds32_isr_save_reg save_reg;
 375
 376   /* The nested type.
 377      It should be set to NDS32_NOT_NESTED by default
 378      unless user specifies attribute to change it.  */
 379   enum nds32_isr_nested_type nested_type;
 380
 381   /* Total vectors.
 382      The total vectors = interrupt + exception numbers + reset.
 383      It should be set to 0 by default.
 384      This field is ONLY used in NDS32_ISR_RESET category.  */
 385   unsigned int total_n_vectors;
 386
 387   /* A string for nmi handler name.
 388      It should be set to empty string by default.
 389      This field is ONLY used in NDS32_ISR_RESET category.  */
 390   char nmi_name[100];
 391
 392   /* A string for warm handler name.
 393      It should be set to empty string by default.
 394      This field is ONLY used in NDS32_ISR_RESET category.  */
 395   char warm_name[100];
 396 };
 397
 398 /* ------------------------------------------------------------------------ */
 399
 400 /* Define code for all nds32 builtins.  */
 401 enum nds32_builtins
 402 {
 403   NDS32_BUILTIN_ISYNC,
 404   NDS32_BUILTIN_ISB,
 405   NDS32_BUILTIN_DSB,
 406   NDS32_BUILTIN_MSYNC_ALL,
 407   NDS32_BUILTIN_MSYNC_STORE,
 408   NDS32_BUILTIN_MFSR,
 409   NDS32_BUILTIN_MFUSR,
 410   NDS32_BUILTIN_MTSR,
 411   NDS32_BUILTIN_MTSR_ISB,
 412   NDS32_BUILTIN_MTSR_DSB,
 413   NDS32_BUILTIN_MTUSR,
 414   NDS32_BUILTIN_SETGIE_EN,
 415   NDS32_BUILTIN_SETGIE_DIS,
 416   NDS32_BUILTIN_FMFCFG,
 417   NDS32_BUILTIN_FMFCSR,
 418   NDS32_BUILTIN_FMTCSR,
 419   NDS32_BUILTIN_FCPYNSS,
 420   NDS32_BUILTIN_FCPYSS,
 421   NDS32_BUILTIN_FCPYNSD,
 422   NDS32_BUILTIN_FCPYSD,
 423   NDS32_BUILTIN_ABS,
 424   NDS32_BUILTIN_AVE,
 425   NDS32_BUILTIN_BCLR,
 426   NDS32_BUILTIN_BSET,
 427   NDS32_BUILTIN_BTGL,
 428   NDS32_BUILTIN_BTST,
 429   NDS32_BUILTIN_CLIP,
 430   NDS32_BUILTIN_CLIPS,
 431   NDS32_BUILTIN_CLZ,
 432   NDS32_BUILTIN_CLO,
 433   NDS32_BUILTIN_MAX,
 434   NDS32_BUILTIN_MIN,
 435   NDS32_BUILTIN_PBSAD,
 436   NDS32_BUILTIN_PBSADA,
 437   NDS32_BUILTIN_BSE,
 438   NDS32_BUILTIN_BSP,
 439   NDS32_BUILTIN_FFB,
 440   NDS32_BUILTIN_FFMISM,
 441   NDS32_BUILTIN_FLMISM,
 442
 443   NDS32_BUILTIN_ROTR,
 444   NDS32_BUILTIN_SVA,
 445   NDS32_BUILTIN_SVS,
 446   NDS32_BUILTIN_WSBH,
 447   NDS32_BUILTIN_JR_ITOFF,
 448   NDS32_BUILTIN_JR_TOFF,
 449   NDS32_BUILTIN_JRAL_ITON,
 450   NDS32_BUILTIN_JRAL_TON,
 451   NDS32_BUILTIN_RET_ITOFF,
 452   NDS32_BUILTIN_RET_TOFF,
 453   NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
 454   NDS32_BUILTIN_STANDBY_WAKE_GRANT,
 455   NDS32_BUILTIN_STANDBY_WAKE_DONE,
 456   NDS32_BUILTIN_TEQZ,
 457   NDS32_BUILTIN_TNEZ,
 458   NDS32_BUILTIN_TRAP,
 459   NDS32_BUILTIN_SETEND_BIG,
 460   NDS32_BUILTIN_SETEND_LITTLE,
 461   NDS32_BUILTIN_SYSCALL,
 462   NDS32_BUILTIN_BREAK,
 463   NDS32_BUILTIN_NOP,
 464   NDS32_BUILTIN_SCHE_BARRIER,
 465   NDS32_BUILTIN_GET_CURRENT_SP,
 466   NDS32_BUILTIN_SET_CURRENT_SP,
 467   NDS32_BUILTIN_RETURN_ADDRESS,
 468   NDS32_BUILTIN_LLW,
 469   NDS32_BUILTIN_LWUP,
 470   NDS32_BUILTIN_LBUP,
 471   NDS32_BUILTIN_SCW,
 472   NDS32_BUILTIN_SWUP,
 473   NDS32_BUILTIN_SBUP,
 474   NDS32_BUILTIN_CCTL_VA_LCK,
 475   NDS32_BUILTIN_CCTL_IDX_WBINVAL,
 476   NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
 477   NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
 478   NDS32_BUILTIN_CCTL_IDX_READ,
 479   NDS32_BUILTIN_CCTL_IDX_WRITE,
 480   NDS32_BUILTIN_CCTL_L1D_INVALALL,
 481   NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
 482   NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
 483   NDS32_BUILTIN_DPREF_QW,
 484   NDS32_BUILTIN_DPREF_HW,
 485   NDS32_BUILTIN_DPREF_W,
 486   NDS32_BUILTIN_DPREF_DW,
 487   NDS32_BUILTIN_TLBOP_TRD,
 488   NDS32_BUILTIN_TLBOP_TWR,
 489   NDS32_BUILTIN_TLBOP_RWR,
 490   NDS32_BUILTIN_TLBOP_RWLK,
 491   NDS32_BUILTIN_TLBOP_UNLK,
 492   NDS32_BUILTIN_TLBOP_PB,
 493   NDS32_BUILTIN_TLBOP_INV,
 494   NDS32_BUILTIN_TLBOP_FLUA,
 495   NDS32_BUILTIN_UALOAD_HW,
 496   NDS32_BUILTIN_UALOAD_W,
 497   NDS32_BUILTIN_UALOAD_DW,
 498   NDS32_BUILTIN_UASTORE_HW,
 499   NDS32_BUILTIN_UASTORE_W,
 500   NDS32_BUILTIN_UASTORE_DW,
 501   NDS32_BUILTIN_GIE_DIS,
 502   NDS32_BUILTIN_GIE_EN,
 503   NDS32_BUILTIN_ENABLE_INT,
 504   NDS32_BUILTIN_DISABLE_INT,
 505   NDS32_BUILTIN_SET_PENDING_SWINT,
 506   NDS32_BUILTIN_CLR_PENDING_SWINT,
 507   NDS32_BUILTIN_CLR_PENDING_HWINT,
 508   NDS32_BUILTIN_GET_ALL_PENDING_INT,
 509   NDS32_BUILTIN_GET_PENDING_INT,
 510   NDS32_BUILTIN_SET_INT_PRIORITY,
 511   NDS32_BUILTIN_GET_INT_PRIORITY,
 512   NDS32_BUILTIN_SET_TRIG_LEVEL,
 513   NDS32_BUILTIN_SET_TRIG_EDGE,
 514   NDS32_BUILTIN_GET_TRIG_TYPE,
 515   NDS32_BUILTIN_COUNT
 516 };
 517
 518 /* ------------------------------------------------------------------------ */
 519
 520 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 521
 522 #define TARGET_ISA_V3 \
 523   (nds32_arch_option == ARCH_V3 \
 524    || nds32_arch_option == ARCH_V3F \
 525    || nds32_arch_option == ARCH_V3S)
 526 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 527
 528 #define TARGET_PIPELINE_N9 \
 529   (nds32_cpu_option == CPU_N9)
 530 #define TARGET_PIPELINE_SIMPLE \
 531   (nds32_cpu_option == CPU_SIMPLE)
 532
 533 #define TARGET_CMODEL_SMALL \
 534    (nds32_cmodel_option == CMODEL_SMALL)
 535 #define TARGET_CMODEL_MEDIUM \
 536    (nds32_cmodel_option == CMODEL_MEDIUM)
 537 #define TARGET_CMODEL_LARGE \
 538    (nds32_cmodel_option == CMODEL_LARGE)
 539
 540 /* When -mcmodel=small or -mcmodel=medium,
 541    compiler may generate gp-base instruction directly.  */
 542 #define TARGET_GP_DIRECT \
 543    (nds32_cmodel_option == CMODEL_SMALL\
 544     || nds32_cmodel_option == CMODEL_MEDIUM)
 545
 546 #define TARGET_MUL_SLOW \
 547   (nds32_mul_config == MUL_TYPE_SLOW)
 548
 549 /* Run-time Target Specification.  */
 550 #define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
 551 /* Use hardware floating point calling convention.  */
 552 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
 553
 554 /* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
 555    1 means  hard ABI and using full floating-point instruction,
 556    2 means hard ABI and only using single-precision floating-point
 557    instruction  */
 558 #if TARGET_ARCH_DEFAULT == 1
 559 #  define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 560 #  define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
 561 #  define TARGET_DEFAULT_FPU_FMA 0
 562 #else
 563 #  if TARGET_ARCH_DEFAULT == 2
 564 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 565 #    define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
 566 #    define TARGET_DEFAULT_FPU_FMA 0
 567 #  else
 568 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2
 569 #    define TARGET_DEFAULT_FPU_ISA 0
 570 #    define TARGET_DEFAULT_FPU_FMA 0
 571 #  endif
 572 #endif
 573
 574 #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
 575 /* ------------------------------------------------------------------------ */
 576 \f
 577 /* Controlling the Compilation Driver.  */
 578
 579 #define OPTION_DEFAULT_SPECS \
 580   {"arch", " %{!march=*:-march=%(VALUE)}" \
 581            " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 582            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
 583            " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
 584            " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 585            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
 586   {"cpu",  "%{!mcpu=*:-mcpu=%(VALUE)}" },   \
 587   {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
 588
 589 #define CC1_SPEC \
 590   ""
 591
 592 #define ASM_SPEC \
 593   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 594   " %{march=*:-march=%*}" \
 595   " %{mabi=*:-mabi=v%*}" \
 596   " %{mconfig-fpu=*:-mfpu-freg=%*}" \
 597   " %{mext-fpu-mac:-mmac}" \
 598   " %{mno-ext-fpu-mac:-mno-mac}" \
 599   " %{mext-fpu-sp:-mfpu-sp-ext}" \
 600   " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
 601   " %{mext-fpu-dp:-mfpu-dp-ext}" \
 602   " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}"
 603
 604 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 605 #define LINK_SPEC \
 606   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 607   " %{mrelax:--relax}"
 608
 609 #define LIB_SPEC \
 610   " -lc -lgloss"
 611
 612 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 613    by applying different crt stuff.  In the convention, crt0.o is the
 614    startup file without constructor/destructor;
 615    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 616    startup files with constructor/destructor.
 617    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 618    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 619    currently provided by GCC for nds32 target.
 620
 621    For nds32 target so far:
 622    If -mno-ctor-dtor, we are going to link
 623    "crt0.o [user objects]".
 624    If general cases, we are going to link
 625    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 626 #define STARTFILE_SPEC \
 627   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 628   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 629 #define ENDFILE_SPEC \
 630   " %{!mno-ctor-dtor:crtend1.o%s}"
 631
 632 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 633    configure gcc with --target=nds32be-* setting.
 634    Check gcc/config.gcc for more information.  */
 635 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 636 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 637 #else
 638 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 639 #endif
 640
 641 /* Currently we only have elf toolchain,
 642    where -mcmodel=medium is always the default.  */
 643 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 644
 645 #define MULTILIB_DEFAULTS \
 646   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 647
 648 \f
 649 /* Run-time Target Specification.  */
 650
 651 #define TARGET_CPU_CPP_BUILTINS() \
 652   nds32_cpu_cpp_builtins (pfile)
 653
 654 \f
 655 /* Defining Data Structures for Per-function Information.  */
 656
 657 /* This macro is called once per function,
 658    before generation of any RTL has begun.  */
 659 #define INIT_EXPANDERS  nds32_init_expanders ()
 660
 661 \f
 662 /* Storage Layout.  */
 663
 664 #define BITS_BIG_ENDIAN 0
 665
 666 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 667
 668 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 669
 670 #define UNITS_PER_WORD 4
 671
 672 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 673   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 674     {                                                                       \
 675       (m) = SImode;                                                         \
 676     }
 677
 678 #define PARM_BOUNDARY 32
 679
 680 #define STACK_BOUNDARY 64
 681
 682 #define FUNCTION_BOUNDARY \
 683   ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
 684
 685 #define BIGGEST_ALIGNMENT 64
 686
 687 #define EMPTY_FIELD_BOUNDARY 32
 688
 689 #define STRUCTURE_SIZE_BOUNDARY 8
 690
 691 #define STRICT_ALIGNMENT 1
 692
 693 #define PCC_BITFIELD_TYPE_MATTERS 1
 694
 695 \f
 696 /* Layout of Source Language Data Types.  */
 697
 698 #define INT_TYPE_SIZE           32
 699 #define SHORT_TYPE_SIZE         16
 700 #define LONG_TYPE_SIZE          32
 701 #define LONG_LONG_TYPE_SIZE     64
 702
 703 #define FLOAT_TYPE_SIZE         32
 704 #define DOUBLE_TYPE_SIZE        64
 705 #define LONG_DOUBLE_TYPE_SIZE   64
 706
 707 #define DEFAULT_SIGNED_CHAR 1
 708
 709 #define SIZE_TYPE "long unsigned int"
 710 #define PTRDIFF_TYPE "long int"
 711 #define WCHAR_TYPE "unsigned int"
 712 #define WCHAR_TYPE_SIZE 32
 713
 714 \f
 715 /* Register Usage.  */
 716
 717 /* Number of actual hardware registers.
 718    The hardware registers are assigned numbers for the compiler
 719    from 0 to just below FIRST_PSEUDO_REGISTER.
 720    All registers that the compiler knows about must be given numbers,
 721    even those that are not normally considered general registers.  */
 722 #define FIRST_PSEUDO_REGISTER 101
 723
 724 /* An initializer that says which registers are used for fixed
 725    purposes all throughout the compiled code and are therefore
 726    not available for general allocation.
 727
 728    $r28 : $fp
 729    $r29 : $gp
 730    $r30 : $lp
 731    $r31 : $sp
 732
 733    caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
 734    callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
 735
 736    reserved for assembler : $r15
 737    reserved for other use : $r24, $r25, $r26, $r27 */
 738 #define FIXED_REGISTERS \
 739 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 740       0,   0,   0,   0,   0,   0,   0,   0,     \
 741   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 742       0,   0,   0,   0,   0,   0,   0,   1,     \
 743   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 744       0,   0,   0,   0,   0,   0,   0,   0,     \
 745   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 746       1,   1,   1,   1,   0,   1,   0,   1,     \
 747   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
 748       1,   1,   1,   1,   1,   1,   1,   1,     \
 749   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
 750       1,   1,   1,   1,   1,   1,   1,   1,     \
 751   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
 752       1,   1,   1,   1,   1,   1,   1,   1,     \
 753   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
 754       1,   1,   1,   1,   1,   1,   1,   1,     \
 755   /* fs30 fs31 fd16      fd17      fd18      */ \
 756       1,   1,   1,   1,   1,   1,   1,   1,     \
 757   /* fd19      fd20      fd21      fd22      */ \
 758       1,   1,   1,   1,   1,   1,   1,   1,     \
 759   /* fd23      fd24      fd25      fd26      */ \
 760       1,   1,   1,   1,   1,   1,   1,   1,     \
 761   /* fd27      fd28      fd29      fd30      */ \
 762       1,   1,   1,   1,   1,   1,   1,   1,     \
 763   /* fd31      Reserved..................... */ \
 764       1,   1,   1,   1,   1                     \
 765 }
 766
 767 /* Identifies the registers that are not available for
 768    general allocation of values that must live across
 769    function calls -- so they are caller-save registers.
 770
 771    0 : callee-save registers
 772    1 : caller-save registers */
 773 #define CALL_USED_REGISTERS \
 774 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 775       1,   1,   1,   1,   1,   1,   0,   0,     \
 776   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 777       0,   0,   0,   0,   0,   0,   0,   1,     \
 778   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 779       1,   1,   1,   1,   1,   1,   1,   1,     \
 780   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 781       1,   1,   1,   1,   0,   1,   0,   1,     \
 782   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
 783       1,   1,   1,   1,   1,   1,   1,   1,     \
 784   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
 785       1,   1,   1,   1,   1,   1,   1,   1,     \
 786   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
 787       1,   1,   1,   1,   1,   1,   1,   1,     \
 788   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
 789       1,   1,   1,   1,   1,   1,   1,   1,     \
 790   /* fs30 fs31 fd16      fd17      fd18      */ \
 791       1,   1,   1,   1,   1,   1,   1,   1,     \
 792   /* fd19      fd20      fd21      fd22      */ \
 793       1,   1,   1,   1,   1,   1,   1,   1,     \
 794   /* fd23      fd24      fd25      fd26      */ \
 795       1,   1,   1,   1,   1,   1,   1,   1,     \
 796   /* fd27      fd28      fd29      fd30      */ \
 797       1,   1,   1,   1,   1,   1,   1,   1,     \
 798   /* fd31      Reserved..................... */ \
 799       1,   1,   1,   1,   1                     \
 800 }
 801
 802 /* In nds32 target, we have three levels of registers:
 803      LOW_COST_REGS    : $r0 ~ $r7
 804      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 805      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 806 #define REG_ALLOC_ORDER \
 807 {   0,   1,   2,   3,   4,   5,   6,   7, \
 808    16,  17,  18,  19,   9,  10,  11,  12, \
 809    13,  14,  8,   15,  20,  21,  22,  23, \
 810    24,  25,  26,  27,  28,  29,  30,  31, \
 811    32,  33,  34,  35,  36,  37,  38,  39, \
 812    40,  41,  42,  43,  44,  45,  46,  47, \
 813    48,  49,  50,  51,  52,  53,  54,  55, \
 814    56,  57,  58,  59,  60,  61,  62,  63, \
 815    64,  65,  66,  67,  68,  69,  70,  71, \
 816    72,  73,  74,  75,  76,  77,  78,  79, \
 817    80,  81,  82,  83,  84,  85,  86,  87, \
 818    88,  89,  90,  91,  92,  93,  94,  95, \
 819    96,  97,  98,  99, 100,                \
 820 }
 821
 822 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
 823    to be rearranged based on optimizing for speed or size.  */
 824 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
 825
 826 /* Tell IRA to use the order we define rather than messing it up with its
 827    own cost calculations.  */
 828 #define HONOR_REG_ALLOC_ORDER optimize_size
 829
 830 \f
 831 /* Register Classes.  */
 832
 833 /* In nds32 target, we have three levels of registers:
 834      Low cost regsiters    : $r0 ~ $r7
 835      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 836      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 837
 838    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 839    so that it provides more chance to use low cost registers.  */
 840 enum reg_class
 841 {
 842   NO_REGS,
 843   R5_REG,
 844   R8_REG,
 845   R15_TA_REG,
 846   STACK_REG,
 847   FRAME_POINTER_REG,
 848   LOW_REGS,
 849   MIDDLE_REGS,
 850   HIGH_REGS,
 851   GENERAL_REGS,
 852   FRAME_REGS,
 853   FP_REGS,
 854   ALL_REGS,
 855   LIM_REG_CLASSES
 856 };
 857
 858 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 859
 860 #define REG_CLASS_NAMES \
 861 {                       \
 862   "NO_REGS",            \
 863   "R5_REG",             \
 864   "R8_REG",             \
 865   "R15_TA_REG",         \
 866   "STACK_REG",          \
 867   "FRAME_POINTER_REG",  \
 868   "LOW_REGS",           \
 869   "MIDDLE_REGS",        \
 870   "HIGH_REGS",          \
 871   "GENERAL_REGS",       \
 872   "FRAME_REGS",         \
 873   "FP_REGS",            \
 874   "ALL_REGS"            \
 875 }
 876
 877 #define REG_CLASS_CONTENTS \
 878 { /* NO_REGS                                    */  \
 879   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 880   /* R5_REG              : 5                    */  \
 881   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 882   /* R8_REG              : 8                    */  \
 883   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 884   /* R15_TA_REG          : 15                   */  \
 885   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 886   /* STACK_REG           : 31                   */  \
 887   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 888   /* FRAME_POINTER_REG   : 28                   */  \
 889   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 890   /* LOW_REGS            : 0-7                  */  \
 891   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 892   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 893   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 894   /* HIGH_REGS           : 12-14, 20-31         */  \
 895   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 896   /* GENERAL_REGS        : 0-31                 */  \
 897   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 898   /* FRAME_REGS          : 32, 33               */  \
 899   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 900   /* FP_REGS             : 34-98                */  \
 901   {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
 902   /* ALL_REGS            : 0-100                */  \
 903   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 904 }
 905
 906 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 907
 908 #define BASE_REG_CLASS GENERAL_REGS
 909 #define INDEX_REG_CLASS GENERAL_REGS
 910
 911 #define TEST_REGNO(R, TEST, VALUE) \
 912   ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
 913
 914 /* Return nonzero if it is suitable for use as a
 915    base register in operand addresses.
 916    So far, we return nonzero only if "num" is a hard reg
 917    of the suitable class or a pseudo register which is
 918    allocated to a suitable hard reg.  */
 919 #define REGNO_OK_FOR_BASE_P(num) \
 920   (TEST_REGNO (num, <, 32) \
 921    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
 922    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
 923
 924 /* Return nonzero if it is suitable for use as a
 925    index register in operand addresses.
 926    So far, we return nonzero only if "num" is a hard reg
 927    of the suitable class or a pseudo register which is
 928    allocated to a suitable hard reg.
 929    The difference between an index register and a base register is that
 930    the index register may be scaled.  */
 931 #define REGNO_OK_FOR_INDEX_P(num) \
 932   (TEST_REGNO (num, <, 32) \
 933    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
 934    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
 935
 936 \f
 937 /* Obsolete Macros for Defining Constraints.  */
 938
 939 \f
 940 /* Stack Layout and Calling Conventions.  */
 941
 942 #define STACK_GROWS_DOWNWARD 1
 943
 944 #define FRAME_GROWS_DOWNWARD 1
 945
 946 #define STACK_POINTER_OFFSET 0
 947
 948 #define FIRST_PARM_OFFSET(fundecl) \
 949   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 950
 951 /* A C expression whose value is RTL representing the address in a stack frame
 952    where the pointer to the caller's frame is stored.  */
 953 #define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
 954   nds32_dynamic_chain_address (frameaddr)
 955
 956 #define RETURN_ADDR_RTX(count, frameaddr) \
 957   nds32_return_addr_rtx (count, frameaddr)
 958
 959 /* A C expression whose value is RTL representing the location
 960    of the incoming return address at the beginning of any function
 961    before the prologue.
 962    If this RTL is REG, you should also define
 963    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 964 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 965 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 966
 967 /* Use $r0 $r1 to pass exception handling information.  */
 968 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
 969 /* The register $r2 that represents a location in which to store a stack
 970    adjustment to be applied before function return.
 971    This is used to unwind the stack to an exception handler's call frame.  */
 972 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
 973
 974 #define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
 975
 976 #define STACK_POINTER_REGNUM SP_REGNUM
 977
 978 #define FRAME_POINTER_REGNUM 33
 979
 980 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 981
 982 #define ARG_POINTER_REGNUM 32
 983
 984 #define STATIC_CHAIN_REGNUM 16
 985
 986 #define ELIMINABLE_REGS                                \
 987 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 988   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 989   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 990   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 991
 992 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 993   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 994
 995 #define ACCUMULATE_OUTGOING_ARGS 1
 996
 997 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 998
 999 #define CUMULATIVE_ARGS nds32_cumulative_args
1000
1001 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
1002   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
1003
1004 #define FUNCTION_ARG_REGNO_P(regno)                                           \
1005  (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
1006   || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)                                \
1007       && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM,                       \
1008                    NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
1009
1010 #define DEFAULT_PCC_STRUCT_RETURN 0
1011
1012 /* EXIT_IGNORE_STACK should be nonzero if, when returning
1013    from a function, the stack pointer does not matter.
1014    The value is tested only in functions that have frame pointers.
1015    In nds32 target, the function epilogue recovers the
1016    stack pointer from the frame.  */
1017 #define EXIT_IGNORE_STACK 1
1018
1019 #define FUNCTION_PROFILER(file, labelno) \
1020   fprintf (file, "/* profiler %d */\n", (labelno))
1021
1022 #define PROFILE_HOOK(LABEL)                                             \
1023   {                                                                     \
1024     rtx fun, lp;                                                        \
1025     lp = get_hard_reg_initial_val (Pmode, LP_REGNUM);                   \
1026     fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount");                        \
1027     emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode);           \
1028   }
1029
1030 \f
1031 /* Implementing the Varargs Macros.  */
1032
1033 \f
1034 /* Trampolines for Nested Functions.  */
1035
1036 /* Giving A-function and B-function,
1037    if B-function wants to call A-function's nested function,
1038    we need to fill trampoline code into A-function's stack
1039    so that B-function can execute the code in stack to indirectly
1040    jump to (like 'trampoline' action) desired nested function.
1041
1042    The trampoline code for nds32 target must contains following parts:
1043
1044      1. instructions (4 * 4 = 16 bytes):
1045           get $pc first
1046           load chain_value to static chain register via $pc
1047           load nested function address to $r15 via $pc
1048           jump to desired nested function via $r15
1049      2. data (4 * 2 = 8 bytes):
1050           chain_value
1051           nested function address
1052
1053    Please check nds32.c implementation for more information.  */
1054 #define TRAMPOLINE_SIZE 24
1055
1056 /* Because all instructions/data in trampoline template are 4-byte size,
1057    we set trampoline alignment 8*4=32 bits.  */
1058 #define TRAMPOLINE_ALIGNMENT 32
1059
1060 \f
1061 /* Implicit Calls to Library Routines.  */
1062
1063 \f
1064 /* Addressing Modes.  */
1065
1066 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
1067 #define HAVE_POST_INCREMENT 1
1068 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
1069 #define HAVE_POST_DECREMENT 1
1070
1071 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
1072 #define HAVE_POST_MODIFY_DISP 1
1073 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
1074 #define HAVE_POST_MODIFY_REG  1
1075
1076 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1077
1078 #define MAX_REGS_PER_ADDRESS 3
1079
1080 \f
1081 /* Anchored Addresses.  */
1082
1083 \f
1084 /* Condition Code Status.  */
1085
1086 \f
1087 /* Describing Relative Costs of Operations.  */
1088
1089 /* A C expression for the cost of a branch instruction.
1090    A value of 1 is the default;
1091    other values are interpreted relative to that.  */
1092 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
1093
1094 /* Override BRANCH_COST heuristic which empirically produces worse
1095    performance for removing short circuiting from the logical ops.  */
1096 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1097
1098 #define SLOW_BYTE_ACCESS 1
1099
1100 #define NO_FUNCTION_CSE 1
1101
1102 \f
1103 /* Adjusting the Instruction Scheduler.  */
1104
1105 \f
1106 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
1107
1108 #define TEXT_SECTION_ASM_OP     "\t.text"
1109 #define DATA_SECTION_ASM_OP     "\t.data"
1110
1111 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1112    So we use '.section .bss' alternatively.  */
1113 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
1114
1115 /* Define this macro to be an expression with a nonzero value if jump tables
1116    (for tablejump insns) should be output in the text section,
1117    along with the assembler instructions.
1118    Otherwise, the readonly data section is used.  */
1119 #define JUMP_TABLES_IN_TEXT_SECTION 1
1120
1121 \f
1122 /* Position Independent Code.  */
1123
1124 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1125
1126 \f
1127 /* Defining the Output Assembler Language.  */
1128
1129 #define ASM_COMMENT_START "!"
1130
1131 #define ASM_APP_ON "! #APP"
1132
1133 #define ASM_APP_OFF "! #NO_APP\n"
1134
1135 #define ASM_OUTPUT_LABELREF(stream, name) \
1136   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1137
1138 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1139   assemble_name (stream, XSTR (sym, 0))
1140
1141 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
1142   assemble_name (stream, buf)
1143
1144 #define LOCAL_LABEL_PREFIX "."
1145
1146 #define REGISTER_NAMES \
1147 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
1148   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
1149   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1150   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
1151   "$AP",  "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1152   "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1153   "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1154   "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1155   "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1156   "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1157   "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1158   "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1159   "$fs62","$fs63",   "LB",   "LE",   "LC"                         \
1160 }
1161
1162 #define ADDITIONAL_REGISTER_NAMES                               \
1163 {                                                               \
1164   {"$r15", 15},                                                 \
1165   {"$r28", 28}, {"$r29", 29},   {"$r30", 30},   {"$r31", 31},   \
1166   {"$a0", 0},   {"$a1", 1},     {"$a2", 2},                     \
1167   {"$a3", 3},   {"$a4", 4},     {"$a5", 5},                     \
1168   {"$s0", 6},   {"$s1", 7},     {"$s2", 8},     {"$s3", 9},     \
1169   {"$s4", 10},  {"$s5", 11},    {"$s6", 12},    {"$s7", 13},    \
1170   {"$s8", 14},                                                  \
1171   {"$t0", 16},  {"$t1", 17},    {"$t2", 18},    {"$t3", 19},    \
1172   {"$t4", 20},  {"$t5", 21},    {"$t6", 22},    {"$t7", 23},    \
1173   {"$t8", 24},  {"$t9", 25},                                    \
1174   {"$p0", 26},  {"$p1", 27},                                    \
1175   {"$h0", 0},   {"$h1", 1},     {"$h2", 2},     {"$h3", 3},     \
1176   {"$h4", 4},   {"$h5", 5},     {"$h6", 6},     {"$h7", 7},     \
1177   {"$h8", 8},   {"$h9", 9},     {"$h10", 10},   {"$h11", 11},   \
1178   {"$h12", 16}, {"$h13", 17},   {"$h14", 18},   {"$h15", 19},   \
1179   {"$o0", 0},   {"$o1", 1},     {"$o2", 2},     {"$o3", 3},     \
1180   {"$o4", 4},   {"$o5", 5},     {"$o6", 6},     {"$o7", 7},     \
1181 }
1182
1183 #define OVERLAPPING_REGISTER_NAMES              \
1184 {                                               \
1185   {"$fd0",  NDS32_FIRST_FPR_REGNUM + 0,  2},    \
1186   {"$fd1",  NDS32_FIRST_FPR_REGNUM + 2,  2},    \
1187   {"$fd2",  NDS32_FIRST_FPR_REGNUM + 4,  2},    \
1188   {"$fd3",  NDS32_FIRST_FPR_REGNUM + 6,  2},    \
1189   {"$fd4",  NDS32_FIRST_FPR_REGNUM + 8,  2},    \
1190   {"$fd5",  NDS32_FIRST_FPR_REGNUM + 10, 2},    \
1191   {"$fd6",  NDS32_FIRST_FPR_REGNUM + 12, 2},    \
1192   {"$fd7",  NDS32_FIRST_FPR_REGNUM + 14, 2},    \
1193   {"$fd8",  NDS32_FIRST_FPR_REGNUM + 16, 2},    \
1194   {"$fd9",  NDS32_FIRST_FPR_REGNUM + 18, 2},    \
1195   {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2},    \
1196   {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2},    \
1197   {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2},    \
1198   {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2},    \
1199   {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2},    \
1200   {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2},    \
1201   {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2},    \
1202   {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2},    \
1203   {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2},    \
1204   {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2},    \
1205   {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2},    \
1206   {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2},    \
1207   {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2},    \
1208   {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2},    \
1209   {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2},    \
1210   {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2},    \
1211   {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2},    \
1212   {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2},    \
1213   {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2},    \
1214   {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2},    \
1215   {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2},    \
1216   {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2},    \
1217 }
1218
1219 /* Output normal jump table entry.  */
1220 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1221   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1222
1223 /* Output pc relative jump table entry.  */
1224 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
1225   do                                                                    \
1226     {                                                                   \
1227       switch (GET_MODE (body))                                          \
1228         {                                                               \
1229         case E_QImode:                                                    \
1230           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
1231           break;                                                        \
1232         case E_HImode:                                                    \
1233           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
1234           break;                                                        \
1235         case E_SImode:                                                    \
1236           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
1237           break;                                                        \
1238         default:                                                        \
1239           gcc_unreachable();                                            \
1240         }                                                               \
1241     } while (0)
1242
1243 /* We have to undef it first because elfos.h formerly define it
1244    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
1245 #undef  ASM_OUTPUT_CASE_LABEL
1246 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
1247   do                                                               \
1248     {                                                              \
1249       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
1250       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
1251     } while (0)
1252
1253 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
1254   do                                                   \
1255     {                                                  \
1256       /* Because our jump table is in text section,    \
1257          we need to make sure 2-byte alignment after   \
1258          the jump table for instructions fetch.  */    \
1259       if (GET_MODE (PATTERN (table)) == QImode)        \
1260         ASM_OUTPUT_ALIGN (stream, 1);                  \
1261       asm_fprintf (stream, "\t! Jump Table End\n");    \
1262     }  while (0)
1263
1264 /* This macro is not documented yet.
1265    But we do need it to make jump table vector aligned.  */
1266 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
1267
1268 #define DWARF2_UNWIND_INFO 1
1269
1270 #define JUMP_ALIGN(x) \
1271   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1272
1273 #define LOOP_ALIGN(x) \
1274   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1275
1276 #define LABEL_ALIGN(x) \
1277   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1278
1279 #define ASM_OUTPUT_ALIGN(stream, power) \
1280   fprintf (stream, "\t.align\t%d\n", power)
1281
1282 \f
1283 /* Controlling Debugging Information Format.  */
1284
1285 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1286
1287 #define DWARF2_DEBUGGING_INFO 1
1288
1289 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1290
1291 \f
1292 /* Cross Compilation and Floating Point.  */
1293
1294 \f
1295 /* Mode Switching Instructions.  */
1296
1297 \f
1298 /* Defining target-specific uses of __attribute__.  */
1299
1300 \f
1301 /* Emulating TLS.  */
1302
1303 \f
1304 /* Defining coprocessor specifics for MIPS targets.  */
1305
1306 \f
1307 /* Parameters for Precompiled Header Validity Checking.  */
1308
1309 \f
1310 /* C++ ABI parameters.  */
1311
1312 \f
1313 /* Adding support for named address spaces.  */
1314
1315 \f
1316 /* Miscellaneous Parameters.  */
1317
1318 /* This is the machine mode that elements of a jump-table should have.  */
1319 #define CASE_VECTOR_MODE Pmode
1320
1321 /* Return the preferred mode for and addr_diff_vec when the mininum
1322    and maximum offset are known.  */
1323 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1324    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1325    : (max_offset >= 100) ? HImode                               \
1326    : QImode)
1327
1328 /* Generate pc relative jump table when -fpic or -Os.  */
1329 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1330
1331 /* Define this macro if operations between registers with integral mode
1332    smaller than a word are always performed on the entire register.  */
1333 #define WORD_REGISTER_OPERATIONS 1
1334
1335 /* A C expression indicating when insns that read memory in mem_mode,
1336    an integral mode narrower than a word, set the bits outside of mem_mode
1337    to be either the sign-extension or the zero-extension of the data read.  */
1338 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1339
1340 /* The maximum number of bytes that a single instruction can move quickly
1341    between memory and registers or between two memory locations.  */
1342 #define MOVE_MAX 4
1343
1344 /* A C expression that is nonzero if on this machine the number of bits
1345    actually used for the count of a shift operation is equal to the number
1346    of bits needed to represent the size of the object being shifted.  */
1347 #define SHIFT_COUNT_TRUNCATED 1
1348
1349 /* A C expression describing the value returned by a comparison operator with
1350    an integral mode and stored by a store-flag instruction ('cstoremode4')
1351    when the condition is true.  */
1352 #define STORE_FLAG_VALUE 1
1353
1354 /* A C expression that indicates whether the architecture defines a value for
1355    clz or ctz with a zero operand.  In nds32 clz for 0 result 32 is defined
1356    in ISA spec */
1357 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
1358
1359 /* An alias for the machine mode for pointers.  */
1360 #define Pmode SImode
1361
1362 /* An alias for the machine mode used for memory references to functions
1363    being called, in call RTL expressions.  */
1364 #define FUNCTION_MODE SImode
1365
1366 /* ------------------------------------------------------------------------ */