1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
596 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
597 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
601 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
604 dump_value_slim (lra_dump_file
, original
, 1);
606 if (new_class
!= lra_get_allocno_class (regno
))
607 lra_change_class (regno
, new_class
, ", change to", false);
608 if (lra_dump_file
!= NULL
)
609 fprintf (lra_dump_file
, "\n");
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original
)
615 && REG_P (curr_insn_input_reloads
[i
].input
)
616 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
617 && (GET_MODE (original
)
618 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
621 *result_reg
= (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
624 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
625 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
633 /* The page contains code to extract memory address parts. */
635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 ok_for_index_p_nonstrict (rtx reg
)
639 unsigned regno
= REGNO (reg
);
641 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
644 /* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
647 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
648 enum rtx_code outer_code
, enum rtx_code index_code
)
650 unsigned regno
= REGNO (reg
);
652 if (regno
>= FIRST_PSEUDO_REGISTER
)
654 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
659 /* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
662 /* Return the offset from REGNO of the least significant register
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 lra_constraint_offset (int regno
, machine_mode mode
)
673 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
675 scalar_int_mode int_mode
;
677 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
678 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
679 return hard_regno_nregs (regno
, mode
) - 1;
683 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
684 if they are the same hard reg, and has special hacks for
685 auto-increment and auto-decrement. This is specifically intended for
686 process_alt_operands to use in determining whether two operands
687 match. X is the operand whose number is the lower of the two.
689 It is supposed that X is the output operand and Y is the input
690 operand. Y_HARD_REGNO is the final hard regno of register Y or
691 register in subreg Y as we know it now. Otherwise, it is a
694 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
697 RTX_CODE code
= GET_CODE (x
);
702 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
703 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
707 i
= get_hard_regno (x
, false);
711 if ((j
= y_hard_regno
) < 0)
714 i
+= lra_constraint_offset (i
, GET_MODE (x
));
715 j
+= lra_constraint_offset (j
, GET_MODE (y
));
720 /* If two operands must match, because they are really a single
721 operand of an assembler insn, then two post-increments are invalid
722 because the assembler insn would increment only once. On the
723 other hand, a post-increment matches ordinary indexing if the
724 post-increment is the output operand. */
725 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
726 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
728 /* Two pre-increments are invalid because the assembler insn would
729 increment only once. On the other hand, a pre-increment matches
730 ordinary indexing if the pre-increment is the input operand. */
731 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
732 || GET_CODE (y
) == PRE_MODIFY
)
733 return operands_match_p (x
, XEXP (y
, 0), -1);
737 if (code
== REG
&& REG_P (y
))
738 return REGNO (x
) == REGNO (y
);
740 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
741 && x
== SUBREG_REG (y
))
743 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
744 && SUBREG_REG (x
) == y
)
747 /* Now we have disposed of all the cases in which different rtx
749 if (code
!= GET_CODE (y
))
752 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
753 if (GET_MODE (x
) != GET_MODE (y
))
762 return label_ref_label (x
) == label_ref_label (y
);
764 return XSTR (x
, 0) == XSTR (y
, 0);
770 /* Compare the elements. If any pair of corresponding elements fail
771 to match, return false for the whole things. */
773 fmt
= GET_RTX_FORMAT (code
);
774 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
780 if (XWINT (x
, i
) != XWINT (y
, i
))
785 if (XINT (x
, i
) != XINT (y
, i
))
790 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
799 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
801 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
803 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
809 /* It is believed that rtx's at this level will never
810 contain anything but integers and other rtx's, except for
811 within LABEL_REFs and SYMBOL_REFs. */
819 /* True if X is a constant that can be forced into the constant pool.
820 MODE is the mode of the operand, or VOIDmode if not known. */
821 #define CONST_POOL_OK_P(MODE, X) \
822 ((MODE) != VOIDmode \
824 && GET_CODE (X) != HIGH \
825 && !targetm.cannot_force_const_mem (MODE, X))
827 /* True if C is a non-empty register class that has too few registers
828 to be safely used as a reload target class. */
829 #define SMALL_REGISTER_CLASS_P(C) \
830 (ira_class_hard_regs_num [(C)] == 1 \
831 || (ira_class_hard_regs_num [(C)] >= 1 \
832 && targetm.class_likely_spilled_p (C)))
834 /* If REG is a reload pseudo, try to make its class satisfying CL. */
836 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
838 enum reg_class rclass
;
840 /* Do not make more accurate class from reloads generated. They are
841 mostly moves with a lot of constraints. Making more accurate
842 class may results in very narrow class and impossibility of find
843 registers for several reloads of one insn. */
844 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
846 if (GET_CODE (reg
) == SUBREG
)
847 reg
= SUBREG_REG (reg
);
848 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
850 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
851 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
854 /* Searches X for any reference to a reg with the same value as REGNO,
855 returning the rtx of the reference found if any. Otherwise,
858 regno_val_use_in (unsigned int regno
, rtx x
)
864 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
867 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
868 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
872 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
875 else if (fmt
[i
] == 'E')
876 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
877 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
884 /* Return true if all current insn non-output operands except INS (it
885 has a negaitve end marker) do not use pseudos with the same value
888 check_conflict_input_operands (int regno
, signed char *ins
)
891 int n_operands
= curr_static_id
->n_operands
;
893 for (int nop
= 0; nop
< n_operands
; nop
++)
894 if (! curr_static_id
->operand
[nop
].is_operator
895 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
897 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
901 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
907 /* Generate reloads for matching OUT and INS (array of input operand
908 numbers with end marker -1) with reg class GOAL_CLASS, considering
909 output operands OUTS (similar array to INS) needing to be in different
910 registers. Add input and output reloads correspondingly to the lists
911 *BEFORE and *AFTER. OUT might be negative. In this case we generate
912 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
913 that the output operand is early clobbered for chosen alternative. */
915 match_reload (signed char out
, signed char *ins
, signed char *outs
,
916 enum reg_class goal_class
, rtx_insn
**before
,
917 rtx_insn
**after
, bool early_clobber_p
)
921 rtx new_in_reg
, new_out_reg
, reg
;
922 machine_mode inmode
, outmode
;
923 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
924 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
926 inmode
= curr_operand_mode
[ins
[0]];
927 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
928 push_to_sequence (*before
);
929 if (inmode
!= outmode
)
931 if (partial_subreg_p (outmode
, inmode
))
934 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
936 if (SCALAR_INT_MODE_P (inmode
))
937 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
939 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
940 LRA_SUBREG_P (new_out_reg
) = 1;
941 /* If the input reg is dying here, we can use the same hard
942 register for REG and IN_RTX. We do it only for original
943 pseudos as reload pseudos can die although original
944 pseudos still live where reload pseudos dies. */
945 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
946 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
948 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
949 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
954 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
956 if (SCALAR_INT_MODE_P (outmode
))
957 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
959 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
960 /* NEW_IN_REG is non-paradoxical subreg. We don't want
961 NEW_OUT_REG living above. We add clobber clause for
962 this. This is just a temporary clobber. We can remove
963 it at the end of LRA work. */
964 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
965 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
966 LRA_SUBREG_P (new_in_reg
) = 1;
967 if (GET_CODE (in_rtx
) == SUBREG
)
969 rtx subreg_reg
= SUBREG_REG (in_rtx
);
971 /* If SUBREG_REG is dying here and sub-registers IN_RTX
972 and NEW_IN_REG are similar, we can use the same hard
973 register for REG and SUBREG_REG. */
974 if (REG_P (subreg_reg
)
975 && (int) REGNO (subreg_reg
) < lra_new_regno_start
976 && GET_MODE (subreg_reg
) == outmode
977 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
978 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
979 && (! early_clobber_p
980 || check_conflict_input_operands (REGNO (subreg_reg
),
982 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
988 /* Pseudos have values -- see comments for lra_reg_info.
989 Different pseudos with the same value do not conflict even if
990 they live in the same place. When we create a pseudo we
991 assign value of original pseudo (if any) from which we
992 created the new pseudo. If we create the pseudo from the
993 input pseudo, the new pseudo will have no conflict with the
994 input pseudo which is wrong when the input pseudo lives after
995 the insn and as the new pseudo value is changed by the insn
996 output. Therefore we create the new pseudo from the output
997 except the case when we have single matched dying input
1000 We cannot reuse the current output register because we might
1001 have a situation like "a <- a op b", where the constraints
1002 force the second input operand ("b") to match the output
1003 operand ("a"). "b" must then be copied into a new register
1004 so that it doesn't clobber the current value of "a".
1006 We can not use the same value if the output pseudo is
1007 early clobbered or the input pseudo is mentioned in the
1008 output, e.g. as an address part in memory, because
1009 output reload will actually extend the pseudo liveness.
1010 We don't care about eliminable hard regs here as we are
1011 interesting only in pseudos. */
1013 /* Matching input's register value is the same as one of the other
1014 output operand. Output operands in a parallel insn must be in
1015 different registers. */
1016 out_conflict
= false;
1019 for (i
= 0; outs
[i
] >= 0; i
++)
1021 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1022 if (REG_P (other_out_rtx
)
1023 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1026 out_conflict
= true;
1032 new_in_reg
= new_out_reg
1033 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1034 && (int) REGNO (in_rtx
) < lra_new_regno_start
1035 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1036 && (! early_clobber_p
1037 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1039 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1041 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1042 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1045 /* In operand can be got from transformations before processing insn
1046 constraints. One example of such transformations is subreg
1047 reloading (see function simplify_operand_subreg). The new
1048 pseudos created by the transformations might have inaccurate
1049 class (ALL_REGS) and we should make their classes more
1051 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1052 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1053 *before
= get_insns ();
1055 /* Add the new pseudo to consider values of subsequent input reload
1057 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1058 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1059 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1060 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1061 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1064 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1065 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1066 *curr_id
->operand_loc
[in
] = new_in_reg
;
1068 lra_update_dups (curr_id
, ins
);
1071 /* See a comment for the input operand above. */
1072 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1073 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1076 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1078 *after
= get_insns ();
1081 *curr_id
->operand_loc
[out
] = new_out_reg
;
1082 lra_update_dup (curr_id
, out
);
1085 /* Return register class which is union of all reg classes in insn
1086 constraint alternative string starting with P. */
1087 static enum reg_class
1088 reg_class_from_constraints (const char *p
)
1091 enum reg_class op_class
= NO_REGS
;
1094 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1101 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1105 enum constraint_num cn
= lookup_constraint (p
);
1106 enum reg_class cl
= reg_class_for_constraint (cn
);
1109 if (insn_extra_address_constraint (cn
))
1111 = (reg_class_subunion
1112 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1113 ADDRESS
, SCRATCH
)]);
1117 op_class
= reg_class_subunion
[op_class
][cl
];
1120 while ((p
+= len
), c
);
1124 /* If OP is a register, return the class of the register as per
1125 get_reg_class, otherwise return NO_REGS. */
1126 static inline enum reg_class
1127 get_op_class (rtx op
)
1129 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1132 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1133 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1134 SUBREG for VAL to make them equal. */
1136 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1138 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1140 /* Usually size of mem_pseudo is greater than val size but in
1141 rare cases it can be less as it can be defined by target
1142 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1145 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1146 GET_CODE (val
) == SUBREG
1147 ? SUBREG_REG (val
) : val
);
1148 LRA_SUBREG_P (val
) = 1;
1152 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1153 LRA_SUBREG_P (mem_pseudo
) = 1;
1156 return to_p
? gen_move_insn (mem_pseudo
, val
)
1157 : gen_move_insn (val
, mem_pseudo
);
1160 /* Process a special case insn (register move), return true if we
1161 don't need to process it anymore. INSN should be a single set
1162 insn. Set up that RTL was changed through CHANGE_P and macro
1163 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1166 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1169 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1171 enum reg_class dclass
, sclass
, secondary_class
;
1172 secondary_reload_info sri
;
1174 lra_assert (curr_insn_set
!= NULL_RTX
);
1175 dreg
= dest
= SET_DEST (curr_insn_set
);
1176 sreg
= src
= SET_SRC (curr_insn_set
);
1177 if (GET_CODE (dest
) == SUBREG
)
1178 dreg
= SUBREG_REG (dest
);
1179 if (GET_CODE (src
) == SUBREG
)
1180 sreg
= SUBREG_REG (src
);
1181 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1183 sclass
= dclass
= NO_REGS
;
1185 dclass
= get_reg_class (REGNO (dreg
));
1186 gcc_assert (dclass
< LIM_REG_CLASSES
);
1187 if (dclass
== ALL_REGS
)
1188 /* ALL_REGS is used for new pseudos created by transformations
1189 like reload of SUBREG_REG (see function
1190 simplify_operand_subreg). We don't know their class yet. We
1191 should figure out the class from processing the insn
1192 constraints not in this fast path function. Even if ALL_REGS
1193 were a right class for the pseudo, secondary_... hooks usually
1194 are not define for ALL_REGS. */
1197 sclass
= get_reg_class (REGNO (sreg
));
1198 gcc_assert (sclass
< LIM_REG_CLASSES
);
1199 if (sclass
== ALL_REGS
)
1200 /* See comments above. */
1202 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1204 #ifdef SECONDARY_MEMORY_NEEDED
1205 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1206 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1208 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1214 if (! REG_P (dreg
) || ! REG_P (sreg
))
1216 sri
.prev_sri
= NULL
;
1217 sri
.icode
= CODE_FOR_nothing
;
1219 secondary_class
= NO_REGS
;
1220 /* Set up hard register for a reload pseudo for hook
1221 secondary_reload because some targets just ignore unassigned
1222 pseudos in the hook. */
1223 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1225 dregno
= REGNO (dreg
);
1226 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1230 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1232 sregno
= REGNO (sreg
);
1233 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1237 if (sclass
!= NO_REGS
)
1239 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1240 (reg_class_t
) sclass
,
1241 GET_MODE (src
), &sri
);
1242 if (sclass
== NO_REGS
1243 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1244 && dclass
!= NO_REGS
))
1246 enum reg_class old_sclass
= secondary_class
;
1247 secondary_reload_info old_sri
= sri
;
1249 sri
.prev_sri
= NULL
;
1250 sri
.icode
= CODE_FOR_nothing
;
1253 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1254 (reg_class_t
) dclass
,
1255 GET_MODE (src
), &sri
);
1256 /* Check the target hook consistency. */
1258 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1259 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1260 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1263 reg_renumber
[sregno
] = -1;
1265 reg_renumber
[dregno
] = -1;
1266 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1270 if (secondary_class
!= NO_REGS
)
1271 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1275 if (sri
.icode
== CODE_FOR_nothing
)
1276 lra_emit_move (new_reg
, src
);
1279 enum reg_class scratch_class
;
1281 scratch_class
= (reg_class_from_constraints
1282 (insn_data
[sri
.icode
].operand
[2].constraint
));
1283 scratch_reg
= (lra_create_new_reg_with_unique_value
1284 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1285 scratch_class
, "scratch"));
1286 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1289 before
= get_insns ();
1291 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1292 if (new_reg
!= NULL_RTX
)
1293 SET_SRC (curr_insn_set
) = new_reg
;
1296 if (lra_dump_file
!= NULL
)
1298 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1299 dump_insn_slim (lra_dump_file
, curr_insn
);
1301 lra_set_insn_deleted (curr_insn
);
1307 /* The following data describe the result of process_alt_operands.
1308 The data are used in curr_insn_transform to generate reloads. */
1310 /* The chosen reg classes which should be used for the corresponding
1312 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1313 /* True if the operand should be the same as another operand and that
1314 other operand does not need a reload. */
1315 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1316 /* True if the operand does not need a reload. */
1317 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1318 /* True if the operand can be offsetable memory. */
1319 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1320 /* The number of an operand to which given operand can be matched to. */
1321 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1322 /* The number of elements in the following array. */
1323 static int goal_alt_dont_inherit_ops_num
;
1324 /* Numbers of operands whose reload pseudos should not be inherited. */
1325 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1326 /* True if the insn commutative operands should be swapped. */
1327 static bool goal_alt_swapped
;
1328 /* The chosen insn alternative. */
1329 static int goal_alt_number
;
1331 /* True if the corresponding operand is the result of an equivalence
1333 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1335 /* The following five variables are used to choose the best insn
1336 alternative. They reflect final characteristics of the best
1339 /* Number of necessary reloads and overall cost reflecting the
1340 previous value and other unpleasantness of the best alternative. */
1341 static int best_losers
, best_overall
;
1342 /* Overall number hard registers used for reloads. For example, on
1343 some targets we need 2 general registers to reload DFmode and only
1344 one floating point register. */
1345 static int best_reload_nregs
;
1346 /* Overall number reflecting distances of previous reloading the same
1347 value. The distances are counted from the current BB start. It is
1348 used to improve inheritance chances. */
1349 static int best_reload_sum
;
1351 /* True if the current insn should have no correspondingly input or
1353 static bool no_input_reloads_p
, no_output_reloads_p
;
1355 /* True if we swapped the commutative operands in the current
1357 static int curr_swapped
;
1359 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1360 register of class CL. Add any input reloads to list BEFORE. AFTER
1361 is nonnull if *LOC is an automodified value; handle that case by
1362 adding the required output reloads to list AFTER. Return true if
1363 the RTL was changed.
1365 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1366 register. Return false if the address register is correct. */
1368 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1372 enum reg_class rclass
, new_class
;
1376 bool subreg_p
, before_p
= false;
1378 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1381 reg
= SUBREG_REG (*loc
);
1382 mode
= GET_MODE (reg
);
1384 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1385 between two registers with different classes, but there normally will
1386 be "mov" which transfers element of vector register into the general
1387 register, and this normally will be a subreg which should be reloaded
1388 as a whole. This is particularly likely to be triggered when
1389 -fno-split-wide-types specified. */
1391 || in_class_p (reg
, cl
, &new_class
)
1392 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1393 loc
= &SUBREG_REG (*loc
);
1397 mode
= GET_MODE (reg
);
1402 /* Always reload memory in an address even if the target supports
1404 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1409 regno
= REGNO (reg
);
1410 rclass
= get_reg_class (regno
);
1412 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1414 if (lra_dump_file
!= NULL
)
1416 fprintf (lra_dump_file
,
1417 "Changing pseudo %d in address of insn %u on equiv ",
1418 REGNO (reg
), INSN_UID (curr_insn
));
1419 dump_value_slim (lra_dump_file
, *loc
, 1);
1420 fprintf (lra_dump_file
, "\n");
1422 *loc
= copy_rtx (*loc
);
1424 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1429 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1430 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1433 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1437 lra_change_class (regno
, new_class
, " Change to", true);
1445 push_to_sequence (*before
);
1446 lra_emit_move (new_reg
, reg
);
1447 *before
= get_insns ();
1454 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1456 *after
= get_insns ();
1462 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1463 the insn to be inserted before curr insn. AFTER returns the
1464 the insn to be inserted after curr insn. ORIGREG and NEWREG
1465 are the original reg and new reg for reload. */
1467 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1472 push_to_sequence (*before
);
1473 lra_emit_move (newreg
, origreg
);
1474 *before
= get_insns ();
1480 lra_emit_move (origreg
, newreg
);
1482 *after
= get_insns ();
1487 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1488 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1490 /* Make reloads for subreg in operand NOP with internal subreg mode
1491 REG_MODE, add new reloads for further processing. Return true if
1492 any change was done. */
1494 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1497 rtx_insn
*before
, *after
;
1498 machine_mode mode
, innermode
;
1500 rtx operand
= *curr_id
->operand_loc
[nop
];
1501 enum reg_class regclass
;
1504 before
= after
= NULL
;
1506 if (GET_CODE (operand
) != SUBREG
)
1509 mode
= GET_MODE (operand
);
1510 reg
= SUBREG_REG (operand
);
1511 innermode
= GET_MODE (reg
);
1512 type
= curr_static_id
->operand
[nop
].type
;
1515 const bool addr_was_valid
1516 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1517 alter_subreg (curr_id
->operand_loc
[nop
], false);
1518 rtx subst
= *curr_id
->operand_loc
[nop
];
1519 lra_assert (MEM_P (subst
));
1522 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1523 MEM_ADDR_SPACE (subst
))
1524 || ((get_constraint_type (lookup_constraint
1525 (curr_static_id
->operand
[nop
].constraint
))
1526 != CT_SPECIAL_MEMORY
)
1527 /* We still can reload address and if the address is
1528 valid, we can remove subreg without reloading its
1530 && valid_address_p (GET_MODE (subst
),
1532 [ira_class_hard_regs
1533 [base_reg_class (GET_MODE (subst
),
1534 MEM_ADDR_SPACE (subst
),
1535 ADDRESS
, SCRATCH
)][0]],
1536 MEM_ADDR_SPACE (subst
))))
1538 /* If we change the address for a paradoxical subreg of memory, the
1539 new address might violate the necessary alignment or the access
1540 might be slow; take this into consideration. We need not worry
1541 about accesses beyond allocated memory for paradoxical memory
1542 subregs as we don't substitute such equiv memory (see processing
1543 equivalences in function lra_constraints) and because for spilled
1544 pseudos we allocate stack memory enough for the biggest
1545 corresponding paradoxical subreg.
1547 However, do not blindly simplify a (subreg (mem ...)) for
1548 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1549 data into a register when the inner is narrower than outer or
1550 missing important data from memory when the inner is wider than
1551 outer. This rule only applies to modes that are no wider than
1553 if (!(GET_MODE_PRECISION (mode
) != GET_MODE_PRECISION (innermode
)
1554 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1555 && GET_MODE_SIZE (innermode
) <= UNITS_PER_WORD
1556 && WORD_REGISTER_OPERATIONS
)
1557 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1558 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1559 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1560 && targetm
.slow_unaligned_access (innermode
,
1564 *curr_id
->operand_loc
[nop
] = operand
;
1566 /* But if the address was not valid, we cannot reload the MEM without
1567 reloading the address first. */
1568 if (!addr_was_valid
)
1569 process_address (nop
, false, &before
, &after
);
1571 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1572 enum reg_class rclass
1573 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1574 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1575 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1577 bool insert_before
, insert_after
;
1578 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1580 insert_before
= (type
!= OP_OUT
1581 || partial_subreg_p (mode
, innermode
));
1582 insert_after
= type
!= OP_IN
;
1583 insert_move_for_subreg (insert_before
? &before
: NULL
,
1584 insert_after
? &after
: NULL
,
1587 SUBREG_REG (operand
) = new_reg
;
1589 /* Convert to MODE. */
1592 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1593 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1594 rclass
, TRUE
, "slow mem", &new_reg
))
1596 bool insert_before
, insert_after
;
1597 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1599 insert_before
= type
!= OP_OUT
;
1600 insert_after
= type
!= OP_IN
;
1601 insert_move_for_subreg (insert_before
? &before
: NULL
,
1602 insert_after
? &after
: NULL
,
1605 *curr_id
->operand_loc
[nop
] = new_reg
;
1606 lra_process_new_insns (curr_insn
, before
, after
,
1607 "Inserting slow mem reload");
1611 /* If the address was valid and became invalid, prefer to reload
1612 the memory. Typical case is when the index scale should
1613 correspond the memory. */
1614 *curr_id
->operand_loc
[nop
] = operand
;
1615 /* Do not return false here as the MEM_P (reg) will be processed
1616 later in this function. */
1618 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1620 alter_subreg (curr_id
->operand_loc
[nop
], false);
1623 else if (CONSTANT_P (reg
))
1625 /* Try to simplify subreg of constant. It is usually result of
1626 equivalence substitution. */
1627 if (innermode
== VOIDmode
1628 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1629 innermode
= curr_static_id
->operand
[nop
].mode
;
1630 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1631 SUBREG_BYTE (operand
))) != NULL_RTX
)
1633 *curr_id
->operand_loc
[nop
] = new_reg
;
1637 /* Put constant into memory when we have mixed modes. It generates
1638 a better code in most cases as it does not need a secondary
1639 reload memory. It also prevents LRA looping when LRA is using
1640 secondary reload memory again and again. */
1641 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1642 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1644 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1645 alter_subreg (curr_id
->operand_loc
[nop
], false);
1648 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1649 if there may be a problem accessing OPERAND in the outer
1652 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1653 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1654 /* Don't reload paradoxical subregs because we could be looping
1655 having repeatedly final regno out of hard regs range. */
1656 && (hard_regno_nregs (hard_regno
, innermode
)
1657 >= hard_regno_nregs (hard_regno
, mode
))
1658 && simplify_subreg_regno (hard_regno
, innermode
,
1659 SUBREG_BYTE (operand
), mode
) < 0
1660 /* Don't reload subreg for matching reload. It is actually
1661 valid subreg in LRA. */
1662 && ! LRA_SUBREG_P (operand
))
1663 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1665 enum reg_class rclass
;
1668 /* There is a big probability that we will get the same class
1669 for the new pseudo and we will get the same insn which
1670 means infinite looping. So spill the new pseudo. */
1673 /* The class will be defined later in curr_insn_transform. */
1675 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1677 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1678 rclass
, TRUE
, "subreg reg", &new_reg
))
1680 bool insert_before
, insert_after
;
1681 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1683 insert_before
= (type
!= OP_OUT
1684 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1685 insert_after
= (type
!= OP_IN
);
1686 insert_move_for_subreg (insert_before
? &before
: NULL
,
1687 insert_after
? &after
: NULL
,
1690 SUBREG_REG (operand
) = new_reg
;
1691 lra_process_new_insns (curr_insn
, before
, after
,
1692 "Inserting subreg reload");
1695 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1696 IRA allocates hardreg to the inner pseudo reg according to its mode
1697 instead of the outermode, so the size of the hardreg may not be enough
1698 to contain the outermode operand, in that case we may need to insert
1699 reload for the reg. For the following two types of paradoxical subreg,
1700 we need to insert reload:
1701 1. If the op_type is OP_IN, and the hardreg could not be paired with
1702 other hardreg to contain the outermode operand
1703 (checked by in_hard_reg_set_p), we need to insert the reload.
1704 2. If the op_type is OP_OUT or OP_INOUT.
1706 Here is a paradoxical subreg example showing how the reload is generated:
1708 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1709 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1711 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1712 here, if reg107 is assigned to hardreg R15, because R15 is the last
1713 hardreg, compiler cannot find another hardreg to pair with R15 to
1714 contain TImode data. So we insert a TImode reload reg180 for it.
1715 After reload is inserted:
1717 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1718 (reg:DI 107 [ __comp ])) -1
1719 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1720 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1722 Two reload hard registers will be allocated to reg180 to save TImode data
1724 else if (REG_P (reg
)
1725 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1726 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1727 && (hard_regno_nregs (hard_regno
, innermode
)
1728 < hard_regno_nregs (hard_regno
, mode
))
1729 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1731 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1734 /* The class will be defined later in curr_insn_transform. */
1735 enum reg_class rclass
1736 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1738 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1739 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1742 bool insert_before
, insert_after
;
1744 PUT_MODE (new_reg
, mode
);
1745 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1746 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1748 insert_before
= (type
!= OP_OUT
);
1749 insert_after
= (type
!= OP_IN
);
1750 insert_move_for_subreg (insert_before
? &before
: NULL
,
1751 insert_after
? &after
: NULL
,
1754 SUBREG_REG (operand
) = new_reg
;
1755 lra_process_new_insns (curr_insn
, before
, after
,
1756 "Inserting paradoxical subreg reload");
1762 /* Return TRUE if X refers for a hard register from SET. */
1764 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1766 int i
, j
, x_hard_regno
;
1773 code
= GET_CODE (x
);
1774 mode
= GET_MODE (x
);
1778 code
= GET_CODE (x
);
1779 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1780 mode
= GET_MODE (x
);
1785 x_hard_regno
= get_hard_regno (x
, true);
1786 return (x_hard_regno
>= 0
1787 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1791 struct address_info ad
;
1793 decompose_mem_address (&ad
, x
);
1794 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1796 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1799 fmt
= GET_RTX_FORMAT (code
);
1800 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1804 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1807 else if (fmt
[i
] == 'E')
1809 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1810 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1817 /* Return true if OP is a spilled pseudo. */
1819 spilled_pseudo_p (rtx op
)
1822 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1825 /* Return true if X is a general constant. */
1827 general_constant_p (rtx x
)
1829 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1833 reg_in_class_p (rtx reg
, enum reg_class cl
)
1836 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1837 return in_class_p (reg
, cl
, NULL
);
1840 /* Return true if SET of RCLASS contains no hard regs which can be
1843 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1849 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1850 COPY_HARD_REG_SET (temp
, set
);
1851 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1852 return (hard_reg_set_subset_p
1853 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1857 /* Used to check validity info about small class input operands. It
1858 should be incremented at start of processing an insn
1860 static unsigned int curr_small_class_check
= 0;
1862 /* Update number of used inputs of class OP_CLASS for operand NOP.
1863 Return true if we have more such class operands than the number of
1866 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1868 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1869 static int small_class_input_nums
[LIM_REG_CLASSES
];
1871 if (SMALL_REGISTER_CLASS_P (op_class
)
1872 /* We are interesting in classes became small because of fixing
1873 some hard regs, e.g. by an user through GCC options. */
1874 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1876 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1877 || curr_static_id
->operand
[nop
].early_clobber
))
1879 if (small_class_check
[op_class
] == curr_small_class_check
)
1880 small_class_input_nums
[op_class
]++;
1883 small_class_check
[op_class
] = curr_small_class_check
;
1884 small_class_input_nums
[op_class
] = 1;
1886 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1892 /* Major function to choose the current insn alternative and what
1893 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1894 negative we should consider only this alternative. Return false if
1895 we can not choose the alternative or find how to reload the
1898 process_alt_operands (int only_alternative
)
1901 int nop
, overall
, nalt
;
1902 int n_alternatives
= curr_static_id
->n_alternatives
;
1903 int n_operands
= curr_static_id
->n_operands
;
1904 /* LOSERS counts the operands that don't fit this alternative and
1905 would require loading. */
1908 /* REJECT is a count of how undesirable this alternative says it is
1909 if any reloading is required. If the alternative matches exactly
1910 then REJECT is ignored, but otherwise it gets this much counted
1911 against it in addition to the reloading needed. */
1913 /* This is defined by '!' or '?' alternative constraint and added to
1914 reject. But in some cases it can be ignored. */
1917 /* The number of elements in the following array. */
1918 int early_clobbered_regs_num
;
1919 /* Numbers of operands which are early clobber registers. */
1920 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1921 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1922 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1923 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1924 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1925 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1926 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1927 /* The number of elements in the following array. */
1928 int curr_alt_dont_inherit_ops_num
;
1929 /* Numbers of operands whose reload pseudos should not be inherited. */
1930 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1932 /* The register when the operand is a subreg of register, otherwise the
1934 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1935 /* The register if the operand is a register or subreg of register,
1937 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1938 int hard_regno
[MAX_RECOG_OPERANDS
];
1939 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1940 int reload_nregs
, reload_sum
;
1944 /* Calculate some data common for all alternatives to speed up the
1946 for (nop
= 0; nop
< n_operands
; nop
++)
1950 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1951 /* The real hard regno of the operand after the allocation. */
1952 hard_regno
[nop
] = get_hard_regno (op
, true);
1954 operand_reg
[nop
] = reg
= op
;
1955 biggest_mode
[nop
] = GET_MODE (op
);
1956 if (GET_CODE (op
) == SUBREG
)
1958 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1959 if (GET_MODE_SIZE (biggest_mode
[nop
])
1960 < GET_MODE_SIZE (GET_MODE (reg
)))
1961 biggest_mode
[nop
] = GET_MODE (reg
);
1964 operand_reg
[nop
] = NULL_RTX
;
1965 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1966 || ((int) REGNO (reg
)
1967 == lra_get_elimination_hard_regno (REGNO (reg
))))
1968 no_subreg_reg_operand
[nop
] = reg
;
1970 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1971 /* Just use natural mode for elimination result. It should
1972 be enough for extra constraints hooks. */
1973 = regno_reg_rtx
[hard_regno
[nop
]];
1976 /* The constraints are made of several alternatives. Each operand's
1977 constraint looks like foo,bar,... with commas separating the
1978 alternatives. The first alternatives for all operands go
1979 together, the second alternatives go together, etc.
1981 First loop over alternatives. */
1982 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1983 if (only_alternative
>= 0)
1984 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1986 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1988 /* Loop over operands for one constraint alternative. */
1989 if (!TEST_BIT (preferred
, nalt
))
1992 curr_small_class_check
++;
1993 overall
= losers
= addr_losers
= 0;
1994 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
1995 for (nop
= 0; nop
< n_operands
; nop
++)
1997 int inc
= (curr_static_id
1998 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1999 if (lra_dump_file
!= NULL
&& inc
!= 0)
2000 fprintf (lra_dump_file
,
2001 " Staticly defined alt reject+=%d\n", inc
);
2002 static_reject
+= inc
;
2004 reject
+= static_reject
;
2005 early_clobbered_regs_num
= 0;
2007 for (nop
= 0; nop
< n_operands
; nop
++)
2011 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2012 bool win
, did_match
, offmemok
, early_clobber_p
;
2013 /* false => this operand can be reloaded somehow for this
2016 /* true => this operand can be reloaded if the alternative
2019 /* True if a constant forced into memory would be OK for
2022 enum reg_class this_alternative
, this_costly_alternative
;
2023 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2024 bool this_alternative_match_win
, this_alternative_win
;
2025 bool this_alternative_offmemok
;
2028 enum constraint_num cn
;
2030 opalt_num
= nalt
* n_operands
+ nop
;
2031 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2033 /* Fast track for no constraints at all. */
2034 curr_alt
[nop
] = NO_REGS
;
2035 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2036 curr_alt_win
[nop
] = true;
2037 curr_alt_match_win
[nop
] = false;
2038 curr_alt_offmemok
[nop
] = false;
2039 curr_alt_matches
[nop
] = -1;
2043 op
= no_subreg_reg_operand
[nop
];
2044 mode
= curr_operand_mode
[nop
];
2046 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2049 early_clobber_p
= false;
2050 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2052 this_costly_alternative
= this_alternative
= NO_REGS
;
2053 /* We update set of possible hard regs besides its class
2054 because reg class might be inaccurate. For example,
2055 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2056 is translated in HI_REGS because classes are merged by
2057 pairs and there is no accurate intermediate class. */
2058 CLEAR_HARD_REG_SET (this_alternative_set
);
2059 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2060 this_alternative_win
= false;
2061 this_alternative_match_win
= false;
2062 this_alternative_offmemok
= false;
2063 this_alternative_matches
= -1;
2065 /* An empty constraint should be excluded by the fast
2067 lra_assert (*p
!= 0 && *p
!= ',');
2070 /* Scan this alternative's specs for this operand; set WIN
2071 if the operand fits any letter in this alternative.
2072 Otherwise, clear BADOP if this operand could fit some
2073 letter after reloads, or set WINREG if this operand could
2074 fit after reloads provided the constraint allows some
2079 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2089 early_clobber_p
= true;
2093 op_reject
+= LRA_MAX_REJECT
;
2096 op_reject
+= LRA_LOSER_COST_FACTOR
;
2100 /* Ignore rest of this alternative. */
2104 case '0': case '1': case '2': case '3': case '4':
2105 case '5': case '6': case '7': case '8': case '9':
2110 m
= strtoul (p
, &end
, 10);
2113 lra_assert (nop
> m
);
2115 this_alternative_matches
= m
;
2116 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2117 /* We are supposed to match a previous operand.
2118 If we do, we win if that one did. If we do
2119 not, count both of the operands as losers.
2120 (This is too conservative, since most of the
2121 time only a single reload insn will be needed
2122 to make the two operands win. As a result,
2123 this alternative may be rejected when it is
2124 actually desirable.) */
2126 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2127 *curr_id
->operand_loc
[m
], m_hregno
))
2129 /* We should reject matching of an early
2130 clobber operand if the matching operand is
2131 not dying in the insn. */
2132 if (! curr_static_id
->operand
[m
].early_clobber
2133 || operand_reg
[nop
] == NULL_RTX
2134 || (find_regno_note (curr_insn
, REG_DEAD
,
2136 || REGNO (op
) == REGNO (operand_reg
[m
])))
2141 /* If we are matching a non-offsettable
2142 address where an offsettable address was
2143 expected, then we must reject this
2144 combination, because we can't reload
2146 if (curr_alt_offmemok
[m
]
2147 && MEM_P (*curr_id
->operand_loc
[m
])
2148 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2153 /* Operands don't match. Both operands must
2154 allow a reload register, otherwise we
2155 cannot make them match. */
2156 if (curr_alt
[m
] == NO_REGS
)
2158 /* Retroactively mark the operand we had to
2159 match as a loser, if it wasn't already and
2160 it wasn't matched to a register constraint
2161 (e.g it might be matched by memory). */
2163 && (operand_reg
[m
] == NULL_RTX
2164 || hard_regno
[m
] < 0))
2168 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2169 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2172 /* Prefer matching earlyclobber alternative as
2173 it results in less hard regs required for
2174 the insn than a non-matching earlyclobber
2176 if (curr_static_id
->operand
[m
].early_clobber
)
2178 if (lra_dump_file
!= NULL
)
2181 " %d Matching earlyclobber alt:"
2186 /* Otherwise we prefer no matching
2187 alternatives because it gives more freedom
2189 else if (operand_reg
[nop
] == NULL_RTX
2190 || (find_regno_note (curr_insn
, REG_DEAD
,
2191 REGNO (operand_reg
[nop
]))
2194 if (lra_dump_file
!= NULL
)
2197 " %d Matching alt: reject+=2\n",
2202 /* If we have to reload this operand and some
2203 previous operand also had to match the same
2204 thing as this operand, we don't know how to do
2206 if (!match_p
|| !curr_alt_win
[m
])
2208 for (i
= 0; i
< nop
; i
++)
2209 if (curr_alt_matches
[i
] == m
)
2217 /* This can be fixed with reloads if the operand
2218 we are supposed to match can be fixed with
2221 this_alternative
= curr_alt
[m
];
2222 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2223 winreg
= this_alternative
!= NO_REGS
;
2229 || general_constant_p (op
)
2230 || spilled_pseudo_p (op
))
2236 cn
= lookup_constraint (p
);
2237 switch (get_constraint_type (cn
))
2240 cl
= reg_class_for_constraint (cn
);
2246 if (CONST_INT_P (op
)
2247 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2253 && satisfies_memory_constraint_p (op
, cn
))
2255 else if (spilled_pseudo_p (op
))
2258 /* If we didn't already win, we can reload constants
2259 via force_const_mem or put the pseudo value into
2260 memory, or make other memory by reloading the
2261 address like for 'o'. */
2262 if (CONST_POOL_OK_P (mode
, op
)
2263 || MEM_P (op
) || REG_P (op
)
2264 /* We can restore the equiv insn by a
2266 || equiv_substition_p
[nop
])
2273 /* If we didn't already win, we can reload the address
2274 into a base register. */
2275 if (satisfies_address_constraint_p (op
, cn
))
2277 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2283 if (constraint_satisfied_p (op
, cn
))
2287 case CT_SPECIAL_MEMORY
:
2289 && satisfies_memory_constraint_p (op
, cn
))
2291 else if (spilled_pseudo_p (op
))
2298 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2299 IOR_HARD_REG_SET (this_alternative_set
,
2300 reg_class_contents
[cl
]);
2303 this_costly_alternative
2304 = reg_class_subunion
[this_costly_alternative
][cl
];
2305 IOR_HARD_REG_SET (this_costly_alternative_set
,
2306 reg_class_contents
[cl
]);
2308 if (mode
== BLKmode
)
2313 if (hard_regno
[nop
] >= 0
2314 && in_hard_reg_set_p (this_alternative_set
,
2315 mode
, hard_regno
[nop
]))
2317 else if (hard_regno
[nop
] < 0
2318 && in_class_p (op
, this_alternative
, NULL
))
2323 if (c
!= ' ' && c
!= '\t')
2324 costly_p
= c
== '*';
2326 while ((p
+= len
), c
);
2328 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2329 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2330 /* Record which operands fit this alternative. */
2333 this_alternative_win
= true;
2334 if (operand_reg
[nop
] != NULL_RTX
)
2336 if (hard_regno
[nop
] >= 0)
2338 if (in_hard_reg_set_p (this_costly_alternative_set
,
2339 mode
, hard_regno
[nop
]))
2341 if (lra_dump_file
!= NULL
)
2342 fprintf (lra_dump_file
,
2343 " %d Costly set: reject++\n",
2350 /* Prefer won reg to spilled pseudo under other
2351 equal conditions for possibe inheritance. */
2354 if (lra_dump_file
!= NULL
)
2357 " %d Non pseudo reload: reject++\n",
2361 if (in_class_p (operand_reg
[nop
],
2362 this_costly_alternative
, NULL
))
2364 if (lra_dump_file
!= NULL
)
2367 " %d Non pseudo costly reload:"
2373 /* We simulate the behavior of old reload here.
2374 Although scratches need hard registers and it
2375 might result in spilling other pseudos, no reload
2376 insns are generated for the scratches. So it
2377 might cost something but probably less than old
2378 reload pass believes. */
2381 if (lra_dump_file
!= NULL
)
2382 fprintf (lra_dump_file
,
2383 " %d Scratch win: reject+=2\n",
2390 this_alternative_match_win
= true;
2393 int const_to_mem
= 0;
2396 reject
+= op_reject
;
2397 /* Never do output reload of stack pointer. It makes
2398 impossible to do elimination when SP is changed in
2400 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2401 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2404 /* If this alternative asks for a specific reg class, see if there
2405 is at least one allocatable register in that class. */
2407 = (this_alternative
== NO_REGS
2408 || (hard_reg_set_subset_p
2409 (reg_class_contents
[this_alternative
],
2410 lra_no_alloc_regs
)));
2412 /* For asms, verify that the class for this alternative is possible
2413 for the mode that is specified. */
2414 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2417 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2418 if (targetm
.hard_regno_mode_ok (i
, mode
)
2419 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2422 if (i
== FIRST_PSEUDO_REGISTER
)
2426 /* If this operand accepts a register, and if the
2427 register class has at least one allocatable register,
2428 then this operand can be reloaded. */
2429 if (winreg
&& !no_regs_p
)
2434 if (lra_dump_file
!= NULL
)
2435 fprintf (lra_dump_file
,
2436 " alt=%d: Bad operand -- refuse\n",
2441 if (this_alternative
!= NO_REGS
)
2443 HARD_REG_SET available_regs
;
2445 COPY_HARD_REG_SET (available_regs
,
2446 reg_class_contents
[this_alternative
]);
2447 AND_COMPL_HARD_REG_SET
2449 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2450 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2451 if (hard_reg_set_empty_p (available_regs
))
2453 /* There are no hard regs holding a value of given
2457 this_alternative
= NO_REGS
;
2458 if (lra_dump_file
!= NULL
)
2459 fprintf (lra_dump_file
,
2460 " %d Using memory because of"
2461 " a bad mode: reject+=2\n",
2467 if (lra_dump_file
!= NULL
)
2468 fprintf (lra_dump_file
,
2469 " alt=%d: Wrong mode -- refuse\n",
2476 /* If not assigned pseudo has a class which a subset of
2477 required reg class, it is a less costly alternative
2478 as the pseudo still can get a hard reg of necessary
2480 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2481 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2482 && ira_class_subset_p
[this_alternative
][cl
])
2484 if (lra_dump_file
!= NULL
)
2487 " %d Super set class reg: reject-=3\n", nop
);
2491 this_alternative_offmemok
= offmemok
;
2492 if (this_costly_alternative
!= NO_REGS
)
2494 if (lra_dump_file
!= NULL
)
2495 fprintf (lra_dump_file
,
2496 " %d Costly loser: reject++\n", nop
);
2499 /* If the operand is dying, has a matching constraint,
2500 and satisfies constraints of the matched operand
2501 which failed to satisfy the own constraints, most probably
2502 the reload for this operand will be gone. */
2503 if (this_alternative_matches
>= 0
2504 && !curr_alt_win
[this_alternative_matches
]
2506 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2507 && (hard_regno
[nop
] >= 0
2508 ? in_hard_reg_set_p (this_alternative_set
,
2509 mode
, hard_regno
[nop
])
2510 : in_class_p (op
, this_alternative
, NULL
)))
2512 if (lra_dump_file
!= NULL
)
2515 " %d Dying matched operand reload: reject++\n",
2521 /* Strict_low_part requires to reload the register
2522 not the sub-register. In this case we should
2523 check that a final reload hard reg can hold the
2525 if (curr_static_id
->operand
[nop
].strict_low
2527 && hard_regno
[nop
] < 0
2528 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2529 && ira_class_hard_regs_num
[this_alternative
] > 0
2530 && (!targetm
.hard_regno_mode_ok
2531 (ira_class_hard_regs
[this_alternative
][0],
2532 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2534 if (lra_dump_file
!= NULL
)
2537 " alt=%d: Strict low subreg reload -- refuse\n",
2543 if (operand_reg
[nop
] != NULL_RTX
2544 /* Output operands and matched input operands are
2545 not inherited. The following conditions do not
2546 exactly describe the previous statement but they
2547 are pretty close. */
2548 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2549 && (this_alternative_matches
< 0
2550 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2552 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2556 /* The value of reload_sum has sense only if we
2557 process insns in their order. It happens only on
2558 the first constraints sub-pass when we do most of
2560 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2561 reload_sum
+= last_reload
- bb_reload_num
;
2563 /* If this is a constant that is reloaded into the
2564 desired class by copying it to memory first, count
2565 that as another reload. This is consistent with
2566 other code and is required to avoid choosing another
2567 alternative when the constant is moved into memory.
2568 Note that the test here is precisely the same as in
2569 the code below that calls force_const_mem. */
2570 if (CONST_POOL_OK_P (mode
, op
)
2571 && ((targetm
.preferred_reload_class
2572 (op
, this_alternative
) == NO_REGS
)
2573 || no_input_reloads_p
))
2580 /* Alternative loses if it requires a type of reload not
2581 permitted for this insn. We can always reload
2582 objects with a REG_UNUSED note. */
2583 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2584 && no_output_reloads_p
2585 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2586 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2587 && no_input_reloads_p
&& ! const_to_mem
)
2588 || (this_alternative_matches
>= 0
2589 && (no_input_reloads_p
2590 || (no_output_reloads_p
2591 && (curr_static_id
->operand
2592 [this_alternative_matches
].type
!= OP_IN
)
2593 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2594 no_subreg_reg_operand
2595 [this_alternative_matches
])))))
2597 if (lra_dump_file
!= NULL
)
2600 " alt=%d: No input/otput reload -- refuse\n",
2605 /* Alternative loses if it required class pseudo can not
2606 hold value of required mode. Such insns can be
2607 described by insn definitions with mode iterators. */
2608 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2609 && ! hard_reg_set_empty_p (this_alternative_set
)
2610 /* It is common practice for constraints to use a
2611 class which does not have actually enough regs to
2612 hold the value (e.g. x86 AREG for mode requiring
2613 more one general reg). Therefore we have 2
2614 conditions to check that the reload pseudo can
2615 not hold the mode value. */
2616 && (!targetm
.hard_regno_mode_ok
2617 (ira_class_hard_regs
[this_alternative
][0],
2618 GET_MODE (*curr_id
->operand_loc
[nop
])))
2619 /* The above condition is not enough as the first
2620 reg in ira_class_hard_regs can be not aligned for
2621 multi-words mode values. */
2622 && (prohibited_class_reg_set_mode_p
2623 (this_alternative
, this_alternative_set
,
2624 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2626 if (lra_dump_file
!= NULL
)
2627 fprintf (lra_dump_file
,
2628 " alt=%d: reload pseudo for op %d "
2629 " can not hold the mode value -- refuse\n",
2634 /* Check strong discouragement of reload of non-constant
2635 into class THIS_ALTERNATIVE. */
2636 if (! CONSTANT_P (op
) && ! no_regs_p
2637 && (targetm
.preferred_reload_class
2638 (op
, this_alternative
) == NO_REGS
2639 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2640 && (targetm
.preferred_output_reload_class
2641 (op
, this_alternative
) == NO_REGS
))))
2643 if (lra_dump_file
!= NULL
)
2644 fprintf (lra_dump_file
,
2645 " %d Non-prefered reload: reject+=%d\n",
2646 nop
, LRA_MAX_REJECT
);
2647 reject
+= LRA_MAX_REJECT
;
2650 if (! (MEM_P (op
) && offmemok
)
2651 && ! (const_to_mem
&& constmemok
))
2653 /* We prefer to reload pseudos over reloading other
2654 things, since such reloads may be able to be
2655 eliminated later. So bump REJECT in other cases.
2656 Don't do this in the case where we are forcing a
2657 constant into memory and it will then win since
2658 we don't want to have a different alternative
2660 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2662 if (lra_dump_file
!= NULL
)
2665 " %d Non-pseudo reload: reject+=2\n",
2672 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2674 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2676 if (lra_dump_file
!= NULL
)
2679 " %d Small class reload: reject+=%d\n",
2680 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2681 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2685 /* We are trying to spill pseudo into memory. It is
2686 usually more costly than moving to a hard register
2687 although it might takes the same number of
2690 Non-pseudo spill may happen also. Suppose a target allows both
2691 register and memory in the operand constraint alternatives,
2692 then it's typical that an eliminable register has a substition
2693 of "base + offset" which can either be reloaded by a simple
2694 "new_reg <= base + offset" which will match the register
2695 constraint, or a similar reg addition followed by further spill
2696 to and reload from memory which will match the memory
2697 constraint, but this memory spill will be much more costly
2700 Code below increases the reject for both pseudo and non-pseudo
2703 && !(MEM_P (op
) && offmemok
)
2704 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2706 if (lra_dump_file
!= NULL
)
2709 " %d Spill %spseudo into memory: reject+=3\n",
2710 nop
, REG_P (op
) ? "" : "Non-");
2712 if (VECTOR_MODE_P (mode
))
2714 /* Spilling vectors into memory is usually more
2715 costly as they contain big values. */
2716 if (lra_dump_file
!= NULL
)
2719 " %d Spill vector pseudo: reject+=2\n",
2725 /* When we use an operand requiring memory in given
2726 alternative, the insn should write *and* read the
2727 value to/from memory it is costly in comparison with
2728 an insn alternative which does not use memory
2729 (e.g. register or immediate operand). We exclude
2730 memory operand for such case as we can satisfy the
2731 memory constraints by reloading address. */
2732 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2734 if (lra_dump_file
!= NULL
)
2737 " Using memory insn operand %d: reject+=3\n",
2742 #ifdef SECONDARY_MEMORY_NEEDED
2743 /* If reload requires moving value through secondary
2744 memory, it will need one more insn at least. */
2745 if (this_alternative
!= NO_REGS
2746 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2747 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2748 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2750 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2751 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2755 /* Input reloads can be inherited more often than output
2756 reloads can be removed, so penalize output
2758 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2760 if (lra_dump_file
!= NULL
)
2763 " %d Non input pseudo reload: reject++\n",
2768 if (MEM_P (op
) && offmemok
)
2770 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2772 if (lra_dump_file
!= NULL
)
2775 " %d Input/Output reload: reject+=%d\n",
2776 nop
, LRA_LOSER_COST_FACTOR
);
2777 reject
+= LRA_LOSER_COST_FACTOR
;
2781 if (early_clobber_p
&& ! scratch_p
)
2783 if (lra_dump_file
!= NULL
)
2784 fprintf (lra_dump_file
,
2785 " %d Early clobber: reject++\n", nop
);
2788 /* ??? We check early clobbers after processing all operands
2789 (see loop below) and there we update the costs more.
2790 Should we update the cost (may be approximately) here
2791 because of early clobber register reloads or it is a rare
2792 or non-important thing to be worth to do it. */
2793 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2794 - (addr_losers
== losers
? static_reject
: 0));
2795 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2797 if (lra_dump_file
!= NULL
)
2798 fprintf (lra_dump_file
,
2799 " alt=%d,overall=%d,losers=%d -- refuse\n",
2800 nalt
, overall
, losers
);
2804 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2806 if (lra_dump_file
!= NULL
)
2807 fprintf (lra_dump_file
,
2808 " alt=%d, not enough small class regs -- refuse\n",
2812 curr_alt
[nop
] = this_alternative
;
2813 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2814 curr_alt_win
[nop
] = this_alternative_win
;
2815 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2816 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2817 curr_alt_matches
[nop
] = this_alternative_matches
;
2819 if (this_alternative_matches
>= 0
2820 && !did_match
&& !this_alternative_win
)
2821 curr_alt_win
[this_alternative_matches
] = false;
2823 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2824 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2827 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2828 /* Prevent processing non-move insns. */
2829 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2830 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2831 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2832 && REG_P (no_subreg_reg_operand
[0])
2833 && REG_P (no_subreg_reg_operand
[1])
2834 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2835 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2836 || (! curr_alt_win
[0] && curr_alt_win
[1]
2837 && REG_P (no_subreg_reg_operand
[1])
2838 /* Check that we reload memory not the memory
2840 && ! (curr_alt_offmemok
[0]
2841 && MEM_P (no_subreg_reg_operand
[0]))
2842 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2843 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2844 && REG_P (no_subreg_reg_operand
[0])
2845 /* Check that we reload memory not the memory
2847 && ! (curr_alt_offmemok
[1]
2848 && MEM_P (no_subreg_reg_operand
[1]))
2849 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2850 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2851 no_subreg_reg_operand
[1])
2852 || (targetm
.preferred_reload_class
2853 (no_subreg_reg_operand
[1],
2854 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2855 /* If it is a result of recent elimination in move
2856 insn we can transform it into an add still by
2857 using this alternative. */
2858 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2860 /* We have a move insn and a new reload insn will be similar
2861 to the current insn. We should avoid such situation as
2862 it results in LRA cycling. */
2863 if (lra_dump_file
!= NULL
)
2864 fprintf (lra_dump_file
,
2865 " Cycle danger: overall += LRA_MAX_REJECT\n");
2866 overall
+= LRA_MAX_REJECT
;
2869 curr_alt_dont_inherit_ops_num
= 0;
2870 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2872 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2873 HARD_REG_SET temp_set
;
2875 i
= early_clobbered_nops
[nop
];
2876 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2877 || hard_regno
[i
] < 0)
2879 lra_assert (operand_reg
[i
] != NULL_RTX
);
2880 clobbered_hard_regno
= hard_regno
[i
];
2881 CLEAR_HARD_REG_SET (temp_set
);
2882 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2883 first_conflict_j
= last_conflict_j
= -1;
2884 for (j
= 0; j
< n_operands
; j
++)
2886 /* We don't want process insides of match_operator and
2887 match_parallel because otherwise we would process
2888 their operands once again generating a wrong
2890 || curr_static_id
->operand
[j
].is_operator
)
2892 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2893 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2895 /* If we don't reload j-th operand, check conflicts. */
2896 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2897 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2899 if (first_conflict_j
< 0)
2900 first_conflict_j
= j
;
2901 last_conflict_j
= j
;
2903 if (last_conflict_j
< 0)
2905 /* If earlyclobber operand conflicts with another
2906 non-matching operand which is actually the same register
2907 as the earlyclobber operand, it is better to reload the
2908 another operand as an operand matching the earlyclobber
2909 operand can be also the same. */
2910 if (first_conflict_j
== last_conflict_j
2911 && operand_reg
[last_conflict_j
] != NULL_RTX
2912 && ! curr_alt_match_win
[last_conflict_j
]
2913 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2915 curr_alt_win
[last_conflict_j
] = false;
2916 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2919 /* Early clobber was already reflected in REJECT. */
2920 lra_assert (reject
> 0);
2921 if (lra_dump_file
!= NULL
)
2924 " %d Conflict early clobber reload: reject--\n",
2927 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2931 /* We need to reload early clobbered register and the
2932 matched registers. */
2933 for (j
= 0; j
< n_operands
; j
++)
2934 if (curr_alt_matches
[j
] == i
)
2936 curr_alt_match_win
[j
] = false;
2938 overall
+= LRA_LOSER_COST_FACTOR
;
2940 if (! curr_alt_match_win
[i
])
2941 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2944 /* Remember pseudos used for match reloads are never
2946 lra_assert (curr_alt_matches
[i
] >= 0);
2947 curr_alt_win
[curr_alt_matches
[i
]] = false;
2949 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2951 /* Early clobber was already reflected in REJECT. */
2952 lra_assert (reject
> 0);
2953 if (lra_dump_file
!= NULL
)
2956 " %d Matched conflict early clobber reloads: "
2960 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2963 if (lra_dump_file
!= NULL
)
2964 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2965 nalt
, overall
, losers
, reload_nregs
);
2967 /* If this alternative can be made to work by reloading, and it
2968 needs less reloading than the others checked so far, record
2969 it as the chosen goal for reloading. */
2970 if ((best_losers
!= 0 && losers
== 0)
2971 || (((best_losers
== 0 && losers
== 0)
2972 || (best_losers
!= 0 && losers
!= 0))
2973 && (best_overall
> overall
2974 || (best_overall
== overall
2975 /* If the cost of the reloads is the same,
2976 prefer alternative which requires minimal
2977 number of reload regs. */
2978 && (reload_nregs
< best_reload_nregs
2979 || (reload_nregs
== best_reload_nregs
2980 && (best_reload_sum
< reload_sum
2981 || (best_reload_sum
== reload_sum
2982 && nalt
< goal_alt_number
))))))))
2984 for (nop
= 0; nop
< n_operands
; nop
++)
2986 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2987 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2988 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2989 goal_alt
[nop
] = curr_alt
[nop
];
2990 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2992 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2993 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2994 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2995 goal_alt_swapped
= curr_swapped
;
2996 best_overall
= overall
;
2997 best_losers
= losers
;
2998 best_reload_nregs
= reload_nregs
;
2999 best_reload_sum
= reload_sum
;
3000 goal_alt_number
= nalt
;
3003 /* Everything is satisfied. Do not process alternatives
3012 /* Make reload base reg from address AD. */
3014 base_to_reg (struct address_info
*ad
)
3018 rtx new_inner
= NULL_RTX
;
3019 rtx new_reg
= NULL_RTX
;
3021 rtx_insn
*last_insn
= get_last_insn();
3023 lra_assert (ad
->disp
== ad
->disp_term
);
3024 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3025 get_index_code (ad
));
3026 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3028 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3029 ad
->disp_term
== NULL
3032 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3034 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3035 code
= recog_memoized (insn
);
3038 delete_insns_since (last_insn
);
3045 /* Make reload base reg + disp from address AD. Return the new pseudo. */
3047 base_plus_disp_to_reg (struct address_info
*ad
)
3052 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
3053 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3054 get_index_code (ad
));
3055 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3057 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
3061 /* Make reload of index part of address AD. Return the new
3064 index_part_to_reg (struct address_info
*ad
)
3068 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3069 INDEX_REG_CLASS
, "index term");
3070 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3071 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3075 /* Return true if we can add a displacement to address AD, even if that
3076 makes the address invalid. The fix-up code requires any new address
3077 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3079 can_add_disp_p (struct address_info
*ad
)
3081 return (!ad
->autoinc_p
3082 && ad
->segment
== NULL
3083 && ad
->base
== ad
->base_term
3084 && ad
->disp
== ad
->disp_term
);
3087 /* Make equiv substitution in address AD. Return true if a substitution
3090 equiv_address_substitution (struct address_info
*ad
)
3092 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3093 HOST_WIDE_INT disp
, scale
;
3096 base_term
= strip_subreg (ad
->base_term
);
3097 if (base_term
== NULL
)
3098 base_reg
= new_base_reg
= NULL_RTX
;
3101 base_reg
= *base_term
;
3102 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3104 index_term
= strip_subreg (ad
->index_term
);
3105 if (index_term
== NULL
)
3106 index_reg
= new_index_reg
= NULL_RTX
;
3109 index_reg
= *index_term
;
3110 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3112 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3116 if (lra_dump_file
!= NULL
)
3118 fprintf (lra_dump_file
, "Changing address in insn %d ",
3119 INSN_UID (curr_insn
));
3120 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3122 if (base_reg
!= new_base_reg
)
3124 if (REG_P (new_base_reg
))
3126 *base_term
= new_base_reg
;
3129 else if (GET_CODE (new_base_reg
) == PLUS
3130 && REG_P (XEXP (new_base_reg
, 0))
3131 && CONST_INT_P (XEXP (new_base_reg
, 1))
3132 && can_add_disp_p (ad
))
3134 disp
+= INTVAL (XEXP (new_base_reg
, 1));
3135 *base_term
= XEXP (new_base_reg
, 0);
3138 if (ad
->base_term2
!= NULL
)
3139 *ad
->base_term2
= *ad
->base_term
;
3141 if (index_reg
!= new_index_reg
)
3143 if (REG_P (new_index_reg
))
3145 *index_term
= new_index_reg
;
3148 else if (GET_CODE (new_index_reg
) == PLUS
3149 && REG_P (XEXP (new_index_reg
, 0))
3150 && CONST_INT_P (XEXP (new_index_reg
, 1))
3151 && can_add_disp_p (ad
)
3152 && (scale
= get_index_scale (ad
)))
3154 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
3155 *index_term
= XEXP (new_index_reg
, 0);
3161 if (ad
->disp
!= NULL
)
3162 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3165 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3166 update_address (ad
);
3170 if (lra_dump_file
!= NULL
)
3173 fprintf (lra_dump_file
, " -- no change\n");
3176 fprintf (lra_dump_file
, " on equiv ");
3177 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3178 fprintf (lra_dump_file
, "\n");
3184 /* Major function to make reloads for an address in operand NOP or
3185 check its correctness (If CHECK_ONLY_P is true). The supported
3188 1) an address that existed before LRA started, at which point it
3189 must have been valid. These addresses are subject to elimination
3190 and may have become invalid due to the elimination offset being out
3193 2) an address created by forcing a constant to memory
3194 (force_const_to_mem). The initial form of these addresses might
3195 not be valid, and it is this function's job to make them valid.
3197 3) a frame address formed from a register and a (possibly zero)
3198 constant offset. As above, these addresses might not be valid and
3199 this function must make them so.
3201 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3202 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3203 address. Return true for any RTL change.
3205 The function is a helper function which does not produce all
3206 transformations (when CHECK_ONLY_P is false) which can be
3207 necessary. It does just basic steps. To do all necessary
3208 transformations use function process_address. */
3210 process_address_1 (int nop
, bool check_only_p
,
3211 rtx_insn
**before
, rtx_insn
**after
)
3213 struct address_info ad
;
3215 HOST_WIDE_INT scale
;
3216 rtx op
= *curr_id
->operand_loc
[nop
];
3217 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3218 enum constraint_num cn
= lookup_constraint (constraint
);
3219 bool change_p
= false;
3222 && GET_MODE (op
) == BLKmode
3223 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3226 if (insn_extra_address_constraint (cn
))
3227 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3228 /* Do not attempt to decompose arbitrary addresses generated by combine
3229 for asm operands with loose constraints, e.g 'X'. */
3231 && !(get_constraint_type (cn
) == CT_FIXED_FORM
3232 && constraint_satisfied_p (op
, cn
)))
3233 decompose_mem_address (&ad
, op
);
3234 else if (GET_CODE (op
) == SUBREG
3235 && MEM_P (SUBREG_REG (op
)))
3236 decompose_mem_address (&ad
, SUBREG_REG (op
));
3239 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3240 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3241 when INDEX_REG_CLASS is a single register class. */
3242 if (ad
.base_term
!= NULL
3243 && ad
.index_term
!= NULL
3244 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3245 && REG_P (*ad
.base_term
)
3246 && REG_P (*ad
.index_term
)
3247 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3248 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3250 std::swap (ad
.base
, ad
.index
);
3251 std::swap (ad
.base_term
, ad
.index_term
);
3254 change_p
= equiv_address_substitution (&ad
);
3255 if (ad
.base_term
!= NULL
3256 && (process_addr_reg
3257 (ad
.base_term
, check_only_p
, before
,
3259 && !(REG_P (*ad
.base_term
)
3260 && find_regno_note (curr_insn
, REG_DEAD
,
3261 REGNO (*ad
.base_term
)) != NULL_RTX
)
3263 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3264 get_index_code (&ad
)))))
3267 if (ad
.base_term2
!= NULL
)
3268 *ad
.base_term2
= *ad
.base_term
;
3270 if (ad
.index_term
!= NULL
3271 && process_addr_reg (ad
.index_term
, check_only_p
,
3272 before
, NULL
, INDEX_REG_CLASS
))
3275 /* Target hooks sometimes don't treat extra-constraint addresses as
3276 legitimate address_operands, so handle them specially. */
3277 if (insn_extra_address_constraint (cn
)
3278 && satisfies_address_constraint_p (&ad
, cn
))
3284 /* There are three cases where the shape of *AD.INNER may now be invalid:
3286 1) the original address was valid, but either elimination or
3287 equiv_address_substitution was applied and that made
3288 the address invalid.
3290 2) the address is an invalid symbolic address created by
3293 3) the address is a frame address with an invalid offset.
3295 4) the address is a frame address with an invalid base.
3297 All these cases involve a non-autoinc address, so there is no
3298 point revalidating other types. */
3299 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3302 /* Any index existed before LRA started, so we can assume that the
3303 presence and shape of the index is valid. */
3304 push_to_sequence (*before
);
3305 lra_assert (ad
.disp
== ad
.disp_term
);
3306 if (ad
.base
== NULL
)
3308 if (ad
.index
== NULL
)
3311 rtx_insn
*last
= get_last_insn ();
3313 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3315 rtx addr
= *ad
.inner
;
3317 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3320 /* addr => lo_sum (new_base, addr), case (2) above. */
3321 insn
= emit_insn (gen_rtx_SET
3323 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3324 code
= recog_memoized (insn
);
3327 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3328 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3330 /* Try to put lo_sum into register. */
3331 insn
= emit_insn (gen_rtx_SET
3333 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3334 code
= recog_memoized (insn
);
3337 *ad
.inner
= new_reg
;
3338 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3348 delete_insns_since (last
);
3353 /* addr => new_base, case (2) above. */
3354 lra_emit_move (new_reg
, addr
);
3356 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3358 insn
= NEXT_INSN (insn
))
3359 if (recog_memoized (insn
) < 0)
3361 if (insn
!= NULL_RTX
)
3363 /* Do nothing if we cannot generate right insns.
3364 This is analogous to reload pass behavior. */
3365 delete_insns_since (last
);
3369 *ad
.inner
= new_reg
;
3374 /* index * scale + disp => new base + index * scale,
3376 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3377 GET_CODE (*ad
.index
));
3379 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3380 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3381 lra_emit_move (new_reg
, *ad
.disp
);
3382 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3383 new_reg
, *ad
.index
);
3386 else if (ad
.index
== NULL
)
3391 rtx_insn
*insns
, *last_insn
;
3392 /* Try to reload base into register only if the base is invalid
3393 for the address but with valid offset, case (4) above. */
3395 new_reg
= base_to_reg (&ad
);
3397 /* base + disp => new base, cases (1) and (3) above. */
3398 /* Another option would be to reload the displacement into an
3399 index register. However, postreload has code to optimize
3400 address reloads that have the same base and different
3401 displacements, so reloading into an index register would
3402 not necessarily be a win. */
3403 if (new_reg
== NULL_RTX
)
3404 new_reg
= base_plus_disp_to_reg (&ad
);
3405 insns
= get_insns ();
3406 last_insn
= get_last_insn ();
3407 /* If we generated at least two insns, try last insn source as
3408 an address. If we succeed, we generate one less insn. */
3409 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3410 && GET_CODE (SET_SRC (set
)) == PLUS
3411 && REG_P (XEXP (SET_SRC (set
), 0))
3412 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3414 *ad
.inner
= SET_SRC (set
);
3415 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3417 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3418 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3419 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3420 get_index_code (&ad
));
3421 regno
= REGNO (*ad
.base_term
);
3422 if (regno
>= FIRST_PSEUDO_REGISTER
3423 && cl
!= lra_get_allocno_class (regno
))
3424 lra_change_class (regno
, cl
, " Change to", true);
3425 new_reg
= SET_SRC (set
);
3426 delete_insns_since (PREV_INSN (last_insn
));
3429 /* Try if target can split displacement into legitimite new disp
3430 and offset. If it's the case, we replace the last insn with
3431 insns for base + offset => new_reg and set new_reg + new disp
3433 last_insn
= get_last_insn ();
3434 if ((set
= single_set (last_insn
)) != NULL_RTX
3435 && GET_CODE (SET_SRC (set
)) == PLUS
3436 && REG_P (XEXP (SET_SRC (set
), 0))
3437 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3438 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3440 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3441 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3444 rtx_insn
*new_insns
;
3446 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3447 new_insns
= get_insns ();
3449 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3450 delete_insns_since (PREV_INSN (last_insn
));
3451 add_insn (new_insns
);
3452 insns
= get_insns ();
3457 *ad
.inner
= new_reg
;
3459 else if (ad
.disp_term
!= NULL
)
3461 /* base + scale * index + disp => new base + scale * index,
3463 new_reg
= base_plus_disp_to_reg (&ad
);
3464 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3465 new_reg
, *ad
.index
);
3467 else if ((scale
= get_index_scale (&ad
)) == 1)
3469 /* The last transformation to one reg will be made in
3470 curr_insn_transform function. */
3474 else if (scale
!= 0)
3476 /* base + scale * index => base + new_reg,
3478 Index part of address may become invalid. For example, we
3479 changed pseudo on the equivalent memory and a subreg of the
3480 pseudo onto the memory of different mode for which the scale is
3482 new_reg
= index_part_to_reg (&ad
);
3483 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3484 *ad
.base_term
, new_reg
);
3488 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3490 rtx addr
= *ad
.inner
;
3492 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3493 /* addr => new_base. */
3494 lra_emit_move (new_reg
, addr
);
3495 *ad
.inner
= new_reg
;
3497 *before
= get_insns ();
3502 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3503 Use process_address_1 as a helper function. Return true for any
3506 If CHECK_ONLY_P is true, just check address correctness. Return
3507 false if the address correct. */
3509 process_address (int nop
, bool check_only_p
,
3510 rtx_insn
**before
, rtx_insn
**after
)
3514 while (process_address_1 (nop
, check_only_p
, before
, after
))
3523 /* Emit insns to reload VALUE into a new register. VALUE is an
3524 auto-increment or auto-decrement RTX whose operand is a register or
3525 memory location; so reloading involves incrementing that location.
3526 IN is either identical to VALUE, or some cheaper place to reload
3527 value being incremented/decremented from.
3529 INC_AMOUNT is the number to increment or decrement by (always
3530 positive and ignored for POST_MODIFY/PRE_MODIFY).
3532 Return pseudo containing the result. */
3534 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3536 /* REG or MEM to be copied and incremented. */
3537 rtx incloc
= XEXP (value
, 0);
3538 /* Nonzero if increment after copying. */
3539 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3540 || GET_CODE (value
) == POST_MODIFY
);
3545 rtx real_in
= in
== value
? incloc
: in
;
3549 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3551 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3552 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3553 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3554 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3555 inc
= XEXP (XEXP (value
, 1), 1);
3559 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3560 inc_amount
= -inc_amount
;
3562 inc
= GEN_INT (inc_amount
);
3565 if (! post
&& REG_P (incloc
))
3568 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3571 if (real_in
!= result
)
3573 /* First copy the location to the result register. */
3574 lra_assert (REG_P (result
));
3575 emit_insn (gen_move_insn (result
, real_in
));
3578 /* We suppose that there are insns to add/sub with the constant
3579 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3580 old reload worked with this assumption. If the assumption
3581 becomes wrong, we should use approach in function
3582 base_plus_disp_to_reg. */
3585 /* See if we can directly increment INCLOC. */
3586 last
= get_last_insn ();
3587 add_insn
= emit_insn (plus_p
3588 ? gen_add2_insn (incloc
, inc
)
3589 : gen_sub2_insn (incloc
, inc
));
3591 code
= recog_memoized (add_insn
);
3594 if (! post
&& result
!= incloc
)
3595 emit_insn (gen_move_insn (result
, incloc
));
3598 delete_insns_since (last
);
3601 /* If couldn't do the increment directly, must increment in RESULT.
3602 The way we do this depends on whether this is pre- or
3603 post-increment. For pre-increment, copy INCLOC to the reload
3604 register, increment it there, then save back. */
3607 if (real_in
!= result
)
3608 emit_insn (gen_move_insn (result
, real_in
));
3610 emit_insn (gen_add2_insn (result
, inc
));
3612 emit_insn (gen_sub2_insn (result
, inc
));
3613 if (result
!= incloc
)
3614 emit_insn (gen_move_insn (incloc
, result
));
3620 Because this might be a jump insn or a compare, and because
3621 RESULT may not be available after the insn in an input
3622 reload, we must do the incrementing before the insn being
3625 We have already copied IN to RESULT. Increment the copy in
3626 RESULT, save that back, then decrement RESULT so it has
3627 the original value. */
3629 emit_insn (gen_add2_insn (result
, inc
));
3631 emit_insn (gen_sub2_insn (result
, inc
));
3632 emit_insn (gen_move_insn (incloc
, result
));
3633 /* Restore non-modified value for the result. We prefer this
3634 way because it does not require an additional hard
3638 if (CONST_INT_P (inc
))
3639 emit_insn (gen_add2_insn (result
,
3640 gen_int_mode (-INTVAL (inc
),
3641 GET_MODE (result
))));
3643 emit_insn (gen_sub2_insn (result
, inc
));
3646 emit_insn (gen_add2_insn (result
, inc
));
3651 /* Return true if the current move insn does not need processing as we
3652 already know that it satisfies its constraints. */
3654 simple_move_p (void)
3657 enum reg_class dclass
, sclass
;
3659 lra_assert (curr_insn_set
!= NULL_RTX
);
3660 dest
= SET_DEST (curr_insn_set
);
3661 src
= SET_SRC (curr_insn_set
);
3663 /* If the instruction has multiple sets we need to process it even if it
3664 is single_set. This can happen if one or more of the SETs are dead.
3666 if (multiple_sets (curr_insn
))
3669 return ((dclass
= get_op_class (dest
)) != NO_REGS
3670 && (sclass
= get_op_class (src
)) != NO_REGS
3671 /* The backend guarantees that register moves of cost 2
3672 never need reloads. */
3673 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3676 /* Swap operands NOP and NOP + 1. */
3678 swap_operands (int nop
)
3680 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3681 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3682 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3683 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3684 /* Swap the duplicates too. */
3685 lra_update_dup (curr_id
, nop
);
3686 lra_update_dup (curr_id
, nop
+ 1);
3689 /* Main entry point of the constraint code: search the body of the
3690 current insn to choose the best alternative. It is mimicking insn
3691 alternative cost calculation model of former reload pass. That is
3692 because machine descriptions were written to use this model. This
3693 model can be changed in future. Make commutative operand exchange
3696 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3697 constraints. Return true if any change happened during function
3700 If CHECK_ONLY_P is true then don't do any transformation. Just
3701 check that the insn satisfies all constraints. If the insn does
3702 not satisfy any constraint, return true. */
3704 curr_insn_transform (bool check_only_p
)
3711 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3712 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3713 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3714 rtx_insn
*before
, *after
;
3716 /* Flag that the insn has been changed through a transformation. */
3719 #ifdef SECONDARY_MEMORY_NEEDED
3722 int max_regno_before
;
3723 int reused_alternative_num
;
3725 curr_insn_set
= single_set (curr_insn
);
3726 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3729 no_input_reloads_p
= no_output_reloads_p
= false;
3730 goal_alt_number
= -1;
3731 change_p
= sec_mem_p
= false;
3732 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3733 reloads; neither are insns that SET cc0. Insns that use CC0 are
3734 not allowed to have any input reloads. */
3735 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3736 no_output_reloads_p
= true;
3738 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3739 no_input_reloads_p
= true;
3740 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3741 no_output_reloads_p
= true;
3743 n_operands
= curr_static_id
->n_operands
;
3744 n_alternatives
= curr_static_id
->n_alternatives
;
3746 /* Just return "no reloads" if insn has no operands with
3748 if (n_operands
== 0 || n_alternatives
== 0)
3751 max_regno_before
= max_reg_num ();
3753 for (i
= 0; i
< n_operands
; i
++)
3755 goal_alt_matched
[i
][0] = -1;
3756 goal_alt_matches
[i
] = -1;
3759 commutative
= curr_static_id
->commutative
;
3761 /* Now see what we need for pseudos that didn't get hard regs or got
3762 the wrong kind of hard reg. For this, we must consider all the
3763 operands together against the register constraints. */
3765 best_losers
= best_overall
= INT_MAX
;
3766 best_reload_sum
= 0;
3768 curr_swapped
= false;
3769 goal_alt_swapped
= false;
3772 /* Make equivalence substitution and memory subreg elimination
3773 before address processing because an address legitimacy can
3774 depend on memory mode. */
3775 for (i
= 0; i
< n_operands
; i
++)
3778 bool op_change_p
= false;
3780 if (curr_static_id
->operand
[i
].is_operator
)
3783 old
= op
= *curr_id
->operand_loc
[i
];
3784 if (GET_CODE (old
) == SUBREG
)
3785 old
= SUBREG_REG (old
);
3786 subst
= get_equiv_with_elimination (old
, curr_insn
);
3787 original_subreg_reg_mode
[i
] = VOIDmode
;
3788 equiv_substition_p
[i
] = false;
3791 equiv_substition_p
[i
] = true;
3792 subst
= copy_rtx (subst
);
3793 lra_assert (REG_P (old
));
3794 if (GET_CODE (op
) != SUBREG
)
3795 *curr_id
->operand_loc
[i
] = subst
;
3798 SUBREG_REG (op
) = subst
;
3799 if (GET_MODE (subst
) == VOIDmode
)
3800 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3802 if (lra_dump_file
!= NULL
)
3804 fprintf (lra_dump_file
,
3805 "Changing pseudo %d in operand %i of insn %u on equiv ",
3806 REGNO (old
), i
, INSN_UID (curr_insn
));
3807 dump_value_slim (lra_dump_file
, subst
, 1);
3808 fprintf (lra_dump_file
, "\n");
3810 op_change_p
= change_p
= true;
3812 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3815 lra_update_dup (curr_id
, i
);
3819 /* Reload address registers and displacements. We do it before
3820 finding an alternative because of memory constraints. */
3821 before
= after
= NULL
;
3822 for (i
= 0; i
< n_operands
; i
++)
3823 if (! curr_static_id
->operand
[i
].is_operator
3824 && process_address (i
, check_only_p
, &before
, &after
))
3829 lra_update_dup (curr_id
, i
);
3833 /* If we've changed the instruction then any alternative that
3834 we chose previously may no longer be valid. */
3835 lra_set_used_insn_alternative (curr_insn
, -1);
3837 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3838 && check_and_process_move (&change_p
, &sec_mem_p
))
3843 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3844 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3845 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3846 reused_alternative_num
, INSN_UID (curr_insn
));
3848 if (process_alt_operands (reused_alternative_num
))
3852 return ! alt_p
|| best_losers
!= 0;
3854 /* If insn is commutative (it's safe to exchange a certain pair of
3855 operands) then we need to try each alternative twice, the second
3856 time matching those two operands as if we had exchanged them. To
3857 do this, really exchange them in operands.
3859 If we have just tried the alternatives the second time, return
3860 operands to normal and drop through. */
3862 if (reused_alternative_num
< 0 && commutative
>= 0)
3864 curr_swapped
= !curr_swapped
;
3867 swap_operands (commutative
);
3871 swap_operands (commutative
);
3874 if (! alt_p
&& ! sec_mem_p
)
3876 /* No alternative works with reloads?? */
3877 if (INSN_CODE (curr_insn
) >= 0)
3878 fatal_insn ("unable to generate reloads for:", curr_insn
);
3879 error_for_asm (curr_insn
,
3880 "inconsistent operand constraints in an %<asm%>");
3881 /* Avoid further trouble with this insn. Don't generate use
3882 pattern here as we could use the insn SP offset. */
3883 lra_set_insn_deleted (curr_insn
);
3887 /* If the best alternative is with operands 1 and 2 swapped, swap
3888 them. Update the operand numbers of any reloads already
3891 if (goal_alt_swapped
)
3893 if (lra_dump_file
!= NULL
)
3894 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3895 INSN_UID (curr_insn
));
3897 /* Swap the duplicates too. */
3898 swap_operands (commutative
);
3902 #ifdef SECONDARY_MEMORY_NEEDED
3903 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3904 too conservatively. So we use the secondary memory only if there
3905 is no any alternative without reloads. */
3906 use_sec_mem_p
= false;
3908 use_sec_mem_p
= true;
3911 for (i
= 0; i
< n_operands
; i
++)
3912 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3914 use_sec_mem_p
= i
< n_operands
;
3919 int in
= -1, out
= -1;
3920 rtx new_reg
, src
, dest
, rld
;
3921 machine_mode sec_mode
, rld_mode
;
3923 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3924 dest
= SET_DEST (curr_insn_set
);
3925 src
= SET_SRC (curr_insn_set
);
3926 for (i
= 0; i
< n_operands
; i
++)
3927 if (*curr_id
->operand_loc
[i
] == dest
)
3929 else if (*curr_id
->operand_loc
[i
] == src
)
3931 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3932 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3933 out
= curr_static_id
->dup_num
[i
];
3934 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3935 in
= curr_static_id
->dup_num
[i
];
3936 lra_assert (out
>= 0 && in
>= 0
3937 && curr_static_id
->operand
[out
].type
== OP_OUT
3938 && curr_static_id
->operand
[in
].type
== OP_IN
);
3939 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
3940 rld_mode
= GET_MODE (rld
);
3941 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
3942 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3943 NO_REGS
, "secondary");
3944 /* If the mode is changed, it should be wider. */
3945 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
3946 if (sec_mode
!= rld_mode
)
3948 /* If the target says specifically to use another mode for
3949 secondary memory moves we can not reuse the original
3951 after
= emit_spill_move (false, new_reg
, dest
);
3952 lra_process_new_insns (curr_insn
, NULL
, after
,
3953 "Inserting the sec. move");
3954 /* We may have non null BEFORE here (e.g. after address
3956 push_to_sequence (before
);
3957 before
= emit_spill_move (true, new_reg
, src
);
3959 before
= get_insns ();
3961 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3962 lra_set_insn_deleted (curr_insn
);
3964 else if (dest
== rld
)
3966 *curr_id
->operand_loc
[out
] = new_reg
;
3967 lra_update_dup (curr_id
, out
);
3968 after
= emit_spill_move (false, new_reg
, dest
);
3969 lra_process_new_insns (curr_insn
, NULL
, after
,
3970 "Inserting the sec. move");
3974 *curr_id
->operand_loc
[in
] = new_reg
;
3975 lra_update_dup (curr_id
, in
);
3976 /* See comments above. */
3977 push_to_sequence (before
);
3978 before
= emit_spill_move (true, new_reg
, src
);
3980 before
= get_insns ();
3982 lra_process_new_insns (curr_insn
, before
, NULL
,
3983 "Inserting the sec. move");
3985 lra_update_insn_regno_info (curr_insn
);
3990 lra_assert (goal_alt_number
>= 0);
3991 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3993 if (lra_dump_file
!= NULL
)
3997 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3998 goal_alt_number
, INSN_UID (curr_insn
));
3999 for (i
= 0; i
< n_operands
; i
++)
4001 p
= (curr_static_id
->operand_alternative
4002 [goal_alt_number
* n_operands
+ i
].constraint
);
4005 fprintf (lra_dump_file
, " (%d) ", i
);
4006 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4007 fputc (*p
, lra_dump_file
);
4009 if (INSN_CODE (curr_insn
) >= 0
4010 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4011 fprintf (lra_dump_file
, " {%s}", p
);
4012 if (curr_id
->sp_offset
!= 0)
4013 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
4014 curr_id
->sp_offset
);
4015 fprintf (lra_dump_file
, "\n");
4018 /* Right now, for any pair of operands I and J that are required to
4019 match, with J < I, goal_alt_matches[I] is J. Add I to
4020 goal_alt_matched[J]. */
4022 for (i
= 0; i
< n_operands
; i
++)
4023 if ((j
= goal_alt_matches
[i
]) >= 0)
4025 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4027 /* We allow matching one output operand and several input
4030 || (curr_static_id
->operand
[j
].type
== OP_OUT
4031 && curr_static_id
->operand
[i
].type
== OP_IN
4032 && (curr_static_id
->operand
4033 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4034 goal_alt_matched
[j
][k
] = i
;
4035 goal_alt_matched
[j
][k
+ 1] = -1;
4038 for (i
= 0; i
< n_operands
; i
++)
4039 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4041 /* Any constants that aren't allowed and can't be reloaded into
4042 registers are here changed into memory references. */
4043 for (i
= 0; i
< n_operands
; i
++)
4044 if (goal_alt_win
[i
])
4047 enum reg_class new_class
;
4048 rtx reg
= *curr_id
->operand_loc
[i
];
4050 if (GET_CODE (reg
) == SUBREG
)
4051 reg
= SUBREG_REG (reg
);
4053 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4055 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4057 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4060 lra_change_class (regno
, new_class
, " Change to", true);
4066 const char *constraint
;
4068 rtx op
= *curr_id
->operand_loc
[i
];
4069 rtx subreg
= NULL_RTX
;
4070 machine_mode mode
= curr_operand_mode
[i
];
4072 if (GET_CODE (op
) == SUBREG
)
4075 op
= SUBREG_REG (op
);
4076 mode
= GET_MODE (op
);
4079 if (CONST_POOL_OK_P (mode
, op
)
4080 && ((targetm
.preferred_reload_class
4081 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4082 || no_input_reloads_p
))
4084 rtx tem
= force_const_mem (mode
, op
);
4087 if (subreg
!= NULL_RTX
)
4088 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4090 *curr_id
->operand_loc
[i
] = tem
;
4091 lra_update_dup (curr_id
, i
);
4092 process_address (i
, false, &before
, &after
);
4094 /* If the alternative accepts constant pool refs directly
4095 there will be no reload needed at all. */
4096 if (subreg
!= NULL_RTX
)
4098 /* Skip alternatives before the one requested. */
4099 constraint
= (curr_static_id
->operand_alternative
4100 [goal_alt_number
* n_operands
+ i
].constraint
);
4102 (c
= *constraint
) && c
!= ',' && c
!= '#';
4103 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4105 enum constraint_num cn
= lookup_constraint (constraint
);
4106 if ((insn_extra_memory_constraint (cn
)
4107 || insn_extra_special_memory_constraint (cn
))
4108 && satisfies_memory_constraint_p (tem
, cn
))
4111 if (c
== '\0' || c
== ',' || c
== '#')
4114 goal_alt_win
[i
] = true;
4120 for (i
= 0; i
< n_operands
; i
++)
4123 bool optional_p
= false;
4125 rtx op
= *curr_id
->operand_loc
[i
];
4127 if (goal_alt_win
[i
])
4129 if (goal_alt
[i
] == NO_REGS
4131 /* When we assign NO_REGS it means that we will not
4132 assign a hard register to the scratch pseudo by
4133 assigment pass and the scratch pseudo will be
4134 spilled. Spilled scratch pseudos are transformed
4135 back to scratches at the LRA end. */
4136 && lra_former_scratch_operand_p (curr_insn
, i
)
4137 && lra_former_scratch_p (REGNO (op
)))
4139 int regno
= REGNO (op
);
4140 lra_change_class (regno
, NO_REGS
, " Change to", true);
4141 if (lra_get_regno_hard_regno (regno
) >= 0)
4142 /* We don't have to mark all insn affected by the
4143 spilled pseudo as there is only one such insn, the
4145 reg_renumber
[regno
] = -1;
4146 lra_assert (bitmap_single_bit_set_p
4147 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4149 /* We can do an optional reload. If the pseudo got a hard
4150 reg, we might improve the code through inheritance. If
4151 it does not get a hard register we coalesce memory/memory
4152 moves later. Ignore move insns to avoid cycling. */
4154 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4155 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4156 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4157 && regno
< new_regno_start
4158 && ! lra_former_scratch_p (regno
)
4159 && reg_renumber
[regno
] < 0
4160 /* Check that the optional reload pseudo will be able to
4161 hold given mode value. */
4162 && ! (prohibited_class_reg_set_mode_p
4163 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4164 PSEUDO_REGNO_MODE (regno
)))
4165 && (curr_insn_set
== NULL_RTX
4166 || !((REG_P (SET_SRC (curr_insn_set
))
4167 || MEM_P (SET_SRC (curr_insn_set
))
4168 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4169 && (REG_P (SET_DEST (curr_insn_set
))
4170 || MEM_P (SET_DEST (curr_insn_set
))
4171 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4177 /* Operands that match previous ones have already been handled. */
4178 if (goal_alt_matches
[i
] >= 0)
4181 /* We should not have an operand with a non-offsettable address
4182 appearing where an offsettable address will do. It also may
4183 be a case when the address should be special in other words
4184 not a general one (e.g. it needs no index reg). */
4185 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4187 enum reg_class rclass
;
4188 rtx
*loc
= &XEXP (op
, 0);
4189 enum rtx_code code
= GET_CODE (*loc
);
4191 push_to_sequence (before
);
4192 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4194 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4195 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4196 /* This value does not matter for MODIFY. */
4197 GET_MODE_SIZE (GET_MODE (op
)));
4198 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4199 "offsetable address", &new_reg
))
4200 lra_emit_move (new_reg
, *loc
);
4201 before
= get_insns ();
4204 lra_update_dup (curr_id
, i
);
4206 else if (goal_alt_matched
[i
][0] == -1)
4210 int hard_regno
, byte
;
4211 enum op_type type
= curr_static_id
->operand
[i
].type
;
4213 loc
= curr_id
->operand_loc
[i
];
4214 mode
= curr_operand_mode
[i
];
4215 if (GET_CODE (*loc
) == SUBREG
)
4217 reg
= SUBREG_REG (*loc
);
4218 byte
= SUBREG_BYTE (*loc
);
4220 /* Strict_low_part requires reload the register not
4221 the sub-register. */
4222 && (curr_static_id
->operand
[i
].strict_low
4223 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4225 = get_try_hard_regno (REGNO (reg
))) >= 0
4226 && (simplify_subreg_regno
4228 GET_MODE (reg
), byte
, mode
) < 0)
4229 && (goal_alt
[i
] == NO_REGS
4230 || (simplify_subreg_regno
4231 (ira_class_hard_regs
[goal_alt
[i
]][0],
4232 GET_MODE (reg
), byte
, mode
) >= 0)))))
4234 /* An OP_INOUT is required when reloading a subreg of a
4235 mode wider than a word to ensure that data beyond the
4236 word being reloaded is preserved. Also automatically
4237 ensure that strict_low_part reloads are made into
4238 OP_INOUT which should already be true from the backend
4241 && (curr_static_id
->operand
[i
].strict_low
4242 || (GET_MODE_SIZE (GET_MODE (reg
)) > UNITS_PER_WORD
4243 && (GET_MODE_SIZE (mode
)
4244 < GET_MODE_SIZE (GET_MODE (reg
))))))
4246 loc
= &SUBREG_REG (*loc
);
4247 mode
= GET_MODE (*loc
);
4251 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4252 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4255 push_to_sequence (before
);
4256 lra_emit_move (new_reg
, old
);
4257 before
= get_insns ();
4262 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4265 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4267 after
= get_insns ();
4271 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4272 if (goal_alt_dont_inherit_ops
[j
] == i
)
4274 lra_set_regno_unique_value (REGNO (new_reg
));
4277 lra_update_dup (curr_id
, i
);
4279 else if (curr_static_id
->operand
[i
].type
== OP_IN
4280 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4283 /* generate reloads for input and matched outputs. */
4284 match_inputs
[0] = i
;
4285 match_inputs
[1] = -1;
4286 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4287 goal_alt
[i
], &before
, &after
,
4288 curr_static_id
->operand_alternative
4289 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4292 else if (curr_static_id
->operand
[i
].type
== OP_OUT
4293 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4295 /* Generate reloads for output and matched inputs. */
4296 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4297 &after
, curr_static_id
->operand_alternative
4298 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4299 else if (curr_static_id
->operand
[i
].type
== OP_IN
4300 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4303 /* Generate reloads for matched inputs. */
4304 match_inputs
[0] = i
;
4305 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4306 match_inputs
[j
+ 1] = k
;
4307 match_inputs
[j
+ 1] = -1;
4308 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4312 /* We must generate code in any case when function
4313 process_alt_operands decides that it is possible. */
4316 /* Memorise processed outputs so that output remaining to be processed
4317 can avoid using the same register value (see match_reload). */
4318 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4320 outputs
[n_outputs
++] = i
;
4321 outputs
[n_outputs
] = -1;
4328 lra_assert (REG_P (reg
));
4329 regno
= REGNO (reg
);
4330 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4331 if (GET_CODE (op
) == SUBREG
)
4332 op
= SUBREG_REG (op
);
4333 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4334 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4335 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4336 if (lra_dump_file
!= NULL
)
4337 fprintf (lra_dump_file
,
4338 " Making reload reg %d for reg %d optional\n",
4342 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4343 || max_regno_before
!= max_reg_num ())
4347 lra_update_operator_dups (curr_id
);
4348 /* Something changes -- process the insn. */
4349 lra_update_insn_regno_info (curr_insn
);
4351 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4355 /* Return true if INSN satisfies all constraints. In other words, no
4356 reload insns are needed. */
4358 lra_constrain_insn (rtx_insn
*insn
)
4360 int saved_new_regno_start
= new_regno_start
;
4361 int saved_new_insn_uid_start
= new_insn_uid_start
;
4365 curr_id
= lra_get_insn_recog_data (curr_insn
);
4366 curr_static_id
= curr_id
->insn_static_data
;
4367 new_insn_uid_start
= get_max_uid ();
4368 new_regno_start
= max_reg_num ();
4369 change_p
= curr_insn_transform (true);
4370 new_regno_start
= saved_new_regno_start
;
4371 new_insn_uid_start
= saved_new_insn_uid_start
;
4375 /* Return true if X is in LIST. */
4377 in_list_p (rtx x
, rtx list
)
4379 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4380 if (XEXP (list
, 0) == x
)
4385 /* Return true if X contains an allocatable hard register (if
4386 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4388 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4394 code
= GET_CODE (x
);
4397 int regno
= REGNO (x
);
4398 HARD_REG_SET alloc_regs
;
4402 if (regno
>= FIRST_PSEUDO_REGISTER
)
4403 regno
= lra_get_regno_hard_regno (regno
);
4406 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4407 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4411 if (regno
< FIRST_PSEUDO_REGISTER
)
4415 return lra_get_regno_hard_regno (regno
) < 0;
4418 fmt
= GET_RTX_FORMAT (code
);
4419 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4423 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4426 else if (fmt
[i
] == 'E')
4428 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4429 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4436 /* Process all regs in location *LOC and change them on equivalent
4437 substitution. Return true if any change was done. */
4439 loc_equivalence_change_p (rtx
*loc
)
4441 rtx subst
, reg
, x
= *loc
;
4442 bool result
= false;
4443 enum rtx_code code
= GET_CODE (x
);
4449 reg
= SUBREG_REG (x
);
4450 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4451 && GET_MODE (subst
) == VOIDmode
)
4453 /* We cannot reload debug location. Simplify subreg here
4454 while we know the inner mode. */
4455 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4456 GET_MODE (reg
), SUBREG_BYTE (x
));
4460 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4466 /* Scan all the operand sub-expressions. */
4467 fmt
= GET_RTX_FORMAT (code
);
4468 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4471 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4472 else if (fmt
[i
] == 'E')
4473 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4475 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4480 /* Similar to loc_equivalence_change_p, but for use as
4481 simplify_replace_fn_rtx callback. DATA is insn for which the
4482 elimination is done. If it null we don't do the elimination. */
4484 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4489 rtx subst
= (data
== NULL
4490 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4497 /* Maximum number of generated reload insns per an insn. It is for
4498 preventing this pass cycling in a bug case. */
4499 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4501 /* The current iteration number of this LRA pass. */
4502 int lra_constraint_iter
;
4504 /* True if we substituted equiv which needs checking register
4505 allocation correctness because the equivalent value contains
4506 allocatable hard registers or when we restore multi-register
4508 bool lra_risky_transformations_p
;
4510 /* Return true if REGNO is referenced in more than one block. */
4512 multi_block_pseudo_p (int regno
)
4514 basic_block bb
= NULL
;
4518 if (regno
< FIRST_PSEUDO_REGISTER
)
4521 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4523 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4524 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4529 /* Return true if LIST contains a deleted insn. */
4531 contains_deleted_insn_p (rtx_insn_list
*list
)
4533 for (; list
!= NULL_RTX
; list
= list
->next ())
4534 if (NOTE_P (list
->insn ())
4535 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4540 /* Return true if X contains a pseudo dying in INSN. */
4542 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4549 return (insn
!= NULL_RTX
4550 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4551 code
= GET_CODE (x
);
4552 fmt
= GET_RTX_FORMAT (code
);
4553 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4557 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4560 else if (fmt
[i
] == 'E')
4562 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4563 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4570 /* Return true if INSN contains a dying pseudo in INSN right hand
4573 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4575 rtx set
= single_set (insn
);
4577 gcc_assert (set
!= NULL
);
4578 return dead_pseudo_p (SET_SRC (set
), insn
);
4581 /* Return true if any init insn of REGNO contains a dying pseudo in
4582 insn right hand side. */
4584 init_insn_rhs_dead_pseudo_p (int regno
)
4586 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4590 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4591 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4596 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4597 reverse only if we have one init insn with given REGNO as a
4600 reverse_equiv_p (int regno
)
4602 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4607 if (! INSN_P (insns
->insn ())
4608 || insns
->next () != NULL
)
4610 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4612 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4615 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4616 call this function only for non-reverse equivalence. */
4618 contains_reloaded_insn_p (int regno
)
4621 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4623 for (; list
!= NULL
; list
= list
->next ())
4624 if ((set
= single_set (list
->insn ())) == NULL_RTX
4625 || ! REG_P (SET_DEST (set
))
4626 || (int) REGNO (SET_DEST (set
)) != regno
)
4631 /* Entry function of LRA constraint pass. Return true if the
4632 constraint pass did change the code. */
4634 lra_constraints (bool first_p
)
4637 int i
, hard_regno
, new_insns_num
;
4638 unsigned int min_len
, new_min_len
, uid
;
4639 rtx set
, x
, reg
, dest_reg
;
4640 basic_block last_bb
;
4643 lra_constraint_iter
++;
4644 if (lra_dump_file
!= NULL
)
4645 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4646 lra_constraint_iter
);
4648 if (pic_offset_table_rtx
4649 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4650 lra_risky_transformations_p
= true;
4652 /* On the first iteration we should check IRA assignment
4653 correctness. In rare cases, the assignments can be wrong as
4654 early clobbers operands are ignored in IRA. */
4655 lra_risky_transformations_p
= first_p
;
4656 new_insn_uid_start
= get_max_uid ();
4657 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4658 /* Mark used hard regs for target stack size calulations. */
4659 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4660 if (lra_reg_info
[i
].nrefs
!= 0
4661 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4665 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4666 for (j
= 0; j
< nregs
; j
++)
4667 df_set_regs_ever_live (hard_regno
+ j
, true);
4669 /* Do elimination before the equivalence processing as we can spill
4670 some pseudos during elimination. */
4671 lra_eliminate (false, first_p
);
4672 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4673 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4674 if (lra_reg_info
[i
].nrefs
!= 0)
4676 ira_reg_equiv
[i
].profitable_p
= true;
4677 reg
= regno_reg_rtx
[i
];
4678 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4680 bool pseudo_p
= contains_reg_p (x
, false, false);
4682 /* After RTL transformation, we can not guarantee that
4683 pseudo in the substitution was not reloaded which might
4684 make equivalence invalid. For example, in reverse
4691 the memory address register was reloaded before the 2nd
4693 if ((! first_p
&& pseudo_p
)
4694 /* We don't use DF for compilation speed sake. So it
4695 is problematic to update live info when we use an
4696 equivalence containing pseudos in more than one
4698 || (pseudo_p
&& multi_block_pseudo_p (i
))
4699 /* If an init insn was deleted for some reason, cancel
4700 the equiv. We could update the equiv insns after
4701 transformations including an equiv insn deletion
4702 but it is not worthy as such cases are extremely
4704 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4705 /* If it is not a reverse equivalence, we check that a
4706 pseudo in rhs of the init insn is not dying in the
4707 insn. Otherwise, the live info at the beginning of
4708 the corresponding BB might be wrong after we
4709 removed the insn. When the equiv can be a
4710 constant, the right hand side of the init insn can
4712 || (! reverse_equiv_p (i
)
4713 && (init_insn_rhs_dead_pseudo_p (i
)
4714 /* If we reloaded the pseudo in an equivalence
4715 init insn, we can not remove the equiv init
4716 insns and the init insns might write into
4717 const memory in this case. */
4718 || contains_reloaded_insn_p (i
)))
4719 /* Prevent access beyond equivalent memory for
4720 paradoxical subregs. */
4722 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4723 > GET_MODE_SIZE (GET_MODE (x
))))
4724 || (pic_offset_table_rtx
4725 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4726 && (targetm
.preferred_reload_class
4727 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4728 || contains_symbol_ref_p (x
))))
4729 ira_reg_equiv
[i
].defined_p
= false;
4730 if (contains_reg_p (x
, false, true))
4731 ira_reg_equiv
[i
].profitable_p
= false;
4732 if (get_equiv (reg
) != reg
)
4733 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4736 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4738 /* We should add all insns containing pseudos which should be
4739 substituted by their equivalences. */
4740 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4741 lra_push_insn_by_uid (uid
);
4742 min_len
= lra_insn_stack_length ();
4746 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4748 curr_insn
= lra_pop_insn ();
4750 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4751 if (curr_bb
!= last_bb
)
4754 bb_reload_num
= lra_curr_reload_num
;
4756 if (min_len
> new_min_len
)
4758 min_len
= new_min_len
;
4761 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4763 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4764 MAX_RELOAD_INSNS_NUMBER
);
4766 if (DEBUG_INSN_P (curr_insn
))
4768 /* We need to check equivalence in debug insn and change
4769 pseudo to the equivalent value if necessary. */
4770 curr_id
= lra_get_insn_recog_data (curr_insn
);
4771 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4773 rtx old
= *curr_id
->operand_loc
[0];
4774 *curr_id
->operand_loc
[0]
4775 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4776 loc_equivalence_callback
, curr_insn
);
4777 if (old
!= *curr_id
->operand_loc
[0])
4779 lra_update_insn_regno_info (curr_insn
);
4784 else if (INSN_P (curr_insn
))
4786 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4788 dest_reg
= SET_DEST (set
);
4789 /* The equivalence pseudo could be set up as SUBREG in a
4790 case when it is a call restore insn in a mode
4791 different from the pseudo mode. */
4792 if (GET_CODE (dest_reg
) == SUBREG
)
4793 dest_reg
= SUBREG_REG (dest_reg
);
4794 if ((REG_P (dest_reg
)
4795 && (x
= get_equiv (dest_reg
)) != dest_reg
4796 /* Remove insns which set up a pseudo whose value
4797 can not be changed. Such insns might be not in
4798 init_insns because we don't update equiv data
4799 during insn transformations.
4801 As an example, let suppose that a pseudo got
4802 hard register and on the 1st pass was not
4803 changed to equivalent constant. We generate an
4804 additional insn setting up the pseudo because of
4805 secondary memory movement. Then the pseudo is
4806 spilled and we use the equiv constant. In this
4807 case we should remove the additional insn and
4808 this insn is not init_insns list. */
4809 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4810 /* Check that this is actually an insn setting
4811 up the equivalence. */
4812 || in_list_p (curr_insn
,
4814 [REGNO (dest_reg
)].init_insns
)))
4815 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4816 && in_list_p (curr_insn
,
4818 [REGNO (SET_SRC (set
))].init_insns
)))
4820 /* This is equiv init insn of pseudo which did not get a
4821 hard register -- remove the insn. */
4822 if (lra_dump_file
!= NULL
)
4824 fprintf (lra_dump_file
,
4825 " Removing equiv init insn %i (freq=%d)\n",
4826 INSN_UID (curr_insn
),
4827 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4828 dump_insn_slim (lra_dump_file
, curr_insn
);
4830 if (contains_reg_p (x
, true, false))
4831 lra_risky_transformations_p
= true;
4832 lra_set_insn_deleted (curr_insn
);
4836 curr_id
= lra_get_insn_recog_data (curr_insn
);
4837 curr_static_id
= curr_id
->insn_static_data
;
4838 init_curr_insn_input_reloads ();
4839 init_curr_operand_mode ();
4840 if (curr_insn_transform (false))
4842 /* Check non-transformed insns too for equiv change as USE
4843 or CLOBBER don't need reloads but can contain pseudos
4844 being changed on their equivalences. */
4845 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4846 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4848 lra_update_insn_regno_info (curr_insn
);
4854 /* If we used a new hard regno, changed_p should be true because the
4855 hard reg is assigned to a new pseudo. */
4856 if (flag_checking
&& !changed_p
)
4858 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4859 if (lra_reg_info
[i
].nrefs
!= 0
4860 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4862 int j
, nregs
= hard_regno_nregs (hard_regno
,
4863 PSEUDO_REGNO_MODE (i
));
4865 for (j
= 0; j
< nregs
; j
++)
4866 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4872 static void initiate_invariants (void);
4873 static void finish_invariants (void);
4875 /* Initiate the LRA constraint pass. It is done once per
4878 lra_constraints_init (void)
4880 initiate_invariants ();
4883 /* Finalize the LRA constraint pass. It is done once per
4886 lra_constraints_finish (void)
4888 finish_invariants ();
4893 /* Structure describes invariants for ineheritance. */
4894 struct lra_invariant
4896 /* The order number of the invariant. */
4898 /* The invariant RTX. */
4900 /* The origin insn of the invariant. */
4904 typedef lra_invariant invariant_t
;
4905 typedef invariant_t
*invariant_ptr_t
;
4906 typedef const invariant_t
*const_invariant_ptr_t
;
4908 /* Pointer to the inheritance invariants. */
4909 static vec
<invariant_ptr_t
> invariants
;
4911 /* Allocation pool for the invariants. */
4912 static object_allocator
<lra_invariant
> *invariants_pool
;
4914 /* Hash table for the invariants. */
4915 static htab_t invariant_table
;
4917 /* Hash function for INVARIANT. */
4919 invariant_hash (const void *invariant
)
4921 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4922 return lra_rtx_hash (inv
);
4925 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4927 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4929 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4930 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4932 return rtx_equal_p (inv1
, inv2
);
4935 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4936 invariant which is in the table. */
4937 static invariant_ptr_t
4938 insert_invariant (rtx invariant_rtx
)
4941 invariant_t invariant
;
4942 invariant_ptr_t invariant_ptr
;
4944 invariant
.invariant_rtx
= invariant_rtx
;
4945 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4946 if (*entry_ptr
== NULL
)
4948 invariant_ptr
= invariants_pool
->allocate ();
4949 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4950 invariant_ptr
->insn
= NULL
;
4951 invariants
.safe_push (invariant_ptr
);
4952 *entry_ptr
= (void *) invariant_ptr
;
4954 return (invariant_ptr_t
) *entry_ptr
;
4957 /* Initiate the invariant table. */
4959 initiate_invariants (void)
4961 invariants
.create (100);
4963 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
4964 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4967 /* Finish the invariant table. */
4969 finish_invariants (void)
4971 htab_delete (invariant_table
);
4972 delete invariants_pool
;
4973 invariants
.release ();
4976 /* Make the invariant table empty. */
4978 clear_invariants (void)
4980 htab_empty (invariant_table
);
4981 invariants_pool
->release ();
4982 invariants
.truncate (0);
4987 /* This page contains code to do inheritance/split
4990 /* Number of reloads passed so far in current EBB. */
4991 static int reloads_num
;
4993 /* Number of calls passed so far in current EBB. */
4994 static int calls_num
;
4996 /* Current reload pseudo check for validity of elements in
4998 static int curr_usage_insns_check
;
5000 /* Info about last usage of registers in EBB to do inheritance/split
5001 transformation. Inheritance transformation is done from a spilled
5002 pseudo and split transformations from a hard register or a pseudo
5003 assigned to a hard register. */
5006 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5007 value INSNS is valid. The insns is chain of optional debug insns
5008 and a finishing non-debug insn using the corresponding reg. The
5009 value is also used to mark the registers which are set up in the
5010 current insn. The negated insn uid is used for this. */
5012 /* Value of global reloads_num at the last insn in INSNS. */
5014 /* Value of global reloads_nums at the last insn in INSNS. */
5016 /* It can be true only for splitting. And it means that the restore
5017 insn should be put after insn given by the following member. */
5019 /* Next insns in the current EBB which use the original reg and the
5020 original reg value is not changed between the current insn and
5021 the next insns. In order words, e.g. for inheritance, if we need
5022 to use the original reg value again in the next insns we can try
5023 to use the value in a hard register from a reload insn of the
5028 /* Map: regno -> corresponding pseudo usage insns. */
5029 static struct usage_insns
*usage_insns
;
5032 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5034 usage_insns
[regno
].check
= curr_usage_insns_check
;
5035 usage_insns
[regno
].insns
= insn
;
5036 usage_insns
[regno
].reloads_num
= reloads_num
;
5037 usage_insns
[regno
].calls_num
= calls_num
;
5038 usage_insns
[regno
].after_p
= after_p
;
5041 /* The function is used to form list REGNO usages which consists of
5042 optional debug insns finished by a non-debug insn using REGNO.
5043 RELOADS_NUM is current number of reload insns processed so far. */
5045 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5047 rtx next_usage_insns
;
5049 if (usage_insns
[regno
].check
== curr_usage_insns_check
5050 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5051 && DEBUG_INSN_P (insn
))
5053 /* Check that we did not add the debug insn yet. */
5054 if (next_usage_insns
!= insn
5055 && (GET_CODE (next_usage_insns
) != INSN_LIST
5056 || XEXP (next_usage_insns
, 0) != insn
))
5057 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5060 else if (NONDEBUG_INSN_P (insn
))
5061 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5063 usage_insns
[regno
].check
= 0;
5066 /* Return first non-debug insn in list USAGE_INSNS. */
5068 skip_usage_debug_insns (rtx usage_insns
)
5072 /* Skip debug insns. */
5073 for (insn
= usage_insns
;
5074 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5075 insn
= XEXP (insn
, 1))
5077 return safe_as_a
<rtx_insn
*> (insn
);
5080 /* Return true if we need secondary memory moves for insn in
5081 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5084 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5085 rtx usage_insns ATTRIBUTE_UNUSED
)
5087 #ifndef SECONDARY_MEMORY_NEEDED
5094 if (inher_cl
== ALL_REGS
5095 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5097 lra_assert (INSN_P (insn
));
5098 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5100 dest
= SET_DEST (set
);
5103 lra_assert (inher_cl
!= NO_REGS
);
5104 cl
= get_reg_class (REGNO (dest
));
5105 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5106 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
5110 /* Registers involved in inheritance/split in the current EBB
5111 (inheritance/split pseudos and original registers). */
5112 static bitmap_head check_only_regs
;
5114 /* Reload pseudos can not be involded in invariant inheritance in the
5116 static bitmap_head invalid_invariant_regs
;
5118 /* Do inheritance transformations for insn INSN, which defines (if
5119 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5120 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5121 form as the "insns" field of usage_insns. Return true if we
5122 succeed in such transformation.
5124 The transformations look like:
5127 ... p <- i (new insn)
5129 <- ... p ... <- ... i ...
5131 ... i <- p (new insn)
5132 <- ... p ... <- ... i ...
5134 <- ... p ... <- ... i ...
5135 where p is a spilled original pseudo and i is a new inheritance pseudo.
5138 The inheritance pseudo has the smallest class of two classes CL and
5139 class of ORIGINAL REGNO. */
5141 inherit_reload_reg (bool def_p
, int original_regno
,
5142 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5144 if (optimize_function_for_size_p (cfun
))
5147 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5148 rtx original_reg
= regno_reg_rtx
[original_regno
];
5149 rtx new_reg
, usage_insn
;
5150 rtx_insn
*new_insns
;
5152 lra_assert (! usage_insns
[original_regno
].after_p
);
5153 if (lra_dump_file
!= NULL
)
5154 fprintf (lra_dump_file
,
5155 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5156 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5158 if (lra_dump_file
!= NULL
)
5160 fprintf (lra_dump_file
,
5161 " Rejecting inheritance for %d "
5162 "because of disjoint classes %s and %s\n",
5163 original_regno
, reg_class_names
[cl
],
5164 reg_class_names
[rclass
]);
5165 fprintf (lra_dump_file
,
5166 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5170 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5171 /* We don't use a subset of two classes because it can be
5172 NO_REGS. This transformation is still profitable in most
5173 cases even if the classes are not intersected as register
5174 move is probably cheaper than a memory load. */
5175 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5177 if (lra_dump_file
!= NULL
)
5178 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5179 reg_class_names
[cl
], reg_class_names
[rclass
]);
5183 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5185 /* Reject inheritance resulting in secondary memory moves.
5186 Otherwise, there is a danger in LRA cycling. Also such
5187 transformation will be unprofitable. */
5188 if (lra_dump_file
!= NULL
)
5190 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5191 rtx set
= single_set (insn
);
5193 lra_assert (set
!= NULL_RTX
);
5195 rtx dest
= SET_DEST (set
);
5197 lra_assert (REG_P (dest
));
5198 fprintf (lra_dump_file
,
5199 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5200 "as secondary mem is needed\n",
5201 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5202 original_regno
, reg_class_names
[rclass
]);
5203 fprintf (lra_dump_file
,
5204 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5208 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5209 rclass
, "inheritance");
5212 lra_emit_move (original_reg
, new_reg
);
5214 lra_emit_move (new_reg
, original_reg
);
5215 new_insns
= get_insns ();
5217 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5219 if (lra_dump_file
!= NULL
)
5221 fprintf (lra_dump_file
,
5222 " Rejecting inheritance %d->%d "
5223 "as it results in 2 or more insns:\n",
5224 original_regno
, REGNO (new_reg
));
5225 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5226 fprintf (lra_dump_file
,
5227 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5231 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5232 lra_update_insn_regno_info (insn
);
5234 /* We now have a new usage insn for original regno. */
5235 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5236 if (lra_dump_file
!= NULL
)
5237 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5238 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5239 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5240 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5241 bitmap_set_bit (&check_only_regs
, original_regno
);
5242 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5244 lra_process_new_insns (insn
, NULL
, new_insns
,
5245 "Add original<-inheritance");
5247 lra_process_new_insns (insn
, new_insns
, NULL
,
5248 "Add inheritance<-original");
5249 while (next_usage_insns
!= NULL_RTX
)
5251 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5253 usage_insn
= next_usage_insns
;
5254 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5255 next_usage_insns
= NULL
;
5259 usage_insn
= XEXP (next_usage_insns
, 0);
5260 lra_assert (DEBUG_INSN_P (usage_insn
));
5261 next_usage_insns
= XEXP (next_usage_insns
, 1);
5263 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5264 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5265 if (lra_dump_file
!= NULL
)
5267 fprintf (lra_dump_file
,
5268 " Inheritance reuse change %d->%d (bb%d):\n",
5269 original_regno
, REGNO (new_reg
),
5270 BLOCK_FOR_INSN (usage_insn
)->index
);
5271 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5274 if (lra_dump_file
!= NULL
)
5275 fprintf (lra_dump_file
,
5276 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5280 /* Return true if we need a caller save/restore for pseudo REGNO which
5281 was assigned to a hard register. */
5283 need_for_call_save_p (int regno
)
5285 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5286 return (usage_insns
[regno
].calls_num
< calls_num
5287 && (overlaps_hard_reg_set_p
5289 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5290 ? lra_reg_info
[regno
].actual_call_used_reg_set
5291 : call_used_reg_set
,
5292 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5293 || (targetm
.hard_regno_call_part_clobbered
5294 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5297 /* Global registers occurring in the current EBB. */
5298 static bitmap_head ebb_global_regs
;
5300 /* Return true if we need a split for hard register REGNO or pseudo
5301 REGNO which was assigned to a hard register.
5302 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5303 used for reloads since the EBB end. It is an approximation of the
5304 used hard registers in the split range. The exact value would
5305 require expensive calculations. If we were aggressive with
5306 splitting because of the approximation, the split pseudo will save
5307 the same hard register assignment and will be removed in the undo
5308 pass. We still need the approximation because too aggressive
5309 splitting would result in too inaccurate cost calculation in the
5310 assignment pass because of too many generated moves which will be
5311 probably removed in the undo pass. */
5313 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5315 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5317 lra_assert (hard_regno
>= 0);
5318 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5319 /* Don't split eliminable hard registers, otherwise we can
5320 split hard registers like hard frame pointer, which
5321 lives on BB start/end according to DF-infrastructure,
5322 when there is a pseudo assigned to the register and
5323 living in the same BB. */
5324 && (regno
>= FIRST_PSEUDO_REGISTER
5325 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5326 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5327 /* Don't split call clobbered hard regs living through
5328 calls, otherwise we might have a check problem in the
5329 assign sub-pass as in the most cases (exception is a
5330 situation when lra_risky_transformations_p value is
5331 true) the assign pass assumes that all pseudos living
5332 through calls are assigned to call saved hard regs. */
5333 && (regno
>= FIRST_PSEUDO_REGISTER
5334 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5335 || usage_insns
[regno
].calls_num
== calls_num
)
5336 /* We need at least 2 reloads to make pseudo splitting
5337 profitable. We should provide hard regno splitting in
5338 any case to solve 1st insn scheduling problem when
5339 moving hard register definition up might result in
5340 impossibility to find hard register for reload pseudo of
5341 small register class. */
5342 && (usage_insns
[regno
].reloads_num
5343 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5344 && (regno
< FIRST_PSEUDO_REGISTER
5345 /* For short living pseudos, spilling + inheritance can
5346 be considered a substitution for splitting.
5347 Therefore we do not splitting for local pseudos. It
5348 decreases also aggressiveness of splitting. The
5349 minimal number of references is chosen taking into
5350 account that for 2 references splitting has no sense
5351 as we can just spill the pseudo. */
5352 || (regno
>= FIRST_PSEUDO_REGISTER
5353 && lra_reg_info
[regno
].nrefs
> 3
5354 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5355 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5358 /* Return class for the split pseudo created from original pseudo with
5359 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5360 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5361 results in no secondary memory movements. */
5362 static enum reg_class
5363 choose_split_class (enum reg_class allocno_class
,
5364 int hard_regno ATTRIBUTE_UNUSED
,
5365 machine_mode mode ATTRIBUTE_UNUSED
)
5367 #ifndef SECONDARY_MEMORY_NEEDED
5368 return allocno_class
;
5371 enum reg_class cl
, best_cl
= NO_REGS
;
5372 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5373 = REGNO_REG_CLASS (hard_regno
);
5375 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
5376 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5377 return allocno_class
;
5379 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5381 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
5382 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
5383 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5384 && (best_cl
== NO_REGS
5385 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5391 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5392 It only makes sense to call this function if NEW_REGNO is always
5393 equal to ORIGINAL_REGNO. */
5396 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5398 if (!ira_reg_equiv
[original_regno
].defined_p
)
5401 ira_expand_reg_equiv ();
5402 ira_reg_equiv
[new_regno
].defined_p
= true;
5403 if (ira_reg_equiv
[original_regno
].memory
)
5404 ira_reg_equiv
[new_regno
].memory
5405 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5406 if (ira_reg_equiv
[original_regno
].constant
)
5407 ira_reg_equiv
[new_regno
].constant
5408 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5409 if (ira_reg_equiv
[original_regno
].invariant
)
5410 ira_reg_equiv
[new_regno
].invariant
5411 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5414 /* Do split transformations for insn INSN, which defines or uses
5415 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5416 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5417 "insns" field of usage_insns.
5419 The transformations look like:
5422 ... s <- p (new insn -- save)
5424 ... p <- s (new insn -- restore)
5425 <- ... p ... <- ... p ...
5427 <- ... p ... <- ... p ...
5428 ... s <- p (new insn -- save)
5430 ... p <- s (new insn -- restore)
5431 <- ... p ... <- ... p ...
5433 where p is an original pseudo got a hard register or a hard
5434 register and s is a new split pseudo. The save is put before INSN
5435 if BEFORE_P is true. Return true if we succeed in such
5438 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5439 rtx next_usage_insns
)
5441 enum reg_class rclass
;
5443 int hard_regno
, nregs
;
5444 rtx new_reg
, usage_insn
;
5445 rtx_insn
*restore
, *save
;
5450 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5452 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5453 hard_regno
= original_regno
;
5454 call_save_p
= false;
5456 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5457 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5458 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5459 as part of a multi-word register. In that case, or if the biggest
5460 mode was larger than a register, just use the reg_rtx. Otherwise,
5461 limit the size to that of the biggest access in the function. */
5462 if (mode
== VOIDmode
5463 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5465 original_reg
= regno_reg_rtx
[hard_regno
];
5466 mode
= reg_rtx_mode
;
5469 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5473 mode
= PSEUDO_REGNO_MODE (original_regno
);
5474 hard_regno
= reg_renumber
[original_regno
];
5475 nregs
= hard_regno_nregs (hard_regno
, mode
);
5476 rclass
= lra_get_allocno_class (original_regno
);
5477 original_reg
= regno_reg_rtx
[original_regno
];
5478 call_save_p
= need_for_call_save_p (original_regno
);
5480 lra_assert (hard_regno
>= 0);
5481 if (lra_dump_file
!= NULL
)
5482 fprintf (lra_dump_file
,
5483 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5487 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5488 hard_regno_nregs (hard_regno
, mode
),
5490 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5494 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5495 if (rclass
== NO_REGS
)
5497 if (lra_dump_file
!= NULL
)
5499 fprintf (lra_dump_file
,
5500 " Rejecting split of %d(%s): "
5501 "no good reg class for %d(%s)\n",
5503 reg_class_names
[lra_get_allocno_class (original_regno
)],
5505 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5508 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5512 /* Split_if_necessary can split hard registers used as part of a
5513 multi-register mode but splits each register individually. The
5514 mode used for each independent register may not be supported
5515 so reject the split. Splitting the wider mode should theoretically
5516 be possible but is not implemented. */
5517 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5519 if (lra_dump_file
!= NULL
)
5521 fprintf (lra_dump_file
,
5522 " Rejecting split of %d(%s): unsuitable mode %s\n",
5524 reg_class_names
[lra_get_allocno_class (original_regno
)],
5525 GET_MODE_NAME (mode
));
5528 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5532 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5533 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5535 int new_regno
= REGNO (new_reg
);
5536 save
= emit_spill_move (true, new_reg
, original_reg
);
5537 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5539 if (lra_dump_file
!= NULL
)
5543 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5544 original_regno
, new_regno
);
5545 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5546 fprintf (lra_dump_file
,
5547 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5551 restore
= emit_spill_move (false, new_reg
, original_reg
);
5552 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5554 if (lra_dump_file
!= NULL
)
5556 fprintf (lra_dump_file
,
5557 " Rejecting split %d->%d "
5558 "resulting in > 2 restore insns:\n",
5559 original_regno
, new_regno
);
5560 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5561 fprintf (lra_dump_file
,
5562 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5566 /* Transfer equivalence information to the spill register, so that
5567 if we fail to allocate the spill register, we have the option of
5568 rematerializing the original value instead of spilling to the stack. */
5569 if (!HARD_REGISTER_NUM_P (original_regno
)
5570 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5571 lra_copy_reg_equiv (new_regno
, original_regno
);
5572 after_p
= usage_insns
[original_regno
].after_p
;
5573 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5574 bitmap_set_bit (&check_only_regs
, new_regno
);
5575 bitmap_set_bit (&check_only_regs
, original_regno
);
5576 bitmap_set_bit (&lra_split_regs
, new_regno
);
5579 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5581 usage_insn
= next_usage_insns
;
5584 usage_insn
= XEXP (next_usage_insns
, 0);
5585 lra_assert (DEBUG_INSN_P (usage_insn
));
5586 next_usage_insns
= XEXP (next_usage_insns
, 1);
5587 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5588 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5589 if (lra_dump_file
!= NULL
)
5591 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5592 original_regno
, new_regno
);
5593 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5596 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5597 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5598 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5599 after_p
? NULL
: restore
,
5600 after_p
? restore
: NULL
,
5602 ? "Add reg<-save" : "Add reg<-split");
5603 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5604 before_p
? NULL
: save
,
5606 ? "Add save<-reg" : "Add split<-reg");
5608 /* If we are trying to split multi-register. We should check
5609 conflicts on the next assignment sub-pass. IRA can allocate on
5610 sub-register levels, LRA do this on pseudos level right now and
5611 this discrepancy may create allocation conflicts after
5613 lra_risky_transformations_p
= true;
5614 if (lra_dump_file
!= NULL
)
5615 fprintf (lra_dump_file
,
5616 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5620 /* Recognize that we need a split transformation for insn INSN, which
5621 defines or uses REGNO in its insn biggest MODE (we use it only if
5622 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5623 hard registers which might be used for reloads since the EBB end.
5624 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5625 uid before starting INSN processing. Return true if we succeed in
5626 such transformation. */
5628 split_if_necessary (int regno
, machine_mode mode
,
5629 HARD_REG_SET potential_reload_hard_regs
,
5630 bool before_p
, rtx_insn
*insn
, int max_uid
)
5634 rtx next_usage_insns
;
5636 if (regno
< FIRST_PSEUDO_REGISTER
)
5637 nregs
= hard_regno_nregs (regno
, mode
);
5638 for (i
= 0; i
< nregs
; i
++)
5639 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5640 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5641 /* To avoid processing the register twice or more. */
5642 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5643 && INSN_UID (next_usage_insns
) < max_uid
)
5644 || (GET_CODE (next_usage_insns
) == INSN_LIST
5645 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5646 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5647 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5652 /* Return TRUE if rtx X is considered as an invariant for
5655 invariant_p (const_rtx x
)
5662 code
= GET_CODE (x
);
5663 mode
= GET_MODE (x
);
5667 code
= GET_CODE (x
);
5668 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
5669 mode
= GET_MODE (x
);
5677 int i
, nregs
, regno
= REGNO (x
);
5679 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5680 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5681 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5683 nregs
= hard_regno_nregs (regno
, mode
);
5684 for (i
= 0; i
< nregs
; i
++)
5685 if (! fixed_regs
[regno
+ i
]
5686 /* A hard register may be clobbered in the current insn
5687 but we can ignore this case because if the hard
5688 register is used it should be set somewhere after the
5690 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5693 fmt
= GET_RTX_FORMAT (code
);
5694 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5698 if (! invariant_p (XEXP (x
, i
)))
5701 else if (fmt
[i
] == 'E')
5703 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5704 if (! invariant_p (XVECEXP (x
, i
, j
)))
5711 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5712 inheritance transformation (using dest_reg instead invariant in a
5713 subsequent insn). */
5715 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5717 invariant_ptr_t invariant_ptr
;
5718 rtx_insn
*insn
, *new_insns
;
5719 rtx insn_set
, insn_reg
, new_reg
;
5721 bool succ_p
= false;
5722 int dst_regno
= REGNO (dst_reg
);
5723 machine_mode dst_mode
= GET_MODE (dst_reg
);
5724 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5726 invariant_ptr
= insert_invariant (invariant_rtx
);
5727 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5729 /* We have a subsequent insn using the invariant. */
5730 insn_set
= single_set (insn
);
5731 lra_assert (insn_set
!= NULL
);
5732 insn_reg
= SET_DEST (insn_set
);
5733 lra_assert (REG_P (insn_reg
));
5734 insn_regno
= REGNO (insn_reg
);
5735 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5737 if (dst_mode
== GET_MODE (insn_reg
)
5738 /* We should consider only result move reg insns which are
5740 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5741 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5743 if (lra_dump_file
!= NULL
)
5744 fprintf (lra_dump_file
,
5745 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5746 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5747 cl
, "invariant inheritance");
5748 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5749 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5750 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5752 lra_emit_move (new_reg
, dst_reg
);
5753 new_insns
= get_insns ();
5755 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5756 "Add invariant inheritance<-original");
5758 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5759 new_insns
= get_insns ();
5761 lra_process_new_insns (insn
, NULL
, new_insns
,
5762 "Changing reload<-inheritance");
5763 lra_set_insn_deleted (insn
);
5765 if (lra_dump_file
!= NULL
)
5767 fprintf (lra_dump_file
,
5768 " Invariant inheritance reuse change %d (bb%d):\n",
5769 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5770 dump_insn_slim (lra_dump_file
, insn
);
5771 fprintf (lra_dump_file
,
5772 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5776 invariant_ptr
->insn
= curr_insn
;
5780 /* Check only registers living at the current program point in the
5782 static bitmap_head live_regs
;
5784 /* Update live info in EBB given by its HEAD and TAIL insns after
5785 inheritance/split transformation. The function removes dead moves
5788 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5793 rtx_insn
*prev_insn
;
5796 basic_block last_bb
, prev_bb
, curr_bb
;
5798 struct lra_insn_reg
*reg
;
5802 last_bb
= BLOCK_FOR_INSN (tail
);
5804 for (curr_insn
= tail
;
5805 curr_insn
!= PREV_INSN (head
);
5806 curr_insn
= prev_insn
)
5808 prev_insn
= PREV_INSN (curr_insn
);
5809 /* We need to process empty blocks too. They contain
5810 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5811 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5813 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5814 if (curr_bb
!= prev_bb
)
5816 if (prev_bb
!= NULL
)
5818 /* Update df_get_live_in (prev_bb): */
5819 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5820 if (bitmap_bit_p (&live_regs
, j
))
5821 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5823 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5825 if (curr_bb
!= last_bb
)
5827 /* Update df_get_live_out (curr_bb): */
5828 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5830 live_p
= bitmap_bit_p (&live_regs
, j
);
5832 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5833 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5839 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5841 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5845 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5847 if (! NONDEBUG_INSN_P (curr_insn
))
5849 curr_id
= lra_get_insn_recog_data (curr_insn
);
5850 curr_static_id
= curr_id
->insn_static_data
;
5852 if ((set
= single_set (curr_insn
)) != NULL_RTX
5853 && REG_P (SET_DEST (set
))
5854 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5855 && SET_DEST (set
) != pic_offset_table_rtx
5856 && bitmap_bit_p (&check_only_regs
, regno
)
5857 && ! bitmap_bit_p (&live_regs
, regno
))
5859 /* See which defined values die here. */
5860 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5861 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5862 bitmap_clear_bit (&live_regs
, reg
->regno
);
5863 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5864 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5865 bitmap_clear_bit (&live_regs
, reg
->regno
);
5866 if (curr_id
->arg_hard_regs
!= NULL
)
5867 /* Make clobbered argument hard registers die. */
5868 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5869 if (regno
>= FIRST_PSEUDO_REGISTER
)
5870 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5871 /* Mark each used value as live. */
5872 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5873 if (reg
->type
!= OP_OUT
5874 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5875 bitmap_set_bit (&live_regs
, reg
->regno
);
5876 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5877 if (reg
->type
!= OP_OUT
5878 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5879 bitmap_set_bit (&live_regs
, reg
->regno
);
5880 if (curr_id
->arg_hard_regs
!= NULL
)
5881 /* Make used argument hard registers live. */
5882 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5883 if (regno
< FIRST_PSEUDO_REGISTER
5884 && bitmap_bit_p (&check_only_regs
, regno
))
5885 bitmap_set_bit (&live_regs
, regno
);
5886 /* It is quite important to remove dead move insns because it
5887 means removing dead store. We don't need to process them for
5891 if (lra_dump_file
!= NULL
)
5893 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5894 dump_insn_slim (lra_dump_file
, curr_insn
);
5896 lra_set_insn_deleted (curr_insn
);
5901 /* The structure describes info to do an inheritance for the current
5902 insn. We need to collect such info first before doing the
5903 transformations because the transformations change the insn
5904 internal representation. */
5907 /* Original regno. */
5909 /* Subsequent insns which can inherit original reg value. */
5913 /* Array containing all info for doing inheritance from the current
5915 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5917 /* Number elements in the previous array. */
5918 static int to_inherit_num
;
5920 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5921 structure to_inherit. */
5923 add_to_inherit (int regno
, rtx insns
)
5927 for (i
= 0; i
< to_inherit_num
; i
++)
5928 if (to_inherit
[i
].regno
== regno
)
5930 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5931 to_inherit
[to_inherit_num
].regno
= regno
;
5932 to_inherit
[to_inherit_num
++].insns
= insns
;
5935 /* Return the last non-debug insn in basic block BB, or the block begin
5938 get_last_insertion_point (basic_block bb
)
5942 FOR_BB_INSNS_REVERSE (bb
, insn
)
5943 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5948 /* Set up RES by registers living on edges FROM except the edge (FROM,
5949 TO) or by registers set up in a jump insn in BB FROM. */
5951 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5954 struct lra_insn_reg
*reg
;
5958 lra_assert (to
!= NULL
);
5960 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5962 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5963 last
= get_last_insertion_point (from
);
5964 if (! JUMP_P (last
))
5966 curr_id
= lra_get_insn_recog_data (last
);
5967 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5968 if (reg
->type
!= OP_IN
)
5969 bitmap_set_bit (res
, reg
->regno
);
5972 /* Used as a temporary results of some bitmap calculations. */
5973 static bitmap_head temp_bitmap
;
5975 /* We split for reloads of small class of hard regs. The following
5976 defines how many hard regs the class should have to be qualified as
5977 small. The code is mostly oriented to x86/x86-64 architecture
5978 where some insns need to use only specific register or pair of
5979 registers and these register can live in RTL explicitly, e.g. for
5980 parameter passing. */
5981 static const int max_small_class_regs_num
= 2;
5983 /* Do inheritance/split transformations in EBB starting with HEAD and
5984 finishing on TAIL. We process EBB insns in the reverse order.
5985 Return true if we did any inheritance/split transformation in the
5988 We should avoid excessive splitting which results in worse code
5989 because of inaccurate cost calculations for spilling new split
5990 pseudos in such case. To achieve this we do splitting only if
5991 register pressure is high in given basic block and there are reload
5992 pseudos requiring hard registers. We could do more register
5993 pressure calculations at any given program point to avoid necessary
5994 splitting even more but it is to expensive and the current approach
5995 works well enough. */
5997 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5999 int i
, src_regno
, dst_regno
, nregs
;
6000 bool change_p
, succ_p
, update_reloads_num_p
;
6001 rtx_insn
*prev_insn
, *last_insn
;
6002 rtx next_usage_insns
, curr_set
;
6004 struct lra_insn_reg
*reg
;
6005 basic_block last_processed_bb
, curr_bb
= NULL
;
6006 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6010 bool head_p
, after_p
;
6013 curr_usage_insns_check
++;
6014 clear_invariants ();
6015 reloads_num
= calls_num
= 0;
6016 bitmap_clear (&check_only_regs
);
6017 bitmap_clear (&invalid_invariant_regs
);
6018 last_processed_bb
= NULL
;
6019 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6020 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6021 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6022 /* We don't process new insns generated in the loop. */
6023 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6025 prev_insn
= PREV_INSN (curr_insn
);
6026 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6027 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6028 if (last_processed_bb
!= curr_bb
)
6030 /* We are at the end of BB. Add qualified living
6031 pseudos for potential splitting. */
6032 to_process
= df_get_live_out (curr_bb
);
6033 if (last_processed_bb
!= NULL
)
6035 /* We are somewhere in the middle of EBB. */
6036 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6038 to_process
= &temp_bitmap
;
6040 last_processed_bb
= curr_bb
;
6041 last_insn
= get_last_insertion_point (curr_bb
);
6042 after_p
= (! JUMP_P (last_insn
)
6043 && (! CALL_P (last_insn
)
6044 || (find_reg_note (last_insn
,
6045 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6046 && ! SIBLING_CALL_P (last_insn
))));
6047 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6048 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6050 if ((int) j
>= lra_constraint_new_regno_start
)
6052 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6054 if (j
< FIRST_PSEUDO_REGISTER
)
6055 SET_HARD_REG_BIT (live_hard_regs
, j
);
6057 add_to_hard_reg_set (&live_hard_regs
,
6058 PSEUDO_REGNO_MODE (j
),
6060 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6064 src_regno
= dst_regno
= -1;
6065 curr_set
= single_set (curr_insn
);
6066 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6067 dst_regno
= REGNO (SET_DEST (curr_set
));
6068 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6069 src_regno
= REGNO (SET_SRC (curr_set
));
6070 update_reloads_num_p
= true;
6071 if (src_regno
< lra_constraint_new_regno_start
6072 && src_regno
>= FIRST_PSEUDO_REGISTER
6073 && reg_renumber
[src_regno
] < 0
6074 && dst_regno
>= lra_constraint_new_regno_start
6075 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6077 /* 'reload_pseudo <- original_pseudo'. */
6078 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6080 update_reloads_num_p
= false;
6082 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6083 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6084 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6085 curr_insn
, next_usage_insns
);
6089 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6090 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6091 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6092 reg_class_contents
[cl
]);
6094 else if (src_regno
< 0
6095 && dst_regno
>= lra_constraint_new_regno_start
6096 && invariant_p (SET_SRC (curr_set
))
6097 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6098 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6099 && ! bitmap_bit_p (&invalid_invariant_regs
,
6100 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6102 /* 'reload_pseudo <- invariant'. */
6103 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6105 update_reloads_num_p
= false;
6106 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6108 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6109 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6110 reg_class_contents
[cl
]);
6112 else if (src_regno
>= lra_constraint_new_regno_start
6113 && dst_regno
< lra_constraint_new_regno_start
6114 && dst_regno
>= FIRST_PSEUDO_REGISTER
6115 && reg_renumber
[dst_regno
] < 0
6116 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6117 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6118 && (next_usage_insns
6119 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6121 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6123 update_reloads_num_p
= false;
6124 /* 'original_pseudo <- reload_pseudo'. */
6125 if (! JUMP_P (curr_insn
)
6126 && inherit_reload_reg (true, dst_regno
, cl
,
6127 curr_insn
, next_usage_insns
))
6130 usage_insns
[dst_regno
].check
= 0;
6131 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6132 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6133 reg_class_contents
[cl
]);
6135 else if (INSN_P (curr_insn
))
6138 int max_uid
= get_max_uid ();
6140 curr_id
= lra_get_insn_recog_data (curr_insn
);
6141 curr_static_id
= curr_id
->insn_static_data
;
6143 /* Process insn definitions. */
6144 for (iter
= 0; iter
< 2; iter
++)
6145 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6148 if (reg
->type
!= OP_IN
6149 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6151 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6152 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6153 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6154 && (next_usage_insns
6155 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6157 struct lra_insn_reg
*r
;
6159 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6160 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6162 /* Don't do inheritance if the pseudo is also
6163 used in the insn. */
6165 /* We can not do inheritance right now
6166 because the current insn reg info (chain
6167 regs) can change after that. */
6168 add_to_inherit (dst_regno
, next_usage_insns
);
6170 /* We can not process one reg twice here because of
6171 usage_insns invalidation. */
6172 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6173 || reg_renumber
[dst_regno
] >= 0)
6174 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6178 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6179 potential_reload_hard_regs
,
6180 false, curr_insn
, max_uid
))
6182 CLEAR_HARD_REG_SET (s
);
6183 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6184 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6186 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6187 reg_renumber
[dst_regno
]);
6188 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6190 /* We should invalidate potential inheritance or
6191 splitting for the current insn usages to the next
6192 usage insns (see code below) as the output pseudo
6194 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6195 && reg_renumber
[dst_regno
] < 0)
6196 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6197 && (dst_regno
< FIRST_PSEUDO_REGISTER
6198 || reg_renumber
[dst_regno
] >= 0)))
6200 /* Invalidate and mark definitions. */
6201 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6202 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6205 nregs
= hard_regno_nregs (dst_regno
,
6207 for (i
= 0; i
< nregs
; i
++)
6208 usage_insns
[dst_regno
+ i
].check
6209 = -(int) INSN_UID (curr_insn
);
6213 /* Process clobbered call regs. */
6214 if (curr_id
->arg_hard_regs
!= NULL
)
6215 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6216 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6217 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6218 = -(int) INSN_UID (curr_insn
);
6219 if (! JUMP_P (curr_insn
))
6220 for (i
= 0; i
< to_inherit_num
; i
++)
6221 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6222 ALL_REGS
, curr_insn
,
6223 to_inherit
[i
].insns
))
6225 if (CALL_P (curr_insn
))
6227 rtx cheap
, pat
, dest
;
6229 int regno
, hard_regno
;
6232 if ((cheap
= find_reg_note (curr_insn
,
6233 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6234 && ((cheap
= XEXP (cheap
, 0)), true)
6235 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6236 && (hard_regno
= reg_renumber
[regno
]) >= 0
6237 /* If there are pending saves/restores, the
6238 optimization is not worth. */
6239 && usage_insns
[regno
].calls_num
== calls_num
- 1
6240 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6242 /* Restore the pseudo from the call result as
6243 REG_RETURNED note says that the pseudo value is
6244 in the call result and the pseudo is an argument
6246 pat
= PATTERN (curr_insn
);
6247 if (GET_CODE (pat
) == PARALLEL
)
6248 pat
= XVECEXP (pat
, 0, 0);
6249 dest
= SET_DEST (pat
);
6250 /* For multiple return values dest is PARALLEL.
6251 Currently we handle only single return value case. */
6255 emit_move_insn (cheap
, copy_rtx (dest
));
6256 restore
= get_insns ();
6258 lra_process_new_insns (curr_insn
, NULL
, restore
,
6259 "Inserting call parameter restore");
6260 /* We don't need to save/restore of the pseudo from
6262 usage_insns
[regno
].calls_num
= calls_num
;
6263 bitmap_set_bit (&check_only_regs
, regno
);
6268 /* Process insn usages. */
6269 for (iter
= 0; iter
< 2; iter
++)
6270 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6273 if ((reg
->type
!= OP_OUT
6274 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6275 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6277 if (src_regno
>= FIRST_PSEUDO_REGISTER
6278 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6280 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6281 && (next_usage_insns
6282 = usage_insns
[src_regno
].insns
) != NULL_RTX
6283 && NONDEBUG_INSN_P (curr_insn
))
6284 add_to_inherit (src_regno
, next_usage_insns
);
6285 else if (usage_insns
[src_regno
].check
6286 != -(int) INSN_UID (curr_insn
))
6287 /* Add usages but only if the reg is not set up
6288 in the same insn. */
6289 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6291 else if (src_regno
< FIRST_PSEUDO_REGISTER
6292 || reg_renumber
[src_regno
] >= 0)
6295 rtx_insn
*use_insn
= curr_insn
;
6297 before_p
= (JUMP_P (curr_insn
)
6298 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6299 if (NONDEBUG_INSN_P (curr_insn
)
6300 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6301 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6302 potential_reload_hard_regs
,
6303 before_p
, curr_insn
, max_uid
))
6306 lra_risky_transformations_p
= true;
6309 usage_insns
[src_regno
].check
= 0;
6311 use_insn
= PREV_INSN (curr_insn
);
6313 if (NONDEBUG_INSN_P (curr_insn
))
6315 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6316 add_to_hard_reg_set (&live_hard_regs
,
6317 reg
->biggest_mode
, src_regno
);
6319 add_to_hard_reg_set (&live_hard_regs
,
6320 PSEUDO_REGNO_MODE (src_regno
),
6321 reg_renumber
[src_regno
]);
6323 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6326 /* Process used call regs. */
6327 if (curr_id
->arg_hard_regs
!= NULL
)
6328 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6329 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6331 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6332 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6334 for (i
= 0; i
< to_inherit_num
; i
++)
6336 src_regno
= to_inherit
[i
].regno
;
6337 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6338 curr_insn
, to_inherit
[i
].insns
))
6341 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6344 if (update_reloads_num_p
6345 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6348 if ((REG_P (SET_DEST (curr_set
))
6349 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6350 && reg_renumber
[regno
] < 0
6351 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6352 || (REG_P (SET_SRC (curr_set
))
6353 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6354 && reg_renumber
[regno
] < 0
6355 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6357 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6359 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6360 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6361 reg_class_contents
[cl
]);
6364 if (NONDEBUG_INSN_P (curr_insn
))
6368 /* Invalidate invariants with changed regs. */
6369 curr_id
= lra_get_insn_recog_data (curr_insn
);
6370 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6371 if (reg
->type
!= OP_IN
)
6373 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6374 bitmap_set_bit (&invalid_invariant_regs
,
6375 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6377 curr_static_id
= curr_id
->insn_static_data
;
6378 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6379 if (reg
->type
!= OP_IN
)
6380 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6381 if (curr_id
->arg_hard_regs
!= NULL
)
6382 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6383 if (regno
>= FIRST_PSEUDO_REGISTER
)
6384 bitmap_set_bit (&invalid_invariant_regs
,
6385 regno
- FIRST_PSEUDO_REGISTER
);
6387 /* We reached the start of the current basic block. */
6388 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6389 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6391 /* We reached the beginning of the current block -- do
6392 rest of spliting in the current BB. */
6393 to_process
= df_get_live_in (curr_bb
);
6394 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6396 /* We are somewhere in the middle of EBB. */
6397 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6398 curr_bb
, &temp_bitmap
);
6399 to_process
= &temp_bitmap
;
6402 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6404 if ((int) j
>= lra_constraint_new_regno_start
)
6406 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6407 && usage_insns
[j
].check
== curr_usage_insns_check
6408 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6410 if (need_for_split_p (potential_reload_hard_regs
, j
))
6412 if (lra_dump_file
!= NULL
&& head_p
)
6414 fprintf (lra_dump_file
,
6415 " ----------------------------------\n");
6418 if (split_reg (false, j
, bb_note (curr_bb
),
6422 usage_insns
[j
].check
= 0;
6430 /* This value affects EBB forming. If probability of edge from EBB to
6431 a BB is not greater than the following value, we don't add the BB
6433 #define EBB_PROBABILITY_CUTOFF \
6434 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6436 /* Current number of inheritance/split iteration. */
6437 int lra_inheritance_iter
;
6439 /* Entry function for inheritance/split pass. */
6441 lra_inheritance (void)
6444 basic_block bb
, start_bb
;
6447 lra_inheritance_iter
++;
6448 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6450 timevar_push (TV_LRA_INHERITANCE
);
6451 if (lra_dump_file
!= NULL
)
6452 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6453 lra_inheritance_iter
);
6454 curr_usage_insns_check
= 0;
6455 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6456 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6457 usage_insns
[i
].check
= 0;
6458 bitmap_initialize (&check_only_regs
, ®_obstack
);
6459 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6460 bitmap_initialize (&live_regs
, ®_obstack
);
6461 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6462 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6463 FOR_EACH_BB_FN (bb
, cfun
)
6466 if (lra_dump_file
!= NULL
)
6467 fprintf (lra_dump_file
, "EBB");
6468 /* Form a EBB starting with BB. */
6469 bitmap_clear (&ebb_global_regs
);
6470 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6473 if (lra_dump_file
!= NULL
)
6474 fprintf (lra_dump_file
, " %d", bb
->index
);
6475 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6476 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6478 e
= find_fallthru_edge (bb
->succs
);
6481 if (e
->probability
.initialized_p ()
6482 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6486 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6487 if (lra_dump_file
!= NULL
)
6488 fprintf (lra_dump_file
, "\n");
6489 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6490 /* Remember that the EBB head and tail can change in
6492 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6494 bitmap_clear (&ebb_global_regs
);
6495 bitmap_clear (&temp_bitmap
);
6496 bitmap_clear (&live_regs
);
6497 bitmap_clear (&invalid_invariant_regs
);
6498 bitmap_clear (&check_only_regs
);
6501 timevar_pop (TV_LRA_INHERITANCE
);
6506 /* This page contains code to undo failed inheritance/split
6509 /* Current number of iteration undoing inheritance/split. */
6510 int lra_undo_inheritance_iter
;
6512 /* Fix BB live info LIVE after removing pseudos created on pass doing
6513 inheritance/split which are REMOVED_PSEUDOS. */
6515 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6520 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6521 if (bitmap_clear_bit (live
, regno
)
6522 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6523 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6526 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6531 if (GET_CODE (reg
) == SUBREG
)
6532 reg
= SUBREG_REG (reg
);
6538 /* Delete a move INSN with destination reg DREGNO and a previous
6539 clobber insn with the same regno. The inheritance/split code can
6540 generate moves with preceding clobber and when we delete such moves
6541 we should delete the clobber insn too to keep the correct life
6544 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6546 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6548 lra_set_insn_deleted (insn
);
6549 lra_assert (dregno
>= 0);
6550 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6551 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6552 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6553 lra_set_insn_deleted (prev_insn
);
6556 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6557 return true if we did any change. The undo transformations for
6558 inheritance looks like
6562 p <- i, i <- p, and i <- i3
6563 where p is original pseudo from which inheritance pseudo i was
6564 created, i and i3 are removed inheritance pseudos, i2 is another
6565 not removed inheritance pseudo. All split pseudos or other
6566 occurrences of removed inheritance pseudos are changed on the
6567 corresponding original pseudos.
6569 The function also schedules insns changed and created during
6570 inheritance/split pass for processing by the subsequent constraint
6573 remove_inheritance_pseudos (bitmap remove_pseudos
)
6576 int regno
, sregno
, prev_sregno
, dregno
;
6579 rtx_insn
*prev_insn
;
6580 bool change_p
, done_p
;
6582 change_p
= ! bitmap_empty_p (remove_pseudos
);
6583 /* We can not finish the function right away if CHANGE_P is true
6584 because we need to marks insns affected by previous
6585 inheritance/split pass for processing by the subsequent
6587 FOR_EACH_BB_FN (bb
, cfun
)
6589 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6590 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6591 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6593 if (! INSN_P (curr_insn
))
6596 sregno
= dregno
= -1;
6597 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6598 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6600 dregno
= get_regno (SET_DEST (set
));
6601 sregno
= get_regno (SET_SRC (set
));
6604 if (sregno
>= 0 && dregno
>= 0)
6606 if (bitmap_bit_p (remove_pseudos
, dregno
)
6607 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6609 /* invariant inheritance pseudo <- original pseudo */
6610 if (lra_dump_file
!= NULL
)
6612 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6613 dump_insn_slim (lra_dump_file
, curr_insn
);
6614 fprintf (lra_dump_file
, "\n");
6616 delete_move_and_clobber (curr_insn
, dregno
);
6619 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6620 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6622 /* reload pseudo <- invariant inheritance pseudo */
6624 /* We can not just change the source. It might be
6625 an insn different from the move. */
6626 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6627 rtx_insn
*new_insns
= get_insns ();
6629 lra_assert (single_set (new_insns
) != NULL
6630 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6631 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6632 "Changing reload<-invariant inheritance");
6633 delete_move_and_clobber (curr_insn
, dregno
);
6636 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6637 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6638 || (bitmap_bit_p (remove_pseudos
, dregno
)
6639 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6640 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6641 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6642 || (bitmap_bit_p (remove_pseudos
, dregno
)
6643 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6644 /* One of the following cases:
6645 original <- removed inheritance pseudo
6646 removed inherit pseudo <- another removed inherit pseudo
6647 removed inherit pseudo <- original pseudo
6649 removed_split_pseudo <- original_reg
6650 original_reg <- removed_split_pseudo */
6652 if (lra_dump_file
!= NULL
)
6654 fprintf (lra_dump_file
, " Removing %s:\n",
6655 bitmap_bit_p (&lra_split_regs
, sregno
)
6656 || bitmap_bit_p (&lra_split_regs
, dregno
)
6657 ? "split" : "inheritance");
6658 dump_insn_slim (lra_dump_file
, curr_insn
);
6660 delete_move_and_clobber (curr_insn
, dregno
);
6663 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6664 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6666 /* Search the following pattern:
6667 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6668 original_pseudo <- inherit_or_split_pseudo1
6669 where the 2nd insn is the current insn and
6670 inherit_or_split_pseudo2 is not removed. If it is found,
6671 change the current insn onto:
6672 original_pseudo <- inherit_or_split_pseudo2. */
6673 for (prev_insn
= PREV_INSN (curr_insn
);
6674 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6675 prev_insn
= PREV_INSN (prev_insn
))
6677 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6678 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6679 /* There should be no subregs in insn we are
6680 searching because only the original reg might
6681 be in subreg when we changed the mode of
6682 load/store for splitting. */
6683 && REG_P (SET_DEST (prev_set
))
6684 && REG_P (SET_SRC (prev_set
))
6685 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6686 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6687 >= FIRST_PSEUDO_REGISTER
)
6688 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6690 /* As we consider chain of inheritance or
6691 splitting described in above comment we should
6692 check that sregno and prev_sregno were
6693 inheritance/split pseudos created from the
6694 same original regno. */
6695 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6696 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6697 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6698 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6700 lra_assert (GET_MODE (SET_SRC (prev_set
))
6701 == GET_MODE (regno_reg_rtx
[sregno
]));
6702 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6703 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6705 SET_SRC (set
) = SET_SRC (prev_set
);
6706 /* As we are finishing with processing the insn
6707 here, check the destination too as it might
6708 inheritance pseudo for another pseudo. */
6709 if (bitmap_bit_p (remove_pseudos
, dregno
)
6710 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6712 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6714 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6715 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6717 SET_DEST (set
) = restore_rtx
;
6719 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6720 lra_set_used_insn_alternative_by_uid
6721 (INSN_UID (curr_insn
), -1);
6723 if (lra_dump_file
!= NULL
)
6725 fprintf (lra_dump_file
, " Change reload insn:\n");
6726 dump_insn_slim (lra_dump_file
, curr_insn
);
6733 struct lra_insn_reg
*reg
;
6734 bool restored_regs_p
= false;
6735 bool kept_regs_p
= false;
6737 curr_id
= lra_get_insn_recog_data (curr_insn
);
6738 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6741 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6742 if (restore_rtx
!= NULL_RTX
)
6744 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6746 lra_substitute_pseudo_within_insn
6747 (curr_insn
, regno
, restore_rtx
, false);
6748 restored_regs_p
= true;
6754 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6756 /* The instruction has changed since the previous
6757 constraints pass. */
6758 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6759 lra_set_used_insn_alternative_by_uid
6760 (INSN_UID (curr_insn
), -1);
6762 else if (restored_regs_p
)
6763 /* The instruction has been restored to the form that
6764 it had during the previous constraints pass. */
6765 lra_update_insn_regno_info (curr_insn
);
6766 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6768 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6769 dump_insn_slim (lra_dump_file
, curr_insn
);
6777 /* If optional reload pseudos failed to get a hard register or was not
6778 inherited, it is better to remove optional reloads. We do this
6779 transformation after undoing inheritance to figure out necessity to
6780 remove optional reloads easier. Return true if we do any
6783 undo_optional_reloads (void)
6785 bool change_p
, keep_p
;
6786 unsigned int regno
, uid
;
6787 bitmap_iterator bi
, bi2
;
6790 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6792 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6793 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6796 /* Keep optional reloads from previous subpasses. */
6797 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6798 /* If the original pseudo changed its allocation, just
6799 removing the optional pseudo is dangerous as the original
6800 pseudo will have longer live range. */
6801 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6803 else if (reg_renumber
[regno
] >= 0)
6804 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6806 insn
= lra_insn_recog_data
[uid
]->insn
;
6807 if ((set
= single_set (insn
)) == NULL_RTX
)
6809 src
= SET_SRC (set
);
6810 dest
= SET_DEST (set
);
6811 if (! REG_P (src
) || ! REG_P (dest
))
6813 if (REGNO (dest
) == regno
6814 /* Ignore insn for optional reloads itself. */
6815 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6816 /* Check only inheritance on last inheritance pass. */
6817 && (int) REGNO (src
) >= new_regno_start
6818 /* Check that the optional reload was inherited. */
6819 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6827 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6828 if (lra_dump_file
!= NULL
)
6829 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6832 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6833 auto_bitmap
insn_bitmap (®_obstack
);
6834 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6836 if (lra_dump_file
!= NULL
)
6837 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6838 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6839 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
6841 insn
= lra_insn_recog_data
[uid
]->insn
;
6842 if ((set
= single_set (insn
)) != NULL_RTX
)
6844 src
= SET_SRC (set
);
6845 dest
= SET_DEST (set
);
6846 if (REG_P (src
) && REG_P (dest
)
6847 && ((REGNO (src
) == regno
6848 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6850 || (REGNO (dest
) == regno
6851 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6854 if (lra_dump_file
!= NULL
)
6856 fprintf (lra_dump_file
, " Deleting move %u\n",
6858 dump_insn_slim (lra_dump_file
, insn
);
6860 delete_move_and_clobber (insn
, REGNO (dest
));
6863 /* We should not worry about generation memory-memory
6864 moves here as if the corresponding inheritance did
6865 not work (inheritance pseudo did not get a hard reg),
6866 we remove the inheritance pseudo and the optional
6869 lra_substitute_pseudo_within_insn
6870 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6871 lra_update_insn_regno_info (insn
);
6872 if (lra_dump_file
!= NULL
)
6874 fprintf (lra_dump_file
,
6875 " Restoring original insn:\n");
6876 dump_insn_slim (lra_dump_file
, insn
);
6880 /* Clear restore_regnos. */
6881 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6882 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6886 /* Entry function for undoing inheritance/split transformation. Return true
6887 if we did any RTL change in this pass. */
6889 lra_undo_inheritance (void)
6893 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6898 lra_undo_inheritance_iter
++;
6899 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6901 if (lra_dump_file
!= NULL
)
6902 fprintf (lra_dump_file
,
6903 "\n********** Undoing inheritance #%d: **********\n\n",
6904 lra_undo_inheritance_iter
);
6905 auto_bitmap
remove_pseudos (®_obstack
);
6906 n_inherit
= n_all_inherit
= 0;
6907 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6908 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6911 if (reg_renumber
[regno
] < 0
6912 /* If the original pseudo changed its allocation, just
6913 removing inheritance is dangerous as for changing
6914 allocation we used shorter live-ranges. */
6915 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6916 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6917 bitmap_set_bit (remove_pseudos
, regno
);
6921 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6922 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6923 n_inherit
, n_all_inherit
,
6924 (double) n_inherit
/ n_all_inherit
* 100);
6925 n_split
= n_all_split
= 0;
6926 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6927 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6929 int restore_regno
= REGNO (restore_rtx
);
6932 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6933 ? reg_renumber
[restore_regno
] : restore_regno
);
6934 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6935 bitmap_set_bit (remove_pseudos
, regno
);
6939 if (lra_dump_file
!= NULL
)
6940 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6941 regno
, restore_regno
);
6944 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6945 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6946 n_split
, n_all_split
,
6947 (double) n_split
/ n_all_split
* 100);
6948 change_p
= remove_inheritance_pseudos (remove_pseudos
);
6949 /* Clear restore_regnos. */
6950 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6951 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6952 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6953 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6954 change_p
= undo_optional_reloads () || change_p
;