1 /* IRA hard register and memory cost calculation for allocnos.
2 Copyright (C) 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
41 /* The file contains code is similar to one in regclass but the code
42 works on the allocno basis. */
44 #ifdef FORBIDDEN_INC_DEC_CLASSES
45 /* Indexed by n, is TRUE if allocno with number N is used in an
46 auto-inc or auto-dec context. */
47 static bool *in_inc_dec
;
50 /* The `costs' struct records the cost of using hard registers of each
51 class considered for the calculation and of using memory for each
56 /* Costs for register classes start here. We process only some
57 register classes (cover classes on the 1st cost calculation
58 iteration and important classes on the 2nd iteration). */
62 /* Initialized once. It is a maximal possible size of the allocated
64 static int max_struct_costs_size
;
66 /* Allocated and initialized once, and used to initialize cost values
68 static struct costs
*init_cost
;
70 /* Allocated once, and used for temporary purposes. */
71 static struct costs
*temp_costs
;
73 /* Allocated once, and used for the cost calculation. */
74 static struct costs
*op_costs
[MAX_RECOG_OPERANDS
];
75 static struct costs
*this_op_costs
[MAX_RECOG_OPERANDS
];
77 /* Record the initial and accumulated cost of each class for each
79 static struct costs
*total_costs
;
81 /* Classes used for cost calculation. They may be different on
82 different iterations of the cost calculations or in different
83 optimization modes. */
84 static enum reg_class
*cost_classes
;
86 /* The size of the previous array. */
87 static int cost_classes_num
;
89 /* Map: cost class -> order number (they start with 0) of the cost
91 static int cost_class_nums
[N_REG_CLASSES
];
93 /* It is the current size of struct costs. */
94 static int struct_costs_size
;
96 /* Return pointer to structure containing costs of allocno with given
98 #define COSTS_OF_ALLOCNO(arr, num) \
99 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
101 /* Record register class preferences of each allocno. Null value
102 means no preferences. It happens on the 1st iteration of the cost
104 static enum reg_class
*allocno_pref
;
106 /* Allocated buffers for allocno_pref. */
107 static enum reg_class
*allocno_pref_buffer
;
109 /* Execution frequency of the current insn. */
110 static int frequency
;
114 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
115 TO_P is FALSE) a register of class CLASS in mode MODE. X must not
116 be a pseudo register. */
118 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class
class, bool to_p
,
119 secondary_reload_info
*prev_sri
)
121 secondary_reload_info sri
;
122 enum reg_class secondary_class
= NO_REGS
;
124 /* If X is a SCRATCH, there is actually nothing to move since we are
125 assuming optimal allocation. */
126 if (GET_CODE (x
) == SCRATCH
)
129 /* Get the class we will actually use for a reload. */
130 class = PREFERRED_RELOAD_CLASS (x
, class);
132 /* If we need a secondary reload for an intermediate, the cost is
133 that to load the input into the intermediate register, then to
135 sri
.prev_sri
= prev_sri
;
137 secondary_class
= targetm
.secondary_reload (to_p
, x
, class, mode
, &sri
);
139 if (ira_register_move_cost
[mode
] == NULL
)
140 ira_init_register_move_cost (mode
);
142 if (secondary_class
!= NO_REGS
)
143 return (move_cost
[mode
][secondary_class
][class] + sri
.extra_cost
144 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
146 /* For memory, use the memory move cost, for (hard) registers, use
147 the cost to move between the register classes, and use 2 for
148 everything else (constants). */
149 if (MEM_P (x
) || class == NO_REGS
)
150 return sri
.extra_cost
+ ira_memory_move_cost
[mode
][class][to_p
!= 0];
153 (sri
.extra_cost
+ move_cost
[mode
][REGNO_REG_CLASS (REGNO (x
))][class]);
155 /* If this is a constant, we may eventually want to call rtx_cost
157 return sri
.extra_cost
+ COSTS_N_INSNS (1);
162 /* Record the cost of using memory or hard registers of various
163 classes for the operands in INSN.
165 N_ALTS is the number of alternatives.
166 N_OPS is the number of operands.
167 OPS is an array of the operands.
168 MODES are the modes of the operands, in case any are VOIDmode.
169 CONSTRAINTS are the constraints to use for the operands. This array
170 is modified by this procedure.
172 This procedure works alternative by alternative. For each
173 alternative we assume that we will be able to allocate all allocnos
174 to their ideal register class and calculate the cost of using that
175 alternative. Then we compute, for each operand that is a
176 pseudo-register, the cost of having the allocno allocated to each
177 register class and using it in that alternative. To this cost is
178 added the cost of the alternative.
180 The cost of each class for this insn is its lowest cost among all
183 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
184 enum machine_mode
*modes
, const char **constraints
,
185 rtx insn
, struct costs
**op_costs
,
186 enum reg_class
*allocno_pref
)
192 /* Process each alternative, each time minimizing an operand's cost
193 with the cost for each operand in that alternative. */
194 for (alt
= 0; alt
< n_alts
; alt
++)
196 enum reg_class classes
[MAX_RECOG_OPERANDS
];
197 int allows_mem
[MAX_RECOG_OPERANDS
];
200 int alt_cost
= 0, op_cost_add
;
202 for (i
= 0; i
< n_ops
; i
++)
205 const char *p
= constraints
[i
];
207 enum machine_mode mode
= modes
[i
];
211 /* Initially show we know nothing about the register class. */
212 classes
[i
] = NO_REGS
;
215 /* If this operand has no constraints at all, we can
216 conclude nothing about it since anything is valid. */
219 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
220 memset (this_op_costs
[i
], 0, struct_costs_size
);
224 /* If this alternative is only relevant when this operand
225 matches a previous operand, we do different things
226 depending on whether this operand is a allocno-reg or not.
227 We must process any modifiers for the operand before we
228 can make this test. */
229 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
232 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
234 /* Copy class and whether memory is allowed from the
235 matching alternative. Then perform any needed cost
236 computations and/or adjustments. */
238 classes
[i
] = classes
[j
];
239 allows_mem
[i
] = allows_mem
[j
];
241 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
243 /* If this matches the other operand, we have no
244 added cost and we win. */
245 if (rtx_equal_p (ops
[j
], op
))
247 /* If we can put the other operand into a register,
248 add to the cost of this alternative the cost to
249 copy this operand to the register used for the
251 else if (classes
[j
] != NO_REGS
)
253 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
257 else if (! REG_P (ops
[j
])
258 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
260 /* This op is an allocno but the one it matches is
263 /* If we can't put the other operand into a
264 register, this alternative can't be used. */
266 if (classes
[j
] == NO_REGS
)
268 /* Otherwise, add to the cost of this alternative
269 the cost to copy the other operand to the hard
270 register used for this operand. */
272 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
276 /* The costs of this operand are not the same as the
277 other operand since move costs are not symmetric.
278 Moreover, if we cannot tie them, this alternative
279 needs to do a copy, which is one insn. */
280 struct costs
*pp
= this_op_costs
[i
];
282 if (ira_register_move_cost
[mode
] == NULL
)
283 ira_init_register_move_cost (mode
);
285 for (k
= 0; k
< cost_classes_num
; k
++)
287 class = cost_classes
[k
];
289 = ((recog_data
.operand_type
[i
] != OP_OUT
290 ? ira_may_move_in_cost
[mode
][class]
291 [classes
[i
]] * frequency
: 0)
292 + (recog_data
.operand_type
[i
] != OP_IN
293 ? ira_may_move_out_cost
[mode
][classes
[i
]]
294 [class] * frequency
: 0));
297 /* If the alternative actually allows memory, make
298 things a bit cheaper since we won't need an extra
301 = ((recog_data
.operand_type
[i
] != OP_IN
302 ? ira_memory_move_cost
[mode
][classes
[i
]][0] : 0)
303 + (recog_data
.operand_type
[i
] != OP_OUT
304 ? ira_memory_move_cost
[mode
][classes
[i
]][1] : 0)
305 - allows_mem
[i
]) * frequency
;
306 /* If we have assigned a class to this allocno in our
307 first pass, add a cost to this alternative
308 corresponding to what we would add if this allocno
309 were not in the appropriate class. We could use
310 cover class here but it is less accurate
314 enum reg_class pref_class
315 = allocno_pref
[ALLOCNO_NUM
316 (ira_curr_regno_allocno_map
319 if (pref_class
== NO_REGS
)
321 += ((recog_data
.operand_type
[i
] != OP_IN
322 ? ira_memory_move_cost
[mode
][classes
[i
]][0]
324 + (recog_data
.operand_type
[i
] != OP_OUT
325 ? ira_memory_move_cost
[mode
][classes
[i
]][1]
327 else if (ira_reg_class_intersect
328 [pref_class
][classes
[i
]] == NO_REGS
)
329 alt_cost
+= (ira_register_move_cost
330 [mode
][pref_class
][classes
[i
]]);
332 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
333 && ! find_reg_note (insn
, REG_DEAD
, op
))
336 /* This is in place of ordinary cost computation for
337 this operand, so skip to the end of the
338 alternative (should be just one character). */
339 while (*p
&& *p
++ != ',')
347 /* Scan all the constraint letters. See if the operand
348 matches any of the constraints. Collect the valid
349 register classes and see if this operand accepts
358 /* Ignore the next letter for this pass. */
364 case '!': case '#': case '&':
365 case '0': case '1': case '2': case '3': case '4':
366 case '5': case '6': case '7': case '8': case '9':
371 win
= address_operand (op
, GET_MODE (op
));
372 /* We know this operand is an address, so we want it
373 to be allocated to a register that can be the
374 base of an address, i.e. BASE_REG_CLASS. */
376 = ira_reg_class_union
[classes
[i
]]
377 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
380 case 'm': case 'o': case 'V':
381 /* It doesn't seem worth distinguishing between
382 offsettable and non-offsettable addresses
391 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
392 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
398 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
399 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
405 if (GET_CODE (op
) == CONST_DOUBLE
406 || (GET_CODE (op
) == CONST_VECTOR
407 && (GET_MODE_CLASS (GET_MODE (op
))
408 == MODE_VECTOR_FLOAT
)))
414 if (GET_CODE (op
) == CONST_DOUBLE
415 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
420 if (GET_CODE (op
) == CONST_INT
421 || (GET_CODE (op
) == CONST_DOUBLE
422 && GET_MODE (op
) == VOIDmode
))
427 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
432 if (GET_CODE (op
) == CONST_INT
433 || (GET_CODE (op
) == CONST_DOUBLE
434 && GET_MODE (op
) == VOIDmode
))
446 if (GET_CODE (op
) == CONST_INT
447 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
458 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
462 classes
[i
] = ira_reg_class_union
[classes
[i
]][GENERAL_REGS
];
466 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
467 classes
[i
] = ira_reg_class_union
[classes
[i
]]
468 [REG_CLASS_FROM_CONSTRAINT (c
, p
)];
469 #ifdef EXTRA_CONSTRAINT_STR
470 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
473 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
475 /* Every MEM can be reloaded to fit. */
480 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
482 /* Every address can be reloaded to fit. */
484 if (address_operand (op
, GET_MODE (op
)))
486 /* We know this operand is an address, so we
487 want it to be allocated to a hard register
488 that can be the base of an address,
489 i.e. BASE_REG_CLASS. */
491 = ira_reg_class_union
[classes
[i
]]
492 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
497 p
+= CONSTRAINT_LEN (c
, p
);
504 /* How we account for this operand now depends on whether it
505 is a pseudo register or not. If it is, we first check if
506 any register classes are valid. If not, we ignore this
507 alternative, since we want to assume that all allocnos get
508 allocated for register preferencing. If some register
509 class is valid, compute the costs of moving the allocno
511 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
513 if (classes
[i
] == NO_REGS
)
515 /* We must always fail if the operand is a REG, but
516 we did not find a suitable class.
518 Otherwise we may perform an uninitialized read
519 from this_op_costs after the `continue' statement
525 struct costs
*pp
= this_op_costs
[i
];
527 if (ira_register_move_cost
[mode
] == NULL
)
528 ira_init_register_move_cost (mode
);
530 for (k
= 0; k
< cost_classes_num
; k
++)
532 class = cost_classes
[k
];
534 = ((recog_data
.operand_type
[i
] != OP_OUT
535 ? ira_may_move_in_cost
[mode
][class]
536 [classes
[i
]] * frequency
: 0)
537 + (recog_data
.operand_type
[i
] != OP_IN
538 ? ira_may_move_out_cost
[mode
][classes
[i
]]
539 [class] * frequency
: 0));
542 /* If the alternative actually allows memory, make
543 things a bit cheaper since we won't need an extra
546 = ((recog_data
.operand_type
[i
] != OP_IN
547 ? ira_memory_move_cost
[mode
][classes
[i
]][0] : 0)
548 + (recog_data
.operand_type
[i
] != OP_OUT
549 ? ira_memory_move_cost
[mode
][classes
[i
]][1] : 0)
550 - allows_mem
[i
]) * frequency
;
551 /* If we have assigned a class to this allocno in our
552 first pass, add a cost to this alternative
553 corresponding to what we would add if this allocno
554 were not in the appropriate class. We could use
555 cover class here but it is less accurate
559 enum reg_class pref_class
560 = allocno_pref
[ALLOCNO_NUM
561 (ira_curr_regno_allocno_map
564 if (pref_class
== NO_REGS
)
566 += ((recog_data
.operand_type
[i
] != OP_IN
567 ? ira_memory_move_cost
[mode
][classes
[i
]][0]
569 + (recog_data
.operand_type
[i
] != OP_OUT
570 ? ira_memory_move_cost
[mode
][classes
[i
]][1]
572 else if (ira_reg_class_intersect
[pref_class
][classes
[i
]]
574 alt_cost
+= (ira_register_move_cost
575 [mode
][pref_class
][classes
[i
]]);
580 /* Otherwise, if this alternative wins, either because we
581 have already determined that or if we have a hard
582 register of the proper class, there is no cost for this
584 else if (win
|| (REG_P (op
)
585 && reg_fits_class_p (op
, classes
[i
],
589 /* If registers are valid, the cost of this alternative
590 includes copying the object to and/or from a
592 else if (classes
[i
] != NO_REGS
)
594 if (recog_data
.operand_type
[i
] != OP_OUT
)
595 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
597 if (recog_data
.operand_type
[i
] != OP_IN
)
598 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
600 /* The only other way this alternative can be used is if
601 this is a constant that could be placed into memory. */
602 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
603 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
611 op_cost_add
= alt_cost
* frequency
;
612 /* Finally, update the costs with the information we've
613 calculated about this alternative. */
614 for (i
= 0; i
< n_ops
; i
++)
615 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
617 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
618 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
620 pp
->mem_cost
= MIN (pp
->mem_cost
,
621 (qq
->mem_cost
+ op_cost_add
) * scale
);
623 for (k
= 0; k
< cost_classes_num
; k
++)
625 = MIN (pp
->cost
[k
], (qq
->cost
[k
] + op_cost_add
) * scale
);
629 /* If this insn is a single set copying operand 1 to operand 0 and
630 one operand is an allocno with the other a hard reg or an allocno
631 that prefers a hard register that is in its own register class
632 then we may want to adjust the cost of that register class to -1.
634 Avoid the adjustment if the source does not die to avoid
635 stressing of register allocator by preferrencing two colliding
636 registers into single class.
638 Also avoid the adjustment if a copy between hard registers of the
639 class is expensive (ten times the cost of a default copy is
640 considered arbitrarily expensive). This avoids losing when the
641 preferred class is very expensive as the source of a copy
643 if ((set
= single_set (insn
)) != 0
644 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
645 && REG_P (ops
[0]) && REG_P (ops
[1])
646 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
647 for (i
= 0; i
<= 1; i
++)
648 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
650 unsigned int regno
= REGNO (ops
[!i
]);
651 enum machine_mode mode
= GET_MODE (ops
[!i
]);
655 if (regno
< FIRST_PSEUDO_REGISTER
)
656 for (k
= 0; k
< cost_classes_num
; k
++)
658 class = cost_classes
[k
];
659 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
660 && (reg_class_size
[class]
661 == (unsigned) CLASS_MAX_NREGS (class, mode
)))
663 if (reg_class_size
[class] == 1)
664 op_costs
[i
]->cost
[k
] = -frequency
;
668 nr
< (unsigned) hard_regno_nregs
[regno
][mode
];
670 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
674 if (nr
== (unsigned) hard_regno_nregs
[regno
][mode
])
675 op_costs
[i
]->cost
[k
] = -frequency
;
684 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
686 ok_for_index_p_nonstrict (rtx reg
)
688 unsigned regno
= REGNO (reg
);
690 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
693 /* A version of regno_ok_for_base_p for use here, when all
694 pseudo-registers should count as OK. Arguments as for
695 regno_ok_for_base_p. */
697 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
698 enum rtx_code outer_code
, enum rtx_code index_code
)
700 unsigned regno
= REGNO (reg
);
702 if (regno
>= FIRST_PSEUDO_REGISTER
)
704 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
707 /* Record the pseudo registers we must reload into hard registers in a
708 subexpression of a memory address, X.
710 If CONTEXT is 0, we are looking at the base part of an address,
711 otherwise we are looking at the index part.
713 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
714 give the context that the rtx appears in. These three arguments
715 are passed down to base_reg_class.
717 SCALE is twice the amount to multiply the cost by (it is twice so
718 we can represent half-cost adjustments). */
720 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
721 enum rtx_code outer_code
, enum rtx_code index_code
,
724 enum rtx_code code
= GET_CODE (x
);
725 enum reg_class
class;
728 class = INDEX_REG_CLASS
;
730 class = base_reg_class (mode
, outer_code
, index_code
);
743 /* When we have an address that is a sum, we must determine
744 whether registers are "base" or "index" regs. If there is a
745 sum of two registers, we must choose one to be the "base".
746 Luckily, we can use the REG_POINTER to make a good choice
747 most of the time. We only need to do this on machines that
748 can have two registers in an address and where the base and
749 index register classes are different.
751 ??? This code used to set REGNO_POINTER_FLAG in some cases,
752 but that seems bogus since it should only be set when we are
753 sure the register is being used as a pointer. */
755 rtx arg0
= XEXP (x
, 0);
756 rtx arg1
= XEXP (x
, 1);
757 enum rtx_code code0
= GET_CODE (arg0
);
758 enum rtx_code code1
= GET_CODE (arg1
);
760 /* Look inside subregs. */
762 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
764 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
766 /* If this machine only allows one register per address, it
767 must be in the first operand. */
768 if (MAX_REGS_PER_ADDRESS
== 1)
769 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
771 /* If index and base registers are the same on this machine,
772 just record registers in any non-constant operands. We
773 assume here, as well as in the tests below, that all
774 addresses are in canonical form. */
775 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
777 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
778 if (! CONSTANT_P (arg1
))
779 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
782 /* If the second operand is a constant integer, it doesn't
783 change what class the first operand must be. */
784 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
785 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
786 /* If the second operand is a symbolic constant, the first
787 operand must be an index register. */
788 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
789 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
790 /* If both operands are registers but one is already a hard
791 register of index or reg-base class, give the other the
792 class that the hard register is not. */
793 else if (code0
== REG
&& code1
== REG
794 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
795 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
796 || ok_for_index_p_nonstrict (arg0
)))
797 record_address_regs (mode
, arg1
,
798 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
801 else if (code0
== REG
&& code1
== REG
802 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
803 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
804 || ok_for_index_p_nonstrict (arg1
)))
805 record_address_regs (mode
, arg0
,
806 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
809 /* If one operand is known to be a pointer, it must be the
810 base with the other operand the index. Likewise if the
811 other operand is a MULT. */
812 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
814 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
815 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
817 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
819 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
820 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
822 /* Otherwise, count equal chances that each might be a base or
823 index register. This case should be rare. */
826 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
827 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
828 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
829 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
834 /* Double the importance of an allocno that is incremented or
835 decremented, since it would take two extra insns if it ends
836 up in the wrong place. */
839 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
840 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
841 if (REG_P (XEXP (XEXP (x
, 1), 1)))
842 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
850 /* Double the importance of an allocno that is incremented or
851 decremented, since it would take two extra insns if it ends
852 up in the wrong place. If the operand is a pseudo-register,
853 show it is being used in an INC_DEC context. */
854 #ifdef FORBIDDEN_INC_DEC_CLASSES
855 if (REG_P (XEXP (x
, 0))
856 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
857 in_inc_dec
[ALLOCNO_NUM (ira_curr_regno_allocno_map
858 [REGNO (XEXP (x
, 0))])] = true;
860 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
868 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
871 pp
= COSTS_OF_ALLOCNO (total_costs
,
872 ALLOCNO_NUM (ira_curr_regno_allocno_map
874 pp
->mem_cost
+= (ira_memory_move_cost
[Pmode
][class][1] * scale
) / 2;
875 if (ira_register_move_cost
[Pmode
] == NULL
)
876 ira_init_register_move_cost (Pmode
);
877 for (k
= 0; k
< cost_classes_num
; k
++)
881 += (ira_may_move_in_cost
[Pmode
][i
][class] * scale
) / 2;
888 const char *fmt
= GET_RTX_FORMAT (code
);
890 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
892 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
900 /* Calculate the costs of insn operands. */
902 record_operand_costs (rtx insn
, struct costs
**op_costs
,
903 enum reg_class
*allocno_pref
)
905 const char *constraints
[MAX_RECOG_OPERANDS
];
906 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
909 for (i
= 0; i
< recog_data
.n_operands
; i
++)
911 constraints
[i
] = recog_data
.constraints
[i
];
912 modes
[i
] = recog_data
.operand_mode
[i
];
915 /* If we get here, we are set up to record the costs of all the
916 operands for this insn. Start by initializing the costs. Then
917 handle any address registers. Finally record the desired classes
918 for any allocnos, doing it twice if some pair of operands are
920 for (i
= 0; i
< recog_data
.n_operands
; i
++)
922 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
924 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
925 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
927 if (MEM_P (recog_data
.operand
[i
]))
928 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
929 XEXP (recog_data
.operand
[i
], 0),
930 0, MEM
, SCRATCH
, frequency
* 2);
931 else if (constraints
[i
][0] == 'p'
932 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0],
934 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
935 SCRATCH
, frequency
* 2);
938 /* Check for commutative in a separate loop so everything will have
939 been initialized. We must do this even if one operand is a
940 constant--see addsi3 in m68k.md. */
941 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
942 if (constraints
[i
][0] == '%')
944 const char *xconstraints
[MAX_RECOG_OPERANDS
];
947 /* Handle commutative operands by swapping the constraints.
948 We assume the modes are the same. */
949 for (j
= 0; j
< recog_data
.n_operands
; j
++)
950 xconstraints
[j
] = constraints
[j
];
952 xconstraints
[i
] = constraints
[i
+1];
953 xconstraints
[i
+1] = constraints
[i
];
954 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
955 recog_data
.operand
, modes
,
956 xconstraints
, insn
, op_costs
, allocno_pref
);
958 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
959 recog_data
.operand
, modes
,
960 constraints
, insn
, op_costs
, allocno_pref
);
965 /* Process one insn INSN. Scan it and record each time it would save
966 code to put a certain allocnos in a certain class. Return the last
967 insn processed, so that the scan can be continued from there. */
969 scan_one_insn (rtx insn
)
971 enum rtx_code pat_code
;
978 pat_code
= GET_CODE (PATTERN (insn
));
979 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
980 || pat_code
== ADDR_VEC
|| pat_code
== ADDR_DIFF_VEC
)
983 set
= single_set (insn
);
986 /* If this insn loads a parameter from its stack slot, then it
987 represents a savings, rather than a cost, if the parameter is
988 stored in memory. Record this fact. */
989 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
990 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
991 && MEM_P (XEXP (note
, 0)))
993 COSTS_OF_ALLOCNO (total_costs
,
994 ALLOCNO_NUM (ira_curr_regno_allocno_map
995 [REGNO (SET_DEST (set
))]))->mem_cost
996 -= (ira_memory_move_cost
[GET_MODE (SET_DEST (set
))][GENERAL_REGS
][1]
998 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
999 0, MEM
, SCRATCH
, frequency
* 2);
1002 record_operand_costs (insn
, op_costs
, allocno_pref
);
1004 /* Now add the cost for each operand to the total costs for its
1006 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1007 if (REG_P (recog_data
.operand
[i
])
1008 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1010 int regno
= REGNO (recog_data
.operand
[i
]);
1012 = COSTS_OF_ALLOCNO (total_costs
,
1013 ALLOCNO_NUM (ira_curr_regno_allocno_map
[regno
]));
1014 struct costs
*q
= op_costs
[i
];
1016 p
->mem_cost
+= q
->mem_cost
;
1017 for (k
= 0; k
< cost_classes_num
; k
++)
1018 p
->cost
[k
] += q
->cost
[k
];
1026 /* Print allocnos costs to file F. */
1028 print_costs (FILE *f
)
1032 ira_allocno_iterator ai
;
1035 FOR_EACH_ALLOCNO (a
, ai
)
1039 int regno
= ALLOCNO_REGNO (a
);
1041 i
= ALLOCNO_NUM (a
);
1042 fprintf (f
, " a%d(r%d,", i
, regno
);
1043 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1044 fprintf (f
, "b%d", bb
->index
);
1046 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1047 fprintf (f
, ") costs:");
1048 for (k
= 0; k
< cost_classes_num
; k
++)
1050 class = cost_classes
[k
];
1051 if (contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (regno
)]
1052 #ifdef FORBIDDEN_INC_DEC_CLASSES
1053 && (! in_inc_dec
[i
] || ! forbidden_inc_dec_class
[class])
1055 #ifdef CANNOT_CHANGE_MODE_CLASS
1056 && ! invalid_mode_change_p (regno
, (enum reg_class
) class,
1057 PSEUDO_REGNO_MODE (regno
))
1060 fprintf (f
, " %s:%d", reg_class_names
[class],
1061 COSTS_OF_ALLOCNO (total_costs
, i
)->cost
[k
]);
1063 fprintf (f
, " MEM:%i\n", COSTS_OF_ALLOCNO (total_costs
, i
)->mem_cost
);
1067 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1070 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1075 bb
= loop_tree_node
->bb
;
1078 frequency
= REG_FREQ_FROM_BB (bb
);
1081 FOR_BB_INSNS (bb
, insn
)
1082 insn
= scan_one_insn (insn
);
1085 /* Find costs of register classes and memory for allocnos and their
1088 find_allocno_class_costs (void)
1095 #ifdef FORBIDDEN_INC_DEC_CLASSES
1096 in_inc_dec
= ira_allocate (sizeof (bool) * ira_allocnos_num
);
1097 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1099 allocno_pref
= NULL
;
1100 /* Normally we scan the insns once and determine the best class to
1101 use for each allocno. However, if -fexpensive-optimizations are
1102 on, we do so twice, the second time using the tentative best
1103 classes to guide the selection. */
1104 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1106 if (internal_flag_ira_verbose
> 0 && ira_dump_file
)
1107 fprintf (ira_dump_file
, "\nPass %i for finding allocno costs\n\n",
1109 /* We could use only cover classes. Unfortunately it does not
1110 work well for some targets where some subclass of cover class
1111 is costly and wrong cover class is chosen. */
1112 for (cost_classes_num
= 0;
1113 cost_classes_num
< ira_important_classes_num
;
1116 cost_classes
[cost_classes_num
]
1117 = ira_important_classes
[cost_classes_num
];
1118 cost_class_nums
[cost_classes
[cost_classes_num
]]
1122 = sizeof (struct costs
) + sizeof (int) * (cost_classes_num
- 1);
1123 /* Zero out our accumulation of the cost of each class for each
1125 memset (total_costs
, 0, ira_allocnos_num
* struct_costs_size
);
1126 #ifdef FORBIDDEN_INC_DEC_CLASSES
1127 memset (in_inc_dec
, 0, ira_allocnos_num
* sizeof (bool));
1130 /* Scan the instructions and record each time it would save code
1131 to put a certain allocno in a certain class. */
1132 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1133 process_bb_node_for_costs
, NULL
);
1136 allocno_pref
= allocno_pref_buffer
;
1138 /* Now for each allocno look at how desirable each class is and
1139 find which class is preferred. */
1140 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1142 ira_allocno_t a
, parent_a
;
1143 int class, a_num
, parent_a_num
;
1144 ira_loop_tree_node_t parent
;
1146 enum reg_class best
, alt_class
, common_class
;
1147 #ifdef FORBIDDEN_INC_DEC_CLASSES
1148 int inc_dec_p
= false;
1151 if (ira_regno_allocno_map
[i
] == NULL
)
1153 memset (temp_costs
, 0, struct_costs_size
);
1154 /* Find cost of all allocnos with the same regno. */
1155 for (a
= ira_regno_allocno_map
[i
];
1157 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1159 a_num
= ALLOCNO_NUM (a
);
1160 if ((flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1161 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
)
1162 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1163 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
)
1165 /* Propagate costs to upper levels in the region
1167 parent_a_num
= ALLOCNO_NUM (parent_a
);
1168 for (k
= 0; k
< cost_classes_num
; k
++)
1169 COSTS_OF_ALLOCNO (total_costs
, parent_a_num
)->cost
[k
]
1170 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1171 COSTS_OF_ALLOCNO (total_costs
, parent_a_num
)->mem_cost
1172 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->mem_cost
;
1174 for (k
= 0; k
< cost_classes_num
; k
++)
1176 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1177 temp_costs
->mem_cost
1178 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->mem_cost
;
1179 #ifdef FORBIDDEN_INC_DEC_CLASSES
1180 if (in_inc_dec
[a_num
])
1184 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1186 alt_class
= NO_REGS
;
1187 /* Find best common class for all allocnos with the same
1189 for (k
= 0; k
< cost_classes_num
; k
++)
1191 class = cost_classes
[k
];
1192 /* Ignore classes that are too small for this operand or
1193 invalid for an operand that was auto-incremented. */
1194 if (! contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1195 #ifdef FORBIDDEN_INC_DEC_CLASSES
1196 || (inc_dec_p
&& forbidden_inc_dec_class
[class])
1198 #ifdef CANNOT_CHANGE_MODE_CLASS
1199 || invalid_mode_change_p (i
, (enum reg_class
) class,
1200 PSEUDO_REGNO_MODE (i
))
1204 if (temp_costs
->cost
[k
] < best_cost
)
1206 best_cost
= temp_costs
->cost
[k
];
1207 best
= (enum reg_class
) class;
1209 else if (temp_costs
->cost
[k
] == best_cost
)
1210 best
= ira_reg_class_union
[best
][class];
1211 if (pass
== flag_expensive_optimizations
1212 && temp_costs
->cost
[k
] < temp_costs
->mem_cost
1213 && (reg_class_size
[reg_class_subunion
[alt_class
][class]]
1214 > reg_class_size
[alt_class
]))
1215 alt_class
= reg_class_subunion
[alt_class
][class];
1217 if (pass
== flag_expensive_optimizations
)
1219 if (best_cost
> temp_costs
->mem_cost
)
1220 best
= alt_class
= NO_REGS
;
1221 else if (best
== alt_class
)
1222 alt_class
= NO_REGS
;
1223 setup_reg_classes (i
, best
, alt_class
);
1224 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1225 fprintf (ira_dump_file
,
1226 " r%d: preferred %s, alternative %s\n",
1227 i
, reg_class_names
[best
], reg_class_names
[alt_class
]);
1229 if (best_cost
> temp_costs
->mem_cost
)
1230 common_class
= NO_REGS
;
1232 /* Make the common class a cover class. Remember all
1233 allocnos with the same regno should have the same cover
1235 common_class
= ira_class_translate
[best
];
1236 for (a
= ira_regno_allocno_map
[i
];
1238 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1240 a_num
= ALLOCNO_NUM (a
);
1241 if (common_class
== NO_REGS
)
1245 /* Finding best class which is subset of the common
1247 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1249 for (k
= 0; k
< cost_classes_num
; k
++)
1251 class = cost_classes
[k
];
1252 if (! ira_class_subset_p
[class][common_class
])
1254 /* Ignore classes that are too small for this
1255 operand or invalid for an operand that was
1256 auto-incremented. */
1257 if (! contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1258 #ifdef FORBIDDEN_INC_DEC_CLASSES
1259 || (inc_dec_p
&& forbidden_inc_dec_class
[class])
1261 #ifdef CANNOT_CHANGE_MODE_CLASS
1262 || invalid_mode_change_p (i
, (enum reg_class
) class,
1263 PSEUDO_REGNO_MODE (i
))
1267 else if (COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
]
1271 = COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1272 best
= (enum reg_class
) class;
1274 else if (COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
]
1276 best
= ira_reg_class_union
[best
][class];
1279 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
1280 && (pass
== 0 || allocno_pref
[a_num
] != best
))
1282 fprintf (ira_dump_file
, " a%d (r%d,", a_num
, i
);
1283 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1284 fprintf (ira_dump_file
, "b%d", bb
->index
);
1286 fprintf (ira_dump_file
, "l%d",
1287 ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1288 fprintf (ira_dump_file
, ") best %s, cover %s\n",
1289 reg_class_names
[best
],
1290 reg_class_names
[ira_class_translate
[best
]]);
1292 allocno_pref
[a_num
] = best
;
1296 if (internal_flag_ira_verbose
> 4 && ira_dump_file
)
1298 print_costs (ira_dump_file
);
1299 fprintf (ira_dump_file
,"\n");
1303 #ifdef FORBIDDEN_INC_DEC_CLASSES
1304 ira_free (in_inc_dec
);
1310 /* Process moves involving hard regs to modify allocno hard register
1311 costs. We can do this only after determining allocno cover class.
1312 If a hard register forms a register class, than moves with the hard
1313 register are already taken into account in class costs for the
1316 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1318 int i
, freq
, cost
, src_regno
, dst_regno
, hard_regno
;
1321 enum reg_class
class, cover_class
, hard_reg_class
;
1322 enum machine_mode mode
;
1324 rtx insn
, set
, src
, dst
;
1326 bb
= loop_tree_node
->bb
;
1329 freq
= REG_FREQ_FROM_BB (bb
);
1332 FOR_BB_INSNS (bb
, insn
)
1334 if (! INSN_P (insn
))
1336 set
= single_set (insn
);
1337 if (set
== NULL_RTX
)
1339 dst
= SET_DEST (set
);
1340 src
= SET_SRC (set
);
1341 if (! REG_P (dst
) || ! REG_P (src
))
1343 dst_regno
= REGNO (dst
);
1344 src_regno
= REGNO (src
);
1345 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1346 && src_regno
< FIRST_PSEUDO_REGISTER
)
1348 hard_regno
= src_regno
;
1350 a
= ira_curr_regno_allocno_map
[dst_regno
];
1352 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1353 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1355 hard_regno
= dst_regno
;
1357 a
= ira_curr_regno_allocno_map
[src_regno
];
1361 class = ALLOCNO_COVER_CLASS (a
);
1362 if (! TEST_HARD_REG_BIT (reg_class_contents
[class], hard_regno
))
1364 i
= ira_class_hard_reg_index
[class][hard_regno
];
1367 mode
= ALLOCNO_MODE (a
);
1368 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
1369 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][class]
1370 : ira_register_move_cost
[mode
][class][hard_reg_class
]) * freq
;
1371 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), class,
1372 ALLOCNO_COVER_CLASS_COST (a
));
1373 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1375 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1376 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1377 ALLOCNO_COVER_CLASS_COST (a
) = MIN (ALLOCNO_COVER_CLASS_COST (a
),
1378 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1379 if (flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1380 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
)
1382 /* Propagate changes to the upper levels in the region
1384 ira_loop_tree_node_t parent
;
1385 int regno
= ALLOCNO_REGNO (a
);
1389 if ((parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) == NULL
)
1391 if ((a
= parent
->regno_allocno_map
[regno
]) == NULL
)
1393 cover_class
= ALLOCNO_COVER_CLASS (a
);
1394 ira_allocate_and_set_costs
1395 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1396 ALLOCNO_COVER_CLASS_COST (a
));
1397 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1399 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1400 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1401 ALLOCNO_COVER_CLASS_COST (a
)
1402 = MIN (ALLOCNO_COVER_CLASS_COST (a
),
1403 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1409 /* After we find hard register and memory costs for allocnos, define
1410 its cover class and modify hard register cost because insns moving
1411 allocno to/from hard registers. */
1413 setup_allocno_cover_class_and_costs (void)
1417 enum reg_class cover_class
, class;
1418 enum machine_mode mode
;
1420 ira_allocno_iterator ai
;
1422 FOR_EACH_ALLOCNO (a
, ai
)
1424 i
= ALLOCNO_NUM (a
);
1425 mode
= ALLOCNO_MODE (a
);
1426 cover_class
= ira_class_translate
[allocno_pref
[i
]];
1427 ira_assert (allocno_pref
[i
] == NO_REGS
|| cover_class
!= NO_REGS
);
1428 ALLOCNO_MEMORY_COST (a
) = ALLOCNO_UPDATED_MEMORY_COST (a
)
1429 = COSTS_OF_ALLOCNO (total_costs
, i
)->mem_cost
;
1430 ira_set_allocno_cover_class (a
, cover_class
);
1431 if (cover_class
== NO_REGS
)
1433 ALLOCNO_AVAILABLE_REGS_NUM (a
) = ira_available_class_regs
[cover_class
];
1434 ALLOCNO_COVER_CLASS_COST (a
)
1435 = (COSTS_OF_ALLOCNO (total_costs
, i
)
1436 ->cost
[cost_class_nums
[allocno_pref
[i
]]]);
1437 if (optimize
&& ALLOCNO_COVER_CLASS (a
) != allocno_pref
[i
])
1439 n
= ira_class_hard_regs_num
[cover_class
];
1440 ALLOCNO_HARD_REG_COSTS (a
)
1441 = reg_costs
= ira_allocate_cost_vector (cover_class
);
1442 for (j
= n
- 1; j
>= 0; j
--)
1444 regno
= ira_class_hard_regs
[cover_class
][j
];
1445 class = REGNO_REG_CLASS (regno
);
1446 reg_costs
[j
] = (COSTS_OF_ALLOCNO (total_costs
, i
)
1447 ->cost
[cost_class_nums
[class]]);
1452 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1453 process_bb_node_for_hard_reg_moves
, NULL
);
1458 /* Function called once during compiler work. */
1460 ira_init_costs_once (void)
1465 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1468 this_op_costs
[i
] = NULL
;
1471 cost_classes
= NULL
;
1474 /* Free allocated temporary cost vectors. */
1476 free_ira_costs (void)
1480 if (init_cost
!= NULL
)
1483 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1485 if (op_costs
[i
] != NULL
)
1487 if (this_op_costs
[i
] != NULL
)
1488 free (this_op_costs
[i
]);
1489 op_costs
[i
] = this_op_costs
[i
] = NULL
;
1491 if (temp_costs
!= NULL
)
1494 if (cost_classes
!= NULL
)
1495 free (cost_classes
);
1496 cost_classes
= NULL
;
1499 /* This is called each time register related information is
1502 ira_init_costs (void)
1507 max_struct_costs_size
1508 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
1509 /* Don't use ira_allocate because vectors live through several IRA calls. */
1510 init_cost
= xmalloc (max_struct_costs_size
);
1511 init_cost
->mem_cost
= 1000000;
1512 for (i
= 0; i
< ira_important_classes_num
; i
++)
1513 init_cost
->cost
[i
] = 1000000;
1514 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1516 op_costs
[i
] = xmalloc (max_struct_costs_size
);
1517 this_op_costs
[i
] = xmalloc (max_struct_costs_size
);
1519 temp_costs
= xmalloc (max_struct_costs_size
);
1520 cost_classes
= xmalloc (sizeof (enum reg_class
) * ira_important_classes_num
);
1523 /* Function called once at the end of compiler work. */
1525 ira_finish_costs_once (void)
1532 /* Entry function which defines cover class, memory and hard register
1533 costs for each allocno. */
1538 ira_allocno_iterator ai
;
1540 total_costs
= ira_allocate (max_struct_costs_size
* ira_allocnos_num
);
1542 = ira_allocate (sizeof (enum reg_class
) * ira_allocnos_num
);
1543 find_allocno_class_costs ();
1544 setup_allocno_cover_class_and_costs ();
1545 /* Because we could process operands only as subregs, check mode of
1546 the registers themselves too. */
1547 FOR_EACH_ALLOCNO (a
, ai
)
1548 if (ira_register_move_cost
[ALLOCNO_MODE (a
)] == NULL
1549 && have_regs_of_mode
[ALLOCNO_MODE (a
)])
1550 ira_init_register_move_cost (ALLOCNO_MODE (a
));
1551 ira_free (allocno_pref_buffer
);
1552 ira_free (total_costs
);
1557 /* Change hard register costs for allocnos which lives through
1558 function calls. This is called only when we found all intersected
1559 calls during building allocno live ranges. */
1561 ira_tune_allocno_costs_and_cover_classes (void)
1564 int cost
, min_cost
, *reg_costs
;
1565 enum reg_class cover_class
, class;
1566 enum machine_mode mode
;
1568 ira_allocno_iterator ai
;
1570 FOR_EACH_ALLOCNO (a
, ai
)
1572 cover_class
= ALLOCNO_COVER_CLASS (a
);
1573 if (cover_class
== NO_REGS
)
1575 mode
= ALLOCNO_MODE (a
);
1576 n
= ira_class_hard_regs_num
[cover_class
];
1578 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0)
1580 ira_allocate_and_set_costs
1581 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1582 ALLOCNO_COVER_CLASS_COST (a
));
1583 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
1584 for (j
= n
- 1; j
>= 0; j
--)
1586 regno
= ira_class_hard_regs
[cover_class
][j
];
1587 class = REGNO_REG_CLASS (regno
);
1589 /* ??? If only part is call clobbered. */
1590 if (! ira_hard_reg_not_in_set_p (regno
, mode
, call_used_reg_set
))
1591 cost
+= (ALLOCNO_CALL_FREQ (a
)
1592 * (ira_memory_move_cost
[mode
][class][0]
1593 + ira_memory_move_cost
[mode
][class][1]));
1594 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
1595 cost
+= ((ira_memory_move_cost
[mode
][class][0]
1596 + ira_memory_move_cost
[mode
][class][1])
1598 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
1600 reg_costs
[j
] += cost
;
1601 if (min_cost
> reg_costs
[j
])
1602 min_cost
= reg_costs
[j
];
1605 if (min_cost
!= INT_MAX
)
1606 ALLOCNO_COVER_CLASS_COST (a
) = min_cost
;