1 /* Machine description for AArch64 architecture.
2 Copyright (C
) 2009-2017 Free Software Foundation
, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software
; you can redistribute it and
/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation
; either version
3, or (at your option
)
12 GCC is distributed in the hope that it will be useful
, but
13 WITHOUT ANY WARRANTY
; without even the implied warranty of
14 MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC
; see the file COPYING3. If not see
19 <http
://www.gnu.org
/licenses
/>.
*/
24 CC_MODE (CC_NZ
); /* Only N and Z bits of condition flags are valid.
*/
25 CC_MODE (CC_Z
); /* Only Z bit of condition flags is valid.
*/
26 CC_MODE (CC_C
); /* Only C bit of condition flags is valid.
*/
28 /* Half
-precision floating point for __fp16.
*/
29 FLOAT_MODE (HF
, 2, 0);
30 ADJUST_FLOAT_FORMAT (HF
, &ieee_half_format
);
33 VECTOR_MODES (INT
, 8); /* V8QI V4HI V2SI.
*/
34 VECTOR_MODES (INT
, 16); /* V16QI V8HI V4SI V2DI.
*/
35 VECTOR_MODES (FLOAT, 8); /* V2SF.
*/
36 VECTOR_MODES (FLOAT, 16); /* V4SF V2DF.
*/
37 VECTOR_MODE (FLOAT, DF
, 1); /* V1DF.
*/
39 /* Oct Int
: 256-bit integer mode needed for
32-byte vector arguments.
*/
42 /* Opaque integer modes for
3 or
4 Neon q
-registers
/ 6 or
8 Neon d
-registers
43 (2 d
-regs
= 1 q
-reg
= TImode
).
*/
47 /* Quad float
: 128-bit floating mode for long doubles.
*/
48 FLOAT_MODE (TF
, 16, ieee_quad_format
);