gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "diagnostic-core.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 #include "params.h"
 101 #include "tree-pass.h"
 102 #include "df.h"
 103 #include "valtrack.h"
 104 #include "cgraph.h"
 105 #include "obstack.h"
 106
 107 /* Number of attempts to combine instructions in this function.  */
 108
 109 static int combine_attempts;
 110
 111 /* Number of attempts that got as far as substitution in this function.  */
 112
 113 static int combine_merges;
 114
 115 /* Number of instructions combined with added SETs in this function.  */
 116
 117 static int combine_extras;
 118
 119 /* Number of instructions combined in this function.  */
 120
 121 static int combine_successes;
 122
 123 /* Totals over entire compilation.  */
 124
 125 static int total_attempts, total_merges, total_extras, total_successes;
 126
 127 /* combine_instructions may try to replace the right hand side of the
 128    second instruction with the value of an associated REG_EQUAL note
 129    before throwing it at try_combine.  That is problematic when there
 130    is a REG_DEAD note for a register used in the old right hand side
 131    and can cause distribute_notes to do wrong things.  This is the
 132    second instruction if it has been so modified, null otherwise.  */
 133
 134 static rtx i2mod;
 135
 136 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 137
 138 static rtx i2mod_old_rhs;
 139
 140 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 141
 142 static rtx i2mod_new_rhs;
 143 \f
 144 typedef struct reg_stat_struct {
 145   /* Record last point of death of (hard or pseudo) register n.  */
 146   rtx                           last_death;
 147
 148   /* Record last point of modification of (hard or pseudo) register n.  */
 149   rtx                           last_set;
 150
 151   /* The next group of fields allows the recording of the last value assigned
 152      to (hard or pseudo) register n.  We use this information to see if an
 153      operation being processed is redundant given a prior operation performed
 154      on the register.  For example, an `and' with a constant is redundant if
 155      all the zero bits are already known to be turned off.
 156
 157      We use an approach similar to that used by cse, but change it in the
 158      following ways:
 159
 160      (1) We do not want to reinitialize at each label.
 161      (2) It is useful, but not critical, to know the actual value assigned
 162          to a register.  Often just its form is helpful.
 163
 164      Therefore, we maintain the following fields:
 165
 166      last_set_value             the last value assigned
 167      last_set_label             records the value of label_tick when the
 168                                 register was assigned
 169      last_set_table_tick        records the value of label_tick when a
 170                                 value using the register is assigned
 171      last_set_invalid           set to nonzero when it is not valid
 172                                 to use the value of this register in some
 173                                 register's value
 174
 175      To understand the usage of these tables, it is important to understand
 176      the distinction between the value in last_set_value being valid and
 177      the register being validly contained in some other expression in the
 178      table.
 179
 180      (The next two parameters are out of date).
 181
 182      reg_stat[i].last_set_value is valid if it is nonzero, and either
 183      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 184
 185      Register I may validly appear in any expression returned for the value
 186      of another register if reg_n_sets[i] is 1.  It may also appear in the
 187      value for register J if reg_stat[j].last_set_invalid is zero, or
 188      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 189
 190      If an expression is found in the table containing a register which may
 191      not validly appear in an expression, the register is replaced by
 192      something that won't match, (clobber (const_int 0)).  */
 193
 194   /* Record last value assigned to (hard or pseudo) register n.  */
 195
 196   rtx                           last_set_value;
 197
 198   /* Record the value of label_tick when an expression involving register n
 199      is placed in last_set_value.  */
 200
 201   int                           last_set_table_tick;
 202
 203   /* Record the value of label_tick when the value for register n is placed in
 204      last_set_value.  */
 205
 206   int                           last_set_label;
 207
 208   /* These fields are maintained in parallel with last_set_value and are
 209      used to store the mode in which the register was last set, the bits
 210      that were known to be zero when it was last set, and the number of
 211      sign bits copies it was known to have when it was last set.  */
 212
 213   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 214   char                          last_set_sign_bit_copies;
 215   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 216
 217   /* Set nonzero if references to register n in expressions should not be
 218      used.  last_set_invalid is set nonzero when this register is being
 219      assigned to and last_set_table_tick == label_tick.  */
 220
 221   char                          last_set_invalid;
 222
 223   /* Some registers that are set more than once and used in more than one
 224      basic block are nevertheless always set in similar ways.  For example,
 225      a QImode register may be loaded from memory in two places on a machine
 226      where byte loads zero extend.
 227
 228      We record in the following fields if a register has some leading bits
 229      that are always equal to the sign bit, and what we know about the
 230      nonzero bits of a register, specifically which bits are known to be
 231      zero.
 232
 233      If an entry is zero, it means that we don't know anything special.  */
 234
 235   unsigned char                 sign_bit_copies;
 236
 237   unsigned HOST_WIDE_INT        nonzero_bits;
 238
 239   /* Record the value of the label_tick when the last truncation
 240      happened.  The field truncated_to_mode is only valid if
 241      truncation_label == label_tick.  */
 242
 243   int                           truncation_label;
 244
 245   /* Record the last truncation seen for this register.  If truncation
 246      is not a nop to this mode we might be able to save an explicit
 247      truncation if we know that value already contains a truncated
 248      value.  */
 249
 250   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 251 } reg_stat_type;
 252
 253
 254 static vec<reg_stat_type> reg_stat;
 255
 256 /* Record the luid of the last insn that invalidated memory
 257    (anything that writes memory, and subroutine calls, but not pushes).  */
 258
 259 static int mem_last_set;
 260
 261 /* Record the luid of the last CALL_INSN
 262    so we can tell whether a potential combination crosses any calls.  */
 263
 264 static int last_call_luid;
 265
 266 /* When `subst' is called, this is the insn that is being modified
 267    (by combining in a previous insn).  The PATTERN of this insn
 268    is still the old pattern partially modified and it should not be
 269    looked at, but this may be used to examine the successors of the insn
 270    to judge whether a simplification is valid.  */
 271
 272 static rtx subst_insn;
 273
 274 /* This is the lowest LUID that `subst' is currently dealing with.
 275    get_last_value will not return a value if the register was set at or
 276    after this LUID.  If not for this mechanism, we could get confused if
 277    I2 or I1 in try_combine were an insn that used the old value of a register
 278    to obtain a new value.  In that case, we might erroneously get the
 279    new value of the register when we wanted the old one.  */
 280
 281 static int subst_low_luid;
 282
 283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 284    must consider all these registers to be always live.  */
 285
 286 static HARD_REG_SET newpat_used_regs;
 287
 288 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 289    insn is the earlier than I2 or I3, combine should rescan starting at
 290    that location.  */
 291
 292 static rtx added_links_insn;
 293
 294 /* Basic block in which we are performing combines.  */
 295 static basic_block this_basic_block;
 296 static bool optimize_this_for_speed_p;
 297
 298 \f
 299 /* Length of the currently allocated uid_insn_cost array.  */
 300
 301 static int max_uid_known;
 302
 303 /* The following array records the insn_rtx_cost for every insn
 304    in the instruction stream.  */
 305
 306 static int *uid_insn_cost;
 307
 308 /* The following array records the LOG_LINKS for every insn in the
 309    instruction stream as struct insn_link pointers.  */
 310
 311 struct insn_link {
 312   rtx insn;
 313   struct insn_link *next;
 314 };
 315
 316 static struct insn_link **uid_log_links;
 317
 318 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 319 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 320
 321 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 322   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 323
 324 /* Links for LOG_LINKS are allocated from this obstack.  */
 325
 326 static struct obstack insn_link_obstack;
 327
 328 /* Allocate a link.  */
 329
 330 static inline struct insn_link *
 331 alloc_insn_link (rtx insn, struct insn_link *next)
 332 {
 333   struct insn_link *l
 334     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 335                                           sizeof (struct insn_link));
 336   l->insn = insn;
 337   l->next = next;
 338   return l;
 339 }
 340
 341 /* Incremented for each basic block.  */
 342
 343 static int label_tick;
 344
 345 /* Reset to label_tick for each extended basic block in scanning order.  */
 346
 347 static int label_tick_ebb_start;
 348
 349 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 350    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 351
 352 static enum machine_mode nonzero_bits_mode;
 353
 354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 355    be safely used.  It is zero while computing them and after combine has
 356    completed.  This former test prevents propagating values based on
 357    previously set values, which can be incorrect if a variable is modified
 358    in a loop.  */
 359
 360 static int nonzero_sign_valid;
 361
 362 \f
 363 /* Record one modification to rtl structure
 364    to be undone by storing old_contents into *where.  */
 365
 366 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 367
 368 struct undo
 369 {
 370   struct undo *next;
 371   enum undo_kind kind;
 372   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 373   union { rtx *r; int *i; struct insn_link **l; } where;
 374 };
 375
 376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 377    num_undo says how many are currently recorded.
 378
 379    other_insn is nonzero if we have modified some other insn in the process
 380    of working on subst_insn.  It must be verified too.  */
 381
 382 struct undobuf
 383 {
 384   struct undo *undos;
 385   struct undo *frees;
 386   rtx other_insn;
 387 };
 388
 389 static struct undobuf undobuf;
 390
 391 /* Number of times the pseudo being substituted for
 392    was found and replaced.  */
 393
 394 static int n_occurrences;
 395
 396 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 397                                          enum machine_mode,
 398                                          unsigned HOST_WIDE_INT,
 399                                          unsigned HOST_WIDE_INT *);
 400 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                                 enum machine_mode,
 402                                                 unsigned int, unsigned int *);
 403 static void do_SUBST (rtx *, rtx);
 404 static void do_SUBST_INT (int *, int);
 405 static void init_reg_last (void);
 406 static void setup_incoming_promotions (rtx);
 407 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 408 static int cant_combine_insn_p (rtx);
 409 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 410 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 411 static int contains_muldiv (rtx);
 412 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 413 static void undo_all (void);
 414 static void undo_commit (void);
 415 static rtx *find_split_point (rtx *, rtx, bool);
 416 static rtx subst (rtx, rtx, rtx, int, int, int);
 417 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 418 static rtx simplify_if_then_else (rtx);
 419 static rtx simplify_set (rtx);
 420 static rtx simplify_logical (rtx);
 421 static rtx expand_compound_operation (rtx);
 422 static const_rtx expand_field_assignment (const_rtx);
 423 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 424                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 425 static rtx extract_left_shift (rtx, int);
 426 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 427                               unsigned HOST_WIDE_INT *);
 428 static rtx canon_reg_for_combine (rtx, rtx);
 429 static rtx force_to_mode (rtx, enum machine_mode,
 430                           unsigned HOST_WIDE_INT, int);
 431 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 432 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 433 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 434 static rtx make_field_assignment (rtx);
 435 static rtx apply_distributive_law (rtx);
 436 static rtx distribute_and_simplify_rtx (rtx, int);
 437 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 438                                      unsigned HOST_WIDE_INT);
 439 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 440                                    unsigned HOST_WIDE_INT);
 441 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 442                             HOST_WIDE_INT, enum machine_mode, int *);
 443 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 444 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 445                                  int);
 446 static int recog_for_combine (rtx *, rtx, rtx *);
 447 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 448 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 449 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 450 static void update_table_tick (rtx);
 451 static void record_value_for_reg (rtx, rtx, rtx);
 452 static void check_promoted_subreg (rtx, rtx);
 453 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 454 static void record_dead_and_set_regs (rtx);
 455 static int get_last_value_validate (rtx *, rtx, int, int);
 456 static rtx get_last_value (const_rtx);
 457 static int use_crosses_set_p (const_rtx, int);
 458 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 459 static int reg_dead_at_p (rtx, rtx);
 460 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 461 static int reg_bitfield_target_p (rtx, rtx);
 462 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 463 static void distribute_links (struct insn_link *);
 464 static void mark_used_regs_combine (rtx);
 465 static void record_promoted_value (rtx, rtx);
 466 static int unmentioned_reg_p_1 (rtx *, void *);
 467 static bool unmentioned_reg_p (rtx, rtx);
 468 static int record_truncated_value (rtx *, void *);
 469 static void record_truncated_values (rtx *, void *);
 470 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 471 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 472 \f
 473
 474 /* It is not safe to use ordinary gen_lowpart in combine.
 475    See comments in gen_lowpart_for_combine.  */
 476 #undef RTL_HOOKS_GEN_LOWPART
 477 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 478
 479 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 482
 483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 484 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 485
 486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 488
 489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 491
 492 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 493
 494 \f
 495 /* Convenience wrapper for the canonicalize_comparison target hook.
 496    Target hooks cannot use enum rtx_code.  */
 497 static inline void
 498 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 499                                 bool op0_preserve_value)
 500 {
 501   int code_int = (int)*code;
 502   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 503   *code = (enum rtx_code)code_int;
 504 }
 505
 506 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 507    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 508    This is a wrapper around split_insns which ensures that the
 509    reg_stat vector is made larger if the splitter creates a new
 510    register.  */
 511
 512 static rtx
 513 combine_split_insns (rtx pattern, rtx insn)
 514 {
 515   rtx ret;
 516   unsigned int nregs;
 517
 518   ret = split_insns (pattern, insn);
 519   nregs = max_reg_num ();
 520   if (nregs > reg_stat.length ())
 521     reg_stat.safe_grow_cleared (nregs);
 522   return ret;
 523 }
 524
 525 /* This is used by find_single_use to locate an rtx in LOC that
 526    contains exactly one use of DEST, which is typically either a REG
 527    or CC0.  It returns a pointer to the innermost rtx expression
 528    containing DEST.  Appearances of DEST that are being used to
 529    totally replace it are not counted.  */
 530
 531 static rtx *
 532 find_single_use_1 (rtx dest, rtx *loc)
 533 {
 534   rtx x = *loc;
 535   enum rtx_code code = GET_CODE (x);
 536   rtx *result = NULL;
 537   rtx *this_result;
 538   int i;
 539   const char *fmt;
 540
 541   switch (code)
 542     {
 543     case CONST:
 544     case LABEL_REF:
 545     case SYMBOL_REF:
 546     CASE_CONST_ANY:
 547     case CLOBBER:
 548       return 0;
 549
 550     case SET:
 551       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 552          of a REG that occupies all of the REG, the insn uses DEST if
 553          it is mentioned in the destination or the source.  Otherwise, we
 554          need just check the source.  */
 555       if (GET_CODE (SET_DEST (x)) != CC0
 556           && GET_CODE (SET_DEST (x)) != PC
 557           && !REG_P (SET_DEST (x))
 558           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 559                 && REG_P (SUBREG_REG (SET_DEST (x)))
 560                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 561                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 562                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 563                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 564         break;
 565
 566       return find_single_use_1 (dest, &SET_SRC (x));
 567
 568     case MEM:
 569     case SUBREG:
 570       return find_single_use_1 (dest, &XEXP (x, 0));
 571
 572     default:
 573       break;
 574     }
 575
 576   /* If it wasn't one of the common cases above, check each expression and
 577      vector of this code.  Look for a unique usage of DEST.  */
 578
 579   fmt = GET_RTX_FORMAT (code);
 580   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 581     {
 582       if (fmt[i] == 'e')
 583         {
 584           if (dest == XEXP (x, i)
 585               || (REG_P (dest) && REG_P (XEXP (x, i))
 586                   && REGNO (dest) == REGNO (XEXP (x, i))))
 587             this_result = loc;
 588           else
 589             this_result = find_single_use_1 (dest, &XEXP (x, i));
 590
 591           if (result == NULL)
 592             result = this_result;
 593           else if (this_result)
 594             /* Duplicate usage.  */
 595             return NULL;
 596         }
 597       else if (fmt[i] == 'E')
 598         {
 599           int j;
 600
 601           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 602             {
 603               if (XVECEXP (x, i, j) == dest
 604                   || (REG_P (dest)
 605                       && REG_P (XVECEXP (x, i, j))
 606                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 607                 this_result = loc;
 608               else
 609                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 610
 611               if (result == NULL)
 612                 result = this_result;
 613               else if (this_result)
 614                 return NULL;
 615             }
 616         }
 617     }
 618
 619   return result;
 620 }
 621
 622
 623 /* See if DEST, produced in INSN, is used only a single time in the
 624    sequel.  If so, return a pointer to the innermost rtx expression in which
 625    it is used.
 626
 627    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 628
 629    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 630    care about REG_DEAD notes or LOG_LINKS.
 631
 632    Otherwise, we find the single use by finding an insn that has a
 633    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 634    only referenced once in that insn, we know that it must be the first
 635    and last insn referencing DEST.  */
 636
 637 static rtx *
 638 find_single_use (rtx dest, rtx insn, rtx *ploc)
 639 {
 640   basic_block bb;
 641   rtx next;
 642   rtx *result;
 643   struct insn_link *link;
 644
 645 #ifdef HAVE_cc0
 646   if (dest == cc0_rtx)
 647     {
 648       next = NEXT_INSN (insn);
 649       if (next == 0
 650           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 651         return 0;
 652
 653       result = find_single_use_1 (dest, &PATTERN (next));
 654       if (result && ploc)
 655         *ploc = next;
 656       return result;
 657     }
 658 #endif
 659
 660   if (!REG_P (dest))
 661     return 0;
 662
 663   bb = BLOCK_FOR_INSN (insn);
 664   for (next = NEXT_INSN (insn);
 665        next && BLOCK_FOR_INSN (next) == bb;
 666        next = NEXT_INSN (next))
 667     if (INSN_P (next) && dead_or_set_p (next, dest))
 668       {
 669         FOR_EACH_LOG_LINK (link, next)
 670           if (link->insn == insn)
 671             break;
 672
 673         if (link)
 674           {
 675             result = find_single_use_1 (dest, &PATTERN (next));
 676             if (ploc)
 677               *ploc = next;
 678             return result;
 679           }
 680       }
 681
 682   return 0;
 683 }
 684 \f
 685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 686    insn.  The substitution can be undone by undo_all.  If INTO is already
 687    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 688    also call SUBST, we have to compute it before we put anything into
 689    the undo table.  */
 690
 691 static void
 692 do_SUBST (rtx *into, rtx newval)
 693 {
 694   struct undo *buf;
 695   rtx oldval = *into;
 696
 697   if (oldval == newval)
 698     return;
 699
 700   /* We'd like to catch as many invalid transformations here as
 701      possible.  Unfortunately, there are way too many mode changes
 702      that are perfectly valid, so we'd waste too much effort for
 703      little gain doing the checks here.  Focus on catching invalid
 704      transformations involving integer constants.  */
 705   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 706       && CONST_INT_P (newval))
 707     {
 708       /* Sanity check that we're replacing oldval with a CONST_INT
 709          that is a valid sign-extension for the original mode.  */
 710       gcc_assert (INTVAL (newval)
 711                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 712
 713       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 714          CONST_INT is not valid, because after the replacement, the
 715          original mode would be gone.  Unfortunately, we can't tell
 716          when do_SUBST is called to replace the operand thereof, so we
 717          perform this test on oldval instead, checking whether an
 718          invalid replacement took place before we got here.  */
 719       gcc_assert (!(GET_CODE (oldval) == SUBREG
 720                     && CONST_INT_P (SUBREG_REG (oldval))));
 721       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 722                     && CONST_INT_P (XEXP (oldval, 0))));
 723     }
 724
 725   if (undobuf.frees)
 726     buf = undobuf.frees, undobuf.frees = buf->next;
 727   else
 728     buf = XNEW (struct undo);
 729
 730   buf->kind = UNDO_RTX;
 731   buf->where.r = into;
 732   buf->old_contents.r = oldval;
 733   *into = newval;
 734
 735   buf->next = undobuf.undos, undobuf.undos = buf;
 736 }
 737
 738 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 739
 740 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 741    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 742    not safe.  */
 743
 744 static void
 745 do_SUBST_INT (int *into, int newval)
 746 {
 747   struct undo *buf;
 748   int oldval = *into;
 749
 750   if (oldval == newval)
 751     return;
 752
 753   if (undobuf.frees)
 754     buf = undobuf.frees, undobuf.frees = buf->next;
 755   else
 756     buf = XNEW (struct undo);
 757
 758   buf->kind = UNDO_INT;
 759   buf->where.i = into;
 760   buf->old_contents.i = oldval;
 761   *into = newval;
 762
 763   buf->next = undobuf.undos, undobuf.undos = buf;
 764 }
 765
 766 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 767
 768 /* Similar to SUBST, but just substitute the mode.  This is used when
 769    changing the mode of a pseudo-register, so that any other
 770    references to the entry in the regno_reg_rtx array will change as
 771    well.  */
 772
 773 static void
 774 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 775 {
 776   struct undo *buf;
 777   enum machine_mode oldval = GET_MODE (*into);
 778
 779   if (oldval == newval)
 780     return;
 781
 782   if (undobuf.frees)
 783     buf = undobuf.frees, undobuf.frees = buf->next;
 784   else
 785     buf = XNEW (struct undo);
 786
 787   buf->kind = UNDO_MODE;
 788   buf->where.r = into;
 789   buf->old_contents.m = oldval;
 790   adjust_reg_mode (*into, newval);
 791
 792   buf->next = undobuf.undos, undobuf.undos = buf;
 793 }
 794
 795 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 796
 797 #ifndef HAVE_cc0
 798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 799
 800 static void
 801 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 802 {
 803   struct undo *buf;
 804   struct insn_link * oldval = *into;
 805
 806   if (oldval == newval)
 807     return;
 808
 809   if (undobuf.frees)
 810     buf = undobuf.frees, undobuf.frees = buf->next;
 811   else
 812     buf = XNEW (struct undo);
 813
 814   buf->kind = UNDO_LINKS;
 815   buf->where.l = into;
 816   buf->old_contents.l = oldval;
 817   *into = newval;
 818
 819   buf->next = undobuf.undos, undobuf.undos = buf;
 820 }
 821
 822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 823 #endif
 824 \f
 825 /* Subroutine of try_combine.  Determine whether the replacement patterns
 826    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 827    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 828    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 829    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 830    of all the instructions can be estimated and the replacements are more
 831    expensive than the original sequence.  */
 832
 833 static bool
 834 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 835                        rtx newi2pat, rtx newotherpat)
 836 {
 837   int i0_cost, i1_cost, i2_cost, i3_cost;
 838   int new_i2_cost, new_i3_cost;
 839   int old_cost, new_cost;
 840
 841   /* Lookup the original insn_rtx_costs.  */
 842   i2_cost = INSN_COST (i2);
 843   i3_cost = INSN_COST (i3);
 844
 845   if (i1)
 846     {
 847       i1_cost = INSN_COST (i1);
 848       if (i0)
 849         {
 850           i0_cost = INSN_COST (i0);
 851           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 852                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 853         }
 854       else
 855         {
 856           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 857                       ? i1_cost + i2_cost + i3_cost : 0);
 858           i0_cost = 0;
 859         }
 860     }
 861   else
 862     {
 863       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 864       i1_cost = i0_cost = 0;
 865     }
 866
 867   /* Calculate the replacement insn_rtx_costs.  */
 868   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 869   if (newi2pat)
 870     {
 871       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 872       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 873                  ? new_i2_cost + new_i3_cost : 0;
 874     }
 875   else
 876     {
 877       new_cost = new_i3_cost;
 878       new_i2_cost = 0;
 879     }
 880
 881   if (undobuf.other_insn)
 882     {
 883       int old_other_cost, new_other_cost;
 884
 885       old_other_cost = INSN_COST (undobuf.other_insn);
 886       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 887       if (old_other_cost > 0 && new_other_cost > 0)
 888         {
 889           old_cost += old_other_cost;
 890           new_cost += new_other_cost;
 891         }
 892       else
 893         old_cost = 0;
 894     }
 895
 896   /* Disallow this combination if both new_cost and old_cost are greater than
 897      zero, and new_cost is greater than old cost.  */
 898   if (old_cost > 0 && new_cost > old_cost)
 899     {
 900       if (dump_file)
 901         {
 902           if (i0)
 903             {
 904               fprintf (dump_file,
 905                        "rejecting combination of insns %d, %d, %d and %d\n",
 906                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 907                        INSN_UID (i3));
 908               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 909                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 910             }
 911           else if (i1)
 912             {
 913               fprintf (dump_file,
 914                        "rejecting combination of insns %d, %d and %d\n",
 915                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 916               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 917                        i1_cost, i2_cost, i3_cost, old_cost);
 918             }
 919           else
 920             {
 921               fprintf (dump_file,
 922                        "rejecting combination of insns %d and %d\n",
 923                        INSN_UID (i2), INSN_UID (i3));
 924               fprintf (dump_file, "original costs %d + %d = %d\n",
 925                        i2_cost, i3_cost, old_cost);
 926             }
 927
 928           if (newi2pat)
 929             {
 930               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 931                        new_i2_cost, new_i3_cost, new_cost);
 932             }
 933           else
 934             fprintf (dump_file, "replacement cost %d\n", new_cost);
 935         }
 936
 937       return false;
 938     }
 939
 940   /* Update the uid_insn_cost array with the replacement costs.  */
 941   INSN_COST (i2) = new_i2_cost;
 942   INSN_COST (i3) = new_i3_cost;
 943   if (i1)
 944     {
 945       INSN_COST (i1) = 0;
 946       if (i0)
 947         INSN_COST (i0) = 0;
 948     }
 949
 950   return true;
 951 }
 952
 953
 954 /* Delete any insns that copy a register to itself.  */
 955
 956 static void
 957 delete_noop_moves (void)
 958 {
 959   rtx insn, next;
 960   basic_block bb;
 961
 962   FOR_EACH_BB (bb)
 963     {
 964       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 965         {
 966           next = NEXT_INSN (insn);
 967           if (INSN_P (insn) && noop_move_p (insn))
 968             {
 969               if (dump_file)
 970                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 971
 972               delete_insn_and_edges (insn);
 973             }
 974         }
 975     }
 976 }
 977
 978 \f
 979 /* Fill in log links field for all insns.  */
 980
 981 static void
 982 create_log_links (void)
 983 {
 984   basic_block bb;
 985   rtx *next_use, insn;
 986   df_ref *def_vec, *use_vec;
 987
 988   next_use = XCNEWVEC (rtx, max_reg_num ());
 989
 990   /* Pass through each block from the end, recording the uses of each
 991      register and establishing log links when def is encountered.
 992      Note that we do not clear next_use array in order to save time,
 993      so we have to test whether the use is in the same basic block as def.
 994
 995      There are a few cases below when we do not consider the definition or
 996      usage -- these are taken from original flow.c did. Don't ask me why it is
 997      done this way; I don't know and if it works, I don't want to know.  */
 998
 999   FOR_EACH_BB (bb)
1000     {
1001       FOR_BB_INSNS_REVERSE (bb, insn)
1002         {
1003           if (!NONDEBUG_INSN_P (insn))
1004             continue;
1005
1006           /* Log links are created only once.  */
1007           gcc_assert (!LOG_LINKS (insn));
1008
1009           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1010             {
1011               df_ref def = *def_vec;
1012               int regno = DF_REF_REGNO (def);
1013               rtx use_insn;
1014
1015               if (!next_use[regno])
1016                 continue;
1017
1018               /* Do not consider if it is pre/post modification in MEM.  */
1019               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1020                 continue;
1021
1022               /* Do not make the log link for frame pointer.  */
1023               if ((regno == FRAME_POINTER_REGNUM
1024                    && (! reload_completed || frame_pointer_needed))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026                   || (regno == HARD_FRAME_POINTER_REGNUM
1027                       && (! reload_completed || frame_pointer_needed))
1028 #endif
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1031 #endif
1032                   )
1033                 continue;
1034
1035               use_insn = next_use[regno];
1036               if (BLOCK_FOR_INSN (use_insn) == bb)
1037                 {
1038                   /* flow.c claimed:
1039
1040                      We don't build a LOG_LINK for hard registers contained
1041                      in ASM_OPERANDs.  If these registers get replaced,
1042                      we might wind up changing the semantics of the insn,
1043                      even if reload can make what appear to be valid
1044                      assignments later.  */
1045                   if (regno >= FIRST_PSEUDO_REGISTER
1046                       || asm_noperands (PATTERN (use_insn)) < 0)
1047                     {
1048                       /* Don't add duplicate links between instructions.  */
1049                       struct insn_link *links;
1050                       FOR_EACH_LOG_LINK (links, use_insn)
1051                         if (insn == links->insn)
1052                           break;
1053
1054                       if (!links)
1055                         LOG_LINKS (use_insn)
1056                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1057                     }
1058                 }
1059               next_use[regno] = NULL_RTX;
1060             }
1061
1062           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1063             {
1064               df_ref use = *use_vec;
1065               int regno = DF_REF_REGNO (use);
1066
1067               /* Do not consider the usage of the stack pointer
1068                  by function call.  */
1069               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1070                 continue;
1071
1072               next_use[regno] = insn;
1073             }
1074         }
1075     }
1076
1077   free (next_use);
1078 }
1079
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1081    true if we found a LOG_LINK that proves that A feeds B.  This only works
1082    if there are no instructions between A and B which could have a link
1083    depending on A, since in that case we would not record a link for B.
1084    We also check the implicit dependency created by a cc0 setter/user
1085    pair.  */
1086
1087 static bool
1088 insn_a_feeds_b (rtx a, rtx b)
1089 {
1090   struct insn_link *links;
1091   FOR_EACH_LOG_LINK (links, b)
1092     if (links->insn == a)
1093       return true;
1094 #ifdef HAVE_cc0
1095   if (sets_cc0_p (a))
1096     return true;
1097 #endif
1098   return false;
1099 }
1100 \f
1101 /* Main entry point for combiner.  F is the first insn of the function.
1102    NREGS is the first unused pseudo-reg number.
1103
1104    Return nonzero if the combiner has turned an indirect jump
1105    instruction into a direct jump.  */
1106 static int
1107 combine_instructions (rtx f, unsigned int nregs)
1108 {
1109   rtx insn, next;
1110 #ifdef HAVE_cc0
1111   rtx prev;
1112 #endif
1113   struct insn_link *links, *nextlinks;
1114   rtx first;
1115   basic_block last_bb;
1116
1117   int new_direct_jump_p = 0;
1118
1119   for (first = f; first && !INSN_P (first); )
1120     first = NEXT_INSN (first);
1121   if (!first)
1122     return 0;
1123
1124   combine_attempts = 0;
1125   combine_merges = 0;
1126   combine_extras = 0;
1127   combine_successes = 0;
1128
1129   rtl_hooks = combine_rtl_hooks;
1130
1131   reg_stat.safe_grow_cleared (nregs);
1132
1133   init_recog_no_volatile ();
1134
1135   /* Allocate array for insn info.  */
1136   max_uid_known = get_max_uid ();
1137   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1138   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1139   gcc_obstack_init (&insn_link_obstack);
1140
1141   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1142
1143   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1144      problems when, for example, we have j <<= 1 in a loop.  */
1145
1146   nonzero_sign_valid = 0;
1147   label_tick = label_tick_ebb_start = 1;
1148
1149   /* Scan all SETs and see if we can deduce anything about what
1150      bits are known to be zero for some registers and how many copies
1151      of the sign bit are known to exist for those registers.
1152
1153      Also set any known values so that we can use it while searching
1154      for what bits are known to be set.  */
1155
1156   setup_incoming_promotions (first);
1157   /* Allow the entry block and the first block to fall into the same EBB.
1158      Conceptually the incoming promotions are assigned to the entry block.  */
1159   last_bb = ENTRY_BLOCK_PTR;
1160
1161   create_log_links ();
1162   FOR_EACH_BB (this_basic_block)
1163     {
1164       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165       last_call_luid = 0;
1166       mem_last_set = -1;
1167
1168       label_tick++;
1169       if (!single_pred_p (this_basic_block)
1170           || single_pred (this_basic_block) != last_bb)
1171         label_tick_ebb_start = label_tick;
1172       last_bb = this_basic_block;
1173
1174       FOR_BB_INSNS (this_basic_block, insn)
1175         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1176           {
1177 #ifdef AUTO_INC_DEC
1178             rtx links;
1179 #endif
1180
1181             subst_low_luid = DF_INSN_LUID (insn);
1182             subst_insn = insn;
1183
1184             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1185                          insn);
1186             record_dead_and_set_regs (insn);
1187
1188 #ifdef AUTO_INC_DEC
1189             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1190               if (REG_NOTE_KIND (links) == REG_INC)
1191                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1192                                                   insn);
1193 #endif
1194
1195             /* Record the current insn_rtx_cost of this instruction.  */
1196             if (NONJUMP_INSN_P (insn))
1197               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1198                                                 optimize_this_for_speed_p);
1199             if (dump_file)
1200               fprintf(dump_file, "insn_cost %d: %d\n",
1201                     INSN_UID (insn), INSN_COST (insn));
1202           }
1203     }
1204
1205   nonzero_sign_valid = 1;
1206
1207   /* Now scan all the insns in forward order.  */
1208   label_tick = label_tick_ebb_start = 1;
1209   init_reg_last ();
1210   setup_incoming_promotions (first);
1211   last_bb = ENTRY_BLOCK_PTR;
1212
1213   FOR_EACH_BB (this_basic_block)
1214     {
1215       rtx last_combined_insn = NULL_RTX;
1216       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217       last_call_luid = 0;
1218       mem_last_set = -1;
1219
1220       label_tick++;
1221       if (!single_pred_p (this_basic_block)
1222           || single_pred (this_basic_block) != last_bb)
1223         label_tick_ebb_start = label_tick;
1224       last_bb = this_basic_block;
1225
1226       rtl_profile_for_bb (this_basic_block);
1227       for (insn = BB_HEAD (this_basic_block);
1228            insn != NEXT_INSN (BB_END (this_basic_block));
1229            insn = next ? next : NEXT_INSN (insn))
1230         {
1231           next = 0;
1232           if (NONDEBUG_INSN_P (insn))
1233             {
1234               while (last_combined_insn
1235                      && INSN_DELETED_P (last_combined_insn))
1236                 last_combined_insn = PREV_INSN (last_combined_insn);
1237               if (last_combined_insn == NULL_RTX
1238                   || BARRIER_P (last_combined_insn)
1239                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1240                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1241                 last_combined_insn = insn;
1242
1243               /* See if we know about function return values before this
1244                  insn based upon SUBREG flags.  */
1245               check_promoted_subreg (insn, PATTERN (insn));
1246
1247               /* See if we can find hardregs and subreg of pseudos in
1248                  narrower modes.  This could help turning TRUNCATEs
1249                  into SUBREGs.  */
1250               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1251
1252               /* Try this insn with each insn it links back to.  */
1253
1254               FOR_EACH_LOG_LINK (links, insn)
1255                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1256                                          NULL_RTX, &new_direct_jump_p,
1257                                          last_combined_insn)) != 0)
1258                   goto retry;
1259
1260               /* Try each sequence of three linked insns ending with this one.  */
1261
1262               FOR_EACH_LOG_LINK (links, insn)
1263                 {
1264                   rtx link = links->insn;
1265
1266                   /* If the linked insn has been replaced by a note, then there
1267                      is no point in pursuing this chain any further.  */
1268                   if (NOTE_P (link))
1269                     continue;
1270
1271                   FOR_EACH_LOG_LINK (nextlinks, link)
1272                     if ((next = try_combine (insn, link, nextlinks->insn,
1273                                              NULL_RTX, &new_direct_jump_p,
1274                                              last_combined_insn)) != 0)
1275                       goto retry;
1276                 }
1277
1278 #ifdef HAVE_cc0
1279               /* Try to combine a jump insn that uses CC0
1280                  with a preceding insn that sets CC0, and maybe with its
1281                  logical predecessor as well.
1282                  This is how we make decrement-and-branch insns.
1283                  We need this special code because data flow connections
1284                  via CC0 do not get entered in LOG_LINKS.  */
1285
1286               if (JUMP_P (insn)
1287                   && (prev = prev_nonnote_insn (insn)) != 0
1288                   && NONJUMP_INSN_P (prev)
1289                   && sets_cc0_p (PATTERN (prev)))
1290                 {
1291                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1292                                            &new_direct_jump_p,
1293                                            last_combined_insn)) != 0)
1294                     goto retry;
1295
1296                   FOR_EACH_LOG_LINK (nextlinks, prev)
1297                     if ((next = try_combine (insn, prev, nextlinks->insn,
1298                                              NULL_RTX, &new_direct_jump_p,
1299                                              last_combined_insn)) != 0)
1300                       goto retry;
1301                 }
1302
1303               /* Do the same for an insn that explicitly references CC0.  */
1304               if (NONJUMP_INSN_P (insn)
1305                   && (prev = prev_nonnote_insn (insn)) != 0
1306                   && NONJUMP_INSN_P (prev)
1307                   && sets_cc0_p (PATTERN (prev))
1308                   && GET_CODE (PATTERN (insn)) == SET
1309                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1310                 {
1311                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1312                                            &new_direct_jump_p,
1313                                            last_combined_insn)) != 0)
1314                     goto retry;
1315
1316                   FOR_EACH_LOG_LINK (nextlinks, prev)
1317                     if ((next = try_combine (insn, prev, nextlinks->insn,
1318                                              NULL_RTX, &new_direct_jump_p,
1319                                              last_combined_insn)) != 0)
1320                       goto retry;
1321                 }
1322
1323               /* Finally, see if any of the insns that this insn links to
1324                  explicitly references CC0.  If so, try this insn, that insn,
1325                  and its predecessor if it sets CC0.  */
1326               FOR_EACH_LOG_LINK (links, insn)
1327                 if (NONJUMP_INSN_P (links->insn)
1328                     && GET_CODE (PATTERN (links->insn)) == SET
1329                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1330                     && (prev = prev_nonnote_insn (links->insn)) != 0
1331                     && NONJUMP_INSN_P (prev)
1332                     && sets_cc0_p (PATTERN (prev))
1333                     && (next = try_combine (insn, links->insn,
1334                                             prev, NULL_RTX, &new_direct_jump_p,
1335                                             last_combined_insn)) != 0)
1336                   goto retry;
1337 #endif
1338
1339               /* Try combining an insn with two different insns whose results it
1340                  uses.  */
1341               FOR_EACH_LOG_LINK (links, insn)
1342                 for (nextlinks = links->next; nextlinks;
1343                      nextlinks = nextlinks->next)
1344                   if ((next = try_combine (insn, links->insn,
1345                                            nextlinks->insn, NULL_RTX,
1346                                            &new_direct_jump_p,
1347                                            last_combined_insn)) != 0)
1348                     goto retry;
1349
1350               /* Try four-instruction combinations.  */
1351               FOR_EACH_LOG_LINK (links, insn)
1352                 {
1353                   struct insn_link *next1;
1354                   rtx link = links->insn;
1355
1356                   /* If the linked insn has been replaced by a note, then there
1357                      is no point in pursuing this chain any further.  */
1358                   if (NOTE_P (link))
1359                     continue;
1360
1361                   FOR_EACH_LOG_LINK (next1, link)
1362                     {
1363                       rtx link1 = next1->insn;
1364                       if (NOTE_P (link1))
1365                         continue;
1366                       /* I0 -> I1 -> I2 -> I3.  */
1367                       FOR_EACH_LOG_LINK (nextlinks, link1)
1368                         if ((next = try_combine (insn, link, link1,
1369                                                  nextlinks->insn,
1370                                                  &new_direct_jump_p,
1371                                                  last_combined_insn)) != 0)
1372                           goto retry;
1373                       /* I0, I1 -> I2, I2 -> I3.  */
1374                       for (nextlinks = next1->next; nextlinks;
1375                            nextlinks = nextlinks->next)
1376                         if ((next = try_combine (insn, link, link1,
1377                                                  nextlinks->insn,
1378                                                  &new_direct_jump_p,
1379                                                  last_combined_insn)) != 0)
1380                           goto retry;
1381                     }
1382
1383                   for (next1 = links->next; next1; next1 = next1->next)
1384                     {
1385                       rtx link1 = next1->insn;
1386                       if (NOTE_P (link1))
1387                         continue;
1388                       /* I0 -> I2; I1, I2 -> I3.  */
1389                       FOR_EACH_LOG_LINK (nextlinks, link)
1390                         if ((next = try_combine (insn, link, link1,
1391                                                  nextlinks->insn,
1392                                                  &new_direct_jump_p,
1393                                                  last_combined_insn)) != 0)
1394                           goto retry;
1395                       /* I0 -> I1; I1, I2 -> I3.  */
1396                       FOR_EACH_LOG_LINK (nextlinks, link1)
1397                         if ((next = try_combine (insn, link, link1,
1398                                                  nextlinks->insn,
1399                                                  &new_direct_jump_p,
1400                                                  last_combined_insn)) != 0)
1401                           goto retry;
1402                     }
1403                 }
1404
1405               /* Try this insn with each REG_EQUAL note it links back to.  */
1406               FOR_EACH_LOG_LINK (links, insn)
1407                 {
1408                   rtx set, note;
1409                   rtx temp = links->insn;
1410                   if ((set = single_set (temp)) != 0
1411                       && (note = find_reg_equal_equiv_note (temp)) != 0
1412                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1413                       /* Avoid using a register that may already been marked
1414                          dead by an earlier instruction.  */
1415                       && ! unmentioned_reg_p (note, SET_SRC (set))
1416                       && (GET_MODE (note) == VOIDmode
1417                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1418                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1419                     {
1420                       /* Temporarily replace the set's source with the
1421                          contents of the REG_EQUAL note.  The insn will
1422                          be deleted or recognized by try_combine.  */
1423                       rtx orig = SET_SRC (set);
1424                       SET_SRC (set) = note;
1425                       i2mod = temp;
1426                       i2mod_old_rhs = copy_rtx (orig);
1427                       i2mod_new_rhs = copy_rtx (note);
1428                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1429                                           &new_direct_jump_p,
1430                                           last_combined_insn);
1431                       i2mod = NULL_RTX;
1432                       if (next)
1433                         goto retry;
1434                       SET_SRC (set) = orig;
1435                     }
1436                 }
1437
1438               if (!NOTE_P (insn))
1439                 record_dead_and_set_regs (insn);
1440
1441             retry:
1442               ;
1443             }
1444         }
1445     }
1446
1447   default_rtl_profile ();
1448   clear_bb_flags ();
1449   new_direct_jump_p |= purge_all_dead_edges ();
1450   delete_noop_moves ();
1451
1452   /* Clean up.  */
1453   obstack_free (&insn_link_obstack, NULL);
1454   free (uid_log_links);
1455   free (uid_insn_cost);
1456   reg_stat.release ();
1457
1458   {
1459     struct undo *undo, *next;
1460     for (undo = undobuf.frees; undo; undo = next)
1461       {
1462         next = undo->next;
1463         free (undo);
1464       }
1465     undobuf.frees = 0;
1466   }
1467
1468   total_attempts += combine_attempts;
1469   total_merges += combine_merges;
1470   total_extras += combine_extras;
1471   total_successes += combine_successes;
1472
1473   nonzero_sign_valid = 0;
1474   rtl_hooks = general_rtl_hooks;
1475
1476   /* Make recognizer allow volatile MEMs again.  */
1477   init_recog ();
1478
1479   return new_direct_jump_p;
1480 }
1481
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1483
1484 static void
1485 init_reg_last (void)
1486 {
1487   unsigned int i;
1488   reg_stat_type *p;
1489
1490   FOR_EACH_VEC_ELT (reg_stat, i, p)
1491     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1492 }
1493 \f
1494 /* Set up any promoted values for incoming argument registers.  */
1495
1496 static void
1497 setup_incoming_promotions (rtx first)
1498 {
1499   tree arg;
1500   bool strictly_local = false;
1501
1502   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1503        arg = DECL_CHAIN (arg))
1504     {
1505       rtx x, reg = DECL_INCOMING_RTL (arg);
1506       int uns1, uns3;
1507       enum machine_mode mode1, mode2, mode3, mode4;
1508
1509       /* Only continue if the incoming argument is in a register.  */
1510       if (!REG_P (reg))
1511         continue;
1512
1513       /* Determine, if possible, whether all call sites of the current
1514          function lie within the current compilation unit.  (This does
1515          take into account the exporting of a function via taking its
1516          address, and so forth.)  */
1517       strictly_local = cgraph_local_info (current_function_decl)->local;
1518
1519       /* The mode and signedness of the argument before any promotions happen
1520          (equal to the mode of the pseudo holding it at that stage).  */
1521       mode1 = TYPE_MODE (TREE_TYPE (arg));
1522       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1523
1524       /* The mode and signedness of the argument after any source language and
1525          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1526       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1527       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1528
1529       /* The mode and signedness of the argument as it is actually passed,
1530          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1531       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1532                                      TREE_TYPE (cfun->decl), 0);
1533
1534       /* The mode of the register in which the argument is being passed.  */
1535       mode4 = GET_MODE (reg);
1536
1537       /* Eliminate sign extensions in the callee when:
1538          (a) A mode promotion has occurred;  */
1539       if (mode1 == mode3)
1540         continue;
1541       /* (b) The mode of the register is the same as the mode of
1542              the argument as it is passed; */
1543       if (mode3 != mode4)
1544         continue;
1545       /* (c) There's no language level extension;  */
1546       if (mode1 == mode2)
1547         ;
1548       /* (c.1) All callers are from the current compilation unit.  If that's
1549          the case we don't have to rely on an ABI, we only have to know
1550          what we're generating right now, and we know that we will do the
1551          mode1 to mode2 promotion with the given sign.  */
1552       else if (!strictly_local)
1553         continue;
1554       /* (c.2) The combination of the two promotions is useful.  This is
1555          true when the signs match, or if the first promotion is unsigned.
1556          In the later case, (sign_extend (zero_extend x)) is the same as
1557          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1558       else if (uns1)
1559         uns3 = true;
1560       else if (uns3)
1561         continue;
1562
1563       /* Record that the value was promoted from mode1 to mode3,
1564          so that any sign extension at the head of the current
1565          function may be eliminated.  */
1566       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1567       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1568       record_value_for_reg (reg, first, x);
1569     }
1570 }
1571
1572 /* Called via note_stores.  If X is a pseudo that is narrower than
1573    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1574
1575    If we are setting only a portion of X and we can't figure out what
1576    portion, assume all bits will be used since we don't know what will
1577    be happening.
1578
1579    Similarly, set how many bits of X are known to be copies of the sign bit
1580    at all locations in the function.  This is the smallest number implied
1581    by any set of X.  */
1582
1583 static void
1584 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1585 {
1586   rtx insn = (rtx) data;
1587   unsigned int num;
1588
1589   if (REG_P (x)
1590       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1591       /* If this register is undefined at the start of the file, we can't
1592          say what its contents were.  */
1593       && ! REGNO_REG_SET_P
1594            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1595       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1596     {
1597       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1598
1599       if (set == 0 || GET_CODE (set) == CLOBBER)
1600         {
1601           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1602           rsp->sign_bit_copies = 1;
1603           return;
1604         }
1605
1606       /* If this register is being initialized using itself, and the
1607          register is uninitialized in this basic block, and there are
1608          no LOG_LINKS which set the register, then part of the
1609          register is uninitialized.  In that case we can't assume
1610          anything about the number of nonzero bits.
1611
1612          ??? We could do better if we checked this in
1613          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1614          could avoid making assumptions about the insn which initially
1615          sets the register, while still using the information in other
1616          insns.  We would have to be careful to check every insn
1617          involved in the combination.  */
1618
1619       if (insn
1620           && reg_referenced_p (x, PATTERN (insn))
1621           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1622                                REGNO (x)))
1623         {
1624           struct insn_link *link;
1625
1626           FOR_EACH_LOG_LINK (link, insn)
1627             if (dead_or_set_p (link->insn, x))
1628               break;
1629           if (!link)
1630             {
1631               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1632               rsp->sign_bit_copies = 1;
1633               return;
1634             }
1635         }
1636
1637       /* If this is a complex assignment, see if we can convert it into a
1638          simple assignment.  */
1639       set = expand_field_assignment (set);
1640
1641       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642          set what we know about X.  */
1643
1644       if (SET_DEST (set) == x
1645           || (paradoxical_subreg_p (SET_DEST (set))
1646               && SUBREG_REG (SET_DEST (set)) == x))
1647         {
1648           rtx src = SET_SRC (set);
1649
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651           /* If X is narrower than a word and SRC is a non-negative
1652              constant that would appear negative in the mode of X,
1653              sign-extend it for use in reg_stat[].nonzero_bits because some
1654              machines (maybe most) will actually do the sign-extension
1655              and this is the conservative approach.
1656
1657              ??? For 2.5, try to tighten up the MD files in this regard
1658              instead of this kludge.  */
1659
1660           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1661               && CONST_INT_P (src)
1662               && INTVAL (src) > 0
1663               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1664             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1665 #endif
1666
1667           /* Don't call nonzero_bits if it cannot change anything.  */
1668           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1669             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1670           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1671           if (rsp->sign_bit_copies == 0
1672               || rsp->sign_bit_copies > num)
1673             rsp->sign_bit_copies = num;
1674         }
1675       else
1676         {
1677           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1678           rsp->sign_bit_copies = 1;
1679         }
1680     }
1681 }
1682 \f
1683 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1684    optionally insns that were previously combined into I3 or that will be
1685    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1686    INSN, SUCC, SUCC2, I3.
1687
1688    Return 0 if the combination is not allowed for any reason.
1689
1690    If the combination is allowed, *PDEST will be set to the single
1691    destination of INSN and *PSRC to the single source, and this function
1692    will return 1.  */
1693
1694 static int
1695 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1696                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1697                rtx *pdest, rtx *psrc)
1698 {
1699   int i;
1700   const_rtx set = 0;
1701   rtx src, dest;
1702   rtx p;
1703 #ifdef AUTO_INC_DEC
1704   rtx link;
1705 #endif
1706   bool all_adjacent = true;
1707   int (*is_volatile_p) (const_rtx);
1708
1709   if (succ)
1710     {
1711       if (succ2)
1712         {
1713           if (next_active_insn (succ2) != i3)
1714             all_adjacent = false;
1715           if (next_active_insn (succ) != succ2)
1716             all_adjacent = false;
1717         }
1718       else if (next_active_insn (succ) != i3)
1719         all_adjacent = false;
1720       if (next_active_insn (insn) != succ)
1721         all_adjacent = false;
1722     }
1723   else if (next_active_insn (insn) != i3)
1724     all_adjacent = false;
1725
1726   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727      or a PARALLEL consisting of such a SET and CLOBBERs.
1728
1729      If INSN has CLOBBER parallel parts, ignore them for our processing.
1730      By definition, these happen during the execution of the insn.  When it
1731      is merged with another insn, all bets are off.  If they are, in fact,
1732      needed and aren't also supplied in I3, they may be added by
1733      recog_for_combine.  Otherwise, it won't match.
1734
1735      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1736      note.
1737
1738      Get the source and destination of INSN.  If more than one, can't
1739      combine.  */
1740
1741   if (GET_CODE (PATTERN (insn)) == SET)
1742     set = PATTERN (insn);
1743   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1744            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1745     {
1746       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1747         {
1748           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1749
1750           switch (GET_CODE (elt))
1751             {
1752             /* This is important to combine floating point insns
1753                for the SH4 port.  */
1754             case USE:
1755               /* Combining an isolated USE doesn't make sense.
1756                  We depend here on combinable_i3pat to reject them.  */
1757               /* The code below this loop only verifies that the inputs of
1758                  the SET in INSN do not change.  We call reg_set_between_p
1759                  to verify that the REG in the USE does not change between
1760                  I3 and INSN.
1761                  If the USE in INSN was for a pseudo register, the matching
1762                  insn pattern will likely match any register; combining this
1763                  with any other USE would only be safe if we knew that the
1764                  used registers have identical values, or if there was
1765                  something to tell them apart, e.g. different modes.  For
1766                  now, we forgo such complicated tests and simply disallow
1767                  combining of USES of pseudo registers with any other USE.  */
1768               if (REG_P (XEXP (elt, 0))
1769                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1770                 {
1771                   rtx i3pat = PATTERN (i3);
1772                   int i = XVECLEN (i3pat, 0) - 1;
1773                   unsigned int regno = REGNO (XEXP (elt, 0));
1774
1775                   do
1776                     {
1777                       rtx i3elt = XVECEXP (i3pat, 0, i);
1778
1779                       if (GET_CODE (i3elt) == USE
1780                           && REG_P (XEXP (i3elt, 0))
1781                           && (REGNO (XEXP (i3elt, 0)) == regno
1782                               ? reg_set_between_p (XEXP (elt, 0),
1783                                                    PREV_INSN (insn), i3)
1784                               : regno >= FIRST_PSEUDO_REGISTER))
1785                         return 0;
1786                     }
1787                   while (--i >= 0);
1788                 }
1789               break;
1790
1791               /* We can ignore CLOBBERs.  */
1792             case CLOBBER:
1793               break;
1794
1795             case SET:
1796               /* Ignore SETs whose result isn't used but not those that
1797                  have side-effects.  */
1798               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1799                   && insn_nothrow_p (insn)
1800                   && !side_effects_p (elt))
1801                 break;
1802
1803               /* If we have already found a SET, this is a second one and
1804                  so we cannot combine with this insn.  */
1805               if (set)
1806                 return 0;
1807
1808               set = elt;
1809               break;
1810
1811             default:
1812               /* Anything else means we can't combine.  */
1813               return 0;
1814             }
1815         }
1816
1817       if (set == 0
1818           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819              so don't do anything with it.  */
1820           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1821         return 0;
1822     }
1823   else
1824     return 0;
1825
1826   if (set == 0)
1827     return 0;
1828
1829   /* The simplification in expand_field_assignment may call back to
1830      get_last_value, so set safe guard here.  */
1831   subst_low_luid = DF_INSN_LUID (insn);
1832
1833   set = expand_field_assignment (set);
1834   src = SET_SRC (set), dest = SET_DEST (set);
1835
1836   /* Don't eliminate a store in the stack pointer.  */
1837   if (dest == stack_pointer_rtx
1838       /* Don't combine with an insn that sets a register to itself if it has
1839          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1840       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1841       /* Can't merge an ASM_OPERANDS.  */
1842       || GET_CODE (src) == ASM_OPERANDS
1843       /* Can't merge a function call.  */
1844       || GET_CODE (src) == CALL
1845       /* Don't eliminate a function call argument.  */
1846       || (CALL_P (i3)
1847           && (find_reg_fusage (i3, USE, dest)
1848               || (REG_P (dest)
1849                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1850                   && global_regs[REGNO (dest)])))
1851       /* Don't substitute into an incremented register.  */
1852       || FIND_REG_INC_NOTE (i3, dest)
1853       || (succ && FIND_REG_INC_NOTE (succ, dest))
1854       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1855       /* Don't substitute into a non-local goto, this confuses CFG.  */
1856       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1857       /* Make sure that DEST is not used after SUCC but before I3.  */
1858       || (!all_adjacent
1859           && ((succ2
1860                && (reg_used_between_p (dest, succ2, i3)
1861                    || reg_used_between_p (dest, succ, succ2)))
1862               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1863       /* Make sure that the value that is to be substituted for the register
1864          does not use any registers whose values alter in between.  However,
1865          If the insns are adjacent, a use can't cross a set even though we
1866          think it might (this can happen for a sequence of insns each setting
1867          the same destination; last_set of that register might point to
1868          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1869          equivalent to the memory so the substitution is valid even if there
1870          are intervening stores.  Also, don't move a volatile asm or
1871          UNSPEC_VOLATILE across any other insns.  */
1872       || (! all_adjacent
1873           && (((!MEM_P (src)
1874                 || ! find_reg_note (insn, REG_EQUIV, src))
1875                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1876               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1877               || GET_CODE (src) == UNSPEC_VOLATILE))
1878       /* Don't combine across a CALL_INSN, because that would possibly
1879          change whether the life span of some REGs crosses calls or not,
1880          and it is a pain to update that information.
1881          Exception: if source is a constant, moving it later can't hurt.
1882          Accept that as a special case.  */
1883       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1884     return 0;
1885
1886   /* DEST must either be a REG or CC0.  */
1887   if (REG_P (dest))
1888     {
1889       /* If register alignment is being enforced for multi-word items in all
1890          cases except for parameters, it is possible to have a register copy
1891          insn referencing a hard register that is not allowed to contain the
1892          mode being copied and which would not be valid as an operand of most
1893          insns.  Eliminate this problem by not combining with such an insn.
1894
1895          Also, on some machines we don't want to extend the life of a hard
1896          register.  */
1897
1898       if (REG_P (src)
1899           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1900                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1901               /* Don't extend the life of a hard register unless it is
1902                  user variable (if we have few registers) or it can't
1903                  fit into the desired register (meaning something special
1904                  is going on).
1905                  Also avoid substituting a return register into I3, because
1906                  reload can't handle a conflict with constraints of other
1907                  inputs.  */
1908               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1909                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1910         return 0;
1911     }
1912   else if (GET_CODE (dest) != CC0)
1913     return 0;
1914
1915
1916   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1917     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1918       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1919         {
1920           /* Don't substitute for a register intended as a clobberable
1921              operand.  */
1922           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1923           if (rtx_equal_p (reg, dest))
1924             return 0;
1925
1926           /* If the clobber represents an earlyclobber operand, we must not
1927              substitute an expression containing the clobbered register.
1928              As we do not analyze the constraint strings here, we have to
1929              make the conservative assumption.  However, if the register is
1930              a fixed hard reg, the clobber cannot represent any operand;
1931              we leave it up to the machine description to either accept or
1932              reject use-and-clobber patterns.  */
1933           if (!REG_P (reg)
1934               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1935               || !fixed_regs[REGNO (reg)])
1936             if (reg_overlap_mentioned_p (reg, src))
1937               return 0;
1938         }
1939
1940   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941      or not), reject, unless nothing volatile comes between it and I3 */
1942
1943   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1944     {
1945       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1946       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1947         return 0;
1948       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1949         return 0;
1950       /* We'll check insns between INSN and I3 below.  */
1951     }
1952
1953   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954      to be an explicit register variable, and was chosen for a reason.  */
1955
1956   if (GET_CODE (src) == ASM_OPERANDS
1957       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1958     return 0;
1959
1960   /* If INSN contains volatile references (specifically volatile MEMs),
1961      we cannot combine across any other volatile references.
1962      Even if INSN doesn't contain volatile references, any intervening
1963      volatile insn might affect machine state.  */
1964
1965   is_volatile_p = volatile_refs_p (PATTERN (insn))
1966     ? volatile_refs_p
1967     : volatile_insn_p;
1968
1969   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1970     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1971       return 0;
1972
1973   /* If INSN contains an autoincrement or autodecrement, make sure that
1974      register is not used between there and I3, and not already used in
1975      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1976      Also insist that I3 not be a jump; if it were one
1977      and the incremented register were spilled, we would lose.  */
1978
1979 #ifdef AUTO_INC_DEC
1980   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1981     if (REG_NOTE_KIND (link) == REG_INC
1982         && (JUMP_P (i3)
1983             || reg_used_between_p (XEXP (link, 0), insn, i3)
1984             || (pred != NULL_RTX
1985                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1986             || (pred2 != NULL_RTX
1987                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1988             || (succ != NULL_RTX
1989                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1990             || (succ2 != NULL_RTX
1991                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1992             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1993       return 0;
1994 #endif
1995
1996 #ifdef HAVE_cc0
1997   /* Don't combine an insn that follows a CC0-setting insn.
1998      An insn that uses CC0 must not be separated from the one that sets it.
1999      We do, however, allow I2 to follow a CC0-setting insn if that insn
2000      is passed as I1; in that case it will be deleted also.
2001      We also allow combining in this case if all the insns are adjacent
2002      because that would leave the two CC0 insns adjacent as well.
2003      It would be more logical to test whether CC0 occurs inside I1 or I2,
2004      but that would be much slower, and this ought to be equivalent.  */
2005
2006   p = prev_nonnote_insn (insn);
2007   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2008       && ! all_adjacent)
2009     return 0;
2010 #endif
2011
2012   /* If we get here, we have passed all the tests and the combination is
2013      to be allowed.  */
2014
2015   *pdest = dest;
2016   *psrc = src;
2017
2018   return 1;
2019 }
2020 \f
2021 /* LOC is the location within I3 that contains its pattern or the component
2022    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2023
2024    One problem is if I3 modifies its output, as opposed to replacing it
2025    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026    doing so would produce an insn that is not equivalent to the original insns.
2027
2028    Consider:
2029
2030          (set (reg:DI 101) (reg:DI 100))
2031          (set (subreg:SI (reg:DI 101) 0) <foo>)
2032
2033    This is NOT equivalent to:
2034
2035          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036                     (set (reg:DI 101) (reg:DI 100))])
2037
2038    Not only does this modify 100 (in which case it might still be valid
2039    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2040
2041    We can also run into a problem if I2 sets a register that I1
2042    uses and I1 gets directly substituted into I3 (not via I2).  In that
2043    case, we would be getting the wrong value of I2DEST into I3, so we
2044    must reject the combination.  This case occurs when I2 and I1 both
2045    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047    of a SET must prevent combination from occurring.  The same situation
2048    can occur for I0, in which case I0_NOT_IN_SRC is set.
2049
2050    Before doing the above check, we first try to expand a field assignment
2051    into a set of logical operations.
2052
2053    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054    we place a register that is both set and used within I3.  If more than one
2055    such register is detected, we fail.
2056
2057    Return 1 if the combination is valid, zero otherwise.  */
2058
2059 static int
2060 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2061                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2062 {
2063   rtx x = *loc;
2064
2065   if (GET_CODE (x) == SET)
2066     {
2067       rtx set = x ;
2068       rtx dest = SET_DEST (set);
2069       rtx src = SET_SRC (set);
2070       rtx inner_dest = dest;
2071       rtx subdest;
2072
2073       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2074              || GET_CODE (inner_dest) == SUBREG
2075              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2076         inner_dest = XEXP (inner_dest, 0);
2077
2078       /* Check for the case where I3 modifies its output, as discussed
2079          above.  We don't want to prevent pseudos from being combined
2080          into the address of a MEM, so only prevent the combination if
2081          i1 or i2 set the same MEM.  */
2082       if ((inner_dest != dest &&
2083            (!MEM_P (inner_dest)
2084             || rtx_equal_p (i2dest, inner_dest)
2085             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2086             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2087            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2088                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2089                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2090
2091           /* This is the same test done in can_combine_p except we can't test
2092              all_adjacent; we don't have to, since this instruction will stay
2093              in place, thus we are not considering increasing the lifetime of
2094              INNER_DEST.
2095
2096              Also, if this insn sets a function argument, combining it with
2097              something that might need a spill could clobber a previous
2098              function argument; the all_adjacent test in can_combine_p also
2099              checks this; here, we do a more specific test for this case.  */
2100
2101           || (REG_P (inner_dest)
2102               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2103               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2104                                         GET_MODE (inner_dest))))
2105           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2106           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2107         return 0;
2108
2109       /* If DEST is used in I3, it is being killed in this insn, so
2110          record that for later.  We have to consider paradoxical
2111          subregs here, since they kill the whole register, but we
2112          ignore partial subregs, STRICT_LOW_PART, etc.
2113          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114          STACK_POINTER_REGNUM, since these are always considered to be
2115          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2116       subdest = dest;
2117       if (GET_CODE (subdest) == SUBREG
2118           && (GET_MODE_SIZE (GET_MODE (subdest))
2119               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2120         subdest = SUBREG_REG (subdest);
2121       if (pi3dest_killed
2122           && REG_P (subdest)
2123           && reg_referenced_p (subdest, PATTERN (i3))
2124           && REGNO (subdest) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2127 #endif
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129           && (REGNO (subdest) != ARG_POINTER_REGNUM
2130               || ! fixed_regs [REGNO (subdest)])
2131 #endif
2132           && REGNO (subdest) != STACK_POINTER_REGNUM)
2133         {
2134           if (*pi3dest_killed)
2135             return 0;
2136
2137           *pi3dest_killed = subdest;
2138         }
2139     }
2140
2141   else if (GET_CODE (x) == PARALLEL)
2142     {
2143       int i;
2144
2145       for (i = 0; i < XVECLEN (x, 0); i++)
2146         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2147                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2148           return 0;
2149     }
2150
2151   return 1;
2152 }
2153 \f
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155    and division.  We don't count multiplications by powers of two here.  */
2156
2157 static int
2158 contains_muldiv (rtx x)
2159 {
2160   switch (GET_CODE (x))
2161     {
2162     case MOD:  case DIV:  case UMOD:  case UDIV:
2163       return 1;
2164
2165     case MULT:
2166       return ! (CONST_INT_P (XEXP (x, 1))
2167                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2168     default:
2169       if (BINARY_P (x))
2170         return contains_muldiv (XEXP (x, 0))
2171             || contains_muldiv (XEXP (x, 1));
2172
2173       if (UNARY_P (x))
2174         return contains_muldiv (XEXP (x, 0));
2175
2176       return 0;
2177     }
2178 }
2179 \f
2180 /* Determine whether INSN can be used in a combination.  Return nonzero if
2181    not.  This is used in try_combine to detect early some cases where we
2182    can't perform combinations.  */
2183
2184 static int
2185 cant_combine_insn_p (rtx insn)
2186 {
2187   rtx set;
2188   rtx src, dest;
2189
2190   /* If this isn't really an insn, we can't do anything.
2191      This can occur when flow deletes an insn that it has merged into an
2192      auto-increment address.  */
2193   if (! INSN_P (insn))
2194     return 1;
2195
2196   /* Never combine loads and stores involving hard regs that are likely
2197      to be spilled.  The register allocator can usually handle such
2198      reg-reg moves by tying.  If we allow the combiner to make
2199      substitutions of likely-spilled regs, reload might die.
2200      As an exception, we allow combinations involving fixed regs; these are
2201      not available to the register allocator so there's no risk involved.  */
2202
2203   set = single_set (insn);
2204   if (! set)
2205     return 0;
2206   src = SET_SRC (set);
2207   dest = SET_DEST (set);
2208   if (GET_CODE (src) == SUBREG)
2209     src = SUBREG_REG (src);
2210   if (GET_CODE (dest) == SUBREG)
2211     dest = SUBREG_REG (dest);
2212   if (REG_P (src) && REG_P (dest)
2213       && ((HARD_REGISTER_P (src)
2214            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2215            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2216           || (HARD_REGISTER_P (dest)
2217               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2218               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2219     return 1;
2220
2221   return 0;
2222 }
2223
2224 struct likely_spilled_retval_info
2225 {
2226   unsigned regno, nregs;
2227   unsigned mask;
2228 };
2229
2230 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2231    hard registers that are known to be written to / clobbered in full.  */
2232 static void
2233 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2234 {
2235   struct likely_spilled_retval_info *const info =
2236     (struct likely_spilled_retval_info *) data;
2237   unsigned regno, nregs;
2238   unsigned new_mask;
2239
2240   if (!REG_P (XEXP (set, 0)))
2241     return;
2242   regno = REGNO (x);
2243   if (regno >= info->regno + info->nregs)
2244     return;
2245   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2246   if (regno + nregs <= info->regno)
2247     return;
2248   new_mask = (2U << (nregs - 1)) - 1;
2249   if (regno < info->regno)
2250     new_mask >>= info->regno - regno;
2251   else
2252     new_mask <<= regno - info->regno;
2253   info->mask &= ~new_mask;
2254 }
2255
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257    it is likely spilled.  This can happen when more than one insn is needed
2258    to copy the return value, e.g. when we consider to combine into the
2259    second copy insn for a complex value.  */
2260
2261 static int
2262 likely_spilled_retval_p (rtx insn)
2263 {
2264   rtx use = BB_END (this_basic_block);
2265   rtx reg, p;
2266   unsigned regno, nregs;
2267   /* We assume here that no machine mode needs more than
2268      32 hard registers when the value overlaps with a register
2269      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2270   unsigned mask;
2271   struct likely_spilled_retval_info info;
2272
2273   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2274     return 0;
2275   reg = XEXP (PATTERN (use), 0);
2276   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2277     return 0;
2278   regno = REGNO (reg);
2279   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2280   if (nregs == 1)
2281     return 0;
2282   mask = (2U << (nregs - 1)) - 1;
2283
2284   /* Disregard parts of the return value that are set later.  */
2285   info.regno = regno;
2286   info.nregs = nregs;
2287   info.mask = mask;
2288   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2289     if (INSN_P (p))
2290       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2291   mask = info.mask;
2292
2293   /* Check if any of the (probably) live return value registers is
2294      likely spilled.  */
2295   nregs --;
2296   do
2297     {
2298       if ((mask & 1 << nregs)
2299           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2300         return 1;
2301     } while (nregs--);
2302   return 0;
2303 }
2304
2305 /* Adjust INSN after we made a change to its destination.
2306
2307    Changing the destination can invalidate notes that say something about
2308    the results of the insn and a LOG_LINK pointing to the insn.  */
2309
2310 static void
2311 adjust_for_new_dest (rtx insn)
2312 {
2313   /* For notes, be conservative and simply remove them.  */
2314   remove_reg_equal_equiv_notes (insn);
2315
2316   /* The new insn will have a destination that was previously the destination
2317      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2318      the next use of that destination.  */
2319   distribute_links (alloc_insn_link (insn, NULL));
2320
2321   df_insn_rescan (insn);
2322 }
2323
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325    ADDED_SETS is nonzero if the original set is still required.  */
2326 static bool
2327 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2328 {
2329   unsigned int regno;
2330
2331   if (!REG_P(x))
2332     return false;
2333
2334   regno = REGNO (x);
2335   /* Allow hard registers if the new mode is legal, and occupies no more
2336      registers than the old mode.  */
2337   if (regno < FIRST_PSEUDO_REGISTER)
2338     return (HARD_REGNO_MODE_OK (regno, mode)
2339             && (hard_regno_nregs[regno][GET_MODE (x)]
2340                 >= hard_regno_nregs[regno][mode]));
2341
2342   /* Or a pseudo that is only used once.  */
2343   return (REG_N_SETS (regno) == 1 && !added_sets
2344           && !REG_USERVAR_P (x));
2345 }
2346
2347
2348 /* Check whether X, the destination of a set, refers to part of
2349    the register specified by REG.  */
2350
2351 static bool
2352 reg_subword_p (rtx x, rtx reg)
2353 {
2354   /* Check that reg is an integer mode register.  */
2355   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2356     return false;
2357
2358   if (GET_CODE (x) == STRICT_LOW_PART
2359       || GET_CODE (x) == ZERO_EXTRACT)
2360     x = XEXP (x, 0);
2361
2362   return GET_CODE (x) == SUBREG
2363          && SUBREG_REG (x) == reg
2364          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2365 }
2366
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368    Note that the INSN should be deleted *after* removing dead edges, so
2369    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370    but not for a (set (pc) (label_ref FOO)).  */
2371
2372 static void
2373 update_cfg_for_uncondjump (rtx insn)
2374 {
2375   basic_block bb = BLOCK_FOR_INSN (insn);
2376   gcc_assert (BB_END (bb) == insn);
2377
2378   purge_dead_edges (bb);
2379
2380   delete_insn (insn);
2381   if (EDGE_COUNT (bb->succs) == 1)
2382     {
2383       rtx insn;
2384
2385       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2386
2387       /* Remove barriers from the footer if there are any.  */
2388       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2389         if (BARRIER_P (insn))
2390           {
2391             if (PREV_INSN (insn))
2392               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2393             else
2394               BB_FOOTER (bb) = NEXT_INSN (insn);
2395             if (NEXT_INSN (insn))
2396               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2397           }
2398         else if (LABEL_P (insn))
2399           break;
2400     }
2401 }
2402
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404    Here I0, I1 and I2 appear earlier than I3.
2405    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2406    I3.
2407
2408    If we are combining more than two insns and the resulting insn is not
2409    recognized, try splitting it into two insns.  If that happens, I2 and I3
2410    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411    Otherwise, I0, I1 and I2 are pseudo-deleted.
2412
2413    Return 0 if the combination does not work.  Then nothing is changed.
2414    If we did the combination, return the insn at which combine should
2415    resume scanning.
2416
2417    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418    new direct jump instruction.
2419
2420    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421    been I3 passed to an earlier try_combine within the same basic
2422    block.  */
2423
2424 static rtx
2425 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2426              rtx last_combined_insn)
2427 {
2428   /* New patterns for I3 and I2, respectively.  */
2429   rtx newpat, newi2pat = 0;
2430   rtvec newpat_vec_with_clobbers = 0;
2431   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2432   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2433      dead.  */
2434   int added_sets_0, added_sets_1, added_sets_2;
2435   /* Total number of SETs to put into I3.  */
2436   int total_sets;
2437   /* Nonzero if I2's or I1's body now appears in I3.  */
2438   int i2_is_used = 0, i1_is_used = 0;
2439   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2440   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2441   /* Contains I3 if the destination of I3 is used in its source, which means
2442      that the old life of I3 is being killed.  If that usage is placed into
2443      I2 and not in I3, a REG_DEAD note must be made.  */
2444   rtx i3dest_killed = 0;
2445   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2446   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2447   /* Copy of SET_SRC of I1 and I0, if needed.  */
2448   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2449   /* Set if I2DEST was reused as a scratch register.  */
2450   bool i2scratch = false;
2451   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2452   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2453   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2454   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2455   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2456   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2457   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2458   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2459   rtx new_i3_notes, new_i2_notes;
2460   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2461   int i3_subst_into_i2 = 0;
2462   /* Notes that I1, I2 or I3 is a MULT operation.  */
2463   int have_mult = 0;
2464   int swap_i2i3 = 0;
2465   int changed_i3_dest = 0;
2466
2467   int maxreg;
2468   rtx temp;
2469   struct insn_link *link;
2470   rtx other_pat = 0;
2471   rtx new_other_notes;
2472   int i;
2473
2474   /* Only try four-insn combinations when there's high likelihood of
2475      success.  Look for simple insns, such as loads of constants or
2476      binary operations involving a constant.  */
2477   if (i0)
2478     {
2479       int i;
2480       int ngood = 0;
2481       int nshift = 0;
2482
2483       if (!flag_expensive_optimizations)
2484         return 0;
2485
2486       for (i = 0; i < 4; i++)
2487         {
2488           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2489           rtx set = single_set (insn);
2490           rtx src;
2491           if (!set)
2492             continue;
2493           src = SET_SRC (set);
2494           if (CONSTANT_P (src))
2495             {
2496               ngood += 2;
2497               break;
2498             }
2499           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2500             ngood++;
2501           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2502                    || GET_CODE (src) == LSHIFTRT)
2503             nshift++;
2504         }
2505       if (ngood < 2 && nshift < 2)
2506         return 0;
2507     }
2508
2509   /* Exit early if one of the insns involved can't be used for
2510      combinations.  */
2511   if (cant_combine_insn_p (i3)
2512       || cant_combine_insn_p (i2)
2513       || (i1 && cant_combine_insn_p (i1))
2514       || (i0 && cant_combine_insn_p (i0))
2515       || likely_spilled_retval_p (i3))
2516     return 0;
2517
2518   combine_attempts++;
2519   undobuf.other_insn = 0;
2520
2521   /* Reset the hard register usage information.  */
2522   CLEAR_HARD_REG_SET (newpat_used_regs);
2523
2524   if (dump_file && (dump_flags & TDF_DETAILS))
2525     {
2526       if (i0)
2527         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2528                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2529       else if (i1)
2530         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2531                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2532       else
2533         fprintf (dump_file, "\nTrying %d -> %d:\n",
2534                  INSN_UID (i2), INSN_UID (i3));
2535     }
2536
2537   /* If multiple insns feed into one of I2 or I3, they can be in any
2538      order.  To simplify the code below, reorder them in sequence.  */
2539   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2540     temp = i2, i2 = i0, i0 = temp;
2541   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2542     temp = i1, i1 = i0, i0 = temp;
2543   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2544     temp = i1, i1 = i2, i2 = temp;
2545
2546   added_links_insn = 0;
2547
2548   /* First check for one important special case that the code below will
2549      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2550      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2551      we may be able to replace that destination with the destination of I3.
2552      This occurs in the common code where we compute both a quotient and
2553      remainder into a structure, in which case we want to do the computation
2554      directly into the structure to avoid register-register copies.
2555
2556      Note that this case handles both multiple sets in I2 and also cases
2557      where I2 has a number of CLOBBERs inside the PARALLEL.
2558
2559      We make very conservative checks below and only try to handle the
2560      most common cases of this.  For example, we only handle the case
2561      where I2 and I3 are adjacent to avoid making difficult register
2562      usage tests.  */
2563
2564   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2565       && REG_P (SET_SRC (PATTERN (i3)))
2566       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2567       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2568       && GET_CODE (PATTERN (i2)) == PARALLEL
2569       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2570       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571          below would need to check what is inside (and reg_overlap_mentioned_p
2572          doesn't support those codes anyway).  Don't allow those destinations;
2573          the resulting insn isn't likely to be recognized anyway.  */
2574       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2575       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2576       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2577                                     SET_DEST (PATTERN (i3)))
2578       && next_active_insn (i2) == i3)
2579     {
2580       rtx p2 = PATTERN (i2);
2581
2582       /* Make sure that the destination of I3,
2583          which we are going to substitute into one output of I2,
2584          is not used within another output of I2.  We must avoid making this:
2585          (parallel [(set (mem (reg 69)) ...)
2586                     (set (reg 69) ...)])
2587          which is not well-defined as to order of actions.
2588          (Besides, reload can't handle output reloads for this.)
2589
2590          The problem can also happen if the dest of I3 is a memory ref,
2591          if another dest in I2 is an indirect memory ref.  */
2592       for (i = 0; i < XVECLEN (p2, 0); i++)
2593         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2594              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2595             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2596                                         SET_DEST (XVECEXP (p2, 0, i))))
2597           break;
2598
2599       if (i == XVECLEN (p2, 0))
2600         for (i = 0; i < XVECLEN (p2, 0); i++)
2601           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2602               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2603             {
2604               combine_merges++;
2605
2606               subst_insn = i3;
2607               subst_low_luid = DF_INSN_LUID (i2);
2608
2609               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2610               i2src = SET_SRC (XVECEXP (p2, 0, i));
2611               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2612               i2dest_killed = dead_or_set_p (i2, i2dest);
2613
2614               /* Replace the dest in I2 with our dest and make the resulting
2615                  insn the new pattern for I3.  Then skip to where we validate
2616                  the pattern.  Everything was set up above.  */
2617               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2618               newpat = p2;
2619               i3_subst_into_i2 = 1;
2620               goto validate_replacement;
2621             }
2622     }
2623
2624   /* If I2 is setting a pseudo to a constant and I3 is setting some
2625      sub-part of it to another constant, merge them by making a new
2626      constant.  */
2627   if (i1 == 0
2628       && (temp = single_set (i2)) != 0
2629       && CONST_SCALAR_INT_P (SET_SRC (temp))
2630       && GET_CODE (PATTERN (i3)) == SET
2631       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2632       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2633     {
2634       rtx dest = SET_DEST (PATTERN (i3));
2635       int offset = -1;
2636       int width = 0;
2637
2638       if (GET_CODE (dest) == ZERO_EXTRACT)
2639         {
2640           if (CONST_INT_P (XEXP (dest, 1))
2641               && CONST_INT_P (XEXP (dest, 2)))
2642             {
2643               width = INTVAL (XEXP (dest, 1));
2644               offset = INTVAL (XEXP (dest, 2));
2645               dest = XEXP (dest, 0);
2646               if (BITS_BIG_ENDIAN)
2647                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2648             }
2649         }
2650       else
2651         {
2652           if (GET_CODE (dest) == STRICT_LOW_PART)
2653             dest = XEXP (dest, 0);
2654           width = GET_MODE_PRECISION (GET_MODE (dest));
2655           offset = 0;
2656         }
2657
2658       if (offset >= 0)
2659         {
2660           /* If this is the low part, we're done.  */
2661           if (subreg_lowpart_p (dest))
2662             ;
2663           /* Handle the case where inner is twice the size of outer.  */
2664           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2665                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2666             offset += GET_MODE_PRECISION (GET_MODE (dest));
2667           /* Otherwise give up for now.  */
2668           else
2669             offset = -1;
2670         }
2671
2672       if (offset >= 0
2673           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2674               <= HOST_BITS_PER_DOUBLE_INT))
2675         {
2676           double_int m, o, i;
2677           rtx inner = SET_SRC (PATTERN (i3));
2678           rtx outer = SET_SRC (temp);
2679
2680           o = rtx_to_double_int (outer);
2681           i = rtx_to_double_int (inner);
2682
2683           m = double_int::mask (width);
2684           i &= m;
2685           m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2686           i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2687           o = o.and_not (m) | i;
2688
2689           combine_merges++;
2690           subst_insn = i3;
2691           subst_low_luid = DF_INSN_LUID (i2);
2692           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2693           i2dest = SET_DEST (temp);
2694           i2dest_killed = dead_or_set_p (i2, i2dest);
2695
2696           /* Replace the source in I2 with the new constant and make the
2697              resulting insn the new pattern for I3.  Then skip to where we
2698              validate the pattern.  Everything was set up above.  */
2699           SUBST (SET_SRC (temp),
2700                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2701
2702           newpat = PATTERN (i2);
2703
2704           /* The dest of I3 has been replaced with the dest of I2.  */
2705           changed_i3_dest = 1;
2706           goto validate_replacement;
2707         }
2708     }
2709
2710 #ifndef HAVE_cc0
2711   /* If we have no I1 and I2 looks like:
2712         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2713                    (set Y OP)])
2714      make up a dummy I1 that is
2715         (set Y OP)
2716      and change I2 to be
2717         (set (reg:CC X) (compare:CC Y (const_int 0)))
2718
2719      (We can ignore any trailing CLOBBERs.)
2720
2721      This undoes a previous combination and allows us to match a branch-and-
2722      decrement insn.  */
2723
2724   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2725       && XVECLEN (PATTERN (i2), 0) >= 2
2726       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2727       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2728           == MODE_CC)
2729       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2730       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2731       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2732       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2733       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2734                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2735     {
2736       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2737         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2738           break;
2739
2740       if (i == 1)
2741         {
2742           /* We make I1 with the same INSN_UID as I2.  This gives it
2743              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2744              never appear in the insn stream so giving it the same INSN_UID
2745              as I2 will not cause a problem.  */
2746
2747           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2748                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2749                              INSN_LOCATION (i2), -1, NULL_RTX);
2750
2751           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2752           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2753                  SET_DEST (PATTERN (i1)));
2754           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2755         }
2756     }
2757 #endif
2758
2759   /* Verify that I2 and I1 are valid for combining.  */
2760   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2761       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2762                                  &i1dest, &i1src))
2763       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2764                                  &i0dest, &i0src)))
2765     {
2766       undo_all ();
2767       return 0;
2768     }
2769
2770   /* Record whether I2DEST is used in I2SRC and similarly for the other
2771      cases.  Knowing this will help in register status updating below.  */
2772   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2773   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2774   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2775   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2776   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2777   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2778   i2dest_killed = dead_or_set_p (i2, i2dest);
2779   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2780   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2781
2782   /* For the earlier insns, determine which of the subsequent ones they
2783      feed.  */
2784   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2785   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2786   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2787                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2788                              && reg_overlap_mentioned_p (i0dest, i2src))));
2789
2790   /* Ensure that I3's pattern can be the destination of combines.  */
2791   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2792                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2793                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2794                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2795                           &i3dest_killed))
2796     {
2797       undo_all ();
2798       return 0;
2799     }
2800
2801   /* See if any of the insns is a MULT operation.  Unless one is, we will
2802      reject a combination that is, since it must be slower.  Be conservative
2803      here.  */
2804   if (GET_CODE (i2src) == MULT
2805       || (i1 != 0 && GET_CODE (i1src) == MULT)
2806       || (i0 != 0 && GET_CODE (i0src) == MULT)
2807       || (GET_CODE (PATTERN (i3)) == SET
2808           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2809     have_mult = 1;
2810
2811   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2812      We used to do this EXCEPT in one case: I3 has a post-inc in an
2813      output operand.  However, that exception can give rise to insns like
2814         mov r3,(r3)+
2815      which is a famous insn on the PDP-11 where the value of r3 used as the
2816      source was model-dependent.  Avoid this sort of thing.  */
2817
2818 #if 0
2819   if (!(GET_CODE (PATTERN (i3)) == SET
2820         && REG_P (SET_SRC (PATTERN (i3)))
2821         && MEM_P (SET_DEST (PATTERN (i3)))
2822         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2823             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2824     /* It's not the exception.  */
2825 #endif
2826 #ifdef AUTO_INC_DEC
2827     {
2828       rtx link;
2829       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2830         if (REG_NOTE_KIND (link) == REG_INC
2831             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2832                 || (i1 != 0
2833                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2834           {
2835             undo_all ();
2836             return 0;
2837           }
2838     }
2839 #endif
2840
2841   /* See if the SETs in I1 or I2 need to be kept around in the merged
2842      instruction: whenever the value set there is still needed past I3.
2843      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2844
2845      For the SET in I1, we have two cases: if I1 and I2 independently feed
2846      into I3, the set in I1 needs to be kept around unless I1DEST dies
2847      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2848      in I1 needs to be kept around unless I1DEST dies or is set in either
2849      I2 or I3.  The same considerations apply to I0.  */
2850
2851   added_sets_2 = !dead_or_set_p (i3, i2dest);
2852
2853   if (i1)
2854     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2855                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2856   else
2857     added_sets_1 = 0;
2858
2859   if (i0)
2860     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2861                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2862                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2863                           && dead_or_set_p (i2, i0dest)));
2864   else
2865     added_sets_0 = 0;
2866
2867   /* We are about to copy insns for the case where they need to be kept
2868      around.  Check that they can be copied in the merged instruction.  */
2869
2870   if (targetm.cannot_copy_insn_p
2871       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2872           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2873           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2874     {
2875       undo_all ();
2876       return 0;
2877     }
2878
2879   /* If the set in I2 needs to be kept around, we must make a copy of
2880      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2881      PATTERN (I2), we are only substituting for the original I1DEST, not into
2882      an already-substituted copy.  This also prevents making self-referential
2883      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2884      I2DEST.  */
2885
2886   if (added_sets_2)
2887     {
2888       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2889         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2890       else
2891         i2pat = copy_rtx (PATTERN (i2));
2892     }
2893
2894   if (added_sets_1)
2895     {
2896       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2897         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2898       else
2899         i1pat = copy_rtx (PATTERN (i1));
2900     }
2901
2902   if (added_sets_0)
2903     {
2904       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2905         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2906       else
2907         i0pat = copy_rtx (PATTERN (i0));
2908     }
2909
2910   combine_merges++;
2911
2912   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2913
2914   maxreg = max_reg_num ();
2915
2916   subst_insn = i3;
2917
2918 #ifndef HAVE_cc0
2919   /* Many machines that don't use CC0 have insns that can both perform an
2920      arithmetic operation and set the condition code.  These operations will
2921      be represented as a PARALLEL with the first element of the vector
2922      being a COMPARE of an arithmetic operation with the constant zero.
2923      The second element of the vector will set some pseudo to the result
2924      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2925      match such a pattern and so will generate an extra insn.   Here we test
2926      for this case, where both the comparison and the operation result are
2927      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2928      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2929
2930   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2931       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2932       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2933       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2934     {
2935       rtx newpat_dest;
2936       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2937       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2938       enum machine_mode compare_mode, orig_compare_mode;
2939       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2940
2941       newpat = PATTERN (i3);
2942       newpat_dest = SET_DEST (newpat);
2943       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2944
2945       if (undobuf.other_insn == 0
2946           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2947                                             &cc_use_insn)))
2948         {
2949           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2950           compare_code = simplify_compare_const (compare_code,
2951                                                  op0, &op1);
2952           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2953         }
2954
2955       /* Do the rest only if op1 is const0_rtx, which may be the
2956          result of simplification.  */
2957       if (op1 == const0_rtx)
2958         {
2959           /* If a single use of the CC is found, prepare to modify it
2960              when SELECT_CC_MODE returns a new CC-class mode, or when
2961              the above simplify_compare_const() returned a new comparison
2962              operator.  undobuf.other_insn is assigned the CC use insn
2963              when modifying it.  */
2964           if (cc_use_loc)
2965             {
2966 #ifdef SELECT_CC_MODE
2967               enum machine_mode new_mode
2968                 = SELECT_CC_MODE (compare_code, op0, op1);
2969               if (new_mode != orig_compare_mode
2970                   && can_change_dest_mode (SET_DEST (newpat),
2971                                            added_sets_2, new_mode))
2972                 {
2973                   unsigned int regno = REGNO (newpat_dest);
2974                   compare_mode = new_mode;
2975                   if (regno < FIRST_PSEUDO_REGISTER)
2976                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2977                   else
2978                     {
2979                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2980                       newpat_dest = regno_reg_rtx[regno];
2981                     }
2982                 }
2983 #endif
2984               /* Cases for modifying the CC-using comparison.  */
2985               if (compare_code != orig_compare_code
2986                   /* ??? Do we need to verify the zero rtx?  */
2987                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2988                 {
2989                   /* Replace cc_use_loc with entire new RTX.  */
2990                   SUBST (*cc_use_loc,
2991                          gen_rtx_fmt_ee (compare_code, compare_mode,
2992                                          newpat_dest, const0_rtx));
2993                   undobuf.other_insn = cc_use_insn;
2994                 }
2995               else if (compare_mode != orig_compare_mode)
2996                 {
2997                   /* Just replace the CC reg with a new mode.  */
2998                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
2999                   undobuf.other_insn = cc_use_insn;
3000                 }
3001             }
3002
3003           /* Now we modify the current newpat:
3004              First, SET_DEST(newpat) is updated if the CC mode has been
3005              altered. For targets without SELECT_CC_MODE, this should be
3006              optimized away.  */
3007           if (compare_mode != orig_compare_mode)
3008             SUBST (SET_DEST (newpat), newpat_dest);
3009           /* This is always done to propagate i2src into newpat.  */
3010           SUBST (SET_SRC (newpat),
3011                  gen_rtx_COMPARE (compare_mode, op0, op1));
3012           /* Create new version of i2pat if needed; the below PARALLEL
3013              creation needs this to work correctly.  */
3014           if (! rtx_equal_p (i2src, op0))
3015             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3016           i2_is_used = 1;
3017         }
3018     }
3019 #endif
3020
3021   if (i2_is_used == 0)
3022     {
3023       /* It is possible that the source of I2 or I1 may be performing
3024          an unneeded operation, such as a ZERO_EXTEND of something
3025          that is known to have the high part zero.  Handle that case
3026          by letting subst look at the inner insns.
3027
3028          Another way to do this would be to have a function that tries
3029          to simplify a single insn instead of merging two or more
3030          insns.  We don't do this because of the potential of infinite
3031          loops and because of the potential extra memory required.
3032          However, doing it the way we are is a bit of a kludge and
3033          doesn't catch all cases.
3034
3035          But only do this if -fexpensive-optimizations since it slows
3036          things down and doesn't usually win.
3037
3038          This is not done in the COMPARE case above because the
3039          unmodified I2PAT is used in the PARALLEL and so a pattern
3040          with a modified I2SRC would not match.  */
3041
3042       if (flag_expensive_optimizations)
3043         {
3044           /* Pass pc_rtx so no substitutions are done, just
3045              simplifications.  */
3046           if (i1)
3047             {
3048               subst_low_luid = DF_INSN_LUID (i1);
3049               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3050             }
3051
3052           subst_low_luid = DF_INSN_LUID (i2);
3053           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3054         }
3055
3056       n_occurrences = 0;                /* `subst' counts here */
3057       subst_low_luid = DF_INSN_LUID (i2);
3058
3059       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3060          copy of I2SRC each time we substitute it, in order to avoid creating
3061          self-referential RTL when we will be substituting I1SRC for I1DEST
3062          later.  Likewise if I0 feeds into I2, either directly or indirectly
3063          through I1, and I0DEST is in I0SRC.  */
3064       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3065                       (i1_feeds_i2_n && i1dest_in_i1src)
3066                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3067                           && i0dest_in_i0src));
3068       substed_i2 = 1;
3069
3070       /* Record whether I2's body now appears within I3's body.  */
3071       i2_is_used = n_occurrences;
3072     }
3073
3074   /* If we already got a failure, don't try to do more.  Otherwise, try to
3075      substitute I1 if we have it.  */
3076
3077   if (i1 && GET_CODE (newpat) != CLOBBER)
3078     {
3079       /* Check that an autoincrement side-effect on I1 has not been lost.
3080          This happens if I1DEST is mentioned in I2 and dies there, and
3081          has disappeared from the new pattern.  */
3082       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3083            && i1_feeds_i2_n
3084            && dead_or_set_p (i2, i1dest)
3085            && !reg_overlap_mentioned_p (i1dest, newpat))
3086            /* Before we can do this substitution, we must redo the test done
3087               above (see detailed comments there) that ensures I1DEST isn't
3088               mentioned in any SETs in NEWPAT that are field assignments.  */
3089           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3090                                 0, 0, 0))
3091         {
3092           undo_all ();
3093           return 0;
3094         }
3095
3096       n_occurrences = 0;
3097       subst_low_luid = DF_INSN_LUID (i1);
3098
3099       /* If the following substitution will modify I1SRC, make a copy of it
3100          for the case where it is substituted for I1DEST in I2PAT later.  */
3101       if (added_sets_2 && i1_feeds_i2_n)
3102         i1src_copy = copy_rtx (i1src);
3103
3104       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3105          copy of I1SRC each time we substitute it, in order to avoid creating
3106          self-referential RTL when we will be substituting I0SRC for I0DEST
3107          later.  */
3108       newpat = subst (newpat, i1dest, i1src, 0, 0,
3109                       i0_feeds_i1_n && i0dest_in_i0src);
3110       substed_i1 = 1;
3111
3112       /* Record whether I1's body now appears within I3's body.  */
3113       i1_is_used = n_occurrences;
3114     }
3115
3116   /* Likewise for I0 if we have it.  */
3117
3118   if (i0 && GET_CODE (newpat) != CLOBBER)
3119     {
3120       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3121            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3122                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3123            && !reg_overlap_mentioned_p (i0dest, newpat))
3124           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3125                                 0, 0, 0))
3126         {
3127           undo_all ();
3128           return 0;
3129         }
3130
3131       /* If the following substitution will modify I0SRC, make a copy of it
3132          for the case where it is substituted for I0DEST in I1PAT later.  */
3133       if (added_sets_1 && i0_feeds_i1_n)
3134         i0src_copy = copy_rtx (i0src);
3135       /* And a copy for I0DEST in I2PAT substitution.  */
3136       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3137                            || (i0_feeds_i2_n)))
3138         i0src_copy2 = copy_rtx (i0src);
3139
3140       n_occurrences = 0;
3141       subst_low_luid = DF_INSN_LUID (i0);
3142       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3143       substed_i0 = 1;
3144     }
3145
3146   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3147      to count all the ways that I2SRC and I1SRC can be used.  */
3148   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3149        && i2_is_used + added_sets_2 > 1)
3150       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3151           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3152               > 1))
3153       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3154           && (n_occurrences + added_sets_0
3155               + (added_sets_1 && i0_feeds_i1_n)
3156               + (added_sets_2 && i0_feeds_i2_n)
3157               > 1))
3158       /* Fail if we tried to make a new register.  */
3159       || max_reg_num () != maxreg
3160       /* Fail if we couldn't do something and have a CLOBBER.  */
3161       || GET_CODE (newpat) == CLOBBER
3162       /* Fail if this new pattern is a MULT and we didn't have one before
3163          at the outer level.  */
3164       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3165           && ! have_mult))
3166     {
3167       undo_all ();
3168       return 0;
3169     }
3170
3171   /* If the actions of the earlier insns must be kept
3172      in addition to substituting them into the latest one,
3173      we must make a new PARALLEL for the latest insn
3174      to hold additional the SETs.  */
3175
3176   if (added_sets_0 || added_sets_1 || added_sets_2)
3177     {
3178       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3179       combine_extras++;
3180
3181       if (GET_CODE (newpat) == PARALLEL)
3182         {
3183           rtvec old = XVEC (newpat, 0);
3184           total_sets = XVECLEN (newpat, 0) + extra_sets;
3185           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3186           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3187                   sizeof (old->elem[0]) * old->num_elem);
3188         }
3189       else
3190         {
3191           rtx old = newpat;
3192           total_sets = 1 + extra_sets;
3193           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3194           XVECEXP (newpat, 0, 0) = old;
3195         }
3196
3197       if (added_sets_0)
3198         XVECEXP (newpat, 0, --total_sets) = i0pat;
3199
3200       if (added_sets_1)
3201         {
3202           rtx t = i1pat;
3203           if (i0_feeds_i1_n)
3204             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3205
3206           XVECEXP (newpat, 0, --total_sets) = t;
3207         }
3208       if (added_sets_2)
3209         {
3210           rtx t = i2pat;
3211           if (i1_feeds_i2_n)
3212             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3213                        i0_feeds_i1_n && i0dest_in_i0src);
3214           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3215             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3216
3217           XVECEXP (newpat, 0, --total_sets) = t;
3218         }
3219     }
3220
3221  validate_replacement:
3222
3223   /* Note which hard regs this insn has as inputs.  */
3224   mark_used_regs_combine (newpat);
3225
3226   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3227      consider splitting this pattern, we might need these clobbers.  */
3228   if (i1 && GET_CODE (newpat) == PARALLEL
3229       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3230     {
3231       int len = XVECLEN (newpat, 0);
3232
3233       newpat_vec_with_clobbers = rtvec_alloc (len);
3234       for (i = 0; i < len; i++)
3235         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3236     }
3237
3238   /* Is the result of combination a valid instruction?  */
3239   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3240
3241   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242      the second SET's destination is a register that is unused and isn't
3243      marked as an instruction that might trap in an EH region.  In that case,
3244      we just need the first SET.   This can occur when simplifying a divmod
3245      insn.  We *must* test for this case here because the code below that
3246      splits two independent SETs doesn't handle this case correctly when it
3247      updates the register status.
3248
3249      It's pointless doing this if we originally had two sets, one from
3250      i3, and one from i2.  Combining then splitting the parallel results
3251      in the original i2 again plus an invalid insn (which we delete).
3252      The net effect is only to move instructions around, which makes
3253      debug info less accurate.
3254
3255      Also check the case where the first SET's destination is unused.
3256      That would not cause incorrect code, but does cause an unneeded
3257      insn to remain.  */
3258
3259   if (insn_code_number < 0
3260       && !(added_sets_2 && i1 == 0)
3261       && GET_CODE (newpat) == PARALLEL
3262       && XVECLEN (newpat, 0) == 2
3263       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3264       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3265       && asm_noperands (newpat) < 0)
3266     {
3267       rtx set0 = XVECEXP (newpat, 0, 0);
3268       rtx set1 = XVECEXP (newpat, 0, 1);
3269
3270       if (((REG_P (SET_DEST (set1))
3271             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3272            || (GET_CODE (SET_DEST (set1)) == SUBREG
3273                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3274           && insn_nothrow_p (i3)
3275           && !side_effects_p (SET_SRC (set1)))
3276         {
3277           newpat = set0;
3278           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3279         }
3280
3281       else if (((REG_P (SET_DEST (set0))
3282                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3283                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3284                     && find_reg_note (i3, REG_UNUSED,
3285                                       SUBREG_REG (SET_DEST (set0)))))
3286                && insn_nothrow_p (i3)
3287                && !side_effects_p (SET_SRC (set0)))
3288         {
3289           newpat = set1;
3290           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3291
3292           if (insn_code_number >= 0)
3293             changed_i3_dest = 1;
3294         }
3295     }
3296
3297   /* If we were combining three insns and the result is a simple SET
3298      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299      insns.  There are two ways to do this.  It can be split using a
3300      machine-specific method (like when you have an addition of a large
3301      constant) or by combine in the function find_split_point.  */
3302
3303   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3304       && asm_noperands (newpat) < 0)
3305     {
3306       rtx parallel, m_split, *split;
3307
3308       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3309          use I2DEST as a scratch register will help.  In the latter case,
3310          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3311
3312       m_split = combine_split_insns (newpat, i3);
3313
3314       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315          inputs of NEWPAT.  */
3316
3317       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318          possible to try that as a scratch reg.  This would require adding
3319          more code to make it work though.  */
3320
3321       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3322         {
3323           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3324
3325           /* First try to split using the original register as a
3326              scratch register.  */
3327           parallel = gen_rtx_PARALLEL (VOIDmode,
3328                                        gen_rtvec (2, newpat,
3329                                                   gen_rtx_CLOBBER (VOIDmode,
3330                                                                    i2dest)));
3331           m_split = combine_split_insns (parallel, i3);
3332
3333           /* If that didn't work, try changing the mode of I2DEST if
3334              we can.  */
3335           if (m_split == 0
3336               && new_mode != GET_MODE (i2dest)
3337               && new_mode != VOIDmode
3338               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3339             {
3340               enum machine_mode old_mode = GET_MODE (i2dest);
3341               rtx ni2dest;
3342
3343               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3344                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3345               else
3346                 {
3347                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3348                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3349                 }
3350
3351               parallel = (gen_rtx_PARALLEL
3352                           (VOIDmode,
3353                            gen_rtvec (2, newpat,
3354                                       gen_rtx_CLOBBER (VOIDmode,
3355                                                        ni2dest))));
3356               m_split = combine_split_insns (parallel, i3);
3357
3358               if (m_split == 0
3359                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3360                 {
3361                   struct undo *buf;
3362
3363                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3364                   buf = undobuf.undos;
3365                   undobuf.undos = buf->next;
3366                   buf->next = undobuf.frees;
3367                   undobuf.frees = buf;
3368                 }
3369             }
3370
3371           i2scratch = m_split != 0;
3372         }
3373
3374       /* If recog_for_combine has discarded clobbers, try to use them
3375          again for the split.  */
3376       if (m_split == 0 && newpat_vec_with_clobbers)
3377         {
3378           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3379           m_split = combine_split_insns (parallel, i3);
3380         }
3381
3382       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3383         {
3384           m_split = PATTERN (m_split);
3385           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3386           if (insn_code_number >= 0)
3387             newpat = m_split;
3388         }
3389       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3390                && (next_nonnote_nondebug_insn (i2) == i3
3391                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3392         {
3393           rtx i2set, i3set;
3394           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3395           newi2pat = PATTERN (m_split);
3396
3397           i3set = single_set (NEXT_INSN (m_split));
3398           i2set = single_set (m_split);
3399
3400           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3401
3402           /* If I2 or I3 has multiple SETs, we won't know how to track
3403              register status, so don't use these insns.  If I2's destination
3404              is used between I2 and I3, we also can't use these insns.  */
3405
3406           if (i2_code_number >= 0 && i2set && i3set
3407               && (next_nonnote_nondebug_insn (i2) == i3
3408                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3409             insn_code_number = recog_for_combine (&newi3pat, i3,
3410                                                   &new_i3_notes);
3411           if (insn_code_number >= 0)
3412             newpat = newi3pat;
3413
3414           /* It is possible that both insns now set the destination of I3.
3415              If so, we must show an extra use of it.  */
3416
3417           if (insn_code_number >= 0)
3418             {
3419               rtx new_i3_dest = SET_DEST (i3set);
3420               rtx new_i2_dest = SET_DEST (i2set);
3421
3422               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3423                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3424                      || GET_CODE (new_i3_dest) == SUBREG)
3425                 new_i3_dest = XEXP (new_i3_dest, 0);
3426
3427               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3428                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3429                      || GET_CODE (new_i2_dest) == SUBREG)
3430                 new_i2_dest = XEXP (new_i2_dest, 0);
3431
3432               if (REG_P (new_i3_dest)
3433                   && REG_P (new_i2_dest)
3434                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3435                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3436             }
3437         }
3438
3439       /* If we can split it and use I2DEST, go ahead and see if that
3440          helps things be recognized.  Verify that none of the registers
3441          are set between I2 and I3.  */
3442       if (insn_code_number < 0
3443           && (split = find_split_point (&newpat, i3, false)) != 0
3444 #ifdef HAVE_cc0
3445           && REG_P (i2dest)
3446 #endif
3447           /* We need I2DEST in the proper mode.  If it is a hard register
3448              or the only use of a pseudo, we can change its mode.
3449              Make sure we don't change a hard register to have a mode that
3450              isn't valid for it, or change the number of registers.  */
3451           && (GET_MODE (*split) == GET_MODE (i2dest)
3452               || GET_MODE (*split) == VOIDmode
3453               || can_change_dest_mode (i2dest, added_sets_2,
3454                                        GET_MODE (*split)))
3455           && (next_nonnote_nondebug_insn (i2) == i3
3456               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3457           /* We can't overwrite I2DEST if its value is still used by
3458              NEWPAT.  */
3459           && ! reg_referenced_p (i2dest, newpat))
3460         {
3461           rtx newdest = i2dest;
3462           enum rtx_code split_code = GET_CODE (*split);
3463           enum machine_mode split_mode = GET_MODE (*split);
3464           bool subst_done = false;
3465           newi2pat = NULL_RTX;
3466
3467           i2scratch = true;
3468
3469           /* *SPLIT may be part of I2SRC, so make sure we have the
3470              original expression around for later debug processing.
3471              We should not need I2SRC any more in other cases.  */
3472           if (MAY_HAVE_DEBUG_INSNS)
3473             i2src = copy_rtx (i2src);
3474           else
3475             i2src = NULL;
3476
3477           /* Get NEWDEST as a register in the proper mode.  We have already
3478              validated that we can do this.  */
3479           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3480             {
3481               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3482                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3483               else
3484                 {
3485                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3486                   newdest = regno_reg_rtx[REGNO (i2dest)];
3487                 }
3488             }
3489
3490           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491              an ASHIFT.  This can occur if it was inside a PLUS and hence
3492              appeared to be a memory address.  This is a kludge.  */
3493           if (split_code == MULT
3494               && CONST_INT_P (XEXP (*split, 1))
3495               && INTVAL (XEXP (*split, 1)) > 0
3496               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3497             {
3498               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3499                                              XEXP (*split, 0), GEN_INT (i)));
3500               /* Update split_code because we may not have a multiply
3501                  anymore.  */
3502               split_code = GET_CODE (*split);
3503             }
3504
3505 #ifdef INSN_SCHEDULING
3506           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507              be written as a ZERO_EXTEND.  */
3508           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3509             {
3510 #ifdef LOAD_EXTEND_OP
3511               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512                  what it really is.  */
3513               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3514                   == SIGN_EXTEND)
3515                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3516                                                     SUBREG_REG (*split)));
3517               else
3518 #endif
3519                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3520                                                     SUBREG_REG (*split)));
3521             }
3522 #endif
3523
3524           /* Attempt to split binary operators using arithmetic identities.  */
3525           if (BINARY_P (SET_SRC (newpat))
3526               && split_mode == GET_MODE (SET_SRC (newpat))
3527               && ! side_effects_p (SET_SRC (newpat)))
3528             {
3529               rtx setsrc = SET_SRC (newpat);
3530               enum machine_mode mode = GET_MODE (setsrc);
3531               enum rtx_code code = GET_CODE (setsrc);
3532               rtx src_op0 = XEXP (setsrc, 0);
3533               rtx src_op1 = XEXP (setsrc, 1);
3534
3535               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3536               if (rtx_equal_p (src_op0, src_op1))
3537                 {
3538                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3539                   SUBST (XEXP (setsrc, 0), newdest);
3540                   SUBST (XEXP (setsrc, 1), newdest);
3541                   subst_done = true;
3542                 }
3543               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3544               else if ((code == PLUS || code == MULT)
3545                        && GET_CODE (src_op0) == code
3546                        && GET_CODE (XEXP (src_op0, 0)) == code
3547                        && (INTEGRAL_MODE_P (mode)
3548                            || (FLOAT_MODE_P (mode)
3549                                && flag_unsafe_math_optimizations)))
3550                 {
3551                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3552                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3553                   rtx r = XEXP (src_op0, 1);
3554                   rtx s = src_op1;
3555
3556                   /* Split both "((X op Y) op X) op Y" and
3557                      "((X op Y) op Y) op X" as "T op T" where T is
3558                      "X op Y".  */
3559                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3560                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3561                     {
3562                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3563                                               XEXP (src_op0, 0));
3564                       SUBST (XEXP (setsrc, 0), newdest);
3565                       SUBST (XEXP (setsrc, 1), newdest);
3566                       subst_done = true;
3567                     }
3568                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3569                      T is "X op Y".  */
3570                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3571                     {
3572                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3573                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3574                       SUBST (XEXP (setsrc, 0), newdest);
3575                       SUBST (XEXP (setsrc, 1), newdest);
3576                       subst_done = true;
3577                     }
3578                 }
3579             }
3580
3581           if (!subst_done)
3582             {
3583               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3584               SUBST (*split, newdest);
3585             }
3586
3587           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3588
3589           /* recog_for_combine might have added CLOBBERs to newi2pat.
3590              Make sure NEWPAT does not depend on the clobbered regs.  */
3591           if (GET_CODE (newi2pat) == PARALLEL)
3592             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3593               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3594                 {
3595                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3596                   if (reg_overlap_mentioned_p (reg, newpat))
3597                     {
3598                       undo_all ();
3599                       return 0;
3600                     }
3601                 }
3602
3603           /* If the split point was a MULT and we didn't have one before,
3604              don't use one now.  */
3605           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3606             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3607         }
3608     }
3609
3610   /* Check for a case where we loaded from memory in a narrow mode and
3611      then sign extended it, but we need both registers.  In that case,
3612      we have a PARALLEL with both loads from the same memory location.
3613      We can split this into a load from memory followed by a register-register
3614      copy.  This saves at least one insn, more if register allocation can
3615      eliminate the copy.
3616
3617      We cannot do this if the destination of the first assignment is a
3618      condition code register or cc0.  We eliminate this case by making sure
3619      the SET_DEST and SET_SRC have the same mode.
3620
3621      We cannot do this if the destination of the second assignment is
3622      a register that we have already assumed is zero-extended.  Similarly
3623      for a SUBREG of such a register.  */
3624
3625   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3626            && GET_CODE (newpat) == PARALLEL
3627            && XVECLEN (newpat, 0) == 2
3628            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3629            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3630            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3631                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3632            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3633            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3634                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3635            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3636                                    DF_INSN_LUID (i2))
3637            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3638            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3639            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3640                  (REG_P (temp)
3641                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3642                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3643                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3644                   && (reg_stat[REGNO (temp)].nonzero_bits
3645                       != GET_MODE_MASK (word_mode))))
3646            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3647                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3648                      (REG_P (temp)
3649                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3650                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3651                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3652                       && (reg_stat[REGNO (temp)].nonzero_bits
3653                           != GET_MODE_MASK (word_mode)))))
3654            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3655                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3656            && ! find_reg_note (i3, REG_UNUSED,
3657                                SET_DEST (XVECEXP (newpat, 0, 0))))
3658     {
3659       rtx ni2dest;
3660
3661       newi2pat = XVECEXP (newpat, 0, 0);
3662       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3663       newpat = XVECEXP (newpat, 0, 1);
3664       SUBST (SET_SRC (newpat),
3665              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3666       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3667
3668       if (i2_code_number >= 0)
3669         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3670
3671       if (insn_code_number >= 0)
3672         swap_i2i3 = 1;
3673     }
3674
3675   /* Similarly, check for a case where we have a PARALLEL of two independent
3676      SETs but we started with three insns.  In this case, we can do the sets
3677      as two separate insns.  This case occurs when some SET allows two
3678      other insns to combine, but the destination of that SET is still live.  */
3679
3680   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3681            && GET_CODE (newpat) == PARALLEL
3682            && XVECLEN (newpat, 0) == 2
3683            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3684            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3685            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3686            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3687            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3688            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3689            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3690                                   XVECEXP (newpat, 0, 0))
3691            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3692                                   XVECEXP (newpat, 0, 1))
3693            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3694                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3695     {
3696       /* Normally, it doesn't matter which of the two is done first,
3697          but the one that references cc0 can't be the second, and
3698          one which uses any regs/memory set in between i2 and i3 can't
3699          be first.  */
3700       if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3701                               DF_INSN_LUID (i2))
3702 #ifdef HAVE_cc0
3703           && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3704 #endif
3705          )
3706         {
3707           newi2pat = XVECEXP (newpat, 0, 1);
3708           newpat = XVECEXP (newpat, 0, 0);
3709         }
3710       else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3711                                    DF_INSN_LUID (i2))
3712 #ifdef HAVE_cc0
3713                && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3714 #endif
3715               )
3716         {
3717           newi2pat = XVECEXP (newpat, 0, 0);
3718           newpat = XVECEXP (newpat, 0, 1);
3719         }
3720       else
3721         {
3722           undo_all ();
3723           return 0;
3724         }
3725
3726       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3727
3728       if (i2_code_number >= 0)
3729         {
3730           /* recog_for_combine might have added CLOBBERs to newi2pat.
3731              Make sure NEWPAT does not depend on the clobbered regs.  */
3732           if (GET_CODE (newi2pat) == PARALLEL)
3733             {
3734               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3735                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3736                   {
3737                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3738                     if (reg_overlap_mentioned_p (reg, newpat))
3739                       {
3740                         undo_all ();
3741                         return 0;
3742                       }
3743                   }
3744             }
3745
3746           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3747         }
3748     }
3749
3750   /* If it still isn't recognized, fail and change things back the way they
3751      were.  */
3752   if ((insn_code_number < 0
3753        /* Is the result a reasonable ASM_OPERANDS?  */
3754        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3755     {
3756       undo_all ();
3757       return 0;
3758     }
3759
3760   /* If we had to change another insn, make sure it is valid also.  */
3761   if (undobuf.other_insn)
3762     {
3763       CLEAR_HARD_REG_SET (newpat_used_regs);
3764
3765       other_pat = PATTERN (undobuf.other_insn);
3766       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3767                                              &new_other_notes);
3768
3769       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3770         {
3771           undo_all ();
3772           return 0;
3773         }
3774     }
3775
3776 #ifdef HAVE_cc0
3777   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3778      they are adjacent to each other or not.  */
3779   {
3780     rtx p = prev_nonnote_insn (i3);
3781     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3782         && sets_cc0_p (newi2pat))
3783       {
3784         undo_all ();
3785         return 0;
3786       }
3787   }
3788 #endif
3789
3790   /* Only allow this combination if insn_rtx_costs reports that the
3791      replacement instructions are cheaper than the originals.  */
3792   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3793     {
3794       undo_all ();
3795       return 0;
3796     }
3797
3798   if (MAY_HAVE_DEBUG_INSNS)
3799     {
3800       struct undo *undo;
3801
3802       for (undo = undobuf.undos; undo; undo = undo->next)
3803         if (undo->kind == UNDO_MODE)
3804           {
3805             rtx reg = *undo->where.r;
3806             enum machine_mode new_mode = GET_MODE (reg);
3807             enum machine_mode old_mode = undo->old_contents.m;
3808
3809             /* Temporarily revert mode back.  */
3810             adjust_reg_mode (reg, old_mode);
3811
3812             if (reg == i2dest && i2scratch)
3813               {
3814                 /* If we used i2dest as a scratch register with a
3815                    different mode, substitute it for the original
3816                    i2src while its original mode is temporarily
3817                    restored, and then clear i2scratch so that we don't
3818                    do it again later.  */
3819                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3820                                      this_basic_block);
3821                 i2scratch = false;
3822                 /* Put back the new mode.  */
3823                 adjust_reg_mode (reg, new_mode);
3824               }
3825             else
3826               {
3827                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3828                 rtx first, last;
3829
3830                 if (reg == i2dest)
3831                   {
3832                     first = i2;
3833                     last = last_combined_insn;
3834                   }
3835                 else
3836                   {
3837                     first = i3;
3838                     last = undobuf.other_insn;
3839                     gcc_assert (last);
3840                     if (DF_INSN_LUID (last)
3841                         < DF_INSN_LUID (last_combined_insn))
3842                       last = last_combined_insn;
3843                   }
3844
3845                 /* We're dealing with a reg that changed mode but not
3846                    meaning, so we want to turn it into a subreg for
3847                    the new mode.  However, because of REG sharing and
3848                    because its mode had already changed, we have to do
3849                    it in two steps.  First, replace any debug uses of
3850                    reg, with its original mode temporarily restored,
3851                    with this copy we have created; then, replace the
3852                    copy with the SUBREG of the original shared reg,
3853                    once again changed to the new mode.  */
3854                 propagate_for_debug (first, last, reg, tempreg,
3855                                      this_basic_block);
3856                 adjust_reg_mode (reg, new_mode);
3857                 propagate_for_debug (first, last, tempreg,
3858                                      lowpart_subreg (old_mode, reg, new_mode),
3859                                      this_basic_block);
3860               }
3861           }
3862     }
3863
3864   /* If we will be able to accept this, we have made a
3865      change to the destination of I3.  This requires us to
3866      do a few adjustments.  */
3867
3868   if (changed_i3_dest)
3869     {
3870       PATTERN (i3) = newpat;
3871       adjust_for_new_dest (i3);
3872     }
3873
3874   /* We now know that we can do this combination.  Merge the insns and
3875      update the status of registers and LOG_LINKS.  */
3876
3877   if (undobuf.other_insn)
3878     {
3879       rtx note, next;
3880
3881       PATTERN (undobuf.other_insn) = other_pat;
3882
3883       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3884          are still valid.  Then add any non-duplicate notes added by
3885          recog_for_combine.  */
3886       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3887         {
3888           next = XEXP (note, 1);
3889
3890           if (REG_NOTE_KIND (note) == REG_UNUSED
3891               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3892             remove_note (undobuf.other_insn, note);
3893         }
3894
3895       distribute_notes (new_other_notes, undobuf.other_insn,
3896                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3897                         NULL_RTX);
3898     }
3899
3900   if (swap_i2i3)
3901     {
3902       rtx insn;
3903       struct insn_link *link;
3904       rtx ni2dest;
3905
3906       /* I3 now uses what used to be its destination and which is now
3907          I2's destination.  This requires us to do a few adjustments.  */
3908       PATTERN (i3) = newpat;
3909       adjust_for_new_dest (i3);
3910
3911       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3912          so we still will.
3913
3914          However, some later insn might be using I2's dest and have
3915          a LOG_LINK pointing at I3.  We must remove this link.
3916          The simplest way to remove the link is to point it at I1,
3917          which we know will be a NOTE.  */
3918
3919       /* newi2pat is usually a SET here; however, recog_for_combine might
3920          have added some clobbers.  */
3921       if (GET_CODE (newi2pat) == PARALLEL)
3922         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3923       else
3924         ni2dest = SET_DEST (newi2pat);
3925
3926       for (insn = NEXT_INSN (i3);
3927            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3928                     || insn != BB_HEAD (this_basic_block->next_bb));
3929            insn = NEXT_INSN (insn))
3930         {
3931           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3932             {
3933               FOR_EACH_LOG_LINK (link, insn)
3934                 if (link->insn == i3)
3935                   link->insn = i1;
3936
3937               break;
3938             }
3939         }
3940     }
3941
3942   {
3943     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3944     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3945     rtx midnotes = 0;
3946     int from_luid;
3947     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3948        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3949        same as i3dest, in which case newi2pat may be setting i1dest.  */
3950     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3951                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3952                    || !i2dest_killed
3953                    ? 0 : i2dest);
3954     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3955                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3956                    || !i1dest_killed
3957                    ? 0 : i1dest);
3958     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3959                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3960                    || !i0dest_killed
3961                    ? 0 : i0dest);
3962
3963     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3964        clear them.  */
3965     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3966     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3967     if (i1)
3968       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3969     if (i0)
3970       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3971
3972     /* Ensure that we do not have something that should not be shared but
3973        occurs multiple times in the new insns.  Check this by first
3974        resetting all the `used' flags and then copying anything is shared.  */
3975
3976     reset_used_flags (i3notes);
3977     reset_used_flags (i2notes);
3978     reset_used_flags (i1notes);
3979     reset_used_flags (i0notes);
3980     reset_used_flags (newpat);
3981     reset_used_flags (newi2pat);
3982     if (undobuf.other_insn)
3983       reset_used_flags (PATTERN (undobuf.other_insn));
3984
3985     i3notes = copy_rtx_if_shared (i3notes);
3986     i2notes = copy_rtx_if_shared (i2notes);
3987     i1notes = copy_rtx_if_shared (i1notes);
3988     i0notes = copy_rtx_if_shared (i0notes);
3989     newpat = copy_rtx_if_shared (newpat);
3990     newi2pat = copy_rtx_if_shared (newi2pat);
3991     if (undobuf.other_insn)
3992       reset_used_flags (PATTERN (undobuf.other_insn));
3993
3994     INSN_CODE (i3) = insn_code_number;
3995     PATTERN (i3) = newpat;
3996
3997     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3998       {
3999         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4000
4001         reset_used_flags (call_usage);
4002         call_usage = copy_rtx (call_usage);
4003
4004         if (substed_i2)
4005           {
4006             /* I2SRC must still be meaningful at this point.  Some splitting
4007                operations can invalidate I2SRC, but those operations do not
4008                apply to calls.  */
4009             gcc_assert (i2src);
4010             replace_rtx (call_usage, i2dest, i2src);
4011           }
4012
4013         if (substed_i1)
4014           replace_rtx (call_usage, i1dest, i1src);
4015         if (substed_i0)
4016           replace_rtx (call_usage, i0dest, i0src);
4017
4018         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4019       }
4020
4021     if (undobuf.other_insn)
4022       INSN_CODE (undobuf.other_insn) = other_code_number;
4023
4024     /* We had one special case above where I2 had more than one set and
4025        we replaced a destination of one of those sets with the destination
4026        of I3.  In that case, we have to update LOG_LINKS of insns later
4027        in this basic block.  Note that this (expensive) case is rare.
4028
4029        Also, in this case, we must pretend that all REG_NOTEs for I2
4030        actually came from I3, so that REG_UNUSED notes from I2 will be
4031        properly handled.  */
4032
4033     if (i3_subst_into_i2)
4034       {
4035         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4036           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4037                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4038               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4039               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4040               && ! find_reg_note (i2, REG_UNUSED,
4041                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4042             for (temp = NEXT_INSN (i2);
4043                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4044                           || BB_HEAD (this_basic_block) != temp);
4045                  temp = NEXT_INSN (temp))
4046               if (temp != i3 && INSN_P (temp))
4047                 FOR_EACH_LOG_LINK (link, temp)
4048                   if (link->insn == i2)
4049                     link->insn = i3;
4050
4051         if (i3notes)
4052           {
4053             rtx link = i3notes;
4054             while (XEXP (link, 1))
4055               link = XEXP (link, 1);
4056             XEXP (link, 1) = i2notes;
4057           }
4058         else
4059           i3notes = i2notes;
4060         i2notes = 0;
4061       }
4062
4063     LOG_LINKS (i3) = NULL;
4064     REG_NOTES (i3) = 0;
4065     LOG_LINKS (i2) = NULL;
4066     REG_NOTES (i2) = 0;
4067
4068     if (newi2pat)
4069       {
4070         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4071           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4072                                this_basic_block);
4073         INSN_CODE (i2) = i2_code_number;
4074         PATTERN (i2) = newi2pat;
4075       }
4076     else
4077       {
4078         if (MAY_HAVE_DEBUG_INSNS && i2src)
4079           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4080                                this_basic_block);
4081         SET_INSN_DELETED (i2);
4082       }
4083
4084     if (i1)
4085       {
4086         LOG_LINKS (i1) = NULL;
4087         REG_NOTES (i1) = 0;
4088         if (MAY_HAVE_DEBUG_INSNS)
4089           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4090                                this_basic_block);
4091         SET_INSN_DELETED (i1);
4092       }
4093
4094     if (i0)
4095       {
4096         LOG_LINKS (i0) = NULL;
4097         REG_NOTES (i0) = 0;
4098         if (MAY_HAVE_DEBUG_INSNS)
4099           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4100                                this_basic_block);
4101         SET_INSN_DELETED (i0);
4102       }
4103
4104     /* Get death notes for everything that is now used in either I3 or
4105        I2 and used to die in a previous insn.  If we built two new
4106        patterns, move from I1 to I2 then I2 to I3 so that we get the
4107        proper movement on registers that I2 modifies.  */
4108
4109     if (i0)
4110       from_luid = DF_INSN_LUID (i0);
4111     else if (i1)
4112       from_luid = DF_INSN_LUID (i1);
4113     else
4114       from_luid = DF_INSN_LUID (i2);
4115     if (newi2pat)
4116       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4117     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4118
4119     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4120     if (i3notes)
4121       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4122                         elim_i2, elim_i1, elim_i0);
4123     if (i2notes)
4124       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4125                         elim_i2, elim_i1, elim_i0);
4126     if (i1notes)
4127       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4128                         elim_i2, elim_i1, elim_i0);
4129     if (i0notes)
4130       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4131                         elim_i2, elim_i1, elim_i0);
4132     if (midnotes)
4133       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4134                         elim_i2, elim_i1, elim_i0);
4135
4136     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4137        know these are REG_UNUSED and want them to go to the desired insn,
4138        so we always pass it as i3.  */
4139
4140     if (newi2pat && new_i2_notes)
4141       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4142                         NULL_RTX);
4143
4144     if (new_i3_notes)
4145       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4146                         NULL_RTX);
4147
4148     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4149        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4150        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4151        in that case, it might delete I2.  Similarly for I2 and I1.
4152        Show an additional death due to the REG_DEAD note we make here.  If
4153        we discard it in distribute_notes, we will decrement it again.  */
4154
4155     if (i3dest_killed)
4156       {
4157         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4158         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4159           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4160                             elim_i1, elim_i0);
4161         else
4162           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4163                             elim_i2, elim_i1, elim_i0);
4164       }
4165
4166     if (i2dest_in_i2src)
4167       {
4168         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4169         if (newi2pat && reg_set_p (i2dest, newi2pat))
4170           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4171                             NULL_RTX, NULL_RTX);
4172         else
4173           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4174                             NULL_RTX, NULL_RTX, NULL_RTX);
4175       }
4176
4177     if (i1dest_in_i1src)
4178       {
4179         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4180         if (newi2pat && reg_set_p (i1dest, newi2pat))
4181           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4182                             NULL_RTX, NULL_RTX);
4183         else
4184           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4185                             NULL_RTX, NULL_RTX, NULL_RTX);
4186       }
4187
4188     if (i0dest_in_i0src)
4189       {
4190         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4191         if (newi2pat && reg_set_p (i0dest, newi2pat))
4192           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4193                             NULL_RTX, NULL_RTX);
4194         else
4195           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4196                             NULL_RTX, NULL_RTX, NULL_RTX);
4197       }
4198
4199     distribute_links (i3links);
4200     distribute_links (i2links);
4201     distribute_links (i1links);
4202     distribute_links (i0links);
4203
4204     if (REG_P (i2dest))
4205       {
4206         struct insn_link *link;
4207         rtx i2_insn = 0, i2_val = 0, set;
4208
4209         /* The insn that used to set this register doesn't exist, and
4210            this life of the register may not exist either.  See if one of
4211            I3's links points to an insn that sets I2DEST.  If it does,
4212            that is now the last known value for I2DEST. If we don't update
4213            this and I2 set the register to a value that depended on its old
4214            contents, we will get confused.  If this insn is used, thing
4215            will be set correctly in combine_instructions.  */
4216         FOR_EACH_LOG_LINK (link, i3)
4217           if ((set = single_set (link->insn)) != 0
4218               && rtx_equal_p (i2dest, SET_DEST (set)))
4219             i2_insn = link->insn, i2_val = SET_SRC (set);
4220
4221         record_value_for_reg (i2dest, i2_insn, i2_val);
4222
4223         /* If the reg formerly set in I2 died only once and that was in I3,
4224            zero its use count so it won't make `reload' do any work.  */
4225         if (! added_sets_2
4226             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4227             && ! i2dest_in_i2src)
4228           INC_REG_N_SETS (REGNO (i2dest), -1);
4229       }
4230
4231     if (i1 && REG_P (i1dest))
4232       {
4233         struct insn_link *link;
4234         rtx i1_insn = 0, i1_val = 0, set;
4235
4236         FOR_EACH_LOG_LINK (link, i3)
4237           if ((set = single_set (link->insn)) != 0
4238               && rtx_equal_p (i1dest, SET_DEST (set)))
4239             i1_insn = link->insn, i1_val = SET_SRC (set);
4240
4241         record_value_for_reg (i1dest, i1_insn, i1_val);
4242
4243         if (! added_sets_1 && ! i1dest_in_i1src)
4244           INC_REG_N_SETS (REGNO (i1dest), -1);
4245       }
4246
4247     if (i0 && REG_P (i0dest))
4248       {
4249         struct insn_link *link;
4250         rtx i0_insn = 0, i0_val = 0, set;
4251
4252         FOR_EACH_LOG_LINK (link, i3)
4253           if ((set = single_set (link->insn)) != 0
4254               && rtx_equal_p (i0dest, SET_DEST (set)))
4255             i0_insn = link->insn, i0_val = SET_SRC (set);
4256
4257         record_value_for_reg (i0dest, i0_insn, i0_val);
4258
4259         if (! added_sets_0 && ! i0dest_in_i0src)
4260           INC_REG_N_SETS (REGNO (i0dest), -1);
4261       }
4262
4263     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4264        been made to this insn.  The order of
4265        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4266        can affect nonzero_bits of newpat */
4267     if (newi2pat)
4268       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4269     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4270   }
4271
4272   if (undobuf.other_insn != NULL_RTX)
4273     {
4274       if (dump_file)
4275         {
4276           fprintf (dump_file, "modifying other_insn ");
4277           dump_insn_slim (dump_file, undobuf.other_insn);
4278         }
4279       df_insn_rescan (undobuf.other_insn);
4280     }
4281
4282   if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4283     {
4284       if (dump_file)
4285         {
4286           fprintf (dump_file, "modifying insn i1 ");
4287           dump_insn_slim (dump_file, i0);
4288         }
4289       df_insn_rescan (i0);
4290     }
4291
4292   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4293     {
4294       if (dump_file)
4295         {
4296           fprintf (dump_file, "modifying insn i1 ");
4297           dump_insn_slim (dump_file, i1);
4298         }
4299       df_insn_rescan (i1);
4300     }
4301
4302   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4303     {
4304       if (dump_file)
4305         {
4306           fprintf (dump_file, "modifying insn i2 ");
4307           dump_insn_slim (dump_file, i2);
4308         }
4309       df_insn_rescan (i2);
4310     }
4311
4312   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4313     {
4314       if (dump_file)
4315         {
4316           fprintf (dump_file, "modifying insn i3 ");
4317           dump_insn_slim (dump_file, i3);
4318         }
4319       df_insn_rescan (i3);
4320     }
4321
4322   /* Set new_direct_jump_p if a new return or simple jump instruction
4323      has been created.  Adjust the CFG accordingly.  */
4324
4325   if (returnjump_p (i3) || any_uncondjump_p (i3))
4326     {
4327       *new_direct_jump_p = 1;
4328       mark_jump_label (PATTERN (i3), i3, 0);
4329       update_cfg_for_uncondjump (i3);
4330     }
4331
4332   if (undobuf.other_insn != NULL_RTX
4333       && (returnjump_p (undobuf.other_insn)
4334           || any_uncondjump_p (undobuf.other_insn)))
4335     {
4336       *new_direct_jump_p = 1;
4337       update_cfg_for_uncondjump (undobuf.other_insn);
4338     }
4339
4340   /* A noop might also need cleaning up of CFG, if it comes from the
4341      simplification of a jump.  */
4342   if (JUMP_P (i3)
4343       && GET_CODE (newpat) == SET
4344       && SET_SRC (newpat) == pc_rtx
4345       && SET_DEST (newpat) == pc_rtx)
4346     {
4347       *new_direct_jump_p = 1;
4348       update_cfg_for_uncondjump (i3);
4349     }
4350
4351   if (undobuf.other_insn != NULL_RTX
4352       && JUMP_P (undobuf.other_insn)
4353       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4354       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4355       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4356     {
4357       *new_direct_jump_p = 1;
4358       update_cfg_for_uncondjump (undobuf.other_insn);
4359     }
4360
4361   combine_successes++;
4362   undo_commit ();
4363
4364   if (added_links_insn
4365       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4366       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4367     return added_links_insn;
4368   else
4369     return newi2pat ? i2 : i3;
4370 }
4371 \f
4372 /* Undo all the modifications recorded in undobuf.  */
4373
4374 static void
4375 undo_all (void)
4376 {
4377   struct undo *undo, *next;
4378
4379   for (undo = undobuf.undos; undo; undo = next)
4380     {
4381       next = undo->next;
4382       switch (undo->kind)
4383         {
4384         case UNDO_RTX:
4385           *undo->where.r = undo->old_contents.r;
4386           break;
4387         case UNDO_INT:
4388           *undo->where.i = undo->old_contents.i;
4389           break;
4390         case UNDO_MODE:
4391           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4392           break;
4393         case UNDO_LINKS:
4394           *undo->where.l = undo->old_contents.l;
4395           break;
4396         default:
4397           gcc_unreachable ();
4398         }
4399
4400       undo->next = undobuf.frees;
4401       undobuf.frees = undo;
4402     }
4403
4404   undobuf.undos = 0;
4405 }
4406
4407 /* We've committed to accepting the changes we made.  Move all
4408    of the undos to the free list.  */
4409
4410 static void
4411 undo_commit (void)
4412 {
4413   struct undo *undo, *next;
4414
4415   for (undo = undobuf.undos; undo; undo = next)
4416     {
4417       next = undo->next;
4418       undo->next = undobuf.frees;
4419       undobuf.frees = undo;
4420     }
4421   undobuf.undos = 0;
4422 }
4423 \f
4424 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4425    where we have an arithmetic expression and return that point.  LOC will
4426    be inside INSN.
4427
4428    try_combine will call this function to see if an insn can be split into
4429    two insns.  */
4430
4431 static rtx *
4432 find_split_point (rtx *loc, rtx insn, bool set_src)
4433 {
4434   rtx x = *loc;
4435   enum rtx_code code = GET_CODE (x);
4436   rtx *split;
4437   unsigned HOST_WIDE_INT len = 0;
4438   HOST_WIDE_INT pos = 0;
4439   int unsignedp = 0;
4440   rtx inner = NULL_RTX;
4441
4442   /* First special-case some codes.  */
4443   switch (code)
4444     {
4445     case SUBREG:
4446 #ifdef INSN_SCHEDULING
4447       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4448          point.  */
4449       if (MEM_P (SUBREG_REG (x)))
4450         return loc;
4451 #endif
4452       return find_split_point (&SUBREG_REG (x), insn, false);
4453
4454     case MEM:
4455 #ifdef HAVE_lo_sum
4456       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4457          using LO_SUM and HIGH.  */
4458       if (GET_CODE (XEXP (x, 0)) == CONST
4459           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4460         {
4461           enum machine_mode address_mode = get_address_mode (x);
4462
4463           SUBST (XEXP (x, 0),
4464                  gen_rtx_LO_SUM (address_mode,
4465                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4466                                  XEXP (x, 0)));
4467           return &XEXP (XEXP (x, 0), 0);
4468         }
4469 #endif
4470
4471       /* If we have a PLUS whose second operand is a constant and the
4472          address is not valid, perhaps will can split it up using
4473          the machine-specific way to split large constants.  We use
4474          the first pseudo-reg (one of the virtual regs) as a placeholder;
4475          it will not remain in the result.  */
4476       if (GET_CODE (XEXP (x, 0)) == PLUS
4477           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4478           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4479                                             MEM_ADDR_SPACE (x)))
4480         {
4481           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4482           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4483                                                       XEXP (x, 0)),
4484                                          subst_insn);
4485
4486           /* This should have produced two insns, each of which sets our
4487              placeholder.  If the source of the second is a valid address,
4488              we can make put both sources together and make a split point
4489              in the middle.  */
4490
4491           if (seq
4492               && NEXT_INSN (seq) != NULL_RTX
4493               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4494               && NONJUMP_INSN_P (seq)
4495               && GET_CODE (PATTERN (seq)) == SET
4496               && SET_DEST (PATTERN (seq)) == reg
4497               && ! reg_mentioned_p (reg,
4498                                     SET_SRC (PATTERN (seq)))
4499               && NONJUMP_INSN_P (NEXT_INSN (seq))
4500               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4501               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4502               && memory_address_addr_space_p
4503                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4504                     MEM_ADDR_SPACE (x)))
4505             {
4506               rtx src1 = SET_SRC (PATTERN (seq));
4507               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4508
4509               /* Replace the placeholder in SRC2 with SRC1.  If we can
4510                  find where in SRC2 it was placed, that can become our
4511                  split point and we can replace this address with SRC2.
4512                  Just try two obvious places.  */
4513
4514               src2 = replace_rtx (src2, reg, src1);
4515               split = 0;
4516               if (XEXP (src2, 0) == src1)
4517                 split = &XEXP (src2, 0);
4518               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4519                        && XEXP (XEXP (src2, 0), 0) == src1)
4520                 split = &XEXP (XEXP (src2, 0), 0);
4521
4522               if (split)
4523                 {
4524                   SUBST (XEXP (x, 0), src2);
4525                   return split;
4526                 }
4527             }
4528
4529           /* If that didn't work, perhaps the first operand is complex and
4530              needs to be computed separately, so make a split point there.
4531              This will occur on machines that just support REG + CONST
4532              and have a constant moved through some previous computation.  */
4533
4534           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4535                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4536                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4537             return &XEXP (XEXP (x, 0), 0);
4538         }
4539
4540       /* If we have a PLUS whose first operand is complex, try computing it
4541          separately by making a split there.  */
4542       if (GET_CODE (XEXP (x, 0)) == PLUS
4543           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4544                                             MEM_ADDR_SPACE (x))
4545           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4546           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4547                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4548         return &XEXP (XEXP (x, 0), 0);
4549       break;
4550
4551     case SET:
4552 #ifdef HAVE_cc0
4553       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4554          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4555          we need to put the operand into a register.  So split at that
4556          point.  */
4557
4558       if (SET_DEST (x) == cc0_rtx
4559           && GET_CODE (SET_SRC (x)) != COMPARE
4560           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4561           && !OBJECT_P (SET_SRC (x))
4562           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4563                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4564         return &SET_SRC (x);
4565 #endif
4566
4567       /* See if we can split SET_SRC as it stands.  */
4568       split = find_split_point (&SET_SRC (x), insn, true);
4569       if (split && split != &SET_SRC (x))
4570         return split;
4571
4572       /* See if we can split SET_DEST as it stands.  */
4573       split = find_split_point (&SET_DEST (x), insn, false);
4574       if (split && split != &SET_DEST (x))
4575         return split;
4576
4577       /* See if this is a bitfield assignment with everything constant.  If
4578          so, this is an IOR of an AND, so split it into that.  */
4579       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4580           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4581           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4582           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4583           && CONST_INT_P (SET_SRC (x))
4584           && ((INTVAL (XEXP (SET_DEST (x), 1))
4585                + INTVAL (XEXP (SET_DEST (x), 2)))
4586               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4587           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4588         {
4589           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4590           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4591           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4592           rtx dest = XEXP (SET_DEST (x), 0);
4593           enum machine_mode mode = GET_MODE (dest);
4594           unsigned HOST_WIDE_INT mask
4595             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4596           rtx or_mask;
4597
4598           if (BITS_BIG_ENDIAN)
4599             pos = GET_MODE_PRECISION (mode) - len - pos;
4600
4601           or_mask = gen_int_mode (src << pos, mode);
4602           if (src == mask)
4603             SUBST (SET_SRC (x),
4604                    simplify_gen_binary (IOR, mode, dest, or_mask));
4605           else
4606             {
4607               rtx negmask = gen_int_mode (~(mask << pos), mode);
4608               SUBST (SET_SRC (x),
4609                      simplify_gen_binary (IOR, mode,
4610                                           simplify_gen_binary (AND, mode,
4611                                                                dest, negmask),
4612                                           or_mask));
4613             }
4614
4615           SUBST (SET_DEST (x), dest);
4616
4617           split = find_split_point (&SET_SRC (x), insn, true);
4618           if (split && split != &SET_SRC (x))
4619             return split;
4620         }
4621
4622       /* Otherwise, see if this is an operation that we can split into two.
4623          If so, try to split that.  */
4624       code = GET_CODE (SET_SRC (x));
4625
4626       switch (code)
4627         {
4628         case AND:
4629           /* If we are AND'ing with a large constant that is only a single
4630              bit and the result is only being used in a context where we
4631              need to know if it is zero or nonzero, replace it with a bit
4632              extraction.  This will avoid the large constant, which might
4633              have taken more than one insn to make.  If the constant were
4634              not a valid argument to the AND but took only one insn to make,
4635              this is no worse, but if it took more than one insn, it will
4636              be better.  */
4637
4638           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4639               && REG_P (XEXP (SET_SRC (x), 0))
4640               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4641               && REG_P (SET_DEST (x))
4642               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4643               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4644               && XEXP (*split, 0) == SET_DEST (x)
4645               && XEXP (*split, 1) == const0_rtx)
4646             {
4647               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4648                                                 XEXP (SET_SRC (x), 0),
4649                                                 pos, NULL_RTX, 1, 1, 0, 0);
4650               if (extraction != 0)
4651                 {
4652                   SUBST (SET_SRC (x), extraction);
4653                   return find_split_point (loc, insn, false);
4654                 }
4655             }
4656           break;
4657
4658         case NE:
4659           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4660              is known to be on, this can be converted into a NEG of a shift.  */
4661           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4662               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4663               && 1 <= (pos = exact_log2
4664                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4665                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4666             {
4667               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4668
4669               SUBST (SET_SRC (x),
4670                      gen_rtx_NEG (mode,
4671                                   gen_rtx_LSHIFTRT (mode,
4672                                                     XEXP (SET_SRC (x), 0),
4673                                                     GEN_INT (pos))));
4674
4675               split = find_split_point (&SET_SRC (x), insn, true);
4676               if (split && split != &SET_SRC (x))
4677                 return split;
4678             }
4679           break;
4680
4681         case SIGN_EXTEND:
4682           inner = XEXP (SET_SRC (x), 0);
4683
4684           /* We can't optimize if either mode is a partial integer
4685              mode as we don't know how many bits are significant
4686              in those modes.  */
4687           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4688               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4689             break;
4690
4691           pos = 0;
4692           len = GET_MODE_PRECISION (GET_MODE (inner));
4693           unsignedp = 0;
4694           break;
4695
4696         case SIGN_EXTRACT:
4697         case ZERO_EXTRACT:
4698           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4699               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4700             {
4701               inner = XEXP (SET_SRC (x), 0);
4702               len = INTVAL (XEXP (SET_SRC (x), 1));
4703               pos = INTVAL (XEXP (SET_SRC (x), 2));
4704
4705               if (BITS_BIG_ENDIAN)
4706                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4707               unsignedp = (code == ZERO_EXTRACT);
4708             }
4709           break;
4710
4711         default:
4712           break;
4713         }
4714
4715       if (len && pos >= 0
4716           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4717         {
4718           enum machine_mode mode = GET_MODE (SET_SRC (x));
4719
4720           /* For unsigned, we have a choice of a shift followed by an
4721              AND or two shifts.  Use two shifts for field sizes where the
4722              constant might be too large.  We assume here that we can
4723              always at least get 8-bit constants in an AND insn, which is
4724              true for every current RISC.  */
4725
4726           if (unsignedp && len <= 8)
4727             {
4728               unsigned HOST_WIDE_INT mask
4729                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4730               SUBST (SET_SRC (x),
4731                      gen_rtx_AND (mode,
4732                                   gen_rtx_LSHIFTRT
4733                                   (mode, gen_lowpart (mode, inner),
4734                                    GEN_INT (pos)),
4735                                   gen_int_mode (mask, mode)));
4736
4737               split = find_split_point (&SET_SRC (x), insn, true);
4738               if (split && split != &SET_SRC (x))
4739                 return split;
4740             }
4741           else
4742             {
4743               SUBST (SET_SRC (x),
4744                      gen_rtx_fmt_ee
4745                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4746                       gen_rtx_ASHIFT (mode,
4747                                       gen_lowpart (mode, inner),
4748                                       GEN_INT (GET_MODE_PRECISION (mode)
4749                                                - len - pos)),
4750                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4751
4752               split = find_split_point (&SET_SRC (x), insn, true);
4753               if (split && split != &SET_SRC (x))
4754                 return split;
4755             }
4756         }
4757
4758       /* See if this is a simple operation with a constant as the second
4759          operand.  It might be that this constant is out of range and hence
4760          could be used as a split point.  */
4761       if (BINARY_P (SET_SRC (x))
4762           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4763           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4764               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4765                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4766         return &XEXP (SET_SRC (x), 1);
4767
4768       /* Finally, see if this is a simple operation with its first operand
4769          not in a register.  The operation might require this operand in a
4770          register, so return it as a split point.  We can always do this
4771          because if the first operand were another operation, we would have
4772          already found it as a split point.  */
4773       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4774           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4775         return &XEXP (SET_SRC (x), 0);
4776
4777       return 0;
4778
4779     case AND:
4780     case IOR:
4781       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4782          it is better to write this as (not (ior A B)) so we can split it.
4783          Similarly for IOR.  */
4784       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4785         {
4786           SUBST (*loc,
4787                  gen_rtx_NOT (GET_MODE (x),
4788                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4789                                               GET_MODE (x),
4790                                               XEXP (XEXP (x, 0), 0),
4791                                               XEXP (XEXP (x, 1), 0))));
4792           return find_split_point (loc, insn, set_src);
4793         }
4794
4795       /* Many RISC machines have a large set of logical insns.  If the
4796          second operand is a NOT, put it first so we will try to split the
4797          other operand first.  */
4798       if (GET_CODE (XEXP (x, 1)) == NOT)
4799         {
4800           rtx tem = XEXP (x, 0);
4801           SUBST (XEXP (x, 0), XEXP (x, 1));
4802           SUBST (XEXP (x, 1), tem);
4803         }
4804       break;
4805
4806     case PLUS:
4807     case MINUS:
4808       /* Canonicalization can produce (minus A (mult B C)), where C is a
4809          constant.  It may be better to try splitting (plus (mult B -C) A)
4810          instead if this isn't a multiply by a power of two.  */
4811       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4812           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4813           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4814         {
4815           enum machine_mode mode = GET_MODE (x);
4816           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4817           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4818           SUBST (*loc, gen_rtx_PLUS (mode,
4819                                      gen_rtx_MULT (mode,
4820                                                    XEXP (XEXP (x, 1), 0),
4821                                                    gen_int_mode (other_int,
4822                                                                  mode)),
4823                                      XEXP (x, 0)));
4824           return find_split_point (loc, insn, set_src);
4825         }
4826
4827       /* Split at a multiply-accumulate instruction.  However if this is
4828          the SET_SRC, we likely do not have such an instruction and it's
4829          worthless to try this split.  */
4830       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4831         return loc;
4832
4833     default:
4834       break;
4835     }
4836
4837   /* Otherwise, select our actions depending on our rtx class.  */
4838   switch (GET_RTX_CLASS (code))
4839     {
4840     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4841     case RTX_TERNARY:
4842       split = find_split_point (&XEXP (x, 2), insn, false);
4843       if (split)
4844         return split;
4845       /* ... fall through ...  */
4846     case RTX_BIN_ARITH:
4847     case RTX_COMM_ARITH:
4848     case RTX_COMPARE:
4849     case RTX_COMM_COMPARE:
4850       split = find_split_point (&XEXP (x, 1), insn, false);
4851       if (split)
4852         return split;
4853       /* ... fall through ...  */
4854     case RTX_UNARY:
4855       /* Some machines have (and (shift ...) ...) insns.  If X is not
4856          an AND, but XEXP (X, 0) is, use it as our split point.  */
4857       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4858         return &XEXP (x, 0);
4859
4860       split = find_split_point (&XEXP (x, 0), insn, false);
4861       if (split)
4862         return split;
4863       return loc;
4864
4865     default:
4866       /* Otherwise, we don't have a split point.  */
4867       return 0;
4868     }
4869 }
4870 \f
4871 /* Throughout X, replace FROM with TO, and return the result.
4872    The result is TO if X is FROM;
4873    otherwise the result is X, but its contents may have been modified.
4874    If they were modified, a record was made in undobuf so that
4875    undo_all will (among other things) return X to its original state.
4876
4877    If the number of changes necessary is too much to record to undo,
4878    the excess changes are not made, so the result is invalid.
4879    The changes already made can still be undone.
4880    undobuf.num_undo is incremented for such changes, so by testing that
4881    the caller can tell whether the result is valid.
4882
4883    `n_occurrences' is incremented each time FROM is replaced.
4884
4885    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4886
4887    IN_COND is nonzero if we are at the top level of a condition.
4888
4889    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4890    by copying if `n_occurrences' is nonzero.  */
4891
4892 static rtx
4893 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4894 {
4895   enum rtx_code code = GET_CODE (x);
4896   enum machine_mode op0_mode = VOIDmode;
4897   const char *fmt;
4898   int len, i;
4899   rtx new_rtx;
4900
4901 /* Two expressions are equal if they are identical copies of a shared
4902    RTX or if they are both registers with the same register number
4903    and mode.  */
4904
4905 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4906   ((X) == (Y)                                           \
4907    || (REG_P (X) && REG_P (Y)   \
4908        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4909
4910   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4911     {
4912       n_occurrences++;
4913       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4914     }
4915
4916   /* If X and FROM are the same register but different modes, they
4917      will not have been seen as equal above.  However, the log links code
4918      will make a LOG_LINKS entry for that case.  If we do nothing, we
4919      will try to rerecognize our original insn and, when it succeeds,
4920      we will delete the feeding insn, which is incorrect.
4921
4922      So force this insn not to match in this (rare) case.  */
4923   if (! in_dest && code == REG && REG_P (from)
4924       && reg_overlap_mentioned_p (x, from))
4925     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4926
4927   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4928      of which may contain things that can be combined.  */
4929   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4930     return x;
4931
4932   /* It is possible to have a subexpression appear twice in the insn.
4933      Suppose that FROM is a register that appears within TO.
4934      Then, after that subexpression has been scanned once by `subst',
4935      the second time it is scanned, TO may be found.  If we were
4936      to scan TO here, we would find FROM within it and create a
4937      self-referent rtl structure which is completely wrong.  */
4938   if (COMBINE_RTX_EQUAL_P (x, to))
4939     return to;
4940
4941   /* Parallel asm_operands need special attention because all of the
4942      inputs are shared across the arms.  Furthermore, unsharing the
4943      rtl results in recognition failures.  Failure to handle this case
4944      specially can result in circular rtl.
4945
4946      Solve this by doing a normal pass across the first entry of the
4947      parallel, and only processing the SET_DESTs of the subsequent
4948      entries.  Ug.  */
4949
4950   if (code == PARALLEL
4951       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4952       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4953     {
4954       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4955
4956       /* If this substitution failed, this whole thing fails.  */
4957       if (GET_CODE (new_rtx) == CLOBBER
4958           && XEXP (new_rtx, 0) == const0_rtx)
4959         return new_rtx;
4960
4961       SUBST (XVECEXP (x, 0, 0), new_rtx);
4962
4963       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4964         {
4965           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4966
4967           if (!REG_P (dest)
4968               && GET_CODE (dest) != CC0
4969               && GET_CODE (dest) != PC)
4970             {
4971               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4972
4973               /* If this substitution failed, this whole thing fails.  */
4974               if (GET_CODE (new_rtx) == CLOBBER
4975                   && XEXP (new_rtx, 0) == const0_rtx)
4976                 return new_rtx;
4977
4978               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4979             }
4980         }
4981     }
4982   else
4983     {
4984       len = GET_RTX_LENGTH (code);
4985       fmt = GET_RTX_FORMAT (code);
4986
4987       /* We don't need to process a SET_DEST that is a register, CC0,
4988          or PC, so set up to skip this common case.  All other cases
4989          where we want to suppress replacing something inside a
4990          SET_SRC are handled via the IN_DEST operand.  */
4991       if (code == SET
4992           && (REG_P (SET_DEST (x))
4993               || GET_CODE (SET_DEST (x)) == CC0
4994               || GET_CODE (SET_DEST (x)) == PC))
4995         fmt = "ie";
4996
4997       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4998          constant.  */
4999       if (fmt[0] == 'e')
5000         op0_mode = GET_MODE (XEXP (x, 0));
5001
5002       for (i = 0; i < len; i++)
5003         {
5004           if (fmt[i] == 'E')
5005             {
5006               int j;
5007               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5008                 {
5009                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5010                     {
5011                       new_rtx = (unique_copy && n_occurrences
5012                              ? copy_rtx (to) : to);
5013                       n_occurrences++;
5014                     }
5015                   else
5016                     {
5017                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5018                                        unique_copy);
5019
5020                       /* If this substitution failed, this whole thing
5021                          fails.  */
5022                       if (GET_CODE (new_rtx) == CLOBBER
5023                           && XEXP (new_rtx, 0) == const0_rtx)
5024                         return new_rtx;
5025                     }
5026
5027                   SUBST (XVECEXP (x, i, j), new_rtx);
5028                 }
5029             }
5030           else if (fmt[i] == 'e')
5031             {
5032               /* If this is a register being set, ignore it.  */
5033               new_rtx = XEXP (x, i);
5034               if (in_dest
5035                   && i == 0
5036                   && (((code == SUBREG || code == ZERO_EXTRACT)
5037                        && REG_P (new_rtx))
5038                       || code == STRICT_LOW_PART))
5039                 ;
5040
5041               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5042                 {
5043                   /* In general, don't install a subreg involving two
5044                      modes not tieable.  It can worsen register
5045                      allocation, and can even make invalid reload
5046                      insns, since the reg inside may need to be copied
5047                      from in the outside mode, and that may be invalid
5048                      if it is an fp reg copied in integer mode.
5049
5050                      We allow two exceptions to this: It is valid if
5051                      it is inside another SUBREG and the mode of that
5052                      SUBREG and the mode of the inside of TO is
5053                      tieable and it is valid if X is a SET that copies
5054                      FROM to CC0.  */
5055
5056                   if (GET_CODE (to) == SUBREG
5057                       && ! MODES_TIEABLE_P (GET_MODE (to),
5058                                             GET_MODE (SUBREG_REG (to)))
5059                       && ! (code == SUBREG
5060                             && MODES_TIEABLE_P (GET_MODE (x),
5061                                                 GET_MODE (SUBREG_REG (to))))
5062 #ifdef HAVE_cc0
5063                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5064 #endif
5065                       )
5066                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5067
5068 #ifdef CANNOT_CHANGE_MODE_CLASS
5069                   if (code == SUBREG
5070                       && REG_P (to)
5071                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5072                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5073                                                    GET_MODE (to),
5074                                                    GET_MODE (x)))
5075                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5076 #endif
5077
5078                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5079                   n_occurrences++;
5080                 }
5081               else
5082                 /* If we are in a SET_DEST, suppress most cases unless we
5083                    have gone inside a MEM, in which case we want to
5084                    simplify the address.  We assume here that things that
5085                    are actually part of the destination have their inner
5086                    parts in the first expression.  This is true for SUBREG,
5087                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5088                    things aside from REG and MEM that should appear in a
5089                    SET_DEST.  */
5090                 new_rtx = subst (XEXP (x, i), from, to,
5091                              (((in_dest
5092                                 && (code == SUBREG || code == STRICT_LOW_PART
5093                                     || code == ZERO_EXTRACT))
5094                                || code == SET)
5095                               && i == 0),
5096                                  code == IF_THEN_ELSE && i == 0,
5097                                  unique_copy);
5098
5099               /* If we found that we will have to reject this combination,
5100                  indicate that by returning the CLOBBER ourselves, rather than
5101                  an expression containing it.  This will speed things up as
5102                  well as prevent accidents where two CLOBBERs are considered
5103                  to be equal, thus producing an incorrect simplification.  */
5104
5105               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5106                 return new_rtx;
5107
5108               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5109                 {
5110                   enum machine_mode mode = GET_MODE (x);
5111
5112                   x = simplify_subreg (GET_MODE (x), new_rtx,
5113                                        GET_MODE (SUBREG_REG (x)),
5114                                        SUBREG_BYTE (x));
5115                   if (! x)
5116                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5117                 }
5118               else if (CONST_INT_P (new_rtx)
5119                        && GET_CODE (x) == ZERO_EXTEND)
5120                 {
5121                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5122                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5123                   gcc_assert (x);
5124                 }
5125               else
5126                 SUBST (XEXP (x, i), new_rtx);
5127             }
5128         }
5129     }
5130
5131   /* Check if we are loading something from the constant pool via float
5132      extension; in this case we would undo compress_float_constant
5133      optimization and degenerate constant load to an immediate value.  */
5134   if (GET_CODE (x) == FLOAT_EXTEND
5135       && MEM_P (XEXP (x, 0))
5136       && MEM_READONLY_P (XEXP (x, 0)))
5137     {
5138       rtx tmp = avoid_constant_pool_reference (x);
5139       if (x != tmp)
5140         return x;
5141     }
5142
5143   /* Try to simplify X.  If the simplification changed the code, it is likely
5144      that further simplification will help, so loop, but limit the number
5145      of repetitions that will be performed.  */
5146
5147   for (i = 0; i < 4; i++)
5148     {
5149       /* If X is sufficiently simple, don't bother trying to do anything
5150          with it.  */
5151       if (code != CONST_INT && code != REG && code != CLOBBER)
5152         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5153
5154       if (GET_CODE (x) == code)
5155         break;
5156
5157       code = GET_CODE (x);
5158
5159       /* We no longer know the original mode of operand 0 since we
5160          have changed the form of X)  */
5161       op0_mode = VOIDmode;
5162     }
5163
5164   return x;
5165 }
5166 \f
5167 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5168    outer level; call `subst' to simplify recursively.  Return the new
5169    expression.
5170
5171    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5172    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5173    of a condition.  */
5174
5175 static rtx
5176 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5177                       int in_cond)
5178 {
5179   enum rtx_code code = GET_CODE (x);
5180   enum machine_mode mode = GET_MODE (x);
5181   rtx temp;
5182   int i;
5183
5184   /* If this is a commutative operation, put a constant last and a complex
5185      expression first.  We don't need to do this for comparisons here.  */
5186   if (COMMUTATIVE_ARITH_P (x)
5187       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5188     {
5189       temp = XEXP (x, 0);
5190       SUBST (XEXP (x, 0), XEXP (x, 1));
5191       SUBST (XEXP (x, 1), temp);
5192     }
5193
5194   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5195      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5196      things.  Check for cases where both arms are testing the same
5197      condition.
5198
5199      Don't do anything if all operands are very simple.  */
5200
5201   if ((BINARY_P (x)
5202        && ((!OBJECT_P (XEXP (x, 0))
5203             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5204                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5205            || (!OBJECT_P (XEXP (x, 1))
5206                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5207                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5208       || (UNARY_P (x)
5209           && (!OBJECT_P (XEXP (x, 0))
5210                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5211                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5212     {
5213       rtx cond, true_rtx, false_rtx;
5214
5215       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5216       if (cond != 0
5217           /* If everything is a comparison, what we have is highly unlikely
5218              to be simpler, so don't use it.  */
5219           && ! (COMPARISON_P (x)
5220                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5221         {
5222           rtx cop1 = const0_rtx;
5223           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5224
5225           if (cond_code == NE && COMPARISON_P (cond))
5226             return x;
5227
5228           /* Simplify the alternative arms; this may collapse the true and
5229              false arms to store-flag values.  Be careful to use copy_rtx
5230              here since true_rtx or false_rtx might share RTL with x as a
5231              result of the if_then_else_cond call above.  */
5232           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5233           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5234
5235           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5236              is unlikely to be simpler.  */
5237           if (general_operand (true_rtx, VOIDmode)
5238               && general_operand (false_rtx, VOIDmode))
5239             {
5240               enum rtx_code reversed;
5241
5242               /* Restarting if we generate a store-flag expression will cause
5243                  us to loop.  Just drop through in this case.  */
5244
5245               /* If the result values are STORE_FLAG_VALUE and zero, we can
5246                  just make the comparison operation.  */
5247               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5248                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5249                                              cond, cop1);
5250               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5251                        && ((reversed = reversed_comparison_code_parts
5252                                         (cond_code, cond, cop1, NULL))
5253                            != UNKNOWN))
5254                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5255                                              cond, cop1);
5256
5257               /* Likewise, we can make the negate of a comparison operation
5258                  if the result values are - STORE_FLAG_VALUE and zero.  */
5259               else if (CONST_INT_P (true_rtx)
5260                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5261                        && false_rtx == const0_rtx)
5262                 x = simplify_gen_unary (NEG, mode,
5263                                         simplify_gen_relational (cond_code,
5264                                                                  mode, VOIDmode,
5265                                                                  cond, cop1),
5266                                         mode);
5267               else if (CONST_INT_P (false_rtx)
5268                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5269                        && true_rtx == const0_rtx
5270                        && ((reversed = reversed_comparison_code_parts
5271                                         (cond_code, cond, cop1, NULL))
5272                            != UNKNOWN))
5273                 x = simplify_gen_unary (NEG, mode,
5274                                         simplify_gen_relational (reversed,
5275                                                                  mode, VOIDmode,
5276                                                                  cond, cop1),
5277                                         mode);
5278               else
5279                 return gen_rtx_IF_THEN_ELSE (mode,
5280                                              simplify_gen_relational (cond_code,
5281                                                                       mode,
5282                                                                       VOIDmode,
5283                                                                       cond,
5284                                                                       cop1),
5285                                              true_rtx, false_rtx);
5286
5287               code = GET_CODE (x);
5288               op0_mode = VOIDmode;
5289             }
5290         }
5291     }
5292
5293   /* Try to fold this expression in case we have constants that weren't
5294      present before.  */
5295   temp = 0;
5296   switch (GET_RTX_CLASS (code))
5297     {
5298     case RTX_UNARY:
5299       if (op0_mode == VOIDmode)
5300         op0_mode = GET_MODE (XEXP (x, 0));
5301       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5302       break;
5303     case RTX_COMPARE:
5304     case RTX_COMM_COMPARE:
5305       {
5306         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5307         if (cmp_mode == VOIDmode)
5308           {
5309             cmp_mode = GET_MODE (XEXP (x, 1));
5310             if (cmp_mode == VOIDmode)
5311               cmp_mode = op0_mode;
5312           }
5313         temp = simplify_relational_operation (code, mode, cmp_mode,
5314                                               XEXP (x, 0), XEXP (x, 1));
5315       }
5316       break;
5317     case RTX_COMM_ARITH:
5318     case RTX_BIN_ARITH:
5319       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5320       break;
5321     case RTX_BITFIELD_OPS:
5322     case RTX_TERNARY:
5323       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5324                                          XEXP (x, 1), XEXP (x, 2));
5325       break;
5326     default:
5327       break;
5328     }
5329
5330   if (temp)
5331     {
5332       x = temp;
5333       code = GET_CODE (temp);
5334       op0_mode = VOIDmode;
5335       mode = GET_MODE (temp);
5336     }
5337
5338   /* First see if we can apply the inverse distributive law.  */
5339   if (code == PLUS || code == MINUS
5340       || code == AND || code == IOR || code == XOR)
5341     {
5342       x = apply_distributive_law (x);
5343       code = GET_CODE (x);
5344       op0_mode = VOIDmode;
5345     }
5346
5347   /* If CODE is an associative operation not otherwise handled, see if we
5348      can associate some operands.  This can win if they are constants or
5349      if they are logically related (i.e. (a & b) & a).  */
5350   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5351        || code == AND || code == IOR || code == XOR
5352        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5353       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5354           || (flag_associative_math && FLOAT_MODE_P (mode))))
5355     {
5356       if (GET_CODE (XEXP (x, 0)) == code)
5357         {
5358           rtx other = XEXP (XEXP (x, 0), 0);
5359           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5360           rtx inner_op1 = XEXP (x, 1);
5361           rtx inner;
5362
5363           /* Make sure we pass the constant operand if any as the second
5364              one if this is a commutative operation.  */
5365           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5366             {
5367               rtx tem = inner_op0;
5368               inner_op0 = inner_op1;
5369               inner_op1 = tem;
5370             }
5371           inner = simplify_binary_operation (code == MINUS ? PLUS
5372                                              : code == DIV ? MULT
5373                                              : code,
5374                                              mode, inner_op0, inner_op1);
5375
5376           /* For commutative operations, try the other pair if that one
5377              didn't simplify.  */
5378           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5379             {
5380               other = XEXP (XEXP (x, 0), 1);
5381               inner = simplify_binary_operation (code, mode,
5382                                                  XEXP (XEXP (x, 0), 0),
5383                                                  XEXP (x, 1));
5384             }
5385
5386           if (inner)
5387             return simplify_gen_binary (code, mode, other, inner);
5388         }
5389     }
5390
5391   /* A little bit of algebraic simplification here.  */
5392   switch (code)
5393     {
5394     case MEM:
5395       /* Ensure that our address has any ASHIFTs converted to MULT in case
5396          address-recognizing predicates are called later.  */
5397       temp = make_compound_operation (XEXP (x, 0), MEM);
5398       SUBST (XEXP (x, 0), temp);
5399       break;
5400
5401     case SUBREG:
5402       if (op0_mode == VOIDmode)
5403         op0_mode = GET_MODE (SUBREG_REG (x));
5404
5405       /* See if this can be moved to simplify_subreg.  */
5406       if (CONSTANT_P (SUBREG_REG (x))
5407           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5408              /* Don't call gen_lowpart if the inner mode
5409                 is VOIDmode and we cannot simplify it, as SUBREG without
5410                 inner mode is invalid.  */
5411           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5412               || gen_lowpart_common (mode, SUBREG_REG (x))))
5413         return gen_lowpart (mode, SUBREG_REG (x));
5414
5415       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5416         break;
5417       {
5418         rtx temp;
5419         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5420                                 SUBREG_BYTE (x));
5421         if (temp)
5422           return temp;
5423
5424         /* If op is known to have all lower bits zero, the result is zero.  */
5425         if (!in_dest
5426             && SCALAR_INT_MODE_P (mode)
5427             && SCALAR_INT_MODE_P (op0_mode)
5428             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5429             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5430             && HWI_COMPUTABLE_MODE_P (op0_mode)
5431             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5432                 & GET_MODE_MASK (mode)) == 0)
5433           return CONST0_RTX (mode);
5434       }
5435
5436       /* Don't change the mode of the MEM if that would change the meaning
5437          of the address.  */
5438       if (MEM_P (SUBREG_REG (x))
5439           && (MEM_VOLATILE_P (SUBREG_REG (x))
5440               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5441                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5442         return gen_rtx_CLOBBER (mode, const0_rtx);
5443
5444       /* Note that we cannot do any narrowing for non-constants since
5445          we might have been counting on using the fact that some bits were
5446          zero.  We now do this in the SET.  */
5447
5448       break;
5449
5450     case NEG:
5451       temp = expand_compound_operation (XEXP (x, 0));
5452
5453       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5454          replaced by (lshiftrt X C).  This will convert
5455          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5456
5457       if (GET_CODE (temp) == ASHIFTRT
5458           && CONST_INT_P (XEXP (temp, 1))
5459           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5460         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5461                                      INTVAL (XEXP (temp, 1)));
5462
5463       /* If X has only a single bit that might be nonzero, say, bit I, convert
5464          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5465          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5466          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5467          or a SUBREG of one since we'd be making the expression more
5468          complex if it was just a register.  */
5469
5470       if (!REG_P (temp)
5471           && ! (GET_CODE (temp) == SUBREG
5472                 && REG_P (SUBREG_REG (temp)))
5473           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5474         {
5475           rtx temp1 = simplify_shift_const
5476             (NULL_RTX, ASHIFTRT, mode,
5477              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5478                                    GET_MODE_PRECISION (mode) - 1 - i),
5479              GET_MODE_PRECISION (mode) - 1 - i);
5480
5481           /* If all we did was surround TEMP with the two shifts, we
5482              haven't improved anything, so don't use it.  Otherwise,
5483              we are better off with TEMP1.  */
5484           if (GET_CODE (temp1) != ASHIFTRT
5485               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5486               || XEXP (XEXP (temp1, 0), 0) != temp)
5487             return temp1;
5488         }
5489       break;
5490
5491     case TRUNCATE:
5492       /* We can't handle truncation to a partial integer mode here
5493          because we don't know the real bitsize of the partial
5494          integer mode.  */
5495       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5496         break;
5497
5498       if (HWI_COMPUTABLE_MODE_P (mode))
5499         SUBST (XEXP (x, 0),
5500                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5501                               GET_MODE_MASK (mode), 0));
5502
5503       /* We can truncate a constant value and return it.  */
5504       if (CONST_INT_P (XEXP (x, 0)))
5505         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5506
5507       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5508          whose value is a comparison can be replaced with a subreg if
5509          STORE_FLAG_VALUE permits.  */
5510       if (HWI_COMPUTABLE_MODE_P (mode)
5511           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5512           && (temp = get_last_value (XEXP (x, 0)))
5513           && COMPARISON_P (temp))
5514         return gen_lowpart (mode, XEXP (x, 0));
5515       break;
5516
5517     case CONST:
5518       /* (const (const X)) can become (const X).  Do it this way rather than
5519          returning the inner CONST since CONST can be shared with a
5520          REG_EQUAL note.  */
5521       if (GET_CODE (XEXP (x, 0)) == CONST)
5522         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5523       break;
5524
5525 #ifdef HAVE_lo_sum
5526     case LO_SUM:
5527       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5528          can add in an offset.  find_split_point will split this address up
5529          again if it doesn't match.  */
5530       if (GET_CODE (XEXP (x, 0)) == HIGH
5531           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5532         return XEXP (x, 1);
5533       break;
5534 #endif
5535
5536     case PLUS:
5537       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5538          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5539          bit-field and can be replaced by either a sign_extend or a
5540          sign_extract.  The `and' may be a zero_extend and the two
5541          <c>, -<c> constants may be reversed.  */
5542       if (GET_CODE (XEXP (x, 0)) == XOR
5543           && CONST_INT_P (XEXP (x, 1))
5544           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5545           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5546           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5547               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5548           && HWI_COMPUTABLE_MODE_P (mode)
5549           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5550                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5551                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5552                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5553               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5554                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5555                       == (unsigned int) i + 1))))
5556         return simplify_shift_const
5557           (NULL_RTX, ASHIFTRT, mode,
5558            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5559                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5560                                  GET_MODE_PRECISION (mode) - (i + 1)),
5561            GET_MODE_PRECISION (mode) - (i + 1));
5562
5563       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5564          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5565          the bitsize of the mode - 1.  This allows simplification of
5566          "a = (b & 8) == 0;"  */
5567       if (XEXP (x, 1) == constm1_rtx
5568           && !REG_P (XEXP (x, 0))
5569           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5570                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5571           && nonzero_bits (XEXP (x, 0), mode) == 1)
5572         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5573            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5574                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5575                                  GET_MODE_PRECISION (mode) - 1),
5576            GET_MODE_PRECISION (mode) - 1);
5577
5578       /* If we are adding two things that have no bits in common, convert
5579          the addition into an IOR.  This will often be further simplified,
5580          for example in cases like ((a & 1) + (a & 2)), which can
5581          become a & 3.  */
5582
5583       if (HWI_COMPUTABLE_MODE_P (mode)
5584           && (nonzero_bits (XEXP (x, 0), mode)
5585               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5586         {
5587           /* Try to simplify the expression further.  */
5588           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5589           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5590
5591           /* If we could, great.  If not, do not go ahead with the IOR
5592              replacement, since PLUS appears in many special purpose
5593              address arithmetic instructions.  */
5594           if (GET_CODE (temp) != CLOBBER
5595               && (GET_CODE (temp) != IOR
5596                   || ((XEXP (temp, 0) != XEXP (x, 0)
5597                        || XEXP (temp, 1) != XEXP (x, 1))
5598                       && (XEXP (temp, 0) != XEXP (x, 1)
5599                           || XEXP (temp, 1) != XEXP (x, 0)))))
5600             return temp;
5601         }
5602       break;
5603
5604     case MINUS:
5605       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5606          (and <foo> (const_int pow2-1))  */
5607       if (GET_CODE (XEXP (x, 1)) == AND
5608           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5609           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5610           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5611         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5612                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5613       break;
5614
5615     case MULT:
5616       /* If we have (mult (plus A B) C), apply the distributive law and then
5617          the inverse distributive law to see if things simplify.  This
5618          occurs mostly in addresses, often when unrolling loops.  */
5619
5620       if (GET_CODE (XEXP (x, 0)) == PLUS)
5621         {
5622           rtx result = distribute_and_simplify_rtx (x, 0);
5623           if (result)
5624             return result;
5625         }
5626
5627       /* Try simplify a*(b/c) as (a*b)/c.  */
5628       if (FLOAT_MODE_P (mode) && flag_associative_math
5629           && GET_CODE (XEXP (x, 0)) == DIV)
5630         {
5631           rtx tem = simplify_binary_operation (MULT, mode,
5632                                                XEXP (XEXP (x, 0), 0),
5633                                                XEXP (x, 1));
5634           if (tem)
5635             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5636         }
5637       break;
5638
5639     case UDIV:
5640       /* If this is a divide by a power of two, treat it as a shift if
5641          its first operand is a shift.  */
5642       if (CONST_INT_P (XEXP (x, 1))
5643           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5644           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5645               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5646               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5647               || GET_CODE (XEXP (x, 0)) == ROTATE
5648               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5649         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5650       break;
5651
5652     case EQ:  case NE:
5653     case GT:  case GTU:  case GE:  case GEU:
5654     case LT:  case LTU:  case LE:  case LEU:
5655     case UNEQ:  case LTGT:
5656     case UNGT:  case UNGE:
5657     case UNLT:  case UNLE:
5658     case UNORDERED: case ORDERED:
5659       /* If the first operand is a condition code, we can't do anything
5660          with it.  */
5661       if (GET_CODE (XEXP (x, 0)) == COMPARE
5662           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5663               && ! CC0_P (XEXP (x, 0))))
5664         {
5665           rtx op0 = XEXP (x, 0);
5666           rtx op1 = XEXP (x, 1);
5667           enum rtx_code new_code;
5668
5669           if (GET_CODE (op0) == COMPARE)
5670             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5671
5672           /* Simplify our comparison, if possible.  */
5673           new_code = simplify_comparison (code, &op0, &op1);
5674
5675           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5676              if only the low-order bit is possibly nonzero in X (such as when
5677              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5678              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5679              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5680              (plus X 1).
5681
5682              Remove any ZERO_EXTRACT we made when thinking this was a
5683              comparison.  It may now be simpler to use, e.g., an AND.  If a
5684              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5685              the call to make_compound_operation in the SET case.
5686
5687              Don't apply these optimizations if the caller would
5688              prefer a comparison rather than a value.
5689              E.g., for the condition in an IF_THEN_ELSE most targets need
5690              an explicit comparison.  */
5691
5692           if (in_cond)
5693             ;
5694
5695           else if (STORE_FLAG_VALUE == 1
5696               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5697               && op1 == const0_rtx
5698               && mode == GET_MODE (op0)
5699               && nonzero_bits (op0, mode) == 1)
5700             return gen_lowpart (mode,
5701                                 expand_compound_operation (op0));
5702
5703           else if (STORE_FLAG_VALUE == 1
5704                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5705                    && op1 == const0_rtx
5706                    && mode == GET_MODE (op0)
5707                    && (num_sign_bit_copies (op0, mode)
5708                        == GET_MODE_PRECISION (mode)))
5709             {
5710               op0 = expand_compound_operation (op0);
5711               return simplify_gen_unary (NEG, mode,
5712                                          gen_lowpart (mode, op0),
5713                                          mode);
5714             }
5715
5716           else if (STORE_FLAG_VALUE == 1
5717                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5718                    && op1 == const0_rtx
5719                    && mode == GET_MODE (op0)
5720                    && nonzero_bits (op0, mode) == 1)
5721             {
5722               op0 = expand_compound_operation (op0);
5723               return simplify_gen_binary (XOR, mode,
5724                                           gen_lowpart (mode, op0),
5725                                           const1_rtx);
5726             }
5727
5728           else if (STORE_FLAG_VALUE == 1
5729                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5730                    && op1 == const0_rtx
5731                    && mode == GET_MODE (op0)
5732                    && (num_sign_bit_copies (op0, mode)
5733                        == GET_MODE_PRECISION (mode)))
5734             {
5735               op0 = expand_compound_operation (op0);
5736               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5737             }
5738
5739           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5740              those above.  */
5741           if (in_cond)
5742             ;
5743
5744           else if (STORE_FLAG_VALUE == -1
5745               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5746               && op1 == const0_rtx
5747               && (num_sign_bit_copies (op0, mode)
5748                   == GET_MODE_PRECISION (mode)))
5749             return gen_lowpart (mode,
5750                                 expand_compound_operation (op0));
5751
5752           else if (STORE_FLAG_VALUE == -1
5753                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5754                    && op1 == const0_rtx
5755                    && mode == GET_MODE (op0)
5756                    && nonzero_bits (op0, mode) == 1)
5757             {
5758               op0 = expand_compound_operation (op0);
5759               return simplify_gen_unary (NEG, mode,
5760                                          gen_lowpart (mode, op0),
5761                                          mode);
5762             }
5763
5764           else if (STORE_FLAG_VALUE == -1
5765                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5766                    && op1 == const0_rtx
5767                    && mode == GET_MODE (op0)
5768                    && (num_sign_bit_copies (op0, mode)
5769                        == GET_MODE_PRECISION (mode)))
5770             {
5771               op0 = expand_compound_operation (op0);
5772               return simplify_gen_unary (NOT, mode,
5773                                          gen_lowpart (mode, op0),
5774                                          mode);
5775             }
5776
5777           /* If X is 0/1, (eq X 0) is X-1.  */
5778           else if (STORE_FLAG_VALUE == -1
5779                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5780                    && op1 == const0_rtx
5781                    && mode == GET_MODE (op0)
5782                    && nonzero_bits (op0, mode) == 1)
5783             {
5784               op0 = expand_compound_operation (op0);
5785               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5786             }
5787
5788           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5789              one bit that might be nonzero, we can convert (ne x 0) to
5790              (ashift x c) where C puts the bit in the sign bit.  Remove any
5791              AND with STORE_FLAG_VALUE when we are done, since we are only
5792              going to test the sign bit.  */
5793           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5794               && HWI_COMPUTABLE_MODE_P (mode)
5795               && val_signbit_p (mode, STORE_FLAG_VALUE)
5796               && op1 == const0_rtx
5797               && mode == GET_MODE (op0)
5798               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5799             {
5800               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5801                                         expand_compound_operation (op0),
5802                                         GET_MODE_PRECISION (mode) - 1 - i);
5803               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5804                 return XEXP (x, 0);
5805               else
5806                 return x;
5807             }
5808
5809           /* If the code changed, return a whole new comparison.
5810              We also need to avoid using SUBST in cases where
5811              simplify_comparison has widened a comparison with a CONST_INT,
5812              since in that case the wider CONST_INT may fail the sanity
5813              checks in do_SUBST.  */
5814           if (new_code != code
5815               || (CONST_INT_P (op1)
5816                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5817                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5818             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5819
5820           /* Otherwise, keep this operation, but maybe change its operands.
5821              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5822           SUBST (XEXP (x, 0), op0);
5823           SUBST (XEXP (x, 1), op1);
5824         }
5825       break;
5826
5827     case IF_THEN_ELSE:
5828       return simplify_if_then_else (x);
5829
5830     case ZERO_EXTRACT:
5831     case SIGN_EXTRACT:
5832     case ZERO_EXTEND:
5833     case SIGN_EXTEND:
5834       /* If we are processing SET_DEST, we are done.  */
5835       if (in_dest)
5836         return x;
5837
5838       return expand_compound_operation (x);
5839
5840     case SET:
5841       return simplify_set (x);
5842
5843     case AND:
5844     case IOR:
5845       return simplify_logical (x);
5846
5847     case ASHIFT:
5848     case LSHIFTRT:
5849     case ASHIFTRT:
5850     case ROTATE:
5851     case ROTATERT:
5852       /* If this is a shift by a constant amount, simplify it.  */
5853       if (CONST_INT_P (XEXP (x, 1)))
5854         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5855                                      INTVAL (XEXP (x, 1)));
5856
5857       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5858         SUBST (XEXP (x, 1),
5859                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5860                               ((unsigned HOST_WIDE_INT) 1
5861                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5862                               - 1,
5863                               0));
5864       break;
5865
5866     default:
5867       break;
5868     }
5869
5870   return x;
5871 }
5872 \f
5873 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5874
5875 static rtx
5876 simplify_if_then_else (rtx x)
5877 {
5878   enum machine_mode mode = GET_MODE (x);
5879   rtx cond = XEXP (x, 0);
5880   rtx true_rtx = XEXP (x, 1);
5881   rtx false_rtx = XEXP (x, 2);
5882   enum rtx_code true_code = GET_CODE (cond);
5883   int comparison_p = COMPARISON_P (cond);
5884   rtx temp;
5885   int i;
5886   enum rtx_code false_code;
5887   rtx reversed;
5888
5889   /* Simplify storing of the truth value.  */
5890   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5891     return simplify_gen_relational (true_code, mode, VOIDmode,
5892                                     XEXP (cond, 0), XEXP (cond, 1));
5893
5894   /* Also when the truth value has to be reversed.  */
5895   if (comparison_p
5896       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5897       && (reversed = reversed_comparison (cond, mode)))
5898     return reversed;
5899
5900   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5901      in it is being compared against certain values.  Get the true and false
5902      comparisons and see if that says anything about the value of each arm.  */
5903
5904   if (comparison_p
5905       && ((false_code = reversed_comparison_code (cond, NULL))
5906           != UNKNOWN)
5907       && REG_P (XEXP (cond, 0)))
5908     {
5909       HOST_WIDE_INT nzb;
5910       rtx from = XEXP (cond, 0);
5911       rtx true_val = XEXP (cond, 1);
5912       rtx false_val = true_val;
5913       int swapped = 0;
5914
5915       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5916
5917       if (false_code == EQ)
5918         {
5919           swapped = 1, true_code = EQ, false_code = NE;
5920           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5921         }
5922
5923       /* If we are comparing against zero and the expression being tested has
5924          only a single bit that might be nonzero, that is its value when it is
5925          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5926
5927       if (true_code == EQ && true_val == const0_rtx
5928           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5929         {
5930           false_code = EQ;
5931           false_val = gen_int_mode (nzb, GET_MODE (from));
5932         }
5933       else if (true_code == EQ && true_val == const0_rtx
5934                && (num_sign_bit_copies (from, GET_MODE (from))
5935                    == GET_MODE_PRECISION (GET_MODE (from))))
5936         {
5937           false_code = EQ;
5938           false_val = constm1_rtx;
5939         }
5940
5941       /* Now simplify an arm if we know the value of the register in the
5942          branch and it is used in the arm.  Be careful due to the potential
5943          of locally-shared RTL.  */
5944
5945       if (reg_mentioned_p (from, true_rtx))
5946         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5947                                       from, true_val),
5948                           pc_rtx, pc_rtx, 0, 0, 0);
5949       if (reg_mentioned_p (from, false_rtx))
5950         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5951                                    from, false_val),
5952                            pc_rtx, pc_rtx, 0, 0, 0);
5953
5954       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5955       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5956
5957       true_rtx = XEXP (x, 1);
5958       false_rtx = XEXP (x, 2);
5959       true_code = GET_CODE (cond);
5960     }
5961
5962   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5963      reversed, do so to avoid needing two sets of patterns for
5964      subtract-and-branch insns.  Similarly if we have a constant in the true
5965      arm, the false arm is the same as the first operand of the comparison, or
5966      the false arm is more complicated than the true arm.  */
5967
5968   if (comparison_p
5969       && reversed_comparison_code (cond, NULL) != UNKNOWN
5970       && (true_rtx == pc_rtx
5971           || (CONSTANT_P (true_rtx)
5972               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5973           || true_rtx == const0_rtx
5974           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5975           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5976               && !OBJECT_P (false_rtx))
5977           || reg_mentioned_p (true_rtx, false_rtx)
5978           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5979     {
5980       true_code = reversed_comparison_code (cond, NULL);
5981       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5982       SUBST (XEXP (x, 1), false_rtx);
5983       SUBST (XEXP (x, 2), true_rtx);
5984
5985       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5986       cond = XEXP (x, 0);
5987
5988       /* It is possible that the conditional has been simplified out.  */
5989       true_code = GET_CODE (cond);
5990       comparison_p = COMPARISON_P (cond);
5991     }
5992
5993   /* If the two arms are identical, we don't need the comparison.  */
5994
5995   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5996     return true_rtx;
5997
5998   /* Convert a == b ? b : a to "a".  */
5999   if (true_code == EQ && ! side_effects_p (cond)
6000       && !HONOR_NANS (mode)
6001       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6002       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6003     return false_rtx;
6004   else if (true_code == NE && ! side_effects_p (cond)
6005            && !HONOR_NANS (mode)
6006            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6007            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6008     return true_rtx;
6009
6010   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6011
6012   if (GET_MODE_CLASS (mode) == MODE_INT
6013       && comparison_p
6014       && XEXP (cond, 1) == const0_rtx
6015       && GET_CODE (false_rtx) == NEG
6016       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6017       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6018       && ! side_effects_p (true_rtx))
6019     switch (true_code)
6020       {
6021       case GT:
6022       case GE:
6023         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6024       case LT:
6025       case LE:
6026         return
6027           simplify_gen_unary (NEG, mode,
6028                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6029                               mode);
6030       default:
6031         break;
6032       }
6033
6034   /* Look for MIN or MAX.  */
6035
6036   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6037       && comparison_p
6038       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6039       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6040       && ! side_effects_p (cond))
6041     switch (true_code)
6042       {
6043       case GE:
6044       case GT:
6045         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6046       case LE:
6047       case LT:
6048         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6049       case GEU:
6050       case GTU:
6051         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6052       case LEU:
6053       case LTU:
6054         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6055       default:
6056         break;
6057       }
6058
6059   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6060      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6061      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6062      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6063      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6064      neither 1 or -1, but it isn't worth checking for.  */
6065
6066   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6067       && comparison_p
6068       && GET_MODE_CLASS (mode) == MODE_INT
6069       && ! side_effects_p (x))
6070     {
6071       rtx t = make_compound_operation (true_rtx, SET);
6072       rtx f = make_compound_operation (false_rtx, SET);
6073       rtx cond_op0 = XEXP (cond, 0);
6074       rtx cond_op1 = XEXP (cond, 1);
6075       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6076       enum machine_mode m = mode;
6077       rtx z = 0, c1 = NULL_RTX;
6078
6079       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6080            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6081            || GET_CODE (t) == ASHIFT
6082            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6083           && rtx_equal_p (XEXP (t, 0), f))
6084         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6085
6086       /* If an identity-zero op is commutative, check whether there
6087          would be a match if we swapped the operands.  */
6088       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6089                 || GET_CODE (t) == XOR)
6090                && rtx_equal_p (XEXP (t, 1), f))
6091         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6092       else if (GET_CODE (t) == SIGN_EXTEND
6093                && (GET_CODE (XEXP (t, 0)) == PLUS
6094                    || GET_CODE (XEXP (t, 0)) == MINUS
6095                    || GET_CODE (XEXP (t, 0)) == IOR
6096                    || GET_CODE (XEXP (t, 0)) == XOR
6097                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6098                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6099                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6100                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6101                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6102                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6103                && (num_sign_bit_copies (f, GET_MODE (f))
6104                    > (unsigned int)
6105                      (GET_MODE_PRECISION (mode)
6106                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6107         {
6108           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6109           extend_op = SIGN_EXTEND;
6110           m = GET_MODE (XEXP (t, 0));
6111         }
6112       else if (GET_CODE (t) == SIGN_EXTEND
6113                && (GET_CODE (XEXP (t, 0)) == PLUS
6114                    || GET_CODE (XEXP (t, 0)) == IOR
6115                    || GET_CODE (XEXP (t, 0)) == XOR)
6116                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6117                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6118                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6119                && (num_sign_bit_copies (f, GET_MODE (f))
6120                    > (unsigned int)
6121                      (GET_MODE_PRECISION (mode)
6122                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6123         {
6124           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6125           extend_op = SIGN_EXTEND;
6126           m = GET_MODE (XEXP (t, 0));
6127         }
6128       else if (GET_CODE (t) == ZERO_EXTEND
6129                && (GET_CODE (XEXP (t, 0)) == PLUS
6130                    || GET_CODE (XEXP (t, 0)) == MINUS
6131                    || GET_CODE (XEXP (t, 0)) == IOR
6132                    || GET_CODE (XEXP (t, 0)) == XOR
6133                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6134                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6135                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6136                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6137                && HWI_COMPUTABLE_MODE_P (mode)
6138                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6139                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6140                && ((nonzero_bits (f, GET_MODE (f))
6141                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6142                    == 0))
6143         {
6144           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6145           extend_op = ZERO_EXTEND;
6146           m = GET_MODE (XEXP (t, 0));
6147         }
6148       else if (GET_CODE (t) == ZERO_EXTEND
6149                && (GET_CODE (XEXP (t, 0)) == PLUS
6150                    || GET_CODE (XEXP (t, 0)) == IOR
6151                    || GET_CODE (XEXP (t, 0)) == XOR)
6152                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6153                && HWI_COMPUTABLE_MODE_P (mode)
6154                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6155                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6156                && ((nonzero_bits (f, GET_MODE (f))
6157                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6158                    == 0))
6159         {
6160           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6161           extend_op = ZERO_EXTEND;
6162           m = GET_MODE (XEXP (t, 0));
6163         }
6164
6165       if (z)
6166         {
6167           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6168                                                  cond_op0, cond_op1),
6169                         pc_rtx, pc_rtx, 0, 0, 0);
6170           temp = simplify_gen_binary (MULT, m, temp,
6171                                       simplify_gen_binary (MULT, m, c1,
6172                                                            const_true_rtx));
6173           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6174           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6175
6176           if (extend_op != UNKNOWN)
6177             temp = simplify_gen_unary (extend_op, mode, temp, m);
6178
6179           return temp;
6180         }
6181     }
6182
6183   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6184      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6185      negation of a single bit, we can convert this operation to a shift.  We
6186      can actually do this more generally, but it doesn't seem worth it.  */
6187
6188   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6189       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6190       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6191            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6192           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6193                == GET_MODE_PRECISION (mode))
6194               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6195     return
6196       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6197                             gen_lowpart (mode, XEXP (cond, 0)), i);
6198
6199   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6200   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6201       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6202       && GET_MODE (XEXP (cond, 0)) == mode
6203       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6204           == nonzero_bits (XEXP (cond, 0), mode)
6205       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6206     return XEXP (cond, 0);
6207
6208   return x;
6209 }
6210 \f
6211 /* Simplify X, a SET expression.  Return the new expression.  */
6212
6213 static rtx
6214 simplify_set (rtx x)
6215 {
6216   rtx src = SET_SRC (x);
6217   rtx dest = SET_DEST (x);
6218   enum machine_mode mode
6219     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6220   rtx other_insn;
6221   rtx *cc_use;
6222
6223   /* (set (pc) (return)) gets written as (return).  */
6224   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6225     return src;
6226
6227   /* Now that we know for sure which bits of SRC we are using, see if we can
6228      simplify the expression for the object knowing that we only need the
6229      low-order bits.  */
6230
6231   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6232     {
6233       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6234       SUBST (SET_SRC (x), src);
6235     }
6236
6237   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6238      the comparison result and try to simplify it unless we already have used
6239      undobuf.other_insn.  */
6240   if ((GET_MODE_CLASS (mode) == MODE_CC
6241        || GET_CODE (src) == COMPARE
6242        || CC0_P (dest))
6243       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6244       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6245       && COMPARISON_P (*cc_use)
6246       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6247     {
6248       enum rtx_code old_code = GET_CODE (*cc_use);
6249       enum rtx_code new_code;
6250       rtx op0, op1, tmp;
6251       int other_changed = 0;
6252       rtx inner_compare = NULL_RTX;
6253       enum machine_mode compare_mode = GET_MODE (dest);
6254
6255       if (GET_CODE (src) == COMPARE)
6256         {
6257           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6258           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6259             {
6260               inner_compare = op0;
6261               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6262             }
6263         }
6264       else
6265         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6266
6267       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6268                                            op0, op1);
6269       if (!tmp)
6270         new_code = old_code;
6271       else if (!CONSTANT_P (tmp))
6272         {
6273           new_code = GET_CODE (tmp);
6274           op0 = XEXP (tmp, 0);
6275           op1 = XEXP (tmp, 1);
6276         }
6277       else
6278         {
6279           rtx pat = PATTERN (other_insn);
6280           undobuf.other_insn = other_insn;
6281           SUBST (*cc_use, tmp);
6282
6283           /* Attempt to simplify CC user.  */
6284           if (GET_CODE (pat) == SET)
6285             {
6286               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6287               if (new_rtx != NULL_RTX)
6288                 SUBST (SET_SRC (pat), new_rtx);
6289             }
6290
6291           /* Convert X into a no-op move.  */
6292           SUBST (SET_DEST (x), pc_rtx);
6293           SUBST (SET_SRC (x), pc_rtx);
6294           return x;
6295         }
6296
6297       /* Simplify our comparison, if possible.  */
6298       new_code = simplify_comparison (new_code, &op0, &op1);
6299
6300 #ifdef SELECT_CC_MODE
6301       /* If this machine has CC modes other than CCmode, check to see if we
6302          need to use a different CC mode here.  */
6303       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6304         compare_mode = GET_MODE (op0);
6305       else if (inner_compare
6306                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6307                && new_code == old_code
6308                && op0 == XEXP (inner_compare, 0)
6309                && op1 == XEXP (inner_compare, 1))
6310         compare_mode = GET_MODE (inner_compare);
6311       else
6312         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6313
6314 #ifndef HAVE_cc0
6315       /* If the mode changed, we have to change SET_DEST, the mode in the
6316          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6317          a hard register, just build new versions with the proper mode.  If it
6318          is a pseudo, we lose unless it is only time we set the pseudo, in
6319          which case we can safely change its mode.  */
6320       if (compare_mode != GET_MODE (dest))
6321         {
6322           if (can_change_dest_mode (dest, 0, compare_mode))
6323             {
6324               unsigned int regno = REGNO (dest);
6325               rtx new_dest;
6326
6327               if (regno < FIRST_PSEUDO_REGISTER)
6328                 new_dest = gen_rtx_REG (compare_mode, regno);
6329               else
6330                 {
6331                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6332                   new_dest = regno_reg_rtx[regno];
6333                 }
6334
6335               SUBST (SET_DEST (x), new_dest);
6336               SUBST (XEXP (*cc_use, 0), new_dest);
6337               other_changed = 1;
6338
6339               dest = new_dest;
6340             }
6341         }
6342 #endif  /* cc0 */
6343 #endif  /* SELECT_CC_MODE */
6344
6345       /* If the code changed, we have to build a new comparison in
6346          undobuf.other_insn.  */
6347       if (new_code != old_code)
6348         {
6349           int other_changed_previously = other_changed;
6350           unsigned HOST_WIDE_INT mask;
6351           rtx old_cc_use = *cc_use;
6352
6353           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6354                                           dest, const0_rtx));
6355           other_changed = 1;
6356
6357           /* If the only change we made was to change an EQ into an NE or
6358              vice versa, OP0 has only one bit that might be nonzero, and OP1
6359              is zero, check if changing the user of the condition code will
6360              produce a valid insn.  If it won't, we can keep the original code
6361              in that insn by surrounding our operation with an XOR.  */
6362
6363           if (((old_code == NE && new_code == EQ)
6364                || (old_code == EQ && new_code == NE))
6365               && ! other_changed_previously && op1 == const0_rtx
6366               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6367               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6368             {
6369               rtx pat = PATTERN (other_insn), note = 0;
6370
6371               if ((recog_for_combine (&pat, other_insn, &note) < 0
6372                    && ! check_asm_operands (pat)))
6373                 {
6374                   *cc_use = old_cc_use;
6375                   other_changed = 0;
6376
6377                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6378                                              gen_int_mode (mask,
6379                                                            GET_MODE (op0)));
6380                 }
6381             }
6382         }
6383
6384       if (other_changed)
6385         undobuf.other_insn = other_insn;
6386
6387       /* Otherwise, if we didn't previously have a COMPARE in the
6388          correct mode, we need one.  */
6389       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6390         {
6391           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6392           src = SET_SRC (x);
6393         }
6394       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6395         {
6396           SUBST (SET_SRC (x), op0);
6397           src = SET_SRC (x);
6398         }
6399       /* Otherwise, update the COMPARE if needed.  */
6400       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6401         {
6402           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6403           src = SET_SRC (x);
6404         }
6405     }
6406   else
6407     {
6408       /* Get SET_SRC in a form where we have placed back any
6409          compound expressions.  Then do the checks below.  */
6410       src = make_compound_operation (src, SET);
6411       SUBST (SET_SRC (x), src);
6412     }
6413
6414   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6415      and X being a REG or (subreg (reg)), we may be able to convert this to
6416      (set (subreg:m2 x) (op)).
6417
6418      We can always do this if M1 is narrower than M2 because that means that
6419      we only care about the low bits of the result.
6420
6421      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6422      perform a narrower operation than requested since the high-order bits will
6423      be undefined.  On machine where it is defined, this transformation is safe
6424      as long as M1 and M2 have the same number of words.  */
6425
6426   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6427       && !OBJECT_P (SUBREG_REG (src))
6428       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6429            / UNITS_PER_WORD)
6430           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6431                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6432 #ifndef WORD_REGISTER_OPERATIONS
6433       && (GET_MODE_SIZE (GET_MODE (src))
6434         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6435 #endif
6436 #ifdef CANNOT_CHANGE_MODE_CLASS
6437       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6438             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6439                                          GET_MODE (SUBREG_REG (src)),
6440                                          GET_MODE (src)))
6441 #endif
6442       && (REG_P (dest)
6443           || (GET_CODE (dest) == SUBREG
6444               && REG_P (SUBREG_REG (dest)))))
6445     {
6446       SUBST (SET_DEST (x),
6447              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6448                                       dest));
6449       SUBST (SET_SRC (x), SUBREG_REG (src));
6450
6451       src = SET_SRC (x), dest = SET_DEST (x);
6452     }
6453
6454 #ifdef HAVE_cc0
6455   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6456      in SRC.  */
6457   if (dest == cc0_rtx
6458       && GET_CODE (src) == SUBREG
6459       && subreg_lowpart_p (src)
6460       && (GET_MODE_PRECISION (GET_MODE (src))
6461           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6462     {
6463       rtx inner = SUBREG_REG (src);
6464       enum machine_mode inner_mode = GET_MODE (inner);
6465
6466       /* Here we make sure that we don't have a sign bit on.  */
6467       if (val_signbit_known_clear_p (GET_MODE (src),
6468                                      nonzero_bits (inner, inner_mode)))
6469         {
6470           SUBST (SET_SRC (x), inner);
6471           src = SET_SRC (x);
6472         }
6473     }
6474 #endif
6475
6476 #ifdef LOAD_EXTEND_OP
6477   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6478      would require a paradoxical subreg.  Replace the subreg with a
6479      zero_extend to avoid the reload that would otherwise be required.  */
6480
6481   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6482       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6483       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6484       && SUBREG_BYTE (src) == 0
6485       && paradoxical_subreg_p (src)
6486       && MEM_P (SUBREG_REG (src)))
6487     {
6488       SUBST (SET_SRC (x),
6489              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6490                             GET_MODE (src), SUBREG_REG (src)));
6491
6492       src = SET_SRC (x);
6493     }
6494 #endif
6495
6496   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6497      are comparing an item known to be 0 or -1 against 0, use a logical
6498      operation instead. Check for one of the arms being an IOR of the other
6499      arm with some value.  We compute three terms to be IOR'ed together.  In
6500      practice, at most two will be nonzero.  Then we do the IOR's.  */
6501
6502   if (GET_CODE (dest) != PC
6503       && GET_CODE (src) == IF_THEN_ELSE
6504       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6505       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6506       && XEXP (XEXP (src, 0), 1) == const0_rtx
6507       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6508 #ifdef HAVE_conditional_move
6509       && ! can_conditionally_move_p (GET_MODE (src))
6510 #endif
6511       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6512                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6513           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6514       && ! side_effects_p (src))
6515     {
6516       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6517                       ? XEXP (src, 1) : XEXP (src, 2));
6518       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6519                    ? XEXP (src, 2) : XEXP (src, 1));
6520       rtx term1 = const0_rtx, term2, term3;
6521
6522       if (GET_CODE (true_rtx) == IOR
6523           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6524         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6525       else if (GET_CODE (true_rtx) == IOR
6526                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6527         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6528       else if (GET_CODE (false_rtx) == IOR
6529                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6530         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6531       else if (GET_CODE (false_rtx) == IOR
6532                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6533         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6534
6535       term2 = simplify_gen_binary (AND, GET_MODE (src),
6536                                    XEXP (XEXP (src, 0), 0), true_rtx);
6537       term3 = simplify_gen_binary (AND, GET_MODE (src),
6538                                    simplify_gen_unary (NOT, GET_MODE (src),
6539                                                        XEXP (XEXP (src, 0), 0),
6540                                                        GET_MODE (src)),
6541                                    false_rtx);
6542
6543       SUBST (SET_SRC (x),
6544              simplify_gen_binary (IOR, GET_MODE (src),
6545                                   simplify_gen_binary (IOR, GET_MODE (src),
6546                                                        term1, term2),
6547                                   term3));
6548
6549       src = SET_SRC (x);
6550     }
6551
6552   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6553      whole thing fail.  */
6554   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6555     return src;
6556   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6557     return dest;
6558   else
6559     /* Convert this into a field assignment operation, if possible.  */
6560     return make_field_assignment (x);
6561 }
6562 \f
6563 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6564    result.  */
6565
6566 static rtx
6567 simplify_logical (rtx x)
6568 {
6569   enum machine_mode mode = GET_MODE (x);
6570   rtx op0 = XEXP (x, 0);
6571   rtx op1 = XEXP (x, 1);
6572
6573   switch (GET_CODE (x))
6574     {
6575     case AND:
6576       /* We can call simplify_and_const_int only if we don't lose
6577          any (sign) bits when converting INTVAL (op1) to
6578          "unsigned HOST_WIDE_INT".  */
6579       if (CONST_INT_P (op1)
6580           && (HWI_COMPUTABLE_MODE_P (mode)
6581               || INTVAL (op1) > 0))
6582         {
6583           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6584           if (GET_CODE (x) != AND)
6585             return x;
6586
6587           op0 = XEXP (x, 0);
6588           op1 = XEXP (x, 1);
6589         }
6590
6591       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6592          apply the distributive law and then the inverse distributive
6593          law to see if things simplify.  */
6594       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6595         {
6596           rtx result = distribute_and_simplify_rtx (x, 0);
6597           if (result)
6598             return result;
6599         }
6600       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6601         {
6602           rtx result = distribute_and_simplify_rtx (x, 1);
6603           if (result)
6604             return result;
6605         }
6606       break;
6607
6608     case IOR:
6609       /* If we have (ior (and A B) C), apply the distributive law and then
6610          the inverse distributive law to see if things simplify.  */
6611
6612       if (GET_CODE (op0) == AND)
6613         {
6614           rtx result = distribute_and_simplify_rtx (x, 0);
6615           if (result)
6616             return result;
6617         }
6618
6619       if (GET_CODE (op1) == AND)
6620         {
6621           rtx result = distribute_and_simplify_rtx (x, 1);
6622           if (result)
6623             return result;
6624         }
6625       break;
6626
6627     default:
6628       gcc_unreachable ();
6629     }
6630
6631   return x;
6632 }
6633 \f
6634 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6635    operations" because they can be replaced with two more basic operations.
6636    ZERO_EXTEND is also considered "compound" because it can be replaced with
6637    an AND operation, which is simpler, though only one operation.
6638
6639    The function expand_compound_operation is called with an rtx expression
6640    and will convert it to the appropriate shifts and AND operations,
6641    simplifying at each stage.
6642
6643    The function make_compound_operation is called to convert an expression
6644    consisting of shifts and ANDs into the equivalent compound expression.
6645    It is the inverse of this function, loosely speaking.  */
6646
6647 static rtx
6648 expand_compound_operation (rtx x)
6649 {
6650   unsigned HOST_WIDE_INT pos = 0, len;
6651   int unsignedp = 0;
6652   unsigned int modewidth;
6653   rtx tem;
6654
6655   switch (GET_CODE (x))
6656     {
6657     case ZERO_EXTEND:
6658       unsignedp = 1;
6659     case SIGN_EXTEND:
6660       /* We can't necessarily use a const_int for a multiword mode;
6661          it depends on implicitly extending the value.
6662          Since we don't know the right way to extend it,
6663          we can't tell whether the implicit way is right.
6664
6665          Even for a mode that is no wider than a const_int,
6666          we can't win, because we need to sign extend one of its bits through
6667          the rest of it, and we don't know which bit.  */
6668       if (CONST_INT_P (XEXP (x, 0)))
6669         return x;
6670
6671       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6672          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6673          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6674          reloaded. If not for that, MEM's would very rarely be safe.
6675
6676          Reject MODEs bigger than a word, because we might not be able
6677          to reference a two-register group starting with an arbitrary register
6678          (and currently gen_lowpart might crash for a SUBREG).  */
6679
6680       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6681         return x;
6682
6683       /* Reject MODEs that aren't scalar integers because turning vector
6684          or complex modes into shifts causes problems.  */
6685
6686       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6687         return x;
6688
6689       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6690       /* If the inner object has VOIDmode (the only way this can happen
6691          is if it is an ASM_OPERANDS), we can't do anything since we don't
6692          know how much masking to do.  */
6693       if (len == 0)
6694         return x;
6695
6696       break;
6697
6698     case ZERO_EXTRACT:
6699       unsignedp = 1;
6700
6701       /* ... fall through ...  */
6702
6703     case SIGN_EXTRACT:
6704       /* If the operand is a CLOBBER, just return it.  */
6705       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6706         return XEXP (x, 0);
6707
6708       if (!CONST_INT_P (XEXP (x, 1))
6709           || !CONST_INT_P (XEXP (x, 2))
6710           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6711         return x;
6712
6713       /* Reject MODEs that aren't scalar integers because turning vector
6714          or complex modes into shifts causes problems.  */
6715
6716       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6717         return x;
6718
6719       len = INTVAL (XEXP (x, 1));
6720       pos = INTVAL (XEXP (x, 2));
6721
6722       /* This should stay within the object being extracted, fail otherwise.  */
6723       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6724         return x;
6725
6726       if (BITS_BIG_ENDIAN)
6727         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6728
6729       break;
6730
6731     default:
6732       return x;
6733     }
6734   /* Convert sign extension to zero extension, if we know that the high
6735      bit is not set, as this is easier to optimize.  It will be converted
6736      back to cheaper alternative in make_extraction.  */
6737   if (GET_CODE (x) == SIGN_EXTEND
6738       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6739           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6740                 & ~(((unsigned HOST_WIDE_INT)
6741                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6742                      >> 1))
6743                == 0)))
6744     {
6745       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6746       rtx temp2 = expand_compound_operation (temp);
6747
6748       /* Make sure this is a profitable operation.  */
6749       if (set_src_cost (x, optimize_this_for_speed_p)
6750           > set_src_cost (temp2, optimize_this_for_speed_p))
6751        return temp2;
6752       else if (set_src_cost (x, optimize_this_for_speed_p)
6753                > set_src_cost (temp, optimize_this_for_speed_p))
6754        return temp;
6755       else
6756        return x;
6757     }
6758
6759   /* We can optimize some special cases of ZERO_EXTEND.  */
6760   if (GET_CODE (x) == ZERO_EXTEND)
6761     {
6762       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6763          know that the last value didn't have any inappropriate bits
6764          set.  */
6765       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6766           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6767           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6768           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6769               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6770         return XEXP (XEXP (x, 0), 0);
6771
6772       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6773       if (GET_CODE (XEXP (x, 0)) == SUBREG
6774           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6775           && subreg_lowpart_p (XEXP (x, 0))
6776           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6777           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6778               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6779         return SUBREG_REG (XEXP (x, 0));
6780
6781       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6782          is a comparison and STORE_FLAG_VALUE permits.  This is like
6783          the first case, but it works even when GET_MODE (x) is larger
6784          than HOST_WIDE_INT.  */
6785       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6786           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6787           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6788           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6789               <= HOST_BITS_PER_WIDE_INT)
6790           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6791         return XEXP (XEXP (x, 0), 0);
6792
6793       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6794       if (GET_CODE (XEXP (x, 0)) == SUBREG
6795           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6796           && subreg_lowpart_p (XEXP (x, 0))
6797           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6798           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6799               <= HOST_BITS_PER_WIDE_INT)
6800           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6801         return SUBREG_REG (XEXP (x, 0));
6802
6803     }
6804
6805   /* If we reach here, we want to return a pair of shifts.  The inner
6806      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6807      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6808      logical depending on the value of UNSIGNEDP.
6809
6810      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6811      converted into an AND of a shift.
6812
6813      We must check for the case where the left shift would have a negative
6814      count.  This can happen in a case like (x >> 31) & 255 on machines
6815      that can't shift by a constant.  On those machines, we would first
6816      combine the shift with the AND to produce a variable-position
6817      extraction.  Then the constant of 31 would be substituted in
6818      to produce such a position.  */
6819
6820   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6821   if (modewidth >= pos + len)
6822     {
6823       enum machine_mode mode = GET_MODE (x);
6824       tem = gen_lowpart (mode, XEXP (x, 0));
6825       if (!tem || GET_CODE (tem) == CLOBBER)
6826         return x;
6827       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6828                                   tem, modewidth - pos - len);
6829       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6830                                   mode, tem, modewidth - len);
6831     }
6832   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6833     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6834                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6835                                                         GET_MODE (x),
6836                                                         XEXP (x, 0), pos),
6837                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6838   else
6839     /* Any other cases we can't handle.  */
6840     return x;
6841
6842   /* If we couldn't do this for some reason, return the original
6843      expression.  */
6844   if (GET_CODE (tem) == CLOBBER)
6845     return x;
6846
6847   return tem;
6848 }
6849 \f
6850 /* X is a SET which contains an assignment of one object into
6851    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6852    or certain SUBREGS). If possible, convert it into a series of
6853    logical operations.
6854
6855    We half-heartedly support variable positions, but do not at all
6856    support variable lengths.  */
6857
6858 static const_rtx
6859 expand_field_assignment (const_rtx x)
6860 {
6861   rtx inner;
6862   rtx pos;                      /* Always counts from low bit.  */
6863   int len;
6864   rtx mask, cleared, masked;
6865   enum machine_mode compute_mode;
6866
6867   /* Loop until we find something we can't simplify.  */
6868   while (1)
6869     {
6870       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6871           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6872         {
6873           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6874           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6875           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6876         }
6877       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6878                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6879         {
6880           inner = XEXP (SET_DEST (x), 0);
6881           len = INTVAL (XEXP (SET_DEST (x), 1));
6882           pos = XEXP (SET_DEST (x), 2);
6883
6884           /* A constant position should stay within the width of INNER.  */
6885           if (CONST_INT_P (pos)
6886               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6887             break;
6888
6889           if (BITS_BIG_ENDIAN)
6890             {
6891               if (CONST_INT_P (pos))
6892                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6893                                - INTVAL (pos));
6894               else if (GET_CODE (pos) == MINUS
6895                        && CONST_INT_P (XEXP (pos, 1))
6896                        && (INTVAL (XEXP (pos, 1))
6897                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6898                 /* If position is ADJUST - X, new position is X.  */
6899                 pos = XEXP (pos, 0);
6900               else
6901                 {
6902                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6903                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6904                                              gen_int_mode (prec - len,
6905                                                            GET_MODE (pos)),
6906                                              pos);
6907                 }
6908             }
6909         }
6910
6911       /* A SUBREG between two modes that occupy the same numbers of words
6912          can be done by moving the SUBREG to the source.  */
6913       else if (GET_CODE (SET_DEST (x)) == SUBREG
6914                /* We need SUBREGs to compute nonzero_bits properly.  */
6915                && nonzero_sign_valid
6916                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6917                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6918                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6919                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6920         {
6921           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6922                            gen_lowpart
6923                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6924                             SET_SRC (x)));
6925           continue;
6926         }
6927       else
6928         break;
6929
6930       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6931         inner = SUBREG_REG (inner);
6932
6933       compute_mode = GET_MODE (inner);
6934
6935       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6936       if (! SCALAR_INT_MODE_P (compute_mode))
6937         {
6938           enum machine_mode imode;
6939
6940           /* Don't do anything for vector or complex integral types.  */
6941           if (! FLOAT_MODE_P (compute_mode))
6942             break;
6943
6944           /* Try to find an integral mode to pun with.  */
6945           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6946           if (imode == BLKmode)
6947             break;
6948
6949           compute_mode = imode;
6950           inner = gen_lowpart (imode, inner);
6951         }
6952
6953       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6954       if (len >= HOST_BITS_PER_WIDE_INT)
6955         break;
6956
6957       /* Now compute the equivalent expression.  Make a copy of INNER
6958          for the SET_DEST in case it is a MEM into which we will substitute;
6959          we don't want shared RTL in that case.  */
6960       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
6961                            compute_mode);
6962       cleared = simplify_gen_binary (AND, compute_mode,
6963                                      simplify_gen_unary (NOT, compute_mode,
6964                                        simplify_gen_binary (ASHIFT,
6965                                                             compute_mode,
6966                                                             mask, pos),
6967                                        compute_mode),
6968                                      inner);
6969       masked = simplify_gen_binary (ASHIFT, compute_mode,
6970                                     simplify_gen_binary (
6971                                       AND, compute_mode,
6972                                       gen_lowpart (compute_mode, SET_SRC (x)),
6973                                       mask),
6974                                     pos);
6975
6976       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6977                        simplify_gen_binary (IOR, compute_mode,
6978                                             cleared, masked));
6979     }
6980
6981   return x;
6982 }
6983 \f
6984 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6985    it is an RTX that represents the (variable) starting position; otherwise,
6986    POS is the (constant) starting bit position.  Both are counted from the LSB.
6987
6988    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6989
6990    IN_DEST is nonzero if this is a reference in the destination of a SET.
6991    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6992    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6993    be used.
6994
6995    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6996    ZERO_EXTRACT should be built even for bits starting at bit 0.
6997
6998    MODE is the desired mode of the result (if IN_DEST == 0).
6999
7000    The result is an RTX for the extraction or NULL_RTX if the target
7001    can't handle it.  */
7002
7003 static rtx
7004 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7005                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7006                  int in_dest, int in_compare)
7007 {
7008   /* This mode describes the size of the storage area
7009      to fetch the overall value from.  Within that, we
7010      ignore the POS lowest bits, etc.  */
7011   enum machine_mode is_mode = GET_MODE (inner);
7012   enum machine_mode inner_mode;
7013   enum machine_mode wanted_inner_mode;
7014   enum machine_mode wanted_inner_reg_mode = word_mode;
7015   enum machine_mode pos_mode = word_mode;
7016   enum machine_mode extraction_mode = word_mode;
7017   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7018   rtx new_rtx = 0;
7019   rtx orig_pos_rtx = pos_rtx;
7020   HOST_WIDE_INT orig_pos;
7021
7022   if (pos_rtx && CONST_INT_P (pos_rtx))
7023     pos = INTVAL (pos_rtx), pos_rtx = 0;
7024
7025   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7026     {
7027       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7028          consider just the QI as the memory to extract from.
7029          The subreg adds or removes high bits; its mode is
7030          irrelevant to the meaning of this extraction,
7031          since POS and LEN count from the lsb.  */
7032       if (MEM_P (SUBREG_REG (inner)))
7033         is_mode = GET_MODE (SUBREG_REG (inner));
7034       inner = SUBREG_REG (inner);
7035     }
7036   else if (GET_CODE (inner) == ASHIFT
7037            && CONST_INT_P (XEXP (inner, 1))
7038            && pos_rtx == 0 && pos == 0
7039            && len > UINTVAL (XEXP (inner, 1)))
7040     {
7041       /* We're extracting the least significant bits of an rtx
7042          (ashift X (const_int C)), where LEN > C.  Extract the
7043          least significant (LEN - C) bits of X, giving an rtx
7044          whose mode is MODE, then shift it left C times.  */
7045       new_rtx = make_extraction (mode, XEXP (inner, 0),
7046                              0, 0, len - INTVAL (XEXP (inner, 1)),
7047                              unsignedp, in_dest, in_compare);
7048       if (new_rtx != 0)
7049         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7050     }
7051   else if (GET_CODE (inner) == TRUNCATE)
7052     inner = XEXP (inner, 0);
7053
7054   inner_mode = GET_MODE (inner);
7055
7056   /* See if this can be done without an extraction.  We never can if the
7057      width of the field is not the same as that of some integer mode. For
7058      registers, we can only avoid the extraction if the position is at the
7059      low-order bit and this is either not in the destination or we have the
7060      appropriate STRICT_LOW_PART operation available.
7061
7062      For MEM, we can avoid an extract if the field starts on an appropriate
7063      boundary and we can change the mode of the memory reference.  */
7064
7065   if (tmode != BLKmode
7066       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7067            && !MEM_P (inner)
7068            && (inner_mode == tmode
7069                || !REG_P (inner)
7070                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7071                || reg_truncated_to_mode (tmode, inner))
7072            && (! in_dest
7073                || (REG_P (inner)
7074                    && have_insn_for (STRICT_LOW_PART, tmode))))
7075           || (MEM_P (inner) && pos_rtx == 0
7076               && (pos
7077                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7078                      : BITS_PER_UNIT)) == 0
7079               /* We can't do this if we are widening INNER_MODE (it
7080                  may not be aligned, for one thing).  */
7081               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7082               && (inner_mode == tmode
7083                   || (! mode_dependent_address_p (XEXP (inner, 0),
7084                                                   MEM_ADDR_SPACE (inner))
7085                       && ! MEM_VOLATILE_P (inner))))))
7086     {
7087       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7088          field.  If the original and current mode are the same, we need not
7089          adjust the offset.  Otherwise, we do if bytes big endian.
7090
7091          If INNER is not a MEM, get a piece consisting of just the field
7092          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7093
7094       if (MEM_P (inner))
7095         {
7096           HOST_WIDE_INT offset;
7097
7098           /* POS counts from lsb, but make OFFSET count in memory order.  */
7099           if (BYTES_BIG_ENDIAN)
7100             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7101           else
7102             offset = pos / BITS_PER_UNIT;
7103
7104           new_rtx = adjust_address_nv (inner, tmode, offset);
7105         }
7106       else if (REG_P (inner))
7107         {
7108           if (tmode != inner_mode)
7109             {
7110               /* We can't call gen_lowpart in a DEST since we
7111                  always want a SUBREG (see below) and it would sometimes
7112                  return a new hard register.  */
7113               if (pos || in_dest)
7114                 {
7115                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7116
7117                   if (WORDS_BIG_ENDIAN
7118                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7119                     final_word = ((GET_MODE_SIZE (inner_mode)
7120                                    - GET_MODE_SIZE (tmode))
7121                                   / UNITS_PER_WORD) - final_word;
7122
7123                   final_word *= UNITS_PER_WORD;
7124                   if (BYTES_BIG_ENDIAN &&
7125                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7126                     final_word += (GET_MODE_SIZE (inner_mode)
7127                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7128
7129                   /* Avoid creating invalid subregs, for example when
7130                      simplifying (x>>32)&255.  */
7131                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7132                     return NULL_RTX;
7133
7134                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7135                 }
7136               else
7137                 new_rtx = gen_lowpart (tmode, inner);
7138             }
7139           else
7140             new_rtx = inner;
7141         }
7142       else
7143         new_rtx = force_to_mode (inner, tmode,
7144                              len >= HOST_BITS_PER_WIDE_INT
7145                              ? ~(unsigned HOST_WIDE_INT) 0
7146                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7147                              0);
7148
7149       /* If this extraction is going into the destination of a SET,
7150          make a STRICT_LOW_PART unless we made a MEM.  */
7151
7152       if (in_dest)
7153         return (MEM_P (new_rtx) ? new_rtx
7154                 : (GET_CODE (new_rtx) != SUBREG
7155                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7156                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7157
7158       if (mode == tmode)
7159         return new_rtx;
7160
7161       if (CONST_SCALAR_INT_P (new_rtx))
7162         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7163                                          mode, new_rtx, tmode);
7164
7165       /* If we know that no extraneous bits are set, and that the high
7166          bit is not set, convert the extraction to the cheaper of
7167          sign and zero extension, that are equivalent in these cases.  */
7168       if (flag_expensive_optimizations
7169           && (HWI_COMPUTABLE_MODE_P (tmode)
7170               && ((nonzero_bits (new_rtx, tmode)
7171                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7172                   == 0)))
7173         {
7174           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7175           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7176
7177           /* Prefer ZERO_EXTENSION, since it gives more information to
7178              backends.  */
7179           if (set_src_cost (temp, optimize_this_for_speed_p)
7180               <= set_src_cost (temp1, optimize_this_for_speed_p))
7181             return temp;
7182           return temp1;
7183         }
7184
7185       /* Otherwise, sign- or zero-extend unless we already are in the
7186          proper mode.  */
7187
7188       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7189                              mode, new_rtx));
7190     }
7191
7192   /* Unless this is a COMPARE or we have a funny memory reference,
7193      don't do anything with zero-extending field extracts starting at
7194      the low-order bit since they are simple AND operations.  */
7195   if (pos_rtx == 0 && pos == 0 && ! in_dest
7196       && ! in_compare && unsignedp)
7197     return 0;
7198
7199   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7200      if the position is not a constant and the length is not 1.  In all
7201      other cases, we would only be going outside our object in cases when
7202      an original shift would have been undefined.  */
7203   if (MEM_P (inner)
7204       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7205           || (pos_rtx != 0 && len != 1)))
7206     return 0;
7207
7208   enum extraction_pattern pattern = (in_dest ? EP_insv
7209                                      : unsignedp ? EP_extzv : EP_extv);
7210
7211   /* If INNER is not from memory, we want it to have the mode of a register
7212      extraction pattern's structure operand, or word_mode if there is no
7213      such pattern.  The same applies to extraction_mode and pos_mode
7214      and their respective operands.
7215
7216      For memory, assume that the desired extraction_mode and pos_mode
7217      are the same as for a register operation, since at present we don't
7218      have named patterns for aligned memory structures.  */
7219   struct extraction_insn insn;
7220   if (get_best_reg_extraction_insn (&insn, pattern,
7221                                     GET_MODE_BITSIZE (inner_mode), mode))
7222     {
7223       wanted_inner_reg_mode = insn.struct_mode;
7224       pos_mode = insn.pos_mode;
7225       extraction_mode = insn.field_mode;
7226     }
7227
7228   /* Never narrow an object, since that might not be safe.  */
7229
7230   if (mode != VOIDmode
7231       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7232     extraction_mode = mode;
7233
7234   if (!MEM_P (inner))
7235     wanted_inner_mode = wanted_inner_reg_mode;
7236   else
7237     {
7238       /* Be careful not to go beyond the extracted object and maintain the
7239          natural alignment of the memory.  */
7240       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7241       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7242              > GET_MODE_BITSIZE (wanted_inner_mode))
7243         {
7244           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7245           gcc_assert (wanted_inner_mode != VOIDmode);
7246         }
7247     }
7248
7249   orig_pos = pos;
7250
7251   if (BITS_BIG_ENDIAN)
7252     {
7253       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7254          BITS_BIG_ENDIAN style.  If position is constant, compute new
7255          position.  Otherwise, build subtraction.
7256          Note that POS is relative to the mode of the original argument.
7257          If it's a MEM we need to recompute POS relative to that.
7258          However, if we're extracting from (or inserting into) a register,
7259          we want to recompute POS relative to wanted_inner_mode.  */
7260       int width = (MEM_P (inner)
7261                    ? GET_MODE_BITSIZE (is_mode)
7262                    : GET_MODE_BITSIZE (wanted_inner_mode));
7263
7264       if (pos_rtx == 0)
7265         pos = width - len - pos;
7266       else
7267         pos_rtx
7268           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7269                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7270                            pos_rtx);
7271       /* POS may be less than 0 now, but we check for that below.
7272          Note that it can only be less than 0 if !MEM_P (inner).  */
7273     }
7274
7275   /* If INNER has a wider mode, and this is a constant extraction, try to
7276      make it smaller and adjust the byte to point to the byte containing
7277      the value.  */
7278   if (wanted_inner_mode != VOIDmode
7279       && inner_mode != wanted_inner_mode
7280       && ! pos_rtx
7281       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7282       && MEM_P (inner)
7283       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7284       && ! MEM_VOLATILE_P (inner))
7285     {
7286       int offset = 0;
7287
7288       /* The computations below will be correct if the machine is big
7289          endian in both bits and bytes or little endian in bits and bytes.
7290          If it is mixed, we must adjust.  */
7291
7292       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7293          adjust OFFSET to compensate.  */
7294       if (BYTES_BIG_ENDIAN
7295           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7296         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7297
7298       /* We can now move to the desired byte.  */
7299       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7300                 * GET_MODE_SIZE (wanted_inner_mode);
7301       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7302
7303       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7304           && is_mode != wanted_inner_mode)
7305         offset = (GET_MODE_SIZE (is_mode)
7306                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7307
7308       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7309     }
7310
7311   /* If INNER is not memory, get it into the proper mode.  If we are changing
7312      its mode, POS must be a constant and smaller than the size of the new
7313      mode.  */
7314   else if (!MEM_P (inner))
7315     {
7316       /* On the LHS, don't create paradoxical subregs implicitely truncating
7317          the register unless TRULY_NOOP_TRUNCATION.  */
7318       if (in_dest
7319           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7320                                              wanted_inner_mode))
7321         return NULL_RTX;
7322
7323       if (GET_MODE (inner) != wanted_inner_mode
7324           && (pos_rtx != 0
7325               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7326         return NULL_RTX;
7327
7328       if (orig_pos < 0)
7329         return NULL_RTX;
7330
7331       inner = force_to_mode (inner, wanted_inner_mode,
7332                              pos_rtx
7333                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7334                              ? ~(unsigned HOST_WIDE_INT) 0
7335                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7336                                 << orig_pos),
7337                              0);
7338     }
7339
7340   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7341      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7342   if (pos_rtx != 0
7343       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7344     {
7345       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7346                                      GET_MODE (pos_rtx));
7347
7348       /* If we know that no extraneous bits are set, and that the high
7349          bit is not set, convert extraction to cheaper one - either
7350          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7351          cases.  */
7352       if (flag_expensive_optimizations
7353           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7354               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7355                    & ~(((unsigned HOST_WIDE_INT)
7356                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7357                        >> 1))
7358                   == 0)))
7359         {
7360           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7361                                           GET_MODE (pos_rtx));
7362
7363           /* Prefer ZERO_EXTENSION, since it gives more information to
7364              backends.  */
7365           if (set_src_cost (temp1, optimize_this_for_speed_p)
7366               < set_src_cost (temp, optimize_this_for_speed_p))
7367             temp = temp1;
7368         }
7369       pos_rtx = temp;
7370     }
7371
7372   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7373      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7374      be a CONST_INT.  */
7375   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7376     pos_rtx = orig_pos_rtx;
7377
7378   else if (pos_rtx == 0)
7379     pos_rtx = GEN_INT (pos);
7380
7381   /* Make the required operation.  See if we can use existing rtx.  */
7382   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7383                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7384   if (! in_dest)
7385     new_rtx = gen_lowpart (mode, new_rtx);
7386
7387   return new_rtx;
7388 }
7389 \f
7390 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7391    with any other operations in X.  Return X without that shift if so.  */
7392
7393 static rtx
7394 extract_left_shift (rtx x, int count)
7395 {
7396   enum rtx_code code = GET_CODE (x);
7397   enum machine_mode mode = GET_MODE (x);
7398   rtx tem;
7399
7400   switch (code)
7401     {
7402     case ASHIFT:
7403       /* This is the shift itself.  If it is wide enough, we will return
7404          either the value being shifted if the shift count is equal to
7405          COUNT or a shift for the difference.  */
7406       if (CONST_INT_P (XEXP (x, 1))
7407           && INTVAL (XEXP (x, 1)) >= count)
7408         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7409                                      INTVAL (XEXP (x, 1)) - count);
7410       break;
7411
7412     case NEG:  case NOT:
7413       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7414         return simplify_gen_unary (code, mode, tem, mode);
7415
7416       break;
7417
7418     case PLUS:  case IOR:  case XOR:  case AND:
7419       /* If we can safely shift this constant and we find the inner shift,
7420          make a new operation.  */
7421       if (CONST_INT_P (XEXP (x, 1))
7422           && (UINTVAL (XEXP (x, 1))
7423               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7424           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7425         {
7426           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7427           return simplify_gen_binary (code, mode, tem,
7428                                       gen_int_mode (val, mode));
7429         }
7430       break;
7431
7432     default:
7433       break;
7434     }
7435
7436   return 0;
7437 }
7438 \f
7439 /* Look at the expression rooted at X.  Look for expressions
7440    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7441    Form these expressions.
7442
7443    Return the new rtx, usually just X.
7444
7445    Also, for machines like the VAX that don't have logical shift insns,
7446    try to convert logical to arithmetic shift operations in cases where
7447    they are equivalent.  This undoes the canonicalizations to logical
7448    shifts done elsewhere.
7449
7450    We try, as much as possible, to re-use rtl expressions to save memory.
7451
7452    IN_CODE says what kind of expression we are processing.  Normally, it is
7453    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7454    being kludges), it is MEM.  When processing the arguments of a comparison
7455    or a COMPARE against zero, it is COMPARE.  */
7456
7457 rtx
7458 make_compound_operation (rtx x, enum rtx_code in_code)
7459 {
7460   enum rtx_code code = GET_CODE (x);
7461   enum machine_mode mode = GET_MODE (x);
7462   int mode_width = GET_MODE_PRECISION (mode);
7463   rtx rhs, lhs;
7464   enum rtx_code next_code;
7465   int i, j;
7466   rtx new_rtx = 0;
7467   rtx tem;
7468   const char *fmt;
7469
7470   /* Select the code to be used in recursive calls.  Once we are inside an
7471      address, we stay there.  If we have a comparison, set to COMPARE,
7472      but once inside, go back to our default of SET.  */
7473
7474   next_code = (code == MEM ? MEM
7475                : ((code == PLUS || code == MINUS)
7476                   && SCALAR_INT_MODE_P (mode)) ? MEM
7477                : ((code == COMPARE || COMPARISON_P (x))
7478                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7479                : in_code == COMPARE ? SET : in_code);
7480
7481   /* Process depending on the code of this operation.  If NEW is set
7482      nonzero, it will be returned.  */
7483
7484   switch (code)
7485     {
7486     case ASHIFT:
7487       /* Convert shifts by constants into multiplications if inside
7488          an address.  */
7489       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7490           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7491           && INTVAL (XEXP (x, 1)) >= 0
7492           && SCALAR_INT_MODE_P (mode))
7493         {
7494           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7495           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7496
7497           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7498           if (GET_CODE (new_rtx) == NEG)
7499             {
7500               new_rtx = XEXP (new_rtx, 0);
7501               multval = -multval;
7502             }
7503           multval = trunc_int_for_mode (multval, mode);
7504           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7505         }
7506       break;
7507
7508     case PLUS:
7509       lhs = XEXP (x, 0);
7510       rhs = XEXP (x, 1);
7511       lhs = make_compound_operation (lhs, next_code);
7512       rhs = make_compound_operation (rhs, next_code);
7513       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7514           && SCALAR_INT_MODE_P (mode))
7515         {
7516           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7517                                      XEXP (lhs, 1));
7518           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7519         }
7520       else if (GET_CODE (lhs) == MULT
7521                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7522         {
7523           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7524                                      simplify_gen_unary (NEG, mode,
7525                                                          XEXP (lhs, 1),
7526                                                          mode));
7527           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7528         }
7529       else
7530         {
7531           SUBST (XEXP (x, 0), lhs);
7532           SUBST (XEXP (x, 1), rhs);
7533           goto maybe_swap;
7534         }
7535       x = gen_lowpart (mode, new_rtx);
7536       goto maybe_swap;
7537
7538     case MINUS:
7539       lhs = XEXP (x, 0);
7540       rhs = XEXP (x, 1);
7541       lhs = make_compound_operation (lhs, next_code);
7542       rhs = make_compound_operation (rhs, next_code);
7543       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7544           && SCALAR_INT_MODE_P (mode))
7545         {
7546           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7547                                      XEXP (rhs, 1));
7548           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7549         }
7550       else if (GET_CODE (rhs) == MULT
7551                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7552         {
7553           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7554                                      simplify_gen_unary (NEG, mode,
7555                                                          XEXP (rhs, 1),
7556                                                          mode));
7557           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7558         }
7559       else
7560         {
7561           SUBST (XEXP (x, 0), lhs);
7562           SUBST (XEXP (x, 1), rhs);
7563           return x;
7564         }
7565       return gen_lowpart (mode, new_rtx);
7566
7567     case AND:
7568       /* If the second operand is not a constant, we can't do anything
7569          with it.  */
7570       if (!CONST_INT_P (XEXP (x, 1)))
7571         break;
7572
7573       /* If the constant is a power of two minus one and the first operand
7574          is a logical right shift, make an extraction.  */
7575       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7576           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7577         {
7578           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7579           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7580                                  0, in_code == COMPARE);
7581         }
7582
7583       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7584       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7585                && subreg_lowpart_p (XEXP (x, 0))
7586                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7587                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7588         {
7589           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7590                                          next_code);
7591           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7592                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7593                                  0, in_code == COMPARE);
7594         }
7595       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7596       else if ((GET_CODE (XEXP (x, 0)) == XOR
7597                 || GET_CODE (XEXP (x, 0)) == IOR)
7598                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7599                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7600                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7601         {
7602           /* Apply the distributive law, and then try to make extractions.  */
7603           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7604                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7605                                              XEXP (x, 1)),
7606                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7607                                              XEXP (x, 1)));
7608           new_rtx = make_compound_operation (new_rtx, in_code);
7609         }
7610
7611       /* If we are have (and (rotate X C) M) and C is larger than the number
7612          of bits in M, this is an extraction.  */
7613
7614       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7615                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7616                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7617                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7618         {
7619           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7620           new_rtx = make_extraction (mode, new_rtx,
7621                                  (GET_MODE_PRECISION (mode)
7622                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7623                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7624         }
7625
7626       /* On machines without logical shifts, if the operand of the AND is
7627          a logical shift and our mask turns off all the propagated sign
7628          bits, we can replace the logical shift with an arithmetic shift.  */
7629       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7630                && !have_insn_for (LSHIFTRT, mode)
7631                && have_insn_for (ASHIFTRT, mode)
7632                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7633                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7634                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7635                && mode_width <= HOST_BITS_PER_WIDE_INT)
7636         {
7637           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7638
7639           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7640           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7641             SUBST (XEXP (x, 0),
7642                    gen_rtx_ASHIFTRT (mode,
7643                                      make_compound_operation
7644                                      (XEXP (XEXP (x, 0), 0), next_code),
7645                                      XEXP (XEXP (x, 0), 1)));
7646         }
7647
7648       /* If the constant is one less than a power of two, this might be
7649          representable by an extraction even if no shift is present.
7650          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7651          we are in a COMPARE.  */
7652       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7653         new_rtx = make_extraction (mode,
7654                                make_compound_operation (XEXP (x, 0),
7655                                                         next_code),
7656                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7657
7658       /* If we are in a comparison and this is an AND with a power of two,
7659          convert this into the appropriate bit extract.  */
7660       else if (in_code == COMPARE
7661                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7662         new_rtx = make_extraction (mode,
7663                                make_compound_operation (XEXP (x, 0),
7664                                                         next_code),
7665                                i, NULL_RTX, 1, 1, 0, 1);
7666
7667       break;
7668
7669     case LSHIFTRT:
7670       /* If the sign bit is known to be zero, replace this with an
7671          arithmetic shift.  */
7672       if (have_insn_for (ASHIFTRT, mode)
7673           && ! have_insn_for (LSHIFTRT, mode)
7674           && mode_width <= HOST_BITS_PER_WIDE_INT
7675           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7676         {
7677           new_rtx = gen_rtx_ASHIFTRT (mode,
7678                                   make_compound_operation (XEXP (x, 0),
7679                                                            next_code),
7680                                   XEXP (x, 1));
7681           break;
7682         }
7683
7684       /* ... fall through ...  */
7685
7686     case ASHIFTRT:
7687       lhs = XEXP (x, 0);
7688       rhs = XEXP (x, 1);
7689
7690       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7691          this is a SIGN_EXTRACT.  */
7692       if (CONST_INT_P (rhs)
7693           && GET_CODE (lhs) == ASHIFT
7694           && CONST_INT_P (XEXP (lhs, 1))
7695           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7696           && INTVAL (XEXP (lhs, 1)) >= 0
7697           && INTVAL (rhs) < mode_width)
7698         {
7699           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7700           new_rtx = make_extraction (mode, new_rtx,
7701                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7702                                  NULL_RTX, mode_width - INTVAL (rhs),
7703                                  code == LSHIFTRT, 0, in_code == COMPARE);
7704           break;
7705         }
7706
7707       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7708          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7709          also do this for some cases of SIGN_EXTRACT, but it doesn't
7710          seem worth the effort; the case checked for occurs on Alpha.  */
7711
7712       if (!OBJECT_P (lhs)
7713           && ! (GET_CODE (lhs) == SUBREG
7714                 && (OBJECT_P (SUBREG_REG (lhs))))
7715           && CONST_INT_P (rhs)
7716           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7717           && INTVAL (rhs) < mode_width
7718           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7719         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7720                                0, NULL_RTX, mode_width - INTVAL (rhs),
7721                                code == LSHIFTRT, 0, in_code == COMPARE);
7722
7723       break;
7724
7725     case SUBREG:
7726       /* Call ourselves recursively on the inner expression.  If we are
7727          narrowing the object and it has a different RTL code from
7728          what it originally did, do this SUBREG as a force_to_mode.  */
7729       {
7730         rtx inner = SUBREG_REG (x), simplified;
7731         enum rtx_code subreg_code = in_code;
7732
7733         /* If in_code is COMPARE, it isn't always safe to pass it through
7734            to the recursive make_compound_operation call.  */
7735         if (subreg_code == COMPARE
7736             && (!subreg_lowpart_p (x)
7737                 || GET_CODE (inner) == SUBREG
7738                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7739                    is (const_int 0), rather than
7740                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7741                 || (GET_CODE (inner) == AND
7742                     && CONST_INT_P (XEXP (inner, 1))
7743                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7744                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7745                        >= GET_MODE_BITSIZE (mode))))
7746           subreg_code = SET;
7747
7748         tem = make_compound_operation (inner, subreg_code);
7749
7750         simplified
7751           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7752         if (simplified)
7753           tem = simplified;
7754
7755         if (GET_CODE (tem) != GET_CODE (inner)
7756             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7757             && subreg_lowpart_p (x))
7758           {
7759             rtx newer
7760               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7761
7762             /* If we have something other than a SUBREG, we might have
7763                done an expansion, so rerun ourselves.  */
7764             if (GET_CODE (newer) != SUBREG)
7765               newer = make_compound_operation (newer, in_code);
7766
7767             /* force_to_mode can expand compounds.  If it just re-expanded the
7768                compound, use gen_lowpart to convert to the desired mode.  */
7769             if (rtx_equal_p (newer, x)
7770                 /* Likewise if it re-expanded the compound only partially.
7771                    This happens for SUBREG of ZERO_EXTRACT if they extract
7772                    the same number of bits.  */
7773                 || (GET_CODE (newer) == SUBREG
7774                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7775                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7776                     && GET_CODE (inner) == AND
7777                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7778               return gen_lowpart (GET_MODE (x), tem);
7779
7780             return newer;
7781           }
7782
7783         if (simplified)
7784           return tem;
7785       }
7786       break;
7787
7788     default:
7789       break;
7790     }
7791
7792   if (new_rtx)
7793     {
7794       x = gen_lowpart (mode, new_rtx);
7795       code = GET_CODE (x);
7796     }
7797
7798   /* Now recursively process each operand of this operation.  We need to
7799      handle ZERO_EXTEND specially so that we don't lose track of the
7800      inner mode.  */
7801   if (GET_CODE (x) == ZERO_EXTEND)
7802     {
7803       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7804       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7805                                             new_rtx, GET_MODE (XEXP (x, 0)));
7806       if (tem)
7807         return tem;
7808       SUBST (XEXP (x, 0), new_rtx);
7809       return x;
7810     }
7811
7812   fmt = GET_RTX_FORMAT (code);
7813   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7814     if (fmt[i] == 'e')
7815       {
7816         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7817         SUBST (XEXP (x, i), new_rtx);
7818       }
7819     else if (fmt[i] == 'E')
7820       for (j = 0; j < XVECLEN (x, i); j++)
7821         {
7822           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7823           SUBST (XVECEXP (x, i, j), new_rtx);
7824         }
7825
7826  maybe_swap:
7827   /* If this is a commutative operation, the changes to the operands
7828      may have made it noncanonical.  */
7829   if (COMMUTATIVE_ARITH_P (x)
7830       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7831     {
7832       tem = XEXP (x, 0);
7833       SUBST (XEXP (x, 0), XEXP (x, 1));
7834       SUBST (XEXP (x, 1), tem);
7835     }
7836
7837   return x;
7838 }
7839 \f
7840 /* Given M see if it is a value that would select a field of bits
7841    within an item, but not the entire word.  Return -1 if not.
7842    Otherwise, return the starting position of the field, where 0 is the
7843    low-order bit.
7844
7845    *PLEN is set to the length of the field.  */
7846
7847 static int
7848 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7849 {
7850   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7851   int pos = m ? ctz_hwi (m) : -1;
7852   int len = 0;
7853
7854   if (pos >= 0)
7855     /* Now shift off the low-order zero bits and see if we have a
7856        power of two minus 1.  */
7857     len = exact_log2 ((m >> pos) + 1);
7858
7859   if (len <= 0)
7860     pos = -1;
7861
7862   *plen = len;
7863   return pos;
7864 }
7865 \f
7866 /* If X refers to a register that equals REG in value, replace these
7867    references with REG.  */
7868 static rtx
7869 canon_reg_for_combine (rtx x, rtx reg)
7870 {
7871   rtx op0, op1, op2;
7872   const char *fmt;
7873   int i;
7874   bool copied;
7875
7876   enum rtx_code code = GET_CODE (x);
7877   switch (GET_RTX_CLASS (code))
7878     {
7879     case RTX_UNARY:
7880       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7881       if (op0 != XEXP (x, 0))
7882         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7883                                    GET_MODE (reg));
7884       break;
7885
7886     case RTX_BIN_ARITH:
7887     case RTX_COMM_ARITH:
7888       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7889       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7890       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7891         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7892       break;
7893
7894     case RTX_COMPARE:
7895     case RTX_COMM_COMPARE:
7896       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7897       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7898       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7899         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7900                                         GET_MODE (op0), op0, op1);
7901       break;
7902
7903     case RTX_TERNARY:
7904     case RTX_BITFIELD_OPS:
7905       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7906       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7907       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7908       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7909         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7910                                      GET_MODE (op0), op0, op1, op2);
7911
7912     case RTX_OBJ:
7913       if (REG_P (x))
7914         {
7915           if (rtx_equal_p (get_last_value (reg), x)
7916               || rtx_equal_p (reg, get_last_value (x)))
7917             return reg;
7918           else
7919             break;
7920         }
7921
7922       /* fall through */
7923
7924     default:
7925       fmt = GET_RTX_FORMAT (code);
7926       copied = false;
7927       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7928         if (fmt[i] == 'e')
7929           {
7930             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7931             if (op != XEXP (x, i))
7932               {
7933                 if (!copied)
7934                   {
7935                     copied = true;
7936                     x = copy_rtx (x);
7937                   }
7938                 XEXP (x, i) = op;
7939               }
7940           }
7941         else if (fmt[i] == 'E')
7942           {
7943             int j;
7944             for (j = 0; j < XVECLEN (x, i); j++)
7945               {
7946                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7947                 if (op != XVECEXP (x, i, j))
7948                   {
7949                     if (!copied)
7950                       {
7951                         copied = true;
7952                         x = copy_rtx (x);
7953                       }
7954                     XVECEXP (x, i, j) = op;
7955                   }
7956               }
7957           }
7958
7959       break;
7960     }
7961
7962   return x;
7963 }
7964
7965 /* Return X converted to MODE.  If the value is already truncated to
7966    MODE we can just return a subreg even though in the general case we
7967    would need an explicit truncation.  */
7968
7969 static rtx
7970 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7971 {
7972   if (!CONST_INT_P (x)
7973       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7974       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7975       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7976     {
7977       /* Bit-cast X into an integer mode.  */
7978       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7979         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7980       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7981                               x, GET_MODE (x));
7982     }
7983
7984   return gen_lowpart (mode, x);
7985 }
7986
7987 /* See if X can be simplified knowing that we will only refer to it in
7988    MODE and will only refer to those bits that are nonzero in MASK.
7989    If other bits are being computed or if masking operations are done
7990    that select a superset of the bits in MASK, they can sometimes be
7991    ignored.
7992
7993    Return a possibly simplified expression, but always convert X to
7994    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
7995
7996    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7997    are all off in X.  This is used when X will be complemented, by either
7998    NOT, NEG, or XOR.  */
7999
8000 static rtx
8001 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8002                int just_select)
8003 {
8004   enum rtx_code code = GET_CODE (x);
8005   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8006   enum machine_mode op_mode;
8007   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8008   rtx op0, op1, temp;
8009
8010   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8011      code below will do the wrong thing since the mode of such an
8012      expression is VOIDmode.
8013
8014      Also do nothing if X is a CLOBBER; this can happen if X was
8015      the return value from a call to gen_lowpart.  */
8016   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8017     return x;
8018
8019   /* We want to perform the operation is its present mode unless we know
8020      that the operation is valid in MODE, in which case we do the operation
8021      in MODE.  */
8022   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8023               && have_insn_for (code, mode))
8024              ? mode : GET_MODE (x));
8025
8026   /* It is not valid to do a right-shift in a narrower mode
8027      than the one it came in with.  */
8028   if ((code == LSHIFTRT || code == ASHIFTRT)
8029       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8030     op_mode = GET_MODE (x);
8031
8032   /* Truncate MASK to fit OP_MODE.  */
8033   if (op_mode)
8034     mask &= GET_MODE_MASK (op_mode);
8035
8036   /* When we have an arithmetic operation, or a shift whose count we
8037      do not know, we need to assume that all bits up to the highest-order
8038      bit in MASK will be needed.  This is how we form such a mask.  */
8039   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8040     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8041   else
8042     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8043                    - 1);
8044
8045   /* Determine what bits of X are guaranteed to be (non)zero.  */
8046   nonzero = nonzero_bits (x, mode);
8047
8048   /* If none of the bits in X are needed, return a zero.  */
8049   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8050     x = const0_rtx;
8051
8052   /* If X is a CONST_INT, return a new one.  Do this here since the
8053      test below will fail.  */
8054   if (CONST_INT_P (x))
8055     {
8056       if (SCALAR_INT_MODE_P (mode))
8057         return gen_int_mode (INTVAL (x) & mask, mode);
8058       else
8059         {
8060           x = GEN_INT (INTVAL (x) & mask);
8061           return gen_lowpart_common (mode, x);
8062         }
8063     }
8064
8065   /* If X is narrower than MODE and we want all the bits in X's mode, just
8066      get X in the proper mode.  */
8067   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8068       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8069     return gen_lowpart (mode, x);
8070
8071   /* We can ignore the effect of a SUBREG if it narrows the mode or
8072      if the constant masks to zero all the bits the mode doesn't have.  */
8073   if (GET_CODE (x) == SUBREG
8074       && subreg_lowpart_p (x)
8075       && ((GET_MODE_SIZE (GET_MODE (x))
8076            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8077           || (0 == (mask
8078                     & GET_MODE_MASK (GET_MODE (x))
8079                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8080     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8081
8082   /* The arithmetic simplifications here only work for scalar integer modes.  */
8083   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8084     return gen_lowpart_or_truncate (mode, x);
8085
8086   switch (code)
8087     {
8088     case CLOBBER:
8089       /* If X is a (clobber (const_int)), return it since we know we are
8090          generating something that won't match.  */
8091       return x;
8092
8093     case SIGN_EXTEND:
8094     case ZERO_EXTEND:
8095     case ZERO_EXTRACT:
8096     case SIGN_EXTRACT:
8097       x = expand_compound_operation (x);
8098       if (GET_CODE (x) != code)
8099         return force_to_mode (x, mode, mask, next_select);
8100       break;
8101
8102     case TRUNCATE:
8103       /* Similarly for a truncate.  */
8104       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8105
8106     case AND:
8107       /* If this is an AND with a constant, convert it into an AND
8108          whose constant is the AND of that constant with MASK.  If it
8109          remains an AND of MASK, delete it since it is redundant.  */
8110
8111       if (CONST_INT_P (XEXP (x, 1)))
8112         {
8113           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8114                                       mask & INTVAL (XEXP (x, 1)));
8115
8116           /* If X is still an AND, see if it is an AND with a mask that
8117              is just some low-order bits.  If so, and it is MASK, we don't
8118              need it.  */
8119
8120           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8121               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8122                   == mask))
8123             x = XEXP (x, 0);
8124
8125           /* If it remains an AND, try making another AND with the bits
8126              in the mode mask that aren't in MASK turned on.  If the
8127              constant in the AND is wide enough, this might make a
8128              cheaper constant.  */
8129
8130           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8131               && GET_MODE_MASK (GET_MODE (x)) != mask
8132               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8133             {
8134               unsigned HOST_WIDE_INT cval
8135                 = UINTVAL (XEXP (x, 1))
8136                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8137               rtx y;
8138
8139               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8140                                        gen_int_mode (cval, GET_MODE (x)));
8141               if (set_src_cost (y, optimize_this_for_speed_p)
8142                   < set_src_cost (x, optimize_this_for_speed_p))
8143                 x = y;
8144             }
8145
8146           break;
8147         }
8148
8149       goto binop;
8150
8151     case PLUS:
8152       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8153          low-order bits (as in an alignment operation) and FOO is already
8154          aligned to that boundary, mask C1 to that boundary as well.
8155          This may eliminate that PLUS and, later, the AND.  */
8156
8157       {
8158         unsigned int width = GET_MODE_PRECISION (mode);
8159         unsigned HOST_WIDE_INT smask = mask;
8160
8161         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8162            number, sign extend it.  */
8163
8164         if (width < HOST_BITS_PER_WIDE_INT
8165             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8166           smask |= HOST_WIDE_INT_M1U << width;
8167
8168         if (CONST_INT_P (XEXP (x, 1))
8169             && exact_log2 (- smask) >= 0
8170             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8171             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8172           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8173                                                (INTVAL (XEXP (x, 1)) & smask)),
8174                                 mode, smask, next_select);
8175       }
8176
8177       /* ... fall through ...  */
8178
8179     case MULT:
8180       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8181          most significant bit in MASK since carries from those bits will
8182          affect the bits we are interested in.  */
8183       mask = fuller_mask;
8184       goto binop;
8185
8186     case MINUS:
8187       /* If X is (minus C Y) where C's least set bit is larger than any bit
8188          in the mask, then we may replace with (neg Y).  */
8189       if (CONST_INT_P (XEXP (x, 0))
8190           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8191                                         & -INTVAL (XEXP (x, 0))))
8192               > mask))
8193         {
8194           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8195                                   GET_MODE (x));
8196           return force_to_mode (x, mode, mask, next_select);
8197         }
8198
8199       /* Similarly, if C contains every bit in the fuller_mask, then we may
8200          replace with (not Y).  */
8201       if (CONST_INT_P (XEXP (x, 0))
8202           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8203         {
8204           x = simplify_gen_unary (NOT, GET_MODE (x),
8205                                   XEXP (x, 1), GET_MODE (x));
8206           return force_to_mode (x, mode, mask, next_select);
8207         }
8208
8209       mask = fuller_mask;
8210       goto binop;
8211
8212     case IOR:
8213     case XOR:
8214       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8215          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8216          operation which may be a bitfield extraction.  Ensure that the
8217          constant we form is not wider than the mode of X.  */
8218
8219       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8220           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8221           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8222           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8223           && CONST_INT_P (XEXP (x, 1))
8224           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8225                + floor_log2 (INTVAL (XEXP (x, 1))))
8226               < GET_MODE_PRECISION (GET_MODE (x)))
8227           && (UINTVAL (XEXP (x, 1))
8228               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8229         {
8230           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8231                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8232                                GET_MODE (x));
8233           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8234                                       XEXP (XEXP (x, 0), 0), temp);
8235           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8236                                    XEXP (XEXP (x, 0), 1));
8237           return force_to_mode (x, mode, mask, next_select);
8238         }
8239
8240     binop:
8241       /* For most binary operations, just propagate into the operation and
8242          change the mode if we have an operation of that mode.  */
8243
8244       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8245       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8246
8247       /* If we ended up truncating both operands, truncate the result of the
8248          operation instead.  */
8249       if (GET_CODE (op0) == TRUNCATE
8250           && GET_CODE (op1) == TRUNCATE)
8251         {
8252           op0 = XEXP (op0, 0);
8253           op1 = XEXP (op1, 0);
8254         }
8255
8256       op0 = gen_lowpart_or_truncate (op_mode, op0);
8257       op1 = gen_lowpart_or_truncate (op_mode, op1);
8258
8259       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8260         x = simplify_gen_binary (code, op_mode, op0, op1);
8261       break;
8262
8263     case ASHIFT:
8264       /* For left shifts, do the same, but just for the first operand.
8265          However, we cannot do anything with shifts where we cannot
8266          guarantee that the counts are smaller than the size of the mode
8267          because such a count will have a different meaning in a
8268          wider mode.  */
8269
8270       if (! (CONST_INT_P (XEXP (x, 1))
8271              && INTVAL (XEXP (x, 1)) >= 0
8272              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8273           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8274                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8275                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8276         break;
8277
8278       /* If the shift count is a constant and we can do arithmetic in
8279          the mode of the shift, refine which bits we need.  Otherwise, use the
8280          conservative form of the mask.  */
8281       if (CONST_INT_P (XEXP (x, 1))
8282           && INTVAL (XEXP (x, 1)) >= 0
8283           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8284           && HWI_COMPUTABLE_MODE_P (op_mode))
8285         mask >>= INTVAL (XEXP (x, 1));
8286       else
8287         mask = fuller_mask;
8288
8289       op0 = gen_lowpart_or_truncate (op_mode,
8290                                      force_to_mode (XEXP (x, 0), op_mode,
8291                                                     mask, next_select));
8292
8293       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8294         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8295       break;
8296
8297     case LSHIFTRT:
8298       /* Here we can only do something if the shift count is a constant,
8299          this shift constant is valid for the host, and we can do arithmetic
8300          in OP_MODE.  */
8301
8302       if (CONST_INT_P (XEXP (x, 1))
8303           && INTVAL (XEXP (x, 1)) >= 0
8304           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8305           && HWI_COMPUTABLE_MODE_P (op_mode))
8306         {
8307           rtx inner = XEXP (x, 0);
8308           unsigned HOST_WIDE_INT inner_mask;
8309
8310           /* Select the mask of the bits we need for the shift operand.  */
8311           inner_mask = mask << INTVAL (XEXP (x, 1));
8312
8313           /* We can only change the mode of the shift if we can do arithmetic
8314              in the mode of the shift and INNER_MASK is no wider than the
8315              width of X's mode.  */
8316           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8317             op_mode = GET_MODE (x);
8318
8319           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8320
8321           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8322             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8323         }
8324
8325       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8326          shift and AND produces only copies of the sign bit (C2 is one less
8327          than a power of two), we can do this with just a shift.  */
8328
8329       if (GET_CODE (x) == LSHIFTRT
8330           && CONST_INT_P (XEXP (x, 1))
8331           /* The shift puts one of the sign bit copies in the least significant
8332              bit.  */
8333           && ((INTVAL (XEXP (x, 1))
8334                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8335               >= GET_MODE_PRECISION (GET_MODE (x)))
8336           && exact_log2 (mask + 1) >= 0
8337           /* Number of bits left after the shift must be more than the mask
8338              needs.  */
8339           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8340               <= GET_MODE_PRECISION (GET_MODE (x)))
8341           /* Must be more sign bit copies than the mask needs.  */
8342           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8343               >= exact_log2 (mask + 1)))
8344         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8345                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8346                                           - exact_log2 (mask + 1)));
8347
8348       goto shiftrt;
8349
8350     case ASHIFTRT:
8351       /* If we are just looking for the sign bit, we don't need this shift at
8352          all, even if it has a variable count.  */
8353       if (val_signbit_p (GET_MODE (x), mask))
8354         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8355
8356       /* If this is a shift by a constant, get a mask that contains those bits
8357          that are not copies of the sign bit.  We then have two cases:  If
8358          MASK only includes those bits, this can be a logical shift, which may
8359          allow simplifications.  If MASK is a single-bit field not within
8360          those bits, we are requesting a copy of the sign bit and hence can
8361          shift the sign bit to the appropriate location.  */
8362
8363       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8364           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8365         {
8366           int i;
8367
8368           /* If the considered data is wider than HOST_WIDE_INT, we can't
8369              represent a mask for all its bits in a single scalar.
8370              But we only care about the lower bits, so calculate these.  */
8371
8372           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8373             {
8374               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8375
8376               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8377                  is the number of bits a full-width mask would have set.
8378                  We need only shift if these are fewer than nonzero can
8379                  hold.  If not, we must keep all bits set in nonzero.  */
8380
8381               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8382                   < HOST_BITS_PER_WIDE_INT)
8383                 nonzero >>= INTVAL (XEXP (x, 1))
8384                             + HOST_BITS_PER_WIDE_INT
8385                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8386             }
8387           else
8388             {
8389               nonzero = GET_MODE_MASK (GET_MODE (x));
8390               nonzero >>= INTVAL (XEXP (x, 1));
8391             }
8392
8393           if ((mask & ~nonzero) == 0)
8394             {
8395               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8396                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8397               if (GET_CODE (x) != ASHIFTRT)
8398                 return force_to_mode (x, mode, mask, next_select);
8399             }
8400
8401           else if ((i = exact_log2 (mask)) >= 0)
8402             {
8403               x = simplify_shift_const
8404                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8405                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8406
8407               if (GET_CODE (x) != ASHIFTRT)
8408                 return force_to_mode (x, mode, mask, next_select);
8409             }
8410         }
8411
8412       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8413          even if the shift count isn't a constant.  */
8414       if (mask == 1)
8415         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8416                                  XEXP (x, 0), XEXP (x, 1));
8417
8418     shiftrt:
8419
8420       /* If this is a zero- or sign-extension operation that just affects bits
8421          we don't care about, remove it.  Be sure the call above returned
8422          something that is still a shift.  */
8423
8424       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8425           && CONST_INT_P (XEXP (x, 1))
8426           && INTVAL (XEXP (x, 1)) >= 0
8427           && (INTVAL (XEXP (x, 1))
8428               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8429           && GET_CODE (XEXP (x, 0)) == ASHIFT
8430           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8431         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8432                               next_select);
8433
8434       break;
8435
8436     case ROTATE:
8437     case ROTATERT:
8438       /* If the shift count is constant and we can do computations
8439          in the mode of X, compute where the bits we care about are.
8440          Otherwise, we can't do anything.  Don't change the mode of
8441          the shift or propagate MODE into the shift, though.  */
8442       if (CONST_INT_P (XEXP (x, 1))
8443           && INTVAL (XEXP (x, 1)) >= 0)
8444         {
8445           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8446                                             GET_MODE (x),
8447                                             gen_int_mode (mask, GET_MODE (x)),
8448                                             XEXP (x, 1));
8449           if (temp && CONST_INT_P (temp))
8450             SUBST (XEXP (x, 0),
8451                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8452                                   INTVAL (temp), next_select));
8453         }
8454       break;
8455
8456     case NEG:
8457       /* If we just want the low-order bit, the NEG isn't needed since it
8458          won't change the low-order bit.  */
8459       if (mask == 1)
8460         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8461
8462       /* We need any bits less significant than the most significant bit in
8463          MASK since carries from those bits will affect the bits we are
8464          interested in.  */
8465       mask = fuller_mask;
8466       goto unop;
8467
8468     case NOT:
8469       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8470          same as the XOR case above.  Ensure that the constant we form is not
8471          wider than the mode of X.  */
8472
8473       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8474           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8475           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8476           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8477               < GET_MODE_PRECISION (GET_MODE (x)))
8478           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8479         {
8480           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8481                                GET_MODE (x));
8482           temp = simplify_gen_binary (XOR, GET_MODE (x),
8483                                       XEXP (XEXP (x, 0), 0), temp);
8484           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8485                                    temp, XEXP (XEXP (x, 0), 1));
8486
8487           return force_to_mode (x, mode, mask, next_select);
8488         }
8489
8490       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8491          use the full mask inside the NOT.  */
8492       mask = fuller_mask;
8493
8494     unop:
8495       op0 = gen_lowpart_or_truncate (op_mode,
8496                                      force_to_mode (XEXP (x, 0), mode, mask,
8497                                                     next_select));
8498       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8499         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8500       break;
8501
8502     case NE:
8503       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8504          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8505          which is equal to STORE_FLAG_VALUE.  */
8506       if ((mask & ~STORE_FLAG_VALUE) == 0
8507           && XEXP (x, 1) == const0_rtx
8508           && GET_MODE (XEXP (x, 0)) == mode
8509           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8510           && (nonzero_bits (XEXP (x, 0), mode)
8511               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8512         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8513
8514       break;
8515
8516     case IF_THEN_ELSE:
8517       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8518          written in a narrower mode.  We play it safe and do not do so.  */
8519
8520       SUBST (XEXP (x, 1),
8521              gen_lowpart_or_truncate (GET_MODE (x),
8522                                       force_to_mode (XEXP (x, 1), mode,
8523                                                      mask, next_select)));
8524       SUBST (XEXP (x, 2),
8525              gen_lowpart_or_truncate (GET_MODE (x),
8526                                       force_to_mode (XEXP (x, 2), mode,
8527                                                      mask, next_select)));
8528       break;
8529
8530     default:
8531       break;
8532     }
8533
8534   /* Ensure we return a value of the proper mode.  */
8535   return gen_lowpart_or_truncate (mode, x);
8536 }
8537 \f
8538 /* Return nonzero if X is an expression that has one of two values depending on
8539    whether some other value is zero or nonzero.  In that case, we return the
8540    value that is being tested, *PTRUE is set to the value if the rtx being
8541    returned has a nonzero value, and *PFALSE is set to the other alternative.
8542
8543    If we return zero, we set *PTRUE and *PFALSE to X.  */
8544
8545 static rtx
8546 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8547 {
8548   enum machine_mode mode = GET_MODE (x);
8549   enum rtx_code code = GET_CODE (x);
8550   rtx cond0, cond1, true0, true1, false0, false1;
8551   unsigned HOST_WIDE_INT nz;
8552
8553   /* If we are comparing a value against zero, we are done.  */
8554   if ((code == NE || code == EQ)
8555       && XEXP (x, 1) == const0_rtx)
8556     {
8557       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8558       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8559       return XEXP (x, 0);
8560     }
8561
8562   /* If this is a unary operation whose operand has one of two values, apply
8563      our opcode to compute those values.  */
8564   else if (UNARY_P (x)
8565            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8566     {
8567       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8568       *pfalse = simplify_gen_unary (code, mode, false0,
8569                                     GET_MODE (XEXP (x, 0)));
8570       return cond0;
8571     }
8572
8573   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8574      make can't possibly match and would suppress other optimizations.  */
8575   else if (code == COMPARE)
8576     ;
8577
8578   /* If this is a binary operation, see if either side has only one of two
8579      values.  If either one does or if both do and they are conditional on
8580      the same value, compute the new true and false values.  */
8581   else if (BINARY_P (x))
8582     {
8583       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8584       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8585
8586       if ((cond0 != 0 || cond1 != 0)
8587           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8588         {
8589           /* If if_then_else_cond returned zero, then true/false are the
8590              same rtl.  We must copy one of them to prevent invalid rtl
8591              sharing.  */
8592           if (cond0 == 0)
8593             true0 = copy_rtx (true0);
8594           else if (cond1 == 0)
8595             true1 = copy_rtx (true1);
8596
8597           if (COMPARISON_P (x))
8598             {
8599               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8600                                                 true0, true1);
8601               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8602                                                  false0, false1);
8603              }
8604           else
8605             {
8606               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8607               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8608             }
8609
8610           return cond0 ? cond0 : cond1;
8611         }
8612
8613       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8614          operands is zero when the other is nonzero, and vice-versa,
8615          and STORE_FLAG_VALUE is 1 or -1.  */
8616
8617       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8618           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8619               || code == UMAX)
8620           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8621         {
8622           rtx op0 = XEXP (XEXP (x, 0), 1);
8623           rtx op1 = XEXP (XEXP (x, 1), 1);
8624
8625           cond0 = XEXP (XEXP (x, 0), 0);
8626           cond1 = XEXP (XEXP (x, 1), 0);
8627
8628           if (COMPARISON_P (cond0)
8629               && COMPARISON_P (cond1)
8630               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8631                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8632                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8633                   || ((swap_condition (GET_CODE (cond0))
8634                        == reversed_comparison_code (cond1, NULL))
8635                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8636                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8637               && ! side_effects_p (x))
8638             {
8639               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8640               *pfalse = simplify_gen_binary (MULT, mode,
8641                                              (code == MINUS
8642                                               ? simplify_gen_unary (NEG, mode,
8643                                                                     op1, mode)
8644                                               : op1),
8645                                               const_true_rtx);
8646               return cond0;
8647             }
8648         }
8649
8650       /* Similarly for MULT, AND and UMIN, except that for these the result
8651          is always zero.  */
8652       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8653           && (code == MULT || code == AND || code == UMIN)
8654           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8655         {
8656           cond0 = XEXP (XEXP (x, 0), 0);
8657           cond1 = XEXP (XEXP (x, 1), 0);
8658
8659           if (COMPARISON_P (cond0)
8660               && COMPARISON_P (cond1)
8661               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8662                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8663                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8664                   || ((swap_condition (GET_CODE (cond0))
8665                        == reversed_comparison_code (cond1, NULL))
8666                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8667                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8668               && ! side_effects_p (x))
8669             {
8670               *ptrue = *pfalse = const0_rtx;
8671               return cond0;
8672             }
8673         }
8674     }
8675
8676   else if (code == IF_THEN_ELSE)
8677     {
8678       /* If we have IF_THEN_ELSE already, extract the condition and
8679          canonicalize it if it is NE or EQ.  */
8680       cond0 = XEXP (x, 0);
8681       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8682       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8683         return XEXP (cond0, 0);
8684       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8685         {
8686           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8687           return XEXP (cond0, 0);
8688         }
8689       else
8690         return cond0;
8691     }
8692
8693   /* If X is a SUBREG, we can narrow both the true and false values
8694      if the inner expression, if there is a condition.  */
8695   else if (code == SUBREG
8696            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8697                                                &true0, &false0)))
8698     {
8699       true0 = simplify_gen_subreg (mode, true0,
8700                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8701       false0 = simplify_gen_subreg (mode, false0,
8702                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8703       if (true0 && false0)
8704         {
8705           *ptrue = true0;
8706           *pfalse = false0;
8707           return cond0;
8708         }
8709     }
8710
8711   /* If X is a constant, this isn't special and will cause confusions
8712      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8713   else if (CONSTANT_P (x)
8714            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8715     ;
8716
8717   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8718      will be least confusing to the rest of the compiler.  */
8719   else if (mode == BImode)
8720     {
8721       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8722       return x;
8723     }
8724
8725   /* If X is known to be either 0 or -1, those are the true and
8726      false values when testing X.  */
8727   else if (x == constm1_rtx || x == const0_rtx
8728            || (mode != VOIDmode
8729                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8730     {
8731       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8732       return x;
8733     }
8734
8735   /* Likewise for 0 or a single bit.  */
8736   else if (HWI_COMPUTABLE_MODE_P (mode)
8737            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8738     {
8739       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8740       return x;
8741     }
8742
8743   /* Otherwise fail; show no condition with true and false values the same.  */
8744   *ptrue = *pfalse = x;
8745   return 0;
8746 }
8747 \f
8748 /* Return the value of expression X given the fact that condition COND
8749    is known to be true when applied to REG as its first operand and VAL
8750    as its second.  X is known to not be shared and so can be modified in
8751    place.
8752
8753    We only handle the simplest cases, and specifically those cases that
8754    arise with IF_THEN_ELSE expressions.  */
8755
8756 static rtx
8757 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8758 {
8759   enum rtx_code code = GET_CODE (x);
8760   rtx temp;
8761   const char *fmt;
8762   int i, j;
8763
8764   if (side_effects_p (x))
8765     return x;
8766
8767   /* If either operand of the condition is a floating point value,
8768      then we have to avoid collapsing an EQ comparison.  */
8769   if (cond == EQ
8770       && rtx_equal_p (x, reg)
8771       && ! FLOAT_MODE_P (GET_MODE (x))
8772       && ! FLOAT_MODE_P (GET_MODE (val)))
8773     return val;
8774
8775   if (cond == UNEQ && rtx_equal_p (x, reg))
8776     return val;
8777
8778   /* If X is (abs REG) and we know something about REG's relationship
8779      with zero, we may be able to simplify this.  */
8780
8781   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8782     switch (cond)
8783       {
8784       case GE:  case GT:  case EQ:
8785         return XEXP (x, 0);
8786       case LT:  case LE:
8787         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8788                                    XEXP (x, 0),
8789                                    GET_MODE (XEXP (x, 0)));
8790       default:
8791         break;
8792       }
8793
8794   /* The only other cases we handle are MIN, MAX, and comparisons if the
8795      operands are the same as REG and VAL.  */
8796
8797   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8798     {
8799       if (rtx_equal_p (XEXP (x, 0), val))
8800         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8801
8802       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8803         {
8804           if (COMPARISON_P (x))
8805             {
8806               if (comparison_dominates_p (cond, code))
8807                 return const_true_rtx;
8808
8809               code = reversed_comparison_code (x, NULL);
8810               if (code != UNKNOWN
8811                   && comparison_dominates_p (cond, code))
8812                 return const0_rtx;
8813               else
8814                 return x;
8815             }
8816           else if (code == SMAX || code == SMIN
8817                    || code == UMIN || code == UMAX)
8818             {
8819               int unsignedp = (code == UMIN || code == UMAX);
8820
8821               /* Do not reverse the condition when it is NE or EQ.
8822                  This is because we cannot conclude anything about
8823                  the value of 'SMAX (x, y)' when x is not equal to y,
8824                  but we can when x equals y.  */
8825               if ((code == SMAX || code == UMAX)
8826                   && ! (cond == EQ || cond == NE))
8827                 cond = reverse_condition (cond);
8828
8829               switch (cond)
8830                 {
8831                 case GE:   case GT:
8832                   return unsignedp ? x : XEXP (x, 1);
8833                 case LE:   case LT:
8834                   return unsignedp ? x : XEXP (x, 0);
8835                 case GEU:  case GTU:
8836                   return unsignedp ? XEXP (x, 1) : x;
8837                 case LEU:  case LTU:
8838                   return unsignedp ? XEXP (x, 0) : x;
8839                 default:
8840                   break;
8841                 }
8842             }
8843         }
8844     }
8845   else if (code == SUBREG)
8846     {
8847       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8848       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8849
8850       if (SUBREG_REG (x) != r)
8851         {
8852           /* We must simplify subreg here, before we lose track of the
8853              original inner_mode.  */
8854           new_rtx = simplify_subreg (GET_MODE (x), r,
8855                                  inner_mode, SUBREG_BYTE (x));
8856           if (new_rtx)
8857             return new_rtx;
8858           else
8859             SUBST (SUBREG_REG (x), r);
8860         }
8861
8862       return x;
8863     }
8864   /* We don't have to handle SIGN_EXTEND here, because even in the
8865      case of replacing something with a modeless CONST_INT, a
8866      CONST_INT is already (supposed to be) a valid sign extension for
8867      its narrower mode, which implies it's already properly
8868      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8869      story is different.  */
8870   else if (code == ZERO_EXTEND)
8871     {
8872       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8873       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8874
8875       if (XEXP (x, 0) != r)
8876         {
8877           /* We must simplify the zero_extend here, before we lose
8878              track of the original inner_mode.  */
8879           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8880                                           r, inner_mode);
8881           if (new_rtx)
8882             return new_rtx;
8883           else
8884             SUBST (XEXP (x, 0), r);
8885         }
8886
8887       return x;
8888     }
8889
8890   fmt = GET_RTX_FORMAT (code);
8891   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8892     {
8893       if (fmt[i] == 'e')
8894         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8895       else if (fmt[i] == 'E')
8896         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8897           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8898                                                 cond, reg, val));
8899     }
8900
8901   return x;
8902 }
8903 \f
8904 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8905    assignment as a field assignment.  */
8906
8907 static int
8908 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8909 {
8910   if (x == y || rtx_equal_p (x, y))
8911     return 1;
8912
8913   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8914     return 0;
8915
8916   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8917      Note that all SUBREGs of MEM are paradoxical; otherwise they
8918      would have been rewritten.  */
8919   if (MEM_P (x) && GET_CODE (y) == SUBREG
8920       && MEM_P (SUBREG_REG (y))
8921       && rtx_equal_p (SUBREG_REG (y),
8922                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8923     return 1;
8924
8925   if (MEM_P (y) && GET_CODE (x) == SUBREG
8926       && MEM_P (SUBREG_REG (x))
8927       && rtx_equal_p (SUBREG_REG (x),
8928                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8929     return 1;
8930
8931   /* We used to see if get_last_value of X and Y were the same but that's
8932      not correct.  In one direction, we'll cause the assignment to have
8933      the wrong destination and in the case, we'll import a register into this
8934      insn that might have already have been dead.   So fail if none of the
8935      above cases are true.  */
8936   return 0;
8937 }
8938 \f
8939 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8940    Return that assignment if so.
8941
8942    We only handle the most common cases.  */
8943
8944 static rtx
8945 make_field_assignment (rtx x)
8946 {
8947   rtx dest = SET_DEST (x);
8948   rtx src = SET_SRC (x);
8949   rtx assign;
8950   rtx rhs, lhs;
8951   HOST_WIDE_INT c1;
8952   HOST_WIDE_INT pos;
8953   unsigned HOST_WIDE_INT len;
8954   rtx other;
8955   enum machine_mode mode;
8956
8957   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8958      a clear of a one-bit field.  We will have changed it to
8959      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8960      for a SUBREG.  */
8961
8962   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8963       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8964       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8965       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8966     {
8967       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8968                                 1, 1, 1, 0);
8969       if (assign != 0)
8970         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8971       return x;
8972     }
8973
8974   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8975       && subreg_lowpart_p (XEXP (src, 0))
8976       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8977           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8978       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8979       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8980       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8981       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8982     {
8983       assign = make_extraction (VOIDmode, dest, 0,
8984                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8985                                 1, 1, 1, 0);
8986       if (assign != 0)
8987         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8988       return x;
8989     }
8990
8991   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8992      one-bit field.  */
8993   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8994       && XEXP (XEXP (src, 0), 0) == const1_rtx
8995       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8996     {
8997       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8998                                 1, 1, 1, 0);
8999       if (assign != 0)
9000         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9001       return x;
9002     }
9003
9004   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9005      SRC is an AND with all bits of that field set, then we can discard
9006      the AND.  */
9007   if (GET_CODE (dest) == ZERO_EXTRACT
9008       && CONST_INT_P (XEXP (dest, 1))
9009       && GET_CODE (src) == AND
9010       && CONST_INT_P (XEXP (src, 1)))
9011     {
9012       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9013       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9014       unsigned HOST_WIDE_INT ze_mask;
9015
9016       if (width >= HOST_BITS_PER_WIDE_INT)
9017         ze_mask = -1;
9018       else
9019         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9020
9021       /* Complete overlap.  We can remove the source AND.  */
9022       if ((and_mask & ze_mask) == ze_mask)
9023         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9024
9025       /* Partial overlap.  We can reduce the source AND.  */
9026       if ((and_mask & ze_mask) != and_mask)
9027         {
9028           mode = GET_MODE (src);
9029           src = gen_rtx_AND (mode, XEXP (src, 0),
9030                              gen_int_mode (and_mask & ze_mask, mode));
9031           return gen_rtx_SET (VOIDmode, dest, src);
9032         }
9033     }
9034
9035   /* The other case we handle is assignments into a constant-position
9036      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9037      a mask that has all one bits except for a group of zero bits and
9038      OTHER is known to have zeros where C1 has ones, this is such an
9039      assignment.  Compute the position and length from C1.  Shift OTHER
9040      to the appropriate position, force it to the required mode, and
9041      make the extraction.  Check for the AND in both operands.  */
9042
9043   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9044     return x;
9045
9046   rhs = expand_compound_operation (XEXP (src, 0));
9047   lhs = expand_compound_operation (XEXP (src, 1));
9048
9049   if (GET_CODE (rhs) == AND
9050       && CONST_INT_P (XEXP (rhs, 1))
9051       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9052     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9053   else if (GET_CODE (lhs) == AND
9054            && CONST_INT_P (XEXP (lhs, 1))
9055            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9056     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9057   else
9058     return x;
9059
9060   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9061   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9062       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9063       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9064     return x;
9065
9066   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9067   if (assign == 0)
9068     return x;
9069
9070   /* The mode to use for the source is the mode of the assignment, or of
9071      what is inside a possible STRICT_LOW_PART.  */
9072   mode = (GET_CODE (assign) == STRICT_LOW_PART
9073           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9074
9075   /* Shift OTHER right POS places and make it the source, restricting it
9076      to the proper length and mode.  */
9077
9078   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9079                                                      GET_MODE (src),
9080                                                      other, pos),
9081                                dest);
9082   src = force_to_mode (src, mode,
9083                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9084                        ? ~(unsigned HOST_WIDE_INT) 0
9085                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9086                        0);
9087
9088   /* If SRC is masked by an AND that does not make a difference in
9089      the value being stored, strip it.  */
9090   if (GET_CODE (assign) == ZERO_EXTRACT
9091       && CONST_INT_P (XEXP (assign, 1))
9092       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9093       && GET_CODE (src) == AND
9094       && CONST_INT_P (XEXP (src, 1))
9095       && UINTVAL (XEXP (src, 1))
9096          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9097     src = XEXP (src, 0);
9098
9099   return gen_rtx_SET (VOIDmode, assign, src);
9100 }
9101 \f
9102 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9103    if so.  */
9104
9105 static rtx
9106 apply_distributive_law (rtx x)
9107 {
9108   enum rtx_code code = GET_CODE (x);
9109   enum rtx_code inner_code;
9110   rtx lhs, rhs, other;
9111   rtx tem;
9112
9113   /* Distributivity is not true for floating point as it can change the
9114      value.  So we don't do it unless -funsafe-math-optimizations.  */
9115   if (FLOAT_MODE_P (GET_MODE (x))
9116       && ! flag_unsafe_math_optimizations)
9117     return x;
9118
9119   /* The outer operation can only be one of the following:  */
9120   if (code != IOR && code != AND && code != XOR
9121       && code != PLUS && code != MINUS)
9122     return x;
9123
9124   lhs = XEXP (x, 0);
9125   rhs = XEXP (x, 1);
9126
9127   /* If either operand is a primitive we can't do anything, so get out
9128      fast.  */
9129   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9130     return x;
9131
9132   lhs = expand_compound_operation (lhs);
9133   rhs = expand_compound_operation (rhs);
9134   inner_code = GET_CODE (lhs);
9135   if (inner_code != GET_CODE (rhs))
9136     return x;
9137
9138   /* See if the inner and outer operations distribute.  */
9139   switch (inner_code)
9140     {
9141     case LSHIFTRT:
9142     case ASHIFTRT:
9143     case AND:
9144     case IOR:
9145       /* These all distribute except over PLUS.  */
9146       if (code == PLUS || code == MINUS)
9147         return x;
9148       break;
9149
9150     case MULT:
9151       if (code != PLUS && code != MINUS)
9152         return x;
9153       break;
9154
9155     case ASHIFT:
9156       /* This is also a multiply, so it distributes over everything.  */
9157       break;
9158
9159     /* This used to handle SUBREG, but this turned out to be counter-
9160        productive, since (subreg (op ...)) usually is not handled by
9161        insn patterns, and this "optimization" therefore transformed
9162        recognizable patterns into unrecognizable ones.  Therefore the
9163        SUBREG case was removed from here.
9164
9165        It is possible that distributing SUBREG over arithmetic operations
9166        leads to an intermediate result than can then be optimized further,
9167        e.g. by moving the outer SUBREG to the other side of a SET as done
9168        in simplify_set.  This seems to have been the original intent of
9169        handling SUBREGs here.
9170
9171        However, with current GCC this does not appear to actually happen,
9172        at least on major platforms.  If some case is found where removing
9173        the SUBREG case here prevents follow-on optimizations, distributing
9174        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9175
9176     default:
9177       return x;
9178     }
9179
9180   /* Set LHS and RHS to the inner operands (A and B in the example
9181      above) and set OTHER to the common operand (C in the example).
9182      There is only one way to do this unless the inner operation is
9183      commutative.  */
9184   if (COMMUTATIVE_ARITH_P (lhs)
9185       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9186     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9187   else if (COMMUTATIVE_ARITH_P (lhs)
9188            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9189     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9190   else if (COMMUTATIVE_ARITH_P (lhs)
9191            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9192     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9193   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9194     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9195   else
9196     return x;
9197
9198   /* Form the new inner operation, seeing if it simplifies first.  */
9199   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9200
9201   /* There is one exception to the general way of distributing:
9202      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9203   if (code == XOR && inner_code == IOR)
9204     {
9205       inner_code = AND;
9206       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9207     }
9208
9209   /* We may be able to continuing distributing the result, so call
9210      ourselves recursively on the inner operation before forming the
9211      outer operation, which we return.  */
9212   return simplify_gen_binary (inner_code, GET_MODE (x),
9213                               apply_distributive_law (tem), other);
9214 }
9215
9216 /* See if X is of the form (* (+ A B) C), and if so convert to
9217    (+ (* A C) (* B C)) and try to simplify.
9218
9219    Most of the time, this results in no change.  However, if some of
9220    the operands are the same or inverses of each other, simplifications
9221    will result.
9222
9223    For example, (and (ior A B) (not B)) can occur as the result of
9224    expanding a bit field assignment.  When we apply the distributive
9225    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9226    which then simplifies to (and (A (not B))).
9227
9228    Note that no checks happen on the validity of applying the inverse
9229    distributive law.  This is pointless since we can do it in the
9230    few places where this routine is called.
9231
9232    N is the index of the term that is decomposed (the arithmetic operation,
9233    i.e. (+ A B) in the first example above).  !N is the index of the term that
9234    is distributed, i.e. of C in the first example above.  */
9235 static rtx
9236 distribute_and_simplify_rtx (rtx x, int n)
9237 {
9238   enum machine_mode mode;
9239   enum rtx_code outer_code, inner_code;
9240   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9241
9242   /* Distributivity is not true for floating point as it can change the
9243      value.  So we don't do it unless -funsafe-math-optimizations.  */
9244   if (FLOAT_MODE_P (GET_MODE (x))
9245       && ! flag_unsafe_math_optimizations)
9246     return NULL_RTX;
9247
9248   decomposed = XEXP (x, n);
9249   if (!ARITHMETIC_P (decomposed))
9250     return NULL_RTX;
9251
9252   mode = GET_MODE (x);
9253   outer_code = GET_CODE (x);
9254   distributed = XEXP (x, !n);
9255
9256   inner_code = GET_CODE (decomposed);
9257   inner_op0 = XEXP (decomposed, 0);
9258   inner_op1 = XEXP (decomposed, 1);
9259
9260   /* Special case (and (xor B C) (not A)), which is equivalent to
9261      (xor (ior A B) (ior A C))  */
9262   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9263     {
9264       distributed = XEXP (distributed, 0);
9265       outer_code = IOR;
9266     }
9267
9268   if (n == 0)
9269     {
9270       /* Distribute the second term.  */
9271       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9272       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9273     }
9274   else
9275     {
9276       /* Distribute the first term.  */
9277       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9278       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9279     }
9280
9281   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9282                                                      new_op0, new_op1));
9283   if (GET_CODE (tmp) != outer_code
9284       && (set_src_cost (tmp, optimize_this_for_speed_p)
9285           < set_src_cost (x, optimize_this_for_speed_p)))
9286     return tmp;
9287
9288   return NULL_RTX;
9289 }
9290 \f
9291 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9292    in MODE.  Return an equivalent form, if different from (and VAROP
9293    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9294
9295 static rtx
9296 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9297                           unsigned HOST_WIDE_INT constop)
9298 {
9299   unsigned HOST_WIDE_INT nonzero;
9300   unsigned HOST_WIDE_INT orig_constop;
9301   rtx orig_varop;
9302   int i;
9303
9304   orig_varop = varop;
9305   orig_constop = constop;
9306   if (GET_CODE (varop) == CLOBBER)
9307     return NULL_RTX;
9308
9309   /* Simplify VAROP knowing that we will be only looking at some of the
9310      bits in it.
9311
9312      Note by passing in CONSTOP, we guarantee that the bits not set in
9313      CONSTOP are not significant and will never be examined.  We must
9314      ensure that is the case by explicitly masking out those bits
9315      before returning.  */
9316   varop = force_to_mode (varop, mode, constop, 0);
9317
9318   /* If VAROP is a CLOBBER, we will fail so return it.  */
9319   if (GET_CODE (varop) == CLOBBER)
9320     return varop;
9321
9322   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9323      to VAROP and return the new constant.  */
9324   if (CONST_INT_P (varop))
9325     return gen_int_mode (INTVAL (varop) & constop, mode);
9326
9327   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9328      a call to nonzero_bits, here we don't care about bits outside
9329      MODE.  */
9330
9331   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9332
9333   /* Turn off all bits in the constant that are known to already be zero.
9334      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9335      which is tested below.  */
9336
9337   constop &= nonzero;
9338
9339   /* If we don't have any bits left, return zero.  */
9340   if (constop == 0)
9341     return const0_rtx;
9342
9343   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9344      a power of two, we can replace this with an ASHIFT.  */
9345   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9346       && (i = exact_log2 (constop)) >= 0)
9347     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9348
9349   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9350      or XOR, then try to apply the distributive law.  This may eliminate
9351      operations if either branch can be simplified because of the AND.
9352      It may also make some cases more complex, but those cases probably
9353      won't match a pattern either with or without this.  */
9354
9355   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9356     return
9357       gen_lowpart
9358         (mode,
9359          apply_distributive_law
9360          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9361                                simplify_and_const_int (NULL_RTX,
9362                                                        GET_MODE (varop),
9363                                                        XEXP (varop, 0),
9364                                                        constop),
9365                                simplify_and_const_int (NULL_RTX,
9366                                                        GET_MODE (varop),
9367                                                        XEXP (varop, 1),
9368                                                        constop))));
9369
9370   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9371      the AND and see if one of the operands simplifies to zero.  If so, we
9372      may eliminate it.  */
9373
9374   if (GET_CODE (varop) == PLUS
9375       && exact_log2 (constop + 1) >= 0)
9376     {
9377       rtx o0, o1;
9378
9379       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9380       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9381       if (o0 == const0_rtx)
9382         return o1;
9383       if (o1 == const0_rtx)
9384         return o0;
9385     }
9386
9387   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9388   varop = gen_lowpart (mode, varop);
9389   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9390     return NULL_RTX;
9391
9392   /* If we are only masking insignificant bits, return VAROP.  */
9393   if (constop == nonzero)
9394     return varop;
9395
9396   if (varop == orig_varop && constop == orig_constop)
9397     return NULL_RTX;
9398
9399   /* Otherwise, return an AND.  */
9400   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9401 }
9402
9403
9404 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9405    in MODE.
9406
9407    Return an equivalent form, if different from X.  Otherwise, return X.  If
9408    X is zero, we are to always construct the equivalent form.  */
9409
9410 static rtx
9411 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9412                         unsigned HOST_WIDE_INT constop)
9413 {
9414   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9415   if (tem)
9416     return tem;
9417
9418   if (!x)
9419     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9420                              gen_int_mode (constop, mode));
9421   if (GET_MODE (x) != mode)
9422     x = gen_lowpart (mode, x);
9423   return x;
9424 }
9425 \f
9426 /* Given a REG, X, compute which bits in X can be nonzero.
9427    We don't care about bits outside of those defined in MODE.
9428
9429    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9430    a shift, AND, or zero_extract, we can do better.  */
9431
9432 static rtx
9433 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9434                               const_rtx known_x ATTRIBUTE_UNUSED,
9435                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9436                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9437                               unsigned HOST_WIDE_INT *nonzero)
9438 {
9439   rtx tem;
9440   reg_stat_type *rsp;
9441
9442   /* If X is a register whose nonzero bits value is current, use it.
9443      Otherwise, if X is a register whose value we can find, use that
9444      value.  Otherwise, use the previously-computed global nonzero bits
9445      for this register.  */
9446
9447   rsp = &reg_stat[REGNO (x)];
9448   if (rsp->last_set_value != 0
9449       && (rsp->last_set_mode == mode
9450           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9451               && GET_MODE_CLASS (mode) == MODE_INT))
9452       && ((rsp->last_set_label >= label_tick_ebb_start
9453            && rsp->last_set_label < label_tick)
9454           || (rsp->last_set_label == label_tick
9455               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9456           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9457               && REG_N_SETS (REGNO (x)) == 1
9458               && !REGNO_REG_SET_P
9459                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9460     {
9461       *nonzero &= rsp->last_set_nonzero_bits;
9462       return NULL;
9463     }
9464
9465   tem = get_last_value (x);
9466
9467   if (tem)
9468     {
9469 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9470       /* If X is narrower than MODE and TEM is a non-negative
9471          constant that would appear negative in the mode of X,
9472          sign-extend it for use in reg_nonzero_bits because some
9473          machines (maybe most) will actually do the sign-extension
9474          and this is the conservative approach.
9475
9476          ??? For 2.5, try to tighten up the MD files in this regard
9477          instead of this kludge.  */
9478
9479       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9480           && CONST_INT_P (tem)
9481           && INTVAL (tem) > 0
9482           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9483         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9484 #endif
9485       return tem;
9486     }
9487   else if (nonzero_sign_valid && rsp->nonzero_bits)
9488     {
9489       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9490
9491       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9492         /* We don't know anything about the upper bits.  */
9493         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9494       *nonzero &= mask;
9495     }
9496
9497   return NULL;
9498 }
9499
9500 /* Return the number of bits at the high-order end of X that are known to
9501    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9502    VOIDmode, X will be used in its own mode.  The returned value  will always
9503    be between 1 and the number of bits in MODE.  */
9504
9505 static rtx
9506 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9507                                      const_rtx known_x ATTRIBUTE_UNUSED,
9508                                      enum machine_mode known_mode
9509                                      ATTRIBUTE_UNUSED,
9510                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9511                                      unsigned int *result)
9512 {
9513   rtx tem;
9514   reg_stat_type *rsp;
9515
9516   rsp = &reg_stat[REGNO (x)];
9517   if (rsp->last_set_value != 0
9518       && rsp->last_set_mode == mode
9519       && ((rsp->last_set_label >= label_tick_ebb_start
9520            && rsp->last_set_label < label_tick)
9521           || (rsp->last_set_label == label_tick
9522               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9523           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9524               && REG_N_SETS (REGNO (x)) == 1
9525               && !REGNO_REG_SET_P
9526                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9527     {
9528       *result = rsp->last_set_sign_bit_copies;
9529       return NULL;
9530     }
9531
9532   tem = get_last_value (x);
9533   if (tem != 0)
9534     return tem;
9535
9536   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9537       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9538     *result = rsp->sign_bit_copies;
9539
9540   return NULL;
9541 }
9542 \f
9543 /* Return the number of "extended" bits there are in X, when interpreted
9544    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9545    unsigned quantities, this is the number of high-order zero bits.
9546    For signed quantities, this is the number of copies of the sign bit
9547    minus 1.  In both case, this function returns the number of "spare"
9548    bits.  For example, if two quantities for which this function returns
9549    at least 1 are added, the addition is known not to overflow.
9550
9551    This function will always return 0 unless called during combine, which
9552    implies that it must be called from a define_split.  */
9553
9554 unsigned int
9555 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9556 {
9557   if (nonzero_sign_valid == 0)
9558     return 0;
9559
9560   return (unsignedp
9561           ? (HWI_COMPUTABLE_MODE_P (mode)
9562              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9563                                - floor_log2 (nonzero_bits (x, mode)))
9564              : 0)
9565           : num_sign_bit_copies (x, mode) - 1);
9566 }
9567
9568 /* This function is called from `simplify_shift_const' to merge two
9569    outer operations.  Specifically, we have already found that we need
9570    to perform operation *POP0 with constant *PCONST0 at the outermost
9571    position.  We would now like to also perform OP1 with constant CONST1
9572    (with *POP0 being done last).
9573
9574    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9575    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9576    complement the innermost operand, otherwise it is unchanged.
9577
9578    MODE is the mode in which the operation will be done.  No bits outside
9579    the width of this mode matter.  It is assumed that the width of this mode
9580    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9581
9582    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9583    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9584    result is simply *PCONST0.
9585
9586    If the resulting operation cannot be expressed as one operation, we
9587    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9588
9589 static int
9590 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9591 {
9592   enum rtx_code op0 = *pop0;
9593   HOST_WIDE_INT const0 = *pconst0;
9594
9595   const0 &= GET_MODE_MASK (mode);
9596   const1 &= GET_MODE_MASK (mode);
9597
9598   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9599   if (op0 == AND)
9600     const1 &= const0;
9601
9602   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9603      if OP0 is SET.  */
9604
9605   if (op1 == UNKNOWN || op0 == SET)
9606     return 1;
9607
9608   else if (op0 == UNKNOWN)
9609     op0 = op1, const0 = const1;
9610
9611   else if (op0 == op1)
9612     {
9613       switch (op0)
9614         {
9615         case AND:
9616           const0 &= const1;
9617           break;
9618         case IOR:
9619           const0 |= const1;
9620           break;
9621         case XOR:
9622           const0 ^= const1;
9623           break;
9624         case PLUS:
9625           const0 += const1;
9626           break;
9627         case NEG:
9628           op0 = UNKNOWN;
9629           break;
9630         default:
9631           break;
9632         }
9633     }
9634
9635   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9636   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9637     return 0;
9638
9639   /* If the two constants aren't the same, we can't do anything.  The
9640      remaining six cases can all be done.  */
9641   else if (const0 != const1)
9642     return 0;
9643
9644   else
9645     switch (op0)
9646       {
9647       case IOR:
9648         if (op1 == AND)
9649           /* (a & b) | b == b */
9650           op0 = SET;
9651         else /* op1 == XOR */
9652           /* (a ^ b) | b == a | b */
9653           {;}
9654         break;
9655
9656       case XOR:
9657         if (op1 == AND)
9658           /* (a & b) ^ b == (~a) & b */
9659           op0 = AND, *pcomp_p = 1;
9660         else /* op1 == IOR */
9661           /* (a | b) ^ b == a & ~b */
9662           op0 = AND, const0 = ~const0;
9663         break;
9664
9665       case AND:
9666         if (op1 == IOR)
9667           /* (a | b) & b == b */
9668         op0 = SET;
9669         else /* op1 == XOR */
9670           /* (a ^ b) & b) == (~a) & b */
9671           *pcomp_p = 1;
9672         break;
9673       default:
9674         break;
9675       }
9676
9677   /* Check for NO-OP cases.  */
9678   const0 &= GET_MODE_MASK (mode);
9679   if (const0 == 0
9680       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9681     op0 = UNKNOWN;
9682   else if (const0 == 0 && op0 == AND)
9683     op0 = SET;
9684   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9685            && op0 == AND)
9686     op0 = UNKNOWN;
9687
9688   *pop0 = op0;
9689
9690   /* ??? Slightly redundant with the above mask, but not entirely.
9691      Moving this above means we'd have to sign-extend the mode mask
9692      for the final test.  */
9693   if (op0 != UNKNOWN && op0 != NEG)
9694     *pconst0 = trunc_int_for_mode (const0, mode);
9695
9696   return 1;
9697 }
9698 \f
9699 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9700    the shift in.  The original shift operation CODE is performed on OP in
9701    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9702    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9703    result of the shift is subject to operation OUTER_CODE with operand
9704    OUTER_CONST.  */
9705
9706 static enum machine_mode
9707 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9708                       enum machine_mode orig_mode, enum machine_mode mode,
9709                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9710 {
9711   if (orig_mode == mode)
9712     return mode;
9713   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9714
9715   /* In general we can't perform in wider mode for right shift and rotate.  */
9716   switch (code)
9717     {
9718     case ASHIFTRT:
9719       /* We can still widen if the bits brought in from the left are identical
9720          to the sign bit of ORIG_MODE.  */
9721       if (num_sign_bit_copies (op, mode)
9722           > (unsigned) (GET_MODE_PRECISION (mode)
9723                         - GET_MODE_PRECISION (orig_mode)))
9724         return mode;
9725       return orig_mode;
9726
9727     case LSHIFTRT:
9728       /* Similarly here but with zero bits.  */
9729       if (HWI_COMPUTABLE_MODE_P (mode)
9730           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9731         return mode;
9732
9733       /* We can also widen if the bits brought in will be masked off.  This
9734          operation is performed in ORIG_MODE.  */
9735       if (outer_code == AND)
9736         {
9737           int care_bits = low_bitmask_len (orig_mode, outer_const);
9738
9739           if (care_bits >= 0
9740               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9741             return mode;
9742         }
9743       /* fall through */
9744
9745     case ROTATE:
9746       return orig_mode;
9747
9748     case ROTATERT:
9749       gcc_unreachable ();
9750
9751     default:
9752       return mode;
9753     }
9754 }
9755
9756 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9757    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9758    if we cannot simplify it.  Otherwise, return a simplified value.
9759
9760    The shift is normally computed in the widest mode we find in VAROP, as
9761    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9762    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9763
9764 static rtx
9765 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9766                         rtx varop, int orig_count)
9767 {
9768   enum rtx_code orig_code = code;
9769   rtx orig_varop = varop;
9770   int count;
9771   enum machine_mode mode = result_mode;
9772   enum machine_mode shift_mode, tmode;
9773   unsigned int mode_words
9774     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9775   /* We form (outer_op (code varop count) (outer_const)).  */
9776   enum rtx_code outer_op = UNKNOWN;
9777   HOST_WIDE_INT outer_const = 0;
9778   int complement_p = 0;
9779   rtx new_rtx, x;
9780
9781   /* Make sure and truncate the "natural" shift on the way in.  We don't
9782      want to do this inside the loop as it makes it more difficult to
9783      combine shifts.  */
9784   if (SHIFT_COUNT_TRUNCATED)
9785     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9786
9787   /* If we were given an invalid count, don't do anything except exactly
9788      what was requested.  */
9789
9790   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9791     return NULL_RTX;
9792
9793   count = orig_count;
9794
9795   /* Unless one of the branches of the `if' in this loop does a `continue',
9796      we will `break' the loop after the `if'.  */
9797
9798   while (count != 0)
9799     {
9800       /* If we have an operand of (clobber (const_int 0)), fail.  */
9801       if (GET_CODE (varop) == CLOBBER)
9802         return NULL_RTX;
9803
9804       /* Convert ROTATERT to ROTATE.  */
9805       if (code == ROTATERT)
9806         {
9807           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9808           code = ROTATE;
9809           if (VECTOR_MODE_P (result_mode))
9810             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9811           else
9812             count = bitsize - count;
9813         }
9814
9815       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9816                                          mode, outer_op, outer_const);
9817
9818       /* Handle cases where the count is greater than the size of the mode
9819          minus 1.  For ASHIFT, use the size minus one as the count (this can
9820          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9821          take the count modulo the size.  For other shifts, the result is
9822          zero.
9823
9824          Since these shifts are being produced by the compiler by combining
9825          multiple operations, each of which are defined, we know what the
9826          result is supposed to be.  */
9827
9828       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9829         {
9830           if (code == ASHIFTRT)
9831             count = GET_MODE_PRECISION (shift_mode) - 1;
9832           else if (code == ROTATE || code == ROTATERT)
9833             count %= GET_MODE_PRECISION (shift_mode);
9834           else
9835             {
9836               /* We can't simply return zero because there may be an
9837                  outer op.  */
9838               varop = const0_rtx;
9839               count = 0;
9840               break;
9841             }
9842         }
9843
9844       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9845          here would cause an infinite loop.  */
9846       if (complement_p)
9847         break;
9848
9849       /* An arithmetic right shift of a quantity known to be -1 or 0
9850          is a no-op.  */
9851       if (code == ASHIFTRT
9852           && (num_sign_bit_copies (varop, shift_mode)
9853               == GET_MODE_PRECISION (shift_mode)))
9854         {
9855           count = 0;
9856           break;
9857         }
9858
9859       /* If we are doing an arithmetic right shift and discarding all but
9860          the sign bit copies, this is equivalent to doing a shift by the
9861          bitsize minus one.  Convert it into that shift because it will often
9862          allow other simplifications.  */
9863
9864       if (code == ASHIFTRT
9865           && (count + num_sign_bit_copies (varop, shift_mode)
9866               >= GET_MODE_PRECISION (shift_mode)))
9867         count = GET_MODE_PRECISION (shift_mode) - 1;
9868
9869       /* We simplify the tests below and elsewhere by converting
9870          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9871          `make_compound_operation' will convert it to an ASHIFTRT for
9872          those machines (such as VAX) that don't have an LSHIFTRT.  */
9873       if (code == ASHIFTRT
9874           && val_signbit_known_clear_p (shift_mode,
9875                                         nonzero_bits (varop, shift_mode)))
9876         code = LSHIFTRT;
9877
9878       if (((code == LSHIFTRT
9879             && HWI_COMPUTABLE_MODE_P (shift_mode)
9880             && !(nonzero_bits (varop, shift_mode) >> count))
9881            || (code == ASHIFT
9882                && HWI_COMPUTABLE_MODE_P (shift_mode)
9883                && !((nonzero_bits (varop, shift_mode) << count)
9884                     & GET_MODE_MASK (shift_mode))))
9885           && !side_effects_p (varop))
9886         varop = const0_rtx;
9887
9888       switch (GET_CODE (varop))
9889         {
9890         case SIGN_EXTEND:
9891         case ZERO_EXTEND:
9892         case SIGN_EXTRACT:
9893         case ZERO_EXTRACT:
9894           new_rtx = expand_compound_operation (varop);
9895           if (new_rtx != varop)
9896             {
9897               varop = new_rtx;
9898               continue;
9899             }
9900           break;
9901
9902         case MEM:
9903           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9904              minus the width of a smaller mode, we can do this with a
9905              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9906           if ((code == ASHIFTRT || code == LSHIFTRT)
9907               && ! mode_dependent_address_p (XEXP (varop, 0),
9908                                              MEM_ADDR_SPACE (varop))
9909               && ! MEM_VOLATILE_P (varop)
9910               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9911                                          MODE_INT, 1)) != BLKmode)
9912             {
9913               new_rtx = adjust_address_nv (varop, tmode,
9914                                        BYTES_BIG_ENDIAN ? 0
9915                                        : count / BITS_PER_UNIT);
9916
9917               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9918                                      : ZERO_EXTEND, mode, new_rtx);
9919               count = 0;
9920               continue;
9921             }
9922           break;
9923
9924         case SUBREG:
9925           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9926              the same number of words as what we've seen so far.  Then store
9927              the widest mode in MODE.  */
9928           if (subreg_lowpart_p (varop)
9929               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9930                   > GET_MODE_SIZE (GET_MODE (varop)))
9931               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9932                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9933                  == mode_words
9934               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9935               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9936             {
9937               varop = SUBREG_REG (varop);
9938               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9939                 mode = GET_MODE (varop);
9940               continue;
9941             }
9942           break;
9943
9944         case MULT:
9945           /* Some machines use MULT instead of ASHIFT because MULT
9946              is cheaper.  But it is still better on those machines to
9947              merge two shifts into one.  */
9948           if (CONST_INT_P (XEXP (varop, 1))
9949               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9950             {
9951               varop
9952                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9953                                        XEXP (varop, 0),
9954                                        GEN_INT (exact_log2 (
9955                                                 UINTVAL (XEXP (varop, 1)))));
9956               continue;
9957             }
9958           break;
9959
9960         case UDIV:
9961           /* Similar, for when divides are cheaper.  */
9962           if (CONST_INT_P (XEXP (varop, 1))
9963               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9964             {
9965               varop
9966                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9967                                        XEXP (varop, 0),
9968                                        GEN_INT (exact_log2 (
9969                                                 UINTVAL (XEXP (varop, 1)))));
9970               continue;
9971             }
9972           break;
9973
9974         case ASHIFTRT:
9975           /* If we are extracting just the sign bit of an arithmetic
9976              right shift, that shift is not needed.  However, the sign
9977              bit of a wider mode may be different from what would be
9978              interpreted as the sign bit in a narrower mode, so, if
9979              the result is narrower, don't discard the shift.  */
9980           if (code == LSHIFTRT
9981               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9982               && (GET_MODE_BITSIZE (result_mode)
9983                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9984             {
9985               varop = XEXP (varop, 0);
9986               continue;
9987             }
9988
9989           /* ... fall through ...  */
9990
9991         case LSHIFTRT:
9992         case ASHIFT:
9993         case ROTATE:
9994           /* Here we have two nested shifts.  The result is usually the
9995              AND of a new shift with a mask.  We compute the result below.  */
9996           if (CONST_INT_P (XEXP (varop, 1))
9997               && INTVAL (XEXP (varop, 1)) >= 0
9998               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
9999               && HWI_COMPUTABLE_MODE_P (result_mode)
10000               && HWI_COMPUTABLE_MODE_P (mode)
10001               && !VECTOR_MODE_P (result_mode))
10002             {
10003               enum rtx_code first_code = GET_CODE (varop);
10004               unsigned int first_count = INTVAL (XEXP (varop, 1));
10005               unsigned HOST_WIDE_INT mask;
10006               rtx mask_rtx;
10007
10008               /* We have one common special case.  We can't do any merging if
10009                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10010                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10011                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10012                  we can convert it to
10013                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10014                  This simplifies certain SIGN_EXTEND operations.  */
10015               if (code == ASHIFT && first_code == ASHIFTRT
10016                   && count == (GET_MODE_PRECISION (result_mode)
10017                                - GET_MODE_PRECISION (GET_MODE (varop))))
10018                 {
10019                   /* C3 has the low-order C1 bits zero.  */
10020
10021                   mask = GET_MODE_MASK (mode)
10022                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10023
10024                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10025                                                   XEXP (varop, 0), mask);
10026                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10027                                                 varop, count);
10028                   count = first_count;
10029                   code = ASHIFTRT;
10030                   continue;
10031                 }
10032
10033               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10034                  than C1 high-order bits equal to the sign bit, we can convert
10035                  this to either an ASHIFT or an ASHIFTRT depending on the
10036                  two counts.
10037
10038                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10039
10040               if (code == ASHIFTRT && first_code == ASHIFT
10041                   && GET_MODE (varop) == shift_mode
10042                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10043                       > first_count))
10044                 {
10045                   varop = XEXP (varop, 0);
10046                   count -= first_count;
10047                   if (count < 0)
10048                     {
10049                       count = -count;
10050                       code = ASHIFT;
10051                     }
10052
10053                   continue;
10054                 }
10055
10056               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10057                  we can only do this if FIRST_CODE is also ASHIFTRT.
10058
10059                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10060                  ASHIFTRT.
10061
10062                  If the mode of this shift is not the mode of the outer shift,
10063                  we can't do this if either shift is a right shift or ROTATE.
10064
10065                  Finally, we can't do any of these if the mode is too wide
10066                  unless the codes are the same.
10067
10068                  Handle the case where the shift codes are the same
10069                  first.  */
10070
10071               if (code == first_code)
10072                 {
10073                   if (GET_MODE (varop) != result_mode
10074                       && (code == ASHIFTRT || code == LSHIFTRT
10075                           || code == ROTATE))
10076                     break;
10077
10078                   count += first_count;
10079                   varop = XEXP (varop, 0);
10080                   continue;
10081                 }
10082
10083               if (code == ASHIFTRT
10084                   || (code == ROTATE && first_code == ASHIFTRT)
10085                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10086                   || (GET_MODE (varop) != result_mode
10087                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10088                           || first_code == ROTATE
10089                           || code == ROTATE)))
10090                 break;
10091
10092               /* To compute the mask to apply after the shift, shift the
10093                  nonzero bits of the inner shift the same way the
10094                  outer shift will.  */
10095
10096               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10097                                        result_mode);
10098
10099               mask_rtx
10100                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10101                                                    GEN_INT (count));
10102
10103               /* Give up if we can't compute an outer operation to use.  */
10104               if (mask_rtx == 0
10105                   || !CONST_INT_P (mask_rtx)
10106                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10107                                         INTVAL (mask_rtx),
10108                                         result_mode, &complement_p))
10109                 break;
10110
10111               /* If the shifts are in the same direction, we add the
10112                  counts.  Otherwise, we subtract them.  */
10113               if ((code == ASHIFTRT || code == LSHIFTRT)
10114                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10115                 count += first_count;
10116               else
10117                 count -= first_count;
10118
10119               /* If COUNT is positive, the new shift is usually CODE,
10120                  except for the two exceptions below, in which case it is
10121                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10122                  always be used  */
10123               if (count > 0
10124                   && ((first_code == ROTATE && code == ASHIFT)
10125                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10126                 code = first_code;
10127               else if (count < 0)
10128                 code = first_code, count = -count;
10129
10130               varop = XEXP (varop, 0);
10131               continue;
10132             }
10133
10134           /* If we have (A << B << C) for any shift, we can convert this to
10135              (A << C << B).  This wins if A is a constant.  Only try this if
10136              B is not a constant.  */
10137
10138           else if (GET_CODE (varop) == code
10139                    && CONST_INT_P (XEXP (varop, 0))
10140                    && !CONST_INT_P (XEXP (varop, 1)))
10141             {
10142               rtx new_rtx = simplify_const_binary_operation (code, mode,
10143                                                          XEXP (varop, 0),
10144                                                          GEN_INT (count));
10145               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10146               count = 0;
10147               continue;
10148             }
10149           break;
10150
10151         case NOT:
10152           if (VECTOR_MODE_P (mode))
10153             break;
10154
10155           /* Make this fit the case below.  */
10156           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10157           continue;
10158
10159         case IOR:
10160         case AND:
10161         case XOR:
10162           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10163              with C the size of VAROP - 1 and the shift is logical if
10164              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10165              we have an (le X 0) operation.   If we have an arithmetic shift
10166              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10167              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10168
10169           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10170               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10171               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10172               && (code == LSHIFTRT || code == ASHIFTRT)
10173               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10174               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10175             {
10176               count = 0;
10177               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10178                                   const0_rtx);
10179
10180               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10181                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10182
10183               continue;
10184             }
10185
10186           /* If we have (shift (logical)), move the logical to the outside
10187              to allow it to possibly combine with another logical and the
10188              shift to combine with another shift.  This also canonicalizes to
10189              what a ZERO_EXTRACT looks like.  Also, some machines have
10190              (and (shift)) insns.  */
10191
10192           if (CONST_INT_P (XEXP (varop, 1))
10193               /* We can't do this if we have (ashiftrt (xor))  and the
10194                  constant has its sign bit set in shift_mode.  */
10195               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10196                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10197                                               shift_mode))
10198               && (new_rtx = simplify_const_binary_operation
10199                   (code, result_mode,
10200                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10201                    GEN_INT (count))) != 0
10202               && CONST_INT_P (new_rtx)
10203               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10204                                   INTVAL (new_rtx), result_mode, &complement_p))
10205             {
10206               varop = XEXP (varop, 0);
10207               continue;
10208             }
10209
10210           /* If we can't do that, try to simplify the shift in each arm of the
10211              logical expression, make a new logical expression, and apply
10212              the inverse distributive law.  This also can't be done
10213              for some (ashiftrt (xor)).  */
10214           if (CONST_INT_P (XEXP (varop, 1))
10215              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10216                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10217                                              shift_mode)))
10218             {
10219               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10220                                               XEXP (varop, 0), count);
10221               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10222                                               XEXP (varop, 1), count);
10223
10224               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10225                                            lhs, rhs);
10226               varop = apply_distributive_law (varop);
10227
10228               count = 0;
10229               continue;
10230             }
10231           break;
10232
10233         case EQ:
10234           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10235              says that the sign bit can be tested, FOO has mode MODE, C is
10236              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10237              that may be nonzero.  */
10238           if (code == LSHIFTRT
10239               && XEXP (varop, 1) == const0_rtx
10240               && GET_MODE (XEXP (varop, 0)) == result_mode
10241               && count == (GET_MODE_PRECISION (result_mode) - 1)
10242               && HWI_COMPUTABLE_MODE_P (result_mode)
10243               && STORE_FLAG_VALUE == -1
10244               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10245               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10246                                   &complement_p))
10247             {
10248               varop = XEXP (varop, 0);
10249               count = 0;
10250               continue;
10251             }
10252           break;
10253
10254         case NEG:
10255           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10256              than the number of bits in the mode is equivalent to A.  */
10257           if (code == LSHIFTRT
10258               && count == (GET_MODE_PRECISION (result_mode) - 1)
10259               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10260             {
10261               varop = XEXP (varop, 0);
10262               count = 0;
10263               continue;
10264             }
10265
10266           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10267              NEG outside to allow shifts to combine.  */
10268           if (code == ASHIFT
10269               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10270                                   &complement_p))
10271             {
10272               varop = XEXP (varop, 0);
10273               continue;
10274             }
10275           break;
10276
10277         case PLUS:
10278           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10279              is one less than the number of bits in the mode is
10280              equivalent to (xor A 1).  */
10281           if (code == LSHIFTRT
10282               && count == (GET_MODE_PRECISION (result_mode) - 1)
10283               && XEXP (varop, 1) == constm1_rtx
10284               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10285               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10286                                   &complement_p))
10287             {
10288               count = 0;
10289               varop = XEXP (varop, 0);
10290               continue;
10291             }
10292
10293           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10294              that might be nonzero in BAR are those being shifted out and those
10295              bits are known zero in FOO, we can replace the PLUS with FOO.
10296              Similarly in the other operand order.  This code occurs when
10297              we are computing the size of a variable-size array.  */
10298
10299           if ((code == ASHIFTRT || code == LSHIFTRT)
10300               && count < HOST_BITS_PER_WIDE_INT
10301               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10302               && (nonzero_bits (XEXP (varop, 1), result_mode)
10303                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10304             {
10305               varop = XEXP (varop, 0);
10306               continue;
10307             }
10308           else if ((code == ASHIFTRT || code == LSHIFTRT)
10309                    && count < HOST_BITS_PER_WIDE_INT
10310                    && HWI_COMPUTABLE_MODE_P (result_mode)
10311                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10312                             >> count)
10313                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10314                             & nonzero_bits (XEXP (varop, 1),
10315                                                  result_mode)))
10316             {
10317               varop = XEXP (varop, 1);
10318               continue;
10319             }
10320
10321           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10322           if (code == ASHIFT
10323               && CONST_INT_P (XEXP (varop, 1))
10324               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10325                                                          XEXP (varop, 1),
10326                                                          GEN_INT (count))) != 0
10327               && CONST_INT_P (new_rtx)
10328               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10329                                   INTVAL (new_rtx), result_mode, &complement_p))
10330             {
10331               varop = XEXP (varop, 0);
10332               continue;
10333             }
10334
10335           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10336              signbit', and attempt to change the PLUS to an XOR and move it to
10337              the outer operation as is done above in the AND/IOR/XOR case
10338              leg for shift(logical). See details in logical handling above
10339              for reasoning in doing so.  */
10340           if (code == LSHIFTRT
10341               && CONST_INT_P (XEXP (varop, 1))
10342               && mode_signbit_p (result_mode, XEXP (varop, 1))
10343               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10344                                                          XEXP (varop, 1),
10345                                                          GEN_INT (count))) != 0
10346               && CONST_INT_P (new_rtx)
10347               && merge_outer_ops (&outer_op, &outer_const, XOR,
10348                                   INTVAL (new_rtx), result_mode, &complement_p))
10349             {
10350               varop = XEXP (varop, 0);
10351               continue;
10352             }
10353
10354           break;
10355
10356         case MINUS:
10357           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10358              with C the size of VAROP - 1 and the shift is logical if
10359              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10360              we have a (gt X 0) operation.  If the shift is arithmetic with
10361              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10362              we have a (neg (gt X 0)) operation.  */
10363
10364           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10365               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10366               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10367               && (code == LSHIFTRT || code == ASHIFTRT)
10368               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10369               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10370               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10371             {
10372               count = 0;
10373               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10374                                   const0_rtx);
10375
10376               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10377                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10378
10379               continue;
10380             }
10381           break;
10382
10383         case TRUNCATE:
10384           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10385              if the truncate does not affect the value.  */
10386           if (code == LSHIFTRT
10387               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10388               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10389               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10390                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10391                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10392             {
10393               rtx varop_inner = XEXP (varop, 0);
10394
10395               varop_inner
10396                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10397                                     XEXP (varop_inner, 0),
10398                                     GEN_INT
10399                                     (count + INTVAL (XEXP (varop_inner, 1))));
10400               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10401               count = 0;
10402               continue;
10403             }
10404           break;
10405
10406         default:
10407           break;
10408         }
10409
10410       break;
10411     }
10412
10413   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10414                                      outer_op, outer_const);
10415
10416   /* We have now finished analyzing the shift.  The result should be
10417      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10418      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10419      to the result of the shift.  OUTER_CONST is the relevant constant,
10420      but we must turn off all bits turned off in the shift.  */
10421
10422   if (outer_op == UNKNOWN
10423       && orig_code == code && orig_count == count
10424       && varop == orig_varop
10425       && shift_mode == GET_MODE (varop))
10426     return NULL_RTX;
10427
10428   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10429   varop = gen_lowpart (shift_mode, varop);
10430   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10431     return NULL_RTX;
10432
10433   /* If we have an outer operation and we just made a shift, it is
10434      possible that we could have simplified the shift were it not
10435      for the outer operation.  So try to do the simplification
10436      recursively.  */
10437
10438   if (outer_op != UNKNOWN)
10439     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10440   else
10441     x = NULL_RTX;
10442
10443   if (x == NULL_RTX)
10444     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10445
10446   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10447      turn off all the bits that the shift would have turned off.  */
10448   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10449     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10450                                 GET_MODE_MASK (result_mode) >> orig_count);
10451
10452   /* Do the remainder of the processing in RESULT_MODE.  */
10453   x = gen_lowpart_or_truncate (result_mode, x);
10454
10455   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10456      operation.  */
10457   if (complement_p)
10458     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10459
10460   if (outer_op != UNKNOWN)
10461     {
10462       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10463           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10464         outer_const = trunc_int_for_mode (outer_const, result_mode);
10465
10466       if (outer_op == AND)
10467         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10468       else if (outer_op == SET)
10469         {
10470           /* This means that we have determined that the result is
10471              equivalent to a constant.  This should be rare.  */
10472           if (!side_effects_p (x))
10473             x = GEN_INT (outer_const);
10474         }
10475       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10476         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10477       else
10478         x = simplify_gen_binary (outer_op, result_mode, x,
10479                                  GEN_INT (outer_const));
10480     }
10481
10482   return x;
10483 }
10484
10485 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10486    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10487    return X or, if it is NULL, synthesize the expression with
10488    simplify_gen_binary.  Otherwise, return a simplified value.
10489
10490    The shift is normally computed in the widest mode we find in VAROP, as
10491    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10492    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10493
10494 static rtx
10495 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10496                       rtx varop, int count)
10497 {
10498   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10499   if (tem)
10500     return tem;
10501
10502   if (!x)
10503     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10504   if (GET_MODE (x) != result_mode)
10505     x = gen_lowpart (result_mode, x);
10506   return x;
10507 }
10508
10509 \f
10510 /* Like recog, but we receive the address of a pointer to a new pattern.
10511    We try to match the rtx that the pointer points to.
10512    If that fails, we may try to modify or replace the pattern,
10513    storing the replacement into the same pointer object.
10514
10515    Modifications include deletion or addition of CLOBBERs.
10516
10517    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10518    the CLOBBERs are placed.
10519
10520    The value is the final insn code from the pattern ultimately matched,
10521    or -1.  */
10522
10523 static int
10524 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10525 {
10526   rtx pat = *pnewpat;
10527   rtx pat_without_clobbers;
10528   int insn_code_number;
10529   int num_clobbers_to_add = 0;
10530   int i;
10531   rtx notes = NULL_RTX;
10532   rtx old_notes, old_pat;
10533   int old_icode;
10534
10535   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10536      we use to indicate that something didn't match.  If we find such a
10537      thing, force rejection.  */
10538   if (GET_CODE (pat) == PARALLEL)
10539     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10540       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10541           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10542         return -1;
10543
10544   old_pat = PATTERN (insn);
10545   old_notes = REG_NOTES (insn);
10546   PATTERN (insn) = pat;
10547   REG_NOTES (insn) = NULL_RTX;
10548
10549   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10550   if (dump_file && (dump_flags & TDF_DETAILS))
10551     {
10552       if (insn_code_number < 0)
10553         fputs ("Failed to match this instruction:\n", dump_file);
10554       else
10555         fputs ("Successfully matched this instruction:\n", dump_file);
10556       print_rtl_single (dump_file, pat);
10557     }
10558
10559   /* If it isn't, there is the possibility that we previously had an insn
10560      that clobbered some register as a side effect, but the combined
10561      insn doesn't need to do that.  So try once more without the clobbers
10562      unless this represents an ASM insn.  */
10563
10564   if (insn_code_number < 0 && ! check_asm_operands (pat)
10565       && GET_CODE (pat) == PARALLEL)
10566     {
10567       int pos;
10568
10569       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10570         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10571           {
10572             if (i != pos)
10573               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10574             pos++;
10575           }
10576
10577       SUBST_INT (XVECLEN (pat, 0), pos);
10578
10579       if (pos == 1)
10580         pat = XVECEXP (pat, 0, 0);
10581
10582       PATTERN (insn) = pat;
10583       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10584       if (dump_file && (dump_flags & TDF_DETAILS))
10585         {
10586           if (insn_code_number < 0)
10587             fputs ("Failed to match this instruction:\n", dump_file);
10588           else
10589             fputs ("Successfully matched this instruction:\n", dump_file);
10590           print_rtl_single (dump_file, pat);
10591         }
10592     }
10593
10594   pat_without_clobbers = pat;
10595
10596   PATTERN (insn) = old_pat;
10597   REG_NOTES (insn) = old_notes;
10598
10599   /* Recognize all noop sets, these will be killed by followup pass.  */
10600   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10601     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10602
10603   /* If we had any clobbers to add, make a new pattern than contains
10604      them.  Then check to make sure that all of them are dead.  */
10605   if (num_clobbers_to_add)
10606     {
10607       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10608                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10609                                                   ? (XVECLEN (pat, 0)
10610                                                      + num_clobbers_to_add)
10611                                                   : num_clobbers_to_add + 1));
10612
10613       if (GET_CODE (pat) == PARALLEL)
10614         for (i = 0; i < XVECLEN (pat, 0); i++)
10615           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10616       else
10617         XVECEXP (newpat, 0, 0) = pat;
10618
10619       add_clobbers (newpat, insn_code_number);
10620
10621       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10622            i < XVECLEN (newpat, 0); i++)
10623         {
10624           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10625               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10626             return -1;
10627           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10628             {
10629               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10630               notes = alloc_reg_note (REG_UNUSED,
10631                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10632             }
10633         }
10634       pat = newpat;
10635     }
10636
10637   if (insn_code_number >= 0
10638       && insn_code_number != NOOP_MOVE_INSN_CODE)
10639     {
10640       old_pat = PATTERN (insn);
10641       old_notes = REG_NOTES (insn);
10642       old_icode = INSN_CODE (insn);
10643       PATTERN (insn) = pat;
10644       REG_NOTES (insn) = notes;
10645
10646       /* Allow targets to reject combined insn.  */
10647       if (!targetm.legitimate_combined_insn (insn))
10648         {
10649           if (dump_file && (dump_flags & TDF_DETAILS))
10650             fputs ("Instruction not appropriate for target.",
10651                    dump_file);
10652
10653           /* Callers expect recog_for_combine to strip
10654              clobbers from the pattern on failure.  */
10655           pat = pat_without_clobbers;
10656           notes = NULL_RTX;
10657
10658           insn_code_number = -1;
10659         }
10660
10661       PATTERN (insn) = old_pat;
10662       REG_NOTES (insn) = old_notes;
10663       INSN_CODE (insn) = old_icode;
10664     }
10665
10666   *pnewpat = pat;
10667   *pnotes = notes;
10668
10669   return insn_code_number;
10670 }
10671 \f
10672 /* Like gen_lowpart_general but for use by combine.  In combine it
10673    is not possible to create any new pseudoregs.  However, it is
10674    safe to create invalid memory addresses, because combine will
10675    try to recognize them and all they will do is make the combine
10676    attempt fail.
10677
10678    If for some reason this cannot do its job, an rtx
10679    (clobber (const_int 0)) is returned.
10680    An insn containing that will not be recognized.  */
10681
10682 static rtx
10683 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10684 {
10685   enum machine_mode imode = GET_MODE (x);
10686   unsigned int osize = GET_MODE_SIZE (omode);
10687   unsigned int isize = GET_MODE_SIZE (imode);
10688   rtx result;
10689
10690   if (omode == imode)
10691     return x;
10692
10693   /* We can only support MODE being wider than a word if X is a
10694      constant integer or has a mode the same size.  */
10695   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10696       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10697     goto fail;
10698
10699   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10700      won't know what to do.  So we will strip off the SUBREG here and
10701      process normally.  */
10702   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10703     {
10704       x = SUBREG_REG (x);
10705
10706       /* For use in case we fall down into the address adjustments
10707          further below, we need to adjust the known mode and size of
10708          x; imode and isize, since we just adjusted x.  */
10709       imode = GET_MODE (x);
10710
10711       if (imode == omode)
10712         return x;
10713
10714       isize = GET_MODE_SIZE (imode);
10715     }
10716
10717   result = gen_lowpart_common (omode, x);
10718
10719   if (result)
10720     return result;
10721
10722   if (MEM_P (x))
10723     {
10724       int offset = 0;
10725
10726       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10727          address.  */
10728       if (MEM_VOLATILE_P (x)
10729           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10730         goto fail;
10731
10732       /* If we want to refer to something bigger than the original memref,
10733          generate a paradoxical subreg instead.  That will force a reload
10734          of the original memref X.  */
10735       if (isize < osize)
10736         return gen_rtx_SUBREG (omode, x, 0);
10737
10738       if (WORDS_BIG_ENDIAN)
10739         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10740
10741       /* Adjust the address so that the address-after-the-data is
10742          unchanged.  */
10743       if (BYTES_BIG_ENDIAN)
10744         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10745
10746       return adjust_address_nv (x, omode, offset);
10747     }
10748
10749   /* If X is a comparison operator, rewrite it in a new mode.  This
10750      probably won't match, but may allow further simplifications.  */
10751   else if (COMPARISON_P (x))
10752     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10753
10754   /* If we couldn't simplify X any other way, just enclose it in a
10755      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10756      include an explicit SUBREG or we may simplify it further in combine.  */
10757   else
10758     {
10759       int offset = 0;
10760       rtx res;
10761
10762       offset = subreg_lowpart_offset (omode, imode);
10763       if (imode == VOIDmode)
10764         {
10765           imode = int_mode_for_mode (omode);
10766           x = gen_lowpart_common (imode, x);
10767           if (x == NULL)
10768             goto fail;
10769         }
10770       res = simplify_gen_subreg (omode, x, imode, offset);
10771       if (res)
10772         return res;
10773     }
10774
10775  fail:
10776   return gen_rtx_CLOBBER (omode, const0_rtx);
10777 }
10778 \f
10779 /* Try to simplify a comparison between OP0 and a constant OP1,
10780    where CODE is the comparison code that will be tested, into a
10781    (CODE OP0 const0_rtx) form.
10782
10783    The result is a possibly different comparison code to use.
10784    *POP1 may be updated.  */
10785
10786 static enum rtx_code
10787 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10788 {
10789   enum machine_mode mode = GET_MODE (op0);
10790   unsigned int mode_width = GET_MODE_PRECISION (mode);
10791   HOST_WIDE_INT const_op = INTVAL (*pop1);
10792
10793   /* Get the constant we are comparing against and turn off all bits
10794      not on in our mode.  */
10795   if (mode != VOIDmode)
10796     const_op = trunc_int_for_mode (const_op, mode);
10797
10798   /* If we are comparing against a constant power of two and the value
10799      being compared can only have that single bit nonzero (e.g., it was
10800      `and'ed with that bit), we can replace this with a comparison
10801      with zero.  */
10802   if (const_op
10803       && (code == EQ || code == NE || code == GE || code == GEU
10804           || code == LT || code == LTU)
10805       && mode_width <= HOST_BITS_PER_WIDE_INT
10806       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10807       && (nonzero_bits (op0, mode)
10808           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10809     {
10810       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10811       const_op = 0;
10812     }
10813
10814   /* Similarly, if we are comparing a value known to be either -1 or
10815      0 with -1, change it to the opposite comparison against zero.  */
10816   if (const_op == -1
10817       && (code == EQ || code == NE || code == GT || code == LE
10818           || code == GEU || code == LTU)
10819       && num_sign_bit_copies (op0, mode) == mode_width)
10820     {
10821       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10822       const_op = 0;
10823     }
10824
10825   /* Do some canonicalizations based on the comparison code.  We prefer
10826      comparisons against zero and then prefer equality comparisons.
10827      If we can reduce the size of a constant, we will do that too.  */
10828   switch (code)
10829     {
10830     case LT:
10831       /* < C is equivalent to <= (C - 1) */
10832       if (const_op > 0)
10833         {
10834           const_op -= 1;
10835           code = LE;
10836           /* ... fall through to LE case below.  */
10837         }
10838       else
10839         break;
10840
10841     case LE:
10842       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10843       if (const_op < 0)
10844         {
10845           const_op += 1;
10846           code = LT;
10847         }
10848
10849       /* If we are doing a <= 0 comparison on a value known to have
10850          a zero sign bit, we can replace this with == 0.  */
10851       else if (const_op == 0
10852                && mode_width <= HOST_BITS_PER_WIDE_INT
10853                && (nonzero_bits (op0, mode)
10854                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10855                == 0)
10856         code = EQ;
10857       break;
10858
10859     case GE:
10860       /* >= C is equivalent to > (C - 1).  */
10861       if (const_op > 0)
10862         {
10863           const_op -= 1;
10864           code = GT;
10865           /* ... fall through to GT below.  */
10866         }
10867       else
10868         break;
10869
10870     case GT:
10871       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10872       if (const_op < 0)
10873         {
10874           const_op += 1;
10875           code = GE;
10876         }
10877
10878       /* If we are doing a > 0 comparison on a value known to have
10879          a zero sign bit, we can replace this with != 0.  */
10880       else if (const_op == 0
10881                && mode_width <= HOST_BITS_PER_WIDE_INT
10882                && (nonzero_bits (op0, mode)
10883                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10884                == 0)
10885         code = NE;
10886       break;
10887
10888     case LTU:
10889       /* < C is equivalent to <= (C - 1).  */
10890       if (const_op > 0)
10891         {
10892           const_op -= 1;
10893           code = LEU;
10894           /* ... fall through ...  */
10895         }
10896       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10897       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10898                && (unsigned HOST_WIDE_INT) const_op
10899                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10900         {
10901           const_op = 0;
10902           code = GE;
10903           break;
10904         }
10905       else
10906         break;
10907
10908     case LEU:
10909       /* unsigned <= 0 is equivalent to == 0 */
10910       if (const_op == 0)
10911         code = EQ;
10912       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10913       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10914                && (unsigned HOST_WIDE_INT) const_op
10915                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10916         {
10917           const_op = 0;
10918           code = GE;
10919         }
10920       break;
10921
10922     case GEU:
10923       /* >= C is equivalent to > (C - 1).  */
10924       if (const_op > 1)
10925         {
10926           const_op -= 1;
10927           code = GTU;
10928           /* ... fall through ...  */
10929         }
10930
10931       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10932       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10933                && (unsigned HOST_WIDE_INT) const_op
10934                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10935         {
10936           const_op = 0;
10937           code = LT;
10938           break;
10939         }
10940       else
10941         break;
10942
10943     case GTU:
10944       /* unsigned > 0 is equivalent to != 0 */
10945       if (const_op == 0)
10946         code = NE;
10947       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10948       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10949                && (unsigned HOST_WIDE_INT) const_op
10950                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10951         {
10952           const_op = 0;
10953           code = LT;
10954         }
10955       break;
10956
10957     default:
10958       break;
10959     }
10960
10961   *pop1 = GEN_INT (const_op);
10962   return code;
10963 }
10964 \f
10965 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10966    comparison code that will be tested.
10967
10968    The result is a possibly different comparison code to use.  *POP0 and
10969    *POP1 may be updated.
10970
10971    It is possible that we might detect that a comparison is either always
10972    true or always false.  However, we do not perform general constant
10973    folding in combine, so this knowledge isn't useful.  Such tautologies
10974    should have been detected earlier.  Hence we ignore all such cases.  */
10975
10976 static enum rtx_code
10977 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10978 {
10979   rtx op0 = *pop0;
10980   rtx op1 = *pop1;
10981   rtx tem, tem1;
10982   int i;
10983   enum machine_mode mode, tmode;
10984
10985   /* Try a few ways of applying the same transformation to both operands.  */
10986   while (1)
10987     {
10988 #ifndef WORD_REGISTER_OPERATIONS
10989       /* The test below this one won't handle SIGN_EXTENDs on these machines,
10990          so check specially.  */
10991       if (code != GTU && code != GEU && code != LTU && code != LEU
10992           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10993           && GET_CODE (XEXP (op0, 0)) == ASHIFT
10994           && GET_CODE (XEXP (op1, 0)) == ASHIFT
10995           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10996           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10997           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10998               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10999           && CONST_INT_P (XEXP (op0, 1))
11000           && XEXP (op0, 1) == XEXP (op1, 1)
11001           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11002           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11003           && (INTVAL (XEXP (op0, 1))
11004               == (GET_MODE_PRECISION (GET_MODE (op0))
11005                   - (GET_MODE_PRECISION
11006                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11007         {
11008           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11009           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11010         }
11011 #endif
11012
11013       /* If both operands are the same constant shift, see if we can ignore the
11014          shift.  We can if the shift is a rotate or if the bits shifted out of
11015          this shift are known to be zero for both inputs and if the type of
11016          comparison is compatible with the shift.  */
11017       if (GET_CODE (op0) == GET_CODE (op1)
11018           && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11019           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11020               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11021                   && (code != GT && code != LT && code != GE && code != LE))
11022               || (GET_CODE (op0) == ASHIFTRT
11023                   && (code != GTU && code != LTU
11024                       && code != GEU && code != LEU)))
11025           && CONST_INT_P (XEXP (op0, 1))
11026           && INTVAL (XEXP (op0, 1)) >= 0
11027           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11028           && XEXP (op0, 1) == XEXP (op1, 1))
11029         {
11030           enum machine_mode mode = GET_MODE (op0);
11031           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11032           int shift_count = INTVAL (XEXP (op0, 1));
11033
11034           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11035             mask &= (mask >> shift_count) << shift_count;
11036           else if (GET_CODE (op0) == ASHIFT)
11037             mask = (mask & (mask << shift_count)) >> shift_count;
11038
11039           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11040               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11041             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11042           else
11043             break;
11044         }
11045
11046       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11047          SUBREGs are of the same mode, and, in both cases, the AND would
11048          be redundant if the comparison was done in the narrower mode,
11049          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11050          and the operand's possibly nonzero bits are 0xffffff01; in that case
11051          if we only care about QImode, we don't need the AND).  This case
11052          occurs if the output mode of an scc insn is not SImode and
11053          STORE_FLAG_VALUE == 1 (e.g., the 386).
11054
11055          Similarly, check for a case where the AND's are ZERO_EXTEND
11056          operations from some narrower mode even though a SUBREG is not
11057          present.  */
11058
11059       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11060                && CONST_INT_P (XEXP (op0, 1))
11061                && CONST_INT_P (XEXP (op1, 1)))
11062         {
11063           rtx inner_op0 = XEXP (op0, 0);
11064           rtx inner_op1 = XEXP (op1, 0);
11065           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11066           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11067           int changed = 0;
11068
11069           if (paradoxical_subreg_p (inner_op0)
11070               && GET_CODE (inner_op1) == SUBREG
11071               && (GET_MODE (SUBREG_REG (inner_op0))
11072                   == GET_MODE (SUBREG_REG (inner_op1)))
11073               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11074                   <= HOST_BITS_PER_WIDE_INT)
11075               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11076                                              GET_MODE (SUBREG_REG (inner_op0)))))
11077               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11078                                              GET_MODE (SUBREG_REG (inner_op1))))))
11079             {
11080               op0 = SUBREG_REG (inner_op0);
11081               op1 = SUBREG_REG (inner_op1);
11082
11083               /* The resulting comparison is always unsigned since we masked
11084                  off the original sign bit.  */
11085               code = unsigned_condition (code);
11086
11087               changed = 1;
11088             }
11089
11090           else if (c0 == c1)
11091             for (tmode = GET_CLASS_NARROWEST_MODE
11092                  (GET_MODE_CLASS (GET_MODE (op0)));
11093                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11094               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11095                 {
11096                   op0 = gen_lowpart (tmode, inner_op0);
11097                   op1 = gen_lowpart (tmode, inner_op1);
11098                   code = unsigned_condition (code);
11099                   changed = 1;
11100                   break;
11101                 }
11102
11103           if (! changed)
11104             break;
11105         }
11106
11107       /* If both operands are NOT, we can strip off the outer operation
11108          and adjust the comparison code for swapped operands; similarly for
11109          NEG, except that this must be an equality comparison.  */
11110       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11111                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11112                    && (code == EQ || code == NE)))
11113         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11114
11115       else
11116         break;
11117     }
11118
11119   /* If the first operand is a constant, swap the operands and adjust the
11120      comparison code appropriately, but don't do this if the second operand
11121      is already a constant integer.  */
11122   if (swap_commutative_operands_p (op0, op1))
11123     {
11124       tem = op0, op0 = op1, op1 = tem;
11125       code = swap_condition (code);
11126     }
11127
11128   /* We now enter a loop during which we will try to simplify the comparison.
11129      For the most part, we only are concerned with comparisons with zero,
11130      but some things may really be comparisons with zero but not start
11131      out looking that way.  */
11132
11133   while (CONST_INT_P (op1))
11134     {
11135       enum machine_mode mode = GET_MODE (op0);
11136       unsigned int mode_width = GET_MODE_PRECISION (mode);
11137       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11138       int equality_comparison_p;
11139       int sign_bit_comparison_p;
11140       int unsigned_comparison_p;
11141       HOST_WIDE_INT const_op;
11142
11143       /* We only want to handle integral modes.  This catches VOIDmode,
11144          CCmode, and the floating-point modes.  An exception is that we
11145          can handle VOIDmode if OP0 is a COMPARE or a comparison
11146          operation.  */
11147
11148       if (GET_MODE_CLASS (mode) != MODE_INT
11149           && ! (mode == VOIDmode
11150                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11151         break;
11152
11153       /* Try to simplify the compare to constant, possibly changing the
11154          comparison op, and/or changing op1 to zero.  */
11155       code = simplify_compare_const (code, op0, &op1);
11156       const_op = INTVAL (op1);
11157
11158       /* Compute some predicates to simplify code below.  */
11159
11160       equality_comparison_p = (code == EQ || code == NE);
11161       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11162       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11163                                || code == GEU);
11164
11165       /* If this is a sign bit comparison and we can do arithmetic in
11166          MODE, say that we will only be needing the sign bit of OP0.  */
11167       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11168         op0 = force_to_mode (op0, mode,
11169                              (unsigned HOST_WIDE_INT) 1
11170                              << (GET_MODE_PRECISION (mode) - 1),
11171                              0);
11172
11173       /* Now try cases based on the opcode of OP0.  If none of the cases
11174          does a "continue", we exit this loop immediately after the
11175          switch.  */
11176
11177       switch (GET_CODE (op0))
11178         {
11179         case ZERO_EXTRACT:
11180           /* If we are extracting a single bit from a variable position in
11181              a constant that has only a single bit set and are comparing it
11182              with zero, we can convert this into an equality comparison
11183              between the position and the location of the single bit.  */
11184           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11185              have already reduced the shift count modulo the word size.  */
11186           if (!SHIFT_COUNT_TRUNCATED
11187               && CONST_INT_P (XEXP (op0, 0))
11188               && XEXP (op0, 1) == const1_rtx
11189               && equality_comparison_p && const_op == 0
11190               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11191             {
11192               if (BITS_BIG_ENDIAN)
11193                 i = BITS_PER_WORD - 1 - i;
11194
11195               op0 = XEXP (op0, 2);
11196               op1 = GEN_INT (i);
11197               const_op = i;
11198
11199               /* Result is nonzero iff shift count is equal to I.  */
11200               code = reverse_condition (code);
11201               continue;
11202             }
11203
11204           /* ... fall through ...  */
11205
11206         case SIGN_EXTRACT:
11207           tem = expand_compound_operation (op0);
11208           if (tem != op0)
11209             {
11210               op0 = tem;
11211               continue;
11212             }
11213           break;
11214
11215         case NOT:
11216           /* If testing for equality, we can take the NOT of the constant.  */
11217           if (equality_comparison_p
11218               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11219             {
11220               op0 = XEXP (op0, 0);
11221               op1 = tem;
11222               continue;
11223             }
11224
11225           /* If just looking at the sign bit, reverse the sense of the
11226              comparison.  */
11227           if (sign_bit_comparison_p)
11228             {
11229               op0 = XEXP (op0, 0);
11230               code = (code == GE ? LT : GE);
11231               continue;
11232             }
11233           break;
11234
11235         case NEG:
11236           /* If testing for equality, we can take the NEG of the constant.  */
11237           if (equality_comparison_p
11238               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11239             {
11240               op0 = XEXP (op0, 0);
11241               op1 = tem;
11242               continue;
11243             }
11244
11245           /* The remaining cases only apply to comparisons with zero.  */
11246           if (const_op != 0)
11247             break;
11248
11249           /* When X is ABS or is known positive,
11250              (neg X) is < 0 if and only if X != 0.  */
11251
11252           if (sign_bit_comparison_p
11253               && (GET_CODE (XEXP (op0, 0)) == ABS
11254                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11255                       && (nonzero_bits (XEXP (op0, 0), mode)
11256                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11257                          == 0)))
11258             {
11259               op0 = XEXP (op0, 0);
11260               code = (code == LT ? NE : EQ);
11261               continue;
11262             }
11263
11264           /* If we have NEG of something whose two high-order bits are the
11265              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11266           if (num_sign_bit_copies (op0, mode) >= 2)
11267             {
11268               op0 = XEXP (op0, 0);
11269               code = swap_condition (code);
11270               continue;
11271             }
11272           break;
11273
11274         case ROTATE:
11275           /* If we are testing equality and our count is a constant, we
11276              can perform the inverse operation on our RHS.  */
11277           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11278               && (tem = simplify_binary_operation (ROTATERT, mode,
11279                                                    op1, XEXP (op0, 1))) != 0)
11280             {
11281               op0 = XEXP (op0, 0);
11282               op1 = tem;
11283               continue;
11284             }
11285
11286           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11287              a particular bit.  Convert it to an AND of a constant of that
11288              bit.  This will be converted into a ZERO_EXTRACT.  */
11289           if (const_op == 0 && sign_bit_comparison_p
11290               && CONST_INT_P (XEXP (op0, 1))
11291               && mode_width <= HOST_BITS_PER_WIDE_INT)
11292             {
11293               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11294                                             ((unsigned HOST_WIDE_INT) 1
11295                                              << (mode_width - 1
11296                                                  - INTVAL (XEXP (op0, 1)))));
11297               code = (code == LT ? NE : EQ);
11298               continue;
11299             }
11300
11301           /* Fall through.  */
11302
11303         case ABS:
11304           /* ABS is ignorable inside an equality comparison with zero.  */
11305           if (const_op == 0 && equality_comparison_p)
11306             {
11307               op0 = XEXP (op0, 0);
11308               continue;
11309             }
11310           break;
11311
11312         case SIGN_EXTEND:
11313           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11314              (compare FOO CONST) if CONST fits in FOO's mode and we
11315              are either testing inequality or have an unsigned
11316              comparison with ZERO_EXTEND or a signed comparison with
11317              SIGN_EXTEND.  But don't do it if we don't have a compare
11318              insn of the given mode, since we'd have to revert it
11319              later on, and then we wouldn't know whether to sign- or
11320              zero-extend.  */
11321           mode = GET_MODE (XEXP (op0, 0));
11322           if (GET_MODE_CLASS (mode) == MODE_INT
11323               && ! unsigned_comparison_p
11324               && HWI_COMPUTABLE_MODE_P (mode)
11325               && trunc_int_for_mode (const_op, mode) == const_op
11326               && have_insn_for (COMPARE, mode))
11327             {
11328               op0 = XEXP (op0, 0);
11329               continue;
11330             }
11331           break;
11332
11333         case SUBREG:
11334           /* Check for the case where we are comparing A - C1 with C2, that is
11335
11336                (subreg:MODE (plus (A) (-C1))) op (C2)
11337
11338              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11339              comparison in the wider mode.  One of the following two conditions
11340              must be true in order for this to be valid:
11341
11342                1. The mode extension results in the same bit pattern being added
11343                   on both sides and the comparison is equality or unsigned.  As
11344                   C2 has been truncated to fit in MODE, the pattern can only be
11345                   all 0s or all 1s.
11346
11347                2. The mode extension results in the sign bit being copied on
11348                   each side.
11349
11350              The difficulty here is that we have predicates for A but not for
11351              (A - C1) so we need to check that C1 is within proper bounds so
11352              as to perturbate A as little as possible.  */
11353
11354           if (mode_width <= HOST_BITS_PER_WIDE_INT
11355               && subreg_lowpart_p (op0)
11356               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11357               && GET_CODE (SUBREG_REG (op0)) == PLUS
11358               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11359             {
11360               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11361               rtx a = XEXP (SUBREG_REG (op0), 0);
11362               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11363
11364               if ((c1 > 0
11365                    && (unsigned HOST_WIDE_INT) c1
11366                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11367                    && (equality_comparison_p || unsigned_comparison_p)
11368                    /* (A - C1) zero-extends if it is positive and sign-extends
11369                       if it is negative, C2 both zero- and sign-extends.  */
11370                    && ((0 == (nonzero_bits (a, inner_mode)
11371                               & ~GET_MODE_MASK (mode))
11372                         && const_op >= 0)
11373                        /* (A - C1) sign-extends if it is positive and 1-extends
11374                           if it is negative, C2 both sign- and 1-extends.  */
11375                        || (num_sign_bit_copies (a, inner_mode)
11376                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11377                                              - mode_width)
11378                            && const_op < 0)))
11379                   || ((unsigned HOST_WIDE_INT) c1
11380                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11381                       /* (A - C1) always sign-extends, like C2.  */
11382                       && num_sign_bit_copies (a, inner_mode)
11383                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11384                                            - (mode_width - 1))))
11385                 {
11386                   op0 = SUBREG_REG (op0);
11387                   continue;
11388                 }
11389             }
11390
11391           /* If the inner mode is narrower and we are extracting the low part,
11392              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11393           if (subreg_lowpart_p (op0)
11394               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11395             /* Fall through */ ;
11396           else
11397             break;
11398
11399           /* ... fall through ...  */
11400
11401         case ZERO_EXTEND:
11402           mode = GET_MODE (XEXP (op0, 0));
11403           if (GET_MODE_CLASS (mode) == MODE_INT
11404               && (unsigned_comparison_p || equality_comparison_p)
11405               && HWI_COMPUTABLE_MODE_P (mode)
11406               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11407               && const_op >= 0
11408               && have_insn_for (COMPARE, mode))
11409             {
11410               op0 = XEXP (op0, 0);
11411               continue;
11412             }
11413           break;
11414
11415         case PLUS:
11416           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11417              this for equality comparisons due to pathological cases involving
11418              overflows.  */
11419           if (equality_comparison_p
11420               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11421                                                         op1, XEXP (op0, 1))))
11422             {
11423               op0 = XEXP (op0, 0);
11424               op1 = tem;
11425               continue;
11426             }
11427
11428           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11429           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11430               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11431             {
11432               op0 = XEXP (XEXP (op0, 0), 0);
11433               code = (code == LT ? EQ : NE);
11434               continue;
11435             }
11436           break;
11437
11438         case MINUS:
11439           /* We used to optimize signed comparisons against zero, but that
11440              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11441              arrive here as equality comparisons, or (GEU, LTU) are
11442              optimized away.  No need to special-case them.  */
11443
11444           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11445              (eq B (minus A C)), whichever simplifies.  We can only do
11446              this for equality comparisons due to pathological cases involving
11447              overflows.  */
11448           if (equality_comparison_p
11449               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11450                                                         XEXP (op0, 1), op1)))
11451             {
11452               op0 = XEXP (op0, 0);
11453               op1 = tem;
11454               continue;
11455             }
11456
11457           if (equality_comparison_p
11458               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11459                                                         XEXP (op0, 0), op1)))
11460             {
11461               op0 = XEXP (op0, 1);
11462               op1 = tem;
11463               continue;
11464             }
11465
11466           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11467              of bits in X minus 1, is one iff X > 0.  */
11468           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11469               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11470               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11471               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11472             {
11473               op0 = XEXP (op0, 1);
11474               code = (code == GE ? LE : GT);
11475               continue;
11476             }
11477           break;
11478
11479         case XOR:
11480           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11481              if C is zero or B is a constant.  */
11482           if (equality_comparison_p
11483               && 0 != (tem = simplify_binary_operation (XOR, mode,
11484                                                         XEXP (op0, 1), op1)))
11485             {
11486               op0 = XEXP (op0, 0);
11487               op1 = tem;
11488               continue;
11489             }
11490           break;
11491
11492         case EQ:  case NE:
11493         case UNEQ:  case LTGT:
11494         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11495         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11496         case UNORDERED: case ORDERED:
11497           /* We can't do anything if OP0 is a condition code value, rather
11498              than an actual data value.  */
11499           if (const_op != 0
11500               || CC0_P (XEXP (op0, 0))
11501               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11502             break;
11503
11504           /* Get the two operands being compared.  */
11505           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11506             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11507           else
11508             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11509
11510           /* Check for the cases where we simply want the result of the
11511              earlier test or the opposite of that result.  */
11512           if (code == NE || code == EQ
11513               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11514                   && (code == LT || code == GE)))
11515             {
11516               enum rtx_code new_code;
11517               if (code == LT || code == NE)
11518                 new_code = GET_CODE (op0);
11519               else
11520                 new_code = reversed_comparison_code (op0, NULL);
11521
11522               if (new_code != UNKNOWN)
11523                 {
11524                   code = new_code;
11525                   op0 = tem;
11526                   op1 = tem1;
11527                   continue;
11528                 }
11529             }
11530           break;
11531
11532         case IOR:
11533           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11534              iff X <= 0.  */
11535           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11536               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11537               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11538             {
11539               op0 = XEXP (op0, 1);
11540               code = (code == GE ? GT : LE);
11541               continue;
11542             }
11543           break;
11544
11545         case AND:
11546           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11547              will be converted to a ZERO_EXTRACT later.  */
11548           if (const_op == 0 && equality_comparison_p
11549               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11550               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11551             {
11552               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11553                                       XEXP (XEXP (op0, 0), 1));
11554               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11555               continue;
11556             }
11557
11558           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11559              zero and X is a comparison and C1 and C2 describe only bits set
11560              in STORE_FLAG_VALUE, we can compare with X.  */
11561           if (const_op == 0 && equality_comparison_p
11562               && mode_width <= HOST_BITS_PER_WIDE_INT
11563               && CONST_INT_P (XEXP (op0, 1))
11564               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11565               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11566               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11567               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11568             {
11569               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11570                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11571               if ((~STORE_FLAG_VALUE & mask) == 0
11572                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11573                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11574                           && COMPARISON_P (tem))))
11575                 {
11576                   op0 = XEXP (XEXP (op0, 0), 0);
11577                   continue;
11578                 }
11579             }
11580
11581           /* If we are doing an equality comparison of an AND of a bit equal
11582              to the sign bit, replace this with a LT or GE comparison of
11583              the underlying value.  */
11584           if (equality_comparison_p
11585               && const_op == 0
11586               && CONST_INT_P (XEXP (op0, 1))
11587               && mode_width <= HOST_BITS_PER_WIDE_INT
11588               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11589                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11590             {
11591               op0 = XEXP (op0, 0);
11592               code = (code == EQ ? GE : LT);
11593               continue;
11594             }
11595
11596           /* If this AND operation is really a ZERO_EXTEND from a narrower
11597              mode, the constant fits within that mode, and this is either an
11598              equality or unsigned comparison, try to do this comparison in
11599              the narrower mode.
11600
11601              Note that in:
11602
11603              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11604              -> (ne:DI (reg:SI 4) (const_int 0))
11605
11606              unless TRULY_NOOP_TRUNCATION allows it or the register is
11607              known to hold a value of the required mode the
11608              transformation is invalid.  */
11609           if ((equality_comparison_p || unsigned_comparison_p)
11610               && CONST_INT_P (XEXP (op0, 1))
11611               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11612                                    & GET_MODE_MASK (mode))
11613                                   + 1)) >= 0
11614               && const_op >> i == 0
11615               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11616               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11617                   || (REG_P (XEXP (op0, 0))
11618                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11619             {
11620               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11621               continue;
11622             }
11623
11624           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11625              fits in both M1 and M2 and the SUBREG is either paradoxical
11626              or represents the low part, permute the SUBREG and the AND
11627              and try again.  */
11628           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11629             {
11630               unsigned HOST_WIDE_INT c1;
11631               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11632               /* Require an integral mode, to avoid creating something like
11633                  (AND:SF ...).  */
11634               if (SCALAR_INT_MODE_P (tmode)
11635                   /* It is unsafe to commute the AND into the SUBREG if the
11636                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11637                      not defined.  As originally written the upper bits
11638                      have a defined value due to the AND operation.
11639                      However, if we commute the AND inside the SUBREG then
11640                      they no longer have defined values and the meaning of
11641                      the code has been changed.  */
11642                   && (0
11643 #ifdef WORD_REGISTER_OPERATIONS
11644                       || (mode_width > GET_MODE_PRECISION (tmode)
11645                           && mode_width <= BITS_PER_WORD)
11646 #endif
11647                       || (mode_width <= GET_MODE_PRECISION (tmode)
11648                           && subreg_lowpart_p (XEXP (op0, 0))))
11649                   && CONST_INT_P (XEXP (op0, 1))
11650                   && mode_width <= HOST_BITS_PER_WIDE_INT
11651                   && HWI_COMPUTABLE_MODE_P (tmode)
11652                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11653                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11654                   && c1 != mask
11655                   && c1 != GET_MODE_MASK (tmode))
11656                 {
11657                   op0 = simplify_gen_binary (AND, tmode,
11658                                              SUBREG_REG (XEXP (op0, 0)),
11659                                              gen_int_mode (c1, tmode));
11660                   op0 = gen_lowpart (mode, op0);
11661                   continue;
11662                 }
11663             }
11664
11665           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11666           if (const_op == 0 && equality_comparison_p
11667               && XEXP (op0, 1) == const1_rtx
11668               && GET_CODE (XEXP (op0, 0)) == NOT)
11669             {
11670               op0 = simplify_and_const_int (NULL_RTX, mode,
11671                                             XEXP (XEXP (op0, 0), 0), 1);
11672               code = (code == NE ? EQ : NE);
11673               continue;
11674             }
11675
11676           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11677              (eq (and (lshiftrt X) 1) 0).
11678              Also handle the case where (not X) is expressed using xor.  */
11679           if (const_op == 0 && equality_comparison_p
11680               && XEXP (op0, 1) == const1_rtx
11681               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11682             {
11683               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11684               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11685
11686               if (GET_CODE (shift_op) == NOT
11687                   || (GET_CODE (shift_op) == XOR
11688                       && CONST_INT_P (XEXP (shift_op, 1))
11689                       && CONST_INT_P (shift_count)
11690                       && HWI_COMPUTABLE_MODE_P (mode)
11691                       && (UINTVAL (XEXP (shift_op, 1))
11692                           == (unsigned HOST_WIDE_INT) 1
11693                                << INTVAL (shift_count))))
11694                 {
11695                   op0
11696                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11697                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11698                   code = (code == NE ? EQ : NE);
11699                   continue;
11700                 }
11701             }
11702           break;
11703
11704         case ASHIFT:
11705           /* If we have (compare (ashift FOO N) (const_int C)) and
11706              the high order N bits of FOO (N+1 if an inequality comparison)
11707              are known to be zero, we can do this by comparing FOO with C
11708              shifted right N bits so long as the low-order N bits of C are
11709              zero.  */
11710           if (CONST_INT_P (XEXP (op0, 1))
11711               && INTVAL (XEXP (op0, 1)) >= 0
11712               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11713                   < HOST_BITS_PER_WIDE_INT)
11714               && (((unsigned HOST_WIDE_INT) const_op
11715                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11716                       - 1)) == 0)
11717               && mode_width <= HOST_BITS_PER_WIDE_INT
11718               && (nonzero_bits (XEXP (op0, 0), mode)
11719                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11720                                + ! equality_comparison_p))) == 0)
11721             {
11722               /* We must perform a logical shift, not an arithmetic one,
11723                  as we want the top N bits of C to be zero.  */
11724               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11725
11726               temp >>= INTVAL (XEXP (op0, 1));
11727               op1 = gen_int_mode (temp, mode);
11728               op0 = XEXP (op0, 0);
11729               continue;
11730             }
11731
11732           /* If we are doing a sign bit comparison, it means we are testing
11733              a particular bit.  Convert it to the appropriate AND.  */
11734           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11735               && mode_width <= HOST_BITS_PER_WIDE_INT)
11736             {
11737               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11738                                             ((unsigned HOST_WIDE_INT) 1
11739                                              << (mode_width - 1
11740                                                  - INTVAL (XEXP (op0, 1)))));
11741               code = (code == LT ? NE : EQ);
11742               continue;
11743             }
11744
11745           /* If this an equality comparison with zero and we are shifting
11746              the low bit to the sign bit, we can convert this to an AND of the
11747              low-order bit.  */
11748           if (const_op == 0 && equality_comparison_p
11749               && CONST_INT_P (XEXP (op0, 1))
11750               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11751             {
11752               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11753               continue;
11754             }
11755           break;
11756
11757         case ASHIFTRT:
11758           /* If this is an equality comparison with zero, we can do this
11759              as a logical shift, which might be much simpler.  */
11760           if (equality_comparison_p && const_op == 0
11761               && CONST_INT_P (XEXP (op0, 1)))
11762             {
11763               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11764                                           XEXP (op0, 0),
11765                                           INTVAL (XEXP (op0, 1)));
11766               continue;
11767             }
11768
11769           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11770              do the comparison in a narrower mode.  */
11771           if (! unsigned_comparison_p
11772               && CONST_INT_P (XEXP (op0, 1))
11773               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11774               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11775               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11776                                          MODE_INT, 1)) != BLKmode
11777               && (((unsigned HOST_WIDE_INT) const_op
11778                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11779                   <= GET_MODE_MASK (tmode)))
11780             {
11781               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11782               continue;
11783             }
11784
11785           /* Likewise if OP0 is a PLUS of a sign extension with a
11786              constant, which is usually represented with the PLUS
11787              between the shifts.  */
11788           if (! unsigned_comparison_p
11789               && CONST_INT_P (XEXP (op0, 1))
11790               && GET_CODE (XEXP (op0, 0)) == PLUS
11791               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11792               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11793               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11794               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11795                                          MODE_INT, 1)) != BLKmode
11796               && (((unsigned HOST_WIDE_INT) const_op
11797                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11798                   <= GET_MODE_MASK (tmode)))
11799             {
11800               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11801               rtx add_const = XEXP (XEXP (op0, 0), 1);
11802               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11803                                                    add_const, XEXP (op0, 1));
11804
11805               op0 = simplify_gen_binary (PLUS, tmode,
11806                                          gen_lowpart (tmode, inner),
11807                                          new_const);
11808               continue;
11809             }
11810
11811           /* ... fall through ...  */
11812         case LSHIFTRT:
11813           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11814              the low order N bits of FOO are known to be zero, we can do this
11815              by comparing FOO with C shifted left N bits so long as no
11816              overflow occurs.  Even if the low order N bits of FOO aren't known
11817              to be zero, if the comparison is >= or < we can use the same
11818              optimization and for > or <= by setting all the low
11819              order N bits in the comparison constant.  */
11820           if (CONST_INT_P (XEXP (op0, 1))
11821               && INTVAL (XEXP (op0, 1)) > 0
11822               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11823               && mode_width <= HOST_BITS_PER_WIDE_INT
11824               && (((unsigned HOST_WIDE_INT) const_op
11825                    + (GET_CODE (op0) != LSHIFTRT
11826                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11827                          + 1)
11828                       : 0))
11829                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11830             {
11831               unsigned HOST_WIDE_INT low_bits
11832                 = (nonzero_bits (XEXP (op0, 0), mode)
11833                    & (((unsigned HOST_WIDE_INT) 1
11834                        << INTVAL (XEXP (op0, 1))) - 1));
11835               if (low_bits == 0 || !equality_comparison_p)
11836                 {
11837                   /* If the shift was logical, then we must make the condition
11838                      unsigned.  */
11839                   if (GET_CODE (op0) == LSHIFTRT)
11840                     code = unsigned_condition (code);
11841
11842                   const_op <<= INTVAL (XEXP (op0, 1));
11843                   if (low_bits != 0
11844                       && (code == GT || code == GTU
11845                           || code == LE || code == LEU))
11846                     const_op
11847                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11848                   op1 = GEN_INT (const_op);
11849                   op0 = XEXP (op0, 0);
11850                   continue;
11851                 }
11852             }
11853
11854           /* If we are using this shift to extract just the sign bit, we
11855              can replace this with an LT or GE comparison.  */
11856           if (const_op == 0
11857               && (equality_comparison_p || sign_bit_comparison_p)
11858               && CONST_INT_P (XEXP (op0, 1))
11859               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11860             {
11861               op0 = XEXP (op0, 0);
11862               code = (code == NE || code == GT ? LT : GE);
11863               continue;
11864             }
11865           break;
11866
11867         default:
11868           break;
11869         }
11870
11871       break;
11872     }
11873
11874   /* Now make any compound operations involved in this comparison.  Then,
11875      check for an outmost SUBREG on OP0 that is not doing anything or is
11876      paradoxical.  The latter transformation must only be performed when
11877      it is known that the "extra" bits will be the same in op0 and op1 or
11878      that they don't matter.  There are three cases to consider:
11879
11880      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11881      care bits and we can assume they have any convenient value.  So
11882      making the transformation is safe.
11883
11884      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11885      In this case the upper bits of op0 are undefined.  We should not make
11886      the simplification in that case as we do not know the contents of
11887      those bits.
11888
11889      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11890      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11891      also be sure that they are the same as the upper bits of op1.
11892
11893      We can never remove a SUBREG for a non-equality comparison because
11894      the sign bit is in a different place in the underlying object.  */
11895
11896   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11897   op1 = make_compound_operation (op1, SET);
11898
11899   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11900       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11901       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11902       && (code == NE || code == EQ))
11903     {
11904       if (paradoxical_subreg_p (op0))
11905         {
11906           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11907              implemented.  */
11908           if (REG_P (SUBREG_REG (op0)))
11909             {
11910               op0 = SUBREG_REG (op0);
11911               op1 = gen_lowpart (GET_MODE (op0), op1);
11912             }
11913         }
11914       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11915                 <= HOST_BITS_PER_WIDE_INT)
11916                && (nonzero_bits (SUBREG_REG (op0),
11917                                  GET_MODE (SUBREG_REG (op0)))
11918                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11919         {
11920           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11921
11922           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11923                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11924             op0 = SUBREG_REG (op0), op1 = tem;
11925         }
11926     }
11927
11928   /* We now do the opposite procedure: Some machines don't have compare
11929      insns in all modes.  If OP0's mode is an integer mode smaller than a
11930      word and we can't do a compare in that mode, see if there is a larger
11931      mode for which we can do the compare.  There are a number of cases in
11932      which we can use the wider mode.  */
11933
11934   mode = GET_MODE (op0);
11935   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11936       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11937       && ! have_insn_for (COMPARE, mode))
11938     for (tmode = GET_MODE_WIDER_MODE (mode);
11939          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11940          tmode = GET_MODE_WIDER_MODE (tmode))
11941       if (have_insn_for (COMPARE, tmode))
11942         {
11943           int zero_extended;
11944
11945           /* If this is a test for negative, we can make an explicit
11946              test of the sign bit.  Test this first so we can use
11947              a paradoxical subreg to extend OP0.  */
11948
11949           if (op1 == const0_rtx && (code == LT || code == GE)
11950               && HWI_COMPUTABLE_MODE_P (mode))
11951             {
11952               unsigned HOST_WIDE_INT sign
11953                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
11954               op0 = simplify_gen_binary (AND, tmode,
11955                                          gen_lowpart (tmode, op0),
11956                                          gen_int_mode (sign, mode));
11957               code = (code == LT) ? NE : EQ;
11958               break;
11959             }
11960
11961           /* If the only nonzero bits in OP0 and OP1 are those in the
11962              narrower mode and this is an equality or unsigned comparison,
11963              we can use the wider mode.  Similarly for sign-extended
11964              values, in which case it is true for all comparisons.  */
11965           zero_extended = ((code == EQ || code == NE
11966                             || code == GEU || code == GTU
11967                             || code == LEU || code == LTU)
11968                            && (nonzero_bits (op0, tmode)
11969                                & ~GET_MODE_MASK (mode)) == 0
11970                            && ((CONST_INT_P (op1)
11971                                 || (nonzero_bits (op1, tmode)
11972                                     & ~GET_MODE_MASK (mode)) == 0)));
11973
11974           if (zero_extended
11975               || ((num_sign_bit_copies (op0, tmode)
11976                    > (unsigned int) (GET_MODE_PRECISION (tmode)
11977                                      - GET_MODE_PRECISION (mode)))
11978                   && (num_sign_bit_copies (op1, tmode)
11979                       > (unsigned int) (GET_MODE_PRECISION (tmode)
11980                                         - GET_MODE_PRECISION (mode)))))
11981             {
11982               /* If OP0 is an AND and we don't have an AND in MODE either,
11983                  make a new AND in the proper mode.  */
11984               if (GET_CODE (op0) == AND
11985                   && !have_insn_for (AND, mode))
11986                 op0 = simplify_gen_binary (AND, tmode,
11987                                            gen_lowpart (tmode,
11988                                                         XEXP (op0, 0)),
11989                                            gen_lowpart (tmode,
11990                                                         XEXP (op0, 1)));
11991               else
11992                 {
11993                   if (zero_extended)
11994                     {
11995                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11996                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11997                     }
11998                   else
11999                     {
12000                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12001                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12002                     }
12003                   break;
12004                 }
12005             }
12006         }
12007
12008   /* We may have changed the comparison operands.  Re-canonicalize.  */
12009   if (swap_commutative_operands_p (op0, op1))
12010     {
12011       tem = op0, op0 = op1, op1 = tem;
12012       code = swap_condition (code);
12013     }
12014
12015   /* If this machine only supports a subset of valid comparisons, see if we
12016      can convert an unsupported one into a supported one.  */
12017   target_canonicalize_comparison (&code, &op0, &op1, 0);
12018
12019   *pop0 = op0;
12020   *pop1 = op1;
12021
12022   return code;
12023 }
12024 \f
12025 /* Utility function for record_value_for_reg.  Count number of
12026    rtxs in X.  */
12027 static int
12028 count_rtxs (rtx x)
12029 {
12030   enum rtx_code code = GET_CODE (x);
12031   const char *fmt;
12032   int i, j, ret = 1;
12033
12034   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12035       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12036     {
12037       rtx x0 = XEXP (x, 0);
12038       rtx x1 = XEXP (x, 1);
12039
12040       if (x0 == x1)
12041         return 1 + 2 * count_rtxs (x0);
12042
12043       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12044            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12045           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12046         return 2 + 2 * count_rtxs (x0)
12047                + count_rtxs (x == XEXP (x1, 0)
12048                              ? XEXP (x1, 1) : XEXP (x1, 0));
12049
12050       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12051            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12052           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12053         return 2 + 2 * count_rtxs (x1)
12054                + count_rtxs (x == XEXP (x0, 0)
12055                              ? XEXP (x0, 1) : XEXP (x0, 0));
12056     }
12057
12058   fmt = GET_RTX_FORMAT (code);
12059   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12060     if (fmt[i] == 'e')
12061       ret += count_rtxs (XEXP (x, i));
12062     else if (fmt[i] == 'E')
12063       for (j = 0; j < XVECLEN (x, i); j++)
12064         ret += count_rtxs (XVECEXP (x, i, j));
12065
12066   return ret;
12067 }
12068 \f
12069 /* Utility function for following routine.  Called when X is part of a value
12070    being stored into last_set_value.  Sets last_set_table_tick
12071    for each register mentioned.  Similar to mention_regs in cse.c  */
12072
12073 static void
12074 update_table_tick (rtx x)
12075 {
12076   enum rtx_code code = GET_CODE (x);
12077   const char *fmt = GET_RTX_FORMAT (code);
12078   int i, j;
12079
12080   if (code == REG)
12081     {
12082       unsigned int regno = REGNO (x);
12083       unsigned int endregno = END_REGNO (x);
12084       unsigned int r;
12085
12086       for (r = regno; r < endregno; r++)
12087         {
12088           reg_stat_type *rsp = &reg_stat[r];
12089           rsp->last_set_table_tick = label_tick;
12090         }
12091
12092       return;
12093     }
12094
12095   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12096     if (fmt[i] == 'e')
12097       {
12098         /* Check for identical subexpressions.  If x contains
12099            identical subexpression we only have to traverse one of
12100            them.  */
12101         if (i == 0 && ARITHMETIC_P (x))
12102           {
12103             /* Note that at this point x1 has already been
12104                processed.  */
12105             rtx x0 = XEXP (x, 0);
12106             rtx x1 = XEXP (x, 1);
12107
12108             /* If x0 and x1 are identical then there is no need to
12109                process x0.  */
12110             if (x0 == x1)
12111               break;
12112
12113             /* If x0 is identical to a subexpression of x1 then while
12114                processing x1, x0 has already been processed.  Thus we
12115                are done with x.  */
12116             if (ARITHMETIC_P (x1)
12117                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12118               break;
12119
12120             /* If x1 is identical to a subexpression of x0 then we
12121                still have to process the rest of x0.  */
12122             if (ARITHMETIC_P (x0)
12123                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12124               {
12125                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12126                 break;
12127               }
12128           }
12129
12130         update_table_tick (XEXP (x, i));
12131       }
12132     else if (fmt[i] == 'E')
12133       for (j = 0; j < XVECLEN (x, i); j++)
12134         update_table_tick (XVECEXP (x, i, j));
12135 }
12136
12137 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12138    are saying that the register is clobbered and we no longer know its
12139    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12140    only permitted with VALUE also zero and is used to invalidate the
12141    register.  */
12142
12143 static void
12144 record_value_for_reg (rtx reg, rtx insn, rtx value)
12145 {
12146   unsigned int regno = REGNO (reg);
12147   unsigned int endregno = END_REGNO (reg);
12148   unsigned int i;
12149   reg_stat_type *rsp;
12150
12151   /* If VALUE contains REG and we have a previous value for REG, substitute
12152      the previous value.  */
12153   if (value && insn && reg_overlap_mentioned_p (reg, value))
12154     {
12155       rtx tem;
12156
12157       /* Set things up so get_last_value is allowed to see anything set up to
12158          our insn.  */
12159       subst_low_luid = DF_INSN_LUID (insn);
12160       tem = get_last_value (reg);
12161
12162       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12163          it isn't going to be useful and will take a lot of time to process,
12164          so just use the CLOBBER.  */
12165
12166       if (tem)
12167         {
12168           if (ARITHMETIC_P (tem)
12169               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12170               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12171             tem = XEXP (tem, 0);
12172           else if (count_occurrences (value, reg, 1) >= 2)
12173             {
12174               /* If there are two or more occurrences of REG in VALUE,
12175                  prevent the value from growing too much.  */
12176               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12177                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12178             }
12179
12180           value = replace_rtx (copy_rtx (value), reg, tem);
12181         }
12182     }
12183
12184   /* For each register modified, show we don't know its value, that
12185      we don't know about its bitwise content, that its value has been
12186      updated, and that we don't know the location of the death of the
12187      register.  */
12188   for (i = regno; i < endregno; i++)
12189     {
12190       rsp = &reg_stat[i];
12191
12192       if (insn)
12193         rsp->last_set = insn;
12194
12195       rsp->last_set_value = 0;
12196       rsp->last_set_mode = VOIDmode;
12197       rsp->last_set_nonzero_bits = 0;
12198       rsp->last_set_sign_bit_copies = 0;
12199       rsp->last_death = 0;
12200       rsp->truncated_to_mode = VOIDmode;
12201     }
12202
12203   /* Mark registers that are being referenced in this value.  */
12204   if (value)
12205     update_table_tick (value);
12206
12207   /* Now update the status of each register being set.
12208      If someone is using this register in this block, set this register
12209      to invalid since we will get confused between the two lives in this
12210      basic block.  This makes using this register always invalid.  In cse, we
12211      scan the table to invalidate all entries using this register, but this
12212      is too much work for us.  */
12213
12214   for (i = regno; i < endregno; i++)
12215     {
12216       rsp = &reg_stat[i];
12217       rsp->last_set_label = label_tick;
12218       if (!insn
12219           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12220         rsp->last_set_invalid = 1;
12221       else
12222         rsp->last_set_invalid = 0;
12223     }
12224
12225   /* The value being assigned might refer to X (like in "x++;").  In that
12226      case, we must replace it with (clobber (const_int 0)) to prevent
12227      infinite loops.  */
12228   rsp = &reg_stat[regno];
12229   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12230     {
12231       value = copy_rtx (value);
12232       if (!get_last_value_validate (&value, insn, label_tick, 1))
12233         value = 0;
12234     }
12235
12236   /* For the main register being modified, update the value, the mode, the
12237      nonzero bits, and the number of sign bit copies.  */
12238
12239   rsp->last_set_value = value;
12240
12241   if (value)
12242     {
12243       enum machine_mode mode = GET_MODE (reg);
12244       subst_low_luid = DF_INSN_LUID (insn);
12245       rsp->last_set_mode = mode;
12246       if (GET_MODE_CLASS (mode) == MODE_INT
12247           && HWI_COMPUTABLE_MODE_P (mode))
12248         mode = nonzero_bits_mode;
12249       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12250       rsp->last_set_sign_bit_copies
12251         = num_sign_bit_copies (value, GET_MODE (reg));
12252     }
12253 }
12254
12255 /* Called via note_stores from record_dead_and_set_regs to handle one
12256    SET or CLOBBER in an insn.  DATA is the instruction in which the
12257    set is occurring.  */
12258
12259 static void
12260 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12261 {
12262   rtx record_dead_insn = (rtx) data;
12263
12264   if (GET_CODE (dest) == SUBREG)
12265     dest = SUBREG_REG (dest);
12266
12267   if (!record_dead_insn)
12268     {
12269       if (REG_P (dest))
12270         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12271       return;
12272     }
12273
12274   if (REG_P (dest))
12275     {
12276       /* If we are setting the whole register, we know its value.  Otherwise
12277          show that we don't know the value.  We can handle SUBREG in
12278          some cases.  */
12279       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12280         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12281       else if (GET_CODE (setter) == SET
12282                && GET_CODE (SET_DEST (setter)) == SUBREG
12283                && SUBREG_REG (SET_DEST (setter)) == dest
12284                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12285                && subreg_lowpart_p (SET_DEST (setter)))
12286         record_value_for_reg (dest, record_dead_insn,
12287                               gen_lowpart (GET_MODE (dest),
12288                                                        SET_SRC (setter)));
12289       else
12290         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12291     }
12292   else if (MEM_P (dest)
12293            /* Ignore pushes, they clobber nothing.  */
12294            && ! push_operand (dest, GET_MODE (dest)))
12295     mem_last_set = DF_INSN_LUID (record_dead_insn);
12296 }
12297
12298 /* Update the records of when each REG was most recently set or killed
12299    for the things done by INSN.  This is the last thing done in processing
12300    INSN in the combiner loop.
12301
12302    We update reg_stat[], in particular fields last_set, last_set_value,
12303    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12304    last_death, and also the similar information mem_last_set (which insn
12305    most recently modified memory) and last_call_luid (which insn was the
12306    most recent subroutine call).  */
12307
12308 static void
12309 record_dead_and_set_regs (rtx insn)
12310 {
12311   rtx link;
12312   unsigned int i;
12313
12314   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12315     {
12316       if (REG_NOTE_KIND (link) == REG_DEAD
12317           && REG_P (XEXP (link, 0)))
12318         {
12319           unsigned int regno = REGNO (XEXP (link, 0));
12320           unsigned int endregno = END_REGNO (XEXP (link, 0));
12321
12322           for (i = regno; i < endregno; i++)
12323             {
12324               reg_stat_type *rsp;
12325
12326               rsp = &reg_stat[i];
12327               rsp->last_death = insn;
12328             }
12329         }
12330       else if (REG_NOTE_KIND (link) == REG_INC)
12331         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12332     }
12333
12334   if (CALL_P (insn))
12335     {
12336       hard_reg_set_iterator hrsi;
12337       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12338         {
12339           reg_stat_type *rsp;
12340
12341           rsp = &reg_stat[i];
12342           rsp->last_set_invalid = 1;
12343           rsp->last_set = insn;
12344           rsp->last_set_value = 0;
12345           rsp->last_set_mode = VOIDmode;
12346           rsp->last_set_nonzero_bits = 0;
12347           rsp->last_set_sign_bit_copies = 0;
12348           rsp->last_death = 0;
12349           rsp->truncated_to_mode = VOIDmode;
12350         }
12351
12352       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12353
12354       /* We can't combine into a call pattern.  Remember, though, that
12355          the return value register is set at this LUID.  We could
12356          still replace a register with the return value from the
12357          wrong subroutine call!  */
12358       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12359     }
12360   else
12361     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12362 }
12363
12364 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12365    register present in the SUBREG, so for each such SUBREG go back and
12366    adjust nonzero and sign bit information of the registers that are
12367    known to have some zero/sign bits set.
12368
12369    This is needed because when combine blows the SUBREGs away, the
12370    information on zero/sign bits is lost and further combines can be
12371    missed because of that.  */
12372
12373 static void
12374 record_promoted_value (rtx insn, rtx subreg)
12375 {
12376   struct insn_link *links;
12377   rtx set;
12378   unsigned int regno = REGNO (SUBREG_REG (subreg));
12379   enum machine_mode mode = GET_MODE (subreg);
12380
12381   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12382     return;
12383
12384   for (links = LOG_LINKS (insn); links;)
12385     {
12386       reg_stat_type *rsp;
12387
12388       insn = links->insn;
12389       set = single_set (insn);
12390
12391       if (! set || !REG_P (SET_DEST (set))
12392           || REGNO (SET_DEST (set)) != regno
12393           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12394         {
12395           links = links->next;
12396           continue;
12397         }
12398
12399       rsp = &reg_stat[regno];
12400       if (rsp->last_set == insn)
12401         {
12402           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12403             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12404         }
12405
12406       if (REG_P (SET_SRC (set)))
12407         {
12408           regno = REGNO (SET_SRC (set));
12409           links = LOG_LINKS (insn);
12410         }
12411       else
12412         break;
12413     }
12414 }
12415
12416 /* Check if X, a register, is known to contain a value already
12417    truncated to MODE.  In this case we can use a subreg to refer to
12418    the truncated value even though in the generic case we would need
12419    an explicit truncation.  */
12420
12421 static bool
12422 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12423 {
12424   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12425   enum machine_mode truncated = rsp->truncated_to_mode;
12426
12427   if (truncated == 0
12428       || rsp->truncation_label < label_tick_ebb_start)
12429     return false;
12430   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12431     return true;
12432   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12433     return true;
12434   return false;
12435 }
12436
12437 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12438    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12439    might be able to turn a truncate into a subreg using this information.
12440    Return -1 if traversing *P is complete or 0 otherwise.  */
12441
12442 static int
12443 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12444 {
12445   rtx x = *p;
12446   enum machine_mode truncated_mode;
12447   reg_stat_type *rsp;
12448
12449   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12450     {
12451       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12452       truncated_mode = GET_MODE (x);
12453
12454       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12455         return -1;
12456
12457       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12458         return -1;
12459
12460       x = SUBREG_REG (x);
12461     }
12462   /* ??? For hard-regs we now record everything.  We might be able to
12463      optimize this using last_set_mode.  */
12464   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12465     truncated_mode = GET_MODE (x);
12466   else
12467     return 0;
12468
12469   rsp = &reg_stat[REGNO (x)];
12470   if (rsp->truncated_to_mode == 0
12471       || rsp->truncation_label < label_tick_ebb_start
12472       || (GET_MODE_SIZE (truncated_mode)
12473           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12474     {
12475       rsp->truncated_to_mode = truncated_mode;
12476       rsp->truncation_label = label_tick;
12477     }
12478
12479   return -1;
12480 }
12481
12482 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12483    the modes they are used in.  This can help truning TRUNCATEs into
12484    SUBREGs.  */
12485
12486 static void
12487 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12488 {
12489   for_each_rtx (x, record_truncated_value, NULL);
12490 }
12491
12492 /* Scan X for promoted SUBREGs.  For each one found,
12493    note what it implies to the registers used in it.  */
12494
12495 static void
12496 check_promoted_subreg (rtx insn, rtx x)
12497 {
12498   if (GET_CODE (x) == SUBREG
12499       && SUBREG_PROMOTED_VAR_P (x)
12500       && REG_P (SUBREG_REG (x)))
12501     record_promoted_value (insn, x);
12502   else
12503     {
12504       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12505       int i, j;
12506
12507       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12508         switch (format[i])
12509           {
12510           case 'e':
12511             check_promoted_subreg (insn, XEXP (x, i));
12512             break;
12513           case 'V':
12514           case 'E':
12515             if (XVEC (x, i) != 0)
12516               for (j = 0; j < XVECLEN (x, i); j++)
12517                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12518             break;
12519           }
12520     }
12521 }
12522 \f
12523 /* Verify that all the registers and memory references mentioned in *LOC are
12524    still valid.  *LOC was part of a value set in INSN when label_tick was
12525    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12526    the invalid references with (clobber (const_int 0)) and return 1.  This
12527    replacement is useful because we often can get useful information about
12528    the form of a value (e.g., if it was produced by a shift that always
12529    produces -1 or 0) even though we don't know exactly what registers it
12530    was produced from.  */
12531
12532 static int
12533 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12534 {
12535   rtx x = *loc;
12536   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12537   int len = GET_RTX_LENGTH (GET_CODE (x));
12538   int i, j;
12539
12540   if (REG_P (x))
12541     {
12542       unsigned int regno = REGNO (x);
12543       unsigned int endregno = END_REGNO (x);
12544       unsigned int j;
12545
12546       for (j = regno; j < endregno; j++)
12547         {
12548           reg_stat_type *rsp = &reg_stat[j];
12549           if (rsp->last_set_invalid
12550               /* If this is a pseudo-register that was only set once and not
12551                  live at the beginning of the function, it is always valid.  */
12552               || (! (regno >= FIRST_PSEUDO_REGISTER
12553                      && REG_N_SETS (regno) == 1
12554                      && (!REGNO_REG_SET_P
12555                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12556                   && rsp->last_set_label > tick))
12557           {
12558             if (replace)
12559               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12560             return replace;
12561           }
12562         }
12563
12564       return 1;
12565     }
12566   /* If this is a memory reference, make sure that there were no stores after
12567      it that might have clobbered the value.  We don't have alias info, so we
12568      assume any store invalidates it.  Moreover, we only have local UIDs, so
12569      we also assume that there were stores in the intervening basic blocks.  */
12570   else if (MEM_P (x) && !MEM_READONLY_P (x)
12571            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12572     {
12573       if (replace)
12574         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12575       return replace;
12576     }
12577
12578   for (i = 0; i < len; i++)
12579     {
12580       if (fmt[i] == 'e')
12581         {
12582           /* Check for identical subexpressions.  If x contains
12583              identical subexpression we only have to traverse one of
12584              them.  */
12585           if (i == 1 && ARITHMETIC_P (x))
12586             {
12587               /* Note that at this point x0 has already been checked
12588                  and found valid.  */
12589               rtx x0 = XEXP (x, 0);
12590               rtx x1 = XEXP (x, 1);
12591
12592               /* If x0 and x1 are identical then x is also valid.  */
12593               if (x0 == x1)
12594                 return 1;
12595
12596               /* If x1 is identical to a subexpression of x0 then
12597                  while checking x0, x1 has already been checked.  Thus
12598                  it is valid and so as x.  */
12599               if (ARITHMETIC_P (x0)
12600                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12601                 return 1;
12602
12603               /* If x0 is identical to a subexpression of x1 then x is
12604                  valid iff the rest of x1 is valid.  */
12605               if (ARITHMETIC_P (x1)
12606                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12607                 return
12608                   get_last_value_validate (&XEXP (x1,
12609                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12610                                            insn, tick, replace);
12611             }
12612
12613           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12614                                        replace) == 0)
12615             return 0;
12616         }
12617       else if (fmt[i] == 'E')
12618         for (j = 0; j < XVECLEN (x, i); j++)
12619           if (get_last_value_validate (&XVECEXP (x, i, j),
12620                                        insn, tick, replace) == 0)
12621             return 0;
12622     }
12623
12624   /* If we haven't found a reason for it to be invalid, it is valid.  */
12625   return 1;
12626 }
12627
12628 /* Get the last value assigned to X, if known.  Some registers
12629    in the value may be replaced with (clobber (const_int 0)) if their value
12630    is known longer known reliably.  */
12631
12632 static rtx
12633 get_last_value (const_rtx x)
12634 {
12635   unsigned int regno;
12636   rtx value;
12637   reg_stat_type *rsp;
12638
12639   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12640      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12641      we cannot predict what values the "extra" bits might have.  */
12642   if (GET_CODE (x) == SUBREG
12643       && subreg_lowpart_p (x)
12644       && !paradoxical_subreg_p (x)
12645       && (value = get_last_value (SUBREG_REG (x))) != 0)
12646     return gen_lowpart (GET_MODE (x), value);
12647
12648   if (!REG_P (x))
12649     return 0;
12650
12651   regno = REGNO (x);
12652   rsp = &reg_stat[regno];
12653   value = rsp->last_set_value;
12654
12655   /* If we don't have a value, or if it isn't for this basic block and
12656      it's either a hard register, set more than once, or it's a live
12657      at the beginning of the function, return 0.
12658
12659      Because if it's not live at the beginning of the function then the reg
12660      is always set before being used (is never used without being set).
12661      And, if it's set only once, and it's always set before use, then all
12662      uses must have the same last value, even if it's not from this basic
12663      block.  */
12664
12665   if (value == 0
12666       || (rsp->last_set_label < label_tick_ebb_start
12667           && (regno < FIRST_PSEUDO_REGISTER
12668               || REG_N_SETS (regno) != 1
12669               || REGNO_REG_SET_P
12670                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12671     return 0;
12672
12673   /* If the value was set in a later insn than the ones we are processing,
12674      we can't use it even if the register was only set once.  */
12675   if (rsp->last_set_label == label_tick
12676       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12677     return 0;
12678
12679   /* If the value has all its registers valid, return it.  */
12680   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12681     return value;
12682
12683   /* Otherwise, make a copy and replace any invalid register with
12684      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12685
12686   value = copy_rtx (value);
12687   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12688     return value;
12689
12690   return 0;
12691 }
12692 \f
12693 /* Return nonzero if expression X refers to a REG or to memory
12694    that is set in an instruction more recent than FROM_LUID.  */
12695
12696 static int
12697 use_crosses_set_p (const_rtx x, int from_luid)
12698 {
12699   const char *fmt;
12700   int i;
12701   enum rtx_code code = GET_CODE (x);
12702
12703   if (code == REG)
12704     {
12705       unsigned int regno = REGNO (x);
12706       unsigned endreg = END_REGNO (x);
12707
12708 #ifdef PUSH_ROUNDING
12709       /* Don't allow uses of the stack pointer to be moved,
12710          because we don't know whether the move crosses a push insn.  */
12711       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12712         return 1;
12713 #endif
12714       for (; regno < endreg; regno++)
12715         {
12716           reg_stat_type *rsp = &reg_stat[regno];
12717           if (rsp->last_set
12718               && rsp->last_set_label == label_tick
12719               && DF_INSN_LUID (rsp->last_set) > from_luid)
12720             return 1;
12721         }
12722       return 0;
12723     }
12724
12725   if (code == MEM && mem_last_set > from_luid)
12726     return 1;
12727
12728   fmt = GET_RTX_FORMAT (code);
12729
12730   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12731     {
12732       if (fmt[i] == 'E')
12733         {
12734           int j;
12735           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12736             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12737               return 1;
12738         }
12739       else if (fmt[i] == 'e'
12740                && use_crosses_set_p (XEXP (x, i), from_luid))
12741         return 1;
12742     }
12743   return 0;
12744 }
12745 \f
12746 /* Define three variables used for communication between the following
12747    routines.  */
12748
12749 static unsigned int reg_dead_regno, reg_dead_endregno;
12750 static int reg_dead_flag;
12751
12752 /* Function called via note_stores from reg_dead_at_p.
12753
12754    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12755    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12756
12757 static void
12758 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12759 {
12760   unsigned int regno, endregno;
12761
12762   if (!REG_P (dest))
12763     return;
12764
12765   regno = REGNO (dest);
12766   endregno = END_REGNO (dest);
12767   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12768     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12769 }
12770
12771 /* Return nonzero if REG is known to be dead at INSN.
12772
12773    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12774    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12775    live.  Otherwise, see if it is live or dead at the start of the basic
12776    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12777    must be assumed to be always live.  */
12778
12779 static int
12780 reg_dead_at_p (rtx reg, rtx insn)
12781 {
12782   basic_block block;
12783   unsigned int i;
12784
12785   /* Set variables for reg_dead_at_p_1.  */
12786   reg_dead_regno = REGNO (reg);
12787   reg_dead_endregno = END_REGNO (reg);
12788
12789   reg_dead_flag = 0;
12790
12791   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12792      we allow the machine description to decide whether use-and-clobber
12793      patterns are OK.  */
12794   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12795     {
12796       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12797         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12798           return 0;
12799     }
12800
12801   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12802      beginning of basic block.  */
12803   block = BLOCK_FOR_INSN (insn);
12804   for (;;)
12805     {
12806       if (INSN_P (insn))
12807         {
12808           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12809           if (reg_dead_flag)
12810             return reg_dead_flag == 1 ? 1 : 0;
12811
12812           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12813             return 1;
12814         }
12815
12816       if (insn == BB_HEAD (block))
12817         break;
12818
12819       insn = PREV_INSN (insn);
12820     }
12821
12822   /* Look at live-in sets for the basic block that we were in.  */
12823   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12824     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12825       return 0;
12826
12827   return 1;
12828 }
12829 \f
12830 /* Note hard registers in X that are used.  */
12831
12832 static void
12833 mark_used_regs_combine (rtx x)
12834 {
12835   RTX_CODE code = GET_CODE (x);
12836   unsigned int regno;
12837   int i;
12838
12839   switch (code)
12840     {
12841     case LABEL_REF:
12842     case SYMBOL_REF:
12843     case CONST:
12844     CASE_CONST_ANY:
12845     case PC:
12846     case ADDR_VEC:
12847     case ADDR_DIFF_VEC:
12848     case ASM_INPUT:
12849 #ifdef HAVE_cc0
12850     /* CC0 must die in the insn after it is set, so we don't need to take
12851        special note of it here.  */
12852     case CC0:
12853 #endif
12854       return;
12855
12856     case CLOBBER:
12857       /* If we are clobbering a MEM, mark any hard registers inside the
12858          address as used.  */
12859       if (MEM_P (XEXP (x, 0)))
12860         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12861       return;
12862
12863     case REG:
12864       regno = REGNO (x);
12865       /* A hard reg in a wide mode may really be multiple registers.
12866          If so, mark all of them just like the first.  */
12867       if (regno < FIRST_PSEUDO_REGISTER)
12868         {
12869           /* None of this applies to the stack, frame or arg pointers.  */
12870           if (regno == STACK_POINTER_REGNUM
12871 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12872               || regno == HARD_FRAME_POINTER_REGNUM
12873 #endif
12874 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12875               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12876 #endif
12877               || regno == FRAME_POINTER_REGNUM)
12878             return;
12879
12880           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12881         }
12882       return;
12883
12884     case SET:
12885       {
12886         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12887            the address.  */
12888         rtx testreg = SET_DEST (x);
12889
12890         while (GET_CODE (testreg) == SUBREG
12891                || GET_CODE (testreg) == ZERO_EXTRACT
12892                || GET_CODE (testreg) == STRICT_LOW_PART)
12893           testreg = XEXP (testreg, 0);
12894
12895         if (MEM_P (testreg))
12896           mark_used_regs_combine (XEXP (testreg, 0));
12897
12898         mark_used_regs_combine (SET_SRC (x));
12899       }
12900       return;
12901
12902     default:
12903       break;
12904     }
12905
12906   /* Recursively scan the operands of this expression.  */
12907
12908   {
12909     const char *fmt = GET_RTX_FORMAT (code);
12910
12911     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12912       {
12913         if (fmt[i] == 'e')
12914           mark_used_regs_combine (XEXP (x, i));
12915         else if (fmt[i] == 'E')
12916           {
12917             int j;
12918
12919             for (j = 0; j < XVECLEN (x, i); j++)
12920               mark_used_regs_combine (XVECEXP (x, i, j));
12921           }
12922       }
12923   }
12924 }
12925 \f
12926 /* Remove register number REGNO from the dead registers list of INSN.
12927
12928    Return the note used to record the death, if there was one.  */
12929
12930 rtx
12931 remove_death (unsigned int regno, rtx insn)
12932 {
12933   rtx note = find_regno_note (insn, REG_DEAD, regno);
12934
12935   if (note)
12936     remove_note (insn, note);
12937
12938   return note;
12939 }
12940
12941 /* For each register (hardware or pseudo) used within expression X, if its
12942    death is in an instruction with luid between FROM_LUID (inclusive) and
12943    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12944    list headed by PNOTES.
12945
12946    That said, don't move registers killed by maybe_kill_insn.
12947
12948    This is done when X is being merged by combination into TO_INSN.  These
12949    notes will then be distributed as needed.  */
12950
12951 static void
12952 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12953              rtx *pnotes)
12954 {
12955   const char *fmt;
12956   int len, i;
12957   enum rtx_code code = GET_CODE (x);
12958
12959   if (code == REG)
12960     {
12961       unsigned int regno = REGNO (x);
12962       rtx where_dead = reg_stat[regno].last_death;
12963
12964       /* Don't move the register if it gets killed in between from and to.  */
12965       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12966           && ! reg_referenced_p (x, maybe_kill_insn))
12967         return;
12968
12969       if (where_dead
12970           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12971           && DF_INSN_LUID (where_dead) >= from_luid
12972           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12973         {
12974           rtx note = remove_death (regno, where_dead);
12975
12976           /* It is possible for the call above to return 0.  This can occur
12977              when last_death points to I2 or I1 that we combined with.
12978              In that case make a new note.
12979
12980              We must also check for the case where X is a hard register
12981              and NOTE is a death note for a range of hard registers
12982              including X.  In that case, we must put REG_DEAD notes for
12983              the remaining registers in place of NOTE.  */
12984
12985           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12986               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12987                   > GET_MODE_SIZE (GET_MODE (x))))
12988             {
12989               unsigned int deadregno = REGNO (XEXP (note, 0));
12990               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12991               unsigned int ourend = END_HARD_REGNO (x);
12992               unsigned int i;
12993
12994               for (i = deadregno; i < deadend; i++)
12995                 if (i < regno || i >= ourend)
12996                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12997             }
12998
12999           /* If we didn't find any note, or if we found a REG_DEAD note that
13000              covers only part of the given reg, and we have a multi-reg hard
13001              register, then to be safe we must check for REG_DEAD notes
13002              for each register other than the first.  They could have
13003              their own REG_DEAD notes lying around.  */
13004           else if ((note == 0
13005                     || (note != 0
13006                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13007                             < GET_MODE_SIZE (GET_MODE (x)))))
13008                    && regno < FIRST_PSEUDO_REGISTER
13009                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13010             {
13011               unsigned int ourend = END_HARD_REGNO (x);
13012               unsigned int i, offset;
13013               rtx oldnotes = 0;
13014
13015               if (note)
13016                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13017               else
13018                 offset = 1;
13019
13020               for (i = regno + offset; i < ourend; i++)
13021                 move_deaths (regno_reg_rtx[i],
13022                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13023             }
13024
13025           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13026             {
13027               XEXP (note, 1) = *pnotes;
13028               *pnotes = note;
13029             }
13030           else
13031             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13032         }
13033
13034       return;
13035     }
13036
13037   else if (GET_CODE (x) == SET)
13038     {
13039       rtx dest = SET_DEST (x);
13040
13041       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13042
13043       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13044          that accesses one word of a multi-word item, some
13045          piece of everything register in the expression is used by
13046          this insn, so remove any old death.  */
13047       /* ??? So why do we test for equality of the sizes?  */
13048
13049       if (GET_CODE (dest) == ZERO_EXTRACT
13050           || GET_CODE (dest) == STRICT_LOW_PART
13051           || (GET_CODE (dest) == SUBREG
13052               && (((GET_MODE_SIZE (GET_MODE (dest))
13053                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13054                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13055                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13056         {
13057           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13058           return;
13059         }
13060
13061       /* If this is some other SUBREG, we know it replaces the entire
13062          value, so use that as the destination.  */
13063       if (GET_CODE (dest) == SUBREG)
13064         dest = SUBREG_REG (dest);
13065
13066       /* If this is a MEM, adjust deaths of anything used in the address.
13067          For a REG (the only other possibility), the entire value is
13068          being replaced so the old value is not used in this insn.  */
13069
13070       if (MEM_P (dest))
13071         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13072                      to_insn, pnotes);
13073       return;
13074     }
13075
13076   else if (GET_CODE (x) == CLOBBER)
13077     return;
13078
13079   len = GET_RTX_LENGTH (code);
13080   fmt = GET_RTX_FORMAT (code);
13081
13082   for (i = 0; i < len; i++)
13083     {
13084       if (fmt[i] == 'E')
13085         {
13086           int j;
13087           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13088             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13089                          to_insn, pnotes);
13090         }
13091       else if (fmt[i] == 'e')
13092         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13093     }
13094 }
13095 \f
13096 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13097    pattern of an insn.  X must be a REG.  */
13098
13099 static int
13100 reg_bitfield_target_p (rtx x, rtx body)
13101 {
13102   int i;
13103
13104   if (GET_CODE (body) == SET)
13105     {
13106       rtx dest = SET_DEST (body);
13107       rtx target;
13108       unsigned int regno, tregno, endregno, endtregno;
13109
13110       if (GET_CODE (dest) == ZERO_EXTRACT)
13111         target = XEXP (dest, 0);
13112       else if (GET_CODE (dest) == STRICT_LOW_PART)
13113         target = SUBREG_REG (XEXP (dest, 0));
13114       else
13115         return 0;
13116
13117       if (GET_CODE (target) == SUBREG)
13118         target = SUBREG_REG (target);
13119
13120       if (!REG_P (target))
13121         return 0;
13122
13123       tregno = REGNO (target), regno = REGNO (x);
13124       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13125         return target == x;
13126
13127       endtregno = end_hard_regno (GET_MODE (target), tregno);
13128       endregno = end_hard_regno (GET_MODE (x), regno);
13129
13130       return endregno > tregno && regno < endtregno;
13131     }
13132
13133   else if (GET_CODE (body) == PARALLEL)
13134     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13135       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13136         return 1;
13137
13138   return 0;
13139 }
13140 \f
13141 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13142    as appropriate.  I3 and I2 are the insns resulting from the combination
13143    insns including FROM (I2 may be zero).
13144
13145    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13146    not need REG_DEAD notes because they are being substituted for.  This
13147    saves searching in the most common cases.
13148
13149    Each note in the list is either ignored or placed on some insns, depending
13150    on the type of note.  */
13151
13152 static void
13153 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13154                   rtx elim_i1, rtx elim_i0)
13155 {
13156   rtx note, next_note;
13157   rtx tem;
13158
13159   for (note = notes; note; note = next_note)
13160     {
13161       rtx place = 0, place2 = 0;
13162
13163       next_note = XEXP (note, 1);
13164       switch (REG_NOTE_KIND (note))
13165         {
13166         case REG_BR_PROB:
13167         case REG_BR_PRED:
13168           /* Doesn't matter much where we put this, as long as it's somewhere.
13169              It is preferable to keep these notes on branches, which is most
13170              likely to be i3.  */
13171           place = i3;
13172           break;
13173
13174         case REG_NON_LOCAL_GOTO:
13175           if (JUMP_P (i3))
13176             place = i3;
13177           else
13178             {
13179               gcc_assert (i2 && JUMP_P (i2));
13180               place = i2;
13181             }
13182           break;
13183
13184         case REG_EH_REGION:
13185           /* These notes must remain with the call or trapping instruction.  */
13186           if (CALL_P (i3))
13187             place = i3;
13188           else if (i2 && CALL_P (i2))
13189             place = i2;
13190           else
13191             {
13192               gcc_assert (cfun->can_throw_non_call_exceptions);
13193               if (may_trap_p (i3))
13194                 place = i3;
13195               else if (i2 && may_trap_p (i2))
13196                 place = i2;
13197               /* ??? Otherwise assume we've combined things such that we
13198                  can now prove that the instructions can't trap.  Drop the
13199                  note in this case.  */
13200             }
13201           break;
13202
13203         case REG_ARGS_SIZE:
13204           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13205              entire adjustment.  Assert i3 contains at least some adjust.  */
13206           if (!noop_move_p (i3))
13207             {
13208               int old_size, args_size = INTVAL (XEXP (note, 0));
13209               /* fixup_args_size_notes looks at REG_NORETURN note,
13210                  so ensure the note is placed there first.  */
13211               if (CALL_P (i3))
13212                 {
13213                   rtx *np;
13214                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13215                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13216                       {
13217                         rtx n = *np;
13218                         *np = XEXP (n, 1);
13219                         XEXP (n, 1) = REG_NOTES (i3);
13220                         REG_NOTES (i3) = n;
13221                         break;
13222                       }
13223                 }
13224               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13225               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13226                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13227               gcc_assert (old_size != args_size
13228                           || (CALL_P (i3)
13229                               && !ACCUMULATE_OUTGOING_ARGS
13230                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13231             }
13232           break;
13233
13234         case REG_NORETURN:
13235         case REG_SETJMP:
13236         case REG_TM:
13237           /* These notes must remain with the call.  It should not be
13238              possible for both I2 and I3 to be a call.  */
13239           if (CALL_P (i3))
13240             place = i3;
13241           else
13242             {
13243               gcc_assert (i2 && CALL_P (i2));
13244               place = i2;
13245             }
13246           break;
13247
13248         case REG_UNUSED:
13249           /* Any clobbers for i3 may still exist, and so we must process
13250              REG_UNUSED notes from that insn.
13251
13252              Any clobbers from i2 or i1 can only exist if they were added by
13253              recog_for_combine.  In that case, recog_for_combine created the
13254              necessary REG_UNUSED notes.  Trying to keep any original
13255              REG_UNUSED notes from these insns can cause incorrect output
13256              if it is for the same register as the original i3 dest.
13257              In that case, we will notice that the register is set in i3,
13258              and then add a REG_UNUSED note for the destination of i3, which
13259              is wrong.  However, it is possible to have REG_UNUSED notes from
13260              i2 or i1 for register which were both used and clobbered, so
13261              we keep notes from i2 or i1 if they will turn into REG_DEAD
13262              notes.  */
13263
13264           /* If this register is set or clobbered in I3, put the note there
13265              unless there is one already.  */
13266           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13267             {
13268               if (from_insn != i3)
13269                 break;
13270
13271               if (! (REG_P (XEXP (note, 0))
13272                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13273                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13274                 place = i3;
13275             }
13276           /* Otherwise, if this register is used by I3, then this register
13277              now dies here, so we must put a REG_DEAD note here unless there
13278              is one already.  */
13279           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13280                    && ! (REG_P (XEXP (note, 0))
13281                          ? find_regno_note (i3, REG_DEAD,
13282                                             REGNO (XEXP (note, 0)))
13283                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13284             {
13285               PUT_REG_NOTE_KIND (note, REG_DEAD);
13286               place = i3;
13287             }
13288           break;
13289
13290         case REG_EQUAL:
13291         case REG_EQUIV:
13292         case REG_NOALIAS:
13293           /* These notes say something about results of an insn.  We can
13294              only support them if they used to be on I3 in which case they
13295              remain on I3.  Otherwise they are ignored.
13296
13297              If the note refers to an expression that is not a constant, we
13298              must also ignore the note since we cannot tell whether the
13299              equivalence is still true.  It might be possible to do
13300              slightly better than this (we only have a problem if I2DEST
13301              or I1DEST is present in the expression), but it doesn't
13302              seem worth the trouble.  */
13303
13304           if (from_insn == i3
13305               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13306             place = i3;
13307           break;
13308
13309         case REG_INC:
13310           /* These notes say something about how a register is used.  They must
13311              be present on any use of the register in I2 or I3.  */
13312           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13313             place = i3;
13314
13315           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13316             {
13317               if (place)
13318                 place2 = i2;
13319               else
13320                 place = i2;
13321             }
13322           break;
13323
13324         case REG_LABEL_TARGET:
13325         case REG_LABEL_OPERAND:
13326           /* This can show up in several ways -- either directly in the
13327              pattern, or hidden off in the constant pool with (or without?)
13328              a REG_EQUAL note.  */
13329           /* ??? Ignore the without-reg_equal-note problem for now.  */
13330           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13331               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13332                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13333                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13334             place = i3;
13335
13336           if (i2
13337               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13338                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13339                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13340                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13341             {
13342               if (place)
13343                 place2 = i2;
13344               else
13345                 place = i2;
13346             }
13347
13348           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13349              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13350              there.  */
13351           if (place && JUMP_P (place)
13352               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13353               && (JUMP_LABEL (place) == NULL
13354                   || JUMP_LABEL (place) == XEXP (note, 0)))
13355             {
13356               rtx label = JUMP_LABEL (place);
13357
13358               if (!label)
13359                 JUMP_LABEL (place) = XEXP (note, 0);
13360               else if (LABEL_P (label))
13361                 LABEL_NUSES (label)--;
13362             }
13363
13364           if (place2 && JUMP_P (place2)
13365               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13366               && (JUMP_LABEL (place2) == NULL
13367                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13368             {
13369               rtx label = JUMP_LABEL (place2);
13370
13371               if (!label)
13372                 JUMP_LABEL (place2) = XEXP (note, 0);
13373               else if (LABEL_P (label))
13374                 LABEL_NUSES (label)--;
13375               place2 = 0;
13376             }
13377           break;
13378
13379         case REG_NONNEG:
13380           /* This note says something about the value of a register prior
13381              to the execution of an insn.  It is too much trouble to see
13382              if the note is still correct in all situations.  It is better
13383              to simply delete it.  */
13384           break;
13385
13386         case REG_DEAD:
13387           /* If we replaced the right hand side of FROM_INSN with a
13388              REG_EQUAL note, the original use of the dying register
13389              will not have been combined into I3 and I2.  In such cases,
13390              FROM_INSN is guaranteed to be the first of the combined
13391              instructions, so we simply need to search back before
13392              FROM_INSN for the previous use or set of this register,
13393              then alter the notes there appropriately.
13394
13395              If the register is used as an input in I3, it dies there.
13396              Similarly for I2, if it is nonzero and adjacent to I3.
13397
13398              If the register is not used as an input in either I3 or I2
13399              and it is not one of the registers we were supposed to eliminate,
13400              there are two possibilities.  We might have a non-adjacent I2
13401              or we might have somehow eliminated an additional register
13402              from a computation.  For example, we might have had A & B where
13403              we discover that B will always be zero.  In this case we will
13404              eliminate the reference to A.
13405
13406              In both cases, we must search to see if we can find a previous
13407              use of A and put the death note there.  */
13408
13409           if (from_insn
13410               && from_insn == i2mod
13411               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13412             tem = from_insn;
13413           else
13414             {
13415               if (from_insn
13416                   && CALL_P (from_insn)
13417                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13418                 place = from_insn;
13419               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13420                 place = i3;
13421               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13422                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13423                 place = i2;
13424               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13425                         && !(i2mod
13426                              && reg_overlap_mentioned_p (XEXP (note, 0),
13427                                                          i2mod_old_rhs)))
13428                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13429                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13430                 break;
13431               tem = i3;
13432             }
13433
13434           if (place == 0)
13435             {
13436               basic_block bb = this_basic_block;
13437
13438               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13439                 {
13440                   if (!NONDEBUG_INSN_P (tem))
13441                     {
13442                       if (tem == BB_HEAD (bb))
13443                         break;
13444                       continue;
13445                     }
13446
13447                   /* If the register is being set at TEM, see if that is all
13448                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13449                      into a REG_UNUSED note instead. Don't delete sets to
13450                      global register vars.  */
13451                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13452                        || !global_regs[REGNO (XEXP (note, 0))])
13453                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13454                     {
13455                       rtx set = single_set (tem);
13456                       rtx inner_dest = 0;
13457 #ifdef HAVE_cc0
13458                       rtx cc0_setter = NULL_RTX;
13459 #endif
13460
13461                       if (set != 0)
13462                         for (inner_dest = SET_DEST (set);
13463                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13464                               || GET_CODE (inner_dest) == SUBREG
13465                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13466                              inner_dest = XEXP (inner_dest, 0))
13467                           ;
13468
13469                       /* Verify that it was the set, and not a clobber that
13470                          modified the register.
13471
13472                          CC0 targets must be careful to maintain setter/user
13473                          pairs.  If we cannot delete the setter due to side
13474                          effects, mark the user with an UNUSED note instead
13475                          of deleting it.  */
13476
13477                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13478                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13479 #ifdef HAVE_cc0
13480                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13481                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13482                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13483 #endif
13484                           )
13485                         {
13486                           /* Move the notes and links of TEM elsewhere.
13487                              This might delete other dead insns recursively.
13488                              First set the pattern to something that won't use
13489                              any register.  */
13490                           rtx old_notes = REG_NOTES (tem);
13491
13492                           PATTERN (tem) = pc_rtx;
13493                           REG_NOTES (tem) = NULL;
13494
13495                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13496                                             NULL_RTX, NULL_RTX, NULL_RTX);
13497                           distribute_links (LOG_LINKS (tem));
13498
13499                           SET_INSN_DELETED (tem);
13500                           if (tem == i2)
13501                             i2 = NULL_RTX;
13502
13503 #ifdef HAVE_cc0
13504                           /* Delete the setter too.  */
13505                           if (cc0_setter)
13506                             {
13507                               PATTERN (cc0_setter) = pc_rtx;
13508                               old_notes = REG_NOTES (cc0_setter);
13509                               REG_NOTES (cc0_setter) = NULL;
13510
13511                               distribute_notes (old_notes, cc0_setter,
13512                                                 cc0_setter, NULL_RTX,
13513                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13514                               distribute_links (LOG_LINKS (cc0_setter));
13515
13516                               SET_INSN_DELETED (cc0_setter);
13517                               if (cc0_setter == i2)
13518                                 i2 = NULL_RTX;
13519                             }
13520 #endif
13521                         }
13522                       else
13523                         {
13524                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13525
13526                           /*  If there isn't already a REG_UNUSED note, put one
13527                               here.  Do not place a REG_DEAD note, even if
13528                               the register is also used here; that would not
13529                               match the algorithm used in lifetime analysis
13530                               and can cause the consistency check in the
13531                               scheduler to fail.  */
13532                           if (! find_regno_note (tem, REG_UNUSED,
13533                                                  REGNO (XEXP (note, 0))))
13534                             place = tem;
13535                           break;
13536                         }
13537                     }
13538                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13539                            || (CALL_P (tem)
13540                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13541                     {
13542                       place = tem;
13543
13544                       /* If we are doing a 3->2 combination, and we have a
13545                          register which formerly died in i3 and was not used
13546                          by i2, which now no longer dies in i3 and is used in
13547                          i2 but does not die in i2, and place is between i2
13548                          and i3, then we may need to move a link from place to
13549                          i2.  */
13550                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13551                           && from_insn
13552                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13553                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13554                         {
13555                           struct insn_link *links = LOG_LINKS (place);
13556                           LOG_LINKS (place) = NULL;
13557                           distribute_links (links);
13558                         }
13559                       break;
13560                     }
13561
13562                   if (tem == BB_HEAD (bb))
13563                     break;
13564                 }
13565
13566             }
13567
13568           /* If the register is set or already dead at PLACE, we needn't do
13569              anything with this note if it is still a REG_DEAD note.
13570              We check here if it is set at all, not if is it totally replaced,
13571              which is what `dead_or_set_p' checks, so also check for it being
13572              set partially.  */
13573
13574           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13575             {
13576               unsigned int regno = REGNO (XEXP (note, 0));
13577               reg_stat_type *rsp = &reg_stat[regno];
13578
13579               if (dead_or_set_p (place, XEXP (note, 0))
13580                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13581                 {
13582                   /* Unless the register previously died in PLACE, clear
13583                      last_death.  [I no longer understand why this is
13584                      being done.] */
13585                   if (rsp->last_death != place)
13586                     rsp->last_death = 0;
13587                   place = 0;
13588                 }
13589               else
13590                 rsp->last_death = place;
13591
13592               /* If this is a death note for a hard reg that is occupying
13593                  multiple registers, ensure that we are still using all
13594                  parts of the object.  If we find a piece of the object
13595                  that is unused, we must arrange for an appropriate REG_DEAD
13596                  note to be added for it.  However, we can't just emit a USE
13597                  and tag the note to it, since the register might actually
13598                  be dead; so we recourse, and the recursive call then finds
13599                  the previous insn that used this register.  */
13600
13601               if (place && regno < FIRST_PSEUDO_REGISTER
13602                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13603                 {
13604                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13605                   bool all_used = true;
13606                   unsigned int i;
13607
13608                   for (i = regno; i < endregno; i++)
13609                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13610                          && ! find_regno_fusage (place, USE, i))
13611                         || dead_or_set_regno_p (place, i))
13612                       {
13613                         all_used = false;
13614                         break;
13615                       }
13616
13617                   if (! all_used)
13618                     {
13619                       /* Put only REG_DEAD notes for pieces that are
13620                          not already dead or set.  */
13621
13622                       for (i = regno; i < endregno;
13623                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13624                         {
13625                           rtx piece = regno_reg_rtx[i];
13626                           basic_block bb = this_basic_block;
13627
13628                           if (! dead_or_set_p (place, piece)
13629                               && ! reg_bitfield_target_p (piece,
13630                                                           PATTERN (place)))
13631                             {
13632                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13633                                                              NULL_RTX);
13634
13635                               distribute_notes (new_note, place, place,
13636                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13637                                                 NULL_RTX);
13638                             }
13639                           else if (! refers_to_regno_p (i, i + 1,
13640                                                         PATTERN (place), 0)
13641                                    && ! find_regno_fusage (place, USE, i))
13642                             for (tem = PREV_INSN (place); ;
13643                                  tem = PREV_INSN (tem))
13644                               {
13645                                 if (!NONDEBUG_INSN_P (tem))
13646                                   {
13647                                     if (tem == BB_HEAD (bb))
13648                                       break;
13649                                     continue;
13650                                   }
13651                                 if (dead_or_set_p (tem, piece)
13652                                     || reg_bitfield_target_p (piece,
13653                                                               PATTERN (tem)))
13654                                   {
13655                                     add_reg_note (tem, REG_UNUSED, piece);
13656                                     break;
13657                                   }
13658                               }
13659                         }
13660
13661                       place = 0;
13662                     }
13663                 }
13664             }
13665           break;
13666
13667         default:
13668           /* Any other notes should not be present at this point in the
13669              compilation.  */
13670           gcc_unreachable ();
13671         }
13672
13673       if (place)
13674         {
13675           XEXP (note, 1) = REG_NOTES (place);
13676           REG_NOTES (place) = note;
13677         }
13678
13679       if (place2)
13680         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13681     }
13682 }
13683 \f
13684 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13685    I3, I2, and I1 to new locations.  This is also called to add a link
13686    pointing at I3 when I3's destination is changed.  */
13687
13688 static void
13689 distribute_links (struct insn_link *links)
13690 {
13691   struct insn_link *link, *next_link;
13692
13693   for (link = links; link; link = next_link)
13694     {
13695       rtx place = 0;
13696       rtx insn;
13697       rtx set, reg;
13698
13699       next_link = link->next;
13700
13701       /* If the insn that this link points to is a NOTE or isn't a single
13702          set, ignore it.  In the latter case, it isn't clear what we
13703          can do other than ignore the link, since we can't tell which
13704          register it was for.  Such links wouldn't be used by combine
13705          anyway.
13706
13707          It is not possible for the destination of the target of the link to
13708          have been changed by combine.  The only potential of this is if we
13709          replace I3, I2, and I1 by I3 and I2.  But in that case the
13710          destination of I2 also remains unchanged.  */
13711
13712       if (NOTE_P (link->insn)
13713           || (set = single_set (link->insn)) == 0)
13714         continue;
13715
13716       reg = SET_DEST (set);
13717       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13718              || GET_CODE (reg) == STRICT_LOW_PART)
13719         reg = XEXP (reg, 0);
13720
13721       /* A LOG_LINK is defined as being placed on the first insn that uses
13722          a register and points to the insn that sets the register.  Start
13723          searching at the next insn after the target of the link and stop
13724          when we reach a set of the register or the end of the basic block.
13725
13726          Note that this correctly handles the link that used to point from
13727          I3 to I2.  Also note that not much searching is typically done here
13728          since most links don't point very far away.  */
13729
13730       for (insn = NEXT_INSN (link->insn);
13731            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13732                      || BB_HEAD (this_basic_block->next_bb) != insn));
13733            insn = NEXT_INSN (insn))
13734         if (DEBUG_INSN_P (insn))
13735           continue;
13736         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13737           {
13738             if (reg_referenced_p (reg, PATTERN (insn)))
13739               place = insn;
13740             break;
13741           }
13742         else if (CALL_P (insn)
13743                  && find_reg_fusage (insn, USE, reg))
13744           {
13745             place = insn;
13746             break;
13747           }
13748         else if (INSN_P (insn) && reg_set_p (reg, insn))
13749           break;
13750
13751       /* If we found a place to put the link, place it there unless there
13752          is already a link to the same insn as LINK at that point.  */
13753
13754       if (place)
13755         {
13756           struct insn_link *link2;
13757
13758           FOR_EACH_LOG_LINK (link2, place)
13759             if (link2->insn == link->insn)
13760               break;
13761
13762           if (link2 == NULL)
13763             {
13764               link->next = LOG_LINKS (place);
13765               LOG_LINKS (place) = link;
13766
13767               /* Set added_links_insn to the earliest insn we added a
13768                  link to.  */
13769               if (added_links_insn == 0
13770                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13771                 added_links_insn = place;
13772             }
13773         }
13774     }
13775 }
13776 \f
13777 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13778    Check whether the expression pointer to by LOC is a register or
13779    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13780    Otherwise return zero.  */
13781
13782 static int
13783 unmentioned_reg_p_1 (rtx *loc, void *expr)
13784 {
13785   rtx x = *loc;
13786
13787   if (x != NULL_RTX
13788       && (REG_P (x) || MEM_P (x))
13789       && ! reg_mentioned_p (x, (rtx) expr))
13790     return 1;
13791   return 0;
13792 }
13793
13794 /* Check for any register or memory mentioned in EQUIV that is not
13795    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13796    of EXPR where some registers may have been replaced by constants.  */
13797
13798 static bool
13799 unmentioned_reg_p (rtx equiv, rtx expr)
13800 {
13801   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13802 }
13803 \f
13804 DEBUG_FUNCTION void
13805 dump_combine_stats (FILE *file)
13806 {
13807   fprintf
13808     (file,
13809      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13810      combine_attempts, combine_merges, combine_extras, combine_successes);
13811 }
13812
13813 void
13814 dump_combine_total_stats (FILE *file)
13815 {
13816   fprintf
13817     (file,
13818      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13819      total_attempts, total_merges, total_extras, total_successes);
13820 }
13821 \f
13822 static bool
13823 gate_handle_combine (void)
13824 {
13825   return (optimize > 0);
13826 }
13827
13828 /* Try combining insns through substitution.  */
13829 static unsigned int
13830 rest_of_handle_combine (void)
13831 {
13832   int rebuild_jump_labels_after_combine;
13833
13834   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13835   df_note_add_problem ();
13836   df_analyze ();
13837
13838   regstat_init_n_sets_and_refs ();
13839
13840   rebuild_jump_labels_after_combine
13841     = combine_instructions (get_insns (), max_reg_num ());
13842
13843   /* Combining insns may have turned an indirect jump into a
13844      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13845      instructions.  */
13846   if (rebuild_jump_labels_after_combine)
13847     {
13848       timevar_push (TV_JUMP);
13849       rebuild_jump_labels (get_insns ());
13850       cleanup_cfg (0);
13851       timevar_pop (TV_JUMP);
13852     }
13853
13854   regstat_free_n_sets_and_refs ();
13855   return 0;
13856 }
13857
13858 namespace {
13859
13860 const pass_data pass_data_combine =
13861 {
13862   RTL_PASS, /* type */
13863   "combine", /* name */
13864   OPTGROUP_NONE, /* optinfo_flags */
13865   true, /* has_gate */
13866   true, /* has_execute */
13867   TV_COMBINE, /* tv_id */
13868   PROP_cfglayout, /* properties_required */
13869   0, /* properties_provided */
13870   0, /* properties_destroyed */
13871   0, /* todo_flags_start */
13872   ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
13873 };
13874
13875 class pass_combine : public rtl_opt_pass
13876 {
13877 public:
13878   pass_combine(gcc::context *ctxt)
13879     : rtl_opt_pass(pass_data_combine, ctxt)
13880   {}
13881
13882   /* opt_pass methods: */
13883   bool gate () { return gate_handle_combine (); }
13884   unsigned int execute () { return rest_of_handle_combine (); }
13885
13886 }; // class pass_combine
13887
13888 } // anon namespace
13889
13890 rtl_opt_pass *
13891 make_pass_combine (gcc::context *ctxt)
13892 {
13893   return new pass_combine (ctxt);
13894 }