gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c

   1 /* Verify that overloaded built-ins for vec_sl with int
   2    inputs produce the right results.  */
   3
   4 /* { dg-do compile } */
   5 /* { dg-require-effective-target powerpc_altivec_ok } */
   6 /* { dg-options "-maltivec -O2" } */
   7
   8 #include <altivec.h>
   9
  10 vector signed int
  11 testsl_signed (vector signed int x, vector unsigned int y)
  12 {
  13   return vec_sl (x, y);
  14 }
  15
  16 vector unsigned int
  17 testsl_unsigned (vector unsigned int x, vector unsigned int y)
  18 {
  19   return vec_sl (x, y);
  20 }
  21
  22 vector signed int
  23 testsr_signed (vector signed int x, vector unsigned int y)
  24 {
  25   return vec_sr (x, y);
  26 }
  27
  28 vector unsigned int
  29 testsr_unsigned (vector unsigned int x, vector unsigned int y)
  30 {
  31   return vec_sr (x, y);
  32 }
  33
  34 vector signed int
  35 testsra_signed (vector signed int x, vector unsigned int y)
  36 {
  37   return vec_sra (x, y);
  38 }
  39
  40 vector unsigned int
  41 testsra_unsigned (vector unsigned int x, vector unsigned int y)
  42 {
  43   return vec_sra (x, y);
  44 }
  45
  46 vector signed int
  47 testrl_signed (vector signed int x, vector unsigned int y)
  48 {
  49   return vec_rl (x, y);
  50 }
  51
  52 vector unsigned int
  53 testrl_unsigned (vector unsigned int x, vector unsigned int y)
  54 {
  55   return vec_rl (x, y);
  56 }
  57
  58 /* { dg-final { scan-assembler-times "vslw" 2 } } */
  59 /* { dg-final { scan-assembler-times "vsrw" 2 } } */
  60 /* { dg-final { scan-assembler-times "vsraw" 2 } } */
  61 /* { dg-final { scan-assembler-times "vrlw" 2 } } */