| blob | 44b196652096be37edd14d7d294baba6ef3858a0 |
1 ;; Patterns for the Intel Wireless MMX technology architecture.
2 ;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 2, or (at your option) any later
10 ;; version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 (define_insn "iwmmxt_iordi3"
23 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
24 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
25 (match_operand:DI 2 "register_operand" "y,r,r")))]
26 "TARGET_REALLY_IWMMXT"
27 "@
28 wor%?\\t%0, %1, %2
29 #
30 #"
31 [(set_attr "predicable" "yes")
32 (set_attr "length" "4,8,8")])
34 (define_insn "iwmmxt_xordi3"
35 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
36 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
37 (match_operand:DI 2 "register_operand" "y,r,r")))]
38 "TARGET_REALLY_IWMMXT"
39 "@
40 wxor%?\\t%0, %1, %2
41 #
42 #"
43 [(set_attr "predicable" "yes")
44 (set_attr "length" "4,8,8")])
46 (define_insn "iwmmxt_anddi3"
47 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
48 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
49 (match_operand:DI 2 "register_operand" "y,r,r")))]
50 "TARGET_REALLY_IWMMXT"
51 "@
52 wand%?\\t%0, %1, %2
53 #
54 #"
55 [(set_attr "predicable" "yes")
56 (set_attr "length" "4,8,8")])
58 (define_insn "iwmmxt_nanddi3"
59 [(set (match_operand:DI 0 "register_operand" "=y")
60 (and:DI (match_operand:DI 1 "register_operand" "y")
61 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
62 "TARGET_REALLY_IWMMXT"
63 "wandn%?\\t%0, %1, %2"
64 [(set_attr "predicable" "yes")])
66 (define_insn "*iwmmxt_arm_movdi"
67 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
68 (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))]
69 "TARGET_REALLY_IWMMXT"
70 "*
71 {
72 switch (which_alternative)
73 {
74 default:
75 return output_move_double (operands);
76 case 0:
77 return \"#\";
78 case 3:
79 return \"wmov%?\\t%0,%1\";
80 case 4:
81 return \"tmcrr%?\\t%0,%Q1,%R1\";
82 case 5:
83 return \"tmrrc%?\\t%Q0,%R0,%1\";
84 case 6:
85 return \"wldrd%?\\t%0,%1\";
86 case 7:
87 return \"wstrd%?\\t%1,%0\";
88 }
89 }"
90 [(set_attr "length" "8,8,8,4,4,4,4,4")
91 (set_attr "type" "*,load1,store2,*,*,*,*,*")
92 (set_attr "pool_range" "*,1020,*,*,*,*,*,*")
93 (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
94 )
96 (define_insn "*iwmmxt_movsi_insn"
97 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
98 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))]
99 "TARGET_REALLY_IWMMXT
100 && ( register_operand (operands[0], SImode)
101 || register_operand (operands[1], SImode))"
102 "*
103 switch (which_alternative)
104 {
105 case 0: return \"mov\\t%0, %1\";
106 case 1: return \"mvn\\t%0, #%B1\";
107 case 2: return \"ldr\\t%0, %1\";
108 case 3: return \"str\\t%1, %0\";
109 case 4: return \"tmcr\\t%0, %1\";
110 case 5: return \"tmrc\\t%0, %1\";
111 case 6: return arm_output_load_gr (operands);
112 case 7: return \"wstrw\\t%1, %0\";
113 default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
114 }"
115 [(set_attr "type" "*,*,load1,store1,*,*,load1,store1,*")
116 (set_attr "length" "*,*,*, *,*,*, 16, *,8")
117 (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*")
118 (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*")
119 ;; Note - the "predicable" attribute is not allowed to have alternatives.
120 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
121 ;; predicating any of the alternatives in this template. Instead,
122 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
123 (set_attr "predicable" "no")
124 ;; Also - we have to pretend that these insns clobber the condition code
125 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
126 ;; them.
127 (set_attr "conds" "clob")]
128 )
130 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
131 ;; cond_exec version explicitly, with appropriate constraints.
133 (define_insn "*cond_iwmmxt_movsi_insn"
134 [(cond_exec
135 (match_operator 2 "arm_comparison_operator"
136 [(match_operand 3 "cc_register" "")
137 (const_int 0)])
138 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
139 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
140 "TARGET_REALLY_IWMMXT
141 && ( register_operand (operands[0], SImode)
142 || register_operand (operands[1], SImode))"
143 "*
144 switch (which_alternative)
145 {
146 case 0: return \"mov%?\\t%0, %1\";
147 case 1: return \"mvn%?\\t%0, #%B1\";
148 case 2: return \"ldr%?\\t%0, %1\";
149 case 3: return \"str%?\\t%1, %0\";
150 case 4: return \"tmcr%?\\t%0, %1\";
151 default: return \"tmrc%?\\t%0, %1\";
152 }"
153 [(set_attr "type" "*,*,load1,store1,*,*")
154 (set_attr "pool_range" "*,*,4096, *,*,*")
155 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
156 )
158 (define_insn "movv8qi_internal"
159 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
160 (match_operand:V8QI 1 "general_operand" "y,y,mi,y,r,mi"))]
161 "TARGET_REALLY_IWMMXT"
162 "*
163 switch (which_alternative)
164 {
165 case 0: return \"wmov%?\\t%0, %1\";
166 case 1: return \"wstrd%?\\t%1, %0\";
167 case 2: return \"wldrd%?\\t%0, %1\";
168 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
169 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
170 default: return output_move_double (operands);
171 }"
172 [(set_attr "predicable" "yes")
173 (set_attr "length" "4, 4, 4,4,4, 8")
174 (set_attr "type" "*,store1,load1,*,*,load1")
175 (set_attr "pool_range" "*, *, 256,*,*, 256")
176 (set_attr "neg_pool_range" "*, *, 244,*,*, 244")])
178 (define_insn "movv4hi_internal"
179 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
180 (match_operand:V4HI 1 "general_operand" "y,y,mi,y,r,mi"))]
181 "TARGET_REALLY_IWMMXT"
182 "*
183 switch (which_alternative)
184 {
185 case 0: return \"wmov%?\\t%0, %1\";
186 case 1: return \"wstrd%?\\t%1, %0\";
187 case 2: return \"wldrd%?\\t%0, %1\";
188 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
189 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
190 default: return output_move_double (operands);
191 }"
192 [(set_attr "predicable" "yes")
193 (set_attr "length" "4, 4, 4,4,4, 8")
194 (set_attr "type" "*,store1,load1,*,*,load1")
195 (set_attr "pool_range" "*, *, 256,*,*, 256")
196 (set_attr "neg_pool_range" "*, *, 244,*,*, 244")])
198 (define_insn "movv2si_internal"
199 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
200 (match_operand:V2SI 1 "general_operand" "y,y,mi,y,r,mi"))]
201 "TARGET_REALLY_IWMMXT"
202 "*
203 switch (which_alternative)
204 {
205 case 0: return \"wmov%?\\t%0, %1\";
206 case 1: return \"wstrd%?\\t%1, %0\";
207 case 2: return \"wldrd%?\\t%0, %1\";
208 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
209 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
210 default: return output_move_double (operands);
211 }"
212 [(set_attr "predicable" "yes")
213 (set_attr "length" "4, 4, 4,4,4, 24")
214 (set_attr "type" "*,store1,load1,*,*,load1")
215 (set_attr "pool_range" "*, *, 256,*,*, 256")
216 (set_attr "neg_pool_range" "*, *, 244,*,*, 244")])
218 ;; This pattern should not be needed. It is to match a
219 ;; wierd case generated by GCC when no optimizations are
220 ;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/
221 ;; compile/simd-5.c at -O0). The mode for operands[1] is
222 ;; deliberately omitted.
223 (define_insn "movv2si_internal_2"
224 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
225 (match_operand 1 "immediate_operand" "mi"))]
226 "TARGET_REALLY_IWMMXT"
227 "* return output_move_double (operands);"
228 [(set_attr "predicable" "yes")
229 (set_attr "length" "8")
230 (set_attr "type" "load1")
231 (set_attr "pool_range" "256")
232 (set_attr "neg_pool_range" "244")])
234 ;; Vector add/subtract
236 (define_insn "addv8qi3"
237 [(set (match_operand:V8QI 0 "register_operand" "=y")
238 (plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
239 (match_operand:V8QI 2 "register_operand" "y")))]
240 "TARGET_REALLY_IWMMXT"
241 "waddb%?\\t%0, %1, %2"
242 [(set_attr "predicable" "yes")])
244 (define_insn "addv4hi3"
245 [(set (match_operand:V4HI 0 "register_operand" "=y")
246 (plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
247 (match_operand:V4HI 2 "register_operand" "y")))]
248 "TARGET_REALLY_IWMMXT"
249 "waddh%?\\t%0, %1, %2"
250 [(set_attr "predicable" "yes")])
252 (define_insn "addv2si3"
253 [(set (match_operand:V2SI 0 "register_operand" "=y")
254 (plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
255 (match_operand:V2SI 2 "register_operand" "y")))]
256 "TARGET_REALLY_IWMMXT"
257 "waddw%?\\t%0, %1, %2"
258 [(set_attr "predicable" "yes")])
260 (define_insn "ssaddv8qi3"
261 [(set (match_operand:V8QI 0 "register_operand" "=y")
262 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
263 (match_operand:V8QI 2 "register_operand" "y")))]
264 "TARGET_REALLY_IWMMXT"
265 "waddbss%?\\t%0, %1, %2"
266 [(set_attr "predicable" "yes")])
268 (define_insn "ssaddv4hi3"
269 [(set (match_operand:V4HI 0 "register_operand" "=y")
270 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
271 (match_operand:V4HI 2 "register_operand" "y")))]
272 "TARGET_REALLY_IWMMXT"
273 "waddhss%?\\t%0, %1, %2"
274 [(set_attr "predicable" "yes")])
276 (define_insn "ssaddv2si3"
277 [(set (match_operand:V2SI 0 "register_operand" "=y")
278 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
279 (match_operand:V2SI 2 "register_operand" "y")))]
280 "TARGET_REALLY_IWMMXT"
281 "waddwss%?\\t%0, %1, %2"
282 [(set_attr "predicable" "yes")])
284 (define_insn "usaddv8qi3"
285 [(set (match_operand:V8QI 0 "register_operand" "=y")
286 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
287 (match_operand:V8QI 2 "register_operand" "y")))]
288 "TARGET_REALLY_IWMMXT"
289 "waddbus%?\\t%0, %1, %2"
290 [(set_attr "predicable" "yes")])
292 (define_insn "usaddv4hi3"
293 [(set (match_operand:V4HI 0 "register_operand" "=y")
294 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
295 (match_operand:V4HI 2 "register_operand" "y")))]
296 "TARGET_REALLY_IWMMXT"
297 "waddhus%?\\t%0, %1, %2"
298 [(set_attr "predicable" "yes")])
300 (define_insn "usaddv2si3"
301 [(set (match_operand:V2SI 0 "register_operand" "=y")
302 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
303 (match_operand:V2SI 2 "register_operand" "y")))]
304 "TARGET_REALLY_IWMMXT"
305 "waddwus%?\\t%0, %1, %2"
306 [(set_attr "predicable" "yes")])
308 (define_insn "subv8qi3"
309 [(set (match_operand:V8QI 0 "register_operand" "=y")
310 (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
311 (match_operand:V8QI 2 "register_operand" "y")))]
312 "TARGET_REALLY_IWMMXT"
313 "wsubb%?\\t%0, %1, %2"
314 [(set_attr "predicable" "yes")])
316 (define_insn "subv4hi3"
317 [(set (match_operand:V4HI 0 "register_operand" "=y")
318 (minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
319 (match_operand:V4HI 2 "register_operand" "y")))]
320 "TARGET_REALLY_IWMMXT"
321 "wsubh%?\\t%0, %1, %2"
322 [(set_attr "predicable" "yes")])
324 (define_insn "subv2si3"
325 [(set (match_operand:V2SI 0 "register_operand" "=y")
326 (minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
327 (match_operand:V2SI 2 "register_operand" "y")))]
328 "TARGET_REALLY_IWMMXT"
329 "wsubw%?\\t%0, %1, %2"
330 [(set_attr "predicable" "yes")])
332 (define_insn "sssubv8qi3"
333 [(set (match_operand:V8QI 0 "register_operand" "=y")
334 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
335 (match_operand:V8QI 2 "register_operand" "y")))]
336 "TARGET_REALLY_IWMMXT"
337 "wsubbss%?\\t%0, %1, %2"
338 [(set_attr "predicable" "yes")])
340 (define_insn "sssubv4hi3"
341 [(set (match_operand:V4HI 0 "register_operand" "=y")
342 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
343 (match_operand:V4HI 2 "register_operand" "y")))]
344 "TARGET_REALLY_IWMMXT"
345 "wsubhss%?\\t%0, %1, %2"
346 [(set_attr "predicable" "yes")])
348 (define_insn "sssubv2si3"
349 [(set (match_operand:V2SI 0 "register_operand" "=y")
350 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
351 (match_operand:V2SI 2 "register_operand" "y")))]
352 "TARGET_REALLY_IWMMXT"
353 "wsubwss%?\\t%0, %1, %2"
354 [(set_attr "predicable" "yes")])
356 (define_insn "ussubv8qi3"
357 [(set (match_operand:V8QI 0 "register_operand" "=y")
358 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
359 (match_operand:V8QI 2 "register_operand" "y")))]
360 "TARGET_REALLY_IWMMXT"
361 "wsubbus%?\\t%0, %1, %2"
362 [(set_attr "predicable" "yes")])
364 (define_insn "ussubv4hi3"
365 [(set (match_operand:V4HI 0 "register_operand" "=y")
366 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
367 (match_operand:V4HI 2 "register_operand" "y")))]
368 "TARGET_REALLY_IWMMXT"
369 "wsubhus%?\\t%0, %1, %2"
370 [(set_attr "predicable" "yes")])
372 (define_insn "ussubv2si3"
373 [(set (match_operand:V2SI 0 "register_operand" "=y")
374 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
375 (match_operand:V2SI 2 "register_operand" "y")))]
376 "TARGET_REALLY_IWMMXT"
377 "wsubwus%?\\t%0, %1, %2"
378 [(set_attr "predicable" "yes")])
380 (define_insn "mulv4hi3"
381 [(set (match_operand:V4HI 0 "register_operand" "=y")
382 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
383 (match_operand:V4HI 2 "register_operand" "y")))]
384 "TARGET_REALLY_IWMMXT"
385 "wmulul%?\\t%0, %1, %2"
386 [(set_attr "predicable" "yes")])
388 (define_insn "smulv4hi3_highpart"
389 [(set (match_operand:V4HI 0 "register_operand" "=y")
390 (truncate:V4HI
391 (lshiftrt:V4SI
392 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
393 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
394 (const_int 16))))]
395 "TARGET_REALLY_IWMMXT"
396 "wmulsm%?\\t%0, %1, %2"
397 [(set_attr "predicable" "yes")])
399 (define_insn "umulv4hi3_highpart"
400 [(set (match_operand:V4HI 0 "register_operand" "=y")
401 (truncate:V4HI
402 (lshiftrt:V4SI
403 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
404 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
405 (const_int 16))))]
406 "TARGET_REALLY_IWMMXT"
407 "wmulum%?\\t%0, %1, %2"
408 [(set_attr "predicable" "yes")])
410 (define_insn "iwmmxt_wmacs"
411 [(set (match_operand:DI 0 "register_operand" "=y")
412 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
413 (match_operand:V4HI 2 "register_operand" "y")
414 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
415 "TARGET_REALLY_IWMMXT"
416 "wmacs%?\\t%0, %2, %3"
417 [(set_attr "predicable" "yes")])
419 (define_insn "iwmmxt_wmacsz"
420 [(set (match_operand:DI 0 "register_operand" "=y")
421 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
422 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
423 "TARGET_REALLY_IWMMXT"
424 "wmacsz%?\\t%0, %1, %2"
425 [(set_attr "predicable" "yes")])
427 (define_insn "iwmmxt_wmacu"
428 [(set (match_operand:DI 0 "register_operand" "=y")
429 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
430 (match_operand:V4HI 2 "register_operand" "y")
431 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
432 "TARGET_REALLY_IWMMXT"
433 "wmacu%?\\t%0, %2, %3"
434 [(set_attr "predicable" "yes")])
436 (define_insn "iwmmxt_wmacuz"
437 [(set (match_operand:DI 0 "register_operand" "=y")
438 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
439 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
440 "TARGET_REALLY_IWMMXT"
441 "wmacuz%?\\t%0, %1, %2"
442 [(set_attr "predicable" "yes")])
444 ;; Same as xordi3, but don't show input operands so that we don't think
445 ;; they are live.
446 (define_insn "iwmmxt_clrdi"
447 [(set (match_operand:DI 0 "register_operand" "=y")
448 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
449 "TARGET_REALLY_IWMMXT"
450 "wxor%?\\t%0, %0, %0"
451 [(set_attr "predicable" "yes")])
453 ;; Seems like cse likes to generate these, so we have to support them.
455 (define_insn "*iwmmxt_clrv8qi"
456 [(set (match_operand:V8QI 0 "register_operand" "=y")
457 (const_vector:V8QI [(const_int 0) (const_int 0)
458 (const_int 0) (const_int 0)
459 (const_int 0) (const_int 0)
460 (const_int 0) (const_int 0)]))]
461 "TARGET_REALLY_IWMMXT"
462 "wxor%?\\t%0, %0, %0"
463 [(set_attr "predicable" "yes")])
465 (define_insn "*iwmmxt_clrv4hi"
466 [(set (match_operand:V4HI 0 "register_operand" "=y")
467 (const_vector:V4HI [(const_int 0) (const_int 0)
468 (const_int 0) (const_int 0)]))]
469 "TARGET_REALLY_IWMMXT"
470 "wxor%?\\t%0, %0, %0"
471 [(set_attr "predicable" "yes")])
473 (define_insn "*iwmmxt_clrv2si"
474 [(set (match_operand:V2SI 0 "register_operand" "=y")
475 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
476 "TARGET_REALLY_IWMMXT"
477 "wxor%?\\t%0, %0, %0"
478 [(set_attr "predicable" "yes")])
480 ;; Unsigned averages/sum of absolute differences
482 (define_insn "iwmmxt_uavgrndv8qi3"
483 [(set (match_operand:V8QI 0 "register_operand" "=y")
484 (ashiftrt:V8QI
485 (plus:V8QI (plus:V8QI
486 (match_operand:V8QI 1 "register_operand" "y")
487 (match_operand:V8QI 2 "register_operand" "y"))
488 (const_vector:V8QI [(const_int 1)
489 (const_int 1)
490 (const_int 1)
491 (const_int 1)
492 (const_int 1)
493 (const_int 1)
494 (const_int 1)
495 (const_int 1)]))
496 (const_int 1)))]
497 "TARGET_REALLY_IWMMXT"
498 "wavg2br%?\\t%0, %1, %2"
499 [(set_attr "predicable" "yes")])
501 (define_insn "iwmmxt_uavgrndv4hi3"
502 [(set (match_operand:V4HI 0 "register_operand" "=y")
503 (ashiftrt:V4HI
504 (plus:V4HI (plus:V4HI
505 (match_operand:V4HI 1 "register_operand" "y")
506 (match_operand:V4HI 2 "register_operand" "y"))
507 (const_vector:V4HI [(const_int 1)
508 (const_int 1)
509 (const_int 1)
510 (const_int 1)]))
511 (const_int 1)))]
512 "TARGET_REALLY_IWMMXT"
513 "wavg2hr%?\\t%0, %1, %2"
514 [(set_attr "predicable" "yes")])
517 (define_insn "iwmmxt_uavgv8qi3"
518 [(set (match_operand:V8QI 0 "register_operand" "=y")
519 (ashiftrt:V8QI (plus:V8QI
520 (match_operand:V8QI 1 "register_operand" "y")
521 (match_operand:V8QI 2 "register_operand" "y"))
522 (const_int 1)))]
523 "TARGET_REALLY_IWMMXT"
524 "wavg2b%?\\t%0, %1, %2"
525 [(set_attr "predicable" "yes")])
527 (define_insn "iwmmxt_uavgv4hi3"
528 [(set (match_operand:V4HI 0 "register_operand" "=y")
529 (ashiftrt:V4HI (plus:V4HI
530 (match_operand:V4HI 1 "register_operand" "y")
531 (match_operand:V4HI 2 "register_operand" "y"))
532 (const_int 1)))]
533 "TARGET_REALLY_IWMMXT"
534 "wavg2h%?\\t%0, %1, %2"
535 [(set_attr "predicable" "yes")])
537 (define_insn "iwmmxt_psadbw"
538 [(set (match_operand:V8QI 0 "register_operand" "=y")
539 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
540 (match_operand:V8QI 2 "register_operand" "y"))))]
541 "TARGET_REALLY_IWMMXT"
542 "psadbw%?\\t%0, %1, %2"
543 [(set_attr "predicable" "yes")])
546 ;; Insert/extract/shuffle
548 (define_insn "iwmmxt_tinsrb"
549 [(set (match_operand:V8QI 0 "register_operand" "=y")
550 (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0")
551 (vec_duplicate:V8QI
552 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
553 (match_operand:SI 3 "immediate_operand" "i")))]
554 "TARGET_REALLY_IWMMXT"
555 "tinsrb%?\\t%0, %2, %3"
556 [(set_attr "predicable" "yes")])
558 (define_insn "iwmmxt_tinsrh"
559 [(set (match_operand:V4HI 0 "register_operand" "=y")
560 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
561 (vec_duplicate:V4HI
562 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
563 (match_operand:SI 3 "immediate_operand" "i")))]
564 "TARGET_REALLY_IWMMXT"
565 "tinsrh%?\\t%0, %2, %3"
566 [(set_attr "predicable" "yes")])
568 (define_insn "iwmmxt_tinsrw"
569 [(set (match_operand:V2SI 0 "register_operand" "=y")
570 (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0")
571 (vec_duplicate:V2SI
572 (match_operand:SI 2 "nonimmediate_operand" "r"))
573 (match_operand:SI 3 "immediate_operand" "i")))]
574 "TARGET_REALLY_IWMMXT"
575 "tinsrw%?\\t%0, %2, %3"
576 [(set_attr "predicable" "yes")])
578 (define_insn "iwmmxt_textrmub"
579 [(set (match_operand:SI 0 "register_operand" "=r")
580 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
581 (parallel
582 [(match_operand:SI 2 "immediate_operand" "i")]))))]
583 "TARGET_REALLY_IWMMXT"
584 "textrmub%?\\t%0, %1, %2"
585 [(set_attr "predicable" "yes")])
587 (define_insn "iwmmxt_textrmsb"
588 [(set (match_operand:SI 0 "register_operand" "=r")
589 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
590 (parallel
591 [(match_operand:SI 2 "immediate_operand" "i")]))))]
592 "TARGET_REALLY_IWMMXT"
593 "textrmsb%?\\t%0, %1, %2"
594 [(set_attr "predicable" "yes")])
596 (define_insn "iwmmxt_textrmuh"
597 [(set (match_operand:SI 0 "register_operand" "=r")
598 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
599 (parallel
600 [(match_operand:SI 2 "immediate_operand" "i")]))))]
601 "TARGET_REALLY_IWMMXT"
602 "textrmuh%?\\t%0, %1, %2"
603 [(set_attr "predicable" "yes")])
605 (define_insn "iwmmxt_textrmsh"
606 [(set (match_operand:SI 0 "register_operand" "=r")
607 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
608 (parallel
609 [(match_operand:SI 2 "immediate_operand" "i")]))))]
610 "TARGET_REALLY_IWMMXT"
611 "textrmsh%?\\t%0, %1, %2"
612 [(set_attr "predicable" "yes")])
614 ;; There are signed/unsigned variants of this instruction, but they are
615 ;; pointless.
616 (define_insn "iwmmxt_textrmw"
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
619 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
620 "TARGET_REALLY_IWMMXT"
621 "textrmsw%?\\t%0, %1, %2"
622 [(set_attr "predicable" "yes")])
624 (define_insn "iwmmxt_wshufh"
625 [(set (match_operand:V4HI 0 "register_operand" "=y")
626 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
627 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
628 "TARGET_REALLY_IWMMXT"
629 "wshufh%?\\t%0, %1, %2"
630 [(set_attr "predicable" "yes")])
632 ;; Mask-generating comparisons
633 ;;
634 ;; Note - you cannot use patterns like these here:
635 ;;
636 ;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
637 ;;
638 ;; Because GCC will assume that the truth value (1 or 0) is installed
639 ;; into the entire destination vector, (with the '1' going into the least
640 ;; significant element of the vector). This is not how these instructions
641 ;; behave.
642 ;;
643 ;; Unfortunately the current patterns are illegal. They are SET insns
644 ;; without a SET in them. They work in most cases for ordinary code
645 ;; generation, but there are circumstances where they can cause gcc to fail.
646 ;; XXX - FIXME.
648 (define_insn "eqv8qi3"
649 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
650 (match_operand:V8QI 1 "register_operand" "y")
651 (match_operand:V8QI 2 "register_operand" "y")]
652 VUNSPEC_WCMP_EQ)]
653 "TARGET_REALLY_IWMMXT"
654 "wcmpeqb%?\\t%0, %1, %2"
655 [(set_attr "predicable" "yes")])
657 (define_insn "eqv4hi3"
658 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
659 (match_operand:V4HI 1 "register_operand" "y")
660 (match_operand:V4HI 2 "register_operand" "y")]
661 VUNSPEC_WCMP_EQ)]
662 "TARGET_REALLY_IWMMXT"
663 "wcmpeqh%?\\t%0, %1, %2"
664 [(set_attr "predicable" "yes")])
666 (define_insn "eqv2si3"
667 [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
668 (match_operand:V2SI 1 "register_operand" "y")
669 (match_operand:V2SI 2 "register_operand" "y")]
670 VUNSPEC_WCMP_EQ)]
671 "TARGET_REALLY_IWMMXT"
672 "wcmpeqw%?\\t%0, %1, %2"
673 [(set_attr "predicable" "yes")])
675 (define_insn "gtuv8qi3"
676 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
677 (match_operand:V8QI 1 "register_operand" "y")
678 (match_operand:V8QI 2 "register_operand" "y")]
679 VUNSPEC_WCMP_GTU)]
680 "TARGET_REALLY_IWMMXT"
681 "wcmpgtub%?\\t%0, %1, %2"
682 [(set_attr "predicable" "yes")])
684 (define_insn "gtuv4hi3"
685 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
686 (match_operand:V4HI 1 "register_operand" "y")
687 (match_operand:V4HI 2 "register_operand" "y")]
688 VUNSPEC_WCMP_GTU)]
689 "TARGET_REALLY_IWMMXT"
690 "wcmpgtuh%?\\t%0, %1, %2"
691 [(set_attr "predicable" "yes")])
693 (define_insn "gtuv2si3"
694 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
695 (match_operand:V2SI 1 "register_operand" "y")
696 (match_operand:V2SI 2 "register_operand" "y")]
697 VUNSPEC_WCMP_GTU)]
698 "TARGET_REALLY_IWMMXT"
699 "wcmpgtuw%?\\t%0, %1, %2"
700 [(set_attr "predicable" "yes")])
702 (define_insn "gtv8qi3"
703 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
704 (match_operand:V8QI 1 "register_operand" "y")
705 (match_operand:V8QI 2 "register_operand" "y")]
706 VUNSPEC_WCMP_GT)]
707 "TARGET_REALLY_IWMMXT"
708 "wcmpgtsb%?\\t%0, %1, %2"
709 [(set_attr "predicable" "yes")])
711 (define_insn "gtv4hi3"
712 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
713 (match_operand:V4HI 1 "register_operand" "y")
714 (match_operand:V4HI 2 "register_operand" "y")]
715 VUNSPEC_WCMP_GT)]
716 "TARGET_REALLY_IWMMXT"
717 "wcmpgtsh%?\\t%0, %1, %2"
718 [(set_attr "predicable" "yes")])
720 (define_insn "gtv2si3"
721 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
722 (match_operand:V2SI 1 "register_operand" "y")
723 (match_operand:V2SI 2 "register_operand" "y")]
724 VUNSPEC_WCMP_GT)]
725 "TARGET_REALLY_IWMMXT"
726 "wcmpgtsw%?\\t%0, %1, %2"
727 [(set_attr "predicable" "yes")])
729 ;; Max/min insns
731 (define_insn "smaxv8qi3"
732 [(set (match_operand:V8QI 0 "register_operand" "=y")
733 (smax:V8QI (match_operand:V8QI 1 "register_operand" "y")
734 (match_operand:V8QI 2 "register_operand" "y")))]
735 "TARGET_REALLY_IWMMXT"
736 "wmaxsb%?\\t%0, %1, %2"
737 [(set_attr "predicable" "yes")])
739 (define_insn "umaxv8qi3"
740 [(set (match_operand:V8QI 0 "register_operand" "=y")
741 (umax:V8QI (match_operand:V8QI 1 "register_operand" "y")
742 (match_operand:V8QI 2 "register_operand" "y")))]
743 "TARGET_REALLY_IWMMXT"
744 "wmaxub%?\\t%0, %1, %2"
745 [(set_attr "predicable" "yes")])
747 (define_insn "smaxv4hi3"
748 [(set (match_operand:V4HI 0 "register_operand" "=y")
749 (smax:V4HI (match_operand:V4HI 1 "register_operand" "y")
750 (match_operand:V4HI 2 "register_operand" "y")))]
751 "TARGET_REALLY_IWMMXT"
752 "wmaxsh%?\\t%0, %1, %2"
753 [(set_attr "predicable" "yes")])
755 (define_insn "umaxv4hi3"
756 [(set (match_operand:V4HI 0 "register_operand" "=y")
757 (umax:V4HI (match_operand:V4HI 1 "register_operand" "y")
758 (match_operand:V4HI 2 "register_operand" "y")))]
759 "TARGET_REALLY_IWMMXT"
760 "wmaxuh%?\\t%0, %1, %2"
761 [(set_attr "predicable" "yes")])
763 (define_insn "smaxv2si3"
764 [(set (match_operand:V2SI 0 "register_operand" "=y")
765 (smax:V2SI (match_operand:V2SI 1 "register_operand" "y")
766 (match_operand:V2SI 2 "register_operand" "y")))]
767 "TARGET_REALLY_IWMMXT"
768 "wmaxsw%?\\t%0, %1, %2"
769 [(set_attr "predicable" "yes")])
771 (define_insn "umaxv2si3"
772 [(set (match_operand:V2SI 0 "register_operand" "=y")
773 (umax:V2SI (match_operand:V2SI 1 "register_operand" "y")
774 (match_operand:V2SI 2 "register_operand" "y")))]
775 "TARGET_REALLY_IWMMXT"
776 "wmaxuw%?\\t%0, %1, %2"
777 [(set_attr "predicable" "yes")])
779 (define_insn "sminv8qi3"
780 [(set (match_operand:V8QI 0 "register_operand" "=y")
781 (smin:V8QI (match_operand:V8QI 1 "register_operand" "y")
782 (match_operand:V8QI 2 "register_operand" "y")))]
783 "TARGET_REALLY_IWMMXT"
784 "wminsb%?\\t%0, %1, %2"
785 [(set_attr "predicable" "yes")])
787 (define_insn "uminv8qi3"
788 [(set (match_operand:V8QI 0 "register_operand" "=y")
789 (umin:V8QI (match_operand:V8QI 1 "register_operand" "y")
790 (match_operand:V8QI 2 "register_operand" "y")))]
791 "TARGET_REALLY_IWMMXT"
792 "wminub%?\\t%0, %1, %2"
793 [(set_attr "predicable" "yes")])
795 (define_insn "sminv4hi3"
796 [(set (match_operand:V4HI 0 "register_operand" "=y")
797 (smin:V4HI (match_operand:V4HI 1 "register_operand" "y")
798 (match_operand:V4HI 2 "register_operand" "y")))]
799 "TARGET_REALLY_IWMMXT"
800 "wminsh%?\\t%0, %1, %2"
801 [(set_attr "predicable" "yes")])
803 (define_insn "uminv4hi3"
804 [(set (match_operand:V4HI 0 "register_operand" "=y")
805 (umin:V4HI (match_operand:V4HI 1 "register_operand" "y")
806 (match_operand:V4HI 2 "register_operand" "y")))]
807 "TARGET_REALLY_IWMMXT"
808 "wminuh%?\\t%0, %1, %2"
809 [(set_attr "predicable" "yes")])
811 (define_insn "sminv2si3"
812 [(set (match_operand:V2SI 0 "register_operand" "=y")
813 (smin:V2SI (match_operand:V2SI 1 "register_operand" "y")
814 (match_operand:V2SI 2 "register_operand" "y")))]
815 "TARGET_REALLY_IWMMXT"
816 "wminsw%?\\t%0, %1, %2"
817 [(set_attr "predicable" "yes")])
819 (define_insn "uminv2si3"
820 [(set (match_operand:V2SI 0 "register_operand" "=y")
821 (umin:V2SI (match_operand:V2SI 1 "register_operand" "y")
822 (match_operand:V2SI 2 "register_operand" "y")))]
823 "TARGET_REALLY_IWMMXT"
824 "wminuw%?\\t%0, %1, %2"
825 [(set_attr "predicable" "yes")])
827 ;; Pack/unpack insns.
829 (define_insn "iwmmxt_wpackhss"
830 [(set (match_operand:V8QI 0 "register_operand" "=y")
831 (vec_concat:V8QI
832 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
833 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
834 "TARGET_REALLY_IWMMXT"
835 "wpackhss%?\\t%0, %1, %2"
836 [(set_attr "predicable" "yes")])
838 (define_insn "iwmmxt_wpackwss"
839 [(set (match_operand:V4HI 0 "register_operand" "=y")
840 (vec_concat:V4HI
841 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
842 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
843 "TARGET_REALLY_IWMMXT"
844 "wpackwss%?\\t%0, %1, %2"
845 [(set_attr "predicable" "yes")])
847 (define_insn "iwmmxt_wpackdss"
848 [(set (match_operand:V2SI 0 "register_operand" "=y")
849 (vec_concat:V2SI
850 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
851 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
852 "TARGET_REALLY_IWMMXT"
853 "wpackdss%?\\t%0, %1, %2"
854 [(set_attr "predicable" "yes")])
856 (define_insn "iwmmxt_wpackhus"
857 [(set (match_operand:V8QI 0 "register_operand" "=y")
858 (vec_concat:V8QI
859 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
860 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
861 "TARGET_REALLY_IWMMXT"
862 "wpackhus%?\\t%0, %1, %2"
863 [(set_attr "predicable" "yes")])
865 (define_insn "iwmmxt_wpackwus"
866 [(set (match_operand:V4HI 0 "register_operand" "=y")
867 (vec_concat:V4HI
868 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
869 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
870 "TARGET_REALLY_IWMMXT"
871 "wpackwus%?\\t%0, %1, %2"
872 [(set_attr "predicable" "yes")])
874 (define_insn "iwmmxt_wpackdus"
875 [(set (match_operand:V2SI 0 "register_operand" "=y")
876 (vec_concat:V2SI
877 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
878 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
879 "TARGET_REALLY_IWMMXT"
880 "wpackdus%?\\t%0, %1, %2"
881 [(set_attr "predicable" "yes")])
884 (define_insn "iwmmxt_wunpckihb"
885 [(set (match_operand:V8QI 0 "register_operand" "=y")
886 (vec_merge:V8QI
887 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
888 (parallel [(const_int 4)
889 (const_int 0)
890 (const_int 5)
891 (const_int 1)
892 (const_int 6)
893 (const_int 2)
894 (const_int 7)
895 (const_int 3)]))
896 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
897 (parallel [(const_int 0)
898 (const_int 4)
899 (const_int 1)
900 (const_int 5)
901 (const_int 2)
902 (const_int 6)
903 (const_int 3)
904 (const_int 7)]))
905 (const_int 85)))]
906 "TARGET_REALLY_IWMMXT"
907 "wunpckihb%?\\t%0, %1, %2"
908 [(set_attr "predicable" "yes")])
910 (define_insn "iwmmxt_wunpckihh"
911 [(set (match_operand:V4HI 0 "register_operand" "=y")
912 (vec_merge:V4HI
913 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
914 (parallel [(const_int 0)
915 (const_int 2)
916 (const_int 1)
917 (const_int 3)]))
918 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
919 (parallel [(const_int 2)
920 (const_int 0)
921 (const_int 3)
922 (const_int 1)]))
923 (const_int 5)))]
924 "TARGET_REALLY_IWMMXT"
925 "wunpckihh%?\\t%0, %1, %2"
926 [(set_attr "predicable" "yes")])
928 (define_insn "iwmmxt_wunpckihw"
929 [(set (match_operand:V2SI 0 "register_operand" "=y")
930 (vec_merge:V2SI
931 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
932 (parallel [(const_int 0)
933 (const_int 1)]))
934 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
935 (parallel [(const_int 1)
936 (const_int 0)]))
937 (const_int 1)))]
938 "TARGET_REALLY_IWMMXT"
939 "wunpckihw%?\\t%0, %1, %2"
940 [(set_attr "predicable" "yes")])
942 (define_insn "iwmmxt_wunpckilb"
943 [(set (match_operand:V8QI 0 "register_operand" "=y")
944 (vec_merge:V8QI
945 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
946 (parallel [(const_int 0)
947 (const_int 4)
948 (const_int 1)
949 (const_int 5)
950 (const_int 2)
951 (const_int 6)
952 (const_int 3)
953 (const_int 7)]))
954 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
955 (parallel [(const_int 4)
956 (const_int 0)
957 (const_int 5)
958 (const_int 1)
959 (const_int 6)
960 (const_int 2)
961 (const_int 7)
962 (const_int 3)]))
963 (const_int 85)))]
964 "TARGET_REALLY_IWMMXT"
965 "wunpckilb%?\\t%0, %1, %2"
966 [(set_attr "predicable" "yes")])
968 (define_insn "iwmmxt_wunpckilh"
969 [(set (match_operand:V4HI 0 "register_operand" "=y")
970 (vec_merge:V4HI
971 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
972 (parallel [(const_int 2)
973 (const_int 0)
974 (const_int 3)
975 (const_int 1)]))
976 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
977 (parallel [(const_int 0)
978 (const_int 2)
979 (const_int 1)
980 (const_int 3)]))
981 (const_int 5)))]
982 "TARGET_REALLY_IWMMXT"
983 "wunpckilh%?\\t%0, %1, %2"
984 [(set_attr "predicable" "yes")])
986 (define_insn "iwmmxt_wunpckilw"
987 [(set (match_operand:V2SI 0 "register_operand" "=y")
988 (vec_merge:V2SI
989 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
990 (parallel [(const_int 1)
991 (const_int 0)]))
992 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
993 (parallel [(const_int 0)
994 (const_int 1)]))
995 (const_int 1)))]
996 "TARGET_REALLY_IWMMXT"
997 "wunpckilw%?\\t%0, %1, %2"
998 [(set_attr "predicable" "yes")])
1000 (define_insn "iwmmxt_wunpckehub"
1001 [(set (match_operand:V4HI 0 "register_operand" "=y")
1002 (zero_extend:V4HI
1003 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1004 (parallel [(const_int 4) (const_int 5)
1005 (const_int 6) (const_int 7)]))))]
1006 "TARGET_REALLY_IWMMXT"
1007 "wunpckehub%?\\t%0, %1"
1008 [(set_attr "predicable" "yes")])
1010 (define_insn "iwmmxt_wunpckehuh"
1011 [(set (match_operand:V2SI 0 "register_operand" "=y")
1012 (zero_extend:V2SI
1013 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1014 (parallel [(const_int 2) (const_int 3)]))))]
1015 "TARGET_REALLY_IWMMXT"
1016 "wunpckehuh%?\\t%0, %1"
1017 [(set_attr "predicable" "yes")])
1019 (define_insn "iwmmxt_wunpckehuw"
1020 [(set (match_operand:DI 0 "register_operand" "=y")
1021 (zero_extend:DI
1022 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1023 (parallel [(const_int 1)]))))]
1024 "TARGET_REALLY_IWMMXT"
1025 "wunpckehuw%?\\t%0, %1"
1026 [(set_attr "predicable" "yes")])
1028 (define_insn "iwmmxt_wunpckehsb"
1029 [(set (match_operand:V4HI 0 "register_operand" "=y")
1030 (sign_extend:V4HI
1031 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1032 (parallel [(const_int 4) (const_int 5)
1033 (const_int 6) (const_int 7)]))))]
1034 "TARGET_REALLY_IWMMXT"
1035 "wunpckehsb%?\\t%0, %1"
1036 [(set_attr "predicable" "yes")])
1038 (define_insn "iwmmxt_wunpckehsh"
1039 [(set (match_operand:V2SI 0 "register_operand" "=y")
1040 (sign_extend:V2SI
1041 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1042 (parallel [(const_int 2) (const_int 3)]))))]
1043 "TARGET_REALLY_IWMMXT"
1044 "wunpckehsh%?\\t%0, %1"
1045 [(set_attr "predicable" "yes")])
1047 (define_insn "iwmmxt_wunpckehsw"
1048 [(set (match_operand:DI 0 "register_operand" "=y")
1049 (sign_extend:DI
1050 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1051 (parallel [(const_int 1)]))))]
1052 "TARGET_REALLY_IWMMXT"
1053 "wunpckehsw%?\\t%0, %1"
1054 [(set_attr "predicable" "yes")])
1056 (define_insn "iwmmxt_wunpckelub"
1057 [(set (match_operand:V4HI 0 "register_operand" "=y")
1058 (zero_extend:V4HI
1059 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1060 (parallel [(const_int 0) (const_int 1)
1061 (const_int 2) (const_int 3)]))))]
1062 "TARGET_REALLY_IWMMXT"
1063 "wunpckelub%?\\t%0, %1"
1064 [(set_attr "predicable" "yes")])
1066 (define_insn "iwmmxt_wunpckeluh"
1067 [(set (match_operand:V2SI 0 "register_operand" "=y")
1068 (zero_extend:V2SI
1069 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1070 (parallel [(const_int 0) (const_int 1)]))))]
1071 "TARGET_REALLY_IWMMXT"
1072 "wunpckeluh%?\\t%0, %1"
1073 [(set_attr "predicable" "yes")])
1075 (define_insn "iwmmxt_wunpckeluw"
1076 [(set (match_operand:DI 0 "register_operand" "=y")
1077 (zero_extend:DI
1078 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1079 (parallel [(const_int 0)]))))]
1080 "TARGET_REALLY_IWMMXT"
1081 "wunpckeluw%?\\t%0, %1"
1082 [(set_attr "predicable" "yes")])
1084 (define_insn "iwmmxt_wunpckelsb"
1085 [(set (match_operand:V4HI 0 "register_operand" "=y")
1086 (sign_extend:V4HI
1087 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1088 (parallel [(const_int 0) (const_int 1)
1089 (const_int 2) (const_int 3)]))))]
1090 "TARGET_REALLY_IWMMXT"
1091 "wunpckelsb%?\\t%0, %1"
1092 [(set_attr "predicable" "yes")])
1094 (define_insn "iwmmxt_wunpckelsh"
1095 [(set (match_operand:V2SI 0 "register_operand" "=y")
1096 (sign_extend:V2SI
1097 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1098 (parallel [(const_int 0) (const_int 1)]))))]
1099 "TARGET_REALLY_IWMMXT"
1100 "wunpckelsh%?\\t%0, %1"
1101 [(set_attr "predicable" "yes")])
1103 (define_insn "iwmmxt_wunpckelsw"
1104 [(set (match_operand:DI 0 "register_operand" "=y")
1105 (sign_extend:DI
1106 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1107 (parallel [(const_int 0)]))))]
1108 "TARGET_REALLY_IWMMXT"
1109 "wunpckelsw%?\\t%0, %1"
1110 [(set_attr "predicable" "yes")])
1112 ;; Shifts
1114 (define_insn "rorv4hi3"
1115 [(set (match_operand:V4HI 0 "register_operand" "=y")
1116 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1117 (match_operand:SI 2 "register_operand" "z")))]
1118 "TARGET_REALLY_IWMMXT"
1119 "wrorhg%?\\t%0, %1, %2"
1120 [(set_attr "predicable" "yes")])
1122 (define_insn "rorv2si3"
1123 [(set (match_operand:V2SI 0 "register_operand" "=y")
1124 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1125 (match_operand:SI 2 "register_operand" "z")))]
1126 "TARGET_REALLY_IWMMXT"
1127 "wrorwg%?\\t%0, %1, %2"
1128 [(set_attr "predicable" "yes")])
1130 (define_insn "rordi3"
1131 [(set (match_operand:DI 0 "register_operand" "=y")
1132 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1133 (match_operand:SI 2 "register_operand" "z")))]
1134 "TARGET_REALLY_IWMMXT"
1135 "wrordg%?\\t%0, %1, %2"
1136 [(set_attr "predicable" "yes")])
1138 (define_insn "ashrv4hi3"
1139 [(set (match_operand:V4HI 0 "register_operand" "=y")
1140 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1141 (match_operand:SI 2 "register_operand" "z")))]
1142 "TARGET_REALLY_IWMMXT"
1143 "wsrahg%?\\t%0, %1, %2"
1144 [(set_attr "predicable" "yes")])
1146 (define_insn "ashrv2si3"
1147 [(set (match_operand:V2SI 0 "register_operand" "=y")
1148 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1149 (match_operand:SI 2 "register_operand" "z")))]
1150 "TARGET_REALLY_IWMMXT"
1151 "wsrawg%?\\t%0, %1, %2"
1152 [(set_attr "predicable" "yes")])
1154 (define_insn "ashrdi3_iwmmxt"
1155 [(set (match_operand:DI 0 "register_operand" "=y")
1156 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1157 (match_operand:SI 2 "register_operand" "z")))]
1158 "TARGET_REALLY_IWMMXT"
1159 "wsradg%?\\t%0, %1, %2"
1160 [(set_attr "predicable" "yes")])
1162 (define_insn "lshrv4hi3"
1163 [(set (match_operand:V4HI 0 "register_operand" "=y")
1164 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1165 (match_operand:SI 2 "register_operand" "z")))]
1166 "TARGET_REALLY_IWMMXT"
1167 "wsrlhg%?\\t%0, %1, %2"
1168 [(set_attr "predicable" "yes")])
1170 (define_insn "lshrv2si3"
1171 [(set (match_operand:V2SI 0 "register_operand" "=y")
1172 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1173 (match_operand:SI 2 "register_operand" "z")))]
1174 "TARGET_REALLY_IWMMXT"
1175 "wsrlwg%?\\t%0, %1, %2"
1176 [(set_attr "predicable" "yes")])
1178 (define_insn "lshrdi3_iwmmxt"
1179 [(set (match_operand:DI 0 "register_operand" "=y")
1180 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1181 (match_operand:SI 2 "register_operand" "z")))]
1182 "TARGET_REALLY_IWMMXT"
1183 "wsrldg%?\\t%0, %1, %2"
1184 [(set_attr "predicable" "yes")])
1186 (define_insn "ashlv4hi3"
1187 [(set (match_operand:V4HI 0 "register_operand" "=y")
1188 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1189 (match_operand:SI 2 "register_operand" "z")))]
1190 "TARGET_REALLY_IWMMXT"
1191 "wsllhg%?\\t%0, %1, %2"
1192 [(set_attr "predicable" "yes")])
1194 (define_insn "ashlv2si3"
1195 [(set (match_operand:V2SI 0 "register_operand" "=y")
1196 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1197 (match_operand:SI 2 "register_operand" "z")))]
1198 "TARGET_REALLY_IWMMXT"
1199 "wsllwg%?\\t%0, %1, %2"
1200 [(set_attr "predicable" "yes")])
1202 (define_insn "ashldi3_iwmmxt"
1203 [(set (match_operand:DI 0 "register_operand" "=y")
1204 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1205 (match_operand:SI 2 "register_operand" "z")))]
1206 "TARGET_REALLY_IWMMXT"
1207 "wslldg%?\\t%0, %1, %2"
1208 [(set_attr "predicable" "yes")])
1210 (define_insn "rorv4hi3_di"
1211 [(set (match_operand:V4HI 0 "register_operand" "=y")
1212 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1213 (match_operand:DI 2 "register_operand" "y")))]
1214 "TARGET_REALLY_IWMMXT"
1215 "wrorh%?\\t%0, %1, %2"
1216 [(set_attr "predicable" "yes")])
1218 (define_insn "rorv2si3_di"
1219 [(set (match_operand:V2SI 0 "register_operand" "=y")
1220 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1221 (match_operand:DI 2 "register_operand" "y")))]
1222 "TARGET_REALLY_IWMMXT"
1223 "wrorw%?\\t%0, %1, %2"
1224 [(set_attr "predicable" "yes")])
1226 (define_insn "rordi3_di"
1227 [(set (match_operand:DI 0 "register_operand" "=y")
1228 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1229 (match_operand:DI 2 "register_operand" "y")))]
1230 "TARGET_REALLY_IWMMXT"
1231 "wrord%?\\t%0, %1, %2"
1232 [(set_attr "predicable" "yes")])
1234 (define_insn "ashrv4hi3_di"
1235 [(set (match_operand:V4HI 0 "register_operand" "=y")
1236 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1237 (match_operand:DI 2 "register_operand" "y")))]
1238 "TARGET_REALLY_IWMMXT"
1239 "wsrah%?\\t%0, %1, %2"
1240 [(set_attr "predicable" "yes")])
1242 (define_insn "ashrv2si3_di"
1243 [(set (match_operand:V2SI 0 "register_operand" "=y")
1244 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1245 (match_operand:DI 2 "register_operand" "y")))]
1246 "TARGET_REALLY_IWMMXT"
1247 "wsraw%?\\t%0, %1, %2"
1248 [(set_attr "predicable" "yes")])
1250 (define_insn "ashrdi3_di"
1251 [(set (match_operand:DI 0 "register_operand" "=y")
1252 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1253 (match_operand:DI 2 "register_operand" "y")))]
1254 "TARGET_REALLY_IWMMXT"
1255 "wsrad%?\\t%0, %1, %2"
1256 [(set_attr "predicable" "yes")])
1258 (define_insn "lshrv4hi3_di"
1259 [(set (match_operand:V4HI 0 "register_operand" "=y")
1260 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1261 (match_operand:DI 2 "register_operand" "y")))]
1262 "TARGET_REALLY_IWMMXT"
1263 "wsrlh%?\\t%0, %1, %2"
1264 [(set_attr "predicable" "yes")])
1266 (define_insn "lshrv2si3_di"
1267 [(set (match_operand:V2SI 0 "register_operand" "=y")
1268 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1269 (match_operand:DI 2 "register_operand" "y")))]
1270 "TARGET_REALLY_IWMMXT"
1271 "wsrlw%?\\t%0, %1, %2"
1272 [(set_attr "predicable" "yes")])
1274 (define_insn "lshrdi3_di"
1275 [(set (match_operand:DI 0 "register_operand" "=y")
1276 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1277 (match_operand:DI 2 "register_operand" "y")))]
1278 "TARGET_REALLY_IWMMXT"
1279 "wsrld%?\\t%0, %1, %2"
1280 [(set_attr "predicable" "yes")])
1282 (define_insn "ashlv4hi3_di"
1283 [(set (match_operand:V4HI 0 "register_operand" "=y")
1284 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1285 (match_operand:DI 2 "register_operand" "y")))]
1286 "TARGET_REALLY_IWMMXT"
1287 "wsllh%?\\t%0, %1, %2"
1288 [(set_attr "predicable" "yes")])
1290 (define_insn "ashlv2si3_di"
1291 [(set (match_operand:V2SI 0 "register_operand" "=y")
1292 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1293 (match_operand:DI 2 "register_operand" "y")))]
1294 "TARGET_REALLY_IWMMXT"
1295 "wsllw%?\\t%0, %1, %2"
1296 [(set_attr "predicable" "yes")])
1298 (define_insn "ashldi3_di"
1299 [(set (match_operand:DI 0 "register_operand" "=y")
1300 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1301 (match_operand:DI 2 "register_operand" "y")))]
1302 "TARGET_REALLY_IWMMXT"
1303 "wslld%?\\t%0, %1, %2"
1304 [(set_attr "predicable" "yes")])
1306 (define_insn "iwmmxt_wmadds"
1307 [(set (match_operand:V4HI 0 "register_operand" "=y")
1308 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1309 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1310 "TARGET_REALLY_IWMMXT"
1311 "wmadds%?\\t%0, %1, %2"
1312 [(set_attr "predicable" "yes")])
1314 (define_insn "iwmmxt_wmaddu"
1315 [(set (match_operand:V4HI 0 "register_operand" "=y")
1316 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1317 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1318 "TARGET_REALLY_IWMMXT"
1319 "wmaddu%?\\t%0, %1, %2"
1320 [(set_attr "predicable" "yes")])
1322 (define_insn "iwmmxt_tmia"
1323 [(set (match_operand:DI 0 "register_operand" "=y")
1324 (plus:DI (match_operand:DI 1 "register_operand" "0")
1325 (mult:DI (sign_extend:DI
1326 (match_operand:SI 2 "register_operand" "r"))
1327 (sign_extend:DI
1328 (match_operand:SI 3 "register_operand" "r")))))]
1329 "TARGET_REALLY_IWMMXT"
1330 "tmia%?\\t%0, %2, %3"
1331 [(set_attr "predicable" "yes")])
1333 (define_insn "iwmmxt_tmiaph"
1334 [(set (match_operand:DI 0 "register_operand" "=y")
1335 (plus:DI (match_operand:DI 1 "register_operand" "0")
1336 (plus:DI
1337 (mult:DI (sign_extend:DI
1338 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1339 (sign_extend:DI
1340 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1341 (mult:DI (sign_extend:DI
1342 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1343 (sign_extend:DI
1344 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1345 "TARGET_REALLY_IWMMXT"
1346 "tmiaph%?\\t%0, %2, %3"
1347 [(set_attr "predicable" "yes")])
1349 (define_insn "iwmmxt_tmiabb"
1350 [(set (match_operand:DI 0 "register_operand" "=y")
1351 (plus:DI (match_operand:DI 1 "register_operand" "0")
1352 (mult:DI (sign_extend:DI
1353 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1354 (sign_extend:DI
1355 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1356 "TARGET_REALLY_IWMMXT"
1357 "tmiabb%?\\t%0, %2, %3"
1358 [(set_attr "predicable" "yes")])
1360 (define_insn "iwmmxt_tmiatb"
1361 [(set (match_operand:DI 0 "register_operand" "=y")
1362 (plus:DI (match_operand:DI 1 "register_operand" "0")
1363 (mult:DI (sign_extend:DI
1364 (truncate:HI (ashiftrt:SI
1365 (match_operand:SI 2 "register_operand" "r")
1366 (const_int 16))))
1367 (sign_extend:DI
1368 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1369 "TARGET_REALLY_IWMMXT"
1370 "tmiatb%?\\t%0, %2, %3"
1371 [(set_attr "predicable" "yes")])
1373 (define_insn "iwmmxt_tmiabt"
1374 [(set (match_operand:DI 0 "register_operand" "=y")
1375 (plus:DI (match_operand:DI 1 "register_operand" "0")
1376 (mult:DI (sign_extend:DI
1377 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1378 (sign_extend:DI
1379 (truncate:HI (ashiftrt:SI
1380 (match_operand:SI 3 "register_operand" "r")
1381 (const_int 16)))))))]
1382 "TARGET_REALLY_IWMMXT"
1383 "tmiabt%?\\t%0, %2, %3"
1384 [(set_attr "predicable" "yes")])
1386 (define_insn "iwmmxt_tmiatt"
1387 [(set (match_operand:DI 0 "register_operand" "=y")
1388 (plus:DI (match_operand:DI 1 "register_operand" "0")
1389 (mult:DI (sign_extend:DI
1390 (truncate:HI (ashiftrt:SI
1391 (match_operand:SI 2 "register_operand" "r")
1392 (const_int 16))))
1393 (sign_extend:DI
1394 (truncate:HI (ashiftrt:SI
1395 (match_operand:SI 3 "register_operand" "r")
1396 (const_int 16)))))))]
1397 "TARGET_REALLY_IWMMXT"
1398 "tmiatt%?\\t%0, %2, %3"
1399 [(set_attr "predicable" "yes")])
1401 (define_insn "iwmmxt_tbcstqi"
1402 [(set (match_operand:V8QI 0 "register_operand" "=y")
1403 (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1404 "TARGET_REALLY_IWMMXT"
1405 "tbcstb%?\\t%0, %1"
1406 [(set_attr "predicable" "yes")])
1408 (define_insn "iwmmxt_tbcsthi"
1409 [(set (match_operand:V4HI 0 "register_operand" "=y")
1410 (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1411 "TARGET_REALLY_IWMMXT"
1412 "tbcsth%?\\t%0, %1"
1413 [(set_attr "predicable" "yes")])
1415 (define_insn "iwmmxt_tbcstsi"
1416 [(set (match_operand:V2SI 0 "register_operand" "=y")
1417 (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1418 "TARGET_REALLY_IWMMXT"
1419 "tbcstw%?\\t%0, %1"
1420 [(set_attr "predicable" "yes")])
1422 (define_insn "iwmmxt_tmovmskb"
1423 [(set (match_operand:SI 0 "register_operand" "=r")
1424 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1425 "TARGET_REALLY_IWMMXT"
1426 "tmovmskb%?\\t%0, %1"
1427 [(set_attr "predicable" "yes")])
1429 (define_insn "iwmmxt_tmovmskh"
1430 [(set (match_operand:SI 0 "register_operand" "=r")
1431 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1432 "TARGET_REALLY_IWMMXT"
1433 "tmovmskh%?\\t%0, %1"
1434 [(set_attr "predicable" "yes")])
1436 (define_insn "iwmmxt_tmovmskw"
1437 [(set (match_operand:SI 0 "register_operand" "=r")
1438 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1439 "TARGET_REALLY_IWMMXT"
1440 "tmovmskw%?\\t%0, %1"
1441 [(set_attr "predicable" "yes")])
1443 (define_insn "iwmmxt_waccb"
1444 [(set (match_operand:DI 0 "register_operand" "=y")
1445 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1446 "TARGET_REALLY_IWMMXT"
1447 "waccb%?\\t%0, %1"
1448 [(set_attr "predicable" "yes")])
1450 (define_insn "iwmmxt_wacch"
1451 [(set (match_operand:DI 0 "register_operand" "=y")
1452 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1453 "TARGET_REALLY_IWMMXT"
1454 "wacch%?\\t%0, %1"
1455 [(set_attr "predicable" "yes")])
1457 (define_insn "iwmmxt_waccw"
1458 [(set (match_operand:DI 0 "register_operand" "=y")
1459 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1460 "TARGET_REALLY_IWMMXT"
1461 "waccw%?\\t%0, %1"
1462 [(set_attr "predicable" "yes")])
1464 (define_insn "iwmmxt_walign"
1465 [(set (match_operand:V8QI 0 "register_operand" "=y,y")
1466 (subreg:V8QI (ashiftrt:TI
1467 (subreg:TI (vec_concat:V16QI
1468 (match_operand:V8QI 1 "register_operand" "y,y")
1469 (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1470 (mult:SI
1471 (match_operand:SI 3 "nonmemory_operand" "i,z")
1472 (const_int 8))) 0))]
1473 "TARGET_REALLY_IWMMXT"
1474 "@
1475 waligni%?\\t%0, %1, %2, %3
1476 walignr%U3%?\\t%0, %1, %2"
1477 [(set_attr "predicable" "yes")])
1479 (define_insn "iwmmxt_tmrc"
1480 [(set (match_operand:SI 0 "register_operand" "=r")
1481 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1482 VUNSPEC_TMRC))]
1483 "TARGET_REALLY_IWMMXT"
1484 "tmrc%?\\t%0, %w1"
1485 [(set_attr "predicable" "yes")])
1487 (define_insn "iwmmxt_tmcr"
1488 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1489 (match_operand:SI 1 "register_operand" "r")]
1490 VUNSPEC_TMCR)]
1491 "TARGET_REALLY_IWMMXT"
1492 "tmcr%?\\t%w0, %1"
1493 [(set_attr "predicable" "yes")])
1495 (define_insn "iwmmxt_wsadb"
1496 [(set (match_operand:V8QI 0 "register_operand" "=y")
1497 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1498 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1499 "TARGET_REALLY_IWMMXT"
1500 "wsadb%?\\t%0, %1, %2"
1501 [(set_attr "predicable" "yes")])
1503 (define_insn "iwmmxt_wsadh"
1504 [(set (match_operand:V4HI 0 "register_operand" "=y")
1505 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1506 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1507 "TARGET_REALLY_IWMMXT"
1508 "wsadh%?\\t%0, %1, %2"
1509 [(set_attr "predicable" "yes")])
1511 (define_insn "iwmmxt_wsadbz"
1512 [(set (match_operand:V8QI 0 "register_operand" "=y")
1513 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1514 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1515 "TARGET_REALLY_IWMMXT"
1516 "wsadbz%?\\t%0, %1, %2"
1517 [(set_attr "predicable" "yes")])
1519 (define_insn "iwmmxt_wsadhz"
1520 [(set (match_operand:V4HI 0 "register_operand" "=y")
1521 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1522 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1523 "TARGET_REALLY_IWMMXT"
1524 "wsadhz%?\\t%0, %1, %2"
1525 [(set_attr "predicable" "yes")])