cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #if HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  22 #include <sys/types.h>
  23 #include <sys/sysctl.h>
  24 #elif defined(__linux__)
  25 #include <signal.h>
  26 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  27 #include <windows.h>
  28 #elif defined(__OS2__)
  29 #define INCL_DOS
  30 #include <os2.h>
  31 #elif defined(__AMIGAOS4__)
  32 #include <proto/exec.h>
  33 #endif
  34
  35 /* Thanks to the FreeBSD project for some of this cpuid code, and
  36  * help understanding how to use it.  Thanks to the Mesa
  37  * team for SSE support detection and more cpu detect code.
  38  */
  39
  40 /* I believe this code works.  However, it has only been used on a PII and PIII */
  41
  42 static void check_os_katmai_support( void );
  43
  44 // return TRUE if cpuid supported
  45 static int has_cpuid(void)
  46 {
  47 // code from libavcodec:
  48 #if ARCH_X86_64
  49    return 1;
  50 #else
  51         long a, c;
  52     __asm__ volatile (
  53                           /* See if CPUID instruction is supported ... */
  54                           /* ... Get copies of EFLAGS into eax and ecx */
  55                           "pushfl\n\t"
  56                           "pop %0\n\t"
  57                           "mov %0, %1\n\t"
  58
  59                           /* ... Toggle the ID bit in one copy and store */
  60                           /*     to the EFLAGS reg */
  61                           "xor $0x200000, %0\n\t"
  62                           "push %0\n\t"
  63                           "popfl\n\t"
  64
  65                           /* ... Get the (hopefully modified) EFLAGS */
  66                           "pushfl\n\t"
  67                           "pop %0\n\t"
  68                           : "=a" (a), "=c" (c)
  69                           :
  70                           : "cc"
  71                           );
  72
  73         return a != c;
  74 #endif
  75 }
  76
  77 static void
  78 do_cpuid(unsigned int ax, unsigned int *p)
  79 {
  80 #if 0
  81         __asm__ volatile(
  82         "cpuid;"
  83         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  84         :  "0" (ax)
  85         );
  86 #else
  87 // code from libavcodec:
  88     __asm__ volatile
  89         ("mov %%"REG_b", %%"REG_S"\n\t"
  90          "cpuid\n\t"
  91          "xchg %%"REG_b", %%"REG_S
  92          : "=a" (p[0]), "=S" (p[1]),
  93            "=c" (p[2]), "=d" (p[3])
  94          : "0" (ax));
  95 #endif
  96
  97 }
  98
  99 void GetCpuCaps( CpuCaps *caps)
 100 {
 101         unsigned int regs[4];
 102         unsigned int regs2[4];
 103
 104         memset(caps, 0, sizeof(*caps));
 105         caps->isX86=1;
 106         caps->cl_size=32; /* default */
 107         if (!has_cpuid()) {
 108             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 109             return;
 110         }
 111         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 112         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 113                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 114         if (regs[0]>=0x00000001)
 115         {
 116                 char *tmpstr, *ptmpstr;
 117                 unsigned cl_size;
 118
 119                 do_cpuid(0x00000001, regs2);
 120
 121                 caps->cpuType=(regs2[0] >> 8)&0xf;
 122                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 123
 124 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 125 // System Instructions, Table 3-2: Effective family computation, page 120.
 126                 if(caps->cpuType==0xf){
 127                     // use extended family (P4, IA64, K8)
 128                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 129                 }
 130                 if(caps->cpuType==0xf || caps->cpuType==6)
 131                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 132
 133                 caps->cpuStepping=regs2[0] & 0xf;
 134
 135                 // general feature flags:
 136                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 137                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 138                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 139                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 140                 caps->hasSSE3 = (regs2[2] & 1);                // 0x0000001
 141                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 142                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 143                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 144                 if(cl_size) caps->cl_size = cl_size;
 145
 146                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 147                 while(*ptmpstr == ' ')        // strip leading spaces
 148                     ptmpstr++;
 149                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 150                 free(tmpstr);
 151                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 152                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 153
 154         }
 155         do_cpuid(0x80000000, regs);
 156         if (regs[0]>=0x80000001) {
 157                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 158                 do_cpuid(0x80000001, regs2);
 159                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 160                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 161                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 162                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 163                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 164         }
 165         if(regs[0]>=0x80000006)
 166         {
 167                 do_cpuid(0x80000006, regs2);
 168                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 169                 caps->cl_size  = regs2[2] & 0xFF;
 170         }
 171         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 172 #if 0
 173         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 174                 gCpuCaps.hasMMX,
 175                 gCpuCaps.hasMMX2,
 176                 gCpuCaps.hasSSE,
 177                 gCpuCaps.hasSSE2,
 178                 gCpuCaps.has3DNow,
 179                 gCpuCaps.has3DNowExt );
 180 #endif
 181
 182                 /* FIXME: Does SSE2 need more OS support, too? */
 183 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 184   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 185   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 186   || defined(__OS2__)
 187                 if (caps->hasSSE)
 188                         check_os_katmai_support();
 189                 if (!caps->hasSSE)
 190                         caps->hasSSE2 = 0;
 191 #else
 192                 caps->hasSSE=0;
 193                 caps->hasSSE2 = 0;
 194 #endif
 195 //              caps->has3DNow=1;
 196 //              caps->hasMMX2 = 0;
 197 //              caps->hasMMX = 0;
 198
 199 #ifndef RUNTIME_CPUDETECT
 200 #if !HAVE_MMX
 201         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 202         caps->hasMMX=0;
 203 #endif
 204 #if !HAVE_MMX2
 205         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 206         caps->hasMMX2=0;
 207 #endif
 208 #if !HAVE_SSE
 209         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 210         caps->hasSSE=0;
 211 #endif
 212 #if !HAVE_SSE2
 213         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 214         caps->hasSSE2=0;
 215 #endif
 216 #if !HAVE_AMD3DNOW
 217         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 218         caps->has3DNow=0;
 219 #endif
 220 #if !HAVE_AMD3DNOWEXT
 221         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 222         caps->has3DNowExt=0;
 223 #endif
 224 #endif  // RUNTIME_CPUDETECT
 225 }
 226
 227 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 228         char vendor[13];
 229         char *retname;
 230         int i;
 231
 232         if (NULL==(retname=malloc(256))) {
 233                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 234                 exit(1);
 235         }
 236         retname[0] = '\0';
 237
 238         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 239
 240         do_cpuid(0x80000000,regs);
 241         if (regs[0] >= 0x80000004)
 242         {
 243                 // CPU has built-in namestring
 244                 for (i = 0x80000002; i <= 0x80000004; i++)
 245                 {
 246                         do_cpuid(i, regs);
 247                         strncat(retname, (char*)regs, 16);
 248                 }
 249         }
 250         return retname;
 251 }
 252
 253 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 254 static void sigill_handler_sse( int signal, struct sigcontext sc )
 255 {
 256    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 257
 258    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 259     * instructions are 3 bytes long.  We must increment the instruction
 260     * pointer manually to avoid repeated execution of the offending
 261     * instruction.
 262     *
 263     * If the SIGILL is caused by a divide-by-zero when unmasked
 264     * exceptions aren't supported, the SIMD FPU status and control
 265     * word will be restored at the end of the test, so we don't need
 266     * to worry about doing it here.  Besides, we may not be able to...
 267     */
 268    sc.eip += 3;
 269
 270    gCpuCaps.hasSSE=0;
 271 }
 272 #endif /* __linux__ && _POSIX_SOURCE */
 273
 274 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
 275 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 276 {
 277    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 278       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 279       ep->ContextRecord->Eip +=3;
 280       gCpuCaps.hasSSE=0;
 281           return EXCEPTION_CONTINUE_EXECUTION;
 282    }
 283    return EXCEPTION_CONTINUE_SEARCH;
 284 }
 285 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 286
 287 #ifdef __OS2__
 288 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 289                                    PEXCEPTIONREGISTRATIONRECORD p2,
 290                                    PCONTEXTRECORD               p3,
 291                                    PVOID                        p4 )
 292 {
 293    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 294       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 295
 296       p3->ctx_RegEip += 3;
 297       gCpuCaps.hasSSE = 0;
 298
 299       return XCPT_CONTINUE_EXECUTION;
 300    }
 301    return XCPT_CONTINUE_SEARCH;
 302 }
 303 #endif
 304
 305 /* If we're running on a processor that can do SSE, let's see if we
 306  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 307  * haven't been configured for a Pentium III but are running on one,
 308  * and RedHat patched 2.2 kernels that have broken exception handling
 309  * support for user space apps that do SSE.
 310  */
 311
 312 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 313 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 314 #elif defined(__APPLE__)
 315 #define SSE_SYSCTL_NAME "hw.optional.sse"
 316 #endif
 317
 318 static void check_os_katmai_support( void )
 319 {
 320 #if ARCH_X86_64
 321    gCpuCaps.hasSSE=1;
 322    gCpuCaps.hasSSE2=1;
 323 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 324    int has_sse=0, ret;
 325    size_t len=sizeof(has_sse);
 326
 327    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 328    if (ret || !has_sse)
 329       gCpuCaps.hasSSE=0;
 330
 331 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 332 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 333    int has_sse, has_sse2, ret, mib[2];
 334    size_t varlen;
 335
 336    mib[0] = CTL_MACHDEP;
 337    mib[1] = CPU_SSE;
 338    varlen = sizeof(has_sse);
 339
 340    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 341    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 342    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 343    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 344
 345    mib[1] = CPU_SSE2;
 346    varlen = sizeof(has_sse2);
 347    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 348    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 349    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 350    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 351 #else
 352    gCpuCaps.hasSSE = 0;
 353    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 354 #endif
 355 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 356    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 357    if ( gCpuCaps.hasSSE ) {
 358       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 359       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 360       __asm__ volatile ("xorps %xmm0, %xmm0");
 361       SetUnhandledExceptionFilter(exc_fil);
 362       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 363    }
 364 #elif defined(__OS2__)
 365    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 366    if ( gCpuCaps.hasSSE ) {
 367       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 368       DosSetExceptionHandler( &RegRec );
 369       __asm__ volatile ("xorps %xmm0, %xmm0");
 370       DosUnsetExceptionHandler( &RegRec );
 371       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 372    }
 373 #elif defined(__linux__)
 374 #if defined(_POSIX_SOURCE)
 375    struct sigaction saved_sigill;
 376
 377    /* Save the original signal handlers.
 378     */
 379    sigaction( SIGILL, NULL, &saved_sigill );
 380
 381    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 382
 383    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 384     * supports the extended FPU save and restore required for SSE.  If
 385     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 386     * doesn't support Streaming SIMD Exceptions, even if the processor
 387     * does.
 388     */
 389    if ( gCpuCaps.hasSSE ) {
 390       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 391
 392 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 393       __asm__ volatile ("xorps %xmm0, %xmm0");
 394
 395       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 396    }
 397
 398    /* Restore the original signal handlers.
 399     */
 400    sigaction( SIGILL, &saved_sigill, NULL );
 401
 402    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 403     * safe to go ahead and hook out the SSE code throughout Mesa.
 404     */
 405    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 406 #else
 407    /* We can't use POSIX signal handling to test the availability of
 408     * SSE, so we disable it by default.
 409     */
 410    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 411    gCpuCaps.hasSSE=0;
 412 #endif /* _POSIX_SOURCE */
 413 #else
 414    /* Do nothing on other platforms for now.
 415     */
 416    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 417    gCpuCaps.hasSSE=0;
 418 #endif /* __linux__ */
 419 }
 420 #else /* ARCH_X86 */
 421
 422 #ifdef __APPLE__
 423 #include <sys/sysctl.h>
 424 #elif defined(__AMIGAOS4__)
 425 /* nothing */
 426 #else
 427 #include <signal.h>
 428 #include <setjmp.h>
 429
 430 static sigjmp_buf jmpbuf;
 431 static volatile sig_atomic_t canjump = 0;
 432
 433 static void sigill_handler (int sig)
 434 {
 435     if (!canjump) {
 436         signal (sig, SIG_DFL);
 437         raise (sig);
 438     }
 439
 440     canjump = 0;
 441     siglongjmp (jmpbuf, 1);
 442 }
 443 #endif /* __APPLE__ */
 444
 445 void GetCpuCaps( CpuCaps *caps)
 446 {
 447         caps->cpuType=0;
 448         caps->cpuModel=0;
 449         caps->cpuStepping=0;
 450         caps->hasMMX=0;
 451         caps->hasMMX2=0;
 452         caps->has3DNow=0;
 453         caps->has3DNowExt=0;
 454         caps->hasSSE=0;
 455         caps->hasSSE2=0;
 456         caps->hasSSE3=0;
 457         caps->hasSSSE3=0;
 458         caps->hasSSE4a=0;
 459         caps->isX86=0;
 460         caps->hasAltiVec = 0;
 461 #if HAVE_ALTIVEC
 462 #ifdef __APPLE__
 463 /*
 464   rip-off from ffmpeg altivec detection code.
 465   this code also appears on Apple's AltiVec pages.
 466  */
 467         {
 468                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 469                 int has_vu = 0;
 470                 size_t len = sizeof(has_vu);
 471                 int err;
 472
 473                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 474
 475                 if (err == 0)
 476                         if (has_vu != 0)
 477                                 caps->hasAltiVec = 1;
 478         }
 479 #elif defined(__AMIGAOS4__)
 480         ULONG result = 0;
 481
 482         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 483         if (result == VECTORTYPE_ALTIVEC)
 484                 caps->hasAltiVec = 1;
 485 #else
 486 /* no Darwin, do it the brute-force way */
 487 /* this is borrowed from the libmpeg2 library */
 488         {
 489           signal (SIGILL, sigill_handler);
 490           if (sigsetjmp (jmpbuf, 1)) {
 491             signal (SIGILL, SIG_DFL);
 492           } else {
 493             canjump = 1;
 494
 495             __asm__ volatile ("mtspr 256, %0\n\t"
 496                           "vand %%v0, %%v0, %%v0"
 497                           :
 498                           : "r" (-1));
 499
 500             signal (SIGILL, SIG_DFL);
 501             caps->hasAltiVec = 1;
 502           }
 503         }
 504 #endif /* __APPLE__ */
 505         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 506 #endif /* HAVE_ALTIVEC */
 507
 508 if (ARCH_IA64)
 509         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 510
 511 if (ARCH_SPARC)
 512         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 513
 514 if (ARCH_ARM)
 515         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 516
 517 if (ARCH_PPC)
 518         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 519
 520 if (ARCH_ALPHA)
 521         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 522
 523 if (ARCH_SGI_MIPS)
 524         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
 525
 526 if (ARCH_PA_RISC)
 527         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 528
 529 if (ARCH_S390)
 530         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 531
 532 if (ARCH_S390X)
 533         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 534
 535 if (ARCH_VAX)
 536         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 537
 538 if (ARCH_XTENSA)
 539         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 540 }
 541 #endif /* !ARCH_X86 */