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vo_glamo: sub.h was moved to sub directory in c9026cb3210205b07e2e068467a18ee40f9259a3
[mplayer/glamo.git] / drivers / libglamo / glamo-regs.h
blob4359a242c70f60632005c51bb728bdb42b8f709a
1 #ifndef _GLAMO_REGS_H
2 #define _GLAMO_REGS_H
3
4 /* Smedia Glamo 336x/337x driver
5 *
6 * (C) 2007 by OpenMoko, Inc.
7 * Author: Harald Welte <laforge@openmoko.org>
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 enum glamo_regster_offsets {
27 GLAMO_REGOFS_GENERIC = 0x0000,
28 GLAMO_REGOFS_HOSTBUS = 0x0200,
29 GLAMO_REGOFS_MEMORY = 0x0300,
30 GLAMO_REGOFS_VIDCAP = 0x0400,
31 GLAMO_REGOFS_ISP = 0x0500,
32 GLAMO_REGOFS_JPEG = 0x0800,
33 GLAMO_REGOFS_MPEG = 0x0c00,
34 GLAMO_REGOFS_LCD = 0x1100,
35 GLAMO_REGOFS_MMC = 0x1400,
36 GLAMO_REGOFS_MPROC0 = 0x1500,
37 GLAMO_REGOFS_MPROC1 = 0x1580,
38 GLAMO_REGOFS_CMDQUEUE = 0x1600,
39 GLAMO_REGOFS_RISC = 0x1680,
40 GLAMO_REGOFS_2D = 0x1700,
41 GLAMO_REGOFS_3D = 0x1b00,
42 };
43
44
45 enum glamo_register_generic {
46 GLAMO_REG_GCONF1 = 0x0000,
47 GLAMO_REG_GCONF2 = 0x0002,
48 #define GLAMO_REG_DEVICE_ID GLAMO_REG_GCONF2
49 GLAMO_REG_GCONF3 = 0x0004,
50 #define GLAMO_REG_REVISION_ID GLAMO_REG_GCONF3
51 GLAMO_REG_IRQ_GEN1 = 0x0006,
52 #define GLAMO_REG_IRQ_ENABLE GLAMO_REG_IRQ_GEN1
53 GLAMO_REG_IRQ_GEN2 = 0x0008,
54 #define GLAMO_REG_IRQ_SET GLAMO_REG_IRQ_GEN2
55 GLAMO_REG_IRQ_GEN3 = 0x000a,
56 #define GLAMO_REG_IRQ_CLEAR GLAMO_REG_IRQ_GEN3
57 GLAMO_REG_IRQ_GEN4 = 0x000c,
58 #define GLAMO_REG_IRQ_STATUS GLAMO_REG_IRQ_GEN4
59 GLAMO_REG_CLOCK_HOST = 0x0010,
60 GLAMO_REG_CLOCK_MEMORY = 0x0012,
61 GLAMO_REG_CLOCK_LCD = 0x0014,
62 GLAMO_REG_CLOCK_MMC = 0x0016,
63 GLAMO_REG_CLOCK_ISP = 0x0018,
64 GLAMO_REG_CLOCK_JPEG = 0x001a,
65 GLAMO_REG_CLOCK_3D = 0x001c,
66 GLAMO_REG_CLOCK_2D = 0x001e,
67 GLAMO_REG_CLOCK_RISC1 = 0x0020, /* 3365 only? */
68 GLAMO_REG_CLOCK_RISC2 = 0x0022, /* 3365 only? */
69 GLAMO_REG_CLOCK_MPEG = 0x0024,
70 GLAMO_REG_CLOCK_MPROC = 0x0026,
71
72 GLAMO_REG_CLOCK_GEN5_1 = 0x0030,
73 GLAMO_REG_CLOCK_GEN5_2 = 0x0032,
74 GLAMO_REG_CLOCK_GEN6 = 0x0034,
75 GLAMO_REG_CLOCK_GEN7 = 0x0036,
76 GLAMO_REG_CLOCK_GEN8 = 0x0038,
77 GLAMO_REG_CLOCK_GEN9 = 0x003a,
78 GLAMO_REG_CLOCK_GEN10 = 0x003c,
79 GLAMO_REG_CLOCK_GEN11 = 0x003e,
80 GLAMO_REG_PLL_GEN1 = 0x0040,
81 GLAMO_REG_PLL_GEN2 = 0x0042,
82 GLAMO_REG_PLL_GEN3 = 0x0044,
83 GLAMO_REG_PLL_GEN4 = 0x0046,
84 GLAMO_REG_PLL_GEN5 = 0x0048,
85 GLAMO_REG_GPIO_GEN1 = 0x0050,
86 GLAMO_REG_GPIO_GEN2 = 0x0052,
87 GLAMO_REG_GPIO_GEN3 = 0x0054,
88 GLAMO_REG_GPIO_GEN4 = 0x0056,
89 GLAMO_REG_GPIO_GEN5 = 0x0058,
90 GLAMO_REG_GPIO_GEN6 = 0x005a,
91 GLAMO_REG_GPIO_GEN7 = 0x005c,
92 GLAMO_REG_GPIO_GEN8 = 0x005e,
93 GLAMO_REG_GPIO_GEN9 = 0x0060,
94 GLAMO_REG_GPIO_GEN10 = 0x0062,
95 GLAMO_REG_DFT_GEN1 = 0x0070,
96 GLAMO_REG_DFT_GEN2 = 0x0072,
97 GLAMO_REG_DFT_GEN3 = 0x0074,
98 GLAMO_REG_DFT_GEN4 = 0x0076,
99
100 GLAMO_REG_DFT_GEN5 = 0x01e0,
101 GLAMO_REG_DFT_GEN6 = 0x01f0,
102 };
103
104 #define GLAMO_REG_HOSTBUS(x) (GLAMO_REGOFS_HOSTBUS-2+(x*2))
105
106 #define REG_MEM(x) (GLAMO_REGOFS_MEMORY+(x))
107 #define GLAMO_REG_MEM_TIMING(x) (GLAMO_REG_MEM_TIMING1-2+(x*2))
108
109 enum glamo_register_mem {
110 GLAMO_REG_MEM_TYPE = REG_MEM(0x00),
111 GLAMO_REG_MEM_GEN = REG_MEM(0x02),
112 GLAMO_REG_MEM_TIMING1 = REG_MEM(0x04),
113 GLAMO_REG_MEM_TIMING2 = REG_MEM(0x06),
114 GLAMO_REG_MEM_TIMING3 = REG_MEM(0x08),
115 GLAMO_REG_MEM_TIMING4 = REG_MEM(0x0a),
116 GLAMO_REG_MEM_TIMING5 = REG_MEM(0x0c),
117 GLAMO_REG_MEM_TIMING6 = REG_MEM(0x0e),
118 GLAMO_REG_MEM_TIMING7 = REG_MEM(0x10),
119 GLAMO_REG_MEM_TIMING8 = REG_MEM(0x12),
120 GLAMO_REG_MEM_TIMING9 = REG_MEM(0x14),
121 GLAMO_REG_MEM_TIMING10 = REG_MEM(0x16),
122 GLAMO_REG_MEM_TIMING11 = REG_MEM(0x18),
123 GLAMO_REG_MEM_POWER1 = REG_MEM(0x1a),
124 GLAMO_REG_MEM_POWER2 = REG_MEM(0x1c),
125 GLAMO_REG_MEM_LCD_BUF1 = REG_MEM(0x1e),
126 GLAMO_REG_MEM_LCD_BUF2 = REG_MEM(0x20),
127 GLAMO_REG_MEM_LCD_BUF3 = REG_MEM(0x22),
128 GLAMO_REG_MEM_LCD_BUF4 = REG_MEM(0x24),
129 GLAMO_REG_MEM_BIST1 = REG_MEM(0x26),
130 GLAMO_REG_MEM_BIST2 = REG_MEM(0x28),
131 GLAMO_REG_MEM_BIST3 = REG_MEM(0x2a),
132 GLAMO_REG_MEM_BIST4 = REG_MEM(0x2c),
133 GLAMO_REG_MEM_BIST5 = REG_MEM(0x2e),
134 GLAMO_REG_MEM_MAH1 = REG_MEM(0x30),
135 GLAMO_REG_MEM_MAH2 = REG_MEM(0x32),
136 GLAMO_REG_MEM_DRAM1 = REG_MEM(0x34),
137 GLAMO_REG_MEM_DRAM2 = REG_MEM(0x36),
138 GLAMO_REG_MEM_CRC = REG_MEM(0x38),
139 };
140
141 #define GLAMO_MEM_TYPE_MASK 0x03
142
143 enum glamo_reg_mem_dram1 {
144 GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11),
145 GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),
146 };
147
148 enum glamo_reg_mem_dram2 {
149 GLAMO_MEM_DRAM2_DEEP_PWRDOWN = (1 << 12),
150 };
151
152 enum glamo_irq {
153 GLAMO_IRQ_HOSTBUS = 0x0001,
154 GLAMO_IRQ_JPEG = 0x0002,
155 GLAMO_IRQ_MPEG = 0x0004,
156 GLAMO_IRQ_MPROC1 = 0x0008,
157 GLAMO_IRQ_MPROC0 = 0x0010,
158 GLAMO_IRQ_CMDQUEUE = 0x0020,
159 GLAMO_IRQ_2D = 0x0040,
160 GLAMO_IRQ_MMC = 0x0080,
161 GLAMO_IRQ_RISC = 0x0100,
162 };
163
164 enum glamo_reg_clock_host {
165 GLAMO_CLOCK_HOST_DG_BCLK = 0x0001,
166 GLAMO_CLOCK_HOST_DG_M0CLK = 0x0004,
167 GLAMO_CLOCK_HOST_RESET = 0x1000,
168 };
169
170 enum glamo_reg_clock_mem {
171 GLAMO_CLOCK_MEM_DG_M1CLK = 0x0001,
172 GLAMO_CLOCK_MEM_EN_M1CLK = 0x0002,
173 GLAMO_CLOCK_MEM_DG_MOCACLK = 0x0004,
174 GLAMO_CLOCK_MEM_EN_MOCACLK = 0x0008,
175 GLAMO_CLOCK_MEM_RESET = 0x1000,
176 GLAMO_CLOCK_MOCA_RESET = 0x2000,
177 };
178
179 enum glamo_reg_clock_lcd {
180 GLAMO_CLOCK_LCD_DG_DCLK = 0x0001,
181 GLAMO_CLOCK_LCD_EN_DCLK = 0x0002,
182 GLAMO_CLOCK_LCD_DG_DMCLK = 0x0004,
183 GLAMO_CLOCK_LCD_EN_DMCLK = 0x0008,
184 //
185 GLAMO_CLOCK_LCD_EN_DHCLK = 0x0020,
186 GLAMO_CLOCK_LCD_DG_M5CLK = 0x0040,
187 GLAMO_CLOCK_LCD_EN_M5CLK = 0x0080,
188 GLAMO_CLOCK_LCD_RESET = 0x1000,
189 };
190
191 enum glamo_reg_clock_mmc {
192 GLAMO_CLOCK_MMC_DG_TCLK = 0x0001,
193 GLAMO_CLOCK_MMC_EN_TCLK = 0x0002,
194 GLAMO_CLOCK_MMC_DG_M9CLK = 0x0004,
195 GLAMO_CLOCK_MMC_EN_M9CLK = 0x0008,
196 GLAMO_CLOCK_MMC_RESET = 0x1000,
197 };
198
199 enum glamo_reg_clock_isp {
200 GLAMO_CLOCK_ISP_DG_I1CLK = 0x0001,
201 GLAMO_CLOCK_ISP_EN_I1CLK = 0x0002,
202 GLAMO_CLOCK_ISP_DG_CCLK = 0x0004,
203 GLAMO_CLOCK_ISP_EN_CCLK = 0x0008,
204 //
205 GLAMO_CLOCK_ISP_EN_SCLK = 0x0020,
206 GLAMO_CLOCK_ISP_DG_M2CLK = 0x0040,
207 GLAMO_CLOCK_ISP_EN_M2CLK = 0x0080,
208 GLAMO_CLOCK_ISP_DG_M15CLK = 0x0100,
209 GLAMO_CLOCK_ISP_EN_M15CLK = 0x0200,
210 GLAMO_CLOCK_ISP1_RESET = 0x1000,
211 GLAMO_CLOCK_ISP2_RESET = 0x2000,
212 };
213
214 enum glamo_reg_clock_jpeg {
215 GLAMO_CLOCK_JPEG_DG_JCLK = 0x0001,
216 GLAMO_CLOCK_JPEG_EN_JCLK = 0x0002,
217 GLAMO_CLOCK_JPEG_DG_M3CLK = 0x0004,
218 GLAMO_CLOCK_JPEG_EN_M3CLK = 0x0008,
219 GLAMO_CLOCK_JPEG_RESET = 0x1000,
220 };
221
222 enum glamo_reg_clock_2d {
223 GLAMO_CLOCK_2D_DG_GCLK = 0x0001,
224 GLAMO_CLOCK_2D_EN_GCLK = 0x0002,
225 GLAMO_CLOCK_2D_DG_M7CLK = 0x0004,
226 GLAMO_CLOCK_2D_EN_M7CLK = 0x0008,
227 GLAMO_CLOCK_2D_DG_M6CLK = 0x0010,
228 GLAMO_CLOCK_2D_EN_M6CLK = 0x0020,
229 GLAMO_CLOCK_2D_RESET = 0x1000,
230 GLAMO_CLOCK_2D_CMDQ_RESET = 0x2000,
231 };
232
233 enum glamo_reg_clock_3d {
234 GLAMO_CLOCK_3D_DG_ECLK = 0x0001,
235 GLAMO_CLOCK_3D_EN_ECLK = 0x0002,
236 GLAMO_CLOCK_3D_DG_RCLK = 0x0004,
237 GLAMO_CLOCK_3D_EN_RCLK = 0x0008,
238 GLAMO_CLOCK_3D_DG_M8CLK = 0x0010,
239 GLAMO_CLOCK_3D_EN_M8CLK = 0x0020,
240 GLAMO_CLOCK_3D_BACK_RESET = 0x1000,
241 GLAMO_CLOCK_3D_FRONT_RESET = 0x2000,
242 };
243
244 enum glamo_reg_clock_mpeg {
245 GLAMO_CLOCK_MPEG_DG_X0CLK = 0x0001,
246 GLAMO_CLOCK_MPEG_EN_X0CLK = 0x0002,
247 GLAMO_CLOCK_MPEG_DG_X1CLK = 0x0004,
248 GLAMO_CLOCK_MPEG_EN_X1CLK = 0x0008,
249 GLAMO_CLOCK_MPEG_DG_X2CLK = 0x0010,
250 GLAMO_CLOCK_MPEG_EN_X2CLK = 0x0020,
251 GLAMO_CLOCK_MPEG_DG_X3CLK = 0x0040,
252 GLAMO_CLOCK_MPEG_EN_X3CLK = 0x0080,
253 GLAMO_CLOCK_MPEG_DG_X4CLK = 0x0100,
254 GLAMO_CLOCK_MPEG_EN_X4CLK = 0x0200,
255 GLAMO_CLOCK_MPEG_DG_X6CLK = 0x0400,
256 GLAMO_CLOCK_MPEG_EN_X6CLK = 0x0800,
257 GLAMO_CLOCK_MPEG_ENC_RESET = 0x1000,
258 GLAMO_CLOCK_MPEG_DEC_RESET = 0x2000,
259 };
260
261 enum glamo_reg_clock_mproc {
262 GLAMO_CLOCK_MPROC_DG_I0CLK = 0x0001,
263 GLAMO_CLOCK_MPROC_EN_I0CLK = 0x0002,
264 GLAMO_CLOCK_MPROC_DG_X5CLK = 0x0004,
265 GLAMO_CLOCK_MPROC_EN_X5CLK = 0x0008,
266 //
267 GLAMO_CLOCK_MPROC_EN_KCLK = 0x0020,
268 GLAMO_CLOCK_MPROC_DG_M4CLK = 0x0040,
269 GLAMO_CLOCK_MPROC_EN_M4CLK = 0x0080,
270 GLAMO_CLOCK_MPROC_DG_M10CLK = 0x0100,
271 GLAMO_CLOCK_MPROC_EN_M10CLK = 0x0200,
272 GLAMO_CLOCK_MPROC_RESET = 0x1000,
273 };
274
275 enum glamo_reg_clock51 {
276 GLAMO_CLOCK_GEN51_EN_DIV_MCLK = 0x0001,
277 GLAMO_CLOCK_GEN51_EN_DIV_SCLK = 0x0002,
278 GLAMO_CLOCK_GEN51_EN_DIV_JCLK = 0x0004,
279 GLAMO_CLOCK_GEN51_EN_DIV_DCLK = 0x0008,
280 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK = 0x0010,
281 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK = 0x0020,
282 GLAMO_CLOCK_GEN51_EN_DIV_GCLK = 0x0040,
283 GLAMO_CLOCK_GEN51_EN_DIV_TCLK = 0x0080,
284 /* FIXME: higher bits */
285 };
286
287 enum glamo_reg_clock52 {
288 GLAMO_CLOCK_GEN52_EN_DIV_ACLK = 0x0001,
289 GLAMO_CLOCK_GEN52_EN_DIV_AMCLK = 0x0002,
290 GLAMO_CLOCK_GEN52_EN_DIV_OCLK = 0x0004,
291 GLAMO_CLOCK_GEN52_EN_DIV_ZCLK = 0x0008,
292 GLAMO_CLOCK_GEN52_EN_DIV_ICLK = 0x0010,
293 /* FIXME: higher bits */
294 };
295
296 enum glamo_reg_hostbus2 {
297 GLAMO_HOSTBUS2_MMIO_EN_ISP = 0x0001,
298 GLAMO_HOSTBUS2_MMIO_EN_JPEG = 0x0002,
299 GLAMO_HOSTBUS2_MMIO_EN_MPEG = 0x0004,
300 GLAMO_HOSTBUS2_MMIO_EN_LCD = 0x0008,
301 GLAMO_HOSTBUS2_MMIO_EN_MMC = 0x0010,
302 GLAMO_HOSTBUS2_MMIO_EN_MICROP0 = 0x0020,
303 GLAMO_HOSTBUS2_MMIO_EN_MICROP1 = 0x0040,
304 GLAMO_HOSTBUS2_MMIO_EN_CMDQ = 0x0080,
305 GLAMO_HOSTBUS2_MMIO_EN_RISC = 0x0100,
306 GLAMO_HOSTBUS2_MMIO_EN_2D = 0x0200,
307 GLAMO_HOSTBUS2_MMIO_EN_3D = 0x0400,
308 };
309
310 /* LCD Controller */
311
312 #define REG_LCD(x) (GLAMO_REGOFS_LCD+(x))
313 enum glamo_reg_lcd {
314 GLAMO_REG_LCD_MODE1 = REG_LCD(0x00),
315 GLAMO_REG_LCD_MODE2 = REG_LCD(0x02),
316 GLAMO_REG_LCD_MODE3 = REG_LCD(0x04),
317 GLAMO_REG_LCD_WIDTH = REG_LCD(0x06),
318 GLAMO_REG_LCD_HEIGHT = REG_LCD(0x08),
319 GLAMO_REG_LCD_POLARITY = REG_LCD(0x0a),
320 GLAMO_REG_LCD_A_BASE1 = REG_LCD(0x0c),
321 GLAMO_REG_LCD_A_BASE2 = REG_LCD(0x0e),
322 GLAMO_REG_LCD_B_BASE1 = REG_LCD(0x10),
323 GLAMO_REG_LCD_B_BASE2 = REG_LCD(0x12),
324 GLAMO_REG_LCD_C_BASE1 = REG_LCD(0x14),
325 GLAMO_REG_LCD_C_BASE2 = REG_LCD(0x16),
326 GLAMO_REG_LCD_PITCH = REG_LCD(0x18),
327 /* RES */
328 GLAMO_REG_LCD_HORIZ_TOTAL = REG_LCD(0x1c),
329 /* RES */
330 GLAMO_REG_LCD_HORIZ_RETR_START = REG_LCD(0x20),
331 /* RES */
332 GLAMO_REG_LCD_HORIZ_RETR_END = REG_LCD(0x24),
333 /* RES */
334 GLAMO_REG_LCD_HORIZ_DISP_START = REG_LCD(0x28),
335 /* RES */
336 GLAMO_REG_LCD_HORIZ_DISP_END = REG_LCD(0x2c),
337 /* RES */
338 GLAMO_REG_LCD_VERT_TOTAL = REG_LCD(0x30),
339 /* RES */
340 GLAMO_REG_LCD_VERT_RETR_START = REG_LCD(0x34),
341 /* RES */
342 GLAMO_REG_LCD_VERT_RETR_END = REG_LCD(0x38),
343 /* RES */
344 GLAMO_REG_LCD_VERT_DISP_START = REG_LCD(0x3c),
345 /* RES */
346 GLAMO_REG_LCD_VERT_DISP_END = REG_LCD(0x40),
347 /* RES */
348 GLAMO_REG_LCD_POL = REG_LCD(0x44),
349 GLAMO_REG_LCD_DATA_START = REG_LCD(0x46),
350 GLAMO_REG_LCD_FRATE_CONTRO = REG_LCD(0x48),
351 GLAMO_REG_LCD_DATA_CMD_HDR = REG_LCD(0x4a),
352 GLAMO_REG_LCD_SP_START = REG_LCD(0x4c),
353 GLAMO_REG_LCD_SP_END = REG_LCD(0x4e),
354 GLAMO_REG_LCD_CURSOR_BASE1 = REG_LCD(0x50),
355 GLAMO_REG_LCD_CURSOR_BASE2 = REG_LCD(0x52),
356 GLAMO_REG_LCD_CURSOR_PITCH = REG_LCD(0x54),
357 GLAMO_REG_LCD_CURSOR_X_SIZE = REG_LCD(0x56),
358 GLAMO_REG_LCD_CURSOR_Y_SIZE = REG_LCD(0x58),
359 GLAMO_REG_LCD_CURSOR_X_POS = REG_LCD(0x5a),
360 GLAMO_REG_LCD_CURSOR_Y_POS = REG_LCD(0x5c),
361 GLAMO_REG_LCD_CURSOR_PRESET = REG_LCD(0x5e),
362 GLAMO_REG_LCD_CURSOR_FG_COLOR = REG_LCD(0x60),
363 /* RES */
364 GLAMO_REG_LCD_CURSOR_BG_COLOR = REG_LCD(0x64),
365 /* RES */
366 GLAMO_REG_LCD_CURSOR_DST_COLOR = REG_LCD(0x68),
367 /* RES */
368 GLAMO_REG_LCD_STATUS1 = REG_LCD(0x80),
369 GLAMO_REG_LCD_STATUS2 = REG_LCD(0x82),
370 GLAMO_REG_LCD_STATUS3 = REG_LCD(0x84),
371 GLAMO_REG_LCD_STATUS4 = REG_LCD(0x86),
372 /* RES */
373 GLAMO_REG_LCD_COMMAND1 = REG_LCD(0xa0),
374 GLAMO_REG_LCD_COMMAND2 = REG_LCD(0xa2),
375 /* RES */
376 GLAMO_REG_LCD_WFORM_DELAY1 = REG_LCD(0xb0),
377 GLAMO_REG_LCD_WFORM_DELAY2 = REG_LCD(0xb2),
378 /* RES */
379 GLAMO_REG_LCD_GAMMA_CORR = REG_LCD(0x100),
380 /* RES */
381 GLAMO_REG_LCD_GAMMA_R_ENTRY01 = REG_LCD(0x110),
382 GLAMO_REG_LCD_GAMMA_R_ENTRY23 = REG_LCD(0x112),
383 GLAMO_REG_LCD_GAMMA_R_ENTRY45 = REG_LCD(0x114),
384 GLAMO_REG_LCD_GAMMA_R_ENTRY67 = REG_LCD(0x116),
385 GLAMO_REG_LCD_GAMMA_R_ENTRY8 = REG_LCD(0x118),
386 /* RES */
387 GLAMO_REG_LCD_GAMMA_G_ENTRY01 = REG_LCD(0x130),
388 GLAMO_REG_LCD_GAMMA_G_ENTRY23 = REG_LCD(0x132),
389 GLAMO_REG_LCD_GAMMA_G_ENTRY45 = REG_LCD(0x134),
390 GLAMO_REG_LCD_GAMMA_G_ENTRY67 = REG_LCD(0x136),
391 GLAMO_REG_LCD_GAMMA_G_ENTRY8 = REG_LCD(0x138),
392 /* RES */
393 GLAMO_REG_LCD_GAMMA_B_ENTRY01 = REG_LCD(0x150),
394 GLAMO_REG_LCD_GAMMA_B_ENTRY23 = REG_LCD(0x152),
395 GLAMO_REG_LCD_GAMMA_B_ENTRY45 = REG_LCD(0x154),
396 GLAMO_REG_LCD_GAMMA_B_ENTRY67 = REG_LCD(0x156),
397 GLAMO_REG_LCD_GAMMA_B_ENTRY8 = REG_LCD(0x158),
398 /* RES */
399 GLAMO_REG_LCD_SRAM_DRIVING1 = REG_LCD(0x160),
400 GLAMO_REG_LCD_SRAM_DRIVING2 = REG_LCD(0x162),
401 GLAMO_REG_LCD_SRAM_DRIVING3 = REG_LCD(0x164),
402 };
403
404 enum glamo_reg_lcd_mode1 {
405 GLAMO_LCD_MODE1_PWRSAVE = 0x0001,
406 GLAMO_LCD_MODE1_PARTIAL_PRT = 0x0002,
407 GLAMO_LCD_MODE1_HWFLIP = 0x0004,
408 GLAMO_LCD_MODE1_LCD2 = 0x0008,
409 /* RES */
410 GLAMO_LCD_MODE1_PARTIAL_MODE = 0x0020,
411 GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
412 GLAMO_LCD_MODE1_PARTIAL_ENABLE = 0x0080,
413 GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
414 GLAMO_LCD_MODE1_HSYNC_HIGH_ACT = 0x0200,
415 GLAMO_LCD_MODE1_VSYNC_HIGH_ACT = 0x0400,
416 GLAMO_LCD_MODE1_HSYNC_FLIP = 0x0800,
417 GLAMO_LCD_MODE1_GAMMA_COR_EN = 0x1000,
418 GLAMO_LCD_MODE1_DITHER_EN = 0x2000,
419 GLAMO_LCD_MODE1_CURSOR_EN = 0x4000,
420 GLAMO_LCD_MODE1_ROTATE_EN = 0x8000,
421 };
422
423 enum glamo_reg_lcd_mode2 {
424 GLAMO_LCD_MODE2_CRC_CHECK_EN = 0x0001,
425 GLAMO_LCD_MODE2_DCMD_PER_LINE = 0x0002,
426 GLAMO_LCD_MODE2_NOUSE_BDEF = 0x0004,
427 GLAMO_LCD_MODE2_OUT_POS_MODE = 0x0008,
428 GLAMO_LCD_MODE2_FRATE_CTRL_EN = 0x0010,
429 GLAMO_LCD_MODE2_SINGLE_BUFFER = 0x0020,
430 GLAMO_LCD_MODE2_SER_LSB_TO_MSB = 0x0040,
431 /* FIXME */
432 };
433
434 enum glamo_reg_lcd_mode3 {
435 /* LCD color source data format */
436 GLAMO_LCD_SRC_RGB565 = 0x0000,
437 GLAMO_LCD_SRC_ARGB1555 = 0x4000,
438 GLAMO_LCD_SRC_ARGB4444 = 0x8000,
439 /* interface type */
440 GLAMO_LCD_MODE3_LCD = 0x1000,
441 GLAMO_LCD_MODE3_RGB = 0x0800,
442 GLAMO_LCD_MODE3_CPU = 0x0000,
443 /* mode */
444 GLAMO_LCD_MODE3_RGB332 = 0x0000,
445 GLAMO_LCD_MODE3_RGB444 = 0x0100,
446 GLAMO_LCD_MODE3_RGB565 = 0x0200,
447 GLAMO_LCD_MODE3_RGB666 = 0x0300,
448 /* depth */
449 GLAMO_LCD_MODE3_6BITS = 0x0000,
450 GLAMO_LCD_MODE3_8BITS = 0x0010,
451 GLAMO_LCD_MODE3_9BITS = 0x0020,
452 GLAMO_LCD_MODE3_16BITS = 0x0030,
453 GLAMO_LCD_MODE3_18BITS = 0x0040,
454 };
455
456 enum glamo_lcd_rot_mode {
457 GLAMO_LCD_ROT_MODE_0 = 0x0000,
458 GLAMO_LCD_ROT_MODE_180 = 0x2000,
459 GLAMO_LCD_ROT_MODE_MIRROR = 0x4000,
460 GLAMO_LCD_ROT_MODE_FLIP = 0x6000,
461 GLAMO_LCD_ROT_MODE_90 = 0x8000,
462 GLAMO_LCD_ROT_MODE_270 = 0xa000,
463 };
464 #define GLAMO_LCD_ROT_MODE_MASK 0xe000
465
466 enum glamo_lcd_cmd_type {
467 GLAMO_LCD_CMD_TYPE_DISP = 0x0000,
468 GLAMO_LCD_CMD_TYPE_PARALLEL = 0x4000,
469 GLAMO_LCD_CMD_TYPE_SERIAL = 0x8000,
470 GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
471 };
472 #define GLAMO_LCD_CMD_TYPE_MASK 0xc000
473
474 enum glamo_lcd_cmds {
475 GLAMO_LCD_CMD_DATA_DISP_FIRE = 0x00,
476 GLAMO_LCD_CMD_DATA_DISP_SYNC = 0x01, /* RGB only */
477 /* switch to command mode, no display */
478 GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
479 /* display until VSYNC, switch to command */
480 GLAMO_LCD_CMD_DATA_FIRE_VSYNC = 0x11,
481 /* display until HSYNC, switch to command */
482 GLAMO_LCD_CMD_DATA_FIRE_HSYNC = 0x12,
483 /* display until VSYNC, 1 black frame, VSYNC, switch to command */
484 GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
485 /* don't care about display and switch to command */
486 GLAMO_LCD_CMD_DATA_FIRE_FREE = 0x14, /* RGB only */
487 /* don't care about display, keep data display but disable data,
488 * and switch to command */
489 GLAMO_LCD_CMD_DATA_FIRE_FREE_D = 0x15, /* RGB only */
490 };
491
492 enum glamo_core_revisions {
493 GLAMO_CORE_REV_A0 = 0x0000,
494 GLAMO_CORE_REV_A1 = 0x0001,
495 GLAMO_CORE_REV_A2 = 0x0002,
496 GLAMO_CORE_REV_A3 = 0x0003,
497 };
498
499 #define REG_ISP(x) (GLAMO_REGOFS_ISP+(x))
500
501 enum glamo_register_isp {
502 GLAMO_REG_ISP_EN1 = REG_ISP(0x00),
503 GLAMO_REG_ISP_EN2 = REG_ISP(0x02),
504 GLAMO_REG_ISP_EN3 = REG_ISP(0x04),
505 GLAMO_REG_ISP_EN4 = REG_ISP(0x06),
506 GLAMO_REG_ISP_CAP_0_ADDRL = REG_ISP(0x08),
507 GLAMO_REG_ISP_CAP_0_ADDRH = REG_ISP(0x0a),
508 GLAMO_REG_ISP_CAP_1_ADDRL = REG_ISP(0x0c),
509 GLAMO_REG_ISP_CAP_1_ADDRH = REG_ISP(0x0e),
510 GLAMO_REG_ISP_DEC_Y_ADDRL = REG_ISP(0x10),
511 GLAMO_REG_ISP_DEC_Y_ADDRH = REG_ISP(0x12),
512 GLAMO_REG_ISP_DEC_U_ADDRL = REG_ISP(0x14),
513 GLAMO_REG_ISP_DEC_U_ADDRH = REG_ISP(0x16),
514 GLAMO_REG_ISP_DEC_V_ADDRL = REG_ISP(0x18),
515 GLAMO_REG_ISP_DEC_V_ADDRH = REG_ISP(0x1a),
516 GLAMO_REG_ISP_CAP_SEG_HEIGHT = REG_ISP(0x1c),
517 GLAMO_REG_ISP_CAP_PITCH = REG_ISP(0x1e),
518 GLAMO_REG_ISP_CAP_HEIGHT = REG_ISP(0x20),
519 GLAMO_REG_ISP_CAP_WIDTH = REG_ISP(0x22),
520 GLAMO_REG_ISP_DEC_PITCH_Y = REG_ISP(0x24),
521 GLAMO_REG_ISP_DEC_PITCH_UV = REG_ISP(0x26),
522 GLAMO_REG_ISP_DEC_HEIGHT = REG_ISP(0x28),
523 GLAMO_REG_ISP_DEC_WIDTH = REG_ISP(0x2a),
524 GLAMO_REG_ISP_ONFLY_MODE1 = REG_ISP(0x2c),
525 GLAMO_REG_ISP_ONFLY_MODE2 = REG_ISP(0x2e),
526 GLAMO_REG_ISP_ONFLY_MODE3 = REG_ISP(0x30),
527 GLAMO_REG_ISP_ONFLY_MODE4 = REG_ISP(0x32),
528 GLAMO_REG_ISP_ONFLY_MODE5 = REG_ISP(0x34),
529 //
530 GLAMO_REG_ISP_YUV2RGB_11 = REG_ISP(0x50),
531 GLAMO_REG_ISP_YUV2RGB_21 = REG_ISP(0x52),
532 GLAMO_REG_ISP_YUV2RGB_32 = REG_ISP(0x54),
533 GLAMO_REG_ISP_YUV2RGB_33 = REG_ISP(0x56),
534 GLAMO_REG_ISP_YUV2RGB_RG = REG_ISP(0x58),
535 GLAMO_REG_ISP_YUV2RGB_B = REG_ISP(0x5a),
536 //
537 GLAMO_REG_ISP_PORT1_SCALEH = REG_ISP(0x76),
538 GLAMO_REG_ISP_PORT1_SCALEV = REG_ISP(0x78),
539 GLAMO_REG_ISP_PORT2_SCALEH = REG_ISP(0x7a),
540 GLAMO_REG_ISP_PORT2_SCALEV = REG_ISP(0x7c),
541 GLAMO_REG_ISP_DEC_SCALEH = REG_ISP(0x7e),
542 GLAMO_REG_ISP_DEC_SCALEV = REG_ISP(0x80),
543 GLAMO_REG_ISP_TURBO = REG_ISP(0x82),
544 GLAMO_REG_ISP_PORT1_CAP_EN = REG_ISP(0x84),
545 GLAMO_REG_ISP_PORT1_CAP_0_ADDRL = REG_ISP(0x86),
546 GLAMO_REG_ISP_PORT1_CAP_0_ADDRH = REG_ISP(0x88),
547 GLAMO_REG_ISP_PORT1_CAP_1_ADDRL = REG_ISP(0x8a),
548 GLAMO_REG_ISP_PORT1_CAP_1_ADDRH = REG_ISP(0x8c),
549 GLAMO_REG_ISP_PORT1_CAP_WIDTH = REG_ISP(0x8e),
550 GLAMO_REG_ISP_PORT1_CAP_HEIGHT = REG_ISP(0x90),
551 GLAMO_REG_ISP_PORT1_CAP_PITCH = REG_ISP(0x92),
552 GLAMO_REG_ISP_PORT1_CAP_CLIP_L = REG_ISP(0x94),
553 GLAMO_REG_ISP_PORT1_CAP_CLIP_R = REG_ISP(0x96),
554 GLAMO_REG_ISP_PORT1_CAP_CLIP_T = REG_ISP(0x98),
555 GLAMO_REG_ISP_PORT1_CAP_CLIP_B = REG_ISP(0x9a),
556 GLAMO_REG_ISP_PORT1_DEC_EN = REG_ISP(0x9c),
557 GLAMO_REG_ISP_PORT1_DEC_0_ADDRL = REG_ISP(0x9e),
558 GLAMO_REG_ISP_PORT1_DEC_0_ADDRH = REG_ISP(0xa0),
559 GLAMO_REG_ISP_PORT1_DEC_1_ADDRL = REG_ISP(0xa2),
560 GLAMO_REG_ISP_PORT1_DEC_1_ADDRH = REG_ISP(0xa4),
561 GLAMO_REG_ISP_PORT1_DEC_WIDTH = REG_ISP(0xa6),
562 GLAMO_REG_ISP_PORT1_DEC_HEIGHT = REG_ISP(0xa8),
563 GLAMO_REG_ISP_PORT1_DEC_PITCH = REG_ISP(0xaa),
564 GLAMO_REG_ISP_PORT1_DEC_CLIP_L = REG_ISP(0xac),
565 GLAMO_REG_ISP_PORT1_DEC_CLIP_R = REG_ISP(0xae),
566 GLAMO_REG_ISP_PORT1_DEC_CLIP_T = REG_ISP(0xb0),
567 GLAMO_REG_ISP_PORT1_DEC_CLIP_B = REG_ISP(0xb2),
568 GLAMO_REG_ISP_PORT2_EN = REG_ISP(0xb4),
569 GLAMO_REG_ISP_PORT2_0_Y_ADDRL = REG_ISP(0xb6),
570 GLAMO_REG_ISP_PORT2_0_Y_ADDRH = REG_ISP(0xb8),
571 GLAMO_REG_ISP_PORT2_0_U_ADDRL = REG_ISP(0xba),
572 GLAMO_REG_ISP_PORT2_0_U_ADDRH = REG_ISP(0xbc),
573 GLAMO_REG_ISP_PORT2_0_V_ADDRL = REG_ISP(0xbe),
574 GLAMO_REG_ISP_PORT2_0_V_ADDRH = REG_ISP(0xc0),
575 GLAMO_REG_ISP_PORT2_1_Y_ADDRL = REG_ISP(0xc2),
576 GLAMO_REG_ISP_PORT2_1_Y_ADDRH = REG_ISP(0xc4),
577 GLAMO_REG_ISP_PORT2_1_U_ADDRL = REG_ISP(0xc6),
578 GLAMO_REG_ISP_PORT2_1_U_ADDRH = REG_ISP(0xc8),
579 GLAMO_REG_ISP_PORT2_1_V_ADDRL = REG_ISP(0xca),
580 GLAMO_REG_ISP_PORT2_1_V_ADDRH = REG_ISP(0xcc),
581 GLAMO_REG_ISP_PORT2_2_Y_ADDRL = REG_ISP(0xce),
582 GLAMO_REG_ISP_PORT2_2_Y_ADDRH = REG_ISP(0xd0),
583 GLAMO_REG_ISP_PORT2_2_U_ADDRL = REG_ISP(0xd2),
584 GLAMO_REG_ISP_PORT2_2_U_ADDRH = REG_ISP(0xd4),
585 GLAMO_REG_ISP_PORT2_2_V_ADDRL = REG_ISP(0xd6),
586 GLAMO_REG_ISP_PORT2_2_V_ADDRH = REG_ISP(0xd8),
587 GLAMO_REG_ISP_PORT2_WIDTH = REG_ISP(0xda),
588 GLAMO_REG_ISP_PORT2_HEIGHT = REG_ISP(0xdc),
589 GLAMO_REG_ISP_PORT2_Y_PITCH = REG_ISP(0xde),
590 GLAMO_REG_ISP_PORT2_UV_PITCH = REG_ISP(0xe0),
591 //
592 GLAMO_REG_ISP_RGB2YUV_11_12 = REG_ISP(0xf6),
593 GLAMO_REG_ISP_RGB2YUV_13_21 = REG_ISP(0xf8),
594 GLAMO_REG_ISP_RGB2YUV_22_23 = REG_ISP(0xfa),
595 GLAMO_REG_ISP_RGB2YUV_31_32 = REG_ISP(0xfc),
596 GLAMO_REG_ISP_RGB2YUV_33 = REG_ISP(0xfe),
597 //
598 GLAMO_REG_ISP_PORT1_SCALEH_MATRIX = REG_ISP(0x10c),
599 GLAMO_REG_ISP_PORT1_SCALEV_MATRIX = REG_ISP(0x120),
600 GLAMO_REG_ISP_PORT2_SCALEH_MATRIX = REG_ISP(0x134),
601 GLAMO_REG_ISP_PORT2_SCALEV_MATRIX = REG_ISP(0x148),
602 GLAMO_REG_ISP_DEC_SCALEH_MATRIX = REG_ISP(0x15c),
603 GLAMO_REG_ISP_DEC_SCALEV_MATRIX = REG_ISP(0x170),
604 GLAMO_REG_ISP_STATUS = REG_ISP(0x184),
605 };
606
607 enum glamo_reg_isp_en1 {
608 GLAMO_ISP_EN1_FIRE_ISP = 0x0001,
609 GLAMO_ISP_EN1_FIRE_CAP = 0x0002,
610 GLAMO_ISP_EN1_VIDEO_CONF = 0x0004,
611 GLAMO_ISP_EN1_BAYER_SRC = 0x0008,
612 //
613 GLAMO_ISP_EN1_YUV_PACK = 0x0040,
614 GLAMO_ISP_EN1_PLANE_MODE = 0x0080,
615 GLAMO_ISP_EN1_YUV_INPUT = 0x0100,
616 GLAMO_ISP_EN1_YUV420 = 0x0200,
617 //
618 };
619
620 enum glamo_reg_isp_en3 {
621 //
622 GLAMO_ISP_EN3_SCALE_IMPROVE = 0x0040,
623 GLAMO_ISP_EN3_PLANE_MODE = 0x0080,
624 GLAMO_ISP_EN3_YUV_INPUT = 0x0100,
625 GLAMO_ISP_EN3_YUV420 = 0x0200,
626 //
627 };
628
629 enum glamo_isp_rot_mode {
630 GLAMO_ISP_ROT_MODE_0 = 0x0000,
631 GLAMO_ISP_ROT_MODE_90 = 0x0400,
632 GLAMO_ISP_ROT_MODE_270 = 0x0800,
633 GLAMO_ISP_ROT_MODE_180 = 0x0c00,
634 GLAMO_ISP_ROT_MODE_MIRROR = 0x1000,
635 GLAMO_ISP_ROT_MODE_FLIP = 0x1400,
636 };
637 #define GLAMO_ISP_ROT_MODE_MASK 0x1c00
638
639 enum glamo_reg_isp_port1_en {
640 GLAMO_ISP_PORT1_EN_OUTPUT = 0x0001,
641 // GLAMO_ISP_PORT1_EN_SCALE = 0x0002,
642 GLAMO_ISP_PORT1_EN_CLIP = 0x0004,
643 GLAMO_ISP_PORT1_EN_CLIP_OUT = 0x0008,
644 GLAMO_ISP_PORT1_EN_DUAL_BUF = 0x0010,
645 };
646
647 enum glamo_reg_isp_port2_en {
648 GLAMO_ISP_PORT2_EN_OUTPUT = 0x0001,
649 GLAMO_ISP_PORT2_EN_SCALE = 0x0002,
650 GLAMO_ISP_PORT2_EN_JPEG = 0x0010,
651 GLAMO_ISP_PORT2_EN_MPEG = 0x0020,
652 GLAMO_ISP_PORT2_EN_ENCODE = 0x0040,
653 GLAMO_ISP_PORT2_EN_DECODE = 0x0080,
654 };
655
656 #define REG_MPEG(x) (GLAMO_REGOFS_MPEG+(x))
657
658 enum glamo_register_mpeg {
659 //
660 GLAMO_REG_MPEG_DC_ADDRL = REG_MPEG(0x3c),
661 GLAMO_REG_MPEG_DC_ADDRH = REG_MPEG(0x3e),
662 GLAMO_REG_MPEG_AC_ADDRL = REG_MPEG(0x40),
663 GLAMO_REG_MPEG_AC_ADDRH = REG_MPEG(0x42),
664 //
665 GLAMO_REG_MPEG_SAFE_1 = REG_MPEG(0x60),
666 GLAMO_REG_MPEG_SAFE_2 = REG_MPEG(0x62),
667 GLAMO_REG_MPEG_SAFE_3 = REG_MPEG(0x64),
668 //
669 GLAMO_REG_MPEG_DEC_OUT0_Y_ADDRL = REG_MPEG(0x6e),
670 GLAMO_REG_MPEG_DEC_OUT0_Y_ADDRH = REG_MPEG(0x70),
671 GLAMO_REG_MPEG_DEC_OUT0_U_ADDRL = REG_MPEG(0x72),
672 GLAMO_REG_MPEG_DEC_OUT0_U_ADDRH = REG_MPEG(0x74),
673 GLAMO_REG_MPEG_DEC_OUT0_V_ADDRL = REG_MPEG(0x76),
674 GLAMO_REG_MPEG_DEC_OUT0_V_ADDRH = REG_MPEG(0x78),
675 GLAMO_REG_MPEG_DEC_OUT1_Y_ADDRL = REG_MPEG(0x7a),
676 GLAMO_REG_MPEG_DEC_OUT1_Y_ADDRH = REG_MPEG(0x7c),
677 GLAMO_REG_MPEG_DEC_OUT1_U_ADDRL = REG_MPEG(0x7e),
678 GLAMO_REG_MPEG_DEC_OUT1_U_ADDRH = REG_MPEG(0x80),
679 GLAMO_REG_MPEG_DEC_OUT1_V_ADDRL = REG_MPEG(0x82),
680 GLAMO_REG_MPEG_DEC_OUT1_V_ADDRH = REG_MPEG(0x84),
681 GLAMO_REG_MPEG_DEC_OUT2_Y_ADDRL = REG_MPEG(0x86),
682 GLAMO_REG_MPEG_DEC_OUT2_Y_ADDRH = REG_MPEG(0x88),
683 GLAMO_REG_MPEG_DEC_OUT2_U_ADDRL = REG_MPEG(0x8a),
684 GLAMO_REG_MPEG_DEC_OUT2_U_ADDRH = REG_MPEG(0x8c),
685 GLAMO_REG_MPEG_DEC_OUT2_V_ADDRL = REG_MPEG(0x8e),
686 GLAMO_REG_MPEG_DEC_OUT2_V_ADDRH = REG_MPEG(0x90),
687 GLAMO_REG_MPEG_DEC_WIDTH = REG_MPEG(0x92),
688 GLAMO_REG_MPEG_DEC_HEIGHT = REG_MPEG(0x94),
689 GLAMO_REG_MPEG_SPECIAL = REG_MPEG(0x96),
690 GLAMO_REG_MPEG_DEC_IN_ADDRL = REG_MPEG(0x98),
691 GLAMO_REG_MPEG_DEC_IN_ADDRH = REG_MPEG(0x9a),
692 //
693 GLAMO_REG_MPEG_DEBLK_THRESHOLD = REG_MPEG(0xc0),
694 //
695 GLAMO_REG_MPEG_DEC_STATUS = REG_MPEG(0xc8),
696 GLAMO_REG_MPEG_DEC_RB0 = REG_MPEG(0xca),
697 GLAMO_REG_MPEG_DEC_RB1 = REG_MPEG(0xcc),
698 };
699
700 #define REG_CMDQ(x) (GLAMO_REGOFS_CMDQUEUE+(x))
701
702 enum glamo_register_cq {
703 GLAMO_REG_CMDQ_BASE_ADDRL = REG_CMDQ(0x00),
704 GLAMO_REG_CMDQ_BASE_ADDRH = REG_CMDQ(0x02),
705 GLAMO_REG_CMDQ_LEN = REG_CMDQ(0x04),
706 GLAMO_REG_CMDQ_WRITE_ADDRL = REG_CMDQ(0x06),
707 GLAMO_REG_CMDQ_WRITE_ADDRH = REG_CMDQ(0x08),
708 GLAMO_REG_CMDQ_FLIP = REG_CMDQ(0x0a),
709 GLAMO_REG_CMDQ_CONTROL = REG_CMDQ(0x0c),
710 GLAMO_REG_CMDQ_READ_ADDRL = REG_CMDQ(0x0e),
711 GLAMO_REG_CMDQ_READ_ADDRH = REG_CMDQ(0x10),
712 GLAMO_REG_CMDQ_STATUS = REG_CMDQ(0x12),
713 };
714
715 #define REG_2D(x) (GLAMO_REGOFS_2D+(x))
716
717 enum glamo_register_2d {
718 GLAMO_REG_2D_SRC_ADDRL = REG_2D(0x00),
719 GLAMO_REG_2D_SRC_ADDRH = REG_2D(0x02),
720 GLAMO_REG_2D_SRC_PITCH = REG_2D(0x04),
721 GLAMO_REG_2D_SRC_X = REG_2D(0x06),
722 GLAMO_REG_2D_SRC_Y = REG_2D(0x08),
723 GLAMO_REG_2D_DST_X = REG_2D(0x0a),
724 GLAMO_REG_2D_DST_Y = REG_2D(0x0c),
725 GLAMO_REG_2D_DST_ADDRL = REG_2D(0x0e),
726 GLAMO_REG_2D_DST_ADDRH = REG_2D(0x10),
727 GLAMO_REG_2D_DST_PITCH = REG_2D(0x12),
728 GLAMO_REG_2D_DST_HEIGHT = REG_2D(0x14),
729 GLAMO_REG_2D_RECT_WIDTH = REG_2D(0x16),
730 GLAMO_REG_2D_RECT_HEIGHT = REG_2D(0x18),
731 GLAMO_REG_2D_PAT_ADDRL = REG_2D(0x1a),
732 GLAMO_REG_2D_PAT_ADDRH = REG_2D(0x1c),
733 GLAMO_REG_2D_PAT_FG = REG_2D(0x1e),
734 GLAMO_REG_2D_PAT_BG = REG_2D(0x20),
735 GLAMO_REG_2D_SRC_FG = REG_2D(0x22),
736 GLAMO_REG_2D_SRC_BG = REG_2D(0x24),
737 GLAMO_REG_2D_MASK1 = REG_2D(0x26),
738 GLAMO_REG_2D_MASK2 = REG_2D(0x28),
739 GLAMO_REG_2D_MASK3 = REG_2D(0x2a),
740 GLAMO_REG_2D_MASK4 = REG_2D(0x2c),
741 GLAMO_REG_2D_ROT_X = REG_2D(0x2e),
742 GLAMO_REG_2D_ROT_Y = REG_2D(0x30),
743 GLAMO_REG_2D_LEFT_CLIP = REG_2D(0x32),
744 GLAMO_REG_2D_TOP_CLIP = REG_2D(0x34),
745 GLAMO_REG_2D_RIGHT_CLIP = REG_2D(0x36),
746 GLAMO_REG_2D_BOTTOM_CLIP = REG_2D(0x38),
747 GLAMO_REG_2D_COMMAND1 = REG_2D(0x3A),
748 GLAMO_REG_2D_COMMAND2 = REG_2D(0x3C),
749 GLAMO_REG_2D_COMMAND3 = REG_2D(0x3E),
750 GLAMO_REG_2D_SAFE = REG_2D(0x40),
751 GLAMO_REG_2D_STATUS = REG_2D(0x42),
752 GLAMO_REG_2D_ID1 = REG_2D(0x44),
753 GLAMO_REG_2D_ID2 = REG_2D(0x46),
754 GLAMO_REG_2D_ID3 = REG_2D(0x48),
755 };
756
757 #endif /* _GLAMO_REGS_H */
mplayer with SMedia Glamo drivers