cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #ifdef WIN32
  33 #include <windows.h>
  34 #endif
  35
  36 #ifdef __AMIGAOS4__
  37 #include <proto/exec.h>
  38 #endif
  39
  40 /* Thanks to the FreeBSD project for some of this cpuid code, and
  41  * help understanding how to use it.  Thanks to the Mesa
  42  * team for SSE support detection and more cpu detect code.
  43  */
  44
  45 /* I believe this code works.  However, it has only been used on a PII and PIII */
  46
  47 static void check_os_katmai_support( void );
  48
  49 #if 1
  50 // return TRUE if cpuid supported
  51 static int has_cpuid(void)
  52 {
  53         long a, c;
  54
  55 // code from libavcodec:
  56     __asm__ __volatile__ (
  57                           /* See if CPUID instruction is supported ... */
  58                           /* ... Get copies of EFLAGS into eax and ecx */
  59                           "pushf\n\t"
  60                           "pop %0\n\t"
  61                           "mov %0, %1\n\t"
  62
  63                           /* ... Toggle the ID bit in one copy and store */
  64                           /*     to the EFLAGS reg */
  65                           "xor $0x200000, %0\n\t"
  66                           "push %0\n\t"
  67                           "popf\n\t"
  68
  69                           /* ... Get the (hopefully modified) EFLAGS */
  70                           "pushf\n\t"
  71                           "pop %0\n\t"
  72                           : "=a" (a), "=c" (c)
  73                           :
  74                           : "cc"
  75                           );
  76
  77         return (a!=c);
  78 }
  79 #endif
  80
  81 static void
  82 do_cpuid(unsigned int ax, unsigned int *p)
  83 {
  84 #if 0
  85         __asm __volatile(
  86         "cpuid;"
  87         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  88         :  "0" (ax)
  89         );
  90 #else
  91 // code from libavcodec:
  92     __asm __volatile
  93         ("mov %%"REG_b", %%"REG_S"\n\t"
  94          "cpuid\n\t"
  95          "xchg %%"REG_b", %%"REG_S
  96          : "=a" (p[0]), "=S" (p[1]),
  97            "=c" (p[2]), "=d" (p[3])
  98          : "0" (ax));
  99 #endif
 100
 101 }
 102
 103 void GetCpuCaps( CpuCaps *caps)
 104 {
 105         unsigned int regs[4];
 106         unsigned int regs2[4];
 107
 108         memset(caps, 0, sizeof(*caps));
 109         caps->isX86=1;
 110         caps->cl_size=32; /* default */
 111         if (!has_cpuid()) {
 112             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 113             return;
 114         }
 115         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 116         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 117                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 118         if (regs[0]>=0x00000001)
 119         {
 120                 char *tmpstr, *ptmpstr;
 121                 unsigned cl_size;
 122
 123                 do_cpuid(0x00000001, regs2);
 124
 125                 caps->cpuType=(regs2[0] >> 8)&0xf;
 126                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 127
 128 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 129 // System Instructions, Table 3-2: Effective family computation, page 120.
 130                 if(caps->cpuType==0xf){
 131                     // use extended family (P4, IA64, K8)
 132                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 133                 }
 134                 if(caps->cpuType==0xf || caps->cpuType==6)
 135                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 136
 137                 caps->cpuStepping=regs2[0] & 0xf;
 138
 139                 // general feature flags:
 140                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 141                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 142                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 143                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 144                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 145                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 146                 if(cl_size) caps->cl_size = cl_size;
 147
 148                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 149                 while(*ptmpstr == ' ')        // strip leading spaces
 150                     ptmpstr++;
 151                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr);
 152                 free(tmpstr);
 153                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n",
 154                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 155
 156         }
 157         do_cpuid(0x80000000, regs);
 158         if (regs[0]>=0x80000001) {
 159                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 160                 do_cpuid(0x80000001, regs2);
 161                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 162                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 163                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 164                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 165         }
 166         if(regs[0]>=0x80000006)
 167         {
 168                 do_cpuid(0x80000006, regs2);
 169                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 170                 caps->cl_size  = regs2[2] & 0xFF;
 171         }
 172         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 173 #if 0
 174         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 175                 gCpuCaps.hasMMX,
 176                 gCpuCaps.hasMMX2,
 177                 gCpuCaps.hasSSE,
 178                 gCpuCaps.hasSSE2,
 179                 gCpuCaps.has3DNow,
 180                 gCpuCaps.has3DNowExt );
 181 #endif
 182
 183                 /* FIXME: Does SSE2 need more OS support, too? */
 184 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__) || defined(__MINGW32__)
 185                 if (caps->hasSSE)
 186                         check_os_katmai_support();
 187                 if (!caps->hasSSE)
 188                         caps->hasSSE2 = 0;
 189 #else
 190                 caps->hasSSE=0;
 191                 caps->hasSSE2 = 0;
 192 #endif
 193 //              caps->has3DNow=1;
 194 //              caps->hasMMX2 = 0;
 195 //              caps->hasMMX = 0;
 196
 197 #ifndef HAVE_MMX
 198         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 199         caps->hasMMX=0;
 200 #endif
 201 #ifndef HAVE_MMX2
 202         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 203         caps->hasMMX2=0;
 204 #endif
 205 #ifndef HAVE_SSE
 206         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 207         caps->hasSSE=0;
 208 #endif
 209 #ifndef HAVE_SSE2
 210         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 211         caps->hasSSE2=0;
 212 #endif
 213 #ifndef HAVE_3DNOW
 214         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 215         caps->has3DNow=0;
 216 #endif
 217 #ifndef HAVE_3DNOWEX
 218         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 219         caps->has3DNowExt=0;
 220 #endif
 221 }
 222
 223
 224 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 225 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 226 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 227 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 228 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 229 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 230
 231 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 232 #include "cputable.h" /* get cpuname and cpuvendors */
 233         char vendor[13];
 234         char *retname;
 235         int i;
 236
 237         if (NULL==(retname=malloc(256))) {
 238                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 239                 exit(1);
 240         }
 241
 242         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 243
 244         do_cpuid(0x80000000,regs);
 245         if (regs[0] >= 0x80000004)
 246         {
 247                 // CPU has built-in namestring
 248                 retname[0] = '\0';
 249                 for (i = 0x80000002; i <= 0x80000004; i++)
 250                 {
 251                         do_cpuid(i, regs);
 252                         strncat(retname, (char*)regs, 16);
 253                 }
 254                 return retname;
 255         }
 256
 257         for(i=0; i<MAX_VENDORS; i++){
 258                 if(!strcmp(cpuvendors[i].string,vendor)){
 259                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 260                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 261                         } else {
 262                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 263                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 264                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 265                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 266                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 267                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 268                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 269                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 270                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 271                         }
 272                 }
 273         }
 274         retname[255] = 0;
 275
 276         //printf("Detected CPU: %s\n", retname);
 277         return retname;
 278 }
 279
 280 #undef CPUID_EXTFAMILY
 281 #undef CPUID_EXTMODEL
 282 #undef CPUID_TYPE
 283 #undef CPUID_FAMILY
 284 #undef CPUID_MODEL
 285 #undef CPUID_STEPPING
 286
 287
 288 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64)
 289 static void sigill_handler_sse( int signal, struct sigcontext sc )
 290 {
 291    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 292
 293    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 294     * instructions are 3 bytes long.  We must increment the instruction
 295     * pointer manually to avoid repeated execution of the offending
 296     * instruction.
 297     *
 298     * If the SIGILL is caused by a divide-by-zero when unmasked
 299     * exceptions aren't supported, the SIMD FPU status and control
 300     * word will be restored at the end of the test, so we don't need
 301     * to worry about doing it here.  Besides, we may not be able to...
 302     */
 303    sc.eip += 3;
 304
 305    gCpuCaps.hasSSE=0;
 306 }
 307 #endif /* __linux__ && _POSIX_SOURCE */
 308
 309 #ifdef WIN32
 310 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 311 {
 312    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 313       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 314       ep->ContextRecord->Eip +=3;
 315       gCpuCaps.hasSSE=0;
 316           return EXCEPTION_CONTINUE_EXECUTION;
 317    }
 318    return EXCEPTION_CONTINUE_SEARCH;
 319 }
 320 #endif /* WIN32 */
 321
 322 /* If we're running on a processor that can do SSE, let's see if we
 323  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 324  * haven't been configured for a Pentium III but are running on one,
 325  * and RedHat patched 2.2 kernels that have broken exception handling
 326  * support for user space apps that do SSE.
 327  */
 328
 329 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 330 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 331 #elif defined(__APPLE__)
 332 #define SSE_SYSCTL_NAME "hw.optional.sse"
 333 #endif
 334
 335 static void check_os_katmai_support( void )
 336 {
 337 #ifdef ARCH_X86_64
 338    gCpuCaps.hasSSE=1;
 339    gCpuCaps.hasSSE2=1;
 340 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 341    int has_sse=0, ret;
 342    size_t len=sizeof(has_sse);
 343
 344    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 345    if (ret || !has_sse)
 346       gCpuCaps.hasSSE=0;
 347
 348 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 349 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 350    int has_sse, has_sse2, ret, mib[2];
 351    size_t varlen;
 352
 353    mib[0] = CTL_MACHDEP;
 354    mib[1] = CPU_SSE;
 355    varlen = sizeof(has_sse);
 356
 357    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 358    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 359    if (ret < 0 || !has_sse) {
 360       gCpuCaps.hasSSE=0;
 361       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 362    } else {
 363       gCpuCaps.hasSSE=1;
 364       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 365    }
 366
 367    mib[1] = CPU_SSE2;
 368    varlen = sizeof(has_sse2);
 369    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 370    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 371    if (ret < 0 || !has_sse2) {
 372       gCpuCaps.hasSSE2=0;
 373       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 374    } else {
 375       gCpuCaps.hasSSE2=1;
 376       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 377    }
 378 #else
 379    gCpuCaps.hasSSE = 0;
 380    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 381 #endif
 382 #elif defined(WIN32)
 383    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 384    if ( gCpuCaps.hasSSE ) {
 385       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 386       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 387       __asm __volatile ("xorps %xmm0, %xmm0");
 388       SetUnhandledExceptionFilter(exc_fil);
 389       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 390       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 391    }
 392 #elif defined(__linux__)
 393 #if defined(_POSIX_SOURCE)
 394    struct sigaction saved_sigill;
 395
 396    /* Save the original signal handlers.
 397     */
 398    sigaction( SIGILL, NULL, &saved_sigill );
 399
 400    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 401
 402    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 403     * supports the extended FPU save and restore required for SSE.  If
 404     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 405     * doesn't support Streaming SIMD Exceptions, even if the processor
 406     * does.
 407     */
 408    if ( gCpuCaps.hasSSE ) {
 409       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 410
 411 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 412       __asm __volatile ("xorps %xmm0, %xmm0");
 413
 414       if ( gCpuCaps.hasSSE ) {
 415          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 416       } else {
 417          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 418       }
 419    }
 420
 421    /* Restore the original signal handlers.
 422     */
 423    sigaction( SIGILL, &saved_sigill, NULL );
 424
 425    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 426     * safe to go ahead and hook out the SSE code throughout Mesa.
 427     */
 428    if ( gCpuCaps.hasSSE ) {
 429       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 430    } else {
 431       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 432    }
 433 #else
 434    /* We can't use POSIX signal handling to test the availability of
 435     * SSE, so we disable it by default.
 436     */
 437    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 438    gCpuCaps.hasSSE=0;
 439 #endif /* _POSIX_SOURCE */
 440 #else
 441    /* Do nothing on other platforms for now.
 442     */
 443    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 444    gCpuCaps.hasSSE=0;
 445 #endif /* __linux__ */
 446 }
 447 #else /* ARCH_X86 */
 448
 449 #ifdef __APPLE__
 450 #include <sys/sysctl.h>
 451 #elif __AMIGAOS4__
 452 /* nothing */
 453 #else
 454 #include <signal.h>
 455 #include <setjmp.h>
 456
 457 static sigjmp_buf jmpbuf;
 458 static volatile sig_atomic_t canjump = 0;
 459
 460 static void sigill_handler (int sig)
 461 {
 462     if (!canjump) {
 463         signal (sig, SIG_DFL);
 464         raise (sig);
 465     }
 466
 467     canjump = 0;
 468     siglongjmp (jmpbuf, 1);
 469 }
 470 #endif /* __APPLE__ */
 471
 472 void GetCpuCaps( CpuCaps *caps)
 473 {
 474         caps->cpuType=0;
 475         caps->cpuModel=0;
 476         caps->cpuStepping=0;
 477         caps->hasMMX=0;
 478         caps->hasMMX2=0;
 479         caps->has3DNow=0;
 480         caps->has3DNowExt=0;
 481         caps->hasSSE=0;
 482         caps->hasSSE2=0;
 483         caps->isX86=0;
 484         caps->hasAltiVec = 0;
 485 #ifdef HAVE_ALTIVEC
 486 #ifdef __APPLE__
 487 /*
 488   rip-off from ffmpeg altivec detection code.
 489   this code also appears on Apple's AltiVec pages.
 490  */
 491         {
 492                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 493                 int has_vu = 0;
 494                 size_t len = sizeof(has_vu);
 495                 int err;
 496
 497                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 498
 499                 if (err == 0)
 500                         if (has_vu != 0)
 501                                 caps->hasAltiVec = 1;
 502         }
 503 #elif __AMIGAOS4__
 504         ULONG result = 0;
 505
 506         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 507         if (result == VECTORTYPE_ALTIVEC)
 508                 caps->hasAltiVec = 1;
 509 #else
 510 /* no Darwin, do it the brute-force way */
 511 /* this is borrowed from the libmpeg2 library */
 512         {
 513           signal (SIGILL, sigill_handler);
 514           if (sigsetjmp (jmpbuf, 1)) {
 515             signal (SIGILL, SIG_DFL);
 516           } else {
 517             canjump = 1;
 518
 519             asm volatile ("mtspr 256, %0\n\t"
 520                           "vand %%v0, %%v0, %%v0"
 521                           :
 522                           : "r" (-1));
 523
 524             signal (SIGILL, SIG_DFL);
 525             caps->hasAltiVec = 1;
 526           }
 527         }
 528 #endif /* __APPLE__ */
 529         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 530 #endif /* HAVE_ALTIVEC */
 531
 532 #ifdef ARCH_IA64
 533         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 534 #endif
 535
 536 #ifdef ARCH_SPARC
 537         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 538 #endif
 539
 540 #ifdef ARCH_ARMV4L
 541         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 542 #endif
 543
 544 #ifdef ARCH_POWERPC
 545         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 546 #endif
 547
 548 #ifdef ARCH_ALPHA
 549         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 550 #endif
 551
 552 #ifdef ARCH_SGI_MIPS
 553         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 554 #endif
 555
 556 #ifdef ARCH_PA_RISC
 557         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 558 #endif
 559
 560 #ifdef ARCH_S390
 561         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 562 #endif
 563
 564 #ifdef ARCH_S390X
 565         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 566 #endif
 567
 568 #ifdef ARCH_VAX
 569         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 570 #endif
 571
 572 #ifdef ARCH_XTENSA
 573         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" );
 574 #endif
 575 }
 576 #endif /* !ARCH_X86 */