cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #if HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  22 #include <sys/types.h>
  23 #include <sys/sysctl.h>
  24 #elif defined(__linux__)
  25 #include <signal.h>
  26 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  27 #include <windows.h>
  28 #elif defined(__OS2__)
  29 #define INCL_DOS
  30 #include <os2.h>
  31 #elif defined(__AMIGAOS4__)
  32 #include <proto/exec.h>
  33 #endif
  34
  35 /* Thanks to the FreeBSD project for some of this cpuid code, and
  36  * help understanding how to use it.  Thanks to the Mesa
  37  * team for SSE support detection and more cpu detect code.
  38  */
  39
  40 /* I believe this code works.  However, it has only been used on a PII and PIII */
  41
  42 static void check_os_katmai_support( void );
  43
  44 // return TRUE if cpuid supported
  45 static int has_cpuid(void)
  46 {
  47         long a, c;
  48
  49 // code from libavcodec:
  50 #if ARCH_X86_64
  51 #define PUSHF "pushfq\n\t"
  52 #define POPF "popfq\n\t"
  53 #else
  54 #define PUSHF "pushfl\n\t"
  55 #define POPF "popfl\n\t"
  56 #endif
  57     __asm__ volatile (
  58                           /* See if CPUID instruction is supported ... */
  59                           /* ... Get copies of EFLAGS into eax and ecx */
  60                           PUSHF
  61                           "pop %0\n\t"
  62                           "mov %0, %1\n\t"
  63
  64                           /* ... Toggle the ID bit in one copy and store */
  65                           /*     to the EFLAGS reg */
  66                           "xor $0x200000, %0\n\t"
  67                           "push %0\n\t"
  68                           POPF
  69
  70                           /* ... Get the (hopefully modified) EFLAGS */
  71                           PUSHF
  72                           "pop %0\n\t"
  73                           : "=a" (a), "=c" (c)
  74                           :
  75                           : "cc"
  76                           );
  77 #undef PUSHF
  78 #undef POPF
  79
  80         return a != c;
  81 }
  82
  83 static void
  84 do_cpuid(unsigned int ax, unsigned int *p)
  85 {
  86 #if 0
  87         __asm__ volatile(
  88         "cpuid;"
  89         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  90         :  "0" (ax)
  91         );
  92 #else
  93 // code from libavcodec:
  94     __asm__ volatile
  95         ("mov %%"REG_b", %%"REG_S"\n\t"
  96          "cpuid\n\t"
  97          "xchg %%"REG_b", %%"REG_S
  98          : "=a" (p[0]), "=S" (p[1]),
  99            "=c" (p[2]), "=d" (p[3])
 100          : "0" (ax));
 101 #endif
 102
 103 }
 104
 105 void GetCpuCaps( CpuCaps *caps)
 106 {
 107         unsigned int regs[4];
 108         unsigned int regs2[4];
 109
 110         memset(caps, 0, sizeof(*caps));
 111         caps->isX86=1;
 112         caps->cl_size=32; /* default */
 113         if (!has_cpuid()) {
 114             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 115             return;
 116         }
 117         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 118         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 119                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 120         if (regs[0]>=0x00000001)
 121         {
 122                 char *tmpstr, *ptmpstr;
 123                 unsigned cl_size;
 124
 125                 do_cpuid(0x00000001, regs2);
 126
 127                 caps->cpuType=(regs2[0] >> 8)&0xf;
 128                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 129
 130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 131 // System Instructions, Table 3-2: Effective family computation, page 120.
 132                 if(caps->cpuType==0xf){
 133                     // use extended family (P4, IA64, K8)
 134                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 135                 }
 136                 if(caps->cpuType==0xf || caps->cpuType==6)
 137                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 138
 139                 caps->cpuStepping=regs2[0] & 0xf;
 140
 141                 // general feature flags:
 142                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 143                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 144                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 145                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 146                 caps->hasSSE3 = (regs2[2] & 1);                // 0x0000001
 147                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 148                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 149                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 150                 if(cl_size) caps->cl_size = cl_size;
 151
 152                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 153                 while(*ptmpstr == ' ')        // strip leading spaces
 154                     ptmpstr++;
 155                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 156                 free(tmpstr);
 157                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 158                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 159
 160         }
 161         do_cpuid(0x80000000, regs);
 162         if (regs[0]>=0x80000001) {
 163                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 164                 do_cpuid(0x80000001, regs2);
 165                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 166                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 167                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 168                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 169                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 170         }
 171         if(regs[0]>=0x80000006)
 172         {
 173                 do_cpuid(0x80000006, regs2);
 174                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 175                 caps->cl_size  = regs2[2] & 0xFF;
 176         }
 177         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 178 #if 0
 179         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 180                 gCpuCaps.hasMMX,
 181                 gCpuCaps.hasMMX2,
 182                 gCpuCaps.hasSSE,
 183                 gCpuCaps.hasSSE2,
 184                 gCpuCaps.has3DNow,
 185                 gCpuCaps.has3DNowExt );
 186 #endif
 187
 188                 /* FIXME: Does SSE2 need more OS support, too? */
 189 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 190   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 191   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 192   || defined(__OS2__)
 193                 if (caps->hasSSE)
 194                         check_os_katmai_support();
 195                 if (!caps->hasSSE)
 196                         caps->hasSSE2 = 0;
 197 #else
 198                 caps->hasSSE=0;
 199                 caps->hasSSE2 = 0;
 200 #endif
 201 //              caps->has3DNow=1;
 202 //              caps->hasMMX2 = 0;
 203 //              caps->hasMMX = 0;
 204
 205 #ifndef RUNTIME_CPUDETECT
 206 #if !HAVE_MMX
 207         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 208         caps->hasMMX=0;
 209 #endif
 210 #if !HAVE_MMX2
 211         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 212         caps->hasMMX2=0;
 213 #endif
 214 #if !HAVE_SSE
 215         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 216         caps->hasSSE=0;
 217 #endif
 218 #if !HAVE_SSE2
 219         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 220         caps->hasSSE2=0;
 221 #endif
 222 #if !HAVE_AMD3DNOW
 223         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 224         caps->has3DNow=0;
 225 #endif
 226 #if !HAVE_AMD3DNOWEXT
 227         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 228         caps->has3DNowExt=0;
 229 #endif
 230 #endif  // RUNTIME_CPUDETECT
 231 }
 232
 233 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 234         char vendor[13];
 235         char *retname;
 236         int i;
 237
 238         if (NULL==(retname=malloc(256))) {
 239                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 240                 exit(1);
 241         }
 242         retname[0] = '\0';
 243
 244         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 245
 246         do_cpuid(0x80000000,regs);
 247         if (regs[0] >= 0x80000004)
 248         {
 249                 // CPU has built-in namestring
 250                 for (i = 0x80000002; i <= 0x80000004; i++)
 251                 {
 252                         do_cpuid(i, regs);
 253                         strncat(retname, (char*)regs, 16);
 254                 }
 255         }
 256         return retname;
 257 }
 258
 259 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 260 static void sigill_handler_sse( int signal, struct sigcontext sc )
 261 {
 262    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 263
 264    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 265     * instructions are 3 bytes long.  We must increment the instruction
 266     * pointer manually to avoid repeated execution of the offending
 267     * instruction.
 268     *
 269     * If the SIGILL is caused by a divide-by-zero when unmasked
 270     * exceptions aren't supported, the SIMD FPU status and control
 271     * word will be restored at the end of the test, so we don't need
 272     * to worry about doing it here.  Besides, we may not be able to...
 273     */
 274    sc.eip += 3;
 275
 276    gCpuCaps.hasSSE=0;
 277 }
 278 #endif /* __linux__ && _POSIX_SOURCE */
 279
 280 #if defined(__MINGW32__) || defined(__CYGWIN__)
 281 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 282 {
 283    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 284       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 285       ep->ContextRecord->Eip +=3;
 286       gCpuCaps.hasSSE=0;
 287           return EXCEPTION_CONTINUE_EXECUTION;
 288    }
 289    return EXCEPTION_CONTINUE_SEARCH;
 290 }
 291 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 292
 293 #ifdef __OS2__
 294 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 295                                    PEXCEPTIONREGISTRATIONRECORD p2,
 296                                    PCONTEXTRECORD               p3,
 297                                    PVOID                        p4 )
 298 {
 299    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 300       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 301
 302       p3->ctx_RegEip += 3;
 303       gCpuCaps.hasSSE = 0;
 304
 305       return XCPT_CONTINUE_EXECUTION;
 306    }
 307    return XCPT_CONTINUE_SEARCH;
 308 }
 309 #endif
 310
 311 /* If we're running on a processor that can do SSE, let's see if we
 312  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 313  * haven't been configured for a Pentium III but are running on one,
 314  * and RedHat patched 2.2 kernels that have broken exception handling
 315  * support for user space apps that do SSE.
 316  */
 317
 318 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 319 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 320 #elif defined(__APPLE__)
 321 #define SSE_SYSCTL_NAME "hw.optional.sse"
 322 #endif
 323
 324 static void check_os_katmai_support( void )
 325 {
 326 #if ARCH_X86_64
 327    gCpuCaps.hasSSE=1;
 328    gCpuCaps.hasSSE2=1;
 329 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 330    int has_sse=0, ret;
 331    size_t len=sizeof(has_sse);
 332
 333    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 334    if (ret || !has_sse)
 335       gCpuCaps.hasSSE=0;
 336
 337 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 338 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 339    int has_sse, has_sse2, ret, mib[2];
 340    size_t varlen;
 341
 342    mib[0] = CTL_MACHDEP;
 343    mib[1] = CPU_SSE;
 344    varlen = sizeof(has_sse);
 345
 346    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 347    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 348    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 349    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 350
 351    mib[1] = CPU_SSE2;
 352    varlen = sizeof(has_sse2);
 353    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 354    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 355    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 356    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 357 #else
 358    gCpuCaps.hasSSE = 0;
 359    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 360 #endif
 361 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 362    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 363    if ( gCpuCaps.hasSSE ) {
 364       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 365       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 366       __asm__ volatile ("xorps %xmm0, %xmm0");
 367       SetUnhandledExceptionFilter(exc_fil);
 368       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 369    }
 370 #elif defined(__OS2__)
 371    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 372    if ( gCpuCaps.hasSSE ) {
 373       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 374       DosSetExceptionHandler( &RegRec );
 375       __asm__ volatile ("xorps %xmm0, %xmm0");
 376       DosUnsetExceptionHandler( &RegRec );
 377       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 378    }
 379 #elif defined(__linux__)
 380 #if defined(_POSIX_SOURCE)
 381    struct sigaction saved_sigill;
 382
 383    /* Save the original signal handlers.
 384     */
 385    sigaction( SIGILL, NULL, &saved_sigill );
 386
 387    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 388
 389    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 390     * supports the extended FPU save and restore required for SSE.  If
 391     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 392     * doesn't support Streaming SIMD Exceptions, even if the processor
 393     * does.
 394     */
 395    if ( gCpuCaps.hasSSE ) {
 396       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 397
 398 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 399       __asm__ volatile ("xorps %xmm0, %xmm0");
 400
 401       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 402    }
 403
 404    /* Restore the original signal handlers.
 405     */
 406    sigaction( SIGILL, &saved_sigill, NULL );
 407
 408    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 409     * safe to go ahead and hook out the SSE code throughout Mesa.
 410     */
 411    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 412 #else
 413    /* We can't use POSIX signal handling to test the availability of
 414     * SSE, so we disable it by default.
 415     */
 416    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 417    gCpuCaps.hasSSE=0;
 418 #endif /* _POSIX_SOURCE */
 419 #else
 420    /* Do nothing on other platforms for now.
 421     */
 422    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 423    gCpuCaps.hasSSE=0;
 424 #endif /* __linux__ */
 425 }
 426 #else /* ARCH_X86 */
 427
 428 #ifdef __APPLE__
 429 #include <sys/sysctl.h>
 430 #elif defined(__AMIGAOS4__)
 431 /* nothing */
 432 #else
 433 #include <signal.h>
 434 #include <setjmp.h>
 435
 436 static sigjmp_buf jmpbuf;
 437 static volatile sig_atomic_t canjump = 0;
 438
 439 static void sigill_handler (int sig)
 440 {
 441     if (!canjump) {
 442         signal (sig, SIG_DFL);
 443         raise (sig);
 444     }
 445
 446     canjump = 0;
 447     siglongjmp (jmpbuf, 1);
 448 }
 449 #endif /* __APPLE__ */
 450
 451 void GetCpuCaps( CpuCaps *caps)
 452 {
 453         caps->cpuType=0;
 454         caps->cpuModel=0;
 455         caps->cpuStepping=0;
 456         caps->hasMMX=0;
 457         caps->hasMMX2=0;
 458         caps->has3DNow=0;
 459         caps->has3DNowExt=0;
 460         caps->hasSSE=0;
 461         caps->hasSSE2=0;
 462         caps->hasSSE3=0;
 463         caps->hasSSSE3=0;
 464         caps->hasSSE4a=0;
 465         caps->isX86=0;
 466         caps->hasAltiVec = 0;
 467 #if HAVE_ALTIVEC
 468 #ifdef __APPLE__
 469 /*
 470   rip-off from ffmpeg altivec detection code.
 471   this code also appears on Apple's AltiVec pages.
 472  */
 473         {
 474                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 475                 int has_vu = 0;
 476                 size_t len = sizeof(has_vu);
 477                 int err;
 478
 479                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 480
 481                 if (err == 0)
 482                         if (has_vu != 0)
 483                                 caps->hasAltiVec = 1;
 484         }
 485 #elif defined(__AMIGAOS4__)
 486         ULONG result = 0;
 487
 488         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 489         if (result == VECTORTYPE_ALTIVEC)
 490                 caps->hasAltiVec = 1;
 491 #else
 492 /* no Darwin, do it the brute-force way */
 493 /* this is borrowed from the libmpeg2 library */
 494         {
 495           signal (SIGILL, sigill_handler);
 496           if (sigsetjmp (jmpbuf, 1)) {
 497             signal (SIGILL, SIG_DFL);
 498           } else {
 499             canjump = 1;
 500
 501             __asm__ volatile ("mtspr 256, %0\n\t"
 502                           "vand %%v0, %%v0, %%v0"
 503                           :
 504                           : "r" (-1));
 505
 506             signal (SIGILL, SIG_DFL);
 507             caps->hasAltiVec = 1;
 508           }
 509         }
 510 #endif /* __APPLE__ */
 511         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 512 #endif /* HAVE_ALTIVEC */
 513
 514 if (ARCH_IA64)
 515         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 516
 517 if (ARCH_SPARC)
 518         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 519
 520 if (ARCH_ARM)
 521         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 522
 523 if (ARCH_PPC)
 524         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 525
 526 if (ARCH_ALPHA)
 527         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 528
 529 if (ARCH_SGI_MIPS)
 530         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
 531
 532 if (ARCH_PA_RISC)
 533         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 534
 535 if (ARCH_S390)
 536         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 537
 538 if (ARCH_S390X)
 539         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 540
 541 if (ARCH_VAX)
 542         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 543
 544 if (ARCH_XTENSA)
 545         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 546 }
 547 #endif /* !ARCH_X86 */