firmware/target/arm/as3525/clock-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef CLOCK_TARGET_H
  22 #define CLOCK_TARGET_H
  23
  24 #include "config.h"
  25 #include "cpu.h"
  26
  27 /* returns clock divider, given maximal target frequency and clock reference */
  28 #define CLK_DIV(ref, target) ((ref + target - 1) / target)
  29
  30
  31 /*  Frequency and Bus Settings
  32  *  These bus settings work on the assumption that unboosted performance will be
  33  *  based on fastbus mode(FCLK == PCLK) at a frequency configured with this file.
  34  *  Boosted performance defaults to synchronous bus but will be changed to
  35  *  asynchronous bus if FCLK is not an integer multiple of PCLK.
  36  *  The player starts up in fastbus mode and synchronous or asynchronous mode is
  37  *  implemented in the set_cpu_frequency() function in system-as3525.c.  There
  38  *  are limitations on both frequencies and frequency relationships listed in 7.3.14
  39  *  of the as3525 datasheet that need to be observed.  If you are determined to
  40  *  use a frequency that is not "legal" you can do that. There are no checks for
  41  *  legal frequency values, only some validity checks to make sure the divider
  42  *  value fits into the number of bits allotted to it.
  43  *
  44  *  The CLOCK_DIV macro does a pretty good job at selecting divider values but
  45  *  you can always override it by choosing your own value and commenting out the
  46  *  macro.   AS3525_FCLK_PREDIV values other than 0 allow you to choose frequencies
  47  *  from lines below the main PLL frequency lines.  AS3525_FCLK_POSTDIV
  48  *  will be calculated automagically depending on the value you have selected
  49  *  for AS3525_FCLK_FREQ.  You may add more PLL frequencies by simply commenting
  50  *  out the current #defines for AS3525_PLLA_FREQ & AS3525_PLLA_SETTING and
  51  *  adding a #define for FREQ and divider setting to produce that frequency.I
  52  *  have included USB & PLLB for future use but commented them out for now.
  53  */
  54
  55 /* Clock Sources  */
  56 #define AS3525_CLK_MAIN           0
  57 #define AS3525_CLK_PLLA           1
  58 #define AS3525_CLK_PLLB           2
  59 #define AS3525_CLK_FCLK           3         /* Available as PCLK input only  */
  60
  61 /** ************ Change these to reconfigure clocking scheme *******************/
  62 #if CONFIG_CPU == AS3525v2
  63
  64 /* PLLA & PLLB registers differ from AS3525(v1)
  65  * PLL bits:
  66  * - bit 0-6 = F-1 (F=multiplier)
  67  * - bit 7-9 = R-1 (R=divisor)
  68  * - bit 10  = OD (output divider)? Divides by 2 if set.
  69  * - bit 11  = unknown (no effect)
  70  * - bit 12  = unknown (always set to 1)
  71  * Fpll = Fin * F / (R * OD), where Fin = 12 MHz
  72  */
  73 #define AS3525_PLLA_FREQ        240000000
  74 #define AS3525_PLLA_SETTING     0x113B
  75
  76 #define AS3525_PLLB_FREQ        192000000   /* allows 44.1kHz with 0.04% error*/
  77 #define AS3525_PLLB_SETTING     0x155F
  78
  79 #define AS3525_FCLK_PREDIV      0
  80 #define AS3525_FCLK_FREQ        AS3525_PLLA_FREQ
  81
  82 /* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), so we don't
  83  * set bit 6 (PCLK_DIV1_SEL) for the moment
  84  *
  85  * Note that setting bits 1:0 have no effect and they always read back as 0
  86  * Also note that CGU_PERI is based on fclk, not PLLA
  87  */
  88
  89 #ifdef SANSA_FUZEV2
  90 /* display is unbearably slow at 24MHz
  91  * 34285715 HZ works ok but 40MHz works even better*/
  92 #define AS3525_DRAM_FREQ        40000000    /* Initial DRAM frequency  */
  93 #else
  94 #define AS3525_DRAM_FREQ        24000000    /* Initial DRAM frequency  */
  95 #endif /* SANSA_FUZEV2 */
  96
  97 #else
  98 /* AS3525v1 */
  99
 100 /* PLL  frequencies and settings*/
 101 #define AS3525_PLLA_FREQ        248000000   /*124,82.7,62,49.6,41.3,35.4 */
 102        /* FCLK_PREDIV->  *7/8 = 217MHz      108.5 ,72.3, 54.25, 43.4, 36.17 */
 103                       /* *6/8 = 186MHz      93, 62, 46.5, 37.2 */
 104                       /* *5/8 = 155MHz      77.5, 51.67, 38.75 */
 105 #define AS3525_PLLA_SETTING     0x261F
 106
 107 /* PLLB frequencies and settings (audio and USB) */
 108 #define AS3525_PLLB_FREQ        384000000   /* allows 44.1kHz with 0.04% error*/
 109 #define AS3525_PLLB_SETTING     0x2630
 110
 111 //#define AS3525_PLLA_FREQ        384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
 112        /* FCLK_PREDIV->  *7/8 = 336MHz      168, 112, 84, 67.2, 56, 48, 42, 37.3*/
 113                       /* *6/8 = 288MHz      144, 96, 72, 57.6, 48, 41.1, */
 114                       /* *5/8 = 240MHz      120, 80, 60, 48, 40  */
 115 //#define AS3525_PLLA_SETTING     0x2630
 116
 117 #define AS3525_FCLK_PREDIV    2 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
 118                                 /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */
 119
 120 #define AS3525_FCLK_FREQ      186000000   /* Boosted FCLK frequency - over 200MHz */
 121                                           /* requires CVDDp bumped to 1.2V        */
 122 #define AS3525_DRAM_FREQ       31000000            /* Initial DRAM frequency  */
 123 #define AS3525_DRAM_FREQ_BOOSTED 62000000
 124 /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
 125
 126 #endif  /* CONFIG_CPU == AS3525v2 */
 127
 128 #define AS3525_PCLK_FREQ      (AS3525_DRAM_FREQ/1)   /* PCLK divided from DRAM freq */
 129 #define AS3525_PCLK_FREQ_BOOSTED (AS3525_DRAM_FREQ_BOOSTED/1)
 130 #define AS3525_DBOP_FREQ      (AS3525_PCLK_FREQ/1)   /* DBOP divided from PCLK freq */
 131
 132 /** ****************************************************************************/
 133
 134 /* Tell the software what frequencies we're running */
 135 #define CPUFREQ_MAX              AS3525_FCLK_FREQ
 136 #define CPUFREQ_DEFAULT          AS3525_PCLK_FREQ
 137 #define CPUFREQ_NORMAL           AS3525_PCLK_FREQ
 138
 139 /* FCLK */
 140 #define AS3525_FCLK_SEL          AS3525_CLK_PLLA
 141 #define AS3525_FCLK_POSTDIV      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
 142
 143 #if CONFIG_CPU == AS3525v2
 144 #define AS3525_FCLK_POSTDIV_UNBOOSTED      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */
 145 /* Since pclk is based on fclk, we need to change CGU_PERI as well */
 146 #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
 147 #endif /* CONFIG_CPU == AS3525v2 */
 148
 149 /* MCLK */
 150 #if CONFIG_CPU == AS3525v2
 151 /* on AMSv2 we can enable PLLB for MCLK to increase PCM sample rate accuracy
 152    with no significant impact on battery life */
 153 #define AS3525_MCLK_SEL          AS3525_CLK_PLLB
 154 #else
 155 #define AS3525_MCLK_SEL          AS3525_CLK_PLLA
 156 #endif /* CONFIG_CPU == AS3525v2 */
 157
 158 #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA)
 159 #define AS3525_MCLK_FREQ         AS3525_PLLA_FREQ
 160 #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB)
 161 #define AS3525_MCLK_FREQ         AS3525_PLLB_FREQ
 162 #else
 163 #error Choose either PLLA or PLLB for MCLK!
 164 #endif
 165
 166 /* PCLK */
 167
 168 #if CONFIG_CPU == AS3525
 169
 170 #define AS3525_PCLK_SEL          AS3525_CLK_PLLA
 171          /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/
 172 #define AS3525_PCLK_DIV1         (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/
 173 #define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
 174 #define AS3525_PCLK_DIV1_BOOSTED (CLK_DIV(AS3525_DRAM_FREQ_BOOSTED, AS3525_PCLK_FREQ_BOOSTED) - 1)
 175 #define AS3525_PCLK_DIV0_BOOSTED (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ_BOOSTED) - 1)
 176
 177 #else
 178
 179 #define AS3525_PCLK_SEL          AS3525_CLK_FCLK
 180 #define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
 181
 182 #endif /* CONFIG_CPU */
 183
 184    /* PCLK as Source */
 185   #define AS3525_DBOP_DIV        (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
 186   #define AS3525_I2C_PRESCALER   CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
 187   #define AS3525_I2C_PRESCALER_BOOSTED   CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_I2C_FREQ)
 188   #define AS3525_I2C_FREQ        400000
 189   #define AS3525_SD_IDENT_DIV    ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
 190   #define AS3525_SD_IDENT_DIV_BOOSTED    ((CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_SD_IDENT_FREQ) / 2) - 1)
 191   #define AS3525_SD_IDENT_FREQ   400000      /* must be between 100 & 400 kHz */
 192   #define AS3525_SSP_PRESCALER   ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1)    /* must be an even number */
 193   #define AS3525_SSP_FREQ        12000000
 194
 195 #define AS3525_IDE_SEL           AS3525_CLK_PLLA           /* Input Source   */
 196 #define AS3525_IDE_DIV           (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
 197
 198 #if CONFIG_CPU == AS3525v2
 199 #define AS3525_MS_FREQ           120000000
 200 #define AS3525_MS_DIV            (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1)
 201 #define AS3525_SDSLOT_FREQ       24000000
 202 #define AS3525_SDSLOT_DIV        (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1)
 203 #define AS3525_IDE_FREQ          80000000
 204 #else
 205 #define AS3525_IDE_FREQ          50000000    /* The OF uses 66MHz maximal freq */
 206 #endif /* CONFIG_CPU == AS3525v2 */
 207
 208
 209 //#define AS3525_USB_SEL           AS3525_CLK_PLLA            /* Input Source   */
 210 //#define AS3525_USB_DIV           /* div = 1/(n=0?1:2n)*/
 211
 212
 213 /* Validity Checks */
 214
 215 /* AS3525_PCLK_FREQ  */
 216 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
 217 #error PCLK frequency is too low : clock divider will not fit !
 218 #endif
 219
 220 /*  AS3525_DBOP_FREQ */
 221 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
 222 #error DBOP frequency is too low : clock divider will not fit !
 223 #endif
 224
 225 /* AS3525_IDE_FREQ */
 226 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
 227 #error IDE frequency is too low : clock divider will not fit !
 228 #endif
 229
 230 /* AS3525_I2C_FREQ */
 231 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
 232 #error I2C frequency is too low : clock divider will not fit !
 233 #endif
 234
 235 /* AS3525_SSP_FREQ */
 236 #if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ)) + 1 ) & ~1) >= (1<<8) /* 8 bits */
 237 #error SSP frequency is too low : clock divider will not fit !
 238 #endif
 239
 240 /* AS3525_SD_IDENT_FREQ */
 241 #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
 242 #error SD IDENTIFICATION frequency is too low : clock divider will not fit !
 243 #endif
 244
 245 /* I2SIN / I2SOUT frequencies */
 246 /* low samplerate */
 247 #if ((AS3525_MCLK_FREQ/(128*8000))) > 512   /* 8kHz = lowest frequency */
 248 #error AS3525_MCLK_FREQ is too high for 8kHz samplerate !
 249 #endif
 250 /* high samplerate */
 251 #if ((AS3525_MCLK_FREQ/(128*96000))) < 1   /* 96kHz = highest frequency */
 252 #error AS3525_MCLK_FREQ is too low for 96kHz samplerate !
 253 #endif
 254
 255 #endif /* CLOCK_TARGET_H */