firmware/target/arm/as3525/clock-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef CLOCK_TARGET_H
  22 #define CLOCK_TARGET_H
  23
  24 /* returns clock divider, given maximal target frequency and clock reference */
  25 #define CLK_DIV(ref, target) ((ref + target - 1) / target)
  26
  27
  28 /*  Frequency and Bus Settings
  29  *  These bus settings work on the assumption that unboosted performance will be
  30  *  based on fastbus mode(FCLK == PCLK) at a frequency configured with this file.
  31  *  Boosted performance defaults to synchronous bus but will be changed to
  32  *  asynchronous bus if FCLK is not an integer multiple of PCLK.
  33  *  The player starts up in fastbus mode and synchronous or asynchronous mode is
  34  *  implemented in the set_cpu_frequency() function in system-as3525.c.  There
  35  *  are limitations on both frequencies and frequency relationships listed in 7.3.14
  36  *  of the as3525 datasheet that need to be observed.  If you are determined to
  37  *  use a frequency that is not "legal" you can do that. There are no checks for
  38  *  legal frequency values, only some validity checks to make sure the divider
  39  *  value fits into the number of bits allotted to it.
  40  *
  41  *  The CLOCK_DIV macro does a pretty good job at selecting divider values but
  42  *  you can always override it by choosing your own value and commenting out the
  43  *  macro.   AS3525_FCLK_PREDIV values other than 0 allow you to choose frequencies
  44  *  from lines below the main PLL frequency lines.  AS3525_FCLK_POSTDIV
  45  *  will be calculated automagically depending on the value you have selected
  46  *  for AS3525_FCLK_FREQ.  You may add more PLL frequencies by simply commenting
  47  *  out the current #defines for AS3525_PLLA_FREQ & AS3525_PLLA_SETTING and
  48  *  adding a #define for FREQ and divider setting to produce that frequency.I
  49  *  have included USB & PLLB for future use but commented them out for now.
  50  */
  51
  52 /* Clock Sources  */
  53 #define AS3525_CLK_MAIN           0
  54 #define AS3525_CLK_PLLA           1
  55 //#define AS3525_CLK_PLLB           2
  56 #define AS3525_CLK_FCLK           3         /* Available as PCLK input only  */
  57
  58 /** ************ Change these to reconfigure clocking scheme *******************/
  59 /* PLL  frequencies and settings*/
  60 #define AS3525_PLLA_FREQ        248000000   /*124,82.7,62,49.6,41.3,35.4 */
  61        /* FCLK_PREDIV->  *7/8 = 217MHz      108.5 ,72.3, 54.25, 43.4, 36.17 */
  62                       /* *6/8 = 186MHz      93, 62, 46.5, 37.2 */
  63                       /* *5/8 = 155MHz      77.5, 51.67, 38.75 */
  64 #define AS3525_PLLA_SETTING     0x261F
  65
  66 //#define AS3525_PLLA_FREQ        384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
  67        /* FCLK_PREDIV->  *7/8 = 336MHz      168, 112, 84, 67.2, 56, 48, 42, 37.3*/
  68                       /* *6/8 = 288MHz      144, 96, 72, 57.6, 48, 41.1, */
  69                       /* *5/8 = 240MHz      120, 80, 60, 48, 40  */
  70 //#define AS3525_PLLA_SETTING     0x2630
  71
  72 /*  PLLB not used at this time! */
  73 //#define AS3525_PLLB_FREQ
  74 //#define AS3525_PLLB_SETTING
  75
  76 #define AS3525_FCLK_PREDIV    0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
  77                                 /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */
  78
  79 #define AS3525_FCLK_FREQ      248000000            /* Boosted FCLK frequency  */
  80 #define AS3525_DRAM_FREQ       62000000            /* Initial DRAM frequency  */
  81         /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
  82 #define AS3525_PCLK_FREQ      AS3525_DRAM_FREQ/1   /* PCLK divided from DRAM freq */
  83 #define AS3525_DBOP_FREQ      AS3525_PCLK_FREQ/1   /* DBOP divided from PCLK freq */
  84
  85 /** ****************************************************************************/
  86
  87 /* Figure out if we need to use asynchronous bus */
  88 #if (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ)
  89 #define ASYNCHRONOUS_BUS                          /* Boosted mode asynchronous */
  90 #endif
  91
  92 /* Tell the software what frequencies we're running */
  93 #define CPUFREQ_MAX              AS3525_FCLK_FREQ
  94 #define CPUFREQ_DEFAULT          AS3525_PCLK_FREQ
  95 #define CPUFREQ_NORMAL           AS3525_PCLK_FREQ
  96
  97 /* FCLK */
  98 #define AS3525_FCLK_SEL          AS3525_CLK_PLLA
  99 #define AS3525_FCLK_POSTDIV      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
 100
 101 /* PCLK */
 102 #ifdef ASYNCHRONOUS_BUS
 103 #define AS3525_PCLK_SEL          AS3525_CLK_PLLA    /* PLLA input for asynchronous */
 104 #define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/
 105 #else
 106 #define AS3525_PCLK_SEL          AS3525_CLK_FCLK    /* Fclk input for synchronous */
 107 #define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
 108 #endif
 109          /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/
 110 #define AS3525_PCLK_DIV1         (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/
 111
 112    /* PCLK as Source */
 113   #define AS3525_DBOP_DIV        (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
 114   #define AS3525_I2C_PRESCALER   CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
 115   #define AS3525_I2C_FREQ        400000
 116   #define AS3525_SD_IDENT_DIV    ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
 117   #define AS3525_SD_IDENT_FREQ   400000      /* must be between 100 & 400 kHz */
 118
 119 #define AS3525_IDE_SEL           AS3525_CLK_PLLA           /* Input Source   */
 120 #define AS3525_IDE_DIV           (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
 121 #define AS3525_IDE_FREQ          90000000    /* The OF uses 66MHz maximal freq
 122                                                but sd transfers fail on some
 123                                                players with this limit */
 124
 125 //#define AS3525_USB_SEL           AS3525_CLK_PLLA            /* Input Source   */
 126 //#define AS3525_USB_DIV           /* div = 1/(n=0?1:2n)*/
 127
 128
 129 /* Validity Checks */
 130
 131 /* AS3525_PCLK_FREQ  */
 132 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
 133 #error PCLK frequency is too low : clock divider will not fit !
 134 #endif
 135 /*  AS3525_DBOP_FREQ */
 136 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
 137 #error DBOP frequency is too low : clock divider will not fit !
 138 #endif
 139 /* AS3525_IDE_FREQ */
 140 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
 141 #error IDE frequency is too low : clock divider will not fit !
 142 #endif
 143 /* AS3525_I2C_FREQ */
 144 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
 145 #error I2C frequency is too low : clock divider will not fit !
 146 #endif
 147 /* AS3525_SD_IDENT_FREQ */
 148 #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
 149 #error SD IDENTIFICATION frequency is too low : clock divider will not fit !
 150 #endif
 151
 152 #endif /* CLOCK_TARGET_H */