Fix for assertion error when expanding macro.
[iverilog.git] / vvp / part.h
blob8bb2d11951963b9f79ac7dc8bf3e84157b8b091b
1 #ifndef __part_H
2 #define __part_H
3 /*
4 * Copyright (c) 2005 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
21 #ident "$Id: part.h,v 1.2 2006/11/16 01:11:26 steve Exp $"
23 # include "schedule.h"
25 /* vvp_fun_part
26 * This node takes a part select of the input vector. Input 0 is the
27 * vector to be selected from, and input 1 is the location where the
28 * select starts. Input 2, which is typically constant, is the width
29 * of the result.
31 class vvp_fun_part : public vvp_net_fun_t, private vvp_gen_event_s {
33 public:
34 vvp_fun_part(unsigned base, unsigned wid);
35 ~vvp_fun_part();
37 public:
38 void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
40 void recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
41 unsigned, unsigned, unsigned);
43 private:
44 void run_run();
46 private:
47 unsigned base_;
48 unsigned wid_;
49 vvp_vector4_t val_;
50 vvp_net_t*net_;
53 /* vvp_fun_part_pv
54 * This node takes a vector input and turns it into the part select of
55 * a wider output network. It used the recv_vec4_pv methods of the
56 * destination nodes to propagate the part select.
58 class vvp_fun_part_pv : public vvp_net_fun_t {
60 public:
61 vvp_fun_part_pv(unsigned base, unsigned wid, unsigned vec_wid);
62 ~vvp_fun_part_pv();
64 public:
65 void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
67 private:
68 unsigned base_;
69 unsigned wid_;
70 unsigned vwid_;
74 * This part select is more flexible in that it takes the vector to
75 * part in port 0, and the base of the part in port 1. The width of
76 * the part to take out is fixed.
78 class vvp_fun_part_var : public vvp_net_fun_t {
80 public:
81 explicit vvp_fun_part_var(unsigned wid);
82 ~vvp_fun_part_var();
84 public:
85 void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
87 private:
88 unsigned base_;
89 unsigned wid_;
90 vvp_vector4_t source_;
91 // Save the last output, for detecting change.
92 vvp_vector4_t ref_;
97 * $Log: part.h,v $
98 * Revision 1.2 2006/11/16 01:11:26 steve
99 * Support part writes into part select nodes.
101 * Revision 1.1 2005/09/20 00:51:53 steve
102 * Lazy processing of vvp_fun_part functor.
105 #endif